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[mirror_ubuntu-hirsute-kernel.git] / drivers / net / ethernet / qlogic / qed / qed_dev.c
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fe56b9e6 1/* QLogic qed NIC Driver
e8f1cb50 2 * Copyright (c) 2015-2017 QLogic Corporation
fe56b9e6 3 *
e8f1cb50
MY		 4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
fe56b9e6
YM		 31 */
32
33#include <linux/types.h>
34#include <asm/byteorder.h>
35#include <linux/io.h>
36#include <linux/delay.h>
37#include <linux/dma-mapping.h>
38#include <linux/errno.h>
39#include <linux/kernel.h>
40#include <linux/mutex.h>
41#include <linux/pci.h>
42#include <linux/slab.h>
43#include <linux/string.h>
a91eb52a 44#include <linux/vmalloc.h>
fe56b9e6
YM		 45#include <linux/etherdevice.h>
46#include <linux/qed/qed_chain.h>
47#include <linux/qed/qed_if.h>
48#include "qed.h"
49#include "qed_cxt.h"
39651abd 50#include "qed_dcbx.h"
fe56b9e6 51#include "qed_dev_api.h"
1e128c81 52#include "qed_fcoe.h"
fe56b9e6
YM		 53#include "qed_hsi.h"
54#include "qed_hw.h"
55#include "qed_init_ops.h"
56#include "qed_int.h"
fc831825 57#include "qed_iscsi.h"
0a7fb11c 58#include "qed_ll2.h"
fe56b9e6 59#include "qed_mcp.h"
1d6cff4f 60#include "qed_ooo.h"
fe56b9e6
YM		 61#include "qed_reg_addr.h"
62#include "qed_sp.h"
32a47e72 63#include "qed_sriov.h"
0b55e27d 64#include "qed_vf.h"
51ff1725 65#include "qed_roce.h"
fe56b9e6 66
0caf5b26 67static DEFINE_SPINLOCK(qm_lock);
39651abd 68
51ff1725
RA		 69#define QED_MIN_DPIS (4)
70#define QED_MIN_PWM_REGION (QED_WID_SIZE * QED_MIN_DPIS)
71
fe56b9e6 72/* API common to all protocols */
c2035eea
RA		 73enum BAR_ID {
74 BAR_ID_0, /* used for GRC */
75 BAR_ID_1 /* Used for doorbells */
76};
77
15582962
RV		 78static u32 qed_hw_bar_size(struct qed_hwfn *p_hwfn,
79 struct qed_ptt *p_ptt, enum BAR_ID bar_id)
c2035eea 80{
1408cc1f
YM		 81 u32 bar_reg = (bar_id == BAR_ID_0 ?
82 PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
83 u32 val;
c2035eea 84
1408cc1f
YM		 85 if (IS_VF(p_hwfn->cdev))
86 return 1 << 17;
87
15582962 88 val = qed_rd(p_hwfn, p_ptt, bar_reg);
c2035eea
RA		 89 if (val)
90 return 1 << (val + 15);
91
92 /* Old MFW initialized above registered only conditionally */
93 if (p_hwfn->cdev->num_hwfns > 1) {
94 DP_INFO(p_hwfn,
95 "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n");
96 return BAR_ID_0 ? 256 * 1024 : 512 * 1024;
97 } else {
98 DP_INFO(p_hwfn,
99 "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n");
100 return 512 * 1024;
101 }
102}
103
1a635e48 104void qed_init_dp(struct qed_dev *cdev, u32 dp_module, u8 dp_level)
fe56b9e6
YM		 105{
106 u32 i;
107
108 cdev->dp_level = dp_level;
109 cdev->dp_module = dp_module;
110 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
111 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
112
113 p_hwfn->dp_level = dp_level;
114 p_hwfn->dp_module = dp_module;
115 }
116}
117
118void qed_init_struct(struct qed_dev *cdev)
119{
120 u8 i;
121
122 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
123 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
124
125 p_hwfn->cdev = cdev;
126 p_hwfn->my_id = i;
127 p_hwfn->b_active = false;
128
129 mutex_init(&p_hwfn->dmae_info.mutex);
130 }
131
132 /* hwfn 0 is always active */
133 cdev->hwfns[0].b_active = true;
134
135 /* set the default cache alignment to 128 */
136 cdev->cache_shift = 7;
137}
138
139static void qed_qm_info_free(struct qed_hwfn *p_hwfn)
140{
141 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
142
143 kfree(qm_info->qm_pq_params);
144 qm_info->qm_pq_params = NULL;
145 kfree(qm_info->qm_vport_params);
146 qm_info->qm_vport_params = NULL;
147 kfree(qm_info->qm_port_params);
148 qm_info->qm_port_params = NULL;
bcd197c8
MC		 149 kfree(qm_info->wfq_data);
150 qm_info->wfq_data = NULL;
fe56b9e6
YM		 151}
152
153void qed_resc_free(struct qed_dev *cdev)
154{
155 int i;
156
1408cc1f
YM		 157 if (IS_VF(cdev))
158 return;
159
fe56b9e6
YM		 160 kfree(cdev->fw_data);
161 cdev->fw_data = NULL;
162
163 kfree(cdev->reset_stats);
164
165 for_each_hwfn(cdev, i) {
166 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
167
168 qed_cxt_mngr_free(p_hwfn);
169 qed_qm_info_free(p_hwfn);
170 qed_spq_free(p_hwfn);
171 qed_eq_free(p_hwfn, p_hwfn->p_eq);
172 qed_consq_free(p_hwfn, p_hwfn->p_consq);
173 qed_int_free(p_hwfn);
0a7fb11c
YM		 174#ifdef CONFIG_QED_LL2
175 qed_ll2_free(p_hwfn, p_hwfn->p_ll2_info);
176#endif
1e128c81
AE		 177 if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
178 qed_fcoe_free(p_hwfn, p_hwfn->p_fcoe_info);
179
1d6cff4f 180 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
fc831825 181 qed_iscsi_free(p_hwfn, p_hwfn->p_iscsi_info);
1d6cff4f
YM		 182 qed_ooo_free(p_hwfn, p_hwfn->p_ooo_info);
183 }
32a47e72 184 qed_iov_free(p_hwfn);
fe56b9e6 185 qed_dmae_info_free(p_hwfn);
270837b3 186 qed_dcbx_info_free(p_hwfn);
fe56b9e6
YM		 187 }
188}
189
b5a9ee7c
AE		 190/******************** QM initialization *******************/
191#define ACTIVE_TCS_BMAP 0x9f
192#define ACTIVE_TCS_BMAP_4PORT_K2 0xf
193
194/* determines the physical queue flags for a given PF. */
195static u32 qed_get_pq_flags(struct qed_hwfn *p_hwfn)
fe56b9e6 196{
b5a9ee7c 197 u32 flags;
fe56b9e6 198
b5a9ee7c
AE		 199 /* common flags */
200 flags = PQ_FLAGS_LB;
fe56b9e6 201
b5a9ee7c
AE		 202 /* feature flags */
203 if (IS_QED_SRIOV(p_hwfn->cdev))
204 flags |= PQ_FLAGS_VFS;
dbb799c3 205
b5a9ee7c
AE		 206 /* protocol flags */
207 switch (p_hwfn->hw_info.personality) {
208 case QED_PCI_ETH:
209 flags |= PQ_FLAGS_MCOS;
210 break;
211 case QED_PCI_FCOE:
212 flags |= PQ_FLAGS_OFLD;
213 break;
214 case QED_PCI_ISCSI:
215 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
216 break;
217 case QED_PCI_ETH_ROCE:
218 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_OFLD | PQ_FLAGS_LLT;
219 break;
220 default:
221 DP_ERR(p_hwfn,
222 "unknown personality %d\n", p_hwfn->hw_info.personality);
223 return 0;
dbb799c3
YM		 224 }
225
b5a9ee7c
AE		 226 return flags;
227}
dbb799c3 228
b5a9ee7c
AE		 229/* Getters for resource amounts necessary for qm initialization */
230u8 qed_init_qm_get_num_tcs(struct qed_hwfn *p_hwfn)
231{
232 return p_hwfn->hw_info.num_hw_tc;
233}
fe56b9e6 234
b5a9ee7c
AE		 235u16 qed_init_qm_get_num_vfs(struct qed_hwfn *p_hwfn)
236{
237 return IS_QED_SRIOV(p_hwfn->cdev) ?
238 p_hwfn->cdev->p_iov_info->total_vfs : 0;
239}
fe56b9e6 240
b5a9ee7c 241#define NUM_DEFAULT_RLS 1
fe56b9e6 242
b5a9ee7c
AE		 243u16 qed_init_qm_get_num_pf_rls(struct qed_hwfn *p_hwfn)
244{
245 u16 num_pf_rls, num_vfs = qed_init_qm_get_num_vfs(p_hwfn);
fe56b9e6 246
b5a9ee7c
AE		 247 /* num RLs can't exceed resource amount of rls or vports */
248 num_pf_rls = (u16) min_t(u32, RESC_NUM(p_hwfn, QED_RL),
249 RESC_NUM(p_hwfn, QED_VPORT));
bcd197c8 250
b5a9ee7c
AE		 251 /* Make sure after we reserve there's something left */
252 if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS)
253 return 0;
fe56b9e6 254
b5a9ee7c
AE		 255 /* subtract rls necessary for VFs and one default one for the PF */
256 num_pf_rls -= num_vfs + NUM_DEFAULT_RLS;
dbb799c3 257
b5a9ee7c
AE		 258 return num_pf_rls;
259}
39651abd 260
b5a9ee7c
AE		 261u16 qed_init_qm_get_num_vports(struct qed_hwfn *p_hwfn)
262{
263 u32 pq_flags = qed_get_pq_flags(p_hwfn);
264
265 /* all pqs share the same vport, except for vfs and pf_rl pqs */
266 return (!!(PQ_FLAGS_RLS & pq_flags)) *
267 qed_init_qm_get_num_pf_rls(p_hwfn) +
268 (!!(PQ_FLAGS_VFS & pq_flags)) *
269 qed_init_qm_get_num_vfs(p_hwfn) + 1;
270}
271
272/* calc amount of PQs according to the requested flags */
273u16 qed_init_qm_get_num_pqs(struct qed_hwfn *p_hwfn)
274{
275 u32 pq_flags = qed_get_pq_flags(p_hwfn);
276
277 return (!!(PQ_FLAGS_RLS & pq_flags)) *
278 qed_init_qm_get_num_pf_rls(p_hwfn) +
279 (!!(PQ_FLAGS_MCOS & pq_flags)) *
280 qed_init_qm_get_num_tcs(p_hwfn) +
281 (!!(PQ_FLAGS_LB & pq_flags)) + (!!(PQ_FLAGS_OOO & pq_flags)) +
282 (!!(PQ_FLAGS_ACK & pq_flags)) + (!!(PQ_FLAGS_OFLD & pq_flags)) +
283 (!!(PQ_FLAGS_LLT & pq_flags)) +
284 (!!(PQ_FLAGS_VFS & pq_flags)) * qed_init_qm_get_num_vfs(p_hwfn);
285}
286
287/* initialize the top level QM params */
288static void qed_init_qm_params(struct qed_hwfn *p_hwfn)
289{
290 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
291 bool four_port;
292
293 /* pq and vport bases for this PF */
294 qm_info->start_pq = (u16) RESC_START(p_hwfn, QED_PQ);
295 qm_info->start_vport = (u8) RESC_START(p_hwfn, QED_VPORT);
296
297 /* rate limiting and weighted fair queueing are always enabled */
298 qm_info->vport_rl_en = 1;
299 qm_info->vport_wfq_en = 1;
fe56b9e6 300
b5a9ee7c
AE		 301 /* TC config is different for AH 4 port */
302 four_port = p_hwfn->cdev->num_ports_in_engines == MAX_NUM_PORTS_K2;
fe56b9e6 303
b5a9ee7c
AE		 304 /* in AH 4 port we have fewer TCs per port */
305 qm_info->max_phys_tcs_per_port = four_port ? NUM_PHYS_TCS_4PORT_K2 :
306 NUM_OF_PHYS_TCS;
307
308 /* unless MFW indicated otherwise, ooo_tc == 3 for
309 * AH 4-port and 4 otherwise.
310 */
311 if (!qm_info->ooo_tc)
312 qm_info->ooo_tc = four_port ? DCBX_TCP_OOO_K2_4PORT_TC :
313 DCBX_TCP_OOO_TC;
314}
315
316/* initialize qm vport params */
317static void qed_init_qm_vport_params(struct qed_hwfn *p_hwfn)
318{
319 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
320 u8 i;
321
322 /* all vports participate in weighted fair queueing */
323 for (i = 0; i < qed_init_qm_get_num_vports(p_hwfn); i++)
324 qm_info->qm_vport_params[i].vport_wfq = 1;
325}
326
327/* initialize qm port params */
328static void qed_init_qm_port_params(struct qed_hwfn *p_hwfn)
329{
fe56b9e6 330 /* Initialize qm port parameters */
b5a9ee7c
AE		 331 u8 i, active_phys_tcs, num_ports = p_hwfn->cdev->num_ports_in_engines;
332
333 /* indicate how ooo and high pri traffic is dealt with */
334 active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ?
335 ACTIVE_TCS_BMAP_4PORT_K2 :
336 ACTIVE_TCS_BMAP;
337
fe56b9e6 338 for (i = 0; i < num_ports; i++) {
b5a9ee7c
AE		 339 struct init_qm_port_params *p_qm_port =
340 &p_hwfn->qm_info.qm_port_params[i];
341
fe56b9e6 342 p_qm_port->active = 1;
b5a9ee7c 343 p_qm_port->active_phys_tcs = active_phys_tcs;
fe56b9e6
YM		 344 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;
345 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
346 }
b5a9ee7c
AE		 347}
348
349/* Reset the params which must be reset for qm init. QM init may be called as
350 * a result of flows other than driver load (e.g. dcbx renegotiation). Other
351 * params may be affected by the init but would simply recalculate to the same
352 * values. The allocations made for QM init, ports, vports, pqs and vfqs are not
353 * affected as these amounts stay the same.
354 */
355static void qed_init_qm_reset_params(struct qed_hwfn *p_hwfn)
356{
357 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
358
359 qm_info->num_pqs = 0;
360 qm_info->num_vports = 0;
361 qm_info->num_pf_rls = 0;
362 qm_info->num_vf_pqs = 0;
363 qm_info->first_vf_pq = 0;
364 qm_info->first_mcos_pq = 0;
365 qm_info->first_rl_pq = 0;
366}
367
368static void qed_init_qm_advance_vport(struct qed_hwfn *p_hwfn)
369{
370 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
371
372 qm_info->num_vports++;
373
374 if (qm_info->num_vports > qed_init_qm_get_num_vports(p_hwfn))
375 DP_ERR(p_hwfn,
376 "vport overflow! qm_info->num_vports %d, qm_init_get_num_vports() %d\n",
377 qm_info->num_vports, qed_init_qm_get_num_vports(p_hwfn));
378}
379
380/* initialize a single pq and manage qm_info resources accounting.
381 * The pq_init_flags param determines whether the PQ is rate limited
382 * (for VF or PF) and whether a new vport is allocated to the pq or not
383 * (i.e. vport will be shared).
384 */
fe56b9e6 385
b5a9ee7c
AE		 386/* flags for pq init */
387#define PQ_INIT_SHARE_VPORT (1 << 0)
388#define PQ_INIT_PF_RL (1 << 1)
389#define PQ_INIT_VF_RL (1 << 2)
fe56b9e6 390
b5a9ee7c
AE		 391/* defines for pq init */
392#define PQ_INIT_DEFAULT_WRR_GROUP 1
393#define PQ_INIT_DEFAULT_TC 0
394#define PQ_INIT_OFLD_TC (p_hwfn->hw_info.offload_tc)
fe56b9e6 395
b5a9ee7c
AE		 396static void qed_init_qm_pq(struct qed_hwfn *p_hwfn,
397 struct qed_qm_info *qm_info,
398 u8 tc, u32 pq_init_flags)
399{
400 u16 pq_idx = qm_info->num_pqs, max_pq = qed_init_qm_get_num_pqs(p_hwfn);
401
402 if (pq_idx > max_pq)
403 DP_ERR(p_hwfn,
404 "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq);
405
406 /* init pq params */
407 qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport +
408 qm_info->num_vports;
409 qm_info->qm_pq_params[pq_idx].tc_id = tc;
410 qm_info->qm_pq_params[pq_idx].wrr_group = PQ_INIT_DEFAULT_WRR_GROUP;
411 qm_info->qm_pq_params[pq_idx].rl_valid =
412 (pq_init_flags & PQ_INIT_PF_RL || pq_init_flags & PQ_INIT_VF_RL);
413
414 /* qm params accounting */
415 qm_info->num_pqs++;
416 if (!(pq_init_flags & PQ_INIT_SHARE_VPORT))
417 qm_info->num_vports++;
418
419 if (pq_init_flags & PQ_INIT_PF_RL)
420 qm_info->num_pf_rls++;
421
422 if (qm_info->num_vports > qed_init_qm_get_num_vports(p_hwfn))
423 DP_ERR(p_hwfn,
424 "vport overflow! qm_info->num_vports %d, qm_init_get_num_vports() %d\n",
425 qm_info->num_vports, qed_init_qm_get_num_vports(p_hwfn));
426
427 if (qm_info->num_pf_rls > qed_init_qm_get_num_pf_rls(p_hwfn))
428 DP_ERR(p_hwfn,
429 "rl overflow! qm_info->num_pf_rls %d, qm_init_get_num_pf_rls() %d\n",
430 qm_info->num_pf_rls, qed_init_qm_get_num_pf_rls(p_hwfn));
431}
432
433/* get pq index according to PQ_FLAGS */
434static u16 *qed_init_qm_get_idx_from_flags(struct qed_hwfn *p_hwfn,
435 u32 pq_flags)
436{
437 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
438
439 /* Can't have multiple flags set here */
440 if (bitmap_weight((unsigned long *)&pq_flags, sizeof(pq_flags)) > 1)
441 goto err;
442
443 switch (pq_flags) {
444 case PQ_FLAGS_RLS:
445 return &qm_info->first_rl_pq;
446 case PQ_FLAGS_MCOS:
447 return &qm_info->first_mcos_pq;
448 case PQ_FLAGS_LB:
449 return &qm_info->pure_lb_pq;
450 case PQ_FLAGS_OOO:
451 return &qm_info->ooo_pq;
452 case PQ_FLAGS_ACK:
453 return &qm_info->pure_ack_pq;
454 case PQ_FLAGS_OFLD:
455 return &qm_info->offload_pq;
456 case PQ_FLAGS_LLT:
457 return &qm_info->low_latency_pq;
458 case PQ_FLAGS_VFS:
459 return &qm_info->first_vf_pq;
460 default:
461 goto err;
462 }
463
464err:
465 DP_ERR(p_hwfn, "BAD pq flags %d\n", pq_flags);
466 return NULL;
467}
468
469/* save pq index in qm info */
470static void qed_init_qm_set_idx(struct qed_hwfn *p_hwfn,
471 u32 pq_flags, u16 pq_val)
472{
473 u16 *base_pq_idx = qed_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
474
475 *base_pq_idx = p_hwfn->qm_info.start_pq + pq_val;
476}
477
478/* get tx pq index, with the PQ TX base already set (ready for context init) */
479u16 qed_get_cm_pq_idx(struct qed_hwfn *p_hwfn, u32 pq_flags)
480{
481 u16 *base_pq_idx = qed_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
482
483 return *base_pq_idx + CM_TX_PQ_BASE;
484}
485
486u16 qed_get_cm_pq_idx_mcos(struct qed_hwfn *p_hwfn, u8 tc)
487{
488 u8 max_tc = qed_init_qm_get_num_tcs(p_hwfn);
489
490 if (tc > max_tc)
491 DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc);
492
493 return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + tc;
494}
495
496u16 qed_get_cm_pq_idx_vf(struct qed_hwfn *p_hwfn, u16 vf)
497{
498 u16 max_vf = qed_init_qm_get_num_vfs(p_hwfn);
499
500 if (vf > max_vf)
501 DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf);
502
503 return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + vf;
504}
505
506u16 qed_get_cm_pq_idx_rl(struct qed_hwfn *p_hwfn, u8 rl)
507{
508 u16 max_rl = qed_init_qm_get_num_pf_rls(p_hwfn);
509
510 if (rl > max_rl)
511 DP_ERR(p_hwfn, "rl %d must be smaller than %d\n", rl, max_rl);
512
513 return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_RLS) + rl;
514}
515
516/* Functions for creating specific types of pqs */
517static void qed_init_qm_lb_pq(struct qed_hwfn *p_hwfn)
518{
519 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
520
521 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_LB))
522 return;
523
524 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_LB, qm_info->num_pqs);
525 qed_init_qm_pq(p_hwfn, qm_info, PURE_LB_TC, PQ_INIT_SHARE_VPORT);
526}
527
528static void qed_init_qm_ooo_pq(struct qed_hwfn *p_hwfn)
529{
530 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
531
532 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_OOO))
533 return;
534
535 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_OOO, qm_info->num_pqs);
536 qed_init_qm_pq(p_hwfn, qm_info, qm_info->ooo_tc, PQ_INIT_SHARE_VPORT);
537}
538
539static void qed_init_qm_pure_ack_pq(struct qed_hwfn *p_hwfn)
540{
541 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
542
543 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_ACK))
544 return;
545
546 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_ACK, qm_info->num_pqs);
547 qed_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
548}
549
550static void qed_init_qm_offload_pq(struct qed_hwfn *p_hwfn)
551{
552 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
553
554 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_OFLD))
555 return;
556
557 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_OFLD, qm_info->num_pqs);
558 qed_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
559}
560
561static void qed_init_qm_low_latency_pq(struct qed_hwfn *p_hwfn)
562{
563 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
564
565 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_LLT))
566 return;
567
568 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_LLT, qm_info->num_pqs);
569 qed_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
570}
571
572static void qed_init_qm_mcos_pqs(struct qed_hwfn *p_hwfn)
573{
574 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
575 u8 tc_idx;
576
577 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_MCOS))
578 return;
579
580 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_MCOS, qm_info->num_pqs);
581 for (tc_idx = 0; tc_idx < qed_init_qm_get_num_tcs(p_hwfn); tc_idx++)
582 qed_init_qm_pq(p_hwfn, qm_info, tc_idx, PQ_INIT_SHARE_VPORT);
583}
584
585static void qed_init_qm_vf_pqs(struct qed_hwfn *p_hwfn)
586{
587 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
588 u16 vf_idx, num_vfs = qed_init_qm_get_num_vfs(p_hwfn);
589
590 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_VFS))
591 return;
592
593 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_VFS, qm_info->num_pqs);
1408cc1f 594 qm_info->num_vf_pqs = num_vfs;
b5a9ee7c
AE		 595 for (vf_idx = 0; vf_idx < num_vfs; vf_idx++)
596 qed_init_qm_pq(p_hwfn,
597 qm_info, PQ_INIT_DEFAULT_TC, PQ_INIT_VF_RL);
598}
fe56b9e6 599
b5a9ee7c
AE		 600static void qed_init_qm_rl_pqs(struct qed_hwfn *p_hwfn)
601{
602 u16 pf_rls_idx, num_pf_rls = qed_init_qm_get_num_pf_rls(p_hwfn);
603 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
a64b02d5 604
b5a9ee7c
AE		 605 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_RLS))
606 return;
607
608 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_RLS, qm_info->num_pqs);
609 for (pf_rls_idx = 0; pf_rls_idx < num_pf_rls; pf_rls_idx++)
610 qed_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_PF_RL);
611}
612
613static void qed_init_qm_pq_params(struct qed_hwfn *p_hwfn)
614{
615 /* rate limited pqs, must come first (FW assumption) */
616 qed_init_qm_rl_pqs(p_hwfn);
617
618 /* pqs for multi cos */
619 qed_init_qm_mcos_pqs(p_hwfn);
620
621 /* pure loopback pq */
622 qed_init_qm_lb_pq(p_hwfn);
623
624 /* out of order pq */
625 qed_init_qm_ooo_pq(p_hwfn);
626
627 /* pure ack pq */
628 qed_init_qm_pure_ack_pq(p_hwfn);
629
630 /* pq for offloaded protocol */
631 qed_init_qm_offload_pq(p_hwfn);
632
633 /* low latency pq */
634 qed_init_qm_low_latency_pq(p_hwfn);
635
636 /* done sharing vports */
637 qed_init_qm_advance_vport(p_hwfn);
638
639 /* pqs for vfs */
640 qed_init_qm_vf_pqs(p_hwfn);
641}
642
643/* compare values of getters against resources amounts */
644static int qed_init_qm_sanity(struct qed_hwfn *p_hwfn)
645{
646 if (qed_init_qm_get_num_vports(p_hwfn) > RESC_NUM(p_hwfn, QED_VPORT)) {
647 DP_ERR(p_hwfn, "requested amount of vports exceeds resource\n");
648 return -EINVAL;
649 }
650
651 if (qed_init_qm_get_num_pqs(p_hwfn) > RESC_NUM(p_hwfn, QED_PQ)) {
652 DP_ERR(p_hwfn, "requested amount of pqs exceeds resource\n");
653 return -EINVAL;
654 }
fe56b9e6
YM		 655
656 return 0;
b5a9ee7c 657}
fe56b9e6 658
b5a9ee7c
AE		 659static void qed_dp_init_qm_params(struct qed_hwfn *p_hwfn)
660{
661 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
662 struct init_qm_vport_params *vport;
663 struct init_qm_port_params *port;
664 struct init_qm_pq_params *pq;
665 int i, tc;
666
667 /* top level params */
668 DP_VERBOSE(p_hwfn,
669 NETIF_MSG_HW,
670 "qm init top level params: start_pq %d, start_vport %d, pure_lb_pq %d, offload_pq %d, pure_ack_pq %d\n",
671 qm_info->start_pq,
672 qm_info->start_vport,
673 qm_info->pure_lb_pq,
674 qm_info->offload_pq, qm_info->pure_ack_pq);
675 DP_VERBOSE(p_hwfn,
676 NETIF_MSG_HW,
677 "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d, num_vports %d, max_phys_tcs_per_port %d\n",
678 qm_info->ooo_pq,
679 qm_info->first_vf_pq,
680 qm_info->num_pqs,
681 qm_info->num_vf_pqs,
682 qm_info->num_vports, qm_info->max_phys_tcs_per_port);
683 DP_VERBOSE(p_hwfn,
684 NETIF_MSG_HW,
685 "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d, pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n",
686 qm_info->pf_rl_en,
687 qm_info->pf_wfq_en,
688 qm_info->vport_rl_en,
689 qm_info->vport_wfq_en,
690 qm_info->pf_wfq,
691 qm_info->pf_rl,
692 qm_info->num_pf_rls, qed_get_pq_flags(p_hwfn));
693
694 /* port table */
695 for (i = 0; i < p_hwfn->cdev->num_ports_in_engines; i++) {
696 port = &(qm_info->qm_port_params[i]);
697 DP_VERBOSE(p_hwfn,
698 NETIF_MSG_HW,
699 "port idx %d, active %d, active_phys_tcs %d, num_pbf_cmd_lines %d, num_btb_blocks %d, reserved %d\n",
700 i,
701 port->active,
702 port->active_phys_tcs,
703 port->num_pbf_cmd_lines,
704 port->num_btb_blocks, port->reserved);
705 }
706
707 /* vport table */
708 for (i = 0; i < qm_info->num_vports; i++) {
709 vport = &(qm_info->qm_vport_params[i]);
710 DP_VERBOSE(p_hwfn,
711 NETIF_MSG_HW,
712 "vport idx %d, vport_rl %d, wfq %d, first_tx_pq_id [ ",
713 qm_info->start_vport + i,
714 vport->vport_rl, vport->vport_wfq);
715 for (tc = 0; tc < NUM_OF_TCS; tc++)
716 DP_VERBOSE(p_hwfn,
717 NETIF_MSG_HW,
718 "%d ", vport->first_tx_pq_id[tc]);
719 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "]\n");
720 }
721
722 /* pq table */
723 for (i = 0; i < qm_info->num_pqs; i++) {
724 pq = &(qm_info->qm_pq_params[i]);
725 DP_VERBOSE(p_hwfn,
726 NETIF_MSG_HW,
727 "pq idx %d, vport_id %d, tc %d, wrr_grp %d, rl_valid %d\n",
728 qm_info->start_pq + i,
729 pq->vport_id,
730 pq->tc_id, pq->wrr_group, pq->rl_valid);
731 }
732}
733
734static void qed_init_qm_info(struct qed_hwfn *p_hwfn)
735{
736 /* reset params required for init run */
737 qed_init_qm_reset_params(p_hwfn);
738
739 /* init QM top level params */
740 qed_init_qm_params(p_hwfn);
741
742 /* init QM port params */
743 qed_init_qm_port_params(p_hwfn);
744
745 /* init QM vport params */
746 qed_init_qm_vport_params(p_hwfn);
747
748 /* init QM physical queue params */
749 qed_init_qm_pq_params(p_hwfn);
750
751 /* display all that init */
752 qed_dp_init_qm_params(p_hwfn);
fe56b9e6
YM		 753}
754
39651abd
SRK		 755/* This function reconfigures the QM pf on the fly.
756 * For this purpose we:
757 * 1. reconfigure the QM database
758 * 2. set new values to runtime arrat
759 * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
760 * 4. activate init tool in QM_PF stage
761 * 5. send an sdm_qm_cmd through rbc interface to release the QM
762 */
763int qed_qm_reconf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
764{
765 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
766 bool b_rc;
767 int rc;
768
39651abd 769 /* initialize qed's qm data structure */
b5a9ee7c 770 qed_init_qm_info(p_hwfn);
39651abd
SRK		 771
772 /* stop PF's qm queues */
773 spin_lock_bh(&qm_lock);
774 b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
775 qm_info->start_pq, qm_info->num_pqs);
776 spin_unlock_bh(&qm_lock);
777 if (!b_rc)
778 return -EINVAL;
779
780 /* clear the QM_PF runtime phase leftovers from previous init */
781 qed_init_clear_rt_data(p_hwfn);
782
783 /* prepare QM portion of runtime array */
15582962 784 qed_qm_init_pf(p_hwfn, p_ptt);
39651abd
SRK		 785
786 /* activate init tool on runtime array */
787 rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
788 p_hwfn->hw_info.hw_mode);
789 if (rc)
790 return rc;
791
792 /* start PF's qm queues */
793 spin_lock_bh(&qm_lock);
794 b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
795 qm_info->start_pq, qm_info->num_pqs);
796 spin_unlock_bh(&qm_lock);
797 if (!b_rc)
798 return -EINVAL;
799
800 return 0;
801}
802
b5a9ee7c
AE		 803static int qed_alloc_qm_data(struct qed_hwfn *p_hwfn)
804{
805 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
806 int rc;
807
808 rc = qed_init_qm_sanity(p_hwfn);
809 if (rc)
810 goto alloc_err;
811
812 qm_info->qm_pq_params = kzalloc(sizeof(*qm_info->qm_pq_params) *
813 qed_init_qm_get_num_pqs(p_hwfn),
814 GFP_KERNEL);
815 if (!qm_info->qm_pq_params)
816 goto alloc_err;
817
818 qm_info->qm_vport_params = kzalloc(sizeof(*qm_info->qm_vport_params) *
819 qed_init_qm_get_num_vports(p_hwfn),
820 GFP_KERNEL);
821 if (!qm_info->qm_vport_params)
822 goto alloc_err;
823
2f7878c0 824 qm_info->qm_port_params = kzalloc(sizeof(*qm_info->qm_port_params) *
b5a9ee7c
AE		 825 p_hwfn->cdev->num_ports_in_engines,
826 GFP_KERNEL);
827 if (!qm_info->qm_port_params)
828 goto alloc_err;
829
830 qm_info->wfq_data = kzalloc(sizeof(*qm_info->wfq_data) *
831 qed_init_qm_get_num_vports(p_hwfn),
832 GFP_KERNEL);
833 if (!qm_info->wfq_data)
834 goto alloc_err;
835
836 return 0;
837
838alloc_err:
839 DP_NOTICE(p_hwfn, "Failed to allocate memory for QM params\n");
840 qed_qm_info_free(p_hwfn);
841 return -ENOMEM;
842}
843
fe56b9e6
YM		 844int qed_resc_alloc(struct qed_dev *cdev)
845{
fc831825 846 struct qed_iscsi_info *p_iscsi_info;
1e128c81 847 struct qed_fcoe_info *p_fcoe_info;
1d6cff4f 848 struct qed_ooo_info *p_ooo_info;
0a7fb11c
YM		 849#ifdef CONFIG_QED_LL2
850 struct qed_ll2_info *p_ll2_info;
851#endif
f9dc4d1f 852 u32 rdma_tasks, excess_tasks;
fe56b9e6
YM		 853 struct qed_consq *p_consq;
854 struct qed_eq *p_eq;
f9dc4d1f 855 u32 line_count;
fe56b9e6
YM		 856 int i, rc = 0;
857
1408cc1f
YM		 858 if (IS_VF(cdev))
859 return rc;
860
fe56b9e6
YM		 861 cdev->fw_data = kzalloc(sizeof(*cdev->fw_data), GFP_KERNEL);
862 if (!cdev->fw_data)
863 return -ENOMEM;
864
865 for_each_hwfn(cdev, i) {
866 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
dbb799c3 867 u32 n_eqes, num_cons;
fe56b9e6
YM		 868
869 /* First allocate the context manager structure */
870 rc = qed_cxt_mngr_alloc(p_hwfn);
871 if (rc)
872 goto alloc_err;
873
874 /* Set the HW cid/tid numbers (in the contest manager)
875 * Must be done prior to any further computations.
876 */
f9dc4d1f 877 rc = qed_cxt_set_pf_params(p_hwfn, RDMA_MAX_TIDS);
fe56b9e6
YM		 878 if (rc)
879 goto alloc_err;
880
b5a9ee7c 881 rc = qed_alloc_qm_data(p_hwfn);
fe56b9e6
YM		 882 if (rc)
883 goto alloc_err;
884
b5a9ee7c
AE		 885 /* init qm info */
886 qed_init_qm_info(p_hwfn);
887
fe56b9e6 888 /* Compute the ILT client partition */
f9dc4d1f
RA		 889 rc = qed_cxt_cfg_ilt_compute(p_hwfn, &line_count);
890 if (rc) {
891 DP_NOTICE(p_hwfn,
892 "too many ILT lines; re-computing with less lines\n");
893 /* In case there are not enough ILT lines we reduce the
894 * number of RDMA tasks and re-compute.
895 */
896 excess_tasks =
897 qed_cxt_cfg_ilt_compute_excess(p_hwfn, line_count);
898 if (!excess_tasks)
899 goto alloc_err;
900
901 rdma_tasks = RDMA_MAX_TIDS - excess_tasks;
902 rc = qed_cxt_set_pf_params(p_hwfn, rdma_tasks);
903 if (rc)
904 goto alloc_err;
905
906 rc = qed_cxt_cfg_ilt_compute(p_hwfn, &line_count);
907 if (rc) {
908 DP_ERR(p_hwfn,
909 "failed ILT compute. Requested too many lines: %u\n",
910 line_count);
911
912 goto alloc_err;
913 }
914 }
fe56b9e6
YM		 915
916 /* CID map / ILT shadow table / T2
917 * The talbes sizes are determined by the computations above
918 */
919 rc = qed_cxt_tables_alloc(p_hwfn);
920 if (rc)
921 goto alloc_err;
922
923 /* SPQ, must follow ILT because initializes SPQ context */
924 rc = qed_spq_alloc(p_hwfn);
925 if (rc)
926 goto alloc_err;
927
928 /* SP status block allocation */
929 p_hwfn->p_dpc_ptt = qed_get_reserved_ptt(p_hwfn,
930 RESERVED_PTT_DPC);
931
932 rc = qed_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
933 if (rc)
934 goto alloc_err;
935
32a47e72
YM		 936 rc = qed_iov_alloc(p_hwfn);
937 if (rc)
938 goto alloc_err;
939
fe56b9e6 940 /* EQ */
dbb799c3
YM		 941 n_eqes = qed_chain_get_capacity(&p_hwfn->p_spq->chain);
942 if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE) {
943 num_cons = qed_cxt_get_proto_cid_count(p_hwfn,
944 PROTOCOLID_ROCE,
8c93beaf 945 NULL) * 2;
dbb799c3
YM		 946 n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
947 } else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
948 num_cons =
949 qed_cxt_get_proto_cid_count(p_hwfn,
8c93beaf
YM		 950 PROTOCOLID_ISCSI,
951 NULL);
dbb799c3
YM		 952 n_eqes += 2 * num_cons;
953 }
954
955 if (n_eqes > 0xFFFF) {
956 DP_ERR(p_hwfn,
957 "Cannot allocate 0x%x EQ elements. The maximum of a u16 chain is 0x%x\n",
958 n_eqes, 0xFFFF);
1b4985b5 959 rc = -EINVAL;
fe56b9e6 960 goto alloc_err;
9b15acbf 961 }
dbb799c3
YM		 962
963 p_eq = qed_eq_alloc(p_hwfn, (u16) n_eqes);
964 if (!p_eq)
965 goto alloc_no_mem;
fe56b9e6
YM		 966 p_hwfn->p_eq = p_eq;
967
968 p_consq = qed_consq_alloc(p_hwfn);
dbb799c3
YM		 969 if (!p_consq)
970 goto alloc_no_mem;
fe56b9e6
YM		 971 p_hwfn->p_consq = p_consq;
972
0a7fb11c
YM		 973#ifdef CONFIG_QED_LL2
974 if (p_hwfn->using_ll2) {
975 p_ll2_info = qed_ll2_alloc(p_hwfn);
976 if (!p_ll2_info)
977 goto alloc_no_mem;
978 p_hwfn->p_ll2_info = p_ll2_info;
979 }
980#endif
1e128c81
AE		 981
982 if (p_hwfn->hw_info.personality == QED_PCI_FCOE) {
983 p_fcoe_info = qed_fcoe_alloc(p_hwfn);
984 if (!p_fcoe_info)
985 goto alloc_no_mem;
986 p_hwfn->p_fcoe_info = p_fcoe_info;
987 }
988
fc831825
YM		 989 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
990 p_iscsi_info = qed_iscsi_alloc(p_hwfn);
991 if (!p_iscsi_info)
992 goto alloc_no_mem;
993 p_hwfn->p_iscsi_info = p_iscsi_info;
1d6cff4f
YM		 994 p_ooo_info = qed_ooo_alloc(p_hwfn);
995 if (!p_ooo_info)
996 goto alloc_no_mem;
997 p_hwfn->p_ooo_info = p_ooo_info;
fc831825 998 }
0a7fb11c 999
fe56b9e6
YM		 1000 /* DMA info initialization */
1001 rc = qed_dmae_info_alloc(p_hwfn);
2591c280 1002 if (rc)
fe56b9e6 1003 goto alloc_err;
39651abd
SRK		 1004
1005 /* DCBX initialization */
1006 rc = qed_dcbx_info_alloc(p_hwfn);
2591c280 1007 if (rc)
39651abd 1008 goto alloc_err;
fe56b9e6
YM		 1009 }
1010
1011 cdev->reset_stats = kzalloc(sizeof(*cdev->reset_stats), GFP_KERNEL);
2591c280 1012 if (!cdev->reset_stats)
83aeb933 1013 goto alloc_no_mem;
fe56b9e6
YM		 1014
1015 return 0;
1016
dbb799c3
YM		 1017alloc_no_mem:
1018 rc = -ENOMEM;
fe56b9e6
YM		 1019alloc_err:
1020 qed_resc_free(cdev);
1021 return rc;
1022}
1023
1024void qed_resc_setup(struct qed_dev *cdev)
1025{
1026 int i;
1027
1408cc1f
YM		 1028 if (IS_VF(cdev))
1029 return;
1030
fe56b9e6
YM		 1031 for_each_hwfn(cdev, i) {
1032 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1033
1034 qed_cxt_mngr_setup(p_hwfn);
1035 qed_spq_setup(p_hwfn);
1036 qed_eq_setup(p_hwfn, p_hwfn->p_eq);
1037 qed_consq_setup(p_hwfn, p_hwfn->p_consq);
1038
1039 /* Read shadow of current MFW mailbox */
1040 qed_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
1041 memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
1042 p_hwfn->mcp_info->mfw_mb_cur,
1043 p_hwfn->mcp_info->mfw_mb_length);
1044
1045 qed_int_setup(p_hwfn, p_hwfn->p_main_ptt);
32a47e72
YM		 1046
1047 qed_iov_setup(p_hwfn, p_hwfn->p_main_ptt);
0a7fb11c
YM		 1048#ifdef CONFIG_QED_LL2
1049 if (p_hwfn->using_ll2)
1050 qed_ll2_setup(p_hwfn, p_hwfn->p_ll2_info);
1051#endif
1e128c81
AE		 1052 if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
1053 qed_fcoe_setup(p_hwfn, p_hwfn->p_fcoe_info);
1054
1d6cff4f 1055 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
fc831825 1056 qed_iscsi_setup(p_hwfn, p_hwfn->p_iscsi_info);
1d6cff4f
YM		 1057 qed_ooo_setup(p_hwfn, p_hwfn->p_ooo_info);
1058 }
fe56b9e6
YM		 1059 }
1060}
1061
fe56b9e6
YM		 1062#define FINAL_CLEANUP_POLL_CNT (100)
1063#define FINAL_CLEANUP_POLL_TIME (10)
1064int qed_final_cleanup(struct qed_hwfn *p_hwfn,
0b55e27d 1065 struct qed_ptt *p_ptt, u16 id, bool is_vf)
fe56b9e6
YM		 1066{
1067 u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
1068 int rc = -EBUSY;
1069
fc48b7a6
YM		 1070 addr = GTT_BAR0_MAP_REG_USDM_RAM +
1071 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
fe56b9e6 1072
0b55e27d
YM		 1073 if (is_vf)
1074 id += 0x10;
1075
fc48b7a6
YM		 1076 command |= X_FINAL_CLEANUP_AGG_INT <<
1077 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
1078 command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
1079 command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
1080 command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
fe56b9e6
YM		 1081
1082 /* Make sure notification is not set before initiating final cleanup */
1083 if (REG_RD(p_hwfn, addr)) {
1a635e48
YM		 1084 DP_NOTICE(p_hwfn,
1085 "Unexpected; Found final cleanup notification before initiating final cleanup\n");
fe56b9e6
YM		 1086 REG_WR(p_hwfn, addr, 0);
1087 }
1088
1089 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
1090 "Sending final cleanup for PFVF[%d] [Command %08x\n]",
1091 id, command);
1092
1093 qed_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
1094
1095 /* Poll until completion */
1096 while (!REG_RD(p_hwfn, addr) && count--)
1097 msleep(FINAL_CLEANUP_POLL_TIME);
1098
1099 if (REG_RD(p_hwfn, addr))
1100 rc = 0;
1101 else
1102 DP_NOTICE(p_hwfn,
1103 "Failed to receive FW final cleanup notification\n");
1104
1105 /* Cleanup afterwards */
1106 REG_WR(p_hwfn, addr, 0);
1107
1108 return rc;
1109}
1110
9c79ddaa 1111static int qed_calc_hw_mode(struct qed_hwfn *p_hwfn)
fe56b9e6
YM		 1112{
1113 int hw_mode = 0;
1114
9c79ddaa
MY		 1115 if (QED_IS_BB_B0(p_hwfn->cdev)) {
1116 hw_mode |= 1 << MODE_BB;
1117 } else if (QED_IS_AH(p_hwfn->cdev)) {
1118 hw_mode |= 1 << MODE_K2;
1119 } else {
1120 DP_NOTICE(p_hwfn, "Unknown chip type %#x\n",
1121 p_hwfn->cdev->type);
1122 return -EINVAL;
1123 }
fe56b9e6
YM		 1124
1125 switch (p_hwfn->cdev->num_ports_in_engines) {
1126 case 1:
1127 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
1128 break;
1129 case 2:
1130 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
1131 break;
1132 case 4:
1133 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
1134 break;
1135 default:
1136 DP_NOTICE(p_hwfn, "num_ports_in_engine = %d not supported\n",
1137 p_hwfn->cdev->num_ports_in_engines);
9c79ddaa 1138 return -EINVAL;
fe56b9e6
YM		 1139 }
1140
1141 switch (p_hwfn->cdev->mf_mode) {
fc48b7a6
YM		 1142 case QED_MF_DEFAULT:
1143 case QED_MF_NPAR:
1144 hw_mode |= 1 << MODE_MF_SI;
fe56b9e6 1145 break;
fc48b7a6 1146 case QED_MF_OVLAN:
fe56b9e6
YM		 1147 hw_mode |= 1 << MODE_MF_SD;
1148 break;
fe56b9e6 1149 default:
fc48b7a6
YM		 1150 DP_NOTICE(p_hwfn, "Unsupported MF mode, init as DEFAULT\n");
1151 hw_mode |= 1 << MODE_MF_SI;
fe56b9e6
YM		 1152 }
1153
1154 hw_mode |= 1 << MODE_ASIC;
1155
1af9dcf7
YM		 1156 if (p_hwfn->cdev->num_hwfns > 1)
1157 hw_mode |= 1 << MODE_100G;
1158
fe56b9e6 1159 p_hwfn->hw_info.hw_mode = hw_mode;
1af9dcf7
YM		 1160
1161 DP_VERBOSE(p_hwfn, (NETIF_MSG_PROBE | NETIF_MSG_IFUP),
1162 "Configuring function for hw_mode: 0x%08x\n",
1163 p_hwfn->hw_info.hw_mode);
9c79ddaa
MY		 1164
1165 return 0;
fe56b9e6
YM		 1166}
1167
1168/* Init run time data for all PFs on an engine. */
1169static void qed_init_cau_rt_data(struct qed_dev *cdev)
1170{
1171 u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
1172 int i, sb_id;
1173
1174 for_each_hwfn(cdev, i) {
1175 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1176 struct qed_igu_info *p_igu_info;
1177 struct qed_igu_block *p_block;
1178 struct cau_sb_entry sb_entry;
1179
1180 p_igu_info = p_hwfn->hw_info.p_igu_info;
1181
1182 for (sb_id = 0; sb_id < QED_MAPPING_MEMORY_SIZE(cdev);
1183 sb_id++) {
1184 p_block = &p_igu_info->igu_map.igu_blocks[sb_id];
1185 if (!p_block->is_pf)
1186 continue;
1187
1188 qed_init_cau_sb_entry(p_hwfn, &sb_entry,
1a635e48
YM		 1189 p_block->function_id, 0, 0);
1190 STORE_RT_REG_AGG(p_hwfn, offset + sb_id * 2, sb_entry);
fe56b9e6
YM		 1191 }
1192 }
1193}
1194
60afed72
TT		 1195static void qed_init_cache_line_size(struct qed_hwfn *p_hwfn,
1196 struct qed_ptt *p_ptt)
1197{
1198 u32 val, wr_mbs, cache_line_size;
1199
1200 val = qed_rd(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0);
1201 switch (val) {
1202 case 0:
1203 wr_mbs = 128;
1204 break;
1205 case 1:
1206 wr_mbs = 256;
1207 break;
1208 case 2:
1209 wr_mbs = 512;
1210 break;
1211 default:
1212 DP_INFO(p_hwfn,
1213 "Unexpected value of PSWRQ2_REG_WR_MBS0 [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
1214 val);
1215 return;
1216 }
1217
1218 cache_line_size = min_t(u32, L1_CACHE_BYTES, wr_mbs);
1219 switch (cache_line_size) {
1220 case 32:
1221 val = 0;
1222 break;
1223 case 64:
1224 val = 1;
1225 break;
1226 case 128:
1227 val = 2;
1228 break;
1229 case 256:
1230 val = 3;
1231 break;
1232 default:
1233 DP_INFO(p_hwfn,
1234 "Unexpected value of cache line size [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
1235 cache_line_size);
1236 }
1237
1238 if (L1_CACHE_BYTES > wr_mbs)
1239 DP_INFO(p_hwfn,
1240 "The cache line size for padding is suboptimal for performance [OS cache line size 0x%x, wr mbs 0x%x]\n",
1241 L1_CACHE_BYTES, wr_mbs);
1242
1243 STORE_RT_REG(p_hwfn, PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET, val);
1244}
1245
fe56b9e6 1246static int qed_hw_init_common(struct qed_hwfn *p_hwfn,
1a635e48 1247 struct qed_ptt *p_ptt, int hw_mode)
fe56b9e6
YM		 1248{
1249 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1250 struct qed_qm_common_rt_init_params params;
1251 struct qed_dev *cdev = p_hwfn->cdev;
9c79ddaa 1252 u8 vf_id, max_num_vfs;
dbb799c3 1253 u16 num_pfs, pf_id;
1408cc1f 1254 u32 concrete_fid;
fe56b9e6
YM		 1255 int rc = 0;
1256
1257 qed_init_cau_rt_data(cdev);
1258
1259 /* Program GTT windows */
1260 qed_gtt_init(p_hwfn);
1261
1262 if (p_hwfn->mcp_info) {
1263 if (p_hwfn->mcp_info->func_info.bandwidth_max)
1264 qm_info->pf_rl_en = 1;
1265 if (p_hwfn->mcp_info->func_info.bandwidth_min)
1266 qm_info->pf_wfq_en = 1;
1267 }
1268
1269 memset(&params, 0, sizeof(params));
1270 params.max_ports_per_engine = p_hwfn->cdev->num_ports_in_engines;
1271 params.max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port;
1272 params.pf_rl_en = qm_info->pf_rl_en;
1273 params.pf_wfq_en = qm_info->pf_wfq_en;
1274 params.vport_rl_en = qm_info->vport_rl_en;
1275 params.vport_wfq_en = qm_info->vport_wfq_en;
1276 params.port_params = qm_info->qm_port_params;
1277
1278 qed_qm_common_rt_init(p_hwfn, &params);
1279
1280 qed_cxt_hw_init_common(p_hwfn);
1281
60afed72
TT		 1282 qed_init_cache_line_size(p_hwfn, p_ptt);
1283
fe56b9e6 1284 rc = qed_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
1a635e48 1285 if (rc)
fe56b9e6
YM		 1286 return rc;
1287
1288 qed_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
1289 qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
1290
dbb799c3
YM		 1291 if (QED_IS_BB(p_hwfn->cdev)) {
1292 num_pfs = NUM_OF_ENG_PFS(p_hwfn->cdev);
1293 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
1294 qed_fid_pretend(p_hwfn, p_ptt, pf_id);
1295 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1296 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1297 }
1298 /* pretend to original PF */
1299 qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1300 }
fe56b9e6 1301
9c79ddaa
MY		 1302 max_num_vfs = QED_IS_AH(cdev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB;
1303 for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
1408cc1f
YM		 1304 concrete_fid = qed_vfid_to_concrete(p_hwfn, vf_id);
1305 qed_fid_pretend(p_hwfn, p_ptt, (u16) concrete_fid);
1306 qed_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
05fafbfb
YM		 1307 qed_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
1308 qed_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
1309 qed_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
1408cc1f
YM		 1310 }
1311 /* pretend to original PF */
1312 qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1313
fe56b9e6
YM		 1314 return rc;
1315}
1316
51ff1725
RA		 1317static int
1318qed_hw_init_dpi_size(struct qed_hwfn *p_hwfn,
1319 struct qed_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
1320{
1321 u32 dpi_page_size_1, dpi_page_size_2, dpi_page_size;
1322 u32 dpi_bit_shift, dpi_count;
1323 u32 min_dpis;
1324
1325 /* Calculate DPI size */
1326 dpi_page_size_1 = QED_WID_SIZE * n_cpus;
1327 dpi_page_size_2 = max_t(u32, QED_WID_SIZE, PAGE_SIZE);
1328 dpi_page_size = max_t(u32, dpi_page_size_1, dpi_page_size_2);
1329 dpi_page_size = roundup_pow_of_two(dpi_page_size);
1330 dpi_bit_shift = ilog2(dpi_page_size / 4096);
1331
1332 dpi_count = pwm_region_size / dpi_page_size;
1333
1334 min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
1335 min_dpis = max_t(u32, QED_MIN_DPIS, min_dpis);
1336
1337 p_hwfn->dpi_size = dpi_page_size;
1338 p_hwfn->dpi_count = dpi_count;
1339
1340 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
1341
1342 if (dpi_count < min_dpis)
1343 return -EINVAL;
1344
1345 return 0;
1346}
1347
1348enum QED_ROCE_EDPM_MODE {
1349 QED_ROCE_EDPM_MODE_ENABLE = 0,
1350 QED_ROCE_EDPM_MODE_FORCE_ON = 1,
1351 QED_ROCE_EDPM_MODE_DISABLE = 2,
1352};
1353
1354static int
1355qed_hw_init_pf_doorbell_bar(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1356{
1357 u32 pwm_regsize, norm_regsize;
1358 u32 non_pwm_conn, min_addr_reg1;
1359 u32 db_bar_size, n_cpus;
1360 u32 roce_edpm_mode;
1361 u32 pf_dems_shift;
1362 int rc = 0;
1363 u8 cond;
1364
15582962 1365 db_bar_size = qed_hw_bar_size(p_hwfn, p_ptt, BAR_ID_1);
51ff1725
RA		 1366 if (p_hwfn->cdev->num_hwfns > 1)
1367 db_bar_size /= 2;
1368
1369 /* Calculate doorbell regions */
1370 non_pwm_conn = qed_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
1371 qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
1372 NULL) +
1373 qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH,
1374 NULL);
1375 norm_regsize = roundup(QED_PF_DEMS_SIZE * non_pwm_conn, 4096);
1376 min_addr_reg1 = norm_regsize / 4096;
1377 pwm_regsize = db_bar_size - norm_regsize;
1378
1379 /* Check that the normal and PWM sizes are valid */
1380 if (db_bar_size < norm_regsize) {
1381 DP_ERR(p_hwfn->cdev,
1382 "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
1383 db_bar_size, norm_regsize);
1384 return -EINVAL;
1385 }
1386
1387 if (pwm_regsize < QED_MIN_PWM_REGION) {
1388 DP_ERR(p_hwfn->cdev,
1389 "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
1390 pwm_regsize,
1391 QED_MIN_PWM_REGION, db_bar_size, norm_regsize);
1392 return -EINVAL;
1393 }
1394
1395 /* Calculate number of DPIs */
1396 roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
1397 if ((roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE) ||
1398 ((roce_edpm_mode == QED_ROCE_EDPM_MODE_FORCE_ON))) {
1399 /* Either EDPM is mandatory, or we are attempting to allocate a
1400 * WID per CPU.
1401 */
c2dedf87 1402 n_cpus = num_present_cpus();
51ff1725
RA		 1403 rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1404 }
1405
1406 cond = (rc && (roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE)) ||
1407 (roce_edpm_mode == QED_ROCE_EDPM_MODE_DISABLE);
1408 if (cond || p_hwfn->dcbx_no_edpm) {
1409 /* Either EDPM is disabled from user configuration, or it is
1410 * disabled via DCBx, or it is not mandatory and we failed to
1411 * allocated a WID per CPU.
1412 */
1413 n_cpus = 1;
1414 rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1415
1416 if (cond)
1417 qed_rdma_dpm_bar(p_hwfn, p_ptt);
1418 }
1419
1420 DP_INFO(p_hwfn,
1421 "doorbell bar: normal_region_size=%d, pwm_region_size=%d, dpi_size=%d, dpi_count=%d, roce_edpm=%s\n",
1422 norm_regsize,
1423 pwm_regsize,
1424 p_hwfn->dpi_size,
1425 p_hwfn->dpi_count,
1426 ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ?
1427 "disabled" : "enabled");
1428
1429 if (rc) {
1430 DP_ERR(p_hwfn,
1431 "Failed to allocate enough DPIs. Allocated %d but the current minimum is %d.\n",
1432 p_hwfn->dpi_count,
1433 p_hwfn->pf_params.rdma_pf_params.min_dpis);
1434 return -EINVAL;
1435 }
1436
1437 p_hwfn->dpi_start_offset = norm_regsize;
1438
1439 /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
1440 pf_dems_shift = ilog2(QED_PF_DEMS_SIZE / 4);
1441 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
1442 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
1443
1444 return 0;
1445}
1446
fe56b9e6 1447static int qed_hw_init_port(struct qed_hwfn *p_hwfn,
1a635e48 1448 struct qed_ptt *p_ptt, int hw_mode)
fe56b9e6 1449{
05fafbfb
YM		 1450 return qed_init_run(p_hwfn, p_ptt, PHASE_PORT,
1451 p_hwfn->port_id, hw_mode);
fe56b9e6
YM		 1452}
1453
1454static int qed_hw_init_pf(struct qed_hwfn *p_hwfn,
1455 struct qed_ptt *p_ptt,
19968430 1456 struct qed_tunnel_info *p_tunn,
fe56b9e6
YM		 1457 int hw_mode,
1458 bool b_hw_start,
1459 enum qed_int_mode int_mode,
1460 bool allow_npar_tx_switch)
1461{
1462 u8 rel_pf_id = p_hwfn->rel_pf_id;
1463 int rc = 0;
1464
1465 if (p_hwfn->mcp_info) {
1466 struct qed_mcp_function_info *p_info;
1467
1468 p_info = &p_hwfn->mcp_info->func_info;
1469 if (p_info->bandwidth_min)
1470 p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
1471
1472 /* Update rate limit once we'll actually have a link */
4b01e519 1473 p_hwfn->qm_info.pf_rl = 100000;
fe56b9e6
YM		 1474 }
1475
15582962 1476 qed_cxt_hw_init_pf(p_hwfn, p_ptt);
fe56b9e6
YM		 1477
1478 qed_int_igu_init_rt(p_hwfn);
1479
1480 /* Set VLAN in NIG if needed */
1a635e48 1481 if (hw_mode & BIT(MODE_MF_SD)) {
fe56b9e6
YM		 1482 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "Configuring LLH_FUNC_TAG\n");
1483 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
1484 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
1485 p_hwfn->hw_info.ovlan);
1486 }
1487
1488 /* Enable classification by MAC if needed */
1a635e48 1489 if (hw_mode & BIT(MODE_MF_SI)) {
fe56b9e6
YM		 1490 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
1491 "Configuring TAGMAC_CLS_TYPE\n");
1492 STORE_RT_REG(p_hwfn,
1493 NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET, 1);
1494 }
1495
1496 /* Protocl Configuration */
dbb799c3
YM		 1497 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
1498 (p_hwfn->hw_info.personality == QED_PCI_ISCSI) ? 1 : 0);
1e128c81
AE		 1499 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
1500 (p_hwfn->hw_info.personality == QED_PCI_FCOE) ? 1 : 0);
fe56b9e6
YM		 1501 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
1502
1503 /* Cleanup chip from previous driver if such remains exist */
0b55e27d 1504 rc = qed_final_cleanup(p_hwfn, p_ptt, rel_pf_id, false);
1a635e48 1505 if (rc)
fe56b9e6
YM		 1506 return rc;
1507
1508 /* PF Init sequence */
1509 rc = qed_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
1510 if (rc)
1511 return rc;
1512
1513 /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
1514 rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
1515 if (rc)
1516 return rc;
1517
1518 /* Pure runtime initializations - directly to the HW */
1519 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
1520
51ff1725
RA		 1521 rc = qed_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
1522 if (rc)
1523 return rc;
1524
fe56b9e6
YM		 1525 if (b_hw_start) {
1526 /* enable interrupts */
1527 qed_int_igu_enable(p_hwfn, p_ptt, int_mode);
1528
1529 /* send function start command */
831bfb0e
YM		 1530 rc = qed_sp_pf_start(p_hwfn, p_tunn, p_hwfn->cdev->mf_mode,
1531 allow_npar_tx_switch);
1e128c81 1532 if (rc) {
fe56b9e6 1533 DP_NOTICE(p_hwfn, "Function start ramrod failed\n");
1e128c81
AE		 1534 return rc;
1535 }
1536 if (p_hwfn->hw_info.personality == QED_PCI_FCOE) {
1537 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1, BIT(2));
1538 qed_wr(p_hwfn, p_ptt,
1539 PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
1540 0x100);
1541 }
fe56b9e6
YM		 1542 }
1543 return rc;
1544}
1545
1546static int qed_change_pci_hwfn(struct qed_hwfn *p_hwfn,
1547 struct qed_ptt *p_ptt,
1548 u8 enable)
1549{
1550 u32 delay_idx = 0, val, set_val = enable ? 1 : 0;
1551
1552 /* Change PF in PXP */
1553 qed_wr(p_hwfn, p_ptt,
1554 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
1555
1556 /* wait until value is set - try for 1 second every 50us */
1557 for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
1558 val = qed_rd(p_hwfn, p_ptt,
1559 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1560 if (val == set_val)
1561 break;
1562
1563 usleep_range(50, 60);
1564 }
1565
1566 if (val != set_val) {
1567 DP_NOTICE(p_hwfn,
1568 "PFID_ENABLE_MASTER wasn't changed after a second\n");
1569 return -EAGAIN;
1570 }
1571
1572 return 0;
1573}
1574
1575static void qed_reset_mb_shadow(struct qed_hwfn *p_hwfn,
1576 struct qed_ptt *p_main_ptt)
1577{
1578 /* Read shadow of current MFW mailbox */
1579 qed_mcp_read_mb(p_hwfn, p_main_ptt);
1580 memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
1a635e48 1581 p_hwfn->mcp_info->mfw_mb_cur, p_hwfn->mcp_info->mfw_mb_length);
fe56b9e6
YM		 1582}
1583
5d24bcf1
TT		 1584static void
1585qed_fill_load_req_params(struct qed_load_req_params *p_load_req,
1586 struct qed_drv_load_params *p_drv_load)
1587{
1588 memset(p_load_req, 0, sizeof(*p_load_req));
1589
1590 p_load_req->drv_role = p_drv_load->is_crash_kernel ?
1591 QED_DRV_ROLE_KDUMP : QED_DRV_ROLE_OS;
1592 p_load_req->timeout_val = p_drv_load->mfw_timeout_val;
1593 p_load_req->avoid_eng_reset = p_drv_load->avoid_eng_reset;
1594 p_load_req->override_force_load = p_drv_load->override_force_load;
1595}
1596
eaf3c0c6
CM		 1597static int qed_vf_start(struct qed_hwfn *p_hwfn,
1598 struct qed_hw_init_params *p_params)
1599{
1600 if (p_params->p_tunn) {
1601 qed_vf_set_vf_start_tunn_update_param(p_params->p_tunn);
1602 qed_vf_pf_tunnel_param_update(p_hwfn, p_params->p_tunn);
1603 }
1604
1605 p_hwfn->b_int_enabled = 1;
1606
1607 return 0;
1608}
1609
c0c2d0b4 1610int qed_hw_init(struct qed_dev *cdev, struct qed_hw_init_params *p_params)
fe56b9e6 1611{
5d24bcf1 1612 struct qed_load_req_params load_req_params;
0fefbfba
SK		 1613 u32 load_code, param, drv_mb_param;
1614 bool b_default_mtu = true;
1615 struct qed_hwfn *p_hwfn;
1616 int rc = 0, mfw_rc, i;
fe56b9e6 1617
c0c2d0b4 1618 if ((p_params->int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) {
bb13ace7
SRK		 1619 DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n");
1620 return -EINVAL;
1621 }
1622
1408cc1f 1623 if (IS_PF(cdev)) {
c0c2d0b4 1624 rc = qed_init_fw_data(cdev, p_params->bin_fw_data);
1a635e48 1625 if (rc)
1408cc1f
YM		 1626 return rc;
1627 }
fe56b9e6
YM		 1628
1629 for_each_hwfn(cdev, i) {
1630 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1631
0fefbfba
SK		 1632 /* If management didn't provide a default, set one of our own */
1633 if (!p_hwfn->hw_info.mtu) {
1634 p_hwfn->hw_info.mtu = 1500;
1635 b_default_mtu = false;
1636 }
1637
1408cc1f 1638 if (IS_VF(cdev)) {
eaf3c0c6 1639 qed_vf_start(p_hwfn, p_params);
1408cc1f
YM		 1640 continue;
1641 }
1642
fe56b9e6
YM		 1643 /* Enable DMAE in PXP */
1644 rc = qed_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true);
1645
9c79ddaa
MY		 1646 rc = qed_calc_hw_mode(p_hwfn);
1647 if (rc)
1648 return rc;
fe56b9e6 1649
5d24bcf1
TT		 1650 qed_fill_load_req_params(&load_req_params,
1651 p_params->p_drv_load_params);
1652 rc = qed_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt,
1653 &load_req_params);
fe56b9e6 1654 if (rc) {
5d24bcf1 1655 DP_NOTICE(p_hwfn, "Failed sending a LOAD_REQ command\n");
fe56b9e6
YM		 1656 return rc;
1657 }
1658
5d24bcf1 1659 load_code = load_req_params.load_code;
fe56b9e6 1660 DP_VERBOSE(p_hwfn, QED_MSG_SP,
5d24bcf1
TT		 1661 "Load request was sent. Load code: 0x%x\n",
1662 load_code);
1663
1664 qed_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
fe56b9e6
YM		 1665
1666 p_hwfn->first_on_engine = (load_code ==
1667 FW_MSG_CODE_DRV_LOAD_ENGINE);
1668
1669 switch (load_code) {
1670 case FW_MSG_CODE_DRV_LOAD_ENGINE:
1671 rc = qed_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
1672 p_hwfn->hw_info.hw_mode);
1673 if (rc)
1674 break;
1675 /* Fall into */
1676 case FW_MSG_CODE_DRV_LOAD_PORT:
1677 rc = qed_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
1678 p_hwfn->hw_info.hw_mode);
1679 if (rc)
1680 break;
1681
1682 /* Fall into */
1683 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
1684 rc = qed_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
c0c2d0b4
MY		 1685 p_params->p_tunn,
1686 p_hwfn->hw_info.hw_mode,
1687 p_params->b_hw_start,
1688 p_params->int_mode,
1689 p_params->allow_npar_tx_switch);
fe56b9e6
YM		 1690 break;
1691 default:
c0c2d0b4
MY		 1692 DP_NOTICE(p_hwfn,
1693 "Unexpected load code [0x%08x]", load_code);
fe56b9e6
YM		 1694 rc = -EINVAL;
1695 break;
1696 }
1697
1698 if (rc)
1699 DP_NOTICE(p_hwfn,
1700 "init phase failed for loadcode 0x%x (rc %d)\n",
1701 load_code, rc);
1702
1703 /* ACK mfw regardless of success or failure of initialization */
1704 mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1705 DRV_MSG_CODE_LOAD_DONE,
1706 0, &load_code, &param);
1707 if (rc)
1708 return rc;
1709 if (mfw_rc) {
1710 DP_NOTICE(p_hwfn, "Failed sending LOAD_DONE command\n");
1711 return mfw_rc;
1712 }
1713
39651abd
SRK		 1714 /* send DCBX attention request command */
1715 DP_VERBOSE(p_hwfn,
1716 QED_MSG_DCB,
1717 "sending phony dcbx set command to trigger DCBx attention handling\n");
1718 mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1719 DRV_MSG_CODE_SET_DCBX,
1720 1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT,
1721 &load_code, &param);
1722 if (mfw_rc) {
1723 DP_NOTICE(p_hwfn,
1724 "Failed to send DCBX attention request\n");
1725 return mfw_rc;
1726 }
1727
fe56b9e6
YM		 1728 p_hwfn->hw_init_done = true;
1729 }
1730
0fefbfba
SK		 1731 if (IS_PF(cdev)) {
1732 p_hwfn = QED_LEADING_HWFN(cdev);
5d24bcf1 1733 drv_mb_param = STORM_FW_VERSION;
0fefbfba
SK		 1734 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1735 DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER,
1736 drv_mb_param, &load_code, &param);
1737 if (rc)
1738 DP_INFO(p_hwfn, "Failed to update firmware version\n");
1739
1740 if (!b_default_mtu) {
1741 rc = qed_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt,
1742 p_hwfn->hw_info.mtu);
1743 if (rc)
1744 DP_INFO(p_hwfn,
1745 "Failed to update default mtu\n");
1746 }
1747
1748 rc = qed_mcp_ov_update_driver_state(p_hwfn,
1749 p_hwfn->p_main_ptt,
1750 QED_OV_DRIVER_STATE_DISABLED);
1751 if (rc)
1752 DP_INFO(p_hwfn, "Failed to update driver state\n");
1753
1754 rc = qed_mcp_ov_update_eswitch(p_hwfn, p_hwfn->p_main_ptt,
1755 QED_OV_ESWITCH_VEB);
1756 if (rc)
1757 DP_INFO(p_hwfn, "Failed to update eswitch mode\n");
1758 }
1759
fe56b9e6
YM		 1760 return 0;
1761}
1762
1763#define QED_HW_STOP_RETRY_LIMIT (10)
1a635e48
YM		 1764static void qed_hw_timers_stop(struct qed_dev *cdev,
1765 struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
8c925c44
YM		 1766{
1767 int i;
1768
1769 /* close timers */
1770 qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
1771 qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
1772
1773 for (i = 0; i < QED_HW_STOP_RETRY_LIMIT; i++) {
1774 if ((!qed_rd(p_hwfn, p_ptt,
1775 TM_REG_PF_SCAN_ACTIVE_CONN)) &&
1a635e48 1776 (!qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
8c925c44
YM		 1777 break;
1778
1779 /* Dependent on number of connection/tasks, possibly
1780 * 1ms sleep is required between polls
1781 */
1782 usleep_range(1000, 2000);
1783 }
1784
1785 if (i < QED_HW_STOP_RETRY_LIMIT)
1786 return;
1787
1788 DP_NOTICE(p_hwfn,
1789 "Timers linear scans are not over [Connection %02x Tasks %02x]\n",
1790 (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
1791 (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
1792}
1793
1794void qed_hw_timers_stop_all(struct qed_dev *cdev)
1795{
1796 int j;
1797
1798 for_each_hwfn(cdev, j) {
1799 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
1800 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt;
1801
1802 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
1803 }
1804}
1805
fe56b9e6
YM		 1806int qed_hw_stop(struct qed_dev *cdev)
1807{
1226337a
TT		 1808 struct qed_hwfn *p_hwfn;
1809 struct qed_ptt *p_ptt;
1810 int rc, rc2 = 0;
8c925c44 1811 int j;
fe56b9e6
YM		 1812
1813 for_each_hwfn(cdev, j) {
1226337a
TT		 1814 p_hwfn = &cdev->hwfns[j];
1815 p_ptt = p_hwfn->p_main_ptt;
fe56b9e6
YM		 1816
1817 DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Stopping hw/fw\n");
1818
1408cc1f 1819 if (IS_VF(cdev)) {
0b55e27d 1820 qed_vf_pf_int_cleanup(p_hwfn);
1226337a
TT		 1821 rc = qed_vf_pf_reset(p_hwfn);
1822 if (rc) {
1823 DP_NOTICE(p_hwfn,
1824 "qed_vf_pf_reset failed. rc = %d.\n",
1825 rc);
1826 rc2 = -EINVAL;
1827 }
1408cc1f
YM		 1828 continue;
1829 }
1830
fe56b9e6
YM		 1831 /* mark the hw as uninitialized... */
1832 p_hwfn->hw_init_done = false;
1833
1226337a
TT		 1834 /* Send unload command to MCP */
1835 rc = qed_mcp_unload_req(p_hwfn, p_ptt);
1836 if (rc) {
1837 DP_NOTICE(p_hwfn,
1838 "Failed sending a UNLOAD_REQ command. rc = %d.\n",
1839 rc);
1840 rc2 = -EINVAL;
1841 }
1842
1843 qed_slowpath_irq_sync(p_hwfn);
1844
1845 /* After this point no MFW attentions are expected, e.g. prevent
1846 * race between pf stop and dcbx pf update.
1847 */
fe56b9e6 1848 rc = qed_sp_pf_stop(p_hwfn);
1226337a 1849 if (rc) {
8c925c44 1850 DP_NOTICE(p_hwfn,
1226337a
TT		 1851 "Failed to close PF against FW [rc = %d]. Continue to stop HW to prevent illegal host access by the device.\n",
1852 rc);
1853 rc2 = -EINVAL;
1854 }
fe56b9e6
YM		 1855
1856 qed_wr(p_hwfn, p_ptt,
1857 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1858
1859 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1860 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1861 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
1862 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1863 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1864
8c925c44 1865 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
fe56b9e6
YM		 1866
1867 /* Disable Attention Generation */
1868 qed_int_igu_disable_int(p_hwfn, p_ptt);
1869
1870 qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
1871 qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
1872
1873 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
1874
1875 /* Need to wait 1ms to guarantee SBs are cleared */
1876 usleep_range(1000, 2000);
1226337a
TT		 1877
1878 /* Disable PF in HW blocks */
1879 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DB_ENABLE, 0);
1880 qed_wr(p_hwfn, p_ptt, QM_REG_PF_EN, 0);
1881
1882 qed_mcp_unload_done(p_hwfn, p_ptt);
1883 if (rc) {
1884 DP_NOTICE(p_hwfn,
1885 "Failed sending a UNLOAD_DONE command. rc = %d.\n",
1886 rc);
1887 rc2 = -EINVAL;
1888 }
fe56b9e6
YM		 1889 }
1890
1408cc1f 1891 if (IS_PF(cdev)) {
1226337a
TT		 1892 p_hwfn = QED_LEADING_HWFN(cdev);
1893 p_ptt = QED_LEADING_HWFN(cdev)->p_main_ptt;
1894
1408cc1f
YM		 1895 /* Disable DMAE in PXP - in CMT, this should only be done for
1896 * first hw-function, and only after all transactions have
1897 * stopped for all active hw-functions.
1898 */
1226337a
TT		 1899 rc = qed_change_pci_hwfn(p_hwfn, p_ptt, false);
1900 if (rc) {
1901 DP_NOTICE(p_hwfn,
1902 "qed_change_pci_hwfn failed. rc = %d.\n", rc);
1903 rc2 = -EINVAL;
1904 }
1408cc1f 1905 }
fe56b9e6 1906
1226337a 1907 return rc2;
fe56b9e6
YM		 1908}
1909
15582962 1910int qed_hw_stop_fastpath(struct qed_dev *cdev)
cee4d264 1911{
8c925c44 1912 int j;
cee4d264
MC		 1913
1914 for_each_hwfn(cdev, j) {
1915 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
15582962 1916 struct qed_ptt *p_ptt;
dacd88d6
YM		 1917
1918 if (IS_VF(cdev)) {
1919 qed_vf_pf_int_cleanup(p_hwfn);
1920 continue;
1921 }
15582962
RV		 1922 p_ptt = qed_ptt_acquire(p_hwfn);
1923 if (!p_ptt)
1924 return -EAGAIN;
cee4d264
MC		 1925
1926 DP_VERBOSE(p_hwfn,
1a635e48 1927 NETIF_MSG_IFDOWN, "Shutting down the fastpath\n");
cee4d264
MC		 1928
1929 qed_wr(p_hwfn, p_ptt,
1930 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1931
1932 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1933 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1934 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
1935 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1936 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1937
cee4d264
MC		 1938 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
1939
1940 /* Need to wait 1ms to guarantee SBs are cleared */
1941 usleep_range(1000, 2000);
15582962 1942 qed_ptt_release(p_hwfn, p_ptt);
cee4d264 1943 }
15582962
RV		 1944
1945 return 0;
cee4d264
MC		 1946}
1947
15582962 1948int qed_hw_start_fastpath(struct qed_hwfn *p_hwfn)
cee4d264 1949{
15582962
RV		 1950 struct qed_ptt *p_ptt;
1951
dacd88d6 1952 if (IS_VF(p_hwfn->cdev))
15582962
RV		 1953 return 0;
1954
1955 p_ptt = qed_ptt_acquire(p_hwfn);
1956 if (!p_ptt)
1957 return -EAGAIN;
dacd88d6 1958
cee4d264 1959 /* Re-open incoming traffic */
15582962
RV		 1960 qed_wr(p_hwfn, p_ptt, NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
1961 qed_ptt_release(p_hwfn, p_ptt);
1962
1963 return 0;
cee4d264
MC		 1964}
1965
fe56b9e6
YM		 1966/* Free hwfn memory and resources acquired in hw_hwfn_prepare */
1967static void qed_hw_hwfn_free(struct qed_hwfn *p_hwfn)
1968{
1969 qed_ptt_pool_free(p_hwfn);
1970 kfree(p_hwfn->hw_info.p_igu_info);
1971}
1972
1973/* Setup bar access */
12e09c69 1974static void qed_hw_hwfn_prepare(struct qed_hwfn *p_hwfn)
fe56b9e6 1975{
fe56b9e6 1976 /* clear indirect access */
9c79ddaa
MY		 1977 if (QED_IS_AH(p_hwfn->cdev)) {
1978 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1979 PGLUE_B_REG_PGL_ADDR_E8_F0_K2, 0);
1980 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1981 PGLUE_B_REG_PGL_ADDR_EC_F0_K2, 0);
1982 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1983 PGLUE_B_REG_PGL_ADDR_F0_F0_K2, 0);
1984 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1985 PGLUE_B_REG_PGL_ADDR_F4_F0_K2, 0);
1986 } else {
1987 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1988 PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0);
1989 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1990 PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0);
1991 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1992 PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0);
1993 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1994 PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0);
1995 }
fe56b9e6
YM		 1996
1997 /* Clean Previous errors if such exist */
1998 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1a635e48 1999 PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, 1 << p_hwfn->abs_pf_id);
fe56b9e6
YM		 2000
2001 /* enable internal target-read */
2002 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2003 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
fe56b9e6
YM		 2004}
2005
2006static void get_function_id(struct qed_hwfn *p_hwfn)
2007{
2008 /* ME Register */
1a635e48
YM		 2009 p_hwfn->hw_info.opaque_fid = (u16) REG_RD(p_hwfn,
2010 PXP_PF_ME_OPAQUE_ADDR);
fe56b9e6
YM		 2011
2012 p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
2013
2014 p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
2015 p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2016 PXP_CONCRETE_FID_PFID);
2017 p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2018 PXP_CONCRETE_FID_PORT);
525ef5c0
YM		 2019
2020 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE,
2021 "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
2022 p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
fe56b9e6
YM		 2023}
2024
25c089d7
YM		 2025static void qed_hw_set_feat(struct qed_hwfn *p_hwfn)
2026{
2027 u32 *feat_num = p_hwfn->hw_info.feat_num;
5a1f965a 2028 struct qed_sb_cnt_info sb_cnt_info;
810bb1f0 2029 u32 non_l2_sbs = 0;
25c089d7 2030
0189efb8
YM		 2031 if (IS_ENABLED(CONFIG_QED_RDMA) &&
2032 p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE) {
2033 /* Roce CNQ each requires: 1 status block + 1 CNQ. We divide
2034 * the status blocks equally between L2 / RoCE but with
2035 * consideration as to how many l2 queues / cnqs we have.
2036 */
51ff1725 2037 feat_num[QED_RDMA_CNQ] =
810bb1f0 2038 min_t(u32, RESC_NUM(p_hwfn, QED_SB) / 2,
51ff1725 2039 RESC_NUM(p_hwfn, QED_RDMA_CNQ_RAM));
810bb1f0
MY		 2040
2041 non_l2_sbs = feat_num[QED_RDMA_CNQ];
51ff1725 2042 }
0189efb8 2043
dec26533
MY		 2044 if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE ||
2045 p_hwfn->hw_info.personality == QED_PCI_ETH) {
2046 /* Start by allocating VF queues, then PF's */
2047 memset(&sb_cnt_info, 0, sizeof(sb_cnt_info));
2048 qed_int_get_num_sbs(p_hwfn, &sb_cnt_info);
2049 feat_num[QED_VF_L2_QUE] = min_t(u32,
2050 RESC_NUM(p_hwfn, QED_L2_QUEUE),
2051 sb_cnt_info.sb_iov_cnt);
2052 feat_num[QED_PF_L2_QUE] = min_t(u32,
2053 RESC_NUM(p_hwfn, QED_SB) -
2054 non_l2_sbs,
2055 RESC_NUM(p_hwfn,
2056 QED_L2_QUEUE) -
2057 FEAT_NUM(p_hwfn,
2058 QED_VF_L2_QUE));
2059 }
5a1f965a 2060
08737a3f
MY		 2061 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI)
2062 feat_num[QED_ISCSI_CQ] = min_t(u32, RESC_NUM(p_hwfn, QED_SB),
2063 RESC_NUM(p_hwfn,
2064 QED_CMDQS_CQS));
5a1f965a
MY		 2065 DP_VERBOSE(p_hwfn,
2066 NETIF_MSG_PROBE,
08737a3f 2067 "#PF_L2_QUEUES=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d ISCSI_CQ=%d #SBS=%d\n",
5a1f965a
MY		 2068 (int)FEAT_NUM(p_hwfn, QED_PF_L2_QUE),
2069 (int)FEAT_NUM(p_hwfn, QED_VF_L2_QUE),
2070 (int)FEAT_NUM(p_hwfn, QED_RDMA_CNQ),
08737a3f 2071 (int)FEAT_NUM(p_hwfn, QED_ISCSI_CQ),
810bb1f0 2072 RESC_NUM(p_hwfn, QED_SB));
25c089d7
YM		 2073}
2074
9c8517c4 2075const char *qed_hw_get_resc_name(enum qed_resources res_id)
2edbff8d 2076{
2edbff8d 2077 switch (res_id) {
2edbff8d 2078 case QED_L2_QUEUE:
9c8517c4 2079 return "L2_QUEUE";
2edbff8d 2080 case QED_VPORT:
9c8517c4 2081 return "VPORT";
2edbff8d 2082 case QED_RSS_ENG:
9c8517c4 2083 return "RSS_ENG";
2edbff8d 2084 case QED_PQ:
9c8517c4 2085 return "PQ";
2edbff8d 2086 case QED_RL:
9c8517c4 2087 return "RL";
2edbff8d 2088 case QED_MAC:
9c8517c4 2089 return "MAC";
2edbff8d 2090 case QED_VLAN:
9c8517c4
TT		 2091 return "VLAN";
2092 case QED_RDMA_CNQ_RAM:
2093 return "RDMA_CNQ_RAM";
2edbff8d 2094 case QED_ILT:
9c8517c4 2095 return "ILT";
2edbff8d 2096 case QED_LL2_QUEUE:
9c8517c4 2097 return "LL2_QUEUE";
2edbff8d 2098 case QED_CMDQS_CQS:
9c8517c4 2099 return "CMDQS_CQS";
2edbff8d 2100 case QED_RDMA_STATS_QUEUE:
9c8517c4
TT		 2101 return "RDMA_STATS_QUEUE";
2102 case QED_BDQ:
2103 return "BDQ";
2104 case QED_SB:
2105 return "SB";
2edbff8d 2106 default:
9c8517c4 2107 return "UNKNOWN_RESOURCE";
2edbff8d 2108 }
9c8517c4
TT		 2109}
2110
2111static int
2112__qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn,
2113 struct qed_ptt *p_ptt,
2114 enum qed_resources res_id,
2115 u32 resc_max_val, u32 *p_mcp_resp)
2116{
2117 int rc;
2edbff8d 2118
9c8517c4
TT		 2119 rc = qed_mcp_set_resc_max_val(p_hwfn, p_ptt, res_id,
2120 resc_max_val, p_mcp_resp);
2121 if (rc) {
2122 DP_NOTICE(p_hwfn,
2123 "MFW response failure for a max value setting of resource %d [%s]\n",
2124 res_id, qed_hw_get_resc_name(res_id));
2125 return rc;
2126 }
2127
2128 if (*p_mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK)
2129 DP_INFO(p_hwfn,
2130 "Failed to set the max value of resource %d [%s]. mcp_resp = 0x%08x.\n",
2131 res_id, qed_hw_get_resc_name(res_id), *p_mcp_resp);
2132
2133 return 0;
2134}
2135
2136static int
2137qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2138{
2139 bool b_ah = QED_IS_AH(p_hwfn->cdev);
2140 u32 resc_max_val, mcp_resp;
2141 u8 res_id;
2142 int rc;
2143
2144 for (res_id = 0; res_id < QED_MAX_RESC; res_id++) {
2145 switch (res_id) {
2146 case QED_LL2_QUEUE:
2147 resc_max_val = MAX_NUM_LL2_RX_QUEUES;
2148 break;
2149 case QED_RDMA_CNQ_RAM:
2150 /* No need for a case for QED_CMDQS_CQS since
2151 * CNQ/CMDQS are the same resource.
2152 */
2153 resc_max_val = NUM_OF_CMDQS_CQS;
2154 break;
2155 case QED_RDMA_STATS_QUEUE:
2156 resc_max_val = b_ah ? RDMA_NUM_STATISTIC_COUNTERS_K2
2157 : RDMA_NUM_STATISTIC_COUNTERS_BB;
2158 break;
2159 case QED_BDQ:
2160 resc_max_val = BDQ_NUM_RESOURCES;
2161 break;
2162 default:
2163 continue;
2164 }
2165
2166 rc = __qed_hw_set_soft_resc_size(p_hwfn, p_ptt, res_id,
2167 resc_max_val, &mcp_resp);
2168 if (rc)
2169 return rc;
2170
2171 /* There's no point to continue to the next resource if the
2172 * command is not supported by the MFW.
2173 * We do continue if the command is supported but the resource
2174 * is unknown to the MFW. Such a resource will be later
2175 * configured with the default allocation values.
2176 */
2177 if (mcp_resp == FW_MSG_CODE_UNSUPPORTED)
2178 return -EINVAL;
2179 }
2180
2181 return 0;
2edbff8d
TT		 2182}
2183
9c8517c4
TT		 2184static
2185int qed_hw_get_dflt_resc(struct qed_hwfn *p_hwfn,
2186 enum qed_resources res_id,
2187 u32 *p_resc_num, u32 *p_resc_start)
fe56b9e6 2188{
1408cc1f 2189 u8 num_funcs = p_hwfn->num_funcs_on_engine;
9c79ddaa 2190 bool b_ah = QED_IS_AH(p_hwfn->cdev);
4ac801b7 2191 struct qed_sb_cnt_info sb_cnt_info;
fe56b9e6 2192
2edbff8d 2193 switch (res_id) {
2edbff8d 2194 case QED_L2_QUEUE:
9c8517c4
TT		 2195 *p_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
2196 MAX_NUM_L2_QUEUES_BB) / num_funcs;
2edbff8d
TT		 2197 break;
2198 case QED_VPORT:
9c8517c4
TT		 2199 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
2200 MAX_NUM_VPORTS_BB) / num_funcs;
2edbff8d
TT		 2201 break;
2202 case QED_RSS_ENG:
9c8517c4
TT		 2203 *p_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
2204 ETH_RSS_ENGINE_NUM_BB) / num_funcs;
2edbff8d
TT		 2205 break;
2206 case QED_PQ:
9c8517c4
TT		 2207 *p_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 :
2208 MAX_QM_TX_QUEUES_BB) / num_funcs;
2209 *p_resc_num &= ~0x7; /* The granularity of the PQs is 8 */
2edbff8d
TT		 2210 break;
2211 case QED_RL:
9c8517c4 2212 *p_resc_num = MAX_QM_GLOBAL_RLS / num_funcs;
2edbff8d
TT		 2213 break;
2214 case QED_MAC:
2215 case QED_VLAN:
2216 /* Each VFC resource can accommodate both a MAC and a VLAN */
9c8517c4 2217 *p_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
2edbff8d
TT		 2218 break;
2219 case QED_ILT:
9c8517c4
TT		 2220 *p_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
2221 PXP_NUM_ILT_RECORDS_BB) / num_funcs;
2edbff8d
TT		 2222 break;
2223 case QED_LL2_QUEUE:
9c8517c4 2224 *p_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
2edbff8d
TT		 2225 break;
2226 case QED_RDMA_CNQ_RAM:
2227 case QED_CMDQS_CQS:
2228 /* CNQ/CMDQS are the same resource */
9c8517c4 2229 *p_resc_num = NUM_OF_CMDQS_CQS / num_funcs;
2edbff8d
TT		 2230 break;
2231 case QED_RDMA_STATS_QUEUE:
9c8517c4
TT		 2232 *p_resc_num = (b_ah ? RDMA_NUM_STATISTIC_COUNTERS_K2 :
2233 RDMA_NUM_STATISTIC_COUNTERS_BB) / num_funcs;
2edbff8d 2234 break;
9c8517c4
TT		 2235 case QED_BDQ:
2236 if (p_hwfn->hw_info.personality != QED_PCI_ISCSI &&
2237 p_hwfn->hw_info.personality != QED_PCI_FCOE)
2238 *p_resc_num = 0;
2239 else
2240 *p_resc_num = 1;
2241 break;
2242 case QED_SB:
2243 memset(&sb_cnt_info, 0, sizeof(sb_cnt_info));
2244 qed_int_get_num_sbs(p_hwfn, &sb_cnt_info);
2245 *p_resc_num = sb_cnt_info.sb_cnt;
2edbff8d 2246 break;
9c8517c4
TT		 2247 default:
2248 return -EINVAL;
2edbff8d 2249 }
08feecd7 2250
2edbff8d 2251 switch (res_id) {
9c8517c4
TT		 2252 case QED_BDQ:
2253 if (!*p_resc_num)
2254 *p_resc_start = 0;
2255 else if (p_hwfn->cdev->num_ports_in_engines == 4)
2256 *p_resc_start = p_hwfn->port_id;
2257 else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI)
2258 *p_resc_start = p_hwfn->port_id;
2259 else if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
2260 *p_resc_start = p_hwfn->port_id + 2;
2261 break;
2edbff8d 2262 default:
9c8517c4
TT		 2263 *p_resc_start = *p_resc_num * p_hwfn->enabled_func_idx;
2264 break;
2edbff8d 2265 }
9c8517c4
TT		 2266
2267 return 0;
2edbff8d
TT		 2268}
2269
9c8517c4
TT		 2270static int __qed_hw_set_resc_info(struct qed_hwfn *p_hwfn,
2271 enum qed_resources res_id)
2edbff8d 2272{
9c8517c4
TT		 2273 u32 dflt_resc_num = 0, dflt_resc_start = 0;
2274 u32 mcp_resp, *p_resc_num, *p_resc_start;
2edbff8d
TT		 2275 int rc;
2276
2277 p_resc_num = &RESC_NUM(p_hwfn, res_id);
2278 p_resc_start = &RESC_START(p_hwfn, res_id);
2279
9c8517c4
TT		 2280 rc = qed_hw_get_dflt_resc(p_hwfn, res_id, &dflt_resc_num,
2281 &dflt_resc_start);
2282 if (rc) {
2edbff8d
TT		 2283 DP_ERR(p_hwfn,
2284 "Failed to get default amount for resource %d [%s]\n",
2285 res_id, qed_hw_get_resc_name(res_id));
9c8517c4 2286 return rc;
2edbff8d
TT		 2287 }
2288
9c8517c4
TT		 2289 rc = qed_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, res_id,
2290 &mcp_resp, p_resc_num, p_resc_start);
2edbff8d
TT		 2291 if (rc) {
2292 DP_NOTICE(p_hwfn,
2293 "MFW response failure for an allocation request for resource %d [%s]\n",
2294 res_id, qed_hw_get_resc_name(res_id));
2295 return rc;
2296 }
2297
2298 /* Default driver values are applied in the following cases:
2299 * - The resource allocation MB command is not supported by the MFW
2300 * - There is an internal error in the MFW while processing the request
2301 * - The resource ID is unknown to the MFW
2302 */
9c8517c4
TT		 2303 if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) {
2304 DP_INFO(p_hwfn,
2305 "Failed to receive allocation info for resource %d [%s]. mcp_resp = 0x%x. Applying default values [%d,%d].\n",
2306 res_id,
2307 qed_hw_get_resc_name(res_id),
2308 mcp_resp, dflt_resc_num, dflt_resc_start);
2edbff8d
TT		 2309 *p_resc_num = dflt_resc_num;
2310 *p_resc_start = dflt_resc_start;
2311 goto out;
2312 }
2313
2314 /* Special handling for status blocks; Would be revised in future */
2315 if (res_id == QED_SB) {
9c8517c4
TT		 2316 *p_resc_num -= 1;
2317 *p_resc_start -= p_hwfn->enabled_func_idx;
2edbff8d 2318 }
2edbff8d
TT		 2319out:
2320 /* PQs have to divide by 8 [that's the HW granularity].
2321 * Reduce number so it would fit.
2322 */
2323 if ((res_id == QED_PQ) && ((*p_resc_num % 8) || (*p_resc_start % 8))) {
2324 DP_INFO(p_hwfn,
2325 "PQs need to align by 8; Number %08x --> %08x, Start %08x --> %08x\n",
2326 *p_resc_num,
2327 (*p_resc_num) & ~0x7,
2328 *p_resc_start, (*p_resc_start) & ~0x7);
2329 *p_resc_num &= ~0x7;
2330 *p_resc_start &= ~0x7;
2331 }
4ac801b7 2332
2edbff8d
TT		 2333 return 0;
2334}
2335
9c8517c4 2336static int qed_hw_set_resc_info(struct qed_hwfn *p_hwfn)
2edbff8d 2337{
2edbff8d 2338 int rc;
9c8517c4 2339 u8 res_id;
2edbff8d
TT		 2340
2341 for (res_id = 0; res_id < QED_MAX_RESC; res_id++) {
9c8517c4 2342 rc = __qed_hw_set_resc_info(p_hwfn, res_id);
2edbff8d
TT		 2343 if (rc)
2344 return rc;
2345 }
dbb799c3 2346
9c8517c4
TT		 2347 return 0;
2348}
2349
2350#define QED_RESC_ALLOC_LOCK_RETRY_CNT 10
2351#define QED_RESC_ALLOC_LOCK_RETRY_INTVL_US 10000 /* 10 msec */
2352
2353static int qed_hw_get_resc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2354{
2355 struct qed_resc_unlock_params resc_unlock_params;
2356 struct qed_resc_lock_params resc_lock_params;
2357 bool b_ah = QED_IS_AH(p_hwfn->cdev);
2358 u8 res_id;
2359 int rc;
2360
2361 /* Setting the max values of the soft resources and the following
2362 * resources allocation queries should be atomic. Since several PFs can
2363 * run in parallel - a resource lock is needed.
2364 * If either the resource lock or resource set value commands are not
2365 * supported - skip the the max values setting, release the lock if
2366 * needed, and proceed to the queries. Other failures, including a
2367 * failure to acquire the lock, will cause this function to fail.
2368 */
2369 memset(&resc_lock_params, 0, sizeof(resc_lock_params));
2370 resc_lock_params.resource = QED_RESC_LOCK_RESC_ALLOC;
2371 resc_lock_params.retry_num = QED_RESC_ALLOC_LOCK_RETRY_CNT;
2372 resc_lock_params.retry_interval = QED_RESC_ALLOC_LOCK_RETRY_INTVL_US;
2373 resc_lock_params.sleep_b4_retry = true;
2374 memset(&resc_unlock_params, 0, sizeof(resc_unlock_params));
2375 resc_unlock_params.resource = QED_RESC_LOCK_RESC_ALLOC;
2376
2377 rc = qed_mcp_resc_lock(p_hwfn, p_ptt, &resc_lock_params);
2378 if (rc && rc != -EINVAL) {
2379 return rc;
2380 } else if (rc == -EINVAL) {
2381 DP_INFO(p_hwfn,
2382 "Skip the max values setting of the soft resources since the resource lock is not supported by the MFW\n");
2383 } else if (!rc && !resc_lock_params.b_granted) {
2384 DP_NOTICE(p_hwfn,
2385 "Failed to acquire the resource lock for the resource allocation commands\n");
2386 return -EBUSY;
2387 } else {
2388 rc = qed_hw_set_soft_resc_size(p_hwfn, p_ptt);
2389 if (rc && rc != -EINVAL) {
2390 DP_NOTICE(p_hwfn,
2391 "Failed to set the max values of the soft resources\n");
2392 goto unlock_and_exit;
2393 } else if (rc == -EINVAL) {
2394 DP_INFO(p_hwfn,
2395 "Skip the max values setting of the soft resources since it is not supported by the MFW\n");
2396 rc = qed_mcp_resc_unlock(p_hwfn, p_ptt,
2397 &resc_unlock_params);
2398 if (rc)
2399 DP_INFO(p_hwfn,
2400 "Failed to release the resource lock for the resource allocation commands\n");
2401 }
2402 }
2403
2404 rc = qed_hw_set_resc_info(p_hwfn);
2405 if (rc)
2406 goto unlock_and_exit;
2407
2408 if (resc_lock_params.b_granted && !resc_unlock_params.b_released) {
2409 rc = qed_mcp_resc_unlock(p_hwfn, p_ptt, &resc_unlock_params);
2410 if (rc)
2411 DP_INFO(p_hwfn,
2412 "Failed to release the resource lock for the resource allocation commands\n");
2413 }
2414
dbb799c3 2415 /* Sanity for ILT */
9c79ddaa
MY		 2416 if ((b_ah && (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
2417 (!b_ah && (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
dbb799c3
YM		 2418 DP_NOTICE(p_hwfn, "Can't assign ILT pages [%08x,...,%08x]\n",
2419 RESC_START(p_hwfn, QED_ILT),
2420 RESC_END(p_hwfn, QED_ILT) - 1);
2421 return -EINVAL;
2422 }
fe56b9e6 2423
25c089d7
YM		 2424 qed_hw_set_feat(p_hwfn);
2425
2edbff8d
TT		 2426 for (res_id = 0; res_id < QED_MAX_RESC; res_id++)
2427 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE, "%s = %d start = %d\n",
2428 qed_hw_get_resc_name(res_id),
2429 RESC_NUM(p_hwfn, res_id),
2430 RESC_START(p_hwfn, res_id));
dbb799c3
YM		 2431
2432 return 0;
9c8517c4
TT		 2433
2434unlock_and_exit:
2435 if (resc_lock_params.b_granted && !resc_unlock_params.b_released)
2436 qed_mcp_resc_unlock(p_hwfn, p_ptt, &resc_unlock_params);
2437 return rc;
fe56b9e6
YM		 2438}
2439
1a635e48 2440static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
fe56b9e6 2441{
fc48b7a6 2442 u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
1e128c81 2443 u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg;
cc875c2e 2444 struct qed_mcp_link_params *link;
fe56b9e6
YM		 2445
2446 /* Read global nvm_cfg address */
2447 nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
2448
2449 /* Verify MCP has initialized it */
2450 if (!nvm_cfg_addr) {
2451 DP_NOTICE(p_hwfn, "Shared memory not initialized\n");
2452 return -EINVAL;
2453 }
2454
2455 /* Read nvm_cfg1 (Notice this is just offset, and not offsize (TBD) */
2456 nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
2457
cc875c2e
YM		 2458 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2459 offsetof(struct nvm_cfg1, glob) +
2460 offsetof(struct nvm_cfg1_glob, core_cfg);
2461
2462 core_cfg = qed_rd(p_hwfn, p_ptt, addr);
2463
2464 switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
2465 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
351a4ded 2466 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
cc875c2e
YM		 2467 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X40G;
2468 break;
351a4ded 2469 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
cc875c2e
YM		 2470 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X50G;
2471 break;
351a4ded 2472 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
cc875c2e
YM		 2473 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X100G;
2474 break;
351a4ded 2475 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
cc875c2e
YM		 2476 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_F;
2477 break;
351a4ded 2478 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
cc875c2e
YM		 2479 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_E;
2480 break;
351a4ded 2481 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
cc875c2e
YM		 2482 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X20G;
2483 break;
351a4ded 2484 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
cc875c2e
YM		 2485 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X40G;
2486 break;
351a4ded 2487 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
cc875c2e
YM		 2488 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X25G;
2489 break;
9c79ddaa
MY		 2490 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
2491 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X10G;
2492 break;
351a4ded 2493 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
cc875c2e
YM		 2494 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X25G;
2495 break;
9c79ddaa
MY		 2496 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
2497 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X25G;
2498 break;
cc875c2e 2499 default:
1a635e48 2500 DP_NOTICE(p_hwfn, "Unknown port mode in 0x%08x\n", core_cfg);
cc875c2e
YM		 2501 break;
2502 }
2503
cc875c2e
YM		 2504 /* Read default link configuration */
2505 link = &p_hwfn->mcp_info->link_input;
2506 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2507 offsetof(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
2508 link_temp = qed_rd(p_hwfn, p_ptt,
2509 port_cfg_addr +
2510 offsetof(struct nvm_cfg1_port, speed_cap_mask));
83aeb933
YM		 2511 link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
2512 link->speed.advertised_speeds = link_temp;
cc875c2e 2513
83aeb933
YM		 2514 link_temp = link->speed.advertised_speeds;
2515 p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp;
cc875c2e
YM		 2516
2517 link_temp = qed_rd(p_hwfn, p_ptt,
2518 port_cfg_addr +
2519 offsetof(struct nvm_cfg1_port, link_settings));
2520 switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
2521 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
2522 case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
2523 link->speed.autoneg = true;
2524 break;
2525 case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
2526 link->speed.forced_speed = 1000;
2527 break;
2528 case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
2529 link->speed.forced_speed = 10000;
2530 break;
2531 case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
2532 link->speed.forced_speed = 25000;
2533 break;
2534 case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
2535 link->speed.forced_speed = 40000;
2536 break;
2537 case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
2538 link->speed.forced_speed = 50000;
2539 break;
351a4ded 2540 case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
cc875c2e
YM		 2541 link->speed.forced_speed = 100000;
2542 break;
2543 default:
1a635e48 2544 DP_NOTICE(p_hwfn, "Unknown Speed in 0x%08x\n", link_temp);
cc875c2e
YM		 2545 }
2546
2547 link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
2548 link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
2549 link->pause.autoneg = !!(link_temp &
2550 NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
2551 link->pause.forced_rx = !!(link_temp &
2552 NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
2553 link->pause.forced_tx = !!(link_temp &
2554 NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
2555 link->loopback_mode = 0;
2556
2557 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
2558 "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n",
2559 link->speed.forced_speed, link->speed.advertised_speeds,
2560 link->speed.autoneg, link->pause.autoneg);
2561
fe56b9e6
YM		 2562 /* Read Multi-function information from shmem */
2563 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2564 offsetof(struct nvm_cfg1, glob) +
2565 offsetof(struct nvm_cfg1_glob, generic_cont0);
2566
2567 generic_cont0 = qed_rd(p_hwfn, p_ptt, addr);
2568
2569 mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
2570 NVM_CFG1_GLOB_MF_MODE_OFFSET;
2571
2572 switch (mf_mode) {
2573 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
fc48b7a6 2574 p_hwfn->cdev->mf_mode = QED_MF_OVLAN;
fe56b9e6
YM		 2575 break;
2576 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
fc48b7a6 2577 p_hwfn->cdev->mf_mode = QED_MF_NPAR;
fe56b9e6 2578 break;
fc48b7a6
YM		 2579 case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
2580 p_hwfn->cdev->mf_mode = QED_MF_DEFAULT;
fe56b9e6
YM		 2581 break;
2582 }
2583 DP_INFO(p_hwfn, "Multi function mode is %08x\n",
2584 p_hwfn->cdev->mf_mode);
2585
fc48b7a6
YM		 2586 /* Read Multi-function information from shmem */
2587 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2588 offsetof(struct nvm_cfg1, glob) +
2589 offsetof(struct nvm_cfg1_glob, device_capabilities);
2590
2591 device_capabilities = qed_rd(p_hwfn, p_ptt, addr);
2592 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
2593 __set_bit(QED_DEV_CAP_ETH,
2594 &p_hwfn->hw_info.device_capabilities);
1e128c81
AE		 2595 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
2596 __set_bit(QED_DEV_CAP_FCOE,
2597 &p_hwfn->hw_info.device_capabilities);
c5ac9319
YM		 2598 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
2599 __set_bit(QED_DEV_CAP_ISCSI,
2600 &p_hwfn->hw_info.device_capabilities);
2601 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
2602 __set_bit(QED_DEV_CAP_ROCE,
2603 &p_hwfn->hw_info.device_capabilities);
fc48b7a6 2604
fe56b9e6
YM		 2605 return qed_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
2606}
2607
1408cc1f
YM		 2608static void qed_get_num_funcs(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2609{
dbb799c3
YM		 2610 u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
2611 u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
9c79ddaa 2612 struct qed_dev *cdev = p_hwfn->cdev;
1408cc1f 2613
9c79ddaa 2614 num_funcs = QED_IS_AH(cdev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
1408cc1f
YM		 2615
2616 /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
2617 * in the other bits are selected.
2618 * Bits 1-15 are for functions 1-15, respectively, and their value is
2619 * '0' only for enabled functions (function 0 always exists and
2620 * enabled).
2621 * In case of CMT, only the "even" functions are enabled, and thus the
2622 * number of functions for both hwfns is learnt from the same bits.
2623 */
2624 reg_function_hide = qed_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE);
2625
2626 if (reg_function_hide & 0x1) {
9c79ddaa
MY		 2627 if (QED_IS_BB(cdev)) {
2628 if (QED_PATH_ID(p_hwfn) && cdev->num_hwfns == 1) {
2629 num_funcs = 0;
2630 eng_mask = 0xaaaa;
2631 } else {
2632 num_funcs = 1;
2633 eng_mask = 0x5554;
2634 }
1408cc1f
YM		 2635 } else {
2636 num_funcs = 1;
9c79ddaa 2637 eng_mask = 0xfffe;
1408cc1f
YM		 2638 }
2639
2640 /* Get the number of the enabled functions on the engine */
2641 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
2642 while (tmp) {
2643 if (tmp & 0x1)
2644 num_funcs++;
2645 tmp >>= 0x1;
2646 }
dbb799c3
YM		 2647
2648 /* Get the PF index within the enabled functions */
2649 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
2650 tmp = reg_function_hide & eng_mask & low_pfs_mask;
2651 while (tmp) {
2652 if (tmp & 0x1)
2653 enabled_func_idx--;
2654 tmp >>= 0x1;
2655 }
1408cc1f
YM		 2656 }
2657
2658 p_hwfn->num_funcs_on_engine = num_funcs;
dbb799c3 2659 p_hwfn->enabled_func_idx = enabled_func_idx;
1408cc1f
YM		 2660
2661 DP_VERBOSE(p_hwfn,
2662 NETIF_MSG_PROBE,
525ef5c0 2663 "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
1408cc1f
YM		 2664 p_hwfn->rel_pf_id,
2665 p_hwfn->abs_pf_id,
525ef5c0 2666 p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
1408cc1f
YM		 2667}
2668
9c79ddaa
MY		 2669static void qed_hw_info_port_num_bb(struct qed_hwfn *p_hwfn,
2670 struct qed_ptt *p_ptt)
fe56b9e6
YM		 2671{
2672 u32 port_mode;
fe56b9e6 2673
9c79ddaa 2674 port_mode = qed_rd(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB_B0);
fe56b9e6
YM		 2675
2676 if (port_mode < 3) {
2677 p_hwfn->cdev->num_ports_in_engines = 1;
2678 } else if (port_mode <= 5) {
2679 p_hwfn->cdev->num_ports_in_engines = 2;
2680 } else {
2681 DP_NOTICE(p_hwfn, "PORT MODE: %d not supported\n",
2682 p_hwfn->cdev->num_ports_in_engines);
2683
2684 /* Default num_ports_in_engines to something */
2685 p_hwfn->cdev->num_ports_in_engines = 1;
2686 }
9c79ddaa
MY		 2687}
2688
2689static void qed_hw_info_port_num_ah(struct qed_hwfn *p_hwfn,
2690 struct qed_ptt *p_ptt)
2691{
2692 u32 port;
2693 int i;
2694
2695 p_hwfn->cdev->num_ports_in_engines = 0;
2696
2697 for (i = 0; i < MAX_NUM_PORTS_K2; i++) {
2698 port = qed_rd(p_hwfn, p_ptt,
2699 CNIG_REG_NIG_PORT0_CONF_K2 + (i * 4));
2700 if (port & 1)
2701 p_hwfn->cdev->num_ports_in_engines++;
2702 }
2703
2704 if (!p_hwfn->cdev->num_ports_in_engines) {
2705 DP_NOTICE(p_hwfn, "All NIG ports are inactive\n");
2706
2707 /* Default num_ports_in_engine to something */
2708 p_hwfn->cdev->num_ports_in_engines = 1;
2709 }
2710}
2711
2712static void qed_hw_info_port_num(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2713{
2714 if (QED_IS_BB(p_hwfn->cdev))
2715 qed_hw_info_port_num_bb(p_hwfn, p_ptt);
2716 else
2717 qed_hw_info_port_num_ah(p_hwfn, p_ptt);
2718}
2719
2720static int
2721qed_get_hw_info(struct qed_hwfn *p_hwfn,
2722 struct qed_ptt *p_ptt,
2723 enum qed_pci_personality personality)
2724{
2725 int rc;
2726
2727 /* Since all information is common, only first hwfns should do this */
2728 if (IS_LEAD_HWFN(p_hwfn)) {
2729 rc = qed_iov_hw_info(p_hwfn);
2730 if (rc)
2731 return rc;
2732 }
2733
2734 qed_hw_info_port_num(p_hwfn, p_ptt);
fe56b9e6
YM		 2735
2736 qed_hw_get_nvm_info(p_hwfn, p_ptt);
2737
2738 rc = qed_int_igu_read_cam(p_hwfn, p_ptt);
2739 if (rc)
2740 return rc;
2741
2742 if (qed_mcp_is_init(p_hwfn))
2743 ether_addr_copy(p_hwfn->hw_info.hw_mac_addr,
2744 p_hwfn->mcp_info->func_info.mac);
2745 else
2746 eth_random_addr(p_hwfn->hw_info.hw_mac_addr);
2747
2748 if (qed_mcp_is_init(p_hwfn)) {
2749 if (p_hwfn->mcp_info->func_info.ovlan != QED_MCP_VLAN_UNSET)
2750 p_hwfn->hw_info.ovlan =
2751 p_hwfn->mcp_info->func_info.ovlan;
2752
2753 qed_mcp_cmd_port_init(p_hwfn, p_ptt);
2754 }
2755
2756 if (qed_mcp_is_init(p_hwfn)) {
2757 enum qed_pci_personality protocol;
2758
2759 protocol = p_hwfn->mcp_info->func_info.protocol;
2760 p_hwfn->hw_info.personality = protocol;
2761 }
2762
b5a9ee7c
AE		 2763 p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
2764 p_hwfn->hw_info.num_active_tc = 1;
2765
1408cc1f
YM		 2766 qed_get_num_funcs(p_hwfn, p_ptt);
2767
0fefbfba
SK		 2768 if (qed_mcp_is_init(p_hwfn))
2769 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu;
2770
9c8517c4 2771 return qed_hw_get_resc(p_hwfn, p_ptt);
fe56b9e6
YM		 2772}
2773
15582962 2774static int qed_get_dev_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
fe56b9e6 2775{
15582962 2776 struct qed_dev *cdev = p_hwfn->cdev;
9c79ddaa 2777 u16 device_id_mask;
fe56b9e6
YM		 2778 u32 tmp;
2779
fc48b7a6 2780 /* Read Vendor Id / Device Id */
1a635e48
YM		 2781 pci_read_config_word(cdev->pdev, PCI_VENDOR_ID, &cdev->vendor_id);
2782 pci_read_config_word(cdev->pdev, PCI_DEVICE_ID, &cdev->device_id);
2783
9c79ddaa
MY		 2784 /* Determine type */
2785 device_id_mask = cdev->device_id & QED_DEV_ID_MASK;
2786 switch (device_id_mask) {
2787 case QED_DEV_ID_MASK_BB:
2788 cdev->type = QED_DEV_TYPE_BB;
2789 break;
2790 case QED_DEV_ID_MASK_AH:
2791 cdev->type = QED_DEV_TYPE_AH;
2792 break;
2793 default:
2794 DP_NOTICE(p_hwfn, "Unknown device id 0x%x\n", cdev->device_id);
2795 return -EBUSY;
2796 }
2797
15582962
RV		 2798 cdev->chip_num = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_NUM);
2799 cdev->chip_rev = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_REV);
2800
fe56b9e6
YM		 2801 MASK_FIELD(CHIP_REV, cdev->chip_rev);
2802
2803 /* Learn number of HW-functions */
15582962 2804 tmp = qed_rd(p_hwfn, p_ptt, MISCS_REG_CMT_ENABLED_FOR_PAIR);
fe56b9e6 2805
fc48b7a6 2806 if (tmp & (1 << p_hwfn->rel_pf_id)) {
fe56b9e6
YM		 2807 DP_NOTICE(cdev->hwfns, "device in CMT mode\n");
2808 cdev->num_hwfns = 2;
2809 } else {
2810 cdev->num_hwfns = 1;
2811 }
2812
15582962 2813 cdev->chip_bond_id = qed_rd(p_hwfn, p_ptt,
fe56b9e6
YM		 2814 MISCS_REG_CHIP_TEST_REG) >> 4;
2815 MASK_FIELD(CHIP_BOND_ID, cdev->chip_bond_id);
15582962 2816 cdev->chip_metal = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_METAL);
fe56b9e6
YM		 2817 MASK_FIELD(CHIP_METAL, cdev->chip_metal);
2818
2819 DP_INFO(cdev->hwfns,
9c79ddaa
MY		 2820 "Chip details - %s %c%d, Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
2821 QED_IS_BB(cdev) ? "BB" : "AH",
2822 'A' + cdev->chip_rev,
2823 (int)cdev->chip_metal,
fe56b9e6
YM		 2824 cdev->chip_num, cdev->chip_rev,
2825 cdev->chip_bond_id, cdev->chip_metal);
12e09c69
YM		 2826
2827 if (QED_IS_BB(cdev) && CHIP_REV_IS_A0(cdev)) {
2828 DP_NOTICE(cdev->hwfns,
2829 "The chip type/rev (BB A0) is not supported!\n");
2830 return -EINVAL;
2831 }
2832
2833 return 0;
fe56b9e6
YM		 2834}
2835
2836static int qed_hw_prepare_single(struct qed_hwfn *p_hwfn,
2837 void __iomem *p_regview,
2838 void __iomem *p_doorbells,
2839 enum qed_pci_personality personality)
2840{
2841 int rc = 0;
2842
2843 /* Split PCI bars evenly between hwfns */
2844 p_hwfn->regview = p_regview;
2845 p_hwfn->doorbells = p_doorbells;
2846
1408cc1f
YM		 2847 if (IS_VF(p_hwfn->cdev))
2848 return qed_vf_hw_prepare(p_hwfn);
2849
fe56b9e6
YM		 2850 /* Validate that chip access is feasible */
2851 if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
2852 DP_ERR(p_hwfn,
2853 "Reading the ME register returns all Fs; Preventing further chip access\n");
2854 return -EINVAL;
2855 }
2856
2857 get_function_id(p_hwfn);
2858
12e09c69
YM		 2859 /* Allocate PTT pool */
2860 rc = qed_ptt_pool_alloc(p_hwfn);
2591c280 2861 if (rc)
fe56b9e6 2862 goto err0;
fe56b9e6 2863
12e09c69
YM		 2864 /* Allocate the main PTT */
2865 p_hwfn->p_main_ptt = qed_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
2866
fe56b9e6 2867 /* First hwfn learns basic information, e.g., number of hwfns */
12e09c69 2868 if (!p_hwfn->my_id) {
15582962 2869 rc = qed_get_dev_info(p_hwfn, p_hwfn->p_main_ptt);
1a635e48 2870 if (rc)
12e09c69
YM		 2871 goto err1;
2872 }
2873
2874 qed_hw_hwfn_prepare(p_hwfn);
fe56b9e6
YM		 2875
2876 /* Initialize MCP structure */
2877 rc = qed_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
2878 if (rc) {
2879 DP_NOTICE(p_hwfn, "Failed initializing mcp command\n");
2880 goto err1;
2881 }
2882
2883 /* Read the device configuration information from the HW and SHMEM */
2884 rc = qed_get_hw_info(p_hwfn, p_hwfn->p_main_ptt, personality);
2885 if (rc) {
2886 DP_NOTICE(p_hwfn, "Failed to get HW information\n");
2887 goto err2;
2888 }
2889
18a69e36
MY		 2890 /* Sending a mailbox to the MFW should be done after qed_get_hw_info()
2891 * is called as it sets the ports number in an engine.
2892 */
2893 if (IS_LEAD_HWFN(p_hwfn)) {
2894 rc = qed_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
2895 if (rc)
2896 DP_NOTICE(p_hwfn, "Failed to initiate PF FLR\n");
2897 }
2898
fe56b9e6
YM		 2899 /* Allocate the init RT array and initialize the init-ops engine */
2900 rc = qed_init_alloc(p_hwfn);
2591c280 2901 if (rc)
fe56b9e6 2902 goto err2;
fe56b9e6
YM		 2903
2904 return rc;
2905err2:
32a47e72
YM		 2906 if (IS_LEAD_HWFN(p_hwfn))
2907 qed_iov_free_hw_info(p_hwfn->cdev);
fe56b9e6
YM		 2908 qed_mcp_free(p_hwfn);
2909err1:
2910 qed_hw_hwfn_free(p_hwfn);
2911err0:
2912 return rc;
2913}
2914
fe56b9e6
YM		 2915int qed_hw_prepare(struct qed_dev *cdev,
2916 int personality)
2917{
c78df14e
AE		 2918 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
2919 int rc;
fe56b9e6
YM		 2920
2921 /* Store the precompiled init data ptrs */
1408cc1f
YM		 2922 if (IS_PF(cdev))
2923 qed_init_iro_array(cdev);
fe56b9e6
YM		 2924
2925 /* Initialize the first hwfn - will learn number of hwfns */
c78df14e
AE		 2926 rc = qed_hw_prepare_single(p_hwfn,
2927 cdev->regview,
fe56b9e6
YM		 2928 cdev->doorbells, personality);
2929 if (rc)
2930 return rc;
2931
c78df14e 2932 personality = p_hwfn->hw_info.personality;
fe56b9e6
YM		 2933
2934 /* Initialize the rest of the hwfns */
c78df14e 2935 if (cdev->num_hwfns > 1) {
fe56b9e6 2936 void __iomem *p_regview, *p_doorbell;
c78df14e
AE		 2937 u8 __iomem *addr;
2938
2939 /* adjust bar offset for second engine */
15582962
RV		 2940 addr = cdev->regview +
2941 qed_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt,
2942 BAR_ID_0) / 2;
c78df14e 2943 p_regview = addr;
fe56b9e6 2944
15582962
RV		 2945 addr = cdev->doorbells +
2946 qed_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt,
2947 BAR_ID_1) / 2;
c78df14e
AE		 2948 p_doorbell = addr;
2949
2950 /* prepare second hw function */
2951 rc = qed_hw_prepare_single(&cdev->hwfns[1], p_regview,
fe56b9e6 2952 p_doorbell, personality);
c78df14e
AE		 2953
2954 /* in case of error, need to free the previously
2955 * initiliazed hwfn 0.
2956 */
fe56b9e6 2957 if (rc) {
1408cc1f
YM		 2958 if (IS_PF(cdev)) {
2959 qed_init_free(p_hwfn);
2960 qed_mcp_free(p_hwfn);
2961 qed_hw_hwfn_free(p_hwfn);
2962 }
fe56b9e6
YM		 2963 }
2964 }
2965
c78df14e 2966 return rc;
fe56b9e6
YM		 2967}
2968
2969void qed_hw_remove(struct qed_dev *cdev)
2970{
0fefbfba 2971 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
fe56b9e6
YM		 2972 int i;
2973
0fefbfba
SK		 2974 if (IS_PF(cdev))
2975 qed_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt,
2976 QED_OV_DRIVER_STATE_NOT_LOADED);
2977
fe56b9e6
YM		 2978 for_each_hwfn(cdev, i) {
2979 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2980
1408cc1f 2981 if (IS_VF(cdev)) {
0b55e27d 2982 qed_vf_pf_release(p_hwfn);
1408cc1f
YM		 2983 continue;
2984 }
2985
fe56b9e6
YM		 2986 qed_init_free(p_hwfn);
2987 qed_hw_hwfn_free(p_hwfn);
2988 qed_mcp_free(p_hwfn);
2989 }
32a47e72
YM		 2990
2991 qed_iov_free_hw_info(cdev);
fe56b9e6
YM		 2992}
2993
a91eb52a
YM		 2994static void qed_chain_free_next_ptr(struct qed_dev *cdev,
2995 struct qed_chain *p_chain)
2996{
2997 void *p_virt = p_chain->p_virt_addr, *p_virt_next = NULL;
2998 dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
2999 struct qed_chain_next *p_next;
3000 u32 size, i;
3001
3002 if (!p_virt)
3003 return;
3004
3005 size = p_chain->elem_size * p_chain->usable_per_page;
3006
3007 for (i = 0; i < p_chain->page_cnt; i++) {
3008 if (!p_virt)
3009 break;
3010
3011 p_next = (struct qed_chain_next *)((u8 *)p_virt + size);
3012 p_virt_next = p_next->next_virt;
3013 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
3014
3015 dma_free_coherent(&cdev->pdev->dev,
3016 QED_CHAIN_PAGE_SIZE, p_virt, p_phys);
3017
3018 p_virt = p_virt_next;
3019 p_phys = p_phys_next;
3020 }
3021}
3022
3023static void qed_chain_free_single(struct qed_dev *cdev,
3024 struct qed_chain *p_chain)
3025{
3026 if (!p_chain->p_virt_addr)
3027 return;
3028
3029 dma_free_coherent(&cdev->pdev->dev,
3030 QED_CHAIN_PAGE_SIZE,
3031 p_chain->p_virt_addr, p_chain->p_phys_addr);
3032}
3033
3034static void qed_chain_free_pbl(struct qed_dev *cdev, struct qed_chain *p_chain)
3035{
3036 void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
3037 u32 page_cnt = p_chain->page_cnt, i, pbl_size;
6d937acf 3038 u8 *p_pbl_virt = p_chain->pbl_sp.p_virt_table;
a91eb52a
YM		 3039
3040 if (!pp_virt_addr_tbl)
3041 return;
3042
6d937acf 3043 if (!p_pbl_virt)
a91eb52a
YM		 3044 goto out;
3045
3046 for (i = 0; i < page_cnt; i++) {
3047 if (!pp_virt_addr_tbl[i])
3048 break;
3049
3050 dma_free_coherent(&cdev->pdev->dev,
3051 QED_CHAIN_PAGE_SIZE,
3052 pp_virt_addr_tbl[i],
3053 *(dma_addr_t *)p_pbl_virt);
3054
3055 p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE;
3056 }
3057
3058 pbl_size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
3059 dma_free_coherent(&cdev->pdev->dev,
3060 pbl_size,
6d937acf
MY		 3061 p_chain->pbl_sp.p_virt_table,
3062 p_chain->pbl_sp.p_phys_table);
a91eb52a
YM		 3063out:
3064 vfree(p_chain->pbl.pp_virt_addr_tbl);
3065}
3066
3067void qed_chain_free(struct qed_dev *cdev, struct qed_chain *p_chain)
3068{
3069 switch (p_chain->mode) {
3070 case QED_CHAIN_MODE_NEXT_PTR:
3071 qed_chain_free_next_ptr(cdev, p_chain);
3072 break;
3073 case QED_CHAIN_MODE_SINGLE:
3074 qed_chain_free_single(cdev, p_chain);
3075 break;
3076 case QED_CHAIN_MODE_PBL:
3077 qed_chain_free_pbl(cdev, p_chain);
3078 break;
3079 }
3080}
3081
3082static int
3083qed_chain_alloc_sanity_check(struct qed_dev *cdev,
3084 enum qed_chain_cnt_type cnt_type,
3085 size_t elem_size, u32 page_cnt)
fe56b9e6 3086{
a91eb52a
YM		 3087 u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
3088
3089 /* The actual chain size can be larger than the maximal possible value
3090 * after rounding up the requested elements number to pages, and after
3091 * taking into acount the unusuable elements (next-ptr elements).
3092 * The size of a "u16" chain can be (U16_MAX + 1) since the chain
3093 * size/capacity fields are of a u32 type.
3094 */
3095 if ((cnt_type == QED_CHAIN_CNT_TYPE_U16 &&
3ef310a7
TT		 3096 chain_size > ((u32)U16_MAX + 1)) ||
3097 (cnt_type == QED_CHAIN_CNT_TYPE_U32 && chain_size > U32_MAX)) {
a91eb52a
YM		 3098 DP_NOTICE(cdev,
3099 "The actual chain size (0x%llx) is larger than the maximal possible value\n",
3100 chain_size);
3101 return -EINVAL;
3102 }
3103
3104 return 0;
3105}
3106
3107static int
3108qed_chain_alloc_next_ptr(struct qed_dev *cdev, struct qed_chain *p_chain)
3109{
3110 void *p_virt = NULL, *p_virt_prev = NULL;
fe56b9e6 3111 dma_addr_t p_phys = 0;
a91eb52a 3112 u32 i;
fe56b9e6 3113
a91eb52a
YM		 3114 for (i = 0; i < p_chain->page_cnt; i++) {
3115 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
3116 QED_CHAIN_PAGE_SIZE,
3117 &p_phys, GFP_KERNEL);
2591c280 3118 if (!p_virt)
a91eb52a 3119 return -ENOMEM;
a91eb52a
YM		 3120
3121 if (i == 0) {
3122 qed_chain_init_mem(p_chain, p_virt, p_phys);
3123 qed_chain_reset(p_chain);
3124 } else {
3125 qed_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3126 p_virt, p_phys);
3127 }
3128
3129 p_virt_prev = p_virt;
3130 }
3131 /* Last page's next element should point to the beginning of the
3132 * chain.
3133 */
3134 qed_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3135 p_chain->p_virt_addr,
3136 p_chain->p_phys_addr);
3137
3138 return 0;
3139}
3140
3141static int
3142qed_chain_alloc_single(struct qed_dev *cdev, struct qed_chain *p_chain)
3143{
3144 dma_addr_t p_phys = 0;
3145 void *p_virt = NULL;
fe56b9e6 3146
fe56b9e6 3147 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
a91eb52a 3148 QED_CHAIN_PAGE_SIZE, &p_phys, GFP_KERNEL);
2591c280 3149 if (!p_virt)
a91eb52a 3150 return -ENOMEM;
fe56b9e6 3151
a91eb52a
YM		 3152 qed_chain_init_mem(p_chain, p_virt, p_phys);
3153 qed_chain_reset(p_chain);
fe56b9e6 3154
a91eb52a
YM		 3155 return 0;
3156}
3157
3158static int qed_chain_alloc_pbl(struct qed_dev *cdev, struct qed_chain *p_chain)
3159{
3160 u32 page_cnt = p_chain->page_cnt, size, i;
3161 dma_addr_t p_phys = 0, p_pbl_phys = 0;
3162 void **pp_virt_addr_tbl = NULL;
3163 u8 *p_pbl_virt = NULL;
3164 void *p_virt = NULL;
3165
3166 size = page_cnt * sizeof(*pp_virt_addr_tbl);
2591c280
JP		 3167 pp_virt_addr_tbl = vzalloc(size);
3168 if (!pp_virt_addr_tbl)
a91eb52a 3169 return -ENOMEM;
fe56b9e6 3170
a91eb52a
YM		 3171 /* The allocation of the PBL table is done with its full size, since it
3172 * is expected to be successive.
3173 * qed_chain_init_pbl_mem() is called even in a case of an allocation
3174 * failure, since pp_virt_addr_tbl was previously allocated, and it
3175 * should be saved to allow its freeing during the error flow.
3176 */
3177 size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
3178 p_pbl_virt = dma_alloc_coherent(&cdev->pdev->dev,
3179 size, &p_pbl_phys, GFP_KERNEL);
3180 qed_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
3181 pp_virt_addr_tbl);
2591c280 3182 if (!p_pbl_virt)
a91eb52a 3183 return -ENOMEM;
fe56b9e6 3184
a91eb52a
YM		 3185 for (i = 0; i < page_cnt; i++) {
3186 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
3187 QED_CHAIN_PAGE_SIZE,
3188 &p_phys, GFP_KERNEL);
2591c280 3189 if (!p_virt)
a91eb52a 3190 return -ENOMEM;
fe56b9e6 3191
a91eb52a
YM		 3192 if (i == 0) {
3193 qed_chain_init_mem(p_chain, p_virt, p_phys);
3194 qed_chain_reset(p_chain);
3195 }
3196
3197 /* Fill the PBL table with the physical address of the page */
3198 *(dma_addr_t *)p_pbl_virt = p_phys;
3199 /* Keep the virtual address of the page */
3200 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
3201
3202 p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE;
3203 }
3204
3205 return 0;
fe56b9e6
YM		 3206}
3207
a91eb52a
YM		 3208int qed_chain_alloc(struct qed_dev *cdev,
3209 enum qed_chain_use_mode intended_use,
3210 enum qed_chain_mode mode,
3211 enum qed_chain_cnt_type cnt_type,
3212 u32 num_elems, size_t elem_size, struct qed_chain *p_chain)
fe56b9e6 3213{
a91eb52a
YM		 3214 u32 page_cnt;
3215 int rc = 0;
fe56b9e6 3216
a91eb52a
YM		 3217 if (mode == QED_CHAIN_MODE_SINGLE)
3218 page_cnt = 1;
3219 else
3220 page_cnt = QED_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
fe56b9e6 3221
a91eb52a
YM		 3222 rc = qed_chain_alloc_sanity_check(cdev, cnt_type, elem_size, page_cnt);
3223 if (rc) {
3224 DP_NOTICE(cdev,
2591c280
JP		 3225 "Cannot allocate a chain with the given arguments:\n");
3226 DP_NOTICE(cdev,
a91eb52a
YM		 3227 "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
3228 intended_use, mode, cnt_type, num_elems, elem_size);
3229 return rc;
fe56b9e6
YM		 3230 }
3231
a91eb52a
YM		 3232 qed_chain_init_params(p_chain, page_cnt, (u8) elem_size, intended_use,
3233 mode, cnt_type);
3234
3235 switch (mode) {
3236 case QED_CHAIN_MODE_NEXT_PTR:
3237 rc = qed_chain_alloc_next_ptr(cdev, p_chain);
3238 break;
3239 case QED_CHAIN_MODE_SINGLE:
3240 rc = qed_chain_alloc_single(cdev, p_chain);
3241 break;
3242 case QED_CHAIN_MODE_PBL:
3243 rc = qed_chain_alloc_pbl(cdev, p_chain);
3244 break;
3245 }
3246 if (rc)
3247 goto nomem;
3248
3249 return 0;
3250
3251nomem:
3252 qed_chain_free(cdev, p_chain);
3253 return rc;
fe56b9e6 3254}
cee4d264 3255
a91eb52a 3256int qed_fw_l2_queue(struct qed_hwfn *p_hwfn, u16 src_id, u16 *dst_id)
cee4d264
MC		 3257{
3258 if (src_id >= RESC_NUM(p_hwfn, QED_L2_QUEUE)) {
3259 u16 min, max;
3260
a91eb52a 3261 min = (u16) RESC_START(p_hwfn, QED_L2_QUEUE);
cee4d264
MC		 3262 max = min + RESC_NUM(p_hwfn, QED_L2_QUEUE);
3263 DP_NOTICE(p_hwfn,
3264 "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
3265 src_id, min, max);
3266
3267 return -EINVAL;
3268 }
3269
3270 *dst_id = RESC_START(p_hwfn, QED_L2_QUEUE) + src_id;
3271
3272 return 0;
3273}
3274
1a635e48 3275int qed_fw_vport(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id)
cee4d264
MC		 3276{
3277 if (src_id >= RESC_NUM(p_hwfn, QED_VPORT)) {
3278 u8 min, max;
3279
3280 min = (u8)RESC_START(p_hwfn, QED_VPORT);
3281 max = min + RESC_NUM(p_hwfn, QED_VPORT);
3282 DP_NOTICE(p_hwfn,
3283 "vport id [%d] is not valid, available indices [%d - %d]\n",
3284 src_id, min, max);
3285
3286 return -EINVAL;
3287 }
3288
3289 *dst_id = RESC_START(p_hwfn, QED_VPORT) + src_id;
3290
3291 return 0;
3292}
3293
1a635e48 3294int qed_fw_rss_eng(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id)
cee4d264
MC		 3295{
3296 if (src_id >= RESC_NUM(p_hwfn, QED_RSS_ENG)) {
3297 u8 min, max;
3298
3299 min = (u8)RESC_START(p_hwfn, QED_RSS_ENG);
3300 max = min + RESC_NUM(p_hwfn, QED_RSS_ENG);
3301 DP_NOTICE(p_hwfn,
3302 "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
3303 src_id, min, max);
3304
3305 return -EINVAL;
3306 }
3307
3308 *dst_id = RESC_START(p_hwfn, QED_RSS_ENG) + src_id;
3309
3310 return 0;
3311}
bcd197c8 3312
0a7fb11c
YM		 3313static void qed_llh_mac_to_filter(u32 *p_high, u32 *p_low,
3314 u8 *p_filter)
3315{
3316 *p_high = p_filter[1] | (p_filter[0] << 8);
3317 *p_low = p_filter[5] | (p_filter[4] << 8) |
3318 (p_filter[3] << 16) | (p_filter[2] << 24);
3319}
3320
3321int qed_llh_add_mac_filter(struct qed_hwfn *p_hwfn,
3322 struct qed_ptt *p_ptt, u8 *p_filter)
3323{
3324 u32 high = 0, low = 0, en;
3325 int i;
3326
3327 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3328 return 0;
3329
3330 qed_llh_mac_to_filter(&high, &low, p_filter);
3331
3332 /* Find a free entry and utilize it */
3333 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3334 en = qed_rd(p_hwfn, p_ptt,
3335 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
3336 if (en)
3337 continue;
3338 qed_wr(p_hwfn, p_ptt,
3339 NIG_REG_LLH_FUNC_FILTER_VALUE +
3340 2 * i * sizeof(u32), low);
3341 qed_wr(p_hwfn, p_ptt,
3342 NIG_REG_LLH_FUNC_FILTER_VALUE +
3343 (2 * i + 1) * sizeof(u32), high);
3344 qed_wr(p_hwfn, p_ptt,
3345 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
3346 qed_wr(p_hwfn, p_ptt,
3347 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3348 i * sizeof(u32), 0);
3349 qed_wr(p_hwfn, p_ptt,
3350 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
3351 break;
3352 }
3353 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
3354 DP_NOTICE(p_hwfn,
3355 "Failed to find an empty LLH filter to utilize\n");
3356 return -EINVAL;
3357 }
3358
3359 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3360 "mac: %pM is added at %d\n",
3361 p_filter, i);
3362
3363 return 0;
3364}
3365
3366void qed_llh_remove_mac_filter(struct qed_hwfn *p_hwfn,
3367 struct qed_ptt *p_ptt, u8 *p_filter)
3368{
3369 u32 high = 0, low = 0;
3370 int i;
3371
3372 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3373 return;
3374
3375 qed_llh_mac_to_filter(&high, &low, p_filter);
3376
3377 /* Find the entry and clean it */
3378 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3379 if (qed_rd(p_hwfn, p_ptt,
3380 NIG_REG_LLH_FUNC_FILTER_VALUE +
3381 2 * i * sizeof(u32)) != low)
3382 continue;
3383 if (qed_rd(p_hwfn, p_ptt,
3384 NIG_REG_LLH_FUNC_FILTER_VALUE +
3385 (2 * i + 1) * sizeof(u32)) != high)
3386 continue;
3387
3388 qed_wr(p_hwfn, p_ptt,
3389 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3390 qed_wr(p_hwfn, p_ptt,
3391 NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * i * sizeof(u32), 0);
3392 qed_wr(p_hwfn, p_ptt,
3393 NIG_REG_LLH_FUNC_FILTER_VALUE +
3394 (2 * i + 1) * sizeof(u32), 0);
3395
3396 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3397 "mac: %pM is removed from %d\n",
3398 p_filter, i);
3399 break;
3400 }
3401 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
3402 DP_NOTICE(p_hwfn, "Tried to remove a non-configured filter\n");
3403}
3404
1e128c81
AE		 3405int
3406qed_llh_add_protocol_filter(struct qed_hwfn *p_hwfn,
3407 struct qed_ptt *p_ptt,
3408 u16 source_port_or_eth_type,
3409 u16 dest_port, enum qed_llh_port_filter_type_t type)
3410{
3411 u32 high = 0, low = 0, en;
3412 int i;
3413
3414 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3415 return 0;
3416
3417 switch (type) {
3418 case QED_LLH_FILTER_ETHERTYPE:
3419 high = source_port_or_eth_type;
3420 break;
3421 case QED_LLH_FILTER_TCP_SRC_PORT:
3422 case QED_LLH_FILTER_UDP_SRC_PORT:
3423 low = source_port_or_eth_type << 16;
3424 break;
3425 case QED_LLH_FILTER_TCP_DEST_PORT:
3426 case QED_LLH_FILTER_UDP_DEST_PORT:
3427 low = dest_port;
3428 break;
3429 case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3430 case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3431 low = (source_port_or_eth_type << 16) | dest_port;
3432 break;
3433 default:
3434 DP_NOTICE(p_hwfn,
3435 "Non valid LLH protocol filter type %d\n", type);
3436 return -EINVAL;
3437 }
3438 /* Find a free entry and utilize it */
3439 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3440 en = qed_rd(p_hwfn, p_ptt,
3441 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
3442 if (en)
3443 continue;
3444 qed_wr(p_hwfn, p_ptt,
3445 NIG_REG_LLH_FUNC_FILTER_VALUE +
3446 2 * i * sizeof(u32), low);
3447 qed_wr(p_hwfn, p_ptt,
3448 NIG_REG_LLH_FUNC_FILTER_VALUE +
3449 (2 * i + 1) * sizeof(u32), high);
3450 qed_wr(p_hwfn, p_ptt,
3451 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 1);
3452 qed_wr(p_hwfn, p_ptt,
3453 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3454 i * sizeof(u32), 1 << type);
3455 qed_wr(p_hwfn, p_ptt,
3456 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
3457 break;
3458 }
3459 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
3460 DP_NOTICE(p_hwfn,
3461 "Failed to find an empty LLH filter to utilize\n");
3462 return -EINVAL;
3463 }
3464 switch (type) {
3465 case QED_LLH_FILTER_ETHERTYPE:
3466 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3467 "ETH type %x is added at %d\n",
3468 source_port_or_eth_type, i);
3469 break;
3470 case QED_LLH_FILTER_TCP_SRC_PORT:
3471 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3472 "TCP src port %x is added at %d\n",
3473 source_port_or_eth_type, i);
3474 break;
3475 case QED_LLH_FILTER_UDP_SRC_PORT:
3476 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3477 "UDP src port %x is added at %d\n",
3478 source_port_or_eth_type, i);
3479 break;
3480 case QED_LLH_FILTER_TCP_DEST_PORT:
3481 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3482 "TCP dst port %x is added at %d\n", dest_port, i);
3483 break;
3484 case QED_LLH_FILTER_UDP_DEST_PORT:
3485 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3486 "UDP dst port %x is added at %d\n", dest_port, i);
3487 break;
3488 case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3489 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3490 "TCP src/dst ports %x/%x are added at %d\n",
3491 source_port_or_eth_type, dest_port, i);
3492 break;
3493 case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3494 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3495 "UDP src/dst ports %x/%x are added at %d\n",
3496 source_port_or_eth_type, dest_port, i);
3497 break;
3498 }
3499 return 0;
3500}
3501
3502void
3503qed_llh_remove_protocol_filter(struct qed_hwfn *p_hwfn,
3504 struct qed_ptt *p_ptt,
3505 u16 source_port_or_eth_type,
3506 u16 dest_port,
3507 enum qed_llh_port_filter_type_t type)
3508{
3509 u32 high = 0, low = 0;
3510 int i;
3511
3512 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3513 return;
3514
3515 switch (type) {
3516 case QED_LLH_FILTER_ETHERTYPE:
3517 high = source_port_or_eth_type;
3518 break;
3519 case QED_LLH_FILTER_TCP_SRC_PORT:
3520 case QED_LLH_FILTER_UDP_SRC_PORT:
3521 low = source_port_or_eth_type << 16;
3522 break;
3523 case QED_LLH_FILTER_TCP_DEST_PORT:
3524 case QED_LLH_FILTER_UDP_DEST_PORT:
3525 low = dest_port;
3526 break;
3527 case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3528 case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3529 low = (source_port_or_eth_type << 16) | dest_port;
3530 break;
3531 default:
3532 DP_NOTICE(p_hwfn,
3533 "Non valid LLH protocol filter type %d\n", type);
3534 return;
3535 }
3536
3537 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3538 if (!qed_rd(p_hwfn, p_ptt,
3539 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32)))
3540 continue;
3541 if (!qed_rd(p_hwfn, p_ptt,
3542 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32)))
3543 continue;
3544 if (!(qed_rd(p_hwfn, p_ptt,
3545 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3546 i * sizeof(u32)) & BIT(type)))
3547 continue;
3548 if (qed_rd(p_hwfn, p_ptt,
3549 NIG_REG_LLH_FUNC_FILTER_VALUE +
3550 2 * i * sizeof(u32)) != low)
3551 continue;
3552 if (qed_rd(p_hwfn, p_ptt,
3553 NIG_REG_LLH_FUNC_FILTER_VALUE +
3554 (2 * i + 1) * sizeof(u32)) != high)
3555 continue;
3556
3557 qed_wr(p_hwfn, p_ptt,
3558 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3559 qed_wr(p_hwfn, p_ptt,
3560 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
3561 qed_wr(p_hwfn, p_ptt,
3562 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3563 i * sizeof(u32), 0);
3564 qed_wr(p_hwfn, p_ptt,
3565 NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * i * sizeof(u32), 0);
3566 qed_wr(p_hwfn, p_ptt,
3567 NIG_REG_LLH_FUNC_FILTER_VALUE +
3568 (2 * i + 1) * sizeof(u32), 0);
3569 break;
3570 }
3571
3572 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
3573 DP_NOTICE(p_hwfn, "Tried to remove a non-configured filter\n");
3574}
3575
722003ac
SRK		 3576static int qed_set_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
3577 u32 hw_addr, void *p_eth_qzone,
3578 size_t eth_qzone_size, u8 timeset)
3579{
3580 struct coalescing_timeset *p_coal_timeset;
3581
3582 if (p_hwfn->cdev->int_coalescing_mode != QED_COAL_MODE_ENABLE) {
3583 DP_NOTICE(p_hwfn, "Coalescing configuration not enabled\n");
3584 return -EINVAL;
3585 }
3586
3587 p_coal_timeset = p_eth_qzone;
3588 memset(p_coal_timeset, 0, eth_qzone_size);
3589 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
3590 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
3591 qed_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
3592
3593 return 0;
3594}
3595
3596int qed_set_rxq_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
3597 u16 coalesce, u8 qid, u16 sb_id)
3598{
3599 struct ustorm_eth_queue_zone eth_qzone;
3600 u8 timeset, timer_res;
3601 u16 fw_qid = 0;
3602 u32 address;
3603 int rc;
3604
3605 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
3606 if (coalesce <= 0x7F) {
3607 timer_res = 0;
3608 } else if (coalesce <= 0xFF) {
3609 timer_res = 1;
3610 } else if (coalesce <= 0x1FF) {
3611 timer_res = 2;
3612 } else {
3613 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
3614 return -EINVAL;
3615 }
3616 timeset = (u8)(coalesce >> timer_res);
3617
3618 rc = qed_fw_l2_queue(p_hwfn, (u16)qid, &fw_qid);
3619 if (rc)
3620 return rc;
3621
3622 rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, false);
3623 if (rc)
3624 goto out;
3625
3626 address = BAR0_MAP_REG_USDM_RAM + USTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
3627
3628 rc = qed_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
3629 sizeof(struct ustorm_eth_queue_zone), timeset);
3630 if (rc)
3631 goto out;
3632
3633 p_hwfn->cdev->rx_coalesce_usecs = coalesce;
3634out:
3635 return rc;
3636}
3637
3638int qed_set_txq_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
3639 u16 coalesce, u8 qid, u16 sb_id)
3640{
3641 struct xstorm_eth_queue_zone eth_qzone;
3642 u8 timeset, timer_res;
3643 u16 fw_qid = 0;
3644 u32 address;
3645 int rc;
3646
3647 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
3648 if (coalesce <= 0x7F) {
3649 timer_res = 0;
3650 } else if (coalesce <= 0xFF) {
3651 timer_res = 1;
3652 } else if (coalesce <= 0x1FF) {
3653 timer_res = 2;
3654 } else {
3655 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
3656 return -EINVAL;
3657 }
3658 timeset = (u8)(coalesce >> timer_res);
3659
3660 rc = qed_fw_l2_queue(p_hwfn, (u16)qid, &fw_qid);
3661 if (rc)
3662 return rc;
3663
3664 rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, true);
3665 if (rc)
3666 goto out;
3667
3668 address = BAR0_MAP_REG_XSDM_RAM + XSTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
3669
3670 rc = qed_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
3671 sizeof(struct xstorm_eth_queue_zone), timeset);
3672 if (rc)
3673 goto out;
3674
3675 p_hwfn->cdev->tx_coalesce_usecs = coalesce;
3676out:
3677 return rc;
3678}
3679
bcd197c8
MC		 3680/* Calculate final WFQ values for all vports and configure them.
3681 * After this configuration each vport will have
3682 * approx min rate = min_pf_rate * (vport_wfq / QED_WFQ_UNIT)
3683 */
3684static void qed_configure_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
3685 struct qed_ptt *p_ptt,
3686 u32 min_pf_rate)
3687{
3688 struct init_qm_vport_params *vport_params;
3689 int i;
3690
3691 vport_params = p_hwfn->qm_info.qm_vport_params;
3692
3693 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
3694 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
3695
3696 vport_params[i].vport_wfq = (wfq_speed * QED_WFQ_UNIT) /
3697 min_pf_rate;
3698 qed_init_vport_wfq(p_hwfn, p_ptt,
3699 vport_params[i].first_tx_pq_id,
3700 vport_params[i].vport_wfq);
3701 }
3702}
3703
3704static void qed_init_wfq_default_param(struct qed_hwfn *p_hwfn,
3705 u32 min_pf_rate)
3706
3707{
3708 int i;
3709
3710 for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
3711 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
3712}
3713
3714static void qed_disable_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
3715 struct qed_ptt *p_ptt,
3716 u32 min_pf_rate)
3717{
3718 struct init_qm_vport_params *vport_params;
3719 int i;
3720
3721 vport_params = p_hwfn->qm_info.qm_vport_params;
3722
3723 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
3724 qed_init_wfq_default_param(p_hwfn, min_pf_rate);
3725 qed_init_vport_wfq(p_hwfn, p_ptt,
3726 vport_params[i].first_tx_pq_id,
3727 vport_params[i].vport_wfq);
3728 }
3729}
3730
3731/* This function performs several validations for WFQ
3732 * configuration and required min rate for a given vport
3733 * 1. req_rate must be greater than one percent of min_pf_rate.
3734 * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
3735 * rates to get less than one percent of min_pf_rate.
3736 * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
3737 */
3738static int qed_init_wfq_param(struct qed_hwfn *p_hwfn,
1a635e48 3739 u16 vport_id, u32 req_rate, u32 min_pf_rate)
bcd197c8
MC		 3740{
3741 u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
3742 int non_requested_count = 0, req_count = 0, i, num_vports;
3743
3744 num_vports = p_hwfn->qm_info.num_vports;
3745
3746 /* Accounting for the vports which are configured for WFQ explicitly */
3747 for (i = 0; i < num_vports; i++) {
3748 u32 tmp_speed;
3749
3750 if ((i != vport_id) &&
3751 p_hwfn->qm_info.wfq_data[i].configured) {
3752 req_count++;
3753 tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
3754 total_req_min_rate += tmp_speed;
3755 }
3756 }
3757
3758 /* Include current vport data as well */
3759 req_count++;
3760 total_req_min_rate += req_rate;
3761 non_requested_count = num_vports - req_count;
3762
3763 if (req_rate < min_pf_rate / QED_WFQ_UNIT) {
3764 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
3765 "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
3766 vport_id, req_rate, min_pf_rate);
3767 return -EINVAL;
3768 }
3769
3770 if (num_vports > QED_WFQ_UNIT) {
3771 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
3772 "Number of vports is greater than %d\n",
3773 QED_WFQ_UNIT);
3774 return -EINVAL;
3775 }
3776
3777 if (total_req_min_rate > min_pf_rate) {
3778 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
3779 "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
3780 total_req_min_rate, min_pf_rate);
3781 return -EINVAL;
3782 }
3783
3784 total_left_rate = min_pf_rate - total_req_min_rate;
3785
3786 left_rate_per_vp = total_left_rate / non_requested_count;
3787 if (left_rate_per_vp < min_pf_rate / QED_WFQ_UNIT) {
3788 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
3789 "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
3790 left_rate_per_vp, min_pf_rate);
3791 return -EINVAL;
3792 }
3793
3794 p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
3795 p_hwfn->qm_info.wfq_data[vport_id].configured = true;
3796
3797 for (i = 0; i < num_vports; i++) {
3798 if (p_hwfn->qm_info.wfq_data[i].configured)
3799 continue;
3800
3801 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
3802 }
3803
3804 return 0;
3805}
3806
733def6a
YM		 3807static int __qed_configure_vport_wfq(struct qed_hwfn *p_hwfn,
3808 struct qed_ptt *p_ptt, u16 vp_id, u32 rate)
3809{
3810 struct qed_mcp_link_state *p_link;
3811 int rc = 0;
3812
3813 p_link = &p_hwfn->cdev->hwfns[0].mcp_info->link_output;
3814
3815 if (!p_link->min_pf_rate) {
3816 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
3817 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
3818 return rc;
3819 }
3820
3821 rc = qed_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
3822
1a635e48 3823 if (!rc)
733def6a
YM		 3824 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt,
3825 p_link->min_pf_rate);
3826 else
3827 DP_NOTICE(p_hwfn,
3828 "Validation failed while configuring min rate\n");
3829
3830 return rc;
3831}
3832
bcd197c8
MC		 3833static int __qed_configure_vp_wfq_on_link_change(struct qed_hwfn *p_hwfn,
3834 struct qed_ptt *p_ptt,
3835 u32 min_pf_rate)
3836{
3837 bool use_wfq = false;
3838 int rc = 0;
3839 u16 i;
3840
3841 /* Validate all pre configured vports for wfq */
3842 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
3843 u32 rate;
3844
3845 if (!p_hwfn->qm_info.wfq_data[i].configured)
3846 continue;
3847
3848 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
3849 use_wfq = true;
3850
3851 rc = qed_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
3852 if (rc) {
3853 DP_NOTICE(p_hwfn,
3854 "WFQ validation failed while configuring min rate\n");
3855 break;
3856 }
3857 }
3858
3859 if (!rc && use_wfq)
3860 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
3861 else
3862 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
3863
3864 return rc;
3865}
3866
733def6a
YM		 3867/* Main API for qed clients to configure vport min rate.
3868 * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
3869 * rate - Speed in Mbps needs to be assigned to a given vport.
3870 */
3871int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate)
3872{
3873 int i, rc = -EINVAL;
3874
3875 /* Currently not supported; Might change in future */
3876 if (cdev->num_hwfns > 1) {
3877 DP_NOTICE(cdev,
3878 "WFQ configuration is not supported for this device\n");
3879 return rc;
3880 }
3881
3882 for_each_hwfn(cdev, i) {
3883 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
3884 struct qed_ptt *p_ptt;
3885
3886 p_ptt = qed_ptt_acquire(p_hwfn);
3887 if (!p_ptt)
3888 return -EBUSY;
3889
3890 rc = __qed_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
3891
d572c430 3892 if (rc) {
733def6a
YM		 3893 qed_ptt_release(p_hwfn, p_ptt);
3894 return rc;
3895 }
3896
3897 qed_ptt_release(p_hwfn, p_ptt);
3898 }
3899
3900 return rc;
3901}
3902
bcd197c8 3903/* API to configure WFQ from mcp link change */
6f437d43
MY		 3904void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev,
3905 struct qed_ptt *p_ptt, u32 min_pf_rate)
bcd197c8
MC		 3906{
3907 int i;
3908
3e7cfce2
YM		 3909 if (cdev->num_hwfns > 1) {
3910 DP_VERBOSE(cdev,
3911 NETIF_MSG_LINK,
3912 "WFQ configuration is not supported for this device\n");
3913 return;
3914 }
3915
bcd197c8
MC		 3916 for_each_hwfn(cdev, i) {
3917 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
3918
6f437d43 3919 __qed_configure_vp_wfq_on_link_change(p_hwfn, p_ptt,
bcd197c8
MC		 3920 min_pf_rate);
3921 }
3922}
4b01e519
MC		 3923
3924int __qed_configure_pf_max_bandwidth(struct qed_hwfn *p_hwfn,
3925 struct qed_ptt *p_ptt,
3926 struct qed_mcp_link_state *p_link,
3927 u8 max_bw)
3928{
3929 int rc = 0;
3930
3931 p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
3932
3933 if (!p_link->line_speed && (max_bw != 100))
3934 return rc;
3935
3936 p_link->speed = (p_link->line_speed * max_bw) / 100;
3937 p_hwfn->qm_info.pf_rl = p_link->speed;
3938
3939 /* Since the limiter also affects Tx-switched traffic, we don't want it
3940 * to limit such traffic in case there's no actual limit.
3941 * In that case, set limit to imaginary high boundary.
3942 */
3943 if (max_bw == 100)
3944 p_hwfn->qm_info.pf_rl = 100000;
3945
3946 rc = qed_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
3947 p_hwfn->qm_info.pf_rl);
3948
3949 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
3950 "Configured MAX bandwidth to be %08x Mb/sec\n",
3951 p_link->speed);
3952
3953 return rc;
3954}
3955
3956/* Main API to configure PF max bandwidth where bw range is [1 - 100] */
3957int qed_configure_pf_max_bandwidth(struct qed_dev *cdev, u8 max_bw)
3958{
3959 int i, rc = -EINVAL;
3960
3961 if (max_bw < 1 || max_bw > 100) {
3962 DP_NOTICE(cdev, "PF max bw valid range is [1-100]\n");
3963 return rc;
3964 }
3965
3966 for_each_hwfn(cdev, i) {
3967 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
3968 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
3969 struct qed_mcp_link_state *p_link;
3970 struct qed_ptt *p_ptt;
3971
3972 p_link = &p_lead->mcp_info->link_output;
3973
3974 p_ptt = qed_ptt_acquire(p_hwfn);
3975 if (!p_ptt)
3976 return -EBUSY;
3977
3978 rc = __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt,
3979 p_link, max_bw);
3980
3981 qed_ptt_release(p_hwfn, p_ptt);
3982
3983 if (rc)
3984 break;
3985 }
3986
3987 return rc;
3988}
a64b02d5
MC		 3989
3990int __qed_configure_pf_min_bandwidth(struct qed_hwfn *p_hwfn,
3991 struct qed_ptt *p_ptt,
3992 struct qed_mcp_link_state *p_link,
3993 u8 min_bw)
3994{
3995 int rc = 0;
3996
3997 p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
3998 p_hwfn->qm_info.pf_wfq = min_bw;
3999
4000 if (!p_link->line_speed)
4001 return rc;
4002
4003 p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
4004
4005 rc = qed_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
4006
4007 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
4008 "Configured MIN bandwidth to be %d Mb/sec\n",
4009 p_link->min_pf_rate);
4010
4011 return rc;
4012}
4013
4014/* Main API to configure PF min bandwidth where bw range is [1-100] */
4015int qed_configure_pf_min_bandwidth(struct qed_dev *cdev, u8 min_bw)
4016{
4017 int i, rc = -EINVAL;
4018
4019 if (min_bw < 1 || min_bw > 100) {
4020 DP_NOTICE(cdev, "PF min bw valid range is [1-100]\n");
4021 return rc;
4022 }
4023
4024 for_each_hwfn(cdev, i) {
4025 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
4026 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
4027 struct qed_mcp_link_state *p_link;
4028 struct qed_ptt *p_ptt;
4029
4030 p_link = &p_lead->mcp_info->link_output;
4031
4032 p_ptt = qed_ptt_acquire(p_hwfn);
4033 if (!p_ptt)
4034 return -EBUSY;
4035
4036 rc = __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt,
4037 p_link, min_bw);
4038 if (rc) {
4039 qed_ptt_release(p_hwfn, p_ptt);
4040 return rc;
4041 }
4042
4043 if (p_link->min_pf_rate) {
4044 u32 min_rate = p_link->min_pf_rate;
4045
4046 rc = __qed_configure_vp_wfq_on_link_change(p_hwfn,
4047 p_ptt,
4048 min_rate);
4049 }
4050
4051 qed_ptt_release(p_hwfn, p_ptt);
4052 }
4053
4054 return rc;
4055}
733def6a
YM		 4056
4057void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
4058{
4059 struct qed_mcp_link_state *p_link;
4060
4061 p_link = &p_hwfn->mcp_info->link_output;
4062
4063 if (p_link->min_pf_rate)
4064 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt,
4065 p_link->min_pf_rate);
4066
4067 memset(p_hwfn->qm_info.wfq_data, 0,
4068 sizeof(*p_hwfn->qm_info.wfq_data) * p_hwfn->qm_info.num_vports);
4069}
9c79ddaa
MY		 4070
4071int qed_device_num_engines(struct qed_dev *cdev)
4072{
4073 return QED_IS_BB(cdev) ? 2 : 1;
4074}
Ubuntu Hirsute Linux kernel mirror