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fe56b9e6 YM |
1 | /* QLogic qed NIC Driver |
2 | * Copyright (c) 2015 QLogic Corporation | |
3 | * | |
4 | * This software is available under the terms of the GNU General Public License | |
5 | * (GPL) Version 2, available from the file COPYING in the main directory of | |
6 | * this source tree. | |
7 | */ | |
8 | ||
9 | #include <linux/types.h> | |
10 | #include <asm/byteorder.h> | |
11 | #include <linux/io.h> | |
12 | #include <linux/delay.h> | |
13 | #include <linux/dma-mapping.h> | |
14 | #include <linux/errno.h> | |
15 | #include <linux/kernel.h> | |
16 | #include <linux/mutex.h> | |
17 | #include <linux/pci.h> | |
18 | #include <linux/slab.h> | |
19 | #include <linux/string.h> | |
20 | #include <linux/etherdevice.h> | |
21 | #include <linux/qed/qed_chain.h> | |
22 | #include <linux/qed/qed_if.h> | |
23 | #include "qed.h" | |
24 | #include "qed_cxt.h" | |
25 | #include "qed_dev_api.h" | |
26 | #include "qed_hsi.h" | |
27 | #include "qed_hw.h" | |
28 | #include "qed_init_ops.h" | |
29 | #include "qed_int.h" | |
30 | #include "qed_mcp.h" | |
31 | #include "qed_reg_addr.h" | |
32 | #include "qed_sp.h" | |
33 | ||
34 | /* API common to all protocols */ | |
c2035eea RA |
35 | enum BAR_ID { |
36 | BAR_ID_0, /* used for GRC */ | |
37 | BAR_ID_1 /* Used for doorbells */ | |
38 | }; | |
39 | ||
40 | static u32 qed_hw_bar_size(struct qed_hwfn *p_hwfn, | |
41 | enum BAR_ID bar_id) | |
42 | { | |
43 | u32 bar_reg = (bar_id == BAR_ID_0 ? | |
44 | PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE); | |
45 | u32 val = qed_rd(p_hwfn, p_hwfn->p_main_ptt, bar_reg); | |
46 | ||
47 | if (val) | |
48 | return 1 << (val + 15); | |
49 | ||
50 | /* Old MFW initialized above registered only conditionally */ | |
51 | if (p_hwfn->cdev->num_hwfns > 1) { | |
52 | DP_INFO(p_hwfn, | |
53 | "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n"); | |
54 | return BAR_ID_0 ? 256 * 1024 : 512 * 1024; | |
55 | } else { | |
56 | DP_INFO(p_hwfn, | |
57 | "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n"); | |
58 | return 512 * 1024; | |
59 | } | |
60 | } | |
61 | ||
fe56b9e6 YM |
62 | void qed_init_dp(struct qed_dev *cdev, |
63 | u32 dp_module, u8 dp_level) | |
64 | { | |
65 | u32 i; | |
66 | ||
67 | cdev->dp_level = dp_level; | |
68 | cdev->dp_module = dp_module; | |
69 | for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) { | |
70 | struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; | |
71 | ||
72 | p_hwfn->dp_level = dp_level; | |
73 | p_hwfn->dp_module = dp_module; | |
74 | } | |
75 | } | |
76 | ||
77 | void qed_init_struct(struct qed_dev *cdev) | |
78 | { | |
79 | u8 i; | |
80 | ||
81 | for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) { | |
82 | struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; | |
83 | ||
84 | p_hwfn->cdev = cdev; | |
85 | p_hwfn->my_id = i; | |
86 | p_hwfn->b_active = false; | |
87 | ||
88 | mutex_init(&p_hwfn->dmae_info.mutex); | |
89 | } | |
90 | ||
91 | /* hwfn 0 is always active */ | |
92 | cdev->hwfns[0].b_active = true; | |
93 | ||
94 | /* set the default cache alignment to 128 */ | |
95 | cdev->cache_shift = 7; | |
96 | } | |
97 | ||
98 | static void qed_qm_info_free(struct qed_hwfn *p_hwfn) | |
99 | { | |
100 | struct qed_qm_info *qm_info = &p_hwfn->qm_info; | |
101 | ||
102 | kfree(qm_info->qm_pq_params); | |
103 | qm_info->qm_pq_params = NULL; | |
104 | kfree(qm_info->qm_vport_params); | |
105 | qm_info->qm_vport_params = NULL; | |
106 | kfree(qm_info->qm_port_params); | |
107 | qm_info->qm_port_params = NULL; | |
bcd197c8 MC |
108 | kfree(qm_info->wfq_data); |
109 | qm_info->wfq_data = NULL; | |
fe56b9e6 YM |
110 | } |
111 | ||
112 | void qed_resc_free(struct qed_dev *cdev) | |
113 | { | |
114 | int i; | |
115 | ||
116 | kfree(cdev->fw_data); | |
117 | cdev->fw_data = NULL; | |
118 | ||
119 | kfree(cdev->reset_stats); | |
120 | ||
25c089d7 YM |
121 | for_each_hwfn(cdev, i) { |
122 | struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; | |
123 | ||
124 | kfree(p_hwfn->p_tx_cids); | |
125 | p_hwfn->p_tx_cids = NULL; | |
126 | kfree(p_hwfn->p_rx_cids); | |
127 | p_hwfn->p_rx_cids = NULL; | |
128 | } | |
129 | ||
fe56b9e6 YM |
130 | for_each_hwfn(cdev, i) { |
131 | struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; | |
132 | ||
133 | qed_cxt_mngr_free(p_hwfn); | |
134 | qed_qm_info_free(p_hwfn); | |
135 | qed_spq_free(p_hwfn); | |
136 | qed_eq_free(p_hwfn, p_hwfn->p_eq); | |
137 | qed_consq_free(p_hwfn, p_hwfn->p_consq); | |
138 | qed_int_free(p_hwfn); | |
139 | qed_dmae_info_free(p_hwfn); | |
140 | } | |
141 | } | |
142 | ||
143 | static int qed_init_qm_info(struct qed_hwfn *p_hwfn) | |
144 | { | |
145 | struct qed_qm_info *qm_info = &p_hwfn->qm_info; | |
146 | struct init_qm_port_params *p_qm_port; | |
147 | u8 num_vports, i, vport_id, num_ports; | |
148 | u16 num_pqs, multi_cos_tcs = 1; | |
149 | ||
150 | memset(qm_info, 0, sizeof(*qm_info)); | |
151 | ||
152 | num_pqs = multi_cos_tcs + 1; /* The '1' is for pure-LB */ | |
153 | num_vports = (u8)RESC_NUM(p_hwfn, QED_VPORT); | |
154 | ||
155 | /* Sanity checking that setup requires legal number of resources */ | |
156 | if (num_pqs > RESC_NUM(p_hwfn, QED_PQ)) { | |
157 | DP_ERR(p_hwfn, | |
158 | "Need too many Physical queues - 0x%04x when only %04x are available\n", | |
159 | num_pqs, RESC_NUM(p_hwfn, QED_PQ)); | |
160 | return -EINVAL; | |
161 | } | |
162 | ||
163 | /* PQs will be arranged as follows: First per-TC PQ then pure-LB quete. | |
164 | */ | |
165 | qm_info->qm_pq_params = kzalloc(sizeof(*qm_info->qm_pq_params) * | |
60fffb3b | 166 | num_pqs, GFP_KERNEL); |
fe56b9e6 YM |
167 | if (!qm_info->qm_pq_params) |
168 | goto alloc_err; | |
169 | ||
170 | qm_info->qm_vport_params = kzalloc(sizeof(*qm_info->qm_vport_params) * | |
60fffb3b | 171 | num_vports, GFP_KERNEL); |
fe56b9e6 YM |
172 | if (!qm_info->qm_vport_params) |
173 | goto alloc_err; | |
174 | ||
175 | qm_info->qm_port_params = kzalloc(sizeof(*qm_info->qm_port_params) * | |
60fffb3b | 176 | MAX_NUM_PORTS, GFP_KERNEL); |
fe56b9e6 YM |
177 | if (!qm_info->qm_port_params) |
178 | goto alloc_err; | |
179 | ||
bcd197c8 MC |
180 | qm_info->wfq_data = kcalloc(num_vports, sizeof(*qm_info->wfq_data), |
181 | GFP_KERNEL); | |
182 | if (!qm_info->wfq_data) | |
183 | goto alloc_err; | |
184 | ||
fe56b9e6 YM |
185 | vport_id = (u8)RESC_START(p_hwfn, QED_VPORT); |
186 | ||
187 | /* First init per-TC PQs */ | |
188 | for (i = 0; i < multi_cos_tcs; i++) { | |
189 | struct init_qm_pq_params *params = &qm_info->qm_pq_params[i]; | |
190 | ||
191 | params->vport_id = vport_id; | |
192 | params->tc_id = p_hwfn->hw_info.non_offload_tc; | |
193 | params->wrr_group = 1; | |
194 | } | |
195 | ||
196 | /* Then init pure-LB PQ */ | |
197 | qm_info->pure_lb_pq = i; | |
198 | qm_info->qm_pq_params[i].vport_id = (u8)RESC_START(p_hwfn, QED_VPORT); | |
199 | qm_info->qm_pq_params[i].tc_id = PURE_LB_TC; | |
200 | qm_info->qm_pq_params[i].wrr_group = 1; | |
201 | i++; | |
202 | ||
203 | qm_info->offload_pq = 0; | |
204 | qm_info->num_pqs = num_pqs; | |
205 | qm_info->num_vports = num_vports; | |
206 | ||
207 | /* Initialize qm port parameters */ | |
208 | num_ports = p_hwfn->cdev->num_ports_in_engines; | |
209 | for (i = 0; i < num_ports; i++) { | |
210 | p_qm_port = &qm_info->qm_port_params[i]; | |
211 | p_qm_port->active = 1; | |
212 | p_qm_port->num_active_phys_tcs = 4; | |
213 | p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports; | |
214 | p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports; | |
215 | } | |
216 | ||
217 | qm_info->max_phys_tcs_per_port = NUM_OF_PHYS_TCS; | |
218 | ||
219 | qm_info->start_pq = (u16)RESC_START(p_hwfn, QED_PQ); | |
220 | ||
221 | qm_info->start_vport = (u8)RESC_START(p_hwfn, QED_VPORT); | |
222 | ||
a64b02d5 MC |
223 | for (i = 0; i < qm_info->num_vports; i++) |
224 | qm_info->qm_vport_params[i].vport_wfq = 1; | |
225 | ||
fe56b9e6 YM |
226 | qm_info->pf_wfq = 0; |
227 | qm_info->pf_rl = 0; | |
228 | qm_info->vport_rl_en = 1; | |
a64b02d5 | 229 | qm_info->vport_wfq_en = 1; |
fe56b9e6 YM |
230 | |
231 | return 0; | |
232 | ||
233 | alloc_err: | |
234 | DP_NOTICE(p_hwfn, "Failed to allocate memory for QM params\n"); | |
bcd197c8 | 235 | qed_qm_info_free(p_hwfn); |
fe56b9e6 YM |
236 | return -ENOMEM; |
237 | } | |
238 | ||
239 | int qed_resc_alloc(struct qed_dev *cdev) | |
240 | { | |
241 | struct qed_consq *p_consq; | |
242 | struct qed_eq *p_eq; | |
243 | int i, rc = 0; | |
244 | ||
245 | cdev->fw_data = kzalloc(sizeof(*cdev->fw_data), GFP_KERNEL); | |
246 | if (!cdev->fw_data) | |
247 | return -ENOMEM; | |
248 | ||
25c089d7 YM |
249 | /* Allocate Memory for the Queue->CID mapping */ |
250 | for_each_hwfn(cdev, i) { | |
251 | struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; | |
252 | int tx_size = sizeof(struct qed_hw_cid_data) * | |
253 | RESC_NUM(p_hwfn, QED_L2_QUEUE); | |
254 | int rx_size = sizeof(struct qed_hw_cid_data) * | |
255 | RESC_NUM(p_hwfn, QED_L2_QUEUE); | |
256 | ||
257 | p_hwfn->p_tx_cids = kzalloc(tx_size, GFP_KERNEL); | |
258 | if (!p_hwfn->p_tx_cids) { | |
259 | DP_NOTICE(p_hwfn, | |
260 | "Failed to allocate memory for Tx Cids\n"); | |
9b15acbf | 261 | rc = -ENOMEM; |
25c089d7 YM |
262 | goto alloc_err; |
263 | } | |
264 | ||
265 | p_hwfn->p_rx_cids = kzalloc(rx_size, GFP_KERNEL); | |
266 | if (!p_hwfn->p_rx_cids) { | |
267 | DP_NOTICE(p_hwfn, | |
268 | "Failed to allocate memory for Rx Cids\n"); | |
9b15acbf | 269 | rc = -ENOMEM; |
25c089d7 YM |
270 | goto alloc_err; |
271 | } | |
272 | } | |
273 | ||
fe56b9e6 YM |
274 | for_each_hwfn(cdev, i) { |
275 | struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; | |
276 | ||
277 | /* First allocate the context manager structure */ | |
278 | rc = qed_cxt_mngr_alloc(p_hwfn); | |
279 | if (rc) | |
280 | goto alloc_err; | |
281 | ||
282 | /* Set the HW cid/tid numbers (in the contest manager) | |
283 | * Must be done prior to any further computations. | |
284 | */ | |
285 | rc = qed_cxt_set_pf_params(p_hwfn); | |
286 | if (rc) | |
287 | goto alloc_err; | |
288 | ||
289 | /* Prepare and process QM requirements */ | |
290 | rc = qed_init_qm_info(p_hwfn); | |
291 | if (rc) | |
292 | goto alloc_err; | |
293 | ||
294 | /* Compute the ILT client partition */ | |
295 | rc = qed_cxt_cfg_ilt_compute(p_hwfn); | |
296 | if (rc) | |
297 | goto alloc_err; | |
298 | ||
299 | /* CID map / ILT shadow table / T2 | |
300 | * The talbes sizes are determined by the computations above | |
301 | */ | |
302 | rc = qed_cxt_tables_alloc(p_hwfn); | |
303 | if (rc) | |
304 | goto alloc_err; | |
305 | ||
306 | /* SPQ, must follow ILT because initializes SPQ context */ | |
307 | rc = qed_spq_alloc(p_hwfn); | |
308 | if (rc) | |
309 | goto alloc_err; | |
310 | ||
311 | /* SP status block allocation */ | |
312 | p_hwfn->p_dpc_ptt = qed_get_reserved_ptt(p_hwfn, | |
313 | RESERVED_PTT_DPC); | |
314 | ||
315 | rc = qed_int_alloc(p_hwfn, p_hwfn->p_main_ptt); | |
316 | if (rc) | |
317 | goto alloc_err; | |
318 | ||
319 | /* EQ */ | |
320 | p_eq = qed_eq_alloc(p_hwfn, 256); | |
9b15acbf DC |
321 | if (!p_eq) { |
322 | rc = -ENOMEM; | |
fe56b9e6 | 323 | goto alloc_err; |
9b15acbf | 324 | } |
fe56b9e6 YM |
325 | p_hwfn->p_eq = p_eq; |
326 | ||
327 | p_consq = qed_consq_alloc(p_hwfn); | |
9b15acbf DC |
328 | if (!p_consq) { |
329 | rc = -ENOMEM; | |
fe56b9e6 | 330 | goto alloc_err; |
9b15acbf | 331 | } |
fe56b9e6 YM |
332 | p_hwfn->p_consq = p_consq; |
333 | ||
334 | /* DMA info initialization */ | |
335 | rc = qed_dmae_info_alloc(p_hwfn); | |
336 | if (rc) { | |
337 | DP_NOTICE(p_hwfn, | |
338 | "Failed to allocate memory for dmae_info structure\n"); | |
339 | goto alloc_err; | |
340 | } | |
341 | } | |
342 | ||
343 | cdev->reset_stats = kzalloc(sizeof(*cdev->reset_stats), GFP_KERNEL); | |
344 | if (!cdev->reset_stats) { | |
345 | DP_NOTICE(cdev, "Failed to allocate reset statistics\n"); | |
9b15acbf | 346 | rc = -ENOMEM; |
fe56b9e6 YM |
347 | goto alloc_err; |
348 | } | |
349 | ||
350 | return 0; | |
351 | ||
352 | alloc_err: | |
353 | qed_resc_free(cdev); | |
354 | return rc; | |
355 | } | |
356 | ||
357 | void qed_resc_setup(struct qed_dev *cdev) | |
358 | { | |
359 | int i; | |
360 | ||
361 | for_each_hwfn(cdev, i) { | |
362 | struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; | |
363 | ||
364 | qed_cxt_mngr_setup(p_hwfn); | |
365 | qed_spq_setup(p_hwfn); | |
366 | qed_eq_setup(p_hwfn, p_hwfn->p_eq); | |
367 | qed_consq_setup(p_hwfn, p_hwfn->p_consq); | |
368 | ||
369 | /* Read shadow of current MFW mailbox */ | |
370 | qed_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt); | |
371 | memcpy(p_hwfn->mcp_info->mfw_mb_shadow, | |
372 | p_hwfn->mcp_info->mfw_mb_cur, | |
373 | p_hwfn->mcp_info->mfw_mb_length); | |
374 | ||
375 | qed_int_setup(p_hwfn, p_hwfn->p_main_ptt); | |
376 | } | |
377 | } | |
378 | ||
fe56b9e6 YM |
379 | #define FINAL_CLEANUP_POLL_CNT (100) |
380 | #define FINAL_CLEANUP_POLL_TIME (10) | |
381 | int qed_final_cleanup(struct qed_hwfn *p_hwfn, | |
382 | struct qed_ptt *p_ptt, | |
383 | u16 id) | |
384 | { | |
385 | u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT; | |
386 | int rc = -EBUSY; | |
387 | ||
fc48b7a6 YM |
388 | addr = GTT_BAR0_MAP_REG_USDM_RAM + |
389 | USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id); | |
fe56b9e6 | 390 | |
fc48b7a6 YM |
391 | command |= X_FINAL_CLEANUP_AGG_INT << |
392 | SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT; | |
393 | command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT; | |
394 | command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT; | |
395 | command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT; | |
fe56b9e6 YM |
396 | |
397 | /* Make sure notification is not set before initiating final cleanup */ | |
398 | if (REG_RD(p_hwfn, addr)) { | |
399 | DP_NOTICE( | |
400 | p_hwfn, | |
401 | "Unexpected; Found final cleanup notification before initiating final cleanup\n"); | |
402 | REG_WR(p_hwfn, addr, 0); | |
403 | } | |
404 | ||
405 | DP_VERBOSE(p_hwfn, QED_MSG_IOV, | |
406 | "Sending final cleanup for PFVF[%d] [Command %08x\n]", | |
407 | id, command); | |
408 | ||
409 | qed_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command); | |
410 | ||
411 | /* Poll until completion */ | |
412 | while (!REG_RD(p_hwfn, addr) && count--) | |
413 | msleep(FINAL_CLEANUP_POLL_TIME); | |
414 | ||
415 | if (REG_RD(p_hwfn, addr)) | |
416 | rc = 0; | |
417 | else | |
418 | DP_NOTICE(p_hwfn, | |
419 | "Failed to receive FW final cleanup notification\n"); | |
420 | ||
421 | /* Cleanup afterwards */ | |
422 | REG_WR(p_hwfn, addr, 0); | |
423 | ||
424 | return rc; | |
425 | } | |
426 | ||
427 | static void qed_calc_hw_mode(struct qed_hwfn *p_hwfn) | |
428 | { | |
429 | int hw_mode = 0; | |
430 | ||
12e09c69 | 431 | hw_mode = (1 << MODE_BB_B0); |
fe56b9e6 YM |
432 | |
433 | switch (p_hwfn->cdev->num_ports_in_engines) { | |
434 | case 1: | |
435 | hw_mode |= 1 << MODE_PORTS_PER_ENG_1; | |
436 | break; | |
437 | case 2: | |
438 | hw_mode |= 1 << MODE_PORTS_PER_ENG_2; | |
439 | break; | |
440 | case 4: | |
441 | hw_mode |= 1 << MODE_PORTS_PER_ENG_4; | |
442 | break; | |
443 | default: | |
444 | DP_NOTICE(p_hwfn, "num_ports_in_engine = %d not supported\n", | |
445 | p_hwfn->cdev->num_ports_in_engines); | |
446 | return; | |
447 | } | |
448 | ||
449 | switch (p_hwfn->cdev->mf_mode) { | |
fc48b7a6 YM |
450 | case QED_MF_DEFAULT: |
451 | case QED_MF_NPAR: | |
452 | hw_mode |= 1 << MODE_MF_SI; | |
fe56b9e6 | 453 | break; |
fc48b7a6 | 454 | case QED_MF_OVLAN: |
fe56b9e6 YM |
455 | hw_mode |= 1 << MODE_MF_SD; |
456 | break; | |
fe56b9e6 | 457 | default: |
fc48b7a6 YM |
458 | DP_NOTICE(p_hwfn, "Unsupported MF mode, init as DEFAULT\n"); |
459 | hw_mode |= 1 << MODE_MF_SI; | |
fe56b9e6 YM |
460 | } |
461 | ||
462 | hw_mode |= 1 << MODE_ASIC; | |
463 | ||
464 | p_hwfn->hw_info.hw_mode = hw_mode; | |
465 | } | |
466 | ||
467 | /* Init run time data for all PFs on an engine. */ | |
468 | static void qed_init_cau_rt_data(struct qed_dev *cdev) | |
469 | { | |
470 | u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET; | |
471 | int i, sb_id; | |
472 | ||
473 | for_each_hwfn(cdev, i) { | |
474 | struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; | |
475 | struct qed_igu_info *p_igu_info; | |
476 | struct qed_igu_block *p_block; | |
477 | struct cau_sb_entry sb_entry; | |
478 | ||
479 | p_igu_info = p_hwfn->hw_info.p_igu_info; | |
480 | ||
481 | for (sb_id = 0; sb_id < QED_MAPPING_MEMORY_SIZE(cdev); | |
482 | sb_id++) { | |
483 | p_block = &p_igu_info->igu_map.igu_blocks[sb_id]; | |
484 | if (!p_block->is_pf) | |
485 | continue; | |
486 | ||
487 | qed_init_cau_sb_entry(p_hwfn, &sb_entry, | |
488 | p_block->function_id, | |
489 | 0, 0); | |
490 | STORE_RT_REG_AGG(p_hwfn, offset + sb_id * 2, | |
491 | sb_entry); | |
492 | } | |
493 | } | |
494 | } | |
495 | ||
496 | static int qed_hw_init_common(struct qed_hwfn *p_hwfn, | |
497 | struct qed_ptt *p_ptt, | |
498 | int hw_mode) | |
499 | { | |
500 | struct qed_qm_info *qm_info = &p_hwfn->qm_info; | |
501 | struct qed_qm_common_rt_init_params params; | |
502 | struct qed_dev *cdev = p_hwfn->cdev; | |
503 | int rc = 0; | |
504 | ||
505 | qed_init_cau_rt_data(cdev); | |
506 | ||
507 | /* Program GTT windows */ | |
508 | qed_gtt_init(p_hwfn); | |
509 | ||
510 | if (p_hwfn->mcp_info) { | |
511 | if (p_hwfn->mcp_info->func_info.bandwidth_max) | |
512 | qm_info->pf_rl_en = 1; | |
513 | if (p_hwfn->mcp_info->func_info.bandwidth_min) | |
514 | qm_info->pf_wfq_en = 1; | |
515 | } | |
516 | ||
517 | memset(¶ms, 0, sizeof(params)); | |
518 | params.max_ports_per_engine = p_hwfn->cdev->num_ports_in_engines; | |
519 | params.max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port; | |
520 | params.pf_rl_en = qm_info->pf_rl_en; | |
521 | params.pf_wfq_en = qm_info->pf_wfq_en; | |
522 | params.vport_rl_en = qm_info->vport_rl_en; | |
523 | params.vport_wfq_en = qm_info->vport_wfq_en; | |
524 | params.port_params = qm_info->qm_port_params; | |
525 | ||
526 | qed_qm_common_rt_init(p_hwfn, ¶ms); | |
527 | ||
528 | qed_cxt_hw_init_common(p_hwfn); | |
529 | ||
530 | /* Close gate from NIG to BRB/Storm; By default they are open, but | |
531 | * we close them to prevent NIG from passing data to reset blocks. | |
532 | * Should have been done in the ENGINE phase, but init-tool lacks | |
533 | * proper port-pretend capabilities. | |
534 | */ | |
535 | qed_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0); | |
536 | qed_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0); | |
537 | qed_port_pretend(p_hwfn, p_ptt, p_hwfn->port_id ^ 1); | |
538 | qed_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0); | |
539 | qed_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0); | |
540 | qed_port_unpretend(p_hwfn, p_ptt); | |
541 | ||
542 | rc = qed_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode); | |
543 | if (rc != 0) | |
544 | return rc; | |
545 | ||
546 | qed_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0); | |
547 | qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1); | |
548 | ||
549 | /* Disable relaxed ordering in the PCI config space */ | |
550 | qed_wr(p_hwfn, p_ptt, 0x20b4, | |
551 | qed_rd(p_hwfn, p_ptt, 0x20b4) & ~0x10); | |
552 | ||
553 | return rc; | |
554 | } | |
555 | ||
556 | static int qed_hw_init_port(struct qed_hwfn *p_hwfn, | |
557 | struct qed_ptt *p_ptt, | |
558 | int hw_mode) | |
559 | { | |
560 | int rc = 0; | |
561 | ||
562 | rc = qed_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id, | |
563 | hw_mode); | |
564 | return rc; | |
565 | } | |
566 | ||
567 | static int qed_hw_init_pf(struct qed_hwfn *p_hwfn, | |
568 | struct qed_ptt *p_ptt, | |
464f6645 | 569 | struct qed_tunn_start_params *p_tunn, |
fe56b9e6 YM |
570 | int hw_mode, |
571 | bool b_hw_start, | |
572 | enum qed_int_mode int_mode, | |
573 | bool allow_npar_tx_switch) | |
574 | { | |
575 | u8 rel_pf_id = p_hwfn->rel_pf_id; | |
576 | int rc = 0; | |
577 | ||
578 | if (p_hwfn->mcp_info) { | |
579 | struct qed_mcp_function_info *p_info; | |
580 | ||
581 | p_info = &p_hwfn->mcp_info->func_info; | |
582 | if (p_info->bandwidth_min) | |
583 | p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min; | |
584 | ||
585 | /* Update rate limit once we'll actually have a link */ | |
4b01e519 | 586 | p_hwfn->qm_info.pf_rl = 100000; |
fe56b9e6 YM |
587 | } |
588 | ||
589 | qed_cxt_hw_init_pf(p_hwfn); | |
590 | ||
591 | qed_int_igu_init_rt(p_hwfn); | |
592 | ||
593 | /* Set VLAN in NIG if needed */ | |
594 | if (hw_mode & (1 << MODE_MF_SD)) { | |
595 | DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "Configuring LLH_FUNC_TAG\n"); | |
596 | STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1); | |
597 | STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET, | |
598 | p_hwfn->hw_info.ovlan); | |
599 | } | |
600 | ||
601 | /* Enable classification by MAC if needed */ | |
87aec47d | 602 | if (hw_mode & (1 << MODE_MF_SI)) { |
fe56b9e6 YM |
603 | DP_VERBOSE(p_hwfn, NETIF_MSG_HW, |
604 | "Configuring TAGMAC_CLS_TYPE\n"); | |
605 | STORE_RT_REG(p_hwfn, | |
606 | NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET, 1); | |
607 | } | |
608 | ||
609 | /* Protocl Configuration */ | |
610 | STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET, 0); | |
611 | STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET, 0); | |
612 | STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0); | |
613 | ||
614 | /* Cleanup chip from previous driver if such remains exist */ | |
615 | rc = qed_final_cleanup(p_hwfn, p_ptt, rel_pf_id); | |
616 | if (rc != 0) | |
617 | return rc; | |
618 | ||
619 | /* PF Init sequence */ | |
620 | rc = qed_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode); | |
621 | if (rc) | |
622 | return rc; | |
623 | ||
624 | /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */ | |
625 | rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode); | |
626 | if (rc) | |
627 | return rc; | |
628 | ||
629 | /* Pure runtime initializations - directly to the HW */ | |
630 | qed_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true); | |
631 | ||
632 | if (b_hw_start) { | |
633 | /* enable interrupts */ | |
634 | qed_int_igu_enable(p_hwfn, p_ptt, int_mode); | |
635 | ||
636 | /* send function start command */ | |
464f6645 | 637 | rc = qed_sp_pf_start(p_hwfn, p_tunn, p_hwfn->cdev->mf_mode); |
fe56b9e6 YM |
638 | if (rc) |
639 | DP_NOTICE(p_hwfn, "Function start ramrod failed\n"); | |
640 | } | |
641 | return rc; | |
642 | } | |
643 | ||
644 | static int qed_change_pci_hwfn(struct qed_hwfn *p_hwfn, | |
645 | struct qed_ptt *p_ptt, | |
646 | u8 enable) | |
647 | { | |
648 | u32 delay_idx = 0, val, set_val = enable ? 1 : 0; | |
649 | ||
650 | /* Change PF in PXP */ | |
651 | qed_wr(p_hwfn, p_ptt, | |
652 | PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val); | |
653 | ||
654 | /* wait until value is set - try for 1 second every 50us */ | |
655 | for (delay_idx = 0; delay_idx < 20000; delay_idx++) { | |
656 | val = qed_rd(p_hwfn, p_ptt, | |
657 | PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER); | |
658 | if (val == set_val) | |
659 | break; | |
660 | ||
661 | usleep_range(50, 60); | |
662 | } | |
663 | ||
664 | if (val != set_val) { | |
665 | DP_NOTICE(p_hwfn, | |
666 | "PFID_ENABLE_MASTER wasn't changed after a second\n"); | |
667 | return -EAGAIN; | |
668 | } | |
669 | ||
670 | return 0; | |
671 | } | |
672 | ||
673 | static void qed_reset_mb_shadow(struct qed_hwfn *p_hwfn, | |
674 | struct qed_ptt *p_main_ptt) | |
675 | { | |
676 | /* Read shadow of current MFW mailbox */ | |
677 | qed_mcp_read_mb(p_hwfn, p_main_ptt); | |
678 | memcpy(p_hwfn->mcp_info->mfw_mb_shadow, | |
679 | p_hwfn->mcp_info->mfw_mb_cur, | |
680 | p_hwfn->mcp_info->mfw_mb_length); | |
681 | } | |
682 | ||
683 | int qed_hw_init(struct qed_dev *cdev, | |
464f6645 | 684 | struct qed_tunn_start_params *p_tunn, |
fe56b9e6 YM |
685 | bool b_hw_start, |
686 | enum qed_int_mode int_mode, | |
687 | bool allow_npar_tx_switch, | |
688 | const u8 *bin_fw_data) | |
689 | { | |
86622ee7 | 690 | u32 load_code, param; |
fe56b9e6 YM |
691 | int rc, mfw_rc, i; |
692 | ||
693 | rc = qed_init_fw_data(cdev, bin_fw_data); | |
694 | if (rc != 0) | |
695 | return rc; | |
696 | ||
697 | for_each_hwfn(cdev, i) { | |
698 | struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; | |
699 | ||
700 | /* Enable DMAE in PXP */ | |
701 | rc = qed_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true); | |
702 | ||
703 | qed_calc_hw_mode(p_hwfn); | |
704 | ||
705 | rc = qed_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt, | |
706 | &load_code); | |
707 | if (rc) { | |
708 | DP_NOTICE(p_hwfn, "Failed sending LOAD_REQ command\n"); | |
709 | return rc; | |
710 | } | |
711 | ||
712 | qed_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt); | |
713 | ||
714 | DP_VERBOSE(p_hwfn, QED_MSG_SP, | |
715 | "Load request was sent. Resp:0x%x, Load code: 0x%x\n", | |
716 | rc, load_code); | |
717 | ||
718 | p_hwfn->first_on_engine = (load_code == | |
719 | FW_MSG_CODE_DRV_LOAD_ENGINE); | |
720 | ||
721 | switch (load_code) { | |
722 | case FW_MSG_CODE_DRV_LOAD_ENGINE: | |
723 | rc = qed_hw_init_common(p_hwfn, p_hwfn->p_main_ptt, | |
724 | p_hwfn->hw_info.hw_mode); | |
725 | if (rc) | |
726 | break; | |
727 | /* Fall into */ | |
728 | case FW_MSG_CODE_DRV_LOAD_PORT: | |
729 | rc = qed_hw_init_port(p_hwfn, p_hwfn->p_main_ptt, | |
730 | p_hwfn->hw_info.hw_mode); | |
731 | if (rc) | |
732 | break; | |
733 | ||
734 | /* Fall into */ | |
735 | case FW_MSG_CODE_DRV_LOAD_FUNCTION: | |
736 | rc = qed_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt, | |
464f6645 | 737 | p_tunn, p_hwfn->hw_info.hw_mode, |
fe56b9e6 YM |
738 | b_hw_start, int_mode, |
739 | allow_npar_tx_switch); | |
740 | break; | |
741 | default: | |
742 | rc = -EINVAL; | |
743 | break; | |
744 | } | |
745 | ||
746 | if (rc) | |
747 | DP_NOTICE(p_hwfn, | |
748 | "init phase failed for loadcode 0x%x (rc %d)\n", | |
749 | load_code, rc); | |
750 | ||
751 | /* ACK mfw regardless of success or failure of initialization */ | |
752 | mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, | |
753 | DRV_MSG_CODE_LOAD_DONE, | |
754 | 0, &load_code, ¶m); | |
755 | if (rc) | |
756 | return rc; | |
757 | if (mfw_rc) { | |
758 | DP_NOTICE(p_hwfn, "Failed sending LOAD_DONE command\n"); | |
759 | return mfw_rc; | |
760 | } | |
761 | ||
762 | p_hwfn->hw_init_done = true; | |
763 | } | |
764 | ||
765 | return 0; | |
766 | } | |
767 | ||
768 | #define QED_HW_STOP_RETRY_LIMIT (10) | |
8c925c44 YM |
769 | static inline void qed_hw_timers_stop(struct qed_dev *cdev, |
770 | struct qed_hwfn *p_hwfn, | |
771 | struct qed_ptt *p_ptt) | |
772 | { | |
773 | int i; | |
774 | ||
775 | /* close timers */ | |
776 | qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0); | |
777 | qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0); | |
778 | ||
779 | for (i = 0; i < QED_HW_STOP_RETRY_LIMIT; i++) { | |
780 | if ((!qed_rd(p_hwfn, p_ptt, | |
781 | TM_REG_PF_SCAN_ACTIVE_CONN)) && | |
782 | (!qed_rd(p_hwfn, p_ptt, | |
783 | TM_REG_PF_SCAN_ACTIVE_TASK))) | |
784 | break; | |
785 | ||
786 | /* Dependent on number of connection/tasks, possibly | |
787 | * 1ms sleep is required between polls | |
788 | */ | |
789 | usleep_range(1000, 2000); | |
790 | } | |
791 | ||
792 | if (i < QED_HW_STOP_RETRY_LIMIT) | |
793 | return; | |
794 | ||
795 | DP_NOTICE(p_hwfn, | |
796 | "Timers linear scans are not over [Connection %02x Tasks %02x]\n", | |
797 | (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN), | |
798 | (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)); | |
799 | } | |
800 | ||
801 | void qed_hw_timers_stop_all(struct qed_dev *cdev) | |
802 | { | |
803 | int j; | |
804 | ||
805 | for_each_hwfn(cdev, j) { | |
806 | struct qed_hwfn *p_hwfn = &cdev->hwfns[j]; | |
807 | struct qed_ptt *p_ptt = p_hwfn->p_main_ptt; | |
808 | ||
809 | qed_hw_timers_stop(cdev, p_hwfn, p_ptt); | |
810 | } | |
811 | } | |
812 | ||
fe56b9e6 YM |
813 | int qed_hw_stop(struct qed_dev *cdev) |
814 | { | |
815 | int rc = 0, t_rc; | |
8c925c44 | 816 | int j; |
fe56b9e6 YM |
817 | |
818 | for_each_hwfn(cdev, j) { | |
819 | struct qed_hwfn *p_hwfn = &cdev->hwfns[j]; | |
820 | struct qed_ptt *p_ptt = p_hwfn->p_main_ptt; | |
821 | ||
822 | DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Stopping hw/fw\n"); | |
823 | ||
824 | /* mark the hw as uninitialized... */ | |
825 | p_hwfn->hw_init_done = false; | |
826 | ||
827 | rc = qed_sp_pf_stop(p_hwfn); | |
828 | if (rc) | |
8c925c44 YM |
829 | DP_NOTICE(p_hwfn, |
830 | "Failed to close PF against FW. Continue to stop HW to prevent illegal host access by the device\n"); | |
fe56b9e6 YM |
831 | |
832 | qed_wr(p_hwfn, p_ptt, | |
833 | NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1); | |
834 | ||
835 | qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0); | |
836 | qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0); | |
837 | qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0); | |
838 | qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0); | |
839 | qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0); | |
840 | ||
8c925c44 | 841 | qed_hw_timers_stop(cdev, p_hwfn, p_ptt); |
fe56b9e6 YM |
842 | |
843 | /* Disable Attention Generation */ | |
844 | qed_int_igu_disable_int(p_hwfn, p_ptt); | |
845 | ||
846 | qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0); | |
847 | qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0); | |
848 | ||
849 | qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true); | |
850 | ||
851 | /* Need to wait 1ms to guarantee SBs are cleared */ | |
852 | usleep_range(1000, 2000); | |
853 | } | |
854 | ||
855 | /* Disable DMAE in PXP - in CMT, this should only be done for | |
856 | * first hw-function, and only after all transactions have | |
857 | * stopped for all active hw-functions. | |
858 | */ | |
859 | t_rc = qed_change_pci_hwfn(&cdev->hwfns[0], | |
860 | cdev->hwfns[0].p_main_ptt, | |
861 | false); | |
862 | if (t_rc != 0) | |
863 | rc = t_rc; | |
864 | ||
865 | return rc; | |
866 | } | |
867 | ||
cee4d264 MC |
868 | void qed_hw_stop_fastpath(struct qed_dev *cdev) |
869 | { | |
8c925c44 | 870 | int j; |
cee4d264 MC |
871 | |
872 | for_each_hwfn(cdev, j) { | |
873 | struct qed_hwfn *p_hwfn = &cdev->hwfns[j]; | |
874 | struct qed_ptt *p_ptt = p_hwfn->p_main_ptt; | |
875 | ||
876 | DP_VERBOSE(p_hwfn, | |
877 | NETIF_MSG_IFDOWN, | |
878 | "Shutting down the fastpath\n"); | |
879 | ||
880 | qed_wr(p_hwfn, p_ptt, | |
881 | NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1); | |
882 | ||
883 | qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0); | |
884 | qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0); | |
885 | qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0); | |
886 | qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0); | |
887 | qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0); | |
888 | ||
cee4d264 MC |
889 | qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false); |
890 | ||
891 | /* Need to wait 1ms to guarantee SBs are cleared */ | |
892 | usleep_range(1000, 2000); | |
893 | } | |
894 | } | |
895 | ||
896 | void qed_hw_start_fastpath(struct qed_hwfn *p_hwfn) | |
897 | { | |
898 | /* Re-open incoming traffic */ | |
899 | qed_wr(p_hwfn, p_hwfn->p_main_ptt, | |
900 | NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0); | |
901 | } | |
902 | ||
fe56b9e6 YM |
903 | static int qed_reg_assert(struct qed_hwfn *hwfn, |
904 | struct qed_ptt *ptt, u32 reg, | |
905 | bool expected) | |
906 | { | |
907 | u32 assert_val = qed_rd(hwfn, ptt, reg); | |
908 | ||
909 | if (assert_val != expected) { | |
910 | DP_NOTICE(hwfn, "Value at address 0x%x != 0x%08x\n", | |
911 | reg, expected); | |
912 | return -EINVAL; | |
913 | } | |
914 | ||
915 | return 0; | |
916 | } | |
917 | ||
918 | int qed_hw_reset(struct qed_dev *cdev) | |
919 | { | |
920 | int rc = 0; | |
921 | u32 unload_resp, unload_param; | |
922 | int i; | |
923 | ||
924 | for_each_hwfn(cdev, i) { | |
925 | struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; | |
926 | ||
927 | DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Resetting hw/fw\n"); | |
928 | ||
929 | /* Check for incorrect states */ | |
930 | qed_reg_assert(p_hwfn, p_hwfn->p_main_ptt, | |
931 | QM_REG_USG_CNT_PF_TX, 0); | |
932 | qed_reg_assert(p_hwfn, p_hwfn->p_main_ptt, | |
933 | QM_REG_USG_CNT_PF_OTHER, 0); | |
934 | ||
935 | /* Disable PF in HW blocks */ | |
936 | qed_wr(p_hwfn, p_hwfn->p_main_ptt, DORQ_REG_PF_DB_ENABLE, 0); | |
937 | qed_wr(p_hwfn, p_hwfn->p_main_ptt, QM_REG_PF_EN, 0); | |
938 | qed_wr(p_hwfn, p_hwfn->p_main_ptt, | |
939 | TCFC_REG_STRONG_ENABLE_PF, 0); | |
940 | qed_wr(p_hwfn, p_hwfn->p_main_ptt, | |
941 | CCFC_REG_STRONG_ENABLE_PF, 0); | |
942 | ||
943 | /* Send unload command to MCP */ | |
944 | rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, | |
945 | DRV_MSG_CODE_UNLOAD_REQ, | |
946 | DRV_MB_PARAM_UNLOAD_WOL_MCP, | |
947 | &unload_resp, &unload_param); | |
948 | if (rc) { | |
949 | DP_NOTICE(p_hwfn, "qed_hw_reset: UNLOAD_REQ failed\n"); | |
950 | unload_resp = FW_MSG_CODE_DRV_UNLOAD_ENGINE; | |
951 | } | |
952 | ||
953 | rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, | |
954 | DRV_MSG_CODE_UNLOAD_DONE, | |
955 | 0, &unload_resp, &unload_param); | |
956 | if (rc) { | |
957 | DP_NOTICE(p_hwfn, "qed_hw_reset: UNLOAD_DONE failed\n"); | |
958 | return rc; | |
959 | } | |
960 | } | |
961 | ||
962 | return rc; | |
963 | } | |
964 | ||
965 | /* Free hwfn memory and resources acquired in hw_hwfn_prepare */ | |
966 | static void qed_hw_hwfn_free(struct qed_hwfn *p_hwfn) | |
967 | { | |
968 | qed_ptt_pool_free(p_hwfn); | |
969 | kfree(p_hwfn->hw_info.p_igu_info); | |
970 | } | |
971 | ||
972 | /* Setup bar access */ | |
12e09c69 | 973 | static void qed_hw_hwfn_prepare(struct qed_hwfn *p_hwfn) |
fe56b9e6 | 974 | { |
fe56b9e6 YM |
975 | /* clear indirect access */ |
976 | qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_88_F0, 0); | |
977 | qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_8C_F0, 0); | |
978 | qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_90_F0, 0); | |
979 | qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_94_F0, 0); | |
980 | ||
981 | /* Clean Previous errors if such exist */ | |
982 | qed_wr(p_hwfn, p_hwfn->p_main_ptt, | |
983 | PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, | |
984 | 1 << p_hwfn->abs_pf_id); | |
985 | ||
986 | /* enable internal target-read */ | |
987 | qed_wr(p_hwfn, p_hwfn->p_main_ptt, | |
988 | PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); | |
fe56b9e6 YM |
989 | } |
990 | ||
991 | static void get_function_id(struct qed_hwfn *p_hwfn) | |
992 | { | |
993 | /* ME Register */ | |
994 | p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR); | |
995 | ||
996 | p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR); | |
997 | ||
998 | p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf; | |
999 | p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid, | |
1000 | PXP_CONCRETE_FID_PFID); | |
1001 | p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid, | |
1002 | PXP_CONCRETE_FID_PORT); | |
1003 | } | |
1004 | ||
25c089d7 YM |
1005 | static void qed_hw_set_feat(struct qed_hwfn *p_hwfn) |
1006 | { | |
1007 | u32 *feat_num = p_hwfn->hw_info.feat_num; | |
1008 | int num_features = 1; | |
1009 | ||
1010 | feat_num[QED_PF_L2_QUE] = min_t(u32, RESC_NUM(p_hwfn, QED_SB) / | |
1011 | num_features, | |
1012 | RESC_NUM(p_hwfn, QED_L2_QUEUE)); | |
1013 | DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE, | |
1014 | "#PF_L2_QUEUES=%d #SBS=%d num_features=%d\n", | |
1015 | feat_num[QED_PF_L2_QUE], RESC_NUM(p_hwfn, QED_SB), | |
1016 | num_features); | |
1017 | } | |
1018 | ||
fe56b9e6 YM |
1019 | static void qed_hw_get_resc(struct qed_hwfn *p_hwfn) |
1020 | { | |
1021 | u32 *resc_start = p_hwfn->hw_info.resc_start; | |
1022 | u32 *resc_num = p_hwfn->hw_info.resc_num; | |
4ac801b7 | 1023 | struct qed_sb_cnt_info sb_cnt_info; |
fe56b9e6 YM |
1024 | int num_funcs, i; |
1025 | ||
fc48b7a6 | 1026 | num_funcs = MAX_NUM_PFS_BB; |
fe56b9e6 | 1027 | |
4ac801b7 YM |
1028 | memset(&sb_cnt_info, 0, sizeof(sb_cnt_info)); |
1029 | qed_int_get_num_sbs(p_hwfn, &sb_cnt_info); | |
1030 | ||
fe56b9e6 YM |
1031 | resc_num[QED_SB] = min_t(u32, |
1032 | (MAX_SB_PER_PATH_BB / num_funcs), | |
4ac801b7 | 1033 | sb_cnt_info.sb_cnt); |
25c089d7 | 1034 | resc_num[QED_L2_QUEUE] = MAX_NUM_L2_QUEUES_BB / num_funcs; |
fe56b9e6 | 1035 | resc_num[QED_VPORT] = MAX_NUM_VPORTS_BB / num_funcs; |
25c089d7 | 1036 | resc_num[QED_RSS_ENG] = ETH_RSS_ENGINE_NUM_BB / num_funcs; |
fe56b9e6 YM |
1037 | resc_num[QED_PQ] = MAX_QM_TX_QUEUES_BB / num_funcs; |
1038 | resc_num[QED_RL] = 8; | |
25c089d7 YM |
1039 | resc_num[QED_MAC] = ETH_NUM_MAC_FILTERS / num_funcs; |
1040 | resc_num[QED_VLAN] = (ETH_NUM_VLAN_FILTERS - 1 /*For vlan0*/) / | |
1041 | num_funcs; | |
fe56b9e6 YM |
1042 | resc_num[QED_ILT] = 950; |
1043 | ||
1044 | for (i = 0; i < QED_MAX_RESC; i++) | |
1045 | resc_start[i] = resc_num[i] * p_hwfn->rel_pf_id; | |
1046 | ||
25c089d7 YM |
1047 | qed_hw_set_feat(p_hwfn); |
1048 | ||
fe56b9e6 YM |
1049 | DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE, |
1050 | "The numbers for each resource are:\n" | |
1051 | "SB = %d start = %d\n" | |
25c089d7 | 1052 | "L2_QUEUE = %d start = %d\n" |
fe56b9e6 YM |
1053 | "VPORT = %d start = %d\n" |
1054 | "PQ = %d start = %d\n" | |
1055 | "RL = %d start = %d\n" | |
25c089d7 YM |
1056 | "MAC = %d start = %d\n" |
1057 | "VLAN = %d start = %d\n" | |
fe56b9e6 YM |
1058 | "ILT = %d start = %d\n", |
1059 | p_hwfn->hw_info.resc_num[QED_SB], | |
1060 | p_hwfn->hw_info.resc_start[QED_SB], | |
25c089d7 YM |
1061 | p_hwfn->hw_info.resc_num[QED_L2_QUEUE], |
1062 | p_hwfn->hw_info.resc_start[QED_L2_QUEUE], | |
fe56b9e6 YM |
1063 | p_hwfn->hw_info.resc_num[QED_VPORT], |
1064 | p_hwfn->hw_info.resc_start[QED_VPORT], | |
1065 | p_hwfn->hw_info.resc_num[QED_PQ], | |
1066 | p_hwfn->hw_info.resc_start[QED_PQ], | |
1067 | p_hwfn->hw_info.resc_num[QED_RL], | |
1068 | p_hwfn->hw_info.resc_start[QED_RL], | |
25c089d7 YM |
1069 | p_hwfn->hw_info.resc_num[QED_MAC], |
1070 | p_hwfn->hw_info.resc_start[QED_MAC], | |
1071 | p_hwfn->hw_info.resc_num[QED_VLAN], | |
1072 | p_hwfn->hw_info.resc_start[QED_VLAN], | |
fe56b9e6 YM |
1073 | p_hwfn->hw_info.resc_num[QED_ILT], |
1074 | p_hwfn->hw_info.resc_start[QED_ILT]); | |
1075 | } | |
1076 | ||
1077 | static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, | |
1078 | struct qed_ptt *p_ptt) | |
1079 | { | |
cc875c2e | 1080 | u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg; |
fc48b7a6 | 1081 | u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities; |
cc875c2e | 1082 | struct qed_mcp_link_params *link; |
fe56b9e6 YM |
1083 | |
1084 | /* Read global nvm_cfg address */ | |
1085 | nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0); | |
1086 | ||
1087 | /* Verify MCP has initialized it */ | |
1088 | if (!nvm_cfg_addr) { | |
1089 | DP_NOTICE(p_hwfn, "Shared memory not initialized\n"); | |
1090 | return -EINVAL; | |
1091 | } | |
1092 | ||
1093 | /* Read nvm_cfg1 (Notice this is just offset, and not offsize (TBD) */ | |
1094 | nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4); | |
1095 | ||
cc875c2e YM |
1096 | addr = MCP_REG_SCRATCH + nvm_cfg1_offset + |
1097 | offsetof(struct nvm_cfg1, glob) + | |
1098 | offsetof(struct nvm_cfg1_glob, core_cfg); | |
1099 | ||
1100 | core_cfg = qed_rd(p_hwfn, p_ptt, addr); | |
1101 | ||
1102 | switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >> | |
1103 | NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) { | |
1104 | case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X40G: | |
1105 | p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X40G; | |
1106 | break; | |
1107 | case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X50G: | |
1108 | p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X50G; | |
1109 | break; | |
1110 | case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X100G: | |
1111 | p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X100G; | |
1112 | break; | |
1113 | case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X10G_F: | |
1114 | p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_F; | |
1115 | break; | |
1116 | case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X10G_E: | |
1117 | p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_E; | |
1118 | break; | |
1119 | case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X20G: | |
1120 | p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X20G; | |
1121 | break; | |
1122 | case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X40G: | |
1123 | p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X40G; | |
1124 | break; | |
1125 | case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X25G: | |
1126 | p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X25G; | |
1127 | break; | |
1128 | case NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X25G: | |
1129 | p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X25G; | |
1130 | break; | |
1131 | default: | |
1132 | DP_NOTICE(p_hwfn, "Unknown port mode in 0x%08x\n", | |
1133 | core_cfg); | |
1134 | break; | |
1135 | } | |
1136 | ||
cc875c2e YM |
1137 | /* Read default link configuration */ |
1138 | link = &p_hwfn->mcp_info->link_input; | |
1139 | port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset + | |
1140 | offsetof(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]); | |
1141 | link_temp = qed_rd(p_hwfn, p_ptt, | |
1142 | port_cfg_addr + | |
1143 | offsetof(struct nvm_cfg1_port, speed_cap_mask)); | |
1144 | link->speed.advertised_speeds = | |
1145 | link_temp & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK; | |
1146 | ||
1147 | p_hwfn->mcp_info->link_capabilities.speed_capabilities = | |
1148 | link->speed.advertised_speeds; | |
1149 | ||
1150 | link_temp = qed_rd(p_hwfn, p_ptt, | |
1151 | port_cfg_addr + | |
1152 | offsetof(struct nvm_cfg1_port, link_settings)); | |
1153 | switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >> | |
1154 | NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) { | |
1155 | case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG: | |
1156 | link->speed.autoneg = true; | |
1157 | break; | |
1158 | case NVM_CFG1_PORT_DRV_LINK_SPEED_1G: | |
1159 | link->speed.forced_speed = 1000; | |
1160 | break; | |
1161 | case NVM_CFG1_PORT_DRV_LINK_SPEED_10G: | |
1162 | link->speed.forced_speed = 10000; | |
1163 | break; | |
1164 | case NVM_CFG1_PORT_DRV_LINK_SPEED_25G: | |
1165 | link->speed.forced_speed = 25000; | |
1166 | break; | |
1167 | case NVM_CFG1_PORT_DRV_LINK_SPEED_40G: | |
1168 | link->speed.forced_speed = 40000; | |
1169 | break; | |
1170 | case NVM_CFG1_PORT_DRV_LINK_SPEED_50G: | |
1171 | link->speed.forced_speed = 50000; | |
1172 | break; | |
1173 | case NVM_CFG1_PORT_DRV_LINK_SPEED_100G: | |
1174 | link->speed.forced_speed = 100000; | |
1175 | break; | |
1176 | default: | |
1177 | DP_NOTICE(p_hwfn, "Unknown Speed in 0x%08x\n", | |
1178 | link_temp); | |
1179 | } | |
1180 | ||
1181 | link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK; | |
1182 | link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET; | |
1183 | link->pause.autoneg = !!(link_temp & | |
1184 | NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG); | |
1185 | link->pause.forced_rx = !!(link_temp & | |
1186 | NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX); | |
1187 | link->pause.forced_tx = !!(link_temp & | |
1188 | NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX); | |
1189 | link->loopback_mode = 0; | |
1190 | ||
1191 | DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, | |
1192 | "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n", | |
1193 | link->speed.forced_speed, link->speed.advertised_speeds, | |
1194 | link->speed.autoneg, link->pause.autoneg); | |
1195 | ||
fe56b9e6 YM |
1196 | /* Read Multi-function information from shmem */ |
1197 | addr = MCP_REG_SCRATCH + nvm_cfg1_offset + | |
1198 | offsetof(struct nvm_cfg1, glob) + | |
1199 | offsetof(struct nvm_cfg1_glob, generic_cont0); | |
1200 | ||
1201 | generic_cont0 = qed_rd(p_hwfn, p_ptt, addr); | |
1202 | ||
1203 | mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >> | |
1204 | NVM_CFG1_GLOB_MF_MODE_OFFSET; | |
1205 | ||
1206 | switch (mf_mode) { | |
1207 | case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED: | |
fc48b7a6 | 1208 | p_hwfn->cdev->mf_mode = QED_MF_OVLAN; |
fe56b9e6 YM |
1209 | break; |
1210 | case NVM_CFG1_GLOB_MF_MODE_NPAR1_0: | |
fc48b7a6 | 1211 | p_hwfn->cdev->mf_mode = QED_MF_NPAR; |
fe56b9e6 | 1212 | break; |
fc48b7a6 YM |
1213 | case NVM_CFG1_GLOB_MF_MODE_DEFAULT: |
1214 | p_hwfn->cdev->mf_mode = QED_MF_DEFAULT; | |
fe56b9e6 YM |
1215 | break; |
1216 | } | |
1217 | DP_INFO(p_hwfn, "Multi function mode is %08x\n", | |
1218 | p_hwfn->cdev->mf_mode); | |
1219 | ||
fc48b7a6 YM |
1220 | /* Read Multi-function information from shmem */ |
1221 | addr = MCP_REG_SCRATCH + nvm_cfg1_offset + | |
1222 | offsetof(struct nvm_cfg1, glob) + | |
1223 | offsetof(struct nvm_cfg1_glob, device_capabilities); | |
1224 | ||
1225 | device_capabilities = qed_rd(p_hwfn, p_ptt, addr); | |
1226 | if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET) | |
1227 | __set_bit(QED_DEV_CAP_ETH, | |
1228 | &p_hwfn->hw_info.device_capabilities); | |
1229 | ||
fe56b9e6 YM |
1230 | return qed_mcp_fill_shmem_func_info(p_hwfn, p_ptt); |
1231 | } | |
1232 | ||
1233 | static int | |
1234 | qed_get_hw_info(struct qed_hwfn *p_hwfn, | |
1235 | struct qed_ptt *p_ptt, | |
1236 | enum qed_pci_personality personality) | |
1237 | { | |
1238 | u32 port_mode; | |
1239 | int rc; | |
1240 | ||
1241 | /* Read the port mode */ | |
1242 | port_mode = qed_rd(p_hwfn, p_ptt, | |
1243 | CNIG_REG_NW_PORT_MODE_BB_B0); | |
1244 | ||
1245 | if (port_mode < 3) { | |
1246 | p_hwfn->cdev->num_ports_in_engines = 1; | |
1247 | } else if (port_mode <= 5) { | |
1248 | p_hwfn->cdev->num_ports_in_engines = 2; | |
1249 | } else { | |
1250 | DP_NOTICE(p_hwfn, "PORT MODE: %d not supported\n", | |
1251 | p_hwfn->cdev->num_ports_in_engines); | |
1252 | ||
1253 | /* Default num_ports_in_engines to something */ | |
1254 | p_hwfn->cdev->num_ports_in_engines = 1; | |
1255 | } | |
1256 | ||
1257 | qed_hw_get_nvm_info(p_hwfn, p_ptt); | |
1258 | ||
1259 | rc = qed_int_igu_read_cam(p_hwfn, p_ptt); | |
1260 | if (rc) | |
1261 | return rc; | |
1262 | ||
1263 | if (qed_mcp_is_init(p_hwfn)) | |
1264 | ether_addr_copy(p_hwfn->hw_info.hw_mac_addr, | |
1265 | p_hwfn->mcp_info->func_info.mac); | |
1266 | else | |
1267 | eth_random_addr(p_hwfn->hw_info.hw_mac_addr); | |
1268 | ||
1269 | if (qed_mcp_is_init(p_hwfn)) { | |
1270 | if (p_hwfn->mcp_info->func_info.ovlan != QED_MCP_VLAN_UNSET) | |
1271 | p_hwfn->hw_info.ovlan = | |
1272 | p_hwfn->mcp_info->func_info.ovlan; | |
1273 | ||
1274 | qed_mcp_cmd_port_init(p_hwfn, p_ptt); | |
1275 | } | |
1276 | ||
1277 | if (qed_mcp_is_init(p_hwfn)) { | |
1278 | enum qed_pci_personality protocol; | |
1279 | ||
1280 | protocol = p_hwfn->mcp_info->func_info.protocol; | |
1281 | p_hwfn->hw_info.personality = protocol; | |
1282 | } | |
1283 | ||
1284 | qed_hw_get_resc(p_hwfn); | |
1285 | ||
1286 | return rc; | |
1287 | } | |
1288 | ||
12e09c69 | 1289 | static int qed_get_dev_info(struct qed_dev *cdev) |
fe56b9e6 | 1290 | { |
fc48b7a6 | 1291 | struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); |
fe56b9e6 YM |
1292 | u32 tmp; |
1293 | ||
fc48b7a6 YM |
1294 | /* Read Vendor Id / Device Id */ |
1295 | pci_read_config_word(cdev->pdev, PCI_VENDOR_ID, | |
1296 | &cdev->vendor_id); | |
1297 | pci_read_config_word(cdev->pdev, PCI_DEVICE_ID, | |
1298 | &cdev->device_id); | |
1299 | cdev->chip_num = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt, | |
fe56b9e6 | 1300 | MISCS_REG_CHIP_NUM); |
fc48b7a6 | 1301 | cdev->chip_rev = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt, |
fe56b9e6 YM |
1302 | MISCS_REG_CHIP_REV); |
1303 | MASK_FIELD(CHIP_REV, cdev->chip_rev); | |
1304 | ||
fc48b7a6 | 1305 | cdev->type = QED_DEV_TYPE_BB; |
fe56b9e6 | 1306 | /* Learn number of HW-functions */ |
fc48b7a6 | 1307 | tmp = qed_rd(p_hwfn, p_hwfn->p_main_ptt, |
fe56b9e6 YM |
1308 | MISCS_REG_CMT_ENABLED_FOR_PAIR); |
1309 | ||
fc48b7a6 | 1310 | if (tmp & (1 << p_hwfn->rel_pf_id)) { |
fe56b9e6 YM |
1311 | DP_NOTICE(cdev->hwfns, "device in CMT mode\n"); |
1312 | cdev->num_hwfns = 2; | |
1313 | } else { | |
1314 | cdev->num_hwfns = 1; | |
1315 | } | |
1316 | ||
fc48b7a6 | 1317 | cdev->chip_bond_id = qed_rd(p_hwfn, p_hwfn->p_main_ptt, |
fe56b9e6 YM |
1318 | MISCS_REG_CHIP_TEST_REG) >> 4; |
1319 | MASK_FIELD(CHIP_BOND_ID, cdev->chip_bond_id); | |
fc48b7a6 | 1320 | cdev->chip_metal = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt, |
fe56b9e6 YM |
1321 | MISCS_REG_CHIP_METAL); |
1322 | MASK_FIELD(CHIP_METAL, cdev->chip_metal); | |
1323 | ||
1324 | DP_INFO(cdev->hwfns, | |
1325 | "Chip details - Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n", | |
1326 | cdev->chip_num, cdev->chip_rev, | |
1327 | cdev->chip_bond_id, cdev->chip_metal); | |
12e09c69 YM |
1328 | |
1329 | if (QED_IS_BB(cdev) && CHIP_REV_IS_A0(cdev)) { | |
1330 | DP_NOTICE(cdev->hwfns, | |
1331 | "The chip type/rev (BB A0) is not supported!\n"); | |
1332 | return -EINVAL; | |
1333 | } | |
1334 | ||
1335 | return 0; | |
fe56b9e6 YM |
1336 | } |
1337 | ||
1338 | static int qed_hw_prepare_single(struct qed_hwfn *p_hwfn, | |
1339 | void __iomem *p_regview, | |
1340 | void __iomem *p_doorbells, | |
1341 | enum qed_pci_personality personality) | |
1342 | { | |
1343 | int rc = 0; | |
1344 | ||
1345 | /* Split PCI bars evenly between hwfns */ | |
1346 | p_hwfn->regview = p_regview; | |
1347 | p_hwfn->doorbells = p_doorbells; | |
1348 | ||
1349 | /* Validate that chip access is feasible */ | |
1350 | if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) { | |
1351 | DP_ERR(p_hwfn, | |
1352 | "Reading the ME register returns all Fs; Preventing further chip access\n"); | |
1353 | return -EINVAL; | |
1354 | } | |
1355 | ||
1356 | get_function_id(p_hwfn); | |
1357 | ||
12e09c69 YM |
1358 | /* Allocate PTT pool */ |
1359 | rc = qed_ptt_pool_alloc(p_hwfn); | |
fe56b9e6 YM |
1360 | if (rc) { |
1361 | DP_NOTICE(p_hwfn, "Failed to prepare hwfn's hw\n"); | |
1362 | goto err0; | |
1363 | } | |
1364 | ||
12e09c69 YM |
1365 | /* Allocate the main PTT */ |
1366 | p_hwfn->p_main_ptt = qed_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN); | |
1367 | ||
fe56b9e6 | 1368 | /* First hwfn learns basic information, e.g., number of hwfns */ |
12e09c69 YM |
1369 | if (!p_hwfn->my_id) { |
1370 | rc = qed_get_dev_info(p_hwfn->cdev); | |
1371 | if (rc != 0) | |
1372 | goto err1; | |
1373 | } | |
1374 | ||
1375 | qed_hw_hwfn_prepare(p_hwfn); | |
fe56b9e6 YM |
1376 | |
1377 | /* Initialize MCP structure */ | |
1378 | rc = qed_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt); | |
1379 | if (rc) { | |
1380 | DP_NOTICE(p_hwfn, "Failed initializing mcp command\n"); | |
1381 | goto err1; | |
1382 | } | |
1383 | ||
1384 | /* Read the device configuration information from the HW and SHMEM */ | |
1385 | rc = qed_get_hw_info(p_hwfn, p_hwfn->p_main_ptt, personality); | |
1386 | if (rc) { | |
1387 | DP_NOTICE(p_hwfn, "Failed to get HW information\n"); | |
1388 | goto err2; | |
1389 | } | |
1390 | ||
1391 | /* Allocate the init RT array and initialize the init-ops engine */ | |
1392 | rc = qed_init_alloc(p_hwfn); | |
1393 | if (rc) { | |
1394 | DP_NOTICE(p_hwfn, "Failed to allocate the init array\n"); | |
1395 | goto err2; | |
1396 | } | |
1397 | ||
1398 | return rc; | |
1399 | err2: | |
1400 | qed_mcp_free(p_hwfn); | |
1401 | err1: | |
1402 | qed_hw_hwfn_free(p_hwfn); | |
1403 | err0: | |
1404 | return rc; | |
1405 | } | |
1406 | ||
fe56b9e6 YM |
1407 | int qed_hw_prepare(struct qed_dev *cdev, |
1408 | int personality) | |
1409 | { | |
c78df14e AE |
1410 | struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); |
1411 | int rc; | |
fe56b9e6 YM |
1412 | |
1413 | /* Store the precompiled init data ptrs */ | |
1414 | qed_init_iro_array(cdev); | |
1415 | ||
1416 | /* Initialize the first hwfn - will learn number of hwfns */ | |
c78df14e AE |
1417 | rc = qed_hw_prepare_single(p_hwfn, |
1418 | cdev->regview, | |
fe56b9e6 YM |
1419 | cdev->doorbells, personality); |
1420 | if (rc) | |
1421 | return rc; | |
1422 | ||
c78df14e | 1423 | personality = p_hwfn->hw_info.personality; |
fe56b9e6 YM |
1424 | |
1425 | /* Initialize the rest of the hwfns */ | |
c78df14e | 1426 | if (cdev->num_hwfns > 1) { |
fe56b9e6 | 1427 | void __iomem *p_regview, *p_doorbell; |
c78df14e AE |
1428 | u8 __iomem *addr; |
1429 | ||
1430 | /* adjust bar offset for second engine */ | |
c2035eea | 1431 | addr = cdev->regview + qed_hw_bar_size(p_hwfn, BAR_ID_0) / 2; |
c78df14e | 1432 | p_regview = addr; |
fe56b9e6 | 1433 | |
c78df14e | 1434 | /* adjust doorbell bar offset for second engine */ |
c2035eea | 1435 | addr = cdev->doorbells + qed_hw_bar_size(p_hwfn, BAR_ID_1) / 2; |
c78df14e AE |
1436 | p_doorbell = addr; |
1437 | ||
1438 | /* prepare second hw function */ | |
1439 | rc = qed_hw_prepare_single(&cdev->hwfns[1], p_regview, | |
fe56b9e6 | 1440 | p_doorbell, personality); |
c78df14e AE |
1441 | |
1442 | /* in case of error, need to free the previously | |
1443 | * initiliazed hwfn 0. | |
1444 | */ | |
fe56b9e6 | 1445 | if (rc) { |
c78df14e AE |
1446 | qed_init_free(p_hwfn); |
1447 | qed_mcp_free(p_hwfn); | |
1448 | qed_hw_hwfn_free(p_hwfn); | |
fe56b9e6 YM |
1449 | } |
1450 | } | |
1451 | ||
c78df14e | 1452 | return rc; |
fe56b9e6 YM |
1453 | } |
1454 | ||
1455 | void qed_hw_remove(struct qed_dev *cdev) | |
1456 | { | |
1457 | int i; | |
1458 | ||
1459 | for_each_hwfn(cdev, i) { | |
1460 | struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; | |
1461 | ||
1462 | qed_init_free(p_hwfn); | |
1463 | qed_hw_hwfn_free(p_hwfn); | |
1464 | qed_mcp_free(p_hwfn); | |
1465 | } | |
1466 | } | |
1467 | ||
1468 | int qed_chain_alloc(struct qed_dev *cdev, | |
1469 | enum qed_chain_use_mode intended_use, | |
1470 | enum qed_chain_mode mode, | |
1471 | u16 num_elems, | |
1472 | size_t elem_size, | |
1473 | struct qed_chain *p_chain) | |
1474 | { | |
1475 | dma_addr_t p_pbl_phys = 0; | |
1476 | void *p_pbl_virt = NULL; | |
1477 | dma_addr_t p_phys = 0; | |
1478 | void *p_virt = NULL; | |
1479 | u16 page_cnt = 0; | |
1480 | size_t size; | |
1481 | ||
1482 | if (mode == QED_CHAIN_MODE_SINGLE) | |
1483 | page_cnt = 1; | |
1484 | else | |
1485 | page_cnt = QED_CHAIN_PAGE_CNT(num_elems, elem_size, mode); | |
1486 | ||
1487 | size = page_cnt * QED_CHAIN_PAGE_SIZE; | |
1488 | p_virt = dma_alloc_coherent(&cdev->pdev->dev, | |
1489 | size, &p_phys, GFP_KERNEL); | |
1490 | if (!p_virt) { | |
1491 | DP_NOTICE(cdev, "Failed to allocate chain mem\n"); | |
1492 | goto nomem; | |
1493 | } | |
1494 | ||
1495 | if (mode == QED_CHAIN_MODE_PBL) { | |
1496 | size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE; | |
1497 | p_pbl_virt = dma_alloc_coherent(&cdev->pdev->dev, | |
1498 | size, &p_pbl_phys, | |
1499 | GFP_KERNEL); | |
1500 | if (!p_pbl_virt) { | |
1501 | DP_NOTICE(cdev, "Failed to allocate chain pbl mem\n"); | |
1502 | goto nomem; | |
1503 | } | |
1504 | ||
1505 | qed_chain_pbl_init(p_chain, p_virt, p_phys, page_cnt, | |
1506 | (u8)elem_size, intended_use, | |
1507 | p_pbl_phys, p_pbl_virt); | |
1508 | } else { | |
1509 | qed_chain_init(p_chain, p_virt, p_phys, page_cnt, | |
1510 | (u8)elem_size, intended_use, mode); | |
1511 | } | |
1512 | ||
1513 | return 0; | |
1514 | ||
1515 | nomem: | |
1516 | dma_free_coherent(&cdev->pdev->dev, | |
1517 | page_cnt * QED_CHAIN_PAGE_SIZE, | |
1518 | p_virt, p_phys); | |
1519 | dma_free_coherent(&cdev->pdev->dev, | |
1520 | page_cnt * QED_CHAIN_PBL_ENTRY_SIZE, | |
1521 | p_pbl_virt, p_pbl_phys); | |
1522 | ||
1523 | return -ENOMEM; | |
1524 | } | |
1525 | ||
1526 | void qed_chain_free(struct qed_dev *cdev, | |
1527 | struct qed_chain *p_chain) | |
1528 | { | |
1529 | size_t size; | |
1530 | ||
1531 | if (!p_chain->p_virt_addr) | |
1532 | return; | |
1533 | ||
1534 | if (p_chain->mode == QED_CHAIN_MODE_PBL) { | |
1535 | size = p_chain->page_cnt * QED_CHAIN_PBL_ENTRY_SIZE; | |
1536 | dma_free_coherent(&cdev->pdev->dev, size, | |
1537 | p_chain->pbl.p_virt_table, | |
1538 | p_chain->pbl.p_phys_table); | |
1539 | } | |
1540 | ||
1541 | size = p_chain->page_cnt * QED_CHAIN_PAGE_SIZE; | |
1542 | dma_free_coherent(&cdev->pdev->dev, size, | |
1543 | p_chain->p_virt_addr, | |
1544 | p_chain->p_phys_addr); | |
1545 | } | |
cee4d264 MC |
1546 | |
1547 | int qed_fw_l2_queue(struct qed_hwfn *p_hwfn, | |
1548 | u16 src_id, u16 *dst_id) | |
1549 | { | |
1550 | if (src_id >= RESC_NUM(p_hwfn, QED_L2_QUEUE)) { | |
1551 | u16 min, max; | |
1552 | ||
1553 | min = (u16)RESC_START(p_hwfn, QED_L2_QUEUE); | |
1554 | max = min + RESC_NUM(p_hwfn, QED_L2_QUEUE); | |
1555 | DP_NOTICE(p_hwfn, | |
1556 | "l2_queue id [%d] is not valid, available indices [%d - %d]\n", | |
1557 | src_id, min, max); | |
1558 | ||
1559 | return -EINVAL; | |
1560 | } | |
1561 | ||
1562 | *dst_id = RESC_START(p_hwfn, QED_L2_QUEUE) + src_id; | |
1563 | ||
1564 | return 0; | |
1565 | } | |
1566 | ||
1567 | int qed_fw_vport(struct qed_hwfn *p_hwfn, | |
1568 | u8 src_id, u8 *dst_id) | |
1569 | { | |
1570 | if (src_id >= RESC_NUM(p_hwfn, QED_VPORT)) { | |
1571 | u8 min, max; | |
1572 | ||
1573 | min = (u8)RESC_START(p_hwfn, QED_VPORT); | |
1574 | max = min + RESC_NUM(p_hwfn, QED_VPORT); | |
1575 | DP_NOTICE(p_hwfn, | |
1576 | "vport id [%d] is not valid, available indices [%d - %d]\n", | |
1577 | src_id, min, max); | |
1578 | ||
1579 | return -EINVAL; | |
1580 | } | |
1581 | ||
1582 | *dst_id = RESC_START(p_hwfn, QED_VPORT) + src_id; | |
1583 | ||
1584 | return 0; | |
1585 | } | |
1586 | ||
1587 | int qed_fw_rss_eng(struct qed_hwfn *p_hwfn, | |
1588 | u8 src_id, u8 *dst_id) | |
1589 | { | |
1590 | if (src_id >= RESC_NUM(p_hwfn, QED_RSS_ENG)) { | |
1591 | u8 min, max; | |
1592 | ||
1593 | min = (u8)RESC_START(p_hwfn, QED_RSS_ENG); | |
1594 | max = min + RESC_NUM(p_hwfn, QED_RSS_ENG); | |
1595 | DP_NOTICE(p_hwfn, | |
1596 | "rss_eng id [%d] is not valid, available indices [%d - %d]\n", | |
1597 | src_id, min, max); | |
1598 | ||
1599 | return -EINVAL; | |
1600 | } | |
1601 | ||
1602 | *dst_id = RESC_START(p_hwfn, QED_RSS_ENG) + src_id; | |
1603 | ||
1604 | return 0; | |
1605 | } | |
bcd197c8 MC |
1606 | |
1607 | /* Calculate final WFQ values for all vports and configure them. | |
1608 | * After this configuration each vport will have | |
1609 | * approx min rate = min_pf_rate * (vport_wfq / QED_WFQ_UNIT) | |
1610 | */ | |
1611 | static void qed_configure_wfq_for_all_vports(struct qed_hwfn *p_hwfn, | |
1612 | struct qed_ptt *p_ptt, | |
1613 | u32 min_pf_rate) | |
1614 | { | |
1615 | struct init_qm_vport_params *vport_params; | |
1616 | int i; | |
1617 | ||
1618 | vport_params = p_hwfn->qm_info.qm_vport_params; | |
1619 | ||
1620 | for (i = 0; i < p_hwfn->qm_info.num_vports; i++) { | |
1621 | u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed; | |
1622 | ||
1623 | vport_params[i].vport_wfq = (wfq_speed * QED_WFQ_UNIT) / | |
1624 | min_pf_rate; | |
1625 | qed_init_vport_wfq(p_hwfn, p_ptt, | |
1626 | vport_params[i].first_tx_pq_id, | |
1627 | vport_params[i].vport_wfq); | |
1628 | } | |
1629 | } | |
1630 | ||
1631 | static void qed_init_wfq_default_param(struct qed_hwfn *p_hwfn, | |
1632 | u32 min_pf_rate) | |
1633 | ||
1634 | { | |
1635 | int i; | |
1636 | ||
1637 | for (i = 0; i < p_hwfn->qm_info.num_vports; i++) | |
1638 | p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1; | |
1639 | } | |
1640 | ||
1641 | static void qed_disable_wfq_for_all_vports(struct qed_hwfn *p_hwfn, | |
1642 | struct qed_ptt *p_ptt, | |
1643 | u32 min_pf_rate) | |
1644 | { | |
1645 | struct init_qm_vport_params *vport_params; | |
1646 | int i; | |
1647 | ||
1648 | vport_params = p_hwfn->qm_info.qm_vport_params; | |
1649 | ||
1650 | for (i = 0; i < p_hwfn->qm_info.num_vports; i++) { | |
1651 | qed_init_wfq_default_param(p_hwfn, min_pf_rate); | |
1652 | qed_init_vport_wfq(p_hwfn, p_ptt, | |
1653 | vport_params[i].first_tx_pq_id, | |
1654 | vport_params[i].vport_wfq); | |
1655 | } | |
1656 | } | |
1657 | ||
1658 | /* This function performs several validations for WFQ | |
1659 | * configuration and required min rate for a given vport | |
1660 | * 1. req_rate must be greater than one percent of min_pf_rate. | |
1661 | * 2. req_rate should not cause other vports [not configured for WFQ explicitly] | |
1662 | * rates to get less than one percent of min_pf_rate. | |
1663 | * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate. | |
1664 | */ | |
1665 | static int qed_init_wfq_param(struct qed_hwfn *p_hwfn, | |
1666 | u16 vport_id, u32 req_rate, | |
1667 | u32 min_pf_rate) | |
1668 | { | |
1669 | u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0; | |
1670 | int non_requested_count = 0, req_count = 0, i, num_vports; | |
1671 | ||
1672 | num_vports = p_hwfn->qm_info.num_vports; | |
1673 | ||
1674 | /* Accounting for the vports which are configured for WFQ explicitly */ | |
1675 | for (i = 0; i < num_vports; i++) { | |
1676 | u32 tmp_speed; | |
1677 | ||
1678 | if ((i != vport_id) && | |
1679 | p_hwfn->qm_info.wfq_data[i].configured) { | |
1680 | req_count++; | |
1681 | tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed; | |
1682 | total_req_min_rate += tmp_speed; | |
1683 | } | |
1684 | } | |
1685 | ||
1686 | /* Include current vport data as well */ | |
1687 | req_count++; | |
1688 | total_req_min_rate += req_rate; | |
1689 | non_requested_count = num_vports - req_count; | |
1690 | ||
1691 | if (req_rate < min_pf_rate / QED_WFQ_UNIT) { | |
1692 | DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, | |
1693 | "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n", | |
1694 | vport_id, req_rate, min_pf_rate); | |
1695 | return -EINVAL; | |
1696 | } | |
1697 | ||
1698 | if (num_vports > QED_WFQ_UNIT) { | |
1699 | DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, | |
1700 | "Number of vports is greater than %d\n", | |
1701 | QED_WFQ_UNIT); | |
1702 | return -EINVAL; | |
1703 | } | |
1704 | ||
1705 | if (total_req_min_rate > min_pf_rate) { | |
1706 | DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, | |
1707 | "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n", | |
1708 | total_req_min_rate, min_pf_rate); | |
1709 | return -EINVAL; | |
1710 | } | |
1711 | ||
1712 | total_left_rate = min_pf_rate - total_req_min_rate; | |
1713 | ||
1714 | left_rate_per_vp = total_left_rate / non_requested_count; | |
1715 | if (left_rate_per_vp < min_pf_rate / QED_WFQ_UNIT) { | |
1716 | DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, | |
1717 | "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n", | |
1718 | left_rate_per_vp, min_pf_rate); | |
1719 | return -EINVAL; | |
1720 | } | |
1721 | ||
1722 | p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate; | |
1723 | p_hwfn->qm_info.wfq_data[vport_id].configured = true; | |
1724 | ||
1725 | for (i = 0; i < num_vports; i++) { | |
1726 | if (p_hwfn->qm_info.wfq_data[i].configured) | |
1727 | continue; | |
1728 | ||
1729 | p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp; | |
1730 | } | |
1731 | ||
1732 | return 0; | |
1733 | } | |
1734 | ||
1735 | static int __qed_configure_vp_wfq_on_link_change(struct qed_hwfn *p_hwfn, | |
1736 | struct qed_ptt *p_ptt, | |
1737 | u32 min_pf_rate) | |
1738 | { | |
1739 | bool use_wfq = false; | |
1740 | int rc = 0; | |
1741 | u16 i; | |
1742 | ||
1743 | /* Validate all pre configured vports for wfq */ | |
1744 | for (i = 0; i < p_hwfn->qm_info.num_vports; i++) { | |
1745 | u32 rate; | |
1746 | ||
1747 | if (!p_hwfn->qm_info.wfq_data[i].configured) | |
1748 | continue; | |
1749 | ||
1750 | rate = p_hwfn->qm_info.wfq_data[i].min_speed; | |
1751 | use_wfq = true; | |
1752 | ||
1753 | rc = qed_init_wfq_param(p_hwfn, i, rate, min_pf_rate); | |
1754 | if (rc) { | |
1755 | DP_NOTICE(p_hwfn, | |
1756 | "WFQ validation failed while configuring min rate\n"); | |
1757 | break; | |
1758 | } | |
1759 | } | |
1760 | ||
1761 | if (!rc && use_wfq) | |
1762 | qed_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate); | |
1763 | else | |
1764 | qed_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate); | |
1765 | ||
1766 | return rc; | |
1767 | } | |
1768 | ||
1769 | /* API to configure WFQ from mcp link change */ | |
1770 | void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev, u32 min_pf_rate) | |
1771 | { | |
1772 | int i; | |
1773 | ||
1774 | for_each_hwfn(cdev, i) { | |
1775 | struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; | |
1776 | ||
1777 | __qed_configure_vp_wfq_on_link_change(p_hwfn, | |
1778 | p_hwfn->p_dpc_ptt, | |
1779 | min_pf_rate); | |
1780 | } | |
1781 | } | |
4b01e519 MC |
1782 | |
1783 | int __qed_configure_pf_max_bandwidth(struct qed_hwfn *p_hwfn, | |
1784 | struct qed_ptt *p_ptt, | |
1785 | struct qed_mcp_link_state *p_link, | |
1786 | u8 max_bw) | |
1787 | { | |
1788 | int rc = 0; | |
1789 | ||
1790 | p_hwfn->mcp_info->func_info.bandwidth_max = max_bw; | |
1791 | ||
1792 | if (!p_link->line_speed && (max_bw != 100)) | |
1793 | return rc; | |
1794 | ||
1795 | p_link->speed = (p_link->line_speed * max_bw) / 100; | |
1796 | p_hwfn->qm_info.pf_rl = p_link->speed; | |
1797 | ||
1798 | /* Since the limiter also affects Tx-switched traffic, we don't want it | |
1799 | * to limit such traffic in case there's no actual limit. | |
1800 | * In that case, set limit to imaginary high boundary. | |
1801 | */ | |
1802 | if (max_bw == 100) | |
1803 | p_hwfn->qm_info.pf_rl = 100000; | |
1804 | ||
1805 | rc = qed_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id, | |
1806 | p_hwfn->qm_info.pf_rl); | |
1807 | ||
1808 | DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, | |
1809 | "Configured MAX bandwidth to be %08x Mb/sec\n", | |
1810 | p_link->speed); | |
1811 | ||
1812 | return rc; | |
1813 | } | |
1814 | ||
1815 | /* Main API to configure PF max bandwidth where bw range is [1 - 100] */ | |
1816 | int qed_configure_pf_max_bandwidth(struct qed_dev *cdev, u8 max_bw) | |
1817 | { | |
1818 | int i, rc = -EINVAL; | |
1819 | ||
1820 | if (max_bw < 1 || max_bw > 100) { | |
1821 | DP_NOTICE(cdev, "PF max bw valid range is [1-100]\n"); | |
1822 | return rc; | |
1823 | } | |
1824 | ||
1825 | for_each_hwfn(cdev, i) { | |
1826 | struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; | |
1827 | struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev); | |
1828 | struct qed_mcp_link_state *p_link; | |
1829 | struct qed_ptt *p_ptt; | |
1830 | ||
1831 | p_link = &p_lead->mcp_info->link_output; | |
1832 | ||
1833 | p_ptt = qed_ptt_acquire(p_hwfn); | |
1834 | if (!p_ptt) | |
1835 | return -EBUSY; | |
1836 | ||
1837 | rc = __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt, | |
1838 | p_link, max_bw); | |
1839 | ||
1840 | qed_ptt_release(p_hwfn, p_ptt); | |
1841 | ||
1842 | if (rc) | |
1843 | break; | |
1844 | } | |
1845 | ||
1846 | return rc; | |
1847 | } | |
a64b02d5 MC |
1848 | |
1849 | int __qed_configure_pf_min_bandwidth(struct qed_hwfn *p_hwfn, | |
1850 | struct qed_ptt *p_ptt, | |
1851 | struct qed_mcp_link_state *p_link, | |
1852 | u8 min_bw) | |
1853 | { | |
1854 | int rc = 0; | |
1855 | ||
1856 | p_hwfn->mcp_info->func_info.bandwidth_min = min_bw; | |
1857 | p_hwfn->qm_info.pf_wfq = min_bw; | |
1858 | ||
1859 | if (!p_link->line_speed) | |
1860 | return rc; | |
1861 | ||
1862 | p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100; | |
1863 | ||
1864 | rc = qed_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw); | |
1865 | ||
1866 | DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, | |
1867 | "Configured MIN bandwidth to be %d Mb/sec\n", | |
1868 | p_link->min_pf_rate); | |
1869 | ||
1870 | return rc; | |
1871 | } | |
1872 | ||
1873 | /* Main API to configure PF min bandwidth where bw range is [1-100] */ | |
1874 | int qed_configure_pf_min_bandwidth(struct qed_dev *cdev, u8 min_bw) | |
1875 | { | |
1876 | int i, rc = -EINVAL; | |
1877 | ||
1878 | if (min_bw < 1 || min_bw > 100) { | |
1879 | DP_NOTICE(cdev, "PF min bw valid range is [1-100]\n"); | |
1880 | return rc; | |
1881 | } | |
1882 | ||
1883 | for_each_hwfn(cdev, i) { | |
1884 | struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; | |
1885 | struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev); | |
1886 | struct qed_mcp_link_state *p_link; | |
1887 | struct qed_ptt *p_ptt; | |
1888 | ||
1889 | p_link = &p_lead->mcp_info->link_output; | |
1890 | ||
1891 | p_ptt = qed_ptt_acquire(p_hwfn); | |
1892 | if (!p_ptt) | |
1893 | return -EBUSY; | |
1894 | ||
1895 | rc = __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt, | |
1896 | p_link, min_bw); | |
1897 | if (rc) { | |
1898 | qed_ptt_release(p_hwfn, p_ptt); | |
1899 | return rc; | |
1900 | } | |
1901 | ||
1902 | if (p_link->min_pf_rate) { | |
1903 | u32 min_rate = p_link->min_pf_rate; | |
1904 | ||
1905 | rc = __qed_configure_vp_wfq_on_link_change(p_hwfn, | |
1906 | p_ptt, | |
1907 | min_rate); | |
1908 | } | |
1909 | ||
1910 | qed_ptt_release(p_hwfn, p_ptt); | |
1911 | } | |
1912 | ||
1913 | return rc; | |
1914 | } |