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[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / qlogic / qed / qed_dev.c
CommitLineData
fe56b9e6 1/* QLogic qed NIC Driver
e8f1cb50 2 * Copyright (c) 2015-2017 QLogic Corporation
fe56b9e6 3 *
e8f1cb50
MY		 4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
fe56b9e6
YM		 31 */
32
33#include <linux/types.h>
34#include <asm/byteorder.h>
35#include <linux/io.h>
36#include <linux/delay.h>
37#include <linux/dma-mapping.h>
38#include <linux/errno.h>
39#include <linux/kernel.h>
40#include <linux/mutex.h>
41#include <linux/pci.h>
42#include <linux/slab.h>
43#include <linux/string.h>
a91eb52a 44#include <linux/vmalloc.h>
fe56b9e6
YM		 45#include <linux/etherdevice.h>
46#include <linux/qed/qed_chain.h>
47#include <linux/qed/qed_if.h>
48#include "qed.h"
49#include "qed_cxt.h"
39651abd 50#include "qed_dcbx.h"
fe56b9e6
YM		 51#include "qed_dev_api.h"
52#include "qed_hsi.h"
53#include "qed_hw.h"
54#include "qed_init_ops.h"
55#include "qed_int.h"
fc831825 56#include "qed_iscsi.h"
0a7fb11c 57#include "qed_ll2.h"
fe56b9e6 58#include "qed_mcp.h"
1d6cff4f 59#include "qed_ooo.h"
fe56b9e6
YM		 60#include "qed_reg_addr.h"
61#include "qed_sp.h"
32a47e72 62#include "qed_sriov.h"
0b55e27d 63#include "qed_vf.h"
51ff1725 64#include "qed_roce.h"
fe56b9e6 65
0caf5b26 66static DEFINE_SPINLOCK(qm_lock);
39651abd 67
51ff1725
RA		 68#define QED_MIN_DPIS (4)
69#define QED_MIN_PWM_REGION (QED_WID_SIZE * QED_MIN_DPIS)
70
fe56b9e6 71/* API common to all protocols */
c2035eea
RA		 72enum BAR_ID {
73 BAR_ID_0, /* used for GRC */
74 BAR_ID_1 /* Used for doorbells */
75};
76
1a635e48 77static u32 qed_hw_bar_size(struct qed_hwfn *p_hwfn, enum BAR_ID bar_id)
c2035eea 78{
1408cc1f
YM		 79 u32 bar_reg = (bar_id == BAR_ID_0 ?
80 PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
81 u32 val;
c2035eea 82
1408cc1f
YM		 83 if (IS_VF(p_hwfn->cdev))
84 return 1 << 17;
85
86 val = qed_rd(p_hwfn, p_hwfn->p_main_ptt, bar_reg);
c2035eea
RA		 87 if (val)
88 return 1 << (val + 15);
89
90 /* Old MFW initialized above registered only conditionally */
91 if (p_hwfn->cdev->num_hwfns > 1) {
92 DP_INFO(p_hwfn,
93 "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n");
94 return BAR_ID_0 ? 256 * 1024 : 512 * 1024;
95 } else {
96 DP_INFO(p_hwfn,
97 "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n");
98 return 512 * 1024;
99 }
100}
101
1a635e48 102void qed_init_dp(struct qed_dev *cdev, u32 dp_module, u8 dp_level)
fe56b9e6
YM		 103{
104 u32 i;
105
106 cdev->dp_level = dp_level;
107 cdev->dp_module = dp_module;
108 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
109 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
110
111 p_hwfn->dp_level = dp_level;
112 p_hwfn->dp_module = dp_module;
113 }
114}
115
116void qed_init_struct(struct qed_dev *cdev)
117{
118 u8 i;
119
120 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
121 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
122
123 p_hwfn->cdev = cdev;
124 p_hwfn->my_id = i;
125 p_hwfn->b_active = false;
126
127 mutex_init(&p_hwfn->dmae_info.mutex);
128 }
129
130 /* hwfn 0 is always active */
131 cdev->hwfns[0].b_active = true;
132
133 /* set the default cache alignment to 128 */
134 cdev->cache_shift = 7;
135}
136
137static void qed_qm_info_free(struct qed_hwfn *p_hwfn)
138{
139 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
140
141 kfree(qm_info->qm_pq_params);
142 qm_info->qm_pq_params = NULL;
143 kfree(qm_info->qm_vport_params);
144 qm_info->qm_vport_params = NULL;
145 kfree(qm_info->qm_port_params);
146 qm_info->qm_port_params = NULL;
bcd197c8
MC		 147 kfree(qm_info->wfq_data);
148 qm_info->wfq_data = NULL;
fe56b9e6
YM		 149}
150
151void qed_resc_free(struct qed_dev *cdev)
152{
153 int i;
154
1408cc1f
YM		 155 if (IS_VF(cdev))
156 return;
157
fe56b9e6
YM		 158 kfree(cdev->fw_data);
159 cdev->fw_data = NULL;
160
161 kfree(cdev->reset_stats);
162
163 for_each_hwfn(cdev, i) {
164 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
165
166 qed_cxt_mngr_free(p_hwfn);
167 qed_qm_info_free(p_hwfn);
168 qed_spq_free(p_hwfn);
169 qed_eq_free(p_hwfn, p_hwfn->p_eq);
170 qed_consq_free(p_hwfn, p_hwfn->p_consq);
171 qed_int_free(p_hwfn);
0a7fb11c
YM		 172#ifdef CONFIG_QED_LL2
173 qed_ll2_free(p_hwfn, p_hwfn->p_ll2_info);
174#endif
1d6cff4f 175 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
fc831825 176 qed_iscsi_free(p_hwfn, p_hwfn->p_iscsi_info);
1d6cff4f
YM		 177 qed_ooo_free(p_hwfn, p_hwfn->p_ooo_info);
178 }
32a47e72 179 qed_iov_free(p_hwfn);
fe56b9e6 180 qed_dmae_info_free(p_hwfn);
39651abd 181 qed_dcbx_info_free(p_hwfn, p_hwfn->p_dcbx_info);
fe56b9e6
YM		 182 }
183}
184
79529291 185static int qed_init_qm_info(struct qed_hwfn *p_hwfn, bool b_sleepable)
fe56b9e6 186{
1408cc1f 187 u8 num_vports, vf_offset = 0, i, vport_id, num_ports, curr_queue = 0;
fe56b9e6
YM		 188 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
189 struct init_qm_port_params *p_qm_port;
dbb799c3
YM		 190 bool init_rdma_offload_pq = false;
191 bool init_pure_ack_pq = false;
192 bool init_ooo_pq = false;
fe56b9e6 193 u16 num_pqs, multi_cos_tcs = 1;
cc3d5eb0
YM		 194 u8 pf_wfq = qm_info->pf_wfq;
195 u32 pf_rl = qm_info->pf_rl;
dbb799c3 196 u16 num_pf_rls = 0;
1408cc1f 197 u16 num_vfs = 0;
fe56b9e6 198
1408cc1f
YM		 199#ifdef CONFIG_QED_SRIOV
200 if (p_hwfn->cdev->p_iov_info)
201 num_vfs = p_hwfn->cdev->p_iov_info->total_vfs;
202#endif
fe56b9e6
YM		 203 memset(qm_info, 0, sizeof(*qm_info));
204
1408cc1f 205 num_pqs = multi_cos_tcs + num_vfs + 1; /* The '1' is for pure-LB */
fe56b9e6
YM		 206 num_vports = (u8)RESC_NUM(p_hwfn, QED_VPORT);
207
dbb799c3
YM		 208 if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE) {
209 num_pqs++; /* for RoCE queue */
210 init_rdma_offload_pq = true;
211 /* we subtract num_vfs because each require a rate limiter,
212 * and one default rate limiter
213 */
214 if (p_hwfn->pf_params.rdma_pf_params.enable_dcqcn)
215 num_pf_rls = RESC_NUM(p_hwfn, QED_RL) - num_vfs - 1;
216
217 num_pqs += num_pf_rls;
218 qm_info->num_pf_rls = (u8) num_pf_rls;
219 }
220
221 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
222 num_pqs += 2; /* for iSCSI pure-ACK / OOO queue */
223 init_pure_ack_pq = true;
224 init_ooo_pq = true;
225 }
226
fe56b9e6
YM		 227 /* Sanity checking that setup requires legal number of resources */
228 if (num_pqs > RESC_NUM(p_hwfn, QED_PQ)) {
229 DP_ERR(p_hwfn,
230 "Need too many Physical queues - 0x%04x when only %04x are available\n",
231 num_pqs, RESC_NUM(p_hwfn, QED_PQ));
232 return -EINVAL;
233 }
234
235 /* PQs will be arranged as follows: First per-TC PQ then pure-LB quete.
236 */
79529291
SRK		 237 qm_info->qm_pq_params = kcalloc(num_pqs,
238 sizeof(struct init_qm_pq_params),
239 b_sleepable ? GFP_KERNEL : GFP_ATOMIC);
fe56b9e6
YM		 240 if (!qm_info->qm_pq_params)
241 goto alloc_err;
242
79529291
SRK		 243 qm_info->qm_vport_params = kcalloc(num_vports,
244 sizeof(struct init_qm_vport_params),
245 b_sleepable ? GFP_KERNEL
246 : GFP_ATOMIC);
fe56b9e6
YM		 247 if (!qm_info->qm_vport_params)
248 goto alloc_err;
249
79529291
SRK		 250 qm_info->qm_port_params = kcalloc(MAX_NUM_PORTS,
251 sizeof(struct init_qm_port_params),
252 b_sleepable ? GFP_KERNEL
253 : GFP_ATOMIC);
fe56b9e6
YM		 254 if (!qm_info->qm_port_params)
255 goto alloc_err;
256
79529291
SRK		 257 qm_info->wfq_data = kcalloc(num_vports, sizeof(struct qed_wfq_data),
258 b_sleepable ? GFP_KERNEL : GFP_ATOMIC);
bcd197c8
MC		 259 if (!qm_info->wfq_data)
260 goto alloc_err;
261
fe56b9e6
YM		 262 vport_id = (u8)RESC_START(p_hwfn, QED_VPORT);
263
dbb799c3
YM		 264 /* First init rate limited queues */
265 for (curr_queue = 0; curr_queue < num_pf_rls; curr_queue++) {
266 qm_info->qm_pq_params[curr_queue].vport_id = vport_id++;
267 qm_info->qm_pq_params[curr_queue].tc_id =
268 p_hwfn->hw_info.non_offload_tc;
269 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
270 qm_info->qm_pq_params[curr_queue].rl_valid = 1;
271 }
272
fe56b9e6 273 /* First init per-TC PQs */
39651abd 274 for (i = 0; i < multi_cos_tcs; i++) {
1408cc1f 275 struct init_qm_pq_params *params =
39651abd
SRK		 276 &qm_info->qm_pq_params[curr_queue++];
277
dbb799c3
YM		 278 if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE ||
279 p_hwfn->hw_info.personality == QED_PCI_ETH) {
39651abd
SRK		 280 params->vport_id = vport_id;
281 params->tc_id = p_hwfn->hw_info.non_offload_tc;
282 params->wrr_group = 1;
283 } else {
284 params->vport_id = vport_id;
285 params->tc_id = p_hwfn->hw_info.offload_tc;
286 params->wrr_group = 1;
287 }
fe56b9e6
YM		 288 }
289
290 /* Then init pure-LB PQ */
1408cc1f
YM		 291 qm_info->pure_lb_pq = curr_queue;
292 qm_info->qm_pq_params[curr_queue].vport_id =
293 (u8) RESC_START(p_hwfn, QED_VPORT);
294 qm_info->qm_pq_params[curr_queue].tc_id = PURE_LB_TC;
295 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
296 curr_queue++;
fe56b9e6
YM		 297
298 qm_info->offload_pq = 0;
dbb799c3
YM		 299 if (init_rdma_offload_pq) {
300 qm_info->offload_pq = curr_queue;
301 qm_info->qm_pq_params[curr_queue].vport_id = vport_id;
302 qm_info->qm_pq_params[curr_queue].tc_id =
303 p_hwfn->hw_info.offload_tc;
304 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
305 curr_queue++;
306 }
307
308 if (init_pure_ack_pq) {
309 qm_info->pure_ack_pq = curr_queue;
310 qm_info->qm_pq_params[curr_queue].vport_id = vport_id;
311 qm_info->qm_pq_params[curr_queue].tc_id =
312 p_hwfn->hw_info.offload_tc;
313 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
314 curr_queue++;
315 }
316
317 if (init_ooo_pq) {
318 qm_info->ooo_pq = curr_queue;
319 qm_info->qm_pq_params[curr_queue].vport_id = vport_id;
320 qm_info->qm_pq_params[curr_queue].tc_id = DCBX_ISCSI_OOO_TC;
321 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
322 curr_queue++;
323 }
324
1408cc1f
YM		 325 /* Then init per-VF PQs */
326 vf_offset = curr_queue;
327 for (i = 0; i < num_vfs; i++) {
328 /* First vport is used by the PF */
329 qm_info->qm_pq_params[curr_queue].vport_id = vport_id + i + 1;
330 qm_info->qm_pq_params[curr_queue].tc_id =
331 p_hwfn->hw_info.non_offload_tc;
332 qm_info->qm_pq_params[curr_queue].wrr_group = 1;
351a4ded 333 qm_info->qm_pq_params[curr_queue].rl_valid = 1;
1408cc1f
YM		 334 curr_queue++;
335 }
336
337 qm_info->vf_queues_offset = vf_offset;
fe56b9e6
YM		 338 qm_info->num_pqs = num_pqs;
339 qm_info->num_vports = num_vports;
340
341 /* Initialize qm port parameters */
342 num_ports = p_hwfn->cdev->num_ports_in_engines;
343 for (i = 0; i < num_ports; i++) {
344 p_qm_port = &qm_info->qm_port_params[i];
345 p_qm_port->active = 1;
351a4ded
YM		 346 if (num_ports == 4)
347 p_qm_port->active_phys_tcs = 0x7;
348 else
349 p_qm_port->active_phys_tcs = 0x9f;
fe56b9e6
YM		 350 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;
351 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
352 }
353
354 qm_info->max_phys_tcs_per_port = NUM_OF_PHYS_TCS;
355
356 qm_info->start_pq = (u16)RESC_START(p_hwfn, QED_PQ);
357
1408cc1f
YM		 358 qm_info->num_vf_pqs = num_vfs;
359 qm_info->start_vport = (u8) RESC_START(p_hwfn, QED_VPORT);
fe56b9e6 360
a64b02d5
MC		 361 for (i = 0; i < qm_info->num_vports; i++)
362 qm_info->qm_vport_params[i].vport_wfq = 1;
363
fe56b9e6 364 qm_info->vport_rl_en = 1;
a64b02d5 365 qm_info->vport_wfq_en = 1;
cc3d5eb0
YM		 366 qm_info->pf_rl = pf_rl;
367 qm_info->pf_wfq = pf_wfq;
fe56b9e6
YM		 368
369 return 0;
370
371alloc_err:
bcd197c8 372 qed_qm_info_free(p_hwfn);
fe56b9e6
YM		 373 return -ENOMEM;
374}
375
39651abd
SRK		 376/* This function reconfigures the QM pf on the fly.
377 * For this purpose we:
378 * 1. reconfigure the QM database
379 * 2. set new values to runtime arrat
380 * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
381 * 4. activate init tool in QM_PF stage
382 * 5. send an sdm_qm_cmd through rbc interface to release the QM
383 */
384int qed_qm_reconf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
385{
386 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
387 bool b_rc;
388 int rc;
389
390 /* qm_info is allocated in qed_init_qm_info() which is already called
391 * from qed_resc_alloc() or previous call of qed_qm_reconf().
392 * The allocated size may change each init, so we free it before next
393 * allocation.
394 */
395 qed_qm_info_free(p_hwfn);
396
397 /* initialize qed's qm data structure */
79529291 398 rc = qed_init_qm_info(p_hwfn, false);
39651abd
SRK		 399 if (rc)
400 return rc;
401
402 /* stop PF's qm queues */
403 spin_lock_bh(&qm_lock);
404 b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
405 qm_info->start_pq, qm_info->num_pqs);
406 spin_unlock_bh(&qm_lock);
407 if (!b_rc)
408 return -EINVAL;
409
410 /* clear the QM_PF runtime phase leftovers from previous init */
411 qed_init_clear_rt_data(p_hwfn);
412
413 /* prepare QM portion of runtime array */
414 qed_qm_init_pf(p_hwfn);
415
416 /* activate init tool on runtime array */
417 rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
418 p_hwfn->hw_info.hw_mode);
419 if (rc)
420 return rc;
421
422 /* start PF's qm queues */
423 spin_lock_bh(&qm_lock);
424 b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
425 qm_info->start_pq, qm_info->num_pqs);
426 spin_unlock_bh(&qm_lock);
427 if (!b_rc)
428 return -EINVAL;
429
430 return 0;
431}
432
fe56b9e6
YM		 433int qed_resc_alloc(struct qed_dev *cdev)
434{
fc831825 435 struct qed_iscsi_info *p_iscsi_info;
1d6cff4f 436 struct qed_ooo_info *p_ooo_info;
0a7fb11c
YM		 437#ifdef CONFIG_QED_LL2
438 struct qed_ll2_info *p_ll2_info;
439#endif
fe56b9e6
YM		 440 struct qed_consq *p_consq;
441 struct qed_eq *p_eq;
442 int i, rc = 0;
443
1408cc1f
YM		 444 if (IS_VF(cdev))
445 return rc;
446
fe56b9e6
YM		 447 cdev->fw_data = kzalloc(sizeof(*cdev->fw_data), GFP_KERNEL);
448 if (!cdev->fw_data)
449 return -ENOMEM;
450
451 for_each_hwfn(cdev, i) {
452 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
dbb799c3 453 u32 n_eqes, num_cons;
fe56b9e6
YM		 454
455 /* First allocate the context manager structure */
456 rc = qed_cxt_mngr_alloc(p_hwfn);
457 if (rc)
458 goto alloc_err;
459
460 /* Set the HW cid/tid numbers (in the contest manager)
461 * Must be done prior to any further computations.
462 */
463 rc = qed_cxt_set_pf_params(p_hwfn);
464 if (rc)
465 goto alloc_err;
466
467 /* Prepare and process QM requirements */
79529291 468 rc = qed_init_qm_info(p_hwfn, true);
fe56b9e6
YM		 469 if (rc)
470 goto alloc_err;
471
472 /* Compute the ILT client partition */
473 rc = qed_cxt_cfg_ilt_compute(p_hwfn);
474 if (rc)
475 goto alloc_err;
476
477 /* CID map / ILT shadow table / T2
478 * The talbes sizes are determined by the computations above
479 */
480 rc = qed_cxt_tables_alloc(p_hwfn);
481 if (rc)
482 goto alloc_err;
483
484 /* SPQ, must follow ILT because initializes SPQ context */
485 rc = qed_spq_alloc(p_hwfn);
486 if (rc)
487 goto alloc_err;
488
489 /* SP status block allocation */
490 p_hwfn->p_dpc_ptt = qed_get_reserved_ptt(p_hwfn,
491 RESERVED_PTT_DPC);
492
493 rc = qed_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
494 if (rc)
495 goto alloc_err;
496
32a47e72
YM		 497 rc = qed_iov_alloc(p_hwfn);
498 if (rc)
499 goto alloc_err;
500
fe56b9e6 501 /* EQ */
dbb799c3
YM		 502 n_eqes = qed_chain_get_capacity(&p_hwfn->p_spq->chain);
503 if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE) {
504 num_cons = qed_cxt_get_proto_cid_count(p_hwfn,
505 PROTOCOLID_ROCE,
8c93beaf 506 NULL) * 2;
dbb799c3
YM		 507 n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
508 } else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
509 num_cons =
510 qed_cxt_get_proto_cid_count(p_hwfn,
8c93beaf
YM		 511 PROTOCOLID_ISCSI,
512 NULL);
dbb799c3
YM		 513 n_eqes += 2 * num_cons;
514 }
515
516 if (n_eqes > 0xFFFF) {
517 DP_ERR(p_hwfn,
518 "Cannot allocate 0x%x EQ elements. The maximum of a u16 chain is 0x%x\n",
519 n_eqes, 0xFFFF);
1b4985b5 520 rc = -EINVAL;
fe56b9e6 521 goto alloc_err;
9b15acbf 522 }
dbb799c3
YM		 523
524 p_eq = qed_eq_alloc(p_hwfn, (u16) n_eqes);
525 if (!p_eq)
526 goto alloc_no_mem;
fe56b9e6
YM		 527 p_hwfn->p_eq = p_eq;
528
529 p_consq = qed_consq_alloc(p_hwfn);
dbb799c3
YM		 530 if (!p_consq)
531 goto alloc_no_mem;
fe56b9e6
YM		 532 p_hwfn->p_consq = p_consq;
533
0a7fb11c
YM		 534#ifdef CONFIG_QED_LL2
535 if (p_hwfn->using_ll2) {
536 p_ll2_info = qed_ll2_alloc(p_hwfn);
537 if (!p_ll2_info)
538 goto alloc_no_mem;
539 p_hwfn->p_ll2_info = p_ll2_info;
540 }
541#endif
fc831825
YM		 542 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
543 p_iscsi_info = qed_iscsi_alloc(p_hwfn);
544 if (!p_iscsi_info)
545 goto alloc_no_mem;
546 p_hwfn->p_iscsi_info = p_iscsi_info;
1d6cff4f
YM		 547 p_ooo_info = qed_ooo_alloc(p_hwfn);
548 if (!p_ooo_info)
549 goto alloc_no_mem;
550 p_hwfn->p_ooo_info = p_ooo_info;
fc831825 551 }
0a7fb11c 552
fe56b9e6
YM		 553 /* DMA info initialization */
554 rc = qed_dmae_info_alloc(p_hwfn);
2591c280 555 if (rc)
fe56b9e6 556 goto alloc_err;
39651abd
SRK		 557
558 /* DCBX initialization */
559 rc = qed_dcbx_info_alloc(p_hwfn);
2591c280 560 if (rc)
39651abd 561 goto alloc_err;
fe56b9e6
YM		 562 }
563
564 cdev->reset_stats = kzalloc(sizeof(*cdev->reset_stats), GFP_KERNEL);
2591c280 565 if (!cdev->reset_stats)
83aeb933 566 goto alloc_no_mem;
fe56b9e6
YM		 567
568 return 0;
569
dbb799c3
YM		 570alloc_no_mem:
571 rc = -ENOMEM;
fe56b9e6
YM		 572alloc_err:
573 qed_resc_free(cdev);
574 return rc;
575}
576
577void qed_resc_setup(struct qed_dev *cdev)
578{
579 int i;
580
1408cc1f
YM		 581 if (IS_VF(cdev))
582 return;
583
fe56b9e6
YM		 584 for_each_hwfn(cdev, i) {
585 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
586
587 qed_cxt_mngr_setup(p_hwfn);
588 qed_spq_setup(p_hwfn);
589 qed_eq_setup(p_hwfn, p_hwfn->p_eq);
590 qed_consq_setup(p_hwfn, p_hwfn->p_consq);
591
592 /* Read shadow of current MFW mailbox */
593 qed_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
594 memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
595 p_hwfn->mcp_info->mfw_mb_cur,
596 p_hwfn->mcp_info->mfw_mb_length);
597
598 qed_int_setup(p_hwfn, p_hwfn->p_main_ptt);
32a47e72
YM		 599
600 qed_iov_setup(p_hwfn, p_hwfn->p_main_ptt);
0a7fb11c
YM		 601#ifdef CONFIG_QED_LL2
602 if (p_hwfn->using_ll2)
603 qed_ll2_setup(p_hwfn, p_hwfn->p_ll2_info);
604#endif
1d6cff4f 605 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
fc831825 606 qed_iscsi_setup(p_hwfn, p_hwfn->p_iscsi_info);
1d6cff4f
YM		 607 qed_ooo_setup(p_hwfn, p_hwfn->p_ooo_info);
608 }
fe56b9e6
YM		 609 }
610}
611
fe56b9e6
YM		 612#define FINAL_CLEANUP_POLL_CNT (100)
613#define FINAL_CLEANUP_POLL_TIME (10)
614int qed_final_cleanup(struct qed_hwfn *p_hwfn,
0b55e27d 615 struct qed_ptt *p_ptt, u16 id, bool is_vf)
fe56b9e6
YM		 616{
617 u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
618 int rc = -EBUSY;
619
fc48b7a6
YM		 620 addr = GTT_BAR0_MAP_REG_USDM_RAM +
621 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
fe56b9e6 622
0b55e27d
YM		 623 if (is_vf)
624 id += 0x10;
625
fc48b7a6
YM		 626 command |= X_FINAL_CLEANUP_AGG_INT <<
627 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
628 command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
629 command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
630 command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
fe56b9e6
YM		 631
632 /* Make sure notification is not set before initiating final cleanup */
633 if (REG_RD(p_hwfn, addr)) {
1a635e48
YM		 634 DP_NOTICE(p_hwfn,
635 "Unexpected; Found final cleanup notification before initiating final cleanup\n");
fe56b9e6
YM		 636 REG_WR(p_hwfn, addr, 0);
637 }
638
639 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
640 "Sending final cleanup for PFVF[%d] [Command %08x\n]",
641 id, command);
642
643 qed_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
644
645 /* Poll until completion */
646 while (!REG_RD(p_hwfn, addr) && count--)
647 msleep(FINAL_CLEANUP_POLL_TIME);
648
649 if (REG_RD(p_hwfn, addr))
650 rc = 0;
651 else
652 DP_NOTICE(p_hwfn,
653 "Failed to receive FW final cleanup notification\n");
654
655 /* Cleanup afterwards */
656 REG_WR(p_hwfn, addr, 0);
657
658 return rc;
659}
660
661static void qed_calc_hw_mode(struct qed_hwfn *p_hwfn)
662{
663 int hw_mode = 0;
664
12e09c69 665 hw_mode = (1 << MODE_BB_B0);
fe56b9e6
YM		 666
667 switch (p_hwfn->cdev->num_ports_in_engines) {
668 case 1:
669 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
670 break;
671 case 2:
672 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
673 break;
674 case 4:
675 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
676 break;
677 default:
678 DP_NOTICE(p_hwfn, "num_ports_in_engine = %d not supported\n",
679 p_hwfn->cdev->num_ports_in_engines);
680 return;
681 }
682
683 switch (p_hwfn->cdev->mf_mode) {
fc48b7a6
YM		 684 case QED_MF_DEFAULT:
685 case QED_MF_NPAR:
686 hw_mode |= 1 << MODE_MF_SI;
fe56b9e6 687 break;
fc48b7a6 688 case QED_MF_OVLAN:
fe56b9e6
YM		 689 hw_mode |= 1 << MODE_MF_SD;
690 break;
fe56b9e6 691 default:
fc48b7a6
YM		 692 DP_NOTICE(p_hwfn, "Unsupported MF mode, init as DEFAULT\n");
693 hw_mode |= 1 << MODE_MF_SI;
fe56b9e6
YM		 694 }
695
696 hw_mode |= 1 << MODE_ASIC;
697
1af9dcf7
YM		 698 if (p_hwfn->cdev->num_hwfns > 1)
699 hw_mode |= 1 << MODE_100G;
700
fe56b9e6 701 p_hwfn->hw_info.hw_mode = hw_mode;
1af9dcf7
YM		 702
703 DP_VERBOSE(p_hwfn, (NETIF_MSG_PROBE | NETIF_MSG_IFUP),
704 "Configuring function for hw_mode: 0x%08x\n",
705 p_hwfn->hw_info.hw_mode);
fe56b9e6
YM		 706}
707
708/* Init run time data for all PFs on an engine. */
709static void qed_init_cau_rt_data(struct qed_dev *cdev)
710{
711 u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
712 int i, sb_id;
713
714 for_each_hwfn(cdev, i) {
715 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
716 struct qed_igu_info *p_igu_info;
717 struct qed_igu_block *p_block;
718 struct cau_sb_entry sb_entry;
719
720 p_igu_info = p_hwfn->hw_info.p_igu_info;
721
722 for (sb_id = 0; sb_id < QED_MAPPING_MEMORY_SIZE(cdev);
723 sb_id++) {
724 p_block = &p_igu_info->igu_map.igu_blocks[sb_id];
725 if (!p_block->is_pf)
726 continue;
727
728 qed_init_cau_sb_entry(p_hwfn, &sb_entry,
1a635e48
YM		 729 p_block->function_id, 0, 0);
730 STORE_RT_REG_AGG(p_hwfn, offset + sb_id * 2, sb_entry);
fe56b9e6
YM		 731 }
732 }
733}
734
735static int qed_hw_init_common(struct qed_hwfn *p_hwfn,
1a635e48 736 struct qed_ptt *p_ptt, int hw_mode)
fe56b9e6
YM		 737{
738 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
739 struct qed_qm_common_rt_init_params params;
740 struct qed_dev *cdev = p_hwfn->cdev;
dbb799c3 741 u16 num_pfs, pf_id;
1408cc1f 742 u32 concrete_fid;
fe56b9e6 743 int rc = 0;
1408cc1f 744 u8 vf_id;
fe56b9e6
YM		 745
746 qed_init_cau_rt_data(cdev);
747
748 /* Program GTT windows */
749 qed_gtt_init(p_hwfn);
750
751 if (p_hwfn->mcp_info) {
752 if (p_hwfn->mcp_info->func_info.bandwidth_max)
753 qm_info->pf_rl_en = 1;
754 if (p_hwfn->mcp_info->func_info.bandwidth_min)
755 qm_info->pf_wfq_en = 1;
756 }
757
758 memset(&params, 0, sizeof(params));
759 params.max_ports_per_engine = p_hwfn->cdev->num_ports_in_engines;
760 params.max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port;
761 params.pf_rl_en = qm_info->pf_rl_en;
762 params.pf_wfq_en = qm_info->pf_wfq_en;
763 params.vport_rl_en = qm_info->vport_rl_en;
764 params.vport_wfq_en = qm_info->vport_wfq_en;
765 params.port_params = qm_info->qm_port_params;
766
767 qed_qm_common_rt_init(p_hwfn, &params);
768
769 qed_cxt_hw_init_common(p_hwfn);
770
771 /* Close gate from NIG to BRB/Storm; By default they are open, but
772 * we close them to prevent NIG from passing data to reset blocks.
773 * Should have been done in the ENGINE phase, but init-tool lacks
774 * proper port-pretend capabilities.
775 */
776 qed_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0);
777 qed_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0);
778 qed_port_pretend(p_hwfn, p_ptt, p_hwfn->port_id ^ 1);
779 qed_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0);
780 qed_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0);
781 qed_port_unpretend(p_hwfn, p_ptt);
782
783 rc = qed_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
1a635e48 784 if (rc)
fe56b9e6
YM		 785 return rc;
786
787 qed_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
788 qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
789
dbb799c3
YM		 790 if (QED_IS_BB(p_hwfn->cdev)) {
791 num_pfs = NUM_OF_ENG_PFS(p_hwfn->cdev);
792 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
793 qed_fid_pretend(p_hwfn, p_ptt, pf_id);
794 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
795 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
796 }
797 /* pretend to original PF */
798 qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
799 }
fe56b9e6 800
1408cc1f
YM		 801 for (vf_id = 0; vf_id < MAX_NUM_VFS_BB; vf_id++) {
802 concrete_fid = qed_vfid_to_concrete(p_hwfn, vf_id);
803 qed_fid_pretend(p_hwfn, p_ptt, (u16) concrete_fid);
804 qed_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
05fafbfb
YM		 805 qed_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
806 qed_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
807 qed_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
1408cc1f
YM		 808 }
809 /* pretend to original PF */
810 qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
811
fe56b9e6
YM		 812 return rc;
813}
814
51ff1725
RA		 815static int
816qed_hw_init_dpi_size(struct qed_hwfn *p_hwfn,
817 struct qed_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
818{
819 u32 dpi_page_size_1, dpi_page_size_2, dpi_page_size;
820 u32 dpi_bit_shift, dpi_count;
821 u32 min_dpis;
822
823 /* Calculate DPI size */
824 dpi_page_size_1 = QED_WID_SIZE * n_cpus;
825 dpi_page_size_2 = max_t(u32, QED_WID_SIZE, PAGE_SIZE);
826 dpi_page_size = max_t(u32, dpi_page_size_1, dpi_page_size_2);
827 dpi_page_size = roundup_pow_of_two(dpi_page_size);
828 dpi_bit_shift = ilog2(dpi_page_size / 4096);
829
830 dpi_count = pwm_region_size / dpi_page_size;
831
832 min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
833 min_dpis = max_t(u32, QED_MIN_DPIS, min_dpis);
834
835 p_hwfn->dpi_size = dpi_page_size;
836 p_hwfn->dpi_count = dpi_count;
837
838 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
839
840 if (dpi_count < min_dpis)
841 return -EINVAL;
842
843 return 0;
844}
845
846enum QED_ROCE_EDPM_MODE {
847 QED_ROCE_EDPM_MODE_ENABLE = 0,
848 QED_ROCE_EDPM_MODE_FORCE_ON = 1,
849 QED_ROCE_EDPM_MODE_DISABLE = 2,
850};
851
852static int
853qed_hw_init_pf_doorbell_bar(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
854{
855 u32 pwm_regsize, norm_regsize;
856 u32 non_pwm_conn, min_addr_reg1;
857 u32 db_bar_size, n_cpus;
858 u32 roce_edpm_mode;
859 u32 pf_dems_shift;
860 int rc = 0;
861 u8 cond;
862
863 db_bar_size = qed_hw_bar_size(p_hwfn, BAR_ID_1);
864 if (p_hwfn->cdev->num_hwfns > 1)
865 db_bar_size /= 2;
866
867 /* Calculate doorbell regions */
868 non_pwm_conn = qed_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
869 qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
870 NULL) +
871 qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH,
872 NULL);
873 norm_regsize = roundup(QED_PF_DEMS_SIZE * non_pwm_conn, 4096);
874 min_addr_reg1 = norm_regsize / 4096;
875 pwm_regsize = db_bar_size - norm_regsize;
876
877 /* Check that the normal and PWM sizes are valid */
878 if (db_bar_size < norm_regsize) {
879 DP_ERR(p_hwfn->cdev,
880 "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
881 db_bar_size, norm_regsize);
882 return -EINVAL;
883 }
884
885 if (pwm_regsize < QED_MIN_PWM_REGION) {
886 DP_ERR(p_hwfn->cdev,
887 "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
888 pwm_regsize,
889 QED_MIN_PWM_REGION, db_bar_size, norm_regsize);
890 return -EINVAL;
891 }
892
893 /* Calculate number of DPIs */
894 roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
895 if ((roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE) ||
896 ((roce_edpm_mode == QED_ROCE_EDPM_MODE_FORCE_ON))) {
897 /* Either EDPM is mandatory, or we are attempting to allocate a
898 * WID per CPU.
899 */
900 n_cpus = num_active_cpus();
901 rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
902 }
903
904 cond = (rc && (roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE)) ||
905 (roce_edpm_mode == QED_ROCE_EDPM_MODE_DISABLE);
906 if (cond || p_hwfn->dcbx_no_edpm) {
907 /* Either EDPM is disabled from user configuration, or it is
908 * disabled via DCBx, or it is not mandatory and we failed to
909 * allocated a WID per CPU.
910 */
911 n_cpus = 1;
912 rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
913
914 if (cond)
915 qed_rdma_dpm_bar(p_hwfn, p_ptt);
916 }
917
918 DP_INFO(p_hwfn,
919 "doorbell bar: normal_region_size=%d, pwm_region_size=%d, dpi_size=%d, dpi_count=%d, roce_edpm=%s\n",
920 norm_regsize,
921 pwm_regsize,
922 p_hwfn->dpi_size,
923 p_hwfn->dpi_count,
924 ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ?
925 "disabled" : "enabled");
926
927 if (rc) {
928 DP_ERR(p_hwfn,
929 "Failed to allocate enough DPIs. Allocated %d but the current minimum is %d.\n",
930 p_hwfn->dpi_count,
931 p_hwfn->pf_params.rdma_pf_params.min_dpis);
932 return -EINVAL;
933 }
934
935 p_hwfn->dpi_start_offset = norm_regsize;
936
937 /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
938 pf_dems_shift = ilog2(QED_PF_DEMS_SIZE / 4);
939 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
940 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
941
942 return 0;
943}
944
fe56b9e6 945static int qed_hw_init_port(struct qed_hwfn *p_hwfn,
1a635e48 946 struct qed_ptt *p_ptt, int hw_mode)
fe56b9e6 947{
05fafbfb
YM		 948 return qed_init_run(p_hwfn, p_ptt, PHASE_PORT,
949 p_hwfn->port_id, hw_mode);
fe56b9e6
YM		 950}
951
952static int qed_hw_init_pf(struct qed_hwfn *p_hwfn,
953 struct qed_ptt *p_ptt,
464f6645 954 struct qed_tunn_start_params *p_tunn,
fe56b9e6
YM		 955 int hw_mode,
956 bool b_hw_start,
957 enum qed_int_mode int_mode,
958 bool allow_npar_tx_switch)
959{
960 u8 rel_pf_id = p_hwfn->rel_pf_id;
961 int rc = 0;
962
963 if (p_hwfn->mcp_info) {
964 struct qed_mcp_function_info *p_info;
965
966 p_info = &p_hwfn->mcp_info->func_info;
967 if (p_info->bandwidth_min)
968 p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
969
970 /* Update rate limit once we'll actually have a link */
4b01e519 971 p_hwfn->qm_info.pf_rl = 100000;
fe56b9e6
YM		 972 }
973
974 qed_cxt_hw_init_pf(p_hwfn);
975
976 qed_int_igu_init_rt(p_hwfn);
977
978 /* Set VLAN in NIG if needed */
1a635e48 979 if (hw_mode & BIT(MODE_MF_SD)) {
fe56b9e6
YM		 980 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "Configuring LLH_FUNC_TAG\n");
981 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
982 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
983 p_hwfn->hw_info.ovlan);
984 }
985
986 /* Enable classification by MAC if needed */
1a635e48 987 if (hw_mode & BIT(MODE_MF_SI)) {
fe56b9e6
YM		 988 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
989 "Configuring TAGMAC_CLS_TYPE\n");
990 STORE_RT_REG(p_hwfn,
991 NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET, 1);
992 }
993
994 /* Protocl Configuration */
dbb799c3
YM		 995 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
996 (p_hwfn->hw_info.personality == QED_PCI_ISCSI) ? 1 : 0);
fe56b9e6
YM		 997 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET, 0);
998 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
999
1000 /* Cleanup chip from previous driver if such remains exist */
0b55e27d 1001 rc = qed_final_cleanup(p_hwfn, p_ptt, rel_pf_id, false);
1a635e48 1002 if (rc)
fe56b9e6
YM		 1003 return rc;
1004
1005 /* PF Init sequence */
1006 rc = qed_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
1007 if (rc)
1008 return rc;
1009
1010 /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
1011 rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
1012 if (rc)
1013 return rc;
1014
1015 /* Pure runtime initializations - directly to the HW */
1016 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
1017
51ff1725
RA		 1018 rc = qed_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
1019 if (rc)
1020 return rc;
1021
fe56b9e6
YM		 1022 if (b_hw_start) {
1023 /* enable interrupts */
1024 qed_int_igu_enable(p_hwfn, p_ptt, int_mode);
1025
1026 /* send function start command */
831bfb0e
YM		 1027 rc = qed_sp_pf_start(p_hwfn, p_tunn, p_hwfn->cdev->mf_mode,
1028 allow_npar_tx_switch);
fe56b9e6
YM		 1029 if (rc)
1030 DP_NOTICE(p_hwfn, "Function start ramrod failed\n");
1031 }
1032 return rc;
1033}
1034
1035static int qed_change_pci_hwfn(struct qed_hwfn *p_hwfn,
1036 struct qed_ptt *p_ptt,
1037 u8 enable)
1038{
1039 u32 delay_idx = 0, val, set_val = enable ? 1 : 0;
1040
1041 /* Change PF in PXP */
1042 qed_wr(p_hwfn, p_ptt,
1043 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
1044
1045 /* wait until value is set - try for 1 second every 50us */
1046 for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
1047 val = qed_rd(p_hwfn, p_ptt,
1048 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1049 if (val == set_val)
1050 break;
1051
1052 usleep_range(50, 60);
1053 }
1054
1055 if (val != set_val) {
1056 DP_NOTICE(p_hwfn,
1057 "PFID_ENABLE_MASTER wasn't changed after a second\n");
1058 return -EAGAIN;
1059 }
1060
1061 return 0;
1062}
1063
1064static void qed_reset_mb_shadow(struct qed_hwfn *p_hwfn,
1065 struct qed_ptt *p_main_ptt)
1066{
1067 /* Read shadow of current MFW mailbox */
1068 qed_mcp_read_mb(p_hwfn, p_main_ptt);
1069 memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
1a635e48 1070 p_hwfn->mcp_info->mfw_mb_cur, p_hwfn->mcp_info->mfw_mb_length);
fe56b9e6
YM		 1071}
1072
1073int qed_hw_init(struct qed_dev *cdev,
464f6645 1074 struct qed_tunn_start_params *p_tunn,
fe56b9e6
YM		 1075 bool b_hw_start,
1076 enum qed_int_mode int_mode,
1077 bool allow_npar_tx_switch,
1078 const u8 *bin_fw_data)
1079{
0fefbfba
SK		 1080 u32 load_code, param, drv_mb_param;
1081 bool b_default_mtu = true;
1082 struct qed_hwfn *p_hwfn;
1083 int rc = 0, mfw_rc, i;
fe56b9e6 1084
bb13ace7
SRK		 1085 if ((int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) {
1086 DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n");
1087 return -EINVAL;
1088 }
1089
1408cc1f
YM		 1090 if (IS_PF(cdev)) {
1091 rc = qed_init_fw_data(cdev, bin_fw_data);
1a635e48 1092 if (rc)
1408cc1f
YM		 1093 return rc;
1094 }
fe56b9e6
YM		 1095
1096 for_each_hwfn(cdev, i) {
1097 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1098
0fefbfba
SK		 1099 /* If management didn't provide a default, set one of our own */
1100 if (!p_hwfn->hw_info.mtu) {
1101 p_hwfn->hw_info.mtu = 1500;
1102 b_default_mtu = false;
1103 }
1104
1408cc1f
YM		 1105 if (IS_VF(cdev)) {
1106 p_hwfn->b_int_enabled = 1;
1107 continue;
1108 }
1109
fe56b9e6
YM		 1110 /* Enable DMAE in PXP */
1111 rc = qed_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true);
1112
1113 qed_calc_hw_mode(p_hwfn);
1114
1a635e48 1115 rc = qed_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt, &load_code);
fe56b9e6
YM		 1116 if (rc) {
1117 DP_NOTICE(p_hwfn, "Failed sending LOAD_REQ command\n");
1118 return rc;
1119 }
1120
1121 qed_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
1122
1123 DP_VERBOSE(p_hwfn, QED_MSG_SP,
1124 "Load request was sent. Resp:0x%x, Load code: 0x%x\n",
1125 rc, load_code);
1126
1127 p_hwfn->first_on_engine = (load_code ==
1128 FW_MSG_CODE_DRV_LOAD_ENGINE);
1129
1130 switch (load_code) {
1131 case FW_MSG_CODE_DRV_LOAD_ENGINE:
1132 rc = qed_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
1133 p_hwfn->hw_info.hw_mode);
1134 if (rc)
1135 break;
1136 /* Fall into */
1137 case FW_MSG_CODE_DRV_LOAD_PORT:
1138 rc = qed_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
1139 p_hwfn->hw_info.hw_mode);
1140 if (rc)
1141 break;
1142
1143 /* Fall into */
1144 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
1145 rc = qed_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
464f6645 1146 p_tunn, p_hwfn->hw_info.hw_mode,
fe56b9e6
YM		 1147 b_hw_start, int_mode,
1148 allow_npar_tx_switch);
1149 break;
1150 default:
1151 rc = -EINVAL;
1152 break;
1153 }
1154
1155 if (rc)
1156 DP_NOTICE(p_hwfn,
1157 "init phase failed for loadcode 0x%x (rc %d)\n",
1158 load_code, rc);
1159
1160 /* ACK mfw regardless of success or failure of initialization */
1161 mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1162 DRV_MSG_CODE_LOAD_DONE,
1163 0, &load_code, &param);
1164 if (rc)
1165 return rc;
1166 if (mfw_rc) {
1167 DP_NOTICE(p_hwfn, "Failed sending LOAD_DONE command\n");
1168 return mfw_rc;
1169 }
1170
39651abd
SRK		 1171 /* send DCBX attention request command */
1172 DP_VERBOSE(p_hwfn,
1173 QED_MSG_DCB,
1174 "sending phony dcbx set command to trigger DCBx attention handling\n");
1175 mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1176 DRV_MSG_CODE_SET_DCBX,
1177 1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT,
1178 &load_code, &param);
1179 if (mfw_rc) {
1180 DP_NOTICE(p_hwfn,
1181 "Failed to send DCBX attention request\n");
1182 return mfw_rc;
1183 }
1184
fe56b9e6
YM		 1185 p_hwfn->hw_init_done = true;
1186 }
1187
0fefbfba
SK		 1188 if (IS_PF(cdev)) {
1189 p_hwfn = QED_LEADING_HWFN(cdev);
1190 drv_mb_param = (FW_MAJOR_VERSION << 24) |
1191 (FW_MINOR_VERSION << 16) |
1192 (FW_REVISION_VERSION << 8) |
1193 (FW_ENGINEERING_VERSION);
1194 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1195 DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER,
1196 drv_mb_param, &load_code, &param);
1197 if (rc)
1198 DP_INFO(p_hwfn, "Failed to update firmware version\n");
1199
1200 if (!b_default_mtu) {
1201 rc = qed_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt,
1202 p_hwfn->hw_info.mtu);
1203 if (rc)
1204 DP_INFO(p_hwfn,
1205 "Failed to update default mtu\n");
1206 }
1207
1208 rc = qed_mcp_ov_update_driver_state(p_hwfn,
1209 p_hwfn->p_main_ptt,
1210 QED_OV_DRIVER_STATE_DISABLED);
1211 if (rc)
1212 DP_INFO(p_hwfn, "Failed to update driver state\n");
1213
1214 rc = qed_mcp_ov_update_eswitch(p_hwfn, p_hwfn->p_main_ptt,
1215 QED_OV_ESWITCH_VEB);
1216 if (rc)
1217 DP_INFO(p_hwfn, "Failed to update eswitch mode\n");
1218 }
1219
fe56b9e6
YM		 1220 return 0;
1221}
1222
1223#define QED_HW_STOP_RETRY_LIMIT (10)
1a635e48
YM		 1224static void qed_hw_timers_stop(struct qed_dev *cdev,
1225 struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
8c925c44
YM		 1226{
1227 int i;
1228
1229 /* close timers */
1230 qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
1231 qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
1232
1233 for (i = 0; i < QED_HW_STOP_RETRY_LIMIT; i++) {
1234 if ((!qed_rd(p_hwfn, p_ptt,
1235 TM_REG_PF_SCAN_ACTIVE_CONN)) &&
1a635e48 1236 (!qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
8c925c44
YM		 1237 break;
1238
1239 /* Dependent on number of connection/tasks, possibly
1240 * 1ms sleep is required between polls
1241 */
1242 usleep_range(1000, 2000);
1243 }
1244
1245 if (i < QED_HW_STOP_RETRY_LIMIT)
1246 return;
1247
1248 DP_NOTICE(p_hwfn,
1249 "Timers linear scans are not over [Connection %02x Tasks %02x]\n",
1250 (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
1251 (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
1252}
1253
1254void qed_hw_timers_stop_all(struct qed_dev *cdev)
1255{
1256 int j;
1257
1258 for_each_hwfn(cdev, j) {
1259 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
1260 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt;
1261
1262 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
1263 }
1264}
1265
fe56b9e6
YM		 1266int qed_hw_stop(struct qed_dev *cdev)
1267{
1268 int rc = 0, t_rc;
8c925c44 1269 int j;
fe56b9e6
YM		 1270
1271 for_each_hwfn(cdev, j) {
1272 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
1273 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt;
1274
1275 DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Stopping hw/fw\n");
1276
1408cc1f 1277 if (IS_VF(cdev)) {
0b55e27d 1278 qed_vf_pf_int_cleanup(p_hwfn);
1408cc1f
YM		 1279 continue;
1280 }
1281
fe56b9e6
YM		 1282 /* mark the hw as uninitialized... */
1283 p_hwfn->hw_init_done = false;
1284
1285 rc = qed_sp_pf_stop(p_hwfn);
1286 if (rc)
8c925c44
YM		 1287 DP_NOTICE(p_hwfn,
1288 "Failed to close PF against FW. Continue to stop HW to prevent illegal host access by the device\n");
fe56b9e6
YM		 1289
1290 qed_wr(p_hwfn, p_ptt,
1291 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1292
1293 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1294 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1295 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
1296 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1297 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1298
8c925c44 1299 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
fe56b9e6
YM		 1300
1301 /* Disable Attention Generation */
1302 qed_int_igu_disable_int(p_hwfn, p_ptt);
1303
1304 qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
1305 qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
1306
1307 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
1308
1309 /* Need to wait 1ms to guarantee SBs are cleared */
1310 usleep_range(1000, 2000);
1311 }
1312
1408cc1f
YM		 1313 if (IS_PF(cdev)) {
1314 /* Disable DMAE in PXP - in CMT, this should only be done for
1315 * first hw-function, and only after all transactions have
1316 * stopped for all active hw-functions.
1317 */
1318 t_rc = qed_change_pci_hwfn(&cdev->hwfns[0],
1319 cdev->hwfns[0].p_main_ptt, false);
1320 if (t_rc != 0)
1321 rc = t_rc;
1322 }
fe56b9e6
YM		 1323
1324 return rc;
1325}
1326
cee4d264
MC		 1327void qed_hw_stop_fastpath(struct qed_dev *cdev)
1328{
8c925c44 1329 int j;
cee4d264
MC		 1330
1331 for_each_hwfn(cdev, j) {
1332 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
dacd88d6
YM		 1333 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt;
1334
1335 if (IS_VF(cdev)) {
1336 qed_vf_pf_int_cleanup(p_hwfn);
1337 continue;
1338 }
cee4d264
MC		 1339
1340 DP_VERBOSE(p_hwfn,
1a635e48 1341 NETIF_MSG_IFDOWN, "Shutting down the fastpath\n");
cee4d264
MC		 1342
1343 qed_wr(p_hwfn, p_ptt,
1344 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1345
1346 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1347 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1348 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
1349 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1350 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1351
cee4d264
MC		 1352 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
1353
1354 /* Need to wait 1ms to guarantee SBs are cleared */
1355 usleep_range(1000, 2000);
1356 }
1357}
1358
1359void qed_hw_start_fastpath(struct qed_hwfn *p_hwfn)
1360{
dacd88d6
YM		 1361 if (IS_VF(p_hwfn->cdev))
1362 return;
1363
cee4d264
MC		 1364 /* Re-open incoming traffic */
1365 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1366 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
1367}
1368
1a635e48
YM		 1369static int qed_reg_assert(struct qed_hwfn *p_hwfn,
1370 struct qed_ptt *p_ptt, u32 reg, bool expected)
fe56b9e6 1371{
1a635e48 1372 u32 assert_val = qed_rd(p_hwfn, p_ptt, reg);
fe56b9e6
YM		 1373
1374 if (assert_val != expected) {
525ef5c0 1375 DP_NOTICE(p_hwfn, "Value at address 0x%08x != 0x%08x\n",
fe56b9e6
YM		 1376 reg, expected);
1377 return -EINVAL;
1378 }
1379
1380 return 0;
1381}
1382
1383int qed_hw_reset(struct qed_dev *cdev)
1384{
1385 int rc = 0;
1386 u32 unload_resp, unload_param;
14d39648 1387 u32 wol_param;
fe56b9e6
YM		 1388 int i;
1389
14d39648
MY		 1390 switch (cdev->wol_config) {
1391 case QED_OV_WOL_DISABLED:
1392 wol_param = DRV_MB_PARAM_UNLOAD_WOL_DISABLED;
1393 break;
1394 case QED_OV_WOL_ENABLED:
1395 wol_param = DRV_MB_PARAM_UNLOAD_WOL_ENABLED;
1396 break;
1397 default:
1398 DP_NOTICE(cdev,
1399 "Unknown WoL configuration %02x\n", cdev->wol_config);
1400 /* Fallthrough */
1401 case QED_OV_WOL_DEFAULT:
1402 wol_param = DRV_MB_PARAM_UNLOAD_WOL_MCP;
1403 }
1404
fe56b9e6
YM		 1405 for_each_hwfn(cdev, i) {
1406 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1407
1408cc1f 1408 if (IS_VF(cdev)) {
0b55e27d
YM		 1409 rc = qed_vf_pf_reset(p_hwfn);
1410 if (rc)
1411 return rc;
1408cc1f
YM		 1412 continue;
1413 }
1414
fe56b9e6
YM		 1415 DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Resetting hw/fw\n");
1416
1417 /* Check for incorrect states */
1418 qed_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
1419 QM_REG_USG_CNT_PF_TX, 0);
1420 qed_reg_assert(p_hwfn, p_hwfn->p_main_ptt,
1421 QM_REG_USG_CNT_PF_OTHER, 0);
1422
1423 /* Disable PF in HW blocks */
1424 qed_wr(p_hwfn, p_hwfn->p_main_ptt, DORQ_REG_PF_DB_ENABLE, 0);
1425 qed_wr(p_hwfn, p_hwfn->p_main_ptt, QM_REG_PF_EN, 0);
1426 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1427 TCFC_REG_STRONG_ENABLE_PF, 0);
1428 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1429 CCFC_REG_STRONG_ENABLE_PF, 0);
1430
1431 /* Send unload command to MCP */
1432 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
14d39648 1433 DRV_MSG_CODE_UNLOAD_REQ, wol_param,
fe56b9e6
YM		 1434 &unload_resp, &unload_param);
1435 if (rc) {
1436 DP_NOTICE(p_hwfn, "qed_hw_reset: UNLOAD_REQ failed\n");
1437 unload_resp = FW_MSG_CODE_DRV_UNLOAD_ENGINE;
1438 }
1439
1440 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1441 DRV_MSG_CODE_UNLOAD_DONE,
1442 0, &unload_resp, &unload_param);
1443 if (rc) {
1444 DP_NOTICE(p_hwfn, "qed_hw_reset: UNLOAD_DONE failed\n");
1445 return rc;
1446 }
1447 }
1448
1449 return rc;
1450}
1451
1452/* Free hwfn memory and resources acquired in hw_hwfn_prepare */
1453static void qed_hw_hwfn_free(struct qed_hwfn *p_hwfn)
1454{
1455 qed_ptt_pool_free(p_hwfn);
1456 kfree(p_hwfn->hw_info.p_igu_info);
1457}
1458
1459/* Setup bar access */
12e09c69 1460static void qed_hw_hwfn_prepare(struct qed_hwfn *p_hwfn)
fe56b9e6 1461{
fe56b9e6
YM		 1462 /* clear indirect access */
1463 qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_88_F0, 0);
1464 qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_8C_F0, 0);
1465 qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_90_F0, 0);
1466 qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_94_F0, 0);
1467
1468 /* Clean Previous errors if such exist */
1469 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1a635e48 1470 PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, 1 << p_hwfn->abs_pf_id);
fe56b9e6
YM		 1471
1472 /* enable internal target-read */
1473 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
1474 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
fe56b9e6
YM		 1475}
1476
1477static void get_function_id(struct qed_hwfn *p_hwfn)
1478{
1479 /* ME Register */
1a635e48
YM		 1480 p_hwfn->hw_info.opaque_fid = (u16) REG_RD(p_hwfn,
1481 PXP_PF_ME_OPAQUE_ADDR);
fe56b9e6
YM		 1482
1483 p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
1484
1485 p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
1486 p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
1487 PXP_CONCRETE_FID_PFID);
1488 p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
1489 PXP_CONCRETE_FID_PORT);
525ef5c0
YM		 1490
1491 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE,
1492 "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
1493 p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
fe56b9e6
YM		 1494}
1495
25c089d7
YM		 1496static void qed_hw_set_feat(struct qed_hwfn *p_hwfn)
1497{
1498 u32 *feat_num = p_hwfn->hw_info.feat_num;
5a1f965a 1499 struct qed_sb_cnt_info sb_cnt_info;
25c089d7
YM		 1500 int num_features = 1;
1501
0189efb8
YM		 1502 if (IS_ENABLED(CONFIG_QED_RDMA) &&
1503 p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE) {
1504 /* Roce CNQ each requires: 1 status block + 1 CNQ. We divide
1505 * the status blocks equally between L2 / RoCE but with
1506 * consideration as to how many l2 queues / cnqs we have.
1507 */
51ff1725
RA		 1508 num_features++;
1509
1510 feat_num[QED_RDMA_CNQ] =
1511 min_t(u32, RESC_NUM(p_hwfn, QED_SB) / num_features,
1512 RESC_NUM(p_hwfn, QED_RDMA_CNQ_RAM));
1513 }
0189efb8 1514
25c089d7
YM		 1515 feat_num[QED_PF_L2_QUE] = min_t(u32, RESC_NUM(p_hwfn, QED_SB) /
1516 num_features,
1517 RESC_NUM(p_hwfn, QED_L2_QUEUE));
5a1f965a
MY		 1518
1519 memset(&sb_cnt_info, 0, sizeof(sb_cnt_info));
1520 qed_int_get_num_sbs(p_hwfn, &sb_cnt_info);
1521 feat_num[QED_VF_L2_QUE] =
1522 min_t(u32,
1523 RESC_NUM(p_hwfn, QED_L2_QUEUE) -
1524 FEAT_NUM(p_hwfn, QED_PF_L2_QUE), sb_cnt_info.sb_iov_cnt);
1525
1526 DP_VERBOSE(p_hwfn,
1527 NETIF_MSG_PROBE,
1528 "#PF_L2_QUEUES=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d #SBS=%d num_features=%d\n",
1529 (int)FEAT_NUM(p_hwfn, QED_PF_L2_QUE),
1530 (int)FEAT_NUM(p_hwfn, QED_VF_L2_QUE),
1531 (int)FEAT_NUM(p_hwfn, QED_RDMA_CNQ),
1532 RESC_NUM(p_hwfn, QED_SB), num_features);
25c089d7
YM		 1533}
1534
2edbff8d
TT		 1535static enum resource_id_enum qed_hw_get_mfw_res_id(enum qed_resources res_id)
1536{
1537 enum resource_id_enum mfw_res_id = RESOURCE_NUM_INVALID;
1538
1539 switch (res_id) {
1540 case QED_SB:
1541 mfw_res_id = RESOURCE_NUM_SB_E;
1542 break;
1543 case QED_L2_QUEUE:
1544 mfw_res_id = RESOURCE_NUM_L2_QUEUE_E;
1545 break;
1546 case QED_VPORT:
1547 mfw_res_id = RESOURCE_NUM_VPORT_E;
1548 break;
1549 case QED_RSS_ENG:
1550 mfw_res_id = RESOURCE_NUM_RSS_ENGINES_E;
1551 break;
1552 case QED_PQ:
1553 mfw_res_id = RESOURCE_NUM_PQ_E;
1554 break;
1555 case QED_RL:
1556 mfw_res_id = RESOURCE_NUM_RL_E;
1557 break;
1558 case QED_MAC:
1559 case QED_VLAN:
1560 /* Each VFC resource can accommodate both a MAC and a VLAN */
1561 mfw_res_id = RESOURCE_VFC_FILTER_E;
1562 break;
1563 case QED_ILT:
1564 mfw_res_id = RESOURCE_ILT_E;
1565 break;
1566 case QED_LL2_QUEUE:
1567 mfw_res_id = RESOURCE_LL2_QUEUE_E;
1568 break;
1569 case QED_RDMA_CNQ_RAM:
1570 case QED_CMDQS_CQS:
1571 /* CNQ/CMDQS are the same resource */
1572 mfw_res_id = RESOURCE_CQS_E;
1573 break;
1574 case QED_RDMA_STATS_QUEUE:
1575 mfw_res_id = RESOURCE_RDMA_STATS_QUEUE_E;
1576 break;
1577 default:
1578 break;
1579 }
1580
1581 return mfw_res_id;
1582}
1583
1584static u32 qed_hw_get_dflt_resc_num(struct qed_hwfn *p_hwfn,
1585 enum qed_resources res_id)
fe56b9e6 1586{
1408cc1f 1587 u8 num_funcs = p_hwfn->num_funcs_on_engine;
4ac801b7 1588 struct qed_sb_cnt_info sb_cnt_info;
2edbff8d 1589 u32 dflt_resc_num = 0;
fe56b9e6 1590
2edbff8d
TT		 1591 switch (res_id) {
1592 case QED_SB:
1593 memset(&sb_cnt_info, 0, sizeof(sb_cnt_info));
1594 qed_int_get_num_sbs(p_hwfn, &sb_cnt_info);
1595 dflt_resc_num = sb_cnt_info.sb_cnt;
1596 break;
1597 case QED_L2_QUEUE:
1598 dflt_resc_num = MAX_NUM_L2_QUEUES_BB / num_funcs;
1599 break;
1600 case QED_VPORT:
1601 dflt_resc_num = MAX_NUM_VPORTS_BB / num_funcs;
1602 break;
1603 case QED_RSS_ENG:
1604 dflt_resc_num = ETH_RSS_ENGINE_NUM_BB / num_funcs;
1605 break;
1606 case QED_PQ:
1607 /* The granularity of the PQs is 8 */
1608 dflt_resc_num = MAX_QM_TX_QUEUES_BB / num_funcs;
1609 dflt_resc_num &= ~0x7;
1610 break;
1611 case QED_RL:
1612 dflt_resc_num = MAX_QM_GLOBAL_RLS / num_funcs;
1613 break;
1614 case QED_MAC:
1615 case QED_VLAN:
1616 /* Each VFC resource can accommodate both a MAC and a VLAN */
1617 dflt_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
1618 break;
1619 case QED_ILT:
1620 dflt_resc_num = PXP_NUM_ILT_RECORDS_BB / num_funcs;
1621 break;
1622 case QED_LL2_QUEUE:
1623 dflt_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
1624 break;
1625 case QED_RDMA_CNQ_RAM:
1626 case QED_CMDQS_CQS:
1627 /* CNQ/CMDQS are the same resource */
1628 dflt_resc_num = NUM_OF_CMDQS_CQS / num_funcs;
1629 break;
1630 case QED_RDMA_STATS_QUEUE:
1631 dflt_resc_num = RDMA_NUM_STATISTIC_COUNTERS_BB / num_funcs;
1632 break;
1633 default:
1634 break;
1635 }
08feecd7 1636
2edbff8d
TT		 1637 return dflt_resc_num;
1638}
08feecd7 1639
2edbff8d
TT		 1640static const char *qed_hw_get_resc_name(enum qed_resources res_id)
1641{
1642 switch (res_id) {
1643 case QED_SB:
1644 return "SB";
1645 case QED_L2_QUEUE:
1646 return "L2_QUEUE";
1647 case QED_VPORT:
1648 return "VPORT";
1649 case QED_RSS_ENG:
1650 return "RSS_ENG";
1651 case QED_PQ:
1652 return "PQ";
1653 case QED_RL:
1654 return "RL";
1655 case QED_MAC:
1656 return "MAC";
1657 case QED_VLAN:
1658 return "VLAN";
1659 case QED_RDMA_CNQ_RAM:
1660 return "RDMA_CNQ_RAM";
1661 case QED_ILT:
1662 return "ILT";
1663 case QED_LL2_QUEUE:
1664 return "LL2_QUEUE";
1665 case QED_CMDQS_CQS:
1666 return "CMDQS_CQS";
1667 case QED_RDMA_STATS_QUEUE:
1668 return "RDMA_STATS_QUEUE";
1669 default:
1670 return "UNKNOWN_RESOURCE";
1671 }
1672}
1673
1674static int qed_hw_set_resc_info(struct qed_hwfn *p_hwfn,
1675 enum qed_resources res_id)
1676{
1677 u32 dflt_resc_num = 0, dflt_resc_start = 0, mcp_resp, mcp_param;
1678 u32 *p_resc_num, *p_resc_start;
1679 struct resource_info resc_info;
1680 int rc;
1681
1682 p_resc_num = &RESC_NUM(p_hwfn, res_id);
1683 p_resc_start = &RESC_START(p_hwfn, res_id);
1684
1685 /* Default values assumes that each function received equal share */
1686 dflt_resc_num = qed_hw_get_dflt_resc_num(p_hwfn, res_id);
1687 if (!dflt_resc_num) {
1688 DP_ERR(p_hwfn,
1689 "Failed to get default amount for resource %d [%s]\n",
1690 res_id, qed_hw_get_resc_name(res_id));
1691 return -EINVAL;
1692 }
1693 dflt_resc_start = dflt_resc_num * p_hwfn->enabled_func_idx;
1694
1695 memset(&resc_info, 0, sizeof(resc_info));
1696 resc_info.res_id = qed_hw_get_mfw_res_id(res_id);
1697 if (resc_info.res_id == RESOURCE_NUM_INVALID) {
1698 DP_ERR(p_hwfn,
1699 "Failed to match resource %d [%s] with the MFW resources\n",
1700 res_id, qed_hw_get_resc_name(res_id));
1701 return -EINVAL;
1702 }
1703
1704 rc = qed_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, &resc_info,
1705 &mcp_resp, &mcp_param);
1706 if (rc) {
1707 DP_NOTICE(p_hwfn,
1708 "MFW response failure for an allocation request for resource %d [%s]\n",
1709 res_id, qed_hw_get_resc_name(res_id));
1710 return rc;
1711 }
1712
1713 /* Default driver values are applied in the following cases:
1714 * - The resource allocation MB command is not supported by the MFW
1715 * - There is an internal error in the MFW while processing the request
1716 * - The resource ID is unknown to the MFW
1717 */
1718 if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK &&
1719 mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_DEPRECATED) {
1720 DP_NOTICE(p_hwfn,
1721 "Resource %d [%s]: No allocation info was received [mcp_resp 0x%x]. Applying default values [num %d, start %d].\n",
1722 res_id,
1723 qed_hw_get_resc_name(res_id),
1724 mcp_resp, dflt_resc_num, dflt_resc_start);
1725 *p_resc_num = dflt_resc_num;
1726 *p_resc_start = dflt_resc_start;
1727 goto out;
1728 }
1729
1730 /* Special handling for status blocks; Would be revised in future */
1731 if (res_id == QED_SB) {
1732 resc_info.size -= 1;
1733 resc_info.offset -= p_hwfn->enabled_func_idx;
1734 }
1735
1736 *p_resc_num = resc_info.size;
1737 *p_resc_start = resc_info.offset;
1738
1739out:
1740 /* PQs have to divide by 8 [that's the HW granularity].
1741 * Reduce number so it would fit.
1742 */
1743 if ((res_id == QED_PQ) && ((*p_resc_num % 8) || (*p_resc_start % 8))) {
1744 DP_INFO(p_hwfn,
1745 "PQs need to align by 8; Number %08x --> %08x, Start %08x --> %08x\n",
1746 *p_resc_num,
1747 (*p_resc_num) & ~0x7,
1748 *p_resc_start, (*p_resc_start) & ~0x7);
1749 *p_resc_num &= ~0x7;
1750 *p_resc_start &= ~0x7;
1751 }
4ac801b7 1752
2edbff8d
TT		 1753 return 0;
1754}
1755
1756static int qed_hw_get_resc(struct qed_hwfn *p_hwfn)
1757{
1758 u8 res_id;
1759 int rc;
1760
1761 for (res_id = 0; res_id < QED_MAX_RESC; res_id++) {
1762 rc = qed_hw_set_resc_info(p_hwfn, res_id);
1763 if (rc)
1764 return rc;
1765 }
dbb799c3
YM		 1766
1767 /* Sanity for ILT */
2edbff8d 1768 if ((RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_BB)) {
dbb799c3
YM		 1769 DP_NOTICE(p_hwfn, "Can't assign ILT pages [%08x,...,%08x]\n",
1770 RESC_START(p_hwfn, QED_ILT),
1771 RESC_END(p_hwfn, QED_ILT) - 1);
1772 return -EINVAL;
1773 }
fe56b9e6 1774
25c089d7
YM		 1775 qed_hw_set_feat(p_hwfn);
1776
fe56b9e6 1777 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE,
2edbff8d
TT		 1778 "The numbers for each resource are:\n");
1779 for (res_id = 0; res_id < QED_MAX_RESC; res_id++)
1780 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE, "%s = %d start = %d\n",
1781 qed_hw_get_resc_name(res_id),
1782 RESC_NUM(p_hwfn, res_id),
1783 RESC_START(p_hwfn, res_id));
dbb799c3
YM		 1784
1785 return 0;
fe56b9e6
YM		 1786}
1787
1a635e48 1788static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
fe56b9e6 1789{
cc875c2e 1790 u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg;
fc48b7a6 1791 u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
cc875c2e 1792 struct qed_mcp_link_params *link;
fe56b9e6
YM		 1793
1794 /* Read global nvm_cfg address */
1795 nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
1796
1797 /* Verify MCP has initialized it */
1798 if (!nvm_cfg_addr) {
1799 DP_NOTICE(p_hwfn, "Shared memory not initialized\n");
1800 return -EINVAL;
1801 }
1802
1803 /* Read nvm_cfg1 (Notice this is just offset, and not offsize (TBD) */
1804 nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
1805
cc875c2e
YM		 1806 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1807 offsetof(struct nvm_cfg1, glob) +
1808 offsetof(struct nvm_cfg1_glob, core_cfg);
1809
1810 core_cfg = qed_rd(p_hwfn, p_ptt, addr);
1811
1812 switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
1813 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
351a4ded 1814 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
cc875c2e
YM		 1815 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X40G;
1816 break;
351a4ded 1817 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
cc875c2e
YM		 1818 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X50G;
1819 break;
351a4ded 1820 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
cc875c2e
YM		 1821 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X100G;
1822 break;
351a4ded 1823 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
cc875c2e
YM		 1824 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_F;
1825 break;
351a4ded 1826 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
cc875c2e
YM		 1827 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_E;
1828 break;
351a4ded 1829 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
cc875c2e
YM		 1830 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X20G;
1831 break;
351a4ded 1832 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
cc875c2e
YM		 1833 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X40G;
1834 break;
351a4ded 1835 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
cc875c2e
YM		 1836 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X25G;
1837 break;
351a4ded 1838 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
cc875c2e
YM		 1839 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X25G;
1840 break;
1841 default:
1a635e48 1842 DP_NOTICE(p_hwfn, "Unknown port mode in 0x%08x\n", core_cfg);
cc875c2e
YM		 1843 break;
1844 }
1845
cc875c2e
YM		 1846 /* Read default link configuration */
1847 link = &p_hwfn->mcp_info->link_input;
1848 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1849 offsetof(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
1850 link_temp = qed_rd(p_hwfn, p_ptt,
1851 port_cfg_addr +
1852 offsetof(struct nvm_cfg1_port, speed_cap_mask));
83aeb933
YM		 1853 link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
1854 link->speed.advertised_speeds = link_temp;
cc875c2e 1855
83aeb933
YM		 1856 link_temp = link->speed.advertised_speeds;
1857 p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp;
cc875c2e
YM		 1858
1859 link_temp = qed_rd(p_hwfn, p_ptt,
1860 port_cfg_addr +
1861 offsetof(struct nvm_cfg1_port, link_settings));
1862 switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
1863 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
1864 case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
1865 link->speed.autoneg = true;
1866 break;
1867 case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
1868 link->speed.forced_speed = 1000;
1869 break;
1870 case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
1871 link->speed.forced_speed = 10000;
1872 break;
1873 case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
1874 link->speed.forced_speed = 25000;
1875 break;
1876 case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
1877 link->speed.forced_speed = 40000;
1878 break;
1879 case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
1880 link->speed.forced_speed = 50000;
1881 break;
351a4ded 1882 case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
cc875c2e
YM		 1883 link->speed.forced_speed = 100000;
1884 break;
1885 default:
1a635e48 1886 DP_NOTICE(p_hwfn, "Unknown Speed in 0x%08x\n", link_temp);
cc875c2e
YM		 1887 }
1888
1889 link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
1890 link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
1891 link->pause.autoneg = !!(link_temp &
1892 NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
1893 link->pause.forced_rx = !!(link_temp &
1894 NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
1895 link->pause.forced_tx = !!(link_temp &
1896 NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
1897 link->loopback_mode = 0;
1898
1899 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
1900 "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n",
1901 link->speed.forced_speed, link->speed.advertised_speeds,
1902 link->speed.autoneg, link->pause.autoneg);
1903
fe56b9e6
YM		 1904 /* Read Multi-function information from shmem */
1905 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1906 offsetof(struct nvm_cfg1, glob) +
1907 offsetof(struct nvm_cfg1_glob, generic_cont0);
1908
1909 generic_cont0 = qed_rd(p_hwfn, p_ptt, addr);
1910
1911 mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
1912 NVM_CFG1_GLOB_MF_MODE_OFFSET;
1913
1914 switch (mf_mode) {
1915 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
fc48b7a6 1916 p_hwfn->cdev->mf_mode = QED_MF_OVLAN;
fe56b9e6
YM		 1917 break;
1918 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
fc48b7a6 1919 p_hwfn->cdev->mf_mode = QED_MF_NPAR;
fe56b9e6 1920 break;
fc48b7a6
YM		 1921 case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
1922 p_hwfn->cdev->mf_mode = QED_MF_DEFAULT;
fe56b9e6
YM		 1923 break;
1924 }
1925 DP_INFO(p_hwfn, "Multi function mode is %08x\n",
1926 p_hwfn->cdev->mf_mode);
1927
fc48b7a6
YM		 1928 /* Read Multi-function information from shmem */
1929 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1930 offsetof(struct nvm_cfg1, glob) +
1931 offsetof(struct nvm_cfg1_glob, device_capabilities);
1932
1933 device_capabilities = qed_rd(p_hwfn, p_ptt, addr);
1934 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
1935 __set_bit(QED_DEV_CAP_ETH,
1936 &p_hwfn->hw_info.device_capabilities);
c5ac9319
YM		 1937 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
1938 __set_bit(QED_DEV_CAP_ISCSI,
1939 &p_hwfn->hw_info.device_capabilities);
1940 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
1941 __set_bit(QED_DEV_CAP_ROCE,
1942 &p_hwfn->hw_info.device_capabilities);
fc48b7a6 1943
fe56b9e6
YM		 1944 return qed_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
1945}
1946
1408cc1f
YM		 1947static void qed_get_num_funcs(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1948{
dbb799c3
YM		 1949 u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
1950 u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
1408cc1f
YM		 1951
1952 num_funcs = MAX_NUM_PFS_BB;
1953
1954 /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
1955 * in the other bits are selected.
1956 * Bits 1-15 are for functions 1-15, respectively, and their value is
1957 * '0' only for enabled functions (function 0 always exists and
1958 * enabled).
1959 * In case of CMT, only the "even" functions are enabled, and thus the
1960 * number of functions for both hwfns is learnt from the same bits.
1961 */
1962 reg_function_hide = qed_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE);
1963
1964 if (reg_function_hide & 0x1) {
1965 if (QED_PATH_ID(p_hwfn) && p_hwfn->cdev->num_hwfns == 1) {
1966 num_funcs = 0;
1967 eng_mask = 0xaaaa;
1968 } else {
1969 num_funcs = 1;
1970 eng_mask = 0x5554;
1971 }
1972
1973 /* Get the number of the enabled functions on the engine */
1974 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
1975 while (tmp) {
1976 if (tmp & 0x1)
1977 num_funcs++;
1978 tmp >>= 0x1;
1979 }
dbb799c3
YM		 1980
1981 /* Get the PF index within the enabled functions */
1982 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
1983 tmp = reg_function_hide & eng_mask & low_pfs_mask;
1984 while (tmp) {
1985 if (tmp & 0x1)
1986 enabled_func_idx--;
1987 tmp >>= 0x1;
1988 }
1408cc1f
YM		 1989 }
1990
1991 p_hwfn->num_funcs_on_engine = num_funcs;
dbb799c3 1992 p_hwfn->enabled_func_idx = enabled_func_idx;
1408cc1f
YM		 1993
1994 DP_VERBOSE(p_hwfn,
1995 NETIF_MSG_PROBE,
525ef5c0 1996 "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
1408cc1f
YM		 1997 p_hwfn->rel_pf_id,
1998 p_hwfn->abs_pf_id,
525ef5c0 1999 p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
1408cc1f
YM		 2000}
2001
fe56b9e6
YM		 2002static int
2003qed_get_hw_info(struct qed_hwfn *p_hwfn,
2004 struct qed_ptt *p_ptt,
2005 enum qed_pci_personality personality)
2006{
2007 u32 port_mode;
2008 int rc;
2009
32a47e72
YM		 2010 /* Since all information is common, only first hwfns should do this */
2011 if (IS_LEAD_HWFN(p_hwfn)) {
2012 rc = qed_iov_hw_info(p_hwfn);
2013 if (rc)
2014 return rc;
2015 }
2016
fe56b9e6
YM		 2017 /* Read the port mode */
2018 port_mode = qed_rd(p_hwfn, p_ptt,
2019 CNIG_REG_NW_PORT_MODE_BB_B0);
2020
2021 if (port_mode < 3) {
2022 p_hwfn->cdev->num_ports_in_engines = 1;
2023 } else if (port_mode <= 5) {
2024 p_hwfn->cdev->num_ports_in_engines = 2;
2025 } else {
2026 DP_NOTICE(p_hwfn, "PORT MODE: %d not supported\n",
2027 p_hwfn->cdev->num_ports_in_engines);
2028
2029 /* Default num_ports_in_engines to something */
2030 p_hwfn->cdev->num_ports_in_engines = 1;
2031 }
2032
2033 qed_hw_get_nvm_info(p_hwfn, p_ptt);
2034
2035 rc = qed_int_igu_read_cam(p_hwfn, p_ptt);
2036 if (rc)
2037 return rc;
2038
2039 if (qed_mcp_is_init(p_hwfn))
2040 ether_addr_copy(p_hwfn->hw_info.hw_mac_addr,
2041 p_hwfn->mcp_info->func_info.mac);
2042 else
2043 eth_random_addr(p_hwfn->hw_info.hw_mac_addr);
2044
2045 if (qed_mcp_is_init(p_hwfn)) {
2046 if (p_hwfn->mcp_info->func_info.ovlan != QED_MCP_VLAN_UNSET)
2047 p_hwfn->hw_info.ovlan =
2048 p_hwfn->mcp_info->func_info.ovlan;
2049
2050 qed_mcp_cmd_port_init(p_hwfn, p_ptt);
2051 }
2052
2053 if (qed_mcp_is_init(p_hwfn)) {
2054 enum qed_pci_personality protocol;
2055
2056 protocol = p_hwfn->mcp_info->func_info.protocol;
2057 p_hwfn->hw_info.personality = protocol;
2058 }
2059
1408cc1f
YM		 2060 qed_get_num_funcs(p_hwfn, p_ptt);
2061
0fefbfba
SK		 2062 if (qed_mcp_is_init(p_hwfn))
2063 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu;
2064
dbb799c3 2065 return qed_hw_get_resc(p_hwfn);
fe56b9e6
YM		 2066}
2067
12e09c69 2068static int qed_get_dev_info(struct qed_dev *cdev)
fe56b9e6 2069{
fc48b7a6 2070 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
fe56b9e6
YM		 2071 u32 tmp;
2072
fc48b7a6 2073 /* Read Vendor Id / Device Id */
1a635e48
YM		 2074 pci_read_config_word(cdev->pdev, PCI_VENDOR_ID, &cdev->vendor_id);
2075 pci_read_config_word(cdev->pdev, PCI_DEVICE_ID, &cdev->device_id);
2076
fc48b7a6 2077 cdev->chip_num = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt,
fe56b9e6 2078 MISCS_REG_CHIP_NUM);
fc48b7a6 2079 cdev->chip_rev = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt,
fe56b9e6
YM		 2080 MISCS_REG_CHIP_REV);
2081 MASK_FIELD(CHIP_REV, cdev->chip_rev);
2082
fc48b7a6 2083 cdev->type = QED_DEV_TYPE_BB;
fe56b9e6 2084 /* Learn number of HW-functions */
fc48b7a6 2085 tmp = qed_rd(p_hwfn, p_hwfn->p_main_ptt,
fe56b9e6
YM		 2086 MISCS_REG_CMT_ENABLED_FOR_PAIR);
2087
fc48b7a6 2088 if (tmp & (1 << p_hwfn->rel_pf_id)) {
fe56b9e6
YM		 2089 DP_NOTICE(cdev->hwfns, "device in CMT mode\n");
2090 cdev->num_hwfns = 2;
2091 } else {
2092 cdev->num_hwfns = 1;
2093 }
2094
fc48b7a6 2095 cdev->chip_bond_id = qed_rd(p_hwfn, p_hwfn->p_main_ptt,
fe56b9e6
YM		 2096 MISCS_REG_CHIP_TEST_REG) >> 4;
2097 MASK_FIELD(CHIP_BOND_ID, cdev->chip_bond_id);
fc48b7a6 2098 cdev->chip_metal = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt,
fe56b9e6
YM		 2099 MISCS_REG_CHIP_METAL);
2100 MASK_FIELD(CHIP_METAL, cdev->chip_metal);
2101
2102 DP_INFO(cdev->hwfns,
2103 "Chip details - Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
2104 cdev->chip_num, cdev->chip_rev,
2105 cdev->chip_bond_id, cdev->chip_metal);
12e09c69
YM		 2106
2107 if (QED_IS_BB(cdev) && CHIP_REV_IS_A0(cdev)) {
2108 DP_NOTICE(cdev->hwfns,
2109 "The chip type/rev (BB A0) is not supported!\n");
2110 return -EINVAL;
2111 }
2112
2113 return 0;
fe56b9e6
YM		 2114}
2115
2116static int qed_hw_prepare_single(struct qed_hwfn *p_hwfn,
2117 void __iomem *p_regview,
2118 void __iomem *p_doorbells,
2119 enum qed_pci_personality personality)
2120{
2121 int rc = 0;
2122
2123 /* Split PCI bars evenly between hwfns */
2124 p_hwfn->regview = p_regview;
2125 p_hwfn->doorbells = p_doorbells;
2126
1408cc1f
YM		 2127 if (IS_VF(p_hwfn->cdev))
2128 return qed_vf_hw_prepare(p_hwfn);
2129
fe56b9e6
YM		 2130 /* Validate that chip access is feasible */
2131 if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
2132 DP_ERR(p_hwfn,
2133 "Reading the ME register returns all Fs; Preventing further chip access\n");
2134 return -EINVAL;
2135 }
2136
2137 get_function_id(p_hwfn);
2138
12e09c69
YM		 2139 /* Allocate PTT pool */
2140 rc = qed_ptt_pool_alloc(p_hwfn);
2591c280 2141 if (rc)
fe56b9e6 2142 goto err0;
fe56b9e6 2143
12e09c69
YM		 2144 /* Allocate the main PTT */
2145 p_hwfn->p_main_ptt = qed_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
2146
fe56b9e6 2147 /* First hwfn learns basic information, e.g., number of hwfns */
12e09c69
YM		 2148 if (!p_hwfn->my_id) {
2149 rc = qed_get_dev_info(p_hwfn->cdev);
1a635e48 2150 if (rc)
12e09c69
YM		 2151 goto err1;
2152 }
2153
2154 qed_hw_hwfn_prepare(p_hwfn);
fe56b9e6
YM		 2155
2156 /* Initialize MCP structure */
2157 rc = qed_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
2158 if (rc) {
2159 DP_NOTICE(p_hwfn, "Failed initializing mcp command\n");
2160 goto err1;
2161 }
2162
2163 /* Read the device configuration information from the HW and SHMEM */
2164 rc = qed_get_hw_info(p_hwfn, p_hwfn->p_main_ptt, personality);
2165 if (rc) {
2166 DP_NOTICE(p_hwfn, "Failed to get HW information\n");
2167 goto err2;
2168 }
2169
2170 /* Allocate the init RT array and initialize the init-ops engine */
2171 rc = qed_init_alloc(p_hwfn);
2591c280 2172 if (rc)
fe56b9e6 2173 goto err2;
fe56b9e6
YM		 2174
2175 return rc;
2176err2:
32a47e72
YM		 2177 if (IS_LEAD_HWFN(p_hwfn))
2178 qed_iov_free_hw_info(p_hwfn->cdev);
fe56b9e6
YM		 2179 qed_mcp_free(p_hwfn);
2180err1:
2181 qed_hw_hwfn_free(p_hwfn);
2182err0:
2183 return rc;
2184}
2185
fe56b9e6
YM		 2186int qed_hw_prepare(struct qed_dev *cdev,
2187 int personality)
2188{
c78df14e
AE		 2189 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
2190 int rc;
fe56b9e6
YM		 2191
2192 /* Store the precompiled init data ptrs */
1408cc1f
YM		 2193 if (IS_PF(cdev))
2194 qed_init_iro_array(cdev);
fe56b9e6
YM		 2195
2196 /* Initialize the first hwfn - will learn number of hwfns */
c78df14e
AE		 2197 rc = qed_hw_prepare_single(p_hwfn,
2198 cdev->regview,
fe56b9e6
YM		 2199 cdev->doorbells, personality);
2200 if (rc)
2201 return rc;
2202
c78df14e 2203 personality = p_hwfn->hw_info.personality;
fe56b9e6
YM		 2204
2205 /* Initialize the rest of the hwfns */
c78df14e 2206 if (cdev->num_hwfns > 1) {
fe56b9e6 2207 void __iomem *p_regview, *p_doorbell;
c78df14e
AE		 2208 u8 __iomem *addr;
2209
2210 /* adjust bar offset for second engine */
c2035eea 2211 addr = cdev->regview + qed_hw_bar_size(p_hwfn, BAR_ID_0) / 2;
c78df14e 2212 p_regview = addr;
fe56b9e6 2213
c78df14e 2214 /* adjust doorbell bar offset for second engine */
c2035eea 2215 addr = cdev->doorbells + qed_hw_bar_size(p_hwfn, BAR_ID_1) / 2;
c78df14e
AE		 2216 p_doorbell = addr;
2217
2218 /* prepare second hw function */
2219 rc = qed_hw_prepare_single(&cdev->hwfns[1], p_regview,
fe56b9e6 2220 p_doorbell, personality);
c78df14e
AE		 2221
2222 /* in case of error, need to free the previously
2223 * initiliazed hwfn 0.
2224 */
fe56b9e6 2225 if (rc) {
1408cc1f
YM		 2226 if (IS_PF(cdev)) {
2227 qed_init_free(p_hwfn);
2228 qed_mcp_free(p_hwfn);
2229 qed_hw_hwfn_free(p_hwfn);
2230 }
fe56b9e6
YM		 2231 }
2232 }
2233
c78df14e 2234 return rc;
fe56b9e6
YM		 2235}
2236
2237void qed_hw_remove(struct qed_dev *cdev)
2238{
0fefbfba 2239 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
fe56b9e6
YM		 2240 int i;
2241
0fefbfba
SK		 2242 if (IS_PF(cdev))
2243 qed_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt,
2244 QED_OV_DRIVER_STATE_NOT_LOADED);
2245
fe56b9e6
YM		 2246 for_each_hwfn(cdev, i) {
2247 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2248
1408cc1f 2249 if (IS_VF(cdev)) {
0b55e27d 2250 qed_vf_pf_release(p_hwfn);
1408cc1f
YM		 2251 continue;
2252 }
2253
fe56b9e6
YM		 2254 qed_init_free(p_hwfn);
2255 qed_hw_hwfn_free(p_hwfn);
2256 qed_mcp_free(p_hwfn);
2257 }
32a47e72
YM		 2258
2259 qed_iov_free_hw_info(cdev);
fe56b9e6
YM		 2260}
2261
a91eb52a
YM		 2262static void qed_chain_free_next_ptr(struct qed_dev *cdev,
2263 struct qed_chain *p_chain)
2264{
2265 void *p_virt = p_chain->p_virt_addr, *p_virt_next = NULL;
2266 dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
2267 struct qed_chain_next *p_next;
2268 u32 size, i;
2269
2270 if (!p_virt)
2271 return;
2272
2273 size = p_chain->elem_size * p_chain->usable_per_page;
2274
2275 for (i = 0; i < p_chain->page_cnt; i++) {
2276 if (!p_virt)
2277 break;
2278
2279 p_next = (struct qed_chain_next *)((u8 *)p_virt + size);
2280 p_virt_next = p_next->next_virt;
2281 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
2282
2283 dma_free_coherent(&cdev->pdev->dev,
2284 QED_CHAIN_PAGE_SIZE, p_virt, p_phys);
2285
2286 p_virt = p_virt_next;
2287 p_phys = p_phys_next;
2288 }
2289}
2290
2291static void qed_chain_free_single(struct qed_dev *cdev,
2292 struct qed_chain *p_chain)
2293{
2294 if (!p_chain->p_virt_addr)
2295 return;
2296
2297 dma_free_coherent(&cdev->pdev->dev,
2298 QED_CHAIN_PAGE_SIZE,
2299 p_chain->p_virt_addr, p_chain->p_phys_addr);
2300}
2301
2302static void qed_chain_free_pbl(struct qed_dev *cdev, struct qed_chain *p_chain)
2303{
2304 void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
2305 u32 page_cnt = p_chain->page_cnt, i, pbl_size;
6d937acf 2306 u8 *p_pbl_virt = p_chain->pbl_sp.p_virt_table;
a91eb52a
YM		 2307
2308 if (!pp_virt_addr_tbl)
2309 return;
2310
6d937acf 2311 if (!p_pbl_virt)
a91eb52a
YM		 2312 goto out;
2313
2314 for (i = 0; i < page_cnt; i++) {
2315 if (!pp_virt_addr_tbl[i])
2316 break;
2317
2318 dma_free_coherent(&cdev->pdev->dev,
2319 QED_CHAIN_PAGE_SIZE,
2320 pp_virt_addr_tbl[i],
2321 *(dma_addr_t *)p_pbl_virt);
2322
2323 p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE;
2324 }
2325
2326 pbl_size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
2327 dma_free_coherent(&cdev->pdev->dev,
2328 pbl_size,
6d937acf
MY		 2329 p_chain->pbl_sp.p_virt_table,
2330 p_chain->pbl_sp.p_phys_table);
a91eb52a
YM		 2331out:
2332 vfree(p_chain->pbl.pp_virt_addr_tbl);
2333}
2334
2335void qed_chain_free(struct qed_dev *cdev, struct qed_chain *p_chain)
2336{
2337 switch (p_chain->mode) {
2338 case QED_CHAIN_MODE_NEXT_PTR:
2339 qed_chain_free_next_ptr(cdev, p_chain);
2340 break;
2341 case QED_CHAIN_MODE_SINGLE:
2342 qed_chain_free_single(cdev, p_chain);
2343 break;
2344 case QED_CHAIN_MODE_PBL:
2345 qed_chain_free_pbl(cdev, p_chain);
2346 break;
2347 }
2348}
2349
2350static int
2351qed_chain_alloc_sanity_check(struct qed_dev *cdev,
2352 enum qed_chain_cnt_type cnt_type,
2353 size_t elem_size, u32 page_cnt)
fe56b9e6 2354{
a91eb52a
YM		 2355 u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
2356
2357 /* The actual chain size can be larger than the maximal possible value
2358 * after rounding up the requested elements number to pages, and after
2359 * taking into acount the unusuable elements (next-ptr elements).
2360 * The size of a "u16" chain can be (U16_MAX + 1) since the chain
2361 * size/capacity fields are of a u32 type.
2362 */
2363 if ((cnt_type == QED_CHAIN_CNT_TYPE_U16 &&
2364 chain_size > 0x10000) ||
2365 (cnt_type == QED_CHAIN_CNT_TYPE_U32 &&
2366 chain_size > 0x100000000ULL)) {
2367 DP_NOTICE(cdev,
2368 "The actual chain size (0x%llx) is larger than the maximal possible value\n",
2369 chain_size);
2370 return -EINVAL;
2371 }
2372
2373 return 0;
2374}
2375
2376static int
2377qed_chain_alloc_next_ptr(struct qed_dev *cdev, struct qed_chain *p_chain)
2378{
2379 void *p_virt = NULL, *p_virt_prev = NULL;
fe56b9e6 2380 dma_addr_t p_phys = 0;
a91eb52a 2381 u32 i;
fe56b9e6 2382
a91eb52a
YM		 2383 for (i = 0; i < p_chain->page_cnt; i++) {
2384 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
2385 QED_CHAIN_PAGE_SIZE,
2386 &p_phys, GFP_KERNEL);
2591c280 2387 if (!p_virt)
a91eb52a 2388 return -ENOMEM;
a91eb52a
YM		 2389
2390 if (i == 0) {
2391 qed_chain_init_mem(p_chain, p_virt, p_phys);
2392 qed_chain_reset(p_chain);
2393 } else {
2394 qed_chain_init_next_ptr_elem(p_chain, p_virt_prev,
2395 p_virt, p_phys);
2396 }
2397
2398 p_virt_prev = p_virt;
2399 }
2400 /* Last page's next element should point to the beginning of the
2401 * chain.
2402 */
2403 qed_chain_init_next_ptr_elem(p_chain, p_virt_prev,
2404 p_chain->p_virt_addr,
2405 p_chain->p_phys_addr);
2406
2407 return 0;
2408}
2409
2410static int
2411qed_chain_alloc_single(struct qed_dev *cdev, struct qed_chain *p_chain)
2412{
2413 dma_addr_t p_phys = 0;
2414 void *p_virt = NULL;
fe56b9e6 2415
fe56b9e6 2416 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
a91eb52a 2417 QED_CHAIN_PAGE_SIZE, &p_phys, GFP_KERNEL);
2591c280 2418 if (!p_virt)
a91eb52a 2419 return -ENOMEM;
fe56b9e6 2420
a91eb52a
YM		 2421 qed_chain_init_mem(p_chain, p_virt, p_phys);
2422 qed_chain_reset(p_chain);
fe56b9e6 2423
a91eb52a
YM		 2424 return 0;
2425}
2426
2427static int qed_chain_alloc_pbl(struct qed_dev *cdev, struct qed_chain *p_chain)
2428{
2429 u32 page_cnt = p_chain->page_cnt, size, i;
2430 dma_addr_t p_phys = 0, p_pbl_phys = 0;
2431 void **pp_virt_addr_tbl = NULL;
2432 u8 *p_pbl_virt = NULL;
2433 void *p_virt = NULL;
2434
2435 size = page_cnt * sizeof(*pp_virt_addr_tbl);
2591c280
JP		 2436 pp_virt_addr_tbl = vzalloc(size);
2437 if (!pp_virt_addr_tbl)
a91eb52a 2438 return -ENOMEM;
fe56b9e6 2439
a91eb52a
YM		 2440 /* The allocation of the PBL table is done with its full size, since it
2441 * is expected to be successive.
2442 * qed_chain_init_pbl_mem() is called even in a case of an allocation
2443 * failure, since pp_virt_addr_tbl was previously allocated, and it
2444 * should be saved to allow its freeing during the error flow.
2445 */
2446 size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
2447 p_pbl_virt = dma_alloc_coherent(&cdev->pdev->dev,
2448 size, &p_pbl_phys, GFP_KERNEL);
2449 qed_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
2450 pp_virt_addr_tbl);
2591c280 2451 if (!p_pbl_virt)
a91eb52a 2452 return -ENOMEM;
fe56b9e6 2453
a91eb52a
YM		 2454 for (i = 0; i < page_cnt; i++) {
2455 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
2456 QED_CHAIN_PAGE_SIZE,
2457 &p_phys, GFP_KERNEL);
2591c280 2458 if (!p_virt)
a91eb52a 2459 return -ENOMEM;
fe56b9e6 2460
a91eb52a
YM		 2461 if (i == 0) {
2462 qed_chain_init_mem(p_chain, p_virt, p_phys);
2463 qed_chain_reset(p_chain);
2464 }
2465
2466 /* Fill the PBL table with the physical address of the page */
2467 *(dma_addr_t *)p_pbl_virt = p_phys;
2468 /* Keep the virtual address of the page */
2469 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
2470
2471 p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE;
2472 }
2473
2474 return 0;
fe56b9e6
YM		 2475}
2476
a91eb52a
YM		 2477int qed_chain_alloc(struct qed_dev *cdev,
2478 enum qed_chain_use_mode intended_use,
2479 enum qed_chain_mode mode,
2480 enum qed_chain_cnt_type cnt_type,
2481 u32 num_elems, size_t elem_size, struct qed_chain *p_chain)
fe56b9e6 2482{
a91eb52a
YM		 2483 u32 page_cnt;
2484 int rc = 0;
fe56b9e6 2485
a91eb52a
YM		 2486 if (mode == QED_CHAIN_MODE_SINGLE)
2487 page_cnt = 1;
2488 else
2489 page_cnt = QED_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
fe56b9e6 2490
a91eb52a
YM		 2491 rc = qed_chain_alloc_sanity_check(cdev, cnt_type, elem_size, page_cnt);
2492 if (rc) {
2493 DP_NOTICE(cdev,
2591c280
JP		 2494 "Cannot allocate a chain with the given arguments:\n");
2495 DP_NOTICE(cdev,
a91eb52a
YM		 2496 "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
2497 intended_use, mode, cnt_type, num_elems, elem_size);
2498 return rc;
fe56b9e6
YM		 2499 }
2500
a91eb52a
YM		 2501 qed_chain_init_params(p_chain, page_cnt, (u8) elem_size, intended_use,
2502 mode, cnt_type);
2503
2504 switch (mode) {
2505 case QED_CHAIN_MODE_NEXT_PTR:
2506 rc = qed_chain_alloc_next_ptr(cdev, p_chain);
2507 break;
2508 case QED_CHAIN_MODE_SINGLE:
2509 rc = qed_chain_alloc_single(cdev, p_chain);
2510 break;
2511 case QED_CHAIN_MODE_PBL:
2512 rc = qed_chain_alloc_pbl(cdev, p_chain);
2513 break;
2514 }
2515 if (rc)
2516 goto nomem;
2517
2518 return 0;
2519
2520nomem:
2521 qed_chain_free(cdev, p_chain);
2522 return rc;
fe56b9e6 2523}
cee4d264 2524
a91eb52a 2525int qed_fw_l2_queue(struct qed_hwfn *p_hwfn, u16 src_id, u16 *dst_id)
cee4d264
MC		 2526{
2527 if (src_id >= RESC_NUM(p_hwfn, QED_L2_QUEUE)) {
2528 u16 min, max;
2529
a91eb52a 2530 min = (u16) RESC_START(p_hwfn, QED_L2_QUEUE);
cee4d264
MC		 2531 max = min + RESC_NUM(p_hwfn, QED_L2_QUEUE);
2532 DP_NOTICE(p_hwfn,
2533 "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
2534 src_id, min, max);
2535
2536 return -EINVAL;
2537 }
2538
2539 *dst_id = RESC_START(p_hwfn, QED_L2_QUEUE) + src_id;
2540
2541 return 0;
2542}
2543
1a635e48 2544int qed_fw_vport(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id)
cee4d264
MC		 2545{
2546 if (src_id >= RESC_NUM(p_hwfn, QED_VPORT)) {
2547 u8 min, max;
2548
2549 min = (u8)RESC_START(p_hwfn, QED_VPORT);
2550 max = min + RESC_NUM(p_hwfn, QED_VPORT);
2551 DP_NOTICE(p_hwfn,
2552 "vport id [%d] is not valid, available indices [%d - %d]\n",
2553 src_id, min, max);
2554
2555 return -EINVAL;
2556 }
2557
2558 *dst_id = RESC_START(p_hwfn, QED_VPORT) + src_id;
2559
2560 return 0;
2561}
2562
1a635e48 2563int qed_fw_rss_eng(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id)
cee4d264
MC		 2564{
2565 if (src_id >= RESC_NUM(p_hwfn, QED_RSS_ENG)) {
2566 u8 min, max;
2567
2568 min = (u8)RESC_START(p_hwfn, QED_RSS_ENG);
2569 max = min + RESC_NUM(p_hwfn, QED_RSS_ENG);
2570 DP_NOTICE(p_hwfn,
2571 "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
2572 src_id, min, max);
2573
2574 return -EINVAL;
2575 }
2576
2577 *dst_id = RESC_START(p_hwfn, QED_RSS_ENG) + src_id;
2578
2579 return 0;
2580}
bcd197c8 2581
0a7fb11c
YM		 2582static void qed_llh_mac_to_filter(u32 *p_high, u32 *p_low,
2583 u8 *p_filter)
2584{
2585 *p_high = p_filter[1] | (p_filter[0] << 8);
2586 *p_low = p_filter[5] | (p_filter[4] << 8) |
2587 (p_filter[3] << 16) | (p_filter[2] << 24);
2588}
2589
2590int qed_llh_add_mac_filter(struct qed_hwfn *p_hwfn,
2591 struct qed_ptt *p_ptt, u8 *p_filter)
2592{
2593 u32 high = 0, low = 0, en;
2594 int i;
2595
2596 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
2597 return 0;
2598
2599 qed_llh_mac_to_filter(&high, &low, p_filter);
2600
2601 /* Find a free entry and utilize it */
2602 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
2603 en = qed_rd(p_hwfn, p_ptt,
2604 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
2605 if (en)
2606 continue;
2607 qed_wr(p_hwfn, p_ptt,
2608 NIG_REG_LLH_FUNC_FILTER_VALUE +
2609 2 * i * sizeof(u32), low);
2610 qed_wr(p_hwfn, p_ptt,
2611 NIG_REG_LLH_FUNC_FILTER_VALUE +
2612 (2 * i + 1) * sizeof(u32), high);
2613 qed_wr(p_hwfn, p_ptt,
2614 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
2615 qed_wr(p_hwfn, p_ptt,
2616 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
2617 i * sizeof(u32), 0);
2618 qed_wr(p_hwfn, p_ptt,
2619 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
2620 break;
2621 }
2622 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
2623 DP_NOTICE(p_hwfn,
2624 "Failed to find an empty LLH filter to utilize\n");
2625 return -EINVAL;
2626 }
2627
2628 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
2629 "mac: %pM is added at %d\n",
2630 p_filter, i);
2631
2632 return 0;
2633}
2634
2635void qed_llh_remove_mac_filter(struct qed_hwfn *p_hwfn,
2636 struct qed_ptt *p_ptt, u8 *p_filter)
2637{
2638 u32 high = 0, low = 0;
2639 int i;
2640
2641 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
2642 return;
2643
2644 qed_llh_mac_to_filter(&high, &low, p_filter);
2645
2646 /* Find the entry and clean it */
2647 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
2648 if (qed_rd(p_hwfn, p_ptt,
2649 NIG_REG_LLH_FUNC_FILTER_VALUE +
2650 2 * i * sizeof(u32)) != low)
2651 continue;
2652 if (qed_rd(p_hwfn, p_ptt,
2653 NIG_REG_LLH_FUNC_FILTER_VALUE +
2654 (2 * i + 1) * sizeof(u32)) != high)
2655 continue;
2656
2657 qed_wr(p_hwfn, p_ptt,
2658 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
2659 qed_wr(p_hwfn, p_ptt,
2660 NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * i * sizeof(u32), 0);
2661 qed_wr(p_hwfn, p_ptt,
2662 NIG_REG_LLH_FUNC_FILTER_VALUE +
2663 (2 * i + 1) * sizeof(u32), 0);
2664
2665 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
2666 "mac: %pM is removed from %d\n",
2667 p_filter, i);
2668 break;
2669 }
2670 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
2671 DP_NOTICE(p_hwfn, "Tried to remove a non-configured filter\n");
2672}
2673
722003ac
SRK		 2674static int qed_set_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
2675 u32 hw_addr, void *p_eth_qzone,
2676 size_t eth_qzone_size, u8 timeset)
2677{
2678 struct coalescing_timeset *p_coal_timeset;
2679
2680 if (p_hwfn->cdev->int_coalescing_mode != QED_COAL_MODE_ENABLE) {
2681 DP_NOTICE(p_hwfn, "Coalescing configuration not enabled\n");
2682 return -EINVAL;
2683 }
2684
2685 p_coal_timeset = p_eth_qzone;
2686 memset(p_coal_timeset, 0, eth_qzone_size);
2687 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
2688 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
2689 qed_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
2690
2691 return 0;
2692}
2693
2694int qed_set_rxq_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
2695 u16 coalesce, u8 qid, u16 sb_id)
2696{
2697 struct ustorm_eth_queue_zone eth_qzone;
2698 u8 timeset, timer_res;
2699 u16 fw_qid = 0;
2700 u32 address;
2701 int rc;
2702
2703 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
2704 if (coalesce <= 0x7F) {
2705 timer_res = 0;
2706 } else if (coalesce <= 0xFF) {
2707 timer_res = 1;
2708 } else if (coalesce <= 0x1FF) {
2709 timer_res = 2;
2710 } else {
2711 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
2712 return -EINVAL;
2713 }
2714 timeset = (u8)(coalesce >> timer_res);
2715
2716 rc = qed_fw_l2_queue(p_hwfn, (u16)qid, &fw_qid);
2717 if (rc)
2718 return rc;
2719
2720 rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, false);
2721 if (rc)
2722 goto out;
2723
2724 address = BAR0_MAP_REG_USDM_RAM + USTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
2725
2726 rc = qed_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
2727 sizeof(struct ustorm_eth_queue_zone), timeset);
2728 if (rc)
2729 goto out;
2730
2731 p_hwfn->cdev->rx_coalesce_usecs = coalesce;
2732out:
2733 return rc;
2734}
2735
2736int qed_set_txq_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
2737 u16 coalesce, u8 qid, u16 sb_id)
2738{
2739 struct xstorm_eth_queue_zone eth_qzone;
2740 u8 timeset, timer_res;
2741 u16 fw_qid = 0;
2742 u32 address;
2743 int rc;
2744
2745 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
2746 if (coalesce <= 0x7F) {
2747 timer_res = 0;
2748 } else if (coalesce <= 0xFF) {
2749 timer_res = 1;
2750 } else if (coalesce <= 0x1FF) {
2751 timer_res = 2;
2752 } else {
2753 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
2754 return -EINVAL;
2755 }
2756 timeset = (u8)(coalesce >> timer_res);
2757
2758 rc = qed_fw_l2_queue(p_hwfn, (u16)qid, &fw_qid);
2759 if (rc)
2760 return rc;
2761
2762 rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, true);
2763 if (rc)
2764 goto out;
2765
2766 address = BAR0_MAP_REG_XSDM_RAM + XSTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid);
2767
2768 rc = qed_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
2769 sizeof(struct xstorm_eth_queue_zone), timeset);
2770 if (rc)
2771 goto out;
2772
2773 p_hwfn->cdev->tx_coalesce_usecs = coalesce;
2774out:
2775 return rc;
2776}
2777
bcd197c8
MC		 2778/* Calculate final WFQ values for all vports and configure them.
2779 * After this configuration each vport will have
2780 * approx min rate = min_pf_rate * (vport_wfq / QED_WFQ_UNIT)
2781 */
2782static void qed_configure_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
2783 struct qed_ptt *p_ptt,
2784 u32 min_pf_rate)
2785{
2786 struct init_qm_vport_params *vport_params;
2787 int i;
2788
2789 vport_params = p_hwfn->qm_info.qm_vport_params;
2790
2791 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
2792 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
2793
2794 vport_params[i].vport_wfq = (wfq_speed * QED_WFQ_UNIT) /
2795 min_pf_rate;
2796 qed_init_vport_wfq(p_hwfn, p_ptt,
2797 vport_params[i].first_tx_pq_id,
2798 vport_params[i].vport_wfq);
2799 }
2800}
2801
2802static void qed_init_wfq_default_param(struct qed_hwfn *p_hwfn,
2803 u32 min_pf_rate)
2804
2805{
2806 int i;
2807
2808 for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
2809 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
2810}
2811
2812static void qed_disable_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
2813 struct qed_ptt *p_ptt,
2814 u32 min_pf_rate)
2815{
2816 struct init_qm_vport_params *vport_params;
2817 int i;
2818
2819 vport_params = p_hwfn->qm_info.qm_vport_params;
2820
2821 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
2822 qed_init_wfq_default_param(p_hwfn, min_pf_rate);
2823 qed_init_vport_wfq(p_hwfn, p_ptt,
2824 vport_params[i].first_tx_pq_id,
2825 vport_params[i].vport_wfq);
2826 }
2827}
2828
2829/* This function performs several validations for WFQ
2830 * configuration and required min rate for a given vport
2831 * 1. req_rate must be greater than one percent of min_pf_rate.
2832 * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
2833 * rates to get less than one percent of min_pf_rate.
2834 * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
2835 */
2836static int qed_init_wfq_param(struct qed_hwfn *p_hwfn,
1a635e48 2837 u16 vport_id, u32 req_rate, u32 min_pf_rate)
bcd197c8
MC		 2838{
2839 u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
2840 int non_requested_count = 0, req_count = 0, i, num_vports;
2841
2842 num_vports = p_hwfn->qm_info.num_vports;
2843
2844 /* Accounting for the vports which are configured for WFQ explicitly */
2845 for (i = 0; i < num_vports; i++) {
2846 u32 tmp_speed;
2847
2848 if ((i != vport_id) &&
2849 p_hwfn->qm_info.wfq_data[i].configured) {
2850 req_count++;
2851 tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
2852 total_req_min_rate += tmp_speed;
2853 }
2854 }
2855
2856 /* Include current vport data as well */
2857 req_count++;
2858 total_req_min_rate += req_rate;
2859 non_requested_count = num_vports - req_count;
2860
2861 if (req_rate < min_pf_rate / QED_WFQ_UNIT) {
2862 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
2863 "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
2864 vport_id, req_rate, min_pf_rate);
2865 return -EINVAL;
2866 }
2867
2868 if (num_vports > QED_WFQ_UNIT) {
2869 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
2870 "Number of vports is greater than %d\n",
2871 QED_WFQ_UNIT);
2872 return -EINVAL;
2873 }
2874
2875 if (total_req_min_rate > min_pf_rate) {
2876 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
2877 "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
2878 total_req_min_rate, min_pf_rate);
2879 return -EINVAL;
2880 }
2881
2882 total_left_rate = min_pf_rate - total_req_min_rate;
2883
2884 left_rate_per_vp = total_left_rate / non_requested_count;
2885 if (left_rate_per_vp < min_pf_rate / QED_WFQ_UNIT) {
2886 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
2887 "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
2888 left_rate_per_vp, min_pf_rate);
2889 return -EINVAL;
2890 }
2891
2892 p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
2893 p_hwfn->qm_info.wfq_data[vport_id].configured = true;
2894
2895 for (i = 0; i < num_vports; i++) {
2896 if (p_hwfn->qm_info.wfq_data[i].configured)
2897 continue;
2898
2899 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
2900 }
2901
2902 return 0;
2903}
2904
733def6a
YM		 2905static int __qed_configure_vport_wfq(struct qed_hwfn *p_hwfn,
2906 struct qed_ptt *p_ptt, u16 vp_id, u32 rate)
2907{
2908 struct qed_mcp_link_state *p_link;
2909 int rc = 0;
2910
2911 p_link = &p_hwfn->cdev->hwfns[0].mcp_info->link_output;
2912
2913 if (!p_link->min_pf_rate) {
2914 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
2915 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
2916 return rc;
2917 }
2918
2919 rc = qed_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
2920
1a635e48 2921 if (!rc)
733def6a
YM		 2922 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt,
2923 p_link->min_pf_rate);
2924 else
2925 DP_NOTICE(p_hwfn,
2926 "Validation failed while configuring min rate\n");
2927
2928 return rc;
2929}
2930
bcd197c8
MC		 2931static int __qed_configure_vp_wfq_on_link_change(struct qed_hwfn *p_hwfn,
2932 struct qed_ptt *p_ptt,
2933 u32 min_pf_rate)
2934{
2935 bool use_wfq = false;
2936 int rc = 0;
2937 u16 i;
2938
2939 /* Validate all pre configured vports for wfq */
2940 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
2941 u32 rate;
2942
2943 if (!p_hwfn->qm_info.wfq_data[i].configured)
2944 continue;
2945
2946 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
2947 use_wfq = true;
2948
2949 rc = qed_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
2950 if (rc) {
2951 DP_NOTICE(p_hwfn,
2952 "WFQ validation failed while configuring min rate\n");
2953 break;
2954 }
2955 }
2956
2957 if (!rc && use_wfq)
2958 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
2959 else
2960 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
2961
2962 return rc;
2963}
2964
733def6a
YM		 2965/* Main API for qed clients to configure vport min rate.
2966 * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
2967 * rate - Speed in Mbps needs to be assigned to a given vport.
2968 */
2969int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate)
2970{
2971 int i, rc = -EINVAL;
2972
2973 /* Currently not supported; Might change in future */
2974 if (cdev->num_hwfns > 1) {
2975 DP_NOTICE(cdev,
2976 "WFQ configuration is not supported for this device\n");
2977 return rc;
2978 }
2979
2980 for_each_hwfn(cdev, i) {
2981 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2982 struct qed_ptt *p_ptt;
2983
2984 p_ptt = qed_ptt_acquire(p_hwfn);
2985 if (!p_ptt)
2986 return -EBUSY;
2987
2988 rc = __qed_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
2989
d572c430 2990 if (rc) {
733def6a
YM		 2991 qed_ptt_release(p_hwfn, p_ptt);
2992 return rc;
2993 }
2994
2995 qed_ptt_release(p_hwfn, p_ptt);
2996 }
2997
2998 return rc;
2999}
3000
bcd197c8
MC		 3001/* API to configure WFQ from mcp link change */
3002void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev, u32 min_pf_rate)
3003{
3004 int i;
3005
3e7cfce2
YM		 3006 if (cdev->num_hwfns > 1) {
3007 DP_VERBOSE(cdev,
3008 NETIF_MSG_LINK,
3009 "WFQ configuration is not supported for this device\n");
3010 return;
3011 }
3012
bcd197c8
MC		 3013 for_each_hwfn(cdev, i) {
3014 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
3015
3016 __qed_configure_vp_wfq_on_link_change(p_hwfn,
3017 p_hwfn->p_dpc_ptt,
3018 min_pf_rate);
3019 }
3020}
4b01e519
MC		 3021
3022int __qed_configure_pf_max_bandwidth(struct qed_hwfn *p_hwfn,
3023 struct qed_ptt *p_ptt,
3024 struct qed_mcp_link_state *p_link,
3025 u8 max_bw)
3026{
3027 int rc = 0;
3028
3029 p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
3030
3031 if (!p_link->line_speed && (max_bw != 100))
3032 return rc;
3033
3034 p_link->speed = (p_link->line_speed * max_bw) / 100;
3035 p_hwfn->qm_info.pf_rl = p_link->speed;
3036
3037 /* Since the limiter also affects Tx-switched traffic, we don't want it
3038 * to limit such traffic in case there's no actual limit.
3039 * In that case, set limit to imaginary high boundary.
3040 */
3041 if (max_bw == 100)
3042 p_hwfn->qm_info.pf_rl = 100000;
3043
3044 rc = qed_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
3045 p_hwfn->qm_info.pf_rl);
3046
3047 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
3048 "Configured MAX bandwidth to be %08x Mb/sec\n",
3049 p_link->speed);
3050
3051 return rc;
3052}
3053
3054/* Main API to configure PF max bandwidth where bw range is [1 - 100] */
3055int qed_configure_pf_max_bandwidth(struct qed_dev *cdev, u8 max_bw)
3056{
3057 int i, rc = -EINVAL;
3058
3059 if (max_bw < 1 || max_bw > 100) {
3060 DP_NOTICE(cdev, "PF max bw valid range is [1-100]\n");
3061 return rc;
3062 }
3063
3064 for_each_hwfn(cdev, i) {
3065 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
3066 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
3067 struct qed_mcp_link_state *p_link;
3068 struct qed_ptt *p_ptt;
3069
3070 p_link = &p_lead->mcp_info->link_output;
3071
3072 p_ptt = qed_ptt_acquire(p_hwfn);
3073 if (!p_ptt)
3074 return -EBUSY;
3075
3076 rc = __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt,
3077 p_link, max_bw);
3078
3079 qed_ptt_release(p_hwfn, p_ptt);
3080
3081 if (rc)
3082 break;
3083 }
3084
3085 return rc;
3086}
a64b02d5
MC		 3087
3088int __qed_configure_pf_min_bandwidth(struct qed_hwfn *p_hwfn,
3089 struct qed_ptt *p_ptt,
3090 struct qed_mcp_link_state *p_link,
3091 u8 min_bw)
3092{
3093 int rc = 0;
3094
3095 p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
3096 p_hwfn->qm_info.pf_wfq = min_bw;
3097
3098 if (!p_link->line_speed)
3099 return rc;
3100
3101 p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
3102
3103 rc = qed_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
3104
3105 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
3106 "Configured MIN bandwidth to be %d Mb/sec\n",
3107 p_link->min_pf_rate);
3108
3109 return rc;
3110}
3111
3112/* Main API to configure PF min bandwidth where bw range is [1-100] */
3113int qed_configure_pf_min_bandwidth(struct qed_dev *cdev, u8 min_bw)
3114{
3115 int i, rc = -EINVAL;
3116
3117 if (min_bw < 1 || min_bw > 100) {
3118 DP_NOTICE(cdev, "PF min bw valid range is [1-100]\n");
3119 return rc;
3120 }
3121
3122 for_each_hwfn(cdev, i) {
3123 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
3124 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
3125 struct qed_mcp_link_state *p_link;
3126 struct qed_ptt *p_ptt;
3127
3128 p_link = &p_lead->mcp_info->link_output;
3129
3130 p_ptt = qed_ptt_acquire(p_hwfn);
3131 if (!p_ptt)
3132 return -EBUSY;
3133
3134 rc = __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt,
3135 p_link, min_bw);
3136 if (rc) {
3137 qed_ptt_release(p_hwfn, p_ptt);
3138 return rc;
3139 }
3140
3141 if (p_link->min_pf_rate) {
3142 u32 min_rate = p_link->min_pf_rate;
3143
3144 rc = __qed_configure_vp_wfq_on_link_change(p_hwfn,
3145 p_ptt,
3146 min_rate);
3147 }
3148
3149 qed_ptt_release(p_hwfn, p_ptt);
3150 }
3151
3152 return rc;
3153}
733def6a
YM		 3154
3155void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3156{
3157 struct qed_mcp_link_state *p_link;
3158
3159 p_link = &p_hwfn->mcp_info->link_output;
3160
3161 if (p_link->min_pf_rate)
3162 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt,
3163 p_link->min_pf_rate);
3164
3165 memset(p_hwfn->qm_info.wfq_data, 0,
3166 sizeof(*p_hwfn->qm_info.wfq_data) * p_hwfn->qm_info.num_vports);
3167}
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