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fe56b9e6 YM |
1 | /* QLogic qed NIC Driver |
2 | * Copyright (c) 2015 QLogic Corporation | |
3 | * | |
4 | * This software is available under the terms of the GNU General Public License | |
5 | * (GPL) Version 2, available from the file COPYING in the main directory of | |
6 | * this source tree. | |
7 | */ | |
8 | ||
9 | #ifndef _QED_HSI_H | |
10 | #define _QED_HSI_H | |
11 | ||
12 | #include <linux/types.h> | |
13 | #include <linux/io.h> | |
14 | #include <linux/bitops.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/kernel.h> | |
17 | #include <linux/list.h> | |
18 | #include <linux/slab.h> | |
19 | #include <linux/qed/common_hsi.h> | |
7a9b6b8f YM |
20 | #include <linux/qed/storage_common.h> |
21 | #include <linux/qed/tcp_common.h> | |
25c089d7 | 22 | #include <linux/qed/eth_common.h> |
7a9b6b8f YM |
23 | #include <linux/qed/iscsi_common.h> |
24 | #include <linux/qed/rdma_common.h> | |
25 | #include <linux/qed/roce_common.h> | |
fe56b9e6 YM |
26 | |
27 | struct qed_hwfn; | |
28 | struct qed_ptt; | |
fe56b9e6 YM |
29 | |
30 | /* opcodes for the event ring */ | |
31 | enum common_event_opcode { | |
32 | COMMON_EVENT_PF_START, | |
33 | COMMON_EVENT_PF_STOP, | |
1408cc1f | 34 | COMMON_EVENT_VF_START, |
0b55e27d | 35 | COMMON_EVENT_VF_STOP, |
37bff2b9 | 36 | COMMON_EVENT_VF_PF_CHANNEL, |
351a4ded YM |
37 | COMMON_EVENT_VF_FLR, |
38 | COMMON_EVENT_PF_UPDATE, | |
39 | COMMON_EVENT_MALICIOUS_VF, | |
40 | COMMON_EVENT_RL_UPDATE, | |
fc48b7a6 | 41 | COMMON_EVENT_EMPTY, |
fe56b9e6 YM |
42 | MAX_COMMON_EVENT_OPCODE |
43 | }; | |
44 | ||
45 | /* Common Ramrod Command IDs */ | |
46 | enum common_ramrod_cmd_id { | |
47 | COMMON_RAMROD_UNUSED, | |
351a4ded YM |
48 | COMMON_RAMROD_PF_START, |
49 | COMMON_RAMROD_PF_STOP, | |
1408cc1f | 50 | COMMON_RAMROD_VF_START, |
0b55e27d | 51 | COMMON_RAMROD_VF_STOP, |
464f6645 | 52 | COMMON_RAMROD_PF_UPDATE, |
351a4ded | 53 | COMMON_RAMROD_RL_UPDATE, |
fc48b7a6 | 54 | COMMON_RAMROD_EMPTY, |
fe56b9e6 YM |
55 | MAX_COMMON_RAMROD_CMD_ID |
56 | }; | |
57 | ||
58 | /* The core storm context for the Ystorm */ | |
59 | struct ystorm_core_conn_st_ctx { | |
60 | __le32 reserved[4]; | |
61 | }; | |
62 | ||
63 | /* The core storm context for the Pstorm */ | |
64 | struct pstorm_core_conn_st_ctx { | |
65 | __le32 reserved[4]; | |
66 | }; | |
67 | ||
68 | /* Core Slowpath Connection storm context of Xstorm */ | |
69 | struct xstorm_core_conn_st_ctx { | |
351a4ded YM |
70 | __le32 spq_base_lo; |
71 | __le32 spq_base_hi; | |
72 | struct regpair consolid_base_addr; | |
73 | __le16 spq_cons; | |
74 | __le16 consolid_cons; | |
75 | __le32 reserved0[55]; | |
fe56b9e6 YM |
76 | }; |
77 | ||
78 | struct xstorm_core_conn_ag_ctx { | |
351a4ded YM |
79 | u8 reserved0; |
80 | u8 core_state; | |
81 | u8 flags0; | |
82 | #define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 | |
83 | #define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 | |
84 | #define XSTORM_CORE_CONN_AG_CTX_RESERVED1_MASK 0x1 | |
85 | #define XSTORM_CORE_CONN_AG_CTX_RESERVED1_SHIFT 1 | |
86 | #define XSTORM_CORE_CONN_AG_CTX_RESERVED2_MASK 0x1 | |
87 | #define XSTORM_CORE_CONN_AG_CTX_RESERVED2_SHIFT 2 | |
88 | #define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 | |
89 | #define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 | |
90 | #define XSTORM_CORE_CONN_AG_CTX_RESERVED3_MASK 0x1 | |
91 | #define XSTORM_CORE_CONN_AG_CTX_RESERVED3_SHIFT 4 | |
92 | #define XSTORM_CORE_CONN_AG_CTX_RESERVED4_MASK 0x1 | |
93 | #define XSTORM_CORE_CONN_AG_CTX_RESERVED4_SHIFT 5 | |
94 | #define XSTORM_CORE_CONN_AG_CTX_RESERVED5_MASK 0x1 | |
95 | #define XSTORM_CORE_CONN_AG_CTX_RESERVED5_SHIFT 6 | |
96 | #define XSTORM_CORE_CONN_AG_CTX_RESERVED6_MASK 0x1 | |
97 | #define XSTORM_CORE_CONN_AG_CTX_RESERVED6_SHIFT 7 | |
fe56b9e6 | 98 | u8 flags1; |
351a4ded YM |
99 | #define XSTORM_CORE_CONN_AG_CTX_RESERVED7_MASK 0x1 |
100 | #define XSTORM_CORE_CONN_AG_CTX_RESERVED7_SHIFT 0 | |
101 | #define XSTORM_CORE_CONN_AG_CTX_RESERVED8_MASK 0x1 | |
102 | #define XSTORM_CORE_CONN_AG_CTX_RESERVED8_SHIFT 1 | |
103 | #define XSTORM_CORE_CONN_AG_CTX_RESERVED9_MASK 0x1 | |
104 | #define XSTORM_CORE_CONN_AG_CTX_RESERVED9_SHIFT 2 | |
105 | #define XSTORM_CORE_CONN_AG_CTX_BIT11_MASK 0x1 | |
106 | #define XSTORM_CORE_CONN_AG_CTX_BIT11_SHIFT 3 | |
107 | #define XSTORM_CORE_CONN_AG_CTX_BIT12_MASK 0x1 | |
108 | #define XSTORM_CORE_CONN_AG_CTX_BIT12_SHIFT 4 | |
109 | #define XSTORM_CORE_CONN_AG_CTX_BIT13_MASK 0x1 | |
110 | #define XSTORM_CORE_CONN_AG_CTX_BIT13_SHIFT 5 | |
111 | #define XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1 | |
112 | #define XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6 | |
113 | #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1 | |
114 | #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7 | |
fe56b9e6 | 115 | u8 flags2; |
351a4ded YM |
116 | #define XSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 |
117 | #define XSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 0 | |
118 | #define XSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 | |
119 | #define XSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 2 | |
120 | #define XSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 | |
121 | #define XSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 4 | |
122 | #define XSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3 | |
123 | #define XSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 6 | |
fe56b9e6 | 124 | u8 flags3; |
351a4ded YM |
125 | #define XSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3 |
126 | #define XSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 0 | |
127 | #define XSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3 | |
128 | #define XSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 2 | |
129 | #define XSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3 | |
130 | #define XSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 4 | |
131 | #define XSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3 | |
132 | #define XSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 6 | |
fe56b9e6 | 133 | u8 flags4; |
351a4ded YM |
134 | #define XSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3 |
135 | #define XSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 0 | |
136 | #define XSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3 | |
137 | #define XSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 2 | |
138 | #define XSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3 | |
139 | #define XSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 4 | |
140 | #define XSTORM_CORE_CONN_AG_CTX_CF11_MASK 0x3 | |
141 | #define XSTORM_CORE_CONN_AG_CTX_CF11_SHIFT 6 | |
fe56b9e6 | 142 | u8 flags5; |
351a4ded YM |
143 | #define XSTORM_CORE_CONN_AG_CTX_CF12_MASK 0x3 |
144 | #define XSTORM_CORE_CONN_AG_CTX_CF12_SHIFT 0 | |
145 | #define XSTORM_CORE_CONN_AG_CTX_CF13_MASK 0x3 | |
146 | #define XSTORM_CORE_CONN_AG_CTX_CF13_SHIFT 2 | |
147 | #define XSTORM_CORE_CONN_AG_CTX_CF14_MASK 0x3 | |
148 | #define XSTORM_CORE_CONN_AG_CTX_CF14_SHIFT 4 | |
149 | #define XSTORM_CORE_CONN_AG_CTX_CF15_MASK 0x3 | |
150 | #define XSTORM_CORE_CONN_AG_CTX_CF15_SHIFT 6 | |
fe56b9e6 | 151 | u8 flags6; |
351a4ded YM |
152 | #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_MASK 0x3 |
153 | #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_SHIFT 0 | |
154 | #define XSTORM_CORE_CONN_AG_CTX_CF17_MASK 0x3 | |
155 | #define XSTORM_CORE_CONN_AG_CTX_CF17_SHIFT 2 | |
156 | #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_MASK 0x3 | |
157 | #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_SHIFT 4 | |
158 | #define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_MASK 0x3 | |
159 | #define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_SHIFT 6 | |
fe56b9e6 | 160 | u8 flags7; |
351a4ded YM |
161 | #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 |
162 | #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 | |
163 | #define XSTORM_CORE_CONN_AG_CTX_RESERVED10_MASK 0x3 | |
164 | #define XSTORM_CORE_CONN_AG_CTX_RESERVED10_SHIFT 2 | |
165 | #define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_MASK 0x3 | |
166 | #define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_SHIFT 4 | |
167 | #define XSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 | |
168 | #define XSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 6 | |
169 | #define XSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 | |
170 | #define XSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 7 | |
fe56b9e6 | 171 | u8 flags8; |
351a4ded YM |
172 | #define XSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 |
173 | #define XSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 0 | |
174 | #define XSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1 | |
175 | #define XSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 1 | |
176 | #define XSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1 | |
177 | #define XSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 2 | |
178 | #define XSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1 | |
179 | #define XSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 3 | |
180 | #define XSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1 | |
181 | #define XSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 4 | |
182 | #define XSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1 | |
183 | #define XSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 5 | |
184 | #define XSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1 | |
185 | #define XSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 6 | |
186 | #define XSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1 | |
187 | #define XSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 7 | |
fe56b9e6 | 188 | u8 flags9; |
351a4ded YM |
189 | #define XSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1 |
190 | #define XSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 0 | |
191 | #define XSTORM_CORE_CONN_AG_CTX_CF11EN_MASK 0x1 | |
192 | #define XSTORM_CORE_CONN_AG_CTX_CF11EN_SHIFT 1 | |
193 | #define XSTORM_CORE_CONN_AG_CTX_CF12EN_MASK 0x1 | |
194 | #define XSTORM_CORE_CONN_AG_CTX_CF12EN_SHIFT 2 | |
195 | #define XSTORM_CORE_CONN_AG_CTX_CF13EN_MASK 0x1 | |
196 | #define XSTORM_CORE_CONN_AG_CTX_CF13EN_SHIFT 3 | |
197 | #define XSTORM_CORE_CONN_AG_CTX_CF14EN_MASK 0x1 | |
198 | #define XSTORM_CORE_CONN_AG_CTX_CF14EN_SHIFT 4 | |
199 | #define XSTORM_CORE_CONN_AG_CTX_CF15EN_MASK 0x1 | |
200 | #define XSTORM_CORE_CONN_AG_CTX_CF15EN_SHIFT 5 | |
201 | #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_MASK 0x1 | |
202 | #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_SHIFT 6 | |
203 | #define XSTORM_CORE_CONN_AG_CTX_CF17EN_MASK 0x1 | |
204 | #define XSTORM_CORE_CONN_AG_CTX_CF17EN_SHIFT 7 | |
fe56b9e6 | 205 | u8 flags10; |
351a4ded YM |
206 | #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 |
207 | #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_SHIFT 0 | |
208 | #define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1 | |
209 | #define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1 | |
210 | #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 | |
211 | #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 | |
212 | #define XSTORM_CORE_CONN_AG_CTX_RESERVED11_MASK 0x1 | |
213 | #define XSTORM_CORE_CONN_AG_CTX_RESERVED11_SHIFT 3 | |
214 | #define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 | |
215 | #define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 | |
216 | #define XSTORM_CORE_CONN_AG_CTX_CF23EN_MASK 0x1 | |
217 | #define XSTORM_CORE_CONN_AG_CTX_CF23EN_SHIFT 5 | |
218 | #define XSTORM_CORE_CONN_AG_CTX_RESERVED12_MASK 0x1 | |
219 | #define XSTORM_CORE_CONN_AG_CTX_RESERVED12_SHIFT 6 | |
220 | #define XSTORM_CORE_CONN_AG_CTX_RESERVED13_MASK 0x1 | |
221 | #define XSTORM_CORE_CONN_AG_CTX_RESERVED13_SHIFT 7 | |
fe56b9e6 | 222 | u8 flags11; |
351a4ded YM |
223 | #define XSTORM_CORE_CONN_AG_CTX_RESERVED14_MASK 0x1 |
224 | #define XSTORM_CORE_CONN_AG_CTX_RESERVED14_SHIFT 0 | |
225 | #define XSTORM_CORE_CONN_AG_CTX_RESERVED15_MASK 0x1 | |
226 | #define XSTORM_CORE_CONN_AG_CTX_RESERVED15_SHIFT 1 | |
227 | #define XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1 | |
228 | #define XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2 | |
229 | #define XSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1 | |
230 | #define XSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 3 | |
231 | #define XSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1 | |
232 | #define XSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 4 | |
233 | #define XSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1 | |
234 | #define XSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 5 | |
235 | #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 | |
236 | #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 | |
237 | #define XSTORM_CORE_CONN_AG_CTX_RULE9EN_MASK 0x1 | |
238 | #define XSTORM_CORE_CONN_AG_CTX_RULE9EN_SHIFT 7 | |
fe56b9e6 | 239 | u8 flags12; |
351a4ded YM |
240 | #define XSTORM_CORE_CONN_AG_CTX_RULE10EN_MASK 0x1 |
241 | #define XSTORM_CORE_CONN_AG_CTX_RULE10EN_SHIFT 0 | |
242 | #define XSTORM_CORE_CONN_AG_CTX_RULE11EN_MASK 0x1 | |
243 | #define XSTORM_CORE_CONN_AG_CTX_RULE11EN_SHIFT 1 | |
244 | #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 | |
245 | #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 | |
246 | #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 | |
247 | #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 | |
248 | #define XSTORM_CORE_CONN_AG_CTX_RULE14EN_MASK 0x1 | |
249 | #define XSTORM_CORE_CONN_AG_CTX_RULE14EN_SHIFT 4 | |
250 | #define XSTORM_CORE_CONN_AG_CTX_RULE15EN_MASK 0x1 | |
251 | #define XSTORM_CORE_CONN_AG_CTX_RULE15EN_SHIFT 5 | |
252 | #define XSTORM_CORE_CONN_AG_CTX_RULE16EN_MASK 0x1 | |
253 | #define XSTORM_CORE_CONN_AG_CTX_RULE16EN_SHIFT 6 | |
254 | #define XSTORM_CORE_CONN_AG_CTX_RULE17EN_MASK 0x1 | |
255 | #define XSTORM_CORE_CONN_AG_CTX_RULE17EN_SHIFT 7 | |
fe56b9e6 | 256 | u8 flags13; |
351a4ded YM |
257 | #define XSTORM_CORE_CONN_AG_CTX_RULE18EN_MASK 0x1 |
258 | #define XSTORM_CORE_CONN_AG_CTX_RULE18EN_SHIFT 0 | |
259 | #define XSTORM_CORE_CONN_AG_CTX_RULE19EN_MASK 0x1 | |
260 | #define XSTORM_CORE_CONN_AG_CTX_RULE19EN_SHIFT 1 | |
261 | #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 | |
262 | #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 | |
263 | #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 | |
264 | #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 | |
265 | #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 | |
266 | #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 | |
267 | #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 | |
268 | #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 | |
269 | #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 | |
270 | #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 | |
271 | #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 | |
272 | #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 | |
fe56b9e6 | 273 | u8 flags14; |
351a4ded YM |
274 | #define XSTORM_CORE_CONN_AG_CTX_BIT16_MASK 0x1 |
275 | #define XSTORM_CORE_CONN_AG_CTX_BIT16_SHIFT 0 | |
276 | #define XSTORM_CORE_CONN_AG_CTX_BIT17_MASK 0x1 | |
277 | #define XSTORM_CORE_CONN_AG_CTX_BIT17_SHIFT 1 | |
278 | #define XSTORM_CORE_CONN_AG_CTX_BIT18_MASK 0x1 | |
279 | #define XSTORM_CORE_CONN_AG_CTX_BIT18_SHIFT 2 | |
280 | #define XSTORM_CORE_CONN_AG_CTX_BIT19_MASK 0x1 | |
281 | #define XSTORM_CORE_CONN_AG_CTX_BIT19_SHIFT 3 | |
282 | #define XSTORM_CORE_CONN_AG_CTX_BIT20_MASK 0x1 | |
283 | #define XSTORM_CORE_CONN_AG_CTX_BIT20_SHIFT 4 | |
284 | #define XSTORM_CORE_CONN_AG_CTX_BIT21_MASK 0x1 | |
285 | #define XSTORM_CORE_CONN_AG_CTX_BIT21_SHIFT 5 | |
286 | #define XSTORM_CORE_CONN_AG_CTX_CF23_MASK 0x3 | |
287 | #define XSTORM_CORE_CONN_AG_CTX_CF23_SHIFT 6 | |
288 | u8 byte2; | |
289 | __le16 physical_q0; | |
290 | __le16 consolid_prod; | |
291 | __le16 reserved16; | |
292 | __le16 tx_bd_cons; | |
293 | __le16 tx_bd_or_spq_prod; | |
294 | __le16 word5; | |
295 | __le16 conn_dpi; | |
296 | u8 byte3; | |
297 | u8 byte4; | |
298 | u8 byte5; | |
299 | u8 byte6; | |
300 | __le32 reg0; | |
301 | __le32 reg1; | |
302 | __le32 reg2; | |
303 | __le32 reg3; | |
304 | __le32 reg4; | |
305 | __le32 reg5; | |
306 | __le32 reg6; | |
307 | __le16 word7; | |
308 | __le16 word8; | |
309 | __le16 word9; | |
310 | __le16 word10; | |
311 | __le32 reg7; | |
312 | __le32 reg8; | |
313 | __le32 reg9; | |
314 | u8 byte7; | |
315 | u8 byte8; | |
316 | u8 byte9; | |
317 | u8 byte10; | |
318 | u8 byte11; | |
319 | u8 byte12; | |
320 | u8 byte13; | |
321 | u8 byte14; | |
322 | u8 byte15; | |
323 | u8 byte16; | |
324 | __le16 word11; | |
325 | __le32 reg10; | |
326 | __le32 reg11; | |
327 | __le32 reg12; | |
328 | __le32 reg13; | |
329 | __le32 reg14; | |
330 | __le32 reg15; | |
331 | __le32 reg16; | |
332 | __le32 reg17; | |
333 | __le32 reg18; | |
334 | __le32 reg19; | |
335 | __le16 word12; | |
336 | __le16 word13; | |
337 | __le16 word14; | |
338 | __le16 word15; | |
fe56b9e6 YM |
339 | }; |
340 | ||
fc48b7a6 | 341 | struct tstorm_core_conn_ag_ctx { |
351a4ded YM |
342 | u8 byte0; |
343 | u8 byte1; | |
344 | u8 flags0; | |
345 | #define TSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 | |
346 | #define TSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0 | |
347 | #define TSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 | |
348 | #define TSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1 | |
349 | #define TSTORM_CORE_CONN_AG_CTX_BIT2_MASK 0x1 | |
350 | #define TSTORM_CORE_CONN_AG_CTX_BIT2_SHIFT 2 | |
351 | #define TSTORM_CORE_CONN_AG_CTX_BIT3_MASK 0x1 | |
352 | #define TSTORM_CORE_CONN_AG_CTX_BIT3_SHIFT 3 | |
353 | #define TSTORM_CORE_CONN_AG_CTX_BIT4_MASK 0x1 | |
354 | #define TSTORM_CORE_CONN_AG_CTX_BIT4_SHIFT 4 | |
355 | #define TSTORM_CORE_CONN_AG_CTX_BIT5_MASK 0x1 | |
356 | #define TSTORM_CORE_CONN_AG_CTX_BIT5_SHIFT 5 | |
357 | #define TSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 | |
358 | #define TSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 6 | |
fc48b7a6 | 359 | u8 flags1; |
351a4ded YM |
360 | #define TSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 |
361 | #define TSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 0 | |
362 | #define TSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 | |
363 | #define TSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 2 | |
364 | #define TSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3 | |
365 | #define TSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 4 | |
366 | #define TSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3 | |
367 | #define TSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 6 | |
fc48b7a6 | 368 | u8 flags2; |
351a4ded YM |
369 | #define TSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3 |
370 | #define TSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 0 | |
371 | #define TSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3 | |
372 | #define TSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 2 | |
373 | #define TSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3 | |
374 | #define TSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 4 | |
375 | #define TSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3 | |
376 | #define TSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 6 | |
fc48b7a6 | 377 | u8 flags3; |
351a4ded YM |
378 | #define TSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3 |
379 | #define TSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 0 | |
380 | #define TSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3 | |
381 | #define TSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 2 | |
382 | #define TSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 | |
383 | #define TSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 4 | |
384 | #define TSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 | |
385 | #define TSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 5 | |
386 | #define TSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 | |
387 | #define TSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 6 | |
388 | #define TSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1 | |
389 | #define TSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 7 | |
fc48b7a6 | 390 | u8 flags4; |
351a4ded YM |
391 | #define TSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1 |
392 | #define TSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 0 | |
393 | #define TSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1 | |
394 | #define TSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 1 | |
395 | #define TSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1 | |
396 | #define TSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 2 | |
397 | #define TSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1 | |
398 | #define TSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 3 | |
399 | #define TSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1 | |
400 | #define TSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 4 | |
401 | #define TSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1 | |
402 | #define TSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 5 | |
403 | #define TSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1 | |
404 | #define TSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 6 | |
405 | #define TSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 | |
406 | #define TSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7 | |
fc48b7a6 | 407 | u8 flags5; |
351a4ded YM |
408 | #define TSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 |
409 | #define TSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0 | |
410 | #define TSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 | |
411 | #define TSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1 | |
412 | #define TSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 | |
413 | #define TSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2 | |
414 | #define TSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 | |
415 | #define TSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3 | |
416 | #define TSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1 | |
417 | #define TSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4 | |
418 | #define TSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1 | |
419 | #define TSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5 | |
420 | #define TSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1 | |
421 | #define TSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6 | |
422 | #define TSTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1 | |
423 | #define TSTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7 | |
424 | __le32 reg0; | |
425 | __le32 reg1; | |
426 | __le32 reg2; | |
427 | __le32 reg3; | |
428 | __le32 reg4; | |
429 | __le32 reg5; | |
430 | __le32 reg6; | |
431 | __le32 reg7; | |
432 | __le32 reg8; | |
433 | u8 byte2; | |
434 | u8 byte3; | |
435 | __le16 word0; | |
436 | u8 byte4; | |
437 | u8 byte5; | |
438 | __le16 word1; | |
439 | __le16 word2; | |
440 | __le16 word3; | |
441 | __le32 reg9; | |
442 | __le32 reg10; | |
fc48b7a6 YM |
443 | }; |
444 | ||
445 | struct ustorm_core_conn_ag_ctx { | |
351a4ded YM |
446 | u8 reserved; |
447 | u8 byte1; | |
448 | u8 flags0; | |
449 | #define USTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 | |
450 | #define USTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0 | |
451 | #define USTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 | |
452 | #define USTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1 | |
453 | #define USTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 | |
454 | #define USTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2 | |
455 | #define USTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 | |
456 | #define USTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4 | |
457 | #define USTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 | |
458 | #define USTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6 | |
fc48b7a6 | 459 | u8 flags1; |
351a4ded YM |
460 | #define USTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3 |
461 | #define USTORM_CORE_CONN_AG_CTX_CF3_SHIFT 0 | |
462 | #define USTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3 | |
463 | #define USTORM_CORE_CONN_AG_CTX_CF4_SHIFT 2 | |
464 | #define USTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3 | |
465 | #define USTORM_CORE_CONN_AG_CTX_CF5_SHIFT 4 | |
466 | #define USTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3 | |
467 | #define USTORM_CORE_CONN_AG_CTX_CF6_SHIFT 6 | |
fc48b7a6 | 468 | u8 flags2; |
351a4ded YM |
469 | #define USTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 |
470 | #define USTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0 | |
471 | #define USTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 | |
472 | #define USTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1 | |
473 | #define USTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 | |
474 | #define USTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2 | |
475 | #define USTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1 | |
476 | #define USTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 3 | |
477 | #define USTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1 | |
478 | #define USTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 4 | |
479 | #define USTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1 | |
480 | #define USTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 5 | |
481 | #define USTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1 | |
482 | #define USTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 6 | |
483 | #define USTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 | |
484 | #define USTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7 | |
fc48b7a6 | 485 | u8 flags3; |
351a4ded YM |
486 | #define USTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 |
487 | #define USTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0 | |
488 | #define USTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 | |
489 | #define USTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1 | |
490 | #define USTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 | |
491 | #define USTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2 | |
492 | #define USTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 | |
493 | #define USTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3 | |
494 | #define USTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1 | |
495 | #define USTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4 | |
496 | #define USTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1 | |
497 | #define USTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5 | |
498 | #define USTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1 | |
499 | #define USTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6 | |
500 | #define USTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1 | |
501 | #define USTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7 | |
502 | u8 byte2; | |
503 | u8 byte3; | |
504 | __le16 word0; | |
505 | __le16 word1; | |
506 | __le32 rx_producers; | |
507 | __le32 reg1; | |
508 | __le32 reg2; | |
509 | __le32 reg3; | |
510 | __le16 word2; | |
511 | __le16 word3; | |
fc48b7a6 YM |
512 | }; |
513 | ||
fe56b9e6 YM |
514 | /* The core storm context for the Mstorm */ |
515 | struct mstorm_core_conn_st_ctx { | |
516 | __le32 reserved[24]; | |
517 | }; | |
518 | ||
519 | /* The core storm context for the Ustorm */ | |
520 | struct ustorm_core_conn_st_ctx { | |
521 | __le32 reserved[4]; | |
522 | }; | |
523 | ||
524 | /* core connection context */ | |
525 | struct core_conn_context { | |
351a4ded YM |
526 | struct ystorm_core_conn_st_ctx ystorm_st_context; |
527 | struct regpair ystorm_st_padding[2]; | |
528 | struct pstorm_core_conn_st_ctx pstorm_st_context; | |
529 | struct regpair pstorm_st_padding[2]; | |
530 | struct xstorm_core_conn_st_ctx xstorm_st_context; | |
531 | struct xstorm_core_conn_ag_ctx xstorm_ag_context; | |
532 | struct tstorm_core_conn_ag_ctx tstorm_ag_context; | |
533 | struct ustorm_core_conn_ag_ctx ustorm_ag_context; | |
534 | struct mstorm_core_conn_st_ctx mstorm_st_context; | |
535 | struct ustorm_core_conn_st_ctx ustorm_st_context; | |
536 | struct regpair ustorm_st_padding[2]; | |
537 | }; | |
538 | ||
05fafbfb YM |
539 | enum core_error_handle { |
540 | LL2_DROP_PACKET, | |
541 | LL2_DO_NOTHING, | |
542 | LL2_ASSERT, | |
543 | MAX_CORE_ERROR_HANDLE | |
544 | }; | |
545 | ||
546 | enum core_event_opcode { | |
547 | CORE_EVENT_TX_QUEUE_START, | |
548 | CORE_EVENT_TX_QUEUE_STOP, | |
549 | CORE_EVENT_RX_QUEUE_START, | |
550 | CORE_EVENT_RX_QUEUE_STOP, | |
551 | MAX_CORE_EVENT_OPCODE | |
552 | }; | |
553 | ||
554 | enum core_l4_pseudo_checksum_mode { | |
555 | CORE_L4_PSEUDO_CSUM_CORRECT_LENGTH, | |
556 | CORE_L4_PSEUDO_CSUM_ZERO_LENGTH, | |
557 | MAX_CORE_L4_PSEUDO_CHECKSUM_MODE | |
558 | }; | |
559 | ||
560 | struct core_ll2_port_stats { | |
561 | struct regpair gsi_invalid_hdr; | |
562 | struct regpair gsi_invalid_pkt_length; | |
563 | struct regpair gsi_unsupported_pkt_typ; | |
564 | struct regpair gsi_crcchksm_error; | |
565 | }; | |
566 | ||
567 | struct core_ll2_pstorm_per_queue_stat { | |
568 | struct regpair sent_ucast_bytes; | |
569 | struct regpair sent_mcast_bytes; | |
570 | struct regpair sent_bcast_bytes; | |
571 | struct regpair sent_ucast_pkts; | |
572 | struct regpair sent_mcast_pkts; | |
573 | struct regpair sent_bcast_pkts; | |
574 | }; | |
575 | ||
576 | struct core_ll2_rx_prod { | |
577 | __le16 bd_prod; | |
578 | __le16 cqe_prod; | |
579 | __le32 reserved; | |
580 | }; | |
581 | ||
582 | struct core_ll2_tstorm_per_queue_stat { | |
583 | struct regpair packet_too_big_discard; | |
584 | struct regpair no_buff_discard; | |
585 | }; | |
586 | ||
587 | struct core_ll2_ustorm_per_queue_stat { | |
588 | struct regpair rcv_ucast_bytes; | |
589 | struct regpair rcv_mcast_bytes; | |
590 | struct regpair rcv_bcast_bytes; | |
591 | struct regpair rcv_ucast_pkts; | |
592 | struct regpair rcv_mcast_pkts; | |
593 | struct regpair rcv_bcast_pkts; | |
594 | }; | |
595 | ||
596 | enum core_ramrod_cmd_id { | |
597 | CORE_RAMROD_UNUSED, | |
598 | CORE_RAMROD_RX_QUEUE_START, | |
599 | CORE_RAMROD_TX_QUEUE_START, | |
600 | CORE_RAMROD_RX_QUEUE_STOP, | |
601 | CORE_RAMROD_TX_QUEUE_STOP, | |
602 | MAX_CORE_RAMROD_CMD_ID | |
603 | }; | |
604 | ||
605 | enum core_roce_flavor_type { | |
606 | CORE_ROCE, | |
607 | CORE_RROCE, | |
608 | MAX_CORE_ROCE_FLAVOR_TYPE | |
609 | }; | |
610 | ||
611 | struct core_rx_action_on_error { | |
612 | u8 error_type; | |
613 | #define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_MASK 0x3 | |
614 | #define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_SHIFT 0 | |
615 | #define CORE_RX_ACTION_ON_ERROR_NO_BUFF_MASK 0x3 | |
616 | #define CORE_RX_ACTION_ON_ERROR_NO_BUFF_SHIFT 2 | |
617 | #define CORE_RX_ACTION_ON_ERROR_RESERVED_MASK 0xF | |
618 | #define CORE_RX_ACTION_ON_ERROR_RESERVED_SHIFT 4 | |
619 | }; | |
620 | ||
621 | struct core_rx_bd { | |
622 | struct regpair addr; | |
623 | __le16 reserved[4]; | |
624 | }; | |
625 | ||
626 | struct core_rx_bd_with_buff_len { | |
627 | struct regpair addr; | |
628 | __le16 buff_length; | |
629 | __le16 reserved[3]; | |
630 | }; | |
631 | ||
632 | union core_rx_bd_union { | |
633 | struct core_rx_bd rx_bd; | |
634 | struct core_rx_bd_with_buff_len rx_bd_with_len; | |
635 | }; | |
636 | ||
637 | struct core_rx_cqe_opaque_data { | |
638 | __le32 data[2]; | |
639 | }; | |
640 | ||
641 | enum core_rx_cqe_type { | |
642 | CORE_RX_CQE_ILLIGAL_TYPE, | |
643 | CORE_RX_CQE_TYPE_REGULAR, | |
644 | CORE_RX_CQE_TYPE_GSI_OFFLOAD, | |
645 | CORE_RX_CQE_TYPE_SLOW_PATH, | |
646 | MAX_CORE_RX_CQE_TYPE | |
647 | }; | |
648 | ||
649 | struct core_rx_fast_path_cqe { | |
650 | u8 type; | |
651 | u8 placement_offset; | |
652 | struct parsing_and_err_flags parse_flags; | |
653 | __le16 packet_length; | |
654 | __le16 vlan; | |
655 | struct core_rx_cqe_opaque_data opaque_data; | |
656 | __le32 reserved[4]; | |
657 | }; | |
658 | ||
659 | struct core_rx_gsi_offload_cqe { | |
660 | u8 type; | |
661 | u8 data_length_error; | |
662 | struct parsing_and_err_flags parse_flags; | |
663 | __le16 data_length; | |
664 | __le16 vlan; | |
665 | __le32 src_mac_addrhi; | |
666 | __le16 src_mac_addrlo; | |
667 | u8 reserved1[2]; | |
668 | __le32 gid_dst[4]; | |
669 | }; | |
670 | ||
671 | struct core_rx_slow_path_cqe { | |
672 | u8 type; | |
673 | u8 ramrod_cmd_id; | |
674 | __le16 echo; | |
675 | __le32 reserved1[7]; | |
676 | }; | |
677 | ||
678 | union core_rx_cqe_union { | |
679 | struct core_rx_fast_path_cqe rx_cqe_fp; | |
680 | struct core_rx_gsi_offload_cqe rx_cqe_gsi; | |
681 | struct core_rx_slow_path_cqe rx_cqe_sp; | |
682 | }; | |
683 | ||
684 | struct core_rx_start_ramrod_data { | |
685 | struct regpair bd_base; | |
686 | struct regpair cqe_pbl_addr; | |
687 | __le16 mtu; | |
688 | __le16 sb_id; | |
689 | u8 sb_index; | |
690 | u8 complete_cqe_flg; | |
691 | u8 complete_event_flg; | |
692 | u8 drop_ttl0_flg; | |
693 | __le16 num_of_pbl_pages; | |
694 | u8 inner_vlan_removal_en; | |
695 | u8 queue_id; | |
696 | u8 main_func_queue; | |
697 | u8 mf_si_bcast_accept_all; | |
698 | u8 mf_si_mcast_accept_all; | |
699 | struct core_rx_action_on_error action_on_error; | |
700 | u8 gsi_offload_flag; | |
701 | u8 reserved[7]; | |
702 | }; | |
703 | ||
704 | struct core_rx_stop_ramrod_data { | |
705 | u8 complete_cqe_flg; | |
706 | u8 complete_event_flg; | |
707 | u8 queue_id; | |
708 | u8 reserved1; | |
709 | __le16 reserved2[2]; | |
710 | }; | |
711 | ||
712 | struct core_tx_bd_flags { | |
713 | u8 as_bitfield; | |
714 | #define CORE_TX_BD_FLAGS_FORCE_VLAN_MODE_MASK 0x1 | |
715 | #define CORE_TX_BD_FLAGS_FORCE_VLAN_MODE_SHIFT 0 | |
716 | #define CORE_TX_BD_FLAGS_VLAN_INSERTION_MASK 0x1 | |
717 | #define CORE_TX_BD_FLAGS_VLAN_INSERTION_SHIFT 1 | |
718 | #define CORE_TX_BD_FLAGS_START_BD_MASK 0x1 | |
719 | #define CORE_TX_BD_FLAGS_START_BD_SHIFT 2 | |
720 | #define CORE_TX_BD_FLAGS_IP_CSUM_MASK 0x1 | |
721 | #define CORE_TX_BD_FLAGS_IP_CSUM_SHIFT 3 | |
722 | #define CORE_TX_BD_FLAGS_L4_CSUM_MASK 0x1 | |
723 | #define CORE_TX_BD_FLAGS_L4_CSUM_SHIFT 4 | |
724 | #define CORE_TX_BD_FLAGS_IPV6_EXT_MASK 0x1 | |
725 | #define CORE_TX_BD_FLAGS_IPV6_EXT_SHIFT 5 | |
726 | #define CORE_TX_BD_FLAGS_L4_PROTOCOL_MASK 0x1 | |
727 | #define CORE_TX_BD_FLAGS_L4_PROTOCOL_SHIFT 6 | |
728 | #define CORE_TX_BD_FLAGS_L4_PSEUDO_CSUM_MODE_MASK 0x1 | |
729 | #define CORE_TX_BD_FLAGS_L4_PSEUDO_CSUM_MODE_SHIFT 7 | |
abd49676 RA |
730 | #define CORE_TX_BD_FLAGS_ROCE_FLAV_MASK 0x1 |
731 | #define CORE_TX_BD_FLAGS_ROCE_FLAV_SHIFT 12 | |
732 | ||
05fafbfb YM |
733 | }; |
734 | ||
735 | struct core_tx_bd { | |
736 | struct regpair addr; | |
737 | __le16 nbytes; | |
738 | __le16 nw_vlan_or_lb_echo; | |
739 | u8 bitfield0; | |
740 | #define CORE_TX_BD_NBDS_MASK 0xF | |
741 | #define CORE_TX_BD_NBDS_SHIFT 0 | |
742 | #define CORE_TX_BD_ROCE_FLAV_MASK 0x1 | |
743 | #define CORE_TX_BD_ROCE_FLAV_SHIFT 4 | |
744 | #define CORE_TX_BD_RESERVED0_MASK 0x7 | |
745 | #define CORE_TX_BD_RESERVED0_SHIFT 5 | |
746 | struct core_tx_bd_flags bd_flags; | |
747 | __le16 bitfield1; | |
748 | #define CORE_TX_BD_L4_HDR_OFFSET_W_MASK 0x3FFF | |
749 | #define CORE_TX_BD_L4_HDR_OFFSET_W_SHIFT 0 | |
750 | #define CORE_TX_BD_TX_DST_MASK 0x1 | |
751 | #define CORE_TX_BD_TX_DST_SHIFT 14 | |
752 | #define CORE_TX_BD_RESERVED1_MASK 0x1 | |
753 | #define CORE_TX_BD_RESERVED1_SHIFT 15 | |
754 | }; | |
755 | ||
756 | enum core_tx_dest { | |
757 | CORE_TX_DEST_NW, | |
758 | CORE_TX_DEST_LB, | |
759 | MAX_CORE_TX_DEST | |
760 | }; | |
761 | ||
762 | struct core_tx_start_ramrod_data { | |
763 | struct regpair pbl_base_addr; | |
764 | __le16 mtu; | |
765 | __le16 sb_id; | |
766 | u8 sb_index; | |
767 | u8 stats_en; | |
768 | u8 stats_id; | |
769 | u8 conn_type; | |
770 | __le16 pbl_size; | |
771 | __le16 qm_pq_id; | |
772 | u8 gsi_offload_flag; | |
773 | u8 resrved[3]; | |
774 | }; | |
775 | ||
776 | struct core_tx_stop_ramrod_data { | |
777 | __le32 reserved0[2]; | |
778 | }; | |
779 | ||
351a4ded YM |
780 | struct eth_mstorm_per_pf_stat { |
781 | struct regpair gre_discard_pkts; | |
782 | struct regpair vxlan_discard_pkts; | |
783 | struct regpair geneve_discard_pkts; | |
784 | struct regpair lb_discard_pkts; | |
fe56b9e6 YM |
785 | }; |
786 | ||
9df2ed04 | 787 | struct eth_mstorm_per_queue_stat { |
351a4ded YM |
788 | struct regpair ttl0_discard; |
789 | struct regpair packet_too_big_discard; | |
790 | struct regpair no_buff_discard; | |
791 | struct regpair not_active_discard; | |
792 | struct regpair tpa_coalesced_pkts; | |
793 | struct regpair tpa_coalesced_events; | |
794 | struct regpair tpa_aborts_num; | |
795 | struct regpair tpa_coalesced_bytes; | |
796 | }; | |
797 | ||
798 | /* Ethernet TX Per PF */ | |
799 | struct eth_pstorm_per_pf_stat { | |
800 | struct regpair sent_lb_ucast_bytes; | |
801 | struct regpair sent_lb_mcast_bytes; | |
802 | struct regpair sent_lb_bcast_bytes; | |
803 | struct regpair sent_lb_ucast_pkts; | |
804 | struct regpair sent_lb_mcast_pkts; | |
805 | struct regpair sent_lb_bcast_pkts; | |
806 | struct regpair sent_gre_bytes; | |
807 | struct regpair sent_vxlan_bytes; | |
808 | struct regpair sent_geneve_bytes; | |
809 | struct regpair sent_gre_pkts; | |
810 | struct regpair sent_vxlan_pkts; | |
811 | struct regpair sent_geneve_pkts; | |
812 | struct regpair gre_drop_pkts; | |
813 | struct regpair vxlan_drop_pkts; | |
814 | struct regpair geneve_drop_pkts; | |
815 | }; | |
816 | ||
817 | /* Ethernet TX Per Queue Stats */ | |
818 | struct eth_pstorm_per_queue_stat { | |
819 | struct regpair sent_ucast_bytes; | |
820 | struct regpair sent_mcast_bytes; | |
821 | struct regpair sent_bcast_bytes; | |
822 | struct regpair sent_ucast_pkts; | |
823 | struct regpair sent_mcast_pkts; | |
824 | struct regpair sent_bcast_pkts; | |
825 | struct regpair error_drop_pkts; | |
826 | }; | |
827 | ||
828 | /* ETH Rx producers data */ | |
829 | struct eth_rx_rate_limit { | |
830 | __le16 mult; | |
831 | __le16 cnst; | |
832 | u8 add_sub_cnst; | |
833 | u8 reserved0; | |
834 | __le16 reserved1; | |
9df2ed04 MC |
835 | }; |
836 | ||
351a4ded YM |
837 | struct eth_ustorm_per_pf_stat { |
838 | struct regpair rcv_lb_ucast_bytes; | |
839 | struct regpair rcv_lb_mcast_bytes; | |
840 | struct regpair rcv_lb_bcast_bytes; | |
841 | struct regpair rcv_lb_ucast_pkts; | |
842 | struct regpair rcv_lb_mcast_pkts; | |
843 | struct regpair rcv_lb_bcast_pkts; | |
844 | struct regpair rcv_gre_bytes; | |
845 | struct regpair rcv_vxlan_bytes; | |
846 | struct regpair rcv_geneve_bytes; | |
847 | struct regpair rcv_gre_pkts; | |
848 | struct regpair rcv_vxlan_pkts; | |
849 | struct regpair rcv_geneve_pkts; | |
9df2ed04 MC |
850 | }; |
851 | ||
852 | struct eth_ustorm_per_queue_stat { | |
351a4ded YM |
853 | struct regpair rcv_ucast_bytes; |
854 | struct regpair rcv_mcast_bytes; | |
855 | struct regpair rcv_bcast_bytes; | |
856 | struct regpair rcv_ucast_pkts; | |
857 | struct regpair rcv_mcast_pkts; | |
858 | struct regpair rcv_bcast_pkts; | |
9df2ed04 MC |
859 | }; |
860 | ||
fe56b9e6 YM |
861 | /* Event Ring Next Page Address */ |
862 | struct event_ring_next_addr { | |
351a4ded YM |
863 | struct regpair addr; |
864 | __le32 reserved[2]; | |
fe56b9e6 YM |
865 | }; |
866 | ||
351a4ded | 867 | /* Event Ring Element */ |
fe56b9e6 | 868 | union event_ring_element { |
351a4ded YM |
869 | struct event_ring_entry entry; |
870 | struct event_ring_next_addr next_addr; | |
871 | }; | |
872 | ||
873 | /* Major and Minor hsi Versions */ | |
874 | struct hsi_fp_ver_struct { | |
875 | u8 minor_ver_arr[2]; | |
876 | u8 major_ver_arr[2]; | |
fe56b9e6 YM |
877 | }; |
878 | ||
351a4ded | 879 | /* Mstorm non-triggering VF zone */ |
05fafbfb YM |
880 | enum malicious_vf_error_id { |
881 | MALICIOUS_VF_NO_ERROR, | |
882 | VF_PF_CHANNEL_NOT_READY, | |
883 | VF_ZONE_MSG_NOT_VALID, | |
884 | VF_ZONE_FUNC_NOT_ENABLED, | |
885 | ETH_PACKET_TOO_SMALL, | |
886 | ETH_ILLEGAL_VLAN_MODE, | |
887 | ETH_MTU_VIOLATION, | |
888 | ETH_ILLEGAL_INBAND_TAGS, | |
889 | ETH_VLAN_INSERT_AND_INBAND_VLAN, | |
890 | ETH_ILLEGAL_NBDS, | |
891 | ETH_FIRST_BD_WO_SOP, | |
892 | ETH_INSUFFICIENT_BDS, | |
893 | ETH_ILLEGAL_LSO_HDR_NBDS, | |
894 | ETH_ILLEGAL_LSO_MSS, | |
895 | ETH_ZERO_SIZE_BD, | |
896 | ETH_ILLEGAL_LSO_HDR_LEN, | |
897 | ETH_INSUFFICIENT_PAYLOAD, | |
898 | ETH_EDPM_OUT_OF_SYNC, | |
899 | ETH_TUNN_IPV6_EXT_NBD_ERR, | |
900 | ETH_CONTROL_PACKET_VIOLATION, | |
901 | MAX_MALICIOUS_VF_ERROR_ID | |
902 | }; | |
903 | ||
1408cc1f YM |
904 | struct mstorm_non_trigger_vf_zone { |
905 | struct eth_mstorm_per_queue_stat eth_queue_stat; | |
05fafbfb | 906 | struct eth_rx_prod_data eth_rx_queue_producers[ETH_MAX_NUM_RX_QUEUES_PER_VF_QUAD]; |
1408cc1f YM |
907 | }; |
908 | ||
351a4ded | 909 | /* Mstorm VF zone */ |
1408cc1f YM |
910 | struct mstorm_vf_zone { |
911 | struct mstorm_non_trigger_vf_zone non_trigger; | |
351a4ded | 912 | |
1408cc1f YM |
913 | }; |
914 | ||
351a4ded | 915 | /* personality per PF */ |
fe56b9e6 | 916 | enum personality_type { |
fc48b7a6 | 917 | BAD_PERSONALITY_TYP, |
c5ac9319 | 918 | PERSONALITY_ISCSI, |
fe56b9e6 | 919 | PERSONALITY_RESERVED2, |
351a4ded | 920 | PERSONALITY_RDMA_AND_ETH, |
fe56b9e6 | 921 | PERSONALITY_RESERVED3, |
fc48b7a6 | 922 | PERSONALITY_CORE, |
351a4ded | 923 | PERSONALITY_ETH, |
fe56b9e6 YM |
924 | PERSONALITY_RESERVED4, |
925 | MAX_PERSONALITY_TYPE | |
926 | }; | |
927 | ||
351a4ded | 928 | /* tunnel configuration */ |
fe56b9e6 | 929 | struct pf_start_tunnel_config { |
351a4ded YM |
930 | u8 set_vxlan_udp_port_flg; |
931 | u8 set_geneve_udp_port_flg; | |
932 | u8 tx_enable_vxlan; | |
933 | u8 tx_enable_l2geneve; | |
934 | u8 tx_enable_ipgeneve; | |
935 | u8 tx_enable_l2gre; | |
936 | u8 tx_enable_ipgre; | |
937 | u8 tunnel_clss_vxlan; | |
938 | u8 tunnel_clss_l2geneve; | |
939 | u8 tunnel_clss_ipgeneve; | |
940 | u8 tunnel_clss_l2gre; | |
941 | u8 tunnel_clss_ipgre; | |
942 | __le16 vxlan_udp_port; | |
943 | __le16 geneve_udp_port; | |
fe56b9e6 YM |
944 | }; |
945 | ||
946 | /* Ramrod data for PF start ramrod */ | |
947 | struct pf_start_ramrod_data { | |
351a4ded YM |
948 | struct regpair event_ring_pbl_addr; |
949 | struct regpair consolid_q_pbl_addr; | |
950 | struct pf_start_tunnel_config tunnel_config; | |
951 | __le16 event_ring_sb_id; | |
952 | u8 base_vf_id; | |
953 | u8 num_vfs; | |
954 | u8 event_ring_num_pages; | |
955 | u8 event_ring_sb_index; | |
956 | u8 path_id; | |
957 | u8 warning_as_error; | |
958 | u8 dont_log_ramrods; | |
959 | u8 personality; | |
960 | __le16 log_type_mask; | |
961 | u8 mf_mode; | |
962 | u8 integ_phase; | |
963 | u8 allow_npar_tx_switching; | |
964 | u8 inner_to_outer_pri_map[8]; | |
965 | u8 pri_map_valid; | |
966 | __le32 outer_tag; | |
967 | struct hsi_fp_ver_struct hsi_fp_ver; | |
968 | ||
969 | }; | |
970 | ||
39651abd SRK |
971 | struct protocol_dcb_data { |
972 | u8 dcb_enable_flag; | |
05fafbfb | 973 | u8 reserved_a; |
39651abd SRK |
974 | u8 dcb_priority; |
975 | u8 dcb_tc; | |
05fafbfb YM |
976 | u8 reserved_b; |
977 | u8 reserved0; | |
39651abd SRK |
978 | }; |
979 | ||
464f6645 | 980 | struct pf_update_tunnel_config { |
351a4ded | 981 | u8 update_rx_pf_clss; |
05fafbfb YM |
982 | u8 update_rx_def_ucast_clss; |
983 | u8 update_rx_def_non_ucast_clss; | |
351a4ded YM |
984 | u8 update_tx_pf_clss; |
985 | u8 set_vxlan_udp_port_flg; | |
986 | u8 set_geneve_udp_port_flg; | |
987 | u8 tx_enable_vxlan; | |
988 | u8 tx_enable_l2geneve; | |
989 | u8 tx_enable_ipgeneve; | |
990 | u8 tx_enable_l2gre; | |
991 | u8 tx_enable_ipgre; | |
992 | u8 tunnel_clss_vxlan; | |
993 | u8 tunnel_clss_l2geneve; | |
994 | u8 tunnel_clss_ipgeneve; | |
995 | u8 tunnel_clss_l2gre; | |
996 | u8 tunnel_clss_ipgre; | |
997 | __le16 vxlan_udp_port; | |
998 | __le16 geneve_udp_port; | |
05fafbfb | 999 | __le16 reserved[2]; |
464f6645 MC |
1000 | }; |
1001 | ||
1002 | struct pf_update_ramrod_data { | |
39651abd SRK |
1003 | u8 pf_id; |
1004 | u8 update_eth_dcb_data_flag; | |
1005 | u8 update_fcoe_dcb_data_flag; | |
1006 | u8 update_iscsi_dcb_data_flag; | |
1007 | u8 update_roce_dcb_data_flag; | |
05fafbfb | 1008 | u8 update_rroce_dcb_data_flag; |
351a4ded | 1009 | u8 update_iwarp_dcb_data_flag; |
39651abd | 1010 | u8 update_mf_vlan_flag; |
39651abd SRK |
1011 | struct protocol_dcb_data eth_dcb_data; |
1012 | struct protocol_dcb_data fcoe_dcb_data; | |
1013 | struct protocol_dcb_data iscsi_dcb_data; | |
1014 | struct protocol_dcb_data roce_dcb_data; | |
05fafbfb | 1015 | struct protocol_dcb_data rroce_dcb_data; |
351a4ded YM |
1016 | struct protocol_dcb_data iwarp_dcb_data; |
1017 | __le16 mf_vlan; | |
05fafbfb | 1018 | __le16 reserved; |
351a4ded | 1019 | struct pf_update_tunnel_config tunnel_config; |
464f6645 MC |
1020 | }; |
1021 | ||
351a4ded | 1022 | /* Ports mode */ |
fe56b9e6 | 1023 | enum ports_mode { |
351a4ded YM |
1024 | ENGX2_PORTX1, |
1025 | ENGX2_PORTX2, | |
1026 | ENGX1_PORTX1, | |
1027 | ENGX1_PORTX2, | |
1028 | ENGX1_PORTX4, | |
fe56b9e6 YM |
1029 | MAX_PORTS_MODE |
1030 | }; | |
1031 | ||
351a4ded YM |
1032 | /* use to index in hsi_fp_[major|minor]_ver_arr per protocol */ |
1033 | enum protocol_version_array_key { | |
1034 | ETH_VER_KEY = 0, | |
1035 | ROCE_VER_KEY, | |
1036 | MAX_PROTOCOL_VERSION_ARRAY_KEY | |
1037 | }; | |
1038 | ||
05fafbfb YM |
1039 | struct rdma_sent_stats { |
1040 | struct regpair sent_bytes; | |
1041 | struct regpair sent_pkts; | |
1042 | }; | |
1043 | ||
1408cc1f YM |
1044 | struct pstorm_non_trigger_vf_zone { |
1045 | struct eth_pstorm_per_queue_stat eth_queue_stat; | |
05fafbfb | 1046 | struct rdma_sent_stats rdma_stats; |
1408cc1f YM |
1047 | }; |
1048 | ||
351a4ded | 1049 | /* Pstorm VF zone */ |
1408cc1f YM |
1050 | struct pstorm_vf_zone { |
1051 | struct pstorm_non_trigger_vf_zone non_trigger; | |
1052 | struct regpair reserved[7]; | |
1053 | }; | |
1054 | ||
fe56b9e6 YM |
1055 | /* Ramrod Header of SPQE */ |
1056 | struct ramrod_header { | |
351a4ded YM |
1057 | __le32 cid; |
1058 | u8 cmd_id; | |
1059 | u8 protocol_id; | |
1060 | __le16 echo; | |
fe56b9e6 YM |
1061 | }; |
1062 | ||
05fafbfb YM |
1063 | struct rdma_rcv_stats { |
1064 | struct regpair rcv_bytes; | |
1065 | struct regpair rcv_pkts; | |
1066 | }; | |
1067 | ||
fe56b9e6 | 1068 | struct slow_path_element { |
351a4ded YM |
1069 | struct ramrod_header hdr; |
1070 | struct regpair data_ptr; | |
1071 | }; | |
1072 | ||
1073 | /* Tstorm non-triggering VF zone */ | |
1074 | struct tstorm_non_trigger_vf_zone { | |
05fafbfb | 1075 | struct rdma_rcv_stats rdma_stats; |
fe56b9e6 YM |
1076 | }; |
1077 | ||
1078 | struct tstorm_per_port_stat { | |
351a4ded YM |
1079 | struct regpair trunc_error_discard; |
1080 | struct regpair mac_error_discard; | |
1081 | struct regpair mftag_filter_discard; | |
1082 | struct regpair eth_mac_filter_discard; | |
05fafbfb YM |
1083 | struct regpair ll2_mac_filter_discard; |
1084 | struct regpair ll2_conn_disabled_discard; | |
1085 | struct regpair iscsi_irregular_pkt; | |
1086 | struct regpair reserved; | |
1087 | struct regpair roce_irregular_pkt; | |
351a4ded | 1088 | struct regpair eth_irregular_pkt; |
05fafbfb YM |
1089 | struct regpair reserved1; |
1090 | struct regpair preroce_irregular_pkt; | |
351a4ded YM |
1091 | struct regpair eth_gre_tunn_filter_discard; |
1092 | struct regpair eth_vxlan_tunn_filter_discard; | |
1093 | struct regpair eth_geneve_tunn_filter_discard; | |
fe56b9e6 YM |
1094 | }; |
1095 | ||
351a4ded YM |
1096 | /* Tstorm VF zone */ |
1097 | struct tstorm_vf_zone { | |
1098 | struct tstorm_non_trigger_vf_zone non_trigger; | |
1099 | }; | |
1100 | ||
1101 | /* Tunnel classification scheme */ | |
1102 | enum tunnel_clss { | |
1103 | TUNNEL_CLSS_MAC_VLAN = 0, | |
1104 | TUNNEL_CLSS_MAC_VNI, | |
1105 | TUNNEL_CLSS_INNER_MAC_VLAN, | |
1106 | TUNNEL_CLSS_INNER_MAC_VNI, | |
1107 | TUNNEL_CLSS_MAC_VLAN_DUAL_STAGE, | |
1108 | MAX_TUNNEL_CLSS | |
1109 | }; | |
1110 | ||
1111 | /* Ustorm non-triggering VF zone */ | |
1408cc1f YM |
1112 | struct ustorm_non_trigger_vf_zone { |
1113 | struct eth_ustorm_per_queue_stat eth_queue_stat; | |
1114 | struct regpair vf_pf_msg_addr; | |
1115 | }; | |
1116 | ||
351a4ded | 1117 | /* Ustorm triggering VF zone */ |
1408cc1f YM |
1118 | struct ustorm_trigger_vf_zone { |
1119 | u8 vf_pf_msg_valid; | |
1120 | u8 reserved[7]; | |
1121 | }; | |
1122 | ||
351a4ded | 1123 | /* Ustorm VF zone */ |
1408cc1f YM |
1124 | struct ustorm_vf_zone { |
1125 | struct ustorm_non_trigger_vf_zone non_trigger; | |
1126 | struct ustorm_trigger_vf_zone trigger; | |
1127 | }; | |
1128 | ||
351a4ded YM |
1129 | /* VF-PF channel data */ |
1130 | struct vf_pf_channel_data { | |
1131 | __le32 ready; | |
1132 | u8 valid; | |
1133 | u8 reserved0; | |
1134 | __le16 reserved1; | |
1135 | }; | |
1136 | ||
1137 | /* Ramrod data for VF start ramrod */ | |
1408cc1f YM |
1138 | struct vf_start_ramrod_data { |
1139 | u8 vf_id; | |
1140 | u8 enable_flr_ack; | |
1141 | __le16 opaque_fid; | |
1142 | u8 personality; | |
351a4ded YM |
1143 | u8 reserved[7]; |
1144 | struct hsi_fp_ver_struct hsi_fp_ver; | |
1145 | ||
1408cc1f YM |
1146 | }; |
1147 | ||
351a4ded | 1148 | /* Ramrod data for VF start ramrod */ |
0b55e27d YM |
1149 | struct vf_stop_ramrod_data { |
1150 | u8 vf_id; | |
1151 | u8 reserved0; | |
1152 | __le16 reserved1; | |
1153 | __le32 reserved2; | |
1154 | }; | |
1155 | ||
05fafbfb YM |
1156 | enum vf_zone_size_mode { |
1157 | VF_ZONE_SIZE_MODE_DEFAULT, | |
1158 | VF_ZONE_SIZE_MODE_DOUBLE, | |
1159 | VF_ZONE_SIZE_MODE_QUAD, | |
1160 | MAX_VF_ZONE_SIZE_MODE | |
1161 | }; | |
1162 | ||
fe56b9e6 | 1163 | struct atten_status_block { |
351a4ded YM |
1164 | __le32 atten_bits; |
1165 | __le32 atten_ack; | |
1166 | __le16 reserved0; | |
1167 | __le16 sb_index; | |
1168 | __le32 reserved1; | |
1169 | }; | |
1170 | ||
1171 | enum command_type_bit { | |
1172 | IGU_COMMAND_TYPE_NOP = 0, | |
1173 | IGU_COMMAND_TYPE_SET = 1, | |
1174 | MAX_COMMAND_TYPE_BIT | |
1175 | }; | |
1176 | ||
1177 | /* DMAE command */ | |
1178 | struct dmae_cmd { | |
1179 | __le32 opcode; | |
1180 | #define DMAE_CMD_SRC_MASK 0x1 | |
1181 | #define DMAE_CMD_SRC_SHIFT 0 | |
1182 | #define DMAE_CMD_DST_MASK 0x3 | |
1183 | #define DMAE_CMD_DST_SHIFT 1 | |
1184 | #define DMAE_CMD_C_DST_MASK 0x1 | |
1185 | #define DMAE_CMD_C_DST_SHIFT 3 | |
1186 | #define DMAE_CMD_CRC_RESET_MASK 0x1 | |
1187 | #define DMAE_CMD_CRC_RESET_SHIFT 4 | |
1188 | #define DMAE_CMD_SRC_ADDR_RESET_MASK 0x1 | |
1189 | #define DMAE_CMD_SRC_ADDR_RESET_SHIFT 5 | |
1190 | #define DMAE_CMD_DST_ADDR_RESET_MASK 0x1 | |
1191 | #define DMAE_CMD_DST_ADDR_RESET_SHIFT 6 | |
1192 | #define DMAE_CMD_COMP_FUNC_MASK 0x1 | |
1193 | #define DMAE_CMD_COMP_FUNC_SHIFT 7 | |
1194 | #define DMAE_CMD_COMP_WORD_EN_MASK 0x1 | |
1195 | #define DMAE_CMD_COMP_WORD_EN_SHIFT 8 | |
1196 | #define DMAE_CMD_COMP_CRC_EN_MASK 0x1 | |
1197 | #define DMAE_CMD_COMP_CRC_EN_SHIFT 9 | |
1198 | #define DMAE_CMD_COMP_CRC_OFFSET_MASK 0x7 | |
1199 | #define DMAE_CMD_COMP_CRC_OFFSET_SHIFT 10 | |
1200 | #define DMAE_CMD_RESERVED1_MASK 0x1 | |
1201 | #define DMAE_CMD_RESERVED1_SHIFT 13 | |
1202 | #define DMAE_CMD_ENDIANITY_MODE_MASK 0x3 | |
1203 | #define DMAE_CMD_ENDIANITY_MODE_SHIFT 14 | |
1204 | #define DMAE_CMD_ERR_HANDLING_MASK 0x3 | |
1205 | #define DMAE_CMD_ERR_HANDLING_SHIFT 16 | |
1206 | #define DMAE_CMD_PORT_ID_MASK 0x3 | |
1207 | #define DMAE_CMD_PORT_ID_SHIFT 18 | |
1208 | #define DMAE_CMD_SRC_PF_ID_MASK 0xF | |
1209 | #define DMAE_CMD_SRC_PF_ID_SHIFT 20 | |
1210 | #define DMAE_CMD_DST_PF_ID_MASK 0xF | |
1211 | #define DMAE_CMD_DST_PF_ID_SHIFT 24 | |
1212 | #define DMAE_CMD_SRC_VF_ID_VALID_MASK 0x1 | |
1213 | #define DMAE_CMD_SRC_VF_ID_VALID_SHIFT 28 | |
1214 | #define DMAE_CMD_DST_VF_ID_VALID_MASK 0x1 | |
1215 | #define DMAE_CMD_DST_VF_ID_VALID_SHIFT 29 | |
1216 | #define DMAE_CMD_RESERVED2_MASK 0x3 | |
1217 | #define DMAE_CMD_RESERVED2_SHIFT 30 | |
1218 | __le32 src_addr_lo; | |
1219 | __le32 src_addr_hi; | |
1220 | __le32 dst_addr_lo; | |
1221 | __le32 dst_addr_hi; | |
1222 | __le16 length_dw; | |
1223 | __le16 opcode_b; | |
1224 | #define DMAE_CMD_SRC_VF_ID_MASK 0xFF | |
1225 | #define DMAE_CMD_SRC_VF_ID_SHIFT 0 | |
1226 | #define DMAE_CMD_DST_VF_ID_MASK 0xFF | |
1227 | #define DMAE_CMD_DST_VF_ID_SHIFT 8 | |
1228 | __le32 comp_addr_lo; | |
1229 | __le32 comp_addr_hi; | |
1230 | __le32 comp_val; | |
1231 | __le32 crc32; | |
1232 | __le32 crc_32_c; | |
1233 | __le16 crc16; | |
1234 | __le16 crc16_c; | |
1235 | __le16 crc10; | |
1236 | __le16 reserved; | |
1237 | __le16 xsum16; | |
1238 | __le16 xsum8; | |
1239 | }; | |
1240 | ||
1241 | enum dmae_cmd_comp_crc_en_enum { | |
1242 | dmae_cmd_comp_crc_disabled, | |
1243 | dmae_cmd_comp_crc_enabled, | |
1244 | MAX_DMAE_CMD_COMP_CRC_EN_ENUM | |
1245 | }; | |
1246 | ||
1247 | enum dmae_cmd_comp_func_enum { | |
1248 | dmae_cmd_comp_func_to_src, | |
1249 | dmae_cmd_comp_func_to_dst, | |
1250 | MAX_DMAE_CMD_COMP_FUNC_ENUM | |
1251 | }; | |
1252 | ||
1253 | enum dmae_cmd_comp_word_en_enum { | |
1254 | dmae_cmd_comp_word_disabled, | |
1255 | dmae_cmd_comp_word_enabled, | |
1256 | MAX_DMAE_CMD_COMP_WORD_EN_ENUM | |
1257 | }; | |
1258 | ||
1259 | enum dmae_cmd_c_dst_enum { | |
1260 | dmae_cmd_c_dst_pcie, | |
1261 | dmae_cmd_c_dst_grc, | |
1262 | MAX_DMAE_CMD_C_DST_ENUM | |
1263 | }; | |
1264 | ||
1265 | enum dmae_cmd_dst_enum { | |
1266 | dmae_cmd_dst_none_0, | |
1267 | dmae_cmd_dst_pcie, | |
1268 | dmae_cmd_dst_grc, | |
1269 | dmae_cmd_dst_none_3, | |
1270 | MAX_DMAE_CMD_DST_ENUM | |
1271 | }; | |
1272 | ||
1273 | enum dmae_cmd_error_handling_enum { | |
1274 | dmae_cmd_error_handling_send_regular_comp, | |
1275 | dmae_cmd_error_handling_send_comp_with_err, | |
1276 | dmae_cmd_error_handling_dont_send_comp, | |
1277 | MAX_DMAE_CMD_ERROR_HANDLING_ENUM | |
1278 | }; | |
1279 | ||
1280 | enum dmae_cmd_src_enum { | |
1281 | dmae_cmd_src_pcie, | |
1282 | dmae_cmd_src_grc, | |
1283 | MAX_DMAE_CMD_SRC_ENUM | |
1284 | }; | |
1285 | ||
1286 | /* IGU cleanup command */ | |
1287 | struct igu_cleanup { | |
1288 | __le32 sb_id_and_flags; | |
1289 | #define IGU_CLEANUP_RESERVED0_MASK 0x7FFFFFF | |
1290 | #define IGU_CLEANUP_RESERVED0_SHIFT 0 | |
1291 | #define IGU_CLEANUP_CLEANUP_SET_MASK 0x1 | |
1292 | #define IGU_CLEANUP_CLEANUP_SET_SHIFT 27 | |
1293 | #define IGU_CLEANUP_CLEANUP_TYPE_MASK 0x7 | |
1294 | #define IGU_CLEANUP_CLEANUP_TYPE_SHIFT 28 | |
1295 | #define IGU_CLEANUP_COMMAND_TYPE_MASK 0x1 | |
1296 | #define IGU_CLEANUP_COMMAND_TYPE_SHIFT 31 | |
1297 | __le32 reserved1; | |
1298 | }; | |
1299 | ||
1300 | /* IGU firmware driver command */ | |
1301 | union igu_command { | |
1302 | struct igu_prod_cons_update prod_cons_update; | |
1303 | struct igu_cleanup cleanup; | |
1304 | }; | |
1305 | ||
1306 | /* IGU firmware driver command */ | |
1307 | struct igu_command_reg_ctrl { | |
1308 | __le16 opaque_fid; | |
1309 | __le16 igu_command_reg_ctrl_fields; | |
1310 | #define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_MASK 0xFFF | |
1311 | #define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_SHIFT 0 | |
1312 | #define IGU_COMMAND_REG_CTRL_RESERVED_MASK 0x7 | |
1313 | #define IGU_COMMAND_REG_CTRL_RESERVED_SHIFT 12 | |
1314 | #define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_MASK 0x1 | |
1315 | #define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_SHIFT 15 | |
1316 | }; | |
1317 | ||
1318 | /* IGU mapping line structure */ | |
1319 | struct igu_mapping_line { | |
1320 | __le32 igu_mapping_line_fields; | |
1321 | #define IGU_MAPPING_LINE_VALID_MASK 0x1 | |
1322 | #define IGU_MAPPING_LINE_VALID_SHIFT 0 | |
1323 | #define IGU_MAPPING_LINE_VECTOR_NUMBER_MASK 0xFF | |
1324 | #define IGU_MAPPING_LINE_VECTOR_NUMBER_SHIFT 1 | |
1325 | #define IGU_MAPPING_LINE_FUNCTION_NUMBER_MASK 0xFF | |
1326 | #define IGU_MAPPING_LINE_FUNCTION_NUMBER_SHIFT 9 | |
1327 | #define IGU_MAPPING_LINE_PF_VALID_MASK 0x1 | |
1328 | #define IGU_MAPPING_LINE_PF_VALID_SHIFT 17 | |
1329 | #define IGU_MAPPING_LINE_IPS_GROUP_MASK 0x3F | |
1330 | #define IGU_MAPPING_LINE_IPS_GROUP_SHIFT 18 | |
1331 | #define IGU_MAPPING_LINE_RESERVED_MASK 0xFF | |
1332 | #define IGU_MAPPING_LINE_RESERVED_SHIFT 24 | |
1333 | }; | |
1334 | ||
1335 | /* IGU MSIX line structure */ | |
1336 | struct igu_msix_vector { | |
1337 | struct regpair address; | |
1338 | __le32 data; | |
1339 | __le32 msix_vector_fields; | |
1340 | #define IGU_MSIX_VECTOR_MASK_BIT_MASK 0x1 | |
1341 | #define IGU_MSIX_VECTOR_MASK_BIT_SHIFT 0 | |
1342 | #define IGU_MSIX_VECTOR_RESERVED0_MASK 0x7FFF | |
1343 | #define IGU_MSIX_VECTOR_RESERVED0_SHIFT 1 | |
1344 | #define IGU_MSIX_VECTOR_STEERING_TAG_MASK 0xFF | |
1345 | #define IGU_MSIX_VECTOR_STEERING_TAG_SHIFT 16 | |
1346 | #define IGU_MSIX_VECTOR_RESERVED1_MASK 0xFF | |
1347 | #define IGU_MSIX_VECTOR_RESERVED1_SHIFT 24 | |
1348 | }; | |
1349 | ||
1350 | struct mstorm_core_conn_ag_ctx { | |
1351 | u8 byte0; | |
1352 | u8 byte1; | |
1353 | u8 flags0; | |
1354 | #define MSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 | |
1355 | #define MSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0 | |
1356 | #define MSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 | |
1357 | #define MSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1 | |
1358 | #define MSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 | |
1359 | #define MSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2 | |
1360 | #define MSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 | |
1361 | #define MSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4 | |
1362 | #define MSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 | |
1363 | #define MSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6 | |
1364 | u8 flags1; | |
1365 | #define MSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 | |
1366 | #define MSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0 | |
1367 | #define MSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 | |
1368 | #define MSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1 | |
1369 | #define MSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 | |
1370 | #define MSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2 | |
1371 | #define MSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 | |
1372 | #define MSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 3 | |
1373 | #define MSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 | |
1374 | #define MSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 4 | |
1375 | #define MSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 | |
1376 | #define MSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 5 | |
1377 | #define MSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 | |
1378 | #define MSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 6 | |
1379 | #define MSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 | |
1380 | #define MSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 7 | |
1381 | __le16 word0; | |
1382 | __le16 word1; | |
1383 | __le32 reg0; | |
1384 | __le32 reg1; | |
fe56b9e6 YM |
1385 | }; |
1386 | ||
351a4ded YM |
1387 | /* per encapsulation type enabling flags */ |
1388 | struct prs_reg_encapsulation_type_en { | |
1389 | u8 flags; | |
1390 | #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_MASK 0x1 | |
1391 | #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_SHIFT 0 | |
1392 | #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_MASK 0x1 | |
1393 | #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_SHIFT 1 | |
1394 | #define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_MASK 0x1 | |
1395 | #define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_SHIFT 2 | |
1396 | #define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_MASK 0x1 | |
1397 | #define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_SHIFT 3 | |
1398 | #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_MASK 0x1 | |
1399 | #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_SHIFT 4 | |
1400 | #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_MASK 0x1 | |
1401 | #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_SHIFT 5 | |
1402 | #define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_MASK 0x3 | |
1403 | #define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_SHIFT 6 | |
1404 | }; | |
1405 | ||
1406 | enum pxp_tph_st_hint { | |
1407 | TPH_ST_HINT_BIDIR, | |
1408 | TPH_ST_HINT_REQUESTER, | |
1409 | TPH_ST_HINT_TARGET, | |
1410 | TPH_ST_HINT_TARGET_PRIO, | |
1411 | MAX_PXP_TPH_ST_HINT | |
1412 | }; | |
1413 | ||
1414 | /* QM hardware structure of enable bypass credit mask */ | |
1415 | struct qm_rf_bypass_mask { | |
1416 | u8 flags; | |
1417 | #define QM_RF_BYPASS_MASK_LINEVOQ_MASK 0x1 | |
1418 | #define QM_RF_BYPASS_MASK_LINEVOQ_SHIFT 0 | |
1419 | #define QM_RF_BYPASS_MASK_RESERVED0_MASK 0x1 | |
1420 | #define QM_RF_BYPASS_MASK_RESERVED0_SHIFT 1 | |
1421 | #define QM_RF_BYPASS_MASK_PFWFQ_MASK 0x1 | |
1422 | #define QM_RF_BYPASS_MASK_PFWFQ_SHIFT 2 | |
1423 | #define QM_RF_BYPASS_MASK_VPWFQ_MASK 0x1 | |
1424 | #define QM_RF_BYPASS_MASK_VPWFQ_SHIFT 3 | |
1425 | #define QM_RF_BYPASS_MASK_PFRL_MASK 0x1 | |
1426 | #define QM_RF_BYPASS_MASK_PFRL_SHIFT 4 | |
1427 | #define QM_RF_BYPASS_MASK_VPQCNRL_MASK 0x1 | |
1428 | #define QM_RF_BYPASS_MASK_VPQCNRL_SHIFT 5 | |
1429 | #define QM_RF_BYPASS_MASK_FWPAUSE_MASK 0x1 | |
1430 | #define QM_RF_BYPASS_MASK_FWPAUSE_SHIFT 6 | |
1431 | #define QM_RF_BYPASS_MASK_RESERVED1_MASK 0x1 | |
1432 | #define QM_RF_BYPASS_MASK_RESERVED1_SHIFT 7 | |
1433 | }; | |
1434 | ||
1435 | /* QM hardware structure of opportunistic credit mask */ | |
1436 | struct qm_rf_opportunistic_mask { | |
1437 | __le16 flags; | |
1438 | #define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_MASK 0x1 | |
1439 | #define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_SHIFT 0 | |
1440 | #define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_MASK 0x1 | |
1441 | #define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_SHIFT 1 | |
1442 | #define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_MASK 0x1 | |
1443 | #define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_SHIFT 2 | |
1444 | #define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_MASK 0x1 | |
1445 | #define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_SHIFT 3 | |
1446 | #define QM_RF_OPPORTUNISTIC_MASK_PFRL_MASK 0x1 | |
1447 | #define QM_RF_OPPORTUNISTIC_MASK_PFRL_SHIFT 4 | |
1448 | #define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_MASK 0x1 | |
1449 | #define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_SHIFT 5 | |
1450 | #define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_MASK 0x1 | |
1451 | #define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_SHIFT 6 | |
1452 | #define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_MASK 0x1 | |
1453 | #define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_SHIFT 7 | |
1454 | #define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_MASK 0x1 | |
1455 | #define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_SHIFT 8 | |
1456 | #define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_MASK 0x7F | |
1457 | #define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_SHIFT 9 | |
1458 | }; | |
1459 | ||
1460 | /* QM hardware structure of QM map memory */ | |
1461 | struct qm_rf_pq_map { | |
1462 | __le32 reg; | |
1463 | #define QM_RF_PQ_MAP_PQ_VALID_MASK 0x1 | |
1464 | #define QM_RF_PQ_MAP_PQ_VALID_SHIFT 0 | |
1465 | #define QM_RF_PQ_MAP_RL_ID_MASK 0xFF | |
1466 | #define QM_RF_PQ_MAP_RL_ID_SHIFT 1 | |
1467 | #define QM_RF_PQ_MAP_VP_PQ_ID_MASK 0x1FF | |
1468 | #define QM_RF_PQ_MAP_VP_PQ_ID_SHIFT 9 | |
1469 | #define QM_RF_PQ_MAP_VOQ_MASK 0x1F | |
1470 | #define QM_RF_PQ_MAP_VOQ_SHIFT 18 | |
1471 | #define QM_RF_PQ_MAP_WRR_WEIGHT_GROUP_MASK 0x3 | |
1472 | #define QM_RF_PQ_MAP_WRR_WEIGHT_GROUP_SHIFT 23 | |
1473 | #define QM_RF_PQ_MAP_RL_VALID_MASK 0x1 | |
1474 | #define QM_RF_PQ_MAP_RL_VALID_SHIFT 25 | |
1475 | #define QM_RF_PQ_MAP_RESERVED_MASK 0x3F | |
1476 | #define QM_RF_PQ_MAP_RESERVED_SHIFT 26 | |
1477 | }; | |
1478 | ||
1479 | /* Completion params for aggregated interrupt completion */ | |
1480 | struct sdm_agg_int_comp_params { | |
1481 | __le16 params; | |
1482 | #define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_MASK 0x3F | |
1483 | #define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT 0 | |
1484 | #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_MASK 0x1 | |
1485 | #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT 6 | |
1486 | #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_MASK 0x1FF | |
1487 | #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT 7 | |
1488 | }; | |
1489 | ||
1490 | /* SDM operation gen command (generate aggregative interrupt) */ | |
1491 | struct sdm_op_gen { | |
1492 | __le32 command; | |
1493 | #define SDM_OP_GEN_COMP_PARAM_MASK 0xFFFF | |
1494 | #define SDM_OP_GEN_COMP_PARAM_SHIFT 0 | |
1495 | #define SDM_OP_GEN_COMP_TYPE_MASK 0xF | |
1496 | #define SDM_OP_GEN_COMP_TYPE_SHIFT 16 | |
1497 | #define SDM_OP_GEN_RESERVED_MASK 0xFFF | |
1498 | #define SDM_OP_GEN_RESERVED_SHIFT 20 | |
1499 | }; | |
1500 | ||
1501 | struct ystorm_core_conn_ag_ctx { | |
1502 | u8 byte0; | |
1503 | u8 byte1; | |
1504 | u8 flags0; | |
1505 | #define YSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 | |
1506 | #define YSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0 | |
1507 | #define YSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 | |
1508 | #define YSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1 | |
1509 | #define YSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 | |
1510 | #define YSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2 | |
1511 | #define YSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 | |
1512 | #define YSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4 | |
1513 | #define YSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 | |
1514 | #define YSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6 | |
1515 | u8 flags1; | |
1516 | #define YSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 | |
1517 | #define YSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0 | |
1518 | #define YSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 | |
1519 | #define YSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1 | |
1520 | #define YSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 | |
1521 | #define YSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2 | |
1522 | #define YSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 | |
1523 | #define YSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 3 | |
1524 | #define YSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 | |
1525 | #define YSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 4 | |
1526 | #define YSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 | |
1527 | #define YSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 5 | |
1528 | #define YSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 | |
1529 | #define YSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 6 | |
1530 | #define YSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 | |
1531 | #define YSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 7 | |
1532 | u8 byte2; | |
1533 | u8 byte3; | |
1534 | __le16 word0; | |
1535 | __le32 reg0; | |
1536 | __le32 reg1; | |
1537 | __le16 word1; | |
1538 | __le16 word2; | |
1539 | __le16 word3; | |
1540 | __le16 word4; | |
1541 | __le32 reg2; | |
1542 | __le32 reg3; | |
1543 | }; | |
1544 | ||
1545 | /****************************************/ | |
1546 | /* Debug Tools HSI constants and macros */ | |
1547 | /****************************************/ | |
1548 | ||
fe56b9e6 | 1549 | enum block_addr { |
351a4ded YM |
1550 | GRCBASE_GRC = 0x50000, |
1551 | GRCBASE_MISCS = 0x9000, | |
1552 | GRCBASE_MISC = 0x8000, | |
1553 | GRCBASE_DBU = 0xa000, | |
1554 | GRCBASE_PGLUE_B = 0x2a8000, | |
1555 | GRCBASE_CNIG = 0x218000, | |
1556 | GRCBASE_CPMU = 0x30000, | |
1557 | GRCBASE_NCSI = 0x40000, | |
1558 | GRCBASE_OPTE = 0x53000, | |
1559 | GRCBASE_BMB = 0x540000, | |
1560 | GRCBASE_PCIE = 0x54000, | |
1561 | GRCBASE_MCP = 0xe00000, | |
1562 | GRCBASE_MCP2 = 0x52000, | |
1563 | GRCBASE_PSWHST = 0x2a0000, | |
1564 | GRCBASE_PSWHST2 = 0x29e000, | |
1565 | GRCBASE_PSWRD = 0x29c000, | |
1566 | GRCBASE_PSWRD2 = 0x29d000, | |
1567 | GRCBASE_PSWWR = 0x29a000, | |
1568 | GRCBASE_PSWWR2 = 0x29b000, | |
1569 | GRCBASE_PSWRQ = 0x280000, | |
1570 | GRCBASE_PSWRQ2 = 0x240000, | |
1571 | GRCBASE_PGLCS = 0x0, | |
1572 | GRCBASE_DMAE = 0xc000, | |
1573 | GRCBASE_PTU = 0x560000, | |
1574 | GRCBASE_TCM = 0x1180000, | |
1575 | GRCBASE_MCM = 0x1200000, | |
1576 | GRCBASE_UCM = 0x1280000, | |
1577 | GRCBASE_XCM = 0x1000000, | |
1578 | GRCBASE_YCM = 0x1080000, | |
1579 | GRCBASE_PCM = 0x1100000, | |
1580 | GRCBASE_QM = 0x2f0000, | |
1581 | GRCBASE_TM = 0x2c0000, | |
1582 | GRCBASE_DORQ = 0x100000, | |
1583 | GRCBASE_BRB = 0x340000, | |
1584 | GRCBASE_SRC = 0x238000, | |
1585 | GRCBASE_PRS = 0x1f0000, | |
1586 | GRCBASE_TSDM = 0xfb0000, | |
1587 | GRCBASE_MSDM = 0xfc0000, | |
1588 | GRCBASE_USDM = 0xfd0000, | |
1589 | GRCBASE_XSDM = 0xf80000, | |
1590 | GRCBASE_YSDM = 0xf90000, | |
1591 | GRCBASE_PSDM = 0xfa0000, | |
1592 | GRCBASE_TSEM = 0x1700000, | |
1593 | GRCBASE_MSEM = 0x1800000, | |
1594 | GRCBASE_USEM = 0x1900000, | |
1595 | GRCBASE_XSEM = 0x1400000, | |
1596 | GRCBASE_YSEM = 0x1500000, | |
1597 | GRCBASE_PSEM = 0x1600000, | |
1598 | GRCBASE_RSS = 0x238800, | |
1599 | GRCBASE_TMLD = 0x4d0000, | |
1600 | GRCBASE_MULD = 0x4e0000, | |
1601 | GRCBASE_YULD = 0x4c8000, | |
1602 | GRCBASE_XYLD = 0x4c0000, | |
1603 | GRCBASE_PRM = 0x230000, | |
1604 | GRCBASE_PBF_PB1 = 0xda0000, | |
1605 | GRCBASE_PBF_PB2 = 0xda4000, | |
1606 | GRCBASE_RPB = 0x23c000, | |
1607 | GRCBASE_BTB = 0xdb0000, | |
1608 | GRCBASE_PBF = 0xd80000, | |
1609 | GRCBASE_RDIF = 0x300000, | |
1610 | GRCBASE_TDIF = 0x310000, | |
1611 | GRCBASE_CDU = 0x580000, | |
1612 | GRCBASE_CCFC = 0x2e0000, | |
1613 | GRCBASE_TCFC = 0x2d0000, | |
1614 | GRCBASE_IGU = 0x180000, | |
1615 | GRCBASE_CAU = 0x1c0000, | |
1616 | GRCBASE_UMAC = 0x51000, | |
1617 | GRCBASE_XMAC = 0x210000, | |
1618 | GRCBASE_DBG = 0x10000, | |
1619 | GRCBASE_NIG = 0x500000, | |
1620 | GRCBASE_WOL = 0x600000, | |
1621 | GRCBASE_BMBN = 0x610000, | |
1622 | GRCBASE_IPC = 0x20000, | |
1623 | GRCBASE_NWM = 0x800000, | |
1624 | GRCBASE_NWS = 0x700000, | |
1625 | GRCBASE_MS = 0x6a0000, | |
1626 | GRCBASE_PHY_PCIE = 0x620000, | |
1627 | GRCBASE_LED = 0x6b8000, | |
1628 | GRCBASE_MISC_AEU = 0x8000, | |
1629 | GRCBASE_BAR0_MAP = 0x1c00000, | |
fe56b9e6 YM |
1630 | MAX_BLOCK_ADDR |
1631 | }; | |
1632 | ||
1633 | enum block_id { | |
1634 | BLOCK_GRC, | |
1635 | BLOCK_MISCS, | |
1636 | BLOCK_MISC, | |
1637 | BLOCK_DBU, | |
1638 | BLOCK_PGLUE_B, | |
1639 | BLOCK_CNIG, | |
1640 | BLOCK_CPMU, | |
1641 | BLOCK_NCSI, | |
1642 | BLOCK_OPTE, | |
1643 | BLOCK_BMB, | |
1644 | BLOCK_PCIE, | |
1645 | BLOCK_MCP, | |
1646 | BLOCK_MCP2, | |
1647 | BLOCK_PSWHST, | |
1648 | BLOCK_PSWHST2, | |
1649 | BLOCK_PSWRD, | |
1650 | BLOCK_PSWRD2, | |
1651 | BLOCK_PSWWR, | |
1652 | BLOCK_PSWWR2, | |
1653 | BLOCK_PSWRQ, | |
1654 | BLOCK_PSWRQ2, | |
1655 | BLOCK_PGLCS, | |
fe56b9e6 | 1656 | BLOCK_DMAE, |
351a4ded | 1657 | BLOCK_PTU, |
fe56b9e6 YM |
1658 | BLOCK_TCM, |
1659 | BLOCK_MCM, | |
1660 | BLOCK_UCM, | |
1661 | BLOCK_XCM, | |
1662 | BLOCK_YCM, | |
1663 | BLOCK_PCM, | |
1664 | BLOCK_QM, | |
1665 | BLOCK_TM, | |
1666 | BLOCK_DORQ, | |
1667 | BLOCK_BRB, | |
1668 | BLOCK_SRC, | |
1669 | BLOCK_PRS, | |
1670 | BLOCK_TSDM, | |
1671 | BLOCK_MSDM, | |
1672 | BLOCK_USDM, | |
1673 | BLOCK_XSDM, | |
1674 | BLOCK_YSDM, | |
1675 | BLOCK_PSDM, | |
1676 | BLOCK_TSEM, | |
1677 | BLOCK_MSEM, | |
1678 | BLOCK_USEM, | |
1679 | BLOCK_XSEM, | |
1680 | BLOCK_YSEM, | |
1681 | BLOCK_PSEM, | |
1682 | BLOCK_RSS, | |
1683 | BLOCK_TMLD, | |
1684 | BLOCK_MULD, | |
1685 | BLOCK_YULD, | |
1686 | BLOCK_XYLD, | |
1687 | BLOCK_PRM, | |
1688 | BLOCK_PBF_PB1, | |
1689 | BLOCK_PBF_PB2, | |
1690 | BLOCK_RPB, | |
1691 | BLOCK_BTB, | |
1692 | BLOCK_PBF, | |
1693 | BLOCK_RDIF, | |
1694 | BLOCK_TDIF, | |
1695 | BLOCK_CDU, | |
1696 | BLOCK_CCFC, | |
1697 | BLOCK_TCFC, | |
1698 | BLOCK_IGU, | |
1699 | BLOCK_CAU, | |
1700 | BLOCK_UMAC, | |
1701 | BLOCK_XMAC, | |
1702 | BLOCK_DBG, | |
1703 | BLOCK_NIG, | |
1704 | BLOCK_WOL, | |
1705 | BLOCK_BMBN, | |
1706 | BLOCK_IPC, | |
1707 | BLOCK_NWM, | |
1708 | BLOCK_NWS, | |
1709 | BLOCK_MS, | |
1710 | BLOCK_PHY_PCIE, | |
351a4ded | 1711 | BLOCK_LED, |
fe56b9e6 YM |
1712 | BLOCK_MISC_AEU, |
1713 | BLOCK_BAR0_MAP, | |
1714 | MAX_BLOCK_ID | |
1715 | }; | |
1716 | ||
351a4ded YM |
1717 | /* binary debug buffer types */ |
1718 | enum bin_dbg_buffer_type { | |
1719 | BIN_BUF_DBG_MODE_TREE, | |
1720 | BIN_BUF_DBG_DUMP_REG, | |
1721 | BIN_BUF_DBG_DUMP_MEM, | |
1722 | BIN_BUF_DBG_IDLE_CHK_REGS, | |
1723 | BIN_BUF_DBG_IDLE_CHK_IMMS, | |
1724 | BIN_BUF_DBG_IDLE_CHK_RULES, | |
1725 | BIN_BUF_DBG_IDLE_CHK_PARSING_DATA, | |
1726 | BIN_BUF_DBG_ATTN_BLOCKS, | |
1727 | BIN_BUF_DBG_ATTN_REGS, | |
1728 | BIN_BUF_DBG_ATTN_INDEXES, | |
1729 | BIN_BUF_DBG_ATTN_NAME_OFFSETS, | |
1730 | BIN_BUF_DBG_PARSING_STRINGS, | |
1731 | MAX_BIN_DBG_BUFFER_TYPE | |
fe56b9e6 YM |
1732 | }; |
1733 | ||
fe56b9e6 | 1734 | |
351a4ded YM |
1735 | /* Attention bit mapping */ |
1736 | struct dbg_attn_bit_mapping { | |
1737 | __le16 data; | |
1738 | #define DBG_ATTN_BIT_MAPPING_VAL_MASK 0x7FFF | |
1739 | #define DBG_ATTN_BIT_MAPPING_VAL_SHIFT 0 | |
1740 | #define DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT_MASK 0x1 | |
1741 | #define DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT_SHIFT 15 | |
fe56b9e6 YM |
1742 | }; |
1743 | ||
351a4ded YM |
1744 | /* Attention block per-type data */ |
1745 | struct dbg_attn_block_type_data { | |
1746 | __le16 names_offset; | |
1747 | __le16 reserved1; | |
1748 | u8 num_regs; | |
1749 | u8 reserved2; | |
1750 | __le16 regs_offset; | |
fe56b9e6 YM |
1751 | }; |
1752 | ||
351a4ded YM |
1753 | /* Block attentions */ |
1754 | struct dbg_attn_block { | |
1755 | struct dbg_attn_block_type_data per_type_data[2]; | |
fe56b9e6 YM |
1756 | }; |
1757 | ||
351a4ded YM |
1758 | /* Attention register result */ |
1759 | struct dbg_attn_reg_result { | |
1760 | __le32 data; | |
1761 | #define DBG_ATTN_REG_RESULT_STS_ADDRESS_MASK 0xFFFFFF | |
1762 | #define DBG_ATTN_REG_RESULT_STS_ADDRESS_SHIFT 0 | |
1763 | #define DBG_ATTN_REG_RESULT_NUM_ATTN_IDX_MASK 0xFF | |
1764 | #define DBG_ATTN_REG_RESULT_NUM_ATTN_IDX_SHIFT 24 | |
1765 | __le16 attn_idx_offset; | |
1766 | __le16 reserved; | |
1767 | __le32 sts_val; | |
1768 | __le32 mask_val; | |
1769 | }; | |
1770 | ||
1771 | /* Attention block result */ | |
1772 | struct dbg_attn_block_result { | |
1773 | u8 block_id; | |
1774 | u8 data; | |
1775 | #define DBG_ATTN_BLOCK_RESULT_ATTN_TYPE_MASK 0x3 | |
1776 | #define DBG_ATTN_BLOCK_RESULT_ATTN_TYPE_SHIFT 0 | |
1777 | #define DBG_ATTN_BLOCK_RESULT_NUM_REGS_MASK 0x3F | |
1778 | #define DBG_ATTN_BLOCK_RESULT_NUM_REGS_SHIFT 2 | |
1779 | __le16 names_offset; | |
1780 | struct dbg_attn_reg_result reg_results[15]; | |
1781 | }; | |
1782 | ||
1783 | /* mode header */ | |
1784 | struct dbg_mode_hdr { | |
1785 | __le16 data; | |
1786 | #define DBG_MODE_HDR_EVAL_MODE_MASK 0x1 | |
1787 | #define DBG_MODE_HDR_EVAL_MODE_SHIFT 0 | |
1788 | #define DBG_MODE_HDR_MODES_BUF_OFFSET_MASK 0x7FFF | |
1789 | #define DBG_MODE_HDR_MODES_BUF_OFFSET_SHIFT 1 | |
1790 | }; | |
1791 | ||
1792 | /* Attention register */ | |
1793 | struct dbg_attn_reg { | |
1794 | struct dbg_mode_hdr mode; | |
1795 | __le16 attn_idx_offset; | |
1796 | __le32 data; | |
1797 | #define DBG_ATTN_REG_STS_ADDRESS_MASK 0xFFFFFF | |
1798 | #define DBG_ATTN_REG_STS_ADDRESS_SHIFT 0 | |
1799 | #define DBG_ATTN_REG_NUM_ATTN_IDX_MASK 0xFF | |
1800 | #define DBG_ATTN_REG_NUM_ATTN_IDX_SHIFT 24 | |
1801 | __le32 sts_clr_address; | |
1802 | __le32 mask_address; | |
1803 | }; | |
1804 | ||
1805 | /* attention types */ | |
1806 | enum dbg_attn_type { | |
1807 | ATTN_TYPE_INTERRUPT, | |
1808 | ATTN_TYPE_PARITY, | |
1809 | MAX_DBG_ATTN_TYPE | |
1810 | }; | |
1811 | ||
c965db44 TT |
1812 | /* condition header for registers dump */ |
1813 | struct dbg_dump_cond_hdr { | |
1814 | struct dbg_mode_hdr mode; /* Mode header */ | |
1815 | u8 block_id; /* block ID */ | |
1816 | u8 data_size; /* size in dwords of the data following this header */ | |
1817 | }; | |
1818 | ||
1819 | /* memory data for registers dump */ | |
1820 | struct dbg_dump_mem { | |
1821 | __le32 dword0; | |
1822 | #define DBG_DUMP_MEM_ADDRESS_MASK 0xFFFFFF | |
1823 | #define DBG_DUMP_MEM_ADDRESS_SHIFT 0 | |
1824 | #define DBG_DUMP_MEM_MEM_GROUP_ID_MASK 0xFF | |
1825 | #define DBG_DUMP_MEM_MEM_GROUP_ID_SHIFT 24 | |
1826 | __le32 dword1; | |
1827 | #define DBG_DUMP_MEM_LENGTH_MASK 0xFFFFFF | |
1828 | #define DBG_DUMP_MEM_LENGTH_SHIFT 0 | |
1829 | #define DBG_DUMP_MEM_RESERVED_MASK 0xFF | |
1830 | #define DBG_DUMP_MEM_RESERVED_SHIFT 24 | |
1831 | }; | |
1832 | ||
1833 | /* register data for registers dump */ | |
1834 | struct dbg_dump_reg { | |
1835 | __le32 data; | |
1836 | #define DBG_DUMP_REG_ADDRESS_MASK 0xFFFFFF /* register address (in dwords) */ | |
1837 | #define DBG_DUMP_REG_ADDRESS_SHIFT 0 | |
1838 | #define DBG_DUMP_REG_LENGTH_MASK 0xFF /* register size (in dwords) */ | |
1839 | #define DBG_DUMP_REG_LENGTH_SHIFT 24 | |
1840 | }; | |
1841 | ||
1842 | /* split header for registers dump */ | |
1843 | struct dbg_dump_split_hdr { | |
1844 | __le32 hdr; | |
1845 | #define DBG_DUMP_SPLIT_HDR_DATA_SIZE_MASK 0xFFFFFF | |
1846 | #define DBG_DUMP_SPLIT_HDR_DATA_SIZE_SHIFT 0 | |
1847 | #define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_MASK 0xFF | |
1848 | #define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_SHIFT 24 | |
1849 | }; | |
1850 | ||
1851 | /* condition header for idle check */ | |
1852 | struct dbg_idle_chk_cond_hdr { | |
1853 | struct dbg_mode_hdr mode; /* Mode header */ | |
1854 | __le16 data_size; /* size in dwords of the data following this header */ | |
1855 | }; | |
1856 | ||
1857 | /* Idle Check condition register */ | |
1858 | struct dbg_idle_chk_cond_reg { | |
1859 | __le32 data; | |
1860 | #define DBG_IDLE_CHK_COND_REG_ADDRESS_MASK 0xFFFFFF | |
1861 | #define DBG_IDLE_CHK_COND_REG_ADDRESS_SHIFT 0 | |
1862 | #define DBG_IDLE_CHK_COND_REG_BLOCK_ID_MASK 0xFF | |
1863 | #define DBG_IDLE_CHK_COND_REG_BLOCK_ID_SHIFT 24 | |
1864 | __le16 num_entries; /* number of registers entries to check */ | |
1865 | u8 entry_size; /* size of registers entry (in dwords) */ | |
1866 | u8 start_entry; /* index of the first entry to check */ | |
1867 | }; | |
1868 | ||
1869 | /* Idle Check info register */ | |
1870 | struct dbg_idle_chk_info_reg { | |
1871 | __le32 data; | |
1872 | #define DBG_IDLE_CHK_INFO_REG_ADDRESS_MASK 0xFFFFFF | |
1873 | #define DBG_IDLE_CHK_INFO_REG_ADDRESS_SHIFT 0 | |
1874 | #define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_MASK 0xFF | |
1875 | #define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_SHIFT 24 | |
1876 | __le16 size; /* register size in dwords */ | |
1877 | struct dbg_mode_hdr mode; /* Mode header */ | |
1878 | }; | |
1879 | ||
1880 | /* Idle Check register */ | |
1881 | union dbg_idle_chk_reg { | |
1882 | struct dbg_idle_chk_cond_reg cond_reg; /* condition register */ | |
1883 | struct dbg_idle_chk_info_reg info_reg; /* info register */ | |
1884 | }; | |
1885 | ||
1886 | /* Idle Check result header */ | |
1887 | struct dbg_idle_chk_result_hdr { | |
1888 | __le16 rule_id; /* Failing rule index */ | |
1889 | __le16 mem_entry_id; /* Failing memory entry index */ | |
1890 | u8 num_dumped_cond_regs; /* number of dumped condition registers */ | |
1891 | u8 num_dumped_info_regs; /* number of dumped condition registers */ | |
1892 | u8 severity; /* from dbg_idle_chk_severity_types enum */ | |
1893 | u8 reserved; | |
1894 | }; | |
1895 | ||
1896 | /* Idle Check result register header */ | |
1897 | struct dbg_idle_chk_result_reg_hdr { | |
1898 | u8 data; | |
1899 | #define DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM_MASK 0x1 | |
1900 | #define DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM_SHIFT 0 | |
1901 | #define DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID_MASK 0x7F | |
1902 | #define DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID_SHIFT 1 | |
1903 | u8 start_entry; /* index of the first checked entry */ | |
1904 | __le16 size; /* register size in dwords */ | |
1905 | }; | |
1906 | ||
1907 | /* Idle Check rule */ | |
1908 | struct dbg_idle_chk_rule { | |
1909 | __le16 rule_id; /* Idle Check rule ID */ | |
1910 | u8 severity; /* value from dbg_idle_chk_severity_types enum */ | |
1911 | u8 cond_id; /* Condition ID */ | |
1912 | u8 num_cond_regs; /* number of condition registers */ | |
1913 | u8 num_info_regs; /* number of info registers */ | |
1914 | u8 num_imms; /* number of immediates in the condition */ | |
1915 | u8 reserved1; | |
1916 | __le16 reg_offset; /* offset of this rules registers in the idle check | |
1917 | * register array (in dbg_idle_chk_reg units). | |
1918 | */ | |
1919 | __le16 imm_offset; /* offset of this rules immediate values in the | |
1920 | * immediate values array (in dwords). | |
1921 | */ | |
1922 | }; | |
1923 | ||
1924 | /* Idle Check rule parsing data */ | |
1925 | struct dbg_idle_chk_rule_parsing_data { | |
1926 | __le32 data; | |
1927 | #define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_MASK 0x1 | |
1928 | #define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_SHIFT 0 | |
1929 | #define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_MASK 0x7FFFFFFF | |
1930 | #define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_SHIFT 1 | |
1931 | }; | |
1932 | ||
1933 | /* idle check severity types */ | |
1934 | enum dbg_idle_chk_severity_types { | |
1935 | /* idle check failure should cause an error */ | |
1936 | IDLE_CHK_SEVERITY_ERROR, | |
1937 | /* idle check failure should cause an error only if theres no traffic */ | |
1938 | IDLE_CHK_SEVERITY_ERROR_NO_TRAFFIC, | |
1939 | /* idle check failure should cause a warning */ | |
1940 | IDLE_CHK_SEVERITY_WARNING, | |
1941 | MAX_DBG_IDLE_CHK_SEVERITY_TYPES | |
1942 | }; | |
1943 | ||
1944 | /* Debug Bus block data */ | |
1945 | struct dbg_bus_block_data { | |
1946 | u8 enabled; /* Indicates if the block is enabled for recording (0/1) */ | |
1947 | u8 hw_id; /* HW ID associated with the block */ | |
1948 | u8 line_num; /* Debug line number to select */ | |
1949 | u8 right_shift; /* Number of units to right the debug data (0-3) */ | |
1950 | u8 cycle_en; /* 4-bit value: bit i set -> unit i is enabled. */ | |
1951 | u8 force_valid; /* 4-bit value: bit i set -> unit i is forced valid. */ | |
1952 | u8 force_frame; /* 4-bit value: bit i set -> unit i frame bit is forced. | |
1953 | */ | |
1954 | u8 reserved; | |
1955 | }; | |
1956 | ||
1957 | /* Debug Bus Clients */ | |
1958 | enum dbg_bus_clients { | |
1959 | DBG_BUS_CLIENT_RBCN, | |
1960 | DBG_BUS_CLIENT_RBCP, | |
1961 | DBG_BUS_CLIENT_RBCR, | |
1962 | DBG_BUS_CLIENT_RBCT, | |
1963 | DBG_BUS_CLIENT_RBCU, | |
1964 | DBG_BUS_CLIENT_RBCF, | |
1965 | DBG_BUS_CLIENT_RBCX, | |
1966 | DBG_BUS_CLIENT_RBCS, | |
1967 | DBG_BUS_CLIENT_RBCH, | |
1968 | DBG_BUS_CLIENT_RBCZ, | |
1969 | DBG_BUS_CLIENT_OTHER_ENGINE, | |
1970 | DBG_BUS_CLIENT_TIMESTAMP, | |
1971 | DBG_BUS_CLIENT_CPU, | |
1972 | DBG_BUS_CLIENT_RBCY, | |
1973 | DBG_BUS_CLIENT_RBCQ, | |
1974 | DBG_BUS_CLIENT_RBCM, | |
1975 | DBG_BUS_CLIENT_RBCB, | |
1976 | DBG_BUS_CLIENT_RBCW, | |
1977 | DBG_BUS_CLIENT_RBCV, | |
1978 | MAX_DBG_BUS_CLIENTS | |
1979 | }; | |
1980 | ||
1981 | /* Debug Bus memory address */ | |
1982 | struct dbg_bus_mem_addr { | |
1983 | __le32 lo; | |
1984 | __le32 hi; | |
1985 | }; | |
1986 | ||
1987 | /* Debug Bus PCI buffer data */ | |
1988 | struct dbg_bus_pci_buf_data { | |
1989 | struct dbg_bus_mem_addr phys_addr; /* PCI buffer physical address */ | |
1990 | struct dbg_bus_mem_addr virt_addr; /* PCI buffer virtual address */ | |
1991 | __le32 size; /* PCI buffer size in bytes */ | |
1992 | }; | |
1993 | ||
1994 | /* Debug Bus Storm EID range filter params */ | |
1995 | struct dbg_bus_storm_eid_range_params { | |
1996 | u8 min; /* Minimal event ID to filter on */ | |
1997 | u8 max; /* Maximal event ID to filter on */ | |
1998 | }; | |
1999 | ||
2000 | /* Debug Bus Storm EID mask filter params */ | |
2001 | struct dbg_bus_storm_eid_mask_params { | |
2002 | u8 val; /* Event ID value */ | |
2003 | u8 mask; /* Event ID mask. 1s in the mask = dont care bits. */ | |
2004 | }; | |
2005 | ||
2006 | /* Debug Bus Storm EID filter params */ | |
2007 | union dbg_bus_storm_eid_params { | |
2008 | struct dbg_bus_storm_eid_range_params range; | |
2009 | struct dbg_bus_storm_eid_mask_params mask; | |
2010 | }; | |
2011 | ||
2012 | /* Debug Bus Storm data */ | |
2013 | struct dbg_bus_storm_data { | |
2014 | u8 fast_enabled; | |
2015 | u8 fast_mode; | |
2016 | u8 slow_enabled; | |
2017 | u8 slow_mode; | |
2018 | u8 hw_id; | |
2019 | u8 eid_filter_en; | |
2020 | u8 eid_range_not_mask; | |
2021 | u8 cid_filter_en; | |
2022 | union dbg_bus_storm_eid_params eid_filter_params; | |
2023 | __le16 reserved; | |
2024 | __le32 cid; | |
2025 | }; | |
2026 | ||
2027 | /* Debug Bus data */ | |
2028 | struct dbg_bus_data { | |
2029 | __le32 app_version; /* The tools version number of the application */ | |
2030 | u8 state; /* The current debug bus state */ | |
2031 | u8 hw_dwords; /* HW dwords per cycle */ | |
2032 | u8 next_hw_id; /* Next HW ID to be associated with an input */ | |
2033 | u8 num_enabled_blocks; /* Number of blocks enabled for recording */ | |
2034 | u8 num_enabled_storms; /* Number of Storms enabled for recording */ | |
2035 | u8 target; /* Output target */ | |
2036 | u8 next_trigger_state; /* ID of next trigger state to be added */ | |
2037 | u8 next_constraint_id; /* ID of next filter/trigger constraint to be | |
2038 | * added. | |
2039 | */ | |
2040 | u8 one_shot_en; /* Indicates if one-shot mode is enabled (0/1) */ | |
2041 | u8 grc_input_en; /* Indicates if GRC recording is enabled (0/1) */ | |
2042 | u8 timestamp_input_en; /* Indicates if timestamp recording is enabled | |
2043 | * (0/1). | |
2044 | */ | |
2045 | u8 filter_en; /* Indicates if the recording filter is enabled (0/1) */ | |
2046 | u8 trigger_en; /* Indicates if the recording trigger is enabled (0/1) */ | |
2047 | u8 adding_filter; /* If true, the next added constraint belong to the | |
2048 | * filter. Otherwise, it belongs to the last added | |
2049 | * trigger state. Valid only if either filter or | |
2050 | * triggers are enabled. | |
2051 | */ | |
2052 | u8 filter_pre_trigger; /* Indicates if the recording filter should be | |
2053 | * applied before the trigger. Valid only if both | |
2054 | * filter and trigger are enabled (0/1). | |
2055 | */ | |
2056 | u8 filter_post_trigger; /* Indicates if the recording filter should be | |
2057 | * applied after the trigger. Valid only if both | |
2058 | * filter and trigger are enabled (0/1). | |
2059 | */ | |
2060 | u8 unify_inputs; /* If true, all inputs are associated with HW ID 0. | |
2061 | * Otherwise, each input is assigned a different HW ID | |
2062 | * (0/1). | |
2063 | */ | |
2064 | u8 rcv_from_other_engine; /* Indicates if the other engine sends it NW | |
2065 | * recording to this engine (0/1). | |
2066 | */ | |
2067 | struct dbg_bus_pci_buf_data pci_buf; /* Debug Bus PCI buffer data. Valid | |
2068 | * only when the target is | |
2069 | * DBG_BUS_TARGET_ID_PCI. | |
2070 | */ | |
2071 | __le16 reserved; | |
2072 | struct dbg_bus_block_data blocks[80];/* Debug Bus data for each block */ | |
2073 | struct dbg_bus_storm_data storms[6]; /* Debug Bus data for each block */ | |
2074 | }; | |
2075 | ||
2076 | /* Debug bus frame modes */ | |
2077 | enum dbg_bus_frame_modes { | |
2078 | DBG_BUS_FRAME_MODE_0HW_4ST = 0, /* 0 HW dwords, 4 Storm dwords */ | |
2079 | DBG_BUS_FRAME_MODE_4HW_0ST = 3, /* 4 HW dwords, 0 Storm dwords */ | |
2080 | DBG_BUS_FRAME_MODE_8HW_0ST = 4, /* 8 HW dwords, 0 Storm dwords */ | |
2081 | MAX_DBG_BUS_FRAME_MODES | |
2082 | }; | |
2083 | ||
2084 | /* Debug bus states */ | |
2085 | enum dbg_bus_states { | |
2086 | DBG_BUS_STATE_IDLE, /* debug bus idle state (not recording) */ | |
2087 | DBG_BUS_STATE_READY, /* debug bus is ready for configuration and | |
2088 | * recording. | |
2089 | */ | |
2090 | DBG_BUS_STATE_RECORDING, /* debug bus is currently recording */ | |
2091 | DBG_BUS_STATE_STOPPED, /* debug bus recording has stopped */ | |
2092 | MAX_DBG_BUS_STATES | |
2093 | }; | |
2094 | ||
2095 | /* Debug bus target IDs */ | |
2096 | enum dbg_bus_targets { | |
2097 | /* records debug bus to DBG block internal buffer */ | |
2098 | DBG_BUS_TARGET_ID_INT_BUF, | |
2099 | /* records debug bus to the NW */ | |
2100 | DBG_BUS_TARGET_ID_NIG, | |
2101 | /* records debug bus to a PCI buffer */ | |
2102 | DBG_BUS_TARGET_ID_PCI, | |
2103 | MAX_DBG_BUS_TARGETS | |
2104 | }; | |
2105 | ||
2106 | /* GRC Dump data */ | |
2107 | struct dbg_grc_data { | |
2108 | __le32 param_val[40]; /* Value of each GRC parameter. Array size must | |
2109 | * match the enum dbg_grc_params. | |
2110 | */ | |
2111 | u8 param_set_by_user[40]; /* Indicates for each GRC parameter if it was | |
2112 | * set by the user (0/1). Array size must | |
2113 | * match the enum dbg_grc_params. | |
2114 | */ | |
2115 | }; | |
2116 | ||
2117 | /* Debug GRC params */ | |
2118 | enum dbg_grc_params { | |
2119 | DBG_GRC_PARAM_DUMP_TSTORM, /* dump Tstorm memories (0/1) */ | |
2120 | DBG_GRC_PARAM_DUMP_MSTORM, /* dump Mstorm memories (0/1) */ | |
2121 | DBG_GRC_PARAM_DUMP_USTORM, /* dump Ustorm memories (0/1) */ | |
2122 | DBG_GRC_PARAM_DUMP_XSTORM, /* dump Xstorm memories (0/1) */ | |
2123 | DBG_GRC_PARAM_DUMP_YSTORM, /* dump Ystorm memories (0/1) */ | |
2124 | DBG_GRC_PARAM_DUMP_PSTORM, /* dump Pstorm memories (0/1) */ | |
2125 | DBG_GRC_PARAM_DUMP_REGS, /* dump non-memory registers (0/1) */ | |
2126 | DBG_GRC_PARAM_DUMP_RAM, /* dump Storm internal RAMs (0/1) */ | |
2127 | DBG_GRC_PARAM_DUMP_PBUF, /* dump Storm passive buffer (0/1) */ | |
2128 | DBG_GRC_PARAM_DUMP_IOR, /* dump Storm IORs (0/1) */ | |
2129 | DBG_GRC_PARAM_DUMP_VFC, /* dump VFC memories (0/1) */ | |
2130 | DBG_GRC_PARAM_DUMP_CM_CTX, /* dump CM contexts (0/1) */ | |
2131 | DBG_GRC_PARAM_DUMP_PXP, /* dump PXP memories (0/1) */ | |
2132 | DBG_GRC_PARAM_DUMP_RSS, /* dump RSS memories (0/1) */ | |
2133 | DBG_GRC_PARAM_DUMP_CAU, /* dump CAU memories (0/1) */ | |
2134 | DBG_GRC_PARAM_DUMP_QM, /* dump QM memories (0/1) */ | |
2135 | DBG_GRC_PARAM_DUMP_MCP, /* dump MCP memories (0/1) */ | |
2136 | DBG_GRC_PARAM_RESERVED, /* reserved */ | |
2137 | DBG_GRC_PARAM_DUMP_CFC, /* dump CFC memories (0/1) */ | |
2138 | DBG_GRC_PARAM_DUMP_IGU, /* dump IGU memories (0/1) */ | |
2139 | DBG_GRC_PARAM_DUMP_BRB, /* dump BRB memories (0/1) */ | |
2140 | DBG_GRC_PARAM_DUMP_BTB, /* dump BTB memories (0/1) */ | |
2141 | DBG_GRC_PARAM_DUMP_BMB, /* dump BMB memories (0/1) */ | |
2142 | DBG_GRC_PARAM_DUMP_NIG, /* dump NIG memories (0/1) */ | |
2143 | DBG_GRC_PARAM_DUMP_MULD, /* dump MULD memories (0/1) */ | |
2144 | DBG_GRC_PARAM_DUMP_PRS, /* dump PRS memories (0/1) */ | |
2145 | DBG_GRC_PARAM_DUMP_DMAE, /* dump PRS memories (0/1) */ | |
2146 | DBG_GRC_PARAM_DUMP_TM, /* dump TM (timers) memories (0/1) */ | |
2147 | DBG_GRC_PARAM_DUMP_SDM, /* dump SDM memories (0/1) */ | |
2148 | DBG_GRC_PARAM_DUMP_DIF, /* dump DIF memories (0/1) */ | |
2149 | DBG_GRC_PARAM_DUMP_STATIC, /* dump static debug data (0/1) */ | |
2150 | DBG_GRC_PARAM_UNSTALL, /* un-stall Storms after dump (0/1) */ | |
2151 | DBG_GRC_PARAM_NUM_LCIDS, /* number of LCIDs (0..320) */ | |
2152 | DBG_GRC_PARAM_NUM_LTIDS, /* number of LTIDs (0..320) */ | |
2153 | /* preset: exclude all memories from dump (1 only) */ | |
2154 | DBG_GRC_PARAM_EXCLUDE_ALL, | |
2155 | /* preset: include memories for crash dump (1 only) */ | |
2156 | DBG_GRC_PARAM_CRASH, | |
2157 | /* perform dump only if MFW is responding (0/1) */ | |
2158 | DBG_GRC_PARAM_PARITY_SAFE, | |
2159 | DBG_GRC_PARAM_DUMP_CM, /* dump CM memories (0/1) */ | |
2160 | DBG_GRC_PARAM_DUMP_PHY, /* dump PHY memories (0/1) */ | |
2161 | MAX_DBG_GRC_PARAMS | |
2162 | }; | |
2163 | ||
2164 | /* Debug reset registers */ | |
2165 | enum dbg_reset_regs { | |
2166 | DBG_RESET_REG_MISCS_PL_UA, | |
2167 | DBG_RESET_REG_MISCS_PL_HV, | |
2168 | DBG_RESET_REG_MISCS_PL_HV_2, | |
2169 | DBG_RESET_REG_MISC_PL_UA, | |
2170 | DBG_RESET_REG_MISC_PL_HV, | |
2171 | DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, | |
2172 | DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, | |
2173 | DBG_RESET_REG_MISC_PL_PDA_VAUX, | |
2174 | MAX_DBG_RESET_REGS | |
2175 | }; | |
2176 | ||
351a4ded YM |
2177 | /* Debug status codes */ |
2178 | enum dbg_status { | |
2179 | DBG_STATUS_OK, | |
2180 | DBG_STATUS_APP_VERSION_NOT_SET, | |
2181 | DBG_STATUS_UNSUPPORTED_APP_VERSION, | |
2182 | DBG_STATUS_DBG_BLOCK_NOT_RESET, | |
2183 | DBG_STATUS_INVALID_ARGS, | |
2184 | DBG_STATUS_OUTPUT_ALREADY_SET, | |
2185 | DBG_STATUS_INVALID_PCI_BUF_SIZE, | |
2186 | DBG_STATUS_PCI_BUF_ALLOC_FAILED, | |
2187 | DBG_STATUS_PCI_BUF_NOT_ALLOCATED, | |
2188 | DBG_STATUS_TOO_MANY_INPUTS, | |
2189 | DBG_STATUS_INPUT_OVERLAP, | |
2190 | DBG_STATUS_HW_ONLY_RECORDING, | |
2191 | DBG_STATUS_STORM_ALREADY_ENABLED, | |
2192 | DBG_STATUS_STORM_NOT_ENABLED, | |
2193 | DBG_STATUS_BLOCK_ALREADY_ENABLED, | |
2194 | DBG_STATUS_BLOCK_NOT_ENABLED, | |
2195 | DBG_STATUS_NO_INPUT_ENABLED, | |
2196 | DBG_STATUS_NO_FILTER_TRIGGER_64B, | |
2197 | DBG_STATUS_FILTER_ALREADY_ENABLED, | |
2198 | DBG_STATUS_TRIGGER_ALREADY_ENABLED, | |
2199 | DBG_STATUS_TRIGGER_NOT_ENABLED, | |
2200 | DBG_STATUS_CANT_ADD_CONSTRAINT, | |
2201 | DBG_STATUS_TOO_MANY_TRIGGER_STATES, | |
2202 | DBG_STATUS_TOO_MANY_CONSTRAINTS, | |
2203 | DBG_STATUS_RECORDING_NOT_STARTED, | |
2204 | DBG_STATUS_DATA_DIDNT_TRIGGER, | |
2205 | DBG_STATUS_NO_DATA_RECORDED, | |
2206 | DBG_STATUS_DUMP_BUF_TOO_SMALL, | |
2207 | DBG_STATUS_DUMP_NOT_CHUNK_ALIGNED, | |
2208 | DBG_STATUS_UNKNOWN_CHIP, | |
2209 | DBG_STATUS_VIRT_MEM_ALLOC_FAILED, | |
2210 | DBG_STATUS_BLOCK_IN_RESET, | |
2211 | DBG_STATUS_INVALID_TRACE_SIGNATURE, | |
2212 | DBG_STATUS_INVALID_NVRAM_BUNDLE, | |
2213 | DBG_STATUS_NVRAM_GET_IMAGE_FAILED, | |
2214 | DBG_STATUS_NON_ALIGNED_NVRAM_IMAGE, | |
2215 | DBG_STATUS_NVRAM_READ_FAILED, | |
2216 | DBG_STATUS_IDLE_CHK_PARSE_FAILED, | |
2217 | DBG_STATUS_MCP_TRACE_BAD_DATA, | |
2218 | DBG_STATUS_MCP_TRACE_NO_META, | |
2219 | DBG_STATUS_MCP_COULD_NOT_HALT, | |
2220 | DBG_STATUS_MCP_COULD_NOT_RESUME, | |
2221 | DBG_STATUS_DMAE_FAILED, | |
2222 | DBG_STATUS_SEMI_FIFO_NOT_EMPTY, | |
2223 | DBG_STATUS_IGU_FIFO_BAD_DATA, | |
2224 | DBG_STATUS_MCP_COULD_NOT_MASK_PRTY, | |
2225 | DBG_STATUS_FW_ASSERTS_PARSE_FAILED, | |
2226 | DBG_STATUS_REG_FIFO_BAD_DATA, | |
2227 | DBG_STATUS_PROTECTION_OVERRIDE_BAD_DATA, | |
2228 | DBG_STATUS_DBG_ARRAY_NOT_SET, | |
05fafbfb | 2229 | DBG_STATUS_MULTI_BLOCKS_WITH_FILTER, |
351a4ded | 2230 | MAX_DBG_STATUS |
fe56b9e6 YM |
2231 | }; |
2232 | ||
c965db44 TT |
2233 | /* Debug Storms IDs */ |
2234 | enum dbg_storms { | |
2235 | DBG_TSTORM_ID, | |
2236 | DBG_MSTORM_ID, | |
2237 | DBG_USTORM_ID, | |
2238 | DBG_XSTORM_ID, | |
2239 | DBG_YSTORM_ID, | |
2240 | DBG_PSTORM_ID, | |
2241 | MAX_DBG_STORMS | |
2242 | }; | |
2243 | ||
2244 | /* Idle Check data */ | |
2245 | struct idle_chk_data { | |
2246 | __le32 buf_size; /* Idle check buffer size in dwords */ | |
2247 | u8 buf_size_set; /* Indicates if the idle check buffer size was set | |
2248 | * (0/1). | |
2249 | */ | |
2250 | u8 reserved1; | |
2251 | __le16 reserved2; | |
2252 | }; | |
2253 | ||
2254 | /* Debug Tools data (per HW function) */ | |
2255 | struct dbg_tools_data { | |
2256 | struct dbg_grc_data grc; /* GRC Dump data */ | |
2257 | struct dbg_bus_data bus; /* Debug Bus data */ | |
2258 | struct idle_chk_data idle_chk; /* Idle Check data */ | |
2259 | u8 mode_enable[40]; /* Indicates if a mode is enabled (0/1) */ | |
2260 | u8 block_in_reset[80]; /* Indicates if a block is in reset state (0/1). | |
2261 | */ | |
2262 | u8 chip_id; /* Chip ID (from enum chip_ids) */ | |
2263 | u8 platform_id; /* Platform ID (from enum platform_ids) */ | |
2264 | u8 initialized; /* Indicates if the data was initialized */ | |
2265 | u8 reserved; | |
2266 | }; | |
2267 | ||
351a4ded YM |
2268 | /********************************/ |
2269 | /* HSI Init Functions constants */ | |
2270 | /********************************/ | |
2271 | ||
2272 | /* Number of VLAN priorities */ | |
2273 | #define NUM_OF_VLAN_PRIORITIES 8 | |
2274 | ||
05fafbfb YM |
2275 | struct init_brb_ram_req { |
2276 | __le32 guranteed_per_tc; | |
2277 | __le32 headroom_per_tc; | |
2278 | __le32 min_pkt_size; | |
2279 | __le32 max_ports_per_engine; | |
2280 | u8 num_active_tcs[MAX_NUM_PORTS]; | |
2281 | }; | |
2282 | ||
2283 | struct init_ets_tc_req { | |
2284 | u8 use_sp; | |
2285 | u8 use_wfq; | |
2286 | __le16 weight; | |
2287 | }; | |
2288 | ||
2289 | struct init_ets_req { | |
2290 | __le32 mtu; | |
2291 | struct init_ets_tc_req tc_req[NUM_OF_TCS]; | |
2292 | }; | |
2293 | ||
2294 | struct init_nig_lb_rl_req { | |
2295 | __le16 lb_mac_rate; | |
2296 | __le16 lb_rate; | |
2297 | __le32 mtu; | |
2298 | __le16 tc_rate[NUM_OF_PHYS_TCS]; | |
2299 | }; | |
2300 | ||
2301 | struct init_nig_pri_tc_map_entry { | |
2302 | u8 tc_id; | |
2303 | u8 valid; | |
2304 | }; | |
2305 | ||
2306 | struct init_nig_pri_tc_map_req { | |
2307 | struct init_nig_pri_tc_map_entry pri[NUM_OF_VLAN_PRIORITIES]; | |
2308 | }; | |
2309 | ||
351a4ded YM |
2310 | struct init_qm_port_params { |
2311 | u8 active; | |
2312 | u8 active_phys_tcs; | |
2313 | __le16 num_pbf_cmd_lines; | |
2314 | __le16 num_btb_blocks; | |
2315 | __le16 reserved; | |
fe56b9e6 YM |
2316 | }; |
2317 | ||
351a4ded YM |
2318 | /* QM per-PQ init parameters */ |
2319 | struct init_qm_pq_params { | |
2320 | u8 vport_id; | |
2321 | u8 tc_id; | |
2322 | u8 wrr_group; | |
2323 | u8 rl_valid; | |
2324 | }; | |
2325 | ||
2326 | /* QM per-vport init parameters */ | |
2327 | struct init_qm_vport_params { | |
2328 | __le32 vport_rl; | |
2329 | __le16 vport_wfq; | |
2330 | __le16 first_tx_pq_id[NUM_OF_TCS]; | |
2331 | }; | |
2332 | ||
2333 | /**************************************/ | |
2334 | /* Init Tool HSI constants and macros */ | |
2335 | /**************************************/ | |
2336 | ||
2337 | /* Width of GRC address in bits (addresses are specified in dwords) */ | |
2338 | #define GRC_ADDR_BITS 23 | |
05fafbfb | 2339 | #define MAX_GRC_ADDR (BIT(GRC_ADDR_BITS) - 1) |
351a4ded YM |
2340 | |
2341 | /* indicates an init that should be applied to any phase ID */ | |
2342 | #define ANY_PHASE_ID 0xffff | |
2343 | ||
2344 | /* Max size in dwords of a zipped array */ | |
2345 | #define MAX_ZIPPED_SIZE 8192 | |
2346 | ||
c965db44 TT |
2347 | struct fw_asserts_ram_section { |
2348 | __le16 section_ram_line_offset; | |
2349 | __le16 section_ram_line_size; | |
2350 | u8 list_dword_offset; | |
2351 | u8 list_element_dword_size; | |
2352 | u8 list_num_elements; | |
2353 | u8 list_next_index_dword_offset; | |
2354 | }; | |
2355 | ||
2356 | struct fw_ver_num { | |
2357 | u8 major; /* Firmware major version number */ | |
2358 | u8 minor; /* Firmware minor version number */ | |
2359 | u8 rev; /* Firmware revision version number */ | |
2360 | u8 eng; /* Firmware engineering version number (for bootleg versions) */ | |
2361 | }; | |
2362 | ||
2363 | struct fw_ver_info { | |
2364 | __le16 tools_ver; /* Tools version number */ | |
2365 | u8 image_id; /* FW image ID (e.g. main) */ | |
2366 | u8 reserved1; | |
2367 | struct fw_ver_num num; /* FW version number */ | |
2368 | __le32 timestamp; /* FW Timestamp in unix time (sec. since 1970) */ | |
2369 | __le32 reserved2; | |
2370 | }; | |
2371 | ||
2372 | struct fw_info { | |
2373 | struct fw_ver_info ver; | |
2374 | struct fw_asserts_ram_section fw_asserts_section; | |
2375 | }; | |
2376 | ||
2377 | struct fw_info_location { | |
2378 | __le32 grc_addr; | |
2379 | __le32 size; | |
2380 | }; | |
2381 | ||
fe56b9e6 | 2382 | enum init_modes { |
351a4ded | 2383 | MODE_RESERVED, |
12e09c69 | 2384 | MODE_BB_B0, |
c965db44 | 2385 | MODE_K2, |
fe56b9e6 | 2386 | MODE_ASIC, |
c965db44 | 2387 | MODE_RESERVED2, |
fe56b9e6 YM |
2388 | MODE_RESERVED3, |
2389 | MODE_RESERVED4, | |
2390 | MODE_RESERVED5, | |
2391 | MODE_SF, | |
2392 | MODE_MF_SD, | |
2393 | MODE_MF_SI, | |
2394 | MODE_PORTS_PER_ENG_1, | |
2395 | MODE_PORTS_PER_ENG_2, | |
2396 | MODE_PORTS_PER_ENG_4, | |
fe56b9e6 | 2397 | MODE_100G, |
351a4ded | 2398 | MODE_40G, |
c965db44 | 2399 | MODE_RESERVED6, |
fe56b9e6 YM |
2400 | MAX_INIT_MODES |
2401 | }; | |
2402 | ||
2403 | enum init_phases { | |
2404 | PHASE_ENGINE, | |
2405 | PHASE_PORT, | |
2406 | PHASE_PF, | |
1408cc1f | 2407 | PHASE_VF, |
fe56b9e6 YM |
2408 | PHASE_QM_PF, |
2409 | MAX_INIT_PHASES | |
2410 | }; | |
2411 | ||
351a4ded YM |
2412 | enum init_split_types { |
2413 | SPLIT_TYPE_NONE, | |
2414 | SPLIT_TYPE_PORT, | |
2415 | SPLIT_TYPE_PF, | |
2416 | SPLIT_TYPE_PORT_PF, | |
2417 | SPLIT_TYPE_VF, | |
2418 | MAX_INIT_SPLIT_TYPES | |
fe56b9e6 YM |
2419 | }; |
2420 | ||
fe56b9e6 YM |
2421 | /* Binary buffer header */ |
2422 | struct bin_buffer_hdr { | |
351a4ded YM |
2423 | __le32 offset; |
2424 | __le32 length; | |
fe56b9e6 YM |
2425 | }; |
2426 | ||
351a4ded YM |
2427 | /* binary init buffer types */ |
2428 | enum bin_init_buffer_type { | |
05fafbfb | 2429 | BIN_BUF_INIT_FW_VER_INFO, |
351a4ded YM |
2430 | BIN_BUF_INIT_CMD, |
2431 | BIN_BUF_INIT_VAL, | |
2432 | BIN_BUF_INIT_MODE_TREE, | |
05fafbfb | 2433 | BIN_BUF_INIT_IRO, |
351a4ded | 2434 | MAX_BIN_INIT_BUFFER_TYPE |
fe56b9e6 YM |
2435 | }; |
2436 | ||
351a4ded | 2437 | /* init array header: raw */ |
fe56b9e6 YM |
2438 | struct init_array_raw_hdr { |
2439 | __le32 data; | |
351a4ded YM |
2440 | #define INIT_ARRAY_RAW_HDR_TYPE_MASK 0xF |
2441 | #define INIT_ARRAY_RAW_HDR_TYPE_SHIFT 0 | |
2442 | #define INIT_ARRAY_RAW_HDR_PARAMS_MASK 0xFFFFFFF | |
2443 | #define INIT_ARRAY_RAW_HDR_PARAMS_SHIFT 4 | |
fe56b9e6 YM |
2444 | }; |
2445 | ||
351a4ded | 2446 | /* init array header: standard */ |
fe56b9e6 YM |
2447 | struct init_array_standard_hdr { |
2448 | __le32 data; | |
351a4ded YM |
2449 | #define INIT_ARRAY_STANDARD_HDR_TYPE_MASK 0xF |
2450 | #define INIT_ARRAY_STANDARD_HDR_TYPE_SHIFT 0 | |
2451 | #define INIT_ARRAY_STANDARD_HDR_SIZE_MASK 0xFFFFFFF | |
2452 | #define INIT_ARRAY_STANDARD_HDR_SIZE_SHIFT 4 | |
fe56b9e6 YM |
2453 | }; |
2454 | ||
351a4ded | 2455 | /* init array header: zipped */ |
fe56b9e6 YM |
2456 | struct init_array_zipped_hdr { |
2457 | __le32 data; | |
351a4ded YM |
2458 | #define INIT_ARRAY_ZIPPED_HDR_TYPE_MASK 0xF |
2459 | #define INIT_ARRAY_ZIPPED_HDR_TYPE_SHIFT 0 | |
2460 | #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_MASK 0xFFFFFFF | |
2461 | #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_SHIFT 4 | |
fe56b9e6 YM |
2462 | }; |
2463 | ||
351a4ded | 2464 | /* init array header: pattern */ |
fe56b9e6 YM |
2465 | struct init_array_pattern_hdr { |
2466 | __le32 data; | |
351a4ded YM |
2467 | #define INIT_ARRAY_PATTERN_HDR_TYPE_MASK 0xF |
2468 | #define INIT_ARRAY_PATTERN_HDR_TYPE_SHIFT 0 | |
2469 | #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_MASK 0xF | |
2470 | #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_SHIFT 4 | |
2471 | #define INIT_ARRAY_PATTERN_HDR_REPETITIONS_MASK 0xFFFFFF | |
2472 | #define INIT_ARRAY_PATTERN_HDR_REPETITIONS_SHIFT 8 | |
fe56b9e6 YM |
2473 | }; |
2474 | ||
351a4ded | 2475 | /* init array header union */ |
fe56b9e6 | 2476 | union init_array_hdr { |
351a4ded YM |
2477 | struct init_array_raw_hdr raw; |
2478 | struct init_array_standard_hdr standard; | |
2479 | struct init_array_zipped_hdr zipped; | |
2480 | struct init_array_pattern_hdr pattern; | |
fe56b9e6 YM |
2481 | }; |
2482 | ||
351a4ded | 2483 | /* init array types */ |
fe56b9e6 | 2484 | enum init_array_types { |
351a4ded YM |
2485 | INIT_ARR_STANDARD, |
2486 | INIT_ARR_ZIPPED, | |
2487 | INIT_ARR_PATTERN, | |
fe56b9e6 YM |
2488 | MAX_INIT_ARRAY_TYPES |
2489 | }; | |
2490 | ||
2491 | /* init operation: callback */ | |
2492 | struct init_callback_op { | |
351a4ded YM |
2493 | __le32 op_data; |
2494 | #define INIT_CALLBACK_OP_OP_MASK 0xF | |
2495 | #define INIT_CALLBACK_OP_OP_SHIFT 0 | |
2496 | #define INIT_CALLBACK_OP_RESERVED_MASK 0xFFFFFFF | |
2497 | #define INIT_CALLBACK_OP_RESERVED_SHIFT 4 | |
2498 | __le16 callback_id; | |
2499 | __le16 block_id; | |
fe56b9e6 YM |
2500 | }; |
2501 | ||
fe56b9e6 YM |
2502 | /* init operation: delay */ |
2503 | struct init_delay_op { | |
351a4ded YM |
2504 | __le32 op_data; |
2505 | #define INIT_DELAY_OP_OP_MASK 0xF | |
2506 | #define INIT_DELAY_OP_OP_SHIFT 0 | |
2507 | #define INIT_DELAY_OP_RESERVED_MASK 0xFFFFFFF | |
2508 | #define INIT_DELAY_OP_RESERVED_SHIFT 4 | |
2509 | __le32 delay; | |
fe56b9e6 YM |
2510 | }; |
2511 | ||
2512 | /* init operation: if_mode */ | |
2513 | struct init_if_mode_op { | |
2514 | __le32 op_data; | |
351a4ded YM |
2515 | #define INIT_IF_MODE_OP_OP_MASK 0xF |
2516 | #define INIT_IF_MODE_OP_OP_SHIFT 0 | |
2517 | #define INIT_IF_MODE_OP_RESERVED1_MASK 0xFFF | |
2518 | #define INIT_IF_MODE_OP_RESERVED1_SHIFT 4 | |
2519 | #define INIT_IF_MODE_OP_CMD_OFFSET_MASK 0xFFFF | |
2520 | #define INIT_IF_MODE_OP_CMD_OFFSET_SHIFT 16 | |
2521 | __le16 reserved2; | |
2522 | __le16 modes_buf_offset; | |
fe56b9e6 YM |
2523 | }; |
2524 | ||
351a4ded | 2525 | /* init operation: if_phase */ |
fe56b9e6 YM |
2526 | struct init_if_phase_op { |
2527 | __le32 op_data; | |
351a4ded YM |
2528 | #define INIT_IF_PHASE_OP_OP_MASK 0xF |
2529 | #define INIT_IF_PHASE_OP_OP_SHIFT 0 | |
2530 | #define INIT_IF_PHASE_OP_DMAE_ENABLE_MASK 0x1 | |
2531 | #define INIT_IF_PHASE_OP_DMAE_ENABLE_SHIFT 4 | |
2532 | #define INIT_IF_PHASE_OP_RESERVED1_MASK 0x7FF | |
2533 | #define INIT_IF_PHASE_OP_RESERVED1_SHIFT 5 | |
2534 | #define INIT_IF_PHASE_OP_CMD_OFFSET_MASK 0xFFFF | |
2535 | #define INIT_IF_PHASE_OP_CMD_OFFSET_SHIFT 16 | |
fe56b9e6 | 2536 | __le32 phase_data; |
351a4ded YM |
2537 | #define INIT_IF_PHASE_OP_PHASE_MASK 0xFF |
2538 | #define INIT_IF_PHASE_OP_PHASE_SHIFT 0 | |
2539 | #define INIT_IF_PHASE_OP_RESERVED2_MASK 0xFF | |
2540 | #define INIT_IF_PHASE_OP_RESERVED2_SHIFT 8 | |
2541 | #define INIT_IF_PHASE_OP_PHASE_ID_MASK 0xFFFF | |
2542 | #define INIT_IF_PHASE_OP_PHASE_ID_SHIFT 16 | |
fe56b9e6 YM |
2543 | }; |
2544 | ||
2545 | /* init mode operators */ | |
2546 | enum init_mode_ops { | |
351a4ded YM |
2547 | INIT_MODE_OP_NOT, |
2548 | INIT_MODE_OP_OR, | |
2549 | INIT_MODE_OP_AND, | |
fe56b9e6 YM |
2550 | MAX_INIT_MODE_OPS |
2551 | }; | |
2552 | ||
2553 | /* init operation: raw */ | |
2554 | struct init_raw_op { | |
351a4ded YM |
2555 | __le32 op_data; |
2556 | #define INIT_RAW_OP_OP_MASK 0xF | |
2557 | #define INIT_RAW_OP_OP_SHIFT 0 | |
2558 | #define INIT_RAW_OP_PARAM1_MASK 0xFFFFFFF | |
2559 | #define INIT_RAW_OP_PARAM1_SHIFT 4 | |
2560 | __le32 param2; | |
fe56b9e6 YM |
2561 | }; |
2562 | ||
2563 | /* init array params */ | |
2564 | struct init_op_array_params { | |
351a4ded YM |
2565 | __le16 size; |
2566 | __le16 offset; | |
fe56b9e6 YM |
2567 | }; |
2568 | ||
2569 | /* Write init operation arguments */ | |
2570 | union init_write_args { | |
351a4ded YM |
2571 | __le32 inline_val; |
2572 | __le32 zeros_count; | |
2573 | __le32 array_offset; | |
2574 | struct init_op_array_params runtime; | |
fe56b9e6 YM |
2575 | }; |
2576 | ||
2577 | /* init operation: write */ | |
2578 | struct init_write_op { | |
2579 | __le32 data; | |
351a4ded YM |
2580 | #define INIT_WRITE_OP_OP_MASK 0xF |
2581 | #define INIT_WRITE_OP_OP_SHIFT 0 | |
2582 | #define INIT_WRITE_OP_SOURCE_MASK 0x7 | |
2583 | #define INIT_WRITE_OP_SOURCE_SHIFT 4 | |
2584 | #define INIT_WRITE_OP_RESERVED_MASK 0x1 | |
2585 | #define INIT_WRITE_OP_RESERVED_SHIFT 7 | |
2586 | #define INIT_WRITE_OP_WIDE_BUS_MASK 0x1 | |
2587 | #define INIT_WRITE_OP_WIDE_BUS_SHIFT 8 | |
2588 | #define INIT_WRITE_OP_ADDRESS_MASK 0x7FFFFF | |
2589 | #define INIT_WRITE_OP_ADDRESS_SHIFT 9 | |
2590 | union init_write_args args; | |
fe56b9e6 YM |
2591 | }; |
2592 | ||
2593 | /* init operation: read */ | |
2594 | struct init_read_op { | |
2595 | __le32 op_data; | |
351a4ded YM |
2596 | #define INIT_READ_OP_OP_MASK 0xF |
2597 | #define INIT_READ_OP_OP_SHIFT 0 | |
2598 | #define INIT_READ_OP_POLL_TYPE_MASK 0xF | |
2599 | #define INIT_READ_OP_POLL_TYPE_SHIFT 4 | |
2600 | #define INIT_READ_OP_RESERVED_MASK 0x1 | |
2601 | #define INIT_READ_OP_RESERVED_SHIFT 8 | |
2602 | #define INIT_READ_OP_ADDRESS_MASK 0x7FFFFF | |
2603 | #define INIT_READ_OP_ADDRESS_SHIFT 9 | |
fe56b9e6 | 2604 | __le32 expected_val; |
351a4ded | 2605 | |
fe56b9e6 YM |
2606 | }; |
2607 | ||
2608 | /* Init operations union */ | |
2609 | union init_op { | |
351a4ded YM |
2610 | struct init_raw_op raw; |
2611 | struct init_write_op write; | |
2612 | struct init_read_op read; | |
2613 | struct init_if_mode_op if_mode; | |
2614 | struct init_if_phase_op if_phase; | |
2615 | struct init_callback_op callback; | |
2616 | struct init_delay_op delay; | |
fe56b9e6 YM |
2617 | }; |
2618 | ||
2619 | /* Init command operation types */ | |
2620 | enum init_op_types { | |
351a4ded YM |
2621 | INIT_OP_READ, |
2622 | INIT_OP_WRITE, | |
fe56b9e6 YM |
2623 | INIT_OP_IF_MODE, |
2624 | INIT_OP_IF_PHASE, | |
351a4ded YM |
2625 | INIT_OP_DELAY, |
2626 | INIT_OP_CALLBACK, | |
fe56b9e6 YM |
2627 | MAX_INIT_OP_TYPES |
2628 | }; | |
2629 | ||
351a4ded | 2630 | /* init polling types */ |
fc48b7a6 | 2631 | enum init_poll_types { |
351a4ded YM |
2632 | INIT_POLL_NONE, |
2633 | INIT_POLL_EQ, | |
2634 | INIT_POLL_OR, | |
2635 | INIT_POLL_AND, | |
fc48b7a6 YM |
2636 | MAX_INIT_POLL_TYPES |
2637 | }; | |
2638 | ||
fe56b9e6 YM |
2639 | /* init source types */ |
2640 | enum init_source_types { | |
351a4ded YM |
2641 | INIT_SRC_INLINE, |
2642 | INIT_SRC_ZEROS, | |
2643 | INIT_SRC_ARRAY, | |
2644 | INIT_SRC_RUNTIME, | |
fe56b9e6 YM |
2645 | MAX_INIT_SOURCE_TYPES |
2646 | }; | |
2647 | ||
2648 | /* Internal RAM Offsets macro data */ | |
2649 | struct iro { | |
351a4ded YM |
2650 | __le32 base; |
2651 | __le16 m1; | |
2652 | __le16 m2; | |
2653 | __le16 m3; | |
2654 | __le16 size; | |
fe56b9e6 YM |
2655 | }; |
2656 | ||
c965db44 TT |
2657 | /***************************** Public Functions *******************************/ |
2658 | /** | |
2659 | * @brief qed_dbg_set_bin_ptr - Sets a pointer to the binary data with debug | |
2660 | * arrays. | |
2661 | * | |
2662 | * @param bin_ptr - a pointer to the binary data with debug arrays. | |
2663 | */ | |
2664 | enum dbg_status qed_dbg_set_bin_ptr(const u8 * const bin_ptr); | |
2665 | /** | |
2666 | * @brief qed_dbg_grc_get_dump_buf_size - Returns the required buffer size for | |
2667 | * GRC Dump. | |
2668 | * | |
2669 | * @param p_hwfn - HW device data | |
2670 | * @param p_ptt - Ptt window used for writing the registers. | |
2671 | * @param buf_size - OUT: required buffer size (in dwords) for the GRC Dump | |
2672 | * data. | |
2673 | * | |
2674 | * @return error if one of the following holds: | |
2675 | * - the version wasn't set | |
2676 | * Otherwise, returns ok. | |
2677 | */ | |
2678 | enum dbg_status qed_dbg_grc_get_dump_buf_size(struct qed_hwfn *p_hwfn, | |
2679 | struct qed_ptt *p_ptt, | |
2680 | u32 *buf_size); | |
2681 | /** | |
2682 | * @brief qed_dbg_grc_dump - Dumps GRC data into the specified buffer. | |
2683 | * | |
2684 | * @param p_hwfn - HW device data | |
2685 | * @param p_ptt - Ptt window used for writing the registers. | |
2686 | * @param dump_buf - Pointer to write the collected GRC data into. | |
2687 | * @param buf_size_in_dwords - Size of the specified buffer in dwords. | |
2688 | * @param num_dumped_dwords - OUT: number of dumped dwords. | |
2689 | * | |
2690 | * @return error if one of the following holds: | |
2691 | * - the version wasn't set | |
2692 | * - the specified dump buffer is too small | |
2693 | * Otherwise, returns ok. | |
2694 | */ | |
2695 | enum dbg_status qed_dbg_grc_dump(struct qed_hwfn *p_hwfn, | |
2696 | struct qed_ptt *p_ptt, | |
2697 | u32 *dump_buf, | |
2698 | u32 buf_size_in_dwords, | |
2699 | u32 *num_dumped_dwords); | |
2700 | /** | |
2701 | * @brief qed_dbg_idle_chk_get_dump_buf_size - Returns the required buffer size | |
2702 | * for idle check results. | |
2703 | * | |
2704 | * @param p_hwfn - HW device data | |
2705 | * @param p_ptt - Ptt window used for writing the registers. | |
2706 | * @param buf_size - OUT: required buffer size (in dwords) for the idle check | |
2707 | * data. | |
2708 | * | |
2709 | * @return error if one of the following holds: | |
2710 | * - the version wasn't set | |
2711 | * Otherwise, returns ok. | |
2712 | */ | |
2713 | enum dbg_status qed_dbg_idle_chk_get_dump_buf_size(struct qed_hwfn *p_hwfn, | |
2714 | struct qed_ptt *p_ptt, | |
2715 | u32 *buf_size); | |
2716 | /** | |
2717 | * @brief qed_dbg_idle_chk_dump - Performs idle check and writes the results | |
2718 | * into the specified buffer. | |
2719 | * | |
2720 | * @param p_hwfn - HW device data | |
2721 | * @param p_ptt - Ptt window used for writing the registers. | |
2722 | * @param dump_buf - Pointer to write the idle check data into. | |
2723 | * @param buf_size_in_dwords - Size of the specified buffer in dwords. | |
2724 | * @param num_dumped_dwords - OUT: number of dumped dwords. | |
2725 | * | |
2726 | * @return error if one of the following holds: | |
2727 | * - the version wasn't set | |
2728 | * - the specified buffer is too small | |
2729 | * Otherwise, returns ok. | |
2730 | */ | |
2731 | enum dbg_status qed_dbg_idle_chk_dump(struct qed_hwfn *p_hwfn, | |
2732 | struct qed_ptt *p_ptt, | |
2733 | u32 *dump_buf, | |
2734 | u32 buf_size_in_dwords, | |
2735 | u32 *num_dumped_dwords); | |
2736 | /** | |
2737 | * @brief qed_dbg_mcp_trace_get_dump_buf_size - Returns the required buffer size | |
2738 | * for mcp trace results. | |
2739 | * | |
2740 | * @param p_hwfn - HW device data | |
2741 | * @param p_ptt - Ptt window used for writing the registers. | |
2742 | * @param buf_size - OUT: required buffer size (in dwords) for mcp trace data. | |
2743 | * | |
2744 | * @return error if one of the following holds: | |
2745 | * - the version wasn't set | |
2746 | * - the trace data in MCP scratchpad contain an invalid signature | |
2747 | * - the bundle ID in NVRAM is invalid | |
2748 | * - the trace meta data cannot be found (in NVRAM or image file) | |
2749 | * Otherwise, returns ok. | |
2750 | */ | |
2751 | enum dbg_status qed_dbg_mcp_trace_get_dump_buf_size(struct qed_hwfn *p_hwfn, | |
2752 | struct qed_ptt *p_ptt, | |
2753 | u32 *buf_size); | |
2754 | /** | |
2755 | * @brief qed_dbg_mcp_trace_dump - Performs mcp trace and writes the results | |
2756 | * into the specified buffer. | |
2757 | * | |
2758 | * @param p_hwfn - HW device data | |
2759 | * @param p_ptt - Ptt window used for writing the registers. | |
2760 | * @param dump_buf - Pointer to write the mcp trace data into. | |
2761 | * @param buf_size_in_dwords - Size of the specified buffer in dwords. | |
2762 | * @param num_dumped_dwords - OUT: number of dumped dwords. | |
2763 | * | |
2764 | * @return error if one of the following holds: | |
2765 | * - the version wasn't set | |
2766 | * - the specified buffer is too small | |
2767 | * - the trace data in MCP scratchpad contain an invalid signature | |
2768 | * - the bundle ID in NVRAM is invalid | |
2769 | * - the trace meta data cannot be found (in NVRAM or image file) | |
2770 | * - the trace meta data cannot be read (from NVRAM or image file) | |
2771 | * Otherwise, returns ok. | |
2772 | */ | |
2773 | enum dbg_status qed_dbg_mcp_trace_dump(struct qed_hwfn *p_hwfn, | |
2774 | struct qed_ptt *p_ptt, | |
2775 | u32 *dump_buf, | |
2776 | u32 buf_size_in_dwords, | |
2777 | u32 *num_dumped_dwords); | |
2778 | /** | |
2779 | * @brief qed_dbg_reg_fifo_get_dump_buf_size - Returns the required buffer size | |
2780 | * for grc trace fifo results. | |
2781 | * | |
2782 | * @param p_hwfn - HW device data | |
2783 | * @param p_ptt - Ptt window used for writing the registers. | |
2784 | * @param buf_size - OUT: required buffer size (in dwords) for reg fifo data. | |
2785 | * | |
2786 | * @return error if one of the following holds: | |
2787 | * - the version wasn't set | |
2788 | * Otherwise, returns ok. | |
2789 | */ | |
2790 | enum dbg_status qed_dbg_reg_fifo_get_dump_buf_size(struct qed_hwfn *p_hwfn, | |
2791 | struct qed_ptt *p_ptt, | |
2792 | u32 *buf_size); | |
2793 | /** | |
2794 | * @brief qed_dbg_reg_fifo_dump - Reads the reg fifo and writes the results into | |
2795 | * the specified buffer. | |
2796 | * | |
2797 | * @param p_hwfn - HW device data | |
2798 | * @param p_ptt - Ptt window used for writing the registers. | |
2799 | * @param dump_buf - Pointer to write the reg fifo data into. | |
2800 | * @param buf_size_in_dwords - Size of the specified buffer in dwords. | |
2801 | * @param num_dumped_dwords - OUT: number of dumped dwords. | |
2802 | * | |
2803 | * @return error if one of the following holds: | |
2804 | * - the version wasn't set | |
2805 | * - the specified buffer is too small | |
2806 | * - DMAE transaction failed | |
2807 | * Otherwise, returns ok. | |
2808 | */ | |
2809 | enum dbg_status qed_dbg_reg_fifo_dump(struct qed_hwfn *p_hwfn, | |
2810 | struct qed_ptt *p_ptt, | |
2811 | u32 *dump_buf, | |
2812 | u32 buf_size_in_dwords, | |
2813 | u32 *num_dumped_dwords); | |
2814 | /** | |
2815 | * @brief qed_dbg_igu_fifo_get_dump_buf_size - Returns the required buffer size | |
2816 | * for the IGU fifo results. | |
2817 | * | |
2818 | * @param p_hwfn - HW device data | |
2819 | * @param p_ptt - Ptt window used for writing the registers. | |
2820 | * @param buf_size - OUT: required buffer size (in dwords) for the IGU fifo | |
2821 | * data. | |
2822 | * | |
2823 | * @return error if one of the following holds: | |
2824 | * - the version wasn't set | |
2825 | * Otherwise, returns ok. | |
2826 | */ | |
2827 | enum dbg_status qed_dbg_igu_fifo_get_dump_buf_size(struct qed_hwfn *p_hwfn, | |
2828 | struct qed_ptt *p_ptt, | |
2829 | u32 *buf_size); | |
2830 | /** | |
2831 | * @brief qed_dbg_igu_fifo_dump - Reads the IGU fifo and writes the results into | |
2832 | * the specified buffer. | |
2833 | * | |
2834 | * @param p_hwfn - HW device data | |
2835 | * @param p_ptt - Ptt window used for writing the registers. | |
2836 | * @param dump_buf - Pointer to write the IGU fifo data into. | |
2837 | * @param buf_size_in_dwords - Size of the specified buffer in dwords. | |
2838 | * @param num_dumped_dwords - OUT: number of dumped dwords. | |
2839 | * | |
2840 | * @return error if one of the following holds: | |
2841 | * - the version wasn't set | |
2842 | * - the specified buffer is too small | |
2843 | * - DMAE transaction failed | |
2844 | * Otherwise, returns ok. | |
2845 | */ | |
2846 | enum dbg_status qed_dbg_igu_fifo_dump(struct qed_hwfn *p_hwfn, | |
2847 | struct qed_ptt *p_ptt, | |
2848 | u32 *dump_buf, | |
2849 | u32 buf_size_in_dwords, | |
2850 | u32 *num_dumped_dwords); | |
2851 | /** | |
2852 | * @brief qed_dbg_protection_override_get_dump_buf_size - Returns the required | |
2853 | * buffer size for protection override window results. | |
2854 | * | |
2855 | * @param p_hwfn - HW device data | |
2856 | * @param p_ptt - Ptt window used for writing the registers. | |
2857 | * @param buf_size - OUT: required buffer size (in dwords) for protection | |
2858 | * override data. | |
2859 | * | |
2860 | * @return error if one of the following holds: | |
2861 | * - the version wasn't set | |
2862 | * Otherwise, returns ok. | |
2863 | */ | |
2864 | enum dbg_status | |
2865 | qed_dbg_protection_override_get_dump_buf_size(struct qed_hwfn *p_hwfn, | |
2866 | struct qed_ptt *p_ptt, | |
2867 | u32 *buf_size); | |
2868 | /** | |
2869 | * @brief qed_dbg_protection_override_dump - Reads protection override window | |
2870 | * entries and writes the results into the specified buffer. | |
2871 | * | |
2872 | * @param p_hwfn - HW device data | |
2873 | * @param p_ptt - Ptt window used for writing the registers. | |
2874 | * @param dump_buf - Pointer to write the protection override data into. | |
2875 | * @param buf_size_in_dwords - Size of the specified buffer in dwords. | |
2876 | * @param num_dumped_dwords - OUT: number of dumped dwords. | |
2877 | * | |
2878 | * @return error if one of the following holds: | |
2879 | * - the version wasn't set | |
2880 | * - the specified buffer is too small | |
2881 | * - DMAE transaction failed | |
2882 | * Otherwise, returns ok. | |
2883 | */ | |
2884 | enum dbg_status qed_dbg_protection_override_dump(struct qed_hwfn *p_hwfn, | |
2885 | struct qed_ptt *p_ptt, | |
2886 | u32 *dump_buf, | |
2887 | u32 buf_size_in_dwords, | |
2888 | u32 *num_dumped_dwords); | |
2889 | /** | |
2890 | * @brief qed_dbg_fw_asserts_get_dump_buf_size - Returns the required buffer | |
2891 | * size for FW Asserts results. | |
2892 | * | |
2893 | * @param p_hwfn - HW device data | |
2894 | * @param p_ptt - Ptt window used for writing the registers. | |
2895 | * @param buf_size - OUT: required buffer size (in dwords) for FW Asserts data. | |
2896 | * | |
2897 | * @return error if one of the following holds: | |
2898 | * - the version wasn't set | |
2899 | * Otherwise, returns ok. | |
2900 | */ | |
2901 | enum dbg_status qed_dbg_fw_asserts_get_dump_buf_size(struct qed_hwfn *p_hwfn, | |
2902 | struct qed_ptt *p_ptt, | |
2903 | u32 *buf_size); | |
2904 | /** | |
2905 | * @brief qed_dbg_fw_asserts_dump - Reads the FW Asserts and writes the results | |
2906 | * into the specified buffer. | |
2907 | * | |
2908 | * @param p_hwfn - HW device data | |
2909 | * @param p_ptt - Ptt window used for writing the registers. | |
2910 | * @param dump_buf - Pointer to write the FW Asserts data into. | |
2911 | * @param buf_size_in_dwords - Size of the specified buffer in dwords. | |
2912 | * @param num_dumped_dwords - OUT: number of dumped dwords. | |
2913 | * | |
2914 | * @return error if one of the following holds: | |
2915 | * - the version wasn't set | |
2916 | * - the specified buffer is too small | |
2917 | * Otherwise, returns ok. | |
2918 | */ | |
2919 | enum dbg_status qed_dbg_fw_asserts_dump(struct qed_hwfn *p_hwfn, | |
2920 | struct qed_ptt *p_ptt, | |
2921 | u32 *dump_buf, | |
2922 | u32 buf_size_in_dwords, | |
2923 | u32 *num_dumped_dwords); | |
351a4ded | 2924 | /** |
c965db44 TT |
2925 | * @brief qed_dbg_print_attn - Prints attention registers values in the |
2926 | * specified results struct. | |
351a4ded YM |
2927 | * |
2928 | * @param p_hwfn | |
2929 | * @param results - Pointer to the attention read results | |
2930 | * | |
2931 | * @return error if one of the following holds: | |
2932 | * - the version wasn't set | |
2933 | * Otherwise, returns ok. | |
2934 | */ | |
2935 | enum dbg_status qed_dbg_print_attn(struct qed_hwfn *p_hwfn, | |
2936 | struct dbg_attn_block_result *results); | |
fe56b9e6 | 2937 | |
c965db44 TT |
2938 | /******************************** Constants **********************************/ |
2939 | ||
351a4ded | 2940 | #define MAX_NAME_LEN 16 |
fe56b9e6 | 2941 | |
c965db44 TT |
2942 | /***************************** Public Functions *******************************/ |
2943 | /** | |
2944 | * @brief qed_dbg_user_set_bin_ptr - Sets a pointer to the binary data with | |
2945 | * debug arrays. | |
2946 | * | |
2947 | * @param bin_ptr - a pointer to the binary data with debug arrays. | |
2948 | */ | |
2949 | enum dbg_status qed_dbg_user_set_bin_ptr(const u8 * const bin_ptr); | |
2950 | /** | |
2951 | * @brief qed_dbg_get_status_str - Returns a string for the specified status. | |
2952 | * | |
2953 | * @param status - a debug status code. | |
2954 | * | |
2955 | * @return a string for the specified status | |
2956 | */ | |
2957 | const char *qed_dbg_get_status_str(enum dbg_status status); | |
2958 | /** | |
2959 | * @brief qed_get_idle_chk_results_buf_size - Returns the required buffer size | |
2960 | * for idle check results (in bytes). | |
2961 | * | |
2962 | * @param p_hwfn - HW device data | |
2963 | * @param dump_buf - idle check dump buffer. | |
2964 | * @param num_dumped_dwords - number of dwords that were dumped. | |
2965 | * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed | |
2966 | * results. | |
2967 | * | |
2968 | * @return error if the parsing fails, ok otherwise. | |
2969 | */ | |
2970 | enum dbg_status qed_get_idle_chk_results_buf_size(struct qed_hwfn *p_hwfn, | |
2971 | u32 *dump_buf, | |
2972 | u32 num_dumped_dwords, | |
2973 | u32 *results_buf_size); | |
2974 | /** | |
2975 | * @brief qed_print_idle_chk_results - Prints idle check results | |
2976 | * | |
2977 | * @param p_hwfn - HW device data | |
2978 | * @param dump_buf - idle check dump buffer. | |
2979 | * @param num_dumped_dwords - number of dwords that were dumped. | |
2980 | * @param results_buf - buffer for printing the idle check results. | |
2981 | * @param num_errors - OUT: number of errors found in idle check. | |
2982 | * @param num_warnings - OUT: number of warnings found in idle check. | |
2983 | * | |
2984 | * @return error if the parsing fails, ok otherwise. | |
2985 | */ | |
2986 | enum dbg_status qed_print_idle_chk_results(struct qed_hwfn *p_hwfn, | |
2987 | u32 *dump_buf, | |
2988 | u32 num_dumped_dwords, | |
2989 | char *results_buf, | |
2990 | u32 *num_errors, | |
2991 | u32 *num_warnings); | |
2992 | /** | |
2993 | * @brief qed_get_mcp_trace_results_buf_size - Returns the required buffer size | |
2994 | * for MCP Trace results (in bytes). | |
2995 | * | |
2996 | * @param p_hwfn - HW device data | |
2997 | * @param dump_buf - MCP Trace dump buffer. | |
2998 | * @param num_dumped_dwords - number of dwords that were dumped. | |
2999 | * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed | |
3000 | * results. | |
3001 | * | |
3002 | * @return error if the parsing fails, ok otherwise. | |
3003 | */ | |
3004 | enum dbg_status qed_get_mcp_trace_results_buf_size(struct qed_hwfn *p_hwfn, | |
3005 | u32 *dump_buf, | |
3006 | u32 num_dumped_dwords, | |
3007 | u32 *results_buf_size); | |
3008 | /** | |
3009 | * @brief qed_print_mcp_trace_results - Prints MCP Trace results | |
3010 | * | |
3011 | * @param p_hwfn - HW device data | |
3012 | * @param dump_buf - mcp trace dump buffer, starting from the header. | |
3013 | * @param num_dumped_dwords - number of dwords that were dumped. | |
3014 | * @param results_buf - buffer for printing the mcp trace results. | |
3015 | * | |
3016 | * @return error if the parsing fails, ok otherwise. | |
3017 | */ | |
3018 | enum dbg_status qed_print_mcp_trace_results(struct qed_hwfn *p_hwfn, | |
3019 | u32 *dump_buf, | |
3020 | u32 num_dumped_dwords, | |
3021 | char *results_buf); | |
3022 | /** | |
3023 | * @brief qed_get_reg_fifo_results_buf_size - Returns the required buffer size | |
3024 | * for reg_fifo results (in bytes). | |
3025 | * | |
3026 | * @param p_hwfn - HW device data | |
3027 | * @param dump_buf - reg fifo dump buffer. | |
3028 | * @param num_dumped_dwords - number of dwords that were dumped. | |
3029 | * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed | |
3030 | * results. | |
3031 | * | |
3032 | * @return error if the parsing fails, ok otherwise. | |
3033 | */ | |
3034 | enum dbg_status qed_get_reg_fifo_results_buf_size(struct qed_hwfn *p_hwfn, | |
3035 | u32 *dump_buf, | |
3036 | u32 num_dumped_dwords, | |
3037 | u32 *results_buf_size); | |
3038 | /** | |
3039 | * @brief qed_print_reg_fifo_results - Prints reg fifo results | |
3040 | * | |
3041 | * @param p_hwfn - HW device data | |
3042 | * @param dump_buf - reg fifo dump buffer, starting from the header. | |
3043 | * @param num_dumped_dwords - number of dwords that were dumped. | |
3044 | * @param results_buf - buffer for printing the reg fifo results. | |
3045 | * | |
3046 | * @return error if the parsing fails, ok otherwise. | |
3047 | */ | |
3048 | enum dbg_status qed_print_reg_fifo_results(struct qed_hwfn *p_hwfn, | |
3049 | u32 *dump_buf, | |
3050 | u32 num_dumped_dwords, | |
3051 | char *results_buf); | |
3052 | /** | |
3053 | * @brief qed_get_igu_fifo_results_buf_size - Returns the required buffer size | |
3054 | * for igu_fifo results (in bytes). | |
3055 | * | |
3056 | * @param p_hwfn - HW device data | |
3057 | * @param dump_buf - IGU fifo dump buffer. | |
3058 | * @param num_dumped_dwords - number of dwords that were dumped. | |
3059 | * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed | |
3060 | * results. | |
3061 | * | |
3062 | * @return error if the parsing fails, ok otherwise. | |
3063 | */ | |
3064 | enum dbg_status qed_get_igu_fifo_results_buf_size(struct qed_hwfn *p_hwfn, | |
3065 | u32 *dump_buf, | |
3066 | u32 num_dumped_dwords, | |
3067 | u32 *results_buf_size); | |
3068 | /** | |
3069 | * @brief qed_print_igu_fifo_results - Prints IGU fifo results | |
3070 | * | |
3071 | * @param p_hwfn - HW device data | |
3072 | * @param dump_buf - IGU fifo dump buffer, starting from the header. | |
3073 | * @param num_dumped_dwords - number of dwords that were dumped. | |
3074 | * @param results_buf - buffer for printing the IGU fifo results. | |
3075 | * | |
3076 | * @return error if the parsing fails, ok otherwise. | |
3077 | */ | |
3078 | enum dbg_status qed_print_igu_fifo_results(struct qed_hwfn *p_hwfn, | |
3079 | u32 *dump_buf, | |
3080 | u32 num_dumped_dwords, | |
3081 | char *results_buf); | |
3082 | /** | |
3083 | * @brief qed_get_protection_override_results_buf_size - Returns the required | |
3084 | * buffer size for protection override results (in bytes). | |
3085 | * | |
3086 | * @param p_hwfn - HW device data | |
3087 | * @param dump_buf - protection override dump buffer. | |
3088 | * @param num_dumped_dwords - number of dwords that were dumped. | |
3089 | * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed | |
3090 | * results. | |
3091 | * | |
3092 | * @return error if the parsing fails, ok otherwise. | |
3093 | */ | |
3094 | enum dbg_status | |
3095 | qed_get_protection_override_results_buf_size(struct qed_hwfn *p_hwfn, | |
3096 | u32 *dump_buf, | |
3097 | u32 num_dumped_dwords, | |
3098 | u32 *results_buf_size); | |
3099 | /** | |
3100 | * @brief qed_print_protection_override_results - Prints protection override | |
3101 | * results. | |
3102 | * | |
3103 | * @param p_hwfn - HW device data | |
3104 | * @param dump_buf - protection override dump buffer, starting from the header. | |
3105 | * @param num_dumped_dwords - number of dwords that were dumped. | |
3106 | * @param results_buf - buffer for printing the reg fifo results. | |
3107 | * | |
3108 | * @return error if the parsing fails, ok otherwise. | |
3109 | */ | |
3110 | enum dbg_status qed_print_protection_override_results(struct qed_hwfn *p_hwfn, | |
3111 | u32 *dump_buf, | |
3112 | u32 num_dumped_dwords, | |
3113 | char *results_buf); | |
3114 | /** | |
3115 | * @brief qed_get_fw_asserts_results_buf_size - Returns the required buffer size | |
3116 | * for FW Asserts results (in bytes). | |
3117 | * | |
3118 | * @param p_hwfn - HW device data | |
3119 | * @param dump_buf - FW Asserts dump buffer. | |
3120 | * @param num_dumped_dwords - number of dwords that were dumped. | |
3121 | * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed | |
3122 | * results. | |
3123 | * | |
3124 | * @return error if the parsing fails, ok otherwise. | |
3125 | */ | |
3126 | enum dbg_status qed_get_fw_asserts_results_buf_size(struct qed_hwfn *p_hwfn, | |
3127 | u32 *dump_buf, | |
3128 | u32 num_dumped_dwords, | |
3129 | u32 *results_buf_size); | |
3130 | /** | |
3131 | * @brief qed_print_fw_asserts_results - Prints FW Asserts results | |
3132 | * | |
3133 | * @param p_hwfn - HW device data | |
3134 | * @param dump_buf - FW Asserts dump buffer, starting from the header. | |
3135 | * @param num_dumped_dwords - number of dwords that were dumped. | |
3136 | * @param results_buf - buffer for printing the FW Asserts results. | |
3137 | * | |
3138 | * @return error if the parsing fails, ok otherwise. | |
3139 | */ | |
3140 | enum dbg_status qed_print_fw_asserts_results(struct qed_hwfn *p_hwfn, | |
3141 | u32 *dump_buf, | |
3142 | u32 num_dumped_dwords, | |
3143 | char *results_buf); | |
fe56b9e6 | 3144 | /* Win 2 */ |
05fafbfb | 3145 | #define GTT_BAR0_MAP_REG_IGU_CMD 0x00f000UL |
351a4ded | 3146 | |
fe56b9e6 | 3147 | /* Win 3 */ |
05fafbfb | 3148 | #define GTT_BAR0_MAP_REG_TSDM_RAM 0x010000UL |
351a4ded | 3149 | |
fe56b9e6 | 3150 | /* Win 4 */ |
05fafbfb | 3151 | #define GTT_BAR0_MAP_REG_MSDM_RAM 0x011000UL |
351a4ded | 3152 | |
fe56b9e6 | 3153 | /* Win 5 */ |
05fafbfb | 3154 | #define GTT_BAR0_MAP_REG_MSDM_RAM_1024 0x012000UL |
351a4ded | 3155 | |
fe56b9e6 | 3156 | /* Win 6 */ |
05fafbfb | 3157 | #define GTT_BAR0_MAP_REG_USDM_RAM 0x013000UL |
351a4ded | 3158 | |
fe56b9e6 | 3159 | /* Win 7 */ |
05fafbfb | 3160 | #define GTT_BAR0_MAP_REG_USDM_RAM_1024 0x014000UL |
351a4ded | 3161 | |
fe56b9e6 | 3162 | /* Win 8 */ |
05fafbfb | 3163 | #define GTT_BAR0_MAP_REG_USDM_RAM_2048 0x015000UL |
351a4ded | 3164 | |
fe56b9e6 | 3165 | /* Win 9 */ |
05fafbfb | 3166 | #define GTT_BAR0_MAP_REG_XSDM_RAM 0x016000UL |
351a4ded | 3167 | |
fe56b9e6 | 3168 | /* Win 10 */ |
05fafbfb | 3169 | #define GTT_BAR0_MAP_REG_YSDM_RAM 0x017000UL |
351a4ded | 3170 | |
fe56b9e6 | 3171 | /* Win 11 */ |
05fafbfb | 3172 | #define GTT_BAR0_MAP_REG_PSDM_RAM 0x018000UL |
fe56b9e6 YM |
3173 | |
3174 | /** | |
3175 | * @brief qed_qm_pf_mem_size - prepare QM ILT sizes | |
3176 | * | |
3177 | * Returns the required host memory size in 4KB units. | |
3178 | * Must be called before all QM init HSI functions. | |
3179 | * | |
351a4ded YM |
3180 | * @param pf_id - physical function ID |
3181 | * @param num_pf_cids - number of connections used by this PF | |
3182 | * @param num_vf_cids - number of connections used by VFs of this PF | |
3183 | * @param num_tids - number of tasks used by this PF | |
3184 | * @param num_pf_pqs - number of PQs used by this PF | |
3185 | * @param num_vf_pqs - number of PQs used by VFs of this PF | |
fe56b9e6 YM |
3186 | * |
3187 | * @return The required host memory size in 4KB units. | |
3188 | */ | |
351a4ded YM |
3189 | u32 qed_qm_pf_mem_size(u8 pf_id, |
3190 | u32 num_pf_cids, | |
3191 | u32 num_vf_cids, | |
3192 | u32 num_tids, u16 num_pf_pqs, u16 num_vf_pqs); | |
fe56b9e6 YM |
3193 | |
3194 | struct qed_qm_common_rt_init_params { | |
351a4ded YM |
3195 | u8 max_ports_per_engine; |
3196 | u8 max_phys_tcs_per_port; | |
3197 | bool pf_rl_en; | |
3198 | bool pf_wfq_en; | |
3199 | bool vport_rl_en; | |
3200 | bool vport_wfq_en; | |
3201 | struct init_qm_port_params *port_params; | |
fe56b9e6 YM |
3202 | }; |
3203 | ||
351a4ded YM |
3204 | int qed_qm_common_rt_init(struct qed_hwfn *p_hwfn, |
3205 | struct qed_qm_common_rt_init_params *p_params); | |
3206 | ||
3207 | struct qed_qm_pf_rt_init_params { | |
3208 | u8 port_id; | |
3209 | u8 pf_id; | |
3210 | u8 max_phys_tcs_per_port; | |
3211 | bool is_first_pf; | |
3212 | u32 num_pf_cids; | |
3213 | u32 num_vf_cids; | |
3214 | u32 num_tids; | |
3215 | u16 start_pq; | |
3216 | u16 num_pf_pqs; | |
3217 | u16 num_vf_pqs; | |
3218 | u8 start_vport; | |
3219 | u8 num_vports; | |
05fafbfb | 3220 | u16 pf_wfq; |
351a4ded YM |
3221 | u32 pf_rl; |
3222 | struct init_qm_pq_params *pq_params; | |
3223 | struct init_qm_vport_params *vport_params; | |
3224 | }; | |
3225 | ||
3226 | int qed_qm_pf_rt_init(struct qed_hwfn *p_hwfn, | |
3227 | struct qed_ptt *p_ptt, | |
3228 | struct qed_qm_pf_rt_init_params *p_params); | |
3229 | ||
fe56b9e6 | 3230 | /** |
351a4ded | 3231 | * @brief qed_init_pf_wfq - Initializes the WFQ weight of the specified PF |
fe56b9e6 YM |
3232 | * |
3233 | * @param p_hwfn | |
351a4ded YM |
3234 | * @param p_ptt - ptt window used for writing the registers |
3235 | * @param pf_id - PF ID | |
3236 | * @param pf_wfq - WFQ weight. Must be non-zero. | |
fe56b9e6 YM |
3237 | * |
3238 | * @return 0 on success, -1 on error. | |
3239 | */ | |
351a4ded YM |
3240 | int qed_init_pf_wfq(struct qed_hwfn *p_hwfn, |
3241 | struct qed_ptt *p_ptt, u8 pf_id, u16 pf_wfq); | |
fe56b9e6 YM |
3242 | |
3243 | /** | |
351a4ded | 3244 | * @brief qed_init_pf_rl - Initializes the rate limit of the specified PF |
fe56b9e6 YM |
3245 | * |
3246 | * @param p_hwfn | |
351a4ded YM |
3247 | * @param p_ptt - ptt window used for writing the registers |
3248 | * @param pf_id - PF ID | |
3249 | * @param pf_rl - rate limit in Mb/sec units | |
fe56b9e6 YM |
3250 | * |
3251 | * @return 0 on success, -1 on error. | |
3252 | */ | |
351a4ded YM |
3253 | int qed_init_pf_rl(struct qed_hwfn *p_hwfn, |
3254 | struct qed_ptt *p_ptt, u8 pf_id, u32 pf_rl); | |
fe56b9e6 YM |
3255 | |
3256 | /** | |
351a4ded | 3257 | * @brief qed_init_vport_wfq Initializes the WFQ weight of the specified VPORT |
fe56b9e6 YM |
3258 | * |
3259 | * @param p_hwfn | |
351a4ded YM |
3260 | * @param p_ptt - ptt window used for writing the registers |
3261 | * @param first_tx_pq_id- An array containing the first Tx PQ ID associated | |
3262 | * with the VPORT for each TC. This array is filled by | |
3263 | * qed_qm_pf_rt_init | |
3264 | * @param vport_wfq - WFQ weight. Must be non-zero. | |
fe56b9e6 YM |
3265 | * |
3266 | * @return 0 on success, -1 on error. | |
3267 | */ | |
351a4ded YM |
3268 | int qed_init_vport_wfq(struct qed_hwfn *p_hwfn, |
3269 | struct qed_ptt *p_ptt, | |
3270 | u16 first_tx_pq_id[NUM_OF_TCS], u16 vport_wfq); | |
fe56b9e6 | 3271 | |
351a4ded YM |
3272 | /** |
3273 | * @brief qed_init_vport_rl - Initializes the rate limit of the specified VPORT | |
3274 | * | |
3275 | * @param p_hwfn | |
3276 | * @param p_ptt - ptt window used for writing the registers | |
3277 | * @param vport_id - VPORT ID | |
3278 | * @param vport_rl - rate limit in Mb/sec units | |
3279 | * | |
3280 | * @return 0 on success, -1 on error. | |
3281 | */ | |
3282 | int qed_init_vport_rl(struct qed_hwfn *p_hwfn, | |
3283 | struct qed_ptt *p_ptt, u8 vport_id, u32 vport_rl); | |
fe56b9e6 YM |
3284 | /** |
3285 | * @brief qed_send_qm_stop_cmd Sends a stop command to the QM | |
3286 | * | |
3287 | * @param p_hwfn | |
351a4ded | 3288 | * @param p_ptt |
fe56b9e6 | 3289 | * @param is_release_cmd - true for release, false for stop. |
351a4ded YM |
3290 | * @param is_tx_pq - true for Tx PQs, false for Other PQs. |
3291 | * @param start_pq - first PQ ID to stop | |
3292 | * @param num_pqs - Number of PQs to stop, starting from start_pq. | |
fe56b9e6 | 3293 | * |
351a4ded | 3294 | * @return bool, true if successful, false if timeout occured while waiting for QM command done. |
fe56b9e6 | 3295 | */ |
351a4ded YM |
3296 | bool qed_send_qm_stop_cmd(struct qed_hwfn *p_hwfn, |
3297 | struct qed_ptt *p_ptt, | |
3298 | bool is_release_cmd, | |
3299 | bool is_tx_pq, u16 start_pq, u16 num_pqs); | |
fe56b9e6 | 3300 | |
351a4ded YM |
3301 | /** |
3302 | * @brief qed_set_vxlan_dest_port - initializes vxlan tunnel destination udp port | |
3303 | * | |
3304 | * @param p_ptt - ptt window used for writing the registers. | |
3305 | * @param dest_port - vxlan destination udp port. | |
3306 | */ | |
464f6645 | 3307 | void qed_set_vxlan_dest_port(struct qed_hwfn *p_hwfn, |
351a4ded YM |
3308 | struct qed_ptt *p_ptt, u16 dest_port); |
3309 | ||
3310 | /** | |
3311 | * @brief qed_set_vxlan_enable - enable or disable VXLAN tunnel in HW | |
3312 | * | |
3313 | * @param p_ptt - ptt window used for writing the registers. | |
3314 | * @param vxlan_enable - vxlan enable flag. | |
3315 | */ | |
464f6645 MC |
3316 | void qed_set_vxlan_enable(struct qed_hwfn *p_hwfn, |
3317 | struct qed_ptt *p_ptt, bool vxlan_enable); | |
351a4ded YM |
3318 | |
3319 | /** | |
3320 | * @brief qed_set_gre_enable - enable or disable GRE tunnel in HW | |
3321 | * | |
3322 | * @param p_ptt - ptt window used for writing the registers. | |
3323 | * @param eth_gre_enable - eth GRE enable enable flag. | |
3324 | * @param ip_gre_enable - IP GRE enable enable flag. | |
3325 | */ | |
464f6645 | 3326 | void qed_set_gre_enable(struct qed_hwfn *p_hwfn, |
351a4ded YM |
3327 | struct qed_ptt *p_ptt, |
3328 | bool eth_gre_enable, bool ip_gre_enable); | |
3329 | ||
3330 | /** | |
3331 | * @brief qed_set_geneve_dest_port - initializes geneve tunnel destination udp port | |
3332 | * | |
3333 | * @param p_ptt - ptt window used for writing the registers. | |
3334 | * @param dest_port - geneve destination udp port. | |
3335 | */ | |
464f6645 MC |
3336 | void qed_set_geneve_dest_port(struct qed_hwfn *p_hwfn, |
3337 | struct qed_ptt *p_ptt, u16 dest_port); | |
351a4ded YM |
3338 | |
3339 | /** | |
3340 | * @brief qed_set_gre_enable - enable or disable GRE tunnel in HW | |
3341 | * | |
3342 | * @param p_ptt - ptt window used for writing the registers. | |
3343 | * @param eth_geneve_enable - eth GENEVE enable enable flag. | |
3344 | * @param ip_geneve_enable - IP GENEVE enable enable flag. | |
3345 | */ | |
464f6645 | 3346 | void qed_set_geneve_enable(struct qed_hwfn *p_hwfn, |
351a4ded YM |
3347 | struct qed_ptt *p_ptt, |
3348 | bool eth_geneve_enable, bool ip_geneve_enable); | |
3349 | ||
3350 | #define YSTORM_FLOW_CONTROL_MODE_OFFSET (IRO[0].base) | |
3351 | #define YSTORM_FLOW_CONTROL_MODE_SIZE (IRO[0].size) | |
3352 | #define TSTORM_PORT_STAT_OFFSET(port_id) \ | |
3353 | (IRO[1].base + ((port_id) * IRO[1].m1)) | |
3354 | #define TSTORM_PORT_STAT_SIZE (IRO[1].size) | |
05fafbfb YM |
3355 | #define TSTORM_LL2_PORT_STAT_OFFSET(port_id) \ |
3356 | (IRO[2].base + ((port_id) * IRO[2].m1)) | |
3357 | #define TSTORM_LL2_PORT_STAT_SIZE (IRO[2].size) | |
351a4ded YM |
3358 | #define USTORM_VF_PF_CHANNEL_READY_OFFSET(vf_id) \ |
3359 | (IRO[3].base + ((vf_id) * IRO[3].m1)) | |
3360 | #define USTORM_VF_PF_CHANNEL_READY_SIZE (IRO[3].size) | |
3361 | #define USTORM_FLR_FINAL_ACK_OFFSET(pf_id) \ | |
3362 | (IRO[4].base + (pf_id) * IRO[4].m1) | |
3363 | #define USTORM_FLR_FINAL_ACK_SIZE (IRO[4].size) | |
3364 | #define USTORM_EQE_CONS_OFFSET(pf_id) \ | |
3365 | (IRO[5].base + ((pf_id) * IRO[5].m1)) | |
3366 | #define USTORM_EQE_CONS_SIZE (IRO[5].size) | |
3367 | #define USTORM_ETH_QUEUE_ZONE_OFFSET(queue_zone_id) \ | |
3368 | (IRO[6].base + ((queue_zone_id) * IRO[6].m1)) | |
3369 | #define USTORM_ETH_QUEUE_ZONE_SIZE (IRO[6].size) | |
3370 | #define USTORM_COMMON_QUEUE_CONS_OFFSET(queue_zone_id) \ | |
3371 | (IRO[7].base + ((queue_zone_id) * IRO[7].m1)) | |
3372 | #define USTORM_COMMON_QUEUE_CONS_SIZE (IRO[7].size) | |
05fafbfb YM |
3373 | #define TSTORM_LL2_RX_PRODS_OFFSET(core_rx_queue_id) \ |
3374 | (IRO[14].base + ((core_rx_queue_id) * IRO[14].m1)) | |
3375 | #define TSTORM_LL2_RX_PRODS_SIZE (IRO[14].size) | |
3376 | #define CORE_LL2_TSTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) \ | |
3377 | (IRO[15].base + ((core_rx_queue_id) * IRO[15].m1)) | |
3378 | #define CORE_LL2_TSTORM_PER_QUEUE_STAT_SIZE (IRO[15].size) | |
3379 | #define CORE_LL2_USTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) \ | |
3380 | (IRO[16].base + ((core_rx_queue_id) * IRO[16].m1)) | |
3381 | #define CORE_LL2_USTORM_PER_QUEUE_STAT_SIZE (IRO[16].size) | |
3382 | #define CORE_LL2_PSTORM_PER_QUEUE_STAT_OFFSET(core_tx_stats_id) \ | |
3383 | (IRO[17].base + ((core_tx_stats_id) * IRO[17].m1)) | |
3384 | #define CORE_LL2_PSTORM_PER_QUEUE_STAT_SIZE (IRO[17]. size) | |
351a4ded YM |
3385 | #define MSTORM_QUEUE_STAT_OFFSET(stat_counter_id) \ |
3386 | (IRO[18].base + ((stat_counter_id) * IRO[18].m1)) | |
3387 | #define MSTORM_QUEUE_STAT_SIZE (IRO[18].size) | |
3388 | #define MSTORM_ETH_PF_PRODS_OFFSET(queue_id) \ | |
3389 | (IRO[19].base + ((queue_id) * IRO[19].m1)) | |
3390 | #define MSTORM_ETH_PF_PRODS_SIZE (IRO[19].size) | |
05fafbfb YM |
3391 | #define MSTORM_ETH_VF_PRODS_OFFSET(vf_id, vf_queue_id) \ |
3392 | (IRO[20].base + ((vf_id) * IRO[20].m1) + ((vf_queue_id) * IRO[20].m2)) | |
3393 | #define MSTORM_ETH_VF_PRODS_SIZE (IRO[20].size) | |
3394 | #define MSTORM_TPA_TIMEOUT_US_OFFSET (IRO[21].base) | |
3395 | #define MSTORM_TPA_TIMEOUT_US_SIZE (IRO[21].size) | |
351a4ded | 3396 | #define MSTORM_ETH_PF_STAT_OFFSET(pf_id) \ |
05fafbfb | 3397 | (IRO[22].base + ((pf_id) * IRO[22].m1)) |
351a4ded YM |
3398 | #define MSTORM_ETH_PF_STAT_SIZE (IRO[21].size) |
3399 | #define USTORM_QUEUE_STAT_OFFSET(stat_counter_id) \ | |
05fafbfb YM |
3400 | (IRO[23].base + ((stat_counter_id) * IRO[23].m1)) |
3401 | #define USTORM_QUEUE_STAT_SIZE (IRO[23].size) | |
351a4ded | 3402 | #define USTORM_ETH_PF_STAT_OFFSET(pf_id) \ |
05fafbfb YM |
3403 | (IRO[24].base + ((pf_id) * IRO[24].m1)) |
3404 | #define USTORM_ETH_PF_STAT_SIZE (IRO[24].size) | |
351a4ded | 3405 | #define PSTORM_QUEUE_STAT_OFFSET(stat_counter_id) \ |
05fafbfb YM |
3406 | (IRO[25].base + ((stat_counter_id) * IRO[25].m1)) |
3407 | #define PSTORM_QUEUE_STAT_SIZE (IRO[25].size) | |
351a4ded | 3408 | #define PSTORM_ETH_PF_STAT_OFFSET(pf_id) \ |
05fafbfb YM |
3409 | (IRO[26].base + ((pf_id) * IRO[26].m1)) |
3410 | #define PSTORM_ETH_PF_STAT_SIZE (IRO[26].size) | |
351a4ded | 3411 | #define PSTORM_CTL_FRAME_ETHTYPE_OFFSET(ethtype) \ |
05fafbfb YM |
3412 | (IRO[27].base + ((ethtype) * IRO[27].m1)) |
3413 | #define PSTORM_CTL_FRAME_ETHTYPE_SIZE (IRO[27].size) | |
3414 | #define TSTORM_ETH_PRS_INPUT_OFFSET (IRO[28].base) | |
3415 | #define TSTORM_ETH_PRS_INPUT_SIZE (IRO[28].size) | |
351a4ded | 3416 | #define ETH_RX_RATE_LIMIT_OFFSET(pf_id) \ |
05fafbfb YM |
3417 | (IRO[29].base + ((pf_id) * IRO[29].m1)) |
3418 | #define ETH_RX_RATE_LIMIT_SIZE (IRO[29].size) | |
351a4ded | 3419 | #define XSTORM_ETH_QUEUE_ZONE_OFFSET(queue_id) \ |
05fafbfb YM |
3420 | (IRO[30].base + ((queue_id) * IRO[30].m1)) |
3421 | #define XSTORM_ETH_QUEUE_ZONE_SIZE (IRO[30].size) | |
3422 | #define TSTORM_SCSI_CMDQ_CONS_OFFSET(cmdq_queue_id) \ | |
3423 | (IRO[34].base + ((cmdq_queue_id) * IRO[34].m1)) | |
3424 | #define TSTORM_SCSI_CMDQ_CONS_SIZE (IRO[34].size) | |
3425 | #define TSTORM_SCSI_BDQ_EXT_PROD_OFFSET(func_id, bdq_id) \ | |
3426 | (IRO[35].base + ((func_id) * IRO[35].m1) + ((bdq_id) * IRO[35].m2)) | |
3427 | #define TSTORM_SCSI_BDQ_EXT_PROD_SIZE (IRO[35].size) | |
3428 | #define MSTORM_SCSI_BDQ_EXT_PROD_OFFSET(func_id, bdq_id) \ | |
3429 | (IRO[36].base + ((func_id) * IRO[36].m1) + ((bdq_id) * IRO[36].m2)) | |
3430 | #define MSTORM_SCSI_BDQ_EXT_PROD_SIZE (IRO[36].size) | |
3431 | #define TSTORM_ISCSI_RX_STATS_OFFSET(pf_id) \ | |
3432 | (IRO[37].base + ((pf_id) * IRO[37].m1)) | |
3433 | #define TSTORM_ISCSI_RX_STATS_SIZE (IRO[37].size) | |
3434 | #define MSTORM_ISCSI_RX_STATS_OFFSET(pf_id) \ | |
3435 | (IRO[38].base + ((pf_id) * IRO[38].m1)) | |
3436 | #define MSTORM_ISCSI_RX_STATS_SIZE (IRO[38].size) | |
3437 | #define USTORM_ISCSI_RX_STATS_OFFSET(pf_id) \ | |
3438 | (IRO[39].base + ((pf_id) * IRO[39].m1)) | |
3439 | #define USTORM_ISCSI_RX_STATS_SIZE (IRO[39].size) | |
3440 | #define XSTORM_ISCSI_TX_STATS_OFFSET(pf_id) \ | |
3441 | (IRO[40].base + ((pf_id) * IRO[40].m1)) | |
3442 | #define XSTORM_ISCSI_TX_STATS_SIZE (IRO[40].size) | |
3443 | #define YSTORM_ISCSI_TX_STATS_OFFSET(pf_id) \ | |
3444 | (IRO[41].base + ((pf_id) * IRO[41].m1)) | |
3445 | #define YSTORM_ISCSI_TX_STATS_SIZE (IRO[41].size) | |
3446 | #define PSTORM_ISCSI_TX_STATS_OFFSET(pf_id) \ | |
3447 | (IRO[42].base + ((pf_id) * IRO[42].m1)) | |
3448 | #define PSTORM_ISCSI_TX_STATS_SIZE (IRO[42].size) | |
3449 | #define PSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) \ | |
3450 | (IRO[45].base + ((rdma_stat_counter_id) * IRO[45].m1)) | |
3451 | #define PSTORM_RDMA_QUEUE_STAT_SIZE (IRO[45].size) | |
3452 | #define TSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) \ | |
3453 | (IRO[46].base + ((rdma_stat_counter_id) * IRO[46].m1)) | |
3454 | #define TSTORM_RDMA_QUEUE_STAT_SIZE (IRO[46].size) | |
3455 | ||
3456 | static const struct iro iro_arr[47] = { | |
351a4ded YM |
3457 | {0x0, 0x0, 0x0, 0x0, 0x8}, |
3458 | {0x4cb0, 0x78, 0x0, 0x0, 0x78}, | |
3459 | {0x6318, 0x20, 0x0, 0x0, 0x20}, | |
3460 | {0xb00, 0x8, 0x0, 0x0, 0x4}, | |
3461 | {0xa80, 0x8, 0x0, 0x0, 0x4}, | |
3462 | {0x0, 0x8, 0x0, 0x0, 0x2}, | |
3463 | {0x80, 0x8, 0x0, 0x0, 0x4}, | |
3464 | {0x84, 0x8, 0x0, 0x0, 0x2}, | |
3465 | {0x4bc0, 0x0, 0x0, 0x0, 0x78}, | |
3466 | {0x3df0, 0x0, 0x0, 0x0, 0x78}, | |
3467 | {0x29b0, 0x0, 0x0, 0x0, 0x78}, | |
3468 | {0x4c38, 0x0, 0x0, 0x0, 0x78}, | |
05fafbfb | 3469 | {0x4990, 0x0, 0x0, 0x0, 0x78}, |
351a4ded YM |
3470 | {0x7e48, 0x0, 0x0, 0x0, 0x78}, |
3471 | {0xa28, 0x8, 0x0, 0x0, 0x8}, | |
3472 | {0x60f8, 0x10, 0x0, 0x0, 0x10}, | |
3473 | {0xb820, 0x30, 0x0, 0x0, 0x30}, | |
3474 | {0x95b8, 0x30, 0x0, 0x0, 0x30}, | |
05fafbfb | 3475 | {0x4b60, 0x80, 0x0, 0x0, 0x40}, |
351a4ded | 3476 | {0x1f8, 0x4, 0x0, 0x0, 0x4}, |
05fafbfb YM |
3477 | {0x53a0, 0x80, 0x4, 0x0, 0x4}, |
3478 | {0xc8f0, 0x0, 0x0, 0x0, 0x4}, | |
3479 | {0x4ba0, 0x80, 0x0, 0x0, 0x20}, | |
351a4ded YM |
3480 | {0x8050, 0x40, 0x0, 0x0, 0x30}, |
3481 | {0xe770, 0x60, 0x0, 0x0, 0x60}, | |
3482 | {0x2b48, 0x80, 0x0, 0x0, 0x38}, | |
05fafbfb | 3483 | {0xf188, 0x78, 0x0, 0x0, 0x78}, |
351a4ded YM |
3484 | {0x1f8, 0x4, 0x0, 0x0, 0x4}, |
3485 | {0xacf0, 0x0, 0x0, 0x0, 0xf0}, | |
3486 | {0xade0, 0x8, 0x0, 0x0, 0x8}, | |
3487 | {0x1f8, 0x8, 0x0, 0x0, 0x8}, | |
3488 | {0xac0, 0x8, 0x0, 0x0, 0x8}, | |
3489 | {0x2578, 0x8, 0x0, 0x0, 0x8}, | |
3490 | {0x24f8, 0x8, 0x0, 0x0, 0x8}, | |
3491 | {0x0, 0x8, 0x0, 0x0, 0x8}, | |
3492 | {0x200, 0x10, 0x8, 0x0, 0x8}, | |
3493 | {0xb78, 0x10, 0x8, 0x0, 0x2}, | |
3494 | {0xd888, 0x38, 0x0, 0x0, 0x24}, | |
05fafbfb YM |
3495 | {0x12c38, 0x10, 0x0, 0x0, 0x8}, |
3496 | {0x11aa0, 0x38, 0x0, 0x0, 0x18}, | |
351a4ded YM |
3497 | {0xa8c0, 0x30, 0x0, 0x0, 0x10}, |
3498 | {0x86f8, 0x28, 0x0, 0x0, 0x18}, | |
05fafbfb | 3499 | {0x101f8, 0x10, 0x0, 0x0, 0x10}, |
351a4ded | 3500 | {0xdd08, 0x48, 0x0, 0x0, 0x38}, |
05fafbfb | 3501 | {0x10660, 0x20, 0x0, 0x0, 0x20}, |
351a4ded YM |
3502 | {0x2b80, 0x80, 0x0, 0x0, 0x10}, |
3503 | {0x5000, 0x10, 0x0, 0x0, 0x10}, | |
fe56b9e6 YM |
3504 | }; |
3505 | ||
3506 | /* Runtime array offsets */ | |
05fafbfb YM |
3507 | #define DORQ_REG_PF_MAX_ICID_0_RT_OFFSET 0 |
3508 | #define DORQ_REG_PF_MAX_ICID_1_RT_OFFSET 1 | |
3509 | #define DORQ_REG_PF_MAX_ICID_2_RT_OFFSET 2 | |
3510 | #define DORQ_REG_PF_MAX_ICID_3_RT_OFFSET 3 | |
3511 | #define DORQ_REG_PF_MAX_ICID_4_RT_OFFSET 4 | |
3512 | #define DORQ_REG_PF_MAX_ICID_5_RT_OFFSET 5 | |
3513 | #define DORQ_REG_PF_MAX_ICID_6_RT_OFFSET 6 | |
3514 | #define DORQ_REG_PF_MAX_ICID_7_RT_OFFSET 7 | |
3515 | #define DORQ_REG_VF_MAX_ICID_0_RT_OFFSET 8 | |
3516 | #define DORQ_REG_VF_MAX_ICID_1_RT_OFFSET 9 | |
3517 | #define DORQ_REG_VF_MAX_ICID_2_RT_OFFSET 10 | |
3518 | #define DORQ_REG_VF_MAX_ICID_3_RT_OFFSET 11 | |
3519 | #define DORQ_REG_VF_MAX_ICID_4_RT_OFFSET 12 | |
3520 | #define DORQ_REG_VF_MAX_ICID_5_RT_OFFSET 13 | |
3521 | #define DORQ_REG_VF_MAX_ICID_6_RT_OFFSET 14 | |
3522 | #define DORQ_REG_VF_MAX_ICID_7_RT_OFFSET 15 | |
3523 | #define DORQ_REG_PF_WAKE_ALL_RT_OFFSET 16 | |
3524 | #define DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET 17 | |
3525 | #define IGU_REG_PF_CONFIGURATION_RT_OFFSET 18 | |
3526 | #define IGU_REG_VF_CONFIGURATION_RT_OFFSET 19 | |
3527 | #define IGU_REG_ATTN_MSG_ADDR_L_RT_OFFSET 20 | |
3528 | #define IGU_REG_ATTN_MSG_ADDR_H_RT_OFFSET 21 | |
3529 | #define IGU_REG_LEADING_EDGE_LATCH_RT_OFFSET 22 | |
3530 | #define IGU_REG_TRAILING_EDGE_LATCH_RT_OFFSET 23 | |
3531 | #define CAU_REG_CQE_AGG_UNIT_SIZE_RT_OFFSET 24 | |
3532 | #define CAU_REG_SB_VAR_MEMORY_RT_OFFSET 761 | |
3533 | #define CAU_REG_SB_VAR_MEMORY_RT_SIZE 736 | |
3534 | #define CAU_REG_SB_VAR_MEMORY_RT_OFFSET 761 | |
3535 | #define CAU_REG_SB_VAR_MEMORY_RT_SIZE 736 | |
3536 | #define CAU_REG_SB_ADDR_MEMORY_RT_OFFSET 1497 | |
3537 | #define CAU_REG_SB_ADDR_MEMORY_RT_SIZE 736 | |
3538 | #define CAU_REG_PI_MEMORY_RT_OFFSET 2233 | |
3539 | #define CAU_REG_PI_MEMORY_RT_SIZE 4416 | |
3540 | #define PRS_REG_SEARCH_RESP_INITIATOR_TYPE_RT_OFFSET 6649 | |
3541 | #define PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET 6650 | |
3542 | #define PRS_REG_TASK_ID_MAX_INITIATOR_VF_RT_OFFSET 6651 | |
3543 | #define PRS_REG_TASK_ID_MAX_TARGET_PF_RT_OFFSET 6652 | |
3544 | #define PRS_REG_TASK_ID_MAX_TARGET_VF_RT_OFFSET 6653 | |
3545 | #define PRS_REG_SEARCH_TCP_RT_OFFSET 6654 | |
3546 | #define PRS_REG_SEARCH_FCOE_RT_OFFSET 6655 | |
3547 | #define PRS_REG_SEARCH_ROCE_RT_OFFSET 6656 | |
3548 | #define PRS_REG_ROCE_DEST_QP_MAX_VF_RT_OFFSET 6657 | |
3549 | #define PRS_REG_ROCE_DEST_QP_MAX_PF_RT_OFFSET 6658 | |
3550 | #define PRS_REG_SEARCH_OPENFLOW_RT_OFFSET 6659 | |
3551 | #define PRS_REG_SEARCH_NON_IP_AS_OPENFLOW_RT_OFFSET 6660 | |
3552 | #define PRS_REG_OPENFLOW_SUPPORT_ONLY_KNOWN_OVER_IP_RT_OFFSET 6661 | |
3553 | #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_RT_OFFSET 6662 | |
3554 | #define PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET 6663 | |
3555 | #define PRS_REG_LIGHT_L2_ETHERTYPE_EN_RT_OFFSET 6664 | |
3556 | #define SRC_REG_FIRSTFREE_RT_OFFSET 6665 | |
3557 | #define SRC_REG_FIRSTFREE_RT_SIZE 2 | |
3558 | #define SRC_REG_LASTFREE_RT_OFFSET 6667 | |
3559 | #define SRC_REG_LASTFREE_RT_SIZE 2 | |
3560 | #define SRC_REG_COUNTFREE_RT_OFFSET 6669 | |
3561 | #define SRC_REG_NUMBER_HASH_BITS_RT_OFFSET 6670 | |
3562 | #define PSWRQ2_REG_CDUT_P_SIZE_RT_OFFSET 6671 | |
3563 | #define PSWRQ2_REG_CDUC_P_SIZE_RT_OFFSET 6672 | |
3564 | #define PSWRQ2_REG_TM_P_SIZE_RT_OFFSET 6673 | |
3565 | #define PSWRQ2_REG_QM_P_SIZE_RT_OFFSET 6674 | |
3566 | #define PSWRQ2_REG_SRC_P_SIZE_RT_OFFSET 6675 | |
3567 | #define PSWRQ2_REG_TSDM_P_SIZE_RT_OFFSET 6676 | |
3568 | #define PSWRQ2_REG_TM_FIRST_ILT_RT_OFFSET 6677 | |
3569 | #define PSWRQ2_REG_TM_LAST_ILT_RT_OFFSET 6678 | |
3570 | #define PSWRQ2_REG_QM_FIRST_ILT_RT_OFFSET 6679 | |
3571 | #define PSWRQ2_REG_QM_LAST_ILT_RT_OFFSET 6680 | |
3572 | #define PSWRQ2_REG_SRC_FIRST_ILT_RT_OFFSET 6681 | |
3573 | #define PSWRQ2_REG_SRC_LAST_ILT_RT_OFFSET 6682 | |
3574 | #define PSWRQ2_REG_CDUC_FIRST_ILT_RT_OFFSET 6683 | |
3575 | #define PSWRQ2_REG_CDUC_LAST_ILT_RT_OFFSET 6684 | |
3576 | #define PSWRQ2_REG_CDUT_FIRST_ILT_RT_OFFSET 6685 | |
3577 | #define PSWRQ2_REG_CDUT_LAST_ILT_RT_OFFSET 6686 | |
3578 | #define PSWRQ2_REG_TSDM_FIRST_ILT_RT_OFFSET 6687 | |
3579 | #define PSWRQ2_REG_TSDM_LAST_ILT_RT_OFFSET 6688 | |
3580 | #define PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6689 | |
3581 | #define PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6690 | |
3582 | #define PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6691 | |
3583 | #define PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET 6692 | |
3584 | #define PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET 6693 | |
3585 | #define PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET 6694 | |
3586 | #define PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET 6695 | |
3587 | #define PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET 6696 | |
3588 | #define PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET 6697 | |
3589 | #define PSWRQ2_REG_VF_BASE_RT_OFFSET 6698 | |
3590 | #define PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET 6699 | |
3591 | #define PSWRQ2_REG_WR_MBS0_RT_OFFSET 6700 | |
3592 | #define PSWRQ2_REG_RD_MBS0_RT_OFFSET 6701 | |
3593 | #define PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET 6702 | |
3594 | #define PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET 6703 | |
3595 | #define PSWRQ2_REG_ILT_MEMORY_RT_OFFSET 6704 | |
3596 | #define PSWRQ2_REG_ILT_MEMORY_RT_SIZE 22000 | |
3597 | #define PGLUE_REG_B_VF_BASE_RT_OFFSET 28704 | |
3598 | #define PGLUE_REG_B_MSDM_OFFSET_MASK_B_RT_OFFSET 28705 | |
3599 | #define PGLUE_REG_B_MSDM_VF_SHIFT_B_RT_OFFSET 28706 | |
3600 | #define PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET 28707 | |
3601 | #define PGLUE_REG_B_PF_BAR0_SIZE_RT_OFFSET 28708 | |
3602 | #define PGLUE_REG_B_PF_BAR1_SIZE_RT_OFFSET 28709 | |
3603 | #define PGLUE_REG_B_VF_BAR1_SIZE_RT_OFFSET 28710 | |
3604 | #define TM_REG_VF_ENABLE_CONN_RT_OFFSET 28711 | |
3605 | #define TM_REG_PF_ENABLE_CONN_RT_OFFSET 28712 | |
3606 | #define TM_REG_PF_ENABLE_TASK_RT_OFFSET 28713 | |
3607 | #define TM_REG_GROUP_SIZE_RESOLUTION_CONN_RT_OFFSET 28714 | |
3608 | #define TM_REG_GROUP_SIZE_RESOLUTION_TASK_RT_OFFSET 28715 | |
3609 | #define TM_REG_CONFIG_CONN_MEM_RT_OFFSET 28716 | |
3610 | #define TM_REG_CONFIG_CONN_MEM_RT_SIZE 416 | |
3611 | #define TM_REG_CONFIG_TASK_MEM_RT_OFFSET 29132 | |
3612 | #define TM_REG_CONFIG_TASK_MEM_RT_SIZE 512 | |
3613 | #define QM_REG_MAXPQSIZE_0_RT_OFFSET 29644 | |
3614 | #define QM_REG_MAXPQSIZE_1_RT_OFFSET 29645 | |
3615 | #define QM_REG_MAXPQSIZE_2_RT_OFFSET 29646 | |
3616 | #define QM_REG_MAXPQSIZETXSEL_0_RT_OFFSET 29647 | |
3617 | #define QM_REG_MAXPQSIZETXSEL_1_RT_OFFSET 29648 | |
3618 | #define QM_REG_MAXPQSIZETXSEL_2_RT_OFFSET 29649 | |
3619 | #define QM_REG_MAXPQSIZETXSEL_3_RT_OFFSET 29650 | |
3620 | #define QM_REG_MAXPQSIZETXSEL_4_RT_OFFSET 29651 | |
3621 | #define QM_REG_MAXPQSIZETXSEL_5_RT_OFFSET 29652 | |
3622 | #define QM_REG_MAXPQSIZETXSEL_6_RT_OFFSET 29653 | |
3623 | #define QM_REG_MAXPQSIZETXSEL_7_RT_OFFSET 29654 | |
3624 | #define QM_REG_MAXPQSIZETXSEL_8_RT_OFFSET 29655 | |
3625 | #define QM_REG_MAXPQSIZETXSEL_9_RT_OFFSET 29656 | |
3626 | #define QM_REG_MAXPQSIZETXSEL_10_RT_OFFSET 29657 | |
3627 | #define QM_REG_MAXPQSIZETXSEL_11_RT_OFFSET 29658 | |
3628 | #define QM_REG_MAXPQSIZETXSEL_12_RT_OFFSET 29659 | |
3629 | #define QM_REG_MAXPQSIZETXSEL_13_RT_OFFSET 29660 | |
3630 | #define QM_REG_MAXPQSIZETXSEL_14_RT_OFFSET 29661 | |
3631 | #define QM_REG_MAXPQSIZETXSEL_15_RT_OFFSET 29662 | |
3632 | #define QM_REG_MAXPQSIZETXSEL_16_RT_OFFSET 29663 | |
3633 | #define QM_REG_MAXPQSIZETXSEL_17_RT_OFFSET 29664 | |
3634 | #define QM_REG_MAXPQSIZETXSEL_18_RT_OFFSET 29665 | |
3635 | #define QM_REG_MAXPQSIZETXSEL_19_RT_OFFSET 29666 | |
3636 | #define QM_REG_MAXPQSIZETXSEL_20_RT_OFFSET 29667 | |
3637 | #define QM_REG_MAXPQSIZETXSEL_21_RT_OFFSET 29668 | |
3638 | #define QM_REG_MAXPQSIZETXSEL_22_RT_OFFSET 29669 | |
3639 | #define QM_REG_MAXPQSIZETXSEL_23_RT_OFFSET 29670 | |
3640 | #define QM_REG_MAXPQSIZETXSEL_24_RT_OFFSET 29671 | |
3641 | #define QM_REG_MAXPQSIZETXSEL_25_RT_OFFSET 29672 | |
3642 | #define QM_REG_MAXPQSIZETXSEL_26_RT_OFFSET 29673 | |
3643 | #define QM_REG_MAXPQSIZETXSEL_27_RT_OFFSET 29674 | |
3644 | #define QM_REG_MAXPQSIZETXSEL_28_RT_OFFSET 29675 | |
3645 | #define QM_REG_MAXPQSIZETXSEL_29_RT_OFFSET 29676 | |
3646 | #define QM_REG_MAXPQSIZETXSEL_30_RT_OFFSET 29677 | |
3647 | #define QM_REG_MAXPQSIZETXSEL_31_RT_OFFSET 29678 | |
3648 | #define QM_REG_MAXPQSIZETXSEL_32_RT_OFFSET 29679 | |
3649 | #define QM_REG_MAXPQSIZETXSEL_33_RT_OFFSET 29680 | |
3650 | #define QM_REG_MAXPQSIZETXSEL_34_RT_OFFSET 29681 | |
3651 | #define QM_REG_MAXPQSIZETXSEL_35_RT_OFFSET 29682 | |
3652 | #define QM_REG_MAXPQSIZETXSEL_36_RT_OFFSET 29683 | |
3653 | #define QM_REG_MAXPQSIZETXSEL_37_RT_OFFSET 29684 | |
3654 | #define QM_REG_MAXPQSIZETXSEL_38_RT_OFFSET 29685 | |
3655 | #define QM_REG_MAXPQSIZETXSEL_39_RT_OFFSET 29686 | |
3656 | #define QM_REG_MAXPQSIZETXSEL_40_RT_OFFSET 29687 | |
3657 | #define QM_REG_MAXPQSIZETXSEL_41_RT_OFFSET 29688 | |
3658 | #define QM_REG_MAXPQSIZETXSEL_42_RT_OFFSET 29689 | |
3659 | #define QM_REG_MAXPQSIZETXSEL_43_RT_OFFSET 29690 | |
3660 | #define QM_REG_MAXPQSIZETXSEL_44_RT_OFFSET 29691 | |
3661 | #define QM_REG_MAXPQSIZETXSEL_45_RT_OFFSET 29692 | |
3662 | #define QM_REG_MAXPQSIZETXSEL_46_RT_OFFSET 29693 | |
3663 | #define QM_REG_MAXPQSIZETXSEL_47_RT_OFFSET 29694 | |
3664 | #define QM_REG_MAXPQSIZETXSEL_48_RT_OFFSET 29695 | |
3665 | #define QM_REG_MAXPQSIZETXSEL_49_RT_OFFSET 29696 | |
3666 | #define QM_REG_MAXPQSIZETXSEL_50_RT_OFFSET 29697 | |
3667 | #define QM_REG_MAXPQSIZETXSEL_51_RT_OFFSET 29698 | |
3668 | #define QM_REG_MAXPQSIZETXSEL_52_RT_OFFSET 29699 | |
3669 | #define QM_REG_MAXPQSIZETXSEL_53_RT_OFFSET 29700 | |
3670 | #define QM_REG_MAXPQSIZETXSEL_54_RT_OFFSET 29701 | |
3671 | #define QM_REG_MAXPQSIZETXSEL_55_RT_OFFSET 29702 | |
3672 | #define QM_REG_MAXPQSIZETXSEL_56_RT_OFFSET 29703 | |
3673 | #define QM_REG_MAXPQSIZETXSEL_57_RT_OFFSET 29704 | |
3674 | #define QM_REG_MAXPQSIZETXSEL_58_RT_OFFSET 29705 | |
3675 | #define QM_REG_MAXPQSIZETXSEL_59_RT_OFFSET 29706 | |
3676 | #define QM_REG_MAXPQSIZETXSEL_60_RT_OFFSET 29707 | |
3677 | #define QM_REG_MAXPQSIZETXSEL_61_RT_OFFSET 29708 | |
3678 | #define QM_REG_MAXPQSIZETXSEL_62_RT_OFFSET 29709 | |
3679 | #define QM_REG_MAXPQSIZETXSEL_63_RT_OFFSET 29710 | |
3680 | #define QM_REG_BASEADDROTHERPQ_RT_OFFSET 29711 | |
3681 | #define QM_REG_BASEADDROTHERPQ_RT_SIZE 128 | |
3682 | #define QM_REG_VOQCRDLINE_RT_OFFSET 29839 | |
3683 | #define QM_REG_VOQCRDLINE_RT_SIZE 20 | |
3684 | #define QM_REG_VOQINITCRDLINE_RT_OFFSET 29859 | |
3685 | #define QM_REG_VOQINITCRDLINE_RT_SIZE 20 | |
3686 | #define QM_REG_AFULLQMBYPTHRPFWFQ_RT_OFFSET 29879 | |
3687 | #define QM_REG_AFULLQMBYPTHRVPWFQ_RT_OFFSET 29880 | |
3688 | #define QM_REG_AFULLQMBYPTHRPFRL_RT_OFFSET 29881 | |
3689 | #define QM_REG_AFULLQMBYPTHRGLBLRL_RT_OFFSET 29882 | |
3690 | #define QM_REG_AFULLOPRTNSTCCRDMASK_RT_OFFSET 29883 | |
3691 | #define QM_REG_WRROTHERPQGRP_0_RT_OFFSET 29884 | |
3692 | #define QM_REG_WRROTHERPQGRP_1_RT_OFFSET 29885 | |
3693 | #define QM_REG_WRROTHERPQGRP_2_RT_OFFSET 29886 | |
3694 | #define QM_REG_WRROTHERPQGRP_3_RT_OFFSET 29887 | |
3695 | #define QM_REG_WRROTHERPQGRP_4_RT_OFFSET 29888 | |
3696 | #define QM_REG_WRROTHERPQGRP_5_RT_OFFSET 29889 | |
3697 | #define QM_REG_WRROTHERPQGRP_6_RT_OFFSET 29890 | |
3698 | #define QM_REG_WRROTHERPQGRP_7_RT_OFFSET 29891 | |
3699 | #define QM_REG_WRROTHERPQGRP_8_RT_OFFSET 29892 | |
3700 | #define QM_REG_WRROTHERPQGRP_9_RT_OFFSET 29893 | |
3701 | #define QM_REG_WRROTHERPQGRP_10_RT_OFFSET 29894 | |
3702 | #define QM_REG_WRROTHERPQGRP_11_RT_OFFSET 29895 | |
3703 | #define QM_REG_WRROTHERPQGRP_12_RT_OFFSET 29896 | |
3704 | #define QM_REG_WRROTHERPQGRP_13_RT_OFFSET 29897 | |
3705 | #define QM_REG_WRROTHERPQGRP_14_RT_OFFSET 29898 | |
3706 | #define QM_REG_WRROTHERPQGRP_15_RT_OFFSET 29899 | |
3707 | #define QM_REG_WRROTHERGRPWEIGHT_0_RT_OFFSET 29900 | |
3708 | #define QM_REG_WRROTHERGRPWEIGHT_1_RT_OFFSET 29901 | |
3709 | #define QM_REG_WRROTHERGRPWEIGHT_2_RT_OFFSET 29902 | |
3710 | #define QM_REG_WRROTHERGRPWEIGHT_3_RT_OFFSET 29903 | |
3711 | #define QM_REG_WRRTXGRPWEIGHT_0_RT_OFFSET 29904 | |
3712 | #define QM_REG_WRRTXGRPWEIGHT_1_RT_OFFSET 29905 | |
3713 | #define QM_REG_PQTX2PF_0_RT_OFFSET 29906 | |
3714 | #define QM_REG_PQTX2PF_1_RT_OFFSET 29907 | |
3715 | #define QM_REG_PQTX2PF_2_RT_OFFSET 29908 | |
3716 | #define QM_REG_PQTX2PF_3_RT_OFFSET 29909 | |
3717 | #define QM_REG_PQTX2PF_4_RT_OFFSET 29910 | |
3718 | #define QM_REG_PQTX2PF_5_RT_OFFSET 29911 | |
3719 | #define QM_REG_PQTX2PF_6_RT_OFFSET 29912 | |
3720 | #define QM_REG_PQTX2PF_7_RT_OFFSET 29913 | |
3721 | #define QM_REG_PQTX2PF_8_RT_OFFSET 29914 | |
3722 | #define QM_REG_PQTX2PF_9_RT_OFFSET 29915 | |
3723 | #define QM_REG_PQTX2PF_10_RT_OFFSET 29916 | |
3724 | #define QM_REG_PQTX2PF_11_RT_OFFSET 29917 | |
3725 | #define QM_REG_PQTX2PF_12_RT_OFFSET 29918 | |
3726 | #define QM_REG_PQTX2PF_13_RT_OFFSET 29919 | |
3727 | #define QM_REG_PQTX2PF_14_RT_OFFSET 29920 | |
3728 | #define QM_REG_PQTX2PF_15_RT_OFFSET 29921 | |
3729 | #define QM_REG_PQTX2PF_16_RT_OFFSET 29922 | |
3730 | #define QM_REG_PQTX2PF_17_RT_OFFSET 29923 | |
3731 | #define QM_REG_PQTX2PF_18_RT_OFFSET 29924 | |
3732 | #define QM_REG_PQTX2PF_19_RT_OFFSET 29925 | |
3733 | #define QM_REG_PQTX2PF_20_RT_OFFSET 29926 | |
3734 | #define QM_REG_PQTX2PF_21_RT_OFFSET 29927 | |
3735 | #define QM_REG_PQTX2PF_22_RT_OFFSET 29928 | |
3736 | #define QM_REG_PQTX2PF_23_RT_OFFSET 29929 | |
3737 | #define QM_REG_PQTX2PF_24_RT_OFFSET 29930 | |
3738 | #define QM_REG_PQTX2PF_25_RT_OFFSET 29931 | |
3739 | #define QM_REG_PQTX2PF_26_RT_OFFSET 29932 | |
3740 | #define QM_REG_PQTX2PF_27_RT_OFFSET 29933 | |
3741 | #define QM_REG_PQTX2PF_28_RT_OFFSET 29934 | |
3742 | #define QM_REG_PQTX2PF_29_RT_OFFSET 29935 | |
3743 | #define QM_REG_PQTX2PF_30_RT_OFFSET 29936 | |
3744 | #define QM_REG_PQTX2PF_31_RT_OFFSET 29937 | |
3745 | #define QM_REG_PQTX2PF_32_RT_OFFSET 29938 | |
3746 | #define QM_REG_PQTX2PF_33_RT_OFFSET 29939 | |
3747 | #define QM_REG_PQTX2PF_34_RT_OFFSET 29940 | |
3748 | #define QM_REG_PQTX2PF_35_RT_OFFSET 29941 | |
3749 | #define QM_REG_PQTX2PF_36_RT_OFFSET 29942 | |
3750 | #define QM_REG_PQTX2PF_37_RT_OFFSET 29943 | |
3751 | #define QM_REG_PQTX2PF_38_RT_OFFSET 29944 | |
3752 | #define QM_REG_PQTX2PF_39_RT_OFFSET 29945 | |
3753 | #define QM_REG_PQTX2PF_40_RT_OFFSET 29946 | |
3754 | #define QM_REG_PQTX2PF_41_RT_OFFSET 29947 | |
3755 | #define QM_REG_PQTX2PF_42_RT_OFFSET 29948 | |
3756 | #define QM_REG_PQTX2PF_43_RT_OFFSET 29949 | |
3757 | #define QM_REG_PQTX2PF_44_RT_OFFSET 29950 | |
3758 | #define QM_REG_PQTX2PF_45_RT_OFFSET 29951 | |
3759 | #define QM_REG_PQTX2PF_46_RT_OFFSET 29952 | |
3760 | #define QM_REG_PQTX2PF_47_RT_OFFSET 29953 | |
3761 | #define QM_REG_PQTX2PF_48_RT_OFFSET 29954 | |
3762 | #define QM_REG_PQTX2PF_49_RT_OFFSET 29955 | |
3763 | #define QM_REG_PQTX2PF_50_RT_OFFSET 29956 | |
3764 | #define QM_REG_PQTX2PF_51_RT_OFFSET 29957 | |
3765 | #define QM_REG_PQTX2PF_52_RT_OFFSET 29958 | |
3766 | #define QM_REG_PQTX2PF_53_RT_OFFSET 29959 | |
3767 | #define QM_REG_PQTX2PF_54_RT_OFFSET 29960 | |
3768 | #define QM_REG_PQTX2PF_55_RT_OFFSET 29961 | |
3769 | #define QM_REG_PQTX2PF_56_RT_OFFSET 29962 | |
3770 | #define QM_REG_PQTX2PF_57_RT_OFFSET 29963 | |
3771 | #define QM_REG_PQTX2PF_58_RT_OFFSET 29964 | |
3772 | #define QM_REG_PQTX2PF_59_RT_OFFSET 29965 | |
3773 | #define QM_REG_PQTX2PF_60_RT_OFFSET 29966 | |
3774 | #define QM_REG_PQTX2PF_61_RT_OFFSET 29967 | |
3775 | #define QM_REG_PQTX2PF_62_RT_OFFSET 29968 | |
3776 | #define QM_REG_PQTX2PF_63_RT_OFFSET 29969 | |
3777 | #define QM_REG_PQOTHER2PF_0_RT_OFFSET 29970 | |
3778 | #define QM_REG_PQOTHER2PF_1_RT_OFFSET 29971 | |
3779 | #define QM_REG_PQOTHER2PF_2_RT_OFFSET 29972 | |
3780 | #define QM_REG_PQOTHER2PF_3_RT_OFFSET 29973 | |
3781 | #define QM_REG_PQOTHER2PF_4_RT_OFFSET 29974 | |
3782 | #define QM_REG_PQOTHER2PF_5_RT_OFFSET 29975 | |
3783 | #define QM_REG_PQOTHER2PF_6_RT_OFFSET 29976 | |
3784 | #define QM_REG_PQOTHER2PF_7_RT_OFFSET 29977 | |
3785 | #define QM_REG_PQOTHER2PF_8_RT_OFFSET 29978 | |
3786 | #define QM_REG_PQOTHER2PF_9_RT_OFFSET 29979 | |
3787 | #define QM_REG_PQOTHER2PF_10_RT_OFFSET 29980 | |
3788 | #define QM_REG_PQOTHER2PF_11_RT_OFFSET 29981 | |
3789 | #define QM_REG_PQOTHER2PF_12_RT_OFFSET 29982 | |
3790 | #define QM_REG_PQOTHER2PF_13_RT_OFFSET 29983 | |
3791 | #define QM_REG_PQOTHER2PF_14_RT_OFFSET 29984 | |
3792 | #define QM_REG_PQOTHER2PF_15_RT_OFFSET 29985 | |
3793 | #define QM_REG_RLGLBLPERIOD_0_RT_OFFSET 29986 | |
3794 | #define QM_REG_RLGLBLPERIOD_1_RT_OFFSET 29987 | |
3795 | #define QM_REG_RLGLBLPERIODTIMER_0_RT_OFFSET 29988 | |
3796 | #define QM_REG_RLGLBLPERIODTIMER_1_RT_OFFSET 29989 | |
3797 | #define QM_REG_RLGLBLPERIODSEL_0_RT_OFFSET 29990 | |
3798 | #define QM_REG_RLGLBLPERIODSEL_1_RT_OFFSET 29991 | |
3799 | #define QM_REG_RLGLBLPERIODSEL_2_RT_OFFSET 29992 | |
3800 | #define QM_REG_RLGLBLPERIODSEL_3_RT_OFFSET 29993 | |
3801 | #define QM_REG_RLGLBLPERIODSEL_4_RT_OFFSET 29994 | |
3802 | #define QM_REG_RLGLBLPERIODSEL_5_RT_OFFSET 29995 | |
3803 | #define QM_REG_RLGLBLPERIODSEL_6_RT_OFFSET 29996 | |
3804 | #define QM_REG_RLGLBLPERIODSEL_7_RT_OFFSET 29997 | |
3805 | #define QM_REG_RLGLBLINCVAL_RT_OFFSET 29998 | |
3806 | #define QM_REG_RLGLBLINCVAL_RT_SIZE 256 | |
3807 | #define QM_REG_RLGLBLUPPERBOUND_RT_OFFSET 30254 | |
3808 | #define QM_REG_RLGLBLUPPERBOUND_RT_SIZE 256 | |
3809 | #define QM_REG_RLGLBLCRD_RT_OFFSET 30510 | |
3810 | #define QM_REG_RLGLBLCRD_RT_SIZE 256 | |
3811 | #define QM_REG_RLGLBLENABLE_RT_OFFSET 30766 | |
3812 | #define QM_REG_RLPFPERIOD_RT_OFFSET 30767 | |
3813 | #define QM_REG_RLPFPERIODTIMER_RT_OFFSET 30768 | |
3814 | #define QM_REG_RLPFINCVAL_RT_OFFSET 30769 | |
3815 | #define QM_REG_RLPFINCVAL_RT_SIZE 16 | |
3816 | #define QM_REG_RLPFUPPERBOUND_RT_OFFSET 30785 | |
3817 | #define QM_REG_RLPFUPPERBOUND_RT_SIZE 16 | |
3818 | #define QM_REG_RLPFCRD_RT_OFFSET 30801 | |
3819 | #define QM_REG_RLPFCRD_RT_SIZE 16 | |
3820 | #define QM_REG_RLPFENABLE_RT_OFFSET 30817 | |
3821 | #define QM_REG_RLPFVOQENABLE_RT_OFFSET 30818 | |
3822 | #define QM_REG_WFQPFWEIGHT_RT_OFFSET 30819 | |
3823 | #define QM_REG_WFQPFWEIGHT_RT_SIZE 16 | |
3824 | #define QM_REG_WFQPFUPPERBOUND_RT_OFFSET 30835 | |
3825 | #define QM_REG_WFQPFUPPERBOUND_RT_SIZE 16 | |
3826 | #define QM_REG_WFQPFCRD_RT_OFFSET 30851 | |
3827 | #define QM_REG_WFQPFCRD_RT_SIZE 160 | |
3828 | #define QM_REG_WFQPFENABLE_RT_OFFSET 31011 | |
3829 | #define QM_REG_WFQVPENABLE_RT_OFFSET 31012 | |
3830 | #define QM_REG_BASEADDRTXPQ_RT_OFFSET 31013 | |
3831 | #define QM_REG_BASEADDRTXPQ_RT_SIZE 512 | |
3832 | #define QM_REG_TXPQMAP_RT_OFFSET 31525 | |
3833 | #define QM_REG_TXPQMAP_RT_SIZE 512 | |
3834 | #define QM_REG_WFQVPWEIGHT_RT_OFFSET 32037 | |
3835 | #define QM_REG_WFQVPWEIGHT_RT_SIZE 512 | |
3836 | #define QM_REG_WFQVPCRD_RT_OFFSET 32549 | |
3837 | #define QM_REG_WFQVPCRD_RT_SIZE 512 | |
3838 | #define QM_REG_WFQVPMAP_RT_OFFSET 33061 | |
3839 | #define QM_REG_WFQVPMAP_RT_SIZE 512 | |
3840 | #define QM_REG_WFQPFCRD_MSB_RT_OFFSET 33573 | |
3841 | #define QM_REG_WFQPFCRD_MSB_RT_SIZE 160 | |
3842 | #define NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET 33733 | |
3843 | #define NIG_REG_OUTER_TAG_VALUE_LIST0_RT_OFFSET 33734 | |
3844 | #define NIG_REG_OUTER_TAG_VALUE_LIST1_RT_OFFSET 33735 | |
3845 | #define NIG_REG_OUTER_TAG_VALUE_LIST2_RT_OFFSET 33736 | |
3846 | #define NIG_REG_OUTER_TAG_VALUE_LIST3_RT_OFFSET 33737 | |
3847 | #define NIG_REG_OUTER_TAG_VALUE_MASK_RT_OFFSET 33738 | |
3848 | #define NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET 33739 | |
3849 | #define NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET 33740 | |
3850 | #define NIG_REG_LLH_FUNC_TAG_EN_RT_SIZE 4 | |
3851 | #define NIG_REG_LLH_FUNC_TAG_HDR_SEL_RT_OFFSET 33744 | |
3852 | #define NIG_REG_LLH_FUNC_TAG_HDR_SEL_RT_SIZE 4 | |
3853 | #define NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET 33748 | |
3854 | #define NIG_REG_LLH_FUNC_TAG_VALUE_RT_SIZE 4 | |
3855 | #define NIG_REG_LLH_FUNC_NO_TAG_RT_OFFSET 33752 | |
3856 | #define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_OFFSET 33753 | |
3857 | #define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_SIZE 32 | |
3858 | #define NIG_REG_LLH_FUNC_FILTER_EN_RT_OFFSET 33785 | |
3859 | #define NIG_REG_LLH_FUNC_FILTER_EN_RT_SIZE 16 | |
3860 | #define NIG_REG_LLH_FUNC_FILTER_MODE_RT_OFFSET 33801 | |
3861 | #define NIG_REG_LLH_FUNC_FILTER_MODE_RT_SIZE 16 | |
3862 | #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET 33817 | |
3863 | #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_SIZE 16 | |
3864 | #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET 33833 | |
3865 | #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_SIZE 16 | |
3866 | #define NIG_REG_TX_EDPM_CTRL_RT_OFFSET 33849 | |
3867 | #define NIG_REG_ROCE_DUPLICATE_TO_HOST_RT_OFFSET 33850 | |
3868 | #define CDU_REG_CID_ADDR_PARAMS_RT_OFFSET 33851 | |
3869 | #define CDU_REG_SEGMENT0_PARAMS_RT_OFFSET 33852 | |
3870 | #define CDU_REG_SEGMENT1_PARAMS_RT_OFFSET 33853 | |
3871 | #define CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET 33854 | |
3872 | #define CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET 33855 | |
3873 | #define CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET 33856 | |
3874 | #define CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET 33857 | |
3875 | #define CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET 33858 | |
3876 | #define CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET 33859 | |
3877 | #define CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET 33860 | |
3878 | #define CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET 33861 | |
3879 | #define CDU_REG_VF_SEG_TYPE_OFFSET_RT_OFFSET 33862 | |
3880 | #define CDU_REG_VF_FL_SEG_TYPE_OFFSET_RT_OFFSET 33863 | |
3881 | #define PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET 33864 | |
3882 | #define PBF_REG_BTB_SHARED_AREA_SIZE_RT_OFFSET 33865 | |
3883 | #define PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET 33866 | |
3884 | #define PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET 33867 | |
3885 | #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_RT_OFFSET 33868 | |
3886 | #define PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET 33869 | |
3887 | #define PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET 33870 | |
3888 | #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_RT_OFFSET 33871 | |
3889 | #define PBF_REG_YCMD_QS_NUM_LINES_VOQ2_RT_OFFSET 33872 | |
3890 | #define PBF_REG_BTB_GUARANTEED_VOQ2_RT_OFFSET 33873 | |
3891 | #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_RT_OFFSET 33874 | |
3892 | #define PBF_REG_YCMD_QS_NUM_LINES_VOQ3_RT_OFFSET 33875 | |
3893 | #define PBF_REG_BTB_GUARANTEED_VOQ3_RT_OFFSET 33876 | |
3894 | #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_RT_OFFSET 33877 | |
3895 | #define PBF_REG_YCMD_QS_NUM_LINES_VOQ4_RT_OFFSET 33878 | |
3896 | #define PBF_REG_BTB_GUARANTEED_VOQ4_RT_OFFSET 33879 | |
3897 | #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_RT_OFFSET 33880 | |
3898 | #define PBF_REG_YCMD_QS_NUM_LINES_VOQ5_RT_OFFSET 33881 | |
3899 | #define PBF_REG_BTB_GUARANTEED_VOQ5_RT_OFFSET 33882 | |
3900 | #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_RT_OFFSET 33883 | |
3901 | #define PBF_REG_YCMD_QS_NUM_LINES_VOQ6_RT_OFFSET 33884 | |
3902 | #define PBF_REG_BTB_GUARANTEED_VOQ6_RT_OFFSET 33885 | |
3903 | #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_RT_OFFSET 33886 | |
3904 | #define PBF_REG_YCMD_QS_NUM_LINES_VOQ7_RT_OFFSET 33887 | |
3905 | #define PBF_REG_BTB_GUARANTEED_VOQ7_RT_OFFSET 33888 | |
3906 | #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_RT_OFFSET 33889 | |
3907 | #define PBF_REG_YCMD_QS_NUM_LINES_VOQ8_RT_OFFSET 33890 | |
3908 | #define PBF_REG_BTB_GUARANTEED_VOQ8_RT_OFFSET 33891 | |
3909 | #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_RT_OFFSET 33892 | |
3910 | #define PBF_REG_YCMD_QS_NUM_LINES_VOQ9_RT_OFFSET 33893 | |
3911 | #define PBF_REG_BTB_GUARANTEED_VOQ9_RT_OFFSET 33894 | |
3912 | #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_RT_OFFSET 33895 | |
3913 | #define PBF_REG_YCMD_QS_NUM_LINES_VOQ10_RT_OFFSET 33896 | |
3914 | #define PBF_REG_BTB_GUARANTEED_VOQ10_RT_OFFSET 33897 | |
3915 | #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_RT_OFFSET 33898 | |
3916 | #define PBF_REG_YCMD_QS_NUM_LINES_VOQ11_RT_OFFSET 33899 | |
3917 | #define PBF_REG_BTB_GUARANTEED_VOQ11_RT_OFFSET 33900 | |
3918 | #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_RT_OFFSET 33901 | |
3919 | #define PBF_REG_YCMD_QS_NUM_LINES_VOQ12_RT_OFFSET 33902 | |
3920 | #define PBF_REG_BTB_GUARANTEED_VOQ12_RT_OFFSET 33903 | |
3921 | #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_RT_OFFSET 33904 | |
3922 | #define PBF_REG_YCMD_QS_NUM_LINES_VOQ13_RT_OFFSET 33905 | |
3923 | #define PBF_REG_BTB_GUARANTEED_VOQ13_RT_OFFSET 33906 | |
3924 | #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_RT_OFFSET 33907 | |
3925 | #define PBF_REG_YCMD_QS_NUM_LINES_VOQ14_RT_OFFSET 33908 | |
3926 | #define PBF_REG_BTB_GUARANTEED_VOQ14_RT_OFFSET 33909 | |
3927 | #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_RT_OFFSET 33910 | |
3928 | #define PBF_REG_YCMD_QS_NUM_LINES_VOQ15_RT_OFFSET 33911 | |
3929 | #define PBF_REG_BTB_GUARANTEED_VOQ15_RT_OFFSET 33912 | |
3930 | #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_RT_OFFSET 33913 | |
3931 | #define PBF_REG_YCMD_QS_NUM_LINES_VOQ16_RT_OFFSET 33914 | |
3932 | #define PBF_REG_BTB_GUARANTEED_VOQ16_RT_OFFSET 33915 | |
3933 | #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_RT_OFFSET 33916 | |
3934 | #define PBF_REG_YCMD_QS_NUM_LINES_VOQ17_RT_OFFSET 33917 | |
3935 | #define PBF_REG_BTB_GUARANTEED_VOQ17_RT_OFFSET 33918 | |
3936 | #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_RT_OFFSET 33919 | |
3937 | #define PBF_REG_YCMD_QS_NUM_LINES_VOQ18_RT_OFFSET 33920 | |
3938 | #define PBF_REG_BTB_GUARANTEED_VOQ18_RT_OFFSET 33921 | |
3939 | #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_RT_OFFSET 33922 | |
3940 | #define PBF_REG_YCMD_QS_NUM_LINES_VOQ19_RT_OFFSET 33923 | |
3941 | #define PBF_REG_BTB_GUARANTEED_VOQ19_RT_OFFSET 33924 | |
3942 | #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_RT_OFFSET 33925 | |
3943 | #define XCM_REG_CON_PHY_Q3_RT_OFFSET 33926 | |
3944 | ||
3945 | #define RUNTIME_ARRAY_SIZE 33927 | |
fe56b9e6 | 3946 | |
fc48b7a6 YM |
3947 | /* The eth storm context for the Tstorm */ |
3948 | struct tstorm_eth_conn_st_ctx { | |
fe56b9e6 YM |
3949 | __le32 reserved[4]; |
3950 | }; | |
3951 | ||
3952 | /* The eth storm context for the Pstorm */ | |
3953 | struct pstorm_eth_conn_st_ctx { | |
3954 | __le32 reserved[8]; | |
3955 | }; | |
3956 | ||
3957 | /* The eth storm context for the Xstorm */ | |
3958 | struct xstorm_eth_conn_st_ctx { | |
3959 | __le32 reserved[60]; | |
3960 | }; | |
3961 | ||
3962 | struct xstorm_eth_conn_ag_ctx { | |
351a4ded YM |
3963 | u8 reserved0; |
3964 | u8 eth_state; | |
3965 | u8 flags0; | |
3966 | #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 | |
3967 | #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 | |
3968 | #define XSTORM_ETH_CONN_AG_CTX_RESERVED1_MASK 0x1 | |
3969 | #define XSTORM_ETH_CONN_AG_CTX_RESERVED1_SHIFT 1 | |
3970 | #define XSTORM_ETH_CONN_AG_CTX_RESERVED2_MASK 0x1 | |
3971 | #define XSTORM_ETH_CONN_AG_CTX_RESERVED2_SHIFT 2 | |
3972 | #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 | |
3973 | #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 | |
3974 | #define XSTORM_ETH_CONN_AG_CTX_RESERVED3_MASK 0x1 | |
3975 | #define XSTORM_ETH_CONN_AG_CTX_RESERVED3_SHIFT 4 | |
3976 | #define XSTORM_ETH_CONN_AG_CTX_RESERVED4_MASK 0x1 | |
3977 | #define XSTORM_ETH_CONN_AG_CTX_RESERVED4_SHIFT 5 | |
3978 | #define XSTORM_ETH_CONN_AG_CTX_RESERVED5_MASK 0x1 | |
3979 | #define XSTORM_ETH_CONN_AG_CTX_RESERVED5_SHIFT 6 | |
3980 | #define XSTORM_ETH_CONN_AG_CTX_RESERVED6_MASK 0x1 | |
3981 | #define XSTORM_ETH_CONN_AG_CTX_RESERVED6_SHIFT 7 | |
3982 | u8 flags1; | |
3983 | #define XSTORM_ETH_CONN_AG_CTX_RESERVED7_MASK 0x1 | |
3984 | #define XSTORM_ETH_CONN_AG_CTX_RESERVED7_SHIFT 0 | |
3985 | #define XSTORM_ETH_CONN_AG_CTX_RESERVED8_MASK 0x1 | |
3986 | #define XSTORM_ETH_CONN_AG_CTX_RESERVED8_SHIFT 1 | |
3987 | #define XSTORM_ETH_CONN_AG_CTX_RESERVED9_MASK 0x1 | |
3988 | #define XSTORM_ETH_CONN_AG_CTX_RESERVED9_SHIFT 2 | |
3989 | #define XSTORM_ETH_CONN_AG_CTX_BIT11_MASK 0x1 | |
3990 | #define XSTORM_ETH_CONN_AG_CTX_BIT11_SHIFT 3 | |
3991 | #define XSTORM_ETH_CONN_AG_CTX_BIT12_MASK 0x1 | |
3992 | #define XSTORM_ETH_CONN_AG_CTX_BIT12_SHIFT 4 | |
3993 | #define XSTORM_ETH_CONN_AG_CTX_BIT13_MASK 0x1 | |
3994 | #define XSTORM_ETH_CONN_AG_CTX_BIT13_SHIFT 5 | |
3995 | #define XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1 | |
3996 | #define XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6 | |
3997 | #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1 | |
3998 | #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7 | |
fe56b9e6 | 3999 | u8 flags2; |
351a4ded YM |
4000 | #define XSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 |
4001 | #define XSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 0 | |
4002 | #define XSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 | |
4003 | #define XSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 2 | |
4004 | #define XSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 | |
4005 | #define XSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 4 | |
4006 | #define XSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3 | |
4007 | #define XSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 6 | |
fe56b9e6 | 4008 | u8 flags3; |
351a4ded YM |
4009 | #define XSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3 |
4010 | #define XSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 0 | |
4011 | #define XSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3 | |
4012 | #define XSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 2 | |
4013 | #define XSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3 | |
4014 | #define XSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 4 | |
4015 | #define XSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3 | |
4016 | #define XSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 6 | |
4017 | u8 flags4; | |
4018 | #define XSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3 | |
4019 | #define XSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 0 | |
4020 | #define XSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3 | |
4021 | #define XSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 2 | |
4022 | #define XSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3 | |
4023 | #define XSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 4 | |
4024 | #define XSTORM_ETH_CONN_AG_CTX_CF11_MASK 0x3 | |
4025 | #define XSTORM_ETH_CONN_AG_CTX_CF11_SHIFT 6 | |
fe56b9e6 | 4026 | u8 flags5; |
351a4ded YM |
4027 | #define XSTORM_ETH_CONN_AG_CTX_CF12_MASK 0x3 |
4028 | #define XSTORM_ETH_CONN_AG_CTX_CF12_SHIFT 0 | |
4029 | #define XSTORM_ETH_CONN_AG_CTX_CF13_MASK 0x3 | |
4030 | #define XSTORM_ETH_CONN_AG_CTX_CF13_SHIFT 2 | |
4031 | #define XSTORM_ETH_CONN_AG_CTX_CF14_MASK 0x3 | |
4032 | #define XSTORM_ETH_CONN_AG_CTX_CF14_SHIFT 4 | |
4033 | #define XSTORM_ETH_CONN_AG_CTX_CF15_MASK 0x3 | |
4034 | #define XSTORM_ETH_CONN_AG_CTX_CF15_SHIFT 6 | |
fe56b9e6 | 4035 | u8 flags6; |
351a4ded YM |
4036 | #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3 |
4037 | #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0 | |
4038 | #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3 | |
4039 | #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2 | |
4040 | #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_MASK 0x3 | |
4041 | #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_SHIFT 4 | |
4042 | #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_MASK 0x3 | |
4043 | #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_SHIFT 6 | |
fe56b9e6 | 4044 | u8 flags7; |
351a4ded YM |
4045 | #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 |
4046 | #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 | |
4047 | #define XSTORM_ETH_CONN_AG_CTX_RESERVED10_MASK 0x3 | |
4048 | #define XSTORM_ETH_CONN_AG_CTX_RESERVED10_SHIFT 2 | |
4049 | #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_MASK 0x3 | |
4050 | #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_SHIFT 4 | |
4051 | #define XSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1 | |
4052 | #define XSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 6 | |
4053 | #define XSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1 | |
4054 | #define XSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 7 | |
fe56b9e6 | 4055 | u8 flags8; |
351a4ded YM |
4056 | #define XSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 |
4057 | #define XSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 0 | |
4058 | #define XSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1 | |
4059 | #define XSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 1 | |
4060 | #define XSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1 | |
4061 | #define XSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 2 | |
4062 | #define XSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1 | |
4063 | #define XSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 3 | |
4064 | #define XSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1 | |
4065 | #define XSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 4 | |
4066 | #define XSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1 | |
4067 | #define XSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 5 | |
4068 | #define XSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1 | |
4069 | #define XSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 6 | |
4070 | #define XSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1 | |
4071 | #define XSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 7 | |
fe56b9e6 | 4072 | u8 flags9; |
351a4ded YM |
4073 | #define XSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1 |
4074 | #define XSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 0 | |
4075 | #define XSTORM_ETH_CONN_AG_CTX_CF11EN_MASK 0x1 | |
4076 | #define XSTORM_ETH_CONN_AG_CTX_CF11EN_SHIFT 1 | |
4077 | #define XSTORM_ETH_CONN_AG_CTX_CF12EN_MASK 0x1 | |
4078 | #define XSTORM_ETH_CONN_AG_CTX_CF12EN_SHIFT 2 | |
4079 | #define XSTORM_ETH_CONN_AG_CTX_CF13EN_MASK 0x1 | |
4080 | #define XSTORM_ETH_CONN_AG_CTX_CF13EN_SHIFT 3 | |
4081 | #define XSTORM_ETH_CONN_AG_CTX_CF14EN_MASK 0x1 | |
4082 | #define XSTORM_ETH_CONN_AG_CTX_CF14EN_SHIFT 4 | |
4083 | #define XSTORM_ETH_CONN_AG_CTX_CF15EN_MASK 0x1 | |
4084 | #define XSTORM_ETH_CONN_AG_CTX_CF15EN_SHIFT 5 | |
4085 | #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1 | |
4086 | #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6 | |
4087 | #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1 | |
4088 | #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7 | |
fe56b9e6 | 4089 | u8 flags10; |
351a4ded YM |
4090 | #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 |
4091 | #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_SHIFT 0 | |
4092 | #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1 | |
4093 | #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1 | |
4094 | #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 | |
4095 | #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 | |
4096 | #define XSTORM_ETH_CONN_AG_CTX_RESERVED11_MASK 0x1 | |
4097 | #define XSTORM_ETH_CONN_AG_CTX_RESERVED11_SHIFT 3 | |
4098 | #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 | |
4099 | #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 | |
4100 | #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1 | |
fe56b9e6 | 4101 | #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5 |
351a4ded YM |
4102 | #define XSTORM_ETH_CONN_AG_CTX_RESERVED12_MASK 0x1 |
4103 | #define XSTORM_ETH_CONN_AG_CTX_RESERVED12_SHIFT 6 | |
4104 | #define XSTORM_ETH_CONN_AG_CTX_RESERVED13_MASK 0x1 | |
4105 | #define XSTORM_ETH_CONN_AG_CTX_RESERVED13_SHIFT 7 | |
fe56b9e6 | 4106 | u8 flags11; |
351a4ded YM |
4107 | #define XSTORM_ETH_CONN_AG_CTX_RESERVED14_MASK 0x1 |
4108 | #define XSTORM_ETH_CONN_AG_CTX_RESERVED14_SHIFT 0 | |
4109 | #define XSTORM_ETH_CONN_AG_CTX_RESERVED15_MASK 0x1 | |
4110 | #define XSTORM_ETH_CONN_AG_CTX_RESERVED15_SHIFT 1 | |
4111 | #define XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1 | |
4112 | #define XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2 | |
4113 | #define XSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1 | |
4114 | #define XSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 3 | |
4115 | #define XSTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1 | |
4116 | #define XSTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 4 | |
4117 | #define XSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1 | |
4118 | #define XSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 5 | |
4119 | #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 | |
4120 | #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 | |
4121 | #define XSTORM_ETH_CONN_AG_CTX_RULE9EN_MASK 0x1 | |
4122 | #define XSTORM_ETH_CONN_AG_CTX_RULE9EN_SHIFT 7 | |
fe56b9e6 | 4123 | u8 flags12; |
351a4ded YM |
4124 | #define XSTORM_ETH_CONN_AG_CTX_RULE10EN_MASK 0x1 |
4125 | #define XSTORM_ETH_CONN_AG_CTX_RULE10EN_SHIFT 0 | |
4126 | #define XSTORM_ETH_CONN_AG_CTX_RULE11EN_MASK 0x1 | |
4127 | #define XSTORM_ETH_CONN_AG_CTX_RULE11EN_SHIFT 1 | |
4128 | #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 | |
4129 | #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 | |
4130 | #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 | |
4131 | #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 | |
4132 | #define XSTORM_ETH_CONN_AG_CTX_RULE14EN_MASK 0x1 | |
4133 | #define XSTORM_ETH_CONN_AG_CTX_RULE14EN_SHIFT 4 | |
4134 | #define XSTORM_ETH_CONN_AG_CTX_RULE15EN_MASK 0x1 | |
4135 | #define XSTORM_ETH_CONN_AG_CTX_RULE15EN_SHIFT 5 | |
4136 | #define XSTORM_ETH_CONN_AG_CTX_RULE16EN_MASK 0x1 | |
4137 | #define XSTORM_ETH_CONN_AG_CTX_RULE16EN_SHIFT 6 | |
4138 | #define XSTORM_ETH_CONN_AG_CTX_RULE17EN_MASK 0x1 | |
4139 | #define XSTORM_ETH_CONN_AG_CTX_RULE17EN_SHIFT 7 | |
fe56b9e6 | 4140 | u8 flags13; |
351a4ded YM |
4141 | #define XSTORM_ETH_CONN_AG_CTX_RULE18EN_MASK 0x1 |
4142 | #define XSTORM_ETH_CONN_AG_CTX_RULE18EN_SHIFT 0 | |
4143 | #define XSTORM_ETH_CONN_AG_CTX_RULE19EN_MASK 0x1 | |
4144 | #define XSTORM_ETH_CONN_AG_CTX_RULE19EN_SHIFT 1 | |
4145 | #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 | |
4146 | #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 | |
4147 | #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 | |
4148 | #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 | |
4149 | #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 | |
4150 | #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 | |
4151 | #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 | |
4152 | #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 | |
4153 | #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 | |
4154 | #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 | |
4155 | #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 | |
4156 | #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 | |
fe56b9e6 | 4157 | u8 flags14; |
351a4ded YM |
4158 | #define XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1 |
4159 | #define XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0 | |
4160 | #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1 | |
4161 | #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1 | |
4162 | #define XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1 | |
4163 | #define XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2 | |
4164 | #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1 | |
4165 | #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3 | |
4166 | #define XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1 | |
4167 | #define XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4 | |
4168 | #define XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 | |
4169 | #define XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5 | |
4170 | #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_MASK 0x3 | |
4171 | #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_SHIFT 6 | |
4172 | u8 edpm_event_id; | |
4173 | __le16 physical_q0; | |
4174 | __le16 quota; | |
4175 | __le16 edpm_num_bds; | |
4176 | __le16 tx_bd_cons; | |
4177 | __le16 tx_bd_prod; | |
4178 | __le16 tx_class; | |
4179 | __le16 conn_dpi; | |
4180 | u8 byte3; | |
4181 | u8 byte4; | |
4182 | u8 byte5; | |
4183 | u8 byte6; | |
4184 | __le32 reg0; | |
4185 | __le32 reg1; | |
4186 | __le32 reg2; | |
4187 | __le32 reg3; | |
4188 | __le32 reg4; | |
4189 | __le32 reg5; | |
4190 | __le32 reg6; | |
4191 | __le16 word7; | |
4192 | __le16 word8; | |
4193 | __le16 word9; | |
4194 | __le16 word10; | |
4195 | __le32 reg7; | |
4196 | __le32 reg8; | |
4197 | __le32 reg9; | |
4198 | u8 byte7; | |
4199 | u8 byte8; | |
4200 | u8 byte9; | |
4201 | u8 byte10; | |
4202 | u8 byte11; | |
4203 | u8 byte12; | |
4204 | u8 byte13; | |
4205 | u8 byte14; | |
4206 | u8 byte15; | |
4207 | u8 byte16; | |
4208 | __le16 word11; | |
4209 | __le32 reg10; | |
4210 | __le32 reg11; | |
4211 | __le32 reg12; | |
4212 | __le32 reg13; | |
4213 | __le32 reg14; | |
4214 | __le32 reg15; | |
4215 | __le32 reg16; | |
4216 | __le32 reg17; | |
4217 | __le32 reg18; | |
4218 | __le32 reg19; | |
4219 | __le16 word12; | |
4220 | __le16 word13; | |
4221 | __le16 word14; | |
4222 | __le16 word15; | |
fc48b7a6 YM |
4223 | }; |
4224 | ||
4225 | /* The eth storm context for the Ystorm */ | |
4226 | struct ystorm_eth_conn_st_ctx { | |
4227 | __le32 reserved[8]; | |
4228 | }; | |
4229 | ||
4230 | struct ystorm_eth_conn_ag_ctx { | |
351a4ded YM |
4231 | u8 byte0; |
4232 | u8 state; | |
4233 | u8 flags0; | |
4234 | #define YSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1 | |
4235 | #define YSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0 | |
4236 | #define YSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 | |
4237 | #define YSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1 | |
4238 | #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3 | |
4239 | #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 2 | |
4240 | #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_MASK 0x3 | |
4241 | #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_SHIFT 4 | |
4242 | #define YSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 | |
4243 | #define YSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6 | |
fc48b7a6 | 4244 | u8 flags1; |
351a4ded YM |
4245 | #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1 |
4246 | #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 0 | |
4247 | #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_MASK 0x1 | |
4248 | #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_SHIFT 1 | |
4249 | #define YSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 | |
4250 | #define YSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2 | |
4251 | #define YSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 | |
4252 | #define YSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3 | |
4253 | #define YSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 | |
4254 | #define YSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4 | |
4255 | #define YSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 | |
4256 | #define YSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5 | |
4257 | #define YSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 | |
4258 | #define YSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6 | |
4259 | #define YSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 | |
4260 | #define YSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7 | |
4261 | u8 tx_q0_int_coallecing_timeset; | |
4262 | u8 byte3; | |
4263 | __le16 word0; | |
4264 | __le32 terminate_spqe; | |
4265 | __le32 reg1; | |
4266 | __le16 tx_bd_cons_upd; | |
4267 | __le16 word2; | |
4268 | __le16 word3; | |
4269 | __le16 word4; | |
4270 | __le32 reg2; | |
4271 | __le32 reg3; | |
fc48b7a6 YM |
4272 | }; |
4273 | ||
4274 | struct tstorm_eth_conn_ag_ctx { | |
351a4ded YM |
4275 | u8 byte0; |
4276 | u8 byte1; | |
4277 | u8 flags0; | |
4278 | #define TSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1 | |
4279 | #define TSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0 | |
4280 | #define TSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 | |
4281 | #define TSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1 | |
4282 | #define TSTORM_ETH_CONN_AG_CTX_BIT2_MASK 0x1 | |
4283 | #define TSTORM_ETH_CONN_AG_CTX_BIT2_SHIFT 2 | |
4284 | #define TSTORM_ETH_CONN_AG_CTX_BIT3_MASK 0x1 | |
4285 | #define TSTORM_ETH_CONN_AG_CTX_BIT3_SHIFT 3 | |
4286 | #define TSTORM_ETH_CONN_AG_CTX_BIT4_MASK 0x1 | |
4287 | #define TSTORM_ETH_CONN_AG_CTX_BIT4_SHIFT 4 | |
4288 | #define TSTORM_ETH_CONN_AG_CTX_BIT5_MASK 0x1 | |
4289 | #define TSTORM_ETH_CONN_AG_CTX_BIT5_SHIFT 5 | |
4290 | #define TSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 | |
4291 | #define TSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 6 | |
fc48b7a6 | 4292 | u8 flags1; |
351a4ded YM |
4293 | #define TSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 |
4294 | #define TSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 0 | |
4295 | #define TSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 | |
4296 | #define TSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 2 | |
4297 | #define TSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3 | |
4298 | #define TSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 4 | |
4299 | #define TSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3 | |
4300 | #define TSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 6 | |
fc48b7a6 | 4301 | u8 flags2; |
351a4ded YM |
4302 | #define TSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3 |
4303 | #define TSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 0 | |
4304 | #define TSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3 | |
4305 | #define TSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 2 | |
4306 | #define TSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3 | |
4307 | #define TSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 4 | |
4308 | #define TSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3 | |
4309 | #define TSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 6 | |
fc48b7a6 | 4310 | u8 flags3; |
351a4ded YM |
4311 | #define TSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3 |
4312 | #define TSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 0 | |
4313 | #define TSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3 | |
4314 | #define TSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 2 | |
4315 | #define TSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1 | |
4316 | #define TSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 4 | |
4317 | #define TSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1 | |
4318 | #define TSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 5 | |
4319 | #define TSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 | |
4320 | #define TSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 6 | |
4321 | #define TSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1 | |
4322 | #define TSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 7 | |
fc48b7a6 | 4323 | u8 flags4; |
351a4ded YM |
4324 | #define TSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1 |
4325 | #define TSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 0 | |
4326 | #define TSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1 | |
4327 | #define TSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 1 | |
4328 | #define TSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1 | |
4329 | #define TSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 2 | |
4330 | #define TSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1 | |
4331 | #define TSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 3 | |
4332 | #define TSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1 | |
4333 | #define TSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 4 | |
4334 | #define TSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1 | |
4335 | #define TSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 5 | |
4336 | #define TSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1 | |
4337 | #define TSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 6 | |
4338 | #define TSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 | |
4339 | #define TSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7 | |
fc48b7a6 | 4340 | u8 flags5; |
351a4ded YM |
4341 | #define TSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 |
4342 | #define TSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0 | |
4343 | #define TSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 | |
4344 | #define TSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1 | |
4345 | #define TSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 | |
4346 | #define TSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2 | |
4347 | #define TSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 | |
4348 | #define TSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3 | |
4349 | #define TSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1 | |
4350 | #define TSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4 | |
4351 | #define TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_MASK 0x1 | |
4352 | #define TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_SHIFT 5 | |
4353 | #define TSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1 | |
4354 | #define TSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6 | |
4355 | #define TSTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1 | |
4356 | #define TSTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7 | |
4357 | __le32 reg0; | |
4358 | __le32 reg1; | |
4359 | __le32 reg2; | |
4360 | __le32 reg3; | |
4361 | __le32 reg4; | |
4362 | __le32 reg5; | |
4363 | __le32 reg6; | |
4364 | __le32 reg7; | |
4365 | __le32 reg8; | |
4366 | u8 byte2; | |
4367 | u8 byte3; | |
4368 | __le16 rx_bd_cons; | |
4369 | u8 byte4; | |
4370 | u8 byte5; | |
4371 | __le16 rx_bd_prod; | |
4372 | __le16 word2; | |
4373 | __le16 word3; | |
4374 | __le32 reg9; | |
4375 | __le32 reg10; | |
fe56b9e6 YM |
4376 | }; |
4377 | ||
fc48b7a6 | 4378 | struct ustorm_eth_conn_ag_ctx { |
351a4ded YM |
4379 | u8 byte0; |
4380 | u8 byte1; | |
4381 | u8 flags0; | |
4382 | #define USTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1 | |
4383 | #define USTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0 | |
4384 | #define USTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 | |
4385 | #define USTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1 | |
4386 | #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_MASK 0x3 | |
4387 | #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_SHIFT 2 | |
4388 | #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_MASK 0x3 | |
4389 | #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_SHIFT 4 | |
4390 | #define USTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 | |
4391 | #define USTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6 | |
fc48b7a6 | 4392 | u8 flags1; |
351a4ded YM |
4393 | #define USTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3 |
4394 | #define USTORM_ETH_CONN_AG_CTX_CF3_SHIFT 0 | |
4395 | #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_MASK 0x3 | |
4396 | #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_SHIFT 2 | |
4397 | #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_MASK 0x3 | |
4398 | #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_SHIFT 4 | |
4399 | #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3 | |
4400 | #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 6 | |
fc48b7a6 | 4401 | u8 flags2; |
351a4ded YM |
4402 | #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_MASK 0x1 |
4403 | #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_SHIFT 0 | |
4404 | #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_MASK 0x1 | |
4405 | #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_SHIFT 1 | |
4406 | #define USTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 | |
4407 | #define USTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2 | |
4408 | #define USTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1 | |
4409 | #define USTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 3 | |
4410 | #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_MASK 0x1 | |
4411 | #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_SHIFT 4 | |
4412 | #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_MASK 0x1 | |
4413 | #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_SHIFT 5 | |
4414 | #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1 | |
4415 | #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 6 | |
4416 | #define USTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 | |
4417 | #define USTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7 | |
fc48b7a6 | 4418 | u8 flags3; |
351a4ded YM |
4419 | #define USTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 |
4420 | #define USTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0 | |
4421 | #define USTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 | |
4422 | #define USTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1 | |
4423 | #define USTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 | |
4424 | #define USTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2 | |
4425 | #define USTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 | |
4426 | #define USTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3 | |
4427 | #define USTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1 | |
4428 | #define USTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4 | |
4429 | #define USTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1 | |
4430 | #define USTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 5 | |
4431 | #define USTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1 | |
4432 | #define USTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6 | |
4433 | #define USTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1 | |
4434 | #define USTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7 | |
4435 | u8 byte2; | |
4436 | u8 byte3; | |
4437 | __le16 word0; | |
4438 | __le16 tx_bd_cons; | |
4439 | __le32 reg0; | |
4440 | __le32 reg1; | |
4441 | __le32 reg2; | |
4442 | __le32 tx_int_coallecing_timeset; | |
4443 | __le16 tx_drv_bd_cons; | |
4444 | __le16 rx_drv_cqe_cons; | |
fe56b9e6 YM |
4445 | }; |
4446 | ||
4447 | /* The eth storm context for the Ustorm */ | |
4448 | struct ustorm_eth_conn_st_ctx { | |
4449 | __le32 reserved[40]; | |
4450 | }; | |
4451 | ||
fc48b7a6 YM |
4452 | /* The eth storm context for the Mstorm */ |
4453 | struct mstorm_eth_conn_st_ctx { | |
4454 | __le32 reserved[8]; | |
4455 | }; | |
4456 | ||
fe56b9e6 YM |
4457 | /* eth connection context */ |
4458 | struct eth_conn_context { | |
351a4ded YM |
4459 | struct tstorm_eth_conn_st_ctx tstorm_st_context; |
4460 | struct regpair tstorm_st_padding[2]; | |
4461 | struct pstorm_eth_conn_st_ctx pstorm_st_context; | |
4462 | struct xstorm_eth_conn_st_ctx xstorm_st_context; | |
4463 | struct xstorm_eth_conn_ag_ctx xstorm_ag_context; | |
4464 | struct ystorm_eth_conn_st_ctx ystorm_st_context; | |
4465 | struct ystorm_eth_conn_ag_ctx ystorm_ag_context; | |
4466 | struct tstorm_eth_conn_ag_ctx tstorm_ag_context; | |
4467 | struct ustorm_eth_conn_ag_ctx ustorm_ag_context; | |
4468 | struct ustorm_eth_conn_st_ctx ustorm_st_context; | |
4469 | struct mstorm_eth_conn_st_ctx mstorm_st_context; | |
fe56b9e6 YM |
4470 | }; |
4471 | ||
05fafbfb YM |
4472 | enum eth_error_code { |
4473 | ETH_OK = 0x00, | |
4474 | ETH_FILTERS_MAC_ADD_FAIL_FULL, | |
4475 | ETH_FILTERS_MAC_ADD_FAIL_FULL_MTT2, | |
4476 | ETH_FILTERS_MAC_ADD_FAIL_DUP_MTT2, | |
4477 | ETH_FILTERS_MAC_ADD_FAIL_DUP_STT2, | |
4478 | ETH_FILTERS_MAC_DEL_FAIL_NOF, | |
4479 | ETH_FILTERS_MAC_DEL_FAIL_NOF_MTT2, | |
4480 | ETH_FILTERS_MAC_DEL_FAIL_NOF_STT2, | |
4481 | ETH_FILTERS_MAC_ADD_FAIL_ZERO_MAC, | |
4482 | ETH_FILTERS_VLAN_ADD_FAIL_FULL, | |
4483 | ETH_FILTERS_VLAN_ADD_FAIL_DUP, | |
4484 | ETH_FILTERS_VLAN_DEL_FAIL_NOF, | |
4485 | ETH_FILTERS_VLAN_DEL_FAIL_NOF_TT1, | |
4486 | ETH_FILTERS_PAIR_ADD_FAIL_DUP, | |
4487 | ETH_FILTERS_PAIR_ADD_FAIL_FULL, | |
4488 | ETH_FILTERS_PAIR_ADD_FAIL_FULL_MAC, | |
4489 | ETH_FILTERS_PAIR_DEL_FAIL_NOF, | |
4490 | ETH_FILTERS_PAIR_DEL_FAIL_NOF_TT1, | |
4491 | ETH_FILTERS_PAIR_ADD_FAIL_ZERO_MAC, | |
4492 | ETH_FILTERS_VNI_ADD_FAIL_FULL, | |
4493 | ETH_FILTERS_VNI_ADD_FAIL_DUP, | |
4494 | MAX_ETH_ERROR_CODE | |
4495 | }; | |
4496 | ||
351a4ded YM |
4497 | enum eth_event_opcode { |
4498 | ETH_EVENT_UNUSED, | |
4499 | ETH_EVENT_VPORT_START, | |
4500 | ETH_EVENT_VPORT_UPDATE, | |
4501 | ETH_EVENT_VPORT_STOP, | |
4502 | ETH_EVENT_TX_QUEUE_START, | |
4503 | ETH_EVENT_TX_QUEUE_STOP, | |
4504 | ETH_EVENT_RX_QUEUE_START, | |
4505 | ETH_EVENT_RX_QUEUE_UPDATE, | |
4506 | ETH_EVENT_RX_QUEUE_STOP, | |
4507 | ETH_EVENT_FILTERS_UPDATE, | |
4508 | ETH_EVENT_RESERVED, | |
4509 | ETH_EVENT_RESERVED2, | |
4510 | ETH_EVENT_RESERVED3, | |
4511 | ETH_EVENT_RX_ADD_UDP_FILTER, | |
4512 | ETH_EVENT_RX_DELETE_UDP_FILTER, | |
4513 | ETH_EVENT_RESERVED4, | |
4514 | ETH_EVENT_RESERVED5, | |
4515 | MAX_ETH_EVENT_OPCODE | |
4516 | }; | |
4517 | ||
4518 | /* Classify rule types in E2/E3 */ | |
cee4d264 | 4519 | enum eth_filter_action { |
351a4ded | 4520 | ETH_FILTER_ACTION_UNUSED, |
cee4d264 MC |
4521 | ETH_FILTER_ACTION_REMOVE, |
4522 | ETH_FILTER_ACTION_ADD, | |
fc48b7a6 | 4523 | ETH_FILTER_ACTION_REMOVE_ALL, |
cee4d264 MC |
4524 | MAX_ETH_FILTER_ACTION |
4525 | }; | |
4526 | ||
351a4ded | 4527 | /* Command for adding/removing a classification rule $$KEEP_ENDIANNESS$$ */ |
cee4d264 | 4528 | struct eth_filter_cmd { |
351a4ded YM |
4529 | u8 type; |
4530 | u8 vport_id; | |
4531 | u8 action; | |
4532 | u8 reserved0; | |
4533 | __le32 vni; | |
4534 | __le16 mac_lsb; | |
4535 | __le16 mac_mid; | |
4536 | __le16 mac_msb; | |
4537 | __le16 vlan_id; | |
cee4d264 MC |
4538 | }; |
4539 | ||
351a4ded | 4540 | /* $$KEEP_ENDIANNESS$$ */ |
cee4d264 | 4541 | struct eth_filter_cmd_header { |
351a4ded YM |
4542 | u8 rx; |
4543 | u8 tx; | |
4544 | u8 cmd_cnt; | |
4545 | u8 assert_on_error; | |
4546 | u8 reserved1[4]; | |
cee4d264 MC |
4547 | }; |
4548 | ||
351a4ded | 4549 | /* Ethernet filter types: mac/vlan/pair */ |
cee4d264 | 4550 | enum eth_filter_type { |
351a4ded | 4551 | ETH_FILTER_TYPE_UNUSED, |
cee4d264 MC |
4552 | ETH_FILTER_TYPE_MAC, |
4553 | ETH_FILTER_TYPE_VLAN, | |
4554 | ETH_FILTER_TYPE_PAIR, | |
4555 | ETH_FILTER_TYPE_INNER_MAC, | |
4556 | ETH_FILTER_TYPE_INNER_VLAN, | |
4557 | ETH_FILTER_TYPE_INNER_PAIR, | |
4558 | ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR, | |
4559 | ETH_FILTER_TYPE_MAC_VNI_PAIR, | |
4560 | ETH_FILTER_TYPE_VNI, | |
4561 | MAX_ETH_FILTER_TYPE | |
4562 | }; | |
4563 | ||
05fafbfb YM |
4564 | enum eth_ipv4_frag_type { |
4565 | ETH_IPV4_NOT_FRAG, | |
4566 | ETH_IPV4_FIRST_FRAG, | |
4567 | ETH_IPV4_NON_FIRST_FRAG, | |
4568 | MAX_ETH_IPV4_FRAG_TYPE | |
4569 | }; | |
4570 | ||
cee4d264 MC |
4571 | enum eth_ramrod_cmd_id { |
4572 | ETH_RAMROD_UNUSED, | |
351a4ded YM |
4573 | ETH_RAMROD_VPORT_START, |
4574 | ETH_RAMROD_VPORT_UPDATE, | |
4575 | ETH_RAMROD_VPORT_STOP, | |
4576 | ETH_RAMROD_RX_QUEUE_START, | |
4577 | ETH_RAMROD_RX_QUEUE_STOP, | |
4578 | ETH_RAMROD_TX_QUEUE_START, | |
4579 | ETH_RAMROD_TX_QUEUE_STOP, | |
4580 | ETH_RAMROD_FILTERS_UPDATE, | |
4581 | ETH_RAMROD_RX_QUEUE_UPDATE, | |
4582 | ETH_RAMROD_RX_CREATE_OPENFLOW_ACTION, | |
4583 | ETH_RAMROD_RX_ADD_OPENFLOW_FILTER, | |
4584 | ETH_RAMROD_RX_DELETE_OPENFLOW_FILTER, | |
4585 | ETH_RAMROD_RX_ADD_UDP_FILTER, | |
4586 | ETH_RAMROD_RX_DELETE_UDP_FILTER, | |
4587 | ETH_RAMROD_RX_CREATE_GFT_ACTION, | |
4588 | ETH_RAMROD_GFT_UPDATE_FILTER, | |
cee4d264 MC |
4589 | MAX_ETH_RAMROD_CMD_ID |
4590 | }; | |
4591 | ||
351a4ded YM |
4592 | /* return code from eth sp ramrods */ |
4593 | struct eth_return_code { | |
4594 | u8 value; | |
4595 | #define ETH_RETURN_CODE_ERR_CODE_MASK 0x1F | |
4596 | #define ETH_RETURN_CODE_ERR_CODE_SHIFT 0 | |
4597 | #define ETH_RETURN_CODE_RESERVED_MASK 0x3 | |
4598 | #define ETH_RETURN_CODE_RESERVED_SHIFT 5 | |
4599 | #define ETH_RETURN_CODE_RX_TX_MASK 0x1 | |
4600 | #define ETH_RETURN_CODE_RX_TX_SHIFT 7 | |
4601 | }; | |
4602 | ||
4603 | /* What to do in case an error occurs */ | |
fc48b7a6 | 4604 | enum eth_tx_err { |
351a4ded | 4605 | ETH_TX_ERR_DROP, |
fc48b7a6 YM |
4606 | ETH_TX_ERR_ASSERT_MALICIOUS, |
4607 | MAX_ETH_TX_ERR | |
4608 | }; | |
4609 | ||
351a4ded | 4610 | /* Array of the different error type behaviors */ |
fc48b7a6 YM |
4611 | struct eth_tx_err_vals { |
4612 | __le16 values; | |
351a4ded YM |
4613 | #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_MASK 0x1 |
4614 | #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_SHIFT 0 | |
4615 | #define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_MASK 0x1 | |
4616 | #define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_SHIFT 1 | |
4617 | #define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_MASK 0x1 | |
4618 | #define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_SHIFT 2 | |
4619 | #define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_MASK 0x1 | |
4620 | #define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_SHIFT 3 | |
4621 | #define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_MASK 0x1 | |
4622 | #define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_SHIFT 4 | |
4623 | #define ETH_TX_ERR_VALS_MTU_VIOLATION_MASK 0x1 | |
4624 | #define ETH_TX_ERR_VALS_MTU_VIOLATION_SHIFT 5 | |
4625 | #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_MASK 0x1 | |
4626 | #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_SHIFT 6 | |
4627 | #define ETH_TX_ERR_VALS_RESERVED_MASK 0x1FF | |
4628 | #define ETH_TX_ERR_VALS_RESERVED_SHIFT 7 | |
4629 | }; | |
4630 | ||
4631 | /* vport rss configuration data */ | |
cee4d264 MC |
4632 | struct eth_vport_rss_config { |
4633 | __le16 capabilities; | |
351a4ded YM |
4634 | #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_MASK 0x1 |
4635 | #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_SHIFT 0 | |
4636 | #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_MASK 0x1 | |
4637 | #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_SHIFT 1 | |
4638 | #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_MASK 0x1 | |
4639 | #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_SHIFT 2 | |
4640 | #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_MASK 0x1 | |
4641 | #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_SHIFT 3 | |
4642 | #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_MASK 0x1 | |
4643 | #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_SHIFT 4 | |
4644 | #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_MASK 0x1 | |
4645 | #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_SHIFT 5 | |
4646 | #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_MASK 0x1 | |
4647 | #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_SHIFT 6 | |
4648 | #define ETH_VPORT_RSS_CONFIG_RESERVED0_MASK 0x1FF | |
4649 | #define ETH_VPORT_RSS_CONFIG_RESERVED0_SHIFT 7 | |
4650 | u8 rss_id; | |
4651 | u8 rss_mode; | |
4652 | u8 update_rss_key; | |
4653 | u8 update_rss_ind_table; | |
4654 | u8 update_rss_capabilities; | |
4655 | u8 tbl_size; | |
4656 | __le32 reserved2[2]; | |
4657 | __le16 indirection_table[ETH_RSS_IND_TABLE_ENTRIES_NUM]; | |
4658 | ||
4659 | __le32 rss_key[ETH_RSS_KEY_SIZE_REGS]; | |
4660 | __le32 reserved3[2]; | |
4661 | }; | |
4662 | ||
4663 | /* eth vport RSS mode */ | |
cee4d264 MC |
4664 | enum eth_vport_rss_mode { |
4665 | ETH_VPORT_RSS_MODE_DISABLED, | |
4666 | ETH_VPORT_RSS_MODE_REGULAR, | |
4667 | MAX_ETH_VPORT_RSS_MODE | |
4668 | }; | |
4669 | ||
351a4ded | 4670 | /* Command for setting classification flags for a vport $$KEEP_ENDIANNESS$$ */ |
cee4d264 MC |
4671 | struct eth_vport_rx_mode { |
4672 | __le16 state; | |
351a4ded YM |
4673 | #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_MASK 0x1 |
4674 | #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_SHIFT 0 | |
4675 | #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_MASK 0x1 | |
4676 | #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_SHIFT 1 | |
4677 | #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_MASK 0x1 | |
4678 | #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_SHIFT 2 | |
4679 | #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_MASK 0x1 | |
4680 | #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_SHIFT 3 | |
4681 | #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_MASK 0x1 | |
4682 | #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_SHIFT 4 | |
4683 | #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_MASK 0x1 | |
4684 | #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_SHIFT 5 | |
4685 | #define ETH_VPORT_RX_MODE_RESERVED1_MASK 0x3FF | |
4686 | #define ETH_VPORT_RX_MODE_RESERVED1_SHIFT 6 | |
cee4d264 MC |
4687 | __le16 reserved2[3]; |
4688 | }; | |
4689 | ||
351a4ded | 4690 | /* Command for setting tpa parameters */ |
cee4d264 | 4691 | struct eth_vport_tpa_param { |
351a4ded YM |
4692 | u8 tpa_ipv4_en_flg; |
4693 | u8 tpa_ipv6_en_flg; | |
4694 | u8 tpa_ipv4_tunn_en_flg; | |
4695 | u8 tpa_ipv6_tunn_en_flg; | |
4696 | u8 tpa_pkt_split_flg; | |
4697 | u8 tpa_hdr_data_split_flg; | |
4698 | u8 tpa_gro_consistent_flg; | |
4699 | ||
4700 | u8 tpa_max_aggs_num; | |
4701 | ||
4702 | __le16 tpa_max_size; | |
4703 | __le16 tpa_min_size_to_start; | |
4704 | ||
4705 | __le16 tpa_min_size_to_cont; | |
4706 | u8 max_buff_num; | |
4707 | u8 reserved; | |
cee4d264 MC |
4708 | }; |
4709 | ||
351a4ded | 4710 | /* Command for setting classification flags for a vport $$KEEP_ENDIANNESS$$ */ |
cee4d264 MC |
4711 | struct eth_vport_tx_mode { |
4712 | __le16 state; | |
351a4ded YM |
4713 | #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_MASK 0x1 |
4714 | #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_SHIFT 0 | |
4715 | #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_MASK 0x1 | |
4716 | #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_SHIFT 1 | |
4717 | #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_MASK 0x1 | |
4718 | #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_SHIFT 2 | |
4719 | #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_MASK 0x1 | |
4720 | #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_SHIFT 3 | |
4721 | #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_MASK 0x1 | |
4722 | #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_SHIFT 4 | |
4723 | #define ETH_VPORT_TX_MODE_RESERVED1_MASK 0x7FF | |
4724 | #define ETH_VPORT_TX_MODE_RESERVED1_SHIFT 5 | |
cee4d264 MC |
4725 | __le16 reserved2[3]; |
4726 | }; | |
4727 | ||
351a4ded | 4728 | /* Ramrod data for rx queue start ramrod */ |
cee4d264 | 4729 | struct rx_queue_start_ramrod_data { |
351a4ded YM |
4730 | __le16 rx_queue_id; |
4731 | __le16 num_of_pbl_pages; | |
4732 | __le16 bd_max_bytes; | |
4733 | __le16 sb_id; | |
4734 | u8 sb_index; | |
4735 | u8 vport_id; | |
4736 | u8 default_rss_queue_flg; | |
4737 | u8 complete_cqe_flg; | |
4738 | u8 complete_event_flg; | |
4739 | u8 stats_counter_id; | |
4740 | u8 pin_context; | |
4741 | u8 pxp_tph_valid_bd; | |
4742 | u8 pxp_tph_valid_pkt; | |
4743 | u8 pxp_st_hint; | |
4744 | ||
4745 | __le16 pxp_st_index; | |
4746 | u8 pmd_mode; | |
4747 | ||
4748 | u8 notify_en; | |
4749 | u8 toggle_val; | |
4750 | ||
4751 | u8 vf_rx_prod_index; | |
05fafbfb YM |
4752 | u8 vf_rx_prod_use_zone_a; |
4753 | u8 reserved[5]; | |
351a4ded YM |
4754 | __le16 reserved1; |
4755 | struct regpair cqe_pbl_addr; | |
4756 | struct regpair bd_base; | |
4757 | struct regpair reserved2; | |
cee4d264 MC |
4758 | }; |
4759 | ||
351a4ded | 4760 | /* Ramrod data for rx queue start ramrod */ |
cee4d264 | 4761 | struct rx_queue_stop_ramrod_data { |
351a4ded YM |
4762 | __le16 rx_queue_id; |
4763 | u8 complete_cqe_flg; | |
4764 | u8 complete_event_flg; | |
4765 | u8 vport_id; | |
4766 | u8 reserved[3]; | |
cee4d264 MC |
4767 | }; |
4768 | ||
351a4ded | 4769 | /* Ramrod data for rx queue update ramrod */ |
cee4d264 | 4770 | struct rx_queue_update_ramrod_data { |
351a4ded YM |
4771 | __le16 rx_queue_id; |
4772 | u8 complete_cqe_flg; | |
4773 | u8 complete_event_flg; | |
4774 | u8 vport_id; | |
4775 | u8 reserved[4]; | |
4776 | u8 reserved1; | |
4777 | u8 reserved2; | |
4778 | u8 reserved3; | |
4779 | __le16 reserved4; | |
4780 | __le16 reserved5; | |
fc48b7a6 | 4781 | struct regpair reserved6; |
cee4d264 MC |
4782 | }; |
4783 | ||
351a4ded YM |
4784 | /* Ramrod data for rx Add UDP Filter */ |
4785 | struct rx_udp_filter_data { | |
4786 | __le16 action_icid; | |
4787 | __le16 vlan_id; | |
4788 | u8 ip_type; | |
4789 | u8 tenant_id_exists; | |
4790 | __le16 reserved1; | |
4791 | __le32 ip_dst_addr[4]; | |
4792 | __le32 ip_src_addr[4]; | |
4793 | __le16 udp_dst_port; | |
4794 | __le16 udp_src_port; | |
4795 | __le32 tenant_id; | |
cee4d264 MC |
4796 | }; |
4797 | ||
351a4ded YM |
4798 | /* Ramrod data for rx queue start ramrod */ |
4799 | struct tx_queue_start_ramrod_data { | |
4800 | __le16 sb_id; | |
4801 | u8 sb_index; | |
4802 | u8 vport_id; | |
4803 | u8 reserved0; | |
4804 | u8 stats_counter_id; | |
4805 | __le16 qm_pq_id; | |
4806 | u8 flags; | |
4807 | #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_MASK 0x1 | |
4808 | #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_SHIFT 0 | |
4809 | #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_MASK 0x1 | |
4810 | #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_SHIFT 1 | |
4811 | #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_TX_DEST_MASK 0x1 | |
4812 | #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_TX_DEST_SHIFT 2 | |
4813 | #define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_MASK 0x1 | |
4814 | #define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_SHIFT 3 | |
4815 | #define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_MASK 0x1 | |
4816 | #define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_SHIFT 4 | |
4817 | #define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_MASK 0x1 | |
4818 | #define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_SHIFT 5 | |
4819 | #define TX_QUEUE_START_RAMROD_DATA_RESERVED1_MASK 0x3 | |
4820 | #define TX_QUEUE_START_RAMROD_DATA_RESERVED1_SHIFT 6 | |
4821 | u8 pxp_st_hint; | |
4822 | u8 pxp_tph_valid_bd; | |
4823 | u8 pxp_tph_valid_pkt; | |
4824 | __le16 pxp_st_index; | |
4825 | __le16 comp_agg_size; | |
4826 | __le16 queue_zone_id; | |
05fafbfb | 4827 | __le16 reserved2; |
351a4ded YM |
4828 | __le16 pbl_size; |
4829 | __le16 tx_queue_id; | |
05fafbfb YM |
4830 | __le16 same_as_last_id; |
4831 | __le16 reserved[3]; | |
351a4ded YM |
4832 | struct regpair pbl_base_addr; |
4833 | struct regpair bd_cons_address; | |
4834 | }; | |
4835 | ||
4836 | /* Ramrod data for tx queue stop ramrod */ | |
cee4d264 MC |
4837 | struct tx_queue_stop_ramrod_data { |
4838 | __le16 reserved[4]; | |
4839 | }; | |
4840 | ||
351a4ded | 4841 | /* Ramrod data for vport update ramrod */ |
cee4d264 | 4842 | struct vport_filter_update_ramrod_data { |
351a4ded YM |
4843 | struct eth_filter_cmd_header filter_cmd_hdr; |
4844 | struct eth_filter_cmd filter_cmds[ETH_FILTER_RULES_COUNT]; | |
cee4d264 MC |
4845 | }; |
4846 | ||
351a4ded | 4847 | /* Ramrod data for vport start ramrod */ |
cee4d264 | 4848 | struct vport_start_ramrod_data { |
351a4ded YM |
4849 | u8 vport_id; |
4850 | u8 sw_fid; | |
4851 | __le16 mtu; | |
4852 | u8 drop_ttl0_en; | |
4853 | u8 inner_vlan_removal_en; | |
4854 | struct eth_vport_rx_mode rx_mode; | |
4855 | struct eth_vport_tx_mode tx_mode; | |
4856 | struct eth_vport_tpa_param tpa_param; | |
4857 | __le16 default_vlan; | |
4858 | u8 tx_switching_en; | |
4859 | u8 anti_spoofing_en; | |
4860 | ||
4861 | u8 default_vlan_en; | |
4862 | ||
4863 | u8 handle_ptp_pkts; | |
4864 | u8 silent_vlan_removal_en; | |
4865 | u8 untagged; | |
4866 | struct eth_tx_err_vals tx_err_behav; | |
4867 | ||
4868 | u8 zero_placement_offset; | |
4869 | u8 ctl_frame_mac_check_en; | |
4870 | u8 ctl_frame_ethtype_check_en; | |
4871 | u8 reserved[5]; | |
4872 | }; | |
4873 | ||
4874 | /* Ramrod data for vport stop ramrod */ | |
cee4d264 | 4875 | struct vport_stop_ramrod_data { |
351a4ded YM |
4876 | u8 vport_id; |
4877 | u8 reserved[7]; | |
cee4d264 MC |
4878 | }; |
4879 | ||
351a4ded | 4880 | /* Ramrod data for vport update ramrod */ |
cee4d264 | 4881 | struct vport_update_ramrod_data_cmn { |
351a4ded YM |
4882 | u8 vport_id; |
4883 | u8 update_rx_active_flg; | |
4884 | u8 rx_active_flg; | |
4885 | u8 update_tx_active_flg; | |
4886 | u8 tx_active_flg; | |
4887 | u8 update_rx_mode_flg; | |
4888 | u8 update_tx_mode_flg; | |
4889 | u8 update_approx_mcast_flg; | |
4890 | ||
4891 | u8 update_rss_flg; | |
4892 | u8 update_inner_vlan_removal_en_flg; | |
4893 | ||
4894 | u8 inner_vlan_removal_en; | |
4895 | u8 update_tpa_param_flg; | |
4896 | u8 update_tpa_en_flg; | |
4897 | u8 update_tx_switching_en_flg; | |
4898 | ||
4899 | u8 tx_switching_en; | |
4900 | u8 update_anti_spoofing_en_flg; | |
4901 | ||
4902 | u8 anti_spoofing_en; | |
4903 | u8 update_handle_ptp_pkts; | |
4904 | ||
4905 | u8 handle_ptp_pkts; | |
4906 | u8 update_default_vlan_en_flg; | |
4907 | ||
4908 | u8 default_vlan_en; | |
4909 | ||
4910 | u8 update_default_vlan_flg; | |
4911 | ||
4912 | __le16 default_vlan; | |
4913 | u8 update_accept_any_vlan_flg; | |
4914 | ||
4915 | u8 accept_any_vlan; | |
4916 | u8 silent_vlan_removal_en; | |
4917 | u8 update_mtu_flg; | |
4918 | ||
4919 | __le16 mtu; | |
4920 | u8 reserved[2]; | |
cee4d264 MC |
4921 | }; |
4922 | ||
4923 | struct vport_update_ramrod_mcast { | |
4924 | __le32 bins[ETH_MULTICAST_MAC_BINS_IN_REGS]; | |
4925 | }; | |
4926 | ||
351a4ded | 4927 | /* Ramrod data for vport update ramrod */ |
cee4d264 | 4928 | struct vport_update_ramrod_data { |
351a4ded YM |
4929 | struct vport_update_ramrod_data_cmn common; |
4930 | ||
4931 | struct eth_vport_rx_mode rx_mode; | |
4932 | struct eth_vport_tx_mode tx_mode; | |
4933 | struct eth_vport_tpa_param tpa_param; | |
4934 | struct vport_update_ramrod_mcast approx_mcast; | |
4935 | struct eth_vport_rss_config rss_config; | |
cee4d264 MC |
4936 | }; |
4937 | ||
7a9b6b8f YM |
4938 | struct mstorm_rdma_task_st_ctx { |
4939 | struct regpair temp[4]; | |
4940 | }; | |
4941 | ||
4942 | struct rdma_close_func_ramrod_data { | |
4943 | u8 cnq_start_offset; | |
4944 | u8 num_cnqs; | |
4945 | u8 vf_id; | |
4946 | u8 vf_valid; | |
4947 | u8 reserved[4]; | |
4948 | }; | |
4949 | ||
4950 | struct rdma_cnq_params { | |
4951 | __le16 sb_num; | |
4952 | u8 sb_index; | |
4953 | u8 num_pbl_pages; | |
4954 | __le32 reserved; | |
4955 | struct regpair pbl_base_addr; | |
4956 | __le16 queue_zone_num; | |
4957 | u8 reserved1[6]; | |
4958 | }; | |
4959 | ||
4960 | struct rdma_create_cq_ramrod_data { | |
4961 | struct regpair cq_handle; | |
4962 | struct regpair pbl_addr; | |
4963 | __le32 max_cqes; | |
4964 | __le16 pbl_num_pages; | |
4965 | __le16 dpi; | |
4966 | u8 is_two_level_pbl; | |
4967 | u8 cnq_id; | |
4968 | u8 pbl_log_page_size; | |
4969 | u8 toggle_bit; | |
4970 | __le16 int_timeout; | |
4971 | __le16 reserved1; | |
4972 | }; | |
4973 | ||
4974 | struct rdma_deregister_tid_ramrod_data { | |
4975 | __le32 itid; | |
4976 | __le32 reserved; | |
4977 | }; | |
4978 | ||
4979 | struct rdma_destroy_cq_output_params { | |
4980 | __le16 cnq_num; | |
4981 | __le16 reserved0; | |
4982 | __le32 reserved1; | |
4983 | }; | |
4984 | ||
4985 | struct rdma_destroy_cq_ramrod_data { | |
4986 | struct regpair output_params_addr; | |
4987 | }; | |
4988 | ||
4989 | enum rdma_event_opcode { | |
4990 | RDMA_EVENT_UNUSED, | |
4991 | RDMA_EVENT_FUNC_INIT, | |
4992 | RDMA_EVENT_FUNC_CLOSE, | |
4993 | RDMA_EVENT_REGISTER_MR, | |
4994 | RDMA_EVENT_DEREGISTER_MR, | |
4995 | RDMA_EVENT_CREATE_CQ, | |
4996 | RDMA_EVENT_RESIZE_CQ, | |
4997 | RDMA_EVENT_DESTROY_CQ, | |
4998 | RDMA_EVENT_CREATE_SRQ, | |
4999 | RDMA_EVENT_MODIFY_SRQ, | |
5000 | RDMA_EVENT_DESTROY_SRQ, | |
5001 | MAX_RDMA_EVENT_OPCODE | |
5002 | }; | |
5003 | ||
5004 | enum rdma_fw_return_code { | |
5005 | RDMA_RETURN_OK = 0, | |
5006 | RDMA_RETURN_REGISTER_MR_BAD_STATE_ERR, | |
5007 | RDMA_RETURN_DEREGISTER_MR_BAD_STATE_ERR, | |
5008 | RDMA_RETURN_RESIZE_CQ_ERR, | |
5009 | RDMA_RETURN_NIG_DRAIN_REQ, | |
5010 | MAX_RDMA_FW_RETURN_CODE | |
5011 | }; | |
5012 | ||
5013 | struct rdma_init_func_hdr { | |
5014 | u8 cnq_start_offset; | |
5015 | u8 num_cnqs; | |
5016 | u8 cq_ring_mode; | |
5017 | u8 cnp_vlan_priority; | |
5018 | __le32 cnp_send_timeout; | |
5019 | u8 cnp_dscp; | |
5020 | u8 vf_id; | |
5021 | u8 vf_valid; | |
5022 | u8 reserved[5]; | |
5023 | }; | |
5024 | ||
5025 | struct rdma_init_func_ramrod_data { | |
5026 | struct rdma_init_func_hdr params_header; | |
5027 | struct rdma_cnq_params cnq_params[NUM_OF_GLOBAL_QUEUES]; | |
5028 | }; | |
5029 | ||
5030 | enum rdma_ramrod_cmd_id { | |
5031 | RDMA_RAMROD_UNUSED, | |
5032 | RDMA_RAMROD_FUNC_INIT, | |
5033 | RDMA_RAMROD_FUNC_CLOSE, | |
5034 | RDMA_RAMROD_REGISTER_MR, | |
5035 | RDMA_RAMROD_DEREGISTER_MR, | |
5036 | RDMA_RAMROD_CREATE_CQ, | |
5037 | RDMA_RAMROD_RESIZE_CQ, | |
5038 | RDMA_RAMROD_DESTROY_CQ, | |
5039 | RDMA_RAMROD_CREATE_SRQ, | |
5040 | RDMA_RAMROD_MODIFY_SRQ, | |
5041 | RDMA_RAMROD_DESTROY_SRQ, | |
5042 | MAX_RDMA_RAMROD_CMD_ID | |
5043 | }; | |
5044 | ||
5045 | struct rdma_register_tid_ramrod_data { | |
5046 | __le32 flags; | |
5047 | #define RDMA_REGISTER_TID_RAMROD_DATA_MAX_ID_MASK 0x3FFFF | |
5048 | #define RDMA_REGISTER_TID_RAMROD_DATA_MAX_ID_SHIFT 0 | |
5049 | #define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_MASK 0x1F | |
5050 | #define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_SHIFT 18 | |
5051 | #define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_MASK 0x1 | |
5052 | #define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_SHIFT 23 | |
5053 | #define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_MASK 0x1 | |
5054 | #define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_SHIFT 24 | |
5055 | #define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_MASK 0x1 | |
5056 | #define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_SHIFT 25 | |
5057 | #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_MASK 0x1 | |
5058 | #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_SHIFT 26 | |
5059 | #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_MASK 0x1 | |
5060 | #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_SHIFT 27 | |
5061 | #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_MASK 0x1 | |
5062 | #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_SHIFT 28 | |
5063 | #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_MASK 0x1 | |
5064 | #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_SHIFT 29 | |
5065 | #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_MASK 0x1 | |
5066 | #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_SHIFT 30 | |
5067 | #define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_MASK 0x1 | |
5068 | #define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_SHIFT 31 | |
5069 | u8 flags1; | |
5070 | #define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_MASK 0x1F | |
5071 | #define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_SHIFT 0 | |
5072 | #define RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_MASK 0x7 | |
5073 | #define RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_SHIFT 5 | |
5074 | u8 flags2; | |
5075 | #define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_MASK 0x1 | |
5076 | #define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_SHIFT 0 | |
5077 | #define RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_MASK 0x1 | |
5078 | #define RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_SHIFT 1 | |
5079 | #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_MASK 0x3F | |
5080 | #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_SHIFT 2 | |
5081 | u8 key; | |
5082 | u8 length_hi; | |
5083 | u8 vf_id; | |
5084 | u8 vf_valid; | |
5085 | __le16 pd; | |
5086 | __le32 length_lo; | |
5087 | __le32 itid; | |
5088 | __le32 reserved2; | |
5089 | struct regpair va; | |
5090 | struct regpair pbl_base; | |
5091 | struct regpair dif_error_addr; | |
5092 | struct regpair dif_runt_addr; | |
5093 | __le32 reserved3[2]; | |
5094 | }; | |
5095 | ||
5096 | struct rdma_resize_cq_output_params { | |
5097 | __le32 old_cq_cons; | |
5098 | __le32 old_cq_prod; | |
5099 | }; | |
5100 | ||
5101 | struct rdma_resize_cq_ramrod_data { | |
5102 | u8 flags; | |
5103 | #define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_MASK 0x1 | |
5104 | #define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_SHIFT 0 | |
5105 | #define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_MASK 0x1 | |
5106 | #define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_SHIFT 1 | |
5107 | #define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_MASK 0x3F | |
5108 | #define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_SHIFT 2 | |
5109 | u8 pbl_log_page_size; | |
5110 | __le16 pbl_num_pages; | |
5111 | __le32 max_cqes; | |
5112 | struct regpair pbl_addr; | |
5113 | struct regpair output_params_addr; | |
5114 | }; | |
5115 | ||
5116 | struct rdma_srq_context { | |
5117 | struct regpair temp[8]; | |
5118 | }; | |
5119 | ||
5120 | struct rdma_srq_create_ramrod_data { | |
5121 | struct regpair pbl_base_addr; | |
5122 | __le16 pages_in_srq_pbl; | |
5123 | __le16 pd_id; | |
5124 | struct rdma_srq_id srq_id; | |
5125 | __le16 page_size; | |
5126 | __le16 reserved1; | |
5127 | __le32 reserved2; | |
5128 | struct regpair producers_addr; | |
5129 | }; | |
5130 | ||
5131 | struct rdma_srq_destroy_ramrod_data { | |
5132 | struct rdma_srq_id srq_id; | |
5133 | __le32 reserved; | |
5134 | }; | |
5135 | ||
5136 | struct rdma_srq_modify_ramrod_data { | |
5137 | struct rdma_srq_id srq_id; | |
5138 | __le32 wqe_limit; | |
5139 | }; | |
5140 | ||
5141 | struct ystorm_rdma_task_st_ctx { | |
5142 | struct regpair temp[4]; | |
5143 | }; | |
5144 | ||
5145 | struct ystorm_rdma_task_ag_ctx { | |
5146 | u8 reserved; | |
5147 | u8 byte1; | |
5148 | __le16 msem_ctx_upd_seq; | |
5149 | u8 flags0; | |
5150 | #define YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF | |
5151 | #define YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 | |
5152 | #define YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 | |
5153 | #define YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 | |
5154 | #define YSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1 | |
5155 | #define YSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5 | |
5156 | #define YSTORM_RDMA_TASK_AG_CTX_VALID_MASK 0x1 | |
5157 | #define YSTORM_RDMA_TASK_AG_CTX_VALID_SHIFT 6 | |
5158 | #define YSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1 | |
5159 | #define YSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7 | |
5160 | u8 flags1; | |
5161 | #define YSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3 | |
5162 | #define YSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0 | |
5163 | #define YSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3 | |
5164 | #define YSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 2 | |
5165 | #define YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_MASK 0x3 | |
5166 | #define YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_SHIFT 4 | |
5167 | #define YSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1 | |
5168 | #define YSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 6 | |
5169 | #define YSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1 | |
5170 | #define YSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 7 | |
5171 | u8 flags2; | |
5172 | #define YSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1 | |
5173 | #define YSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT 0 | |
5174 | #define YSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 | |
5175 | #define YSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 1 | |
5176 | #define YSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 | |
5177 | #define YSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 2 | |
5178 | #define YSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 | |
5179 | #define YSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 3 | |
5180 | #define YSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1 | |
5181 | #define YSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 4 | |
5182 | #define YSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 | |
5183 | #define YSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 5 | |
5184 | #define YSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1 | |
5185 | #define YSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 6 | |
5186 | #define YSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1 | |
5187 | #define YSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 7 | |
5188 | u8 key; | |
5189 | __le32 mw_cnt; | |
5190 | u8 ref_cnt_seq; | |
5191 | u8 ctx_upd_seq; | |
5192 | __le16 dif_flags; | |
5193 | __le16 tx_ref_count; | |
5194 | __le16 last_used_ltid; | |
5195 | __le16 parent_mr_lo; | |
5196 | __le16 parent_mr_hi; | |
5197 | __le32 fbo_lo; | |
5198 | __le32 fbo_hi; | |
5199 | }; | |
5200 | ||
5201 | struct mstorm_rdma_task_ag_ctx { | |
5202 | u8 reserved; | |
5203 | u8 byte1; | |
5204 | __le16 icid; | |
5205 | u8 flags0; | |
5206 | #define MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF | |
5207 | #define MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 | |
5208 | #define MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 | |
5209 | #define MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 | |
5210 | #define MSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1 | |
5211 | #define MSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5 | |
5212 | #define MSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1 | |
5213 | #define MSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT 6 | |
5214 | #define MSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1 | |
5215 | #define MSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7 | |
5216 | u8 flags1; | |
5217 | #define MSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3 | |
5218 | #define MSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0 | |
5219 | #define MSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3 | |
5220 | #define MSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 2 | |
5221 | #define MSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3 | |
5222 | #define MSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT 4 | |
5223 | #define MSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1 | |
5224 | #define MSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 6 | |
5225 | #define MSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1 | |
5226 | #define MSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 7 | |
5227 | u8 flags2; | |
5228 | #define MSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1 | |
5229 | #define MSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT 0 | |
5230 | #define MSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 | |
5231 | #define MSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 1 | |
5232 | #define MSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 | |
5233 | #define MSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 2 | |
5234 | #define MSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 | |
5235 | #define MSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 3 | |
5236 | #define MSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1 | |
5237 | #define MSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 4 | |
5238 | #define MSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 | |
5239 | #define MSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 5 | |
5240 | #define MSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1 | |
5241 | #define MSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 6 | |
5242 | #define MSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1 | |
5243 | #define MSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 7 | |
5244 | u8 key; | |
5245 | __le32 mw_cnt; | |
5246 | u8 ref_cnt_seq; | |
5247 | u8 ctx_upd_seq; | |
5248 | __le16 dif_flags; | |
5249 | __le16 tx_ref_count; | |
5250 | __le16 last_used_ltid; | |
5251 | __le16 parent_mr_lo; | |
5252 | __le16 parent_mr_hi; | |
5253 | __le32 fbo_lo; | |
5254 | __le32 fbo_hi; | |
5255 | }; | |
5256 | ||
5257 | struct ustorm_rdma_task_st_ctx { | |
5258 | struct regpair temp[2]; | |
5259 | }; | |
5260 | ||
5261 | struct ustorm_rdma_task_ag_ctx { | |
5262 | u8 reserved; | |
5263 | u8 byte1; | |
5264 | __le16 icid; | |
5265 | u8 flags0; | |
5266 | #define USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF | |
5267 | #define USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 | |
5268 | #define USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 | |
5269 | #define USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 | |
5270 | #define USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_MASK 0x1 | |
5271 | #define USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_SHIFT 5 | |
5272 | #define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_MASK 0x3 | |
5273 | #define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_SHIFT 6 | |
5274 | u8 flags1; | |
5275 | #define USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_MASK 0x3 | |
5276 | #define USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_SHIFT 0 | |
5277 | #define USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_MASK 0x3 | |
5278 | #define USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_SHIFT 2 | |
5279 | #define USTORM_RDMA_TASK_AG_CTX_CF3_MASK 0x3 | |
5280 | #define USTORM_RDMA_TASK_AG_CTX_CF3_SHIFT 4 | |
5281 | #define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3 | |
5282 | #define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6 | |
5283 | u8 flags2; | |
5284 | #define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_MASK 0x1 | |
5285 | #define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_SHIFT 0 | |
5286 | #define USTORM_RDMA_TASK_AG_CTX_RESERVED2_MASK 0x1 | |
5287 | #define USTORM_RDMA_TASK_AG_CTX_RESERVED2_SHIFT 1 | |
5288 | #define USTORM_RDMA_TASK_AG_CTX_RESERVED3_MASK 0x1 | |
5289 | #define USTORM_RDMA_TASK_AG_CTX_RESERVED3_SHIFT 2 | |
5290 | #define USTORM_RDMA_TASK_AG_CTX_CF3EN_MASK 0x1 | |
5291 | #define USTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT 3 | |
5292 | #define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1 | |
5293 | #define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4 | |
5294 | #define USTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 | |
5295 | #define USTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 5 | |
5296 | #define USTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 | |
5297 | #define USTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 6 | |
5298 | #define USTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 | |
5299 | #define USTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 7 | |
5300 | u8 flags3; | |
5301 | #define USTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1 | |
5302 | #define USTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 0 | |
5303 | #define USTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 | |
5304 | #define USTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 1 | |
5305 | #define USTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1 | |
5306 | #define USTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 2 | |
5307 | #define USTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1 | |
5308 | #define USTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 3 | |
5309 | #define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF | |
5310 | #define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4 | |
5311 | __le32 dif_err_intervals; | |
5312 | __le32 dif_error_1st_interval; | |
5313 | __le32 reg2; | |
5314 | __le32 dif_runt_value; | |
5315 | __le32 reg4; | |
5316 | __le32 reg5; | |
5317 | }; | |
5318 | ||
5319 | struct rdma_task_context { | |
5320 | struct ystorm_rdma_task_st_ctx ystorm_st_context; | |
5321 | struct ystorm_rdma_task_ag_ctx ystorm_ag_context; | |
5322 | struct tdif_task_context tdif_context; | |
5323 | struct mstorm_rdma_task_ag_ctx mstorm_ag_context; | |
5324 | struct mstorm_rdma_task_st_ctx mstorm_st_context; | |
5325 | struct rdif_task_context rdif_context; | |
5326 | struct ustorm_rdma_task_st_ctx ustorm_st_context; | |
5327 | struct regpair ustorm_st_padding[2]; | |
5328 | struct ustorm_rdma_task_ag_ctx ustorm_ag_context; | |
5329 | }; | |
5330 | ||
5331 | enum rdma_tid_type { | |
5332 | RDMA_TID_REGISTERED_MR, | |
5333 | RDMA_TID_FMR, | |
5334 | RDMA_TID_MW_TYPE1, | |
5335 | RDMA_TID_MW_TYPE2A, | |
5336 | MAX_RDMA_TID_TYPE | |
5337 | }; | |
5338 | ||
5339 | struct mstorm_rdma_conn_ag_ctx { | |
5340 | u8 byte0; | |
5341 | u8 byte1; | |
5342 | u8 flags0; | |
5343 | #define MSTORM_RDMA_CONN_AG_CTX_BIT0_MASK 0x1 | |
5344 | #define MSTORM_RDMA_CONN_AG_CTX_BIT0_SHIFT 0 | |
5345 | #define MSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 | |
5346 | #define MSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1 | |
5347 | #define MSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3 | |
5348 | #define MSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 2 | |
5349 | #define MSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 | |
5350 | #define MSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4 | |
5351 | #define MSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 | |
5352 | #define MSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6 | |
5353 | u8 flags1; | |
5354 | #define MSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1 | |
5355 | #define MSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 0 | |
5356 | #define MSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 | |
5357 | #define MSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1 | |
5358 | #define MSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 | |
5359 | #define MSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2 | |
5360 | #define MSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1 | |
5361 | #define MSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 3 | |
5362 | #define MSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1 | |
5363 | #define MSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 4 | |
5364 | #define MSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 | |
5365 | #define MSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 5 | |
5366 | #define MSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 | |
5367 | #define MSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 6 | |
5368 | #define MSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 | |
5369 | #define MSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 7 | |
5370 | __le16 word0; | |
5371 | __le16 word1; | |
5372 | __le32 reg0; | |
5373 | __le32 reg1; | |
5374 | }; | |
5375 | ||
5376 | struct tstorm_rdma_conn_ag_ctx { | |
5377 | u8 reserved0; | |
5378 | u8 byte1; | |
5379 | u8 flags0; | |
5380 | #define TSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 | |
5381 | #define TSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 | |
5382 | #define TSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 | |
5383 | #define TSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1 | |
5384 | #define TSTORM_RDMA_CONN_AG_CTX_BIT2_MASK 0x1 | |
5385 | #define TSTORM_RDMA_CONN_AG_CTX_BIT2_SHIFT 2 | |
5386 | #define TSTORM_RDMA_CONN_AG_CTX_BIT3_MASK 0x1 | |
5387 | #define TSTORM_RDMA_CONN_AG_CTX_BIT3_SHIFT 3 | |
5388 | #define TSTORM_RDMA_CONN_AG_CTX_BIT4_MASK 0x1 | |
5389 | #define TSTORM_RDMA_CONN_AG_CTX_BIT4_SHIFT 4 | |
5390 | #define TSTORM_RDMA_CONN_AG_CTX_BIT5_MASK 0x1 | |
5391 | #define TSTORM_RDMA_CONN_AG_CTX_BIT5_SHIFT 5 | |
5392 | #define TSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3 | |
5393 | #define TSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 6 | |
5394 | u8 flags1; | |
5395 | #define TSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 | |
5396 | #define TSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 0 | |
5397 | #define TSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 | |
5398 | #define TSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 2 | |
5399 | #define TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3 | |
5400 | #define TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4 | |
5401 | #define TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 | |
5402 | #define TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 | |
5403 | u8 flags2; | |
5404 | #define TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3 | |
5405 | #define TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0 | |
5406 | #define TSTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3 | |
5407 | #define TSTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 2 | |
5408 | #define TSTORM_RDMA_CONN_AG_CTX_CF7_MASK 0x3 | |
5409 | #define TSTORM_RDMA_CONN_AG_CTX_CF7_SHIFT 4 | |
5410 | #define TSTORM_RDMA_CONN_AG_CTX_CF8_MASK 0x3 | |
5411 | #define TSTORM_RDMA_CONN_AG_CTX_CF8_SHIFT 6 | |
5412 | u8 flags3; | |
5413 | #define TSTORM_RDMA_CONN_AG_CTX_CF9_MASK 0x3 | |
5414 | #define TSTORM_RDMA_CONN_AG_CTX_CF9_SHIFT 0 | |
5415 | #define TSTORM_RDMA_CONN_AG_CTX_CF10_MASK 0x3 | |
5416 | #define TSTORM_RDMA_CONN_AG_CTX_CF10_SHIFT 2 | |
5417 | #define TSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1 | |
5418 | #define TSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 4 | |
5419 | #define TSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 | |
5420 | #define TSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 5 | |
5421 | #define TSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 | |
5422 | #define TSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 6 | |
5423 | #define TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1 | |
5424 | #define TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7 | |
5425 | u8 flags4; | |
5426 | #define TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 | |
5427 | #define TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0 | |
5428 | #define TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1 | |
5429 | #define TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1 | |
5430 | #define TSTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1 | |
5431 | #define TSTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 2 | |
5432 | #define TSTORM_RDMA_CONN_AG_CTX_CF7EN_MASK 0x1 | |
5433 | #define TSTORM_RDMA_CONN_AG_CTX_CF7EN_SHIFT 3 | |
5434 | #define TSTORM_RDMA_CONN_AG_CTX_CF8EN_MASK 0x1 | |
5435 | #define TSTORM_RDMA_CONN_AG_CTX_CF8EN_SHIFT 4 | |
5436 | #define TSTORM_RDMA_CONN_AG_CTX_CF9EN_MASK 0x1 | |
5437 | #define TSTORM_RDMA_CONN_AG_CTX_CF9EN_SHIFT 5 | |
5438 | #define TSTORM_RDMA_CONN_AG_CTX_CF10EN_MASK 0x1 | |
5439 | #define TSTORM_RDMA_CONN_AG_CTX_CF10EN_SHIFT 6 | |
5440 | #define TSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1 | |
5441 | #define TSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 7 | |
5442 | u8 flags5; | |
5443 | #define TSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1 | |
5444 | #define TSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 0 | |
5445 | #define TSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 | |
5446 | #define TSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 1 | |
5447 | #define TSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 | |
5448 | #define TSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 2 | |
5449 | #define TSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 | |
5450 | #define TSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 3 | |
5451 | #define TSTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1 | |
5452 | #define TSTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 4 | |
5453 | #define TSTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1 | |
5454 | #define TSTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 5 | |
5455 | #define TSTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1 | |
5456 | #define TSTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 6 | |
5457 | #define TSTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK 0x1 | |
5458 | #define TSTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT 7 | |
5459 | __le32 reg0; | |
5460 | __le32 reg1; | |
5461 | __le32 reg2; | |
5462 | __le32 reg3; | |
5463 | __le32 reg4; | |
5464 | __le32 reg5; | |
5465 | __le32 reg6; | |
5466 | __le32 reg7; | |
5467 | __le32 reg8; | |
5468 | u8 byte2; | |
5469 | u8 byte3; | |
5470 | __le16 word0; | |
5471 | u8 byte4; | |
5472 | u8 byte5; | |
5473 | __le16 word1; | |
5474 | __le16 word2; | |
5475 | __le16 word3; | |
5476 | __le32 reg9; | |
5477 | __le32 reg10; | |
5478 | }; | |
5479 | ||
5480 | struct tstorm_rdma_task_ag_ctx { | |
5481 | u8 byte0; | |
5482 | u8 byte1; | |
5483 | __le16 word0; | |
5484 | u8 flags0; | |
5485 | #define TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_MASK 0xF | |
5486 | #define TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_SHIFT 0 | |
5487 | #define TSTORM_RDMA_TASK_AG_CTX_BIT0_MASK 0x1 | |
5488 | #define TSTORM_RDMA_TASK_AG_CTX_BIT0_SHIFT 4 | |
5489 | #define TSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1 | |
5490 | #define TSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5 | |
5491 | #define TSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1 | |
5492 | #define TSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT 6 | |
5493 | #define TSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1 | |
5494 | #define TSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7 | |
5495 | u8 flags1; | |
5496 | #define TSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1 | |
5497 | #define TSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT 0 | |
5498 | #define TSTORM_RDMA_TASK_AG_CTX_BIT5_MASK 0x1 | |
5499 | #define TSTORM_RDMA_TASK_AG_CTX_BIT5_SHIFT 1 | |
5500 | #define TSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3 | |
5501 | #define TSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 2 | |
5502 | #define TSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3 | |
5503 | #define TSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 4 | |
5504 | #define TSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3 | |
5505 | #define TSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT 6 | |
5506 | u8 flags2; | |
5507 | #define TSTORM_RDMA_TASK_AG_CTX_CF3_MASK 0x3 | |
5508 | #define TSTORM_RDMA_TASK_AG_CTX_CF3_SHIFT 0 | |
5509 | #define TSTORM_RDMA_TASK_AG_CTX_CF4_MASK 0x3 | |
5510 | #define TSTORM_RDMA_TASK_AG_CTX_CF4_SHIFT 2 | |
5511 | #define TSTORM_RDMA_TASK_AG_CTX_CF5_MASK 0x3 | |
5512 | #define TSTORM_RDMA_TASK_AG_CTX_CF5_SHIFT 4 | |
5513 | #define TSTORM_RDMA_TASK_AG_CTX_CF6_MASK 0x3 | |
5514 | #define TSTORM_RDMA_TASK_AG_CTX_CF6_SHIFT 6 | |
5515 | u8 flags3; | |
5516 | #define TSTORM_RDMA_TASK_AG_CTX_CF7_MASK 0x3 | |
5517 | #define TSTORM_RDMA_TASK_AG_CTX_CF7_SHIFT 0 | |
5518 | #define TSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1 | |
5519 | #define TSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 2 | |
5520 | #define TSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1 | |
5521 | #define TSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 3 | |
5522 | #define TSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1 | |
5523 | #define TSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT 4 | |
5524 | #define TSTORM_RDMA_TASK_AG_CTX_CF3EN_MASK 0x1 | |
5525 | #define TSTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT 5 | |
5526 | #define TSTORM_RDMA_TASK_AG_CTX_CF4EN_MASK 0x1 | |
5527 | #define TSTORM_RDMA_TASK_AG_CTX_CF4EN_SHIFT 6 | |
5528 | #define TSTORM_RDMA_TASK_AG_CTX_CF5EN_MASK 0x1 | |
5529 | #define TSTORM_RDMA_TASK_AG_CTX_CF5EN_SHIFT 7 | |
5530 | u8 flags4; | |
5531 | #define TSTORM_RDMA_TASK_AG_CTX_CF6EN_MASK 0x1 | |
5532 | #define TSTORM_RDMA_TASK_AG_CTX_CF6EN_SHIFT 0 | |
5533 | #define TSTORM_RDMA_TASK_AG_CTX_CF7EN_MASK 0x1 | |
5534 | #define TSTORM_RDMA_TASK_AG_CTX_CF7EN_SHIFT 1 | |
5535 | #define TSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 | |
5536 | #define TSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 2 | |
5537 | #define TSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 | |
5538 | #define TSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 3 | |
5539 | #define TSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 | |
5540 | #define TSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 4 | |
5541 | #define TSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1 | |
5542 | #define TSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 5 | |
5543 | #define TSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 | |
5544 | #define TSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 6 | |
5545 | #define TSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1 | |
5546 | #define TSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 7 | |
5547 | u8 byte2; | |
5548 | __le16 word1; | |
5549 | __le32 reg0; | |
5550 | u8 byte3; | |
5551 | u8 byte4; | |
5552 | __le16 word2; | |
5553 | __le16 word3; | |
5554 | __le16 word4; | |
5555 | __le32 reg1; | |
5556 | __le32 reg2; | |
5557 | }; | |
5558 | ||
5559 | struct ustorm_rdma_conn_ag_ctx { | |
5560 | u8 reserved; | |
5561 | u8 byte1; | |
5562 | u8 flags0; | |
5563 | #define USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 | |
5564 | #define USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 | |
5565 | #define USTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 | |
5566 | #define USTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1 | |
5567 | #define USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 | |
5568 | #define USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 2 | |
5569 | #define USTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 | |
5570 | #define USTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4 | |
5571 | #define USTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 | |
5572 | #define USTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6 | |
5573 | u8 flags1; | |
5574 | #define USTORM_RDMA_CONN_AG_CTX_CF3_MASK 0x3 | |
5575 | #define USTORM_RDMA_CONN_AG_CTX_CF3_SHIFT 0 | |
5576 | #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_MASK 0x3 | |
5577 | #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT 2 | |
5578 | #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_MASK 0x3 | |
5579 | #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_SHIFT 4 | |
5580 | #define USTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3 | |
5581 | #define USTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 6 | |
5582 | u8 flags2; | |
5583 | #define USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 | |
5584 | #define USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0 | |
5585 | #define USTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 | |
5586 | #define USTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1 | |
5587 | #define USTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 | |
5588 | #define USTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2 | |
5589 | #define USTORM_RDMA_CONN_AG_CTX_CF3EN_MASK 0x1 | |
5590 | #define USTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT 3 | |
5591 | #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK 0x1 | |
5592 | #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT 4 | |
5593 | #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_MASK 0x1 | |
5594 | #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT 5 | |
5595 | #define USTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1 | |
5596 | #define USTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 6 | |
5597 | #define USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_MASK 0x1 | |
5598 | #define USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_SHIFT 7 | |
5599 | u8 flags3; | |
5600 | #define USTORM_RDMA_CONN_AG_CTX_CQ_EN_MASK 0x1 | |
5601 | #define USTORM_RDMA_CONN_AG_CTX_CQ_EN_SHIFT 0 | |
5602 | #define USTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 | |
5603 | #define USTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 1 | |
5604 | #define USTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 | |
5605 | #define USTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 2 | |
5606 | #define USTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 | |
5607 | #define USTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 3 | |
5608 | #define USTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1 | |
5609 | #define USTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 4 | |
5610 | #define USTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1 | |
5611 | #define USTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 5 | |
5612 | #define USTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1 | |
5613 | #define USTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 6 | |
5614 | #define USTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK 0x1 | |
5615 | #define USTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT 7 | |
5616 | u8 byte2; | |
5617 | u8 byte3; | |
5618 | __le16 conn_dpi; | |
5619 | __le16 word1; | |
5620 | __le32 cq_cons; | |
5621 | __le32 cq_se_prod; | |
5622 | __le32 cq_prod; | |
5623 | __le32 reg3; | |
5624 | __le16 int_timeout; | |
5625 | __le16 word3; | |
5626 | }; | |
5627 | ||
5628 | struct xstorm_roce_conn_ag_ctx_dq_ext_ld_part { | |
5629 | u8 reserved0; | |
5630 | u8 state; | |
5631 | u8 flags0; | |
5632 | #define XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1 | |
5633 | #define XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0 | |
5634 | #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_MASK 0x1 | |
5635 | #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_SHIFT 1 | |
5636 | #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_MASK 0x1 | |
5637 | #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_SHIFT 2 | |
5638 | #define XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1 | |
5639 | #define XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT 3 | |
5640 | #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_MASK 0x1 | |
5641 | #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_SHIFT 4 | |
5642 | #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_MASK 0x1 | |
5643 | #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_SHIFT 5 | |
5644 | #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_MASK 0x1 | |
5645 | #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_SHIFT 6 | |
5646 | #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_MASK 0x1 | |
5647 | #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_SHIFT 7 | |
5648 | u8 flags1; | |
5649 | #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_MASK 0x1 | |
5650 | #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_SHIFT 0 | |
5651 | #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_MASK 0x1 | |
5652 | #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_SHIFT 1 | |
5653 | #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_MASK 0x1 | |
5654 | #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_SHIFT 2 | |
5655 | #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_MASK 0x1 | |
5656 | #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_SHIFT 3 | |
5657 | #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_MASK 0x1 | |
5658 | #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_SHIFT 4 | |
5659 | #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT13_MASK 0x1 | |
5660 | #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT13_SHIFT 5 | |
5661 | #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_MASK 0x1 | |
5662 | #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_SHIFT 6 | |
5663 | #define XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_MASK 0x1 | |
5664 | #define XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_SHIFT 7 | |
5665 | u8 flags2; | |
5666 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF0_MASK 0x3 | |
5667 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF0_SHIFT 0 | |
5668 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF1_MASK 0x3 | |
5669 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF1_SHIFT 2 | |
5670 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF2_MASK 0x3 | |
5671 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF2_SHIFT 4 | |
5672 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF3_MASK 0x3 | |
5673 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF3_SHIFT 6 | |
5674 | u8 flags3; | |
5675 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF4_MASK 0x3 | |
5676 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF4_SHIFT 0 | |
5677 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF5_MASK 0x3 | |
5678 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF5_SHIFT 2 | |
5679 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF6_MASK 0x3 | |
5680 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF6_SHIFT 4 | |
5681 | #define XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_MASK 0x3 | |
5682 | #define XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_SHIFT 6 | |
5683 | u8 flags4; | |
5684 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF8_MASK 0x3 | |
5685 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF8_SHIFT 0 | |
5686 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF9_MASK 0x3 | |
5687 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF9_SHIFT 2 | |
5688 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF10_MASK 0x3 | |
5689 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF10_SHIFT 4 | |
5690 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF11_MASK 0x3 | |
5691 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF11_SHIFT 6 | |
5692 | u8 flags5; | |
5693 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF12_MASK 0x3 | |
5694 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF12_SHIFT 0 | |
5695 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF13_MASK 0x3 | |
5696 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF13_SHIFT 2 | |
5697 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF14_MASK 0x3 | |
5698 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF14_SHIFT 4 | |
5699 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF15_MASK 0x3 | |
5700 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF15_SHIFT 6 | |
5701 | u8 flags6; | |
5702 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF16_MASK 0x3 | |
5703 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF16_SHIFT 0 | |
5704 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF17_MASK 0x3 | |
5705 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF17_SHIFT 2 | |
5706 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF18_MASK 0x3 | |
5707 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF18_SHIFT 4 | |
5708 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF19_MASK 0x3 | |
5709 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF19_SHIFT 6 | |
5710 | u8 flags7; | |
5711 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF20_MASK 0x3 | |
5712 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF20_SHIFT 0 | |
5713 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF21_MASK 0x3 | |
5714 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF21_SHIFT 2 | |
5715 | #define XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3 | |
5716 | #define XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT 4 | |
5717 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1 | |
5718 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_SHIFT 6 | |
5719 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1 | |
5720 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_SHIFT 7 | |
5721 | u8 flags8; | |
5722 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1 | |
5723 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0 | |
5724 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1 | |
5725 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_SHIFT 1 | |
5726 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_MASK 0x1 | |
5727 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_SHIFT 2 | |
5728 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_MASK 0x1 | |
5729 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_SHIFT 3 | |
5730 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_MASK 0x1 | |
5731 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_SHIFT 4 | |
5732 | #define XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_MASK 0x1 | |
5733 | #define XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_SHIFT 5 | |
5734 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1 | |
5735 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_SHIFT 6 | |
5736 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1 | |
5737 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_SHIFT 7 | |
5738 | u8 flags9; | |
5739 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1 | |
5740 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0 | |
5741 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1 | |
5742 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_SHIFT 1 | |
5743 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1 | |
5744 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_SHIFT 2 | |
5745 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1 | |
5746 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_SHIFT 3 | |
5747 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_MASK 0x1 | |
5748 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_SHIFT 4 | |
5749 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1 | |
5750 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_SHIFT 5 | |
5751 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_MASK 0x1 | |
5752 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_SHIFT 6 | |
5753 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_MASK 0x1 | |
5754 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_SHIFT 7 | |
5755 | u8 flags10; | |
5756 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_MASK 0x1 | |
5757 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_SHIFT 0 | |
5758 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_MASK 0x1 | |
5759 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_SHIFT 1 | |
5760 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_MASK 0x1 | |
5761 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_SHIFT 2 | |
5762 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_MASK 0x1 | |
5763 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_SHIFT 3 | |
5764 | #define XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1 | |
5765 | #define XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT 4 | |
5766 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_MASK 0x1 | |
5767 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_SHIFT 5 | |
5768 | #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_MASK 0x1 | |
5769 | #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_SHIFT 6 | |
5770 | #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_MASK 0x1 | |
5771 | #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_SHIFT 7 | |
5772 | u8 flags11; | |
5773 | #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_MASK 0x1 | |
5774 | #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_SHIFT 0 | |
5775 | #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_MASK 0x1 | |
5776 | #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_SHIFT 1 | |
5777 | #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_MASK 0x1 | |
5778 | #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_SHIFT 2 | |
5779 | #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1 | |
5780 | #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_SHIFT 3 | |
5781 | #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1 | |
5782 | #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_SHIFT 4 | |
5783 | #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_MASK 0x1 | |
5784 | #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_SHIFT 5 | |
5785 | #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1 | |
5786 | #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT 6 | |
5787 | #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1 | |
5788 | #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_SHIFT 7 | |
5789 | u8 flags12; | |
5790 | #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_MASK 0x1 | |
5791 | #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_SHIFT 0 | |
5792 | #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1 | |
5793 | #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_SHIFT 1 | |
5794 | #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1 | |
5795 | #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT 2 | |
5796 | #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1 | |
5797 | #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT 3 | |
5798 | #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_MASK 0x1 | |
5799 | #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_SHIFT 4 | |
5800 | #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1 | |
5801 | #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_SHIFT 5 | |
5802 | #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_MASK 0x1 | |
5803 | #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_SHIFT 6 | |
5804 | #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_MASK 0x1 | |
5805 | #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_SHIFT 7 | |
5806 | u8 flags13; | |
5807 | #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1 | |
5808 | #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0 | |
5809 | #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1 | |
5810 | #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_SHIFT 1 | |
5811 | #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1 | |
5812 | #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT 2 | |
5813 | #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1 | |
5814 | #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT 3 | |
5815 | #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1 | |
5816 | #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT 4 | |
5817 | #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1 | |
5818 | #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT 5 | |
5819 | #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1 | |
5820 | #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT 6 | |
5821 | #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1 | |
5822 | #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT 7 | |
5823 | u8 flags14; | |
5824 | #define XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_MASK 0x1 | |
5825 | #define XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_SHIFT 0 | |
5826 | #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_MASK 0x1 | |
5827 | #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_SHIFT 1 | |
5828 | #define XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_MASK 0x3 | |
5829 | #define XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_SHIFT 2 | |
5830 | #define XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_MASK 0x1 | |
5831 | #define XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_SHIFT 4 | |
5832 | #define XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1 | |
5833 | #define XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT 5 | |
5834 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF23_MASK 0x3 | |
5835 | #define XSTORMROCECONNAGCTXDQEXTLDPART_CF23_SHIFT 6 | |
5836 | u8 byte2; | |
5837 | __le16 physical_q0; | |
5838 | __le16 word1; | |
5839 | __le16 word2; | |
5840 | __le16 word3; | |
5841 | __le16 word4; | |
5842 | __le16 word5; | |
5843 | __le16 conn_dpi; | |
5844 | u8 byte3; | |
5845 | u8 byte4; | |
5846 | u8 byte5; | |
5847 | u8 byte6; | |
5848 | __le32 reg0; | |
5849 | __le32 reg1; | |
5850 | __le32 reg2; | |
5851 | __le32 snd_nxt_psn; | |
5852 | __le32 reg4; | |
5853 | }; | |
5854 | ||
5855 | struct xstorm_rdma_conn_ag_ctx { | |
5856 | u8 reserved0; | |
5857 | u8 state; | |
5858 | u8 flags0; | |
5859 | #define XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 | |
5860 | #define XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 | |
5861 | #define XSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 | |
5862 | #define XSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1 | |
5863 | #define XSTORM_RDMA_CONN_AG_CTX_BIT2_MASK 0x1 | |
5864 | #define XSTORM_RDMA_CONN_AG_CTX_BIT2_SHIFT 2 | |
5865 | #define XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 | |
5866 | #define XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 | |
5867 | #define XSTORM_RDMA_CONN_AG_CTX_BIT4_MASK 0x1 | |
5868 | #define XSTORM_RDMA_CONN_AG_CTX_BIT4_SHIFT 4 | |
5869 | #define XSTORM_RDMA_CONN_AG_CTX_BIT5_MASK 0x1 | |
5870 | #define XSTORM_RDMA_CONN_AG_CTX_BIT5_SHIFT 5 | |
5871 | #define XSTORM_RDMA_CONN_AG_CTX_BIT6_MASK 0x1 | |
5872 | #define XSTORM_RDMA_CONN_AG_CTX_BIT6_SHIFT 6 | |
5873 | #define XSTORM_RDMA_CONN_AG_CTX_BIT7_MASK 0x1 | |
5874 | #define XSTORM_RDMA_CONN_AG_CTX_BIT7_SHIFT 7 | |
5875 | u8 flags1; | |
5876 | #define XSTORM_RDMA_CONN_AG_CTX_BIT8_MASK 0x1 | |
5877 | #define XSTORM_RDMA_CONN_AG_CTX_BIT8_SHIFT 0 | |
5878 | #define XSTORM_RDMA_CONN_AG_CTX_BIT9_MASK 0x1 | |
5879 | #define XSTORM_RDMA_CONN_AG_CTX_BIT9_SHIFT 1 | |
5880 | #define XSTORM_RDMA_CONN_AG_CTX_BIT10_MASK 0x1 | |
5881 | #define XSTORM_RDMA_CONN_AG_CTX_BIT10_SHIFT 2 | |
5882 | #define XSTORM_RDMA_CONN_AG_CTX_BIT11_MASK 0x1 | |
5883 | #define XSTORM_RDMA_CONN_AG_CTX_BIT11_SHIFT 3 | |
5884 | #define XSTORM_RDMA_CONN_AG_CTX_BIT12_MASK 0x1 | |
5885 | #define XSTORM_RDMA_CONN_AG_CTX_BIT12_SHIFT 4 | |
5886 | #define XSTORM_RDMA_CONN_AG_CTX_BIT13_MASK 0x1 | |
5887 | #define XSTORM_RDMA_CONN_AG_CTX_BIT13_SHIFT 5 | |
5888 | #define XSTORM_RDMA_CONN_AG_CTX_BIT14_MASK 0x1 | |
5889 | #define XSTORM_RDMA_CONN_AG_CTX_BIT14_SHIFT 6 | |
5890 | #define XSTORM_RDMA_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1 | |
5891 | #define XSTORM_RDMA_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7 | |
5892 | u8 flags2; | |
5893 | #define XSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3 | |
5894 | #define XSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 0 | |
5895 | #define XSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 | |
5896 | #define XSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 2 | |
5897 | #define XSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 | |
5898 | #define XSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 4 | |
5899 | #define XSTORM_RDMA_CONN_AG_CTX_CF3_MASK 0x3 | |
5900 | #define XSTORM_RDMA_CONN_AG_CTX_CF3_SHIFT 6 | |
5901 | u8 flags3; | |
5902 | #define XSTORM_RDMA_CONN_AG_CTX_CF4_MASK 0x3 | |
5903 | #define XSTORM_RDMA_CONN_AG_CTX_CF4_SHIFT 0 | |
5904 | #define XSTORM_RDMA_CONN_AG_CTX_CF5_MASK 0x3 | |
5905 | #define XSTORM_RDMA_CONN_AG_CTX_CF5_SHIFT 2 | |
5906 | #define XSTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3 | |
5907 | #define XSTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 4 | |
5908 | #define XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 | |
5909 | #define XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 | |
5910 | u8 flags4; | |
5911 | #define XSTORM_RDMA_CONN_AG_CTX_CF8_MASK 0x3 | |
5912 | #define XSTORM_RDMA_CONN_AG_CTX_CF8_SHIFT 0 | |
5913 | #define XSTORM_RDMA_CONN_AG_CTX_CF9_MASK 0x3 | |
5914 | #define XSTORM_RDMA_CONN_AG_CTX_CF9_SHIFT 2 | |
5915 | #define XSTORM_RDMA_CONN_AG_CTX_CF10_MASK 0x3 | |
5916 | #define XSTORM_RDMA_CONN_AG_CTX_CF10_SHIFT 4 | |
5917 | #define XSTORM_RDMA_CONN_AG_CTX_CF11_MASK 0x3 | |
5918 | #define XSTORM_RDMA_CONN_AG_CTX_CF11_SHIFT 6 | |
5919 | u8 flags5; | |
5920 | #define XSTORM_RDMA_CONN_AG_CTX_CF12_MASK 0x3 | |
5921 | #define XSTORM_RDMA_CONN_AG_CTX_CF12_SHIFT 0 | |
5922 | #define XSTORM_RDMA_CONN_AG_CTX_CF13_MASK 0x3 | |
5923 | #define XSTORM_RDMA_CONN_AG_CTX_CF13_SHIFT 2 | |
5924 | #define XSTORM_RDMA_CONN_AG_CTX_CF14_MASK 0x3 | |
5925 | #define XSTORM_RDMA_CONN_AG_CTX_CF14_SHIFT 4 | |
5926 | #define XSTORM_RDMA_CONN_AG_CTX_CF15_MASK 0x3 | |
5927 | #define XSTORM_RDMA_CONN_AG_CTX_CF15_SHIFT 6 | |
5928 | u8 flags6; | |
5929 | #define XSTORM_RDMA_CONN_AG_CTX_CF16_MASK 0x3 | |
5930 | #define XSTORM_RDMA_CONN_AG_CTX_CF16_SHIFT 0 | |
5931 | #define XSTORM_RDMA_CONN_AG_CTX_CF17_MASK 0x3 | |
5932 | #define XSTORM_RDMA_CONN_AG_CTX_CF17_SHIFT 2 | |
5933 | #define XSTORM_RDMA_CONN_AG_CTX_CF18_MASK 0x3 | |
5934 | #define XSTORM_RDMA_CONN_AG_CTX_CF18_SHIFT 4 | |
5935 | #define XSTORM_RDMA_CONN_AG_CTX_CF19_MASK 0x3 | |
5936 | #define XSTORM_RDMA_CONN_AG_CTX_CF19_SHIFT 6 | |
5937 | u8 flags7; | |
5938 | #define XSTORM_RDMA_CONN_AG_CTX_CF20_MASK 0x3 | |
5939 | #define XSTORM_RDMA_CONN_AG_CTX_CF20_SHIFT 0 | |
5940 | #define XSTORM_RDMA_CONN_AG_CTX_CF21_MASK 0x3 | |
5941 | #define XSTORM_RDMA_CONN_AG_CTX_CF21_SHIFT 2 | |
5942 | #define XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_MASK 0x3 | |
5943 | #define XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_SHIFT 4 | |
5944 | #define XSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1 | |
5945 | #define XSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 6 | |
5946 | #define XSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 | |
5947 | #define XSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 7 | |
5948 | u8 flags8; | |
5949 | #define XSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 | |
5950 | #define XSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 0 | |
5951 | #define XSTORM_RDMA_CONN_AG_CTX_CF3EN_MASK 0x1 | |
5952 | #define XSTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT 1 | |
5953 | #define XSTORM_RDMA_CONN_AG_CTX_CF4EN_MASK 0x1 | |
5954 | #define XSTORM_RDMA_CONN_AG_CTX_CF4EN_SHIFT 2 | |
5955 | #define XSTORM_RDMA_CONN_AG_CTX_CF5EN_MASK 0x1 | |
5956 | #define XSTORM_RDMA_CONN_AG_CTX_CF5EN_SHIFT 3 | |
5957 | #define XSTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1 | |
5958 | #define XSTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 4 | |
5959 | #define XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 | |
5960 | #define XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5 | |
5961 | #define XSTORM_RDMA_CONN_AG_CTX_CF8EN_MASK 0x1 | |
5962 | #define XSTORM_RDMA_CONN_AG_CTX_CF8EN_SHIFT 6 | |
5963 | #define XSTORM_RDMA_CONN_AG_CTX_CF9EN_MASK 0x1 | |
5964 | #define XSTORM_RDMA_CONN_AG_CTX_CF9EN_SHIFT 7 | |
5965 | u8 flags9; | |
5966 | #define XSTORM_RDMA_CONN_AG_CTX_CF10EN_MASK 0x1 | |
5967 | #define XSTORM_RDMA_CONN_AG_CTX_CF10EN_SHIFT 0 | |
5968 | #define XSTORM_RDMA_CONN_AG_CTX_CF11EN_MASK 0x1 | |
5969 | #define XSTORM_RDMA_CONN_AG_CTX_CF11EN_SHIFT 1 | |
5970 | #define XSTORM_RDMA_CONN_AG_CTX_CF12EN_MASK 0x1 | |
5971 | #define XSTORM_RDMA_CONN_AG_CTX_CF12EN_SHIFT 2 | |
5972 | #define XSTORM_RDMA_CONN_AG_CTX_CF13EN_MASK 0x1 | |
5973 | #define XSTORM_RDMA_CONN_AG_CTX_CF13EN_SHIFT 3 | |
5974 | #define XSTORM_RDMA_CONN_AG_CTX_CF14EN_MASK 0x1 | |
5975 | #define XSTORM_RDMA_CONN_AG_CTX_CF14EN_SHIFT 4 | |
5976 | #define XSTORM_RDMA_CONN_AG_CTX_CF15EN_MASK 0x1 | |
5977 | #define XSTORM_RDMA_CONN_AG_CTX_CF15EN_SHIFT 5 | |
5978 | #define XSTORM_RDMA_CONN_AG_CTX_CF16EN_MASK 0x1 | |
5979 | #define XSTORM_RDMA_CONN_AG_CTX_CF16EN_SHIFT 6 | |
5980 | #define XSTORM_RDMA_CONN_AG_CTX_CF17EN_MASK 0x1 | |
5981 | #define XSTORM_RDMA_CONN_AG_CTX_CF17EN_SHIFT 7 | |
5982 | u8 flags10; | |
5983 | #define XSTORM_RDMA_CONN_AG_CTX_CF18EN_MASK 0x1 | |
5984 | #define XSTORM_RDMA_CONN_AG_CTX_CF18EN_SHIFT 0 | |
5985 | #define XSTORM_RDMA_CONN_AG_CTX_CF19EN_MASK 0x1 | |
5986 | #define XSTORM_RDMA_CONN_AG_CTX_CF19EN_SHIFT 1 | |
5987 | #define XSTORM_RDMA_CONN_AG_CTX_CF20EN_MASK 0x1 | |
5988 | #define XSTORM_RDMA_CONN_AG_CTX_CF20EN_SHIFT 2 | |
5989 | #define XSTORM_RDMA_CONN_AG_CTX_CF21EN_MASK 0x1 | |
5990 | #define XSTORM_RDMA_CONN_AG_CTX_CF21EN_SHIFT 3 | |
5991 | #define XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 | |
5992 | #define XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 | |
5993 | #define XSTORM_RDMA_CONN_AG_CTX_CF23EN_MASK 0x1 | |
5994 | #define XSTORM_RDMA_CONN_AG_CTX_CF23EN_SHIFT 5 | |
5995 | #define XSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1 | |
5996 | #define XSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 6 | |
5997 | #define XSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1 | |
5998 | #define XSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 7 | |
5999 | u8 flags11; | |
6000 | #define XSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 | |
6001 | #define XSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 0 | |
6002 | #define XSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 | |
6003 | #define XSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 1 | |
6004 | #define XSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 | |
6005 | #define XSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 2 | |
6006 | #define XSTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1 | |
6007 | #define XSTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 3 | |
6008 | #define XSTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1 | |
6009 | #define XSTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 4 | |
6010 | #define XSTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1 | |
6011 | #define XSTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 5 | |
6012 | #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 | |
6013 | #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 | |
6014 | #define XSTORM_RDMA_CONN_AG_CTX_RULE9EN_MASK 0x1 | |
6015 | #define XSTORM_RDMA_CONN_AG_CTX_RULE9EN_SHIFT 7 | |
6016 | u8 flags12; | |
6017 | #define XSTORM_RDMA_CONN_AG_CTX_RULE10EN_MASK 0x1 | |
6018 | #define XSTORM_RDMA_CONN_AG_CTX_RULE10EN_SHIFT 0 | |
6019 | #define XSTORM_RDMA_CONN_AG_CTX_RULE11EN_MASK 0x1 | |
6020 | #define XSTORM_RDMA_CONN_AG_CTX_RULE11EN_SHIFT 1 | |
6021 | #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 | |
6022 | #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 | |
6023 | #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 | |
6024 | #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 | |
6025 | #define XSTORM_RDMA_CONN_AG_CTX_RULE14EN_MASK 0x1 | |
6026 | #define XSTORM_RDMA_CONN_AG_CTX_RULE14EN_SHIFT 4 | |
6027 | #define XSTORM_RDMA_CONN_AG_CTX_RULE15EN_MASK 0x1 | |
6028 | #define XSTORM_RDMA_CONN_AG_CTX_RULE15EN_SHIFT 5 | |
6029 | #define XSTORM_RDMA_CONN_AG_CTX_RULE16EN_MASK 0x1 | |
6030 | #define XSTORM_RDMA_CONN_AG_CTX_RULE16EN_SHIFT 6 | |
6031 | #define XSTORM_RDMA_CONN_AG_CTX_RULE17EN_MASK 0x1 | |
6032 | #define XSTORM_RDMA_CONN_AG_CTX_RULE17EN_SHIFT 7 | |
6033 | u8 flags13; | |
6034 | #define XSTORM_RDMA_CONN_AG_CTX_RULE18EN_MASK 0x1 | |
6035 | #define XSTORM_RDMA_CONN_AG_CTX_RULE18EN_SHIFT 0 | |
6036 | #define XSTORM_RDMA_CONN_AG_CTX_RULE19EN_MASK 0x1 | |
6037 | #define XSTORM_RDMA_CONN_AG_CTX_RULE19EN_SHIFT 1 | |
6038 | #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 | |
6039 | #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 | |
6040 | #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 | |
6041 | #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 | |
6042 | #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 | |
6043 | #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 | |
6044 | #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 | |
6045 | #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 | |
6046 | #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 | |
6047 | #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 | |
6048 | #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 | |
6049 | #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 | |
6050 | u8 flags14; | |
6051 | #define XSTORM_RDMA_CONN_AG_CTX_MIGRATION_MASK 0x1 | |
6052 | #define XSTORM_RDMA_CONN_AG_CTX_MIGRATION_SHIFT 0 | |
6053 | #define XSTORM_RDMA_CONN_AG_CTX_BIT17_MASK 0x1 | |
6054 | #define XSTORM_RDMA_CONN_AG_CTX_BIT17_SHIFT 1 | |
6055 | #define XSTORM_RDMA_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3 | |
6056 | #define XSTORM_RDMA_CONN_AG_CTX_DPM_PORT_NUM_SHIFT 2 | |
6057 | #define XSTORM_RDMA_CONN_AG_CTX_RESERVED_MASK 0x1 | |
6058 | #define XSTORM_RDMA_CONN_AG_CTX_RESERVED_SHIFT 4 | |
6059 | #define XSTORM_RDMA_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 | |
6060 | #define XSTORM_RDMA_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5 | |
6061 | #define XSTORM_RDMA_CONN_AG_CTX_CF23_MASK 0x3 | |
6062 | #define XSTORM_RDMA_CONN_AG_CTX_CF23_SHIFT 6 | |
6063 | u8 byte2; | |
6064 | __le16 physical_q0; | |
6065 | __le16 word1; | |
6066 | __le16 word2; | |
6067 | __le16 word3; | |
6068 | __le16 word4; | |
6069 | __le16 word5; | |
6070 | __le16 conn_dpi; | |
6071 | u8 byte3; | |
6072 | u8 byte4; | |
6073 | u8 byte5; | |
6074 | u8 byte6; | |
6075 | __le32 reg0; | |
6076 | __le32 reg1; | |
6077 | __le32 reg2; | |
6078 | __le32 snd_nxt_psn; | |
6079 | __le32 reg4; | |
6080 | __le32 reg5; | |
6081 | __le32 reg6; | |
6082 | }; | |
6083 | ||
6084 | struct ystorm_rdma_conn_ag_ctx { | |
6085 | u8 byte0; | |
6086 | u8 byte1; | |
6087 | u8 flags0; | |
6088 | #define YSTORM_RDMA_CONN_AG_CTX_BIT0_MASK 0x1 | |
6089 | #define YSTORM_RDMA_CONN_AG_CTX_BIT0_SHIFT 0 | |
6090 | #define YSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 | |
6091 | #define YSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1 | |
6092 | #define YSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3 | |
6093 | #define YSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 2 | |
6094 | #define YSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 | |
6095 | #define YSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4 | |
6096 | #define YSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 | |
6097 | #define YSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6 | |
6098 | u8 flags1; | |
6099 | #define YSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1 | |
6100 | #define YSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 0 | |
6101 | #define YSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 | |
6102 | #define YSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1 | |
6103 | #define YSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 | |
6104 | #define YSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2 | |
6105 | #define YSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1 | |
6106 | #define YSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 3 | |
6107 | #define YSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1 | |
6108 | #define YSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 4 | |
6109 | #define YSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 | |
6110 | #define YSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 5 | |
6111 | #define YSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 | |
6112 | #define YSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 6 | |
6113 | #define YSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 | |
6114 | #define YSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 7 | |
6115 | u8 byte2; | |
6116 | u8 byte3; | |
6117 | __le16 word0; | |
6118 | __le32 reg0; | |
6119 | __le32 reg1; | |
6120 | __le16 word1; | |
6121 | __le16 word2; | |
6122 | __le16 word3; | |
6123 | __le16 word4; | |
6124 | __le32 reg2; | |
6125 | __le32 reg3; | |
6126 | }; | |
6127 | ||
6128 | struct mstorm_roce_conn_st_ctx { | |
6129 | struct regpair temp[6]; | |
6130 | }; | |
6131 | ||
6132 | struct pstorm_roce_conn_st_ctx { | |
6133 | struct regpair temp[16]; | |
6134 | }; | |
6135 | ||
6136 | struct ystorm_roce_conn_st_ctx { | |
6137 | struct regpair temp[2]; | |
6138 | }; | |
6139 | ||
6140 | struct xstorm_roce_conn_st_ctx { | |
6141 | struct regpair temp[22]; | |
6142 | }; | |
6143 | ||
6144 | struct tstorm_roce_conn_st_ctx { | |
6145 | struct regpair temp[30]; | |
6146 | }; | |
6147 | ||
6148 | struct ustorm_roce_conn_st_ctx { | |
6149 | struct regpair temp[12]; | |
6150 | }; | |
6151 | ||
6152 | struct roce_conn_context { | |
6153 | struct ystorm_roce_conn_st_ctx ystorm_st_context; | |
6154 | struct regpair ystorm_st_padding[2]; | |
6155 | struct pstorm_roce_conn_st_ctx pstorm_st_context; | |
6156 | struct xstorm_roce_conn_st_ctx xstorm_st_context; | |
6157 | struct regpair xstorm_st_padding[2]; | |
6158 | struct xstorm_rdma_conn_ag_ctx xstorm_ag_context; | |
6159 | struct tstorm_rdma_conn_ag_ctx tstorm_ag_context; | |
6160 | struct timers_context timer_context; | |
6161 | struct ustorm_rdma_conn_ag_ctx ustorm_ag_context; | |
6162 | struct tstorm_roce_conn_st_ctx tstorm_st_context; | |
6163 | struct mstorm_roce_conn_st_ctx mstorm_st_context; | |
6164 | struct ustorm_roce_conn_st_ctx ustorm_st_context; | |
6165 | struct regpair ustorm_st_padding[2]; | |
6166 | }; | |
6167 | ||
6168 | struct roce_create_qp_req_ramrod_data { | |
6169 | __le16 flags; | |
6170 | #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_MASK 0x3 | |
6171 | #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_SHIFT 0 | |
6172 | #define ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_MASK 0x1 | |
6173 | #define ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_SHIFT 2 | |
6174 | #define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_MASK 0x1 | |
6175 | #define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_SHIFT 3 | |
6176 | #define ROCE_CREATE_QP_REQ_RAMROD_DATA_PRI_MASK 0x7 | |
6177 | #define ROCE_CREATE_QP_REQ_RAMROD_DATA_PRI_SHIFT 4 | |
6178 | #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RESERVED_MASK 0x1 | |
6179 | #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RESERVED_SHIFT 7 | |
6180 | #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK 0xF | |
6181 | #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_SHIFT 8 | |
6182 | #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK 0xF | |
6183 | #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_SHIFT 12 | |
6184 | u8 max_ord; | |
6185 | u8 traffic_class; | |
6186 | u8 hop_limit; | |
6187 | u8 orq_num_pages; | |
6188 | __le16 p_key; | |
6189 | __le32 flow_label; | |
6190 | __le32 dst_qp_id; | |
6191 | __le32 ack_timeout_val; | |
6192 | __le32 initial_psn; | |
6193 | __le16 mtu; | |
6194 | __le16 pd; | |
6195 | __le16 sq_num_pages; | |
6196 | __le16 reseved2; | |
6197 | struct regpair sq_pbl_addr; | |
6198 | struct regpair orq_pbl_addr; | |
6199 | __le16 local_mac_addr[3]; | |
6200 | __le16 remote_mac_addr[3]; | |
6201 | __le16 vlan_id; | |
6202 | __le16 udp_src_port; | |
6203 | __le32 src_gid[4]; | |
6204 | __le32 dst_gid[4]; | |
6205 | struct regpair qp_handle_for_cqe; | |
6206 | struct regpair qp_handle_for_async; | |
6207 | u8 stats_counter_id; | |
6208 | u8 reserved3[7]; | |
6209 | __le32 cq_cid; | |
6210 | __le16 physical_queue0; | |
6211 | __le16 dpi; | |
6212 | }; | |
6213 | ||
6214 | struct roce_create_qp_resp_ramrod_data { | |
6215 | __le16 flags; | |
6216 | #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_MASK 0x3 | |
6217 | #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_SHIFT 0 | |
6218 | #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1 | |
6219 | #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_SHIFT 2 | |
6220 | #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1 | |
6221 | #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_SHIFT 3 | |
6222 | #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK 0x1 | |
6223 | #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN_SHIFT 4 | |
6224 | #define ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_MASK 0x1 | |
6225 | #define ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_SHIFT 5 | |
6226 | #define ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_MASK 0x1 | |
6227 | #define ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_SHIFT 6 | |
05fafbfb YM |
6228 | #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN_MASK 0x1 |
6229 | #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN_SHIFT 7 | |
7a9b6b8f YM |
6230 | #define ROCE_CREATE_QP_RESP_RAMROD_DATA_PRI_MASK 0x7 |
6231 | #define ROCE_CREATE_QP_RESP_RAMROD_DATA_PRI_SHIFT 8 | |
6232 | #define ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK 0x1F | |
6233 | #define ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_SHIFT 11 | |
6234 | u8 max_ird; | |
6235 | u8 traffic_class; | |
6236 | u8 hop_limit; | |
6237 | u8 irq_num_pages; | |
6238 | __le16 p_key; | |
6239 | __le32 flow_label; | |
6240 | __le32 dst_qp_id; | |
6241 | u8 stats_counter_id; | |
6242 | u8 reserved1; | |
6243 | __le16 mtu; | |
6244 | __le32 initial_psn; | |
6245 | __le16 pd; | |
6246 | __le16 rq_num_pages; | |
6247 | struct rdma_srq_id srq_id; | |
6248 | struct regpair rq_pbl_addr; | |
6249 | struct regpair irq_pbl_addr; | |
6250 | __le16 local_mac_addr[3]; | |
6251 | __le16 remote_mac_addr[3]; | |
6252 | __le16 vlan_id; | |
6253 | __le16 udp_src_port; | |
6254 | __le32 src_gid[4]; | |
6255 | __le32 dst_gid[4]; | |
6256 | struct regpair qp_handle_for_cqe; | |
6257 | struct regpair qp_handle_for_async; | |
6258 | __le32 reserved2[2]; | |
6259 | __le32 cq_cid; | |
6260 | __le16 physical_queue0; | |
6261 | __le16 dpi; | |
6262 | }; | |
6263 | ||
6264 | struct roce_destroy_qp_req_output_params { | |
6265 | __le32 num_bound_mw; | |
6266 | __le32 reserved; | |
6267 | }; | |
6268 | ||
6269 | struct roce_destroy_qp_req_ramrod_data { | |
6270 | struct regpair output_params_addr; | |
6271 | }; | |
6272 | ||
6273 | struct roce_destroy_qp_resp_output_params { | |
6274 | __le32 num_invalidated_mw; | |
6275 | __le32 reserved; | |
6276 | }; | |
6277 | ||
6278 | struct roce_destroy_qp_resp_ramrod_data { | |
6279 | struct regpair output_params_addr; | |
6280 | }; | |
6281 | ||
6282 | enum roce_event_opcode { | |
6283 | ROCE_EVENT_CREATE_QP = 11, | |
6284 | ROCE_EVENT_MODIFY_QP, | |
6285 | ROCE_EVENT_QUERY_QP, | |
6286 | ROCE_EVENT_DESTROY_QP, | |
6287 | MAX_ROCE_EVENT_OPCODE | |
6288 | }; | |
6289 | ||
05fafbfb YM |
6290 | struct roce_init_func_ramrod_data { |
6291 | struct rdma_init_func_ramrod_data rdma; | |
6292 | }; | |
6293 | ||
7a9b6b8f YM |
6294 | struct roce_modify_qp_req_ramrod_data { |
6295 | __le16 flags; | |
6296 | #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK 0x1 | |
6297 | #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_SHIFT 0 | |
6298 | #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG_MASK 0x1 | |
6299 | #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG_SHIFT 1 | |
6300 | #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY_MASK 0x1 | |
6301 | #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY_SHIFT 2 | |
6302 | #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG_MASK 0x1 | |
6303 | #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG_SHIFT 3 | |
6304 | #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK 0x1 | |
6305 | #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG_SHIFT 4 | |
6306 | #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG_MASK 0x1 | |
6307 | #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG_SHIFT 5 | |
6308 | #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG_MASK 0x1 | |
6309 | #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG_SHIFT 6 | |
6310 | #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG_MASK 0x1 | |
6311 | #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG_SHIFT 7 | |
6312 | #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG_MASK 0x1 | |
6313 | #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG_SHIFT 8 | |
6314 | #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_FLG_MASK 0x1 | |
6315 | #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_FLG_SHIFT 9 | |
6316 | #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_MASK 0x7 | |
6317 | #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_SHIFT 10 | |
6318 | #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_MASK 0x7 | |
6319 | #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_SHIFT 13 | |
6320 | u8 fields; | |
6321 | #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK 0xF | |
6322 | #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_SHIFT 0 | |
6323 | #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK 0xF | |
6324 | #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_SHIFT 4 | |
6325 | u8 max_ord; | |
6326 | u8 traffic_class; | |
6327 | u8 hop_limit; | |
6328 | __le16 p_key; | |
6329 | __le32 flow_label; | |
6330 | __le32 ack_timeout_val; | |
6331 | __le16 mtu; | |
6332 | __le16 reserved2; | |
6333 | __le32 reserved3[3]; | |
6334 | __le32 src_gid[4]; | |
6335 | __le32 dst_gid[4]; | |
6336 | }; | |
6337 | ||
6338 | struct roce_modify_qp_resp_ramrod_data { | |
6339 | __le16 flags; | |
6340 | #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK 0x1 | |
6341 | #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_SHIFT 0 | |
6342 | #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1 | |
6343 | #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN_SHIFT 1 | |
6344 | #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1 | |
6345 | #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN_SHIFT 2 | |
6346 | #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK 0x1 | |
6347 | #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN_SHIFT 3 | |
6348 | #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG_MASK 0x1 | |
6349 | #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG_SHIFT 4 | |
6350 | #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK 0x1 | |
6351 | #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG_SHIFT 5 | |
6352 | #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG_MASK 0x1 | |
6353 | #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG_SHIFT 6 | |
6354 | #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_FLG_MASK 0x1 | |
6355 | #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_FLG_SHIFT 7 | |
6356 | #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG_MASK 0x1 | |
6357 | #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG_SHIFT 8 | |
6358 | #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_MASK 0x1 | |
6359 | #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_SHIFT 9 | |
6360 | #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RESERVED1_MASK 0x3F | |
6361 | #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RESERVED1_SHIFT 10 | |
6362 | u8 fields; | |
6363 | #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_MASK 0x7 | |
6364 | #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_SHIFT 0 | |
6365 | #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK 0x1F | |
6366 | #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_SHIFT 3 | |
6367 | u8 max_ird; | |
6368 | u8 traffic_class; | |
6369 | u8 hop_limit; | |
6370 | __le16 p_key; | |
6371 | __le32 flow_label; | |
6372 | __le16 mtu; | |
6373 | __le16 reserved2; | |
6374 | __le32 src_gid[4]; | |
6375 | __le32 dst_gid[4]; | |
6376 | }; | |
6377 | ||
6378 | struct roce_query_qp_req_output_params { | |
6379 | __le32 psn; | |
6380 | __le32 flags; | |
6381 | #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_MASK 0x1 | |
6382 | #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_SHIFT 0 | |
6383 | #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG_MASK 0x1 | |
6384 | #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG_SHIFT 1 | |
6385 | #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_RESERVED0_MASK 0x3FFFFFFF | |
6386 | #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_RESERVED0_SHIFT 2 | |
6387 | }; | |
6388 | ||
6389 | struct roce_query_qp_req_ramrod_data { | |
6390 | struct regpair output_params_addr; | |
6391 | }; | |
6392 | ||
6393 | struct roce_query_qp_resp_output_params { | |
6394 | __le32 psn; | |
6395 | __le32 err_flag; | |
6396 | #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG_MASK 0x1 | |
6397 | #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG_SHIFT 0 | |
6398 | #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_RESERVED0_MASK 0x7FFFFFFF | |
6399 | #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_RESERVED0_SHIFT 1 | |
6400 | }; | |
6401 | ||
6402 | struct roce_query_qp_resp_ramrod_data { | |
6403 | struct regpair output_params_addr; | |
6404 | }; | |
6405 | ||
6406 | enum roce_ramrod_cmd_id { | |
6407 | ROCE_RAMROD_CREATE_QP = 11, | |
6408 | ROCE_RAMROD_MODIFY_QP, | |
6409 | ROCE_RAMROD_QUERY_QP, | |
6410 | ROCE_RAMROD_DESTROY_QP, | |
6411 | MAX_ROCE_RAMROD_CMD_ID | |
6412 | }; | |
6413 | ||
6414 | struct mstorm_roce_req_conn_ag_ctx { | |
6415 | u8 byte0; | |
6416 | u8 byte1; | |
6417 | u8 flags0; | |
6418 | #define MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1 | |
6419 | #define MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0 | |
6420 | #define MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1 | |
6421 | #define MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1 | |
6422 | #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3 | |
6423 | #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2 | |
6424 | #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 | |
6425 | #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4 | |
6426 | #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3 | |
6427 | #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6 | |
6428 | u8 flags1; | |
6429 | #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1 | |
6430 | #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0 | |
6431 | #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 | |
6432 | #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1 | |
6433 | #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1 | |
6434 | #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2 | |
6435 | #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 | |
6436 | #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 3 | |
6437 | #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 | |
6438 | #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 4 | |
6439 | #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 | |
6440 | #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 5 | |
6441 | #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 | |
6442 | #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 6 | |
6443 | #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 | |
6444 | #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 7 | |
6445 | __le16 word0; | |
6446 | __le16 word1; | |
6447 | __le32 reg0; | |
6448 | __le32 reg1; | |
6449 | }; | |
6450 | ||
6451 | struct mstorm_roce_resp_conn_ag_ctx { | |
6452 | u8 byte0; | |
6453 | u8 byte1; | |
6454 | u8 flags0; | |
6455 | #define MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1 | |
6456 | #define MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0 | |
6457 | #define MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1 | |
6458 | #define MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1 | |
6459 | #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 | |
6460 | #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2 | |
6461 | #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3 | |
6462 | #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4 | |
6463 | #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3 | |
6464 | #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6 | |
6465 | u8 flags1; | |
6466 | #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 | |
6467 | #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0 | |
6468 | #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1 | |
6469 | #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1 | |
6470 | #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1 | |
6471 | #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2 | |
6472 | #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 | |
6473 | #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 3 | |
6474 | #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 | |
6475 | #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 4 | |
6476 | #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 | |
6477 | #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 5 | |
6478 | #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 | |
6479 | #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 6 | |
6480 | #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 | |
6481 | #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 7 | |
6482 | __le16 word0; | |
6483 | __le16 word1; | |
6484 | __le32 reg0; | |
6485 | __le32 reg1; | |
6486 | }; | |
6487 | ||
6488 | enum roce_flavor { | |
6489 | PLAIN_ROCE /* RoCE v1 */ , | |
6490 | RROCE_IPV4 /* RoCE v2 (Routable RoCE) over ipv4 */ , | |
6491 | RROCE_IPV6 /* RoCE v2 (Routable RoCE) over ipv6 */ , | |
6492 | MAX_ROCE_FLAVOR | |
6493 | }; | |
6494 | ||
6495 | struct tstorm_roce_req_conn_ag_ctx { | |
6496 | u8 reserved0; | |
6497 | u8 state; | |
6498 | u8 flags0; | |
6499 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 | |
6500 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 | |
6501 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURED_MASK 0x1 | |
6502 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURED_SHIFT 1 | |
6503 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURED_MASK 0x1 | |
6504 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURED_SHIFT 2 | |
6505 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_MASK 0x1 | |
6506 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_SHIFT 3 | |
6507 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1 | |
6508 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 4 | |
6509 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_MASK 0x1 | |
6510 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_SHIFT 5 | |
6511 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_MASK 0x3 | |
6512 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_SHIFT 6 | |
6513 | u8 flags1; | |
6514 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 | |
6515 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 0 | |
6516 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_MASK 0x3 | |
6517 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_SHIFT 2 | |
6518 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3 | |
6519 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4 | |
6520 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 | |
6521 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 | |
6522 | u8 flags2; | |
6523 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3 | |
6524 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0 | |
6525 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_MASK 0x3 | |
6526 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_SHIFT 2 | |
6527 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_MASK 0x3 | |
6528 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_SHIFT 4 | |
6529 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_MASK 0x3 | |
6530 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_SHIFT 6 | |
6531 | u8 flags3; | |
6532 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_MASK 0x3 | |
6533 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_SHIFT 0 | |
6534 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_MASK 0x3 | |
6535 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_SHIFT 2 | |
6536 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_MASK 0x1 | |
6537 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_SHIFT 4 | |
6538 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 | |
6539 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 5 | |
6540 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_MASK 0x1 | |
6541 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_SHIFT 6 | |
6542 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1 | |
6543 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7 | |
6544 | u8 flags4; | |
6545 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 | |
6546 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0 | |
6547 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1 | |
6548 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1 | |
6549 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_MASK 0x1 | |
6550 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_SHIFT 2 | |
6551 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_MASK 0x1 | |
6552 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_SHIFT 3 | |
6553 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_MASK 0x1 | |
6554 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_SHIFT 4 | |
6555 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_MASK 0x1 | |
6556 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_SHIFT 5 | |
6557 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_MASK 0x1 | |
6558 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_SHIFT 6 | |
6559 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 | |
6560 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 7 | |
6561 | u8 flags5; | |
6562 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 | |
6563 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 0 | |
6564 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 | |
6565 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 1 | |
6566 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 | |
6567 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 2 | |
6568 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 | |
6569 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 3 | |
6570 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1 | |
6571 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 4 | |
6572 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_MASK 0x1 | |
6573 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_SHIFT 5 | |
6574 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK 0x1 | |
6575 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT 6 | |
6576 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK 0x1 | |
6577 | #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT 7 | |
6578 | __le32 reg0; | |
6579 | __le32 snd_nxt_psn; | |
6580 | __le32 snd_max_psn; | |
6581 | __le32 orq_prod; | |
6582 | __le32 reg4; | |
6583 | __le32 reg5; | |
6584 | __le32 reg6; | |
6585 | __le32 reg7; | |
6586 | __le32 reg8; | |
6587 | u8 tx_cqe_error_type; | |
6588 | u8 orq_cache_idx; | |
6589 | __le16 snd_sq_cons_th; | |
6590 | u8 byte4; | |
6591 | u8 byte5; | |
6592 | __le16 snd_sq_cons; | |
6593 | __le16 word2; | |
6594 | __le16 word3; | |
6595 | __le32 reg9; | |
6596 | __le32 reg10; | |
6597 | }; | |
6598 | ||
6599 | struct tstorm_roce_resp_conn_ag_ctx { | |
6600 | u8 byte0; | |
6601 | u8 state; | |
6602 | u8 flags0; | |
6603 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 | |
6604 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 | |
6605 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1 | |
6606 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1 | |
6607 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_MASK 0x1 | |
6608 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_SHIFT 2 | |
6609 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_MASK 0x1 | |
6610 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_SHIFT 3 | |
6611 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1 | |
6612 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 4 | |
6613 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_MASK 0x1 | |
6614 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_SHIFT 5 | |
6615 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 | |
6616 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 6 | |
6617 | u8 flags1; | |
6618 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3 | |
6619 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT 0 | |
6620 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_MASK 0x3 | |
6621 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_SHIFT 2 | |
6622 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3 | |
6623 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 4 | |
6624 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 | |
6625 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 | |
6626 | u8 flags2; | |
6627 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3 | |
6628 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0 | |
6629 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK 0x3 | |
6630 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT 2 | |
6631 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_MASK 0x3 | |
6632 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_SHIFT 4 | |
6633 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK 0x3 | |
6634 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT 6 | |
6635 | u8 flags3; | |
6636 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK 0x3 | |
6637 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT 0 | |
6638 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK 0x3 | |
6639 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT 2 | |
6640 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 | |
6641 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 4 | |
6642 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1 | |
6643 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 5 | |
6644 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_MASK 0x1 | |
6645 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_SHIFT 6 | |
6646 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1 | |
6647 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 7 | |
6648 | u8 flags4; | |
6649 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 | |
6650 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0 | |
6651 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1 | |
6652 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1 | |
6653 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK 0x1 | |
6654 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT 2 | |
6655 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_MASK 0x1 | |
6656 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_SHIFT 3 | |
6657 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK 0x1 | |
6658 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT 4 | |
6659 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK 0x1 | |
6660 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT 5 | |
6661 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK 0x1 | |
6662 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT 6 | |
6663 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 | |
6664 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 7 | |
6665 | u8 flags5; | |
6666 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 | |
6667 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 0 | |
6668 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 | |
6669 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 1 | |
6670 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 | |
6671 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 2 | |
6672 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 | |
6673 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 3 | |
6674 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1 | |
6675 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 4 | |
6676 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_MASK 0x1 | |
6677 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_SHIFT 5 | |
6678 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1 | |
6679 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 6 | |
6680 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK 0x1 | |
6681 | #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT 7 | |
6682 | __le32 psn_and_rxmit_id_echo; | |
6683 | __le32 reg1; | |
6684 | __le32 reg2; | |
6685 | __le32 reg3; | |
6686 | __le32 reg4; | |
6687 | __le32 reg5; | |
6688 | __le32 reg6; | |
6689 | __le32 reg7; | |
6690 | __le32 reg8; | |
6691 | u8 tx_async_error_type; | |
6692 | u8 byte3; | |
6693 | __le16 rq_cons; | |
6694 | u8 byte4; | |
6695 | u8 byte5; | |
6696 | __le16 rq_prod; | |
6697 | __le16 conn_dpi; | |
6698 | __le16 irq_cons; | |
6699 | __le32 num_invlidated_mw; | |
6700 | __le32 reg10; | |
6701 | }; | |
6702 | ||
6703 | struct ustorm_roce_req_conn_ag_ctx { | |
6704 | u8 byte0; | |
6705 | u8 byte1; | |
6706 | u8 flags0; | |
6707 | #define USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1 | |
6708 | #define USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0 | |
6709 | #define USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1 | |
6710 | #define USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1 | |
6711 | #define USTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3 | |
6712 | #define USTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2 | |
6713 | #define USTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 | |
6714 | #define USTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4 | |
6715 | #define USTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3 | |
6716 | #define USTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6 | |
6717 | u8 flags1; | |
6718 | #define USTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK 0x3 | |
6719 | #define USTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT 0 | |
6720 | #define USTORM_ROCE_REQ_CONN_AG_CTX_CF4_MASK 0x3 | |
6721 | #define USTORM_ROCE_REQ_CONN_AG_CTX_CF4_SHIFT 2 | |
6722 | #define USTORM_ROCE_REQ_CONN_AG_CTX_CF5_MASK 0x3 | |
6723 | #define USTORM_ROCE_REQ_CONN_AG_CTX_CF5_SHIFT 4 | |
6724 | #define USTORM_ROCE_REQ_CONN_AG_CTX_CF6_MASK 0x3 | |
6725 | #define USTORM_ROCE_REQ_CONN_AG_CTX_CF6_SHIFT 6 | |
6726 | u8 flags2; | |
6727 | #define USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1 | |
6728 | #define USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0 | |
6729 | #define USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 | |
6730 | #define USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1 | |
6731 | #define USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1 | |
6732 | #define USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2 | |
6733 | #define USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK 0x1 | |
6734 | #define USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT 3 | |
6735 | #define USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_MASK 0x1 | |
6736 | #define USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_SHIFT 4 | |
6737 | #define USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_MASK 0x1 | |
6738 | #define USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_SHIFT 5 | |
6739 | #define USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_MASK 0x1 | |
6740 | #define USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_SHIFT 6 | |
6741 | #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 | |
6742 | #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 7 | |
6743 | u8 flags3; | |
6744 | #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 | |
6745 | #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 0 | |
6746 | #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 | |
6747 | #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 1 | |
6748 | #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 | |
6749 | #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 2 | |
6750 | #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 | |
6751 | #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 3 | |
6752 | #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1 | |
6753 | #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 4 | |
6754 | #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK 0x1 | |
6755 | #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT 5 | |
6756 | #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK 0x1 | |
6757 | #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT 6 | |
6758 | #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK 0x1 | |
6759 | #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT 7 | |
6760 | u8 byte2; | |
6761 | u8 byte3; | |
6762 | __le16 word0; | |
6763 | __le16 word1; | |
6764 | __le32 reg0; | |
6765 | __le32 reg1; | |
6766 | __le32 reg2; | |
6767 | __le32 reg3; | |
6768 | __le16 word2; | |
6769 | __le16 word3; | |
6770 | }; | |
6771 | ||
6772 | struct ustorm_roce_resp_conn_ag_ctx { | |
6773 | u8 byte0; | |
6774 | u8 byte1; | |
6775 | u8 flags0; | |
6776 | #define USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1 | |
6777 | #define USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0 | |
6778 | #define USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1 | |
6779 | #define USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1 | |
6780 | #define USTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 | |
6781 | #define USTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2 | |
6782 | #define USTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3 | |
6783 | #define USTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4 | |
6784 | #define USTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3 | |
6785 | #define USTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6 | |
6786 | u8 flags1; | |
6787 | #define USTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3 | |
6788 | #define USTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 0 | |
6789 | #define USTORM_ROCE_RESP_CONN_AG_CTX_CF4_MASK 0x3 | |
6790 | #define USTORM_ROCE_RESP_CONN_AG_CTX_CF4_SHIFT 2 | |
6791 | #define USTORM_ROCE_RESP_CONN_AG_CTX_CF5_MASK 0x3 | |
6792 | #define USTORM_ROCE_RESP_CONN_AG_CTX_CF5_SHIFT 4 | |
6793 | #define USTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK 0x3 | |
6794 | #define USTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT 6 | |
6795 | u8 flags2; | |
6796 | #define USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 | |
6797 | #define USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0 | |
6798 | #define USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1 | |
6799 | #define USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1 | |
6800 | #define USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1 | |
6801 | #define USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2 | |
6802 | #define USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1 | |
6803 | #define USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 3 | |
6804 | #define USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_MASK 0x1 | |
6805 | #define USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_SHIFT 4 | |
6806 | #define USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_MASK 0x1 | |
6807 | #define USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_SHIFT 5 | |
6808 | #define USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK 0x1 | |
6809 | #define USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT 6 | |
6810 | #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 | |
6811 | #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 7 | |
6812 | u8 flags3; | |
6813 | #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 | |
6814 | #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 0 | |
6815 | #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 | |
6816 | #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 1 | |
6817 | #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 | |
6818 | #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 2 | |
6819 | #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 | |
6820 | #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 3 | |
6821 | #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1 | |
6822 | #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 4 | |
6823 | #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK 0x1 | |
6824 | #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT 5 | |
6825 | #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1 | |
6826 | #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 6 | |
6827 | #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK 0x1 | |
6828 | #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT 7 | |
6829 | u8 byte2; | |
6830 | u8 byte3; | |
6831 | __le16 word0; | |
6832 | __le16 word1; | |
6833 | __le32 reg0; | |
6834 | __le32 reg1; | |
6835 | __le32 reg2; | |
6836 | __le32 reg3; | |
6837 | __le16 word2; | |
6838 | __le16 word3; | |
6839 | }; | |
6840 | ||
6841 | struct xstorm_roce_req_conn_ag_ctx { | |
6842 | u8 reserved0; | |
6843 | u8 state; | |
6844 | u8 flags0; | |
6845 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 | |
6846 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 | |
6847 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_MASK 0x1 | |
6848 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_SHIFT 1 | |
6849 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_MASK 0x1 | |
6850 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_SHIFT 2 | |
6851 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 | |
6852 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 | |
6853 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_MASK 0x1 | |
6854 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_SHIFT 4 | |
6855 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_MASK 0x1 | |
6856 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_SHIFT 5 | |
6857 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_MASK 0x1 | |
6858 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_SHIFT 6 | |
6859 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_MASK 0x1 | |
6860 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_SHIFT 7 | |
6861 | u8 flags1; | |
6862 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_MASK 0x1 | |
6863 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_SHIFT 0 | |
6864 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_MASK 0x1 | |
6865 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_SHIFT 1 | |
6866 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_MASK 0x1 | |
6867 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_SHIFT 2 | |
6868 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_MASK 0x1 | |
6869 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_SHIFT 3 | |
6870 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT12_MASK 0x1 | |
6871 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT12_SHIFT 4 | |
6872 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT13_MASK 0x1 | |
6873 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT13_SHIFT 5 | |
6874 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_MASK 0x1 | |
6875 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_SHIFT 6 | |
6876 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1 | |
6877 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7 | |
6878 | u8 flags2; | |
6879 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3 | |
6880 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 0 | |
6881 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 | |
6882 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 2 | |
6883 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3 | |
6884 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 4 | |
6885 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK 0x3 | |
6886 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT 6 | |
6887 | u8 flags3; | |
6888 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_MASK 0x3 | |
6889 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_SHIFT 0 | |
6890 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3 | |
6891 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_SHIFT 2 | |
6892 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_MASK 0x3 | |
6893 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_SHIFT 4 | |
6894 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 | |
6895 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 | |
6896 | u8 flags4; | |
6897 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF8_MASK 0x3 | |
6898 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF8_SHIFT 0 | |
6899 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF9_MASK 0x3 | |
6900 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF9_SHIFT 2 | |
6901 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_MASK 0x3 | |
6902 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_SHIFT 4 | |
6903 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_MASK 0x3 | |
6904 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_SHIFT 6 | |
6905 | u8 flags5; | |
6906 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_MASK 0x3 | |
6907 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_SHIFT 0 | |
6908 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_MASK 0x3 | |
6909 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_SHIFT 2 | |
6910 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_MASK 0x3 | |
6911 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_SHIFT 4 | |
6912 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_MASK 0x3 | |
6913 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_SHIFT 6 | |
6914 | u8 flags6; | |
6915 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_MASK 0x3 | |
6916 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_SHIFT 0 | |
6917 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_MASK 0x3 | |
6918 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_SHIFT 2 | |
6919 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_MASK 0x3 | |
6920 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_SHIFT 4 | |
6921 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_MASK 0x3 | |
6922 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_SHIFT 6 | |
6923 | u8 flags7; | |
6924 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_MASK 0x3 | |
6925 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_SHIFT 0 | |
6926 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_MASK 0x3 | |
6927 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_SHIFT 2 | |
6928 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_MASK 0x3 | |
6929 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_SHIFT 4 | |
6930 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1 | |
6931 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 6 | |
6932 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 | |
6933 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 7 | |
6934 | u8 flags8; | |
6935 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1 | |
6936 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 0 | |
6937 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK 0x1 | |
6938 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT 1 | |
6939 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK 0x1 | |
6940 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_SHIFT 2 | |
6941 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1 | |
6942 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 3 | |
6943 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_MASK 0x1 | |
6944 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_SHIFT 4 | |
6945 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 | |
6946 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5 | |
6947 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF8EN_MASK 0x1 | |
6948 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF8EN_SHIFT 6 | |
6949 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF9EN_MASK 0x1 | |
6950 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF9EN_SHIFT 7 | |
6951 | u8 flags9; | |
6952 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_MASK 0x1 | |
6953 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_SHIFT 0 | |
6954 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_MASK 0x1 | |
6955 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_SHIFT 1 | |
6956 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_MASK 0x1 | |
6957 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_SHIFT 2 | |
6958 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_MASK 0x1 | |
6959 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_SHIFT 3 | |
6960 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_MASK 0x1 | |
6961 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_SHIFT 4 | |
6962 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_MASK 0x1 | |
6963 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_SHIFT 5 | |
6964 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_MASK 0x1 | |
6965 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_SHIFT 6 | |
6966 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_MASK 0x1 | |
6967 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_SHIFT 7 | |
6968 | u8 flags10; | |
6969 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_MASK 0x1 | |
6970 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_SHIFT 0 | |
6971 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_MASK 0x1 | |
6972 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_SHIFT 1 | |
6973 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_MASK 0x1 | |
6974 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_SHIFT 2 | |
6975 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_MASK 0x1 | |
6976 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_SHIFT 3 | |
6977 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 | |
6978 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 | |
6979 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_MASK 0x1 | |
6980 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_SHIFT 5 | |
6981 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 | |
6982 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 6 | |
6983 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 | |
6984 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 7 | |
6985 | u8 flags11; | |
6986 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 | |
6987 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 0 | |
6988 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 | |
6989 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 1 | |
6990 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 | |
6991 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 2 | |
6992 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1 | |
6993 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 3 | |
6994 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK 0x1 | |
6995 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT 4 | |
6996 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_MASK 0x1 | |
6997 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_SHIFT 5 | |
6998 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 | |
6999 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 | |
7000 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_MASK 0x1 | |
7001 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_SHIFT 7 | |
7002 | u8 flags12; | |
7003 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_MASK 0x1 | |
7004 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_SHIFT 0 | |
7005 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_MASK 0x1 | |
7006 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_SHIFT 1 | |
7007 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 | |
7008 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 | |
7009 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 | |
7010 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 | |
7011 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_MASK 0x1 | |
7012 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_SHIFT 4 | |
7013 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_MASK 0x1 | |
7014 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_SHIFT 5 | |
7015 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_MASK 0x1 | |
7016 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_SHIFT 6 | |
7017 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_MASK 0x1 | |
7018 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_SHIFT 7 | |
7019 | u8 flags13; | |
7020 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_MASK 0x1 | |
7021 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_SHIFT 0 | |
7022 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_MASK 0x1 | |
7023 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_SHIFT 1 | |
7024 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 | |
7025 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 | |
7026 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 | |
7027 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 | |
7028 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 | |
7029 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 | |
7030 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 | |
7031 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 | |
7032 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 | |
7033 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 | |
7034 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 | |
7035 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 | |
7036 | u8 flags14; | |
7037 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_MASK 0x1 | |
7038 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_SHIFT 0 | |
7039 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_MASK 0x1 | |
7040 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_SHIFT 1 | |
7041 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3 | |
7042 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_SHIFT 2 | |
7043 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_MASK 0x1 | |
7044 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_SHIFT 4 | |
7045 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 | |
7046 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5 | |
7047 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_MASK 0x3 | |
7048 | #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_SHIFT 6 | |
7049 | u8 byte2; | |
7050 | __le16 physical_q0; | |
7051 | __le16 word1; | |
7052 | __le16 sq_cmp_cons; | |
7053 | __le16 sq_cons; | |
7054 | __le16 sq_prod; | |
7055 | __le16 word5; | |
7056 | __le16 conn_dpi; | |
7057 | u8 byte3; | |
7058 | u8 byte4; | |
7059 | u8 byte5; | |
7060 | u8 byte6; | |
7061 | __le32 lsn; | |
7062 | __le32 ssn; | |
7063 | __le32 snd_una_psn; | |
7064 | __le32 snd_nxt_psn; | |
7065 | __le32 reg4; | |
7066 | __le32 orq_cons_th; | |
7067 | __le32 orq_cons; | |
7068 | }; | |
7069 | ||
7070 | struct xstorm_roce_resp_conn_ag_ctx { | |
7071 | u8 reserved0; | |
7072 | u8 state; | |
7073 | u8 flags0; | |
7074 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 | |
7075 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 | |
7076 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_MASK 0x1 | |
7077 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_SHIFT 1 | |
7078 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_MASK 0x1 | |
7079 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_SHIFT 2 | |
7080 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 | |
7081 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 | |
7082 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_MASK 0x1 | |
7083 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_SHIFT 4 | |
7084 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_MASK 0x1 | |
7085 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_SHIFT 5 | |
7086 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_MASK 0x1 | |
7087 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_SHIFT 6 | |
7088 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_MASK 0x1 | |
7089 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_SHIFT 7 | |
7090 | u8 flags1; | |
7091 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_MASK 0x1 | |
7092 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_SHIFT 0 | |
7093 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_MASK 0x1 | |
7094 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_SHIFT 1 | |
7095 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_MASK 0x1 | |
7096 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_SHIFT 2 | |
7097 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_MASK 0x1 | |
7098 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_SHIFT 3 | |
7099 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT12_MASK 0x1 | |
7100 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT12_SHIFT 4 | |
7101 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT13_MASK 0x1 | |
7102 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT13_SHIFT 5 | |
7103 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_MASK 0x1 | |
7104 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_SHIFT 6 | |
7105 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1 | |
7106 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7 | |
7107 | u8 flags2; | |
7108 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 | |
7109 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 0 | |
7110 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3 | |
7111 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 2 | |
7112 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3 | |
7113 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 4 | |
7114 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3 | |
7115 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 6 | |
7116 | u8 flags3; | |
7117 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_MASK 0x3 | |
7118 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_SHIFT 0 | |
7119 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3 | |
7120 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT 2 | |
7121 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_MASK 0x3 | |
7122 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_SHIFT 4 | |
7123 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 | |
7124 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 | |
7125 | u8 flags4; | |
7126 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK 0x3 | |
7127 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT 0 | |
7128 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK 0x3 | |
7129 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT 2 | |
7130 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK 0x3 | |
7131 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT 4 | |
7132 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_MASK 0x3 | |
7133 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_SHIFT 6 | |
7134 | u8 flags5; | |
7135 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_MASK 0x3 | |
7136 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_SHIFT 0 | |
7137 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_MASK 0x3 | |
7138 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_SHIFT 2 | |
7139 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_MASK 0x3 | |
7140 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_SHIFT 4 | |
7141 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_MASK 0x3 | |
7142 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_SHIFT 6 | |
7143 | u8 flags6; | |
7144 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_MASK 0x3 | |
7145 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_SHIFT 0 | |
7146 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_MASK 0x3 | |
7147 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_SHIFT 2 | |
7148 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_MASK 0x3 | |
7149 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_SHIFT 4 | |
7150 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_MASK 0x3 | |
7151 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_SHIFT 6 | |
7152 | u8 flags7; | |
7153 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_MASK 0x3 | |
7154 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_SHIFT 0 | |
7155 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_MASK 0x3 | |
7156 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_SHIFT 2 | |
7157 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_MASK 0x3 | |
7158 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_SHIFT 4 | |
7159 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 | |
7160 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 6 | |
7161 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1 | |
7162 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 7 | |
7163 | u8 flags8; | |
7164 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1 | |
7165 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 0 | |
7166 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1 | |
7167 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 1 | |
7168 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_MASK 0x1 | |
7169 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_SHIFT 2 | |
7170 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1 | |
7171 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 3 | |
7172 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_MASK 0x1 | |
7173 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_SHIFT 4 | |
7174 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 | |
7175 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5 | |
7176 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK 0x1 | |
7177 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT 6 | |
7178 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK 0x1 | |
7179 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT 7 | |
7180 | u8 flags9; | |
7181 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK 0x1 | |
7182 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT 0 | |
7183 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_MASK 0x1 | |
7184 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_SHIFT 1 | |
7185 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_MASK 0x1 | |
7186 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_SHIFT 2 | |
7187 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_MASK 0x1 | |
7188 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_SHIFT 3 | |
7189 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_MASK 0x1 | |
7190 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_SHIFT 4 | |
7191 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_MASK 0x1 | |
7192 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_SHIFT 5 | |
7193 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_MASK 0x1 | |
7194 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_SHIFT 6 | |
7195 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_MASK 0x1 | |
7196 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_SHIFT 7 | |
7197 | u8 flags10; | |
7198 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_MASK 0x1 | |
7199 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_SHIFT 0 | |
7200 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_MASK 0x1 | |
7201 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_SHIFT 1 | |
7202 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_MASK 0x1 | |
7203 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_SHIFT 2 | |
7204 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_MASK 0x1 | |
7205 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_SHIFT 3 | |
7206 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 | |
7207 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 | |
7208 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_MASK 0x1 | |
7209 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_SHIFT 5 | |
7210 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 | |
7211 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 6 | |
7212 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 | |
7213 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 7 | |
7214 | u8 flags11; | |
7215 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 | |
7216 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 0 | |
7217 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 | |
7218 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 1 | |
7219 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 | |
7220 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 2 | |
7221 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1 | |
7222 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 3 | |
7223 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK 0x1 | |
7224 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT 4 | |
7225 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1 | |
7226 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 5 | |
7227 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 | |
7228 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 | |
7229 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_MASK 0x1 | |
7230 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_SHIFT 7 | |
7231 | u8 flags12; | |
7232 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE10EN_MASK 0x1 | |
7233 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE10EN_SHIFT 0 | |
7234 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_MASK 0x1 | |
7235 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_SHIFT 1 | |
7236 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 | |
7237 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 | |
7238 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 | |
7239 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 | |
7240 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_MASK 0x1 | |
7241 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_SHIFT 4 | |
7242 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_MASK 0x1 | |
7243 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_SHIFT 5 | |
7244 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_MASK 0x1 | |
7245 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_SHIFT 6 | |
7246 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_MASK 0x1 | |
7247 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_SHIFT 7 | |
7248 | u8 flags13; | |
7249 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_MASK 0x1 | |
7250 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_SHIFT 0 | |
7251 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_MASK 0x1 | |
7252 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_SHIFT 1 | |
7253 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 | |
7254 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 | |
7255 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 | |
7256 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 | |
7257 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 | |
7258 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 | |
7259 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 | |
7260 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 | |
7261 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 | |
7262 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 | |
7263 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 | |
7264 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 | |
7265 | u8 flags14; | |
7266 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_MASK 0x1 | |
7267 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_SHIFT 0 | |
7268 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_MASK 0x1 | |
7269 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_SHIFT 1 | |
7270 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_MASK 0x1 | |
7271 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_SHIFT 2 | |
7272 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_MASK 0x1 | |
7273 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_SHIFT 3 | |
7274 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_MASK 0x1 | |
7275 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_SHIFT 4 | |
7276 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_MASK 0x1 | |
7277 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_SHIFT 5 | |
7278 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_MASK 0x3 | |
7279 | #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_SHIFT 6 | |
7280 | u8 byte2; | |
7281 | __le16 physical_q0; | |
7282 | __le16 word1; | |
7283 | __le16 irq_prod; | |
7284 | __le16 word3; | |
7285 | __le16 word4; | |
7286 | __le16 word5; | |
7287 | __le16 irq_cons; | |
7288 | u8 rxmit_opcode; | |
7289 | u8 byte4; | |
7290 | u8 byte5; | |
7291 | u8 byte6; | |
7292 | __le32 rxmit_psn_and_id; | |
7293 | __le32 rxmit_bytes_length; | |
7294 | __le32 psn; | |
7295 | __le32 reg3; | |
7296 | __le32 reg4; | |
7297 | __le32 reg5; | |
7298 | __le32 msn_and_syndrome; | |
7299 | }; | |
7300 | ||
7301 | struct ystorm_roce_req_conn_ag_ctx { | |
7302 | u8 byte0; | |
7303 | u8 byte1; | |
7304 | u8 flags0; | |
7305 | #define YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1 | |
7306 | #define YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0 | |
7307 | #define YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1 | |
7308 | #define YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1 | |
7309 | #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3 | |
7310 | #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2 | |
7311 | #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 | |
7312 | #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4 | |
7313 | #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3 | |
7314 | #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6 | |
7315 | u8 flags1; | |
7316 | #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1 | |
7317 | #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0 | |
7318 | #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 | |
7319 | #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1 | |
7320 | #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1 | |
7321 | #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2 | |
7322 | #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 | |
7323 | #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 3 | |
7324 | #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 | |
7325 | #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 4 | |
7326 | #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 | |
7327 | #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 5 | |
7328 | #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 | |
7329 | #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 6 | |
7330 | #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 | |
7331 | #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 7 | |
7332 | u8 byte2; | |
7333 | u8 byte3; | |
7334 | __le16 word0; | |
7335 | __le32 reg0; | |
7336 | __le32 reg1; | |
7337 | __le16 word1; | |
7338 | __le16 word2; | |
7339 | __le16 word3; | |
7340 | __le16 word4; | |
7341 | __le32 reg2; | |
7342 | __le32 reg3; | |
7343 | }; | |
7344 | ||
7345 | struct ystorm_roce_resp_conn_ag_ctx { | |
7346 | u8 byte0; | |
7347 | u8 byte1; | |
7348 | u8 flags0; | |
7349 | #define YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1 | |
7350 | #define YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0 | |
7351 | #define YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1 | |
7352 | #define YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1 | |
7353 | #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 | |
7354 | #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2 | |
7355 | #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3 | |
7356 | #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4 | |
7357 | #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3 | |
7358 | #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6 | |
7359 | u8 flags1; | |
7360 | #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 | |
7361 | #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0 | |
7362 | #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1 | |
7363 | #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1 | |
7364 | #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1 | |
7365 | #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2 | |
7366 | #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 | |
7367 | #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 3 | |
7368 | #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 | |
7369 | #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 4 | |
7370 | #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 | |
7371 | #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 5 | |
7372 | #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 | |
7373 | #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 6 | |
7374 | #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 | |
7375 | #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 7 | |
7376 | u8 byte2; | |
7377 | u8 byte3; | |
7378 | __le16 word0; | |
7379 | __le32 reg0; | |
7380 | __le32 reg1; | |
7381 | __le16 word1; | |
7382 | __le16 word2; | |
7383 | __le16 word3; | |
7384 | __le16 word4; | |
7385 | __le32 reg2; | |
7386 | __le32 reg3; | |
7387 | }; | |
7388 | ||
7389 | struct ystorm_iscsi_conn_st_ctx { | |
7390 | __le32 reserved[4]; | |
7391 | }; | |
7392 | ||
7393 | struct pstorm_iscsi_tcp_conn_st_ctx { | |
7394 | __le32 tcp[32]; | |
7395 | __le32 iscsi[4]; | |
7396 | }; | |
7397 | ||
7398 | struct xstorm_iscsi_tcp_conn_st_ctx { | |
7399 | __le32 reserved_iscsi[40]; | |
7400 | __le32 reserved_tcp[4]; | |
7401 | }; | |
7402 | ||
7403 | struct xstorm_iscsi_conn_ag_ctx { | |
7404 | u8 cdu_validation; | |
7405 | u8 state; | |
7406 | u8 flags0; | |
7407 | #define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 | |
7408 | #define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 | |
7409 | #define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM1_MASK 0x1 | |
7410 | #define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM1_SHIFT 1 | |
7411 | #define XSTORM_ISCSI_CONN_AG_CTX_RESERVED1_MASK 0x1 | |
7412 | #define XSTORM_ISCSI_CONN_AG_CTX_RESERVED1_SHIFT 2 | |
7413 | #define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 | |
7414 | #define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 | |
7415 | #define XSTORM_ISCSI_CONN_AG_CTX_BIT4_MASK 0x1 | |
7416 | #define XSTORM_ISCSI_CONN_AG_CTX_BIT4_SHIFT 4 | |
7417 | #define XSTORM_ISCSI_CONN_AG_CTX_RESERVED2_MASK 0x1 | |
7418 | #define XSTORM_ISCSI_CONN_AG_CTX_RESERVED2_SHIFT 5 | |
7419 | #define XSTORM_ISCSI_CONN_AG_CTX_BIT6_MASK 0x1 | |
7420 | #define XSTORM_ISCSI_CONN_AG_CTX_BIT6_SHIFT 6 | |
7421 | #define XSTORM_ISCSI_CONN_AG_CTX_BIT7_MASK 0x1 | |
7422 | #define XSTORM_ISCSI_CONN_AG_CTX_BIT7_SHIFT 7 | |
7423 | u8 flags1; | |
7424 | #define XSTORM_ISCSI_CONN_AG_CTX_BIT8_MASK 0x1 | |
7425 | #define XSTORM_ISCSI_CONN_AG_CTX_BIT8_SHIFT 0 | |
7426 | #define XSTORM_ISCSI_CONN_AG_CTX_BIT9_MASK 0x1 | |
7427 | #define XSTORM_ISCSI_CONN_AG_CTX_BIT9_SHIFT 1 | |
7428 | #define XSTORM_ISCSI_CONN_AG_CTX_BIT10_MASK 0x1 | |
7429 | #define XSTORM_ISCSI_CONN_AG_CTX_BIT10_SHIFT 2 | |
7430 | #define XSTORM_ISCSI_CONN_AG_CTX_BIT11_MASK 0x1 | |
7431 | #define XSTORM_ISCSI_CONN_AG_CTX_BIT11_SHIFT 3 | |
7432 | #define XSTORM_ISCSI_CONN_AG_CTX_BIT12_MASK 0x1 | |
7433 | #define XSTORM_ISCSI_CONN_AG_CTX_BIT12_SHIFT 4 | |
7434 | #define XSTORM_ISCSI_CONN_AG_CTX_BIT13_MASK 0x1 | |
7435 | #define XSTORM_ISCSI_CONN_AG_CTX_BIT13_SHIFT 5 | |
7436 | #define XSTORM_ISCSI_CONN_AG_CTX_BIT14_MASK 0x1 | |
7437 | #define XSTORM_ISCSI_CONN_AG_CTX_BIT14_SHIFT 6 | |
7438 | #define XSTORM_ISCSI_CONN_AG_CTX_TX_TRUNCATE_MASK 0x1 | |
7439 | #define XSTORM_ISCSI_CONN_AG_CTX_TX_TRUNCATE_SHIFT 7 | |
7440 | u8 flags2; | |
7441 | #define XSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3 | |
7442 | #define XSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 0 | |
7443 | #define XSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3 | |
7444 | #define XSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 2 | |
7445 | #define XSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3 | |
7446 | #define XSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 4 | |
7447 | #define XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3 | |
7448 | #define XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 6 | |
7449 | u8 flags3; | |
7450 | #define XSTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3 | |
7451 | #define XSTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT 0 | |
7452 | #define XSTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3 | |
7453 | #define XSTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT 2 | |
7454 | #define XSTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3 | |
7455 | #define XSTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT 4 | |
7456 | #define XSTORM_ISCSI_CONN_AG_CTX_CF7_MASK 0x3 | |
7457 | #define XSTORM_ISCSI_CONN_AG_CTX_CF7_SHIFT 6 | |
7458 | u8 flags4; | |
7459 | #define XSTORM_ISCSI_CONN_AG_CTX_CF8_MASK 0x3 | |
7460 | #define XSTORM_ISCSI_CONN_AG_CTX_CF8_SHIFT 0 | |
7461 | #define XSTORM_ISCSI_CONN_AG_CTX_CF9_MASK 0x3 | |
7462 | #define XSTORM_ISCSI_CONN_AG_CTX_CF9_SHIFT 2 | |
7463 | #define XSTORM_ISCSI_CONN_AG_CTX_CF10_MASK 0x3 | |
7464 | #define XSTORM_ISCSI_CONN_AG_CTX_CF10_SHIFT 4 | |
7465 | #define XSTORM_ISCSI_CONN_AG_CTX_CF11_MASK 0x3 | |
7466 | #define XSTORM_ISCSI_CONN_AG_CTX_CF11_SHIFT 6 | |
7467 | u8 flags5; | |
7468 | #define XSTORM_ISCSI_CONN_AG_CTX_CF12_MASK 0x3 | |
7469 | #define XSTORM_ISCSI_CONN_AG_CTX_CF12_SHIFT 0 | |
7470 | #define XSTORM_ISCSI_CONN_AG_CTX_CF13_MASK 0x3 | |
7471 | #define XSTORM_ISCSI_CONN_AG_CTX_CF13_SHIFT 2 | |
7472 | #define XSTORM_ISCSI_CONN_AG_CTX_CF14_MASK 0x3 | |
7473 | #define XSTORM_ISCSI_CONN_AG_CTX_CF14_SHIFT 4 | |
7474 | #define XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_MASK 0x3 | |
7475 | #define XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_SHIFT 6 | |
7476 | u8 flags6; | |
7477 | #define XSTORM_ISCSI_CONN_AG_CTX_CF16_MASK 0x3 | |
7478 | #define XSTORM_ISCSI_CONN_AG_CTX_CF16_SHIFT 0 | |
7479 | #define XSTORM_ISCSI_CONN_AG_CTX_CF17_MASK 0x3 | |
7480 | #define XSTORM_ISCSI_CONN_AG_CTX_CF17_SHIFT 2 | |
7481 | #define XSTORM_ISCSI_CONN_AG_CTX_CF18_MASK 0x3 | |
7482 | #define XSTORM_ISCSI_CONN_AG_CTX_CF18_SHIFT 4 | |
7483 | #define XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_MASK 0x3 | |
7484 | #define XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_SHIFT 6 | |
7485 | u8 flags7; | |
7486 | #define XSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 | |
7487 | #define XSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 | |
7488 | #define XSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q1_MASK 0x3 | |
7489 | #define XSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q1_SHIFT 2 | |
7490 | #define XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_MASK 0x3 | |
7491 | #define XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_SHIFT 4 | |
7492 | #define XSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1 | |
7493 | #define XSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 6 | |
7494 | #define XSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1 | |
7495 | #define XSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 7 | |
7496 | u8 flags8; | |
7497 | #define XSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1 | |
7498 | #define XSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 0 | |
7499 | #define XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1 | |
7500 | #define XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 1 | |
7501 | #define XSTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK 0x1 | |
7502 | #define XSTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT 2 | |
7503 | #define XSTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK 0x1 | |
7504 | #define XSTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT 3 | |
7505 | #define XSTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK 0x1 | |
7506 | #define XSTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT 4 | |
7507 | #define XSTORM_ISCSI_CONN_AG_CTX_CF7EN_MASK 0x1 | |
7508 | #define XSTORM_ISCSI_CONN_AG_CTX_CF7EN_SHIFT 5 | |
7509 | #define XSTORM_ISCSI_CONN_AG_CTX_CF8EN_MASK 0x1 | |
7510 | #define XSTORM_ISCSI_CONN_AG_CTX_CF8EN_SHIFT 6 | |
7511 | #define XSTORM_ISCSI_CONN_AG_CTX_CF9EN_MASK 0x1 | |
7512 | #define XSTORM_ISCSI_CONN_AG_CTX_CF9EN_SHIFT 7 | |
7513 | u8 flags9; | |
7514 | #define XSTORM_ISCSI_CONN_AG_CTX_CF10EN_MASK 0x1 | |
7515 | #define XSTORM_ISCSI_CONN_AG_CTX_CF10EN_SHIFT 0 | |
7516 | #define XSTORM_ISCSI_CONN_AG_CTX_CF11EN_MASK 0x1 | |
7517 | #define XSTORM_ISCSI_CONN_AG_CTX_CF11EN_SHIFT 1 | |
7518 | #define XSTORM_ISCSI_CONN_AG_CTX_CF12EN_MASK 0x1 | |
7519 | #define XSTORM_ISCSI_CONN_AG_CTX_CF12EN_SHIFT 2 | |
7520 | #define XSTORM_ISCSI_CONN_AG_CTX_CF13EN_MASK 0x1 | |
7521 | #define XSTORM_ISCSI_CONN_AG_CTX_CF13EN_SHIFT 3 | |
7522 | #define XSTORM_ISCSI_CONN_AG_CTX_CF14EN_MASK 0x1 | |
7523 | #define XSTORM_ISCSI_CONN_AG_CTX_CF14EN_SHIFT 4 | |
7524 | #define XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_EN_MASK 0x1 | |
7525 | #define XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_EN_SHIFT 5 | |
7526 | #define XSTORM_ISCSI_CONN_AG_CTX_CF16EN_MASK 0x1 | |
7527 | #define XSTORM_ISCSI_CONN_AG_CTX_CF16EN_SHIFT 6 | |
7528 | #define XSTORM_ISCSI_CONN_AG_CTX_CF17EN_MASK 0x1 | |
7529 | #define XSTORM_ISCSI_CONN_AG_CTX_CF17EN_SHIFT 7 | |
7530 | u8 flags10; | |
7531 | #define XSTORM_ISCSI_CONN_AG_CTX_CF18EN_MASK 0x1 | |
7532 | #define XSTORM_ISCSI_CONN_AG_CTX_CF18EN_SHIFT 0 | |
7533 | #define XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_EN_MASK 0x1 | |
7534 | #define XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_EN_SHIFT 1 | |
7535 | #define XSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 | |
7536 | #define XSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 | |
7537 | #define XSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q1_EN_MASK 0x1 | |
7538 | #define XSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q1_EN_SHIFT 3 | |
7539 | #define XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 | |
7540 | #define XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 | |
7541 | #define XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_EN_MASK 0x1 | |
7542 | #define XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_EN_SHIFT 5 | |
7543 | #define XSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1 | |
7544 | #define XSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 6 | |
7545 | #define XSTORM_ISCSI_CONN_AG_CTX_MORE_TO_SEND_DEC_RULE_EN_MASK 0x1 | |
7546 | #define XSTORM_ISCSI_CONN_AG_CTX_MORE_TO_SEND_DEC_RULE_EN_SHIFT 7 | |
7547 | u8 flags11; | |
7548 | #define XSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1 | |
7549 | #define XSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 0 | |
7550 | #define XSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1 | |
7551 | #define XSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 1 | |
7552 | #define XSTORM_ISCSI_CONN_AG_CTX_RESERVED3_MASK 0x1 | |
7553 | #define XSTORM_ISCSI_CONN_AG_CTX_RESERVED3_SHIFT 2 | |
7554 | #define XSTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK 0x1 | |
7555 | #define XSTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT 3 | |
7556 | #define XSTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK 0x1 | |
7557 | #define XSTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT 4 | |
7558 | #define XSTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK 0x1 | |
7559 | #define XSTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT 5 | |
7560 | #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 | |
7561 | #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 | |
7562 | #define XSTORM_ISCSI_CONN_AG_CTX_RULE9EN_MASK 0x1 | |
7563 | #define XSTORM_ISCSI_CONN_AG_CTX_RULE9EN_SHIFT 7 | |
7564 | u8 flags12; | |
7565 | #define XSTORM_ISCSI_CONN_AG_CTX_SQ_DEC_RULE_EN_MASK 0x1 | |
7566 | #define XSTORM_ISCSI_CONN_AG_CTX_SQ_DEC_RULE_EN_SHIFT 0 | |
7567 | #define XSTORM_ISCSI_CONN_AG_CTX_RULE11EN_MASK 0x1 | |
7568 | #define XSTORM_ISCSI_CONN_AG_CTX_RULE11EN_SHIFT 1 | |
7569 | #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 | |
7570 | #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 | |
7571 | #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 | |
7572 | #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 | |
7573 | #define XSTORM_ISCSI_CONN_AG_CTX_RULE14EN_MASK 0x1 | |
7574 | #define XSTORM_ISCSI_CONN_AG_CTX_RULE14EN_SHIFT 4 | |
7575 | #define XSTORM_ISCSI_CONN_AG_CTX_RULE15EN_MASK 0x1 | |
7576 | #define XSTORM_ISCSI_CONN_AG_CTX_RULE15EN_SHIFT 5 | |
7577 | #define XSTORM_ISCSI_CONN_AG_CTX_RULE16EN_MASK 0x1 | |
7578 | #define XSTORM_ISCSI_CONN_AG_CTX_RULE16EN_SHIFT 6 | |
7579 | #define XSTORM_ISCSI_CONN_AG_CTX_RULE17EN_MASK 0x1 | |
7580 | #define XSTORM_ISCSI_CONN_AG_CTX_RULE17EN_SHIFT 7 | |
7581 | u8 flags13; | |
7582 | #define XSTORM_ISCSI_CONN_AG_CTX_R2TQ_DEC_RULE_EN_MASK 0x1 | |
7583 | #define XSTORM_ISCSI_CONN_AG_CTX_R2TQ_DEC_RULE_EN_SHIFT 0 | |
7584 | #define XSTORM_ISCSI_CONN_AG_CTX_HQ_DEC_RULE_EN_MASK 0x1 | |
7585 | #define XSTORM_ISCSI_CONN_AG_CTX_HQ_DEC_RULE_EN_SHIFT 1 | |
7586 | #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 | |
7587 | #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 | |
7588 | #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 | |
7589 | #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 | |
7590 | #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 | |
7591 | #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 | |
7592 | #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 | |
7593 | #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 | |
7594 | #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 | |
7595 | #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 | |
7596 | #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 | |
7597 | #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 | |
7598 | u8 flags14; | |
7599 | #define XSTORM_ISCSI_CONN_AG_CTX_BIT16_MASK 0x1 | |
7600 | #define XSTORM_ISCSI_CONN_AG_CTX_BIT16_SHIFT 0 | |
7601 | #define XSTORM_ISCSI_CONN_AG_CTX_BIT17_MASK 0x1 | |
7602 | #define XSTORM_ISCSI_CONN_AG_CTX_BIT17_SHIFT 1 | |
7603 | #define XSTORM_ISCSI_CONN_AG_CTX_BIT18_MASK 0x1 | |
7604 | #define XSTORM_ISCSI_CONN_AG_CTX_BIT18_SHIFT 2 | |
7605 | #define XSTORM_ISCSI_CONN_AG_CTX_BIT19_MASK 0x1 | |
7606 | #define XSTORM_ISCSI_CONN_AG_CTX_BIT19_SHIFT 3 | |
7607 | #define XSTORM_ISCSI_CONN_AG_CTX_BIT20_MASK 0x1 | |
7608 | #define XSTORM_ISCSI_CONN_AG_CTX_BIT20_SHIFT 4 | |
7609 | #define XSTORM_ISCSI_CONN_AG_CTX_DUMMY_READ_DONE_MASK 0x1 | |
7610 | #define XSTORM_ISCSI_CONN_AG_CTX_DUMMY_READ_DONE_SHIFT 5 | |
7611 | #define XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_MASK 0x3 | |
7612 | #define XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_SHIFT 6 | |
7613 | u8 byte2; | |
7614 | __le16 physical_q0; | |
7615 | __le16 physical_q1; | |
7616 | __le16 dummy_dorq_var; | |
7617 | __le16 sq_cons; | |
7618 | __le16 sq_prod; | |
7619 | __le16 word5; | |
7620 | __le16 slow_io_total_data_tx_update; | |
7621 | u8 byte3; | |
7622 | u8 byte4; | |
7623 | u8 byte5; | |
7624 | u8 byte6; | |
7625 | __le32 reg0; | |
7626 | __le32 reg1; | |
7627 | __le32 reg2; | |
7628 | __le32 more_to_send_seq; | |
7629 | __le32 reg4; | |
7630 | __le32 reg5; | |
7631 | __le32 hq_scan_next_relevant_ack; | |
7632 | __le16 r2tq_prod; | |
7633 | __le16 r2tq_cons; | |
7634 | __le16 hq_prod; | |
7635 | __le16 hq_cons; | |
7636 | __le32 remain_seq; | |
7637 | __le32 bytes_to_next_pdu; | |
7638 | __le32 hq_tcp_seq; | |
7639 | u8 byte7; | |
7640 | u8 byte8; | |
7641 | u8 byte9; | |
7642 | u8 byte10; | |
7643 | u8 byte11; | |
7644 | u8 byte12; | |
7645 | u8 byte13; | |
7646 | u8 byte14; | |
7647 | u8 byte15; | |
7648 | u8 byte16; | |
7649 | __le16 word11; | |
7650 | __le32 reg10; | |
7651 | __le32 reg11; | |
7652 | __le32 exp_stat_sn; | |
7653 | __le32 reg13; | |
7654 | __le32 reg14; | |
7655 | __le32 reg15; | |
7656 | __le32 reg16; | |
7657 | __le32 reg17; | |
7658 | }; | |
7659 | ||
7660 | struct tstorm_iscsi_conn_ag_ctx { | |
7661 | u8 reserved0; | |
7662 | u8 state; | |
7663 | u8 flags0; | |
7664 | #define TSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 | |
7665 | #define TSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 | |
7666 | #define TSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1 | |
7667 | #define TSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1 | |
7668 | #define TSTORM_ISCSI_CONN_AG_CTX_BIT2_MASK 0x1 | |
7669 | #define TSTORM_ISCSI_CONN_AG_CTX_BIT2_SHIFT 2 | |
7670 | #define TSTORM_ISCSI_CONN_AG_CTX_BIT3_MASK 0x1 | |
7671 | #define TSTORM_ISCSI_CONN_AG_CTX_BIT3_SHIFT 3 | |
7672 | #define TSTORM_ISCSI_CONN_AG_CTX_BIT4_MASK 0x1 | |
7673 | #define TSTORM_ISCSI_CONN_AG_CTX_BIT4_SHIFT 4 | |
7674 | #define TSTORM_ISCSI_CONN_AG_CTX_BIT5_MASK 0x1 | |
7675 | #define TSTORM_ISCSI_CONN_AG_CTX_BIT5_SHIFT 5 | |
7676 | #define TSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3 | |
7677 | #define TSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 6 | |
7678 | u8 flags1; | |
7679 | #define TSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3 | |
7680 | #define TSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 0 | |
7681 | #define TSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3 | |
7682 | #define TSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 2 | |
7683 | #define TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3 | |
7684 | #define TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 4 | |
7685 | #define TSTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3 | |
7686 | #define TSTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT 6 | |
7687 | u8 flags2; | |
7688 | #define TSTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3 | |
7689 | #define TSTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT 0 | |
7690 | #define TSTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3 | |
7691 | #define TSTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT 2 | |
7692 | #define TSTORM_ISCSI_CONN_AG_CTX_CF7_MASK 0x3 | |
7693 | #define TSTORM_ISCSI_CONN_AG_CTX_CF7_SHIFT 4 | |
7694 | #define TSTORM_ISCSI_CONN_AG_CTX_CF8_MASK 0x3 | |
7695 | #define TSTORM_ISCSI_CONN_AG_CTX_CF8_SHIFT 6 | |
7696 | u8 flags3; | |
7697 | #define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 | |
7698 | #define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 | |
7699 | #define TSTORM_ISCSI_CONN_AG_CTX_CF10_MASK 0x3 | |
7700 | #define TSTORM_ISCSI_CONN_AG_CTX_CF10_SHIFT 2 | |
7701 | #define TSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1 | |
7702 | #define TSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 4 | |
7703 | #define TSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1 | |
7704 | #define TSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 5 | |
7705 | #define TSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1 | |
7706 | #define TSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 6 | |
7707 | #define TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1 | |
7708 | #define TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 7 | |
7709 | u8 flags4; | |
7710 | #define TSTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK 0x1 | |
7711 | #define TSTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT 0 | |
7712 | #define TSTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK 0x1 | |
7713 | #define TSTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT 1 | |
7714 | #define TSTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK 0x1 | |
7715 | #define TSTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT 2 | |
7716 | #define TSTORM_ISCSI_CONN_AG_CTX_CF7EN_MASK 0x1 | |
7717 | #define TSTORM_ISCSI_CONN_AG_CTX_CF7EN_SHIFT 3 | |
7718 | #define TSTORM_ISCSI_CONN_AG_CTX_CF8EN_MASK 0x1 | |
7719 | #define TSTORM_ISCSI_CONN_AG_CTX_CF8EN_SHIFT 4 | |
7720 | #define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 | |
7721 | #define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 5 | |
7722 | #define TSTORM_ISCSI_CONN_AG_CTX_CF10EN_MASK 0x1 | |
7723 | #define TSTORM_ISCSI_CONN_AG_CTX_CF10EN_SHIFT 6 | |
7724 | #define TSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1 | |
7725 | #define TSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 7 | |
7726 | u8 flags5; | |
7727 | #define TSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1 | |
7728 | #define TSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 0 | |
7729 | #define TSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1 | |
7730 | #define TSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 1 | |
7731 | #define TSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1 | |
7732 | #define TSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 2 | |
7733 | #define TSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1 | |
7734 | #define TSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 3 | |
7735 | #define TSTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK 0x1 | |
7736 | #define TSTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT 4 | |
7737 | #define TSTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK 0x1 | |
7738 | #define TSTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT 5 | |
7739 | #define TSTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK 0x1 | |
7740 | #define TSTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT 6 | |
7741 | #define TSTORM_ISCSI_CONN_AG_CTX_RULE8EN_MASK 0x1 | |
7742 | #define TSTORM_ISCSI_CONN_AG_CTX_RULE8EN_SHIFT 7 | |
7743 | __le32 reg0; | |
7744 | __le32 reg1; | |
7745 | __le32 reg2; | |
7746 | __le32 reg3; | |
7747 | __le32 reg4; | |
7748 | __le32 reg5; | |
7749 | __le32 reg6; | |
7750 | __le32 reg7; | |
7751 | __le32 reg8; | |
7752 | u8 byte2; | |
7753 | u8 byte3; | |
7754 | __le16 word0; | |
7755 | }; | |
7756 | ||
7757 | struct ustorm_iscsi_conn_ag_ctx { | |
7758 | u8 byte0; | |
7759 | u8 byte1; | |
7760 | u8 flags0; | |
7761 | #define USTORM_ISCSI_CONN_AG_CTX_BIT0_MASK 0x1 | |
7762 | #define USTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT 0 | |
7763 | #define USTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1 | |
7764 | #define USTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1 | |
7765 | #define USTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3 | |
7766 | #define USTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 2 | |
7767 | #define USTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3 | |
7768 | #define USTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 4 | |
7769 | #define USTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3 | |
7770 | #define USTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 6 | |
7771 | u8 flags1; | |
7772 | #define USTORM_ISCSI_CONN_AG_CTX_CF3_MASK 0x3 | |
7773 | #define USTORM_ISCSI_CONN_AG_CTX_CF3_SHIFT 0 | |
7774 | #define USTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3 | |
7775 | #define USTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT 2 | |
7776 | #define USTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3 | |
7777 | #define USTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT 4 | |
7778 | #define USTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3 | |
7779 | #define USTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT 6 | |
7780 | u8 flags2; | |
7781 | #define USTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1 | |
7782 | #define USTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 0 | |
7783 | #define USTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1 | |
7784 | #define USTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 1 | |
7785 | #define USTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1 | |
7786 | #define USTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 2 | |
7787 | #define USTORM_ISCSI_CONN_AG_CTX_CF3EN_MASK 0x1 | |
7788 | #define USTORM_ISCSI_CONN_AG_CTX_CF3EN_SHIFT 3 | |
7789 | #define USTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK 0x1 | |
7790 | #define USTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT 4 | |
7791 | #define USTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK 0x1 | |
7792 | #define USTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT 5 | |
7793 | #define USTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK 0x1 | |
7794 | #define USTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT 6 | |
7795 | #define USTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1 | |
7796 | #define USTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 7 | |
7797 | u8 flags3; | |
7798 | #define USTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1 | |
7799 | #define USTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 0 | |
7800 | #define USTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1 | |
7801 | #define USTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 1 | |
7802 | #define USTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1 | |
7803 | #define USTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 2 | |
7804 | #define USTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1 | |
7805 | #define USTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 3 | |
7806 | #define USTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK 0x1 | |
7807 | #define USTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT 4 | |
7808 | #define USTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK 0x1 | |
7809 | #define USTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT 5 | |
7810 | #define USTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK 0x1 | |
7811 | #define USTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT 6 | |
7812 | #define USTORM_ISCSI_CONN_AG_CTX_RULE8EN_MASK 0x1 | |
7813 | #define USTORM_ISCSI_CONN_AG_CTX_RULE8EN_SHIFT 7 | |
7814 | u8 byte2; | |
7815 | u8 byte3; | |
7816 | __le16 word0; | |
7817 | __le16 word1; | |
7818 | __le32 reg0; | |
7819 | __le32 reg1; | |
7820 | __le32 reg2; | |
7821 | __le32 reg3; | |
7822 | __le16 word2; | |
7823 | __le16 word3; | |
7824 | }; | |
7825 | ||
7826 | struct tstorm_iscsi_conn_st_ctx { | |
7827 | __le32 reserved[40]; | |
7828 | }; | |
7829 | ||
7830 | struct mstorm_iscsi_conn_ag_ctx { | |
7831 | u8 reserved; | |
7832 | u8 state; | |
7833 | u8 flags0; | |
7834 | #define MSTORM_ISCSI_CONN_AG_CTX_BIT0_MASK 0x1 | |
7835 | #define MSTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT 0 | |
7836 | #define MSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1 | |
7837 | #define MSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1 | |
7838 | #define MSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3 | |
7839 | #define MSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 2 | |
7840 | #define MSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3 | |
7841 | #define MSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 4 | |
7842 | #define MSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3 | |
7843 | #define MSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 6 | |
7844 | u8 flags1; | |
7845 | #define MSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1 | |
7846 | #define MSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 0 | |
7847 | #define MSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1 | |
7848 | #define MSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 1 | |
7849 | #define MSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1 | |
7850 | #define MSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 2 | |
7851 | #define MSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1 | |
7852 | #define MSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 3 | |
7853 | #define MSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1 | |
7854 | #define MSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 4 | |
7855 | #define MSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1 | |
7856 | #define MSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 5 | |
7857 | #define MSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1 | |
7858 | #define MSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 6 | |
7859 | #define MSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1 | |
7860 | #define MSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 7 | |
7861 | __le16 word0; | |
7862 | __le16 word1; | |
7863 | __le32 reg0; | |
7864 | __le32 reg1; | |
7865 | }; | |
7866 | ||
7867 | struct mstorm_iscsi_tcp_conn_st_ctx { | |
7868 | __le32 reserved_tcp[20]; | |
7869 | __le32 reserved_iscsi[8]; | |
7870 | }; | |
7871 | ||
7872 | struct ustorm_iscsi_conn_st_ctx { | |
7873 | __le32 reserved[52]; | |
7874 | }; | |
7875 | ||
7876 | struct iscsi_conn_context { | |
7877 | struct ystorm_iscsi_conn_st_ctx ystorm_st_context; | |
7878 | struct regpair ystorm_st_padding[2]; | |
7879 | struct pstorm_iscsi_tcp_conn_st_ctx pstorm_st_context; | |
7880 | struct regpair pstorm_st_padding[2]; | |
7881 | struct pb_context xpb2_context; | |
7882 | struct xstorm_iscsi_tcp_conn_st_ctx xstorm_st_context; | |
7883 | struct regpair xstorm_st_padding[2]; | |
7884 | struct xstorm_iscsi_conn_ag_ctx xstorm_ag_context; | |
7885 | struct tstorm_iscsi_conn_ag_ctx tstorm_ag_context; | |
7886 | struct regpair tstorm_ag_padding[2]; | |
7887 | struct timers_context timer_context; | |
7888 | struct ustorm_iscsi_conn_ag_ctx ustorm_ag_context; | |
7889 | struct pb_context upb_context; | |
7890 | struct tstorm_iscsi_conn_st_ctx tstorm_st_context; | |
7891 | struct regpair tstorm_st_padding[2]; | |
7892 | struct mstorm_iscsi_conn_ag_ctx mstorm_ag_context; | |
7893 | struct mstorm_iscsi_tcp_conn_st_ctx mstorm_st_context; | |
7894 | struct ustorm_iscsi_conn_st_ctx ustorm_st_context; | |
7895 | }; | |
7896 | ||
7897 | struct iscsi_init_ramrod_params { | |
7898 | struct iscsi_spe_func_init iscsi_init_spe; | |
7899 | struct tcp_init_params tcp_init; | |
7900 | }; | |
7901 | ||
7902 | struct ystorm_iscsi_conn_ag_ctx { | |
7903 | u8 byte0; | |
7904 | u8 byte1; | |
7905 | u8 flags0; | |
7906 | #define YSTORM_ISCSI_CONN_AG_CTX_BIT0_MASK 0x1 | |
7907 | #define YSTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT 0 | |
7908 | #define YSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1 | |
7909 | #define YSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1 | |
7910 | #define YSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3 | |
7911 | #define YSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 2 | |
7912 | #define YSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3 | |
7913 | #define YSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 4 | |
7914 | #define YSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3 | |
7915 | #define YSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 6 | |
7916 | u8 flags1; | |
7917 | #define YSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1 | |
7918 | #define YSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 0 | |
7919 | #define YSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1 | |
7920 | #define YSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 1 | |
7921 | #define YSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1 | |
7922 | #define YSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 2 | |
7923 | #define YSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1 | |
7924 | #define YSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 3 | |
7925 | #define YSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1 | |
7926 | #define YSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 4 | |
7927 | #define YSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1 | |
7928 | #define YSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 5 | |
7929 | #define YSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1 | |
7930 | #define YSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 6 | |
7931 | #define YSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1 | |
7932 | #define YSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 7 | |
7933 | u8 byte2; | |
7934 | u8 byte3; | |
7935 | __le16 word0; | |
7936 | __le32 reg0; | |
7937 | __le32 reg1; | |
7938 | __le16 word1; | |
7939 | __le16 word2; | |
7940 | __le16 word3; | |
7941 | __le16 word4; | |
7942 | __le32 reg2; | |
7943 | __le32 reg3; | |
7944 | }; | |
c965db44 TT |
7945 | |
7946 | #define MFW_TRACE_SIGNATURE 0x25071946 | |
7947 | ||
7948 | /* The trace in the buffer */ | |
7949 | #define MFW_TRACE_EVENTID_MASK 0x00ffff | |
7950 | #define MFW_TRACE_PRM_SIZE_MASK 0x0f0000 | |
7951 | #define MFW_TRACE_PRM_SIZE_SHIFT 16 | |
7952 | #define MFW_TRACE_ENTRY_SIZE 3 | |
7953 | ||
7954 | struct mcp_trace { | |
7955 | u32 signature; /* Help to identify that the trace is valid */ | |
7956 | u32 size; /* the size of the trace buffer in bytes */ | |
7957 | u32 curr_level; /* 2 - all will be written to the buffer | |
7958 | * 1 - debug trace will not be written | |
7959 | * 0 - just errors will be written to the buffer | |
7960 | */ | |
7961 | u32 modules_mask[2]; /* a bit per module, 1 means write it, 0 means | |
7962 | * mask it. | |
7963 | */ | |
7964 | ||
7965 | /* Warning: the following pointers are assumed to be 32bits as they are | |
7966 | * used only in the MFW. | |
7967 | */ | |
7968 | u32 trace_prod; /* The next trace will be written to this offset */ | |
7969 | u32 trace_oldest; /* The oldest valid trace starts at this offset | |
7970 | * (usually very close after the current producer). | |
7971 | */ | |
7972 | }; | |
7973 | ||
351a4ded | 7974 | #define VF_MAX_STATIC 192 |
fe56b9e6 | 7975 | |
351a4ded YM |
7976 | #define MCP_GLOB_PATH_MAX 2 |
7977 | #define MCP_PORT_MAX 2 | |
7978 | #define MCP_GLOB_PORT_MAX 4 | |
7979 | #define MCP_GLOB_FUNC_MAX 16 | |
fe56b9e6 | 7980 | |
c965db44 | 7981 | typedef u32 offsize_t; /* In DWORDS !!! */ |
fe56b9e6 | 7982 | /* Offset from the beginning of the MCP scratchpad */ |
351a4ded YM |
7983 | #define OFFSIZE_OFFSET_SHIFT 0 |
7984 | #define OFFSIZE_OFFSET_MASK 0x0000ffff | |
fe56b9e6 | 7985 | /* Size of specific element (not the whole array if any) */ |
351a4ded YM |
7986 | #define OFFSIZE_SIZE_SHIFT 16 |
7987 | #define OFFSIZE_SIZE_MASK 0xffff0000 | |
fe56b9e6 | 7988 | |
351a4ded YM |
7989 | #define SECTION_OFFSET(_offsize) ((((_offsize & \ |
7990 | OFFSIZE_OFFSET_MASK) >> \ | |
7991 | OFFSIZE_OFFSET_SHIFT) << 2)) | |
fe56b9e6 | 7992 | |
351a4ded YM |
7993 | #define QED_SECTION_SIZE(_offsize) (((_offsize & \ |
7994 | OFFSIZE_SIZE_MASK) >> \ | |
7995 | OFFSIZE_SIZE_SHIFT) << 2) | |
fe56b9e6 | 7996 | |
351a4ded YM |
7997 | #define SECTION_ADDR(_offsize, idx) (MCP_REG_SCRATCH + \ |
7998 | SECTION_OFFSET(_offsize) + \ | |
7999 | (QED_SECTION_SIZE(_offsize) * idx)) | |
8000 | ||
8001 | #define SECTION_OFFSIZE_ADDR(_pub_base, _section) \ | |
8002 | (_pub_base + offsetof(struct mcp_public_data, sections[_section])) | |
fe56b9e6 | 8003 | |
fe56b9e6 | 8004 | /* PHY configuration */ |
351a4ded YM |
8005 | struct eth_phy_cfg { |
8006 | u32 speed; | |
8007 | #define ETH_SPEED_AUTONEG 0 | |
8008 | #define ETH_SPEED_SMARTLINQ 0x8 | |
8009 | ||
8010 | u32 pause; | |
8011 | #define ETH_PAUSE_NONE 0x0 | |
8012 | #define ETH_PAUSE_AUTONEG 0x1 | |
8013 | #define ETH_PAUSE_RX 0x2 | |
8014 | #define ETH_PAUSE_TX 0x4 | |
8015 | ||
8016 | u32 adv_speed; | |
8017 | u32 loopback_mode; | |
8018 | #define ETH_LOOPBACK_NONE (0) | |
8019 | #define ETH_LOOPBACK_INT_PHY (1) | |
8020 | #define ETH_LOOPBACK_EXT_PHY (2) | |
8021 | #define ETH_LOOPBACK_EXT (3) | |
8022 | #define ETH_LOOPBACK_MAC (4) | |
8023 | ||
fe56b9e6 | 8024 | u32 feature_config_flags; |
351a4ded | 8025 | #define ETH_EEE_MODE_ADV_LPI (1 << 0) |
fe56b9e6 YM |
8026 | }; |
8027 | ||
8028 | struct port_mf_cfg { | |
351a4ded YM |
8029 | u32 dynamic_cfg; |
8030 | #define PORT_MF_CFG_OV_TAG_MASK 0x0000ffff | |
8031 | #define PORT_MF_CFG_OV_TAG_SHIFT 0 | |
8032 | #define PORT_MF_CFG_OV_TAG_DEFAULT PORT_MF_CFG_OV_TAG_MASK | |
8033 | ||
8034 | u32 reserved[1]; | |
8035 | }; | |
8036 | ||
8037 | struct eth_stats { | |
8038 | u64 r64; | |
8039 | u64 r127; | |
8040 | u64 r255; | |
8041 | u64 r511; | |
8042 | u64 r1023; | |
8043 | u64 r1518; | |
8044 | u64 r1522; | |
8045 | u64 r2047; | |
8046 | u64 r4095; | |
8047 | u64 r9216; | |
8048 | u64 r16383; | |
8049 | u64 rfcs; | |
8050 | u64 rxcf; | |
8051 | u64 rxpf; | |
8052 | u64 rxpp; | |
8053 | u64 raln; | |
8054 | u64 rfcr; | |
8055 | u64 rovr; | |
8056 | u64 rjbr; | |
8057 | u64 rund; | |
8058 | u64 rfrg; | |
8059 | u64 t64; | |
8060 | u64 t127; | |
8061 | u64 t255; | |
8062 | u64 t511; | |
8063 | u64 t1023; | |
8064 | u64 t1518; | |
8065 | u64 t2047; | |
8066 | u64 t4095; | |
8067 | u64 t9216; | |
8068 | u64 t16383; | |
8069 | u64 txpf; | |
8070 | u64 txpp; | |
8071 | u64 tlpiec; | |
8072 | u64 tncl; | |
8073 | u64 rbyte; | |
8074 | u64 rxuca; | |
8075 | u64 rxmca; | |
8076 | u64 rxbca; | |
8077 | u64 rxpok; | |
8078 | u64 tbyte; | |
8079 | u64 txuca; | |
8080 | u64 txmca; | |
8081 | u64 txbca; | |
8082 | u64 txcf; | |
fe56b9e6 YM |
8083 | }; |
8084 | ||
8085 | struct brb_stats { | |
351a4ded YM |
8086 | u64 brb_truncate[8]; |
8087 | u64 brb_discard[8]; | |
fe56b9e6 YM |
8088 | }; |
8089 | ||
8090 | struct port_stats { | |
351a4ded YM |
8091 | struct brb_stats brb; |
8092 | struct eth_stats eth; | |
fe56b9e6 YM |
8093 | }; |
8094 | ||
fe56b9e6 YM |
8095 | struct couple_mode_teaming { |
8096 | u8 port_cmt[MCP_GLOB_PORT_MAX]; | |
351a4ded | 8097 | #define PORT_CMT_IN_TEAM (1 << 0) |
fe56b9e6 | 8098 | |
351a4ded YM |
8099 | #define PORT_CMT_PORT_ROLE (1 << 1) |
8100 | #define PORT_CMT_PORT_INACTIVE (0 << 1) | |
8101 | #define PORT_CMT_PORT_ACTIVE (1 << 1) | |
fe56b9e6 | 8102 | |
351a4ded YM |
8103 | #define PORT_CMT_TEAM_MASK (1 << 2) |
8104 | #define PORT_CMT_TEAM0 (0 << 2) | |
8105 | #define PORT_CMT_TEAM1 (1 << 2) | |
fe56b9e6 YM |
8106 | }; |
8107 | ||
351a4ded YM |
8108 | #define LLDP_CHASSIS_ID_STAT_LEN 4 |
8109 | #define LLDP_PORT_ID_STAT_LEN 4 | |
8110 | #define DCBX_MAX_APP_PROTOCOL 32 | |
8111 | #define MAX_SYSTEM_LLDP_TLV_DATA 32 | |
fe56b9e6 | 8112 | |
351a4ded | 8113 | enum _lldp_agent { |
fe56b9e6 YM |
8114 | LLDP_NEAREST_BRIDGE = 0, |
8115 | LLDP_NEAREST_NON_TPMR_BRIDGE, | |
8116 | LLDP_NEAREST_CUSTOMER_BRIDGE, | |
8117 | LLDP_MAX_LLDP_AGENTS | |
8118 | }; | |
8119 | ||
8120 | struct lldp_config_params_s { | |
8121 | u32 config; | |
351a4ded YM |
8122 | #define LLDP_CONFIG_TX_INTERVAL_MASK 0x000000ff |
8123 | #define LLDP_CONFIG_TX_INTERVAL_SHIFT 0 | |
8124 | #define LLDP_CONFIG_HOLD_MASK 0x00000f00 | |
8125 | #define LLDP_CONFIG_HOLD_SHIFT 8 | |
8126 | #define LLDP_CONFIG_MAX_CREDIT_MASK 0x0000f000 | |
8127 | #define LLDP_CONFIG_MAX_CREDIT_SHIFT 12 | |
8128 | #define LLDP_CONFIG_ENABLE_RX_MASK 0x40000000 | |
8129 | #define LLDP_CONFIG_ENABLE_RX_SHIFT 30 | |
8130 | #define LLDP_CONFIG_ENABLE_TX_MASK 0x80000000 | |
8131 | #define LLDP_CONFIG_ENABLE_TX_SHIFT 31 | |
8132 | u32 local_chassis_id[LLDP_CHASSIS_ID_STAT_LEN]; | |
8133 | u32 local_port_id[LLDP_PORT_ID_STAT_LEN]; | |
fe56b9e6 YM |
8134 | }; |
8135 | ||
8136 | struct lldp_status_params_s { | |
351a4ded YM |
8137 | u32 prefix_seq_num; |
8138 | u32 status; | |
8139 | u32 peer_chassis_id[LLDP_CHASSIS_ID_STAT_LEN]; | |
8140 | u32 peer_port_id[LLDP_PORT_ID_STAT_LEN]; | |
8141 | u32 suffix_seq_num; | |
fe56b9e6 YM |
8142 | }; |
8143 | ||
8144 | struct dcbx_ets_feature { | |
8145 | u32 flags; | |
351a4ded YM |
8146 | #define DCBX_ETS_ENABLED_MASK 0x00000001 |
8147 | #define DCBX_ETS_ENABLED_SHIFT 0 | |
8148 | #define DCBX_ETS_WILLING_MASK 0x00000002 | |
8149 | #define DCBX_ETS_WILLING_SHIFT 1 | |
8150 | #define DCBX_ETS_ERROR_MASK 0x00000004 | |
8151 | #define DCBX_ETS_ERROR_SHIFT 2 | |
8152 | #define DCBX_ETS_CBS_MASK 0x00000008 | |
8153 | #define DCBX_ETS_CBS_SHIFT 3 | |
8154 | #define DCBX_ETS_MAX_TCS_MASK 0x000000f0 | |
8155 | #define DCBX_ETS_MAX_TCS_SHIFT 4 | |
8156 | #define DCBX_ISCSI_OOO_TC_MASK 0x00000f00 | |
8157 | #define DCBX_ISCSI_OOO_TC_SHIFT 8 | |
8158 | u32 pri_tc_tbl[1]; | |
8159 | #define DCBX_ISCSI_OOO_TC (4) | |
8160 | ||
8161 | #define NIG_ETS_ISCSI_OOO_CLIENT_OFFSET (DCBX_ISCSI_OOO_TC + 1) | |
8162 | #define DCBX_CEE_STRICT_PRIORITY 0xf | |
8163 | u32 tc_bw_tbl[2]; | |
8164 | u32 tc_tsa_tbl[2]; | |
8165 | #define DCBX_ETS_TSA_STRICT 0 | |
8166 | #define DCBX_ETS_TSA_CBS 1 | |
8167 | #define DCBX_ETS_TSA_ETS 2 | |
fe56b9e6 YM |
8168 | }; |
8169 | ||
8170 | struct dcbx_app_priority_entry { | |
8171 | u32 entry; | |
351a4ded YM |
8172 | #define DCBX_APP_PRI_MAP_MASK 0x000000ff |
8173 | #define DCBX_APP_PRI_MAP_SHIFT 0 | |
8174 | #define DCBX_APP_PRI_0 0x01 | |
8175 | #define DCBX_APP_PRI_1 0x02 | |
8176 | #define DCBX_APP_PRI_2 0x04 | |
8177 | #define DCBX_APP_PRI_3 0x08 | |
8178 | #define DCBX_APP_PRI_4 0x10 | |
8179 | #define DCBX_APP_PRI_5 0x20 | |
8180 | #define DCBX_APP_PRI_6 0x40 | |
8181 | #define DCBX_APP_PRI_7 0x80 | |
8182 | #define DCBX_APP_SF_MASK 0x00000300 | |
8183 | #define DCBX_APP_SF_SHIFT 8 | |
8184 | #define DCBX_APP_SF_ETHTYPE 0 | |
8185 | #define DCBX_APP_SF_PORT 1 | |
fb9ea8a9 SRK |
8186 | #define DCBX_APP_SF_IEEE_MASK 0x0000f000 |
8187 | #define DCBX_APP_SF_IEEE_SHIFT 12 | |
8188 | #define DCBX_APP_SF_IEEE_RESERVED 0 | |
8189 | #define DCBX_APP_SF_IEEE_ETHTYPE 1 | |
8190 | #define DCBX_APP_SF_IEEE_TCP_PORT 2 | |
8191 | #define DCBX_APP_SF_IEEE_UDP_PORT 3 | |
8192 | #define DCBX_APP_SF_IEEE_TCP_UDP_PORT 4 | |
8193 | ||
351a4ded YM |
8194 | #define DCBX_APP_PROTOCOL_ID_MASK 0xffff0000 |
8195 | #define DCBX_APP_PROTOCOL_ID_SHIFT 16 | |
8196 | }; | |
8197 | ||
fe56b9e6 YM |
8198 | struct dcbx_app_priority_feature { |
8199 | u32 flags; | |
351a4ded YM |
8200 | #define DCBX_APP_ENABLED_MASK 0x00000001 |
8201 | #define DCBX_APP_ENABLED_SHIFT 0 | |
8202 | #define DCBX_APP_WILLING_MASK 0x00000002 | |
8203 | #define DCBX_APP_WILLING_SHIFT 1 | |
8204 | #define DCBX_APP_ERROR_MASK 0x00000004 | |
8205 | #define DCBX_APP_ERROR_SHIFT 2 | |
8206 | #define DCBX_APP_MAX_TCS_MASK 0x0000f000 | |
8207 | #define DCBX_APP_MAX_TCS_SHIFT 12 | |
8208 | #define DCBX_APP_NUM_ENTRIES_MASK 0x00ff0000 | |
8209 | #define DCBX_APP_NUM_ENTRIES_SHIFT 16 | |
fe56b9e6 YM |
8210 | struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL]; |
8211 | }; | |
8212 | ||
fe56b9e6 | 8213 | struct dcbx_features { |
fe56b9e6 | 8214 | struct dcbx_ets_feature ets; |
351a4ded YM |
8215 | u32 pfc; |
8216 | #define DCBX_PFC_PRI_EN_BITMAP_MASK 0x000000ff | |
8217 | #define DCBX_PFC_PRI_EN_BITMAP_SHIFT 0 | |
8218 | #define DCBX_PFC_PRI_EN_BITMAP_PRI_0 0x01 | |
8219 | #define DCBX_PFC_PRI_EN_BITMAP_PRI_1 0x02 | |
8220 | #define DCBX_PFC_PRI_EN_BITMAP_PRI_2 0x04 | |
8221 | #define DCBX_PFC_PRI_EN_BITMAP_PRI_3 0x08 | |
8222 | #define DCBX_PFC_PRI_EN_BITMAP_PRI_4 0x10 | |
8223 | #define DCBX_PFC_PRI_EN_BITMAP_PRI_5 0x20 | |
8224 | #define DCBX_PFC_PRI_EN_BITMAP_PRI_6 0x40 | |
8225 | #define DCBX_PFC_PRI_EN_BITMAP_PRI_7 0x80 | |
8226 | ||
8227 | #define DCBX_PFC_FLAGS_MASK 0x0000ff00 | |
8228 | #define DCBX_PFC_FLAGS_SHIFT 8 | |
8229 | #define DCBX_PFC_CAPS_MASK 0x00000f00 | |
8230 | #define DCBX_PFC_CAPS_SHIFT 8 | |
8231 | #define DCBX_PFC_MBC_MASK 0x00004000 | |
8232 | #define DCBX_PFC_MBC_SHIFT 14 | |
8233 | #define DCBX_PFC_WILLING_MASK 0x00008000 | |
8234 | #define DCBX_PFC_WILLING_SHIFT 15 | |
8235 | #define DCBX_PFC_ENABLED_MASK 0x00010000 | |
8236 | #define DCBX_PFC_ENABLED_SHIFT 16 | |
8237 | #define DCBX_PFC_ERROR_MASK 0x00020000 | |
8238 | #define DCBX_PFC_ERROR_SHIFT 17 | |
fe56b9e6 | 8239 | |
fe56b9e6 YM |
8240 | struct dcbx_app_priority_feature app; |
8241 | }; | |
8242 | ||
8243 | struct dcbx_local_params { | |
8244 | u32 config; | |
351a4ded YM |
8245 | #define DCBX_CONFIG_VERSION_MASK 0x00000007 |
8246 | #define DCBX_CONFIG_VERSION_SHIFT 0 | |
8247 | #define DCBX_CONFIG_VERSION_DISABLED 0 | |
8248 | #define DCBX_CONFIG_VERSION_IEEE 1 | |
8249 | #define DCBX_CONFIG_VERSION_CEE 2 | |
8250 | #define DCBX_CONFIG_VERSION_STATIC 4 | |
fe56b9e6 | 8251 | |
351a4ded YM |
8252 | u32 flags; |
8253 | struct dcbx_features features; | |
fe56b9e6 YM |
8254 | }; |
8255 | ||
8256 | struct dcbx_mib { | |
351a4ded YM |
8257 | u32 prefix_seq_num; |
8258 | u32 flags; | |
8259 | struct dcbx_features features; | |
8260 | u32 suffix_seq_num; | |
fe56b9e6 YM |
8261 | }; |
8262 | ||
8263 | struct lldp_system_tlvs_buffer_s { | |
351a4ded YM |
8264 | u16 valid; |
8265 | u16 length; | |
8266 | u32 data[MAX_SYSTEM_LLDP_TLV_DATA]; | |
fe56b9e6 YM |
8267 | }; |
8268 | ||
351a4ded YM |
8269 | struct dcb_dscp_map { |
8270 | u32 flags; | |
8271 | #define DCB_DSCP_ENABLE_MASK 0x1 | |
8272 | #define DCB_DSCP_ENABLE_SHIFT 0 | |
8273 | #define DCB_DSCP_ENABLE 1 | |
8274 | u32 dscp_pri_map[8]; | |
fe56b9e6 YM |
8275 | }; |
8276 | ||
351a4ded YM |
8277 | struct public_global { |
8278 | u32 max_path; | |
8279 | u32 max_ports; | |
8280 | u32 debug_mb_offset; | |
8281 | u32 phymod_dbg_mb_offset; | |
8282 | struct couple_mode_teaming cmt; | |
8283 | s32 internal_temperature; | |
8284 | u32 mfw_ver; | |
8285 | u32 running_bundle_id; | |
8286 | s32 external_temperature; | |
8287 | u32 mdump_reason; | |
8288 | }; | |
fe56b9e6 | 8289 | |
fe56b9e6 | 8290 | struct fw_flr_mb { |
351a4ded YM |
8291 | u32 aggint; |
8292 | u32 opgen_addr; | |
8293 | u32 accum_ack; | |
fe56b9e6 YM |
8294 | }; |
8295 | ||
8296 | struct public_path { | |
351a4ded YM |
8297 | struct fw_flr_mb flr_mb; |
8298 | u32 mcp_vf_disabled[VF_MAX_STATIC / 32]; | |
8299 | ||
8300 | u32 process_kill; | |
8301 | #define PROCESS_KILL_COUNTER_MASK 0x0000ffff | |
8302 | #define PROCESS_KILL_COUNTER_SHIFT 0 | |
8303 | #define PROCESS_KILL_GLOB_AEU_BIT_MASK 0xffff0000 | |
8304 | #define PROCESS_KILL_GLOB_AEU_BIT_SHIFT 16 | |
fe56b9e6 YM |
8305 | #define GLOBAL_AEU_BIT(aeu_reg_id, aeu_bit) (aeu_reg_id * 32 + aeu_bit) |
8306 | }; | |
8307 | ||
fe56b9e6 | 8308 | struct public_port { |
351a4ded | 8309 | u32 validity_map; |
fe56b9e6 YM |
8310 | |
8311 | u32 link_status; | |
351a4ded YM |
8312 | #define LINK_STATUS_LINK_UP 0x00000001 |
8313 | #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001e | |
8314 | #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (1 << 1) | |
8315 | #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (2 << 1) | |
8316 | #define LINK_STATUS_SPEED_AND_DUPLEX_10G (3 << 1) | |
8317 | #define LINK_STATUS_SPEED_AND_DUPLEX_20G (4 << 1) | |
8318 | #define LINK_STATUS_SPEED_AND_DUPLEX_40G (5 << 1) | |
8319 | #define LINK_STATUS_SPEED_AND_DUPLEX_50G (6 << 1) | |
8320 | #define LINK_STATUS_SPEED_AND_DUPLEX_100G (7 << 1) | |
8321 | #define LINK_STATUS_SPEED_AND_DUPLEX_25G (8 << 1) | |
8322 | ||
8323 | #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020 | |
8324 | ||
8325 | #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040 | |
8326 | #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080 | |
8327 | ||
8328 | #define LINK_STATUS_PFC_ENABLED 0x00000100 | |
8329 | #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200 | |
8330 | #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400 | |
8331 | #define LINK_STATUS_LINK_PARTNER_10G_CAPABLE 0x00000800 | |
8332 | #define LINK_STATUS_LINK_PARTNER_20G_CAPABLE 0x00001000 | |
8333 | #define LINK_STATUS_LINK_PARTNER_40G_CAPABLE 0x00002000 | |
8334 | #define LINK_STATUS_LINK_PARTNER_50G_CAPABLE 0x00004000 | |
8335 | #define LINK_STATUS_LINK_PARTNER_100G_CAPABLE 0x00008000 | |
8336 | #define LINK_STATUS_LINK_PARTNER_25G_CAPABLE 0x00010000 | |
8337 | ||
8338 | #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000 | |
8339 | #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0 << 18) | |
8340 | #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1 << 18) | |
8341 | #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2 << 18) | |
8342 | #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3 << 18) | |
8343 | ||
8344 | #define LINK_STATUS_SFP_TX_FAULT 0x00100000 | |
8345 | #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00200000 | |
8346 | #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00400000 | |
8347 | #define LINK_STATUS_RX_SIGNAL_PRESENT 0x00800000 | |
8348 | #define LINK_STATUS_MAC_LOCAL_FAULT 0x01000000 | |
8349 | #define LINK_STATUS_MAC_REMOTE_FAULT 0x02000000 | |
8350 | #define LINK_STATUS_UNSUPPORTED_SPD_REQ 0x04000000 | |
8351 | ||
8352 | u32 link_status1; | |
8353 | u32 ext_phy_fw_version; | |
8354 | u32 drv_phy_cfg_addr; | |
8355 | ||
8356 | u32 port_stx; | |
8357 | ||
8358 | u32 stat_nig_timer; | |
8359 | ||
8360 | struct port_mf_cfg port_mf_config; | |
8361 | struct port_stats stats; | |
8362 | ||
8363 | u32 media_type; | |
8364 | #define MEDIA_UNSPECIFIED 0x0 | |
8365 | #define MEDIA_SFPP_10G_FIBER 0x1 | |
8366 | #define MEDIA_XFP_FIBER 0x2 | |
8367 | #define MEDIA_DA_TWINAX 0x3 | |
8368 | #define MEDIA_BASE_T 0x4 | |
8369 | #define MEDIA_SFP_1G_FIBER 0x5 | |
8370 | #define MEDIA_MODULE_FIBER 0x6 | |
8371 | #define MEDIA_KR 0xf0 | |
8372 | #define MEDIA_NOT_PRESENT 0xff | |
fe56b9e6 YM |
8373 | |
8374 | u32 lfa_status; | |
351a4ded YM |
8375 | u32 link_change_count; |
8376 | ||
8377 | struct lldp_config_params_s lldp_config_params[LLDP_MAX_LLDP_AGENTS]; | |
8378 | struct lldp_status_params_s lldp_status_params[LLDP_MAX_LLDP_AGENTS]; | |
8379 | struct lldp_system_tlvs_buffer_s system_lldp_tlvs_buf; | |
fe56b9e6 YM |
8380 | |
8381 | /* DCBX related MIB */ | |
351a4ded YM |
8382 | struct dcbx_local_params local_admin_dcbx_mib; |
8383 | struct dcbx_mib remote_dcbx_mib; | |
8384 | struct dcbx_mib operational_dcbx_mib; | |
fc48b7a6 | 8385 | |
351a4ded YM |
8386 | u32 reserved[2]; |
8387 | u32 transceiver_data; | |
8388 | #define ETH_TRANSCEIVER_STATE_MASK 0x000000FF | |
8389 | #define ETH_TRANSCEIVER_STATE_SHIFT 0x00000000 | |
8390 | #define ETH_TRANSCEIVER_STATE_UNPLUGGED 0x00000000 | |
8391 | #define ETH_TRANSCEIVER_STATE_PRESENT 0x00000001 | |
8392 | #define ETH_TRANSCEIVER_STATE_VALID 0x00000003 | |
8393 | #define ETH_TRANSCEIVER_STATE_UPDATING 0x00000008 | |
fe56b9e6 | 8394 | |
351a4ded YM |
8395 | u32 wol_info; |
8396 | u32 wol_pkt_len; | |
8397 | u32 wol_pkt_details; | |
8398 | struct dcb_dscp_map dcb_dscp_map; | |
8399 | }; | |
fe56b9e6 YM |
8400 | |
8401 | struct public_func { | |
351a4ded | 8402 | u32 reserved0[2]; |
fe56b9e6 | 8403 | |
351a4ded YM |
8404 | u32 mtu_size; |
8405 | ||
8406 | u32 reserved[7]; | |
8407 | ||
8408 | u32 config; | |
8409 | #define FUNC_MF_CFG_FUNC_HIDE 0x00000001 | |
8410 | #define FUNC_MF_CFG_PAUSE_ON_HOST_RING 0x00000002 | |
8411 | #define FUNC_MF_CFG_PAUSE_ON_HOST_RING_SHIFT 0x00000001 | |
8412 | ||
8413 | #define FUNC_MF_CFG_PROTOCOL_MASK 0x000000f0 | |
8414 | #define FUNC_MF_CFG_PROTOCOL_SHIFT 4 | |
8415 | #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000000 | |
c5ac9319 YM |
8416 | #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000010 |
8417 | #define FUNC_MF_CFG_PROTOCOL_ROCE 0x00000030 | |
351a4ded YM |
8418 | #define FUNC_MF_CFG_PROTOCOL_MAX 0x00000030 |
8419 | ||
8420 | #define FUNC_MF_CFG_MIN_BW_MASK 0x0000ff00 | |
8421 | #define FUNC_MF_CFG_MIN_BW_SHIFT 8 | |
8422 | #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000 | |
8423 | #define FUNC_MF_CFG_MAX_BW_MASK 0x00ff0000 | |
8424 | #define FUNC_MF_CFG_MAX_BW_SHIFT 16 | |
8425 | #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x00640000 | |
8426 | ||
8427 | u32 status; | |
8428 | #define FUNC_STATUS_VLINK_DOWN 0x00000001 | |
8429 | ||
8430 | u32 mac_upper; | |
8431 | #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff | |
8432 | #define FUNC_MF_CFG_UPPERMAC_SHIFT 0 | |
8433 | #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK | |
8434 | u32 mac_lower; | |
8435 | #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff | |
8436 | ||
8437 | u32 fcoe_wwn_port_name_upper; | |
8438 | u32 fcoe_wwn_port_name_lower; | |
8439 | ||
8440 | u32 fcoe_wwn_node_name_upper; | |
8441 | u32 fcoe_wwn_node_name_lower; | |
8442 | ||
8443 | u32 ovlan_stag; | |
8444 | #define FUNC_MF_CFG_OV_STAG_MASK 0x0000ffff | |
8445 | #define FUNC_MF_CFG_OV_STAG_SHIFT 0 | |
8446 | #define FUNC_MF_CFG_OV_STAG_DEFAULT FUNC_MF_CFG_OV_STAG_MASK | |
8447 | ||
8448 | u32 pf_allocation; | |
8449 | ||
8450 | u32 preserve_data; | |
8451 | ||
8452 | u32 driver_last_activity_ts; | |
8453 | ||
8454 | u32 drv_ack_vf_disabled[VF_MAX_STATIC / 32]; | |
8455 | ||
8456 | u32 drv_id; | |
8457 | #define DRV_ID_PDA_COMP_VER_MASK 0x0000ffff | |
8458 | #define DRV_ID_PDA_COMP_VER_SHIFT 0 | |
8459 | ||
8460 | #define DRV_ID_MCP_HSI_VER_MASK 0x00ff0000 | |
8461 | #define DRV_ID_MCP_HSI_VER_SHIFT 16 | |
8462 | #define DRV_ID_MCP_HSI_VER_CURRENT (1 << DRV_ID_MCP_HSI_VER_SHIFT) | |
8463 | ||
8464 | #define DRV_ID_DRV_TYPE_MASK 0x7f000000 | |
8465 | #define DRV_ID_DRV_TYPE_SHIFT 24 | |
8466 | #define DRV_ID_DRV_TYPE_UNKNOWN (0 << DRV_ID_DRV_TYPE_SHIFT) | |
8467 | #define DRV_ID_DRV_TYPE_LINUX (1 << DRV_ID_DRV_TYPE_SHIFT) | |
8468 | ||
8469 | #define DRV_ID_DRV_INIT_HW_MASK 0x80000000 | |
8470 | #define DRV_ID_DRV_INIT_HW_SHIFT 31 | |
8471 | #define DRV_ID_DRV_INIT_HW_FLAG (1 << DRV_ID_DRV_INIT_HW_SHIFT) | |
8472 | }; | |
fe56b9e6 YM |
8473 | |
8474 | struct mcp_mac { | |
351a4ded YM |
8475 | u32 mac_upper; |
8476 | u32 mac_lower; | |
fe56b9e6 YM |
8477 | }; |
8478 | ||
8479 | struct mcp_val64 { | |
351a4ded YM |
8480 | u32 lo; |
8481 | u32 hi; | |
fe56b9e6 YM |
8482 | }; |
8483 | ||
8484 | struct mcp_file_att { | |
351a4ded YM |
8485 | u32 nvm_start_addr; |
8486 | u32 len; | |
8487 | }; | |
8488 | ||
8489 | struct bist_nvm_image_att { | |
8490 | u32 return_code; | |
8491 | u32 image_type; | |
8492 | u32 nvm_start_addr; | |
8493 | u32 len; | |
fe56b9e6 YM |
8494 | }; |
8495 | ||
8496 | #define MCP_DRV_VER_STR_SIZE 16 | |
8497 | #define MCP_DRV_VER_STR_SIZE_DWORD (MCP_DRV_VER_STR_SIZE / sizeof(u32)) | |
8498 | #define MCP_DRV_NVM_BUF_LEN 32 | |
8499 | struct drv_version_stc { | |
351a4ded YM |
8500 | u32 version; |
8501 | u8 name[MCP_DRV_VER_STR_SIZE - 4]; | |
8502 | }; | |
8503 | ||
8504 | struct lan_stats_stc { | |
8505 | u64 ucast_rx_pkts; | |
8506 | u64 ucast_tx_pkts; | |
8507 | u32 fcs_err; | |
8508 | u32 rserved; | |
8509 | }; | |
8510 | ||
8511 | struct ocbb_data_stc { | |
8512 | u32 ocbb_host_addr; | |
8513 | u32 ocsd_host_addr; | |
8514 | u32 ocsd_req_update_interval; | |
8515 | }; | |
8516 | ||
8517 | #define MAX_NUM_OF_SENSORS 7 | |
8518 | struct temperature_status_stc { | |
8519 | u32 num_of_sensors; | |
8520 | u32 sensor[MAX_NUM_OF_SENSORS]; | |
8521 | }; | |
8522 | ||
8523 | /* crash dump configuration header */ | |
8524 | struct mdump_config_stc { | |
8525 | u32 version; | |
8526 | u32 config; | |
8527 | u32 epoc; | |
8528 | u32 num_of_logs; | |
8529 | u32 valid_logs; | |
fe56b9e6 YM |
8530 | }; |
8531 | ||
8532 | union drv_union_data { | |
351a4ded YM |
8533 | u32 ver_str[MCP_DRV_VER_STR_SIZE_DWORD]; |
8534 | struct mcp_mac wol_mac; | |
8535 | ||
8536 | struct eth_phy_cfg drv_phy_cfg; | |
fe56b9e6 | 8537 | |
351a4ded | 8538 | struct mcp_val64 val64; |
fe56b9e6 | 8539 | |
351a4ded | 8540 | u8 raw_data[MCP_DRV_NVM_BUF_LEN]; |
fe56b9e6 | 8541 | |
351a4ded | 8542 | struct mcp_file_att file_att; |
fe56b9e6 | 8543 | |
351a4ded | 8544 | u32 ack_vf_disabled[VF_MAX_STATIC / 32]; |
fe56b9e6 | 8545 | |
351a4ded | 8546 | struct drv_version_stc drv_version; |
fe56b9e6 | 8547 | |
351a4ded YM |
8548 | struct lan_stats_stc lan_stats; |
8549 | u64 reserved_stats[11]; | |
8550 | struct ocbb_data_stc ocbb_info; | |
8551 | struct temperature_status_stc temp_info; | |
8552 | struct bist_nvm_image_att nvm_image_att; | |
8553 | struct mdump_config_stc mdump_config; | |
fe56b9e6 YM |
8554 | }; |
8555 | ||
8556 | struct public_drv_mb { | |
8557 | u32 drv_mb_header; | |
351a4ded YM |
8558 | #define DRV_MSG_CODE_MASK 0xffff0000 |
8559 | #define DRV_MSG_CODE_LOAD_REQ 0x10000000 | |
8560 | #define DRV_MSG_CODE_LOAD_DONE 0x11000000 | |
8561 | #define DRV_MSG_CODE_INIT_HW 0x12000000 | |
8562 | #define DRV_MSG_CODE_UNLOAD_REQ 0x20000000 | |
8563 | #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000 | |
8564 | #define DRV_MSG_CODE_INIT_PHY 0x22000000 | |
8565 | #define DRV_MSG_CODE_LINK_RESET 0x23000000 | |
8566 | #define DRV_MSG_CODE_SET_DCBX 0x25000000 | |
8567 | ||
4b01e519 | 8568 | #define DRV_MSG_CODE_BW_UPDATE_ACK 0x32000000 |
351a4ded YM |
8569 | #define DRV_MSG_CODE_NIG_DRAIN 0x30000000 |
8570 | #define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000 | |
8571 | #define DRV_MSG_CODE_CFG_VF_MSIX 0xc0010000 | |
c965db44 TT |
8572 | #define DRV_MSG_CODE_NVM_GET_FILE_ATT 0x00030000 |
8573 | #define DRV_MSG_CODE_NVM_READ_NVRAM 0x00050000 | |
351a4ded YM |
8574 | #define DRV_MSG_CODE_MCP_RESET 0x00090000 |
8575 | #define DRV_MSG_CODE_SET_VERSION 0x000f0000 | |
4102426f | 8576 | #define DRV_MSG_CODE_MCP_HALT 0x00100000 |
351a4ded | 8577 | |
6c754246 SRK |
8578 | #define DRV_MSG_CODE_GET_STATS 0x00130000 |
8579 | #define DRV_MSG_CODE_STATS_TYPE_LAN 1 | |
8580 | #define DRV_MSG_CODE_STATS_TYPE_FCOE 2 | |
8581 | #define DRV_MSG_CODE_STATS_TYPE_ISCSI 3 | |
8582 | #define DRV_MSG_CODE_STATS_TYPE_RDMA 4 | |
8583 | ||
4102426f TT |
8584 | #define DRV_MSG_CODE_MASK_PARITIES 0x001a0000 |
8585 | ||
351a4ded YM |
8586 | #define DRV_MSG_CODE_BIST_TEST 0x001e0000 |
8587 | #define DRV_MSG_CODE_SET_LED_MODE 0x00200000 | |
8588 | ||
8589 | #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff | |
fe56b9e6 YM |
8590 | |
8591 | u32 drv_mb_param; | |
351a4ded YM |
8592 | #define DRV_MB_PARAM_UNLOAD_WOL_MCP 0x00000001 |
8593 | #define DRV_MB_PARAM_DCBX_NOTIFY_MASK 0x000000FF | |
8594 | #define DRV_MB_PARAM_DCBX_NOTIFY_SHIFT 3 | |
c965db44 TT |
8595 | |
8596 | #define DRV_MB_PARAM_NVM_LEN_SHIFT 24 | |
8597 | ||
351a4ded YM |
8598 | #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT 0 |
8599 | #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK 0x000000FF | |
8600 | #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT 8 | |
8601 | #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK 0x0000FF00 | |
6ad8c632 SRK |
8602 | #define DRV_MB_PARAM_LLDP_SEND_MASK 0x00000001 |
8603 | #define DRV_MB_PARAM_LLDP_SEND_SHIFT 0 | |
8604 | ||
351a4ded YM |
8605 | |
8606 | #define DRV_MB_PARAM_SET_LED_MODE_OPER 0x0 | |
8607 | #define DRV_MB_PARAM_SET_LED_MODE_ON 0x1 | |
8608 | #define DRV_MB_PARAM_SET_LED_MODE_OFF 0x2 | |
fe56b9e6 | 8609 | |
351a4ded YM |
8610 | #define DRV_MB_PARAM_BIST_REGISTER_TEST 1 |
8611 | #define DRV_MB_PARAM_BIST_CLOCK_TEST 2 | |
8612 | ||
8613 | #define DRV_MB_PARAM_BIST_RC_UNKNOWN 0 | |
8614 | #define DRV_MB_PARAM_BIST_RC_PASSED 1 | |
8615 | #define DRV_MB_PARAM_BIST_RC_FAILED 2 | |
8616 | #define DRV_MB_PARAM_BIST_RC_INVALID_PARAMETER 3 | |
8617 | ||
8618 | #define DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT 0 | |
8619 | #define DRV_MB_PARAM_BIST_TEST_INDEX_MASK 0x000000FF | |
03dc76ca | 8620 | |
fe56b9e6 | 8621 | u32 fw_mb_header; |
351a4ded YM |
8622 | #define FW_MSG_CODE_MASK 0xffff0000 |
8623 | #define FW_MSG_CODE_DRV_LOAD_ENGINE 0x10100000 | |
8624 | #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000 | |
8625 | #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000 | |
8626 | #define FW_MSG_CODE_DRV_LOAD_REFUSED_PDA 0x10200000 | |
8627 | #define FW_MSG_CODE_DRV_LOAD_REFUSED_HSI 0x10210000 | |
8628 | #define FW_MSG_CODE_DRV_LOAD_REFUSED_DIAG 0x10220000 | |
8629 | #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000 | |
8630 | #define FW_MSG_CODE_DRV_UNLOAD_ENGINE 0x20110000 | |
8631 | #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20120000 | |
8632 | #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20130000 | |
8633 | #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000 | |
8634 | #define FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE 0xb0010000 | |
c965db44 TT |
8635 | |
8636 | #define FW_MSG_CODE_NVM_OK 0x00010000 | |
351a4ded YM |
8637 | #define FW_MSG_CODE_OK 0x00160000 |
8638 | ||
8639 | #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff | |
8640 | ||
8641 | u32 fw_mb_param; | |
8642 | ||
8643 | u32 drv_pulse_mb; | |
8644 | #define DRV_PULSE_SEQ_MASK 0x00007fff | |
8645 | #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000 | |
8646 | #define DRV_PULSE_ALWAYS_ALIVE 0x00008000 | |
8647 | ||
fe56b9e6 | 8648 | u32 mcp_pulse_mb; |
351a4ded YM |
8649 | #define MCP_PULSE_SEQ_MASK 0x00007fff |
8650 | #define MCP_PULSE_ALWAYS_ALIVE 0x00008000 | |
8651 | #define MCP_EVENT_MASK 0xffff0000 | |
8652 | #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000 | |
fe56b9e6 YM |
8653 | |
8654 | union drv_union_data union_data; | |
8655 | }; | |
8656 | ||
fe56b9e6 YM |
8657 | enum MFW_DRV_MSG_TYPE { |
8658 | MFW_DRV_MSG_LINK_CHANGE, | |
8659 | MFW_DRV_MSG_FLR_FW_ACK_FAILED, | |
8660 | MFW_DRV_MSG_VF_DISABLED, | |
8661 | MFW_DRV_MSG_LLDP_DATA_UPDATED, | |
8662 | MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED, | |
8663 | MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED, | |
351a4ded | 8664 | MFW_DRV_MSG_RESERVED4, |
334c03b5 | 8665 | MFW_DRV_MSG_BW_UPDATE, |
351a4ded | 8666 | MFW_DRV_MSG_BW_UPDATE5, |
6c754246 SRK |
8667 | MFW_DRV_MSG_GET_LAN_STATS, |
8668 | MFW_DRV_MSG_GET_FCOE_STATS, | |
8669 | MFW_DRV_MSG_GET_ISCSI_STATS, | |
8670 | MFW_DRV_MSG_GET_RDMA_STATS, | |
351a4ded | 8671 | MFW_DRV_MSG_BW_UPDATE10, |
334c03b5 | 8672 | MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE, |
351a4ded | 8673 | MFW_DRV_MSG_BW_UPDATE11, |
fe56b9e6 YM |
8674 | MFW_DRV_MSG_MAX |
8675 | }; | |
8676 | ||
351a4ded YM |
8677 | #define MFW_DRV_MSG_MAX_DWORDS(msgs) (((msgs - 1) >> 2) + 1) |
8678 | #define MFW_DRV_MSG_DWORD(msg_id) (msg_id >> 2) | |
8679 | #define MFW_DRV_MSG_OFFSET(msg_id) ((msg_id & 0x3) << 3) | |
8680 | #define MFW_DRV_MSG_MASK(msg_id) (0xff << MFW_DRV_MSG_OFFSET(msg_id)) | |
fe56b9e6 YM |
8681 | |
8682 | struct public_mfw_mb { | |
351a4ded YM |
8683 | u32 sup_msgs; |
8684 | u32 msg[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)]; | |
8685 | u32 ack[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)]; | |
fe56b9e6 YM |
8686 | }; |
8687 | ||
fe56b9e6 | 8688 | enum public_sections { |
351a4ded YM |
8689 | PUBLIC_DRV_MB, |
8690 | PUBLIC_MFW_MB, | |
fe56b9e6 YM |
8691 | PUBLIC_GLOBAL, |
8692 | PUBLIC_PATH, | |
8693 | PUBLIC_PORT, | |
8694 | PUBLIC_FUNC, | |
8695 | PUBLIC_MAX_SECTIONS | |
8696 | }; | |
8697 | ||
fe56b9e6 | 8698 | struct mcp_public_data { |
351a4ded YM |
8699 | u32 num_sections; |
8700 | u32 sections[PUBLIC_MAX_SECTIONS]; | |
8701 | struct public_drv_mb drv_mb[MCP_GLOB_FUNC_MAX]; | |
8702 | struct public_mfw_mb mfw_mb[MCP_GLOB_FUNC_MAX]; | |
8703 | struct public_global global; | |
8704 | struct public_path path[MCP_GLOB_PATH_MAX]; | |
8705 | struct public_port port[MCP_GLOB_PORT_MAX]; | |
8706 | struct public_func func[MCP_GLOB_FUNC_MAX]; | |
fe56b9e6 YM |
8707 | }; |
8708 | ||
8709 | struct nvm_cfg_mac_address { | |
351a4ded YM |
8710 | u32 mac_addr_hi; |
8711 | #define NVM_CFG_MAC_ADDRESS_HI_MASK 0x0000FFFF | |
8712 | #define NVM_CFG_MAC_ADDRESS_HI_OFFSET 0 | |
8713 | u32 mac_addr_lo; | |
fe56b9e6 YM |
8714 | }; |
8715 | ||
fe56b9e6 | 8716 | struct nvm_cfg1_glob { |
351a4ded YM |
8717 | u32 generic_cont0; |
8718 | #define NVM_CFG1_GLOB_MF_MODE_MASK 0x00000FF0 | |
8719 | #define NVM_CFG1_GLOB_MF_MODE_OFFSET 4 | |
8720 | #define NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED 0x0 | |
8721 | #define NVM_CFG1_GLOB_MF_MODE_DEFAULT 0x1 | |
8722 | #define NVM_CFG1_GLOB_MF_MODE_SPIO4 0x2 | |
8723 | #define NVM_CFG1_GLOB_MF_MODE_NPAR1_0 0x3 | |
8724 | #define NVM_CFG1_GLOB_MF_MODE_NPAR1_5 0x4 | |
8725 | #define NVM_CFG1_GLOB_MF_MODE_NPAR2_0 0x5 | |
8726 | #define NVM_CFG1_GLOB_MF_MODE_BD 0x6 | |
8727 | #define NVM_CFG1_GLOB_MF_MODE_UFP 0x7 | |
8728 | u32 engineering_change[3]; | |
8729 | u32 manufacturing_id; | |
8730 | u32 serial_number[4]; | |
8731 | u32 pcie_cfg; | |
8732 | u32 mgmt_traffic; | |
8733 | u32 core_cfg; | |
8734 | #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK 0x000000FF | |
8735 | #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET 0 | |
8736 | #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G 0x0 | |
8737 | #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G 0x1 | |
8738 | #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G 0x2 | |
8739 | #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F 0x3 | |
8740 | #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E 0x4 | |
8741 | #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G 0x5 | |
8742 | #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G 0xB | |
8743 | #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G 0xC | |
8744 | #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G 0xD | |
8745 | #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G 0xE | |
8746 | u32 e_lane_cfg1; | |
8747 | u32 e_lane_cfg2; | |
8748 | u32 f_lane_cfg1; | |
8749 | u32 f_lane_cfg2; | |
8750 | u32 mps10_preemphasis; | |
8751 | u32 mps10_driver_current; | |
8752 | u32 mps25_preemphasis; | |
8753 | u32 mps25_driver_current; | |
8754 | u32 pci_id; | |
8755 | u32 pci_subsys_id; | |
8756 | u32 bar; | |
8757 | u32 mps10_txfir_main; | |
8758 | u32 mps10_txfir_post; | |
8759 | u32 mps25_txfir_main; | |
8760 | u32 mps25_txfir_post; | |
8761 | u32 manufacture_ver; | |
8762 | u32 manufacture_time; | |
8763 | u32 led_global_settings; | |
8764 | u32 generic_cont1; | |
8765 | u32 mbi_version; | |
8766 | u32 mbi_date; | |
8767 | u32 misc_sig; | |
8768 | u32 device_capabilities; | |
8769 | #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET 0x1 | |
c5ac9319 YM |
8770 | #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI 0x4 |
8771 | #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE 0x8 | |
351a4ded YM |
8772 | u32 power_dissipated; |
8773 | u32 power_consumed; | |
8774 | u32 efi_version; | |
8775 | u32 multi_network_modes_capability; | |
8776 | u32 reserved[41]; | |
fe56b9e6 YM |
8777 | }; |
8778 | ||
8779 | struct nvm_cfg1_path { | |
351a4ded | 8780 | u32 reserved[30]; |
fe56b9e6 YM |
8781 | }; |
8782 | ||
8783 | struct nvm_cfg1_port { | |
351a4ded YM |
8784 | u32 reserved__m_relocated_to_option_123; |
8785 | u32 reserved__m_relocated_to_option_124; | |
8786 | u32 generic_cont0; | |
8787 | #define NVM_CFG1_PORT_DCBX_MODE_MASK 0x000F0000 | |
8788 | #define NVM_CFG1_PORT_DCBX_MODE_OFFSET 16 | |
8789 | #define NVM_CFG1_PORT_DCBX_MODE_DISABLED 0x0 | |
8790 | #define NVM_CFG1_PORT_DCBX_MODE_IEEE 0x1 | |
8791 | #define NVM_CFG1_PORT_DCBX_MODE_CEE 0x2 | |
8792 | #define NVM_CFG1_PORT_DCBX_MODE_DYNAMIC 0x3 | |
8793 | #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_MASK 0x00F00000 | |
8794 | #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_OFFSET 20 | |
8795 | #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ETHERNET 0x1 | |
8796 | #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_FCOE 0x2 | |
8797 | #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ISCSI 0x4 | |
8798 | u32 pcie_cfg; | |
8799 | u32 features; | |
8800 | u32 speed_cap_mask; | |
8801 | #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK 0x0000FFFF | |
8802 | #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_OFFSET 0 | |
8803 | #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G 0x1 | |
8804 | #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G 0x2 | |
8805 | #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G 0x8 | |
8806 | #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G 0x10 | |
8807 | #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G 0x20 | |
8808 | #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40 | |
8809 | u32 link_settings; | |
8810 | #define NVM_CFG1_PORT_DRV_LINK_SPEED_MASK 0x0000000F | |
8811 | #define NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET 0 | |
8812 | #define NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG 0x0 | |
8813 | #define NVM_CFG1_PORT_DRV_LINK_SPEED_1G 0x1 | |
8814 | #define NVM_CFG1_PORT_DRV_LINK_SPEED_10G 0x2 | |
8815 | #define NVM_CFG1_PORT_DRV_LINK_SPEED_25G 0x4 | |
8816 | #define NVM_CFG1_PORT_DRV_LINK_SPEED_40G 0x5 | |
8817 | #define NVM_CFG1_PORT_DRV_LINK_SPEED_50G 0x6 | |
8818 | #define NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G 0x7 | |
8819 | #define NVM_CFG1_PORT_DRV_LINK_SPEED_SMARTLINQ 0x8 | |
8820 | #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK 0x00000070 | |
8821 | #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET 4 | |
8822 | #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG 0x1 | |
8823 | #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX 0x2 | |
8824 | #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX 0x4 | |
8825 | u32 phy_cfg; | |
8826 | u32 mgmt_traffic; | |
8827 | u32 ext_phy; | |
8828 | u32 mba_cfg1; | |
8829 | u32 mba_cfg2; | |
8830 | u32 vf_cfg; | |
8831 | struct nvm_cfg_mac_address lldp_mac_address; | |
8832 | u32 led_port_settings; | |
8833 | u32 transceiver_00; | |
8834 | u32 device_ids; | |
8835 | u32 board_cfg; | |
8836 | u32 mnm_10g_cap; | |
8837 | u32 mnm_10g_ctrl; | |
8838 | u32 mnm_10g_misc; | |
8839 | u32 mnm_25g_cap; | |
8840 | u32 mnm_25g_ctrl; | |
8841 | u32 mnm_25g_misc; | |
8842 | u32 mnm_40g_cap; | |
8843 | u32 mnm_40g_ctrl; | |
8844 | u32 mnm_40g_misc; | |
8845 | u32 mnm_50g_cap; | |
8846 | u32 mnm_50g_ctrl; | |
8847 | u32 mnm_50g_misc; | |
8848 | u32 mnm_100g_cap; | |
8849 | u32 mnm_100g_ctrl; | |
8850 | u32 mnm_100g_misc; | |
8851 | u32 reserved[116]; | |
fe56b9e6 YM |
8852 | }; |
8853 | ||
8854 | struct nvm_cfg1_func { | |
351a4ded YM |
8855 | struct nvm_cfg_mac_address mac_address; |
8856 | u32 rsrv1; | |
8857 | u32 rsrv2; | |
8858 | u32 device_id; | |
8859 | u32 cmn_cfg; | |
8860 | u32 pci_cfg; | |
8861 | struct nvm_cfg_mac_address fcoe_node_wwn_mac_addr; | |
8862 | struct nvm_cfg_mac_address fcoe_port_wwn_mac_addr; | |
8863 | u32 preboot_generic_cfg; | |
8864 | u32 reserved[8]; | |
fe56b9e6 YM |
8865 | }; |
8866 | ||
8867 | struct nvm_cfg1 { | |
351a4ded YM |
8868 | struct nvm_cfg1_glob glob; |
8869 | struct nvm_cfg1_path path[MCP_GLOB_PATH_MAX]; | |
8870 | struct nvm_cfg1_port port[MCP_GLOB_PORT_MAX]; | |
8871 | struct nvm_cfg1_func func[MCP_GLOB_FUNC_MAX]; | |
fe56b9e6 | 8872 | }; |
c965db44 TT |
8873 | |
8874 | enum spad_sections { | |
8875 | SPAD_SECTION_TRACE, | |
8876 | SPAD_SECTION_NVM_CFG, | |
8877 | SPAD_SECTION_PUBLIC, | |
8878 | SPAD_SECTION_PRIVATE, | |
8879 | SPAD_SECTION_MAX | |
8880 | }; | |
8881 | ||
8882 | #define MCP_TRACE_SIZE 2048 /* 2kb */ | |
8883 | ||
8884 | /* This section is located at a fixed location in the beginning of the | |
8885 | * scratchpad, to ensure that the MCP trace is not run over during MFW upgrade. | |
8886 | * All the rest of data has a floating location which differs from version to | |
8887 | * version, and is pointed by the mcp_meta_data below. | |
8888 | * Moreover, the spad_layout section is part of the MFW firmware, and is loaded | |
8889 | * with it from nvram in order to clear this portion. | |
8890 | */ | |
8891 | struct static_init { | |
8892 | u32 num_sections; | |
8893 | offsize_t sections[SPAD_SECTION_MAX]; | |
8894 | #define SECTION(_sec_) (*((offsize_t *)(STRUCT_OFFSET(sections[_sec_])))) | |
8895 | ||
8896 | struct mcp_trace trace; | |
8897 | #define MCP_TRACE_P ((struct mcp_trace *)(STRUCT_OFFSET(trace))) | |
8898 | u8 trace_buffer[MCP_TRACE_SIZE]; | |
8899 | #define MCP_TRACE_BUF ((u8 *)(STRUCT_OFFSET(trace_buffer))) | |
8900 | /* running_mfw has the same definition as in nvm_map.h. | |
8901 | * This bit indicate both the running dir, and the running bundle. | |
8902 | * It is set once when the LIM is loaded. | |
8903 | */ | |
8904 | u32 running_mfw; | |
8905 | #define RUNNING_MFW (*((u32 *)(STRUCT_OFFSET(running_mfw)))) | |
8906 | u32 build_time; | |
8907 | #define MFW_BUILD_TIME (*((u32 *)(STRUCT_OFFSET(build_time)))) | |
8908 | u32 reset_type; | |
8909 | #define RESET_TYPE (*((u32 *)(STRUCT_OFFSET(reset_type)))) | |
8910 | u32 mfw_secure_mode; | |
8911 | #define MFW_SECURE_MODE (*((u32 *)(STRUCT_OFFSET(mfw_secure_mode)))) | |
8912 | u16 pme_status_pf_bitmap; | |
8913 | #define PME_STATUS_PF_BITMAP (*((u16 *)(STRUCT_OFFSET(pme_status_pf_bitmap)))) | |
8914 | u16 pme_enable_pf_bitmap; | |
8915 | #define PME_ENABLE_PF_BITMAP (*((u16 *)(STRUCT_OFFSET(pme_enable_pf_bitmap)))) | |
8916 | u32 mim_nvm_addr; | |
8917 | u32 mim_start_addr; | |
8918 | u32 ah_pcie_link_params; | |
8919 | #define AH_PCIE_LINK_PARAMS_LINK_SPEED_MASK (0x000000ff) | |
8920 | #define AH_PCIE_LINK_PARAMS_LINK_SPEED_SHIFT (0) | |
8921 | #define AH_PCIE_LINK_PARAMS_LINK_WIDTH_MASK (0x0000ff00) | |
8922 | #define AH_PCIE_LINK_PARAMS_LINK_WIDTH_SHIFT (8) | |
8923 | #define AH_PCIE_LINK_PARAMS_ASPM_MODE_MASK (0x00ff0000) | |
8924 | #define AH_PCIE_LINK_PARAMS_ASPM_MODE_SHIFT (16) | |
8925 | #define AH_PCIE_LINK_PARAMS_ASPM_CAP_MASK (0xff000000) | |
8926 | #define AH_PCIE_LINK_PARAMS_ASPM_CAP_SHIFT (24) | |
8927 | #define AH_PCIE_LINK_PARAMS (*((u32 *)(STRUCT_OFFSET(ah_pcie_link_params)))) | |
8928 | ||
8929 | u32 rsrv_persist[5]; /* Persist reserved for MFW upgrades */ | |
8930 | }; | |
8931 | ||
8932 | enum nvm_image_type { | |
8933 | NVM_TYPE_TIM1 = 0x01, | |
8934 | NVM_TYPE_TIM2 = 0x02, | |
8935 | NVM_TYPE_MIM1 = 0x03, | |
8936 | NVM_TYPE_MIM2 = 0x04, | |
8937 | NVM_TYPE_MBA = 0x05, | |
8938 | NVM_TYPE_MODULES_PN = 0x06, | |
8939 | NVM_TYPE_VPD = 0x07, | |
8940 | NVM_TYPE_MFW_TRACE1 = 0x08, | |
8941 | NVM_TYPE_MFW_TRACE2 = 0x09, | |
8942 | NVM_TYPE_NVM_CFG1 = 0x0a, | |
8943 | NVM_TYPE_L2B = 0x0b, | |
8944 | NVM_TYPE_DIR1 = 0x0c, | |
8945 | NVM_TYPE_EAGLE_FW1 = 0x0d, | |
8946 | NVM_TYPE_FALCON_FW1 = 0x0e, | |
8947 | NVM_TYPE_PCIE_FW1 = 0x0f, | |
8948 | NVM_TYPE_HW_SET = 0x10, | |
8949 | NVM_TYPE_LIM = 0x11, | |
8950 | NVM_TYPE_AVS_FW1 = 0x12, | |
8951 | NVM_TYPE_DIR2 = 0x13, | |
8952 | NVM_TYPE_CCM = 0x14, | |
8953 | NVM_TYPE_EAGLE_FW2 = 0x15, | |
8954 | NVM_TYPE_FALCON_FW2 = 0x16, | |
8955 | NVM_TYPE_PCIE_FW2 = 0x17, | |
8956 | NVM_TYPE_AVS_FW2 = 0x18, | |
8957 | NVM_TYPE_INIT_HW = 0x19, | |
8958 | NVM_TYPE_DEFAULT_CFG = 0x1a, | |
8959 | NVM_TYPE_MDUMP = 0x1b, | |
8960 | NVM_TYPE_META = 0x1c, | |
8961 | NVM_TYPE_ISCSI_CFG = 0x1d, | |
8962 | NVM_TYPE_FCOE_CFG = 0x1f, | |
8963 | NVM_TYPE_ETH_PHY_FW1 = 0x20, | |
8964 | NVM_TYPE_ETH_PHY_FW2 = 0x21, | |
8965 | NVM_TYPE_MAX, | |
8966 | }; | |
8967 | ||
8968 | #define DIR_ID_1 (0) | |
8969 | ||
fe56b9e6 | 8970 | #endif |