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qed: Print multi-bit attentions properly
[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / qlogic / qed / qed_int.c
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fe56b9e6 1/* QLogic qed NIC Driver
e8f1cb50 2 * Copyright (c) 2015-2017 QLogic Corporation
fe56b9e6 3 *
e8f1cb50
MY		 4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
fe56b9e6
YM		 31 */
32
33#include <linux/types.h>
34#include <asm/byteorder.h>
35#include <linux/io.h>
36#include <linux/bitops.h>
37#include <linux/delay.h>
38#include <linux/dma-mapping.h>
39#include <linux/errno.h>
40#include <linux/interrupt.h>
41#include <linux/kernel.h>
42#include <linux/pci.h>
43#include <linux/slab.h>
44#include <linux/string.h>
45#include "qed.h"
46#include "qed_hsi.h"
47#include "qed_hw.h"
48#include "qed_init_ops.h"
49#include "qed_int.h"
50#include "qed_mcp.h"
51#include "qed_reg_addr.h"
52#include "qed_sp.h"
1408cc1f
YM		 53#include "qed_sriov.h"
54#include "qed_vf.h"
fe56b9e6
YM		 55
56struct qed_pi_info {
57 qed_int_comp_cb_t comp_cb;
58 void *cookie;
59};
60
61struct qed_sb_sp_info {
62 struct qed_sb_info sb_info;
63
64 /* per protocol index data */
65 struct qed_pi_info pi_info_arr[PIS_PER_SB];
66};
67
ff38577a
YM		 68enum qed_attention_type {
69 QED_ATTN_TYPE_ATTN,
70 QED_ATTN_TYPE_PARITY,
71};
72
cc875c2e
YM		 73#define SB_ATTN_ALIGNED_SIZE(p_hwfn) \
74 ALIGNED_TYPE_SIZE(struct atten_status_block, p_hwfn)
75
0d956e8a
YM		 76struct aeu_invert_reg_bit {
77 char bit_name[30];
78
79#define ATTENTION_PARITY (1 << 0)
80
81#define ATTENTION_LENGTH_MASK (0x00000ff0)
82#define ATTENTION_LENGTH_SHIFT (4)
83#define ATTENTION_LENGTH(flags) (((flags) & ATTENTION_LENGTH_MASK) >> \
84 ATTENTION_LENGTH_SHIFT)
85#define ATTENTION_SINGLE (1 << ATTENTION_LENGTH_SHIFT)
86#define ATTENTION_PAR (ATTENTION_SINGLE | ATTENTION_PARITY)
87#define ATTENTION_PAR_INT ((2 << ATTENTION_LENGTH_SHIFT) | \
88 ATTENTION_PARITY)
89
90/* Multiple bits start with this offset */
91#define ATTENTION_OFFSET_MASK (0x000ff000)
92#define ATTENTION_OFFSET_SHIFT (12)
ba36f718
MY		 93
94#define ATTENTION_BB_MASK (0x00700000)
95#define ATTENTION_BB_SHIFT (20)
96#define ATTENTION_BB(value) (value << ATTENTION_BB_SHIFT)
97#define ATTENTION_BB_DIFFERENT BIT(23)
98
0d956e8a 99 unsigned int flags;
ff38577a 100
b4149dc7
YM		 101 /* Callback to call if attention will be triggered */
102 int (*cb)(struct qed_hwfn *p_hwfn);
103
ff38577a 104 enum block_id block_index;
0d956e8a
YM		 105};
106
107struct aeu_invert_reg {
108 struct aeu_invert_reg_bit bits[32];
109};
110
111#define MAX_ATTN_GRPS (8)
112#define NUM_ATTN_REGS (9)
113
b4149dc7
YM		 114/* Specific HW attention callbacks */
115static int qed_mcp_attn_cb(struct qed_hwfn *p_hwfn)
116{
117 u32 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_STATE);
118
119 /* This might occur on certain instances; Log it once then mask it */
120 DP_INFO(p_hwfn->cdev, "MCP_REG_CPU_STATE: %08x - Masking...\n",
121 tmp);
122 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_EVENT_MASK,
123 0xffffffff);
124
125 return 0;
126}
127
128#define QED_PSWHST_ATTENTION_INCORRECT_ACCESS (0x1)
129#define ATTENTION_INCORRECT_ACCESS_WR_MASK (0x1)
130#define ATTENTION_INCORRECT_ACCESS_WR_SHIFT (0)
131#define ATTENTION_INCORRECT_ACCESS_CLIENT_MASK (0xf)
132#define ATTENTION_INCORRECT_ACCESS_CLIENT_SHIFT (1)
133#define ATTENTION_INCORRECT_ACCESS_VF_VALID_MASK (0x1)
134#define ATTENTION_INCORRECT_ACCESS_VF_VALID_SHIFT (5)
135#define ATTENTION_INCORRECT_ACCESS_VF_ID_MASK (0xff)
136#define ATTENTION_INCORRECT_ACCESS_VF_ID_SHIFT (6)
137#define ATTENTION_INCORRECT_ACCESS_PF_ID_MASK (0xf)
138#define ATTENTION_INCORRECT_ACCESS_PF_ID_SHIFT (14)
139#define ATTENTION_INCORRECT_ACCESS_BYTE_EN_MASK (0xff)
140#define ATTENTION_INCORRECT_ACCESS_BYTE_EN_SHIFT (18)
141static int qed_pswhst_attn_cb(struct qed_hwfn *p_hwfn)
142{
143 u32 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
144 PSWHST_REG_INCORRECT_ACCESS_VALID);
145
146 if (tmp & QED_PSWHST_ATTENTION_INCORRECT_ACCESS) {
147 u32 addr, data, length;
148
149 addr = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
150 PSWHST_REG_INCORRECT_ACCESS_ADDRESS);
151 data = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
152 PSWHST_REG_INCORRECT_ACCESS_DATA);
153 length = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
154 PSWHST_REG_INCORRECT_ACCESS_LENGTH);
155
156 DP_INFO(p_hwfn->cdev,
157 "Incorrect access to %08x of length %08x - PF [%02x] VF [%04x] [valid %02x] client [%02x] write [%02x] Byte-Enable [%04x] [%08x]\n",
158 addr, length,
159 (u8) GET_FIELD(data, ATTENTION_INCORRECT_ACCESS_PF_ID),
160 (u8) GET_FIELD(data, ATTENTION_INCORRECT_ACCESS_VF_ID),
161 (u8) GET_FIELD(data,
162 ATTENTION_INCORRECT_ACCESS_VF_VALID),
163 (u8) GET_FIELD(data,
164 ATTENTION_INCORRECT_ACCESS_CLIENT),
165 (u8) GET_FIELD(data, ATTENTION_INCORRECT_ACCESS_WR),
166 (u8) GET_FIELD(data,
167 ATTENTION_INCORRECT_ACCESS_BYTE_EN),
168 data);
169 }
170
171 return 0;
172}
173
174#define QED_GRC_ATTENTION_VALID_BIT (1 << 0)
175#define QED_GRC_ATTENTION_ADDRESS_MASK (0x7fffff)
176#define QED_GRC_ATTENTION_ADDRESS_SHIFT (0)
177#define QED_GRC_ATTENTION_RDWR_BIT (1 << 23)
178#define QED_GRC_ATTENTION_MASTER_MASK (0xf)
179#define QED_GRC_ATTENTION_MASTER_SHIFT (24)
180#define QED_GRC_ATTENTION_PF_MASK (0xf)
181#define QED_GRC_ATTENTION_PF_SHIFT (0)
182#define QED_GRC_ATTENTION_VF_MASK (0xff)
183#define QED_GRC_ATTENTION_VF_SHIFT (4)
184#define QED_GRC_ATTENTION_PRIV_MASK (0x3)
185#define QED_GRC_ATTENTION_PRIV_SHIFT (14)
186#define QED_GRC_ATTENTION_PRIV_VF (0)
187static const char *attn_master_to_str(u8 master)
188{
189 switch (master) {
190 case 1: return "PXP";
191 case 2: return "MCP";
192 case 3: return "MSDM";
193 case 4: return "PSDM";
194 case 5: return "YSDM";
195 case 6: return "USDM";
196 case 7: return "TSDM";
197 case 8: return "XSDM";
198 case 9: return "DBU";
199 case 10: return "DMAE";
200 default:
9165dabb 201 return "Unknown";
b4149dc7
YM		 202 }
203}
204
205static int qed_grc_attn_cb(struct qed_hwfn *p_hwfn)
206{
207 u32 tmp, tmp2;
208
209 /* We've already cleared the timeout interrupt register, so we learn
210 * of interrupts via the validity register
211 */
212 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
213 GRC_REG_TIMEOUT_ATTN_ACCESS_VALID);
214 if (!(tmp & QED_GRC_ATTENTION_VALID_BIT))
215 goto out;
216
217 /* Read the GRC timeout information */
218 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
219 GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0);
220 tmp2 = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
221 GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_1);
222
223 DP_INFO(p_hwfn->cdev,
224 "GRC timeout [%08x:%08x] - %s Address [%08x] [Master %s] [PF: %02x %s %02x]\n",
225 tmp2, tmp,
226 (tmp & QED_GRC_ATTENTION_RDWR_BIT) ? "Write to" : "Read from",
227 GET_FIELD(tmp, QED_GRC_ATTENTION_ADDRESS) << 2,
228 attn_master_to_str(GET_FIELD(tmp, QED_GRC_ATTENTION_MASTER)),
229 GET_FIELD(tmp2, QED_GRC_ATTENTION_PF),
230 (GET_FIELD(tmp2, QED_GRC_ATTENTION_PRIV) ==
231 QED_GRC_ATTENTION_PRIV_VF) ? "VF" : "(Ireelevant)",
232 GET_FIELD(tmp2, QED_GRC_ATTENTION_VF));
233
234out:
235 /* Regardles of anything else, clean the validity bit */
236 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt,
237 GRC_REG_TIMEOUT_ATTN_ACCESS_VALID, 0);
238 return 0;
239}
240
241#define PGLUE_ATTENTION_VALID (1 << 29)
242#define PGLUE_ATTENTION_RD_VALID (1 << 26)
243#define PGLUE_ATTENTION_DETAILS_PFID_MASK (0xf)
244#define PGLUE_ATTENTION_DETAILS_PFID_SHIFT (20)
245#define PGLUE_ATTENTION_DETAILS_VF_VALID_MASK (0x1)
246#define PGLUE_ATTENTION_DETAILS_VF_VALID_SHIFT (19)
247#define PGLUE_ATTENTION_DETAILS_VFID_MASK (0xff)
248#define PGLUE_ATTENTION_DETAILS_VFID_SHIFT (24)
249#define PGLUE_ATTENTION_DETAILS2_WAS_ERR_MASK (0x1)
250#define PGLUE_ATTENTION_DETAILS2_WAS_ERR_SHIFT (21)
251#define PGLUE_ATTENTION_DETAILS2_BME_MASK (0x1)
252#define PGLUE_ATTENTION_DETAILS2_BME_SHIFT (22)
253#define PGLUE_ATTENTION_DETAILS2_FID_EN_MASK (0x1)
254#define PGLUE_ATTENTION_DETAILS2_FID_EN_SHIFT (23)
255#define PGLUE_ATTENTION_ICPL_VALID (1 << 23)
256#define PGLUE_ATTENTION_ZLR_VALID (1 << 25)
257#define PGLUE_ATTENTION_ILT_VALID (1 << 23)
258static int qed_pglub_rbc_attn_cb(struct qed_hwfn *p_hwfn)
259{
260 u32 tmp;
261
262 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
263 PGLUE_B_REG_TX_ERR_WR_DETAILS2);
264 if (tmp & PGLUE_ATTENTION_VALID) {
265 u32 addr_lo, addr_hi, details;
266
267 addr_lo = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
268 PGLUE_B_REG_TX_ERR_WR_ADD_31_0);
269 addr_hi = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
270 PGLUE_B_REG_TX_ERR_WR_ADD_63_32);
271 details = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
272 PGLUE_B_REG_TX_ERR_WR_DETAILS);
273
274 DP_INFO(p_hwfn,
275 "Illegal write by chip to [%08x:%08x] blocked.\n"
276 "Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x]\n"
277 "Details2 %08x [Was_error %02x BME deassert %02x FID_enable deassert %02x]\n",
278 addr_hi, addr_lo, details,
279 (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_PFID),
280 (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_VFID),
281 GET_FIELD(details,
282 PGLUE_ATTENTION_DETAILS_VF_VALID) ? 1 : 0,
283 tmp,
284 GET_FIELD(tmp,
285 PGLUE_ATTENTION_DETAILS2_WAS_ERR) ? 1 : 0,
286 GET_FIELD(tmp,
287 PGLUE_ATTENTION_DETAILS2_BME) ? 1 : 0,
288 GET_FIELD(tmp,
289 PGLUE_ATTENTION_DETAILS2_FID_EN) ? 1 : 0);
290 }
291
292 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
293 PGLUE_B_REG_TX_ERR_RD_DETAILS2);
294 if (tmp & PGLUE_ATTENTION_RD_VALID) {
295 u32 addr_lo, addr_hi, details;
296
297 addr_lo = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
298 PGLUE_B_REG_TX_ERR_RD_ADD_31_0);
299 addr_hi = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
300 PGLUE_B_REG_TX_ERR_RD_ADD_63_32);
301 details = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
302 PGLUE_B_REG_TX_ERR_RD_DETAILS);
303
304 DP_INFO(p_hwfn,
305 "Illegal read by chip from [%08x:%08x] blocked.\n"
306 " Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x]\n"
307 " Details2 %08x [Was_error %02x BME deassert %02x FID_enable deassert %02x]\n",
308 addr_hi, addr_lo, details,
309 (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_PFID),
310 (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_VFID),
311 GET_FIELD(details,
312 PGLUE_ATTENTION_DETAILS_VF_VALID) ? 1 : 0,
313 tmp,
314 GET_FIELD(tmp, PGLUE_ATTENTION_DETAILS2_WAS_ERR) ? 1
315 : 0,
316 GET_FIELD(tmp, PGLUE_ATTENTION_DETAILS2_BME) ? 1 : 0,
317 GET_FIELD(tmp, PGLUE_ATTENTION_DETAILS2_FID_EN) ? 1
318 : 0);
319 }
320
321 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
322 PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL);
323 if (tmp & PGLUE_ATTENTION_ICPL_VALID)
324 DP_INFO(p_hwfn, "ICPL eror - %08x\n", tmp);
325
326 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
327 PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS);
328 if (tmp & PGLUE_ATTENTION_ZLR_VALID) {
329 u32 addr_hi, addr_lo;
330
331 addr_lo = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
332 PGLUE_B_REG_MASTER_ZLR_ERR_ADD_31_0);
333 addr_hi = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
334 PGLUE_B_REG_MASTER_ZLR_ERR_ADD_63_32);
335
336 DP_INFO(p_hwfn, "ZLR eror - %08x [Address %08x:%08x]\n",
337 tmp, addr_hi, addr_lo);
338 }
339
340 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
341 PGLUE_B_REG_VF_ILT_ERR_DETAILS2);
342 if (tmp & PGLUE_ATTENTION_ILT_VALID) {
343 u32 addr_hi, addr_lo, details;
344
345 addr_lo = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
346 PGLUE_B_REG_VF_ILT_ERR_ADD_31_0);
347 addr_hi = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
348 PGLUE_B_REG_VF_ILT_ERR_ADD_63_32);
349 details = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
350 PGLUE_B_REG_VF_ILT_ERR_DETAILS);
351
352 DP_INFO(p_hwfn,
353 "ILT error - Details %08x Details2 %08x [Address %08x:%08x]\n",
354 details, tmp, addr_hi, addr_lo);
355 }
356
357 /* Clear the indications */
358 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt,
359 PGLUE_B_REG_LATCHED_ERRORS_CLR, (1 << 2));
360
361 return 0;
362}
363
364#define QED_DORQ_ATTENTION_REASON_MASK (0xfffff)
365#define QED_DORQ_ATTENTION_OPAQUE_MASK (0xffff)
366#define QED_DORQ_ATTENTION_SIZE_MASK (0x7f)
367#define QED_DORQ_ATTENTION_SIZE_SHIFT (16)
368static int qed_dorq_attn_cb(struct qed_hwfn *p_hwfn)
369{
370 u32 reason;
371
372 reason = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, DORQ_REG_DB_DROP_REASON) &
373 QED_DORQ_ATTENTION_REASON_MASK;
374 if (reason) {
375 u32 details = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
376 DORQ_REG_DB_DROP_DETAILS);
377
378 DP_INFO(p_hwfn->cdev,
9165dabb 379 "DORQ db_drop: address 0x%08x Opaque FID 0x%04x Size [bytes] 0x%08x Reason: 0x%08x\n",
b4149dc7
YM		 380 qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
381 DORQ_REG_DB_DROP_DETAILS_ADDRESS),
382 (u16)(details & QED_DORQ_ATTENTION_OPAQUE_MASK),
383 GET_FIELD(details, QED_DORQ_ATTENTION_SIZE) * 4,
384 reason);
385 }
386
387 return -EINVAL;
388}
389
ba36f718
MY		 390/* Instead of major changes to the data-structure, we have a some 'special'
391 * identifiers for sources that changed meaning between adapters.
392 */
393enum aeu_invert_reg_special_type {
394 AEU_INVERT_REG_SPECIAL_CNIG_0,
395 AEU_INVERT_REG_SPECIAL_CNIG_1,
396 AEU_INVERT_REG_SPECIAL_CNIG_2,
397 AEU_INVERT_REG_SPECIAL_CNIG_3,
398 AEU_INVERT_REG_SPECIAL_MAX,
399};
400
401static struct aeu_invert_reg_bit
402aeu_descs_special[AEU_INVERT_REG_SPECIAL_MAX] = {
403 {"CNIG port 0", ATTENTION_SINGLE, NULL, BLOCK_CNIG},
404 {"CNIG port 1", ATTENTION_SINGLE, NULL, BLOCK_CNIG},
405 {"CNIG port 2", ATTENTION_SINGLE, NULL, BLOCK_CNIG},
406 {"CNIG port 3", ATTENTION_SINGLE, NULL, BLOCK_CNIG},
407};
408
0d956e8a
YM		 409/* Notice aeu_invert_reg must be defined in the same order of bits as HW; */
410static struct aeu_invert_reg aeu_descs[NUM_ATTN_REGS] = {
411 {
412 { /* After Invert 1 */
413 {"GPIO0 function%d",
b4149dc7 414 (32 << ATTENTION_LENGTH_SHIFT), NULL, MAX_BLOCK_ID},
0d956e8a
YM		 415 }
416 },
417
418 {
419 { /* After Invert 2 */
b4149dc7
YM		 420 {"PGLUE config_space", ATTENTION_SINGLE,
421 NULL, MAX_BLOCK_ID},
422 {"PGLUE misc_flr", ATTENTION_SINGLE,
423 NULL, MAX_BLOCK_ID},
424 {"PGLUE B RBC", ATTENTION_PAR_INT,
425 qed_pglub_rbc_attn_cb, BLOCK_PGLUE_B},
426 {"PGLUE misc_mctp", ATTENTION_SINGLE,
427 NULL, MAX_BLOCK_ID},
428 {"Flash event", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID},
429 {"SMB event", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID},
430 {"Main Power", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID},
0d956e8a 431 {"SW timers #%d", (8 << ATTENTION_LENGTH_SHIFT) |
ff38577a 432 (1 << ATTENTION_OFFSET_SHIFT),
b4149dc7 433 NULL, MAX_BLOCK_ID},
0d956e8a 434 {"PCIE glue/PXP VPD %d",
b4149dc7 435 (16 << ATTENTION_LENGTH_SHIFT), NULL, BLOCK_PGLCS},
0d956e8a
YM		 436 }
437 },
438
439 {
440 { /* After Invert 3 */
441 {"General Attention %d",
b4149dc7 442 (32 << ATTENTION_LENGTH_SHIFT), NULL, MAX_BLOCK_ID},
0d956e8a
YM		 443 }
444 },
445
446 {
447 { /* After Invert 4 */
ff38577a 448 {"General Attention 32", ATTENTION_SINGLE,
b4149dc7 449 NULL, MAX_BLOCK_ID},
0d956e8a
YM		 450 {"General Attention %d",
451 (2 << ATTENTION_LENGTH_SHIFT) |
b4149dc7 452 (33 << ATTENTION_OFFSET_SHIFT), NULL, MAX_BLOCK_ID},
ff38577a 453 {"General Attention 35", ATTENTION_SINGLE,
b4149dc7 454 NULL, MAX_BLOCK_ID},
ba36f718
MY		 455 {"NWS Parity",
456 ATTENTION_PAR | ATTENTION_BB_DIFFERENT |
457 ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_0),
458 NULL, BLOCK_NWS},
459 {"NWS Interrupt",
460 ATTENTION_SINGLE | ATTENTION_BB_DIFFERENT |
461 ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_1),
462 NULL, BLOCK_NWS},
463 {"NWM Parity",
464 ATTENTION_PAR | ATTENTION_BB_DIFFERENT |
465 ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_2),
466 NULL, BLOCK_NWM},
467 {"NWM Interrupt",
468 ATTENTION_SINGLE | ATTENTION_BB_DIFFERENT |
469 ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_3),
470 NULL, BLOCK_NWM},
b4149dc7
YM		 471 {"MCP CPU", ATTENTION_SINGLE,
472 qed_mcp_attn_cb, MAX_BLOCK_ID},
473 {"MCP Watchdog timer", ATTENTION_SINGLE,
474 NULL, MAX_BLOCK_ID},
475 {"MCP M2P", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID},
ff38577a 476 {"AVS stop status ready", ATTENTION_SINGLE,
b4149dc7
YM		 477 NULL, MAX_BLOCK_ID},
478 {"MSTAT", ATTENTION_PAR_INT, NULL, MAX_BLOCK_ID},
479 {"MSTAT per-path", ATTENTION_PAR_INT,
480 NULL, MAX_BLOCK_ID},
ff38577a 481 {"Reserved %d", (6 << ATTENTION_LENGTH_SHIFT),
b4149dc7
YM		 482 NULL, MAX_BLOCK_ID},
483 {"NIG", ATTENTION_PAR_INT, NULL, BLOCK_NIG},
484 {"BMB/OPTE/MCP", ATTENTION_PAR_INT, NULL, BLOCK_BMB},
485 {"BTB", ATTENTION_PAR_INT, NULL, BLOCK_BTB},
486 {"BRB", ATTENTION_PAR_INT, NULL, BLOCK_BRB},
487 {"PRS", ATTENTION_PAR_INT, NULL, BLOCK_PRS},
0d956e8a
YM		 488 }
489 },
490
491 {
492 { /* After Invert 5 */
b4149dc7
YM		 493 {"SRC", ATTENTION_PAR_INT, NULL, BLOCK_SRC},
494 {"PB Client1", ATTENTION_PAR_INT, NULL, BLOCK_PBF_PB1},
495 {"PB Client2", ATTENTION_PAR_INT, NULL, BLOCK_PBF_PB2},
496 {"RPB", ATTENTION_PAR_INT, NULL, BLOCK_RPB},
497 {"PBF", ATTENTION_PAR_INT, NULL, BLOCK_PBF},
498 {"QM", ATTENTION_PAR_INT, NULL, BLOCK_QM},
499 {"TM", ATTENTION_PAR_INT, NULL, BLOCK_TM},
500 {"MCM", ATTENTION_PAR_INT, NULL, BLOCK_MCM},
501 {"MSDM", ATTENTION_PAR_INT, NULL, BLOCK_MSDM},
502 {"MSEM", ATTENTION_PAR_INT, NULL, BLOCK_MSEM},
503 {"PCM", ATTENTION_PAR_INT, NULL, BLOCK_PCM},
504 {"PSDM", ATTENTION_PAR_INT, NULL, BLOCK_PSDM},
505 {"PSEM", ATTENTION_PAR_INT, NULL, BLOCK_PSEM},
506 {"TCM", ATTENTION_PAR_INT, NULL, BLOCK_TCM},
507 {"TSDM", ATTENTION_PAR_INT, NULL, BLOCK_TSDM},
508 {"TSEM", ATTENTION_PAR_INT, NULL, BLOCK_TSEM},
0d956e8a
YM		 509 }
510 },
511
512 {
513 { /* After Invert 6 */
b4149dc7
YM		 514 {"UCM", ATTENTION_PAR_INT, NULL, BLOCK_UCM},
515 {"USDM", ATTENTION_PAR_INT, NULL, BLOCK_USDM},
516 {"USEM", ATTENTION_PAR_INT, NULL, BLOCK_USEM},
517 {"XCM", ATTENTION_PAR_INT, NULL, BLOCK_XCM},
518 {"XSDM", ATTENTION_PAR_INT, NULL, BLOCK_XSDM},
519 {"XSEM", ATTENTION_PAR_INT, NULL, BLOCK_XSEM},
520 {"YCM", ATTENTION_PAR_INT, NULL, BLOCK_YCM},
521 {"YSDM", ATTENTION_PAR_INT, NULL, BLOCK_YSDM},
522 {"YSEM", ATTENTION_PAR_INT, NULL, BLOCK_YSEM},
523 {"XYLD", ATTENTION_PAR_INT, NULL, BLOCK_XYLD},
524 {"TMLD", ATTENTION_PAR_INT, NULL, BLOCK_TMLD},
525 {"MYLD", ATTENTION_PAR_INT, NULL, BLOCK_MULD},
526 {"YULD", ATTENTION_PAR_INT, NULL, BLOCK_YULD},
527 {"DORQ", ATTENTION_PAR_INT,
528 qed_dorq_attn_cb, BLOCK_DORQ},
529 {"DBG", ATTENTION_PAR_INT, NULL, BLOCK_DBG},
530 {"IPC", ATTENTION_PAR_INT, NULL, BLOCK_IPC},
0d956e8a
YM		 531 }
532 },
533
534 {
535 { /* After Invert 7 */
b4149dc7
YM		 536 {"CCFC", ATTENTION_PAR_INT, NULL, BLOCK_CCFC},
537 {"CDU", ATTENTION_PAR_INT, NULL, BLOCK_CDU},
538 {"DMAE", ATTENTION_PAR_INT, NULL, BLOCK_DMAE},
539 {"IGU", ATTENTION_PAR_INT, NULL, BLOCK_IGU},
540 {"ATC", ATTENTION_PAR_INT, NULL, MAX_BLOCK_ID},
541 {"CAU", ATTENTION_PAR_INT, NULL, BLOCK_CAU},
542 {"PTU", ATTENTION_PAR_INT, NULL, BLOCK_PTU},
543 {"PRM", ATTENTION_PAR_INT, NULL, BLOCK_PRM},
544 {"TCFC", ATTENTION_PAR_INT, NULL, BLOCK_TCFC},
545 {"RDIF", ATTENTION_PAR_INT, NULL, BLOCK_RDIF},
546 {"TDIF", ATTENTION_PAR_INT, NULL, BLOCK_TDIF},
547 {"RSS", ATTENTION_PAR_INT, NULL, BLOCK_RSS},
548 {"MISC", ATTENTION_PAR_INT, NULL, BLOCK_MISC},
549 {"MISCS", ATTENTION_PAR_INT, NULL, BLOCK_MISCS},
550 {"PCIE", ATTENTION_PAR, NULL, BLOCK_PCIE},
551 {"Vaux PCI core", ATTENTION_SINGLE, NULL, BLOCK_PGLCS},
552 {"PSWRQ", ATTENTION_PAR_INT, NULL, BLOCK_PSWRQ},
0d956e8a
YM		 553 }
554 },
555
556 {
557 { /* After Invert 8 */
b4149dc7
YM		 558 {"PSWRQ (pci_clk)", ATTENTION_PAR_INT,
559 NULL, BLOCK_PSWRQ2},
560 {"PSWWR", ATTENTION_PAR_INT, NULL, BLOCK_PSWWR},
561 {"PSWWR (pci_clk)", ATTENTION_PAR_INT,
562 NULL, BLOCK_PSWWR2},
563 {"PSWRD", ATTENTION_PAR_INT, NULL, BLOCK_PSWRD},
564 {"PSWRD (pci_clk)", ATTENTION_PAR_INT,
565 NULL, BLOCK_PSWRD2},
566 {"PSWHST", ATTENTION_PAR_INT,
567 qed_pswhst_attn_cb, BLOCK_PSWHST},
568 {"PSWHST (pci_clk)", ATTENTION_PAR_INT,
569 NULL, BLOCK_PSWHST2},
570 {"GRC", ATTENTION_PAR_INT,
571 qed_grc_attn_cb, BLOCK_GRC},
572 {"CPMU", ATTENTION_PAR_INT, NULL, BLOCK_CPMU},
573 {"NCSI", ATTENTION_PAR_INT, NULL, BLOCK_NCSI},
574 {"MSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID},
575 {"PSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID},
576 {"TSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID},
577 {"USEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID},
578 {"XSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID},
579 {"YSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID},
580 {"pxp_misc_mps", ATTENTION_PAR, NULL, BLOCK_PGLCS},
ff38577a 581 {"PCIE glue/PXP Exp. ROM", ATTENTION_SINGLE,
b4149dc7
YM		 582 NULL, BLOCK_PGLCS},
583 {"PERST_B assertion", ATTENTION_SINGLE,
584 NULL, MAX_BLOCK_ID},
ff38577a 585 {"PERST_B deassertion", ATTENTION_SINGLE,
b4149dc7 586 NULL, MAX_BLOCK_ID},
ff38577a 587 {"Reserved %d", (2 << ATTENTION_LENGTH_SHIFT),
b4149dc7 588 NULL, MAX_BLOCK_ID},
0d956e8a
YM		 589 }
590 },
591
592 {
593 { /* After Invert 9 */
b4149dc7
YM		 594 {"MCP Latched memory", ATTENTION_PAR,
595 NULL, MAX_BLOCK_ID},
ff38577a 596 {"MCP Latched scratchpad cache", ATTENTION_SINGLE,
b4149dc7
YM		 597 NULL, MAX_BLOCK_ID},
598 {"MCP Latched ump_tx", ATTENTION_PAR,
599 NULL, MAX_BLOCK_ID},
ff38577a 600 {"MCP Latched scratchpad", ATTENTION_PAR,
b4149dc7 601 NULL, MAX_BLOCK_ID},
ff38577a 602 {"Reserved %d", (28 << ATTENTION_LENGTH_SHIFT),
b4149dc7 603 NULL, MAX_BLOCK_ID},
0d956e8a
YM		 604 }
605 },
606};
607
ba36f718
MY		 608static struct aeu_invert_reg_bit *
609qed_int_aeu_translate(struct qed_hwfn *p_hwfn,
610 struct aeu_invert_reg_bit *p_bit)
611{
612 if (!QED_IS_BB(p_hwfn->cdev))
613 return p_bit;
614
615 if (!(p_bit->flags & ATTENTION_BB_DIFFERENT))
616 return p_bit;
617
618 return &aeu_descs_special[(p_bit->flags & ATTENTION_BB_MASK) >>
619 ATTENTION_BB_SHIFT];
620}
621
622static bool qed_int_is_parity_flag(struct qed_hwfn *p_hwfn,
623 struct aeu_invert_reg_bit *p_bit)
624{
625 return !!(qed_int_aeu_translate(p_hwfn, p_bit)->flags &
626 ATTENTION_PARITY);
627}
628
0d956e8a 629#define ATTN_STATE_BITS (0xfff)
cc875c2e
YM		 630#define ATTN_BITS_MASKABLE (0x3ff)
631struct qed_sb_attn_info {
632 /* Virtual & Physical address of the SB */
633 struct atten_status_block *sb_attn;
0d956e8a 634 dma_addr_t sb_phys;
cc875c2e
YM		 635
636 /* Last seen running index */
0d956e8a
YM		 637 u16 index;
638
639 /* A mask of the AEU bits resulting in a parity error */
640 u32 parity_mask[NUM_ATTN_REGS];
641
642 /* A pointer to the attention description structure */
643 struct aeu_invert_reg *p_aeu_desc;
cc875c2e
YM		 644
645 /* Previously asserted attentions, which are still unasserted */
0d956e8a 646 u16 known_attn;
cc875c2e
YM		 647
648 /* Cleanup address for the link's general hw attention */
0d956e8a 649 u32 mfw_attn_addr;
cc875c2e
YM		 650};
651
652static inline u16 qed_attn_update_idx(struct qed_hwfn *p_hwfn,
1a635e48 653 struct qed_sb_attn_info *p_sb_desc)
cc875c2e 654{
1a635e48 655 u16 rc = 0, index;
cc875c2e
YM		 656
657 /* Make certain HW write took affect */
658 mmiowb();
659
660 index = le16_to_cpu(p_sb_desc->sb_attn->sb_index);
661 if (p_sb_desc->index != index) {
662 p_sb_desc->index = index;
663 rc = QED_SB_ATT_IDX;
664 }
665
666 /* Make certain we got a consistent view with HW */
667 mmiowb();
668
669 return rc;
670}
671
672/**
673 * @brief qed_int_assertion - handles asserted attention bits
674 *
675 * @param p_hwfn
676 * @param asserted_bits newly asserted bits
677 * @return int
678 */
1a635e48 679static int qed_int_assertion(struct qed_hwfn *p_hwfn, u16 asserted_bits)
cc875c2e
YM		 680{
681 struct qed_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn;
682 u32 igu_mask;
683
684 /* Mask the source of the attention in the IGU */
1a635e48 685 igu_mask = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE);
cc875c2e
YM		 686 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "IGU mask: 0x%08x --> 0x%08x\n",
687 igu_mask, igu_mask & ~(asserted_bits & ATTN_BITS_MASKABLE));
688 igu_mask &= ~(asserted_bits & ATTN_BITS_MASKABLE);
689 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, igu_mask);
690
691 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
692 "inner known ATTN state: 0x%04x --> 0x%04x\n",
693 sb_attn_sw->known_attn,
694 sb_attn_sw->known_attn | asserted_bits);
695 sb_attn_sw->known_attn |= asserted_bits;
696
697 /* Handle MCP events */
698 if (asserted_bits & 0x100) {
699 qed_mcp_handle_events(p_hwfn, p_hwfn->p_dpc_ptt);
700 /* Clean the MCP attention */
701 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt,
702 sb_attn_sw->mfw_attn_addr, 0);
703 }
704
705 DIRECT_REG_WR((u8 __iomem *)p_hwfn->regview +
706 GTT_BAR0_MAP_REG_IGU_CMD +
707 ((IGU_CMD_ATTN_BIT_SET_UPPER -
708 IGU_CMD_INT_ACK_BASE) << 3),
709 (u32)asserted_bits);
710
711 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "set cmd IGU: 0x%04x\n",
712 asserted_bits);
713
714 return 0;
715}
716
0ebbd1c8
MY		 717static void qed_int_attn_print(struct qed_hwfn *p_hwfn,
718 enum block_id id,
719 enum dbg_attn_type type, bool b_clear)
ff38577a 720{
0ebbd1c8
MY		 721 struct dbg_attn_block_result attn_results;
722 enum dbg_status status;
ff38577a 723
0ebbd1c8 724 memset(&attn_results, 0, sizeof(attn_results));
ff38577a 725
0ebbd1c8
MY		 726 status = qed_dbg_read_attn(p_hwfn, p_hwfn->p_dpc_ptt, id, type,
727 b_clear, &attn_results);
728 if (status != DBG_STATUS_OK)
ff38577a 729 DP_NOTICE(p_hwfn,
0ebbd1c8
MY		 730 "Failed to parse attention information [status: %s]\n",
731 qed_dbg_get_status_str(status));
732 else
733 qed_dbg_parse_attn(p_hwfn, &attn_results);
ff38577a
YM		 734}
735
0d956e8a
YM		 736/**
737 * @brief qed_int_deassertion_aeu_bit - handles the effects of a single
738 * cause of the attention
739 *
740 * @param p_hwfn
741 * @param p_aeu - descriptor of an AEU bit which caused the attention
742 * @param aeu_en_reg - register offset of the AEU enable reg. which configured
743 * this bit to this group.
744 * @param bit_index - index of this bit in the aeu_en_reg
745 *
746 * @return int
747 */
748static int
749qed_int_deassertion_aeu_bit(struct qed_hwfn *p_hwfn,
750 struct aeu_invert_reg_bit *p_aeu,
751 u32 aeu_en_reg,
6010179d 752 const char *p_bit_name, u32 bitmask)
0d956e8a 753{
0ebbd1c8 754 bool b_fatal = false;
0d956e8a 755 int rc = -EINVAL;
b4149dc7 756 u32 val;
0d956e8a
YM		 757
758 DP_INFO(p_hwfn, "Deasserted attention `%s'[%08x]\n",
6010179d 759 p_bit_name, bitmask);
0d956e8a 760
b4149dc7
YM		 761 /* Call callback before clearing the interrupt status */
762 if (p_aeu->cb) {
763 DP_INFO(p_hwfn, "`%s (attention)': Calling Callback function\n",
6010179d 764 p_bit_name);
b4149dc7
YM		 765 rc = p_aeu->cb(p_hwfn);
766 }
767
0ebbd1c8
MY		 768 if (rc)
769 b_fatal = true;
770
771 /* Print HW block interrupt registers */
772 if (p_aeu->block_index != MAX_BLOCK_ID)
773 qed_int_attn_print(p_hwfn, p_aeu->block_index,
774 ATTN_TYPE_INTERRUPT, !b_fatal);
775
ff38577a 776
b4149dc7
YM		 777 /* If the attention is benign, no need to prevent it */
778 if (!rc)
779 goto out;
780
0d956e8a
YM		 781 /* Prevent this Attention from being asserted in the future */
782 val = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg);
b4149dc7 783 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg, (val & ~bitmask));
0d956e8a 784 DP_INFO(p_hwfn, "`%s' - Disabled future attentions\n",
6010179d 785 p_bit_name);
0d956e8a 786
b4149dc7 787out:
0d956e8a
YM		 788 return rc;
789}
790
ff38577a
YM		 791/**
792 * @brief qed_int_deassertion_parity - handle a single parity AEU source
793 *
794 * @param p_hwfn
795 * @param p_aeu - descriptor of an AEU bit which caused the parity
796 * @param bit_index
797 */
798static void qed_int_deassertion_parity(struct qed_hwfn *p_hwfn,
799 struct aeu_invert_reg_bit *p_aeu,
800 u8 bit_index)
801{
802 u32 block_id = p_aeu->block_index;
803
804 DP_INFO(p_hwfn->cdev, "%s[%d] parity attention is set\n",
805 p_aeu->bit_name, bit_index);
806
807 if (block_id != MAX_BLOCK_ID) {
0ebbd1c8 808 qed_int_attn_print(p_hwfn, block_id, ATTN_TYPE_PARITY, false);
ff38577a
YM		 809
810 /* In BB, there's a single parity bit for several blocks */
811 if (block_id == BLOCK_BTB) {
0ebbd1c8
MY		 812 qed_int_attn_print(p_hwfn, BLOCK_OPTE,
813 ATTN_TYPE_PARITY, false);
814 qed_int_attn_print(p_hwfn, BLOCK_MCP,
815 ATTN_TYPE_PARITY, false);
ff38577a
YM		 816 }
817 }
818}
819
cc875c2e
YM		 820/**
821 * @brief - handles deassertion of previously asserted attentions.
822 *
823 * @param p_hwfn
824 * @param deasserted_bits - newly deasserted bits
825 * @return int
826 *
827 */
828static int qed_int_deassertion(struct qed_hwfn *p_hwfn,
829 u16 deasserted_bits)
830{
831 struct qed_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn;
0d956e8a
YM		 832 u32 aeu_inv_arr[NUM_ATTN_REGS], aeu_mask;
833 u8 i, j, k, bit_idx;
834 int rc = 0;
835
836 /* Read the attention registers in the AEU */
837 for (i = 0; i < NUM_ATTN_REGS; i++) {
838 aeu_inv_arr[i] = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
839 MISC_REG_AEU_AFTER_INVERT_1_IGU +
840 i * 0x4);
841 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
842 "Deasserted bits [%d]: %08x\n",
843 i, aeu_inv_arr[i]);
844 }
845
846 /* Find parity attentions first */
847 for (i = 0; i < NUM_ATTN_REGS; i++) {
848 struct aeu_invert_reg *p_aeu = &sb_attn_sw->p_aeu_desc[i];
849 u32 en = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
850 MISC_REG_AEU_ENABLE1_IGU_OUT_0 +
851 i * sizeof(u32));
852 u32 parities;
853
854 /* Skip register in which no parity bit is currently set */
855 parities = sb_attn_sw->parity_mask[i] & aeu_inv_arr[i] & en;
856 if (!parities)
857 continue;
cc875c2e 858
0d956e8a
YM		 859 for (j = 0, bit_idx = 0; bit_idx < 32; j++) {
860 struct aeu_invert_reg_bit *p_bit = &p_aeu->bits[j];
861
ba36f718 862 if (qed_int_is_parity_flag(p_hwfn, p_bit) &&
1a635e48 863 !!(parities & BIT(bit_idx)))
ff38577a
YM		 864 qed_int_deassertion_parity(p_hwfn, p_bit,
865 bit_idx);
0d956e8a
YM		 866
867 bit_idx += ATTENTION_LENGTH(p_bit->flags);
868 }
869 }
870
871 /* Find non-parity cause for attention and act */
872 for (k = 0; k < MAX_ATTN_GRPS; k++) {
873 struct aeu_invert_reg_bit *p_aeu;
874
875 /* Handle only groups whose attention is currently deasserted */
876 if (!(deasserted_bits & (1 << k)))
877 continue;
878
879 for (i = 0; i < NUM_ATTN_REGS; i++) {
880 u32 aeu_en = MISC_REG_AEU_ENABLE1_IGU_OUT_0 +
881 i * sizeof(u32) +
882 k * sizeof(u32) * NUM_ATTN_REGS;
883 u32 en, bits;
884
885 en = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en);
886 bits = aeu_inv_arr[i] & en;
887
888 /* Skip if no bit from this group is currently set */
889 if (!bits)
890 continue;
891
892 /* Find all set bits from current register which belong
893 * to current group, making them responsible for the
894 * previous assertion.
895 */
896 for (j = 0, bit_idx = 0; bit_idx < 32; j++) {
6010179d 897 long unsigned int bitmask;
0d956e8a 898 u8 bit, bit_len;
0d956e8a
YM		 899
900 p_aeu = &sb_attn_sw->p_aeu_desc[i].bits[j];
ba36f718 901 p_aeu = qed_int_aeu_translate(p_hwfn, p_aeu);
0d956e8a
YM		 902
903 bit = bit_idx;
904 bit_len = ATTENTION_LENGTH(p_aeu->flags);
ba36f718 905 if (qed_int_is_parity_flag(p_hwfn, p_aeu)) {
0d956e8a
YM		 906 /* Skip Parity */
907 bit++;
908 bit_len--;
909 }
910
911 bitmask = bits & (((1 << bit_len) - 1) << bit);
6010179d
MY		 912 bitmask >>= bit;
913
0d956e8a 914 if (bitmask) {
6010179d
MY		 915 u32 flags = p_aeu->flags;
916 char bit_name[30];
917 u8 num;
918
919 num = (u8)find_first_bit(&bitmask,
920 bit_len);
921
922 /* Some bits represent more than a
923 * a single interrupt. Correctly print
924 * their name.
925 */
926 if (ATTENTION_LENGTH(flags) > 2 ||
927 ((flags & ATTENTION_PAR_INT) &&
928 ATTENTION_LENGTH(flags) > 1))
929 snprintf(bit_name, 30,
930 p_aeu->bit_name, num);
931 else
932 strncpy(bit_name,
933 p_aeu->bit_name, 30);
934
935 /* We now need to pass bitmask in its
936 * correct position.
937 */
938 bitmask <<= bit;
939
0d956e8a
YM		 940 /* Handle source of the attention */
941 qed_int_deassertion_aeu_bit(p_hwfn,
942 p_aeu,
943 aeu_en,
6010179d 944 bit_name,
0d956e8a
YM		 945 bitmask);
946 }
947
948 bit_idx += ATTENTION_LENGTH(p_aeu->flags);
949 }
950 }
951 }
cc875c2e
YM		 952
953 /* Clear IGU indication for the deasserted bits */
954 DIRECT_REG_WR((u8 __iomem *)p_hwfn->regview +
0d956e8a
YM		 955 GTT_BAR0_MAP_REG_IGU_CMD +
956 ((IGU_CMD_ATTN_BIT_CLR_UPPER -
957 IGU_CMD_INT_ACK_BASE) << 3),
958 ~((u32)deasserted_bits));
cc875c2e
YM		 959
960 /* Unmask deasserted attentions in IGU */
1a635e48 961 aeu_mask = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE);
cc875c2e
YM		 962 aeu_mask |= (deasserted_bits & ATTN_BITS_MASKABLE);
963 qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, aeu_mask);
964
965 /* Clear deassertion from inner state */
966 sb_attn_sw->known_attn &= ~deasserted_bits;
967
0d956e8a 968 return rc;
cc875c2e
YM		 969}
970
971static int qed_int_attentions(struct qed_hwfn *p_hwfn)
972{
973 struct qed_sb_attn_info *p_sb_attn_sw = p_hwfn->p_sb_attn;
974 struct atten_status_block *p_sb_attn = p_sb_attn_sw->sb_attn;
975 u32 attn_bits = 0, attn_acks = 0;
976 u16 asserted_bits, deasserted_bits;
977 __le16 index;
978 int rc = 0;
979
980 /* Read current attention bits/acks - safeguard against attentions
981 * by guaranting work on a synchronized timeframe
982 */
983 do {
984 index = p_sb_attn->sb_index;
985 attn_bits = le32_to_cpu(p_sb_attn->atten_bits);
986 attn_acks = le32_to_cpu(p_sb_attn->atten_ack);
987 } while (index != p_sb_attn->sb_index);
988 p_sb_attn->sb_index = index;
989
990 /* Attention / Deassertion are meaningful (and in correct state)
991 * only when they differ and consistent with known state - deassertion
992 * when previous attention & current ack, and assertion when current
993 * attention with no previous attention
994 */
995 asserted_bits = (attn_bits & ~attn_acks & ATTN_STATE_BITS) &
996 ~p_sb_attn_sw->known_attn;
997 deasserted_bits = (~attn_bits & attn_acks & ATTN_STATE_BITS) &
998 p_sb_attn_sw->known_attn;
999
1000 if ((asserted_bits & ~0x100) || (deasserted_bits & ~0x100)) {
1001 DP_INFO(p_hwfn,
1002 "Attention: Index: 0x%04x, Bits: 0x%08x, Acks: 0x%08x, asserted: 0x%04x, De-asserted 0x%04x [Prev. known: 0x%04x]\n",
1003 index, attn_bits, attn_acks, asserted_bits,
1004 deasserted_bits, p_sb_attn_sw->known_attn);
1005 } else if (asserted_bits == 0x100) {
1a635e48 1006 DP_INFO(p_hwfn, "MFW indication via attention\n");
cc875c2e
YM		 1007 } else {
1008 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
1009 "MFW indication [deassertion]\n");
1010 }
1011
1012 if (asserted_bits) {
1013 rc = qed_int_assertion(p_hwfn, asserted_bits);
1014 if (rc)
1015 return rc;
1016 }
1017
1a635e48 1018 if (deasserted_bits)
cc875c2e 1019 rc = qed_int_deassertion(p_hwfn, deasserted_bits);
cc875c2e
YM		 1020
1021 return rc;
1022}
1023
1024static void qed_sb_ack_attn(struct qed_hwfn *p_hwfn,
1a635e48 1025 void __iomem *igu_addr, u32 ack_cons)
cc875c2e
YM		 1026{
1027 struct igu_prod_cons_update igu_ack = { 0 };
1028
1029 igu_ack.sb_id_and_flags =
1030 ((ack_cons << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) |
1031 (1 << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) |
1032 (IGU_INT_NOP << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) |
1033 (IGU_SEG_ACCESS_ATTN <<
1034 IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT));
1035
1036 DIRECT_REG_WR(igu_addr, igu_ack.sb_id_and_flags);
1037
1038 /* Both segments (interrupts & acks) are written to same place address;
1039 * Need to guarantee all commands will be received (in-order) by HW.
1040 */
1041 mmiowb();
1042 barrier();
1043}
1044
fe56b9e6
YM		 1045void qed_int_sp_dpc(unsigned long hwfn_cookie)
1046{
1047 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)hwfn_cookie;
1048 struct qed_pi_info *pi_info = NULL;
cc875c2e 1049 struct qed_sb_attn_info *sb_attn;
fe56b9e6
YM		 1050 struct qed_sb_info *sb_info;
1051 int arr_size;
1052 u16 rc = 0;
1053
fe56b9e6
YM		 1054 if (!p_hwfn->p_sp_sb) {
1055 DP_ERR(p_hwfn->cdev, "DPC called - no p_sp_sb\n");
1056 return;
1057 }
1058
1059 sb_info = &p_hwfn->p_sp_sb->sb_info;
1060 arr_size = ARRAY_SIZE(p_hwfn->p_sp_sb->pi_info_arr);
1061 if (!sb_info) {
1062 DP_ERR(p_hwfn->cdev,
1063 "Status block is NULL - cannot ack interrupts\n");
1064 return;
1065 }
1066
cc875c2e
YM		 1067 if (!p_hwfn->p_sb_attn) {
1068 DP_ERR(p_hwfn->cdev, "DPC called - no p_sb_attn");
1069 return;
1070 }
1071 sb_attn = p_hwfn->p_sb_attn;
1072
fe56b9e6
YM		 1073 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "DPC Called! (hwfn %p %d)\n",
1074 p_hwfn, p_hwfn->my_id);
1075
1076 /* Disable ack for def status block. Required both for msix +
1077 * inta in non-mask mode, in inta does no harm.
1078 */
1079 qed_sb_ack(sb_info, IGU_INT_DISABLE, 0);
1080
1081 /* Gather Interrupts/Attentions information */
1082 if (!sb_info->sb_virt) {
1a635e48
YM		 1083 DP_ERR(p_hwfn->cdev,
1084 "Interrupt Status block is NULL - cannot check for new interrupts!\n");
fe56b9e6
YM		 1085 } else {
1086 u32 tmp_index = sb_info->sb_ack;
1087
1088 rc = qed_sb_update_sb_idx(sb_info);
1089 DP_VERBOSE(p_hwfn->cdev, NETIF_MSG_INTR,
1090 "Interrupt indices: 0x%08x --> 0x%08x\n",
1091 tmp_index, sb_info->sb_ack);
1092 }
1093
cc875c2e 1094 if (!sb_attn || !sb_attn->sb_attn) {
1a635e48
YM		 1095 DP_ERR(p_hwfn->cdev,
1096 "Attentions Status block is NULL - cannot check for new attentions!\n");
cc875c2e
YM		 1097 } else {
1098 u16 tmp_index = sb_attn->index;
1099
1100 rc |= qed_attn_update_idx(p_hwfn, sb_attn);
1101 DP_VERBOSE(p_hwfn->cdev, NETIF_MSG_INTR,
1102 "Attention indices: 0x%08x --> 0x%08x\n",
1103 tmp_index, sb_attn->index);
1104 }
1105
fe56b9e6
YM		 1106 /* Check if we expect interrupts at this time. if not just ack them */
1107 if (!(rc & QED_SB_EVENT_MASK)) {
1108 qed_sb_ack(sb_info, IGU_INT_ENABLE, 1);
1109 return;
1110 }
1111
1112 /* Check the validity of the DPC ptt. If not ack interrupts and fail */
1113 if (!p_hwfn->p_dpc_ptt) {
1114 DP_NOTICE(p_hwfn->cdev, "Failed to allocate PTT\n");
1115 qed_sb_ack(sb_info, IGU_INT_ENABLE, 1);
1116 return;
1117 }
1118
cc875c2e
YM		 1119 if (rc & QED_SB_ATT_IDX)
1120 qed_int_attentions(p_hwfn);
1121
fe56b9e6
YM		 1122 if (rc & QED_SB_IDX) {
1123 int pi;
1124
1125 /* Look for a free index */
1126 for (pi = 0; pi < arr_size; pi++) {
1127 pi_info = &p_hwfn->p_sp_sb->pi_info_arr[pi];
1128 if (pi_info->comp_cb)
1129 pi_info->comp_cb(p_hwfn, pi_info->cookie);
1130 }
1131 }
1132
cc875c2e
YM		 1133 if (sb_attn && (rc & QED_SB_ATT_IDX))
1134 /* This should be done before the interrupts are enabled,
1135 * since otherwise a new attention will be generated.
1136 */
1137 qed_sb_ack_attn(p_hwfn, sb_info->igu_addr, sb_attn->index);
1138
fe56b9e6
YM		 1139 qed_sb_ack(sb_info, IGU_INT_ENABLE, 1);
1140}
1141
cc875c2e
YM		 1142static void qed_int_sb_attn_free(struct qed_hwfn *p_hwfn)
1143{
4ac801b7
YM		 1144 struct qed_sb_attn_info *p_sb = p_hwfn->p_sb_attn;
1145
1146 if (!p_sb)
1147 return;
1148
1149 if (p_sb->sb_attn)
1150 dma_free_coherent(&p_hwfn->cdev->pdev->dev,
1151 SB_ATTN_ALIGNED_SIZE(p_hwfn),
1a635e48 1152 p_sb->sb_attn, p_sb->sb_phys);
4ac801b7 1153 kfree(p_sb);
3587cb87 1154 p_hwfn->p_sb_attn = NULL;
cc875c2e
YM		 1155}
1156
1157static void qed_int_sb_attn_setup(struct qed_hwfn *p_hwfn,
1158 struct qed_ptt *p_ptt)
1159{
1160 struct qed_sb_attn_info *sb_info = p_hwfn->p_sb_attn;
1161
1162 memset(sb_info->sb_attn, 0, sizeof(*sb_info->sb_attn));
1163
1164 sb_info->index = 0;
1165 sb_info->known_attn = 0;
1166
1167 /* Configure Attention Status Block in IGU */
1168 qed_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_L,
1169 lower_32_bits(p_hwfn->p_sb_attn->sb_phys));
1170 qed_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_H,
1171 upper_32_bits(p_hwfn->p_sb_attn->sb_phys));
1172}
1173
1174static void qed_int_sb_attn_init(struct qed_hwfn *p_hwfn,
1175 struct qed_ptt *p_ptt,
1a635e48 1176 void *sb_virt_addr, dma_addr_t sb_phy_addr)
cc875c2e
YM		 1177{
1178 struct qed_sb_attn_info *sb_info = p_hwfn->p_sb_attn;
0d956e8a 1179 int i, j, k;
cc875c2e
YM		 1180
1181 sb_info->sb_attn = sb_virt_addr;
1182 sb_info->sb_phys = sb_phy_addr;
1183
0d956e8a
YM		 1184 /* Set the pointer to the AEU descriptors */
1185 sb_info->p_aeu_desc = aeu_descs;
1186
1187 /* Calculate Parity Masks */
1188 memset(sb_info->parity_mask, 0, sizeof(u32) * NUM_ATTN_REGS);
1189 for (i = 0; i < NUM_ATTN_REGS; i++) {
1190 /* j is array index, k is bit index */
1191 for (j = 0, k = 0; k < 32; j++) {
ba36f718 1192 struct aeu_invert_reg_bit *p_aeu;
0d956e8a 1193
ba36f718
MY		 1194 p_aeu = &aeu_descs[i].bits[j];
1195 if (qed_int_is_parity_flag(p_hwfn, p_aeu))
0d956e8a
YM		 1196 sb_info->parity_mask[i] |= 1 << k;
1197
ba36f718 1198 k += ATTENTION_LENGTH(p_aeu->flags);
0d956e8a
YM		 1199 }
1200 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
1201 "Attn Mask [Reg %d]: 0x%08x\n",
1202 i, sb_info->parity_mask[i]);
1203 }
1204
cc875c2e
YM		 1205 /* Set the address of cleanup for the mcp attention */
1206 sb_info->mfw_attn_addr = (p_hwfn->rel_pf_id << 3) +
1207 MISC_REG_AEU_GENERAL_ATTN_0;
1208
1209 qed_int_sb_attn_setup(p_hwfn, p_ptt);
1210}
1211
1212static int qed_int_sb_attn_alloc(struct qed_hwfn *p_hwfn,
1213 struct qed_ptt *p_ptt)
1214{
1215 struct qed_dev *cdev = p_hwfn->cdev;
1216 struct qed_sb_attn_info *p_sb;
cc875c2e 1217 dma_addr_t p_phys = 0;
1a635e48 1218 void *p_virt;
cc875c2e
YM		 1219
1220 /* SB struct */
60fffb3b 1221 p_sb = kmalloc(sizeof(*p_sb), GFP_KERNEL);
2591c280 1222 if (!p_sb)
cc875c2e 1223 return -ENOMEM;
cc875c2e
YM		 1224
1225 /* SB ring */
1226 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
1227 SB_ATTN_ALIGNED_SIZE(p_hwfn),
1228 &p_phys, GFP_KERNEL);
1229
1230 if (!p_virt) {
cc875c2e
YM		 1231 kfree(p_sb);
1232 return -ENOMEM;
1233 }
1234
1235 /* Attention setup */
1236 p_hwfn->p_sb_attn = p_sb;
1237 qed_int_sb_attn_init(p_hwfn, p_ptt, p_virt, p_phys);
1238
1239 return 0;
1240}
1241
fe56b9e6
YM		 1242/* coalescing timeout = timeset << (timer_res + 1) */
1243#define QED_CAU_DEF_RX_USECS 24
1244#define QED_CAU_DEF_TX_USECS 48
1245
1246void qed_init_cau_sb_entry(struct qed_hwfn *p_hwfn,
1247 struct cau_sb_entry *p_sb_entry,
1a635e48 1248 u8 pf_id, u16 vf_number, u8 vf_valid)
fe56b9e6 1249{
4ac801b7 1250 struct qed_dev *cdev = p_hwfn->cdev;
fe56b9e6 1251 u32 cau_state;
722003ac 1252 u8 timer_res;
fe56b9e6
YM		 1253
1254 memset(p_sb_entry, 0, sizeof(*p_sb_entry));
1255
1256 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_PF_NUMBER, pf_id);
1257 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_VF_NUMBER, vf_number);
1258 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_VF_VALID, vf_valid);
1259 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_SB_TIMESET0, 0x7F);
1260 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_SB_TIMESET1, 0x7F);
1261
fe56b9e6
YM		 1262 cau_state = CAU_HC_DISABLE_STATE;
1263
4ac801b7 1264 if (cdev->int_coalescing_mode == QED_COAL_MODE_ENABLE) {
fe56b9e6 1265 cau_state = CAU_HC_ENABLE_STATE;
4ac801b7
YM		 1266 if (!cdev->rx_coalesce_usecs)
1267 cdev->rx_coalesce_usecs = QED_CAU_DEF_RX_USECS;
1268 if (!cdev->tx_coalesce_usecs)
1269 cdev->tx_coalesce_usecs = QED_CAU_DEF_TX_USECS;
fe56b9e6
YM		 1270 }
1271
722003ac
SRK		 1272 /* Coalesce = (timeset << timer-res), timeset is 7bit wide */
1273 if (cdev->rx_coalesce_usecs <= 0x7F)
1274 timer_res = 0;
1275 else if (cdev->rx_coalesce_usecs <= 0xFF)
1276 timer_res = 1;
1277 else
1278 timer_res = 2;
1279 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES0, timer_res);
1280
1281 if (cdev->tx_coalesce_usecs <= 0x7F)
1282 timer_res = 0;
1283 else if (cdev->tx_coalesce_usecs <= 0xFF)
1284 timer_res = 1;
1285 else
1286 timer_res = 2;
1287 SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES1, timer_res);
1288
fe56b9e6
YM		 1289 SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE0, cau_state);
1290 SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE1, cau_state);
1291}
1292
1293void qed_int_cau_conf_sb(struct qed_hwfn *p_hwfn,
1294 struct qed_ptt *p_ptt,
1295 dma_addr_t sb_phys,
1a635e48 1296 u16 igu_sb_id, u16 vf_number, u8 vf_valid)
fe56b9e6
YM		 1297{
1298 struct cau_sb_entry sb_entry;
fe56b9e6
YM		 1299
1300 qed_init_cau_sb_entry(p_hwfn, &sb_entry, p_hwfn->rel_pf_id,
1301 vf_number, vf_valid);
1302
1303 if (p_hwfn->hw_init_done) {
0a0c5d3b
YM		 1304 /* Wide-bus, initialize via DMAE */
1305 u64 phys_addr = (u64)sb_phys;
1306
1307 qed_dmae_host2grc(p_hwfn, p_ptt, (u64)(uintptr_t)&phys_addr,
1308 CAU_REG_SB_ADDR_MEMORY +
1309 igu_sb_id * sizeof(u64), 2, 0);
1310 qed_dmae_host2grc(p_hwfn, p_ptt, (u64)(uintptr_t)&sb_entry,
1311 CAU_REG_SB_VAR_MEMORY +
1312 igu_sb_id * sizeof(u64), 2, 0);
fe56b9e6
YM		 1313 } else {
1314 /* Initialize Status Block Address */
1315 STORE_RT_REG_AGG(p_hwfn,
1316 CAU_REG_SB_ADDR_MEMORY_RT_OFFSET +
1317 igu_sb_id * 2,
1318 sb_phys);
1319
1320 STORE_RT_REG_AGG(p_hwfn,
1321 CAU_REG_SB_VAR_MEMORY_RT_OFFSET +
1322 igu_sb_id * 2,
1323 sb_entry);
1324 }
1325
1326 /* Configure pi coalescing if set */
1327 if (p_hwfn->cdev->int_coalescing_mode == QED_COAL_MODE_ENABLE) {
b5a9ee7c 1328 u8 num_tc = p_hwfn->hw_info.num_hw_tc;
722003ac 1329 u8 timeset, timer_res;
b5a9ee7c 1330 u8 i;
fe56b9e6 1331
722003ac
SRK		 1332 /* timeset = (coalesce >> timer-res), timeset is 7bit wide */
1333 if (p_hwfn->cdev->rx_coalesce_usecs <= 0x7F)
1334 timer_res = 0;
1335 else if (p_hwfn->cdev->rx_coalesce_usecs <= 0xFF)
1336 timer_res = 1;
1337 else
1338 timer_res = 2;
1339 timeset = (u8)(p_hwfn->cdev->rx_coalesce_usecs >> timer_res);
fe56b9e6 1340 qed_int_cau_conf_pi(p_hwfn, p_ptt, igu_sb_id, RX_PI,
1a635e48 1341 QED_COAL_RX_STATE_MACHINE, timeset);
fe56b9e6 1342
722003ac
SRK		 1343 if (p_hwfn->cdev->tx_coalesce_usecs <= 0x7F)
1344 timer_res = 0;
1345 else if (p_hwfn->cdev->tx_coalesce_usecs <= 0xFF)
1346 timer_res = 1;
1347 else
1348 timer_res = 2;
1349 timeset = (u8)(p_hwfn->cdev->tx_coalesce_usecs >> timer_res);
fe56b9e6
YM		 1350 for (i = 0; i < num_tc; i++) {
1351 qed_int_cau_conf_pi(p_hwfn, p_ptt,
1352 igu_sb_id, TX_PI(i),
1353 QED_COAL_TX_STATE_MACHINE,
1354 timeset);
1355 }
1356 }
1357}
1358
1359void qed_int_cau_conf_pi(struct qed_hwfn *p_hwfn,
1360 struct qed_ptt *p_ptt,
1361 u16 igu_sb_id,
1362 u32 pi_index,
1363 enum qed_coalescing_fsm coalescing_fsm,
1364 u8 timeset)
1365{
1366 struct cau_pi_entry pi_entry;
1a635e48 1367 u32 sb_offset, pi_offset;
fe56b9e6 1368
1408cc1f
YM		 1369 if (IS_VF(p_hwfn->cdev))
1370 return;
1371
fe56b9e6
YM		 1372 sb_offset = igu_sb_id * PIS_PER_SB;
1373 memset(&pi_entry, 0, sizeof(struct cau_pi_entry));
1374
1375 SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_PI_TIMESET, timeset);
1376 if (coalescing_fsm == QED_COAL_RX_STATE_MACHINE)
1377 SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_FSM_SEL, 0);
1378 else
1379 SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_FSM_SEL, 1);
1380
1381 pi_offset = sb_offset + pi_index;
1382 if (p_hwfn->hw_init_done) {
1383 qed_wr(p_hwfn, p_ptt,
1384 CAU_REG_PI_MEMORY + pi_offset * sizeof(u32),
1385 *((u32 *)&(pi_entry)));
1386 } else {
1387 STORE_RT_REG(p_hwfn,
1388 CAU_REG_PI_MEMORY_RT_OFFSET + pi_offset,
1389 *((u32 *)&(pi_entry)));
1390 }
1391}
1392
1393void qed_int_sb_setup(struct qed_hwfn *p_hwfn,
1a635e48 1394 struct qed_ptt *p_ptt, struct qed_sb_info *sb_info)
fe56b9e6
YM		 1395{
1396 /* zero status block and ack counter */
1397 sb_info->sb_ack = 0;
1398 memset(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt));
1399
1408cc1f
YM		 1400 if (IS_PF(p_hwfn->cdev))
1401 qed_int_cau_conf_sb(p_hwfn, p_ptt, sb_info->sb_phys,
1402 sb_info->igu_sb_id, 0, 0);
fe56b9e6
YM		 1403}
1404
1405/**
1406 * @brief qed_get_igu_sb_id - given a sw sb_id return the
1407 * igu_sb_id
1408 *
1409 * @param p_hwfn
1410 * @param sb_id
1411 *
1412 * @return u16
1413 */
1a635e48 1414static u16 qed_get_igu_sb_id(struct qed_hwfn *p_hwfn, u16 sb_id)
fe56b9e6
YM		 1415{
1416 u16 igu_sb_id;
1417
1418 /* Assuming continuous set of IGU SBs dedicated for given PF */
1419 if (sb_id == QED_SP_SB_ID)
1420 igu_sb_id = p_hwfn->hw_info.p_igu_info->igu_dsb_id;
1408cc1f 1421 else if (IS_PF(p_hwfn->cdev))
fe56b9e6 1422 igu_sb_id = sb_id + p_hwfn->hw_info.p_igu_info->igu_base_sb;
1408cc1f
YM		 1423 else
1424 igu_sb_id = qed_vf_get_igu_sb_id(p_hwfn, sb_id);
fe56b9e6 1425
525ef5c0
YM		 1426 if (sb_id == QED_SP_SB_ID)
1427 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
1428 "Slowpath SB index in IGU is 0x%04x\n", igu_sb_id);
1429 else
1430 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
1431 "SB [%04x] <--> IGU SB [%04x]\n", sb_id, igu_sb_id);
fe56b9e6
YM		 1432
1433 return igu_sb_id;
1434}
1435
1436int qed_int_sb_init(struct qed_hwfn *p_hwfn,
1437 struct qed_ptt *p_ptt,
1438 struct qed_sb_info *sb_info,
1a635e48 1439 void *sb_virt_addr, dma_addr_t sb_phy_addr, u16 sb_id)
fe56b9e6
YM		 1440{
1441 sb_info->sb_virt = sb_virt_addr;
1442 sb_info->sb_phys = sb_phy_addr;
1443
1444 sb_info->igu_sb_id = qed_get_igu_sb_id(p_hwfn, sb_id);
1445
1446 if (sb_id != QED_SP_SB_ID) {
1447 p_hwfn->sbs_info[sb_id] = sb_info;
1448 p_hwfn->num_sbs++;
1449 }
1450
1451 sb_info->cdev = p_hwfn->cdev;
1452
1453 /* The igu address will hold the absolute address that needs to be
1454 * written to for a specific status block
1455 */
1408cc1f
YM		 1456 if (IS_PF(p_hwfn->cdev)) {
1457 sb_info->igu_addr = (u8 __iomem *)p_hwfn->regview +
1458 GTT_BAR0_MAP_REG_IGU_CMD +
1459 (sb_info->igu_sb_id << 3);
1460 } else {
1461 sb_info->igu_addr = (u8 __iomem *)p_hwfn->regview +
1462 PXP_VF_BAR0_START_IGU +
1463 ((IGU_CMD_INT_ACK_BASE +
1464 sb_info->igu_sb_id) << 3);
1465 }
fe56b9e6
YM		 1466
1467 sb_info->flags |= QED_SB_INFO_INIT;
1468
1469 qed_int_sb_setup(p_hwfn, p_ptt, sb_info);
1470
1471 return 0;
1472}
1473
1474int qed_int_sb_release(struct qed_hwfn *p_hwfn,
1a635e48 1475 struct qed_sb_info *sb_info, u16 sb_id)
fe56b9e6
YM		 1476{
1477 if (sb_id == QED_SP_SB_ID) {
1478 DP_ERR(p_hwfn, "Do Not free sp sb using this function");
1479 return -EINVAL;
1480 }
1481
1482 /* zero status block and ack counter */
1483 sb_info->sb_ack = 0;
1484 memset(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt));
1485
4ac801b7
YM		 1486 if (p_hwfn->sbs_info[sb_id] != NULL) {
1487 p_hwfn->sbs_info[sb_id] = NULL;
1488 p_hwfn->num_sbs--;
1489 }
fe56b9e6
YM		 1490
1491 return 0;
1492}
1493
1494static void qed_int_sp_sb_free(struct qed_hwfn *p_hwfn)
1495{
1496 struct qed_sb_sp_info *p_sb = p_hwfn->p_sp_sb;
1497
4ac801b7
YM		 1498 if (!p_sb)
1499 return;
1500
1501 if (p_sb->sb_info.sb_virt)
1502 dma_free_coherent(&p_hwfn->cdev->pdev->dev,
1503 SB_ALIGNED_SIZE(p_hwfn),
1504 p_sb->sb_info.sb_virt,
1505 p_sb->sb_info.sb_phys);
1506 kfree(p_sb);
3587cb87 1507 p_hwfn->p_sp_sb = NULL;
fe56b9e6
YM		 1508}
1509
1a635e48 1510static int qed_int_sp_sb_alloc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
fe56b9e6
YM		 1511{
1512 struct qed_sb_sp_info *p_sb;
1513 dma_addr_t p_phys = 0;
1514 void *p_virt;
1515
1516 /* SB struct */
60fffb3b 1517 p_sb = kmalloc(sizeof(*p_sb), GFP_KERNEL);
2591c280 1518 if (!p_sb)
fe56b9e6 1519 return -ENOMEM;
fe56b9e6
YM		 1520
1521 /* SB ring */
1522 p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
1523 SB_ALIGNED_SIZE(p_hwfn),
1524 &p_phys, GFP_KERNEL);
1525 if (!p_virt) {
fe56b9e6
YM		 1526 kfree(p_sb);
1527 return -ENOMEM;
1528 }
1529
1530 /* Status Block setup */
1531 p_hwfn->p_sp_sb = p_sb;
1532 qed_int_sb_init(p_hwfn, p_ptt, &p_sb->sb_info, p_virt,
1533 p_phys, QED_SP_SB_ID);
1534
1535 memset(p_sb->pi_info_arr, 0, sizeof(p_sb->pi_info_arr));
1536
1537 return 0;
1538}
1539
fe56b9e6
YM		 1540int qed_int_register_cb(struct qed_hwfn *p_hwfn,
1541 qed_int_comp_cb_t comp_cb,
1a635e48 1542 void *cookie, u8 *sb_idx, __le16 **p_fw_cons)
fe56b9e6
YM		 1543{
1544 struct qed_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb;
4ac801b7 1545 int rc = -ENOMEM;
fe56b9e6
YM		 1546 u8 pi;
1547
1548 /* Look for a free index */
1549 for (pi = 0; pi < ARRAY_SIZE(p_sp_sb->pi_info_arr); pi++) {
4ac801b7
YM		 1550 if (p_sp_sb->pi_info_arr[pi].comp_cb)
1551 continue;
1552
1553 p_sp_sb->pi_info_arr[pi].comp_cb = comp_cb;
1554 p_sp_sb->pi_info_arr[pi].cookie = cookie;
1555 *sb_idx = pi;
1556 *p_fw_cons = &p_sp_sb->sb_info.sb_virt->pi_array[pi];
1557 rc = 0;
1558 break;
fe56b9e6
YM		 1559 }
1560
4ac801b7 1561 return rc;
fe56b9e6
YM		 1562}
1563
1564int qed_int_unregister_cb(struct qed_hwfn *p_hwfn, u8 pi)
1565{
1566 struct qed_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb;
fe56b9e6 1567
4ac801b7
YM		 1568 if (p_sp_sb->pi_info_arr[pi].comp_cb == NULL)
1569 return -ENOMEM;
fe56b9e6 1570
4ac801b7
YM		 1571 p_sp_sb->pi_info_arr[pi].comp_cb = NULL;
1572 p_sp_sb->pi_info_arr[pi].cookie = NULL;
1573
1574 return 0;
fe56b9e6
YM		 1575}
1576
1577u16 qed_int_get_sp_sb_id(struct qed_hwfn *p_hwfn)
1578{
1579 return p_hwfn->p_sp_sb->sb_info.igu_sb_id;
1580}
1581
1582void qed_int_igu_enable_int(struct qed_hwfn *p_hwfn,
1a635e48 1583 struct qed_ptt *p_ptt, enum qed_int_mode int_mode)
fe56b9e6 1584{
cc875c2e 1585 u32 igu_pf_conf = IGU_PF_CONF_FUNC_EN | IGU_PF_CONF_ATTN_BIT_EN;
fe56b9e6
YM		 1586
1587 p_hwfn->cdev->int_mode = int_mode;
1588 switch (p_hwfn->cdev->int_mode) {
1589 case QED_INT_MODE_INTA:
1590 igu_pf_conf |= IGU_PF_CONF_INT_LINE_EN;
1591 igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
1592 break;
1593
1594 case QED_INT_MODE_MSI:
1595 igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN;
1596 igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
1597 break;
1598
1599 case QED_INT_MODE_MSIX:
1600 igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN;
1601 break;
1602 case QED_INT_MODE_POLL:
1603 break;
1604 }
1605
1606 qed_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, igu_pf_conf);
1607}
1608
8f16bc97
SK		 1609int qed_int_igu_enable(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
1610 enum qed_int_mode int_mode)
fe56b9e6 1611{
fea24857 1612 int rc = 0;
fe56b9e6 1613
0d956e8a
YM		 1614 /* Configure AEU signal change to produce attentions */
1615 qed_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ENABLE, 0);
cc875c2e
YM		 1616 qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0xfff);
1617 qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0xfff);
0d956e8a 1618 qed_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ENABLE, 0xfff);
cc875c2e 1619
fe56b9e6
YM		 1620 /* Flush the writes to IGU */
1621 mmiowb();
cc875c2e
YM		 1622
1623 /* Unmask AEU signals toward IGU */
1624 qed_wr(p_hwfn, p_ptt, MISC_REG_AEU_MASK_ATTN_IGU, 0xff);
8f16bc97
SK		 1625 if ((int_mode != QED_INT_MODE_INTA) || IS_LEAD_HWFN(p_hwfn)) {
1626 rc = qed_slowpath_irq_req(p_hwfn);
1a635e48 1627 if (rc) {
8f16bc97
SK		 1628 DP_NOTICE(p_hwfn, "Slowpath IRQ request failed\n");
1629 return -EINVAL;
1630 }
1631 p_hwfn->b_int_requested = true;
1632 }
1633 /* Enable interrupt Generation */
1634 qed_int_igu_enable_int(p_hwfn, p_ptt, int_mode);
1635 p_hwfn->b_int_enabled = 1;
1636
1637 return rc;
fe56b9e6
YM		 1638}
1639
1a635e48 1640void qed_int_igu_disable_int(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
fe56b9e6
YM		 1641{
1642 p_hwfn->b_int_enabled = 0;
1643
1408cc1f
YM		 1644 if (IS_VF(p_hwfn->cdev))
1645 return;
1646
fe56b9e6
YM		 1647 qed_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, 0);
1648}
1649
1650#define IGU_CLEANUP_SLEEP_LENGTH (1000)
b2b897eb
YM		 1651static void qed_int_igu_cleanup_sb(struct qed_hwfn *p_hwfn,
1652 struct qed_ptt *p_ptt,
1653 u32 sb_id, bool cleanup_set, u16 opaque_fid)
fe56b9e6 1654{
b2b897eb 1655 u32 cmd_ctrl = 0, val = 0, sb_bit = 0, sb_bit_addr = 0, data = 0;
fe56b9e6
YM		 1656 u32 pxp_addr = IGU_CMD_INT_ACK_BASE + sb_id;
1657 u32 sleep_cnt = IGU_CLEANUP_SLEEP_LENGTH;
fe56b9e6
YM		 1658
1659 /* Set the data field */
1660 SET_FIELD(data, IGU_CLEANUP_CLEANUP_SET, cleanup_set ? 1 : 0);
1661 SET_FIELD(data, IGU_CLEANUP_CLEANUP_TYPE, 0);
1662 SET_FIELD(data, IGU_CLEANUP_COMMAND_TYPE, IGU_COMMAND_TYPE_SET);
1663
1664 /* Set the control register */
1665 SET_FIELD(cmd_ctrl, IGU_CTRL_REG_PXP_ADDR, pxp_addr);
1666 SET_FIELD(cmd_ctrl, IGU_CTRL_REG_FID, opaque_fid);
1667 SET_FIELD(cmd_ctrl, IGU_CTRL_REG_TYPE, IGU_CTRL_CMD_TYPE_WR);
1668
1669 qed_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_32LSB_DATA, data);
1670
1671 barrier();
1672
1673 qed_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_CTRL, cmd_ctrl);
1674
1675 /* Flush the write to IGU */
1676 mmiowb();
1677
1678 /* calculate where to read the status bit from */
1679 sb_bit = 1 << (sb_id % 32);
1680 sb_bit_addr = sb_id / 32 * sizeof(u32);
1681
1682 sb_bit_addr += IGU_REG_CLEANUP_STATUS_0;
1683
1684 /* Now wait for the command to complete */
1685 do {
1686 val = qed_rd(p_hwfn, p_ptt, sb_bit_addr);
1687
1688 if ((val & sb_bit) == (cleanup_set ? sb_bit : 0))
1689 break;
1690
1691 usleep_range(5000, 10000);
1692 } while (--sleep_cnt);
1693
1694 if (!sleep_cnt)
1695 DP_NOTICE(p_hwfn,
1696 "Timeout waiting for clear status 0x%08x [for sb %d]\n",
1697 val, sb_id);
1698}
1699
1700void qed_int_igu_init_pure_rt_single(struct qed_hwfn *p_hwfn,
1701 struct qed_ptt *p_ptt,
b2b897eb 1702 u32 sb_id, u16 opaque, bool b_set)
fe56b9e6 1703{
b2b897eb 1704 int pi, i;
fe56b9e6
YM		 1705
1706 /* Set */
1707 if (b_set)
1708 qed_int_igu_cleanup_sb(p_hwfn, p_ptt, sb_id, 1, opaque);
1709
1710 /* Clear */
1711 qed_int_igu_cleanup_sb(p_hwfn, p_ptt, sb_id, 0, opaque);
1712
b2b897eb
YM		 1713 /* Wait for the IGU SB to cleanup */
1714 for (i = 0; i < IGU_CLEANUP_SLEEP_LENGTH; i++) {
1715 u32 val;
1716
1717 val = qed_rd(p_hwfn, p_ptt,
1718 IGU_REG_WRITE_DONE_PENDING + ((sb_id / 32) * 4));
1719 if (val & (1 << (sb_id % 32)))
1720 usleep_range(10, 20);
1721 else
1722 break;
1723 }
1724 if (i == IGU_CLEANUP_SLEEP_LENGTH)
1725 DP_NOTICE(p_hwfn,
1726 "Failed SB[0x%08x] still appearing in WRITE_DONE_PENDING\n",
1727 sb_id);
1728
fe56b9e6
YM		 1729 /* Clear the CAU for the SB */
1730 for (pi = 0; pi < 12; pi++)
1731 qed_wr(p_hwfn, p_ptt,
1732 CAU_REG_PI_MEMORY + (sb_id * 12 + pi) * 4, 0);
1733}
1734
1735void qed_int_igu_init_pure_rt(struct qed_hwfn *p_hwfn,
1736 struct qed_ptt *p_ptt,
b2b897eb 1737 bool b_set, bool b_slowpath)
fe56b9e6
YM		 1738{
1739 u32 igu_base_sb = p_hwfn->hw_info.p_igu_info->igu_base_sb;
1740 u32 igu_sb_cnt = p_hwfn->hw_info.p_igu_info->igu_sb_cnt;
b2b897eb 1741 u32 sb_id = 0, val = 0;
fe56b9e6
YM		 1742
1743 val = qed_rd(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION);
1744 val |= IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN;
1745 val &= ~IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN;
1746 qed_wr(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION, val);
1747
1748 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
1749 "IGU cleaning SBs [%d,...,%d]\n",
1750 igu_base_sb, igu_base_sb + igu_sb_cnt - 1);
1751
1752 for (sb_id = igu_base_sb; sb_id < igu_base_sb + igu_sb_cnt; sb_id++)
1753 qed_int_igu_init_pure_rt_single(p_hwfn, p_ptt, sb_id,
1754 p_hwfn->hw_info.opaque_fid,
1755 b_set);
1756
b2b897eb
YM		 1757 if (!b_slowpath)
1758 return;
1759
1760 sb_id = p_hwfn->hw_info.p_igu_info->igu_dsb_id;
1761 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
1762 "IGU cleaning slowpath SB [%d]\n", sb_id);
1763 qed_int_igu_init_pure_rt_single(p_hwfn, p_ptt, sb_id,
1764 p_hwfn->hw_info.opaque_fid, b_set);
fe56b9e6
YM		 1765}
1766
1a635e48
YM		 1767static u32 qed_int_igu_read_cam_block(struct qed_hwfn *p_hwfn,
1768 struct qed_ptt *p_ptt, u16 sb_id)
4ac801b7
YM		 1769{
1770 u32 val = qed_rd(p_hwfn, p_ptt,
1a635e48 1771 IGU_REG_MAPPING_MEMORY + sizeof(u32) * sb_id);
4ac801b7
YM		 1772 struct qed_igu_block *p_block;
1773
1774 p_block = &p_hwfn->hw_info.p_igu_info->igu_map.igu_blocks[sb_id];
1775
1776 /* stop scanning when hit first invalid PF entry */
1777 if (!GET_FIELD(val, IGU_MAPPING_LINE_VALID) &&
1778 GET_FIELD(val, IGU_MAPPING_LINE_PF_VALID))
1779 goto out;
1780
1781 /* Fill the block information */
1782 p_block->status = QED_IGU_STATUS_VALID;
1783 p_block->function_id = GET_FIELD(val,
1784 IGU_MAPPING_LINE_FUNCTION_NUMBER);
1785 p_block->is_pf = GET_FIELD(val, IGU_MAPPING_LINE_PF_VALID);
1786 p_block->vector_number = GET_FIELD(val,
1787 IGU_MAPPING_LINE_VECTOR_NUMBER);
1788
1789 DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
1790 "IGU_BLOCK: [SB 0x%04x, Value in CAM 0x%08x] func_id = %d is_pf = %d vector_num = 0x%x\n",
1791 sb_id, val, p_block->function_id,
1792 p_block->is_pf, p_block->vector_number);
1793
1794out:
1795 return val;
1796}
1797
1a635e48 1798int qed_int_igu_read_cam(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
fe56b9e6
YM		 1799{
1800 struct qed_igu_info *p_igu_info;
1408cc1f
YM		 1801 u32 val, min_vf = 0, max_vf = 0;
1802 u16 sb_id, last_iov_sb_id = 0;
fe56b9e6 1803 struct qed_igu_block *blk;
fe56b9e6
YM		 1804 u16 prev_sb_id = 0xFF;
1805
60fffb3b 1806 p_hwfn->hw_info.p_igu_info = kzalloc(sizeof(*p_igu_info), GFP_KERNEL);
fe56b9e6
YM		 1807 if (!p_hwfn->hw_info.p_igu_info)
1808 return -ENOMEM;
1809
1810 p_igu_info = p_hwfn->hw_info.p_igu_info;
1811
1408cc1f 1812 /* Initialize base sb / sb cnt for PFs and VFs */
fe56b9e6
YM		 1813 p_igu_info->igu_base_sb = 0xffff;
1814 p_igu_info->igu_sb_cnt = 0;
1815 p_igu_info->igu_dsb_id = 0xffff;
1816 p_igu_info->igu_base_sb_iov = 0xffff;
1817
1408cc1f
YM		 1818 if (p_hwfn->cdev->p_iov_info) {
1819 struct qed_hw_sriov_info *p_iov = p_hwfn->cdev->p_iov_info;
1820
1821 min_vf = p_iov->first_vf_in_pf;
1822 max_vf = p_iov->first_vf_in_pf + p_iov->total_vfs;
1823 }
1824
fe56b9e6
YM		 1825 for (sb_id = 0; sb_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev);
1826 sb_id++) {
1827 blk = &p_igu_info->igu_map.igu_blocks[sb_id];
1828
4ac801b7 1829 val = qed_int_igu_read_cam_block(p_hwfn, p_ptt, sb_id);
fe56b9e6
YM		 1830
1831 /* stop scanning when hit first invalid PF entry */
1832 if (!GET_FIELD(val, IGU_MAPPING_LINE_VALID) &&
1833 GET_FIELD(val, IGU_MAPPING_LINE_PF_VALID))
1834 break;
1835
fe56b9e6
YM		 1836 if (blk->is_pf) {
1837 if (blk->function_id == p_hwfn->rel_pf_id) {
1838 blk->status |= QED_IGU_STATUS_PF;
1839
1840 if (blk->vector_number == 0) {
1841 if (p_igu_info->igu_dsb_id == 0xffff)
1842 p_igu_info->igu_dsb_id = sb_id;
1843 } else {
1844 if (p_igu_info->igu_base_sb ==
1845 0xffff) {
1846 p_igu_info->igu_base_sb = sb_id;
1847 } else if (prev_sb_id != sb_id - 1) {
1848 DP_NOTICE(p_hwfn->cdev,
1849 "consecutive igu vectors for HWFN %x broken",
1850 p_hwfn->rel_pf_id);
1851 break;
1852 }
1853 prev_sb_id = sb_id;
1854 /* we don't count the default */
1855 (p_igu_info->igu_sb_cnt)++;
1856 }
1857 }
1408cc1f
YM		 1858 } else {
1859 if ((blk->function_id >= min_vf) &&
1860 (blk->function_id < max_vf)) {
1861 /* Available for VFs of this PF */
1862 if (p_igu_info->igu_base_sb_iov == 0xffff) {
1863 p_igu_info->igu_base_sb_iov = sb_id;
1864 } else if (last_iov_sb_id != sb_id - 1) {
1865 if (!val) {
1866 DP_VERBOSE(p_hwfn->cdev,
1867 NETIF_MSG_INTR,
1868 "First uninitialized IGU CAM entry at index 0x%04x\n",
1869 sb_id);
1870 } else {
1871 DP_NOTICE(p_hwfn->cdev,
1872 "Consecutive igu vectors for HWFN %x vfs is broken [jumps from %04x to %04x]\n",
1873 p_hwfn->rel_pf_id,
1874 last_iov_sb_id,
1875 sb_id); }
1876 break;
1877 }
1878 blk->status |= QED_IGU_STATUS_FREE;
1879 p_hwfn->hw_info.p_igu_info->free_blks++;
1880 last_iov_sb_id = sb_id;
1881 }
fe56b9e6
YM		 1882 }
1883 }
5a1f965a
MY		 1884
1885 /* There's a possibility the igu_sb_cnt_iov doesn't properly reflect
1886 * the number of VF SBs [especially for first VF on engine, as we can't
8ac1ed79 1887 * differentiate between empty entries and its entries].
5a1f965a
MY		 1888 * Since we don't really support more SBs than VFs today, prevent any
1889 * such configuration by sanitizing the number of SBs to equal the
1890 * number of VFs.
1891 */
1892 if (IS_PF_SRIOV(p_hwfn)) {
1893 u16 total_vfs = p_hwfn->cdev->p_iov_info->total_vfs;
1894
1895 if (total_vfs < p_igu_info->free_blks) {
1896 DP_VERBOSE(p_hwfn,
1897 (NETIF_MSG_INTR | QED_MSG_IOV),
1898 "Limiting number of SBs for IOV - %04x --> %04x\n",
1899 p_igu_info->free_blks,
1900 p_hwfn->cdev->p_iov_info->total_vfs);
1901 p_igu_info->free_blks = total_vfs;
1902 } else if (total_vfs > p_igu_info->free_blks) {
1903 DP_NOTICE(p_hwfn,
1904 "IGU has only %04x SBs for VFs while the device has %04x VFs\n",
1905 p_igu_info->free_blks, total_vfs);
1906 return -EINVAL;
1907 }
1908 }
1408cc1f
YM		 1909 p_igu_info->igu_sb_cnt_iov = p_igu_info->free_blks;
1910
1911 DP_VERBOSE(
1912 p_hwfn,
1913 NETIF_MSG_INTR,
1914 "IGU igu_base_sb=0x%x [IOV 0x%x] igu_sb_cnt=%d [IOV 0x%x] igu_dsb_id=0x%x\n",
1915 p_igu_info->igu_base_sb,
1916 p_igu_info->igu_base_sb_iov,
1917 p_igu_info->igu_sb_cnt,
1918 p_igu_info->igu_sb_cnt_iov,
1919 p_igu_info->igu_dsb_id);
fe56b9e6
YM		 1920
1921 if (p_igu_info->igu_base_sb == 0xffff ||
1922 p_igu_info->igu_dsb_id == 0xffff ||
1923 p_igu_info->igu_sb_cnt == 0) {
1924 DP_NOTICE(p_hwfn,
1925 "IGU CAM returned invalid values igu_base_sb=0x%x igu_sb_cnt=%d igu_dsb_id=0x%x\n",
1926 p_igu_info->igu_base_sb,
1927 p_igu_info->igu_sb_cnt,
1928 p_igu_info->igu_dsb_id);
1929 return -EINVAL;
1930 }
1931
1932 return 0;
1933}
1934
1935/**
1936 * @brief Initialize igu runtime registers
1937 *
1938 * @param p_hwfn
1939 */
1940void qed_int_igu_init_rt(struct qed_hwfn *p_hwfn)
1941{
1a635e48 1942 u32 igu_pf_conf = IGU_PF_CONF_FUNC_EN;
fe56b9e6
YM		 1943
1944 STORE_RT_REG(p_hwfn, IGU_REG_PF_CONFIGURATION_RT_OFFSET, igu_pf_conf);
1945}
1946
1947u64 qed_int_igu_read_sisr_reg(struct qed_hwfn *p_hwfn)
1948{
fe56b9e6
YM		 1949 u32 lsb_igu_cmd_addr = IGU_REG_SISR_MDPC_WMASK_LSB_UPPER -
1950 IGU_CMD_INT_ACK_BASE;
1951 u32 msb_igu_cmd_addr = IGU_REG_SISR_MDPC_WMASK_MSB_UPPER -
1952 IGU_CMD_INT_ACK_BASE;
1a635e48
YM		 1953 u32 intr_status_hi = 0, intr_status_lo = 0;
1954 u64 intr_status = 0;
fe56b9e6
YM		 1955
1956 intr_status_lo = REG_RD(p_hwfn,
1957 GTT_BAR0_MAP_REG_IGU_CMD +
1958 lsb_igu_cmd_addr * 8);
1959 intr_status_hi = REG_RD(p_hwfn,
1960 GTT_BAR0_MAP_REG_IGU_CMD +
1961 msb_igu_cmd_addr * 8);
1962 intr_status = ((u64)intr_status_hi << 32) + (u64)intr_status_lo;
1963
1964 return intr_status;
1965}
1966
1967static void qed_int_sp_dpc_setup(struct qed_hwfn *p_hwfn)
1968{
1969 tasklet_init(p_hwfn->sp_dpc,
1970 qed_int_sp_dpc, (unsigned long)p_hwfn);
1971 p_hwfn->b_sp_dpc_enabled = true;
1972}
1973
1974static int qed_int_sp_dpc_alloc(struct qed_hwfn *p_hwfn)
1975{
60fffb3b 1976 p_hwfn->sp_dpc = kmalloc(sizeof(*p_hwfn->sp_dpc), GFP_KERNEL);
fe56b9e6
YM		 1977 if (!p_hwfn->sp_dpc)
1978 return -ENOMEM;
1979
1980 return 0;
1981}
1982
1983static void qed_int_sp_dpc_free(struct qed_hwfn *p_hwfn)
1984{
1985 kfree(p_hwfn->sp_dpc);
3587cb87 1986 p_hwfn->sp_dpc = NULL;
fe56b9e6
YM		 1987}
1988
1a635e48 1989int qed_int_alloc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
fe56b9e6
YM		 1990{
1991 int rc = 0;
1992
1993 rc = qed_int_sp_dpc_alloc(p_hwfn);
2591c280 1994 if (rc)
fe56b9e6 1995 return rc;
2591c280 1996
fe56b9e6 1997 rc = qed_int_sp_sb_alloc(p_hwfn, p_ptt);
2591c280 1998 if (rc)
fe56b9e6 1999 return rc;
2591c280 2000
cc875c2e 2001 rc = qed_int_sb_attn_alloc(p_hwfn, p_ptt);
83aeb933 2002
fe56b9e6
YM		 2003 return rc;
2004}
2005
2006void qed_int_free(struct qed_hwfn *p_hwfn)
2007{
2008 qed_int_sp_sb_free(p_hwfn);
cc875c2e 2009 qed_int_sb_attn_free(p_hwfn);
fe56b9e6
YM		 2010 qed_int_sp_dpc_free(p_hwfn);
2011}
2012
1a635e48 2013void qed_int_setup(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
fe56b9e6 2014{
0d956e8a
YM		 2015 qed_int_sb_setup(p_hwfn, p_ptt, &p_hwfn->p_sp_sb->sb_info);
2016 qed_int_sb_attn_setup(p_hwfn, p_ptt);
fe56b9e6
YM		 2017 qed_int_sp_dpc_setup(p_hwfn);
2018}
2019
4ac801b7
YM		 2020void qed_int_get_num_sbs(struct qed_hwfn *p_hwfn,
2021 struct qed_sb_cnt_info *p_sb_cnt_info)
fe56b9e6
YM		 2022{
2023 struct qed_igu_info *info = p_hwfn->hw_info.p_igu_info;
2024
4ac801b7
YM		 2025 if (!info || !p_sb_cnt_info)
2026 return;
fe56b9e6 2027
4ac801b7
YM		 2028 p_sb_cnt_info->sb_cnt = info->igu_sb_cnt;
2029 p_sb_cnt_info->sb_iov_cnt = info->igu_sb_cnt_iov;
2030 p_sb_cnt_info->sb_free_blk = info->free_blks;
fe56b9e6 2031}
8f16bc97 2032
1408cc1f
YM		 2033u16 qed_int_queue_id_from_sb_id(struct qed_hwfn *p_hwfn, u16 sb_id)
2034{
2035 struct qed_igu_info *p_info = p_hwfn->hw_info.p_igu_info;
2036
2037 /* Determine origin of SB id */
2038 if ((sb_id >= p_info->igu_base_sb) &&
2039 (sb_id < p_info->igu_base_sb + p_info->igu_sb_cnt)) {
2040 return sb_id - p_info->igu_base_sb;
2041 } else if ((sb_id >= p_info->igu_base_sb_iov) &&
2042 (sb_id < p_info->igu_base_sb_iov + p_info->igu_sb_cnt_iov)) {
5a1f965a
MY		 2043 /* We want the first VF queue to be adjacent to the
2044 * last PF queue. Since L2 queues can be partial to
2045 * SBs, we'll use the feature instead.
2046 */
2047 return sb_id - p_info->igu_base_sb_iov +
2048 FEAT_NUM(p_hwfn, QED_PF_L2_QUE);
1408cc1f
YM		 2049 } else {
2050 DP_NOTICE(p_hwfn, "SB %d not in range for function\n", sb_id);
2051 return 0;
2052 }
2053}
2054
8f16bc97
SK		 2055void qed_int_disable_post_isr_release(struct qed_dev *cdev)
2056{
2057 int i;
2058
2059 for_each_hwfn(cdev, i)
2060 cdev->hwfns[i].b_int_requested = false;
2061}
722003ac
SRK		 2062
2063int qed_int_set_timer_res(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
2064 u8 timer_res, u16 sb_id, bool tx)
2065{
2066 struct cau_sb_entry sb_entry;
2067 int rc;
2068
2069 if (!p_hwfn->hw_init_done) {
2070 DP_ERR(p_hwfn, "hardware not initialized yet\n");
2071 return -EINVAL;
2072 }
2073
2074 rc = qed_dmae_grc2host(p_hwfn, p_ptt, CAU_REG_SB_VAR_MEMORY +
2075 sb_id * sizeof(u64),
2076 (u64)(uintptr_t)&sb_entry, 2, 0);
2077 if (rc) {
2078 DP_ERR(p_hwfn, "dmae_grc2host failed %d\n", rc);
2079 return rc;
2080 }
2081
2082 if (tx)
2083 SET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES1, timer_res);
2084 else
2085 SET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES0, timer_res);
2086
2087 rc = qed_dmae_host2grc(p_hwfn, p_ptt,
2088 (u64)(uintptr_t)&sb_entry,
2089 CAU_REG_SB_VAR_MEMORY +
2090 sb_id * sizeof(u64), 2, 0);
2091 if (rc) {
2092 DP_ERR(p_hwfn, "dmae_host2grc failed %d\n", rc);
2093 return rc;
2094 }
2095
2096 return rc;
2097}
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