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qed: Change metadata needed for SPQ entries
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / qlogic / qed / qed_l2.c
CommitLineData
25c089d7
YM		 1/* QLogic qed NIC Driver
2 * Copyright (c) 2015 QLogic Corporation
3 *
4 * This software is available under the terms of the GNU General Public License
5 * (GPL) Version 2, available from the file COPYING in the main directory of
6 * this source tree.
7 */
8
9#include <linux/types.h>
10#include <asm/byteorder.h>
11#include <asm/param.h>
12#include <linux/delay.h>
13#include <linux/dma-mapping.h>
14#include <linux/etherdevice.h>
15#include <linux/interrupt.h>
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/pci.h>
19#include <linux/slab.h>
20#include <linux/stddef.h>
21#include <linux/string.h>
22#include <linux/version.h>
23#include <linux/workqueue.h>
24#include <linux/bitops.h>
25#include <linux/bug.h>
26#include "qed.h"
27#include <linux/qed/qed_chain.h>
28#include "qed_cxt.h"
29#include "qed_dev_api.h"
30#include <linux/qed/qed_eth_if.h>
31#include "qed_hsi.h"
32#include "qed_hw.h"
33#include "qed_int.h"
34#include "qed_reg_addr.h"
35#include "qed_sp.h"
36
cee4d264
MC		 37enum qed_rss_caps {
38 QED_RSS_IPV4 = 0x1,
39 QED_RSS_IPV6 = 0x2,
40 QED_RSS_IPV4_TCP = 0x4,
41 QED_RSS_IPV6_TCP = 0x8,
42 QED_RSS_IPV4_UDP = 0x10,
43 QED_RSS_IPV6_UDP = 0x20,
44};
45
46/* Should be the same as ETH_RSS_IND_TABLE_ENTRIES_NUM */
47#define QED_RSS_IND_TABLE_SIZE 128
48#define QED_RSS_KEY_SIZE 10 /* size in 32b chunks */
49
50struct qed_rss_params {
51 u8 update_rss_config;
52 u8 rss_enable;
53 u8 rss_eng_id;
54 u8 update_rss_capabilities;
55 u8 update_rss_ind_table;
56 u8 update_rss_key;
57 u8 rss_caps;
58 u8 rss_table_size_log;
59 u16 rss_ind_table[QED_RSS_IND_TABLE_SIZE];
60 u32 rss_key[QED_RSS_KEY_SIZE];
61};
62
63enum qed_filter_opcode {
64 QED_FILTER_ADD,
65 QED_FILTER_REMOVE,
66 QED_FILTER_MOVE,
67 QED_FILTER_REPLACE, /* Delete all MACs and add new one instead */
68 QED_FILTER_FLUSH, /* Removes all filters */
69};
70
71enum qed_filter_ucast_type {
72 QED_FILTER_MAC,
73 QED_FILTER_VLAN,
74 QED_FILTER_MAC_VLAN,
75 QED_FILTER_INNER_MAC,
76 QED_FILTER_INNER_VLAN,
77 QED_FILTER_INNER_PAIR,
78 QED_FILTER_INNER_MAC_VNI_PAIR,
79 QED_FILTER_MAC_VNI_PAIR,
80 QED_FILTER_VNI,
81};
82
83struct qed_filter_ucast {
84 enum qed_filter_opcode opcode;
85 enum qed_filter_ucast_type type;
86 u8 is_rx_filter;
87 u8 is_tx_filter;
88 u8 vport_to_add_to;
89 u8 vport_to_remove_from;
90 unsigned char mac[ETH_ALEN];
91 u8 assert_on_error;
92 u16 vlan;
93 u32 vni;
94};
95
96struct qed_filter_mcast {
97 /* MOVE is not supported for multicast */
98 enum qed_filter_opcode opcode;
99 u8 vport_to_add_to;
100 u8 vport_to_remove_from;
101 u8 num_mc_addrs;
102#define QED_MAX_MC_ADDRS 64
103 unsigned char mac[QED_MAX_MC_ADDRS][ETH_ALEN];
104};
105
106struct qed_filter_accept_flags {
107 u8 update_rx_mode_config;
108 u8 update_tx_mode_config;
109 u8 rx_accept_filter;
110 u8 tx_accept_filter;
111#define QED_ACCEPT_NONE 0x01
112#define QED_ACCEPT_UCAST_MATCHED 0x02
113#define QED_ACCEPT_UCAST_UNMATCHED 0x04
114#define QED_ACCEPT_MCAST_MATCHED 0x08
115#define QED_ACCEPT_MCAST_UNMATCHED 0x10
116#define QED_ACCEPT_BCAST 0x20
117};
118
119struct qed_sp_vport_update_params {
120 u16 opaque_fid;
121 u8 vport_id;
122 u8 update_vport_active_rx_flg;
123 u8 vport_active_rx_flg;
124 u8 update_vport_active_tx_flg;
125 u8 vport_active_tx_flg;
126 u8 update_approx_mcast_flg;
3f9b4a69
YM		 127 u8 update_accept_any_vlan_flg;
128 u8 accept_any_vlan;
cee4d264
MC		 129 unsigned long bins[8];
130 struct qed_rss_params *rss_params;
131 struct qed_filter_accept_flags accept_flags;
132};
133
134#define QED_MAX_SGES_NUM 16
135#define CRC32_POLY 0x1edc6f41
136
137static int qed_sp_vport_start(struct qed_hwfn *p_hwfn,
138 u32 concrete_fid,
139 u16 opaque_fid,
140 u8 vport_id,
141 u16 mtu,
142 u8 drop_ttl0_flg,
143 u8 inner_vlan_removal_en_flg)
144{
cee4d264
MC		 145 struct vport_start_ramrod_data *p_ramrod = NULL;
146 struct qed_spq_entry *p_ent = NULL;
06f56b81 147 struct qed_sp_init_data init_data;
cee4d264
MC		 148 int rc = -EINVAL;
149 u16 rx_mode = 0;
150 u8 abs_vport_id = 0;
151
152 rc = qed_fw_vport(p_hwfn, vport_id, &abs_vport_id);
153 if (rc != 0)
154 return rc;
155
06f56b81
YM		 156 memset(&init_data, 0, sizeof(init_data));
157 init_data.cid = qed_spq_get_cid(p_hwfn);
158 init_data.opaque_fid = opaque_fid;
159 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
cee4d264
MC		 160
161 rc = qed_sp_init_request(p_hwfn, &p_ent,
cee4d264 162 ETH_RAMROD_VPORT_START,
06f56b81 163 PROTOCOLID_ETH, &init_data);
cee4d264
MC		 164 if (rc)
165 return rc;
166
167 p_ramrod = &p_ent->ramrod.vport_start;
168 p_ramrod->vport_id = abs_vport_id;
169
170 p_ramrod->mtu = cpu_to_le16(mtu);
171 p_ramrod->inner_vlan_removal_en = inner_vlan_removal_en_flg;
172 p_ramrod->drop_ttl0_en = drop_ttl0_flg;
173
174 SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_UCAST_DROP_ALL, 1);
175 SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_MCAST_DROP_ALL, 1);
176
177 p_ramrod->rx_mode.state = cpu_to_le16(rx_mode);
178
179 /* TPA related fields */
180 memset(&p_ramrod->tpa_param, 0,
181 sizeof(struct eth_vport_tpa_param));
182
183 /* Software Function ID in hwfn (PFs are 0 - 15, VFs are 16 - 135) */
184 p_ramrod->sw_fid = qed_concrete_to_sw_fid(p_hwfn->cdev,
185 concrete_fid);
186
187 return qed_spq_post(p_hwfn, p_ent, NULL);
188}
189
190static int
191qed_sp_vport_update_rss(struct qed_hwfn *p_hwfn,
192 struct vport_update_ramrod_data *p_ramrod,
193 struct qed_rss_params *p_params)
194{
195 struct eth_vport_rss_config *rss = &p_ramrod->rss_config;
196 u16 abs_l2_queue = 0, capabilities = 0;
197 int rc = 0, i;
198
199 if (!p_params) {
200 p_ramrod->common.update_rss_flg = 0;
201 return rc;
202 }
203
204 BUILD_BUG_ON(QED_RSS_IND_TABLE_SIZE !=
205 ETH_RSS_IND_TABLE_ENTRIES_NUM);
206
207 rc = qed_fw_rss_eng(p_hwfn, p_params->rss_eng_id, &rss->rss_id);
208 if (rc)
209 return rc;
210
211 p_ramrod->common.update_rss_flg = p_params->update_rss_config;
212 rss->update_rss_capabilities = p_params->update_rss_capabilities;
213 rss->update_rss_ind_table = p_params->update_rss_ind_table;
214 rss->update_rss_key = p_params->update_rss_key;
215
216 rss->rss_mode = p_params->rss_enable ?
217 ETH_VPORT_RSS_MODE_REGULAR :
218 ETH_VPORT_RSS_MODE_DISABLED;
219
220 SET_FIELD(capabilities,
221 ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY,
222 !!(p_params->rss_caps & QED_RSS_IPV4));
223 SET_FIELD(capabilities,
224 ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY,
225 !!(p_params->rss_caps & QED_RSS_IPV6));
226 SET_FIELD(capabilities,
227 ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY,
228 !!(p_params->rss_caps & QED_RSS_IPV4_TCP));
229 SET_FIELD(capabilities,
230 ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY,
231 !!(p_params->rss_caps & QED_RSS_IPV6_TCP));
232 SET_FIELD(capabilities,
233 ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY,
234 !!(p_params->rss_caps & QED_RSS_IPV4_UDP));
235 SET_FIELD(capabilities,
236 ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY,
237 !!(p_params->rss_caps & QED_RSS_IPV6_UDP));
238 rss->tbl_size = p_params->rss_table_size_log;
239
240 rss->capabilities = cpu_to_le16(capabilities);
241
242 DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP,
243 "update rss flag %d, rss_mode = %d, update_caps = %d, capabilities = %d, update_ind = %d, update_rss_key = %d\n",
244 p_ramrod->common.update_rss_flg,
245 rss->rss_mode, rss->update_rss_capabilities,
246 capabilities, rss->update_rss_ind_table,
247 rss->update_rss_key);
248
249 for (i = 0; i < QED_RSS_IND_TABLE_SIZE; i++) {
250 rc = qed_fw_l2_queue(p_hwfn,
251 (u8)p_params->rss_ind_table[i],
252 &abs_l2_queue);
253 if (rc)
254 return rc;
255
256 rss->indirection_table[i] = cpu_to_le16(abs_l2_queue);
257 DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP, "i= %d, queue = %d\n",
258 i, rss->indirection_table[i]);
259 }
260
261 for (i = 0; i < 10; i++)
262 rss->rss_key[i] = cpu_to_le32(p_params->rss_key[i]);
263
264 return rc;
265}
266
267static void
268qed_sp_update_accept_mode(struct qed_hwfn *p_hwfn,
269 struct vport_update_ramrod_data *p_ramrod,
270 struct qed_filter_accept_flags accept_flags)
271{
272 p_ramrod->common.update_rx_mode_flg =
273 accept_flags.update_rx_mode_config;
274
275 p_ramrod->common.update_tx_mode_flg =
276 accept_flags.update_tx_mode_config;
277
278 /* Set Rx mode accept flags */
279 if (p_ramrod->common.update_rx_mode_flg) {
280 u8 accept_filter = accept_flags.rx_accept_filter;
281 u16 state = 0;
282
283 SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_DROP_ALL,
284 !(!!(accept_filter & QED_ACCEPT_UCAST_MATCHED) ||
285 !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED)));
286
287 SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED,
288 !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED));
289
290 SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_DROP_ALL,
291 !(!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) ||
292 !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED)));
293
294 SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL,
295 (!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) &&
296 !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED)));
297
298 SET_FIELD(state, ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL,
299 !!(accept_filter & QED_ACCEPT_BCAST));
300
301 p_ramrod->rx_mode.state = cpu_to_le16(state);
302 DP_VERBOSE(p_hwfn, QED_MSG_SP,
303 "p_ramrod->rx_mode.state = 0x%x\n", state);
304 }
305
306 /* Set Tx mode accept flags */
307 if (p_ramrod->common.update_tx_mode_flg) {
308 u8 accept_filter = accept_flags.tx_accept_filter;
309 u16 state = 0;
310
311 SET_FIELD(state, ETH_VPORT_TX_MODE_UCAST_DROP_ALL,
312 !!(accept_filter & QED_ACCEPT_NONE));
313
314 SET_FIELD(state, ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL,
315 (!!(accept_filter & QED_ACCEPT_UCAST_MATCHED) &&
316 !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED)));
317
318 SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_DROP_ALL,
319 !!(accept_filter & QED_ACCEPT_NONE));
320
321 SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL,
322 (!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) &&
323 !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED)));
324
325 SET_FIELD(state, ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL,
326 !!(accept_filter & QED_ACCEPT_BCAST));
327
328 p_ramrod->tx_mode.state = cpu_to_le16(state);
329 DP_VERBOSE(p_hwfn, QED_MSG_SP,
330 "p_ramrod->tx_mode.state = 0x%x\n", state);
331 }
332}
333
334static void
335qed_sp_update_mcast_bin(struct qed_hwfn *p_hwfn,
336 struct vport_update_ramrod_data *p_ramrod,
337 struct qed_sp_vport_update_params *p_params)
338{
339 int i;
340
341 memset(&p_ramrod->approx_mcast.bins, 0,
342 sizeof(p_ramrod->approx_mcast.bins));
343
344 if (p_params->update_approx_mcast_flg) {
345 p_ramrod->common.update_approx_mcast_flg = 1;
346 for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) {
347 u32 *p_bins = (u32 *)p_params->bins;
348 __le32 val = cpu_to_le32(p_bins[i]);
349
350 p_ramrod->approx_mcast.bins[i] = val;
351 }
352 }
353}
354
355static int
356qed_sp_vport_update(struct qed_hwfn *p_hwfn,
357 struct qed_sp_vport_update_params *p_params,
358 enum spq_mode comp_mode,
359 struct qed_spq_comp_cb *p_comp_data)
360{
361 struct qed_rss_params *p_rss_params = p_params->rss_params;
362 struct vport_update_ramrod_data_cmn *p_cmn;
06f56b81 363 struct qed_sp_init_data init_data;
cee4d264
MC		 364 struct vport_update_ramrod_data *p_ramrod = NULL;
365 struct qed_spq_entry *p_ent = NULL;
366 u8 abs_vport_id = 0;
367 int rc = -EINVAL;
368
369 rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
370 if (rc != 0)
371 return rc;
372
06f56b81
YM		 373 memset(&init_data, 0, sizeof(init_data));
374 init_data.cid = qed_spq_get_cid(p_hwfn);
375 init_data.opaque_fid = p_params->opaque_fid;
376 init_data.comp_mode = comp_mode;
377 init_data.p_comp_data = p_comp_data;
cee4d264
MC		 378
379 rc = qed_sp_init_request(p_hwfn, &p_ent,
cee4d264 380 ETH_RAMROD_VPORT_UPDATE,
06f56b81 381 PROTOCOLID_ETH, &init_data);
cee4d264
MC		 382 if (rc)
383 return rc;
384
385 /* Copy input params to ramrod according to FW struct */
386 p_ramrod = &p_ent->ramrod.vport_update;
387 p_cmn = &p_ramrod->common;
388
389 p_cmn->vport_id = abs_vport_id;
390 p_cmn->rx_active_flg = p_params->vport_active_rx_flg;
391 p_cmn->update_rx_active_flg = p_params->update_vport_active_rx_flg;
392 p_cmn->tx_active_flg = p_params->vport_active_tx_flg;
393 p_cmn->update_tx_active_flg = p_params->update_vport_active_tx_flg;
3f9b4a69
YM		 394 p_cmn->accept_any_vlan = p_params->accept_any_vlan;
395 p_cmn->update_accept_any_vlan_flg =
396 p_params->update_accept_any_vlan_flg;
cee4d264
MC		 397 rc = qed_sp_vport_update_rss(p_hwfn, p_ramrod, p_rss_params);
398 if (rc) {
399 /* Return spq entry which is taken in qed_sp_init_request()*/
400 qed_spq_return_entry(p_hwfn, p_ent);
401 return rc;
402 }
403
404 /* Update mcast bins for VFs, PF doesn't use this functionality */
405 qed_sp_update_mcast_bin(p_hwfn, p_ramrod, p_params);
406
407 qed_sp_update_accept_mode(p_hwfn, p_ramrod, p_params->accept_flags);
408 return qed_spq_post(p_hwfn, p_ent, NULL);
409}
410
411static int qed_sp_vport_stop(struct qed_hwfn *p_hwfn,
412 u16 opaque_fid,
413 u8 vport_id)
414{
cee4d264 415 struct vport_stop_ramrod_data *p_ramrod;
06f56b81 416 struct qed_sp_init_data init_data;
cee4d264
MC		 417 struct qed_spq_entry *p_ent;
418 u8 abs_vport_id = 0;
419 int rc;
420
421 rc = qed_fw_vport(p_hwfn, vport_id, &abs_vport_id);
422 if (rc != 0)
423 return rc;
424
06f56b81
YM		 425 memset(&init_data, 0, sizeof(init_data));
426 init_data.cid = qed_spq_get_cid(p_hwfn);
427 init_data.opaque_fid = opaque_fid;
428 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
cee4d264
MC		 429
430 rc = qed_sp_init_request(p_hwfn, &p_ent,
cee4d264 431 ETH_RAMROD_VPORT_STOP,
06f56b81 432 PROTOCOLID_ETH, &init_data);
cee4d264
MC		 433 if (rc)
434 return rc;
435
436 p_ramrod = &p_ent->ramrod.vport_stop;
437 p_ramrod->vport_id = abs_vport_id;
438
439 return qed_spq_post(p_hwfn, p_ent, NULL);
440}
441
442static int qed_filter_accept_cmd(struct qed_dev *cdev,
443 u8 vport,
444 struct qed_filter_accept_flags accept_flags,
3f9b4a69
YM		 445 u8 update_accept_any_vlan,
446 u8 accept_any_vlan,
447 enum spq_mode comp_mode,
448 struct qed_spq_comp_cb *p_comp_data)
cee4d264
MC		 449{
450 struct qed_sp_vport_update_params vport_update_params;
451 int i, rc;
452
453 /* Prepare and send the vport rx_mode change */
454 memset(&vport_update_params, 0, sizeof(vport_update_params));
455 vport_update_params.vport_id = vport;
456 vport_update_params.accept_flags = accept_flags;
3f9b4a69
YM		 457 vport_update_params.update_accept_any_vlan_flg = update_accept_any_vlan;
458 vport_update_params.accept_any_vlan = accept_any_vlan;
cee4d264
MC		 459
460 for_each_hwfn(cdev, i) {
461 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
462
463 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
464
465 rc = qed_sp_vport_update(p_hwfn, &vport_update_params,
466 comp_mode, p_comp_data);
467 if (rc != 0) {
468 DP_ERR(cdev, "Update rx_mode failed %d\n", rc);
469 return rc;
470 }
471
472 DP_VERBOSE(p_hwfn, QED_MSG_SP,
473 "Accept filter configured, flags = [Rx]%x [Tx]%x\n",
474 accept_flags.rx_accept_filter,
475 accept_flags.tx_accept_filter);
3f9b4a69
YM		 476 if (update_accept_any_vlan)
477 DP_VERBOSE(p_hwfn, QED_MSG_SP,
478 "accept_any_vlan=%d configured\n",
479 accept_any_vlan);
cee4d264
MC		 480 }
481
482 return 0;
483}
484
485static int qed_sp_release_queue_cid(
486 struct qed_hwfn *p_hwfn,
487 struct qed_hw_cid_data *p_cid_data)
488{
489 if (!p_cid_data->b_cid_allocated)
490 return 0;
491
492 qed_cxt_release_cid(p_hwfn, p_cid_data->cid);
493
494 p_cid_data->b_cid_allocated = false;
495
496 return 0;
497}
498
499static int
500qed_sp_eth_rxq_start_ramrod(struct qed_hwfn *p_hwfn,
501 u16 opaque_fid,
502 u32 cid,
503 struct qed_queue_start_common_params *params,
504 u8 stats_id,
505 u16 bd_max_bytes,
506 dma_addr_t bd_chain_phys_addr,
507 dma_addr_t cqe_pbl_addr,
508 u16 cqe_pbl_size)
509{
510 struct rx_queue_start_ramrod_data *p_ramrod = NULL;
cee4d264 511 struct qed_spq_entry *p_ent = NULL;
06f56b81 512 struct qed_sp_init_data init_data;
cee4d264
MC		 513 struct qed_hw_cid_data *p_rx_cid;
514 u16 abs_rx_q_id = 0;
515 u8 abs_vport_id = 0;
516 int rc = -EINVAL;
517
518 /* Store information for the stop */
519 p_rx_cid = &p_hwfn->p_rx_cids[params->queue_id];
520 p_rx_cid->cid = cid;
521 p_rx_cid->opaque_fid = opaque_fid;
522 p_rx_cid->vport_id = params->vport_id;
523
524 rc = qed_fw_vport(p_hwfn, params->vport_id, &abs_vport_id);
525 if (rc != 0)
526 return rc;
527
528 rc = qed_fw_l2_queue(p_hwfn, params->queue_id, &abs_rx_q_id);
529 if (rc != 0)
530 return rc;
531
532 DP_VERBOSE(p_hwfn, QED_MSG_SP,
533 "opaque_fid=0x%x, cid=0x%x, rx_qid=0x%x, vport_id=0x%x, sb_id=0x%x\n",
534 opaque_fid, cid, params->queue_id, params->vport_id,
535 params->sb);
536
06f56b81
YM		 537 /* Get SPQ entry */
538 memset(&init_data, 0, sizeof(init_data));
539 init_data.cid = cid;
540 init_data.opaque_fid = opaque_fid;
541 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
cee4d264
MC		 542
543 rc = qed_sp_init_request(p_hwfn, &p_ent,
cee4d264 544 ETH_RAMROD_RX_QUEUE_START,
06f56b81 545 PROTOCOLID_ETH, &init_data);
cee4d264
MC		 546 if (rc)
547 return rc;
548
549 p_ramrod = &p_ent->ramrod.rx_queue_start;
550
551 p_ramrod->sb_id = cpu_to_le16(params->sb);
552 p_ramrod->sb_index = params->sb_idx;
553 p_ramrod->vport_id = abs_vport_id;
554 p_ramrod->stats_counter_id = stats_id;
555 p_ramrod->rx_queue_id = cpu_to_le16(abs_rx_q_id);
556 p_ramrod->complete_cqe_flg = 0;
557 p_ramrod->complete_event_flg = 1;
558
559 p_ramrod->bd_max_bytes = cpu_to_le16(bd_max_bytes);
560 p_ramrod->bd_base.hi = DMA_HI_LE(bd_chain_phys_addr);
561 p_ramrod->bd_base.lo = DMA_LO_LE(bd_chain_phys_addr);
562
563 p_ramrod->num_of_pbl_pages = cpu_to_le16(cqe_pbl_size);
564 p_ramrod->cqe_pbl_addr.hi = DMA_HI_LE(cqe_pbl_addr);
565 p_ramrod->cqe_pbl_addr.lo = DMA_LO_LE(cqe_pbl_addr);
566
567 rc = qed_spq_post(p_hwfn, p_ent, NULL);
568
569 return rc;
570}
571
572static int
573qed_sp_eth_rx_queue_start(struct qed_hwfn *p_hwfn,
574 u16 opaque_fid,
575 struct qed_queue_start_common_params *params,
576 u16 bd_max_bytes,
577 dma_addr_t bd_chain_phys_addr,
578 dma_addr_t cqe_pbl_addr,
579 u16 cqe_pbl_size,
580 void __iomem **pp_prod)
581{
582 struct qed_hw_cid_data *p_rx_cid;
583 u64 init_prod_val = 0;
584 u16 abs_l2_queue = 0;
585 u8 abs_stats_id = 0;
586 int rc;
587
588 rc = qed_fw_l2_queue(p_hwfn, params->queue_id, &abs_l2_queue);
589 if (rc != 0)
590 return rc;
591
592 rc = qed_fw_vport(p_hwfn, params->vport_id, &abs_stats_id);
593 if (rc != 0)
594 return rc;
595
596 *pp_prod = (u8 __iomem *)p_hwfn->regview +
597 GTT_BAR0_MAP_REG_MSDM_RAM +
598 MSTORM_PRODS_OFFSET(abs_l2_queue);
599
600 /* Init the rcq, rx bd and rx sge (if valid) producers to 0 */
601 __internal_ram_wr(p_hwfn, *pp_prod, sizeof(u64),
602 (u32 *)(&init_prod_val));
603
604 /* Allocate a CID for the queue */
605 p_rx_cid = &p_hwfn->p_rx_cids[params->queue_id];
606 rc = qed_cxt_acquire_cid(p_hwfn, PROTOCOLID_ETH,
607 &p_rx_cid->cid);
608 if (rc) {
609 DP_NOTICE(p_hwfn, "Failed to acquire cid\n");
610 return rc;
611 }
612 p_rx_cid->b_cid_allocated = true;
613
614 rc = qed_sp_eth_rxq_start_ramrod(p_hwfn,
615 opaque_fid,
616 p_rx_cid->cid,
617 params,
618 abs_stats_id,
619 bd_max_bytes,
620 bd_chain_phys_addr,
621 cqe_pbl_addr,
622 cqe_pbl_size);
623
624 if (rc != 0)
625 qed_sp_release_queue_cid(p_hwfn, p_rx_cid);
626
627 return rc;
628}
629
630static int qed_sp_eth_rx_queue_stop(struct qed_hwfn *p_hwfn,
631 u16 rx_queue_id,
632 bool eq_completion_only,
633 bool cqe_completion)
634{
635 struct qed_hw_cid_data *p_rx_cid = &p_hwfn->p_rx_cids[rx_queue_id];
636 struct rx_queue_stop_ramrod_data *p_ramrod = NULL;
cee4d264 637 struct qed_spq_entry *p_ent = NULL;
06f56b81 638 struct qed_sp_init_data init_data;
cee4d264
MC		 639 u16 abs_rx_q_id = 0;
640 int rc = -EINVAL;
641
06f56b81
YM		 642 /* Get SPQ entry */
643 memset(&init_data, 0, sizeof(init_data));
644 init_data.cid = p_rx_cid->cid;
645 init_data.opaque_fid = p_rx_cid->opaque_fid;
646 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
cee4d264
MC		 647
648 rc = qed_sp_init_request(p_hwfn, &p_ent,
cee4d264 649 ETH_RAMROD_RX_QUEUE_STOP,
06f56b81 650 PROTOCOLID_ETH, &init_data);
cee4d264
MC		 651 if (rc)
652 return rc;
653
654 p_ramrod = &p_ent->ramrod.rx_queue_stop;
655
656 qed_fw_vport(p_hwfn, p_rx_cid->vport_id, &p_ramrod->vport_id);
657 qed_fw_l2_queue(p_hwfn, rx_queue_id, &abs_rx_q_id);
658 p_ramrod->rx_queue_id = cpu_to_le16(abs_rx_q_id);
659
660 /* Cleaning the queue requires the completion to arrive there.
661 * In addition, VFs require the answer to come as eqe to PF.
662 */
663 p_ramrod->complete_cqe_flg =
664 (!!(p_rx_cid->opaque_fid == p_hwfn->hw_info.opaque_fid) &&
665 !eq_completion_only) || cqe_completion;
666 p_ramrod->complete_event_flg =
667 !(p_rx_cid->opaque_fid == p_hwfn->hw_info.opaque_fid) ||
668 eq_completion_only;
669
670 rc = qed_spq_post(p_hwfn, p_ent, NULL);
671 if (rc)
672 return rc;
673
674 return qed_sp_release_queue_cid(p_hwfn, p_rx_cid);
675}
676
677static int
678qed_sp_eth_txq_start_ramrod(struct qed_hwfn *p_hwfn,
679 u16 opaque_fid,
680 u32 cid,
681 struct qed_queue_start_common_params *p_params,
682 u8 stats_id,
683 dma_addr_t pbl_addr,
684 u16 pbl_size,
685 union qed_qm_pq_params *p_pq_params)
686{
687 struct tx_queue_start_ramrod_data *p_ramrod = NULL;
cee4d264 688 struct qed_spq_entry *p_ent = NULL;
06f56b81 689 struct qed_sp_init_data init_data;
cee4d264
MC		 690 struct qed_hw_cid_data *p_tx_cid;
691 u8 abs_vport_id;
692 int rc = -EINVAL;
693 u16 pq_id;
694
695 /* Store information for the stop */
696 p_tx_cid = &p_hwfn->p_tx_cids[p_params->queue_id];
697 p_tx_cid->cid = cid;
698 p_tx_cid->opaque_fid = opaque_fid;
699
700 rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
701 if (rc)
702 return rc;
703
06f56b81
YM		 704 /* Get SPQ entry */
705 memset(&init_data, 0, sizeof(init_data));
706 init_data.cid = cid;
707 init_data.opaque_fid = opaque_fid;
708 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
cee4d264 709
06f56b81 710 rc = qed_sp_init_request(p_hwfn, &p_ent,
cee4d264 711 ETH_RAMROD_TX_QUEUE_START,
06f56b81 712 PROTOCOLID_ETH, &init_data);
cee4d264
MC		 713 if (rc)
714 return rc;
715
716 p_ramrod = &p_ent->ramrod.tx_queue_start;
717 p_ramrod->vport_id = abs_vport_id;
718
719 p_ramrod->sb_id = cpu_to_le16(p_params->sb);
720 p_ramrod->sb_index = p_params->sb_idx;
721 p_ramrod->stats_counter_id = stats_id;
cee4d264
MC		 722
723 p_ramrod->pbl_size = cpu_to_le16(pbl_size);
724 p_ramrod->pbl_base_addr.hi = DMA_HI_LE(pbl_addr);
725 p_ramrod->pbl_base_addr.lo = DMA_LO_LE(pbl_addr);
726
727 pq_id = qed_get_qm_pq(p_hwfn,
728 PROTOCOLID_ETH,
729 p_pq_params);
730 p_ramrod->qm_pq_id = cpu_to_le16(pq_id);
731
732 return qed_spq_post(p_hwfn, p_ent, NULL);
733}
734
735static int
736qed_sp_eth_tx_queue_start(struct qed_hwfn *p_hwfn,
737 u16 opaque_fid,
738 struct qed_queue_start_common_params *p_params,
739 dma_addr_t pbl_addr,
740 u16 pbl_size,
741 void __iomem **pp_doorbell)
742{
743 struct qed_hw_cid_data *p_tx_cid;
744 union qed_qm_pq_params pq_params;
745 u8 abs_stats_id = 0;
746 int rc;
747
748 rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_stats_id);
749 if (rc)
750 return rc;
751
752 p_tx_cid = &p_hwfn->p_tx_cids[p_params->queue_id];
753 memset(p_tx_cid, 0, sizeof(*p_tx_cid));
754 memset(&pq_params, 0, sizeof(pq_params));
755
756 /* Allocate a CID for the queue */
757 rc = qed_cxt_acquire_cid(p_hwfn, PROTOCOLID_ETH,
758 &p_tx_cid->cid);
759 if (rc) {
760 DP_NOTICE(p_hwfn, "Failed to acquire cid\n");
761 return rc;
762 }
763 p_tx_cid->b_cid_allocated = true;
764
765 DP_VERBOSE(p_hwfn, QED_MSG_SP,
766 "opaque_fid=0x%x, cid=0x%x, tx_qid=0x%x, vport_id=0x%x, sb_id=0x%x\n",
767 opaque_fid, p_tx_cid->cid,
768 p_params->queue_id, p_params->vport_id, p_params->sb);
769
770 rc = qed_sp_eth_txq_start_ramrod(p_hwfn,
771 opaque_fid,
772 p_tx_cid->cid,
773 p_params,
774 abs_stats_id,
775 pbl_addr,
776 pbl_size,
777 &pq_params);
778
779 *pp_doorbell = (u8 __iomem *)p_hwfn->doorbells +
780 qed_db_addr(p_tx_cid->cid, DQ_DEMS_LEGACY);
781
782 if (rc)
783 qed_sp_release_queue_cid(p_hwfn, p_tx_cid);
784
785 return rc;
786}
787
788static int qed_sp_eth_tx_queue_stop(struct qed_hwfn *p_hwfn,
789 u16 tx_queue_id)
790{
791 struct qed_hw_cid_data *p_tx_cid = &p_hwfn->p_tx_cids[tx_queue_id];
cee4d264 792 struct qed_spq_entry *p_ent = NULL;
06f56b81 793 struct qed_sp_init_data init_data;
cee4d264
MC		 794 int rc = -EINVAL;
795
06f56b81
YM		 796 /* Get SPQ entry */
797 memset(&init_data, 0, sizeof(init_data));
798 init_data.cid = p_tx_cid->cid;
799 init_data.opaque_fid = p_tx_cid->opaque_fid;
800 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
cee4d264
MC		 801
802 rc = qed_sp_init_request(p_hwfn, &p_ent,
cee4d264 803 ETH_RAMROD_TX_QUEUE_STOP,
06f56b81 804 PROTOCOLID_ETH, &init_data);
cee4d264
MC		 805 if (rc)
806 return rc;
807
808 rc = qed_spq_post(p_hwfn, p_ent, NULL);
809 if (rc)
810 return rc;
811
812 return qed_sp_release_queue_cid(p_hwfn, p_tx_cid);
813}
814
815static enum eth_filter_action
816qed_filter_action(enum qed_filter_opcode opcode)
817{
818 enum eth_filter_action action = MAX_ETH_FILTER_ACTION;
819
820 switch (opcode) {
821 case QED_FILTER_ADD:
822 action = ETH_FILTER_ACTION_ADD;
823 break;
824 case QED_FILTER_REMOVE:
825 action = ETH_FILTER_ACTION_REMOVE;
826 break;
cee4d264 827 case QED_FILTER_FLUSH:
fc48b7a6 828 action = ETH_FILTER_ACTION_REMOVE_ALL;
cee4d264
MC		 829 break;
830 default:
831 action = MAX_ETH_FILTER_ACTION;
832 }
833
834 return action;
835}
836
837static void qed_set_fw_mac_addr(__le16 *fw_msb,
838 __le16 *fw_mid,
839 __le16 *fw_lsb,
840 u8 *mac)
841{
842 ((u8 *)fw_msb)[0] = mac[1];
843 ((u8 *)fw_msb)[1] = mac[0];
844 ((u8 *)fw_mid)[0] = mac[3];
845 ((u8 *)fw_mid)[1] = mac[2];
846 ((u8 *)fw_lsb)[0] = mac[5];
847 ((u8 *)fw_lsb)[1] = mac[4];
848}
849
850static int
851qed_filter_ucast_common(struct qed_hwfn *p_hwfn,
852 u16 opaque_fid,
853 struct qed_filter_ucast *p_filter_cmd,
854 struct vport_filter_update_ramrod_data **pp_ramrod,
855 struct qed_spq_entry **pp_ent,
856 enum spq_mode comp_mode,
857 struct qed_spq_comp_cb *p_comp_data)
858{
859 u8 vport_to_add_to = 0, vport_to_remove_from = 0;
860 struct vport_filter_update_ramrod_data *p_ramrod;
cee4d264
MC		 861 struct eth_filter_cmd *p_first_filter;
862 struct eth_filter_cmd *p_second_filter;
06f56b81 863 struct qed_sp_init_data init_data;
cee4d264
MC		 864 enum eth_filter_action action;
865 int rc;
866
867 rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from,
868 &vport_to_remove_from);
869 if (rc)
870 return rc;
871
872 rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to,
873 &vport_to_add_to);
874 if (rc)
875 return rc;
876
06f56b81
YM		 877 /* Get SPQ entry */
878 memset(&init_data, 0, sizeof(init_data));
879 init_data.cid = qed_spq_get_cid(p_hwfn);
880 init_data.opaque_fid = opaque_fid;
881 init_data.comp_mode = comp_mode;
882 init_data.p_comp_data = p_comp_data;
cee4d264
MC		 883
884 rc = qed_sp_init_request(p_hwfn, pp_ent,
cee4d264 885 ETH_RAMROD_FILTERS_UPDATE,
06f56b81 886 PROTOCOLID_ETH, &init_data);
cee4d264
MC		 887 if (rc)
888 return rc;
889
890 *pp_ramrod = &(*pp_ent)->ramrod.vport_filter_update;
891 p_ramrod = *pp_ramrod;
892 p_ramrod->filter_cmd_hdr.rx = p_filter_cmd->is_rx_filter ? 1 : 0;
893 p_ramrod->filter_cmd_hdr.tx = p_filter_cmd->is_tx_filter ? 1 : 0;
894
895 switch (p_filter_cmd->opcode) {
fc48b7a6 896 case QED_FILTER_REPLACE:
cee4d264
MC		 897 case QED_FILTER_MOVE:
898 p_ramrod->filter_cmd_hdr.cmd_cnt = 2; break;
899 default:
900 p_ramrod->filter_cmd_hdr.cmd_cnt = 1; break;
901 }
902
903 p_first_filter = &p_ramrod->filter_cmds[0];
904 p_second_filter = &p_ramrod->filter_cmds[1];
905
906 switch (p_filter_cmd->type) {
907 case QED_FILTER_MAC:
908 p_first_filter->type = ETH_FILTER_TYPE_MAC; break;
909 case QED_FILTER_VLAN:
910 p_first_filter->type = ETH_FILTER_TYPE_VLAN; break;
911 case QED_FILTER_MAC_VLAN:
912 p_first_filter->type = ETH_FILTER_TYPE_PAIR; break;
913 case QED_FILTER_INNER_MAC:
914 p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC; break;
915 case QED_FILTER_INNER_VLAN:
916 p_first_filter->type = ETH_FILTER_TYPE_INNER_VLAN; break;
917 case QED_FILTER_INNER_PAIR:
918 p_first_filter->type = ETH_FILTER_TYPE_INNER_PAIR; break;
919 case QED_FILTER_INNER_MAC_VNI_PAIR:
920 p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR;
921 break;
922 case QED_FILTER_MAC_VNI_PAIR:
923 p_first_filter->type = ETH_FILTER_TYPE_MAC_VNI_PAIR; break;
924 case QED_FILTER_VNI:
925 p_first_filter->type = ETH_FILTER_TYPE_VNI; break;
926 }
927
928 if ((p_first_filter->type == ETH_FILTER_TYPE_MAC) ||
929 (p_first_filter->type == ETH_FILTER_TYPE_PAIR) ||
930 (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC) ||
931 (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR) ||
932 (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) ||
933 (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR)) {
934 qed_set_fw_mac_addr(&p_first_filter->mac_msb,
935 &p_first_filter->mac_mid,
936 &p_first_filter->mac_lsb,
937 (u8 *)p_filter_cmd->mac);
938 }
939
940 if ((p_first_filter->type == ETH_FILTER_TYPE_VLAN) ||
941 (p_first_filter->type == ETH_FILTER_TYPE_PAIR) ||
942 (p_first_filter->type == ETH_FILTER_TYPE_INNER_VLAN) ||
943 (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR))
944 p_first_filter->vlan_id = cpu_to_le16(p_filter_cmd->vlan);
945
946 if ((p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) ||
947 (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR) ||
948 (p_first_filter->type == ETH_FILTER_TYPE_VNI))
949 p_first_filter->vni = cpu_to_le32(p_filter_cmd->vni);
950
951 if (p_filter_cmd->opcode == QED_FILTER_MOVE) {
952 p_second_filter->type = p_first_filter->type;
953 p_second_filter->mac_msb = p_first_filter->mac_msb;
954 p_second_filter->mac_mid = p_first_filter->mac_mid;
955 p_second_filter->mac_lsb = p_first_filter->mac_lsb;
956 p_second_filter->vlan_id = p_first_filter->vlan_id;
957 p_second_filter->vni = p_first_filter->vni;
958
959 p_first_filter->action = ETH_FILTER_ACTION_REMOVE;
960
961 p_first_filter->vport_id = vport_to_remove_from;
962
963 p_second_filter->action = ETH_FILTER_ACTION_ADD;
964 p_second_filter->vport_id = vport_to_add_to;
fc48b7a6
YM		 965 } else if (p_filter_cmd->opcode == QED_FILTER_REPLACE) {
966 p_first_filter->vport_id = vport_to_add_to;
967 memcpy(p_second_filter, p_first_filter,
968 sizeof(*p_second_filter));
969 p_first_filter->action = ETH_FILTER_ACTION_REMOVE_ALL;
970 p_second_filter->action = ETH_FILTER_ACTION_ADD;
cee4d264
MC		 971 } else {
972 action = qed_filter_action(p_filter_cmd->opcode);
973
974 if (action == MAX_ETH_FILTER_ACTION) {
975 DP_NOTICE(p_hwfn,
976 "%d is not supported yet\n",
977 p_filter_cmd->opcode);
978 return -EINVAL;
979 }
980
981 p_first_filter->action = action;
982 p_first_filter->vport_id = (p_filter_cmd->opcode ==
983 QED_FILTER_REMOVE) ?
984 vport_to_remove_from :
985 vport_to_add_to;
986 }
987
988 return 0;
989}
990
991static int qed_sp_eth_filter_ucast(struct qed_hwfn *p_hwfn,
992 u16 opaque_fid,
993 struct qed_filter_ucast *p_filter_cmd,
994 enum spq_mode comp_mode,
995 struct qed_spq_comp_cb *p_comp_data)
996{
997 struct vport_filter_update_ramrod_data *p_ramrod = NULL;
998 struct qed_spq_entry *p_ent = NULL;
999 struct eth_filter_cmd_header *p_header;
1000 int rc;
1001
1002 rc = qed_filter_ucast_common(p_hwfn, opaque_fid, p_filter_cmd,
1003 &p_ramrod, &p_ent,
1004 comp_mode, p_comp_data);
1005 if (rc != 0) {
1006 DP_ERR(p_hwfn, "Uni. filter command failed %d\n", rc);
1007 return rc;
1008 }
1009 p_header = &p_ramrod->filter_cmd_hdr;
1010 p_header->assert_on_error = p_filter_cmd->assert_on_error;
1011
1012 rc = qed_spq_post(p_hwfn, p_ent, NULL);
1013 if (rc != 0) {
1014 DP_ERR(p_hwfn,
1015 "Unicast filter ADD command failed %d\n",
1016 rc);
1017 return rc;
1018 }
1019
1020 DP_VERBOSE(p_hwfn, QED_MSG_SP,
1021 "Unicast filter configured, opcode = %s, type = %s, cmd_cnt = %d, is_rx_filter = %d, is_tx_filter = %d\n",
1022 (p_filter_cmd->opcode == QED_FILTER_ADD) ? "ADD" :
1023 ((p_filter_cmd->opcode == QED_FILTER_REMOVE) ?
1024 "REMOVE" :
1025 ((p_filter_cmd->opcode == QED_FILTER_MOVE) ?
1026 "MOVE" : "REPLACE")),
1027 (p_filter_cmd->type == QED_FILTER_MAC) ? "MAC" :
1028 ((p_filter_cmd->type == QED_FILTER_VLAN) ?
1029 "VLAN" : "MAC & VLAN"),
1030 p_ramrod->filter_cmd_hdr.cmd_cnt,
1031 p_filter_cmd->is_rx_filter,
1032 p_filter_cmd->is_tx_filter);
1033 DP_VERBOSE(p_hwfn, QED_MSG_SP,
1034 "vport_to_add_to = %d, vport_to_remove_from = %d, mac = %2x:%2x:%2x:%2x:%2x:%2x, vlan = %d\n",
1035 p_filter_cmd->vport_to_add_to,
1036 p_filter_cmd->vport_to_remove_from,
1037 p_filter_cmd->mac[0],
1038 p_filter_cmd->mac[1],
1039 p_filter_cmd->mac[2],
1040 p_filter_cmd->mac[3],
1041 p_filter_cmd->mac[4],
1042 p_filter_cmd->mac[5],
1043 p_filter_cmd->vlan);
1044
1045 return 0;
1046}
1047
1048/*******************************************************************************
1049 * Description:
1050 * Calculates crc 32 on a buffer
1051 * Note: crc32_length MUST be aligned to 8
1052 * Return:
1053 ******************************************************************************/
1054static u32 qed_calc_crc32c(u8 *crc32_packet,
1055 u32 crc32_length,
1056 u32 crc32_seed,
1057 u8 complement)
1058{
1059 u32 byte = 0;
1060 u32 bit = 0;
1061 u8 msb = 0;
1062 u8 current_byte = 0;
1063 u32 crc32_result = crc32_seed;
1064
1065 if ((!crc32_packet) ||
1066 (crc32_length == 0) ||
1067 ((crc32_length % 8) != 0))
1068 return crc32_result;
1069 for (byte = 0; byte < crc32_length; byte++) {
1070 current_byte = crc32_packet[byte];
1071 for (bit = 0; bit < 8; bit++) {
1072 msb = (u8)(crc32_result >> 31);
1073 crc32_result = crc32_result << 1;
1074 if (msb != (0x1 & (current_byte >> bit))) {
1075 crc32_result = crc32_result ^ CRC32_POLY;
1076 crc32_result |= 1; /*crc32_result[0] = 1;*/
1077 }
1078 }
1079 }
1080 return crc32_result;
1081}
1082
1083static inline u32 qed_crc32c_le(u32 seed,
1084 u8 *mac,
1085 u32 len)
1086{
1087 u32 packet_buf[2] = { 0 };
1088
1089 memcpy((u8 *)(&packet_buf[0]), &mac[0], 6);
1090 return qed_calc_crc32c((u8 *)packet_buf, 8, seed, 0);
1091}
1092
1093static u8 qed_mcast_bin_from_mac(u8 *mac)
1094{
1095 u32 crc = qed_crc32c_le(ETH_MULTICAST_BIN_FROM_MAC_SEED,
1096 mac, ETH_ALEN);
1097
1098 return crc & 0xff;
1099}
1100
1101static int
1102qed_sp_eth_filter_mcast(struct qed_hwfn *p_hwfn,
1103 u16 opaque_fid,
1104 struct qed_filter_mcast *p_filter_cmd,
1105 enum spq_mode comp_mode,
1106 struct qed_spq_comp_cb *p_comp_data)
1107{
1108 unsigned long bins[ETH_MULTICAST_MAC_BINS_IN_REGS];
1109 struct vport_update_ramrod_data *p_ramrod = NULL;
cee4d264 1110 struct qed_spq_entry *p_ent = NULL;
06f56b81 1111 struct qed_sp_init_data init_data;
cee4d264
MC		 1112 u8 abs_vport_id = 0;
1113 int rc, i;
1114
1115 if (p_filter_cmd->opcode == QED_FILTER_ADD) {
1116 rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to,
1117 &abs_vport_id);
1118 if (rc)
1119 return rc;
1120 } else {
1121 rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from,
1122 &abs_vport_id);
1123 if (rc)
1124 return rc;
1125 }
1126
06f56b81
YM		 1127 /* Get SPQ entry */
1128 memset(&init_data, 0, sizeof(init_data));
1129 init_data.cid = qed_spq_get_cid(p_hwfn);
1130 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
1131 init_data.comp_mode = comp_mode;
1132 init_data.p_comp_data = p_comp_data;
cee4d264
MC		 1133
1134 rc = qed_sp_init_request(p_hwfn, &p_ent,
cee4d264 1135 ETH_RAMROD_VPORT_UPDATE,
06f56b81 1136 PROTOCOLID_ETH, &init_data);
cee4d264
MC		 1137 if (rc) {
1138 DP_ERR(p_hwfn, "Multi-cast command failed %d\n", rc);
1139 return rc;
1140 }
1141
1142 p_ramrod = &p_ent->ramrod.vport_update;
1143 p_ramrod->common.update_approx_mcast_flg = 1;
1144
1145 /* explicitly clear out the entire vector */
1146 memset(&p_ramrod->approx_mcast.bins, 0,
1147 sizeof(p_ramrod->approx_mcast.bins));
1148 memset(bins, 0, sizeof(unsigned long) *
1149 ETH_MULTICAST_MAC_BINS_IN_REGS);
1150 /* filter ADD op is explicit set op and it removes
1151 * any existing filters for the vport
1152 */
1153 if (p_filter_cmd->opcode == QED_FILTER_ADD) {
1154 for (i = 0; i < p_filter_cmd->num_mc_addrs; i++) {
1155 u32 bit;
1156
1157 bit = qed_mcast_bin_from_mac(p_filter_cmd->mac[i]);
1158 __set_bit(bit, bins);
1159 }
1160
1161 /* Convert to correct endianity */
1162 for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) {
1163 u32 *p_bins = (u32 *)bins;
1164 struct vport_update_ramrod_mcast *approx_mcast;
1165
1166 approx_mcast = &p_ramrod->approx_mcast;
1167 approx_mcast->bins[i] = cpu_to_le32(p_bins[i]);
1168 }
1169 }
1170
1171 p_ramrod->common.vport_id = abs_vport_id;
1172
1173 return qed_spq_post(p_hwfn, p_ent, NULL);
1174}
1175
1176static int
1177qed_filter_mcast_cmd(struct qed_dev *cdev,
1178 struct qed_filter_mcast *p_filter_cmd,
1179 enum spq_mode comp_mode,
1180 struct qed_spq_comp_cb *p_comp_data)
1181{
1182 int rc = 0;
1183 int i;
1184
1185 /* only ADD and REMOVE operations are supported for multi-cast */
1186 if ((p_filter_cmd->opcode != QED_FILTER_ADD &&
1187 (p_filter_cmd->opcode != QED_FILTER_REMOVE)) ||
1188 (p_filter_cmd->num_mc_addrs > QED_MAX_MC_ADDRS))
1189 return -EINVAL;
1190
1191 for_each_hwfn(cdev, i) {
1192 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1193
1194 u16 opaque_fid;
1195
1196 if (rc != 0)
1197 break;
1198
1199 opaque_fid = p_hwfn->hw_info.opaque_fid;
1200
1201 rc = qed_sp_eth_filter_mcast(p_hwfn,
1202 opaque_fid,
1203 p_filter_cmd,
1204 comp_mode,
1205 p_comp_data);
1206 }
1207 return rc;
1208}
1209
1210static int qed_filter_ucast_cmd(struct qed_dev *cdev,
1211 struct qed_filter_ucast *p_filter_cmd,
1212 enum spq_mode comp_mode,
1213 struct qed_spq_comp_cb *p_comp_data)
1214{
1215 int rc = 0;
1216 int i;
1217
1218 for_each_hwfn(cdev, i) {
1219 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1220 u16 opaque_fid;
1221
1222 if (rc != 0)
1223 break;
1224
1225 opaque_fid = p_hwfn->hw_info.opaque_fid;
1226
1227 rc = qed_sp_eth_filter_ucast(p_hwfn,
1228 opaque_fid,
1229 p_filter_cmd,
1230 comp_mode,
1231 p_comp_data);
1232 }
1233
1234 return rc;
1235}
1236
25c089d7
YM		 1237static int qed_fill_eth_dev_info(struct qed_dev *cdev,
1238 struct qed_dev_eth_info *info)
1239{
1240 int i;
1241
1242 memset(info, 0, sizeof(*info));
1243
1244 info->num_tc = 1;
1245
1246 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
1247 for_each_hwfn(cdev, i)
1248 info->num_queues += FEAT_NUM(&cdev->hwfns[i],
1249 QED_PF_L2_QUE);
1250 if (cdev->int_params.fp_msix_cnt)
1251 info->num_queues = min_t(u8, info->num_queues,
1252 cdev->int_params.fp_msix_cnt);
1253 } else {
1254 info->num_queues = cdev->num_hwfns;
1255 }
1256
1257 info->num_vlan_filters = RESC_NUM(&cdev->hwfns[0], QED_VLAN);
1258 ether_addr_copy(info->port_mac,
1259 cdev->hwfns[0].hw_info.hw_mac_addr);
1260
1261 qed_fill_dev_info(cdev, &info->common);
1262
1263 return 0;
1264}
1265
cc875c2e
YM		 1266static void qed_register_eth_ops(struct qed_dev *cdev,
1267 struct qed_eth_cb_ops *ops,
1268 void *cookie)
1269{
1270 cdev->protocol_ops.eth = ops;
1271 cdev->ops_cookie = cookie;
1272}
1273
cee4d264
MC		 1274static int qed_start_vport(struct qed_dev *cdev,
1275 u8 vport_id,
1276 u16 mtu,
1277 u8 drop_ttl0_flg,
1278 u8 inner_vlan_removal_en_flg)
1279{
1280 int rc, i;
1281
1282 for_each_hwfn(cdev, i) {
1283 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1284
1285 rc = qed_sp_vport_start(p_hwfn,
1286 p_hwfn->hw_info.concrete_fid,
1287 p_hwfn->hw_info.opaque_fid,
1288 vport_id,
1289 mtu,
1290 drop_ttl0_flg,
1291 inner_vlan_removal_en_flg);
1292
1293 if (rc) {
1294 DP_ERR(cdev, "Failed to start VPORT\n");
1295 return rc;
1296 }
1297
1298 qed_hw_start_fastpath(p_hwfn);
1299
1300 DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
1301 "Started V-PORT %d with MTU %d\n",
1302 vport_id, mtu);
1303 }
1304
9df2ed04
MC		 1305 qed_reset_vport_stats(cdev);
1306
cee4d264
MC		 1307 return 0;
1308}
1309
1310static int qed_stop_vport(struct qed_dev *cdev,
1311 u8 vport_id)
1312{
1313 int rc, i;
1314
1315 for_each_hwfn(cdev, i) {
1316 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1317
1318 rc = qed_sp_vport_stop(p_hwfn,
1319 p_hwfn->hw_info.opaque_fid,
1320 vport_id);
1321
1322 if (rc) {
1323 DP_ERR(cdev, "Failed to stop VPORT\n");
1324 return rc;
1325 }
1326 }
1327 return 0;
1328}
1329
1330static int qed_update_vport(struct qed_dev *cdev,
1331 struct qed_update_vport_params *params)
1332{
1333 struct qed_sp_vport_update_params sp_params;
1334 struct qed_rss_params sp_rss_params;
1335 int rc, i;
1336
1337 if (!cdev)
1338 return -ENODEV;
1339
1340 memset(&sp_params, 0, sizeof(sp_params));
1341 memset(&sp_rss_params, 0, sizeof(sp_rss_params));
1342
1343 /* Translate protocol params into sp params */
1344 sp_params.vport_id = params->vport_id;
1345 sp_params.update_vport_active_rx_flg =
1346 params->update_vport_active_flg;
1347 sp_params.update_vport_active_tx_flg =
1348 params->update_vport_active_flg;
1349 sp_params.vport_active_rx_flg = params->vport_active_flg;
1350 sp_params.vport_active_tx_flg = params->vport_active_flg;
3f9b4a69
YM		 1351 sp_params.accept_any_vlan = params->accept_any_vlan;
1352 sp_params.update_accept_any_vlan_flg =
1353 params->update_accept_any_vlan_flg;
cee4d264
MC		 1354
1355 /* RSS - is a bit tricky, since upper-layer isn't familiar with hwfns.
1356 * We need to re-fix the rss values per engine for CMT.
1357 */
1358 if (cdev->num_hwfns > 1 && params->update_rss_flg) {
1359 struct qed_update_vport_rss_params *rss =
1360 &params->rss_params;
1361 int k, max = 0;
1362
1363 /* Find largest entry, since it's possible RSS needs to
1364 * be disabled [in case only 1 queue per-hwfn]
1365 */
1366 for (k = 0; k < QED_RSS_IND_TABLE_SIZE; k++)
1367 max = (max > rss->rss_ind_table[k]) ?
1368 max : rss->rss_ind_table[k];
1369
1370 /* Either fix RSS values or disable RSS */
1371 if (cdev->num_hwfns < max + 1) {
1372 int divisor = (max + cdev->num_hwfns - 1) /
1373 cdev->num_hwfns;
1374
1375 DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
1376 "CMT - fixing RSS values (modulo %02x)\n",
1377 divisor);
1378
1379 for (k = 0; k < QED_RSS_IND_TABLE_SIZE; k++)
1380 rss->rss_ind_table[k] =
1381 rss->rss_ind_table[k] % divisor;
1382 } else {
1383 DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
1384 "CMT - 1 queue per-hwfn; Disabling RSS\n");
1385 params->update_rss_flg = 0;
1386 }
1387 }
1388
1389 /* Now, update the RSS configuration for actual configuration */
1390 if (params->update_rss_flg) {
1391 sp_rss_params.update_rss_config = 1;
1392 sp_rss_params.rss_enable = 1;
1393 sp_rss_params.update_rss_capabilities = 1;
1394 sp_rss_params.update_rss_ind_table = 1;
1395 sp_rss_params.update_rss_key = 1;
1396 sp_rss_params.rss_caps = QED_RSS_IPV4 |
1397 QED_RSS_IPV6 |
1398 QED_RSS_IPV4_TCP | QED_RSS_IPV6_TCP;
1399 sp_rss_params.rss_table_size_log = 7; /* 2^7 = 128 */
1400 memcpy(sp_rss_params.rss_ind_table,
1401 params->rss_params.rss_ind_table,
1402 QED_RSS_IND_TABLE_SIZE * sizeof(u16));
1403 memcpy(sp_rss_params.rss_key, params->rss_params.rss_key,
1404 QED_RSS_KEY_SIZE * sizeof(u32));
1405 }
1406 sp_params.rss_params = &sp_rss_params;
1407
1408 for_each_hwfn(cdev, i) {
1409 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1410
1411 sp_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
1412 rc = qed_sp_vport_update(p_hwfn, &sp_params,
1413 QED_SPQ_MODE_EBLOCK,
1414 NULL);
1415 if (rc) {
1416 DP_ERR(cdev, "Failed to update VPORT\n");
1417 return rc;
1418 }
1419
1420 DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
1421 "Updated V-PORT %d: active_flag %d [update %d]\n",
1422 params->vport_id, params->vport_active_flg,
1423 params->update_vport_active_flg);
1424 }
1425
1426 return 0;
1427}
1428
1429static int qed_start_rxq(struct qed_dev *cdev,
1430 struct qed_queue_start_common_params *params,
1431 u16 bd_max_bytes,
1432 dma_addr_t bd_chain_phys_addr,
1433 dma_addr_t cqe_pbl_addr,
1434 u16 cqe_pbl_size,
1435 void __iomem **pp_prod)
1436{
1437 int rc, hwfn_index;
1438 struct qed_hwfn *p_hwfn;
1439
1440 hwfn_index = params->rss_id % cdev->num_hwfns;
1441 p_hwfn = &cdev->hwfns[hwfn_index];
1442
1443 /* Fix queue ID in 100g mode */
1444 params->queue_id /= cdev->num_hwfns;
1445
1446 rc = qed_sp_eth_rx_queue_start(p_hwfn,
1447 p_hwfn->hw_info.opaque_fid,
1448 params,
1449 bd_max_bytes,
1450 bd_chain_phys_addr,
1451 cqe_pbl_addr,
1452 cqe_pbl_size,
1453 pp_prod);
1454
1455 if (rc) {
1456 DP_ERR(cdev, "Failed to start RXQ#%d\n", params->queue_id);
1457 return rc;
1458 }
1459
1460 DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
1461 "Started RX-Q %d [rss %d] on V-PORT %d and SB %d\n",
1462 params->queue_id, params->rss_id, params->vport_id,
1463 params->sb);
1464
1465 return 0;
1466}
1467
1468static int qed_stop_rxq(struct qed_dev *cdev,
1469 struct qed_stop_rxq_params *params)
1470{
1471 int rc, hwfn_index;
1472 struct qed_hwfn *p_hwfn;
1473
1474 hwfn_index = params->rss_id % cdev->num_hwfns;
1475 p_hwfn = &cdev->hwfns[hwfn_index];
1476
1477 rc = qed_sp_eth_rx_queue_stop(p_hwfn,
1478 params->rx_queue_id / cdev->num_hwfns,
1479 params->eq_completion_only,
1480 false);
1481 if (rc) {
1482 DP_ERR(cdev, "Failed to stop RXQ#%d\n", params->rx_queue_id);
1483 return rc;
1484 }
1485
1486 return 0;
1487}
1488
1489static int qed_start_txq(struct qed_dev *cdev,
1490 struct qed_queue_start_common_params *p_params,
1491 dma_addr_t pbl_addr,
1492 u16 pbl_size,
1493 void __iomem **pp_doorbell)
1494{
1495 struct qed_hwfn *p_hwfn;
1496 int rc, hwfn_index;
1497
1498 hwfn_index = p_params->rss_id % cdev->num_hwfns;
1499 p_hwfn = &cdev->hwfns[hwfn_index];
1500
1501 /* Fix queue ID in 100g mode */
1502 p_params->queue_id /= cdev->num_hwfns;
1503
1504 rc = qed_sp_eth_tx_queue_start(p_hwfn,
1505 p_hwfn->hw_info.opaque_fid,
1506 p_params,
1507 pbl_addr,
1508 pbl_size,
1509 pp_doorbell);
1510
1511 if (rc) {
1512 DP_ERR(cdev, "Failed to start TXQ#%d\n", p_params->queue_id);
1513 return rc;
1514 }
1515
1516 DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
1517 "Started TX-Q %d [rss %d] on V-PORT %d and SB %d\n",
1518 p_params->queue_id, p_params->rss_id, p_params->vport_id,
1519 p_params->sb);
1520
1521 return 0;
1522}
1523
1524#define QED_HW_STOP_RETRY_LIMIT (10)
1525static int qed_fastpath_stop(struct qed_dev *cdev)
1526{
1527 qed_hw_stop_fastpath(cdev);
1528
1529 return 0;
1530}
1531
1532static int qed_stop_txq(struct qed_dev *cdev,
1533 struct qed_stop_txq_params *params)
1534{
1535 struct qed_hwfn *p_hwfn;
1536 int rc, hwfn_index;
1537
1538 hwfn_index = params->rss_id % cdev->num_hwfns;
1539 p_hwfn = &cdev->hwfns[hwfn_index];
1540
1541 rc = qed_sp_eth_tx_queue_stop(p_hwfn,
1542 params->tx_queue_id / cdev->num_hwfns);
1543 if (rc) {
1544 DP_ERR(cdev, "Failed to stop TXQ#%d\n", params->tx_queue_id);
1545 return rc;
1546 }
1547
1548 return 0;
1549}
1550
1551static int qed_configure_filter_rx_mode(struct qed_dev *cdev,
1552 enum qed_filter_rx_mode_type type)
1553{
1554 struct qed_filter_accept_flags accept_flags;
1555
1556 memset(&accept_flags, 0, sizeof(accept_flags));
1557
1558 accept_flags.update_rx_mode_config = 1;
1559 accept_flags.update_tx_mode_config = 1;
1560 accept_flags.rx_accept_filter = QED_ACCEPT_UCAST_MATCHED |
1561 QED_ACCEPT_MCAST_MATCHED |
1562 QED_ACCEPT_BCAST;
1563 accept_flags.tx_accept_filter = QED_ACCEPT_UCAST_MATCHED |
1564 QED_ACCEPT_MCAST_MATCHED |
1565 QED_ACCEPT_BCAST;
1566
1567 if (type == QED_FILTER_RX_MODE_TYPE_PROMISC)
1568 accept_flags.rx_accept_filter |= QED_ACCEPT_UCAST_UNMATCHED |
1569 QED_ACCEPT_MCAST_UNMATCHED;
1570 else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC)
1571 accept_flags.rx_accept_filter |= QED_ACCEPT_MCAST_UNMATCHED;
1572
3f9b4a69 1573 return qed_filter_accept_cmd(cdev, 0, accept_flags, false, false,
cee4d264
MC		 1574 QED_SPQ_MODE_CB, NULL);
1575}
1576
1577static int qed_configure_filter_ucast(struct qed_dev *cdev,
1578 struct qed_filter_ucast_params *params)
1579{
1580 struct qed_filter_ucast ucast;
1581
1582 if (!params->vlan_valid && !params->mac_valid) {
1583 DP_NOTICE(
1584 cdev,
1585 "Tried configuring a unicast filter, but both MAC and VLAN are not set\n");
1586 return -EINVAL;
1587 }
1588
1589 memset(&ucast, 0, sizeof(ucast));
1590 switch (params->type) {
1591 case QED_FILTER_XCAST_TYPE_ADD:
1592 ucast.opcode = QED_FILTER_ADD;
1593 break;
1594 case QED_FILTER_XCAST_TYPE_DEL:
1595 ucast.opcode = QED_FILTER_REMOVE;
1596 break;
1597 case QED_FILTER_XCAST_TYPE_REPLACE:
1598 ucast.opcode = QED_FILTER_REPLACE;
1599 break;
1600 default:
1601 DP_NOTICE(cdev, "Unknown unicast filter type %d\n",
1602 params->type);
1603 }
1604
1605 if (params->vlan_valid && params->mac_valid) {
1606 ucast.type = QED_FILTER_MAC_VLAN;
1607 ether_addr_copy(ucast.mac, params->mac);
1608 ucast.vlan = params->vlan;
1609 } else if (params->mac_valid) {
1610 ucast.type = QED_FILTER_MAC;
1611 ether_addr_copy(ucast.mac, params->mac);
1612 } else {
1613 ucast.type = QED_FILTER_VLAN;
1614 ucast.vlan = params->vlan;
1615 }
1616
1617 ucast.is_rx_filter = true;
1618 ucast.is_tx_filter = true;
1619
1620 return qed_filter_ucast_cmd(cdev, &ucast, QED_SPQ_MODE_CB, NULL);
1621}
1622
1623static int qed_configure_filter_mcast(struct qed_dev *cdev,
1624 struct qed_filter_mcast_params *params)
1625{
1626 struct qed_filter_mcast mcast;
1627 int i;
1628
1629 memset(&mcast, 0, sizeof(mcast));
1630 switch (params->type) {
1631 case QED_FILTER_XCAST_TYPE_ADD:
1632 mcast.opcode = QED_FILTER_ADD;
1633 break;
1634 case QED_FILTER_XCAST_TYPE_DEL:
1635 mcast.opcode = QED_FILTER_REMOVE;
1636 break;
1637 default:
1638 DP_NOTICE(cdev, "Unknown multicast filter type %d\n",
1639 params->type);
1640 }
1641
1642 mcast.num_mc_addrs = params->num;
1643 for (i = 0; i < mcast.num_mc_addrs; i++)
1644 ether_addr_copy(mcast.mac[i], params->mac[i]);
1645
1646 return qed_filter_mcast_cmd(cdev, &mcast,
1647 QED_SPQ_MODE_CB, NULL);
1648}
1649
1650static int qed_configure_filter(struct qed_dev *cdev,
1651 struct qed_filter_params *params)
1652{
1653 enum qed_filter_rx_mode_type accept_flags;
1654
1655 switch (params->type) {
1656 case QED_FILTER_TYPE_UCAST:
1657 return qed_configure_filter_ucast(cdev, &params->filter.ucast);
1658 case QED_FILTER_TYPE_MCAST:
1659 return qed_configure_filter_mcast(cdev, &params->filter.mcast);
1660 case QED_FILTER_TYPE_RX_MODE:
1661 accept_flags = params->filter.accept_flags;
1662 return qed_configure_filter_rx_mode(cdev, accept_flags);
1663 default:
1664 DP_NOTICE(cdev, "Unknown filter type %d\n",
1665 (int)params->type);
1666 return -EINVAL;
1667 }
1668}
1669
1670static int qed_fp_cqe_completion(struct qed_dev *dev,
1671 u8 rss_id,
1672 struct eth_slow_path_rx_cqe *cqe)
1673{
1674 return qed_eth_cqe_completion(&dev->hwfns[rss_id % dev->num_hwfns],
1675 cqe);
1676}
1677
25c089d7
YM		 1678static const struct qed_eth_ops qed_eth_ops_pass = {
1679 .common = &qed_common_ops_pass,
1680 .fill_dev_info = &qed_fill_eth_dev_info,
cc875c2e 1681 .register_ops = &qed_register_eth_ops,
cee4d264
MC		 1682 .vport_start = &qed_start_vport,
1683 .vport_stop = &qed_stop_vport,
1684 .vport_update = &qed_update_vport,
1685 .q_rx_start = &qed_start_rxq,
1686 .q_rx_stop = &qed_stop_rxq,
1687 .q_tx_start = &qed_start_txq,
1688 .q_tx_stop = &qed_stop_txq,
1689 .filter_config = &qed_configure_filter,
1690 .fastpath_stop = &qed_fastpath_stop,
1691 .eth_cqe_completion = &qed_fp_cqe_completion,
9df2ed04 1692 .get_vport_stats = &qed_get_vport_stats,
25c089d7
YM		 1693};
1694
1695const struct qed_eth_ops *qed_get_eth_ops(u32 version)
1696{
1697 if (version != QED_ETH_INTERFACE_VERSION) {
1698 pr_notice("Cannot supply ethtool operations [%08x != %08x]\n",
1699 version, QED_ETH_INTERFACE_VERSION);
1700 return NULL;
1701 }
1702
1703 return &qed_eth_ops_pass;
1704}
1705EXPORT_SYMBOL(qed_get_eth_ops);
1706
1707void qed_put_eth_ops(void)
1708{
1709 /* TODO - reference count for module? */
1710}
1711EXPORT_SYMBOL(qed_put_eth_ops);
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