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qed*: Support PVID configuration
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / qlogic / qed / qed_l2.c
CommitLineData
25c089d7
YM		 1/* QLogic qed NIC Driver
2 * Copyright (c) 2015 QLogic Corporation
3 *
4 * This software is available under the terms of the GNU General Public License
5 * (GPL) Version 2, available from the file COPYING in the main directory of
6 * this source tree.
7 */
8
9#include <linux/types.h>
10#include <asm/byteorder.h>
11#include <asm/param.h>
12#include <linux/delay.h>
13#include <linux/dma-mapping.h>
14#include <linux/etherdevice.h>
15#include <linux/interrupt.h>
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/pci.h>
19#include <linux/slab.h>
20#include <linux/stddef.h>
21#include <linux/string.h>
22#include <linux/version.h>
23#include <linux/workqueue.h>
24#include <linux/bitops.h>
25#include <linux/bug.h>
26#include "qed.h"
27#include <linux/qed/qed_chain.h>
28#include "qed_cxt.h"
29#include "qed_dev_api.h"
30#include <linux/qed/qed_eth_if.h>
31#include "qed_hsi.h"
32#include "qed_hw.h"
33#include "qed_int.h"
dacd88d6 34#include "qed_l2.h"
86622ee7 35#include "qed_mcp.h"
25c089d7
YM		 36#include "qed_reg_addr.h"
37#include "qed_sp.h"
1408cc1f 38#include "qed_sriov.h"
25c089d7 39
088c8618 40
cee4d264
MC		 41#define QED_MAX_SGES_NUM 16
42#define CRC32_POLY 0x1edc6f41
43
dacd88d6
YM		 44int qed_sp_eth_vport_start(struct qed_hwfn *p_hwfn,
45 struct qed_sp_vport_start_params *p_params)
cee4d264 46{
cee4d264
MC		 47 struct vport_start_ramrod_data *p_ramrod = NULL;
48 struct qed_spq_entry *p_ent = NULL;
06f56b81 49 struct qed_sp_init_data init_data;
dacd88d6 50 u8 abs_vport_id = 0;
cee4d264
MC		 51 int rc = -EINVAL;
52 u16 rx_mode = 0;
cee4d264 53
088c8618 54 rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
cee4d264
MC		 55 if (rc != 0)
56 return rc;
57
06f56b81
YM		 58 memset(&init_data, 0, sizeof(init_data));
59 init_data.cid = qed_spq_get_cid(p_hwfn);
088c8618 60 init_data.opaque_fid = p_params->opaque_fid;
06f56b81 61 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
cee4d264
MC		 62
63 rc = qed_sp_init_request(p_hwfn, &p_ent,
cee4d264 64 ETH_RAMROD_VPORT_START,
06f56b81 65 PROTOCOLID_ETH, &init_data);
cee4d264
MC		 66 if (rc)
67 return rc;
68
69 p_ramrod = &p_ent->ramrod.vport_start;
70 p_ramrod->vport_id = abs_vport_id;
71
088c8618
MC		 72 p_ramrod->mtu = cpu_to_le16(p_params->mtu);
73 p_ramrod->inner_vlan_removal_en = p_params->remove_inner_vlan;
74 p_ramrod->drop_ttl0_en = p_params->drop_ttl0;
cee4d264
MC		 75
76 SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_UCAST_DROP_ALL, 1);
77 SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_MCAST_DROP_ALL, 1);
78
79 p_ramrod->rx_mode.state = cpu_to_le16(rx_mode);
80
81 /* TPA related fields */
82 memset(&p_ramrod->tpa_param, 0,
83 sizeof(struct eth_vport_tpa_param));
84
088c8618
MC		 85 p_ramrod->tpa_param.max_buff_num = p_params->max_buffers_per_cqe;
86
87 switch (p_params->tpa_mode) {
88 case QED_TPA_MODE_GRO:
89 p_ramrod->tpa_param.tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
90 p_ramrod->tpa_param.tpa_max_size = (u16)-1;
91 p_ramrod->tpa_param.tpa_min_size_to_cont = p_params->mtu / 2;
92 p_ramrod->tpa_param.tpa_min_size_to_start = p_params->mtu / 2;
93 p_ramrod->tpa_param.tpa_ipv4_en_flg = 1;
94 p_ramrod->tpa_param.tpa_ipv6_en_flg = 1;
95 p_ramrod->tpa_param.tpa_pkt_split_flg = 1;
96 p_ramrod->tpa_param.tpa_gro_consistent_flg = 1;
97 break;
98 default:
99 break;
100 }
101
cee4d264
MC		 102 /* Software Function ID in hwfn (PFs are 0 - 15, VFs are 16 - 135) */
103 p_ramrod->sw_fid = qed_concrete_to_sw_fid(p_hwfn->cdev,
088c8618 104 p_params->concrete_fid);
cee4d264
MC		 105
106 return qed_spq_post(p_hwfn, p_ent, NULL);
107}
108
dacd88d6
YM		 109int qed_sp_vport_start(struct qed_hwfn *p_hwfn,
110 struct qed_sp_vport_start_params *p_params)
111{
112 if (IS_VF(p_hwfn->cdev)) {
113 return qed_vf_pf_vport_start(p_hwfn, p_params->vport_id,
114 p_params->mtu,
115 p_params->remove_inner_vlan,
116 p_params->tpa_mode,
08feecd7
YM		 117 p_params->max_buffers_per_cqe,
118 p_params->only_untagged);
dacd88d6
YM		 119 }
120
121 return qed_sp_eth_vport_start(p_hwfn, p_params);
122}
123
cee4d264
MC		 124static int
125qed_sp_vport_update_rss(struct qed_hwfn *p_hwfn,
126 struct vport_update_ramrod_data *p_ramrod,
127 struct qed_rss_params *p_params)
128{
129 struct eth_vport_rss_config *rss = &p_ramrod->rss_config;
130 u16 abs_l2_queue = 0, capabilities = 0;
131 int rc = 0, i;
132
133 if (!p_params) {
134 p_ramrod->common.update_rss_flg = 0;
135 return rc;
136 }
137
138 BUILD_BUG_ON(QED_RSS_IND_TABLE_SIZE !=
139 ETH_RSS_IND_TABLE_ENTRIES_NUM);
140
141 rc = qed_fw_rss_eng(p_hwfn, p_params->rss_eng_id, &rss->rss_id);
142 if (rc)
143 return rc;
144
145 p_ramrod->common.update_rss_flg = p_params->update_rss_config;
146 rss->update_rss_capabilities = p_params->update_rss_capabilities;
147 rss->update_rss_ind_table = p_params->update_rss_ind_table;
148 rss->update_rss_key = p_params->update_rss_key;
149
150 rss->rss_mode = p_params->rss_enable ?
151 ETH_VPORT_RSS_MODE_REGULAR :
152 ETH_VPORT_RSS_MODE_DISABLED;
153
154 SET_FIELD(capabilities,
155 ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY,
156 !!(p_params->rss_caps & QED_RSS_IPV4));
157 SET_FIELD(capabilities,
158 ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY,
159 !!(p_params->rss_caps & QED_RSS_IPV6));
160 SET_FIELD(capabilities,
161 ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY,
162 !!(p_params->rss_caps & QED_RSS_IPV4_TCP));
163 SET_FIELD(capabilities,
164 ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY,
165 !!(p_params->rss_caps & QED_RSS_IPV6_TCP));
166 SET_FIELD(capabilities,
167 ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY,
168 !!(p_params->rss_caps & QED_RSS_IPV4_UDP));
169 SET_FIELD(capabilities,
170 ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY,
171 !!(p_params->rss_caps & QED_RSS_IPV6_UDP));
172 rss->tbl_size = p_params->rss_table_size_log;
173
174 rss->capabilities = cpu_to_le16(capabilities);
175
176 DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP,
177 "update rss flag %d, rss_mode = %d, update_caps = %d, capabilities = %d, update_ind = %d, update_rss_key = %d\n",
178 p_ramrod->common.update_rss_flg,
179 rss->rss_mode, rss->update_rss_capabilities,
180 capabilities, rss->update_rss_ind_table,
181 rss->update_rss_key);
182
183 for (i = 0; i < QED_RSS_IND_TABLE_SIZE; i++) {
184 rc = qed_fw_l2_queue(p_hwfn,
185 (u8)p_params->rss_ind_table[i],
186 &abs_l2_queue);
187 if (rc)
188 return rc;
189
190 rss->indirection_table[i] = cpu_to_le16(abs_l2_queue);
191 DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP, "i= %d, queue = %d\n",
192 i, rss->indirection_table[i]);
193 }
194
195 for (i = 0; i < 10; i++)
196 rss->rss_key[i] = cpu_to_le32(p_params->rss_key[i]);
197
198 return rc;
199}
200
201static void
202qed_sp_update_accept_mode(struct qed_hwfn *p_hwfn,
203 struct vport_update_ramrod_data *p_ramrod,
204 struct qed_filter_accept_flags accept_flags)
205{
206 p_ramrod->common.update_rx_mode_flg =
207 accept_flags.update_rx_mode_config;
208
209 p_ramrod->common.update_tx_mode_flg =
210 accept_flags.update_tx_mode_config;
211
212 /* Set Rx mode accept flags */
213 if (p_ramrod->common.update_rx_mode_flg) {
214 u8 accept_filter = accept_flags.rx_accept_filter;
215 u16 state = 0;
216
217 SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_DROP_ALL,
218 !(!!(accept_filter & QED_ACCEPT_UCAST_MATCHED) ||
219 !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED)));
220
221 SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED,
222 !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED));
223
224 SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_DROP_ALL,
225 !(!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) ||
226 !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED)));
227
228 SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL,
229 (!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) &&
230 !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED)));
231
232 SET_FIELD(state, ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL,
233 !!(accept_filter & QED_ACCEPT_BCAST));
234
235 p_ramrod->rx_mode.state = cpu_to_le16(state);
236 DP_VERBOSE(p_hwfn, QED_MSG_SP,
237 "p_ramrod->rx_mode.state = 0x%x\n", state);
238 }
239
240 /* Set Tx mode accept flags */
241 if (p_ramrod->common.update_tx_mode_flg) {
242 u8 accept_filter = accept_flags.tx_accept_filter;
243 u16 state = 0;
244
245 SET_FIELD(state, ETH_VPORT_TX_MODE_UCAST_DROP_ALL,
246 !!(accept_filter & QED_ACCEPT_NONE));
247
248 SET_FIELD(state, ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL,
249 (!!(accept_filter & QED_ACCEPT_UCAST_MATCHED) &&
250 !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED)));
251
252 SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_DROP_ALL,
253 !!(accept_filter & QED_ACCEPT_NONE));
254
255 SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL,
256 (!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) &&
257 !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED)));
258
259 SET_FIELD(state, ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL,
260 !!(accept_filter & QED_ACCEPT_BCAST));
261
262 p_ramrod->tx_mode.state = cpu_to_le16(state);
263 DP_VERBOSE(p_hwfn, QED_MSG_SP,
264 "p_ramrod->tx_mode.state = 0x%x\n", state);
265 }
266}
267
17b235c1
YM		 268static void
269qed_sp_vport_update_sge_tpa(struct qed_hwfn *p_hwfn,
270 struct vport_update_ramrod_data *p_ramrod,
271 struct qed_sge_tpa_params *p_params)
272{
273 struct eth_vport_tpa_param *p_tpa;
274
275 if (!p_params) {
276 p_ramrod->common.update_tpa_param_flg = 0;
277 p_ramrod->common.update_tpa_en_flg = 0;
278 p_ramrod->common.update_tpa_param_flg = 0;
279 return;
280 }
281
282 p_ramrod->common.update_tpa_en_flg = p_params->update_tpa_en_flg;
283 p_tpa = &p_ramrod->tpa_param;
284 p_tpa->tpa_ipv4_en_flg = p_params->tpa_ipv4_en_flg;
285 p_tpa->tpa_ipv6_en_flg = p_params->tpa_ipv6_en_flg;
286 p_tpa->tpa_ipv4_tunn_en_flg = p_params->tpa_ipv4_tunn_en_flg;
287 p_tpa->tpa_ipv6_tunn_en_flg = p_params->tpa_ipv6_tunn_en_flg;
288
289 p_ramrod->common.update_tpa_param_flg = p_params->update_tpa_param_flg;
290 p_tpa->max_buff_num = p_params->max_buffers_per_cqe;
291 p_tpa->tpa_pkt_split_flg = p_params->tpa_pkt_split_flg;
292 p_tpa->tpa_hdr_data_split_flg = p_params->tpa_hdr_data_split_flg;
293 p_tpa->tpa_gro_consistent_flg = p_params->tpa_gro_consistent_flg;
294 p_tpa->tpa_max_aggs_num = p_params->tpa_max_aggs_num;
295 p_tpa->tpa_max_size = p_params->tpa_max_size;
296 p_tpa->tpa_min_size_to_start = p_params->tpa_min_size_to_start;
297 p_tpa->tpa_min_size_to_cont = p_params->tpa_min_size_to_cont;
298}
299
cee4d264
MC		 300static void
301qed_sp_update_mcast_bin(struct qed_hwfn *p_hwfn,
302 struct vport_update_ramrod_data *p_ramrod,
303 struct qed_sp_vport_update_params *p_params)
304{
305 int i;
306
307 memset(&p_ramrod->approx_mcast.bins, 0,
308 sizeof(p_ramrod->approx_mcast.bins));
309
310 if (p_params->update_approx_mcast_flg) {
311 p_ramrod->common.update_approx_mcast_flg = 1;
312 for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) {
313 u32 *p_bins = (u32 *)p_params->bins;
314 __le32 val = cpu_to_le32(p_bins[i]);
315
316 p_ramrod->approx_mcast.bins[i] = val;
317 }
318 }
319}
320
dacd88d6
YM		 321int qed_sp_vport_update(struct qed_hwfn *p_hwfn,
322 struct qed_sp_vport_update_params *p_params,
323 enum spq_mode comp_mode,
324 struct qed_spq_comp_cb *p_comp_data)
cee4d264
MC		 325{
326 struct qed_rss_params *p_rss_params = p_params->rss_params;
327 struct vport_update_ramrod_data_cmn *p_cmn;
06f56b81 328 struct qed_sp_init_data init_data;
cee4d264
MC		 329 struct vport_update_ramrod_data *p_ramrod = NULL;
330 struct qed_spq_entry *p_ent = NULL;
17b235c1 331 u8 abs_vport_id = 0, val;
cee4d264
MC		 332 int rc = -EINVAL;
333
dacd88d6
YM		 334 if (IS_VF(p_hwfn->cdev)) {
335 rc = qed_vf_pf_vport_update(p_hwfn, p_params);
336 return rc;
337 }
338
cee4d264
MC		 339 rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
340 if (rc != 0)
341 return rc;
342
06f56b81
YM		 343 memset(&init_data, 0, sizeof(init_data));
344 init_data.cid = qed_spq_get_cid(p_hwfn);
345 init_data.opaque_fid = p_params->opaque_fid;
346 init_data.comp_mode = comp_mode;
347 init_data.p_comp_data = p_comp_data;
cee4d264
MC		 348
349 rc = qed_sp_init_request(p_hwfn, &p_ent,
cee4d264 350 ETH_RAMROD_VPORT_UPDATE,
06f56b81 351 PROTOCOLID_ETH, &init_data);
cee4d264
MC		 352 if (rc)
353 return rc;
354
355 /* Copy input params to ramrod according to FW struct */
356 p_ramrod = &p_ent->ramrod.vport_update;
357 p_cmn = &p_ramrod->common;
358
359 p_cmn->vport_id = abs_vport_id;
360 p_cmn->rx_active_flg = p_params->vport_active_rx_flg;
361 p_cmn->update_rx_active_flg = p_params->update_vport_active_rx_flg;
362 p_cmn->tx_active_flg = p_params->vport_active_tx_flg;
363 p_cmn->update_tx_active_flg = p_params->update_vport_active_tx_flg;
3f9b4a69
YM		 364 p_cmn->accept_any_vlan = p_params->accept_any_vlan;
365 p_cmn->update_accept_any_vlan_flg =
366 p_params->update_accept_any_vlan_flg;
17b235c1
YM		 367
368 p_cmn->inner_vlan_removal_en = p_params->inner_vlan_removal_flg;
369 val = p_params->update_inner_vlan_removal_flg;
370 p_cmn->update_inner_vlan_removal_en_flg = val;
08feecd7
YM		 371
372 p_cmn->default_vlan_en = p_params->default_vlan_enable_flg;
373 val = p_params->update_default_vlan_enable_flg;
374 p_cmn->update_default_vlan_en_flg = val;
375
376 p_cmn->default_vlan = cpu_to_le16(p_params->default_vlan);
377 p_cmn->update_default_vlan_flg = p_params->update_default_vlan_flg;
378
379 p_cmn->silent_vlan_removal_en = p_params->silent_vlan_removal_flg;
380
17b235c1
YM		 381 p_ramrod->common.tx_switching_en = p_params->tx_switching_flg;
382 p_cmn->update_tx_switching_en_flg = p_params->update_tx_switching_flg;
383
cee4d264
MC		 384 rc = qed_sp_vport_update_rss(p_hwfn, p_ramrod, p_rss_params);
385 if (rc) {
386 /* Return spq entry which is taken in qed_sp_init_request()*/
387 qed_spq_return_entry(p_hwfn, p_ent);
388 return rc;
389 }
390
391 /* Update mcast bins for VFs, PF doesn't use this functionality */
392 qed_sp_update_mcast_bin(p_hwfn, p_ramrod, p_params);
393
394 qed_sp_update_accept_mode(p_hwfn, p_ramrod, p_params->accept_flags);
17b235c1 395 qed_sp_vport_update_sge_tpa(p_hwfn, p_ramrod, p_params->sge_tpa_params);
cee4d264
MC		 396 return qed_spq_post(p_hwfn, p_ent, NULL);
397}
398
dacd88d6 399int qed_sp_vport_stop(struct qed_hwfn *p_hwfn, u16 opaque_fid, u8 vport_id)
cee4d264 400{
cee4d264 401 struct vport_stop_ramrod_data *p_ramrod;
06f56b81 402 struct qed_sp_init_data init_data;
cee4d264
MC		 403 struct qed_spq_entry *p_ent;
404 u8 abs_vport_id = 0;
405 int rc;
406
dacd88d6
YM		 407 if (IS_VF(p_hwfn->cdev))
408 return qed_vf_pf_vport_stop(p_hwfn);
409
cee4d264
MC		 410 rc = qed_fw_vport(p_hwfn, vport_id, &abs_vport_id);
411 if (rc != 0)
412 return rc;
413
06f56b81
YM		 414 memset(&init_data, 0, sizeof(init_data));
415 init_data.cid = qed_spq_get_cid(p_hwfn);
416 init_data.opaque_fid = opaque_fid;
417 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
cee4d264
MC		 418
419 rc = qed_sp_init_request(p_hwfn, &p_ent,
cee4d264 420 ETH_RAMROD_VPORT_STOP,
06f56b81 421 PROTOCOLID_ETH, &init_data);
cee4d264
MC		 422 if (rc)
423 return rc;
424
425 p_ramrod = &p_ent->ramrod.vport_stop;
426 p_ramrod->vport_id = abs_vport_id;
427
428 return qed_spq_post(p_hwfn, p_ent, NULL);
429}
430
dacd88d6
YM		 431static int
432qed_vf_pf_accept_flags(struct qed_hwfn *p_hwfn,
433 struct qed_filter_accept_flags *p_accept_flags)
434{
435 struct qed_sp_vport_update_params s_params;
436
437 memset(&s_params, 0, sizeof(s_params));
438 memcpy(&s_params.accept_flags, p_accept_flags,
439 sizeof(struct qed_filter_accept_flags));
440
441 return qed_vf_pf_vport_update(p_hwfn, &s_params);
442}
443
cee4d264
MC		 444static int qed_filter_accept_cmd(struct qed_dev *cdev,
445 u8 vport,
446 struct qed_filter_accept_flags accept_flags,
3f9b4a69
YM		 447 u8 update_accept_any_vlan,
448 u8 accept_any_vlan,
dacd88d6
YM		 449 enum spq_mode comp_mode,
450 struct qed_spq_comp_cb *p_comp_data)
cee4d264
MC		 451{
452 struct qed_sp_vport_update_params vport_update_params;
453 int i, rc;
454
455 /* Prepare and send the vport rx_mode change */
456 memset(&vport_update_params, 0, sizeof(vport_update_params));
457 vport_update_params.vport_id = vport;
458 vport_update_params.accept_flags = accept_flags;
3f9b4a69
YM		 459 vport_update_params.update_accept_any_vlan_flg = update_accept_any_vlan;
460 vport_update_params.accept_any_vlan = accept_any_vlan;
cee4d264
MC		 461
462 for_each_hwfn(cdev, i) {
463 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
464
465 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
466
dacd88d6
YM		 467 if (IS_VF(cdev)) {
468 rc = qed_vf_pf_accept_flags(p_hwfn, &accept_flags);
469 if (rc)
470 return rc;
471 continue;
472 }
473
cee4d264
MC		 474 rc = qed_sp_vport_update(p_hwfn, &vport_update_params,
475 comp_mode, p_comp_data);
476 if (rc != 0) {
477 DP_ERR(cdev, "Update rx_mode failed %d\n", rc);
478 return rc;
479 }
480
481 DP_VERBOSE(p_hwfn, QED_MSG_SP,
482 "Accept filter configured, flags = [Rx]%x [Tx]%x\n",
483 accept_flags.rx_accept_filter,
484 accept_flags.tx_accept_filter);
3f9b4a69
YM		 485 if (update_accept_any_vlan)
486 DP_VERBOSE(p_hwfn, QED_MSG_SP,
487 "accept_any_vlan=%d configured\n",
488 accept_any_vlan);
cee4d264
MC		 489 }
490
491 return 0;
492}
493
494static int qed_sp_release_queue_cid(
495 struct qed_hwfn *p_hwfn,
496 struct qed_hw_cid_data *p_cid_data)
497{
498 if (!p_cid_data->b_cid_allocated)
499 return 0;
500
501 qed_cxt_release_cid(p_hwfn, p_cid_data->cid);
502
503 p_cid_data->b_cid_allocated = false;
504
505 return 0;
506}
507
dacd88d6
YM		 508int qed_sp_eth_rxq_start_ramrod(struct qed_hwfn *p_hwfn,
509 u16 opaque_fid,
510 u32 cid,
511 struct qed_queue_start_common_params *params,
512 u8 stats_id,
513 u16 bd_max_bytes,
514 dma_addr_t bd_chain_phys_addr,
515 dma_addr_t cqe_pbl_addr, u16 cqe_pbl_size)
cee4d264
MC		 516{
517 struct rx_queue_start_ramrod_data *p_ramrod = NULL;
cee4d264 518 struct qed_spq_entry *p_ent = NULL;
06f56b81 519 struct qed_sp_init_data init_data;
cee4d264
MC		 520 struct qed_hw_cid_data *p_rx_cid;
521 u16 abs_rx_q_id = 0;
522 u8 abs_vport_id = 0;
523 int rc = -EINVAL;
524
525 /* Store information for the stop */
526 p_rx_cid = &p_hwfn->p_rx_cids[params->queue_id];
527 p_rx_cid->cid = cid;
528 p_rx_cid->opaque_fid = opaque_fid;
529 p_rx_cid->vport_id = params->vport_id;
530
531 rc = qed_fw_vport(p_hwfn, params->vport_id, &abs_vport_id);
532 if (rc != 0)
533 return rc;
534
535 rc = qed_fw_l2_queue(p_hwfn, params->queue_id, &abs_rx_q_id);
536 if (rc != 0)
537 return rc;
538
539 DP_VERBOSE(p_hwfn, QED_MSG_SP,
540 "opaque_fid=0x%x, cid=0x%x, rx_qid=0x%x, vport_id=0x%x, sb_id=0x%x\n",
541 opaque_fid, cid, params->queue_id, params->vport_id,
542 params->sb);
543
06f56b81
YM		 544 /* Get SPQ entry */
545 memset(&init_data, 0, sizeof(init_data));
546 init_data.cid = cid;
547 init_data.opaque_fid = opaque_fid;
548 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
cee4d264
MC		 549
550 rc = qed_sp_init_request(p_hwfn, &p_ent,
cee4d264 551 ETH_RAMROD_RX_QUEUE_START,
06f56b81 552 PROTOCOLID_ETH, &init_data);
cee4d264
MC		 553 if (rc)
554 return rc;
555
556 p_ramrod = &p_ent->ramrod.rx_queue_start;
557
558 p_ramrod->sb_id = cpu_to_le16(params->sb);
559 p_ramrod->sb_index = params->sb_idx;
560 p_ramrod->vport_id = abs_vport_id;
561 p_ramrod->stats_counter_id = stats_id;
562 p_ramrod->rx_queue_id = cpu_to_le16(abs_rx_q_id);
563 p_ramrod->complete_cqe_flg = 0;
564 p_ramrod->complete_event_flg = 1;
565
566 p_ramrod->bd_max_bytes = cpu_to_le16(bd_max_bytes);
94494598 567 DMA_REGPAIR_LE(p_ramrod->bd_base, bd_chain_phys_addr);
cee4d264
MC		 568
569 p_ramrod->num_of_pbl_pages = cpu_to_le16(cqe_pbl_size);
94494598 570 DMA_REGPAIR_LE(p_ramrod->cqe_pbl_addr, cqe_pbl_addr);
cee4d264
MC		 571
572 rc = qed_spq_post(p_hwfn, p_ent, NULL);
573
574 return rc;
575}
576
577static int
578qed_sp_eth_rx_queue_start(struct qed_hwfn *p_hwfn,
579 u16 opaque_fid,
580 struct qed_queue_start_common_params *params,
581 u16 bd_max_bytes,
582 dma_addr_t bd_chain_phys_addr,
583 dma_addr_t cqe_pbl_addr,
dacd88d6 584 u16 cqe_pbl_size, void __iomem **pp_prod)
cee4d264
MC		 585{
586 struct qed_hw_cid_data *p_rx_cid;
587 u64 init_prod_val = 0;
588 u16 abs_l2_queue = 0;
589 u8 abs_stats_id = 0;
590 int rc;
591
dacd88d6
YM		 592 if (IS_VF(p_hwfn->cdev)) {
593 return qed_vf_pf_rxq_start(p_hwfn,
594 params->queue_id,
595 params->sb,
596 params->sb_idx,
597 bd_max_bytes,
598 bd_chain_phys_addr,
599 cqe_pbl_addr, cqe_pbl_size, pp_prod);
600 }
601
cee4d264
MC		 602 rc = qed_fw_l2_queue(p_hwfn, params->queue_id, &abs_l2_queue);
603 if (rc != 0)
604 return rc;
605
606 rc = qed_fw_vport(p_hwfn, params->vport_id, &abs_stats_id);
607 if (rc != 0)
608 return rc;
609
610 *pp_prod = (u8 __iomem *)p_hwfn->regview +
611 GTT_BAR0_MAP_REG_MSDM_RAM +
612 MSTORM_PRODS_OFFSET(abs_l2_queue);
613
614 /* Init the rcq, rx bd and rx sge (if valid) producers to 0 */
615 __internal_ram_wr(p_hwfn, *pp_prod, sizeof(u64),
616 (u32 *)(&init_prod_val));
617
618 /* Allocate a CID for the queue */
619 p_rx_cid = &p_hwfn->p_rx_cids[params->queue_id];
620 rc = qed_cxt_acquire_cid(p_hwfn, PROTOCOLID_ETH,
621 &p_rx_cid->cid);
622 if (rc) {
623 DP_NOTICE(p_hwfn, "Failed to acquire cid\n");
624 return rc;
625 }
626 p_rx_cid->b_cid_allocated = true;
627
628 rc = qed_sp_eth_rxq_start_ramrod(p_hwfn,
629 opaque_fid,
630 p_rx_cid->cid,
631 params,
632 abs_stats_id,
633 bd_max_bytes,
634 bd_chain_phys_addr,
635 cqe_pbl_addr,
636 cqe_pbl_size);
637
638 if (rc != 0)
639 qed_sp_release_queue_cid(p_hwfn, p_rx_cid);
640
641 return rc;
642}
643
17b235c1
YM		 644int qed_sp_eth_rx_queues_update(struct qed_hwfn *p_hwfn,
645 u16 rx_queue_id,
646 u8 num_rxqs,
647 u8 complete_cqe_flg,
648 u8 complete_event_flg,
649 enum spq_mode comp_mode,
650 struct qed_spq_comp_cb *p_comp_data)
651{
652 struct rx_queue_update_ramrod_data *p_ramrod = NULL;
653 struct qed_spq_entry *p_ent = NULL;
654 struct qed_sp_init_data init_data;
655 struct qed_hw_cid_data *p_rx_cid;
656 u16 qid, abs_rx_q_id = 0;
657 int rc = -EINVAL;
658 u8 i;
659
660 memset(&init_data, 0, sizeof(init_data));
661 init_data.comp_mode = comp_mode;
662 init_data.p_comp_data = p_comp_data;
663
664 for (i = 0; i < num_rxqs; i++) {
665 qid = rx_queue_id + i;
666 p_rx_cid = &p_hwfn->p_rx_cids[qid];
667
668 /* Get SPQ entry */
669 init_data.cid = p_rx_cid->cid;
670 init_data.opaque_fid = p_rx_cid->opaque_fid;
671
672 rc = qed_sp_init_request(p_hwfn, &p_ent,
673 ETH_RAMROD_RX_QUEUE_UPDATE,
674 PROTOCOLID_ETH, &init_data);
675 if (rc)
676 return rc;
677
678 p_ramrod = &p_ent->ramrod.rx_queue_update;
679
680 qed_fw_vport(p_hwfn, p_rx_cid->vport_id, &p_ramrod->vport_id);
681 qed_fw_l2_queue(p_hwfn, qid, &abs_rx_q_id);
682 p_ramrod->rx_queue_id = cpu_to_le16(abs_rx_q_id);
683 p_ramrod->complete_cqe_flg = complete_cqe_flg;
684 p_ramrod->complete_event_flg = complete_event_flg;
685
686 rc = qed_spq_post(p_hwfn, p_ent, NULL);
687 if (rc)
688 return rc;
689 }
690
691 return rc;
692}
693
dacd88d6
YM		 694int qed_sp_eth_rx_queue_stop(struct qed_hwfn *p_hwfn,
695 u16 rx_queue_id,
696 bool eq_completion_only, bool cqe_completion)
cee4d264
MC		 697{
698 struct qed_hw_cid_data *p_rx_cid = &p_hwfn->p_rx_cids[rx_queue_id];
699 struct rx_queue_stop_ramrod_data *p_ramrod = NULL;
cee4d264 700 struct qed_spq_entry *p_ent = NULL;
06f56b81 701 struct qed_sp_init_data init_data;
cee4d264
MC		 702 u16 abs_rx_q_id = 0;
703 int rc = -EINVAL;
704
dacd88d6
YM		 705 if (IS_VF(p_hwfn->cdev))
706 return qed_vf_pf_rxq_stop(p_hwfn, rx_queue_id, cqe_completion);
707
06f56b81
YM		 708 /* Get SPQ entry */
709 memset(&init_data, 0, sizeof(init_data));
710 init_data.cid = p_rx_cid->cid;
711 init_data.opaque_fid = p_rx_cid->opaque_fid;
712 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
cee4d264
MC		 713
714 rc = qed_sp_init_request(p_hwfn, &p_ent,
cee4d264 715 ETH_RAMROD_RX_QUEUE_STOP,
06f56b81 716 PROTOCOLID_ETH, &init_data);
cee4d264
MC		 717 if (rc)
718 return rc;
719
720 p_ramrod = &p_ent->ramrod.rx_queue_stop;
721
722 qed_fw_vport(p_hwfn, p_rx_cid->vport_id, &p_ramrod->vport_id);
723 qed_fw_l2_queue(p_hwfn, rx_queue_id, &abs_rx_q_id);
724 p_ramrod->rx_queue_id = cpu_to_le16(abs_rx_q_id);
725
726 /* Cleaning the queue requires the completion to arrive there.
727 * In addition, VFs require the answer to come as eqe to PF.
728 */
729 p_ramrod->complete_cqe_flg =
730 (!!(p_rx_cid->opaque_fid == p_hwfn->hw_info.opaque_fid) &&
731 !eq_completion_only) || cqe_completion;
732 p_ramrod->complete_event_flg =
733 !(p_rx_cid->opaque_fid == p_hwfn->hw_info.opaque_fid) ||
734 eq_completion_only;
735
736 rc = qed_spq_post(p_hwfn, p_ent, NULL);
737 if (rc)
738 return rc;
739
740 return qed_sp_release_queue_cid(p_hwfn, p_rx_cid);
741}
742
dacd88d6
YM		 743int qed_sp_eth_txq_start_ramrod(struct qed_hwfn *p_hwfn,
744 u16 opaque_fid,
745 u32 cid,
746 struct qed_queue_start_common_params *p_params,
747 u8 stats_id,
748 dma_addr_t pbl_addr,
749 u16 pbl_size,
750 union qed_qm_pq_params *p_pq_params)
cee4d264
MC		 751{
752 struct tx_queue_start_ramrod_data *p_ramrod = NULL;
cee4d264 753 struct qed_spq_entry *p_ent = NULL;
06f56b81 754 struct qed_sp_init_data init_data;
cee4d264
MC		 755 struct qed_hw_cid_data *p_tx_cid;
756 u8 abs_vport_id;
757 int rc = -EINVAL;
758 u16 pq_id;
759
760 /* Store information for the stop */
761 p_tx_cid = &p_hwfn->p_tx_cids[p_params->queue_id];
762 p_tx_cid->cid = cid;
763 p_tx_cid->opaque_fid = opaque_fid;
764
765 rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
766 if (rc)
767 return rc;
768
06f56b81
YM		 769 /* Get SPQ entry */
770 memset(&init_data, 0, sizeof(init_data));
771 init_data.cid = cid;
772 init_data.opaque_fid = opaque_fid;
773 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
cee4d264 774
06f56b81 775 rc = qed_sp_init_request(p_hwfn, &p_ent,
cee4d264 776 ETH_RAMROD_TX_QUEUE_START,
06f56b81 777 PROTOCOLID_ETH, &init_data);
cee4d264
MC		 778 if (rc)
779 return rc;
780
781 p_ramrod = &p_ent->ramrod.tx_queue_start;
782 p_ramrod->vport_id = abs_vport_id;
783
784 p_ramrod->sb_id = cpu_to_le16(p_params->sb);
785 p_ramrod->sb_index = p_params->sb_idx;
786 p_ramrod->stats_counter_id = stats_id;
cee4d264
MC		 787
788 p_ramrod->pbl_size = cpu_to_le16(pbl_size);
94494598 789 DMA_REGPAIR_LE(p_ramrod->pbl_base_addr, pbl_addr);
cee4d264
MC		 790
791 pq_id = qed_get_qm_pq(p_hwfn,
792 PROTOCOLID_ETH,
793 p_pq_params);
794 p_ramrod->qm_pq_id = cpu_to_le16(pq_id);
795
796 return qed_spq_post(p_hwfn, p_ent, NULL);
797}
798
799static int
800qed_sp_eth_tx_queue_start(struct qed_hwfn *p_hwfn,
801 u16 opaque_fid,
802 struct qed_queue_start_common_params *p_params,
803 dma_addr_t pbl_addr,
dacd88d6 804 u16 pbl_size, void __iomem **pp_doorbell)
cee4d264
MC		 805{
806 struct qed_hw_cid_data *p_tx_cid;
807 union qed_qm_pq_params pq_params;
808 u8 abs_stats_id = 0;
809 int rc;
810
dacd88d6
YM		 811 if (IS_VF(p_hwfn->cdev)) {
812 return qed_vf_pf_txq_start(p_hwfn,
813 p_params->queue_id,
814 p_params->sb,
815 p_params->sb_idx,
816 pbl_addr, pbl_size, pp_doorbell);
817 }
818
cee4d264
MC		 819 rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_stats_id);
820 if (rc)
821 return rc;
822
823 p_tx_cid = &p_hwfn->p_tx_cids[p_params->queue_id];
824 memset(p_tx_cid, 0, sizeof(*p_tx_cid));
825 memset(&pq_params, 0, sizeof(pq_params));
826
827 /* Allocate a CID for the queue */
828 rc = qed_cxt_acquire_cid(p_hwfn, PROTOCOLID_ETH,
829 &p_tx_cid->cid);
830 if (rc) {
831 DP_NOTICE(p_hwfn, "Failed to acquire cid\n");
832 return rc;
833 }
834 p_tx_cid->b_cid_allocated = true;
835
836 DP_VERBOSE(p_hwfn, QED_MSG_SP,
837 "opaque_fid=0x%x, cid=0x%x, tx_qid=0x%x, vport_id=0x%x, sb_id=0x%x\n",
838 opaque_fid, p_tx_cid->cid,
839 p_params->queue_id, p_params->vport_id, p_params->sb);
840
841 rc = qed_sp_eth_txq_start_ramrod(p_hwfn,
842 opaque_fid,
843 p_tx_cid->cid,
844 p_params,
845 abs_stats_id,
846 pbl_addr,
847 pbl_size,
848 &pq_params);
849
850 *pp_doorbell = (u8 __iomem *)p_hwfn->doorbells +
851 qed_db_addr(p_tx_cid->cid, DQ_DEMS_LEGACY);
852
853 if (rc)
854 qed_sp_release_queue_cid(p_hwfn, p_tx_cid);
855
856 return rc;
857}
858
dacd88d6 859int qed_sp_eth_tx_queue_stop(struct qed_hwfn *p_hwfn, u16 tx_queue_id)
cee4d264
MC		 860{
861 struct qed_hw_cid_data *p_tx_cid = &p_hwfn->p_tx_cids[tx_queue_id];
cee4d264 862 struct qed_spq_entry *p_ent = NULL;
06f56b81 863 struct qed_sp_init_data init_data;
cee4d264
MC		 864 int rc = -EINVAL;
865
dacd88d6
YM		 866 if (IS_VF(p_hwfn->cdev))
867 return qed_vf_pf_txq_stop(p_hwfn, tx_queue_id);
868
06f56b81
YM		 869 /* Get SPQ entry */
870 memset(&init_data, 0, sizeof(init_data));
871 init_data.cid = p_tx_cid->cid;
872 init_data.opaque_fid = p_tx_cid->opaque_fid;
873 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
cee4d264
MC		 874
875 rc = qed_sp_init_request(p_hwfn, &p_ent,
cee4d264 876 ETH_RAMROD_TX_QUEUE_STOP,
06f56b81 877 PROTOCOLID_ETH, &init_data);
cee4d264
MC		 878 if (rc)
879 return rc;
880
881 rc = qed_spq_post(p_hwfn, p_ent, NULL);
882 if (rc)
883 return rc;
884
885 return qed_sp_release_queue_cid(p_hwfn, p_tx_cid);
886}
887
888static enum eth_filter_action
889qed_filter_action(enum qed_filter_opcode opcode)
890{
891 enum eth_filter_action action = MAX_ETH_FILTER_ACTION;
892
893 switch (opcode) {
894 case QED_FILTER_ADD:
895 action = ETH_FILTER_ACTION_ADD;
896 break;
897 case QED_FILTER_REMOVE:
898 action = ETH_FILTER_ACTION_REMOVE;
899 break;
cee4d264 900 case QED_FILTER_FLUSH:
fc48b7a6 901 action = ETH_FILTER_ACTION_REMOVE_ALL;
cee4d264
MC		 902 break;
903 default:
904 action = MAX_ETH_FILTER_ACTION;
905 }
906
907 return action;
908}
909
910static void qed_set_fw_mac_addr(__le16 *fw_msb,
911 __le16 *fw_mid,
912 __le16 *fw_lsb,
913 u8 *mac)
914{
915 ((u8 *)fw_msb)[0] = mac[1];
916 ((u8 *)fw_msb)[1] = mac[0];
917 ((u8 *)fw_mid)[0] = mac[3];
918 ((u8 *)fw_mid)[1] = mac[2];
919 ((u8 *)fw_lsb)[0] = mac[5];
920 ((u8 *)fw_lsb)[1] = mac[4];
921}
922
923static int
924qed_filter_ucast_common(struct qed_hwfn *p_hwfn,
925 u16 opaque_fid,
926 struct qed_filter_ucast *p_filter_cmd,
927 struct vport_filter_update_ramrod_data **pp_ramrod,
928 struct qed_spq_entry **pp_ent,
929 enum spq_mode comp_mode,
930 struct qed_spq_comp_cb *p_comp_data)
931{
932 u8 vport_to_add_to = 0, vport_to_remove_from = 0;
933 struct vport_filter_update_ramrod_data *p_ramrod;
cee4d264
MC		 934 struct eth_filter_cmd *p_first_filter;
935 struct eth_filter_cmd *p_second_filter;
06f56b81 936 struct qed_sp_init_data init_data;
cee4d264
MC		 937 enum eth_filter_action action;
938 int rc;
939
940 rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from,
941 &vport_to_remove_from);
942 if (rc)
943 return rc;
944
945 rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to,
946 &vport_to_add_to);
947 if (rc)
948 return rc;
949
06f56b81
YM		 950 /* Get SPQ entry */
951 memset(&init_data, 0, sizeof(init_data));
952 init_data.cid = qed_spq_get_cid(p_hwfn);
953 init_data.opaque_fid = opaque_fid;
954 init_data.comp_mode = comp_mode;
955 init_data.p_comp_data = p_comp_data;
cee4d264
MC		 956
957 rc = qed_sp_init_request(p_hwfn, pp_ent,
cee4d264 958 ETH_RAMROD_FILTERS_UPDATE,
06f56b81 959 PROTOCOLID_ETH, &init_data);
cee4d264
MC		 960 if (rc)
961 return rc;
962
963 *pp_ramrod = &(*pp_ent)->ramrod.vport_filter_update;
964 p_ramrod = *pp_ramrod;
965 p_ramrod->filter_cmd_hdr.rx = p_filter_cmd->is_rx_filter ? 1 : 0;
966 p_ramrod->filter_cmd_hdr.tx = p_filter_cmd->is_tx_filter ? 1 : 0;
967
968 switch (p_filter_cmd->opcode) {
fc48b7a6 969 case QED_FILTER_REPLACE:
cee4d264
MC		 970 case QED_FILTER_MOVE:
971 p_ramrod->filter_cmd_hdr.cmd_cnt = 2; break;
972 default:
973 p_ramrod->filter_cmd_hdr.cmd_cnt = 1; break;
974 }
975
976 p_first_filter = &p_ramrod->filter_cmds[0];
977 p_second_filter = &p_ramrod->filter_cmds[1];
978
979 switch (p_filter_cmd->type) {
980 case QED_FILTER_MAC:
981 p_first_filter->type = ETH_FILTER_TYPE_MAC; break;
982 case QED_FILTER_VLAN:
983 p_first_filter->type = ETH_FILTER_TYPE_VLAN; break;
984 case QED_FILTER_MAC_VLAN:
985 p_first_filter->type = ETH_FILTER_TYPE_PAIR; break;
986 case QED_FILTER_INNER_MAC:
987 p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC; break;
988 case QED_FILTER_INNER_VLAN:
989 p_first_filter->type = ETH_FILTER_TYPE_INNER_VLAN; break;
990 case QED_FILTER_INNER_PAIR:
991 p_first_filter->type = ETH_FILTER_TYPE_INNER_PAIR; break;
992 case QED_FILTER_INNER_MAC_VNI_PAIR:
993 p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR;
994 break;
995 case QED_FILTER_MAC_VNI_PAIR:
996 p_first_filter->type = ETH_FILTER_TYPE_MAC_VNI_PAIR; break;
997 case QED_FILTER_VNI:
998 p_first_filter->type = ETH_FILTER_TYPE_VNI; break;
999 }
1000
1001 if ((p_first_filter->type == ETH_FILTER_TYPE_MAC) ||
1002 (p_first_filter->type == ETH_FILTER_TYPE_PAIR) ||
1003 (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC) ||
1004 (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR) ||
1005 (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) ||
1006 (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR)) {
1007 qed_set_fw_mac_addr(&p_first_filter->mac_msb,
1008 &p_first_filter->mac_mid,
1009 &p_first_filter->mac_lsb,
1010 (u8 *)p_filter_cmd->mac);
1011 }
1012
1013 if ((p_first_filter->type == ETH_FILTER_TYPE_VLAN) ||
1014 (p_first_filter->type == ETH_FILTER_TYPE_PAIR) ||
1015 (p_first_filter->type == ETH_FILTER_TYPE_INNER_VLAN) ||
1016 (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR))
1017 p_first_filter->vlan_id = cpu_to_le16(p_filter_cmd->vlan);
1018
1019 if ((p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) ||
1020 (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR) ||
1021 (p_first_filter->type == ETH_FILTER_TYPE_VNI))
1022 p_first_filter->vni = cpu_to_le32(p_filter_cmd->vni);
1023
1024 if (p_filter_cmd->opcode == QED_FILTER_MOVE) {
1025 p_second_filter->type = p_first_filter->type;
1026 p_second_filter->mac_msb = p_first_filter->mac_msb;
1027 p_second_filter->mac_mid = p_first_filter->mac_mid;
1028 p_second_filter->mac_lsb = p_first_filter->mac_lsb;
1029 p_second_filter->vlan_id = p_first_filter->vlan_id;
1030 p_second_filter->vni = p_first_filter->vni;
1031
1032 p_first_filter->action = ETH_FILTER_ACTION_REMOVE;
1033
1034 p_first_filter->vport_id = vport_to_remove_from;
1035
1036 p_second_filter->action = ETH_FILTER_ACTION_ADD;
1037 p_second_filter->vport_id = vport_to_add_to;
fc48b7a6
YM		 1038 } else if (p_filter_cmd->opcode == QED_FILTER_REPLACE) {
1039 p_first_filter->vport_id = vport_to_add_to;
1040 memcpy(p_second_filter, p_first_filter,
1041 sizeof(*p_second_filter));
1042 p_first_filter->action = ETH_FILTER_ACTION_REMOVE_ALL;
1043 p_second_filter->action = ETH_FILTER_ACTION_ADD;
cee4d264
MC		 1044 } else {
1045 action = qed_filter_action(p_filter_cmd->opcode);
1046
1047 if (action == MAX_ETH_FILTER_ACTION) {
1048 DP_NOTICE(p_hwfn,
1049 "%d is not supported yet\n",
1050 p_filter_cmd->opcode);
1051 return -EINVAL;
1052 }
1053
1054 p_first_filter->action = action;
1055 p_first_filter->vport_id = (p_filter_cmd->opcode ==
1056 QED_FILTER_REMOVE) ?
1057 vport_to_remove_from :
1058 vport_to_add_to;
1059 }
1060
1061 return 0;
1062}
1063
dacd88d6
YM		 1064int qed_sp_eth_filter_ucast(struct qed_hwfn *p_hwfn,
1065 u16 opaque_fid,
1066 struct qed_filter_ucast *p_filter_cmd,
1067 enum spq_mode comp_mode,
1068 struct qed_spq_comp_cb *p_comp_data)
cee4d264
MC		 1069{
1070 struct vport_filter_update_ramrod_data *p_ramrod = NULL;
1071 struct qed_spq_entry *p_ent = NULL;
1072 struct eth_filter_cmd_header *p_header;
1073 int rc;
1074
1075 rc = qed_filter_ucast_common(p_hwfn, opaque_fid, p_filter_cmd,
1076 &p_ramrod, &p_ent,
1077 comp_mode, p_comp_data);
1078 if (rc != 0) {
1079 DP_ERR(p_hwfn, "Uni. filter command failed %d\n", rc);
1080 return rc;
1081 }
1082 p_header = &p_ramrod->filter_cmd_hdr;
1083 p_header->assert_on_error = p_filter_cmd->assert_on_error;
1084
1085 rc = qed_spq_post(p_hwfn, p_ent, NULL);
1086 if (rc != 0) {
1087 DP_ERR(p_hwfn,
1088 "Unicast filter ADD command failed %d\n",
1089 rc);
1090 return rc;
1091 }
1092
1093 DP_VERBOSE(p_hwfn, QED_MSG_SP,
1094 "Unicast filter configured, opcode = %s, type = %s, cmd_cnt = %d, is_rx_filter = %d, is_tx_filter = %d\n",
1095 (p_filter_cmd->opcode == QED_FILTER_ADD) ? "ADD" :
1096 ((p_filter_cmd->opcode == QED_FILTER_REMOVE) ?
1097 "REMOVE" :
1098 ((p_filter_cmd->opcode == QED_FILTER_MOVE) ?
1099 "MOVE" : "REPLACE")),
1100 (p_filter_cmd->type == QED_FILTER_MAC) ? "MAC" :
1101 ((p_filter_cmd->type == QED_FILTER_VLAN) ?
1102 "VLAN" : "MAC & VLAN"),
1103 p_ramrod->filter_cmd_hdr.cmd_cnt,
1104 p_filter_cmd->is_rx_filter,
1105 p_filter_cmd->is_tx_filter);
1106 DP_VERBOSE(p_hwfn, QED_MSG_SP,
1107 "vport_to_add_to = %d, vport_to_remove_from = %d, mac = %2x:%2x:%2x:%2x:%2x:%2x, vlan = %d\n",
1108 p_filter_cmd->vport_to_add_to,
1109 p_filter_cmd->vport_to_remove_from,
1110 p_filter_cmd->mac[0],
1111 p_filter_cmd->mac[1],
1112 p_filter_cmd->mac[2],
1113 p_filter_cmd->mac[3],
1114 p_filter_cmd->mac[4],
1115 p_filter_cmd->mac[5],
1116 p_filter_cmd->vlan);
1117
1118 return 0;
1119}
1120
1121/*******************************************************************************
1122 * Description:
1123 * Calculates crc 32 on a buffer
1124 * Note: crc32_length MUST be aligned to 8
1125 * Return:
1126 ******************************************************************************/
1127static u32 qed_calc_crc32c(u8 *crc32_packet,
1128 u32 crc32_length,
1129 u32 crc32_seed,
1130 u8 complement)
1131{
1132 u32 byte = 0;
1133 u32 bit = 0;
1134 u8 msb = 0;
1135 u8 current_byte = 0;
1136 u32 crc32_result = crc32_seed;
1137
1138 if ((!crc32_packet) ||
1139 (crc32_length == 0) ||
1140 ((crc32_length % 8) != 0))
1141 return crc32_result;
1142 for (byte = 0; byte < crc32_length; byte++) {
1143 current_byte = crc32_packet[byte];
1144 for (bit = 0; bit < 8; bit++) {
1145 msb = (u8)(crc32_result >> 31);
1146 crc32_result = crc32_result << 1;
1147 if (msb != (0x1 & (current_byte >> bit))) {
1148 crc32_result = crc32_result ^ CRC32_POLY;
1149 crc32_result |= 1; /*crc32_result[0] = 1;*/
1150 }
1151 }
1152 }
1153 return crc32_result;
1154}
1155
1156static inline u32 qed_crc32c_le(u32 seed,
1157 u8 *mac,
1158 u32 len)
1159{
1160 u32 packet_buf[2] = { 0 };
1161
1162 memcpy((u8 *)(&packet_buf[0]), &mac[0], 6);
1163 return qed_calc_crc32c((u8 *)packet_buf, 8, seed, 0);
1164}
1165
dacd88d6 1166u8 qed_mcast_bin_from_mac(u8 *mac)
cee4d264
MC		 1167{
1168 u32 crc = qed_crc32c_le(ETH_MULTICAST_BIN_FROM_MAC_SEED,
1169 mac, ETH_ALEN);
1170
1171 return crc & 0xff;
1172}
1173
1174static int
1175qed_sp_eth_filter_mcast(struct qed_hwfn *p_hwfn,
1176 u16 opaque_fid,
1177 struct qed_filter_mcast *p_filter_cmd,
1178 enum spq_mode comp_mode,
1179 struct qed_spq_comp_cb *p_comp_data)
1180{
1181 unsigned long bins[ETH_MULTICAST_MAC_BINS_IN_REGS];
1182 struct vport_update_ramrod_data *p_ramrod = NULL;
cee4d264 1183 struct qed_spq_entry *p_ent = NULL;
06f56b81 1184 struct qed_sp_init_data init_data;
cee4d264
MC		 1185 u8 abs_vport_id = 0;
1186 int rc, i;
1187
1188 if (p_filter_cmd->opcode == QED_FILTER_ADD) {
1189 rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to,
1190 &abs_vport_id);
1191 if (rc)
1192 return rc;
1193 } else {
1194 rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from,
1195 &abs_vport_id);
1196 if (rc)
1197 return rc;
1198 }
1199
06f56b81
YM		 1200 /* Get SPQ entry */
1201 memset(&init_data, 0, sizeof(init_data));
1202 init_data.cid = qed_spq_get_cid(p_hwfn);
1203 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
1204 init_data.comp_mode = comp_mode;
1205 init_data.p_comp_data = p_comp_data;
cee4d264
MC		 1206
1207 rc = qed_sp_init_request(p_hwfn, &p_ent,
cee4d264 1208 ETH_RAMROD_VPORT_UPDATE,
06f56b81 1209 PROTOCOLID_ETH, &init_data);
cee4d264
MC		 1210 if (rc) {
1211 DP_ERR(p_hwfn, "Multi-cast command failed %d\n", rc);
1212 return rc;
1213 }
1214
1215 p_ramrod = &p_ent->ramrod.vport_update;
1216 p_ramrod->common.update_approx_mcast_flg = 1;
1217
1218 /* explicitly clear out the entire vector */
1219 memset(&p_ramrod->approx_mcast.bins, 0,
1220 sizeof(p_ramrod->approx_mcast.bins));
1221 memset(bins, 0, sizeof(unsigned long) *
1222 ETH_MULTICAST_MAC_BINS_IN_REGS);
1223 /* filter ADD op is explicit set op and it removes
1224 * any existing filters for the vport
1225 */
1226 if (p_filter_cmd->opcode == QED_FILTER_ADD) {
1227 for (i = 0; i < p_filter_cmd->num_mc_addrs; i++) {
1228 u32 bit;
1229
1230 bit = qed_mcast_bin_from_mac(p_filter_cmd->mac[i]);
1231 __set_bit(bit, bins);
1232 }
1233
1234 /* Convert to correct endianity */
1235 for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) {
1236 u32 *p_bins = (u32 *)bins;
1237 struct vport_update_ramrod_mcast *approx_mcast;
1238
1239 approx_mcast = &p_ramrod->approx_mcast;
1240 approx_mcast->bins[i] = cpu_to_le32(p_bins[i]);
1241 }
1242 }
1243
1244 p_ramrod->common.vport_id = abs_vport_id;
1245
1246 return qed_spq_post(p_hwfn, p_ent, NULL);
1247}
1248
dacd88d6
YM		 1249static int qed_filter_mcast_cmd(struct qed_dev *cdev,
1250 struct qed_filter_mcast *p_filter_cmd,
1251 enum spq_mode comp_mode,
1252 struct qed_spq_comp_cb *p_comp_data)
cee4d264
MC		 1253{
1254 int rc = 0;
1255 int i;
1256
1257 /* only ADD and REMOVE operations are supported for multi-cast */
1258 if ((p_filter_cmd->opcode != QED_FILTER_ADD &&
1259 (p_filter_cmd->opcode != QED_FILTER_REMOVE)) ||
1260 (p_filter_cmd->num_mc_addrs > QED_MAX_MC_ADDRS))
1261 return -EINVAL;
1262
1263 for_each_hwfn(cdev, i) {
1264 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1265
1266 u16 opaque_fid;
1267
dacd88d6
YM		 1268 if (IS_VF(cdev)) {
1269 qed_vf_pf_filter_mcast(p_hwfn, p_filter_cmd);
1270 continue;
1271 }
cee4d264
MC		 1272
1273 opaque_fid = p_hwfn->hw_info.opaque_fid;
1274
1275 rc = qed_sp_eth_filter_mcast(p_hwfn,
1276 opaque_fid,
1277 p_filter_cmd,
1278 comp_mode,
1279 p_comp_data);
1280 }
1281 return rc;
1282}
1283
1284static int qed_filter_ucast_cmd(struct qed_dev *cdev,
1285 struct qed_filter_ucast *p_filter_cmd,
1286 enum spq_mode comp_mode,
1287 struct qed_spq_comp_cb *p_comp_data)
1288{
1289 int rc = 0;
1290 int i;
1291
1292 for_each_hwfn(cdev, i) {
1293 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1294 u16 opaque_fid;
1295
dacd88d6
YM		 1296 if (IS_VF(cdev)) {
1297 rc = qed_vf_pf_filter_ucast(p_hwfn, p_filter_cmd);
1298 continue;
1299 }
cee4d264
MC		 1300
1301 opaque_fid = p_hwfn->hw_info.opaque_fid;
1302
1303 rc = qed_sp_eth_filter_ucast(p_hwfn,
1304 opaque_fid,
1305 p_filter_cmd,
1306 comp_mode,
1307 p_comp_data);
dacd88d6
YM		 1308 if (rc != 0)
1309 break;
cee4d264
MC		 1310 }
1311
1312 return rc;
1313}
1314
86622ee7
YM		 1315/* Statistics related code */
1316static void __qed_get_vport_pstats_addrlen(struct qed_hwfn *p_hwfn,
1317 u32 *p_addr,
dacd88d6 1318 u32 *p_len, u16 statistics_bin)
86622ee7 1319{
dacd88d6
YM		 1320 if (IS_PF(p_hwfn->cdev)) {
1321 *p_addr = BAR0_MAP_REG_PSDM_RAM +
1322 PSTORM_QUEUE_STAT_OFFSET(statistics_bin);
1323 *p_len = sizeof(struct eth_pstorm_per_queue_stat);
1324 } else {
1325 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
1326 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1327
1328 *p_addr = p_resp->pfdev_info.stats_info.pstats.address;
1329 *p_len = p_resp->pfdev_info.stats_info.pstats.len;
1330 }
86622ee7
YM		 1331}
1332
1333static void __qed_get_vport_pstats(struct qed_hwfn *p_hwfn,
1334 struct qed_ptt *p_ptt,
1335 struct qed_eth_stats *p_stats,
1336 u16 statistics_bin)
1337{
1338 struct eth_pstorm_per_queue_stat pstats;
1339 u32 pstats_addr = 0, pstats_len = 0;
1340
1341 __qed_get_vport_pstats_addrlen(p_hwfn, &pstats_addr, &pstats_len,
1342 statistics_bin);
1343
1344 memset(&pstats, 0, sizeof(pstats));
dacd88d6
YM		 1345 qed_memcpy_from(p_hwfn, p_ptt, &pstats, pstats_addr, pstats_len);
1346
1347 p_stats->tx_ucast_bytes += HILO_64_REGPAIR(pstats.sent_ucast_bytes);
1348 p_stats->tx_mcast_bytes += HILO_64_REGPAIR(pstats.sent_mcast_bytes);
1349 p_stats->tx_bcast_bytes += HILO_64_REGPAIR(pstats.sent_bcast_bytes);
1350 p_stats->tx_ucast_pkts += HILO_64_REGPAIR(pstats.sent_ucast_pkts);
1351 p_stats->tx_mcast_pkts += HILO_64_REGPAIR(pstats.sent_mcast_pkts);
1352 p_stats->tx_bcast_pkts += HILO_64_REGPAIR(pstats.sent_bcast_pkts);
1353 p_stats->tx_err_drop_pkts += HILO_64_REGPAIR(pstats.error_drop_pkts);
86622ee7
YM		 1354}
1355
1356static void __qed_get_vport_tstats(struct qed_hwfn *p_hwfn,
1357 struct qed_ptt *p_ptt,
1358 struct qed_eth_stats *p_stats,
1359 u16 statistics_bin)
1360{
86622ee7 1361 struct tstorm_per_port_stat tstats;
dacd88d6 1362 u32 tstats_addr, tstats_len;
86622ee7 1363
dacd88d6
YM		 1364 if (IS_PF(p_hwfn->cdev)) {
1365 tstats_addr = BAR0_MAP_REG_TSDM_RAM +
1366 TSTORM_PORT_STAT_OFFSET(MFW_PORT(p_hwfn));
1367 tstats_len = sizeof(struct tstorm_per_port_stat);
1368 } else {
1369 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
1370 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1371
1372 tstats_addr = p_resp->pfdev_info.stats_info.tstats.address;
1373 tstats_len = p_resp->pfdev_info.stats_info.tstats.len;
1374 }
86622ee7
YM		 1375
1376 memset(&tstats, 0, sizeof(tstats));
dacd88d6 1377 qed_memcpy_from(p_hwfn, p_ptt, &tstats, tstats_addr, tstats_len);
86622ee7
YM		 1378
1379 p_stats->mftag_filter_discards +=
1380 HILO_64_REGPAIR(tstats.mftag_filter_discard);
1381 p_stats->mac_filter_discards +=
1382 HILO_64_REGPAIR(tstats.eth_mac_filter_discard);
1383}
1384
1385static void __qed_get_vport_ustats_addrlen(struct qed_hwfn *p_hwfn,
1386 u32 *p_addr,
dacd88d6 1387 u32 *p_len, u16 statistics_bin)
86622ee7 1388{
dacd88d6
YM		 1389 if (IS_PF(p_hwfn->cdev)) {
1390 *p_addr = BAR0_MAP_REG_USDM_RAM +
1391 USTORM_QUEUE_STAT_OFFSET(statistics_bin);
1392 *p_len = sizeof(struct eth_ustorm_per_queue_stat);
1393 } else {
1394 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
1395 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1396
1397 *p_addr = p_resp->pfdev_info.stats_info.ustats.address;
1398 *p_len = p_resp->pfdev_info.stats_info.ustats.len;
1399 }
86622ee7
YM		 1400}
1401
1402static void __qed_get_vport_ustats(struct qed_hwfn *p_hwfn,
1403 struct qed_ptt *p_ptt,
1404 struct qed_eth_stats *p_stats,
1405 u16 statistics_bin)
1406{
1407 struct eth_ustorm_per_queue_stat ustats;
1408 u32 ustats_addr = 0, ustats_len = 0;
1409
1410 __qed_get_vport_ustats_addrlen(p_hwfn, &ustats_addr, &ustats_len,
1411 statistics_bin);
1412
1413 memset(&ustats, 0, sizeof(ustats));
dacd88d6
YM		 1414 qed_memcpy_from(p_hwfn, p_ptt, &ustats, ustats_addr, ustats_len);
1415
1416 p_stats->rx_ucast_bytes += HILO_64_REGPAIR(ustats.rcv_ucast_bytes);
1417 p_stats->rx_mcast_bytes += HILO_64_REGPAIR(ustats.rcv_mcast_bytes);
1418 p_stats->rx_bcast_bytes += HILO_64_REGPAIR(ustats.rcv_bcast_bytes);
1419 p_stats->rx_ucast_pkts += HILO_64_REGPAIR(ustats.rcv_ucast_pkts);
1420 p_stats->rx_mcast_pkts += HILO_64_REGPAIR(ustats.rcv_mcast_pkts);
1421 p_stats->rx_bcast_pkts += HILO_64_REGPAIR(ustats.rcv_bcast_pkts);
86622ee7
YM		 1422}
1423
1424static void __qed_get_vport_mstats_addrlen(struct qed_hwfn *p_hwfn,
1425 u32 *p_addr,
dacd88d6 1426 u32 *p_len, u16 statistics_bin)
86622ee7 1427{
dacd88d6
YM		 1428 if (IS_PF(p_hwfn->cdev)) {
1429 *p_addr = BAR0_MAP_REG_MSDM_RAM +
1430 MSTORM_QUEUE_STAT_OFFSET(statistics_bin);
1431 *p_len = sizeof(struct eth_mstorm_per_queue_stat);
1432 } else {
1433 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
1434 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1435
1436 *p_addr = p_resp->pfdev_info.stats_info.mstats.address;
1437 *p_len = p_resp->pfdev_info.stats_info.mstats.len;
1438 }
86622ee7
YM		 1439}
1440
1441static void __qed_get_vport_mstats(struct qed_hwfn *p_hwfn,
1442 struct qed_ptt *p_ptt,
1443 struct qed_eth_stats *p_stats,
1444 u16 statistics_bin)
1445{
1446 struct eth_mstorm_per_queue_stat mstats;
1447 u32 mstats_addr = 0, mstats_len = 0;
1448
1449 __qed_get_vport_mstats_addrlen(p_hwfn, &mstats_addr, &mstats_len,
1450 statistics_bin);
1451
1452 memset(&mstats, 0, sizeof(mstats));
dacd88d6 1453 qed_memcpy_from(p_hwfn, p_ptt, &mstats, mstats_addr, mstats_len);
86622ee7 1454
dacd88d6 1455 p_stats->no_buff_discards += HILO_64_REGPAIR(mstats.no_buff_discard);
86622ee7
YM		 1456 p_stats->packet_too_big_discard +=
1457 HILO_64_REGPAIR(mstats.packet_too_big_discard);
dacd88d6 1458 p_stats->ttl0_discard += HILO_64_REGPAIR(mstats.ttl0_discard);
86622ee7
YM		 1459 p_stats->tpa_coalesced_pkts +=
1460 HILO_64_REGPAIR(mstats.tpa_coalesced_pkts);
1461 p_stats->tpa_coalesced_events +=
1462 HILO_64_REGPAIR(mstats.tpa_coalesced_events);
dacd88d6 1463 p_stats->tpa_aborts_num += HILO_64_REGPAIR(mstats.tpa_aborts_num);
86622ee7
YM		 1464 p_stats->tpa_coalesced_bytes +=
1465 HILO_64_REGPAIR(mstats.tpa_coalesced_bytes);
1466}
1467
1468static void __qed_get_vport_port_stats(struct qed_hwfn *p_hwfn,
1469 struct qed_ptt *p_ptt,
1470 struct qed_eth_stats *p_stats)
1471{
1472 struct port_stats port_stats;
1473 int j;
1474
1475 memset(&port_stats, 0, sizeof(port_stats));
1476
1477 qed_memcpy_from(p_hwfn, p_ptt, &port_stats,
1478 p_hwfn->mcp_info->port_addr +
1479 offsetof(struct public_port, stats),
1480 sizeof(port_stats));
1481
1482 p_stats->rx_64_byte_packets += port_stats.pmm.r64;
d4967cf3
YM		 1483 p_stats->rx_65_to_127_byte_packets += port_stats.pmm.r127;
1484 p_stats->rx_128_to_255_byte_packets += port_stats.pmm.r255;
1485 p_stats->rx_256_to_511_byte_packets += port_stats.pmm.r511;
1486 p_stats->rx_512_to_1023_byte_packets += port_stats.pmm.r1023;
1487 p_stats->rx_1024_to_1518_byte_packets += port_stats.pmm.r1518;
1488 p_stats->rx_1519_to_1522_byte_packets += port_stats.pmm.r1522;
1489 p_stats->rx_1519_to_2047_byte_packets += port_stats.pmm.r2047;
1490 p_stats->rx_2048_to_4095_byte_packets += port_stats.pmm.r4095;
1491 p_stats->rx_4096_to_9216_byte_packets += port_stats.pmm.r9216;
1492 p_stats->rx_9217_to_16383_byte_packets += port_stats.pmm.r16383;
86622ee7
YM		 1493 p_stats->rx_crc_errors += port_stats.pmm.rfcs;
1494 p_stats->rx_mac_crtl_frames += port_stats.pmm.rxcf;
1495 p_stats->rx_pause_frames += port_stats.pmm.rxpf;
1496 p_stats->rx_pfc_frames += port_stats.pmm.rxpp;
1497 p_stats->rx_align_errors += port_stats.pmm.raln;
1498 p_stats->rx_carrier_errors += port_stats.pmm.rfcr;
1499 p_stats->rx_oversize_packets += port_stats.pmm.rovr;
1500 p_stats->rx_jabbers += port_stats.pmm.rjbr;
1501 p_stats->rx_undersize_packets += port_stats.pmm.rund;
1502 p_stats->rx_fragments += port_stats.pmm.rfrg;
1503 p_stats->tx_64_byte_packets += port_stats.pmm.t64;
1504 p_stats->tx_65_to_127_byte_packets += port_stats.pmm.t127;
1505 p_stats->tx_128_to_255_byte_packets += port_stats.pmm.t255;
1506 p_stats->tx_256_to_511_byte_packets += port_stats.pmm.t511;
1507 p_stats->tx_512_to_1023_byte_packets += port_stats.pmm.t1023;
1508 p_stats->tx_1024_to_1518_byte_packets += port_stats.pmm.t1518;
1509 p_stats->tx_1519_to_2047_byte_packets += port_stats.pmm.t2047;
1510 p_stats->tx_2048_to_4095_byte_packets += port_stats.pmm.t4095;
1511 p_stats->tx_4096_to_9216_byte_packets += port_stats.pmm.t9216;
1512 p_stats->tx_9217_to_16383_byte_packets += port_stats.pmm.t16383;
1513 p_stats->tx_pause_frames += port_stats.pmm.txpf;
1514 p_stats->tx_pfc_frames += port_stats.pmm.txpp;
1515 p_stats->tx_lpi_entry_count += port_stats.pmm.tlpiec;
1516 p_stats->tx_total_collisions += port_stats.pmm.tncl;
1517 p_stats->rx_mac_bytes += port_stats.pmm.rbyte;
1518 p_stats->rx_mac_uc_packets += port_stats.pmm.rxuca;
1519 p_stats->rx_mac_mc_packets += port_stats.pmm.rxmca;
1520 p_stats->rx_mac_bc_packets += port_stats.pmm.rxbca;
1521 p_stats->rx_mac_frames_ok += port_stats.pmm.rxpok;
1522 p_stats->tx_mac_bytes += port_stats.pmm.tbyte;
1523 p_stats->tx_mac_uc_packets += port_stats.pmm.txuca;
1524 p_stats->tx_mac_mc_packets += port_stats.pmm.txmca;
1525 p_stats->tx_mac_bc_packets += port_stats.pmm.txbca;
1526 p_stats->tx_mac_ctrl_frames += port_stats.pmm.txcf;
1527 for (j = 0; j < 8; j++) {
1528 p_stats->brb_truncates += port_stats.brb.brb_truncate[j];
1529 p_stats->brb_discards += port_stats.brb.brb_discard[j];
1530 }
1531}
1532
1533static void __qed_get_vport_stats(struct qed_hwfn *p_hwfn,
1534 struct qed_ptt *p_ptt,
1535 struct qed_eth_stats *stats,
dacd88d6 1536 u16 statistics_bin, bool b_get_port_stats)
86622ee7
YM		 1537{
1538 __qed_get_vport_mstats(p_hwfn, p_ptt, stats, statistics_bin);
1539 __qed_get_vport_ustats(p_hwfn, p_ptt, stats, statistics_bin);
1540 __qed_get_vport_tstats(p_hwfn, p_ptt, stats, statistics_bin);
1541 __qed_get_vport_pstats(p_hwfn, p_ptt, stats, statistics_bin);
1542
dacd88d6 1543 if (b_get_port_stats && p_hwfn->mcp_info)
86622ee7
YM		 1544 __qed_get_vport_port_stats(p_hwfn, p_ptt, stats);
1545}
1546
1547static void _qed_get_vport_stats(struct qed_dev *cdev,
1548 struct qed_eth_stats *stats)
1549{
dacd88d6
YM		 1550 u8 fw_vport = 0;
1551 int i;
86622ee7
YM		 1552
1553 memset(stats, 0, sizeof(*stats));
1554
1555 for_each_hwfn(cdev, i) {
1556 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
dacd88d6
YM		 1557 struct qed_ptt *p_ptt = IS_PF(cdev) ? qed_ptt_acquire(p_hwfn)
1558 : NULL;
1559
1560 if (IS_PF(cdev)) {
1561 /* The main vport index is relative first */
1562 if (qed_fw_vport(p_hwfn, 0, &fw_vport)) {
1563 DP_ERR(p_hwfn, "No vport available!\n");
1564 goto out;
1565 }
86622ee7
YM		 1566 }
1567
dacd88d6 1568 if (IS_PF(cdev) && !p_ptt) {
86622ee7
YM		 1569 DP_ERR(p_hwfn, "Failed to acquire ptt\n");
1570 continue;
1571 }
1572
dacd88d6
YM		 1573 __qed_get_vport_stats(p_hwfn, p_ptt, stats, fw_vport,
1574 IS_PF(cdev) ? true : false);
86622ee7 1575
dacd88d6
YM		 1576out:
1577 if (IS_PF(cdev) && p_ptt)
1578 qed_ptt_release(p_hwfn, p_ptt);
86622ee7
YM		 1579 }
1580}
1581
1582void qed_get_vport_stats(struct qed_dev *cdev,
1583 struct qed_eth_stats *stats)
1584{
1585 u32 i;
1586
1587 if (!cdev) {
1588 memset(stats, 0, sizeof(*stats));
1589 return;
1590 }
1591
1592 _qed_get_vport_stats(cdev, stats);
1593
1594 if (!cdev->reset_stats)
1595 return;
1596
1597 /* Reduce the statistics baseline */
1598 for (i = 0; i < sizeof(struct qed_eth_stats) / sizeof(u64); i++)
1599 ((u64 *)stats)[i] -= ((u64 *)cdev->reset_stats)[i];
1600}
1601
1602/* zeroes V-PORT specific portion of stats (Port stats remains untouched) */
1603void qed_reset_vport_stats(struct qed_dev *cdev)
1604{
1605 int i;
1606
1607 for_each_hwfn(cdev, i) {
1608 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1609 struct eth_mstorm_per_queue_stat mstats;
1610 struct eth_ustorm_per_queue_stat ustats;
1611 struct eth_pstorm_per_queue_stat pstats;
dacd88d6
YM		 1612 struct qed_ptt *p_ptt = IS_PF(cdev) ? qed_ptt_acquire(p_hwfn)
1613 : NULL;
86622ee7
YM		 1614 u32 addr = 0, len = 0;
1615
dacd88d6 1616 if (IS_PF(cdev) && !p_ptt) {
86622ee7
YM		 1617 DP_ERR(p_hwfn, "Failed to acquire ptt\n");
1618 continue;
1619 }
1620
1621 memset(&mstats, 0, sizeof(mstats));
1622 __qed_get_vport_mstats_addrlen(p_hwfn, &addr, &len, 0);
1623 qed_memcpy_to(p_hwfn, p_ptt, addr, &mstats, len);
1624
1625 memset(&ustats, 0, sizeof(ustats));
1626 __qed_get_vport_ustats_addrlen(p_hwfn, &addr, &len, 0);
1627 qed_memcpy_to(p_hwfn, p_ptt, addr, &ustats, len);
1628
1629 memset(&pstats, 0, sizeof(pstats));
1630 __qed_get_vport_pstats_addrlen(p_hwfn, &addr, &len, 0);
1631 qed_memcpy_to(p_hwfn, p_ptt, addr, &pstats, len);
1632
dacd88d6
YM		 1633 if (IS_PF(cdev))
1634 qed_ptt_release(p_hwfn, p_ptt);
86622ee7
YM		 1635 }
1636
1637 /* PORT statistics are not necessarily reset, so we need to
1638 * read and create a baseline for future statistics.
1639 */
1640 if (!cdev->reset_stats)
1641 DP_INFO(cdev, "Reset stats not allocated\n");
1642 else
1643 _qed_get_vport_stats(cdev, cdev->reset_stats);
1644}
1645
25c089d7
YM		 1646static int qed_fill_eth_dev_info(struct qed_dev *cdev,
1647 struct qed_dev_eth_info *info)
1648{
1649 int i;
1650
1651 memset(info, 0, sizeof(*info));
1652
1653 info->num_tc = 1;
1654
1408cc1f
YM		 1655 if (IS_PF(cdev)) {
1656 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
1657 for_each_hwfn(cdev, i)
1658 info->num_queues +=
1659 FEAT_NUM(&cdev->hwfns[i], QED_PF_L2_QUE);
1660 if (cdev->int_params.fp_msix_cnt)
1661 info->num_queues =
1662 min_t(u8, info->num_queues,
1663 cdev->int_params.fp_msix_cnt);
1664 } else {
1665 info->num_queues = cdev->num_hwfns;
1666 }
1667
1668 info->num_vlan_filters = RESC_NUM(&cdev->hwfns[0], QED_VLAN);
1669 ether_addr_copy(info->port_mac,
1670 cdev->hwfns[0].hw_info.hw_mac_addr);
25c089d7 1671 } else {
1408cc1f
YM		 1672 qed_vf_get_num_rxqs(QED_LEADING_HWFN(cdev), &info->num_queues);
1673 if (cdev->num_hwfns > 1) {
1674 u8 queues = 0;
25c089d7 1675
1408cc1f
YM		 1676 qed_vf_get_num_rxqs(&cdev->hwfns[1], &queues);
1677 info->num_queues += queues;
1678 }
1679
1680 qed_vf_get_num_vlan_filters(&cdev->hwfns[0],
1681 &info->num_vlan_filters);
1682 qed_vf_get_port_mac(&cdev->hwfns[0], info->port_mac);
1683 }
25c089d7
YM		 1684
1685 qed_fill_dev_info(cdev, &info->common);
1686
1408cc1f
YM		 1687 if (IS_VF(cdev))
1688 memset(info->common.hw_mac, 0, ETH_ALEN);
1689
25c089d7
YM		 1690 return 0;
1691}
1692
cc875c2e 1693static void qed_register_eth_ops(struct qed_dev *cdev,
1408cc1f 1694 struct qed_eth_cb_ops *ops, void *cookie)
cc875c2e 1695{
1408cc1f
YM		 1696 cdev->protocol_ops.eth = ops;
1697 cdev->ops_cookie = cookie;
1698
1699 /* For VF, we start bulletin reading */
1700 if (IS_VF(cdev))
1701 qed_vf_start_iov_wq(cdev);
cc875c2e
YM		 1702}
1703
cee4d264 1704static int qed_start_vport(struct qed_dev *cdev,
088c8618 1705 struct qed_start_vport_params *params)
cee4d264
MC		 1706{
1707 int rc, i;
1708
1709 for_each_hwfn(cdev, i) {
088c8618 1710 struct qed_sp_vport_start_params start = { 0 };
cee4d264
MC		 1711 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1712
088c8618
MC		 1713 start.tpa_mode = params->gro_enable ? QED_TPA_MODE_GRO :
1714 QED_TPA_MODE_NONE;
1715 start.remove_inner_vlan = params->remove_inner_vlan;
08feecd7 1716 start.only_untagged = true; /* untagged only */
088c8618
MC		 1717 start.drop_ttl0 = params->drop_ttl0;
1718 start.opaque_fid = p_hwfn->hw_info.opaque_fid;
1719 start.concrete_fid = p_hwfn->hw_info.concrete_fid;
1720 start.vport_id = params->vport_id;
1721 start.max_buffers_per_cqe = 16;
1722 start.mtu = params->mtu;
1723
1724 rc = qed_sp_vport_start(p_hwfn, &start);
cee4d264
MC		 1725 if (rc) {
1726 DP_ERR(cdev, "Failed to start VPORT\n");
1727 return rc;
1728 }
1729
1730 qed_hw_start_fastpath(p_hwfn);
1731
1732 DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
1733 "Started V-PORT %d with MTU %d\n",
088c8618 1734 start.vport_id, start.mtu);
cee4d264
MC		 1735 }
1736
9df2ed04
MC		 1737 qed_reset_vport_stats(cdev);
1738
cee4d264
MC		 1739 return 0;
1740}
1741
1742static int qed_stop_vport(struct qed_dev *cdev,
1743 u8 vport_id)
1744{
1745 int rc, i;
1746
1747 for_each_hwfn(cdev, i) {
1748 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1749
1750 rc = qed_sp_vport_stop(p_hwfn,
1751 p_hwfn->hw_info.opaque_fid,
1752 vport_id);
1753
1754 if (rc) {
1755 DP_ERR(cdev, "Failed to stop VPORT\n");
1756 return rc;
1757 }
1758 }
1759 return 0;
1760}
1761
1762static int qed_update_vport(struct qed_dev *cdev,
1763 struct qed_update_vport_params *params)
1764{
1765 struct qed_sp_vport_update_params sp_params;
1766 struct qed_rss_params sp_rss_params;
1767 int rc, i;
1768
1769 if (!cdev)
1770 return -ENODEV;
1771
1772 memset(&sp_params, 0, sizeof(sp_params));
1773 memset(&sp_rss_params, 0, sizeof(sp_rss_params));
1774
1775 /* Translate protocol params into sp params */
1776 sp_params.vport_id = params->vport_id;
1777 sp_params.update_vport_active_rx_flg =
1778 params->update_vport_active_flg;
1779 sp_params.update_vport_active_tx_flg =
1780 params->update_vport_active_flg;
1781 sp_params.vport_active_rx_flg = params->vport_active_flg;
1782 sp_params.vport_active_tx_flg = params->vport_active_flg;
3f9b4a69
YM		 1783 sp_params.accept_any_vlan = params->accept_any_vlan;
1784 sp_params.update_accept_any_vlan_flg =
1785 params->update_accept_any_vlan_flg;
cee4d264
MC		 1786
1787 /* RSS - is a bit tricky, since upper-layer isn't familiar with hwfns.
1788 * We need to re-fix the rss values per engine for CMT.
1789 */
1790 if (cdev->num_hwfns > 1 && params->update_rss_flg) {
1791 struct qed_update_vport_rss_params *rss =
1792 &params->rss_params;
1793 int k, max = 0;
1794
1795 /* Find largest entry, since it's possible RSS needs to
1796 * be disabled [in case only 1 queue per-hwfn]
1797 */
1798 for (k = 0; k < QED_RSS_IND_TABLE_SIZE; k++)
1799 max = (max > rss->rss_ind_table[k]) ?
1800 max : rss->rss_ind_table[k];
1801
1802 /* Either fix RSS values or disable RSS */
1803 if (cdev->num_hwfns < max + 1) {
1804 int divisor = (max + cdev->num_hwfns - 1) /
1805 cdev->num_hwfns;
1806
1807 DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
1808 "CMT - fixing RSS values (modulo %02x)\n",
1809 divisor);
1810
1811 for (k = 0; k < QED_RSS_IND_TABLE_SIZE; k++)
1812 rss->rss_ind_table[k] =
1813 rss->rss_ind_table[k] % divisor;
1814 } else {
1815 DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
1816 "CMT - 1 queue per-hwfn; Disabling RSS\n");
1817 params->update_rss_flg = 0;
1818 }
1819 }
1820
1821 /* Now, update the RSS configuration for actual configuration */
1822 if (params->update_rss_flg) {
1823 sp_rss_params.update_rss_config = 1;
1824 sp_rss_params.rss_enable = 1;
1825 sp_rss_params.update_rss_capabilities = 1;
1826 sp_rss_params.update_rss_ind_table = 1;
1827 sp_rss_params.update_rss_key = 1;
8c5ebd0c 1828 sp_rss_params.rss_caps = params->rss_params.rss_caps;
cee4d264
MC		 1829 sp_rss_params.rss_table_size_log = 7; /* 2^7 = 128 */
1830 memcpy(sp_rss_params.rss_ind_table,
1831 params->rss_params.rss_ind_table,
1832 QED_RSS_IND_TABLE_SIZE * sizeof(u16));
1833 memcpy(sp_rss_params.rss_key, params->rss_params.rss_key,
1834 QED_RSS_KEY_SIZE * sizeof(u32));
1835 }
1836 sp_params.rss_params = &sp_rss_params;
1837
1838 for_each_hwfn(cdev, i) {
1839 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1840
1841 sp_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
1842 rc = qed_sp_vport_update(p_hwfn, &sp_params,
1843 QED_SPQ_MODE_EBLOCK,
1844 NULL);
1845 if (rc) {
1846 DP_ERR(cdev, "Failed to update VPORT\n");
1847 return rc;
1848 }
1849
1850 DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
1851 "Updated V-PORT %d: active_flag %d [update %d]\n",
1852 params->vport_id, params->vport_active_flg,
1853 params->update_vport_active_flg);
1854 }
1855
1856 return 0;
1857}
1858
1859static int qed_start_rxq(struct qed_dev *cdev,
1860 struct qed_queue_start_common_params *params,
1861 u16 bd_max_bytes,
1862 dma_addr_t bd_chain_phys_addr,
1863 dma_addr_t cqe_pbl_addr,
1864 u16 cqe_pbl_size,
1865 void __iomem **pp_prod)
1866{
1867 int rc, hwfn_index;
1868 struct qed_hwfn *p_hwfn;
1869
1870 hwfn_index = params->rss_id % cdev->num_hwfns;
1871 p_hwfn = &cdev->hwfns[hwfn_index];
1872
1873 /* Fix queue ID in 100g mode */
1874 params->queue_id /= cdev->num_hwfns;
1875
1876 rc = qed_sp_eth_rx_queue_start(p_hwfn,
1877 p_hwfn->hw_info.opaque_fid,
1878 params,
1879 bd_max_bytes,
1880 bd_chain_phys_addr,
1881 cqe_pbl_addr,
1882 cqe_pbl_size,
1883 pp_prod);
1884
1885 if (rc) {
1886 DP_ERR(cdev, "Failed to start RXQ#%d\n", params->queue_id);
1887 return rc;
1888 }
1889
1890 DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
1891 "Started RX-Q %d [rss %d] on V-PORT %d and SB %d\n",
1892 params->queue_id, params->rss_id, params->vport_id,
1893 params->sb);
1894
1895 return 0;
1896}
1897
1898static int qed_stop_rxq(struct qed_dev *cdev,
1899 struct qed_stop_rxq_params *params)
1900{
1901 int rc, hwfn_index;
1902 struct qed_hwfn *p_hwfn;
1903
1904 hwfn_index = params->rss_id % cdev->num_hwfns;
1905 p_hwfn = &cdev->hwfns[hwfn_index];
1906
1907 rc = qed_sp_eth_rx_queue_stop(p_hwfn,
1908 params->rx_queue_id / cdev->num_hwfns,
1909 params->eq_completion_only,
1910 false);
1911 if (rc) {
1912 DP_ERR(cdev, "Failed to stop RXQ#%d\n", params->rx_queue_id);
1913 return rc;
1914 }
1915
1916 return 0;
1917}
1918
1919static int qed_start_txq(struct qed_dev *cdev,
1920 struct qed_queue_start_common_params *p_params,
1921 dma_addr_t pbl_addr,
1922 u16 pbl_size,
1923 void __iomem **pp_doorbell)
1924{
1925 struct qed_hwfn *p_hwfn;
1926 int rc, hwfn_index;
1927
1928 hwfn_index = p_params->rss_id % cdev->num_hwfns;
1929 p_hwfn = &cdev->hwfns[hwfn_index];
1930
1931 /* Fix queue ID in 100g mode */
1932 p_params->queue_id /= cdev->num_hwfns;
1933
1934 rc = qed_sp_eth_tx_queue_start(p_hwfn,
1935 p_hwfn->hw_info.opaque_fid,
1936 p_params,
1937 pbl_addr,
1938 pbl_size,
1939 pp_doorbell);
1940
1941 if (rc) {
1942 DP_ERR(cdev, "Failed to start TXQ#%d\n", p_params->queue_id);
1943 return rc;
1944 }
1945
1946 DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
1947 "Started TX-Q %d [rss %d] on V-PORT %d and SB %d\n",
1948 p_params->queue_id, p_params->rss_id, p_params->vport_id,
1949 p_params->sb);
1950
1951 return 0;
1952}
1953
1954#define QED_HW_STOP_RETRY_LIMIT (10)
1955static int qed_fastpath_stop(struct qed_dev *cdev)
1956{
1957 qed_hw_stop_fastpath(cdev);
1958
1959 return 0;
1960}
1961
1962static int qed_stop_txq(struct qed_dev *cdev,
1963 struct qed_stop_txq_params *params)
1964{
1965 struct qed_hwfn *p_hwfn;
1966 int rc, hwfn_index;
1967
1968 hwfn_index = params->rss_id % cdev->num_hwfns;
1969 p_hwfn = &cdev->hwfns[hwfn_index];
1970
1971 rc = qed_sp_eth_tx_queue_stop(p_hwfn,
1972 params->tx_queue_id / cdev->num_hwfns);
1973 if (rc) {
1974 DP_ERR(cdev, "Failed to stop TXQ#%d\n", params->tx_queue_id);
1975 return rc;
1976 }
1977
1978 return 0;
1979}
1980
464f6645
MC		 1981static int qed_tunn_configure(struct qed_dev *cdev,
1982 struct qed_tunn_params *tunn_params)
1983{
1984 struct qed_tunn_update_params tunn_info;
1985 int i, rc;
1986
1408cc1f
YM		 1987 if (IS_VF(cdev))
1988 return 0;
1989
464f6645
MC		 1990 memset(&tunn_info, 0, sizeof(tunn_info));
1991 if (tunn_params->update_vxlan_port == 1) {
1992 tunn_info.update_vxlan_udp_port = 1;
1993 tunn_info.vxlan_udp_port = tunn_params->vxlan_port;
1994 }
1995
1996 if (tunn_params->update_geneve_port == 1) {
1997 tunn_info.update_geneve_udp_port = 1;
1998 tunn_info.geneve_udp_port = tunn_params->geneve_port;
1999 }
2000
2001 for_each_hwfn(cdev, i) {
2002 struct qed_hwfn *hwfn = &cdev->hwfns[i];
2003
2004 rc = qed_sp_pf_update_tunn_cfg(hwfn, &tunn_info,
2005 QED_SPQ_MODE_EBLOCK, NULL);
2006
2007 if (rc)
2008 return rc;
2009 }
2010
2011 return 0;
2012}
2013
cee4d264
MC		 2014static int qed_configure_filter_rx_mode(struct qed_dev *cdev,
2015 enum qed_filter_rx_mode_type type)
2016{
2017 struct qed_filter_accept_flags accept_flags;
2018
2019 memset(&accept_flags, 0, sizeof(accept_flags));
2020
2021 accept_flags.update_rx_mode_config = 1;
2022 accept_flags.update_tx_mode_config = 1;
2023 accept_flags.rx_accept_filter = QED_ACCEPT_UCAST_MATCHED |
2024 QED_ACCEPT_MCAST_MATCHED |
2025 QED_ACCEPT_BCAST;
2026 accept_flags.tx_accept_filter = QED_ACCEPT_UCAST_MATCHED |
2027 QED_ACCEPT_MCAST_MATCHED |
2028 QED_ACCEPT_BCAST;
2029
2030 if (type == QED_FILTER_RX_MODE_TYPE_PROMISC)
2031 accept_flags.rx_accept_filter |= QED_ACCEPT_UCAST_UNMATCHED |
2032 QED_ACCEPT_MCAST_UNMATCHED;
2033 else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC)
2034 accept_flags.rx_accept_filter |= QED_ACCEPT_MCAST_UNMATCHED;
2035
3f9b4a69 2036 return qed_filter_accept_cmd(cdev, 0, accept_flags, false, false,
cee4d264
MC		 2037 QED_SPQ_MODE_CB, NULL);
2038}
2039
2040static int qed_configure_filter_ucast(struct qed_dev *cdev,
2041 struct qed_filter_ucast_params *params)
2042{
2043 struct qed_filter_ucast ucast;
2044
2045 if (!params->vlan_valid && !params->mac_valid) {
2046 DP_NOTICE(
2047 cdev,
2048 "Tried configuring a unicast filter, but both MAC and VLAN are not set\n");
2049 return -EINVAL;
2050 }
2051
2052 memset(&ucast, 0, sizeof(ucast));
2053 switch (params->type) {
2054 case QED_FILTER_XCAST_TYPE_ADD:
2055 ucast.opcode = QED_FILTER_ADD;
2056 break;
2057 case QED_FILTER_XCAST_TYPE_DEL:
2058 ucast.opcode = QED_FILTER_REMOVE;
2059 break;
2060 case QED_FILTER_XCAST_TYPE_REPLACE:
2061 ucast.opcode = QED_FILTER_REPLACE;
2062 break;
2063 default:
2064 DP_NOTICE(cdev, "Unknown unicast filter type %d\n",
2065 params->type);
2066 }
2067
2068 if (params->vlan_valid && params->mac_valid) {
2069 ucast.type = QED_FILTER_MAC_VLAN;
2070 ether_addr_copy(ucast.mac, params->mac);
2071 ucast.vlan = params->vlan;
2072 } else if (params->mac_valid) {
2073 ucast.type = QED_FILTER_MAC;
2074 ether_addr_copy(ucast.mac, params->mac);
2075 } else {
2076 ucast.type = QED_FILTER_VLAN;
2077 ucast.vlan = params->vlan;
2078 }
2079
2080 ucast.is_rx_filter = true;
2081 ucast.is_tx_filter = true;
2082
2083 return qed_filter_ucast_cmd(cdev, &ucast, QED_SPQ_MODE_CB, NULL);
2084}
2085
2086static int qed_configure_filter_mcast(struct qed_dev *cdev,
2087 struct qed_filter_mcast_params *params)
2088{
2089 struct qed_filter_mcast mcast;
2090 int i;
2091
2092 memset(&mcast, 0, sizeof(mcast));
2093 switch (params->type) {
2094 case QED_FILTER_XCAST_TYPE_ADD:
2095 mcast.opcode = QED_FILTER_ADD;
2096 break;
2097 case QED_FILTER_XCAST_TYPE_DEL:
2098 mcast.opcode = QED_FILTER_REMOVE;
2099 break;
2100 default:
2101 DP_NOTICE(cdev, "Unknown multicast filter type %d\n",
2102 params->type);
2103 }
2104
2105 mcast.num_mc_addrs = params->num;
2106 for (i = 0; i < mcast.num_mc_addrs; i++)
2107 ether_addr_copy(mcast.mac[i], params->mac[i]);
2108
2109 return qed_filter_mcast_cmd(cdev, &mcast,
2110 QED_SPQ_MODE_CB, NULL);
2111}
2112
2113static int qed_configure_filter(struct qed_dev *cdev,
2114 struct qed_filter_params *params)
2115{
2116 enum qed_filter_rx_mode_type accept_flags;
2117
2118 switch (params->type) {
2119 case QED_FILTER_TYPE_UCAST:
2120 return qed_configure_filter_ucast(cdev, &params->filter.ucast);
2121 case QED_FILTER_TYPE_MCAST:
2122 return qed_configure_filter_mcast(cdev, &params->filter.mcast);
2123 case QED_FILTER_TYPE_RX_MODE:
2124 accept_flags = params->filter.accept_flags;
2125 return qed_configure_filter_rx_mode(cdev, accept_flags);
2126 default:
2127 DP_NOTICE(cdev, "Unknown filter type %d\n",
2128 (int)params->type);
2129 return -EINVAL;
2130 }
2131}
2132
2133static int qed_fp_cqe_completion(struct qed_dev *dev,
2134 u8 rss_id,
2135 struct eth_slow_path_rx_cqe *cqe)
2136{
2137 return qed_eth_cqe_completion(&dev->hwfns[rss_id % dev->num_hwfns],
2138 cqe);
2139}
2140
0b55e27d
YM		 2141#ifdef CONFIG_QED_SRIOV
2142extern const struct qed_iov_hv_ops qed_iov_ops_pass;
2143#endif
2144
25c089d7
YM		 2145static const struct qed_eth_ops qed_eth_ops_pass = {
2146 .common = &qed_common_ops_pass,
0b55e27d
YM		 2147#ifdef CONFIG_QED_SRIOV
2148 .iov = &qed_iov_ops_pass,
2149#endif
25c089d7 2150 .fill_dev_info = &qed_fill_eth_dev_info,
cc875c2e 2151 .register_ops = &qed_register_eth_ops,
cee4d264
MC		 2152 .vport_start = &qed_start_vport,
2153 .vport_stop = &qed_stop_vport,
2154 .vport_update = &qed_update_vport,
2155 .q_rx_start = &qed_start_rxq,
2156 .q_rx_stop = &qed_stop_rxq,
2157 .q_tx_start = &qed_start_txq,
2158 .q_tx_stop = &qed_stop_txq,
2159 .filter_config = &qed_configure_filter,
2160 .fastpath_stop = &qed_fastpath_stop,
2161 .eth_cqe_completion = &qed_fp_cqe_completion,
9df2ed04 2162 .get_vport_stats = &qed_get_vport_stats,
464f6645 2163 .tunn_config = &qed_tunn_configure,
25c089d7
YM		 2164};
2165
95114344 2166const struct qed_eth_ops *qed_get_eth_ops(void)
25c089d7 2167{
25c089d7
YM		 2168 return &qed_eth_ops_pass;
2169}
2170EXPORT_SYMBOL(qed_get_eth_ops);
2171
2172void qed_put_eth_ops(void)
2173{
2174 /* TODO - reference count for module? */
2175}
2176EXPORT_SYMBOL(qed_put_eth_ops);
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