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qed: Fix bug in tx promiscuous mode settings
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / qlogic / qed / qed_l2.c
CommitLineData
25c089d7 1/* QLogic qed NIC Driver
e8f1cb50 2 * Copyright (c) 2015-2017 QLogic Corporation
25c089d7 3 *
e8f1cb50
MY		 4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
25c089d7
YM		 31 */
32
33#include <linux/types.h>
34#include <asm/byteorder.h>
35#include <asm/param.h>
36#include <linux/delay.h>
37#include <linux/dma-mapping.h>
38#include <linux/etherdevice.h>
39#include <linux/interrupt.h>
40#include <linux/kernel.h>
41#include <linux/module.h>
42#include <linux/pci.h>
43#include <linux/slab.h>
44#include <linux/stddef.h>
45#include <linux/string.h>
25c089d7
YM		 46#include <linux/workqueue.h>
47#include <linux/bitops.h>
48#include <linux/bug.h>
3da7a37a 49#include <linux/vmalloc.h>
25c089d7
YM		 50#include "qed.h"
51#include <linux/qed/qed_chain.h>
52#include "qed_cxt.h"
53#include "qed_dev_api.h"
54#include <linux/qed/qed_eth_if.h>
55#include "qed_hsi.h"
56#include "qed_hw.h"
57#include "qed_int.h"
dacd88d6 58#include "qed_l2.h"
86622ee7 59#include "qed_mcp.h"
25c089d7
YM		 60#include "qed_reg_addr.h"
61#include "qed_sp.h"
1408cc1f 62#include "qed_sriov.h"
25c089d7 63
088c8618 64
cee4d264
MC		 65#define QED_MAX_SGES_NUM 16
66#define CRC32_POLY 0x1edc6f41
67
0db711bb
MY		 68struct qed_l2_info {
69 u32 queues;
70 unsigned long **pp_qid_usage;
71
72 /* The lock is meant to synchronize access to the qid usage */
73 struct mutex lock;
74};
75
76int qed_l2_alloc(struct qed_hwfn *p_hwfn)
77{
78 struct qed_l2_info *p_l2_info;
79 unsigned long **pp_qids;
80 u32 i;
81
c851a9dc 82 if (!QED_IS_L2_PERSONALITY(p_hwfn))
0db711bb
MY		 83 return 0;
84
85 p_l2_info = kzalloc(sizeof(*p_l2_info), GFP_KERNEL);
86 if (!p_l2_info)
87 return -ENOMEM;
88 p_hwfn->p_l2_info = p_l2_info;
89
90 if (IS_PF(p_hwfn->cdev)) {
91 p_l2_info->queues = RESC_NUM(p_hwfn, QED_L2_QUEUE);
92 } else {
93 u8 rx = 0, tx = 0;
94
95 qed_vf_get_num_rxqs(p_hwfn, &rx);
96 qed_vf_get_num_txqs(p_hwfn, &tx);
97
98 p_l2_info->queues = max_t(u8, rx, tx);
99 }
100
101 pp_qids = kzalloc(sizeof(unsigned long *) * p_l2_info->queues,
102 GFP_KERNEL);
103 if (!pp_qids)
104 return -ENOMEM;
105 p_l2_info->pp_qid_usage = pp_qids;
106
107 for (i = 0; i < p_l2_info->queues; i++) {
108 pp_qids[i] = kzalloc(MAX_QUEUES_PER_QZONE / 8, GFP_KERNEL);
109 if (!pp_qids[i])
110 return -ENOMEM;
111 }
112
113 return 0;
114}
115
116void qed_l2_setup(struct qed_hwfn *p_hwfn)
117{
32c10ee8 118 if (!QED_IS_L2_PERSONALITY(p_hwfn))
0db711bb
MY		 119 return;
120
121 mutex_init(&p_hwfn->p_l2_info->lock);
122}
123
124void qed_l2_free(struct qed_hwfn *p_hwfn)
125{
126 u32 i;
127
32c10ee8 128 if (!QED_IS_L2_PERSONALITY(p_hwfn))
0db711bb
MY		 129 return;
130
131 if (!p_hwfn->p_l2_info)
132 return;
133
134 if (!p_hwfn->p_l2_info->pp_qid_usage)
135 goto out_l2_info;
136
137 /* Free until hit first uninitialized entry */
138 for (i = 0; i < p_hwfn->p_l2_info->queues; i++) {
139 if (!p_hwfn->p_l2_info->pp_qid_usage[i])
140 break;
141 kfree(p_hwfn->p_l2_info->pp_qid_usage[i]);
142 }
143
144 kfree(p_hwfn->p_l2_info->pp_qid_usage);
145
146out_l2_info:
147 kfree(p_hwfn->p_l2_info);
148 p_hwfn->p_l2_info = NULL;
149}
150
bbe3f233
MY		 151static bool qed_eth_queue_qid_usage_add(struct qed_hwfn *p_hwfn,
152 struct qed_queue_cid *p_cid)
153{
154 struct qed_l2_info *p_l2_info = p_hwfn->p_l2_info;
155 u16 queue_id = p_cid->rel.queue_id;
156 bool b_rc = true;
157 u8 first;
158
159 mutex_lock(&p_l2_info->lock);
160
0331402a 161 if (queue_id >= p_l2_info->queues) {
bbe3f233
MY		 162 DP_NOTICE(p_hwfn,
163 "Requested to increase usage for qzone %04x out of %08x\n",
164 queue_id, p_l2_info->queues);
165 b_rc = false;
166 goto out;
167 }
168
169 first = (u8)find_first_zero_bit(p_l2_info->pp_qid_usage[queue_id],
170 MAX_QUEUES_PER_QZONE);
171 if (first >= MAX_QUEUES_PER_QZONE) {
172 b_rc = false;
173 goto out;
174 }
175
176 __set_bit(first, p_l2_info->pp_qid_usage[queue_id]);
177 p_cid->qid_usage_idx = first;
178
179out:
180 mutex_unlock(&p_l2_info->lock);
181 return b_rc;
182}
183
184static void qed_eth_queue_qid_usage_del(struct qed_hwfn *p_hwfn,
185 struct qed_queue_cid *p_cid)
186{
187 mutex_lock(&p_hwfn->p_l2_info->lock);
188
189 clear_bit(p_cid->qid_usage_idx,
190 p_hwfn->p_l2_info->pp_qid_usage[p_cid->rel.queue_id]);
191
192 mutex_unlock(&p_hwfn->p_l2_info->lock);
193}
194
3da7a37a
MY		 195void qed_eth_queue_cid_release(struct qed_hwfn *p_hwfn,
196 struct qed_queue_cid *p_cid)
197{
08bc8f15
MY		 198 bool b_legacy_vf = !!(p_cid->vf_legacy & QED_QCID_LEGACY_VF_CID);
199
200 if (IS_PF(p_hwfn->cdev) && !b_legacy_vf)
201 _qed_cxt_release_cid(p_hwfn, p_cid->cid, p_cid->vfid);
bbe3f233
MY		 202
203 /* For PF's VFs we maintain the index inside queue-zone in IOV */
204 if (p_cid->vfid == QED_QUEUE_CID_SELF)
205 qed_eth_queue_qid_usage_del(p_hwfn, p_cid);
206
3da7a37a
MY		 207 vfree(p_cid);
208}
209
210/* The internal is only meant to be directly called by PFs initializeing CIDs
211 * for their VFs.
212 */
3946497a 213static struct qed_queue_cid *
3da7a37a
MY		 214_qed_eth_queue_to_cid(struct qed_hwfn *p_hwfn,
215 u16 opaque_fid,
216 u32 cid,
3946497a 217 struct qed_queue_start_common_params *p_params,
007bc371 218 bool b_is_rx,
3946497a 219 struct qed_queue_cid_vf_params *p_vf_params)
3da7a37a 220{
3da7a37a
MY		 221 struct qed_queue_cid *p_cid;
222 int rc;
223
224 p_cid = vmalloc(sizeof(*p_cid));
225 if (!p_cid)
226 return NULL;
227 memset(p_cid, 0, sizeof(*p_cid));
228
229 p_cid->opaque_fid = opaque_fid;
230 p_cid->cid = cid;
f29ffdb6 231 p_cid->p_owner = p_hwfn;
3da7a37a 232
f604b17d
MY		 233 /* Fill in parameters */
234 p_cid->rel.vport_id = p_params->vport_id;
235 p_cid->rel.queue_id = p_params->queue_id;
236 p_cid->rel.stats_id = p_params->stats_id;
237 p_cid->sb_igu_id = p_params->p_sb->igu_sb_id;
007bc371 238 p_cid->b_is_rx = b_is_rx;
f604b17d
MY		 239 p_cid->sb_idx = p_params->sb_idx;
240
3946497a
MY		 241 /* Fill-in bits related to VFs' queues if information was provided */
242 if (p_vf_params) {
243 p_cid->vfid = p_vf_params->vfid;
244 p_cid->vf_qid = p_vf_params->vf_qid;
3b19f478 245 p_cid->vf_legacy = p_vf_params->vf_legacy;
3946497a
MY		 246 } else {
247 p_cid->vfid = QED_QUEUE_CID_SELF;
248 }
249
3da7a37a
MY		 250 /* Don't try calculating the absolute indices for VFs */
251 if (IS_VF(p_hwfn->cdev)) {
252 p_cid->abs = p_cid->rel;
253 goto out;
254 }
255
256 /* Calculate the engine-absolute indices of the resources.
257 * This would guarantee they're valid later on.
258 * In some cases [SBs] we already have the right values.
259 */
260 rc = qed_fw_vport(p_hwfn, p_cid->rel.vport_id, &p_cid->abs.vport_id);
261 if (rc)
262 goto fail;
263
264 rc = qed_fw_l2_queue(p_hwfn, p_cid->rel.queue_id, &p_cid->abs.queue_id);
265 if (rc)
266 goto fail;
267
268 /* In case of a PF configuring its VF's queues, the stats-id is already
269 * absolute [since there's a single index that's suitable per-VF].
270 */
3946497a 271 if (p_cid->vfid == QED_QUEUE_CID_SELF) {
3da7a37a
MY		 272 rc = qed_fw_vport(p_hwfn, p_cid->rel.stats_id,
273 &p_cid->abs.stats_id);
274 if (rc)
275 goto fail;
276 } else {
277 p_cid->abs.stats_id = p_cid->rel.stats_id;
278 }
279
3da7a37a 280out:
bbe3f233
MY		 281 /* VF-images have provided the qid_usage_idx on their own.
282 * Otherwise, we need to allocate a unique one.
283 */
284 if (!p_vf_params) {
285 if (!qed_eth_queue_qid_usage_add(p_hwfn, p_cid))
286 goto fail;
287 } else {
288 p_cid->qid_usage_idx = p_vf_params->qid_usage_idx;
289 }
290
3da7a37a
MY		 291 DP_VERBOSE(p_hwfn,
292 QED_MSG_SP,
bbe3f233 293 "opaque_fid: %04x CID %08x vport %02x [%02x] qzone %04x.%02x [%04x] stats %02x [%02x] SB %04x PI %02x\n",
3da7a37a
MY		 294 p_cid->opaque_fid,
295 p_cid->cid,
296 p_cid->rel.vport_id,
297 p_cid->abs.vport_id,
298 p_cid->rel.queue_id,
bbe3f233 299 p_cid->qid_usage_idx,
3da7a37a
MY		 300 p_cid->abs.queue_id,
301 p_cid->rel.stats_id,
f604b17d 302 p_cid->abs.stats_id, p_cid->sb_igu_id, p_cid->sb_idx);
3da7a37a
MY		 303
304 return p_cid;
305
306fail:
307 vfree(p_cid);
308 return NULL;
309}
310
3946497a
MY		 311struct qed_queue_cid *
312qed_eth_queue_to_cid(struct qed_hwfn *p_hwfn,
313 u16 opaque_fid,
314 struct qed_queue_start_common_params *p_params,
007bc371 315 bool b_is_rx,
3946497a 316 struct qed_queue_cid_vf_params *p_vf_params)
3da7a37a
MY		 317{
318 struct qed_queue_cid *p_cid;
08bc8f15 319 u8 vfid = QED_CXT_PF_CID;
3946497a 320 bool b_legacy_vf = false;
3da7a37a
MY		 321 u32 cid = 0;
322
08bc8f15
MY		 323 /* In case of legacy VFs, The CID can be derived from the additional
324 * VF parameters - the VF assumes queue X uses CID X, so we can simply
325 * use the vf_qid for this purpose as well.
326 */
327 if (p_vf_params) {
328 vfid = p_vf_params->vfid;
329
330 if (p_vf_params->vf_legacy & QED_QCID_LEGACY_VF_CID) {
331 b_legacy_vf = true;
332 cid = p_vf_params->vf_qid;
333 }
334 }
335
3da7a37a
MY		 336 /* Get a unique firmware CID for this queue, in case it's a PF.
337 * VF's don't need a CID as the queue configuration will be done
338 * by PF.
339 */
3946497a 340 if (IS_PF(p_hwfn->cdev) && !b_legacy_vf) {
08bc8f15
MY		 341 if (_qed_cxt_acquire_cid(p_hwfn, PROTOCOLID_ETH,
342 &cid, vfid)) {
3da7a37a
MY		 343 DP_NOTICE(p_hwfn, "Failed to acquire cid\n");
344 return NULL;
345 }
346 }
347
3946497a 348 p_cid = _qed_eth_queue_to_cid(p_hwfn, opaque_fid, cid,
007bc371 349 p_params, b_is_rx, p_vf_params);
3946497a 350 if (!p_cid && IS_PF(p_hwfn->cdev) && !b_legacy_vf)
08bc8f15 351 _qed_cxt_release_cid(p_hwfn, cid, vfid);
3da7a37a
MY		 352
353 return p_cid;
354}
355
3946497a
MY		 356static struct qed_queue_cid *
357qed_eth_queue_to_cid_pf(struct qed_hwfn *p_hwfn,
358 u16 opaque_fid,
007bc371 359 bool b_is_rx,
3946497a
MY		 360 struct qed_queue_start_common_params *p_params)
361{
007bc371 362 return qed_eth_queue_to_cid(p_hwfn, opaque_fid, p_params, b_is_rx,
3946497a
MY		 363 NULL);
364}
365
dacd88d6
YM		 366int qed_sp_eth_vport_start(struct qed_hwfn *p_hwfn,
367 struct qed_sp_vport_start_params *p_params)
cee4d264 368{
cee4d264
MC		 369 struct vport_start_ramrod_data *p_ramrod = NULL;
370 struct qed_spq_entry *p_ent = NULL;
06f56b81 371 struct qed_sp_init_data init_data;
dacd88d6 372 u8 abs_vport_id = 0;
cee4d264
MC		 373 int rc = -EINVAL;
374 u16 rx_mode = 0;
cee4d264 375
088c8618 376 rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
1a635e48 377 if (rc)
cee4d264
MC		 378 return rc;
379
06f56b81
YM		 380 memset(&init_data, 0, sizeof(init_data));
381 init_data.cid = qed_spq_get_cid(p_hwfn);
088c8618 382 init_data.opaque_fid = p_params->opaque_fid;
06f56b81 383 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
cee4d264
MC		 384
385 rc = qed_sp_init_request(p_hwfn, &p_ent,
cee4d264 386 ETH_RAMROD_VPORT_START,
06f56b81 387 PROTOCOLID_ETH, &init_data);
cee4d264
MC		 388 if (rc)
389 return rc;
390
391 p_ramrod = &p_ent->ramrod.vport_start;
392 p_ramrod->vport_id = abs_vport_id;
393
088c8618 394 p_ramrod->mtu = cpu_to_le16(p_params->mtu);
c78c70fa 395 p_ramrod->handle_ptp_pkts = p_params->handle_ptp_pkts;
088c8618
MC		 396 p_ramrod->inner_vlan_removal_en = p_params->remove_inner_vlan;
397 p_ramrod->drop_ttl0_en = p_params->drop_ttl0;
e6bd8923 398 p_ramrod->untagged = p_params->only_untagged;
cee4d264
MC		 399
400 SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_UCAST_DROP_ALL, 1);
401 SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_MCAST_DROP_ALL, 1);
402
403 p_ramrod->rx_mode.state = cpu_to_le16(rx_mode);
404
405 /* TPA related fields */
1a635e48 406 memset(&p_ramrod->tpa_param, 0, sizeof(struct eth_vport_tpa_param));
cee4d264 407
088c8618
MC		 408 p_ramrod->tpa_param.max_buff_num = p_params->max_buffers_per_cqe;
409
410 switch (p_params->tpa_mode) {
411 case QED_TPA_MODE_GRO:
412 p_ramrod->tpa_param.tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
413 p_ramrod->tpa_param.tpa_max_size = (u16)-1;
414 p_ramrod->tpa_param.tpa_min_size_to_cont = p_params->mtu / 2;
415 p_ramrod->tpa_param.tpa_min_size_to_start = p_params->mtu / 2;
416 p_ramrod->tpa_param.tpa_ipv4_en_flg = 1;
417 p_ramrod->tpa_param.tpa_ipv6_en_flg = 1;
418 p_ramrod->tpa_param.tpa_pkt_split_flg = 1;
419 p_ramrod->tpa_param.tpa_gro_consistent_flg = 1;
420 break;
421 default:
422 break;
423 }
424
831bfb0e
YM		 425 p_ramrod->tx_switching_en = p_params->tx_switching;
426
11a85d75
YM		 427 p_ramrod->ctl_frame_mac_check_en = !!p_params->check_mac;
428 p_ramrod->ctl_frame_ethtype_check_en = !!p_params->check_ethtype;
429
cee4d264
MC		 430 /* Software Function ID in hwfn (PFs are 0 - 15, VFs are 16 - 135) */
431 p_ramrod->sw_fid = qed_concrete_to_sw_fid(p_hwfn->cdev,
088c8618 432 p_params->concrete_fid);
cee4d264
MC		 433
434 return qed_spq_post(p_hwfn, p_ent, NULL);
435}
436
ba56947a
BX		 437static int qed_sp_vport_start(struct qed_hwfn *p_hwfn,
438 struct qed_sp_vport_start_params *p_params)
dacd88d6
YM		 439{
440 if (IS_VF(p_hwfn->cdev)) {
441 return qed_vf_pf_vport_start(p_hwfn, p_params->vport_id,
442 p_params->mtu,
443 p_params->remove_inner_vlan,
444 p_params->tpa_mode,
08feecd7
YM		 445 p_params->max_buffers_per_cqe,
446 p_params->only_untagged);
dacd88d6
YM		 447 }
448
449 return qed_sp_eth_vport_start(p_hwfn, p_params);
450}
451
cee4d264
MC		 452static int
453qed_sp_vport_update_rss(struct qed_hwfn *p_hwfn,
454 struct vport_update_ramrod_data *p_ramrod,
f29ffdb6 455 struct qed_rss_params *p_rss)
cee4d264 456{
f29ffdb6
MY		 457 struct eth_vport_rss_config *p_config;
458 u16 capabilities = 0;
459 int i, table_size;
460 int rc = 0;
cee4d264 461
f29ffdb6 462 if (!p_rss) {
cee4d264
MC		 463 p_ramrod->common.update_rss_flg = 0;
464 return rc;
465 }
f29ffdb6 466 p_config = &p_ramrod->rss_config;
cee4d264 467
f29ffdb6 468 BUILD_BUG_ON(QED_RSS_IND_TABLE_SIZE != ETH_RSS_IND_TABLE_ENTRIES_NUM);
cee4d264 469
f29ffdb6 470 rc = qed_fw_rss_eng(p_hwfn, p_rss->rss_eng_id, &p_config->rss_id);
cee4d264
MC		 471 if (rc)
472 return rc;
473
f29ffdb6
MY		 474 p_ramrod->common.update_rss_flg = p_rss->update_rss_config;
475 p_config->update_rss_capabilities = p_rss->update_rss_capabilities;
476 p_config->update_rss_ind_table = p_rss->update_rss_ind_table;
477 p_config->update_rss_key = p_rss->update_rss_key;
cee4d264 478
f29ffdb6
MY		 479 p_config->rss_mode = p_rss->rss_enable ?
480 ETH_VPORT_RSS_MODE_REGULAR :
481 ETH_VPORT_RSS_MODE_DISABLED;
cee4d264
MC		 482
483 SET_FIELD(capabilities,
484 ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY,
f29ffdb6 485 !!(p_rss->rss_caps & QED_RSS_IPV4));
cee4d264
MC		 486 SET_FIELD(capabilities,
487 ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY,
f29ffdb6 488 !!(p_rss->rss_caps & QED_RSS_IPV6));
cee4d264
MC		 489 SET_FIELD(capabilities,
490 ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY,
f29ffdb6 491 !!(p_rss->rss_caps & QED_RSS_IPV4_TCP));
cee4d264
MC		 492 SET_FIELD(capabilities,
493 ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY,
f29ffdb6 494 !!(p_rss->rss_caps & QED_RSS_IPV6_TCP));
cee4d264
MC		 495 SET_FIELD(capabilities,
496 ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY,
f29ffdb6 497 !!(p_rss->rss_caps & QED_RSS_IPV4_UDP));
cee4d264
MC		 498 SET_FIELD(capabilities,
499 ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY,
f29ffdb6
MY		 500 !!(p_rss->rss_caps & QED_RSS_IPV6_UDP));
501 p_config->tbl_size = p_rss->rss_table_size_log;
cee4d264 502
f29ffdb6 503 p_config->capabilities = cpu_to_le16(capabilities);
cee4d264
MC		 504
505 DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP,
506 "update rss flag %d, rss_mode = %d, update_caps = %d, capabilities = %d, update_ind = %d, update_rss_key = %d\n",
507 p_ramrod->common.update_rss_flg,
f29ffdb6
MY		 508 p_config->rss_mode,
509 p_config->update_rss_capabilities,
510 p_config->capabilities,
511 p_config->update_rss_ind_table, p_config->update_rss_key);
cee4d264 512
f29ffdb6
MY		 513 table_size = min_t(int, QED_RSS_IND_TABLE_SIZE,
514 1 << p_config->tbl_size);
515 for (i = 0; i < table_size; i++) {
516 struct qed_queue_cid *p_queue = p_rss->rss_ind_table[i];
cee4d264 517
f29ffdb6
MY		 518 if (!p_queue)
519 return -EINVAL;
520
521 p_config->indirection_table[i] =
522 cpu_to_le16(p_queue->abs.queue_id);
523 }
524
525 DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP,
526 "Configured RSS indirection table [%d entries]:\n",
527 table_size);
528 for (i = 0; i < QED_RSS_IND_TABLE_SIZE; i += 0x10) {
529 DP_VERBOSE(p_hwfn,
530 NETIF_MSG_IFUP,
531 "%04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x\n",
532 le16_to_cpu(p_config->indirection_table[i]),
533 le16_to_cpu(p_config->indirection_table[i + 1]),
534 le16_to_cpu(p_config->indirection_table[i + 2]),
535 le16_to_cpu(p_config->indirection_table[i + 3]),
536 le16_to_cpu(p_config->indirection_table[i + 4]),
537 le16_to_cpu(p_config->indirection_table[i + 5]),
538 le16_to_cpu(p_config->indirection_table[i + 6]),
539 le16_to_cpu(p_config->indirection_table[i + 7]),
540 le16_to_cpu(p_config->indirection_table[i + 8]),
541 le16_to_cpu(p_config->indirection_table[i + 9]),
542 le16_to_cpu(p_config->indirection_table[i + 10]),
543 le16_to_cpu(p_config->indirection_table[i + 11]),
544 le16_to_cpu(p_config->indirection_table[i + 12]),
545 le16_to_cpu(p_config->indirection_table[i + 13]),
546 le16_to_cpu(p_config->indirection_table[i + 14]),
547 le16_to_cpu(p_config->indirection_table[i + 15]));
cee4d264
MC		 548 }
549
550 for (i = 0; i < 10; i++)
f29ffdb6 551 p_config->rss_key[i] = cpu_to_le32(p_rss->rss_key[i]);
cee4d264
MC		 552
553 return rc;
554}
555
556static void
557qed_sp_update_accept_mode(struct qed_hwfn *p_hwfn,
558 struct vport_update_ramrod_data *p_ramrod,
559 struct qed_filter_accept_flags accept_flags)
560{
561 p_ramrod->common.update_rx_mode_flg =
562 accept_flags.update_rx_mode_config;
563
564 p_ramrod->common.update_tx_mode_flg =
565 accept_flags.update_tx_mode_config;
566
567 /* Set Rx mode accept flags */
568 if (p_ramrod->common.update_rx_mode_flg) {
569 u8 accept_filter = accept_flags.rx_accept_filter;
570 u16 state = 0;
571
572 SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_DROP_ALL,
573 !(!!(accept_filter & QED_ACCEPT_UCAST_MATCHED) ||
574 !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED)));
575
576 SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED,
577 !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED));
578
579 SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_DROP_ALL,
580 !(!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) ||
581 !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED)));
582
583 SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL,
584 (!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) &&
585 !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED)));
586
587 SET_FIELD(state, ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL,
588 !!(accept_filter & QED_ACCEPT_BCAST));
589
590 p_ramrod->rx_mode.state = cpu_to_le16(state);
591 DP_VERBOSE(p_hwfn, QED_MSG_SP,
592 "p_ramrod->rx_mode.state = 0x%x\n", state);
593 }
594
595 /* Set Tx mode accept flags */
596 if (p_ramrod->common.update_tx_mode_flg) {
597 u8 accept_filter = accept_flags.tx_accept_filter;
598 u16 state = 0;
599
600 SET_FIELD(state, ETH_VPORT_TX_MODE_UCAST_DROP_ALL,
601 !!(accept_filter & QED_ACCEPT_NONE));
602
cee4d264
MC		 603 SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_DROP_ALL,
604 !!(accept_filter & QED_ACCEPT_NONE));
605
606 SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL,
607 (!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) &&
608 !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED)));
609
1c4f6fa2
MC		 610 SET_FIELD(state, ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL,
611 (!!(accept_filter & QED_ACCEPT_UCAST_MATCHED) &&
612 !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED)));
613
cee4d264
MC		 614 SET_FIELD(state, ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL,
615 !!(accept_filter & QED_ACCEPT_BCAST));
616
617 p_ramrod->tx_mode.state = cpu_to_le16(state);
618 DP_VERBOSE(p_hwfn, QED_MSG_SP,
619 "p_ramrod->tx_mode.state = 0x%x\n", state);
620 }
621}
622
17b235c1
YM		 623static void
624qed_sp_vport_update_sge_tpa(struct qed_hwfn *p_hwfn,
625 struct vport_update_ramrod_data *p_ramrod,
626 struct qed_sge_tpa_params *p_params)
627{
628 struct eth_vport_tpa_param *p_tpa;
629
630 if (!p_params) {
631 p_ramrod->common.update_tpa_param_flg = 0;
632 p_ramrod->common.update_tpa_en_flg = 0;
633 p_ramrod->common.update_tpa_param_flg = 0;
634 return;
635 }
636
637 p_ramrod->common.update_tpa_en_flg = p_params->update_tpa_en_flg;
638 p_tpa = &p_ramrod->tpa_param;
639 p_tpa->tpa_ipv4_en_flg = p_params->tpa_ipv4_en_flg;
640 p_tpa->tpa_ipv6_en_flg = p_params->tpa_ipv6_en_flg;
641 p_tpa->tpa_ipv4_tunn_en_flg = p_params->tpa_ipv4_tunn_en_flg;
642 p_tpa->tpa_ipv6_tunn_en_flg = p_params->tpa_ipv6_tunn_en_flg;
643
644 p_ramrod->common.update_tpa_param_flg = p_params->update_tpa_param_flg;
645 p_tpa->max_buff_num = p_params->max_buffers_per_cqe;
646 p_tpa->tpa_pkt_split_flg = p_params->tpa_pkt_split_flg;
647 p_tpa->tpa_hdr_data_split_flg = p_params->tpa_hdr_data_split_flg;
648 p_tpa->tpa_gro_consistent_flg = p_params->tpa_gro_consistent_flg;
649 p_tpa->tpa_max_aggs_num = p_params->tpa_max_aggs_num;
650 p_tpa->tpa_max_size = p_params->tpa_max_size;
651 p_tpa->tpa_min_size_to_start = p_params->tpa_min_size_to_start;
652 p_tpa->tpa_min_size_to_cont = p_params->tpa_min_size_to_cont;
653}
654
cee4d264
MC		 655static void
656qed_sp_update_mcast_bin(struct qed_hwfn *p_hwfn,
657 struct vport_update_ramrod_data *p_ramrod,
658 struct qed_sp_vport_update_params *p_params)
659{
660 int i;
661
662 memset(&p_ramrod->approx_mcast.bins, 0,
663 sizeof(p_ramrod->approx_mcast.bins));
664
83aeb933
YM		 665 if (!p_params->update_approx_mcast_flg)
666 return;
cee4d264 667
83aeb933
YM		 668 p_ramrod->common.update_approx_mcast_flg = 1;
669 for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) {
b2aa32e7 670 u32 *p_bins = p_params->bins;
83aeb933
YM		 671
672 p_ramrod->approx_mcast.bins[i] = cpu_to_le32(p_bins[i]);
cee4d264
MC		 673 }
674}
675
dacd88d6
YM		 676int qed_sp_vport_update(struct qed_hwfn *p_hwfn,
677 struct qed_sp_vport_update_params *p_params,
678 enum spq_mode comp_mode,
679 struct qed_spq_comp_cb *p_comp_data)
cee4d264
MC		 680{
681 struct qed_rss_params *p_rss_params = p_params->rss_params;
682 struct vport_update_ramrod_data_cmn *p_cmn;
06f56b81 683 struct qed_sp_init_data init_data;
cee4d264
MC		 684 struct vport_update_ramrod_data *p_ramrod = NULL;
685 struct qed_spq_entry *p_ent = NULL;
17b235c1 686 u8 abs_vport_id = 0, val;
cee4d264
MC		 687 int rc = -EINVAL;
688
dacd88d6
YM		 689 if (IS_VF(p_hwfn->cdev)) {
690 rc = qed_vf_pf_vport_update(p_hwfn, p_params);
691 return rc;
692 }
693
cee4d264 694 rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
1a635e48 695 if (rc)
cee4d264
MC		 696 return rc;
697
06f56b81
YM		 698 memset(&init_data, 0, sizeof(init_data));
699 init_data.cid = qed_spq_get_cid(p_hwfn);
700 init_data.opaque_fid = p_params->opaque_fid;
701 init_data.comp_mode = comp_mode;
702 init_data.p_comp_data = p_comp_data;
cee4d264
MC		 703
704 rc = qed_sp_init_request(p_hwfn, &p_ent,
cee4d264 705 ETH_RAMROD_VPORT_UPDATE,
06f56b81 706 PROTOCOLID_ETH, &init_data);
cee4d264
MC		 707 if (rc)
708 return rc;
709
710 /* Copy input params to ramrod according to FW struct */
711 p_ramrod = &p_ent->ramrod.vport_update;
712 p_cmn = &p_ramrod->common;
713
714 p_cmn->vport_id = abs_vport_id;
715 p_cmn->rx_active_flg = p_params->vport_active_rx_flg;
716 p_cmn->update_rx_active_flg = p_params->update_vport_active_rx_flg;
717 p_cmn->tx_active_flg = p_params->vport_active_tx_flg;
718 p_cmn->update_tx_active_flg = p_params->update_vport_active_tx_flg;
3f9b4a69 719 p_cmn->accept_any_vlan = p_params->accept_any_vlan;
83aeb933
YM		 720 val = p_params->update_accept_any_vlan_flg;
721 p_cmn->update_accept_any_vlan_flg = val;
17b235c1
YM		 722
723 p_cmn->inner_vlan_removal_en = p_params->inner_vlan_removal_flg;
724 val = p_params->update_inner_vlan_removal_flg;
725 p_cmn->update_inner_vlan_removal_en_flg = val;
08feecd7
YM		 726
727 p_cmn->default_vlan_en = p_params->default_vlan_enable_flg;
728 val = p_params->update_default_vlan_enable_flg;
729 p_cmn->update_default_vlan_en_flg = val;
730
731 p_cmn->default_vlan = cpu_to_le16(p_params->default_vlan);
732 p_cmn->update_default_vlan_flg = p_params->update_default_vlan_flg;
733
734 p_cmn->silent_vlan_removal_en = p_params->silent_vlan_removal_flg;
735
17b235c1
YM		 736 p_ramrod->common.tx_switching_en = p_params->tx_switching_flg;
737 p_cmn->update_tx_switching_en_flg = p_params->update_tx_switching_flg;
738
6ddc7608
YM		 739 p_cmn->anti_spoofing_en = p_params->anti_spoofing_en;
740 val = p_params->update_anti_spoofing_en_flg;
741 p_ramrod->common.update_anti_spoofing_en_flg = val;
742
cee4d264
MC		 743 rc = qed_sp_vport_update_rss(p_hwfn, p_ramrod, p_rss_params);
744 if (rc) {
745 /* Return spq entry which is taken in qed_sp_init_request()*/
746 qed_spq_return_entry(p_hwfn, p_ent);
747 return rc;
748 }
749
750 /* Update mcast bins for VFs, PF doesn't use this functionality */
751 qed_sp_update_mcast_bin(p_hwfn, p_ramrod, p_params);
752
753 qed_sp_update_accept_mode(p_hwfn, p_ramrod, p_params->accept_flags);
17b235c1 754 qed_sp_vport_update_sge_tpa(p_hwfn, p_ramrod, p_params->sge_tpa_params);
cee4d264
MC		 755 return qed_spq_post(p_hwfn, p_ent, NULL);
756}
757
dacd88d6 758int qed_sp_vport_stop(struct qed_hwfn *p_hwfn, u16 opaque_fid, u8 vport_id)
cee4d264 759{
cee4d264 760 struct vport_stop_ramrod_data *p_ramrod;
06f56b81 761 struct qed_sp_init_data init_data;
cee4d264
MC		 762 struct qed_spq_entry *p_ent;
763 u8 abs_vport_id = 0;
764 int rc;
765
dacd88d6
YM		 766 if (IS_VF(p_hwfn->cdev))
767 return qed_vf_pf_vport_stop(p_hwfn);
768
cee4d264 769 rc = qed_fw_vport(p_hwfn, vport_id, &abs_vport_id);
1a635e48 770 if (rc)
cee4d264
MC		 771 return rc;
772
06f56b81
YM		 773 memset(&init_data, 0, sizeof(init_data));
774 init_data.cid = qed_spq_get_cid(p_hwfn);
775 init_data.opaque_fid = opaque_fid;
776 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
cee4d264
MC		 777
778 rc = qed_sp_init_request(p_hwfn, &p_ent,
cee4d264 779 ETH_RAMROD_VPORT_STOP,
06f56b81 780 PROTOCOLID_ETH, &init_data);
cee4d264
MC		 781 if (rc)
782 return rc;
783
784 p_ramrod = &p_ent->ramrod.vport_stop;
785 p_ramrod->vport_id = abs_vport_id;
786
787 return qed_spq_post(p_hwfn, p_ent, NULL);
788}
789
dacd88d6
YM		 790static int
791qed_vf_pf_accept_flags(struct qed_hwfn *p_hwfn,
792 struct qed_filter_accept_flags *p_accept_flags)
793{
794 struct qed_sp_vport_update_params s_params;
795
796 memset(&s_params, 0, sizeof(s_params));
797 memcpy(&s_params.accept_flags, p_accept_flags,
798 sizeof(struct qed_filter_accept_flags));
799
800 return qed_vf_pf_vport_update(p_hwfn, &s_params);
801}
802
cee4d264
MC		 803static int qed_filter_accept_cmd(struct qed_dev *cdev,
804 u8 vport,
805 struct qed_filter_accept_flags accept_flags,
3f9b4a69
YM		 806 u8 update_accept_any_vlan,
807 u8 accept_any_vlan,
dacd88d6
YM		 808 enum spq_mode comp_mode,
809 struct qed_spq_comp_cb *p_comp_data)
cee4d264
MC		 810{
811 struct qed_sp_vport_update_params vport_update_params;
812 int i, rc;
813
814 /* Prepare and send the vport rx_mode change */
815 memset(&vport_update_params, 0, sizeof(vport_update_params));
816 vport_update_params.vport_id = vport;
817 vport_update_params.accept_flags = accept_flags;
3f9b4a69
YM		 818 vport_update_params.update_accept_any_vlan_flg = update_accept_any_vlan;
819 vport_update_params.accept_any_vlan = accept_any_vlan;
cee4d264
MC		 820
821 for_each_hwfn(cdev, i) {
822 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
823
824 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
825
dacd88d6
YM		 826 if (IS_VF(cdev)) {
827 rc = qed_vf_pf_accept_flags(p_hwfn, &accept_flags);
828 if (rc)
829 return rc;
830 continue;
831 }
832
cee4d264
MC		 833 rc = qed_sp_vport_update(p_hwfn, &vport_update_params,
834 comp_mode, p_comp_data);
1a635e48 835 if (rc) {
cee4d264
MC		 836 DP_ERR(cdev, "Update rx_mode failed %d\n", rc);
837 return rc;
838 }
839
840 DP_VERBOSE(p_hwfn, QED_MSG_SP,
841 "Accept filter configured, flags = [Rx]%x [Tx]%x\n",
842 accept_flags.rx_accept_filter,
843 accept_flags.tx_accept_filter);
3f9b4a69
YM		 844 if (update_accept_any_vlan)
845 DP_VERBOSE(p_hwfn, QED_MSG_SP,
846 "accept_any_vlan=%d configured\n",
847 accept_any_vlan);
cee4d264
MC		 848 }
849
850 return 0;
851}
852
3da7a37a
MY		 853int qed_eth_rxq_start_ramrod(struct qed_hwfn *p_hwfn,
854 struct qed_queue_cid *p_cid,
855 u16 bd_max_bytes,
856 dma_addr_t bd_chain_phys_addr,
857 dma_addr_t cqe_pbl_addr, u16 cqe_pbl_size)
cee4d264
MC		 858{
859 struct rx_queue_start_ramrod_data *p_ramrod = NULL;
cee4d264 860 struct qed_spq_entry *p_ent = NULL;
06f56b81 861 struct qed_sp_init_data init_data;
cee4d264
MC		 862 int rc = -EINVAL;
863
cee4d264 864 DP_VERBOSE(p_hwfn, QED_MSG_SP,
3da7a37a
MY		 865 "opaque_fid=0x%x, cid=0x%x, rx_qzone=0x%x, vport_id=0x%x, sb_id=0x%x\n",
866 p_cid->opaque_fid, p_cid->cid,
f604b17d 867 p_cid->abs.queue_id, p_cid->abs.vport_id, p_cid->sb_igu_id);
cee4d264 868
06f56b81
YM		 869 /* Get SPQ entry */
870 memset(&init_data, 0, sizeof(init_data));
3da7a37a
MY		 871 init_data.cid = p_cid->cid;
872 init_data.opaque_fid = p_cid->opaque_fid;
06f56b81 873 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
cee4d264
MC		 874
875 rc = qed_sp_init_request(p_hwfn, &p_ent,
cee4d264 876 ETH_RAMROD_RX_QUEUE_START,
06f56b81 877 PROTOCOLID_ETH, &init_data);
cee4d264
MC		 878 if (rc)
879 return rc;
880
881 p_ramrod = &p_ent->ramrod.rx_queue_start;
882
f604b17d
MY		 883 p_ramrod->sb_id = cpu_to_le16(p_cid->sb_igu_id);
884 p_ramrod->sb_index = p_cid->sb_idx;
3da7a37a
MY		 885 p_ramrod->vport_id = p_cid->abs.vport_id;
886 p_ramrod->stats_counter_id = p_cid->abs.stats_id;
887 p_ramrod->rx_queue_id = cpu_to_le16(p_cid->abs.queue_id);
1a635e48
YM		 888 p_ramrod->complete_cqe_flg = 0;
889 p_ramrod->complete_event_flg = 1;
cee4d264 890
1a635e48 891 p_ramrod->bd_max_bytes = cpu_to_le16(bd_max_bytes);
94494598 892 DMA_REGPAIR_LE(p_ramrod->bd_base, bd_chain_phys_addr);
cee4d264 893
1a635e48 894 p_ramrod->num_of_pbl_pages = cpu_to_le16(cqe_pbl_size);
94494598 895 DMA_REGPAIR_LE(p_ramrod->cqe_pbl_addr, cqe_pbl_addr);
cee4d264 896
3946497a 897 if (p_cid->vfid != QED_QUEUE_CID_SELF) {
3b19f478
MY		 898 bool b_legacy_vf = !!(p_cid->vf_legacy &
899 QED_QCID_LEGACY_VF_RX_PROD);
900
3da7a37a 901 p_ramrod->vf_rx_prod_index = p_cid->vf_qid;
351a4ded 902 DP_VERBOSE(p_hwfn, QED_MSG_SP,
a044df83 903 "Queue%s is meant for VF rxq[%02x]\n",
3b19f478
MY		 904 b_legacy_vf ? " [legacy]" : "", p_cid->vf_qid);
905 p_ramrod->vf_rx_prod_use_zone_a = b_legacy_vf;
a044df83 906 }
cee4d264 907
351a4ded 908 return qed_spq_post(p_hwfn, p_ent, NULL);
cee4d264
MC		 909}
910
911static int
3da7a37a
MY		 912qed_eth_pf_rx_queue_start(struct qed_hwfn *p_hwfn,
913 struct qed_queue_cid *p_cid,
cee4d264
MC		 914 u16 bd_max_bytes,
915 dma_addr_t bd_chain_phys_addr,
916 dma_addr_t cqe_pbl_addr,
dacd88d6 917 u16 cqe_pbl_size, void __iomem **pp_prod)
cee4d264 918{
b21290b7 919 u32 init_prod_val = 0;
cee4d264 920
3da7a37a
MY		 921 *pp_prod = p_hwfn->regview +
922 GTT_BAR0_MAP_REG_MSDM_RAM +
923 MSTORM_ETH_PF_PRODS_OFFSET(p_cid->abs.queue_id);
cee4d264
MC		 924
925 /* Init the rcq, rx bd and rx sge (if valid) producers to 0 */
b21290b7 926 __internal_ram_wr(p_hwfn, *pp_prod, sizeof(u32),
cee4d264
MC		 927 (u32 *)(&init_prod_val));
928
3da7a37a
MY		 929 return qed_eth_rxq_start_ramrod(p_hwfn, p_cid,
930 bd_max_bytes,
931 bd_chain_phys_addr,
932 cqe_pbl_addr, cqe_pbl_size);
933}
934
935static int
936qed_eth_rx_queue_start(struct qed_hwfn *p_hwfn,
937 u16 opaque_fid,
938 struct qed_queue_start_common_params *p_params,
939 u16 bd_max_bytes,
940 dma_addr_t bd_chain_phys_addr,
941 dma_addr_t cqe_pbl_addr,
942 u16 cqe_pbl_size,
943 struct qed_rxq_start_ret_params *p_ret_params)
944{
945 struct qed_queue_cid *p_cid;
946 int rc;
947
cee4d264 948 /* Allocate a CID for the queue */
007bc371 949 p_cid = qed_eth_queue_to_cid_pf(p_hwfn, opaque_fid, true, p_params);
3da7a37a
MY		 950 if (!p_cid)
951 return -ENOMEM;
cee4d264 952
3da7a37a
MY		 953 if (IS_PF(p_hwfn->cdev)) {
954 rc = qed_eth_pf_rx_queue_start(p_hwfn, p_cid,
955 bd_max_bytes,
956 bd_chain_phys_addr,
957 cqe_pbl_addr, cqe_pbl_size,
958 &p_ret_params->p_prod);
959 } else {
960 rc = qed_vf_pf_rxq_start(p_hwfn, p_cid,
cee4d264
MC		 961 bd_max_bytes,
962 bd_chain_phys_addr,
3da7a37a
MY		 963 cqe_pbl_addr,
964 cqe_pbl_size, &p_ret_params->p_prod);
965 }
cee4d264 966
3da7a37a 967 /* Provide the caller with a reference to as handler */
1a635e48 968 if (rc)
3da7a37a
MY		 969 qed_eth_queue_cid_release(p_hwfn, p_cid);
970 else
971 p_ret_params->p_handle = (void *)p_cid;
cee4d264
MC		 972
973 return rc;
974}
975
17b235c1 976int qed_sp_eth_rx_queues_update(struct qed_hwfn *p_hwfn,
3da7a37a 977 void **pp_rxq_handles,
17b235c1
YM		 978 u8 num_rxqs,
979 u8 complete_cqe_flg,
980 u8 complete_event_flg,
981 enum spq_mode comp_mode,
982 struct qed_spq_comp_cb *p_comp_data)
983{
984 struct rx_queue_update_ramrod_data *p_ramrod = NULL;
985 struct qed_spq_entry *p_ent = NULL;
986 struct qed_sp_init_data init_data;
3da7a37a 987 struct qed_queue_cid *p_cid;
17b235c1
YM		 988 int rc = -EINVAL;
989 u8 i;
990
991 memset(&init_data, 0, sizeof(init_data));
992 init_data.comp_mode = comp_mode;
993 init_data.p_comp_data = p_comp_data;
994
995 for (i = 0; i < num_rxqs; i++) {
3da7a37a 996 p_cid = ((struct qed_queue_cid **)pp_rxq_handles)[i];
17b235c1
YM		 997
998 /* Get SPQ entry */
3da7a37a
MY		 999 init_data.cid = p_cid->cid;
1000 init_data.opaque_fid = p_cid->opaque_fid;
17b235c1
YM		 1001
1002 rc = qed_sp_init_request(p_hwfn, &p_ent,
1003 ETH_RAMROD_RX_QUEUE_UPDATE,
1004 PROTOCOLID_ETH, &init_data);
1005 if (rc)
1006 return rc;
1007
1008 p_ramrod = &p_ent->ramrod.rx_queue_update;
3da7a37a 1009 p_ramrod->vport_id = p_cid->abs.vport_id;
17b235c1 1010
3da7a37a 1011 p_ramrod->rx_queue_id = cpu_to_le16(p_cid->abs.queue_id);
17b235c1
YM		 1012 p_ramrod->complete_cqe_flg = complete_cqe_flg;
1013 p_ramrod->complete_event_flg = complete_event_flg;
1014
1015 rc = qed_spq_post(p_hwfn, p_ent, NULL);
1016 if (rc)
1017 return rc;
1018 }
1019
1020 return rc;
1021}
1022
3da7a37a
MY		 1023static int
1024qed_eth_pf_rx_queue_stop(struct qed_hwfn *p_hwfn,
1025 struct qed_queue_cid *p_cid,
1026 bool b_eq_completion_only, bool b_cqe_completion)
cee4d264 1027{
cee4d264 1028 struct rx_queue_stop_ramrod_data *p_ramrod = NULL;
cee4d264 1029 struct qed_spq_entry *p_ent = NULL;
06f56b81 1030 struct qed_sp_init_data init_data;
3da7a37a 1031 int rc;
dacd88d6 1032
06f56b81 1033 memset(&init_data, 0, sizeof(init_data));
3da7a37a
MY		 1034 init_data.cid = p_cid->cid;
1035 init_data.opaque_fid = p_cid->opaque_fid;
06f56b81 1036 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
cee4d264
MC		 1037
1038 rc = qed_sp_init_request(p_hwfn, &p_ent,
cee4d264 1039 ETH_RAMROD_RX_QUEUE_STOP,
06f56b81 1040 PROTOCOLID_ETH, &init_data);
cee4d264
MC		 1041 if (rc)
1042 return rc;
1043
1044 p_ramrod = &p_ent->ramrod.rx_queue_stop;
3da7a37a
MY		 1045 p_ramrod->vport_id = p_cid->abs.vport_id;
1046 p_ramrod->rx_queue_id = cpu_to_le16(p_cid->abs.queue_id);
cee4d264
MC		 1047
1048 /* Cleaning the queue requires the completion to arrive there.
1049 * In addition, VFs require the answer to come as eqe to PF.
1050 */
3946497a 1051 p_ramrod->complete_cqe_flg = ((p_cid->vfid == QED_QUEUE_CID_SELF) &&
3da7a37a
MY		 1052 !b_eq_completion_only) ||
1053 b_cqe_completion;
3946497a
MY		 1054 p_ramrod->complete_event_flg = (p_cid->vfid != QED_QUEUE_CID_SELF) ||
1055 b_eq_completion_only;
cee4d264 1056
3da7a37a
MY		 1057 return qed_spq_post(p_hwfn, p_ent, NULL);
1058}
1059
1060int qed_eth_rx_queue_stop(struct qed_hwfn *p_hwfn,
1061 void *p_rxq,
1062 bool eq_completion_only, bool cqe_completion)
1063{
1064 struct qed_queue_cid *p_cid = (struct qed_queue_cid *)p_rxq;
1065 int rc = -EINVAL;
cee4d264 1066
3da7a37a
MY		 1067 if (IS_PF(p_hwfn->cdev))
1068 rc = qed_eth_pf_rx_queue_stop(p_hwfn, p_cid,
1069 eq_completion_only,
1070 cqe_completion);
1071 else
1072 rc = qed_vf_pf_rxq_stop(p_hwfn, p_cid, cqe_completion);
1073
1074 if (!rc)
1075 qed_eth_queue_cid_release(p_hwfn, p_cid);
1076 return rc;
cee4d264
MC		 1077}
1078
3da7a37a
MY		 1079int
1080qed_eth_txq_start_ramrod(struct qed_hwfn *p_hwfn,
1081 struct qed_queue_cid *p_cid,
1082 dma_addr_t pbl_addr, u16 pbl_size, u16 pq_id)
cee4d264
MC		 1083{
1084 struct tx_queue_start_ramrod_data *p_ramrod = NULL;
cee4d264 1085 struct qed_spq_entry *p_ent = NULL;
06f56b81 1086 struct qed_sp_init_data init_data;
cee4d264 1087 int rc = -EINVAL;
351a4ded 1088
06f56b81
YM		 1089 /* Get SPQ entry */
1090 memset(&init_data, 0, sizeof(init_data));
3da7a37a
MY		 1091 init_data.cid = p_cid->cid;
1092 init_data.opaque_fid = p_cid->opaque_fid;
06f56b81 1093 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
cee4d264 1094
06f56b81 1095 rc = qed_sp_init_request(p_hwfn, &p_ent,
cee4d264 1096 ETH_RAMROD_TX_QUEUE_START,
06f56b81 1097 PROTOCOLID_ETH, &init_data);
cee4d264
MC		 1098 if (rc)
1099 return rc;
1100
1a635e48 1101 p_ramrod = &p_ent->ramrod.tx_queue_start;
3da7a37a 1102 p_ramrod->vport_id = p_cid->abs.vport_id;
1a635e48 1103
f604b17d
MY		 1104 p_ramrod->sb_id = cpu_to_le16(p_cid->sb_igu_id);
1105 p_ramrod->sb_index = p_cid->sb_idx;
3da7a37a 1106 p_ramrod->stats_counter_id = p_cid->abs.stats_id;
cee4d264 1107
3da7a37a
MY		 1108 p_ramrod->queue_zone_id = cpu_to_le16(p_cid->abs.queue_id);
1109 p_ramrod->same_as_last_id = cpu_to_le16(p_cid->abs.queue_id);
cee4d264 1110
1a635e48 1111 p_ramrod->pbl_size = cpu_to_le16(pbl_size);
94494598 1112 DMA_REGPAIR_LE(p_ramrod->pbl_base_addr, pbl_addr);
cee4d264 1113
1a635e48 1114 p_ramrod->qm_pq_id = cpu_to_le16(pq_id);
cee4d264
MC		 1115
1116 return qed_spq_post(p_hwfn, p_ent, NULL);
1117}
1118
1119static int
3da7a37a
MY		 1120qed_eth_pf_tx_queue_start(struct qed_hwfn *p_hwfn,
1121 struct qed_queue_cid *p_cid,
1122 u8 tc,
cee4d264 1123 dma_addr_t pbl_addr,
dacd88d6 1124 u16 pbl_size, void __iomem **pp_doorbell)
cee4d264 1125{
cee4d264
MC		 1126 int rc;
1127
dacd88d6 1128
3da7a37a
MY		 1129 rc = qed_eth_txq_start_ramrod(p_hwfn, p_cid,
1130 pbl_addr, pbl_size,
b5a9ee7c 1131 qed_get_cm_pq_idx_mcos(p_hwfn, tc));
cee4d264
MC		 1132 if (rc)
1133 return rc;
1134
3da7a37a
MY		 1135 /* Provide the caller with the necessary return values */
1136 *pp_doorbell = p_hwfn->doorbells +
1137 qed_db_addr(p_cid->cid, DQ_DEMS_LEGACY);
cee4d264 1138
3da7a37a
MY		 1139 return 0;
1140}
cee4d264 1141
3da7a37a
MY		 1142static int
1143qed_eth_tx_queue_start(struct qed_hwfn *p_hwfn,
1144 u16 opaque_fid,
1145 struct qed_queue_start_common_params *p_params,
1146 u8 tc,
1147 dma_addr_t pbl_addr,
1148 u16 pbl_size,
1149 struct qed_txq_start_ret_params *p_ret_params)
1150{
1151 struct qed_queue_cid *p_cid;
1152 int rc;
1153
007bc371 1154 p_cid = qed_eth_queue_to_cid_pf(p_hwfn, opaque_fid, false, p_params);
3da7a37a
MY		 1155 if (!p_cid)
1156 return -EINVAL;
1157
1158 if (IS_PF(p_hwfn->cdev))
1159 rc = qed_eth_pf_tx_queue_start(p_hwfn, p_cid, tc,
1160 pbl_addr, pbl_size,
1161 &p_ret_params->p_doorbell);
1162 else
1163 rc = qed_vf_pf_txq_start(p_hwfn, p_cid,
1164 pbl_addr, pbl_size,
1165 &p_ret_params->p_doorbell);
cee4d264
MC		 1166
1167 if (rc)
3da7a37a
MY		 1168 qed_eth_queue_cid_release(p_hwfn, p_cid);
1169 else
1170 p_ret_params->p_handle = (void *)p_cid;
cee4d264
MC		 1171
1172 return rc;
1173}
1174
3da7a37a
MY		 1175static int
1176qed_eth_pf_tx_queue_stop(struct qed_hwfn *p_hwfn, struct qed_queue_cid *p_cid)
cee4d264 1177{
cee4d264 1178 struct qed_spq_entry *p_ent = NULL;
06f56b81 1179 struct qed_sp_init_data init_data;
3da7a37a 1180 int rc;
dacd88d6 1181
06f56b81 1182 memset(&init_data, 0, sizeof(init_data));
3da7a37a
MY		 1183 init_data.cid = p_cid->cid;
1184 init_data.opaque_fid = p_cid->opaque_fid;
06f56b81 1185 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
cee4d264
MC		 1186
1187 rc = qed_sp_init_request(p_hwfn, &p_ent,
cee4d264 1188 ETH_RAMROD_TX_QUEUE_STOP,
06f56b81 1189 PROTOCOLID_ETH, &init_data);
cee4d264
MC		 1190 if (rc)
1191 return rc;
1192
3da7a37a
MY		 1193 return qed_spq_post(p_hwfn, p_ent, NULL);
1194}
1195
1196int qed_eth_tx_queue_stop(struct qed_hwfn *p_hwfn, void *p_handle)
1197{
1198 struct qed_queue_cid *p_cid = (struct qed_queue_cid *)p_handle;
1199 int rc;
1200
1201 if (IS_PF(p_hwfn->cdev))
1202 rc = qed_eth_pf_tx_queue_stop(p_hwfn, p_cid);
1203 else
1204 rc = qed_vf_pf_txq_stop(p_hwfn, p_cid);
cee4d264 1205
3da7a37a
MY		 1206 if (!rc)
1207 qed_eth_queue_cid_release(p_hwfn, p_cid);
1208 return rc;
cee4d264
MC		 1209}
1210
1a635e48 1211static enum eth_filter_action qed_filter_action(enum qed_filter_opcode opcode)
cee4d264
MC		 1212{
1213 enum eth_filter_action action = MAX_ETH_FILTER_ACTION;
1214
1215 switch (opcode) {
1216 case QED_FILTER_ADD:
1217 action = ETH_FILTER_ACTION_ADD;
1218 break;
1219 case QED_FILTER_REMOVE:
1220 action = ETH_FILTER_ACTION_REMOVE;
1221 break;
cee4d264 1222 case QED_FILTER_FLUSH:
fc48b7a6 1223 action = ETH_FILTER_ACTION_REMOVE_ALL;
cee4d264
MC		 1224 break;
1225 default:
1226 action = MAX_ETH_FILTER_ACTION;
1227 }
1228
1229 return action;
1230}
1231
cee4d264
MC		 1232static int
1233qed_filter_ucast_common(struct qed_hwfn *p_hwfn,
1234 u16 opaque_fid,
1235 struct qed_filter_ucast *p_filter_cmd,
1236 struct vport_filter_update_ramrod_data **pp_ramrod,
1237 struct qed_spq_entry **pp_ent,
1238 enum spq_mode comp_mode,
1239 struct qed_spq_comp_cb *p_comp_data)
1240{
1241 u8 vport_to_add_to = 0, vport_to_remove_from = 0;
1242 struct vport_filter_update_ramrod_data *p_ramrod;
cee4d264
MC		 1243 struct eth_filter_cmd *p_first_filter;
1244 struct eth_filter_cmd *p_second_filter;
06f56b81 1245 struct qed_sp_init_data init_data;
cee4d264
MC		 1246 enum eth_filter_action action;
1247 int rc;
1248
1249 rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from,
1250 &vport_to_remove_from);
1251 if (rc)
1252 return rc;
1253
1254 rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to,
1255 &vport_to_add_to);
1256 if (rc)
1257 return rc;
1258
06f56b81
YM		 1259 /* Get SPQ entry */
1260 memset(&init_data, 0, sizeof(init_data));
1261 init_data.cid = qed_spq_get_cid(p_hwfn);
1262 init_data.opaque_fid = opaque_fid;
1263 init_data.comp_mode = comp_mode;
1264 init_data.p_comp_data = p_comp_data;
cee4d264
MC		 1265
1266 rc = qed_sp_init_request(p_hwfn, pp_ent,
cee4d264 1267 ETH_RAMROD_FILTERS_UPDATE,
06f56b81 1268 PROTOCOLID_ETH, &init_data);
cee4d264
MC		 1269 if (rc)
1270 return rc;
1271
1272 *pp_ramrod = &(*pp_ent)->ramrod.vport_filter_update;
1273 p_ramrod = *pp_ramrod;
1274 p_ramrod->filter_cmd_hdr.rx = p_filter_cmd->is_rx_filter ? 1 : 0;
1275 p_ramrod->filter_cmd_hdr.tx = p_filter_cmd->is_tx_filter ? 1 : 0;
1276
1277 switch (p_filter_cmd->opcode) {
fc48b7a6 1278 case QED_FILTER_REPLACE:
cee4d264
MC		 1279 case QED_FILTER_MOVE:
1280 p_ramrod->filter_cmd_hdr.cmd_cnt = 2; break;
1281 default:
1282 p_ramrod->filter_cmd_hdr.cmd_cnt = 1; break;
1283 }
1284
1285 p_first_filter = &p_ramrod->filter_cmds[0];
1286 p_second_filter = &p_ramrod->filter_cmds[1];
1287
1288 switch (p_filter_cmd->type) {
1289 case QED_FILTER_MAC:
1290 p_first_filter->type = ETH_FILTER_TYPE_MAC; break;
1291 case QED_FILTER_VLAN:
1292 p_first_filter->type = ETH_FILTER_TYPE_VLAN; break;
1293 case QED_FILTER_MAC_VLAN:
1294 p_first_filter->type = ETH_FILTER_TYPE_PAIR; break;
1295 case QED_FILTER_INNER_MAC:
1296 p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC; break;
1297 case QED_FILTER_INNER_VLAN:
1298 p_first_filter->type = ETH_FILTER_TYPE_INNER_VLAN; break;
1299 case QED_FILTER_INNER_PAIR:
1300 p_first_filter->type = ETH_FILTER_TYPE_INNER_PAIR; break;
1301 case QED_FILTER_INNER_MAC_VNI_PAIR:
1302 p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR;
1303 break;
1304 case QED_FILTER_MAC_VNI_PAIR:
1305 p_first_filter->type = ETH_FILTER_TYPE_MAC_VNI_PAIR; break;
1306 case QED_FILTER_VNI:
1307 p_first_filter->type = ETH_FILTER_TYPE_VNI; break;
1308 }
1309
1310 if ((p_first_filter->type == ETH_FILTER_TYPE_MAC) ||
1311 (p_first_filter->type == ETH_FILTER_TYPE_PAIR) ||
1312 (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC) ||
1313 (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR) ||
1314 (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) ||
1315 (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR)) {
1316 qed_set_fw_mac_addr(&p_first_filter->mac_msb,
1317 &p_first_filter->mac_mid,
1318 &p_first_filter->mac_lsb,
1319 (u8 *)p_filter_cmd->mac);
1320 }
1321
1322 if ((p_first_filter->type == ETH_FILTER_TYPE_VLAN) ||
1323 (p_first_filter->type == ETH_FILTER_TYPE_PAIR) ||
1324 (p_first_filter->type == ETH_FILTER_TYPE_INNER_VLAN) ||
1325 (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR))
1326 p_first_filter->vlan_id = cpu_to_le16(p_filter_cmd->vlan);
1327
1328 if ((p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) ||
1329 (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR) ||
1330 (p_first_filter->type == ETH_FILTER_TYPE_VNI))
1331 p_first_filter->vni = cpu_to_le32(p_filter_cmd->vni);
1332
1333 if (p_filter_cmd->opcode == QED_FILTER_MOVE) {
1a635e48
YM		 1334 p_second_filter->type = p_first_filter->type;
1335 p_second_filter->mac_msb = p_first_filter->mac_msb;
1336 p_second_filter->mac_mid = p_first_filter->mac_mid;
1337 p_second_filter->mac_lsb = p_first_filter->mac_lsb;
1338 p_second_filter->vlan_id = p_first_filter->vlan_id;
1339 p_second_filter->vni = p_first_filter->vni;
cee4d264
MC		 1340
1341 p_first_filter->action = ETH_FILTER_ACTION_REMOVE;
1342
1343 p_first_filter->vport_id = vport_to_remove_from;
1344
1a635e48
YM		 1345 p_second_filter->action = ETH_FILTER_ACTION_ADD;
1346 p_second_filter->vport_id = vport_to_add_to;
fc48b7a6
YM		 1347 } else if (p_filter_cmd->opcode == QED_FILTER_REPLACE) {
1348 p_first_filter->vport_id = vport_to_add_to;
1349 memcpy(p_second_filter, p_first_filter,
1350 sizeof(*p_second_filter));
1351 p_first_filter->action = ETH_FILTER_ACTION_REMOVE_ALL;
1352 p_second_filter->action = ETH_FILTER_ACTION_ADD;
cee4d264
MC		 1353 } else {
1354 action = qed_filter_action(p_filter_cmd->opcode);
1355
1356 if (action == MAX_ETH_FILTER_ACTION) {
1357 DP_NOTICE(p_hwfn,
1358 "%d is not supported yet\n",
1359 p_filter_cmd->opcode);
1360 return -EINVAL;
1361 }
1362
1363 p_first_filter->action = action;
1364 p_first_filter->vport_id = (p_filter_cmd->opcode ==
1365 QED_FILTER_REMOVE) ?
1366 vport_to_remove_from :
1367 vport_to_add_to;
1368 }
1369
1370 return 0;
1371}
1372
dacd88d6
YM		 1373int qed_sp_eth_filter_ucast(struct qed_hwfn *p_hwfn,
1374 u16 opaque_fid,
1375 struct qed_filter_ucast *p_filter_cmd,
1376 enum spq_mode comp_mode,
1377 struct qed_spq_comp_cb *p_comp_data)
cee4d264
MC		 1378{
1379 struct vport_filter_update_ramrod_data *p_ramrod = NULL;
1380 struct qed_spq_entry *p_ent = NULL;
1381 struct eth_filter_cmd_header *p_header;
1382 int rc;
1383
1384 rc = qed_filter_ucast_common(p_hwfn, opaque_fid, p_filter_cmd,
1385 &p_ramrod, &p_ent,
1386 comp_mode, p_comp_data);
1a635e48 1387 if (rc) {
cee4d264
MC		 1388 DP_ERR(p_hwfn, "Uni. filter command failed %d\n", rc);
1389 return rc;
1390 }
1391 p_header = &p_ramrod->filter_cmd_hdr;
1392 p_header->assert_on_error = p_filter_cmd->assert_on_error;
1393
1394 rc = qed_spq_post(p_hwfn, p_ent, NULL);
1a635e48
YM		 1395 if (rc) {
1396 DP_ERR(p_hwfn, "Unicast filter ADD command failed %d\n", rc);
cee4d264
MC		 1397 return rc;
1398 }
1399
1400 DP_VERBOSE(p_hwfn, QED_MSG_SP,
1401 "Unicast filter configured, opcode = %s, type = %s, cmd_cnt = %d, is_rx_filter = %d, is_tx_filter = %d\n",
1402 (p_filter_cmd->opcode == QED_FILTER_ADD) ? "ADD" :
1403 ((p_filter_cmd->opcode == QED_FILTER_REMOVE) ?
1404 "REMOVE" :
1405 ((p_filter_cmd->opcode == QED_FILTER_MOVE) ?
1406 "MOVE" : "REPLACE")),
1407 (p_filter_cmd->type == QED_FILTER_MAC) ? "MAC" :
1408 ((p_filter_cmd->type == QED_FILTER_VLAN) ?
1409 "VLAN" : "MAC & VLAN"),
1410 p_ramrod->filter_cmd_hdr.cmd_cnt,
1411 p_filter_cmd->is_rx_filter,
1412 p_filter_cmd->is_tx_filter);
1413 DP_VERBOSE(p_hwfn, QED_MSG_SP,
1414 "vport_to_add_to = %d, vport_to_remove_from = %d, mac = %2x:%2x:%2x:%2x:%2x:%2x, vlan = %d\n",
1415 p_filter_cmd->vport_to_add_to,
1416 p_filter_cmd->vport_to_remove_from,
1417 p_filter_cmd->mac[0],
1418 p_filter_cmd->mac[1],
1419 p_filter_cmd->mac[2],
1420 p_filter_cmd->mac[3],
1421 p_filter_cmd->mac[4],
1422 p_filter_cmd->mac[5],
1423 p_filter_cmd->vlan);
1424
1425 return 0;
1426}
1427
1428/*******************************************************************************
1429 * Description:
1430 * Calculates crc 32 on a buffer
1431 * Note: crc32_length MUST be aligned to 8
1432 * Return:
1433 ******************************************************************************/
1434static u32 qed_calc_crc32c(u8 *crc32_packet,
1a635e48 1435 u32 crc32_length, u32 crc32_seed, u8 complement)
cee4d264 1436{
1a635e48
YM		 1437 u32 byte = 0, bit = 0, crc32_result = crc32_seed;
1438 u8 msb = 0, current_byte = 0;
cee4d264
MC		 1439
1440 if ((!crc32_packet) ||
1441 (crc32_length == 0) ||
1442 ((crc32_length % 8) != 0))
1443 return crc32_result;
1444 for (byte = 0; byte < crc32_length; byte++) {
1445 current_byte = crc32_packet[byte];
1446 for (bit = 0; bit < 8; bit++) {
1447 msb = (u8)(crc32_result >> 31);
1448 crc32_result = crc32_result << 1;
1449 if (msb != (0x1 & (current_byte >> bit))) {
1450 crc32_result = crc32_result ^ CRC32_POLY;
1451 crc32_result |= 1; /*crc32_result[0] = 1;*/
1452 }
1453 }
1454 }
1455 return crc32_result;
1456}
1457
1a635e48 1458static u32 qed_crc32c_le(u32 seed, u8 *mac, u32 len)
cee4d264
MC		 1459{
1460 u32 packet_buf[2] = { 0 };
1461
1462 memcpy((u8 *)(&packet_buf[0]), &mac[0], 6);
1463 return qed_calc_crc32c((u8 *)packet_buf, 8, seed, 0);
1464}
1465
dacd88d6 1466u8 qed_mcast_bin_from_mac(u8 *mac)
cee4d264
MC		 1467{
1468 u32 crc = qed_crc32c_le(ETH_MULTICAST_BIN_FROM_MAC_SEED,
1469 mac, ETH_ALEN);
1470
1471 return crc & 0xff;
1472}
1473
1474static int
1475qed_sp_eth_filter_mcast(struct qed_hwfn *p_hwfn,
1476 u16 opaque_fid,
1477 struct qed_filter_mcast *p_filter_cmd,
1478 enum spq_mode comp_mode,
1479 struct qed_spq_comp_cb *p_comp_data)
1480{
cee4d264 1481 struct vport_update_ramrod_data *p_ramrod = NULL;
b2aa32e7 1482 u32 bins[ETH_MULTICAST_MAC_BINS_IN_REGS];
cee4d264 1483 struct qed_spq_entry *p_ent = NULL;
06f56b81 1484 struct qed_sp_init_data init_data;
cee4d264
MC		 1485 u8 abs_vport_id = 0;
1486 int rc, i;
1487
83aeb933 1488 if (p_filter_cmd->opcode == QED_FILTER_ADD)
cee4d264
MC		 1489 rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to,
1490 &abs_vport_id);
83aeb933 1491 else
cee4d264
MC		 1492 rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from,
1493 &abs_vport_id);
83aeb933
YM		 1494 if (rc)
1495 return rc;
cee4d264 1496
06f56b81
YM		 1497 /* Get SPQ entry */
1498 memset(&init_data, 0, sizeof(init_data));
1499 init_data.cid = qed_spq_get_cid(p_hwfn);
1500 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
1501 init_data.comp_mode = comp_mode;
1502 init_data.p_comp_data = p_comp_data;
cee4d264
MC		 1503
1504 rc = qed_sp_init_request(p_hwfn, &p_ent,
cee4d264 1505 ETH_RAMROD_VPORT_UPDATE,
06f56b81 1506 PROTOCOLID_ETH, &init_data);
cee4d264
MC		 1507 if (rc) {
1508 DP_ERR(p_hwfn, "Multi-cast command failed %d\n", rc);
1509 return rc;
1510 }
1511
1512 p_ramrod = &p_ent->ramrod.vport_update;
1513 p_ramrod->common.update_approx_mcast_flg = 1;
1514
1515 /* explicitly clear out the entire vector */
1516 memset(&p_ramrod->approx_mcast.bins, 0,
1517 sizeof(p_ramrod->approx_mcast.bins));
b2aa32e7 1518 memset(bins, 0, sizeof(bins));
cee4d264
MC		 1519 /* filter ADD op is explicit set op and it removes
1520 * any existing filters for the vport
1521 */
1522 if (p_filter_cmd->opcode == QED_FILTER_ADD) {
1523 for (i = 0; i < p_filter_cmd->num_mc_addrs; i++) {
b2aa32e7 1524 u32 bit, nbits;
cee4d264
MC		 1525
1526 bit = qed_mcast_bin_from_mac(p_filter_cmd->mac[i]);
b2aa32e7
SRK		 1527 nbits = sizeof(u32) * BITS_PER_BYTE;
1528 bins[bit / nbits] |= 1 << (bit % nbits);
cee4d264
MC		 1529 }
1530
1531 /* Convert to correct endianity */
1532 for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) {
1a635e48 1533 struct vport_update_ramrod_mcast *p_ramrod_bins;
cee4d264 1534
1a635e48 1535 p_ramrod_bins = &p_ramrod->approx_mcast;
b2aa32e7 1536 p_ramrod_bins->bins[i] = cpu_to_le32(bins[i]);
cee4d264
MC		 1537 }
1538 }
1539
1540 p_ramrod->common.vport_id = abs_vport_id;
1541
1542 return qed_spq_post(p_hwfn, p_ent, NULL);
1543}
1544
dacd88d6
YM		 1545static int qed_filter_mcast_cmd(struct qed_dev *cdev,
1546 struct qed_filter_mcast *p_filter_cmd,
1547 enum spq_mode comp_mode,
1548 struct qed_spq_comp_cb *p_comp_data)
cee4d264
MC		 1549{
1550 int rc = 0;
1551 int i;
1552
1553 /* only ADD and REMOVE operations are supported for multi-cast */
1554 if ((p_filter_cmd->opcode != QED_FILTER_ADD &&
1555 (p_filter_cmd->opcode != QED_FILTER_REMOVE)) ||
1556 (p_filter_cmd->num_mc_addrs > QED_MAX_MC_ADDRS))
1557 return -EINVAL;
1558
1559 for_each_hwfn(cdev, i) {
1560 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1561
1562 u16 opaque_fid;
1563
dacd88d6
YM		 1564 if (IS_VF(cdev)) {
1565 qed_vf_pf_filter_mcast(p_hwfn, p_filter_cmd);
1566 continue;
1567 }
cee4d264
MC		 1568
1569 opaque_fid = p_hwfn->hw_info.opaque_fid;
1570
1571 rc = qed_sp_eth_filter_mcast(p_hwfn,
1572 opaque_fid,
1573 p_filter_cmd,
1a635e48 1574 comp_mode, p_comp_data);
cee4d264
MC		 1575 }
1576 return rc;
1577}
1578
1579static int qed_filter_ucast_cmd(struct qed_dev *cdev,
1580 struct qed_filter_ucast *p_filter_cmd,
1581 enum spq_mode comp_mode,
1582 struct qed_spq_comp_cb *p_comp_data)
1583{
1584 int rc = 0;
1585 int i;
1586
1587 for_each_hwfn(cdev, i) {
1588 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1589 u16 opaque_fid;
1590
dacd88d6
YM		 1591 if (IS_VF(cdev)) {
1592 rc = qed_vf_pf_filter_ucast(p_hwfn, p_filter_cmd);
1593 continue;
1594 }
cee4d264
MC		 1595
1596 opaque_fid = p_hwfn->hw_info.opaque_fid;
1597
1598 rc = qed_sp_eth_filter_ucast(p_hwfn,
1599 opaque_fid,
1600 p_filter_cmd,
1a635e48
YM		 1601 comp_mode, p_comp_data);
1602 if (rc)
dacd88d6 1603 break;
cee4d264
MC		 1604 }
1605
1606 return rc;
1607}
1608
86622ee7
YM		 1609/* Statistics related code */
1610static void __qed_get_vport_pstats_addrlen(struct qed_hwfn *p_hwfn,
1611 u32 *p_addr,
dacd88d6 1612 u32 *p_len, u16 statistics_bin)
86622ee7 1613{
dacd88d6
YM		 1614 if (IS_PF(p_hwfn->cdev)) {
1615 *p_addr = BAR0_MAP_REG_PSDM_RAM +
1616 PSTORM_QUEUE_STAT_OFFSET(statistics_bin);
1617 *p_len = sizeof(struct eth_pstorm_per_queue_stat);
1618 } else {
1619 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
1620 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1621
1622 *p_addr = p_resp->pfdev_info.stats_info.pstats.address;
1623 *p_len = p_resp->pfdev_info.stats_info.pstats.len;
1624 }
86622ee7
YM		 1625}
1626
1627static void __qed_get_vport_pstats(struct qed_hwfn *p_hwfn,
1628 struct qed_ptt *p_ptt,
1629 struct qed_eth_stats *p_stats,
1630 u16 statistics_bin)
1631{
1632 struct eth_pstorm_per_queue_stat pstats;
1633 u32 pstats_addr = 0, pstats_len = 0;
1634
1635 __qed_get_vport_pstats_addrlen(p_hwfn, &pstats_addr, &pstats_len,
1636 statistics_bin);
1637
1638 memset(&pstats, 0, sizeof(pstats));
dacd88d6
YM		 1639 qed_memcpy_from(p_hwfn, p_ptt, &pstats, pstats_addr, pstats_len);
1640
9c79ddaa
MY		 1641 p_stats->common.tx_ucast_bytes +=
1642 HILO_64_REGPAIR(pstats.sent_ucast_bytes);
1643 p_stats->common.tx_mcast_bytes +=
1644 HILO_64_REGPAIR(pstats.sent_mcast_bytes);
1645 p_stats->common.tx_bcast_bytes +=
1646 HILO_64_REGPAIR(pstats.sent_bcast_bytes);
1647 p_stats->common.tx_ucast_pkts +=
1648 HILO_64_REGPAIR(pstats.sent_ucast_pkts);
1649 p_stats->common.tx_mcast_pkts +=
1650 HILO_64_REGPAIR(pstats.sent_mcast_pkts);
1651 p_stats->common.tx_bcast_pkts +=
1652 HILO_64_REGPAIR(pstats.sent_bcast_pkts);
1653 p_stats->common.tx_err_drop_pkts +=
1654 HILO_64_REGPAIR(pstats.error_drop_pkts);
86622ee7
YM		 1655}
1656
1657static void __qed_get_vport_tstats(struct qed_hwfn *p_hwfn,
1658 struct qed_ptt *p_ptt,
1659 struct qed_eth_stats *p_stats,
1660 u16 statistics_bin)
1661{
86622ee7 1662 struct tstorm_per_port_stat tstats;
dacd88d6 1663 u32 tstats_addr, tstats_len;
86622ee7 1664
dacd88d6
YM		 1665 if (IS_PF(p_hwfn->cdev)) {
1666 tstats_addr = BAR0_MAP_REG_TSDM_RAM +
1667 TSTORM_PORT_STAT_OFFSET(MFW_PORT(p_hwfn));
1668 tstats_len = sizeof(struct tstorm_per_port_stat);
1669 } else {
1670 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
1671 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1672
1673 tstats_addr = p_resp->pfdev_info.stats_info.tstats.address;
1674 tstats_len = p_resp->pfdev_info.stats_info.tstats.len;
1675 }
86622ee7
YM		 1676
1677 memset(&tstats, 0, sizeof(tstats));
dacd88d6 1678 qed_memcpy_from(p_hwfn, p_ptt, &tstats, tstats_addr, tstats_len);
86622ee7 1679
9c79ddaa
MY		 1680 p_stats->common.mftag_filter_discards +=
1681 HILO_64_REGPAIR(tstats.mftag_filter_discard);
1682 p_stats->common.mac_filter_discards +=
1683 HILO_64_REGPAIR(tstats.eth_mac_filter_discard);
86622ee7
YM		 1684}
1685
1686static void __qed_get_vport_ustats_addrlen(struct qed_hwfn *p_hwfn,
1687 u32 *p_addr,
dacd88d6 1688 u32 *p_len, u16 statistics_bin)
86622ee7 1689{
dacd88d6
YM		 1690 if (IS_PF(p_hwfn->cdev)) {
1691 *p_addr = BAR0_MAP_REG_USDM_RAM +
1692 USTORM_QUEUE_STAT_OFFSET(statistics_bin);
1693 *p_len = sizeof(struct eth_ustorm_per_queue_stat);
1694 } else {
1695 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
1696 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1697
1698 *p_addr = p_resp->pfdev_info.stats_info.ustats.address;
1699 *p_len = p_resp->pfdev_info.stats_info.ustats.len;
1700 }
86622ee7
YM		 1701}
1702
1703static void __qed_get_vport_ustats(struct qed_hwfn *p_hwfn,
1704 struct qed_ptt *p_ptt,
1705 struct qed_eth_stats *p_stats,
1706 u16 statistics_bin)
1707{
1708 struct eth_ustorm_per_queue_stat ustats;
1709 u32 ustats_addr = 0, ustats_len = 0;
1710
1711 __qed_get_vport_ustats_addrlen(p_hwfn, &ustats_addr, &ustats_len,
1712 statistics_bin);
1713
1714 memset(&ustats, 0, sizeof(ustats));
dacd88d6
YM		 1715 qed_memcpy_from(p_hwfn, p_ptt, &ustats, ustats_addr, ustats_len);
1716
9c79ddaa
MY		 1717 p_stats->common.rx_ucast_bytes +=
1718 HILO_64_REGPAIR(ustats.rcv_ucast_bytes);
1719 p_stats->common.rx_mcast_bytes +=
1720 HILO_64_REGPAIR(ustats.rcv_mcast_bytes);
1721 p_stats->common.rx_bcast_bytes +=
1722 HILO_64_REGPAIR(ustats.rcv_bcast_bytes);
1723 p_stats->common.rx_ucast_pkts += HILO_64_REGPAIR(ustats.rcv_ucast_pkts);
1724 p_stats->common.rx_mcast_pkts += HILO_64_REGPAIR(ustats.rcv_mcast_pkts);
1725 p_stats->common.rx_bcast_pkts += HILO_64_REGPAIR(ustats.rcv_bcast_pkts);
86622ee7
YM		 1726}
1727
1728static void __qed_get_vport_mstats_addrlen(struct qed_hwfn *p_hwfn,
1729 u32 *p_addr,
dacd88d6 1730 u32 *p_len, u16 statistics_bin)
86622ee7 1731{
dacd88d6
YM		 1732 if (IS_PF(p_hwfn->cdev)) {
1733 *p_addr = BAR0_MAP_REG_MSDM_RAM +
1734 MSTORM_QUEUE_STAT_OFFSET(statistics_bin);
1735 *p_len = sizeof(struct eth_mstorm_per_queue_stat);
1736 } else {
1737 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
1738 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1739
1740 *p_addr = p_resp->pfdev_info.stats_info.mstats.address;
1741 *p_len = p_resp->pfdev_info.stats_info.mstats.len;
1742 }
86622ee7
YM		 1743}
1744
1745static void __qed_get_vport_mstats(struct qed_hwfn *p_hwfn,
1746 struct qed_ptt *p_ptt,
1747 struct qed_eth_stats *p_stats,
1748 u16 statistics_bin)
1749{
1750 struct eth_mstorm_per_queue_stat mstats;
1751 u32 mstats_addr = 0, mstats_len = 0;
1752
1753 __qed_get_vport_mstats_addrlen(p_hwfn, &mstats_addr, &mstats_len,
1754 statistics_bin);
1755
1756 memset(&mstats, 0, sizeof(mstats));
dacd88d6 1757 qed_memcpy_from(p_hwfn, p_ptt, &mstats, mstats_addr, mstats_len);
86622ee7 1758
9c79ddaa
MY		 1759 p_stats->common.no_buff_discards +=
1760 HILO_64_REGPAIR(mstats.no_buff_discard);
1761 p_stats->common.packet_too_big_discard +=
1762 HILO_64_REGPAIR(mstats.packet_too_big_discard);
1763 p_stats->common.ttl0_discard += HILO_64_REGPAIR(mstats.ttl0_discard);
1764 p_stats->common.tpa_coalesced_pkts +=
1765 HILO_64_REGPAIR(mstats.tpa_coalesced_pkts);
1766 p_stats->common.tpa_coalesced_events +=
1767 HILO_64_REGPAIR(mstats.tpa_coalesced_events);
1768 p_stats->common.tpa_aborts_num +=
1769 HILO_64_REGPAIR(mstats.tpa_aborts_num);
1770 p_stats->common.tpa_coalesced_bytes +=
1771 HILO_64_REGPAIR(mstats.tpa_coalesced_bytes);
86622ee7
YM		 1772}
1773
1774static void __qed_get_vport_port_stats(struct qed_hwfn *p_hwfn,
1775 struct qed_ptt *p_ptt,
1776 struct qed_eth_stats *p_stats)
1777{
9c79ddaa 1778 struct qed_eth_stats_common *p_common = &p_stats->common;
86622ee7
YM		 1779 struct port_stats port_stats;
1780 int j;
1781
1782 memset(&port_stats, 0, sizeof(port_stats));
1783
1784 qed_memcpy_from(p_hwfn, p_ptt, &port_stats,
1785 p_hwfn->mcp_info->port_addr +
1786 offsetof(struct public_port, stats),
1787 sizeof(port_stats));
1788
9c79ddaa
MY		 1789 p_common->rx_64_byte_packets += port_stats.eth.r64;
1790 p_common->rx_65_to_127_byte_packets += port_stats.eth.r127;
1791 p_common->rx_128_to_255_byte_packets += port_stats.eth.r255;
1792 p_common->rx_256_to_511_byte_packets += port_stats.eth.r511;
1793 p_common->rx_512_to_1023_byte_packets += port_stats.eth.r1023;
1794 p_common->rx_1024_to_1518_byte_packets += port_stats.eth.r1518;
1795 p_common->rx_crc_errors += port_stats.eth.rfcs;
1796 p_common->rx_mac_crtl_frames += port_stats.eth.rxcf;
1797 p_common->rx_pause_frames += port_stats.eth.rxpf;
1798 p_common->rx_pfc_frames += port_stats.eth.rxpp;
1799 p_common->rx_align_errors += port_stats.eth.raln;
1800 p_common->rx_carrier_errors += port_stats.eth.rfcr;
1801 p_common->rx_oversize_packets += port_stats.eth.rovr;
1802 p_common->rx_jabbers += port_stats.eth.rjbr;
1803 p_common->rx_undersize_packets += port_stats.eth.rund;
1804 p_common->rx_fragments += port_stats.eth.rfrg;
1805 p_common->tx_64_byte_packets += port_stats.eth.t64;
1806 p_common->tx_65_to_127_byte_packets += port_stats.eth.t127;
1807 p_common->tx_128_to_255_byte_packets += port_stats.eth.t255;
1808 p_common->tx_256_to_511_byte_packets += port_stats.eth.t511;
1809 p_common->tx_512_to_1023_byte_packets += port_stats.eth.t1023;
1810 p_common->tx_1024_to_1518_byte_packets += port_stats.eth.t1518;
1811 p_common->tx_pause_frames += port_stats.eth.txpf;
1812 p_common->tx_pfc_frames += port_stats.eth.txpp;
1813 p_common->rx_mac_bytes += port_stats.eth.rbyte;
1814 p_common->rx_mac_uc_packets += port_stats.eth.rxuca;
1815 p_common->rx_mac_mc_packets += port_stats.eth.rxmca;
1816 p_common->rx_mac_bc_packets += port_stats.eth.rxbca;
1817 p_common->rx_mac_frames_ok += port_stats.eth.rxpok;
1818 p_common->tx_mac_bytes += port_stats.eth.tbyte;
1819 p_common->tx_mac_uc_packets += port_stats.eth.txuca;
1820 p_common->tx_mac_mc_packets += port_stats.eth.txmca;
1821 p_common->tx_mac_bc_packets += port_stats.eth.txbca;
1822 p_common->tx_mac_ctrl_frames += port_stats.eth.txcf;
86622ee7 1823 for (j = 0; j < 8; j++) {
9c79ddaa
MY		 1824 p_common->brb_truncates += port_stats.brb.brb_truncate[j];
1825 p_common->brb_discards += port_stats.brb.brb_discard[j];
1826 }
1827
1828 if (QED_IS_BB(p_hwfn->cdev)) {
1829 struct qed_eth_stats_bb *p_bb = &p_stats->bb;
1830
1831 p_bb->rx_1519_to_1522_byte_packets +=
1832 port_stats.eth.u0.bb0.r1522;
1833 p_bb->rx_1519_to_2047_byte_packets +=
1834 port_stats.eth.u0.bb0.r2047;
1835 p_bb->rx_2048_to_4095_byte_packets +=
1836 port_stats.eth.u0.bb0.r4095;
1837 p_bb->rx_4096_to_9216_byte_packets +=
1838 port_stats.eth.u0.bb0.r9216;
1839 p_bb->rx_9217_to_16383_byte_packets +=
1840 port_stats.eth.u0.bb0.r16383;
1841 p_bb->tx_1519_to_2047_byte_packets +=
1842 port_stats.eth.u1.bb1.t2047;
1843 p_bb->tx_2048_to_4095_byte_packets +=
1844 port_stats.eth.u1.bb1.t4095;
1845 p_bb->tx_4096_to_9216_byte_packets +=
1846 port_stats.eth.u1.bb1.t9216;
1847 p_bb->tx_9217_to_16383_byte_packets +=
1848 port_stats.eth.u1.bb1.t16383;
1849 p_bb->tx_lpi_entry_count += port_stats.eth.u2.bb2.tlpiec;
1850 p_bb->tx_total_collisions += port_stats.eth.u2.bb2.tncl;
1851 } else {
1852 struct qed_eth_stats_ah *p_ah = &p_stats->ah;
1853
1854 p_ah->rx_1519_to_max_byte_packets +=
1855 port_stats.eth.u0.ah0.r1519_to_max;
1856 p_ah->tx_1519_to_max_byte_packets =
1857 port_stats.eth.u1.ah1.t1519_to_max;
86622ee7
YM		 1858 }
1859}
1860
1861static void __qed_get_vport_stats(struct qed_hwfn *p_hwfn,
1862 struct qed_ptt *p_ptt,
1863 struct qed_eth_stats *stats,
dacd88d6 1864 u16 statistics_bin, bool b_get_port_stats)
86622ee7
YM		 1865{
1866 __qed_get_vport_mstats(p_hwfn, p_ptt, stats, statistics_bin);
1867 __qed_get_vport_ustats(p_hwfn, p_ptt, stats, statistics_bin);
1868 __qed_get_vport_tstats(p_hwfn, p_ptt, stats, statistics_bin);
1869 __qed_get_vport_pstats(p_hwfn, p_ptt, stats, statistics_bin);
1870
dacd88d6 1871 if (b_get_port_stats && p_hwfn->mcp_info)
86622ee7
YM		 1872 __qed_get_vport_port_stats(p_hwfn, p_ptt, stats);
1873}
1874
1875static void _qed_get_vport_stats(struct qed_dev *cdev,
1876 struct qed_eth_stats *stats)
1877{
dacd88d6
YM		 1878 u8 fw_vport = 0;
1879 int i;
86622ee7
YM		 1880
1881 memset(stats, 0, sizeof(*stats));
1882
1883 for_each_hwfn(cdev, i) {
1884 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
dacd88d6
YM		 1885 struct qed_ptt *p_ptt = IS_PF(cdev) ? qed_ptt_acquire(p_hwfn)
1886 : NULL;
1887
1888 if (IS_PF(cdev)) {
1889 /* The main vport index is relative first */
1890 if (qed_fw_vport(p_hwfn, 0, &fw_vport)) {
1891 DP_ERR(p_hwfn, "No vport available!\n");
1892 goto out;
1893 }
86622ee7
YM		 1894 }
1895
dacd88d6 1896 if (IS_PF(cdev) && !p_ptt) {
86622ee7
YM		 1897 DP_ERR(p_hwfn, "Failed to acquire ptt\n");
1898 continue;
1899 }
1900
dacd88d6
YM		 1901 __qed_get_vport_stats(p_hwfn, p_ptt, stats, fw_vport,
1902 IS_PF(cdev) ? true : false);
86622ee7 1903
dacd88d6
YM		 1904out:
1905 if (IS_PF(cdev) && p_ptt)
1906 qed_ptt_release(p_hwfn, p_ptt);
86622ee7
YM		 1907 }
1908}
1909
1a635e48 1910void qed_get_vport_stats(struct qed_dev *cdev, struct qed_eth_stats *stats)
86622ee7
YM		 1911{
1912 u32 i;
1913
1914 if (!cdev) {
1915 memset(stats, 0, sizeof(*stats));
1916 return;
1917 }
1918
1919 _qed_get_vport_stats(cdev, stats);
1920
1921 if (!cdev->reset_stats)
1922 return;
1923
1924 /* Reduce the statistics baseline */
1925 for (i = 0; i < sizeof(struct qed_eth_stats) / sizeof(u64); i++)
1926 ((u64 *)stats)[i] -= ((u64 *)cdev->reset_stats)[i];
1927}
1928
1929/* zeroes V-PORT specific portion of stats (Port stats remains untouched) */
1930void qed_reset_vport_stats(struct qed_dev *cdev)
1931{
1932 int i;
1933
1934 for_each_hwfn(cdev, i) {
1935 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1936 struct eth_mstorm_per_queue_stat mstats;
1937 struct eth_ustorm_per_queue_stat ustats;
1938 struct eth_pstorm_per_queue_stat pstats;
dacd88d6
YM		 1939 struct qed_ptt *p_ptt = IS_PF(cdev) ? qed_ptt_acquire(p_hwfn)
1940 : NULL;
86622ee7
YM		 1941 u32 addr = 0, len = 0;
1942
dacd88d6 1943 if (IS_PF(cdev) && !p_ptt) {
86622ee7
YM		 1944 DP_ERR(p_hwfn, "Failed to acquire ptt\n");
1945 continue;
1946 }
1947
1948 memset(&mstats, 0, sizeof(mstats));
1949 __qed_get_vport_mstats_addrlen(p_hwfn, &addr, &len, 0);
1950 qed_memcpy_to(p_hwfn, p_ptt, addr, &mstats, len);
1951
1952 memset(&ustats, 0, sizeof(ustats));
1953 __qed_get_vport_ustats_addrlen(p_hwfn, &addr, &len, 0);
1954 qed_memcpy_to(p_hwfn, p_ptt, addr, &ustats, len);
1955
1956 memset(&pstats, 0, sizeof(pstats));
1957 __qed_get_vport_pstats_addrlen(p_hwfn, &addr, &len, 0);
1958 qed_memcpy_to(p_hwfn, p_ptt, addr, &pstats, len);
1959
dacd88d6
YM		 1960 if (IS_PF(cdev))
1961 qed_ptt_release(p_hwfn, p_ptt);
86622ee7
YM		 1962 }
1963
1964 /* PORT statistics are not necessarily reset, so we need to
1965 * read and create a baseline for future statistics.
1966 */
1967 if (!cdev->reset_stats)
1968 DP_INFO(cdev, "Reset stats not allocated\n");
1969 else
1970 _qed_get_vport_stats(cdev, cdev->reset_stats);
1971}
1972
d51e4af5
CM		 1973static void
1974qed_arfs_mode_configure(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
1975 struct qed_arfs_config_params *p_cfg_params)
1976{
1977 if (p_cfg_params->arfs_enable) {
1978 qed_set_rfs_mode_enable(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
1979 p_cfg_params->tcp, p_cfg_params->udp,
1980 p_cfg_params->ipv4, p_cfg_params->ipv6);
1981 DP_VERBOSE(p_hwfn, QED_MSG_SP,
1982 "tcp = %s, udp = %s, ipv4 = %s, ipv6 =%s\n",
1983 p_cfg_params->tcp ? "Enable" : "Disable",
1984 p_cfg_params->udp ? "Enable" : "Disable",
1985 p_cfg_params->ipv4 ? "Enable" : "Disable",
1986 p_cfg_params->ipv6 ? "Enable" : "Disable");
1987 } else {
1988 qed_set_rfs_mode_disable(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1989 }
1990
1991 DP_VERBOSE(p_hwfn, QED_MSG_SP, "Configured ARFS mode : %s\n",
1992 p_cfg_params->arfs_enable ? "Enable" : "Disable");
1993}
1994
1995static int
1996qed_configure_rfs_ntuple_filter(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
1997 struct qed_spq_comp_cb *p_cb,
1998 dma_addr_t p_addr, u16 length, u16 qid,
1999 u8 vport_id, bool b_is_add)
2000{
2001 struct rx_update_gft_filter_data *p_ramrod = NULL;
2002 struct qed_spq_entry *p_ent = NULL;
2003 struct qed_sp_init_data init_data;
2004 u16 abs_rx_q_id = 0;
2005 u8 abs_vport_id = 0;
2006 int rc = -EINVAL;
2007
2008 rc = qed_fw_vport(p_hwfn, vport_id, &abs_vport_id);
2009 if (rc)
2010 return rc;
2011
2012 rc = qed_fw_l2_queue(p_hwfn, qid, &abs_rx_q_id);
2013 if (rc)
2014 return rc;
2015
2016 /* Get SPQ entry */
2017 memset(&init_data, 0, sizeof(init_data));
2018 init_data.cid = qed_spq_get_cid(p_hwfn);
2019
2020 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
2021
2022 if (p_cb) {
2023 init_data.comp_mode = QED_SPQ_MODE_CB;
2024 init_data.p_comp_data = p_cb;
2025 } else {
2026 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
2027 }
2028
2029 rc = qed_sp_init_request(p_hwfn, &p_ent,
2030 ETH_RAMROD_GFT_UPDATE_FILTER,
2031 PROTOCOLID_ETH, &init_data);
2032 if (rc)
2033 return rc;
2034
2035 p_ramrod = &p_ent->ramrod.rx_update_gft;
2036 DMA_REGPAIR_LE(p_ramrod->pkt_hdr_addr, p_addr);
2037 p_ramrod->pkt_hdr_length = cpu_to_le16(length);
2038 p_ramrod->rx_qid_or_action_icid = cpu_to_le16(abs_rx_q_id);
2039 p_ramrod->vport_id = abs_vport_id;
2040 p_ramrod->filter_type = RFS_FILTER_TYPE;
2041 p_ramrod->filter_action = b_is_add ? GFT_ADD_FILTER : GFT_DELETE_FILTER;
2042
2043 DP_VERBOSE(p_hwfn, QED_MSG_SP,
2044 "V[%0x], Q[%04x] - %s filter from 0x%llx [length %04xb]\n",
2045 abs_vport_id, abs_rx_q_id,
2046 b_is_add ? "Adding" : "Removing", (u64)p_addr, length);
2047
2048 return qed_spq_post(p_hwfn, p_ent, NULL);
2049}
2050
bf5a94bf
RV		 2051int qed_get_rxq_coalesce(struct qed_hwfn *p_hwfn,
2052 struct qed_ptt *p_ptt,
2053 struct qed_queue_cid *p_cid, u16 *p_rx_coal)
2054{
2055 u32 coalesce, address, is_valid;
2056 struct cau_sb_entry sb_entry;
2057 u8 timer_res;
2058 int rc;
2059
2060 rc = qed_dmae_grc2host(p_hwfn, p_ptt, CAU_REG_SB_VAR_MEMORY +
2061 p_cid->sb_igu_id * sizeof(u64),
2062 (u64)(uintptr_t)&sb_entry, 2, 0);
2063 if (rc) {
2064 DP_ERR(p_hwfn, "dmae_grc2host failed %d\n", rc);
2065 return rc;
2066 }
2067
2068 timer_res = GET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES0);
2069
2070 address = BAR0_MAP_REG_USDM_RAM +
2071 USTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
2072 coalesce = qed_rd(p_hwfn, p_ptt, address);
2073
2074 is_valid = GET_FIELD(coalesce, COALESCING_TIMESET_VALID);
2075 if (!is_valid)
2076 return -EINVAL;
2077
2078 coalesce = GET_FIELD(coalesce, COALESCING_TIMESET_TIMESET);
2079 *p_rx_coal = (u16)(coalesce << timer_res);
2080
2081 return 0;
2082}
2083
2084int qed_get_txq_coalesce(struct qed_hwfn *p_hwfn,
2085 struct qed_ptt *p_ptt,
2086 struct qed_queue_cid *p_cid, u16 *p_tx_coal)
2087{
2088 u32 coalesce, address, is_valid;
2089 struct cau_sb_entry sb_entry;
2090 u8 timer_res;
2091 int rc;
2092
2093 rc = qed_dmae_grc2host(p_hwfn, p_ptt, CAU_REG_SB_VAR_MEMORY +
2094 p_cid->sb_igu_id * sizeof(u64),
2095 (u64)(uintptr_t)&sb_entry, 2, 0);
2096 if (rc) {
2097 DP_ERR(p_hwfn, "dmae_grc2host failed %d\n", rc);
2098 return rc;
2099 }
2100
2101 timer_res = GET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES1);
2102
2103 address = BAR0_MAP_REG_XSDM_RAM +
2104 XSTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
2105 coalesce = qed_rd(p_hwfn, p_ptt, address);
2106
2107 is_valid = GET_FIELD(coalesce, COALESCING_TIMESET_VALID);
2108 if (!is_valid)
2109 return -EINVAL;
2110
2111 coalesce = GET_FIELD(coalesce, COALESCING_TIMESET_TIMESET);
2112 *p_tx_coal = (u16)(coalesce << timer_res);
2113
2114 return 0;
2115}
2116
2117int qed_get_queue_coalesce(struct qed_hwfn *p_hwfn, u16 *p_coal, void *handle)
2118{
2119 struct qed_queue_cid *p_cid = handle;
2120 struct qed_ptt *p_ptt;
2121 int rc = 0;
2122
2123 if (IS_VF(p_hwfn->cdev)) {
2124 rc = qed_vf_pf_get_coalesce(p_hwfn, p_coal, p_cid);
2125 if (rc)
2126 DP_NOTICE(p_hwfn, "Unable to read queue coalescing\n");
2127
2128 return rc;
2129 }
2130
2131 p_ptt = qed_ptt_acquire(p_hwfn);
2132 if (!p_ptt)
2133 return -EAGAIN;
2134
2135 if (p_cid->b_is_rx) {
2136 rc = qed_get_rxq_coalesce(p_hwfn, p_ptt, p_cid, p_coal);
2137 if (rc)
2138 goto out;
2139 } else {
2140 rc = qed_get_txq_coalesce(p_hwfn, p_ptt, p_cid, p_coal);
2141 if (rc)
2142 goto out;
2143 }
2144
2145out:
2146 qed_ptt_release(p_hwfn, p_ptt);
2147
2148 return rc;
2149}
2150
25c089d7
YM		 2151static int qed_fill_eth_dev_info(struct qed_dev *cdev,
2152 struct qed_dev_eth_info *info)
2153{
2154 int i;
2155
2156 memset(info, 0, sizeof(*info));
2157
2158 info->num_tc = 1;
2159
1408cc1f 2160 if (IS_PF(cdev)) {
25eb8d46 2161 int max_vf_vlan_filters = 0;
7b7e70f9 2162 int max_vf_mac_filters = 0;
25eb8d46 2163
1408cc1f 2164 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
e1d32acb
MY		 2165 u16 num_queues = 0;
2166
2167 /* Since the feature controls only queue-zones,
2168 * make sure we have the contexts [rx, tx, xdp] to
2169 * match.
2170 */
2171 for_each_hwfn(cdev, i) {
2172 struct qed_hwfn *hwfn = &cdev->hwfns[i];
2173 u16 l2_queues = (u16)FEAT_NUM(hwfn,
2174 QED_PF_L2_QUE);
2175 u16 cids;
2176
2177 cids = hwfn->pf_params.eth_pf_params.num_cons;
2178 num_queues += min_t(u16, l2_queues, cids / 3);
2179 }
2180
2181 /* queues might theoretically be >256, but interrupts'
2182 * upper-limit guarantes that it would fit in a u8.
2183 */
2184 if (cdev->int_params.fp_msix_cnt) {
2185 u8 irqs = cdev->int_params.fp_msix_cnt;
2186
2187 info->num_queues = (u8)min_t(u16,
2188 num_queues, irqs);
2189 }
1408cc1f
YM		 2190 } else {
2191 info->num_queues = cdev->num_hwfns;
2192 }
2193
7b7e70f9 2194 if (IS_QED_SRIOV(cdev)) {
25eb8d46
YM		 2195 max_vf_vlan_filters = cdev->p_iov_info->total_vfs *
2196 QED_ETH_VF_NUM_VLAN_FILTERS;
7b7e70f9
YM		 2197 max_vf_mac_filters = cdev->p_iov_info->total_vfs *
2198 QED_ETH_VF_NUM_MAC_FILTERS;
2199 }
2200 info->num_vlan_filters = RESC_NUM(QED_LEADING_HWFN(cdev),
2201 QED_VLAN) -
25eb8d46 2202 max_vf_vlan_filters;
7b7e70f9
YM		 2203 info->num_mac_filters = RESC_NUM(QED_LEADING_HWFN(cdev),
2204 QED_MAC) -
2205 max_vf_mac_filters;
25eb8d46 2206
1408cc1f
YM		 2207 ether_addr_copy(info->port_mac,
2208 cdev->hwfns[0].hw_info.hw_mac_addr);
cbb8a12c
MY		 2209
2210 info->xdp_supported = true;
25c089d7 2211 } else {
cbb8a12c
MY		 2212 u16 total_cids = 0;
2213
2214 /* Determine queues & XDP support */
2215 for_each_hwfn(cdev, i) {
2216 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2217 u8 queues, cids;
25c089d7 2218
cbb8a12c
MY		 2219 qed_vf_get_num_cids(p_hwfn, &cids);
2220 qed_vf_get_num_rxqs(p_hwfn, &queues);
1408cc1f 2221 info->num_queues += queues;
cbb8a12c 2222 total_cids += cids;
1408cc1f
YM		 2223 }
2224
cbb8a12c
MY		 2225 /* Enable VF XDP in case PF guarntees sufficient connections */
2226 if (total_cids >= info->num_queues * 3)
2227 info->xdp_supported = true;
2228
1408cc1f 2229 qed_vf_get_num_vlan_filters(&cdev->hwfns[0],
2edbff8d 2230 (u8 *)&info->num_vlan_filters);
b0fca312
MY		 2231 qed_vf_get_num_mac_filters(&cdev->hwfns[0],
2232 (u8 *)&info->num_mac_filters);
1408cc1f 2233 qed_vf_get_port_mac(&cdev->hwfns[0], info->port_mac);
d8c2c7e3
YM		 2234
2235 info->is_legacy = !!cdev->hwfns[0].vf_iov_info->b_pre_fp_hsi;
1408cc1f 2236 }
25c089d7
YM		 2237
2238 qed_fill_dev_info(cdev, &info->common);
2239
1408cc1f 2240 if (IS_VF(cdev))
0ee28e31 2241 eth_zero_addr(info->common.hw_mac);
1408cc1f 2242
25c089d7
YM		 2243 return 0;
2244}
2245
cc875c2e 2246static void qed_register_eth_ops(struct qed_dev *cdev,
1408cc1f 2247 struct qed_eth_cb_ops *ops, void *cookie)
cc875c2e 2248{
1408cc1f
YM		 2249 cdev->protocol_ops.eth = ops;
2250 cdev->ops_cookie = cookie;
2251
2252 /* For VF, we start bulletin reading */
2253 if (IS_VF(cdev))
2254 qed_vf_start_iov_wq(cdev);
cc875c2e
YM		 2255}
2256
eff16960
YM		 2257static bool qed_check_mac(struct qed_dev *cdev, u8 *mac)
2258{
2259 if (IS_PF(cdev))
2260 return true;
2261
2262 return qed_vf_check_mac(&cdev->hwfns[0], mac);
2263}
2264
cee4d264 2265static int qed_start_vport(struct qed_dev *cdev,
088c8618 2266 struct qed_start_vport_params *params)
cee4d264
MC		 2267{
2268 int rc, i;
2269
2270 for_each_hwfn(cdev, i) {
088c8618 2271 struct qed_sp_vport_start_params start = { 0 };
cee4d264
MC		 2272 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2273
088c8618
MC		 2274 start.tpa_mode = params->gro_enable ? QED_TPA_MODE_GRO :
2275 QED_TPA_MODE_NONE;
2276 start.remove_inner_vlan = params->remove_inner_vlan;
08feecd7 2277 start.only_untagged = true; /* untagged only */
088c8618
MC		 2278 start.drop_ttl0 = params->drop_ttl0;
2279 start.opaque_fid = p_hwfn->hw_info.opaque_fid;
2280 start.concrete_fid = p_hwfn->hw_info.concrete_fid;
c78c70fa 2281 start.handle_ptp_pkts = params->handle_ptp_pkts;
088c8618
MC		 2282 start.vport_id = params->vport_id;
2283 start.max_buffers_per_cqe = 16;
2284 start.mtu = params->mtu;
2285
2286 rc = qed_sp_vport_start(p_hwfn, &start);
cee4d264
MC		 2287 if (rc) {
2288 DP_ERR(cdev, "Failed to start VPORT\n");
2289 return rc;
2290 }
2291
15582962
RV		 2292 rc = qed_hw_start_fastpath(p_hwfn);
2293 if (rc) {
2294 DP_ERR(cdev, "Failed to start VPORT fastpath\n");
2295 return rc;
2296 }
cee4d264
MC		 2297
2298 DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
2299 "Started V-PORT %d with MTU %d\n",
088c8618 2300 start.vport_id, start.mtu);
cee4d264
MC		 2301 }
2302
a0d26d5a
YM		 2303 if (params->clear_stats)
2304 qed_reset_vport_stats(cdev);
9df2ed04 2305
cee4d264
MC		 2306 return 0;
2307}
2308
1a635e48 2309static int qed_stop_vport(struct qed_dev *cdev, u8 vport_id)
cee4d264
MC		 2310{
2311 int rc, i;
2312
2313 for_each_hwfn(cdev, i) {
2314 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2315
2316 rc = qed_sp_vport_stop(p_hwfn,
1a635e48 2317 p_hwfn->hw_info.opaque_fid, vport_id);
cee4d264
MC		 2318
2319 if (rc) {
2320 DP_ERR(cdev, "Failed to stop VPORT\n");
2321 return rc;
2322 }
2323 }
2324 return 0;
2325}
2326
f29ffdb6
MY		 2327static int qed_update_vport_rss(struct qed_dev *cdev,
2328 struct qed_update_vport_rss_params *input,
2329 struct qed_rss_params *rss)
2330{
2331 int i, fn;
2332
2333 /* Update configuration with what's correct regardless of CMT */
2334 rss->update_rss_config = 1;
2335 rss->rss_enable = 1;
2336 rss->update_rss_capabilities = 1;
2337 rss->update_rss_ind_table = 1;
2338 rss->update_rss_key = 1;
2339 rss->rss_caps = input->rss_caps;
2340 memcpy(rss->rss_key, input->rss_key, QED_RSS_KEY_SIZE * sizeof(u32));
2341
2342 /* In regular scenario, we'd simply need to take input handlers.
2343 * But in CMT, we'd have to split the handlers according to the
2344 * engine they were configured on. We'd then have to understand
2345 * whether RSS is really required, since 2-queues on CMT doesn't
2346 * require RSS.
2347 */
2348 if (cdev->num_hwfns == 1) {
2349 memcpy(rss->rss_ind_table,
2350 input->rss_ind_table,
2351 QED_RSS_IND_TABLE_SIZE * sizeof(void *));
2352 rss->rss_table_size_log = 7;
2353 return 0;
2354 }
2355
2356 /* Start by copying the non-spcific information to the 2nd copy */
2357 memcpy(&rss[1], &rss[0], sizeof(struct qed_rss_params));
2358
2359 /* CMT should be round-robin */
2360 for (i = 0; i < QED_RSS_IND_TABLE_SIZE; i++) {
2361 struct qed_queue_cid *cid = input->rss_ind_table[i];
2362 struct qed_rss_params *t_rss;
2363
2364 if (cid->p_owner == QED_LEADING_HWFN(cdev))
2365 t_rss = &rss[0];
2366 else
2367 t_rss = &rss[1];
2368
2369 t_rss->rss_ind_table[i / cdev->num_hwfns] = cid;
2370 }
2371
2372 /* Make sure RSS is actually required */
2373 for_each_hwfn(cdev, fn) {
2374 for (i = 1; i < QED_RSS_IND_TABLE_SIZE / cdev->num_hwfns; i++) {
2375 if (rss[fn].rss_ind_table[i] !=
2376 rss[fn].rss_ind_table[0])
2377 break;
2378 }
2379 if (i == QED_RSS_IND_TABLE_SIZE / cdev->num_hwfns) {
2380 DP_VERBOSE(cdev, NETIF_MSG_IFUP,
2381 "CMT - 1 queue per-hwfn; Disabling RSS\n");
2382 return -EINVAL;
2383 }
2384 rss[fn].rss_table_size_log = 6;
2385 }
2386
2387 return 0;
2388}
2389
cee4d264
MC		 2390static int qed_update_vport(struct qed_dev *cdev,
2391 struct qed_update_vport_params *params)
2392{
2393 struct qed_sp_vport_update_params sp_params;
f29ffdb6
MY		 2394 struct qed_rss_params *rss;
2395 int rc = 0, i;
cee4d264
MC		 2396
2397 if (!cdev)
2398 return -ENODEV;
2399
f29ffdb6
MY		 2400 rss = vzalloc(sizeof(*rss) * cdev->num_hwfns);
2401 if (!rss)
2402 return -ENOMEM;
2403
cee4d264 2404 memset(&sp_params, 0, sizeof(sp_params));
cee4d264
MC		 2405
2406 /* Translate protocol params into sp params */
2407 sp_params.vport_id = params->vport_id;
1a635e48
YM		 2408 sp_params.update_vport_active_rx_flg = params->update_vport_active_flg;
2409 sp_params.update_vport_active_tx_flg = params->update_vport_active_flg;
cee4d264
MC		 2410 sp_params.vport_active_rx_flg = params->vport_active_flg;
2411 sp_params.vport_active_tx_flg = params->vport_active_flg;
831bfb0e
YM		 2412 sp_params.update_tx_switching_flg = params->update_tx_switching_flg;
2413 sp_params.tx_switching_flg = params->tx_switching_flg;
3f9b4a69
YM		 2414 sp_params.accept_any_vlan = params->accept_any_vlan;
2415 sp_params.update_accept_any_vlan_flg =
2416 params->update_accept_any_vlan_flg;
cee4d264 2417
f29ffdb6
MY		 2418 /* Prepare the RSS configuration */
2419 if (params->update_rss_flg)
2420 if (qed_update_vport_rss(cdev, &params->rss_params, rss))
cee4d264 2421 params->update_rss_flg = 0;
cee4d264
MC		 2422
2423 for_each_hwfn(cdev, i) {
2424 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2425
f29ffdb6
MY		 2426 if (params->update_rss_flg)
2427 sp_params.rss_params = &rss[i];
2428
cee4d264
MC		 2429 sp_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2430 rc = qed_sp_vport_update(p_hwfn, &sp_params,
2431 QED_SPQ_MODE_EBLOCK,
2432 NULL);
2433 if (rc) {
2434 DP_ERR(cdev, "Failed to update VPORT\n");
f29ffdb6 2435 goto out;
cee4d264
MC		 2436 }
2437
2438 DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
2439 "Updated V-PORT %d: active_flag %d [update %d]\n",
2440 params->vport_id, params->vport_active_flg,
2441 params->update_vport_active_flg);
2442 }
2443
f29ffdb6
MY		 2444out:
2445 vfree(rss);
2446 return rc;
cee4d264
MC		 2447}
2448
2449static int qed_start_rxq(struct qed_dev *cdev,
3da7a37a
MY		 2450 u8 rss_num,
2451 struct qed_queue_start_common_params *p_params,
cee4d264
MC		 2452 u16 bd_max_bytes,
2453 dma_addr_t bd_chain_phys_addr,
2454 dma_addr_t cqe_pbl_addr,
2455 u16 cqe_pbl_size,
3da7a37a 2456 struct qed_rxq_start_ret_params *ret_params)
cee4d264 2457{
cee4d264 2458 struct qed_hwfn *p_hwfn;
1a635e48 2459 int rc, hwfn_index;
cee4d264 2460
3da7a37a 2461 hwfn_index = rss_num % cdev->num_hwfns;
cee4d264
MC		 2462 p_hwfn = &cdev->hwfns[hwfn_index];
2463
3da7a37a
MY		 2464 p_params->queue_id = p_params->queue_id / cdev->num_hwfns;
2465 p_params->stats_id = p_params->vport_id;
cee4d264 2466
3da7a37a
MY		 2467 rc = qed_eth_rx_queue_start(p_hwfn,
2468 p_hwfn->hw_info.opaque_fid,
2469 p_params,
2470 bd_max_bytes,
2471 bd_chain_phys_addr,
2472 cqe_pbl_addr, cqe_pbl_size, ret_params);
cee4d264 2473 if (rc) {
3da7a37a 2474 DP_ERR(cdev, "Failed to start RXQ#%d\n", p_params->queue_id);
cee4d264
MC		 2475 return rc;
2476 }
2477
2478 DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
f604b17d 2479 "Started RX-Q %d [rss_num %d] on V-PORT %d and SB igu %d\n",
3da7a37a 2480 p_params->queue_id, rss_num, p_params->vport_id,
f604b17d 2481 p_params->p_sb->igu_sb_id);
cee4d264
MC		 2482
2483 return 0;
2484}
2485
3da7a37a 2486static int qed_stop_rxq(struct qed_dev *cdev, u8 rss_id, void *handle)
cee4d264
MC		 2487{
2488 int rc, hwfn_index;
2489 struct qed_hwfn *p_hwfn;
2490
3da7a37a
MY		 2491 hwfn_index = rss_id % cdev->num_hwfns;
2492 p_hwfn = &cdev->hwfns[hwfn_index];
cee4d264 2493
3da7a37a 2494 rc = qed_eth_rx_queue_stop(p_hwfn, handle, false, false);
cee4d264 2495 if (rc) {
3da7a37a 2496 DP_ERR(cdev, "Failed to stop RXQ#%02x\n", rss_id);
cee4d264
MC		 2497 return rc;
2498 }
2499
2500 return 0;
2501}
2502
2503static int qed_start_txq(struct qed_dev *cdev,
3da7a37a 2504 u8 rss_num,
cee4d264
MC		 2505 struct qed_queue_start_common_params *p_params,
2506 dma_addr_t pbl_addr,
2507 u16 pbl_size,
3da7a37a 2508 struct qed_txq_start_ret_params *ret_params)
cee4d264
MC		 2509{
2510 struct qed_hwfn *p_hwfn;
2511 int rc, hwfn_index;
2512
3da7a37a
MY		 2513 hwfn_index = rss_num % cdev->num_hwfns;
2514 p_hwfn = &cdev->hwfns[hwfn_index];
2515 p_params->queue_id = p_params->queue_id / cdev->num_hwfns;
2516 p_params->stats_id = p_params->vport_id;
cee4d264 2517
3da7a37a
MY		 2518 rc = qed_eth_tx_queue_start(p_hwfn,
2519 p_hwfn->hw_info.opaque_fid,
2520 p_params, 0,
2521 pbl_addr, pbl_size, ret_params);
cee4d264
MC		 2522
2523 if (rc) {
2524 DP_ERR(cdev, "Failed to start TXQ#%d\n", p_params->queue_id);
2525 return rc;
2526 }
2527
2528 DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
f604b17d 2529 "Started TX-Q %d [rss_num %d] on V-PORT %d and SB igu %d\n",
3da7a37a 2530 p_params->queue_id, rss_num, p_params->vport_id,
f604b17d 2531 p_params->p_sb->igu_sb_id);
cee4d264
MC		 2532
2533 return 0;
2534}
2535
2536#define QED_HW_STOP_RETRY_LIMIT (10)
2537static int qed_fastpath_stop(struct qed_dev *cdev)
2538{
15582962
RV		 2539 int rc;
2540
2541 rc = qed_hw_stop_fastpath(cdev);
2542 if (rc) {
2543 DP_ERR(cdev, "Failed to stop Fastpath\n");
2544 return rc;
2545 }
cee4d264
MC		 2546
2547 return 0;
2548}
2549
3da7a37a 2550static int qed_stop_txq(struct qed_dev *cdev, u8 rss_id, void *handle)
cee4d264
MC		 2551{
2552 struct qed_hwfn *p_hwfn;
2553 int rc, hwfn_index;
2554
3da7a37a
MY		 2555 hwfn_index = rss_id % cdev->num_hwfns;
2556 p_hwfn = &cdev->hwfns[hwfn_index];
cee4d264 2557
3da7a37a 2558 rc = qed_eth_tx_queue_stop(p_hwfn, handle);
cee4d264 2559 if (rc) {
3da7a37a 2560 DP_ERR(cdev, "Failed to stop TXQ#%02x\n", rss_id);
cee4d264
MC		 2561 return rc;
2562 }
2563
2564 return 0;
2565}
2566
464f6645
MC		 2567static int qed_tunn_configure(struct qed_dev *cdev,
2568 struct qed_tunn_params *tunn_params)
2569{
19968430 2570 struct qed_tunnel_info tunn_info;
464f6645
MC		 2571 int i, rc;
2572
2573 memset(&tunn_info, 0, sizeof(tunn_info));
19968430
CM		 2574 if (tunn_params->update_vxlan_port) {
2575 tunn_info.vxlan_port.b_update_port = true;
2576 tunn_info.vxlan_port.port = tunn_params->vxlan_port;
464f6645
MC		 2577 }
2578
19968430
CM		 2579 if (tunn_params->update_geneve_port) {
2580 tunn_info.geneve_port.b_update_port = true;
2581 tunn_info.geneve_port.port = tunn_params->geneve_port;
464f6645
MC		 2582 }
2583
2584 for_each_hwfn(cdev, i) {
2585 struct qed_hwfn *hwfn = &cdev->hwfns[i];
4f64675f 2586 struct qed_ptt *p_ptt;
97379f15
CM		 2587 struct qed_tunnel_info *tun;
2588
2589 tun = &hwfn->cdev->tunnel;
4f64675f
MC		 2590 if (IS_PF(cdev)) {
2591 p_ptt = qed_ptt_acquire(hwfn);
2592 if (!p_ptt)
2593 return -EAGAIN;
2594 } else {
2595 p_ptt = NULL;
2596 }
464f6645 2597
4f64675f 2598 rc = qed_sp_pf_update_tunn_cfg(hwfn, p_ptt, &tunn_info,
464f6645 2599 QED_SPQ_MODE_EBLOCK, NULL);
4f64675f
MC		 2600 if (rc) {
2601 if (IS_PF(cdev))
2602 qed_ptt_release(hwfn, p_ptt);
464f6645 2603 return rc;
4f64675f 2604 }
97379f15
CM		 2605
2606 if (IS_PF_SRIOV(hwfn)) {
2607 u16 vxlan_port, geneve_port;
2608 int j;
2609
2610 vxlan_port = tun->vxlan_port.port;
2611 geneve_port = tun->geneve_port.port;
2612
2613 qed_for_each_vf(hwfn, j) {
2614 qed_iov_bulletin_set_udp_ports(hwfn, j,
2615 vxlan_port,
2616 geneve_port);
2617 }
2618
2619 qed_schedule_iov(hwfn, QED_IOV_WQ_BULLETIN_UPDATE_FLAG);
2620 }
4f64675f
MC		 2621 if (IS_PF(cdev))
2622 qed_ptt_release(hwfn, p_ptt);
464f6645
MC		 2623 }
2624
2625 return 0;
2626}
2627
cee4d264
MC		 2628static int qed_configure_filter_rx_mode(struct qed_dev *cdev,
2629 enum qed_filter_rx_mode_type type)
2630{
2631 struct qed_filter_accept_flags accept_flags;
2632
2633 memset(&accept_flags, 0, sizeof(accept_flags));
2634
1a635e48
YM		 2635 accept_flags.update_rx_mode_config = 1;
2636 accept_flags.update_tx_mode_config = 1;
2637 accept_flags.rx_accept_filter = QED_ACCEPT_UCAST_MATCHED |
2638 QED_ACCEPT_MCAST_MATCHED |
2639 QED_ACCEPT_BCAST;
cee4d264
MC		 2640 accept_flags.tx_accept_filter = QED_ACCEPT_UCAST_MATCHED |
2641 QED_ACCEPT_MCAST_MATCHED |
2642 QED_ACCEPT_BCAST;
2643
88067876 2644 if (type == QED_FILTER_RX_MODE_TYPE_PROMISC) {
cee4d264
MC		 2645 accept_flags.rx_accept_filter |= QED_ACCEPT_UCAST_UNMATCHED |
2646 QED_ACCEPT_MCAST_UNMATCHED;
1c4f6fa2
MC		 2647 accept_flags.tx_accept_filter |= QED_ACCEPT_UCAST_UNMATCHED |
2648 QED_ACCEPT_MCAST_UNMATCHED;
88067876 2649 } else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC) {
cee4d264 2650 accept_flags.rx_accept_filter |= QED_ACCEPT_MCAST_UNMATCHED;
88067876
MY		 2651 accept_flags.tx_accept_filter |= QED_ACCEPT_MCAST_UNMATCHED;
2652 }
cee4d264 2653
3f9b4a69 2654 return qed_filter_accept_cmd(cdev, 0, accept_flags, false, false,
cee4d264
MC		 2655 QED_SPQ_MODE_CB, NULL);
2656}
2657
2658static int qed_configure_filter_ucast(struct qed_dev *cdev,
2659 struct qed_filter_ucast_params *params)
2660{
2661 struct qed_filter_ucast ucast;
2662
2663 if (!params->vlan_valid && !params->mac_valid) {
1a635e48
YM		 2664 DP_NOTICE(cdev,
2665 "Tried configuring a unicast filter, but both MAC and VLAN are not set\n");
cee4d264
MC		 2666 return -EINVAL;
2667 }
2668
2669 memset(&ucast, 0, sizeof(ucast));
2670 switch (params->type) {
2671 case QED_FILTER_XCAST_TYPE_ADD:
2672 ucast.opcode = QED_FILTER_ADD;
2673 break;
2674 case QED_FILTER_XCAST_TYPE_DEL:
2675 ucast.opcode = QED_FILTER_REMOVE;
2676 break;
2677 case QED_FILTER_XCAST_TYPE_REPLACE:
2678 ucast.opcode = QED_FILTER_REPLACE;
2679 break;
2680 default:
2681 DP_NOTICE(cdev, "Unknown unicast filter type %d\n",
2682 params->type);
2683 }
2684
2685 if (params->vlan_valid && params->mac_valid) {
2686 ucast.type = QED_FILTER_MAC_VLAN;
2687 ether_addr_copy(ucast.mac, params->mac);
2688 ucast.vlan = params->vlan;
2689 } else if (params->mac_valid) {
2690 ucast.type = QED_FILTER_MAC;
2691 ether_addr_copy(ucast.mac, params->mac);
2692 } else {
2693 ucast.type = QED_FILTER_VLAN;
2694 ucast.vlan = params->vlan;
2695 }
2696
2697 ucast.is_rx_filter = true;
2698 ucast.is_tx_filter = true;
2699
2700 return qed_filter_ucast_cmd(cdev, &ucast, QED_SPQ_MODE_CB, NULL);
2701}
2702
2703static int qed_configure_filter_mcast(struct qed_dev *cdev,
2704 struct qed_filter_mcast_params *params)
2705{
2706 struct qed_filter_mcast mcast;
2707 int i;
2708
2709 memset(&mcast, 0, sizeof(mcast));
2710 switch (params->type) {
2711 case QED_FILTER_XCAST_TYPE_ADD:
2712 mcast.opcode = QED_FILTER_ADD;
2713 break;
2714 case QED_FILTER_XCAST_TYPE_DEL:
2715 mcast.opcode = QED_FILTER_REMOVE;
2716 break;
2717 default:
2718 DP_NOTICE(cdev, "Unknown multicast filter type %d\n",
2719 params->type);
2720 }
2721
2722 mcast.num_mc_addrs = params->num;
2723 for (i = 0; i < mcast.num_mc_addrs; i++)
2724 ether_addr_copy(mcast.mac[i], params->mac[i]);
2725
1a635e48 2726 return qed_filter_mcast_cmd(cdev, &mcast, QED_SPQ_MODE_CB, NULL);
cee4d264
MC		 2727}
2728
2729static int qed_configure_filter(struct qed_dev *cdev,
2730 struct qed_filter_params *params)
2731{
2732 enum qed_filter_rx_mode_type accept_flags;
2733
2734 switch (params->type) {
2735 case QED_FILTER_TYPE_UCAST:
2736 return qed_configure_filter_ucast(cdev, &params->filter.ucast);
2737 case QED_FILTER_TYPE_MCAST:
2738 return qed_configure_filter_mcast(cdev, &params->filter.mcast);
2739 case QED_FILTER_TYPE_RX_MODE:
2740 accept_flags = params->filter.accept_flags;
2741 return qed_configure_filter_rx_mode(cdev, accept_flags);
2742 default:
1a635e48 2743 DP_NOTICE(cdev, "Unknown filter type %d\n", (int)params->type);
cee4d264
MC		 2744 return -EINVAL;
2745 }
2746}
2747
d51e4af5
CM		 2748static int qed_configure_arfs_searcher(struct qed_dev *cdev, bool en_searcher)
2749{
2750 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
2751 struct qed_arfs_config_params arfs_config_params;
2752
2753 memset(&arfs_config_params, 0, sizeof(arfs_config_params));
2754 arfs_config_params.tcp = true;
2755 arfs_config_params.udp = true;
2756 arfs_config_params.ipv4 = true;
2757 arfs_config_params.ipv6 = true;
2758 arfs_config_params.arfs_enable = en_searcher;
2759
2760 qed_arfs_mode_configure(p_hwfn, p_hwfn->p_arfs_ptt,
2761 &arfs_config_params);
2762 return 0;
2763}
2764
2765static void
2766qed_arfs_sp_response_handler(struct qed_hwfn *p_hwfn,
2767 void *cookie, union event_ring_data *data,
2768 u8 fw_return_code)
2769{
2770 struct qed_common_cb_ops *op = p_hwfn->cdev->protocol_ops.common;
2771 void *dev = p_hwfn->cdev->ops_cookie;
2772
2773 op->arfs_filter_op(dev, cookie, fw_return_code);
2774}
2775
2776static int qed_ntuple_arfs_filter_config(struct qed_dev *cdev, void *cookie,
2777 dma_addr_t mapping, u16 length,
2778 u16 vport_id, u16 rx_queue_id,
2779 bool add_filter)
2780{
2781 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
2782 struct qed_spq_comp_cb cb;
2783 int rc = -EINVAL;
2784
2785 cb.function = qed_arfs_sp_response_handler;
2786 cb.cookie = cookie;
2787
2788 rc = qed_configure_rfs_ntuple_filter(p_hwfn, p_hwfn->p_arfs_ptt,
2789 &cb, mapping, length, rx_queue_id,
2790 vport_id, add_filter);
2791 if (rc)
2792 DP_NOTICE(p_hwfn,
2793 "Failed to issue a-RFS filter configuration\n");
2794 else
2795 DP_VERBOSE(p_hwfn, NETIF_MSG_DRV,
2796 "Successfully issued a-RFS filter configuration\n");
2797
2798 return rc;
2799}
2800
bf5a94bf
RV		 2801static int qed_get_coalesce(struct qed_dev *cdev, u16 *coal, void *handle)
2802{
2803 struct qed_queue_cid *p_cid = handle;
2804 struct qed_hwfn *p_hwfn;
2805 int rc;
2806
2807 p_hwfn = p_cid->p_owner;
2808 rc = qed_get_queue_coalesce(p_hwfn, coal, handle);
2809 if (rc)
9e4a5613 2810 DP_NOTICE(p_hwfn, "Unable to read queue coalescing\n");
bf5a94bf
RV		 2811
2812 return rc;
2813}
2814
cee4d264 2815static int qed_fp_cqe_completion(struct qed_dev *dev,
1a635e48 2816 u8 rss_id, struct eth_slow_path_rx_cqe *cqe)
cee4d264
MC		 2817{
2818 return qed_eth_cqe_completion(&dev->hwfns[rss_id % dev->num_hwfns],
2819 cqe);
2820}
2821
0b55e27d
YM		 2822#ifdef CONFIG_QED_SRIOV
2823extern const struct qed_iov_hv_ops qed_iov_ops_pass;
2824#endif
2825
a1d8d8a5
SRK		 2826#ifdef CONFIG_DCB
2827extern const struct qed_eth_dcbnl_ops qed_dcbnl_ops_pass;
2828#endif
2829
c78c70fa
SRK		 2830extern const struct qed_eth_ptp_ops qed_ptp_ops_pass;
2831
25c089d7
YM		 2832static const struct qed_eth_ops qed_eth_ops_pass = {
2833 .common = &qed_common_ops_pass,
0b55e27d
YM		 2834#ifdef CONFIG_QED_SRIOV
2835 .iov = &qed_iov_ops_pass,
a1d8d8a5
SRK		 2836#endif
2837#ifdef CONFIG_DCB
2838 .dcb = &qed_dcbnl_ops_pass,
0b55e27d 2839#endif
c78c70fa 2840 .ptp = &qed_ptp_ops_pass,
25c089d7 2841 .fill_dev_info = &qed_fill_eth_dev_info,
cc875c2e 2842 .register_ops = &qed_register_eth_ops,
eff16960 2843 .check_mac = &qed_check_mac,
cee4d264
MC		 2844 .vport_start = &qed_start_vport,
2845 .vport_stop = &qed_stop_vport,
2846 .vport_update = &qed_update_vport,
2847 .q_rx_start = &qed_start_rxq,
2848 .q_rx_stop = &qed_stop_rxq,
2849 .q_tx_start = &qed_start_txq,
2850 .q_tx_stop = &qed_stop_txq,
2851 .filter_config = &qed_configure_filter,
2852 .fastpath_stop = &qed_fastpath_stop,
2853 .eth_cqe_completion = &qed_fp_cqe_completion,
9df2ed04 2854 .get_vport_stats = &qed_get_vport_stats,
464f6645 2855 .tunn_config = &qed_tunn_configure,
d51e4af5
CM		 2856 .ntuple_filter_config = &qed_ntuple_arfs_filter_config,
2857 .configure_arfs_searcher = &qed_configure_arfs_searcher,
bf5a94bf 2858 .get_coalesce = &qed_get_coalesce,
25c089d7
YM		 2859};
2860
95114344 2861const struct qed_eth_ops *qed_get_eth_ops(void)
25c089d7 2862{
25c089d7
YM		 2863 return &qed_eth_ops_pass;
2864}
2865EXPORT_SYMBOL(qed_get_eth_ops);
2866
2867void qed_put_eth_ops(void)
2868{
2869 /* TODO - reference count for module? */
2870}
2871EXPORT_SYMBOL(qed_put_eth_ops);
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