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25c089d7 | 1 | /* QLogic qed NIC Driver |
e8f1cb50 | 2 | * Copyright (c) 2015-2017 QLogic Corporation |
25c089d7 | 3 | * |
e8f1cb50 MY |
4 | * This software is available to you under a choice of one of two |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and /or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
25c089d7 YM |
31 | */ |
32 | ||
33 | #include <linux/types.h> | |
34 | #include <asm/byteorder.h> | |
35 | #include <asm/param.h> | |
36 | #include <linux/delay.h> | |
37 | #include <linux/dma-mapping.h> | |
38 | #include <linux/etherdevice.h> | |
39 | #include <linux/interrupt.h> | |
40 | #include <linux/kernel.h> | |
41 | #include <linux/module.h> | |
42 | #include <linux/pci.h> | |
43 | #include <linux/slab.h> | |
44 | #include <linux/stddef.h> | |
45 | #include <linux/string.h> | |
25c089d7 YM |
46 | #include <linux/workqueue.h> |
47 | #include <linux/bitops.h> | |
48 | #include <linux/bug.h> | |
3da7a37a | 49 | #include <linux/vmalloc.h> |
25c089d7 YM |
50 | #include "qed.h" |
51 | #include <linux/qed/qed_chain.h> | |
52 | #include "qed_cxt.h" | |
53 | #include "qed_dev_api.h" | |
54 | #include <linux/qed/qed_eth_if.h> | |
55 | #include "qed_hsi.h" | |
56 | #include "qed_hw.h" | |
57 | #include "qed_int.h" | |
dacd88d6 | 58 | #include "qed_l2.h" |
86622ee7 | 59 | #include "qed_mcp.h" |
25c089d7 YM |
60 | #include "qed_reg_addr.h" |
61 | #include "qed_sp.h" | |
1408cc1f | 62 | #include "qed_sriov.h" |
25c089d7 | 63 | |
088c8618 | 64 | |
cee4d264 MC |
65 | #define QED_MAX_SGES_NUM 16 |
66 | #define CRC32_POLY 0x1edc6f41 | |
67 | ||
0db711bb MY |
68 | struct qed_l2_info { |
69 | u32 queues; | |
70 | unsigned long **pp_qid_usage; | |
71 | ||
72 | /* The lock is meant to synchronize access to the qid usage */ | |
73 | struct mutex lock; | |
74 | }; | |
75 | ||
76 | int qed_l2_alloc(struct qed_hwfn *p_hwfn) | |
77 | { | |
78 | struct qed_l2_info *p_l2_info; | |
79 | unsigned long **pp_qids; | |
80 | u32 i; | |
81 | ||
c851a9dc | 82 | if (!QED_IS_L2_PERSONALITY(p_hwfn)) |
0db711bb MY |
83 | return 0; |
84 | ||
85 | p_l2_info = kzalloc(sizeof(*p_l2_info), GFP_KERNEL); | |
86 | if (!p_l2_info) | |
87 | return -ENOMEM; | |
88 | p_hwfn->p_l2_info = p_l2_info; | |
89 | ||
90 | if (IS_PF(p_hwfn->cdev)) { | |
91 | p_l2_info->queues = RESC_NUM(p_hwfn, QED_L2_QUEUE); | |
92 | } else { | |
93 | u8 rx = 0, tx = 0; | |
94 | ||
95 | qed_vf_get_num_rxqs(p_hwfn, &rx); | |
96 | qed_vf_get_num_txqs(p_hwfn, &tx); | |
97 | ||
98 | p_l2_info->queues = max_t(u8, rx, tx); | |
99 | } | |
100 | ||
6396bb22 | 101 | pp_qids = kcalloc(p_l2_info->queues, sizeof(unsigned long *), |
0db711bb MY |
102 | GFP_KERNEL); |
103 | if (!pp_qids) | |
104 | return -ENOMEM; | |
105 | p_l2_info->pp_qid_usage = pp_qids; | |
106 | ||
107 | for (i = 0; i < p_l2_info->queues; i++) { | |
108 | pp_qids[i] = kzalloc(MAX_QUEUES_PER_QZONE / 8, GFP_KERNEL); | |
109 | if (!pp_qids[i]) | |
110 | return -ENOMEM; | |
111 | } | |
112 | ||
113 | return 0; | |
114 | } | |
115 | ||
116 | void qed_l2_setup(struct qed_hwfn *p_hwfn) | |
117 | { | |
af6858ee | 118 | if (!QED_IS_L2_PERSONALITY(p_hwfn)) |
0db711bb MY |
119 | return; |
120 | ||
121 | mutex_init(&p_hwfn->p_l2_info->lock); | |
122 | } | |
123 | ||
124 | void qed_l2_free(struct qed_hwfn *p_hwfn) | |
125 | { | |
126 | u32 i; | |
127 | ||
af6858ee | 128 | if (!QED_IS_L2_PERSONALITY(p_hwfn)) |
0db711bb MY |
129 | return; |
130 | ||
131 | if (!p_hwfn->p_l2_info) | |
132 | return; | |
133 | ||
134 | if (!p_hwfn->p_l2_info->pp_qid_usage) | |
135 | goto out_l2_info; | |
136 | ||
137 | /* Free until hit first uninitialized entry */ | |
138 | for (i = 0; i < p_hwfn->p_l2_info->queues; i++) { | |
139 | if (!p_hwfn->p_l2_info->pp_qid_usage[i]) | |
140 | break; | |
141 | kfree(p_hwfn->p_l2_info->pp_qid_usage[i]); | |
142 | } | |
143 | ||
144 | kfree(p_hwfn->p_l2_info->pp_qid_usage); | |
145 | ||
146 | out_l2_info: | |
147 | kfree(p_hwfn->p_l2_info); | |
148 | p_hwfn->p_l2_info = NULL; | |
149 | } | |
150 | ||
bbe3f233 MY |
151 | static bool qed_eth_queue_qid_usage_add(struct qed_hwfn *p_hwfn, |
152 | struct qed_queue_cid *p_cid) | |
153 | { | |
154 | struct qed_l2_info *p_l2_info = p_hwfn->p_l2_info; | |
155 | u16 queue_id = p_cid->rel.queue_id; | |
156 | bool b_rc = true; | |
157 | u8 first; | |
158 | ||
159 | mutex_lock(&p_l2_info->lock); | |
160 | ||
0331402a | 161 | if (queue_id >= p_l2_info->queues) { |
bbe3f233 MY |
162 | DP_NOTICE(p_hwfn, |
163 | "Requested to increase usage for qzone %04x out of %08x\n", | |
164 | queue_id, p_l2_info->queues); | |
165 | b_rc = false; | |
166 | goto out; | |
167 | } | |
168 | ||
169 | first = (u8)find_first_zero_bit(p_l2_info->pp_qid_usage[queue_id], | |
170 | MAX_QUEUES_PER_QZONE); | |
171 | if (first >= MAX_QUEUES_PER_QZONE) { | |
172 | b_rc = false; | |
173 | goto out; | |
174 | } | |
175 | ||
176 | __set_bit(first, p_l2_info->pp_qid_usage[queue_id]); | |
177 | p_cid->qid_usage_idx = first; | |
178 | ||
179 | out: | |
180 | mutex_unlock(&p_l2_info->lock); | |
181 | return b_rc; | |
182 | } | |
183 | ||
184 | static void qed_eth_queue_qid_usage_del(struct qed_hwfn *p_hwfn, | |
185 | struct qed_queue_cid *p_cid) | |
186 | { | |
187 | mutex_lock(&p_hwfn->p_l2_info->lock); | |
188 | ||
189 | clear_bit(p_cid->qid_usage_idx, | |
190 | p_hwfn->p_l2_info->pp_qid_usage[p_cid->rel.queue_id]); | |
191 | ||
192 | mutex_unlock(&p_hwfn->p_l2_info->lock); | |
193 | } | |
194 | ||
3da7a37a MY |
195 | void qed_eth_queue_cid_release(struct qed_hwfn *p_hwfn, |
196 | struct qed_queue_cid *p_cid) | |
197 | { | |
08bc8f15 MY |
198 | bool b_legacy_vf = !!(p_cid->vf_legacy & QED_QCID_LEGACY_VF_CID); |
199 | ||
200 | if (IS_PF(p_hwfn->cdev) && !b_legacy_vf) | |
201 | _qed_cxt_release_cid(p_hwfn, p_cid->cid, p_cid->vfid); | |
bbe3f233 MY |
202 | |
203 | /* For PF's VFs we maintain the index inside queue-zone in IOV */ | |
204 | if (p_cid->vfid == QED_QUEUE_CID_SELF) | |
205 | qed_eth_queue_qid_usage_del(p_hwfn, p_cid); | |
206 | ||
3da7a37a MY |
207 | vfree(p_cid); |
208 | } | |
209 | ||
210 | /* The internal is only meant to be directly called by PFs initializeing CIDs | |
211 | * for their VFs. | |
212 | */ | |
3946497a | 213 | static struct qed_queue_cid * |
3da7a37a MY |
214 | _qed_eth_queue_to_cid(struct qed_hwfn *p_hwfn, |
215 | u16 opaque_fid, | |
216 | u32 cid, | |
3946497a | 217 | struct qed_queue_start_common_params *p_params, |
007bc371 | 218 | bool b_is_rx, |
3946497a | 219 | struct qed_queue_cid_vf_params *p_vf_params) |
3da7a37a | 220 | { |
3da7a37a MY |
221 | struct qed_queue_cid *p_cid; |
222 | int rc; | |
223 | ||
5f58dff9 | 224 | p_cid = vzalloc(sizeof(*p_cid)); |
3da7a37a MY |
225 | if (!p_cid) |
226 | return NULL; | |
3da7a37a MY |
227 | |
228 | p_cid->opaque_fid = opaque_fid; | |
229 | p_cid->cid = cid; | |
f29ffdb6 | 230 | p_cid->p_owner = p_hwfn; |
3da7a37a | 231 | |
f604b17d MY |
232 | /* Fill in parameters */ |
233 | p_cid->rel.vport_id = p_params->vport_id; | |
234 | p_cid->rel.queue_id = p_params->queue_id; | |
235 | p_cid->rel.stats_id = p_params->stats_id; | |
236 | p_cid->sb_igu_id = p_params->p_sb->igu_sb_id; | |
007bc371 | 237 | p_cid->b_is_rx = b_is_rx; |
f604b17d MY |
238 | p_cid->sb_idx = p_params->sb_idx; |
239 | ||
3946497a MY |
240 | /* Fill-in bits related to VFs' queues if information was provided */ |
241 | if (p_vf_params) { | |
242 | p_cid->vfid = p_vf_params->vfid; | |
243 | p_cid->vf_qid = p_vf_params->vf_qid; | |
3b19f478 | 244 | p_cid->vf_legacy = p_vf_params->vf_legacy; |
3946497a MY |
245 | } else { |
246 | p_cid->vfid = QED_QUEUE_CID_SELF; | |
247 | } | |
248 | ||
3da7a37a MY |
249 | /* Don't try calculating the absolute indices for VFs */ |
250 | if (IS_VF(p_hwfn->cdev)) { | |
251 | p_cid->abs = p_cid->rel; | |
252 | goto out; | |
253 | } | |
254 | ||
255 | /* Calculate the engine-absolute indices of the resources. | |
256 | * This would guarantee they're valid later on. | |
257 | * In some cases [SBs] we already have the right values. | |
258 | */ | |
259 | rc = qed_fw_vport(p_hwfn, p_cid->rel.vport_id, &p_cid->abs.vport_id); | |
260 | if (rc) | |
261 | goto fail; | |
262 | ||
263 | rc = qed_fw_l2_queue(p_hwfn, p_cid->rel.queue_id, &p_cid->abs.queue_id); | |
264 | if (rc) | |
265 | goto fail; | |
266 | ||
267 | /* In case of a PF configuring its VF's queues, the stats-id is already | |
268 | * absolute [since there's a single index that's suitable per-VF]. | |
269 | */ | |
3946497a | 270 | if (p_cid->vfid == QED_QUEUE_CID_SELF) { |
3da7a37a MY |
271 | rc = qed_fw_vport(p_hwfn, p_cid->rel.stats_id, |
272 | &p_cid->abs.stats_id); | |
273 | if (rc) | |
274 | goto fail; | |
275 | } else { | |
276 | p_cid->abs.stats_id = p_cid->rel.stats_id; | |
277 | } | |
278 | ||
3da7a37a | 279 | out: |
bbe3f233 MY |
280 | /* VF-images have provided the qid_usage_idx on their own. |
281 | * Otherwise, we need to allocate a unique one. | |
282 | */ | |
283 | if (!p_vf_params) { | |
284 | if (!qed_eth_queue_qid_usage_add(p_hwfn, p_cid)) | |
285 | goto fail; | |
286 | } else { | |
287 | p_cid->qid_usage_idx = p_vf_params->qid_usage_idx; | |
288 | } | |
289 | ||
3da7a37a MY |
290 | DP_VERBOSE(p_hwfn, |
291 | QED_MSG_SP, | |
bbe3f233 | 292 | "opaque_fid: %04x CID %08x vport %02x [%02x] qzone %04x.%02x [%04x] stats %02x [%02x] SB %04x PI %02x\n", |
3da7a37a MY |
293 | p_cid->opaque_fid, |
294 | p_cid->cid, | |
295 | p_cid->rel.vport_id, | |
296 | p_cid->abs.vport_id, | |
297 | p_cid->rel.queue_id, | |
bbe3f233 | 298 | p_cid->qid_usage_idx, |
3da7a37a MY |
299 | p_cid->abs.queue_id, |
300 | p_cid->rel.stats_id, | |
f604b17d | 301 | p_cid->abs.stats_id, p_cid->sb_igu_id, p_cid->sb_idx); |
3da7a37a MY |
302 | |
303 | return p_cid; | |
304 | ||
305 | fail: | |
306 | vfree(p_cid); | |
307 | return NULL; | |
308 | } | |
309 | ||
3946497a MY |
310 | struct qed_queue_cid * |
311 | qed_eth_queue_to_cid(struct qed_hwfn *p_hwfn, | |
312 | u16 opaque_fid, | |
313 | struct qed_queue_start_common_params *p_params, | |
007bc371 | 314 | bool b_is_rx, |
3946497a | 315 | struct qed_queue_cid_vf_params *p_vf_params) |
3da7a37a MY |
316 | { |
317 | struct qed_queue_cid *p_cid; | |
08bc8f15 | 318 | u8 vfid = QED_CXT_PF_CID; |
3946497a | 319 | bool b_legacy_vf = false; |
3da7a37a MY |
320 | u32 cid = 0; |
321 | ||
08bc8f15 MY |
322 | /* In case of legacy VFs, The CID can be derived from the additional |
323 | * VF parameters - the VF assumes queue X uses CID X, so we can simply | |
324 | * use the vf_qid for this purpose as well. | |
325 | */ | |
326 | if (p_vf_params) { | |
327 | vfid = p_vf_params->vfid; | |
328 | ||
329 | if (p_vf_params->vf_legacy & QED_QCID_LEGACY_VF_CID) { | |
330 | b_legacy_vf = true; | |
331 | cid = p_vf_params->vf_qid; | |
332 | } | |
333 | } | |
334 | ||
3da7a37a MY |
335 | /* Get a unique firmware CID for this queue, in case it's a PF. |
336 | * VF's don't need a CID as the queue configuration will be done | |
337 | * by PF. | |
338 | */ | |
3946497a | 339 | if (IS_PF(p_hwfn->cdev) && !b_legacy_vf) { |
08bc8f15 MY |
340 | if (_qed_cxt_acquire_cid(p_hwfn, PROTOCOLID_ETH, |
341 | &cid, vfid)) { | |
3da7a37a MY |
342 | DP_NOTICE(p_hwfn, "Failed to acquire cid\n"); |
343 | return NULL; | |
344 | } | |
345 | } | |
346 | ||
3946497a | 347 | p_cid = _qed_eth_queue_to_cid(p_hwfn, opaque_fid, cid, |
007bc371 | 348 | p_params, b_is_rx, p_vf_params); |
3946497a | 349 | if (!p_cid && IS_PF(p_hwfn->cdev) && !b_legacy_vf) |
08bc8f15 | 350 | _qed_cxt_release_cid(p_hwfn, cid, vfid); |
3da7a37a MY |
351 | |
352 | return p_cid; | |
353 | } | |
354 | ||
3946497a MY |
355 | static struct qed_queue_cid * |
356 | qed_eth_queue_to_cid_pf(struct qed_hwfn *p_hwfn, | |
357 | u16 opaque_fid, | |
007bc371 | 358 | bool b_is_rx, |
3946497a MY |
359 | struct qed_queue_start_common_params *p_params) |
360 | { | |
007bc371 | 361 | return qed_eth_queue_to_cid(p_hwfn, opaque_fid, p_params, b_is_rx, |
3946497a MY |
362 | NULL); |
363 | } | |
364 | ||
dacd88d6 YM |
365 | int qed_sp_eth_vport_start(struct qed_hwfn *p_hwfn, |
366 | struct qed_sp_vport_start_params *p_params) | |
cee4d264 | 367 | { |
cee4d264 MC |
368 | struct vport_start_ramrod_data *p_ramrod = NULL; |
369 | struct qed_spq_entry *p_ent = NULL; | |
06f56b81 | 370 | struct qed_sp_init_data init_data; |
dacd88d6 | 371 | u8 abs_vport_id = 0; |
cee4d264 MC |
372 | int rc = -EINVAL; |
373 | u16 rx_mode = 0; | |
cee4d264 | 374 | |
088c8618 | 375 | rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id); |
1a635e48 | 376 | if (rc) |
cee4d264 MC |
377 | return rc; |
378 | ||
06f56b81 YM |
379 | memset(&init_data, 0, sizeof(init_data)); |
380 | init_data.cid = qed_spq_get_cid(p_hwfn); | |
088c8618 | 381 | init_data.opaque_fid = p_params->opaque_fid; |
06f56b81 | 382 | init_data.comp_mode = QED_SPQ_MODE_EBLOCK; |
cee4d264 MC |
383 | |
384 | rc = qed_sp_init_request(p_hwfn, &p_ent, | |
cee4d264 | 385 | ETH_RAMROD_VPORT_START, |
06f56b81 | 386 | PROTOCOLID_ETH, &init_data); |
cee4d264 MC |
387 | if (rc) |
388 | return rc; | |
389 | ||
390 | p_ramrod = &p_ent->ramrod.vport_start; | |
391 | p_ramrod->vport_id = abs_vport_id; | |
392 | ||
088c8618 | 393 | p_ramrod->mtu = cpu_to_le16(p_params->mtu); |
c78c70fa | 394 | p_ramrod->handle_ptp_pkts = p_params->handle_ptp_pkts; |
088c8618 MC |
395 | p_ramrod->inner_vlan_removal_en = p_params->remove_inner_vlan; |
396 | p_ramrod->drop_ttl0_en = p_params->drop_ttl0; | |
e6bd8923 | 397 | p_ramrod->untagged = p_params->only_untagged; |
cee4d264 MC |
398 | |
399 | SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_UCAST_DROP_ALL, 1); | |
400 | SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_MCAST_DROP_ALL, 1); | |
401 | ||
402 | p_ramrod->rx_mode.state = cpu_to_le16(rx_mode); | |
403 | ||
404 | /* TPA related fields */ | |
1a635e48 | 405 | memset(&p_ramrod->tpa_param, 0, sizeof(struct eth_vport_tpa_param)); |
cee4d264 | 406 | |
088c8618 MC |
407 | p_ramrod->tpa_param.max_buff_num = p_params->max_buffers_per_cqe; |
408 | ||
409 | switch (p_params->tpa_mode) { | |
410 | case QED_TPA_MODE_GRO: | |
411 | p_ramrod->tpa_param.tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM; | |
412 | p_ramrod->tpa_param.tpa_max_size = (u16)-1; | |
413 | p_ramrod->tpa_param.tpa_min_size_to_cont = p_params->mtu / 2; | |
414 | p_ramrod->tpa_param.tpa_min_size_to_start = p_params->mtu / 2; | |
415 | p_ramrod->tpa_param.tpa_ipv4_en_flg = 1; | |
416 | p_ramrod->tpa_param.tpa_ipv6_en_flg = 1; | |
417 | p_ramrod->tpa_param.tpa_pkt_split_flg = 1; | |
418 | p_ramrod->tpa_param.tpa_gro_consistent_flg = 1; | |
419 | break; | |
420 | default: | |
421 | break; | |
422 | } | |
423 | ||
831bfb0e YM |
424 | p_ramrod->tx_switching_en = p_params->tx_switching; |
425 | ||
11a85d75 YM |
426 | p_ramrod->ctl_frame_mac_check_en = !!p_params->check_mac; |
427 | p_ramrod->ctl_frame_ethtype_check_en = !!p_params->check_ethtype; | |
428 | ||
cee4d264 MC |
429 | /* Software Function ID in hwfn (PFs are 0 - 15, VFs are 16 - 135) */ |
430 | p_ramrod->sw_fid = qed_concrete_to_sw_fid(p_hwfn->cdev, | |
088c8618 | 431 | p_params->concrete_fid); |
cee4d264 MC |
432 | |
433 | return qed_spq_post(p_hwfn, p_ent, NULL); | |
434 | } | |
435 | ||
ba56947a BX |
436 | static int qed_sp_vport_start(struct qed_hwfn *p_hwfn, |
437 | struct qed_sp_vport_start_params *p_params) | |
dacd88d6 YM |
438 | { |
439 | if (IS_VF(p_hwfn->cdev)) { | |
440 | return qed_vf_pf_vport_start(p_hwfn, p_params->vport_id, | |
441 | p_params->mtu, | |
442 | p_params->remove_inner_vlan, | |
443 | p_params->tpa_mode, | |
08feecd7 YM |
444 | p_params->max_buffers_per_cqe, |
445 | p_params->only_untagged); | |
dacd88d6 YM |
446 | } |
447 | ||
448 | return qed_sp_eth_vport_start(p_hwfn, p_params); | |
449 | } | |
450 | ||
cee4d264 MC |
451 | static int |
452 | qed_sp_vport_update_rss(struct qed_hwfn *p_hwfn, | |
453 | struct vport_update_ramrod_data *p_ramrod, | |
f29ffdb6 | 454 | struct qed_rss_params *p_rss) |
cee4d264 | 455 | { |
f29ffdb6 MY |
456 | struct eth_vport_rss_config *p_config; |
457 | u16 capabilities = 0; | |
458 | int i, table_size; | |
459 | int rc = 0; | |
cee4d264 | 460 | |
f29ffdb6 | 461 | if (!p_rss) { |
cee4d264 MC |
462 | p_ramrod->common.update_rss_flg = 0; |
463 | return rc; | |
464 | } | |
f29ffdb6 | 465 | p_config = &p_ramrod->rss_config; |
cee4d264 | 466 | |
f29ffdb6 | 467 | BUILD_BUG_ON(QED_RSS_IND_TABLE_SIZE != ETH_RSS_IND_TABLE_ENTRIES_NUM); |
cee4d264 | 468 | |
f29ffdb6 | 469 | rc = qed_fw_rss_eng(p_hwfn, p_rss->rss_eng_id, &p_config->rss_id); |
cee4d264 MC |
470 | if (rc) |
471 | return rc; | |
472 | ||
f29ffdb6 MY |
473 | p_ramrod->common.update_rss_flg = p_rss->update_rss_config; |
474 | p_config->update_rss_capabilities = p_rss->update_rss_capabilities; | |
475 | p_config->update_rss_ind_table = p_rss->update_rss_ind_table; | |
476 | p_config->update_rss_key = p_rss->update_rss_key; | |
cee4d264 | 477 | |
f29ffdb6 MY |
478 | p_config->rss_mode = p_rss->rss_enable ? |
479 | ETH_VPORT_RSS_MODE_REGULAR : | |
480 | ETH_VPORT_RSS_MODE_DISABLED; | |
cee4d264 MC |
481 | |
482 | SET_FIELD(capabilities, | |
483 | ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY, | |
f29ffdb6 | 484 | !!(p_rss->rss_caps & QED_RSS_IPV4)); |
cee4d264 MC |
485 | SET_FIELD(capabilities, |
486 | ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY, | |
f29ffdb6 | 487 | !!(p_rss->rss_caps & QED_RSS_IPV6)); |
cee4d264 MC |
488 | SET_FIELD(capabilities, |
489 | ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY, | |
f29ffdb6 | 490 | !!(p_rss->rss_caps & QED_RSS_IPV4_TCP)); |
cee4d264 MC |
491 | SET_FIELD(capabilities, |
492 | ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY, | |
f29ffdb6 | 493 | !!(p_rss->rss_caps & QED_RSS_IPV6_TCP)); |
cee4d264 MC |
494 | SET_FIELD(capabilities, |
495 | ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY, | |
f29ffdb6 | 496 | !!(p_rss->rss_caps & QED_RSS_IPV4_UDP)); |
cee4d264 MC |
497 | SET_FIELD(capabilities, |
498 | ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY, | |
f29ffdb6 MY |
499 | !!(p_rss->rss_caps & QED_RSS_IPV6_UDP)); |
500 | p_config->tbl_size = p_rss->rss_table_size_log; | |
cee4d264 | 501 | |
f29ffdb6 | 502 | p_config->capabilities = cpu_to_le16(capabilities); |
cee4d264 MC |
503 | |
504 | DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP, | |
505 | "update rss flag %d, rss_mode = %d, update_caps = %d, capabilities = %d, update_ind = %d, update_rss_key = %d\n", | |
506 | p_ramrod->common.update_rss_flg, | |
f29ffdb6 MY |
507 | p_config->rss_mode, |
508 | p_config->update_rss_capabilities, | |
509 | p_config->capabilities, | |
510 | p_config->update_rss_ind_table, p_config->update_rss_key); | |
cee4d264 | 511 | |
f29ffdb6 MY |
512 | table_size = min_t(int, QED_RSS_IND_TABLE_SIZE, |
513 | 1 << p_config->tbl_size); | |
514 | for (i = 0; i < table_size; i++) { | |
515 | struct qed_queue_cid *p_queue = p_rss->rss_ind_table[i]; | |
cee4d264 | 516 | |
f29ffdb6 MY |
517 | if (!p_queue) |
518 | return -EINVAL; | |
519 | ||
520 | p_config->indirection_table[i] = | |
521 | cpu_to_le16(p_queue->abs.queue_id); | |
522 | } | |
523 | ||
524 | DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP, | |
525 | "Configured RSS indirection table [%d entries]:\n", | |
526 | table_size); | |
527 | for (i = 0; i < QED_RSS_IND_TABLE_SIZE; i += 0x10) { | |
528 | DP_VERBOSE(p_hwfn, | |
529 | NETIF_MSG_IFUP, | |
530 | "%04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x\n", | |
531 | le16_to_cpu(p_config->indirection_table[i]), | |
532 | le16_to_cpu(p_config->indirection_table[i + 1]), | |
533 | le16_to_cpu(p_config->indirection_table[i + 2]), | |
534 | le16_to_cpu(p_config->indirection_table[i + 3]), | |
535 | le16_to_cpu(p_config->indirection_table[i + 4]), | |
536 | le16_to_cpu(p_config->indirection_table[i + 5]), | |
537 | le16_to_cpu(p_config->indirection_table[i + 6]), | |
538 | le16_to_cpu(p_config->indirection_table[i + 7]), | |
539 | le16_to_cpu(p_config->indirection_table[i + 8]), | |
540 | le16_to_cpu(p_config->indirection_table[i + 9]), | |
541 | le16_to_cpu(p_config->indirection_table[i + 10]), | |
542 | le16_to_cpu(p_config->indirection_table[i + 11]), | |
543 | le16_to_cpu(p_config->indirection_table[i + 12]), | |
544 | le16_to_cpu(p_config->indirection_table[i + 13]), | |
545 | le16_to_cpu(p_config->indirection_table[i + 14]), | |
546 | le16_to_cpu(p_config->indirection_table[i + 15])); | |
cee4d264 MC |
547 | } |
548 | ||
549 | for (i = 0; i < 10; i++) | |
f29ffdb6 | 550 | p_config->rss_key[i] = cpu_to_le32(p_rss->rss_key[i]); |
cee4d264 MC |
551 | |
552 | return rc; | |
553 | } | |
554 | ||
555 | static void | |
556 | qed_sp_update_accept_mode(struct qed_hwfn *p_hwfn, | |
557 | struct vport_update_ramrod_data *p_ramrod, | |
558 | struct qed_filter_accept_flags accept_flags) | |
559 | { | |
560 | p_ramrod->common.update_rx_mode_flg = | |
561 | accept_flags.update_rx_mode_config; | |
562 | ||
563 | p_ramrod->common.update_tx_mode_flg = | |
564 | accept_flags.update_tx_mode_config; | |
565 | ||
566 | /* Set Rx mode accept flags */ | |
567 | if (p_ramrod->common.update_rx_mode_flg) { | |
568 | u8 accept_filter = accept_flags.rx_accept_filter; | |
569 | u16 state = 0; | |
570 | ||
571 | SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_DROP_ALL, | |
572 | !(!!(accept_filter & QED_ACCEPT_UCAST_MATCHED) || | |
573 | !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED))); | |
574 | ||
575 | SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED, | |
576 | !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED)); | |
577 | ||
578 | SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_DROP_ALL, | |
579 | !(!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) || | |
580 | !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED))); | |
581 | ||
582 | SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL, | |
583 | (!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) && | |
584 | !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED))); | |
585 | ||
586 | SET_FIELD(state, ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL, | |
587 | !!(accept_filter & QED_ACCEPT_BCAST)); | |
588 | ||
d52c89f1 MK |
589 | SET_FIELD(state, ETH_VPORT_RX_MODE_ACCEPT_ANY_VNI, |
590 | !!(accept_filter & QED_ACCEPT_ANY_VNI)); | |
591 | ||
cee4d264 MC |
592 | p_ramrod->rx_mode.state = cpu_to_le16(state); |
593 | DP_VERBOSE(p_hwfn, QED_MSG_SP, | |
594 | "p_ramrod->rx_mode.state = 0x%x\n", state); | |
595 | } | |
596 | ||
597 | /* Set Tx mode accept flags */ | |
598 | if (p_ramrod->common.update_tx_mode_flg) { | |
599 | u8 accept_filter = accept_flags.tx_accept_filter; | |
600 | u16 state = 0; | |
601 | ||
602 | SET_FIELD(state, ETH_VPORT_TX_MODE_UCAST_DROP_ALL, | |
603 | !!(accept_filter & QED_ACCEPT_NONE)); | |
604 | ||
cee4d264 MC |
605 | SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_DROP_ALL, |
606 | !!(accept_filter & QED_ACCEPT_NONE)); | |
607 | ||
608 | SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL, | |
609 | (!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) && | |
610 | !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED))); | |
611 | ||
612 | SET_FIELD(state, ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL, | |
613 | !!(accept_filter & QED_ACCEPT_BCAST)); | |
614 | ||
615 | p_ramrod->tx_mode.state = cpu_to_le16(state); | |
616 | DP_VERBOSE(p_hwfn, QED_MSG_SP, | |
617 | "p_ramrod->tx_mode.state = 0x%x\n", state); | |
618 | } | |
619 | } | |
620 | ||
17b235c1 YM |
621 | static void |
622 | qed_sp_vport_update_sge_tpa(struct qed_hwfn *p_hwfn, | |
623 | struct vport_update_ramrod_data *p_ramrod, | |
624 | struct qed_sge_tpa_params *p_params) | |
625 | { | |
626 | struct eth_vport_tpa_param *p_tpa; | |
627 | ||
628 | if (!p_params) { | |
629 | p_ramrod->common.update_tpa_param_flg = 0; | |
630 | p_ramrod->common.update_tpa_en_flg = 0; | |
631 | p_ramrod->common.update_tpa_param_flg = 0; | |
632 | return; | |
633 | } | |
634 | ||
635 | p_ramrod->common.update_tpa_en_flg = p_params->update_tpa_en_flg; | |
636 | p_tpa = &p_ramrod->tpa_param; | |
637 | p_tpa->tpa_ipv4_en_flg = p_params->tpa_ipv4_en_flg; | |
638 | p_tpa->tpa_ipv6_en_flg = p_params->tpa_ipv6_en_flg; | |
639 | p_tpa->tpa_ipv4_tunn_en_flg = p_params->tpa_ipv4_tunn_en_flg; | |
640 | p_tpa->tpa_ipv6_tunn_en_flg = p_params->tpa_ipv6_tunn_en_flg; | |
641 | ||
642 | p_ramrod->common.update_tpa_param_flg = p_params->update_tpa_param_flg; | |
643 | p_tpa->max_buff_num = p_params->max_buffers_per_cqe; | |
644 | p_tpa->tpa_pkt_split_flg = p_params->tpa_pkt_split_flg; | |
645 | p_tpa->tpa_hdr_data_split_flg = p_params->tpa_hdr_data_split_flg; | |
646 | p_tpa->tpa_gro_consistent_flg = p_params->tpa_gro_consistent_flg; | |
647 | p_tpa->tpa_max_aggs_num = p_params->tpa_max_aggs_num; | |
648 | p_tpa->tpa_max_size = p_params->tpa_max_size; | |
649 | p_tpa->tpa_min_size_to_start = p_params->tpa_min_size_to_start; | |
650 | p_tpa->tpa_min_size_to_cont = p_params->tpa_min_size_to_cont; | |
651 | } | |
652 | ||
cee4d264 MC |
653 | static void |
654 | qed_sp_update_mcast_bin(struct qed_hwfn *p_hwfn, | |
655 | struct vport_update_ramrod_data *p_ramrod, | |
656 | struct qed_sp_vport_update_params *p_params) | |
657 | { | |
658 | int i; | |
659 | ||
660 | memset(&p_ramrod->approx_mcast.bins, 0, | |
661 | sizeof(p_ramrod->approx_mcast.bins)); | |
662 | ||
83aeb933 YM |
663 | if (!p_params->update_approx_mcast_flg) |
664 | return; | |
cee4d264 | 665 | |
83aeb933 YM |
666 | p_ramrod->common.update_approx_mcast_flg = 1; |
667 | for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) { | |
25c020a9 | 668 | u32 *p_bins = p_params->bins; |
83aeb933 YM |
669 | |
670 | p_ramrod->approx_mcast.bins[i] = cpu_to_le32(p_bins[i]); | |
cee4d264 MC |
671 | } |
672 | } | |
673 | ||
dacd88d6 YM |
674 | int qed_sp_vport_update(struct qed_hwfn *p_hwfn, |
675 | struct qed_sp_vport_update_params *p_params, | |
676 | enum spq_mode comp_mode, | |
677 | struct qed_spq_comp_cb *p_comp_data) | |
cee4d264 MC |
678 | { |
679 | struct qed_rss_params *p_rss_params = p_params->rss_params; | |
680 | struct vport_update_ramrod_data_cmn *p_cmn; | |
06f56b81 | 681 | struct qed_sp_init_data init_data; |
cee4d264 MC |
682 | struct vport_update_ramrod_data *p_ramrod = NULL; |
683 | struct qed_spq_entry *p_ent = NULL; | |
17b235c1 | 684 | u8 abs_vport_id = 0, val; |
cee4d264 MC |
685 | int rc = -EINVAL; |
686 | ||
dacd88d6 YM |
687 | if (IS_VF(p_hwfn->cdev)) { |
688 | rc = qed_vf_pf_vport_update(p_hwfn, p_params); | |
689 | return rc; | |
690 | } | |
691 | ||
cee4d264 | 692 | rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id); |
1a635e48 | 693 | if (rc) |
cee4d264 MC |
694 | return rc; |
695 | ||
06f56b81 YM |
696 | memset(&init_data, 0, sizeof(init_data)); |
697 | init_data.cid = qed_spq_get_cid(p_hwfn); | |
698 | init_data.opaque_fid = p_params->opaque_fid; | |
699 | init_data.comp_mode = comp_mode; | |
700 | init_data.p_comp_data = p_comp_data; | |
cee4d264 MC |
701 | |
702 | rc = qed_sp_init_request(p_hwfn, &p_ent, | |
cee4d264 | 703 | ETH_RAMROD_VPORT_UPDATE, |
06f56b81 | 704 | PROTOCOLID_ETH, &init_data); |
cee4d264 MC |
705 | if (rc) |
706 | return rc; | |
707 | ||
708 | /* Copy input params to ramrod according to FW struct */ | |
709 | p_ramrod = &p_ent->ramrod.vport_update; | |
710 | p_cmn = &p_ramrod->common; | |
711 | ||
712 | p_cmn->vport_id = abs_vport_id; | |
713 | p_cmn->rx_active_flg = p_params->vport_active_rx_flg; | |
714 | p_cmn->update_rx_active_flg = p_params->update_vport_active_rx_flg; | |
715 | p_cmn->tx_active_flg = p_params->vport_active_tx_flg; | |
716 | p_cmn->update_tx_active_flg = p_params->update_vport_active_tx_flg; | |
3f9b4a69 | 717 | p_cmn->accept_any_vlan = p_params->accept_any_vlan; |
83aeb933 YM |
718 | val = p_params->update_accept_any_vlan_flg; |
719 | p_cmn->update_accept_any_vlan_flg = val; | |
17b235c1 YM |
720 | |
721 | p_cmn->inner_vlan_removal_en = p_params->inner_vlan_removal_flg; | |
722 | val = p_params->update_inner_vlan_removal_flg; | |
723 | p_cmn->update_inner_vlan_removal_en_flg = val; | |
08feecd7 YM |
724 | |
725 | p_cmn->default_vlan_en = p_params->default_vlan_enable_flg; | |
726 | val = p_params->update_default_vlan_enable_flg; | |
727 | p_cmn->update_default_vlan_en_flg = val; | |
728 | ||
729 | p_cmn->default_vlan = cpu_to_le16(p_params->default_vlan); | |
730 | p_cmn->update_default_vlan_flg = p_params->update_default_vlan_flg; | |
731 | ||
732 | p_cmn->silent_vlan_removal_en = p_params->silent_vlan_removal_flg; | |
733 | ||
17b235c1 YM |
734 | p_ramrod->common.tx_switching_en = p_params->tx_switching_flg; |
735 | p_cmn->update_tx_switching_en_flg = p_params->update_tx_switching_flg; | |
736 | ||
6ddc7608 YM |
737 | p_cmn->anti_spoofing_en = p_params->anti_spoofing_en; |
738 | val = p_params->update_anti_spoofing_en_flg; | |
739 | p_ramrod->common.update_anti_spoofing_en_flg = val; | |
740 | ||
cee4d264 MC |
741 | rc = qed_sp_vport_update_rss(p_hwfn, p_ramrod, p_rss_params); |
742 | if (rc) { | |
743 | /* Return spq entry which is taken in qed_sp_init_request()*/ | |
744 | qed_spq_return_entry(p_hwfn, p_ent); | |
745 | return rc; | |
746 | } | |
747 | ||
748 | /* Update mcast bins for VFs, PF doesn't use this functionality */ | |
749 | qed_sp_update_mcast_bin(p_hwfn, p_ramrod, p_params); | |
750 | ||
751 | qed_sp_update_accept_mode(p_hwfn, p_ramrod, p_params->accept_flags); | |
17b235c1 | 752 | qed_sp_vport_update_sge_tpa(p_hwfn, p_ramrod, p_params->sge_tpa_params); |
cee4d264 MC |
753 | return qed_spq_post(p_hwfn, p_ent, NULL); |
754 | } | |
755 | ||
dacd88d6 | 756 | int qed_sp_vport_stop(struct qed_hwfn *p_hwfn, u16 opaque_fid, u8 vport_id) |
cee4d264 | 757 | { |
cee4d264 | 758 | struct vport_stop_ramrod_data *p_ramrod; |
06f56b81 | 759 | struct qed_sp_init_data init_data; |
cee4d264 MC |
760 | struct qed_spq_entry *p_ent; |
761 | u8 abs_vport_id = 0; | |
762 | int rc; | |
763 | ||
dacd88d6 YM |
764 | if (IS_VF(p_hwfn->cdev)) |
765 | return qed_vf_pf_vport_stop(p_hwfn); | |
766 | ||
cee4d264 | 767 | rc = qed_fw_vport(p_hwfn, vport_id, &abs_vport_id); |
1a635e48 | 768 | if (rc) |
cee4d264 MC |
769 | return rc; |
770 | ||
06f56b81 YM |
771 | memset(&init_data, 0, sizeof(init_data)); |
772 | init_data.cid = qed_spq_get_cid(p_hwfn); | |
773 | init_data.opaque_fid = opaque_fid; | |
774 | init_data.comp_mode = QED_SPQ_MODE_EBLOCK; | |
cee4d264 MC |
775 | |
776 | rc = qed_sp_init_request(p_hwfn, &p_ent, | |
cee4d264 | 777 | ETH_RAMROD_VPORT_STOP, |
06f56b81 | 778 | PROTOCOLID_ETH, &init_data); |
cee4d264 MC |
779 | if (rc) |
780 | return rc; | |
781 | ||
782 | p_ramrod = &p_ent->ramrod.vport_stop; | |
783 | p_ramrod->vport_id = abs_vport_id; | |
784 | ||
785 | return qed_spq_post(p_hwfn, p_ent, NULL); | |
786 | } | |
787 | ||
dacd88d6 YM |
788 | static int |
789 | qed_vf_pf_accept_flags(struct qed_hwfn *p_hwfn, | |
790 | struct qed_filter_accept_flags *p_accept_flags) | |
791 | { | |
792 | struct qed_sp_vport_update_params s_params; | |
793 | ||
794 | memset(&s_params, 0, sizeof(s_params)); | |
795 | memcpy(&s_params.accept_flags, p_accept_flags, | |
796 | sizeof(struct qed_filter_accept_flags)); | |
797 | ||
798 | return qed_vf_pf_vport_update(p_hwfn, &s_params); | |
799 | } | |
800 | ||
cee4d264 MC |
801 | static int qed_filter_accept_cmd(struct qed_dev *cdev, |
802 | u8 vport, | |
803 | struct qed_filter_accept_flags accept_flags, | |
3f9b4a69 YM |
804 | u8 update_accept_any_vlan, |
805 | u8 accept_any_vlan, | |
dacd88d6 YM |
806 | enum spq_mode comp_mode, |
807 | struct qed_spq_comp_cb *p_comp_data) | |
cee4d264 MC |
808 | { |
809 | struct qed_sp_vport_update_params vport_update_params; | |
810 | int i, rc; | |
811 | ||
812 | /* Prepare and send the vport rx_mode change */ | |
813 | memset(&vport_update_params, 0, sizeof(vport_update_params)); | |
814 | vport_update_params.vport_id = vport; | |
815 | vport_update_params.accept_flags = accept_flags; | |
3f9b4a69 YM |
816 | vport_update_params.update_accept_any_vlan_flg = update_accept_any_vlan; |
817 | vport_update_params.accept_any_vlan = accept_any_vlan; | |
cee4d264 MC |
818 | |
819 | for_each_hwfn(cdev, i) { | |
820 | struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; | |
821 | ||
822 | vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid; | |
823 | ||
dacd88d6 YM |
824 | if (IS_VF(cdev)) { |
825 | rc = qed_vf_pf_accept_flags(p_hwfn, &accept_flags); | |
826 | if (rc) | |
827 | return rc; | |
828 | continue; | |
829 | } | |
830 | ||
cee4d264 MC |
831 | rc = qed_sp_vport_update(p_hwfn, &vport_update_params, |
832 | comp_mode, p_comp_data); | |
1a635e48 | 833 | if (rc) { |
cee4d264 MC |
834 | DP_ERR(cdev, "Update rx_mode failed %d\n", rc); |
835 | return rc; | |
836 | } | |
837 | ||
838 | DP_VERBOSE(p_hwfn, QED_MSG_SP, | |
839 | "Accept filter configured, flags = [Rx]%x [Tx]%x\n", | |
840 | accept_flags.rx_accept_filter, | |
841 | accept_flags.tx_accept_filter); | |
3f9b4a69 YM |
842 | if (update_accept_any_vlan) |
843 | DP_VERBOSE(p_hwfn, QED_MSG_SP, | |
844 | "accept_any_vlan=%d configured\n", | |
845 | accept_any_vlan); | |
cee4d264 MC |
846 | } |
847 | ||
848 | return 0; | |
849 | } | |
850 | ||
3da7a37a MY |
851 | int qed_eth_rxq_start_ramrod(struct qed_hwfn *p_hwfn, |
852 | struct qed_queue_cid *p_cid, | |
853 | u16 bd_max_bytes, | |
854 | dma_addr_t bd_chain_phys_addr, | |
855 | dma_addr_t cqe_pbl_addr, u16 cqe_pbl_size) | |
cee4d264 MC |
856 | { |
857 | struct rx_queue_start_ramrod_data *p_ramrod = NULL; | |
cee4d264 | 858 | struct qed_spq_entry *p_ent = NULL; |
06f56b81 | 859 | struct qed_sp_init_data init_data; |
cee4d264 MC |
860 | int rc = -EINVAL; |
861 | ||
cee4d264 | 862 | DP_VERBOSE(p_hwfn, QED_MSG_SP, |
3da7a37a MY |
863 | "opaque_fid=0x%x, cid=0x%x, rx_qzone=0x%x, vport_id=0x%x, sb_id=0x%x\n", |
864 | p_cid->opaque_fid, p_cid->cid, | |
f604b17d | 865 | p_cid->abs.queue_id, p_cid->abs.vport_id, p_cid->sb_igu_id); |
cee4d264 | 866 | |
06f56b81 YM |
867 | /* Get SPQ entry */ |
868 | memset(&init_data, 0, sizeof(init_data)); | |
3da7a37a MY |
869 | init_data.cid = p_cid->cid; |
870 | init_data.opaque_fid = p_cid->opaque_fid; | |
06f56b81 | 871 | init_data.comp_mode = QED_SPQ_MODE_EBLOCK; |
cee4d264 MC |
872 | |
873 | rc = qed_sp_init_request(p_hwfn, &p_ent, | |
cee4d264 | 874 | ETH_RAMROD_RX_QUEUE_START, |
06f56b81 | 875 | PROTOCOLID_ETH, &init_data); |
cee4d264 MC |
876 | if (rc) |
877 | return rc; | |
878 | ||
879 | p_ramrod = &p_ent->ramrod.rx_queue_start; | |
880 | ||
f604b17d MY |
881 | p_ramrod->sb_id = cpu_to_le16(p_cid->sb_igu_id); |
882 | p_ramrod->sb_index = p_cid->sb_idx; | |
3da7a37a MY |
883 | p_ramrod->vport_id = p_cid->abs.vport_id; |
884 | p_ramrod->stats_counter_id = p_cid->abs.stats_id; | |
885 | p_ramrod->rx_queue_id = cpu_to_le16(p_cid->abs.queue_id); | |
1a635e48 YM |
886 | p_ramrod->complete_cqe_flg = 0; |
887 | p_ramrod->complete_event_flg = 1; | |
cee4d264 | 888 | |
1a635e48 | 889 | p_ramrod->bd_max_bytes = cpu_to_le16(bd_max_bytes); |
94494598 | 890 | DMA_REGPAIR_LE(p_ramrod->bd_base, bd_chain_phys_addr); |
cee4d264 | 891 | |
1a635e48 | 892 | p_ramrod->num_of_pbl_pages = cpu_to_le16(cqe_pbl_size); |
94494598 | 893 | DMA_REGPAIR_LE(p_ramrod->cqe_pbl_addr, cqe_pbl_addr); |
cee4d264 | 894 | |
3946497a | 895 | if (p_cid->vfid != QED_QUEUE_CID_SELF) { |
3b19f478 MY |
896 | bool b_legacy_vf = !!(p_cid->vf_legacy & |
897 | QED_QCID_LEGACY_VF_RX_PROD); | |
898 | ||
3da7a37a | 899 | p_ramrod->vf_rx_prod_index = p_cid->vf_qid; |
351a4ded | 900 | DP_VERBOSE(p_hwfn, QED_MSG_SP, |
a044df83 | 901 | "Queue%s is meant for VF rxq[%02x]\n", |
3b19f478 MY |
902 | b_legacy_vf ? " [legacy]" : "", p_cid->vf_qid); |
903 | p_ramrod->vf_rx_prod_use_zone_a = b_legacy_vf; | |
a044df83 | 904 | } |
cee4d264 | 905 | |
351a4ded | 906 | return qed_spq_post(p_hwfn, p_ent, NULL); |
cee4d264 MC |
907 | } |
908 | ||
909 | static int | |
3da7a37a MY |
910 | qed_eth_pf_rx_queue_start(struct qed_hwfn *p_hwfn, |
911 | struct qed_queue_cid *p_cid, | |
cee4d264 MC |
912 | u16 bd_max_bytes, |
913 | dma_addr_t bd_chain_phys_addr, | |
914 | dma_addr_t cqe_pbl_addr, | |
dacd88d6 | 915 | u16 cqe_pbl_size, void __iomem **pp_prod) |
cee4d264 | 916 | { |
b21290b7 | 917 | u32 init_prod_val = 0; |
cee4d264 | 918 | |
3da7a37a MY |
919 | *pp_prod = p_hwfn->regview + |
920 | GTT_BAR0_MAP_REG_MSDM_RAM + | |
921 | MSTORM_ETH_PF_PRODS_OFFSET(p_cid->abs.queue_id); | |
cee4d264 MC |
922 | |
923 | /* Init the rcq, rx bd and rx sge (if valid) producers to 0 */ | |
b21290b7 | 924 | __internal_ram_wr(p_hwfn, *pp_prod, sizeof(u32), |
cee4d264 MC |
925 | (u32 *)(&init_prod_val)); |
926 | ||
3da7a37a MY |
927 | return qed_eth_rxq_start_ramrod(p_hwfn, p_cid, |
928 | bd_max_bytes, | |
929 | bd_chain_phys_addr, | |
930 | cqe_pbl_addr, cqe_pbl_size); | |
931 | } | |
932 | ||
933 | static int | |
934 | qed_eth_rx_queue_start(struct qed_hwfn *p_hwfn, | |
935 | u16 opaque_fid, | |
936 | struct qed_queue_start_common_params *p_params, | |
937 | u16 bd_max_bytes, | |
938 | dma_addr_t bd_chain_phys_addr, | |
939 | dma_addr_t cqe_pbl_addr, | |
940 | u16 cqe_pbl_size, | |
941 | struct qed_rxq_start_ret_params *p_ret_params) | |
942 | { | |
943 | struct qed_queue_cid *p_cid; | |
944 | int rc; | |
945 | ||
cee4d264 | 946 | /* Allocate a CID for the queue */ |
007bc371 | 947 | p_cid = qed_eth_queue_to_cid_pf(p_hwfn, opaque_fid, true, p_params); |
3da7a37a MY |
948 | if (!p_cid) |
949 | return -ENOMEM; | |
cee4d264 | 950 | |
3da7a37a MY |
951 | if (IS_PF(p_hwfn->cdev)) { |
952 | rc = qed_eth_pf_rx_queue_start(p_hwfn, p_cid, | |
953 | bd_max_bytes, | |
954 | bd_chain_phys_addr, | |
955 | cqe_pbl_addr, cqe_pbl_size, | |
956 | &p_ret_params->p_prod); | |
957 | } else { | |
958 | rc = qed_vf_pf_rxq_start(p_hwfn, p_cid, | |
cee4d264 MC |
959 | bd_max_bytes, |
960 | bd_chain_phys_addr, | |
3da7a37a MY |
961 | cqe_pbl_addr, |
962 | cqe_pbl_size, &p_ret_params->p_prod); | |
963 | } | |
cee4d264 | 964 | |
3da7a37a | 965 | /* Provide the caller with a reference to as handler */ |
1a635e48 | 966 | if (rc) |
3da7a37a MY |
967 | qed_eth_queue_cid_release(p_hwfn, p_cid); |
968 | else | |
969 | p_ret_params->p_handle = (void *)p_cid; | |
cee4d264 MC |
970 | |
971 | return rc; | |
972 | } | |
973 | ||
17b235c1 | 974 | int qed_sp_eth_rx_queues_update(struct qed_hwfn *p_hwfn, |
3da7a37a | 975 | void **pp_rxq_handles, |
17b235c1 YM |
976 | u8 num_rxqs, |
977 | u8 complete_cqe_flg, | |
978 | u8 complete_event_flg, | |
979 | enum spq_mode comp_mode, | |
980 | struct qed_spq_comp_cb *p_comp_data) | |
981 | { | |
982 | struct rx_queue_update_ramrod_data *p_ramrod = NULL; | |
983 | struct qed_spq_entry *p_ent = NULL; | |
984 | struct qed_sp_init_data init_data; | |
3da7a37a | 985 | struct qed_queue_cid *p_cid; |
17b235c1 YM |
986 | int rc = -EINVAL; |
987 | u8 i; | |
988 | ||
989 | memset(&init_data, 0, sizeof(init_data)); | |
990 | init_data.comp_mode = comp_mode; | |
991 | init_data.p_comp_data = p_comp_data; | |
992 | ||
993 | for (i = 0; i < num_rxqs; i++) { | |
3da7a37a | 994 | p_cid = ((struct qed_queue_cid **)pp_rxq_handles)[i]; |
17b235c1 YM |
995 | |
996 | /* Get SPQ entry */ | |
3da7a37a MY |
997 | init_data.cid = p_cid->cid; |
998 | init_data.opaque_fid = p_cid->opaque_fid; | |
17b235c1 YM |
999 | |
1000 | rc = qed_sp_init_request(p_hwfn, &p_ent, | |
1001 | ETH_RAMROD_RX_QUEUE_UPDATE, | |
1002 | PROTOCOLID_ETH, &init_data); | |
1003 | if (rc) | |
1004 | return rc; | |
1005 | ||
1006 | p_ramrod = &p_ent->ramrod.rx_queue_update; | |
3da7a37a | 1007 | p_ramrod->vport_id = p_cid->abs.vport_id; |
17b235c1 | 1008 | |
3da7a37a | 1009 | p_ramrod->rx_queue_id = cpu_to_le16(p_cid->abs.queue_id); |
17b235c1 YM |
1010 | p_ramrod->complete_cqe_flg = complete_cqe_flg; |
1011 | p_ramrod->complete_event_flg = complete_event_flg; | |
1012 | ||
1013 | rc = qed_spq_post(p_hwfn, p_ent, NULL); | |
1014 | if (rc) | |
1015 | return rc; | |
1016 | } | |
1017 | ||
1018 | return rc; | |
1019 | } | |
1020 | ||
3da7a37a MY |
1021 | static int |
1022 | qed_eth_pf_rx_queue_stop(struct qed_hwfn *p_hwfn, | |
1023 | struct qed_queue_cid *p_cid, | |
1024 | bool b_eq_completion_only, bool b_cqe_completion) | |
cee4d264 | 1025 | { |
cee4d264 | 1026 | struct rx_queue_stop_ramrod_data *p_ramrod = NULL; |
cee4d264 | 1027 | struct qed_spq_entry *p_ent = NULL; |
06f56b81 | 1028 | struct qed_sp_init_data init_data; |
3da7a37a | 1029 | int rc; |
dacd88d6 | 1030 | |
06f56b81 | 1031 | memset(&init_data, 0, sizeof(init_data)); |
3da7a37a MY |
1032 | init_data.cid = p_cid->cid; |
1033 | init_data.opaque_fid = p_cid->opaque_fid; | |
06f56b81 | 1034 | init_data.comp_mode = QED_SPQ_MODE_EBLOCK; |
cee4d264 MC |
1035 | |
1036 | rc = qed_sp_init_request(p_hwfn, &p_ent, | |
cee4d264 | 1037 | ETH_RAMROD_RX_QUEUE_STOP, |
06f56b81 | 1038 | PROTOCOLID_ETH, &init_data); |
cee4d264 MC |
1039 | if (rc) |
1040 | return rc; | |
1041 | ||
1042 | p_ramrod = &p_ent->ramrod.rx_queue_stop; | |
3da7a37a MY |
1043 | p_ramrod->vport_id = p_cid->abs.vport_id; |
1044 | p_ramrod->rx_queue_id = cpu_to_le16(p_cid->abs.queue_id); | |
cee4d264 MC |
1045 | |
1046 | /* Cleaning the queue requires the completion to arrive there. | |
1047 | * In addition, VFs require the answer to come as eqe to PF. | |
1048 | */ | |
3946497a | 1049 | p_ramrod->complete_cqe_flg = ((p_cid->vfid == QED_QUEUE_CID_SELF) && |
3da7a37a MY |
1050 | !b_eq_completion_only) || |
1051 | b_cqe_completion; | |
3946497a MY |
1052 | p_ramrod->complete_event_flg = (p_cid->vfid != QED_QUEUE_CID_SELF) || |
1053 | b_eq_completion_only; | |
cee4d264 | 1054 | |
3da7a37a MY |
1055 | return qed_spq_post(p_hwfn, p_ent, NULL); |
1056 | } | |
1057 | ||
1058 | int qed_eth_rx_queue_stop(struct qed_hwfn *p_hwfn, | |
1059 | void *p_rxq, | |
1060 | bool eq_completion_only, bool cqe_completion) | |
1061 | { | |
1062 | struct qed_queue_cid *p_cid = (struct qed_queue_cid *)p_rxq; | |
1063 | int rc = -EINVAL; | |
cee4d264 | 1064 | |
3da7a37a MY |
1065 | if (IS_PF(p_hwfn->cdev)) |
1066 | rc = qed_eth_pf_rx_queue_stop(p_hwfn, p_cid, | |
1067 | eq_completion_only, | |
1068 | cqe_completion); | |
1069 | else | |
1070 | rc = qed_vf_pf_rxq_stop(p_hwfn, p_cid, cqe_completion); | |
1071 | ||
1072 | if (!rc) | |
1073 | qed_eth_queue_cid_release(p_hwfn, p_cid); | |
1074 | return rc; | |
cee4d264 MC |
1075 | } |
1076 | ||
3da7a37a MY |
1077 | int |
1078 | qed_eth_txq_start_ramrod(struct qed_hwfn *p_hwfn, | |
1079 | struct qed_queue_cid *p_cid, | |
1080 | dma_addr_t pbl_addr, u16 pbl_size, u16 pq_id) | |
cee4d264 MC |
1081 | { |
1082 | struct tx_queue_start_ramrod_data *p_ramrod = NULL; | |
cee4d264 | 1083 | struct qed_spq_entry *p_ent = NULL; |
06f56b81 | 1084 | struct qed_sp_init_data init_data; |
cee4d264 | 1085 | int rc = -EINVAL; |
351a4ded | 1086 | |
06f56b81 YM |
1087 | /* Get SPQ entry */ |
1088 | memset(&init_data, 0, sizeof(init_data)); | |
3da7a37a MY |
1089 | init_data.cid = p_cid->cid; |
1090 | init_data.opaque_fid = p_cid->opaque_fid; | |
06f56b81 | 1091 | init_data.comp_mode = QED_SPQ_MODE_EBLOCK; |
cee4d264 | 1092 | |
06f56b81 | 1093 | rc = qed_sp_init_request(p_hwfn, &p_ent, |
cee4d264 | 1094 | ETH_RAMROD_TX_QUEUE_START, |
06f56b81 | 1095 | PROTOCOLID_ETH, &init_data); |
cee4d264 MC |
1096 | if (rc) |
1097 | return rc; | |
1098 | ||
1a635e48 | 1099 | p_ramrod = &p_ent->ramrod.tx_queue_start; |
3da7a37a | 1100 | p_ramrod->vport_id = p_cid->abs.vport_id; |
1a635e48 | 1101 | |
f604b17d MY |
1102 | p_ramrod->sb_id = cpu_to_le16(p_cid->sb_igu_id); |
1103 | p_ramrod->sb_index = p_cid->sb_idx; | |
3da7a37a | 1104 | p_ramrod->stats_counter_id = p_cid->abs.stats_id; |
cee4d264 | 1105 | |
3da7a37a MY |
1106 | p_ramrod->queue_zone_id = cpu_to_le16(p_cid->abs.queue_id); |
1107 | p_ramrod->same_as_last_id = cpu_to_le16(p_cid->abs.queue_id); | |
cee4d264 | 1108 | |
1a635e48 | 1109 | p_ramrod->pbl_size = cpu_to_le16(pbl_size); |
94494598 | 1110 | DMA_REGPAIR_LE(p_ramrod->pbl_base_addr, pbl_addr); |
cee4d264 | 1111 | |
1a635e48 | 1112 | p_ramrod->qm_pq_id = cpu_to_le16(pq_id); |
cee4d264 MC |
1113 | |
1114 | return qed_spq_post(p_hwfn, p_ent, NULL); | |
1115 | } | |
1116 | ||
1117 | static int | |
3da7a37a MY |
1118 | qed_eth_pf_tx_queue_start(struct qed_hwfn *p_hwfn, |
1119 | struct qed_queue_cid *p_cid, | |
1120 | u8 tc, | |
cee4d264 | 1121 | dma_addr_t pbl_addr, |
dacd88d6 | 1122 | u16 pbl_size, void __iomem **pp_doorbell) |
cee4d264 | 1123 | { |
cee4d264 MC |
1124 | int rc; |
1125 | ||
dacd88d6 | 1126 | |
3da7a37a MY |
1127 | rc = qed_eth_txq_start_ramrod(p_hwfn, p_cid, |
1128 | pbl_addr, pbl_size, | |
b5a9ee7c | 1129 | qed_get_cm_pq_idx_mcos(p_hwfn, tc)); |
cee4d264 MC |
1130 | if (rc) |
1131 | return rc; | |
1132 | ||
3da7a37a MY |
1133 | /* Provide the caller with the necessary return values */ |
1134 | *pp_doorbell = p_hwfn->doorbells + | |
1135 | qed_db_addr(p_cid->cid, DQ_DEMS_LEGACY); | |
cee4d264 | 1136 | |
3da7a37a MY |
1137 | return 0; |
1138 | } | |
cee4d264 | 1139 | |
3da7a37a MY |
1140 | static int |
1141 | qed_eth_tx_queue_start(struct qed_hwfn *p_hwfn, | |
1142 | u16 opaque_fid, | |
1143 | struct qed_queue_start_common_params *p_params, | |
1144 | u8 tc, | |
1145 | dma_addr_t pbl_addr, | |
1146 | u16 pbl_size, | |
1147 | struct qed_txq_start_ret_params *p_ret_params) | |
1148 | { | |
1149 | struct qed_queue_cid *p_cid; | |
1150 | int rc; | |
1151 | ||
007bc371 | 1152 | p_cid = qed_eth_queue_to_cid_pf(p_hwfn, opaque_fid, false, p_params); |
3da7a37a MY |
1153 | if (!p_cid) |
1154 | return -EINVAL; | |
1155 | ||
1156 | if (IS_PF(p_hwfn->cdev)) | |
1157 | rc = qed_eth_pf_tx_queue_start(p_hwfn, p_cid, tc, | |
1158 | pbl_addr, pbl_size, | |
1159 | &p_ret_params->p_doorbell); | |
1160 | else | |
1161 | rc = qed_vf_pf_txq_start(p_hwfn, p_cid, | |
1162 | pbl_addr, pbl_size, | |
1163 | &p_ret_params->p_doorbell); | |
cee4d264 MC |
1164 | |
1165 | if (rc) | |
3da7a37a MY |
1166 | qed_eth_queue_cid_release(p_hwfn, p_cid); |
1167 | else | |
1168 | p_ret_params->p_handle = (void *)p_cid; | |
cee4d264 MC |
1169 | |
1170 | return rc; | |
1171 | } | |
1172 | ||
3da7a37a MY |
1173 | static int |
1174 | qed_eth_pf_tx_queue_stop(struct qed_hwfn *p_hwfn, struct qed_queue_cid *p_cid) | |
cee4d264 | 1175 | { |
cee4d264 | 1176 | struct qed_spq_entry *p_ent = NULL; |
06f56b81 | 1177 | struct qed_sp_init_data init_data; |
3da7a37a | 1178 | int rc; |
dacd88d6 | 1179 | |
06f56b81 | 1180 | memset(&init_data, 0, sizeof(init_data)); |
3da7a37a MY |
1181 | init_data.cid = p_cid->cid; |
1182 | init_data.opaque_fid = p_cid->opaque_fid; | |
06f56b81 | 1183 | init_data.comp_mode = QED_SPQ_MODE_EBLOCK; |
cee4d264 MC |
1184 | |
1185 | rc = qed_sp_init_request(p_hwfn, &p_ent, | |
cee4d264 | 1186 | ETH_RAMROD_TX_QUEUE_STOP, |
06f56b81 | 1187 | PROTOCOLID_ETH, &init_data); |
cee4d264 MC |
1188 | if (rc) |
1189 | return rc; | |
1190 | ||
3da7a37a MY |
1191 | return qed_spq_post(p_hwfn, p_ent, NULL); |
1192 | } | |
1193 | ||
1194 | int qed_eth_tx_queue_stop(struct qed_hwfn *p_hwfn, void *p_handle) | |
1195 | { | |
1196 | struct qed_queue_cid *p_cid = (struct qed_queue_cid *)p_handle; | |
1197 | int rc; | |
1198 | ||
1199 | if (IS_PF(p_hwfn->cdev)) | |
1200 | rc = qed_eth_pf_tx_queue_stop(p_hwfn, p_cid); | |
1201 | else | |
1202 | rc = qed_vf_pf_txq_stop(p_hwfn, p_cid); | |
cee4d264 | 1203 | |
3da7a37a MY |
1204 | if (!rc) |
1205 | qed_eth_queue_cid_release(p_hwfn, p_cid); | |
1206 | return rc; | |
cee4d264 MC |
1207 | } |
1208 | ||
1a635e48 | 1209 | static enum eth_filter_action qed_filter_action(enum qed_filter_opcode opcode) |
cee4d264 MC |
1210 | { |
1211 | enum eth_filter_action action = MAX_ETH_FILTER_ACTION; | |
1212 | ||
1213 | switch (opcode) { | |
1214 | case QED_FILTER_ADD: | |
1215 | action = ETH_FILTER_ACTION_ADD; | |
1216 | break; | |
1217 | case QED_FILTER_REMOVE: | |
1218 | action = ETH_FILTER_ACTION_REMOVE; | |
1219 | break; | |
cee4d264 | 1220 | case QED_FILTER_FLUSH: |
fc48b7a6 | 1221 | action = ETH_FILTER_ACTION_REMOVE_ALL; |
cee4d264 MC |
1222 | break; |
1223 | default: | |
1224 | action = MAX_ETH_FILTER_ACTION; | |
1225 | } | |
1226 | ||
1227 | return action; | |
1228 | } | |
1229 | ||
cee4d264 MC |
1230 | static int |
1231 | qed_filter_ucast_common(struct qed_hwfn *p_hwfn, | |
1232 | u16 opaque_fid, | |
1233 | struct qed_filter_ucast *p_filter_cmd, | |
1234 | struct vport_filter_update_ramrod_data **pp_ramrod, | |
1235 | struct qed_spq_entry **pp_ent, | |
1236 | enum spq_mode comp_mode, | |
1237 | struct qed_spq_comp_cb *p_comp_data) | |
1238 | { | |
1239 | u8 vport_to_add_to = 0, vport_to_remove_from = 0; | |
1240 | struct vport_filter_update_ramrod_data *p_ramrod; | |
cee4d264 MC |
1241 | struct eth_filter_cmd *p_first_filter; |
1242 | struct eth_filter_cmd *p_second_filter; | |
06f56b81 | 1243 | struct qed_sp_init_data init_data; |
cee4d264 MC |
1244 | enum eth_filter_action action; |
1245 | int rc; | |
1246 | ||
1247 | rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from, | |
1248 | &vport_to_remove_from); | |
1249 | if (rc) | |
1250 | return rc; | |
1251 | ||
1252 | rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to, | |
1253 | &vport_to_add_to); | |
1254 | if (rc) | |
1255 | return rc; | |
1256 | ||
06f56b81 YM |
1257 | /* Get SPQ entry */ |
1258 | memset(&init_data, 0, sizeof(init_data)); | |
1259 | init_data.cid = qed_spq_get_cid(p_hwfn); | |
1260 | init_data.opaque_fid = opaque_fid; | |
1261 | init_data.comp_mode = comp_mode; | |
1262 | init_data.p_comp_data = p_comp_data; | |
cee4d264 MC |
1263 | |
1264 | rc = qed_sp_init_request(p_hwfn, pp_ent, | |
cee4d264 | 1265 | ETH_RAMROD_FILTERS_UPDATE, |
06f56b81 | 1266 | PROTOCOLID_ETH, &init_data); |
cee4d264 MC |
1267 | if (rc) |
1268 | return rc; | |
1269 | ||
1270 | *pp_ramrod = &(*pp_ent)->ramrod.vport_filter_update; | |
1271 | p_ramrod = *pp_ramrod; | |
1272 | p_ramrod->filter_cmd_hdr.rx = p_filter_cmd->is_rx_filter ? 1 : 0; | |
1273 | p_ramrod->filter_cmd_hdr.tx = p_filter_cmd->is_tx_filter ? 1 : 0; | |
1274 | ||
1275 | switch (p_filter_cmd->opcode) { | |
fc48b7a6 | 1276 | case QED_FILTER_REPLACE: |
cee4d264 MC |
1277 | case QED_FILTER_MOVE: |
1278 | p_ramrod->filter_cmd_hdr.cmd_cnt = 2; break; | |
1279 | default: | |
1280 | p_ramrod->filter_cmd_hdr.cmd_cnt = 1; break; | |
1281 | } | |
1282 | ||
1283 | p_first_filter = &p_ramrod->filter_cmds[0]; | |
1284 | p_second_filter = &p_ramrod->filter_cmds[1]; | |
1285 | ||
1286 | switch (p_filter_cmd->type) { | |
1287 | case QED_FILTER_MAC: | |
1288 | p_first_filter->type = ETH_FILTER_TYPE_MAC; break; | |
1289 | case QED_FILTER_VLAN: | |
1290 | p_first_filter->type = ETH_FILTER_TYPE_VLAN; break; | |
1291 | case QED_FILTER_MAC_VLAN: | |
1292 | p_first_filter->type = ETH_FILTER_TYPE_PAIR; break; | |
1293 | case QED_FILTER_INNER_MAC: | |
1294 | p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC; break; | |
1295 | case QED_FILTER_INNER_VLAN: | |
1296 | p_first_filter->type = ETH_FILTER_TYPE_INNER_VLAN; break; | |
1297 | case QED_FILTER_INNER_PAIR: | |
1298 | p_first_filter->type = ETH_FILTER_TYPE_INNER_PAIR; break; | |
1299 | case QED_FILTER_INNER_MAC_VNI_PAIR: | |
1300 | p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR; | |
1301 | break; | |
1302 | case QED_FILTER_MAC_VNI_PAIR: | |
1303 | p_first_filter->type = ETH_FILTER_TYPE_MAC_VNI_PAIR; break; | |
1304 | case QED_FILTER_VNI: | |
1305 | p_first_filter->type = ETH_FILTER_TYPE_VNI; break; | |
1306 | } | |
1307 | ||
1308 | if ((p_first_filter->type == ETH_FILTER_TYPE_MAC) || | |
1309 | (p_first_filter->type == ETH_FILTER_TYPE_PAIR) || | |
1310 | (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC) || | |
1311 | (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR) || | |
1312 | (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) || | |
1313 | (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR)) { | |
1314 | qed_set_fw_mac_addr(&p_first_filter->mac_msb, | |
1315 | &p_first_filter->mac_mid, | |
1316 | &p_first_filter->mac_lsb, | |
1317 | (u8 *)p_filter_cmd->mac); | |
1318 | } | |
1319 | ||
1320 | if ((p_first_filter->type == ETH_FILTER_TYPE_VLAN) || | |
1321 | (p_first_filter->type == ETH_FILTER_TYPE_PAIR) || | |
1322 | (p_first_filter->type == ETH_FILTER_TYPE_INNER_VLAN) || | |
1323 | (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR)) | |
1324 | p_first_filter->vlan_id = cpu_to_le16(p_filter_cmd->vlan); | |
1325 | ||
1326 | if ((p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) || | |
1327 | (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR) || | |
1328 | (p_first_filter->type == ETH_FILTER_TYPE_VNI)) | |
1329 | p_first_filter->vni = cpu_to_le32(p_filter_cmd->vni); | |
1330 | ||
1331 | if (p_filter_cmd->opcode == QED_FILTER_MOVE) { | |
1a635e48 YM |
1332 | p_second_filter->type = p_first_filter->type; |
1333 | p_second_filter->mac_msb = p_first_filter->mac_msb; | |
1334 | p_second_filter->mac_mid = p_first_filter->mac_mid; | |
1335 | p_second_filter->mac_lsb = p_first_filter->mac_lsb; | |
1336 | p_second_filter->vlan_id = p_first_filter->vlan_id; | |
1337 | p_second_filter->vni = p_first_filter->vni; | |
cee4d264 MC |
1338 | |
1339 | p_first_filter->action = ETH_FILTER_ACTION_REMOVE; | |
1340 | ||
1341 | p_first_filter->vport_id = vport_to_remove_from; | |
1342 | ||
1a635e48 YM |
1343 | p_second_filter->action = ETH_FILTER_ACTION_ADD; |
1344 | p_second_filter->vport_id = vport_to_add_to; | |
fc48b7a6 YM |
1345 | } else if (p_filter_cmd->opcode == QED_FILTER_REPLACE) { |
1346 | p_first_filter->vport_id = vport_to_add_to; | |
1347 | memcpy(p_second_filter, p_first_filter, | |
1348 | sizeof(*p_second_filter)); | |
1349 | p_first_filter->action = ETH_FILTER_ACTION_REMOVE_ALL; | |
1350 | p_second_filter->action = ETH_FILTER_ACTION_ADD; | |
cee4d264 MC |
1351 | } else { |
1352 | action = qed_filter_action(p_filter_cmd->opcode); | |
1353 | ||
1354 | if (action == MAX_ETH_FILTER_ACTION) { | |
1355 | DP_NOTICE(p_hwfn, | |
1356 | "%d is not supported yet\n", | |
1357 | p_filter_cmd->opcode); | |
1358 | return -EINVAL; | |
1359 | } | |
1360 | ||
1361 | p_first_filter->action = action; | |
1362 | p_first_filter->vport_id = (p_filter_cmd->opcode == | |
1363 | QED_FILTER_REMOVE) ? | |
1364 | vport_to_remove_from : | |
1365 | vport_to_add_to; | |
1366 | } | |
1367 | ||
1368 | return 0; | |
1369 | } | |
1370 | ||
dacd88d6 YM |
1371 | int qed_sp_eth_filter_ucast(struct qed_hwfn *p_hwfn, |
1372 | u16 opaque_fid, | |
1373 | struct qed_filter_ucast *p_filter_cmd, | |
1374 | enum spq_mode comp_mode, | |
1375 | struct qed_spq_comp_cb *p_comp_data) | |
cee4d264 MC |
1376 | { |
1377 | struct vport_filter_update_ramrod_data *p_ramrod = NULL; | |
1378 | struct qed_spq_entry *p_ent = NULL; | |
1379 | struct eth_filter_cmd_header *p_header; | |
1380 | int rc; | |
1381 | ||
1382 | rc = qed_filter_ucast_common(p_hwfn, opaque_fid, p_filter_cmd, | |
1383 | &p_ramrod, &p_ent, | |
1384 | comp_mode, p_comp_data); | |
1a635e48 | 1385 | if (rc) { |
cee4d264 MC |
1386 | DP_ERR(p_hwfn, "Uni. filter command failed %d\n", rc); |
1387 | return rc; | |
1388 | } | |
1389 | p_header = &p_ramrod->filter_cmd_hdr; | |
1390 | p_header->assert_on_error = p_filter_cmd->assert_on_error; | |
1391 | ||
1392 | rc = qed_spq_post(p_hwfn, p_ent, NULL); | |
1a635e48 YM |
1393 | if (rc) { |
1394 | DP_ERR(p_hwfn, "Unicast filter ADD command failed %d\n", rc); | |
cee4d264 MC |
1395 | return rc; |
1396 | } | |
1397 | ||
1398 | DP_VERBOSE(p_hwfn, QED_MSG_SP, | |
1399 | "Unicast filter configured, opcode = %s, type = %s, cmd_cnt = %d, is_rx_filter = %d, is_tx_filter = %d\n", | |
1400 | (p_filter_cmd->opcode == QED_FILTER_ADD) ? "ADD" : | |
1401 | ((p_filter_cmd->opcode == QED_FILTER_REMOVE) ? | |
1402 | "REMOVE" : | |
1403 | ((p_filter_cmd->opcode == QED_FILTER_MOVE) ? | |
1404 | "MOVE" : "REPLACE")), | |
1405 | (p_filter_cmd->type == QED_FILTER_MAC) ? "MAC" : | |
1406 | ((p_filter_cmd->type == QED_FILTER_VLAN) ? | |
1407 | "VLAN" : "MAC & VLAN"), | |
1408 | p_ramrod->filter_cmd_hdr.cmd_cnt, | |
1409 | p_filter_cmd->is_rx_filter, | |
1410 | p_filter_cmd->is_tx_filter); | |
1411 | DP_VERBOSE(p_hwfn, QED_MSG_SP, | |
1412 | "vport_to_add_to = %d, vport_to_remove_from = %d, mac = %2x:%2x:%2x:%2x:%2x:%2x, vlan = %d\n", | |
1413 | p_filter_cmd->vport_to_add_to, | |
1414 | p_filter_cmd->vport_to_remove_from, | |
1415 | p_filter_cmd->mac[0], | |
1416 | p_filter_cmd->mac[1], | |
1417 | p_filter_cmd->mac[2], | |
1418 | p_filter_cmd->mac[3], | |
1419 | p_filter_cmd->mac[4], | |
1420 | p_filter_cmd->mac[5], | |
1421 | p_filter_cmd->vlan); | |
1422 | ||
1423 | return 0; | |
1424 | } | |
1425 | ||
1426 | /******************************************************************************* | |
1427 | * Description: | |
1428 | * Calculates crc 32 on a buffer | |
1429 | * Note: crc32_length MUST be aligned to 8 | |
1430 | * Return: | |
1431 | ******************************************************************************/ | |
1432 | static u32 qed_calc_crc32c(u8 *crc32_packet, | |
1a635e48 | 1433 | u32 crc32_length, u32 crc32_seed, u8 complement) |
cee4d264 | 1434 | { |
1a635e48 YM |
1435 | u32 byte = 0, bit = 0, crc32_result = crc32_seed; |
1436 | u8 msb = 0, current_byte = 0; | |
cee4d264 MC |
1437 | |
1438 | if ((!crc32_packet) || | |
1439 | (crc32_length == 0) || | |
1440 | ((crc32_length % 8) != 0)) | |
1441 | return crc32_result; | |
1442 | for (byte = 0; byte < crc32_length; byte++) { | |
1443 | current_byte = crc32_packet[byte]; | |
1444 | for (bit = 0; bit < 8; bit++) { | |
1445 | msb = (u8)(crc32_result >> 31); | |
1446 | crc32_result = crc32_result << 1; | |
1447 | if (msb != (0x1 & (current_byte >> bit))) { | |
1448 | crc32_result = crc32_result ^ CRC32_POLY; | |
1449 | crc32_result |= 1; /*crc32_result[0] = 1;*/ | |
1450 | } | |
1451 | } | |
1452 | } | |
1453 | return crc32_result; | |
1454 | } | |
1455 | ||
1a635e48 | 1456 | static u32 qed_crc32c_le(u32 seed, u8 *mac, u32 len) |
cee4d264 MC |
1457 | { |
1458 | u32 packet_buf[2] = { 0 }; | |
1459 | ||
1460 | memcpy((u8 *)(&packet_buf[0]), &mac[0], 6); | |
1461 | return qed_calc_crc32c((u8 *)packet_buf, 8, seed, 0); | |
1462 | } | |
1463 | ||
dacd88d6 | 1464 | u8 qed_mcast_bin_from_mac(u8 *mac) |
cee4d264 MC |
1465 | { |
1466 | u32 crc = qed_crc32c_le(ETH_MULTICAST_BIN_FROM_MAC_SEED, | |
1467 | mac, ETH_ALEN); | |
1468 | ||
1469 | return crc & 0xff; | |
1470 | } | |
1471 | ||
1472 | static int | |
1473 | qed_sp_eth_filter_mcast(struct qed_hwfn *p_hwfn, | |
1474 | u16 opaque_fid, | |
1475 | struct qed_filter_mcast *p_filter_cmd, | |
1476 | enum spq_mode comp_mode, | |
1477 | struct qed_spq_comp_cb *p_comp_data) | |
1478 | { | |
cee4d264 | 1479 | struct vport_update_ramrod_data *p_ramrod = NULL; |
25c020a9 | 1480 | u32 bins[ETH_MULTICAST_MAC_BINS_IN_REGS]; |
cee4d264 | 1481 | struct qed_spq_entry *p_ent = NULL; |
06f56b81 | 1482 | struct qed_sp_init_data init_data; |
cee4d264 MC |
1483 | u8 abs_vport_id = 0; |
1484 | int rc, i; | |
1485 | ||
83aeb933 | 1486 | if (p_filter_cmd->opcode == QED_FILTER_ADD) |
cee4d264 MC |
1487 | rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to, |
1488 | &abs_vport_id); | |
83aeb933 | 1489 | else |
cee4d264 MC |
1490 | rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from, |
1491 | &abs_vport_id); | |
83aeb933 YM |
1492 | if (rc) |
1493 | return rc; | |
cee4d264 | 1494 | |
06f56b81 YM |
1495 | /* Get SPQ entry */ |
1496 | memset(&init_data, 0, sizeof(init_data)); | |
1497 | init_data.cid = qed_spq_get_cid(p_hwfn); | |
1498 | init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; | |
1499 | init_data.comp_mode = comp_mode; | |
1500 | init_data.p_comp_data = p_comp_data; | |
cee4d264 MC |
1501 | |
1502 | rc = qed_sp_init_request(p_hwfn, &p_ent, | |
cee4d264 | 1503 | ETH_RAMROD_VPORT_UPDATE, |
06f56b81 | 1504 | PROTOCOLID_ETH, &init_data); |
cee4d264 MC |
1505 | if (rc) { |
1506 | DP_ERR(p_hwfn, "Multi-cast command failed %d\n", rc); | |
1507 | return rc; | |
1508 | } | |
1509 | ||
1510 | p_ramrod = &p_ent->ramrod.vport_update; | |
1511 | p_ramrod->common.update_approx_mcast_flg = 1; | |
1512 | ||
1513 | /* explicitly clear out the entire vector */ | |
1514 | memset(&p_ramrod->approx_mcast.bins, 0, | |
1515 | sizeof(p_ramrod->approx_mcast.bins)); | |
25c020a9 | 1516 | memset(bins, 0, sizeof(bins)); |
cee4d264 MC |
1517 | /* filter ADD op is explicit set op and it removes |
1518 | * any existing filters for the vport | |
1519 | */ | |
1520 | if (p_filter_cmd->opcode == QED_FILTER_ADD) { | |
1521 | for (i = 0; i < p_filter_cmd->num_mc_addrs; i++) { | |
25c020a9 | 1522 | u32 bit, nbits; |
cee4d264 MC |
1523 | |
1524 | bit = qed_mcast_bin_from_mac(p_filter_cmd->mac[i]); | |
25c020a9 SRK |
1525 | nbits = sizeof(u32) * BITS_PER_BYTE; |
1526 | bins[bit / nbits] |= 1 << (bit % nbits); | |
cee4d264 MC |
1527 | } |
1528 | ||
1529 | /* Convert to correct endianity */ | |
1530 | for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) { | |
1a635e48 | 1531 | struct vport_update_ramrod_mcast *p_ramrod_bins; |
cee4d264 | 1532 | |
1a635e48 | 1533 | p_ramrod_bins = &p_ramrod->approx_mcast; |
25c020a9 | 1534 | p_ramrod_bins->bins[i] = cpu_to_le32(bins[i]); |
cee4d264 MC |
1535 | } |
1536 | } | |
1537 | ||
1538 | p_ramrod->common.vport_id = abs_vport_id; | |
1539 | ||
1540 | return qed_spq_post(p_hwfn, p_ent, NULL); | |
1541 | } | |
1542 | ||
dacd88d6 YM |
1543 | static int qed_filter_mcast_cmd(struct qed_dev *cdev, |
1544 | struct qed_filter_mcast *p_filter_cmd, | |
1545 | enum spq_mode comp_mode, | |
1546 | struct qed_spq_comp_cb *p_comp_data) | |
cee4d264 MC |
1547 | { |
1548 | int rc = 0; | |
1549 | int i; | |
1550 | ||
1551 | /* only ADD and REMOVE operations are supported for multi-cast */ | |
1552 | if ((p_filter_cmd->opcode != QED_FILTER_ADD && | |
1553 | (p_filter_cmd->opcode != QED_FILTER_REMOVE)) || | |
1554 | (p_filter_cmd->num_mc_addrs > QED_MAX_MC_ADDRS)) | |
1555 | return -EINVAL; | |
1556 | ||
1557 | for_each_hwfn(cdev, i) { | |
1558 | struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; | |
1559 | ||
1560 | u16 opaque_fid; | |
1561 | ||
dacd88d6 YM |
1562 | if (IS_VF(cdev)) { |
1563 | qed_vf_pf_filter_mcast(p_hwfn, p_filter_cmd); | |
1564 | continue; | |
1565 | } | |
cee4d264 MC |
1566 | |
1567 | opaque_fid = p_hwfn->hw_info.opaque_fid; | |
1568 | ||
1569 | rc = qed_sp_eth_filter_mcast(p_hwfn, | |
1570 | opaque_fid, | |
1571 | p_filter_cmd, | |
1a635e48 | 1572 | comp_mode, p_comp_data); |
cee4d264 MC |
1573 | } |
1574 | return rc; | |
1575 | } | |
1576 | ||
1577 | static int qed_filter_ucast_cmd(struct qed_dev *cdev, | |
1578 | struct qed_filter_ucast *p_filter_cmd, | |
1579 | enum spq_mode comp_mode, | |
1580 | struct qed_spq_comp_cb *p_comp_data) | |
1581 | { | |
1582 | int rc = 0; | |
1583 | int i; | |
1584 | ||
1585 | for_each_hwfn(cdev, i) { | |
1586 | struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; | |
1587 | u16 opaque_fid; | |
1588 | ||
dacd88d6 YM |
1589 | if (IS_VF(cdev)) { |
1590 | rc = qed_vf_pf_filter_ucast(p_hwfn, p_filter_cmd); | |
1591 | continue; | |
1592 | } | |
cee4d264 MC |
1593 | |
1594 | opaque_fid = p_hwfn->hw_info.opaque_fid; | |
1595 | ||
1596 | rc = qed_sp_eth_filter_ucast(p_hwfn, | |
1597 | opaque_fid, | |
1598 | p_filter_cmd, | |
1a635e48 YM |
1599 | comp_mode, p_comp_data); |
1600 | if (rc) | |
dacd88d6 | 1601 | break; |
cee4d264 MC |
1602 | } |
1603 | ||
1604 | return rc; | |
1605 | } | |
1606 | ||
86622ee7 YM |
1607 | /* Statistics related code */ |
1608 | static void __qed_get_vport_pstats_addrlen(struct qed_hwfn *p_hwfn, | |
1609 | u32 *p_addr, | |
dacd88d6 | 1610 | u32 *p_len, u16 statistics_bin) |
86622ee7 | 1611 | { |
dacd88d6 YM |
1612 | if (IS_PF(p_hwfn->cdev)) { |
1613 | *p_addr = BAR0_MAP_REG_PSDM_RAM + | |
1614 | PSTORM_QUEUE_STAT_OFFSET(statistics_bin); | |
1615 | *p_len = sizeof(struct eth_pstorm_per_queue_stat); | |
1616 | } else { | |
1617 | struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info; | |
1618 | struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp; | |
1619 | ||
1620 | *p_addr = p_resp->pfdev_info.stats_info.pstats.address; | |
1621 | *p_len = p_resp->pfdev_info.stats_info.pstats.len; | |
1622 | } | |
86622ee7 YM |
1623 | } |
1624 | ||
1625 | static void __qed_get_vport_pstats(struct qed_hwfn *p_hwfn, | |
1626 | struct qed_ptt *p_ptt, | |
1627 | struct qed_eth_stats *p_stats, | |
1628 | u16 statistics_bin) | |
1629 | { | |
1630 | struct eth_pstorm_per_queue_stat pstats; | |
1631 | u32 pstats_addr = 0, pstats_len = 0; | |
1632 | ||
1633 | __qed_get_vport_pstats_addrlen(p_hwfn, &pstats_addr, &pstats_len, | |
1634 | statistics_bin); | |
1635 | ||
1636 | memset(&pstats, 0, sizeof(pstats)); | |
dacd88d6 YM |
1637 | qed_memcpy_from(p_hwfn, p_ptt, &pstats, pstats_addr, pstats_len); |
1638 | ||
9c79ddaa MY |
1639 | p_stats->common.tx_ucast_bytes += |
1640 | HILO_64_REGPAIR(pstats.sent_ucast_bytes); | |
1641 | p_stats->common.tx_mcast_bytes += | |
1642 | HILO_64_REGPAIR(pstats.sent_mcast_bytes); | |
1643 | p_stats->common.tx_bcast_bytes += | |
1644 | HILO_64_REGPAIR(pstats.sent_bcast_bytes); | |
1645 | p_stats->common.tx_ucast_pkts += | |
1646 | HILO_64_REGPAIR(pstats.sent_ucast_pkts); | |
1647 | p_stats->common.tx_mcast_pkts += | |
1648 | HILO_64_REGPAIR(pstats.sent_mcast_pkts); | |
1649 | p_stats->common.tx_bcast_pkts += | |
1650 | HILO_64_REGPAIR(pstats.sent_bcast_pkts); | |
1651 | p_stats->common.tx_err_drop_pkts += | |
1652 | HILO_64_REGPAIR(pstats.error_drop_pkts); | |
86622ee7 YM |
1653 | } |
1654 | ||
1655 | static void __qed_get_vport_tstats(struct qed_hwfn *p_hwfn, | |
1656 | struct qed_ptt *p_ptt, | |
1657 | struct qed_eth_stats *p_stats, | |
1658 | u16 statistics_bin) | |
1659 | { | |
86622ee7 | 1660 | struct tstorm_per_port_stat tstats; |
dacd88d6 | 1661 | u32 tstats_addr, tstats_len; |
86622ee7 | 1662 | |
dacd88d6 YM |
1663 | if (IS_PF(p_hwfn->cdev)) { |
1664 | tstats_addr = BAR0_MAP_REG_TSDM_RAM + | |
1665 | TSTORM_PORT_STAT_OFFSET(MFW_PORT(p_hwfn)); | |
1666 | tstats_len = sizeof(struct tstorm_per_port_stat); | |
1667 | } else { | |
1668 | struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info; | |
1669 | struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp; | |
1670 | ||
1671 | tstats_addr = p_resp->pfdev_info.stats_info.tstats.address; | |
1672 | tstats_len = p_resp->pfdev_info.stats_info.tstats.len; | |
1673 | } | |
86622ee7 YM |
1674 | |
1675 | memset(&tstats, 0, sizeof(tstats)); | |
dacd88d6 | 1676 | qed_memcpy_from(p_hwfn, p_ptt, &tstats, tstats_addr, tstats_len); |
86622ee7 | 1677 | |
9c79ddaa MY |
1678 | p_stats->common.mftag_filter_discards += |
1679 | HILO_64_REGPAIR(tstats.mftag_filter_discard); | |
1680 | p_stats->common.mac_filter_discards += | |
1681 | HILO_64_REGPAIR(tstats.eth_mac_filter_discard); | |
608e00d0 MC |
1682 | p_stats->common.gft_filter_drop += |
1683 | HILO_64_REGPAIR(tstats.eth_gft_drop_pkt); | |
86622ee7 YM |
1684 | } |
1685 | ||
1686 | static void __qed_get_vport_ustats_addrlen(struct qed_hwfn *p_hwfn, | |
1687 | u32 *p_addr, | |
dacd88d6 | 1688 | u32 *p_len, u16 statistics_bin) |
86622ee7 | 1689 | { |
dacd88d6 YM |
1690 | if (IS_PF(p_hwfn->cdev)) { |
1691 | *p_addr = BAR0_MAP_REG_USDM_RAM + | |
1692 | USTORM_QUEUE_STAT_OFFSET(statistics_bin); | |
1693 | *p_len = sizeof(struct eth_ustorm_per_queue_stat); | |
1694 | } else { | |
1695 | struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info; | |
1696 | struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp; | |
1697 | ||
1698 | *p_addr = p_resp->pfdev_info.stats_info.ustats.address; | |
1699 | *p_len = p_resp->pfdev_info.stats_info.ustats.len; | |
1700 | } | |
86622ee7 YM |
1701 | } |
1702 | ||
1703 | static void __qed_get_vport_ustats(struct qed_hwfn *p_hwfn, | |
1704 | struct qed_ptt *p_ptt, | |
1705 | struct qed_eth_stats *p_stats, | |
1706 | u16 statistics_bin) | |
1707 | { | |
1708 | struct eth_ustorm_per_queue_stat ustats; | |
1709 | u32 ustats_addr = 0, ustats_len = 0; | |
1710 | ||
1711 | __qed_get_vport_ustats_addrlen(p_hwfn, &ustats_addr, &ustats_len, | |
1712 | statistics_bin); | |
1713 | ||
1714 | memset(&ustats, 0, sizeof(ustats)); | |
dacd88d6 YM |
1715 | qed_memcpy_from(p_hwfn, p_ptt, &ustats, ustats_addr, ustats_len); |
1716 | ||
9c79ddaa MY |
1717 | p_stats->common.rx_ucast_bytes += |
1718 | HILO_64_REGPAIR(ustats.rcv_ucast_bytes); | |
1719 | p_stats->common.rx_mcast_bytes += | |
1720 | HILO_64_REGPAIR(ustats.rcv_mcast_bytes); | |
1721 | p_stats->common.rx_bcast_bytes += | |
1722 | HILO_64_REGPAIR(ustats.rcv_bcast_bytes); | |
1723 | p_stats->common.rx_ucast_pkts += HILO_64_REGPAIR(ustats.rcv_ucast_pkts); | |
1724 | p_stats->common.rx_mcast_pkts += HILO_64_REGPAIR(ustats.rcv_mcast_pkts); | |
1725 | p_stats->common.rx_bcast_pkts += HILO_64_REGPAIR(ustats.rcv_bcast_pkts); | |
86622ee7 YM |
1726 | } |
1727 | ||
1728 | static void __qed_get_vport_mstats_addrlen(struct qed_hwfn *p_hwfn, | |
1729 | u32 *p_addr, | |
dacd88d6 | 1730 | u32 *p_len, u16 statistics_bin) |
86622ee7 | 1731 | { |
dacd88d6 YM |
1732 | if (IS_PF(p_hwfn->cdev)) { |
1733 | *p_addr = BAR0_MAP_REG_MSDM_RAM + | |
1734 | MSTORM_QUEUE_STAT_OFFSET(statistics_bin); | |
1735 | *p_len = sizeof(struct eth_mstorm_per_queue_stat); | |
1736 | } else { | |
1737 | struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info; | |
1738 | struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp; | |
1739 | ||
1740 | *p_addr = p_resp->pfdev_info.stats_info.mstats.address; | |
1741 | *p_len = p_resp->pfdev_info.stats_info.mstats.len; | |
1742 | } | |
86622ee7 YM |
1743 | } |
1744 | ||
1745 | static void __qed_get_vport_mstats(struct qed_hwfn *p_hwfn, | |
1746 | struct qed_ptt *p_ptt, | |
1747 | struct qed_eth_stats *p_stats, | |
1748 | u16 statistics_bin) | |
1749 | { | |
1750 | struct eth_mstorm_per_queue_stat mstats; | |
1751 | u32 mstats_addr = 0, mstats_len = 0; | |
1752 | ||
1753 | __qed_get_vport_mstats_addrlen(p_hwfn, &mstats_addr, &mstats_len, | |
1754 | statistics_bin); | |
1755 | ||
1756 | memset(&mstats, 0, sizeof(mstats)); | |
dacd88d6 | 1757 | qed_memcpy_from(p_hwfn, p_ptt, &mstats, mstats_addr, mstats_len); |
86622ee7 | 1758 | |
9c79ddaa MY |
1759 | p_stats->common.no_buff_discards += |
1760 | HILO_64_REGPAIR(mstats.no_buff_discard); | |
1761 | p_stats->common.packet_too_big_discard += | |
1762 | HILO_64_REGPAIR(mstats.packet_too_big_discard); | |
1763 | p_stats->common.ttl0_discard += HILO_64_REGPAIR(mstats.ttl0_discard); | |
1764 | p_stats->common.tpa_coalesced_pkts += | |
1765 | HILO_64_REGPAIR(mstats.tpa_coalesced_pkts); | |
1766 | p_stats->common.tpa_coalesced_events += | |
1767 | HILO_64_REGPAIR(mstats.tpa_coalesced_events); | |
1768 | p_stats->common.tpa_aborts_num += | |
1769 | HILO_64_REGPAIR(mstats.tpa_aborts_num); | |
1770 | p_stats->common.tpa_coalesced_bytes += | |
1771 | HILO_64_REGPAIR(mstats.tpa_coalesced_bytes); | |
86622ee7 YM |
1772 | } |
1773 | ||
1774 | static void __qed_get_vport_port_stats(struct qed_hwfn *p_hwfn, | |
1775 | struct qed_ptt *p_ptt, | |
1776 | struct qed_eth_stats *p_stats) | |
1777 | { | |
9c79ddaa | 1778 | struct qed_eth_stats_common *p_common = &p_stats->common; |
86622ee7 YM |
1779 | struct port_stats port_stats; |
1780 | int j; | |
1781 | ||
1782 | memset(&port_stats, 0, sizeof(port_stats)); | |
1783 | ||
1784 | qed_memcpy_from(p_hwfn, p_ptt, &port_stats, | |
1785 | p_hwfn->mcp_info->port_addr + | |
1786 | offsetof(struct public_port, stats), | |
1787 | sizeof(port_stats)); | |
1788 | ||
9c79ddaa MY |
1789 | p_common->rx_64_byte_packets += port_stats.eth.r64; |
1790 | p_common->rx_65_to_127_byte_packets += port_stats.eth.r127; | |
1791 | p_common->rx_128_to_255_byte_packets += port_stats.eth.r255; | |
1792 | p_common->rx_256_to_511_byte_packets += port_stats.eth.r511; | |
1793 | p_common->rx_512_to_1023_byte_packets += port_stats.eth.r1023; | |
1794 | p_common->rx_1024_to_1518_byte_packets += port_stats.eth.r1518; | |
1795 | p_common->rx_crc_errors += port_stats.eth.rfcs; | |
1796 | p_common->rx_mac_crtl_frames += port_stats.eth.rxcf; | |
1797 | p_common->rx_pause_frames += port_stats.eth.rxpf; | |
1798 | p_common->rx_pfc_frames += port_stats.eth.rxpp; | |
1799 | p_common->rx_align_errors += port_stats.eth.raln; | |
1800 | p_common->rx_carrier_errors += port_stats.eth.rfcr; | |
1801 | p_common->rx_oversize_packets += port_stats.eth.rovr; | |
1802 | p_common->rx_jabbers += port_stats.eth.rjbr; | |
1803 | p_common->rx_undersize_packets += port_stats.eth.rund; | |
1804 | p_common->rx_fragments += port_stats.eth.rfrg; | |
1805 | p_common->tx_64_byte_packets += port_stats.eth.t64; | |
1806 | p_common->tx_65_to_127_byte_packets += port_stats.eth.t127; | |
1807 | p_common->tx_128_to_255_byte_packets += port_stats.eth.t255; | |
1808 | p_common->tx_256_to_511_byte_packets += port_stats.eth.t511; | |
1809 | p_common->tx_512_to_1023_byte_packets += port_stats.eth.t1023; | |
1810 | p_common->tx_1024_to_1518_byte_packets += port_stats.eth.t1518; | |
1811 | p_common->tx_pause_frames += port_stats.eth.txpf; | |
1812 | p_common->tx_pfc_frames += port_stats.eth.txpp; | |
1813 | p_common->rx_mac_bytes += port_stats.eth.rbyte; | |
1814 | p_common->rx_mac_uc_packets += port_stats.eth.rxuca; | |
1815 | p_common->rx_mac_mc_packets += port_stats.eth.rxmca; | |
1816 | p_common->rx_mac_bc_packets += port_stats.eth.rxbca; | |
1817 | p_common->rx_mac_frames_ok += port_stats.eth.rxpok; | |
1818 | p_common->tx_mac_bytes += port_stats.eth.tbyte; | |
1819 | p_common->tx_mac_uc_packets += port_stats.eth.txuca; | |
1820 | p_common->tx_mac_mc_packets += port_stats.eth.txmca; | |
1821 | p_common->tx_mac_bc_packets += port_stats.eth.txbca; | |
1822 | p_common->tx_mac_ctrl_frames += port_stats.eth.txcf; | |
86622ee7 | 1823 | for (j = 0; j < 8; j++) { |
9c79ddaa MY |
1824 | p_common->brb_truncates += port_stats.brb.brb_truncate[j]; |
1825 | p_common->brb_discards += port_stats.brb.brb_discard[j]; | |
1826 | } | |
1827 | ||
1828 | if (QED_IS_BB(p_hwfn->cdev)) { | |
1829 | struct qed_eth_stats_bb *p_bb = &p_stats->bb; | |
1830 | ||
1831 | p_bb->rx_1519_to_1522_byte_packets += | |
1832 | port_stats.eth.u0.bb0.r1522; | |
1833 | p_bb->rx_1519_to_2047_byte_packets += | |
1834 | port_stats.eth.u0.bb0.r2047; | |
1835 | p_bb->rx_2048_to_4095_byte_packets += | |
1836 | port_stats.eth.u0.bb0.r4095; | |
1837 | p_bb->rx_4096_to_9216_byte_packets += | |
1838 | port_stats.eth.u0.bb0.r9216; | |
1839 | p_bb->rx_9217_to_16383_byte_packets += | |
1840 | port_stats.eth.u0.bb0.r16383; | |
1841 | p_bb->tx_1519_to_2047_byte_packets += | |
1842 | port_stats.eth.u1.bb1.t2047; | |
1843 | p_bb->tx_2048_to_4095_byte_packets += | |
1844 | port_stats.eth.u1.bb1.t4095; | |
1845 | p_bb->tx_4096_to_9216_byte_packets += | |
1846 | port_stats.eth.u1.bb1.t9216; | |
1847 | p_bb->tx_9217_to_16383_byte_packets += | |
1848 | port_stats.eth.u1.bb1.t16383; | |
1849 | p_bb->tx_lpi_entry_count += port_stats.eth.u2.bb2.tlpiec; | |
1850 | p_bb->tx_total_collisions += port_stats.eth.u2.bb2.tncl; | |
1851 | } else { | |
1852 | struct qed_eth_stats_ah *p_ah = &p_stats->ah; | |
1853 | ||
1854 | p_ah->rx_1519_to_max_byte_packets += | |
1855 | port_stats.eth.u0.ah0.r1519_to_max; | |
1856 | p_ah->tx_1519_to_max_byte_packets = | |
1857 | port_stats.eth.u1.ah1.t1519_to_max; | |
86622ee7 | 1858 | } |
32d26a68 SRK |
1859 | |
1860 | p_common->link_change_count = qed_rd(p_hwfn, p_ptt, | |
1861 | p_hwfn->mcp_info->port_addr + | |
1862 | offsetof(struct public_port, | |
1863 | link_change_count)); | |
86622ee7 YM |
1864 | } |
1865 | ||
1866 | static void __qed_get_vport_stats(struct qed_hwfn *p_hwfn, | |
1867 | struct qed_ptt *p_ptt, | |
1868 | struct qed_eth_stats *stats, | |
dacd88d6 | 1869 | u16 statistics_bin, bool b_get_port_stats) |
86622ee7 YM |
1870 | { |
1871 | __qed_get_vport_mstats(p_hwfn, p_ptt, stats, statistics_bin); | |
1872 | __qed_get_vport_ustats(p_hwfn, p_ptt, stats, statistics_bin); | |
1873 | __qed_get_vport_tstats(p_hwfn, p_ptt, stats, statistics_bin); | |
1874 | __qed_get_vport_pstats(p_hwfn, p_ptt, stats, statistics_bin); | |
1875 | ||
dacd88d6 | 1876 | if (b_get_port_stats && p_hwfn->mcp_info) |
86622ee7 YM |
1877 | __qed_get_vport_port_stats(p_hwfn, p_ptt, stats); |
1878 | } | |
1879 | ||
1880 | static void _qed_get_vport_stats(struct qed_dev *cdev, | |
1881 | struct qed_eth_stats *stats) | |
1882 | { | |
dacd88d6 YM |
1883 | u8 fw_vport = 0; |
1884 | int i; | |
86622ee7 YM |
1885 | |
1886 | memset(stats, 0, sizeof(*stats)); | |
1887 | ||
1888 | for_each_hwfn(cdev, i) { | |
1889 | struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; | |
dacd88d6 YM |
1890 | struct qed_ptt *p_ptt = IS_PF(cdev) ? qed_ptt_acquire(p_hwfn) |
1891 | : NULL; | |
1892 | ||
1893 | if (IS_PF(cdev)) { | |
1894 | /* The main vport index is relative first */ | |
1895 | if (qed_fw_vport(p_hwfn, 0, &fw_vport)) { | |
1896 | DP_ERR(p_hwfn, "No vport available!\n"); | |
1897 | goto out; | |
1898 | } | |
86622ee7 YM |
1899 | } |
1900 | ||
dacd88d6 | 1901 | if (IS_PF(cdev) && !p_ptt) { |
86622ee7 YM |
1902 | DP_ERR(p_hwfn, "Failed to acquire ptt\n"); |
1903 | continue; | |
1904 | } | |
1905 | ||
dacd88d6 YM |
1906 | __qed_get_vport_stats(p_hwfn, p_ptt, stats, fw_vport, |
1907 | IS_PF(cdev) ? true : false); | |
86622ee7 | 1908 | |
dacd88d6 YM |
1909 | out: |
1910 | if (IS_PF(cdev) && p_ptt) | |
1911 | qed_ptt_release(p_hwfn, p_ptt); | |
86622ee7 YM |
1912 | } |
1913 | } | |
1914 | ||
1a635e48 | 1915 | void qed_get_vport_stats(struct qed_dev *cdev, struct qed_eth_stats *stats) |
86622ee7 YM |
1916 | { |
1917 | u32 i; | |
1918 | ||
1919 | if (!cdev) { | |
1920 | memset(stats, 0, sizeof(*stats)); | |
1921 | return; | |
1922 | } | |
1923 | ||
1924 | _qed_get_vport_stats(cdev, stats); | |
1925 | ||
1926 | if (!cdev->reset_stats) | |
1927 | return; | |
1928 | ||
1929 | /* Reduce the statistics baseline */ | |
1930 | for (i = 0; i < sizeof(struct qed_eth_stats) / sizeof(u64); i++) | |
1931 | ((u64 *)stats)[i] -= ((u64 *)cdev->reset_stats)[i]; | |
1932 | } | |
1933 | ||
1934 | /* zeroes V-PORT specific portion of stats (Port stats remains untouched) */ | |
1935 | void qed_reset_vport_stats(struct qed_dev *cdev) | |
1936 | { | |
1937 | int i; | |
1938 | ||
1939 | for_each_hwfn(cdev, i) { | |
1940 | struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; | |
1941 | struct eth_mstorm_per_queue_stat mstats; | |
1942 | struct eth_ustorm_per_queue_stat ustats; | |
1943 | struct eth_pstorm_per_queue_stat pstats; | |
dacd88d6 YM |
1944 | struct qed_ptt *p_ptt = IS_PF(cdev) ? qed_ptt_acquire(p_hwfn) |
1945 | : NULL; | |
86622ee7 YM |
1946 | u32 addr = 0, len = 0; |
1947 | ||
dacd88d6 | 1948 | if (IS_PF(cdev) && !p_ptt) { |
86622ee7 YM |
1949 | DP_ERR(p_hwfn, "Failed to acquire ptt\n"); |
1950 | continue; | |
1951 | } | |
1952 | ||
1953 | memset(&mstats, 0, sizeof(mstats)); | |
1954 | __qed_get_vport_mstats_addrlen(p_hwfn, &addr, &len, 0); | |
1955 | qed_memcpy_to(p_hwfn, p_ptt, addr, &mstats, len); | |
1956 | ||
1957 | memset(&ustats, 0, sizeof(ustats)); | |
1958 | __qed_get_vport_ustats_addrlen(p_hwfn, &addr, &len, 0); | |
1959 | qed_memcpy_to(p_hwfn, p_ptt, addr, &ustats, len); | |
1960 | ||
1961 | memset(&pstats, 0, sizeof(pstats)); | |
1962 | __qed_get_vport_pstats_addrlen(p_hwfn, &addr, &len, 0); | |
1963 | qed_memcpy_to(p_hwfn, p_ptt, addr, &pstats, len); | |
1964 | ||
dacd88d6 YM |
1965 | if (IS_PF(cdev)) |
1966 | qed_ptt_release(p_hwfn, p_ptt); | |
86622ee7 YM |
1967 | } |
1968 | ||
1969 | /* PORT statistics are not necessarily reset, so we need to | |
1970 | * read and create a baseline for future statistics. | |
32d26a68 | 1971 | * Link change stat is maintained by MFW, return its value as is. |
86622ee7 | 1972 | */ |
32d26a68 | 1973 | if (!cdev->reset_stats) { |
86622ee7 | 1974 | DP_INFO(cdev, "Reset stats not allocated\n"); |
32d26a68 | 1975 | } else { |
86622ee7 | 1976 | _qed_get_vport_stats(cdev, cdev->reset_stats); |
32d26a68 SRK |
1977 | cdev->reset_stats->common.link_change_count = 0; |
1978 | } | |
86622ee7 YM |
1979 | } |
1980 | ||
da090917 TT |
1981 | static enum gft_profile_type |
1982 | qed_arfs_mode_to_hsi(enum qed_filter_config_mode mode) | |
1983 | { | |
1984 | if (mode == QED_FILTER_CONFIG_MODE_5_TUPLE) | |
1985 | return GFT_PROFILE_TYPE_4_TUPLE; | |
1986 | if (mode == QED_FILTER_CONFIG_MODE_IP_DEST) | |
50bc60cb | 1987 | return GFT_PROFILE_TYPE_IP_DST_ADDR; |
3893fc62 MC |
1988 | if (mode == QED_FILTER_CONFIG_MODE_IP_SRC) |
1989 | return GFT_PROFILE_TYPE_IP_SRC_ADDR; | |
da090917 TT |
1990 | return GFT_PROFILE_TYPE_L4_DST_PORT; |
1991 | } | |
1992 | ||
1993 | void qed_arfs_mode_configure(struct qed_hwfn *p_hwfn, | |
1994 | struct qed_ptt *p_ptt, | |
1995 | struct qed_arfs_config_params *p_cfg_params) | |
1996 | { | |
1997 | if (p_cfg_params->mode != QED_FILTER_CONFIG_MODE_DISABLE) { | |
1998 | qed_gft_config(p_hwfn, p_ptt, p_hwfn->rel_pf_id, | |
1999 | p_cfg_params->tcp, | |
2000 | p_cfg_params->udp, | |
2001 | p_cfg_params->ipv4, | |
2002 | p_cfg_params->ipv6, | |
2003 | qed_arfs_mode_to_hsi(p_cfg_params->mode)); | |
2004 | DP_VERBOSE(p_hwfn, | |
2005 | QED_MSG_SP, | |
2006 | "Configured Filtering: tcp = %s, udp = %s, ipv4 = %s, ipv6 =%s mode=%08x\n", | |
d51e4af5 CM |
2007 | p_cfg_params->tcp ? "Enable" : "Disable", |
2008 | p_cfg_params->udp ? "Enable" : "Disable", | |
2009 | p_cfg_params->ipv4 ? "Enable" : "Disable", | |
da090917 TT |
2010 | p_cfg_params->ipv6 ? "Enable" : "Disable", |
2011 | (u32)p_cfg_params->mode); | |
d51e4af5 | 2012 | } else { |
da090917 TT |
2013 | DP_VERBOSE(p_hwfn, QED_MSG_SP, "Disabled Filtering\n"); |
2014 | qed_gft_disable(p_hwfn, p_ptt, p_hwfn->rel_pf_id); | |
d51e4af5 | 2015 | } |
d51e4af5 CM |
2016 | } |
2017 | ||
da090917 TT |
2018 | int |
2019 | qed_configure_rfs_ntuple_filter(struct qed_hwfn *p_hwfn, | |
d51e4af5 | 2020 | struct qed_spq_comp_cb *p_cb, |
da090917 | 2021 | struct qed_ntuple_filter_params *p_params) |
d51e4af5 CM |
2022 | { |
2023 | struct rx_update_gft_filter_data *p_ramrod = NULL; | |
2024 | struct qed_spq_entry *p_ent = NULL; | |
2025 | struct qed_sp_init_data init_data; | |
2026 | u16 abs_rx_q_id = 0; | |
2027 | u8 abs_vport_id = 0; | |
2028 | int rc = -EINVAL; | |
2029 | ||
d51e4af5 CM |
2030 | /* Get SPQ entry */ |
2031 | memset(&init_data, 0, sizeof(init_data)); | |
2032 | init_data.cid = qed_spq_get_cid(p_hwfn); | |
2033 | ||
2034 | init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; | |
2035 | ||
2036 | if (p_cb) { | |
2037 | init_data.comp_mode = QED_SPQ_MODE_CB; | |
2038 | init_data.p_comp_data = p_cb; | |
2039 | } else { | |
2040 | init_data.comp_mode = QED_SPQ_MODE_EBLOCK; | |
2041 | } | |
2042 | ||
2043 | rc = qed_sp_init_request(p_hwfn, &p_ent, | |
2044 | ETH_RAMROD_GFT_UPDATE_FILTER, | |
2045 | PROTOCOLID_ETH, &init_data); | |
2046 | if (rc) | |
2047 | return rc; | |
2048 | ||
2049 | p_ramrod = &p_ent->ramrod.rx_update_gft; | |
da090917 TT |
2050 | |
2051 | DMA_REGPAIR_LE(p_ramrod->pkt_hdr_addr, p_params->addr); | |
2052 | p_ramrod->pkt_hdr_length = cpu_to_le16(p_params->length); | |
2053 | ||
608e00d0 MC |
2054 | if (p_params->b_is_drop) { |
2055 | p_ramrod->vport_id = cpu_to_le16(ETH_GFT_TRASHCAN_VPORT); | |
2056 | } else { | |
2057 | rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id); | |
2058 | if (rc) | |
2059 | return rc; | |
2060 | ||
2061 | if (p_params->qid != QED_RFS_NTUPLE_QID_RSS) { | |
2062 | rc = qed_fw_l2_queue(p_hwfn, p_params->qid, | |
2063 | &abs_rx_q_id); | |
2064 | if (rc) | |
2065 | return rc; | |
2066 | ||
2067 | p_ramrod->rx_qid_valid = 1; | |
2068 | p_ramrod->rx_qid = cpu_to_le16(abs_rx_q_id); | |
2069 | } | |
2070 | ||
2071 | p_ramrod->vport_id = cpu_to_le16((u16)abs_vport_id); | |
da090917 TT |
2072 | } |
2073 | ||
2074 | p_ramrod->flow_id_valid = 0; | |
2075 | p_ramrod->flow_id = 0; | |
da090917 TT |
2076 | p_ramrod->filter_action = p_params->b_is_add ? GFT_ADD_FILTER |
2077 | : GFT_DELETE_FILTER; | |
d51e4af5 CM |
2078 | |
2079 | DP_VERBOSE(p_hwfn, QED_MSG_SP, | |
2080 | "V[%0x], Q[%04x] - %s filter from 0x%llx [length %04xb]\n", | |
2081 | abs_vport_id, abs_rx_q_id, | |
da090917 TT |
2082 | p_params->b_is_add ? "Adding" : "Removing", |
2083 | (u64)p_params->addr, p_params->length); | |
d51e4af5 CM |
2084 | |
2085 | return qed_spq_post(p_hwfn, p_ent, NULL); | |
2086 | } | |
2087 | ||
bf5a94bf RV |
2088 | int qed_get_rxq_coalesce(struct qed_hwfn *p_hwfn, |
2089 | struct qed_ptt *p_ptt, | |
2090 | struct qed_queue_cid *p_cid, u16 *p_rx_coal) | |
2091 | { | |
2092 | u32 coalesce, address, is_valid; | |
2093 | struct cau_sb_entry sb_entry; | |
2094 | u8 timer_res; | |
2095 | int rc; | |
2096 | ||
2097 | rc = qed_dmae_grc2host(p_hwfn, p_ptt, CAU_REG_SB_VAR_MEMORY + | |
2098 | p_cid->sb_igu_id * sizeof(u64), | |
2099 | (u64)(uintptr_t)&sb_entry, 2, 0); | |
2100 | if (rc) { | |
2101 | DP_ERR(p_hwfn, "dmae_grc2host failed %d\n", rc); | |
2102 | return rc; | |
2103 | } | |
2104 | ||
2105 | timer_res = GET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES0); | |
2106 | ||
2107 | address = BAR0_MAP_REG_USDM_RAM + | |
2108 | USTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id); | |
2109 | coalesce = qed_rd(p_hwfn, p_ptt, address); | |
2110 | ||
2111 | is_valid = GET_FIELD(coalesce, COALESCING_TIMESET_VALID); | |
2112 | if (!is_valid) | |
2113 | return -EINVAL; | |
2114 | ||
2115 | coalesce = GET_FIELD(coalesce, COALESCING_TIMESET_TIMESET); | |
2116 | *p_rx_coal = (u16)(coalesce << timer_res); | |
2117 | ||
2118 | return 0; | |
2119 | } | |
2120 | ||
2121 | int qed_get_txq_coalesce(struct qed_hwfn *p_hwfn, | |
2122 | struct qed_ptt *p_ptt, | |
2123 | struct qed_queue_cid *p_cid, u16 *p_tx_coal) | |
2124 | { | |
2125 | u32 coalesce, address, is_valid; | |
2126 | struct cau_sb_entry sb_entry; | |
2127 | u8 timer_res; | |
2128 | int rc; | |
2129 | ||
2130 | rc = qed_dmae_grc2host(p_hwfn, p_ptt, CAU_REG_SB_VAR_MEMORY + | |
2131 | p_cid->sb_igu_id * sizeof(u64), | |
2132 | (u64)(uintptr_t)&sb_entry, 2, 0); | |
2133 | if (rc) { | |
2134 | DP_ERR(p_hwfn, "dmae_grc2host failed %d\n", rc); | |
2135 | return rc; | |
2136 | } | |
2137 | ||
2138 | timer_res = GET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES1); | |
2139 | ||
2140 | address = BAR0_MAP_REG_XSDM_RAM + | |
2141 | XSTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id); | |
2142 | coalesce = qed_rd(p_hwfn, p_ptt, address); | |
2143 | ||
2144 | is_valid = GET_FIELD(coalesce, COALESCING_TIMESET_VALID); | |
2145 | if (!is_valid) | |
2146 | return -EINVAL; | |
2147 | ||
2148 | coalesce = GET_FIELD(coalesce, COALESCING_TIMESET_TIMESET); | |
2149 | *p_tx_coal = (u16)(coalesce << timer_res); | |
2150 | ||
2151 | return 0; | |
2152 | } | |
2153 | ||
2154 | int qed_get_queue_coalesce(struct qed_hwfn *p_hwfn, u16 *p_coal, void *handle) | |
2155 | { | |
2156 | struct qed_queue_cid *p_cid = handle; | |
2157 | struct qed_ptt *p_ptt; | |
2158 | int rc = 0; | |
2159 | ||
2160 | if (IS_VF(p_hwfn->cdev)) { | |
2161 | rc = qed_vf_pf_get_coalesce(p_hwfn, p_coal, p_cid); | |
2162 | if (rc) | |
2163 | DP_NOTICE(p_hwfn, "Unable to read queue coalescing\n"); | |
2164 | ||
2165 | return rc; | |
2166 | } | |
2167 | ||
2168 | p_ptt = qed_ptt_acquire(p_hwfn); | |
2169 | if (!p_ptt) | |
2170 | return -EAGAIN; | |
2171 | ||
2172 | if (p_cid->b_is_rx) { | |
2173 | rc = qed_get_rxq_coalesce(p_hwfn, p_ptt, p_cid, p_coal); | |
2174 | if (rc) | |
2175 | goto out; | |
2176 | } else { | |
2177 | rc = qed_get_txq_coalesce(p_hwfn, p_ptt, p_cid, p_coal); | |
2178 | if (rc) | |
2179 | goto out; | |
2180 | } | |
2181 | ||
2182 | out: | |
2183 | qed_ptt_release(p_hwfn, p_ptt); | |
2184 | ||
2185 | return rc; | |
2186 | } | |
2187 | ||
25c089d7 YM |
2188 | static int qed_fill_eth_dev_info(struct qed_dev *cdev, |
2189 | struct qed_dev_eth_info *info) | |
2190 | { | |
5e7baf0f | 2191 | struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); |
25c089d7 YM |
2192 | int i; |
2193 | ||
2194 | memset(info, 0, sizeof(*info)); | |
2195 | ||
1408cc1f | 2196 | if (IS_PF(cdev)) { |
25eb8d46 | 2197 | int max_vf_vlan_filters = 0; |
7b7e70f9 | 2198 | int max_vf_mac_filters = 0; |
25eb8d46 | 2199 | |
5e7baf0f MC |
2200 | info->num_tc = p_hwfn->hw_info.num_hw_tc; |
2201 | ||
1408cc1f | 2202 | if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) { |
e1d32acb MY |
2203 | u16 num_queues = 0; |
2204 | ||
2205 | /* Since the feature controls only queue-zones, | |
2206 | * make sure we have the contexts [rx, tx, xdp] to | |
2207 | * match. | |
2208 | */ | |
2209 | for_each_hwfn(cdev, i) { | |
2210 | struct qed_hwfn *hwfn = &cdev->hwfns[i]; | |
2211 | u16 l2_queues = (u16)FEAT_NUM(hwfn, | |
2212 | QED_PF_L2_QUE); | |
2213 | u16 cids; | |
2214 | ||
2215 | cids = hwfn->pf_params.eth_pf_params.num_cons; | |
2216 | num_queues += min_t(u16, l2_queues, cids / 3); | |
2217 | } | |
2218 | ||
2219 | /* queues might theoretically be >256, but interrupts' | |
2220 | * upper-limit guarantes that it would fit in a u8. | |
2221 | */ | |
2222 | if (cdev->int_params.fp_msix_cnt) { | |
2223 | u8 irqs = cdev->int_params.fp_msix_cnt; | |
2224 | ||
2225 | info->num_queues = (u8)min_t(u16, | |
2226 | num_queues, irqs); | |
2227 | } | |
1408cc1f YM |
2228 | } else { |
2229 | info->num_queues = cdev->num_hwfns; | |
2230 | } | |
2231 | ||
7b7e70f9 | 2232 | if (IS_QED_SRIOV(cdev)) { |
25eb8d46 YM |
2233 | max_vf_vlan_filters = cdev->p_iov_info->total_vfs * |
2234 | QED_ETH_VF_NUM_VLAN_FILTERS; | |
7b7e70f9 YM |
2235 | max_vf_mac_filters = cdev->p_iov_info->total_vfs * |
2236 | QED_ETH_VF_NUM_MAC_FILTERS; | |
2237 | } | |
2238 | info->num_vlan_filters = RESC_NUM(QED_LEADING_HWFN(cdev), | |
2239 | QED_VLAN) - | |
25eb8d46 | 2240 | max_vf_vlan_filters; |
7b7e70f9 YM |
2241 | info->num_mac_filters = RESC_NUM(QED_LEADING_HWFN(cdev), |
2242 | QED_MAC) - | |
2243 | max_vf_mac_filters; | |
25eb8d46 | 2244 | |
1408cc1f YM |
2245 | ether_addr_copy(info->port_mac, |
2246 | cdev->hwfns[0].hw_info.hw_mac_addr); | |
cbb8a12c MY |
2247 | |
2248 | info->xdp_supported = true; | |
25c089d7 | 2249 | } else { |
cbb8a12c MY |
2250 | u16 total_cids = 0; |
2251 | ||
5e7baf0f MC |
2252 | info->num_tc = 1; |
2253 | ||
cbb8a12c MY |
2254 | /* Determine queues & XDP support */ |
2255 | for_each_hwfn(cdev, i) { | |
2256 | struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; | |
2257 | u8 queues, cids; | |
25c089d7 | 2258 | |
cbb8a12c MY |
2259 | qed_vf_get_num_cids(p_hwfn, &cids); |
2260 | qed_vf_get_num_rxqs(p_hwfn, &queues); | |
1408cc1f | 2261 | info->num_queues += queues; |
cbb8a12c | 2262 | total_cids += cids; |
1408cc1f YM |
2263 | } |
2264 | ||
cbb8a12c MY |
2265 | /* Enable VF XDP in case PF guarntees sufficient connections */ |
2266 | if (total_cids >= info->num_queues * 3) | |
2267 | info->xdp_supported = true; | |
2268 | ||
1408cc1f | 2269 | qed_vf_get_num_vlan_filters(&cdev->hwfns[0], |
2edbff8d | 2270 | (u8 *)&info->num_vlan_filters); |
b0fca312 MY |
2271 | qed_vf_get_num_mac_filters(&cdev->hwfns[0], |
2272 | (u8 *)&info->num_mac_filters); | |
1408cc1f | 2273 | qed_vf_get_port_mac(&cdev->hwfns[0], info->port_mac); |
d8c2c7e3 YM |
2274 | |
2275 | info->is_legacy = !!cdev->hwfns[0].vf_iov_info->b_pre_fp_hsi; | |
1408cc1f | 2276 | } |
25c089d7 YM |
2277 | |
2278 | qed_fill_dev_info(cdev, &info->common); | |
2279 | ||
1408cc1f | 2280 | if (IS_VF(cdev)) |
0ee28e31 | 2281 | eth_zero_addr(info->common.hw_mac); |
1408cc1f | 2282 | |
25c089d7 YM |
2283 | return 0; |
2284 | } | |
2285 | ||
cc875c2e | 2286 | static void qed_register_eth_ops(struct qed_dev *cdev, |
1408cc1f | 2287 | struct qed_eth_cb_ops *ops, void *cookie) |
cc875c2e | 2288 | { |
1408cc1f YM |
2289 | cdev->protocol_ops.eth = ops; |
2290 | cdev->ops_cookie = cookie; | |
2291 | ||
2292 | /* For VF, we start bulletin reading */ | |
2293 | if (IS_VF(cdev)) | |
2294 | qed_vf_start_iov_wq(cdev); | |
cc875c2e YM |
2295 | } |
2296 | ||
eff16960 YM |
2297 | static bool qed_check_mac(struct qed_dev *cdev, u8 *mac) |
2298 | { | |
2299 | if (IS_PF(cdev)) | |
2300 | return true; | |
2301 | ||
2302 | return qed_vf_check_mac(&cdev->hwfns[0], mac); | |
2303 | } | |
2304 | ||
cee4d264 | 2305 | static int qed_start_vport(struct qed_dev *cdev, |
088c8618 | 2306 | struct qed_start_vport_params *params) |
cee4d264 MC |
2307 | { |
2308 | int rc, i; | |
2309 | ||
2310 | for_each_hwfn(cdev, i) { | |
088c8618 | 2311 | struct qed_sp_vport_start_params start = { 0 }; |
cee4d264 MC |
2312 | struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; |
2313 | ||
088c8618 MC |
2314 | start.tpa_mode = params->gro_enable ? QED_TPA_MODE_GRO : |
2315 | QED_TPA_MODE_NONE; | |
2316 | start.remove_inner_vlan = params->remove_inner_vlan; | |
08feecd7 | 2317 | start.only_untagged = true; /* untagged only */ |
088c8618 MC |
2318 | start.drop_ttl0 = params->drop_ttl0; |
2319 | start.opaque_fid = p_hwfn->hw_info.opaque_fid; | |
2320 | start.concrete_fid = p_hwfn->hw_info.concrete_fid; | |
c78c70fa | 2321 | start.handle_ptp_pkts = params->handle_ptp_pkts; |
088c8618 MC |
2322 | start.vport_id = params->vport_id; |
2323 | start.max_buffers_per_cqe = 16; | |
2324 | start.mtu = params->mtu; | |
2325 | ||
2326 | rc = qed_sp_vport_start(p_hwfn, &start); | |
cee4d264 MC |
2327 | if (rc) { |
2328 | DP_ERR(cdev, "Failed to start VPORT\n"); | |
2329 | return rc; | |
2330 | } | |
2331 | ||
15582962 RV |
2332 | rc = qed_hw_start_fastpath(p_hwfn); |
2333 | if (rc) { | |
2334 | DP_ERR(cdev, "Failed to start VPORT fastpath\n"); | |
2335 | return rc; | |
2336 | } | |
cee4d264 MC |
2337 | |
2338 | DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP), | |
2339 | "Started V-PORT %d with MTU %d\n", | |
088c8618 | 2340 | start.vport_id, start.mtu); |
cee4d264 MC |
2341 | } |
2342 | ||
a0d26d5a YM |
2343 | if (params->clear_stats) |
2344 | qed_reset_vport_stats(cdev); | |
9df2ed04 | 2345 | |
cee4d264 MC |
2346 | return 0; |
2347 | } | |
2348 | ||
1a635e48 | 2349 | static int qed_stop_vport(struct qed_dev *cdev, u8 vport_id) |
cee4d264 MC |
2350 | { |
2351 | int rc, i; | |
2352 | ||
2353 | for_each_hwfn(cdev, i) { | |
2354 | struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; | |
2355 | ||
2356 | rc = qed_sp_vport_stop(p_hwfn, | |
1a635e48 | 2357 | p_hwfn->hw_info.opaque_fid, vport_id); |
cee4d264 MC |
2358 | |
2359 | if (rc) { | |
2360 | DP_ERR(cdev, "Failed to stop VPORT\n"); | |
2361 | return rc; | |
2362 | } | |
2363 | } | |
2364 | return 0; | |
2365 | } | |
2366 | ||
f29ffdb6 MY |
2367 | static int qed_update_vport_rss(struct qed_dev *cdev, |
2368 | struct qed_update_vport_rss_params *input, | |
2369 | struct qed_rss_params *rss) | |
2370 | { | |
2371 | int i, fn; | |
2372 | ||
2373 | /* Update configuration with what's correct regardless of CMT */ | |
2374 | rss->update_rss_config = 1; | |
2375 | rss->rss_enable = 1; | |
2376 | rss->update_rss_capabilities = 1; | |
2377 | rss->update_rss_ind_table = 1; | |
2378 | rss->update_rss_key = 1; | |
2379 | rss->rss_caps = input->rss_caps; | |
2380 | memcpy(rss->rss_key, input->rss_key, QED_RSS_KEY_SIZE * sizeof(u32)); | |
2381 | ||
2382 | /* In regular scenario, we'd simply need to take input handlers. | |
2383 | * But in CMT, we'd have to split the handlers according to the | |
2384 | * engine they were configured on. We'd then have to understand | |
2385 | * whether RSS is really required, since 2-queues on CMT doesn't | |
2386 | * require RSS. | |
2387 | */ | |
2388 | if (cdev->num_hwfns == 1) { | |
2389 | memcpy(rss->rss_ind_table, | |
2390 | input->rss_ind_table, | |
2391 | QED_RSS_IND_TABLE_SIZE * sizeof(void *)); | |
2392 | rss->rss_table_size_log = 7; | |
2393 | return 0; | |
2394 | } | |
2395 | ||
2396 | /* Start by copying the non-spcific information to the 2nd copy */ | |
2397 | memcpy(&rss[1], &rss[0], sizeof(struct qed_rss_params)); | |
2398 | ||
2399 | /* CMT should be round-robin */ | |
2400 | for (i = 0; i < QED_RSS_IND_TABLE_SIZE; i++) { | |
2401 | struct qed_queue_cid *cid = input->rss_ind_table[i]; | |
2402 | struct qed_rss_params *t_rss; | |
2403 | ||
2404 | if (cid->p_owner == QED_LEADING_HWFN(cdev)) | |
2405 | t_rss = &rss[0]; | |
2406 | else | |
2407 | t_rss = &rss[1]; | |
2408 | ||
2409 | t_rss->rss_ind_table[i / cdev->num_hwfns] = cid; | |
2410 | } | |
2411 | ||
2412 | /* Make sure RSS is actually required */ | |
2413 | for_each_hwfn(cdev, fn) { | |
2414 | for (i = 1; i < QED_RSS_IND_TABLE_SIZE / cdev->num_hwfns; i++) { | |
2415 | if (rss[fn].rss_ind_table[i] != | |
2416 | rss[fn].rss_ind_table[0]) | |
2417 | break; | |
2418 | } | |
2419 | if (i == QED_RSS_IND_TABLE_SIZE / cdev->num_hwfns) { | |
2420 | DP_VERBOSE(cdev, NETIF_MSG_IFUP, | |
2421 | "CMT - 1 queue per-hwfn; Disabling RSS\n"); | |
2422 | return -EINVAL; | |
2423 | } | |
2424 | rss[fn].rss_table_size_log = 6; | |
2425 | } | |
2426 | ||
2427 | return 0; | |
2428 | } | |
2429 | ||
cee4d264 MC |
2430 | static int qed_update_vport(struct qed_dev *cdev, |
2431 | struct qed_update_vport_params *params) | |
2432 | { | |
2433 | struct qed_sp_vport_update_params sp_params; | |
f29ffdb6 MY |
2434 | struct qed_rss_params *rss; |
2435 | int rc = 0, i; | |
cee4d264 MC |
2436 | |
2437 | if (!cdev) | |
2438 | return -ENODEV; | |
2439 | ||
fad953ce | 2440 | rss = vzalloc(array_size(sizeof(*rss), cdev->num_hwfns)); |
f29ffdb6 MY |
2441 | if (!rss) |
2442 | return -ENOMEM; | |
2443 | ||
cee4d264 | 2444 | memset(&sp_params, 0, sizeof(sp_params)); |
cee4d264 MC |
2445 | |
2446 | /* Translate protocol params into sp params */ | |
2447 | sp_params.vport_id = params->vport_id; | |
1a635e48 YM |
2448 | sp_params.update_vport_active_rx_flg = params->update_vport_active_flg; |
2449 | sp_params.update_vport_active_tx_flg = params->update_vport_active_flg; | |
cee4d264 MC |
2450 | sp_params.vport_active_rx_flg = params->vport_active_flg; |
2451 | sp_params.vport_active_tx_flg = params->vport_active_flg; | |
831bfb0e YM |
2452 | sp_params.update_tx_switching_flg = params->update_tx_switching_flg; |
2453 | sp_params.tx_switching_flg = params->tx_switching_flg; | |
3f9b4a69 YM |
2454 | sp_params.accept_any_vlan = params->accept_any_vlan; |
2455 | sp_params.update_accept_any_vlan_flg = | |
2456 | params->update_accept_any_vlan_flg; | |
cee4d264 | 2457 | |
f29ffdb6 MY |
2458 | /* Prepare the RSS configuration */ |
2459 | if (params->update_rss_flg) | |
2460 | if (qed_update_vport_rss(cdev, ¶ms->rss_params, rss)) | |
cee4d264 | 2461 | params->update_rss_flg = 0; |
cee4d264 MC |
2462 | |
2463 | for_each_hwfn(cdev, i) { | |
2464 | struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; | |
2465 | ||
f29ffdb6 MY |
2466 | if (params->update_rss_flg) |
2467 | sp_params.rss_params = &rss[i]; | |
2468 | ||
cee4d264 MC |
2469 | sp_params.opaque_fid = p_hwfn->hw_info.opaque_fid; |
2470 | rc = qed_sp_vport_update(p_hwfn, &sp_params, | |
2471 | QED_SPQ_MODE_EBLOCK, | |
2472 | NULL); | |
2473 | if (rc) { | |
2474 | DP_ERR(cdev, "Failed to update VPORT\n"); | |
f29ffdb6 | 2475 | goto out; |
cee4d264 MC |
2476 | } |
2477 | ||
2478 | DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP), | |
2479 | "Updated V-PORT %d: active_flag %d [update %d]\n", | |
2480 | params->vport_id, params->vport_active_flg, | |
2481 | params->update_vport_active_flg); | |
2482 | } | |
2483 | ||
f29ffdb6 MY |
2484 | out: |
2485 | vfree(rss); | |
2486 | return rc; | |
cee4d264 MC |
2487 | } |
2488 | ||
2489 | static int qed_start_rxq(struct qed_dev *cdev, | |
3da7a37a MY |
2490 | u8 rss_num, |
2491 | struct qed_queue_start_common_params *p_params, | |
cee4d264 MC |
2492 | u16 bd_max_bytes, |
2493 | dma_addr_t bd_chain_phys_addr, | |
2494 | dma_addr_t cqe_pbl_addr, | |
2495 | u16 cqe_pbl_size, | |
3da7a37a | 2496 | struct qed_rxq_start_ret_params *ret_params) |
cee4d264 | 2497 | { |
cee4d264 | 2498 | struct qed_hwfn *p_hwfn; |
1a635e48 | 2499 | int rc, hwfn_index; |
cee4d264 | 2500 | |
3da7a37a | 2501 | hwfn_index = rss_num % cdev->num_hwfns; |
cee4d264 MC |
2502 | p_hwfn = &cdev->hwfns[hwfn_index]; |
2503 | ||
3da7a37a MY |
2504 | p_params->queue_id = p_params->queue_id / cdev->num_hwfns; |
2505 | p_params->stats_id = p_params->vport_id; | |
cee4d264 | 2506 | |
3da7a37a MY |
2507 | rc = qed_eth_rx_queue_start(p_hwfn, |
2508 | p_hwfn->hw_info.opaque_fid, | |
2509 | p_params, | |
2510 | bd_max_bytes, | |
2511 | bd_chain_phys_addr, | |
2512 | cqe_pbl_addr, cqe_pbl_size, ret_params); | |
cee4d264 | 2513 | if (rc) { |
3da7a37a | 2514 | DP_ERR(cdev, "Failed to start RXQ#%d\n", p_params->queue_id); |
cee4d264 MC |
2515 | return rc; |
2516 | } | |
2517 | ||
2518 | DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP), | |
f604b17d | 2519 | "Started RX-Q %d [rss_num %d] on V-PORT %d and SB igu %d\n", |
3da7a37a | 2520 | p_params->queue_id, rss_num, p_params->vport_id, |
f604b17d | 2521 | p_params->p_sb->igu_sb_id); |
cee4d264 MC |
2522 | |
2523 | return 0; | |
2524 | } | |
2525 | ||
3da7a37a | 2526 | static int qed_stop_rxq(struct qed_dev *cdev, u8 rss_id, void *handle) |
cee4d264 MC |
2527 | { |
2528 | int rc, hwfn_index; | |
2529 | struct qed_hwfn *p_hwfn; | |
2530 | ||
3da7a37a MY |
2531 | hwfn_index = rss_id % cdev->num_hwfns; |
2532 | p_hwfn = &cdev->hwfns[hwfn_index]; | |
cee4d264 | 2533 | |
3da7a37a | 2534 | rc = qed_eth_rx_queue_stop(p_hwfn, handle, false, false); |
cee4d264 | 2535 | if (rc) { |
3da7a37a | 2536 | DP_ERR(cdev, "Failed to stop RXQ#%02x\n", rss_id); |
cee4d264 MC |
2537 | return rc; |
2538 | } | |
2539 | ||
2540 | return 0; | |
2541 | } | |
2542 | ||
2543 | static int qed_start_txq(struct qed_dev *cdev, | |
3da7a37a | 2544 | u8 rss_num, |
cee4d264 MC |
2545 | struct qed_queue_start_common_params *p_params, |
2546 | dma_addr_t pbl_addr, | |
2547 | u16 pbl_size, | |
3da7a37a | 2548 | struct qed_txq_start_ret_params *ret_params) |
cee4d264 MC |
2549 | { |
2550 | struct qed_hwfn *p_hwfn; | |
2551 | int rc, hwfn_index; | |
2552 | ||
3da7a37a MY |
2553 | hwfn_index = rss_num % cdev->num_hwfns; |
2554 | p_hwfn = &cdev->hwfns[hwfn_index]; | |
2555 | p_params->queue_id = p_params->queue_id / cdev->num_hwfns; | |
2556 | p_params->stats_id = p_params->vport_id; | |
cee4d264 | 2557 | |
3da7a37a MY |
2558 | rc = qed_eth_tx_queue_start(p_hwfn, |
2559 | p_hwfn->hw_info.opaque_fid, | |
5e7baf0f | 2560 | p_params, p_params->tc, |
3da7a37a | 2561 | pbl_addr, pbl_size, ret_params); |
cee4d264 MC |
2562 | |
2563 | if (rc) { | |
2564 | DP_ERR(cdev, "Failed to start TXQ#%d\n", p_params->queue_id); | |
2565 | return rc; | |
2566 | } | |
2567 | ||
2568 | DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP), | |
f604b17d | 2569 | "Started TX-Q %d [rss_num %d] on V-PORT %d and SB igu %d\n", |
3da7a37a | 2570 | p_params->queue_id, rss_num, p_params->vport_id, |
f604b17d | 2571 | p_params->p_sb->igu_sb_id); |
cee4d264 MC |
2572 | |
2573 | return 0; | |
2574 | } | |
2575 | ||
2576 | #define QED_HW_STOP_RETRY_LIMIT (10) | |
2577 | static int qed_fastpath_stop(struct qed_dev *cdev) | |
2578 | { | |
15582962 RV |
2579 | int rc; |
2580 | ||
2581 | rc = qed_hw_stop_fastpath(cdev); | |
2582 | if (rc) { | |
2583 | DP_ERR(cdev, "Failed to stop Fastpath\n"); | |
2584 | return rc; | |
2585 | } | |
cee4d264 MC |
2586 | |
2587 | return 0; | |
2588 | } | |
2589 | ||
3da7a37a | 2590 | static int qed_stop_txq(struct qed_dev *cdev, u8 rss_id, void *handle) |
cee4d264 MC |
2591 | { |
2592 | struct qed_hwfn *p_hwfn; | |
2593 | int rc, hwfn_index; | |
2594 | ||
3da7a37a MY |
2595 | hwfn_index = rss_id % cdev->num_hwfns; |
2596 | p_hwfn = &cdev->hwfns[hwfn_index]; | |
cee4d264 | 2597 | |
3da7a37a | 2598 | rc = qed_eth_tx_queue_stop(p_hwfn, handle); |
cee4d264 | 2599 | if (rc) { |
3da7a37a | 2600 | DP_ERR(cdev, "Failed to stop TXQ#%02x\n", rss_id); |
cee4d264 MC |
2601 | return rc; |
2602 | } | |
2603 | ||
2604 | return 0; | |
2605 | } | |
2606 | ||
464f6645 MC |
2607 | static int qed_tunn_configure(struct qed_dev *cdev, |
2608 | struct qed_tunn_params *tunn_params) | |
2609 | { | |
19968430 | 2610 | struct qed_tunnel_info tunn_info; |
464f6645 MC |
2611 | int i, rc; |
2612 | ||
2613 | memset(&tunn_info, 0, sizeof(tunn_info)); | |
19968430 CM |
2614 | if (tunn_params->update_vxlan_port) { |
2615 | tunn_info.vxlan_port.b_update_port = true; | |
2616 | tunn_info.vxlan_port.port = tunn_params->vxlan_port; | |
464f6645 MC |
2617 | } |
2618 | ||
19968430 CM |
2619 | if (tunn_params->update_geneve_port) { |
2620 | tunn_info.geneve_port.b_update_port = true; | |
2621 | tunn_info.geneve_port.port = tunn_params->geneve_port; | |
464f6645 MC |
2622 | } |
2623 | ||
2624 | for_each_hwfn(cdev, i) { | |
2625 | struct qed_hwfn *hwfn = &cdev->hwfns[i]; | |
4f64675f | 2626 | struct qed_ptt *p_ptt; |
97379f15 CM |
2627 | struct qed_tunnel_info *tun; |
2628 | ||
2629 | tun = &hwfn->cdev->tunnel; | |
4f64675f MC |
2630 | if (IS_PF(cdev)) { |
2631 | p_ptt = qed_ptt_acquire(hwfn); | |
2632 | if (!p_ptt) | |
2633 | return -EAGAIN; | |
2634 | } else { | |
2635 | p_ptt = NULL; | |
2636 | } | |
464f6645 | 2637 | |
4f64675f | 2638 | rc = qed_sp_pf_update_tunn_cfg(hwfn, p_ptt, &tunn_info, |
464f6645 | 2639 | QED_SPQ_MODE_EBLOCK, NULL); |
4f64675f MC |
2640 | if (rc) { |
2641 | if (IS_PF(cdev)) | |
2642 | qed_ptt_release(hwfn, p_ptt); | |
464f6645 | 2643 | return rc; |
4f64675f | 2644 | } |
97379f15 CM |
2645 | |
2646 | if (IS_PF_SRIOV(hwfn)) { | |
2647 | u16 vxlan_port, geneve_port; | |
2648 | int j; | |
2649 | ||
2650 | vxlan_port = tun->vxlan_port.port; | |
2651 | geneve_port = tun->geneve_port.port; | |
2652 | ||
2653 | qed_for_each_vf(hwfn, j) { | |
2654 | qed_iov_bulletin_set_udp_ports(hwfn, j, | |
2655 | vxlan_port, | |
2656 | geneve_port); | |
2657 | } | |
2658 | ||
2659 | qed_schedule_iov(hwfn, QED_IOV_WQ_BULLETIN_UPDATE_FLAG); | |
2660 | } | |
4f64675f MC |
2661 | if (IS_PF(cdev)) |
2662 | qed_ptt_release(hwfn, p_ptt); | |
464f6645 MC |
2663 | } |
2664 | ||
2665 | return 0; | |
2666 | } | |
2667 | ||
cee4d264 MC |
2668 | static int qed_configure_filter_rx_mode(struct qed_dev *cdev, |
2669 | enum qed_filter_rx_mode_type type) | |
2670 | { | |
2671 | struct qed_filter_accept_flags accept_flags; | |
2672 | ||
2673 | memset(&accept_flags, 0, sizeof(accept_flags)); | |
2674 | ||
1a635e48 YM |
2675 | accept_flags.update_rx_mode_config = 1; |
2676 | accept_flags.update_tx_mode_config = 1; | |
2677 | accept_flags.rx_accept_filter = QED_ACCEPT_UCAST_MATCHED | | |
2678 | QED_ACCEPT_MCAST_MATCHED | | |
2679 | QED_ACCEPT_BCAST; | |
cee4d264 MC |
2680 | accept_flags.tx_accept_filter = QED_ACCEPT_UCAST_MATCHED | |
2681 | QED_ACCEPT_MCAST_MATCHED | | |
2682 | QED_ACCEPT_BCAST; | |
2683 | ||
88067876 | 2684 | if (type == QED_FILTER_RX_MODE_TYPE_PROMISC) { |
cee4d264 MC |
2685 | accept_flags.rx_accept_filter |= QED_ACCEPT_UCAST_UNMATCHED | |
2686 | QED_ACCEPT_MCAST_UNMATCHED; | |
88067876 MY |
2687 | accept_flags.tx_accept_filter |= QED_ACCEPT_MCAST_UNMATCHED; |
2688 | } else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC) { | |
cee4d264 | 2689 | accept_flags.rx_accept_filter |= QED_ACCEPT_MCAST_UNMATCHED; |
88067876 MY |
2690 | accept_flags.tx_accept_filter |= QED_ACCEPT_MCAST_UNMATCHED; |
2691 | } | |
cee4d264 | 2692 | |
3f9b4a69 | 2693 | return qed_filter_accept_cmd(cdev, 0, accept_flags, false, false, |
cee4d264 MC |
2694 | QED_SPQ_MODE_CB, NULL); |
2695 | } | |
2696 | ||
2697 | static int qed_configure_filter_ucast(struct qed_dev *cdev, | |
2698 | struct qed_filter_ucast_params *params) | |
2699 | { | |
2700 | struct qed_filter_ucast ucast; | |
2701 | ||
2702 | if (!params->vlan_valid && !params->mac_valid) { | |
1a635e48 YM |
2703 | DP_NOTICE(cdev, |
2704 | "Tried configuring a unicast filter, but both MAC and VLAN are not set\n"); | |
cee4d264 MC |
2705 | return -EINVAL; |
2706 | } | |
2707 | ||
2708 | memset(&ucast, 0, sizeof(ucast)); | |
2709 | switch (params->type) { | |
2710 | case QED_FILTER_XCAST_TYPE_ADD: | |
2711 | ucast.opcode = QED_FILTER_ADD; | |
2712 | break; | |
2713 | case QED_FILTER_XCAST_TYPE_DEL: | |
2714 | ucast.opcode = QED_FILTER_REMOVE; | |
2715 | break; | |
2716 | case QED_FILTER_XCAST_TYPE_REPLACE: | |
2717 | ucast.opcode = QED_FILTER_REPLACE; | |
2718 | break; | |
2719 | default: | |
2720 | DP_NOTICE(cdev, "Unknown unicast filter type %d\n", | |
2721 | params->type); | |
2722 | } | |
2723 | ||
2724 | if (params->vlan_valid && params->mac_valid) { | |
2725 | ucast.type = QED_FILTER_MAC_VLAN; | |
2726 | ether_addr_copy(ucast.mac, params->mac); | |
2727 | ucast.vlan = params->vlan; | |
2728 | } else if (params->mac_valid) { | |
2729 | ucast.type = QED_FILTER_MAC; | |
2730 | ether_addr_copy(ucast.mac, params->mac); | |
2731 | } else { | |
2732 | ucast.type = QED_FILTER_VLAN; | |
2733 | ucast.vlan = params->vlan; | |
2734 | } | |
2735 | ||
2736 | ucast.is_rx_filter = true; | |
2737 | ucast.is_tx_filter = true; | |
2738 | ||
2739 | return qed_filter_ucast_cmd(cdev, &ucast, QED_SPQ_MODE_CB, NULL); | |
2740 | } | |
2741 | ||
2742 | static int qed_configure_filter_mcast(struct qed_dev *cdev, | |
2743 | struct qed_filter_mcast_params *params) | |
2744 | { | |
2745 | struct qed_filter_mcast mcast; | |
2746 | int i; | |
2747 | ||
2748 | memset(&mcast, 0, sizeof(mcast)); | |
2749 | switch (params->type) { | |
2750 | case QED_FILTER_XCAST_TYPE_ADD: | |
2751 | mcast.opcode = QED_FILTER_ADD; | |
2752 | break; | |
2753 | case QED_FILTER_XCAST_TYPE_DEL: | |
2754 | mcast.opcode = QED_FILTER_REMOVE; | |
2755 | break; | |
2756 | default: | |
2757 | DP_NOTICE(cdev, "Unknown multicast filter type %d\n", | |
2758 | params->type); | |
2759 | } | |
2760 | ||
2761 | mcast.num_mc_addrs = params->num; | |
2762 | for (i = 0; i < mcast.num_mc_addrs; i++) | |
2763 | ether_addr_copy(mcast.mac[i], params->mac[i]); | |
2764 | ||
1a635e48 | 2765 | return qed_filter_mcast_cmd(cdev, &mcast, QED_SPQ_MODE_CB, NULL); |
cee4d264 MC |
2766 | } |
2767 | ||
2768 | static int qed_configure_filter(struct qed_dev *cdev, | |
2769 | struct qed_filter_params *params) | |
2770 | { | |
2771 | enum qed_filter_rx_mode_type accept_flags; | |
2772 | ||
2773 | switch (params->type) { | |
2774 | case QED_FILTER_TYPE_UCAST: | |
2775 | return qed_configure_filter_ucast(cdev, ¶ms->filter.ucast); | |
2776 | case QED_FILTER_TYPE_MCAST: | |
2777 | return qed_configure_filter_mcast(cdev, ¶ms->filter.mcast); | |
2778 | case QED_FILTER_TYPE_RX_MODE: | |
2779 | accept_flags = params->filter.accept_flags; | |
2780 | return qed_configure_filter_rx_mode(cdev, accept_flags); | |
2781 | default: | |
1a635e48 | 2782 | DP_NOTICE(cdev, "Unknown filter type %d\n", (int)params->type); |
cee4d264 MC |
2783 | return -EINVAL; |
2784 | } | |
2785 | } | |
2786 | ||
da090917 TT |
2787 | static int qed_configure_arfs_searcher(struct qed_dev *cdev, |
2788 | enum qed_filter_config_mode mode) | |
d51e4af5 CM |
2789 | { |
2790 | struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); | |
2791 | struct qed_arfs_config_params arfs_config_params; | |
2792 | ||
2793 | memset(&arfs_config_params, 0, sizeof(arfs_config_params)); | |
2794 | arfs_config_params.tcp = true; | |
2795 | arfs_config_params.udp = true; | |
2796 | arfs_config_params.ipv4 = true; | |
2797 | arfs_config_params.ipv6 = true; | |
da090917 | 2798 | arfs_config_params.mode = mode; |
d51e4af5 CM |
2799 | qed_arfs_mode_configure(p_hwfn, p_hwfn->p_arfs_ptt, |
2800 | &arfs_config_params); | |
2801 | return 0; | |
2802 | } | |
2803 | ||
2804 | static void | |
2805 | qed_arfs_sp_response_handler(struct qed_hwfn *p_hwfn, | |
da090917 TT |
2806 | void *cookie, |
2807 | union event_ring_data *data, u8 fw_return_code) | |
d51e4af5 CM |
2808 | { |
2809 | struct qed_common_cb_ops *op = p_hwfn->cdev->protocol_ops.common; | |
2810 | void *dev = p_hwfn->cdev->ops_cookie; | |
2811 | ||
2812 | op->arfs_filter_op(dev, cookie, fw_return_code); | |
2813 | } | |
2814 | ||
da090917 TT |
2815 | static int |
2816 | qed_ntuple_arfs_filter_config(struct qed_dev *cdev, | |
2817 | void *cookie, | |
2818 | struct qed_ntuple_filter_params *params) | |
d51e4af5 CM |
2819 | { |
2820 | struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); | |
2821 | struct qed_spq_comp_cb cb; | |
2822 | int rc = -EINVAL; | |
2823 | ||
2824 | cb.function = qed_arfs_sp_response_handler; | |
2825 | cb.cookie = cookie; | |
2826 | ||
da090917 TT |
2827 | if (params->b_is_vf) { |
2828 | if (!qed_iov_is_valid_vfid(p_hwfn, params->vf_id, false, | |
2829 | false)) { | |
2830 | DP_INFO(p_hwfn, "vfid 0x%02x is out of bounds\n", | |
2831 | params->vf_id); | |
2832 | return rc; | |
2833 | } | |
2834 | ||
2835 | params->vport_id = params->vf_id + 1; | |
2836 | params->qid = QED_RFS_NTUPLE_QID_RSS; | |
2837 | } | |
2838 | ||
2839 | rc = qed_configure_rfs_ntuple_filter(p_hwfn, &cb, params); | |
d51e4af5 CM |
2840 | if (rc) |
2841 | DP_NOTICE(p_hwfn, | |
2842 | "Failed to issue a-RFS filter configuration\n"); | |
2843 | else | |
2844 | DP_VERBOSE(p_hwfn, NETIF_MSG_DRV, | |
2845 | "Successfully issued a-RFS filter configuration\n"); | |
2846 | ||
2847 | return rc; | |
2848 | } | |
2849 | ||
bf5a94bf RV |
2850 | static int qed_get_coalesce(struct qed_dev *cdev, u16 *coal, void *handle) |
2851 | { | |
2852 | struct qed_queue_cid *p_cid = handle; | |
2853 | struct qed_hwfn *p_hwfn; | |
2854 | int rc; | |
2855 | ||
2856 | p_hwfn = p_cid->p_owner; | |
2857 | rc = qed_get_queue_coalesce(p_hwfn, coal, handle); | |
2858 | if (rc) | |
9e4a5613 | 2859 | DP_NOTICE(p_hwfn, "Unable to read queue coalescing\n"); |
bf5a94bf RV |
2860 | |
2861 | return rc; | |
2862 | } | |
2863 | ||
cee4d264 | 2864 | static int qed_fp_cqe_completion(struct qed_dev *dev, |
1a635e48 | 2865 | u8 rss_id, struct eth_slow_path_rx_cqe *cqe) |
cee4d264 MC |
2866 | { |
2867 | return qed_eth_cqe_completion(&dev->hwfns[rss_id % dev->num_hwfns], | |
2868 | cqe); | |
2869 | } | |
2870 | ||
809c45a0 SS |
2871 | static int qed_req_bulletin_update_mac(struct qed_dev *cdev, u8 *mac) |
2872 | { | |
2873 | int i, ret; | |
2874 | ||
2875 | if (IS_PF(cdev)) | |
2876 | return 0; | |
2877 | ||
2878 | for_each_hwfn(cdev, i) { | |
2879 | struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; | |
2880 | ||
2881 | ret = qed_vf_pf_bulletin_update_mac(p_hwfn, mac); | |
2882 | if (ret) | |
2883 | return ret; | |
2884 | } | |
2885 | ||
2886 | return 0; | |
2887 | } | |
2888 | ||
0b55e27d YM |
2889 | #ifdef CONFIG_QED_SRIOV |
2890 | extern const struct qed_iov_hv_ops qed_iov_ops_pass; | |
2891 | #endif | |
2892 | ||
a1d8d8a5 SRK |
2893 | #ifdef CONFIG_DCB |
2894 | extern const struct qed_eth_dcbnl_ops qed_dcbnl_ops_pass; | |
2895 | #endif | |
2896 | ||
c78c70fa SRK |
2897 | extern const struct qed_eth_ptp_ops qed_ptp_ops_pass; |
2898 | ||
25c089d7 YM |
2899 | static const struct qed_eth_ops qed_eth_ops_pass = { |
2900 | .common = &qed_common_ops_pass, | |
0b55e27d YM |
2901 | #ifdef CONFIG_QED_SRIOV |
2902 | .iov = &qed_iov_ops_pass, | |
a1d8d8a5 SRK |
2903 | #endif |
2904 | #ifdef CONFIG_DCB | |
2905 | .dcb = &qed_dcbnl_ops_pass, | |
0b55e27d | 2906 | #endif |
c78c70fa | 2907 | .ptp = &qed_ptp_ops_pass, |
25c089d7 | 2908 | .fill_dev_info = &qed_fill_eth_dev_info, |
cc875c2e | 2909 | .register_ops = &qed_register_eth_ops, |
eff16960 | 2910 | .check_mac = &qed_check_mac, |
cee4d264 MC |
2911 | .vport_start = &qed_start_vport, |
2912 | .vport_stop = &qed_stop_vport, | |
2913 | .vport_update = &qed_update_vport, | |
2914 | .q_rx_start = &qed_start_rxq, | |
2915 | .q_rx_stop = &qed_stop_rxq, | |
2916 | .q_tx_start = &qed_start_txq, | |
2917 | .q_tx_stop = &qed_stop_txq, | |
2918 | .filter_config = &qed_configure_filter, | |
2919 | .fastpath_stop = &qed_fastpath_stop, | |
2920 | .eth_cqe_completion = &qed_fp_cqe_completion, | |
9df2ed04 | 2921 | .get_vport_stats = &qed_get_vport_stats, |
464f6645 | 2922 | .tunn_config = &qed_tunn_configure, |
d51e4af5 CM |
2923 | .ntuple_filter_config = &qed_ntuple_arfs_filter_config, |
2924 | .configure_arfs_searcher = &qed_configure_arfs_searcher, | |
bf5a94bf | 2925 | .get_coalesce = &qed_get_coalesce, |
809c45a0 | 2926 | .req_bulletin_update_mac = &qed_req_bulletin_update_mac, |
25c089d7 YM |
2927 | }; |
2928 | ||
95114344 | 2929 | const struct qed_eth_ops *qed_get_eth_ops(void) |
25c089d7 | 2930 | { |
25c089d7 YM |
2931 | return &qed_eth_ops_pass; |
2932 | } | |
2933 | EXPORT_SYMBOL(qed_get_eth_ops); | |
2934 | ||
2935 | void qed_put_eth_ops(void) | |
2936 | { | |
2937 | /* TODO - reference count for module? */ | |
2938 | } | |
2939 | EXPORT_SYMBOL(qed_put_eth_ops); |