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Merge tag 'sh-pfc-for-v5.1-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git...
[mirror_ubuntu-focal-kernel.git] / drivers / net / ethernet / qlogic / qed / qed_l2.c
CommitLineData
25c089d7 1/* QLogic qed NIC Driver
e8f1cb50 2 * Copyright (c) 2015-2017 QLogic Corporation
25c089d7 3 *
e8f1cb50
MY		 4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
25c089d7
YM		 31 */
32
33#include <linux/types.h>
34#include <asm/byteorder.h>
35#include <asm/param.h>
36#include <linux/delay.h>
37#include <linux/dma-mapping.h>
38#include <linux/etherdevice.h>
39#include <linux/interrupt.h>
40#include <linux/kernel.h>
41#include <linux/module.h>
42#include <linux/pci.h>
43#include <linux/slab.h>
44#include <linux/stddef.h>
45#include <linux/string.h>
25c089d7
YM		 46#include <linux/workqueue.h>
47#include <linux/bitops.h>
48#include <linux/bug.h>
3da7a37a 49#include <linux/vmalloc.h>
25c089d7
YM		 50#include "qed.h"
51#include <linux/qed/qed_chain.h>
52#include "qed_cxt.h"
53#include "qed_dev_api.h"
54#include <linux/qed/qed_eth_if.h>
55#include "qed_hsi.h"
56#include "qed_hw.h"
57#include "qed_int.h"
dacd88d6 58#include "qed_l2.h"
86622ee7 59#include "qed_mcp.h"
25c089d7
YM		 60#include "qed_reg_addr.h"
61#include "qed_sp.h"
1408cc1f 62#include "qed_sriov.h"
25c089d7 63
088c8618 64
cee4d264
MC		 65#define QED_MAX_SGES_NUM 16
66#define CRC32_POLY 0x1edc6f41
67
0db711bb
MY		 68struct qed_l2_info {
69 u32 queues;
70 unsigned long **pp_qid_usage;
71
72 /* The lock is meant to synchronize access to the qid usage */
73 struct mutex lock;
74};
75
76int qed_l2_alloc(struct qed_hwfn *p_hwfn)
77{
78 struct qed_l2_info *p_l2_info;
79 unsigned long **pp_qids;
80 u32 i;
81
c851a9dc 82 if (!QED_IS_L2_PERSONALITY(p_hwfn))
0db711bb
MY		 83 return 0;
84
85 p_l2_info = kzalloc(sizeof(*p_l2_info), GFP_KERNEL);
86 if (!p_l2_info)
87 return -ENOMEM;
88 p_hwfn->p_l2_info = p_l2_info;
89
90 if (IS_PF(p_hwfn->cdev)) {
91 p_l2_info->queues = RESC_NUM(p_hwfn, QED_L2_QUEUE);
92 } else {
93 u8 rx = 0, tx = 0;
94
95 qed_vf_get_num_rxqs(p_hwfn, &rx);
96 qed_vf_get_num_txqs(p_hwfn, &tx);
97
98 p_l2_info->queues = max_t(u8, rx, tx);
99 }
100
6396bb22 101 pp_qids = kcalloc(p_l2_info->queues, sizeof(unsigned long *),
0db711bb
MY		 102 GFP_KERNEL);
103 if (!pp_qids)
104 return -ENOMEM;
105 p_l2_info->pp_qid_usage = pp_qids;
106
107 for (i = 0; i < p_l2_info->queues; i++) {
108 pp_qids[i] = kzalloc(MAX_QUEUES_PER_QZONE / 8, GFP_KERNEL);
109 if (!pp_qids[i])
110 return -ENOMEM;
111 }
112
113 return 0;
114}
115
116void qed_l2_setup(struct qed_hwfn *p_hwfn)
117{
af6858ee 118 if (!QED_IS_L2_PERSONALITY(p_hwfn))
0db711bb
MY		 119 return;
120
121 mutex_init(&p_hwfn->p_l2_info->lock);
122}
123
124void qed_l2_free(struct qed_hwfn *p_hwfn)
125{
126 u32 i;
127
af6858ee 128 if (!QED_IS_L2_PERSONALITY(p_hwfn))
0db711bb
MY		 129 return;
130
131 if (!p_hwfn->p_l2_info)
132 return;
133
134 if (!p_hwfn->p_l2_info->pp_qid_usage)
135 goto out_l2_info;
136
137 /* Free until hit first uninitialized entry */
138 for (i = 0; i < p_hwfn->p_l2_info->queues; i++) {
139 if (!p_hwfn->p_l2_info->pp_qid_usage[i])
140 break;
141 kfree(p_hwfn->p_l2_info->pp_qid_usage[i]);
142 }
143
144 kfree(p_hwfn->p_l2_info->pp_qid_usage);
145
146out_l2_info:
147 kfree(p_hwfn->p_l2_info);
148 p_hwfn->p_l2_info = NULL;
149}
150
bbe3f233
MY		 151static bool qed_eth_queue_qid_usage_add(struct qed_hwfn *p_hwfn,
152 struct qed_queue_cid *p_cid)
153{
154 struct qed_l2_info *p_l2_info = p_hwfn->p_l2_info;
155 u16 queue_id = p_cid->rel.queue_id;
156 bool b_rc = true;
157 u8 first;
158
159 mutex_lock(&p_l2_info->lock);
160
0331402a 161 if (queue_id >= p_l2_info->queues) {
bbe3f233
MY		 162 DP_NOTICE(p_hwfn,
163 "Requested to increase usage for qzone %04x out of %08x\n",
164 queue_id, p_l2_info->queues);
165 b_rc = false;
166 goto out;
167 }
168
169 first = (u8)find_first_zero_bit(p_l2_info->pp_qid_usage[queue_id],
170 MAX_QUEUES_PER_QZONE);
171 if (first >= MAX_QUEUES_PER_QZONE) {
172 b_rc = false;
173 goto out;
174 }
175
176 __set_bit(first, p_l2_info->pp_qid_usage[queue_id]);
177 p_cid->qid_usage_idx = first;
178
179out:
180 mutex_unlock(&p_l2_info->lock);
181 return b_rc;
182}
183
184static void qed_eth_queue_qid_usage_del(struct qed_hwfn *p_hwfn,
185 struct qed_queue_cid *p_cid)
186{
187 mutex_lock(&p_hwfn->p_l2_info->lock);
188
189 clear_bit(p_cid->qid_usage_idx,
190 p_hwfn->p_l2_info->pp_qid_usage[p_cid->rel.queue_id]);
191
192 mutex_unlock(&p_hwfn->p_l2_info->lock);
193}
194
3da7a37a
MY		 195void qed_eth_queue_cid_release(struct qed_hwfn *p_hwfn,
196 struct qed_queue_cid *p_cid)
197{
08bc8f15
MY		 198 bool b_legacy_vf = !!(p_cid->vf_legacy & QED_QCID_LEGACY_VF_CID);
199
200 if (IS_PF(p_hwfn->cdev) && !b_legacy_vf)
201 _qed_cxt_release_cid(p_hwfn, p_cid->cid, p_cid->vfid);
bbe3f233
MY		 202
203 /* For PF's VFs we maintain the index inside queue-zone in IOV */
204 if (p_cid->vfid == QED_QUEUE_CID_SELF)
205 qed_eth_queue_qid_usage_del(p_hwfn, p_cid);
206
3da7a37a
MY		 207 vfree(p_cid);
208}
209
210/* The internal is only meant to be directly called by PFs initializeing CIDs
211 * for their VFs.
212 */
3946497a 213static struct qed_queue_cid *
3da7a37a
MY		 214_qed_eth_queue_to_cid(struct qed_hwfn *p_hwfn,
215 u16 opaque_fid,
216 u32 cid,
3946497a 217 struct qed_queue_start_common_params *p_params,
007bc371 218 bool b_is_rx,
3946497a 219 struct qed_queue_cid_vf_params *p_vf_params)
3da7a37a 220{
3da7a37a
MY		 221 struct qed_queue_cid *p_cid;
222 int rc;
223
5f58dff9 224 p_cid = vzalloc(sizeof(*p_cid));
3da7a37a
MY		 225 if (!p_cid)
226 return NULL;
3da7a37a
MY		 227
228 p_cid->opaque_fid = opaque_fid;
229 p_cid->cid = cid;
f29ffdb6 230 p_cid->p_owner = p_hwfn;
3da7a37a 231
f604b17d
MY		 232 /* Fill in parameters */
233 p_cid->rel.vport_id = p_params->vport_id;
234 p_cid->rel.queue_id = p_params->queue_id;
235 p_cid->rel.stats_id = p_params->stats_id;
236 p_cid->sb_igu_id = p_params->p_sb->igu_sb_id;
007bc371 237 p_cid->b_is_rx = b_is_rx;
f604b17d
MY		 238 p_cid->sb_idx = p_params->sb_idx;
239
3946497a
MY		 240 /* Fill-in bits related to VFs' queues if information was provided */
241 if (p_vf_params) {
242 p_cid->vfid = p_vf_params->vfid;
243 p_cid->vf_qid = p_vf_params->vf_qid;
3b19f478 244 p_cid->vf_legacy = p_vf_params->vf_legacy;
3946497a
MY		 245 } else {
246 p_cid->vfid = QED_QUEUE_CID_SELF;
247 }
248
3da7a37a
MY		 249 /* Don't try calculating the absolute indices for VFs */
250 if (IS_VF(p_hwfn->cdev)) {
251 p_cid->abs = p_cid->rel;
252 goto out;
253 }
254
255 /* Calculate the engine-absolute indices of the resources.
256 * This would guarantee they're valid later on.
257 * In some cases [SBs] we already have the right values.
258 */
259 rc = qed_fw_vport(p_hwfn, p_cid->rel.vport_id, &p_cid->abs.vport_id);
260 if (rc)
261 goto fail;
262
263 rc = qed_fw_l2_queue(p_hwfn, p_cid->rel.queue_id, &p_cid->abs.queue_id);
264 if (rc)
265 goto fail;
266
267 /* In case of a PF configuring its VF's queues, the stats-id is already
268 * absolute [since there's a single index that's suitable per-VF].
269 */
3946497a 270 if (p_cid->vfid == QED_QUEUE_CID_SELF) {
3da7a37a
MY		 271 rc = qed_fw_vport(p_hwfn, p_cid->rel.stats_id,
272 &p_cid->abs.stats_id);
273 if (rc)
274 goto fail;
275 } else {
276 p_cid->abs.stats_id = p_cid->rel.stats_id;
277 }
278
3da7a37a 279out:
bbe3f233
MY		 280 /* VF-images have provided the qid_usage_idx on their own.
281 * Otherwise, we need to allocate a unique one.
282 */
283 if (!p_vf_params) {
284 if (!qed_eth_queue_qid_usage_add(p_hwfn, p_cid))
285 goto fail;
286 } else {
287 p_cid->qid_usage_idx = p_vf_params->qid_usage_idx;
288 }
289
3da7a37a
MY		 290 DP_VERBOSE(p_hwfn,
291 QED_MSG_SP,
bbe3f233 292 "opaque_fid: %04x CID %08x vport %02x [%02x] qzone %04x.%02x [%04x] stats %02x [%02x] SB %04x PI %02x\n",
3da7a37a
MY		 293 p_cid->opaque_fid,
294 p_cid->cid,
295 p_cid->rel.vport_id,
296 p_cid->abs.vport_id,
297 p_cid->rel.queue_id,
bbe3f233 298 p_cid->qid_usage_idx,
3da7a37a
MY		 299 p_cid->abs.queue_id,
300 p_cid->rel.stats_id,
f604b17d 301 p_cid->abs.stats_id, p_cid->sb_igu_id, p_cid->sb_idx);
3da7a37a
MY		 302
303 return p_cid;
304
305fail:
306 vfree(p_cid);
307 return NULL;
308}
309
3946497a
MY		 310struct qed_queue_cid *
311qed_eth_queue_to_cid(struct qed_hwfn *p_hwfn,
312 u16 opaque_fid,
313 struct qed_queue_start_common_params *p_params,
007bc371 314 bool b_is_rx,
3946497a 315 struct qed_queue_cid_vf_params *p_vf_params)
3da7a37a
MY		 316{
317 struct qed_queue_cid *p_cid;
08bc8f15 318 u8 vfid = QED_CXT_PF_CID;
3946497a 319 bool b_legacy_vf = false;
3da7a37a
MY		 320 u32 cid = 0;
321
08bc8f15
MY		 322 /* In case of legacy VFs, The CID can be derived from the additional
323 * VF parameters - the VF assumes queue X uses CID X, so we can simply
324 * use the vf_qid for this purpose as well.
325 */
326 if (p_vf_params) {
327 vfid = p_vf_params->vfid;
328
329 if (p_vf_params->vf_legacy & QED_QCID_LEGACY_VF_CID) {
330 b_legacy_vf = true;
331 cid = p_vf_params->vf_qid;
332 }
333 }
334
3da7a37a
MY		 335 /* Get a unique firmware CID for this queue, in case it's a PF.
336 * VF's don't need a CID as the queue configuration will be done
337 * by PF.
338 */
3946497a 339 if (IS_PF(p_hwfn->cdev) && !b_legacy_vf) {
08bc8f15
MY		 340 if (_qed_cxt_acquire_cid(p_hwfn, PROTOCOLID_ETH,
341 &cid, vfid)) {
3da7a37a
MY		 342 DP_NOTICE(p_hwfn, "Failed to acquire cid\n");
343 return NULL;
344 }
345 }
346
3946497a 347 p_cid = _qed_eth_queue_to_cid(p_hwfn, opaque_fid, cid,
007bc371 348 p_params, b_is_rx, p_vf_params);
3946497a 349 if (!p_cid && IS_PF(p_hwfn->cdev) && !b_legacy_vf)
08bc8f15 350 _qed_cxt_release_cid(p_hwfn, cid, vfid);
3da7a37a
MY		 351
352 return p_cid;
353}
354
3946497a
MY		 355static struct qed_queue_cid *
356qed_eth_queue_to_cid_pf(struct qed_hwfn *p_hwfn,
357 u16 opaque_fid,
007bc371 358 bool b_is_rx,
3946497a
MY		 359 struct qed_queue_start_common_params *p_params)
360{
007bc371 361 return qed_eth_queue_to_cid(p_hwfn, opaque_fid, p_params, b_is_rx,
3946497a
MY		 362 NULL);
363}
364
dacd88d6
YM		 365int qed_sp_eth_vport_start(struct qed_hwfn *p_hwfn,
366 struct qed_sp_vport_start_params *p_params)
cee4d264 367{
cee4d264
MC		 368 struct vport_start_ramrod_data *p_ramrod = NULL;
369 struct qed_spq_entry *p_ent = NULL;
06f56b81 370 struct qed_sp_init_data init_data;
dacd88d6 371 u8 abs_vport_id = 0;
cee4d264
MC		 372 int rc = -EINVAL;
373 u16 rx_mode = 0;
cee4d264 374
088c8618 375 rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
1a635e48 376 if (rc)
cee4d264
MC		 377 return rc;
378
06f56b81
YM		 379 memset(&init_data, 0, sizeof(init_data));
380 init_data.cid = qed_spq_get_cid(p_hwfn);
088c8618 381 init_data.opaque_fid = p_params->opaque_fid;
06f56b81 382 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
cee4d264
MC		 383
384 rc = qed_sp_init_request(p_hwfn, &p_ent,
cee4d264 385 ETH_RAMROD_VPORT_START,
06f56b81 386 PROTOCOLID_ETH, &init_data);
cee4d264
MC		 387 if (rc)
388 return rc;
389
390 p_ramrod = &p_ent->ramrod.vport_start;
391 p_ramrod->vport_id = abs_vport_id;
392
088c8618 393 p_ramrod->mtu = cpu_to_le16(p_params->mtu);
c78c70fa 394 p_ramrod->handle_ptp_pkts = p_params->handle_ptp_pkts;
088c8618
MC		 395 p_ramrod->inner_vlan_removal_en = p_params->remove_inner_vlan;
396 p_ramrod->drop_ttl0_en = p_params->drop_ttl0;
e6bd8923 397 p_ramrod->untagged = p_params->only_untagged;
cee4d264
MC		 398
399 SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_UCAST_DROP_ALL, 1);
400 SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_MCAST_DROP_ALL, 1);
401
402 p_ramrod->rx_mode.state = cpu_to_le16(rx_mode);
403
404 /* TPA related fields */
1a635e48 405 memset(&p_ramrod->tpa_param, 0, sizeof(struct eth_vport_tpa_param));
cee4d264 406
088c8618
MC		 407 p_ramrod->tpa_param.max_buff_num = p_params->max_buffers_per_cqe;
408
409 switch (p_params->tpa_mode) {
410 case QED_TPA_MODE_GRO:
411 p_ramrod->tpa_param.tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
412 p_ramrod->tpa_param.tpa_max_size = (u16)-1;
413 p_ramrod->tpa_param.tpa_min_size_to_cont = p_params->mtu / 2;
414 p_ramrod->tpa_param.tpa_min_size_to_start = p_params->mtu / 2;
415 p_ramrod->tpa_param.tpa_ipv4_en_flg = 1;
416 p_ramrod->tpa_param.tpa_ipv6_en_flg = 1;
417 p_ramrod->tpa_param.tpa_pkt_split_flg = 1;
418 p_ramrod->tpa_param.tpa_gro_consistent_flg = 1;
419 break;
420 default:
421 break;
422 }
423
831bfb0e
YM		 424 p_ramrod->tx_switching_en = p_params->tx_switching;
425
11a85d75
YM		 426 p_ramrod->ctl_frame_mac_check_en = !!p_params->check_mac;
427 p_ramrod->ctl_frame_ethtype_check_en = !!p_params->check_ethtype;
428
cee4d264
MC		 429 /* Software Function ID in hwfn (PFs are 0 - 15, VFs are 16 - 135) */
430 p_ramrod->sw_fid = qed_concrete_to_sw_fid(p_hwfn->cdev,
088c8618 431 p_params->concrete_fid);
cee4d264
MC		 432
433 return qed_spq_post(p_hwfn, p_ent, NULL);
434}
435
ba56947a
BX		 436static int qed_sp_vport_start(struct qed_hwfn *p_hwfn,
437 struct qed_sp_vport_start_params *p_params)
dacd88d6
YM		 438{
439 if (IS_VF(p_hwfn->cdev)) {
440 return qed_vf_pf_vport_start(p_hwfn, p_params->vport_id,
441 p_params->mtu,
442 p_params->remove_inner_vlan,
443 p_params->tpa_mode,
08feecd7
YM		 444 p_params->max_buffers_per_cqe,
445 p_params->only_untagged);
dacd88d6
YM		 446 }
447
448 return qed_sp_eth_vport_start(p_hwfn, p_params);
449}
450
cee4d264
MC		 451static int
452qed_sp_vport_update_rss(struct qed_hwfn *p_hwfn,
453 struct vport_update_ramrod_data *p_ramrod,
f29ffdb6 454 struct qed_rss_params *p_rss)
cee4d264 455{
f29ffdb6
MY		 456 struct eth_vport_rss_config *p_config;
457 u16 capabilities = 0;
458 int i, table_size;
459 int rc = 0;
cee4d264 460
f29ffdb6 461 if (!p_rss) {
cee4d264
MC		 462 p_ramrod->common.update_rss_flg = 0;
463 return rc;
464 }
f29ffdb6 465 p_config = &p_ramrod->rss_config;
cee4d264 466
f29ffdb6 467 BUILD_BUG_ON(QED_RSS_IND_TABLE_SIZE != ETH_RSS_IND_TABLE_ENTRIES_NUM);
cee4d264 468
f29ffdb6 469 rc = qed_fw_rss_eng(p_hwfn, p_rss->rss_eng_id, &p_config->rss_id);
cee4d264
MC		 470 if (rc)
471 return rc;
472
f29ffdb6
MY		 473 p_ramrod->common.update_rss_flg = p_rss->update_rss_config;
474 p_config->update_rss_capabilities = p_rss->update_rss_capabilities;
475 p_config->update_rss_ind_table = p_rss->update_rss_ind_table;
476 p_config->update_rss_key = p_rss->update_rss_key;
cee4d264 477
f29ffdb6
MY		 478 p_config->rss_mode = p_rss->rss_enable ?
479 ETH_VPORT_RSS_MODE_REGULAR :
480 ETH_VPORT_RSS_MODE_DISABLED;
cee4d264
MC		 481
482 SET_FIELD(capabilities,
483 ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY,
f29ffdb6 484 !!(p_rss->rss_caps & QED_RSS_IPV4));
cee4d264
MC		 485 SET_FIELD(capabilities,
486 ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY,
f29ffdb6 487 !!(p_rss->rss_caps & QED_RSS_IPV6));
cee4d264
MC		 488 SET_FIELD(capabilities,
489 ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY,
f29ffdb6 490 !!(p_rss->rss_caps & QED_RSS_IPV4_TCP));
cee4d264
MC		 491 SET_FIELD(capabilities,
492 ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY,
f29ffdb6 493 !!(p_rss->rss_caps & QED_RSS_IPV6_TCP));
cee4d264
MC		 494 SET_FIELD(capabilities,
495 ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY,
f29ffdb6 496 !!(p_rss->rss_caps & QED_RSS_IPV4_UDP));
cee4d264
MC		 497 SET_FIELD(capabilities,
498 ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY,
f29ffdb6
MY		 499 !!(p_rss->rss_caps & QED_RSS_IPV6_UDP));
500 p_config->tbl_size = p_rss->rss_table_size_log;
cee4d264 501
f29ffdb6 502 p_config->capabilities = cpu_to_le16(capabilities);
cee4d264
MC		 503
504 DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP,
505 "update rss flag %d, rss_mode = %d, update_caps = %d, capabilities = %d, update_ind = %d, update_rss_key = %d\n",
506 p_ramrod->common.update_rss_flg,
f29ffdb6
MY		 507 p_config->rss_mode,
508 p_config->update_rss_capabilities,
509 p_config->capabilities,
510 p_config->update_rss_ind_table, p_config->update_rss_key);
cee4d264 511
f29ffdb6
MY		 512 table_size = min_t(int, QED_RSS_IND_TABLE_SIZE,
513 1 << p_config->tbl_size);
514 for (i = 0; i < table_size; i++) {
515 struct qed_queue_cid *p_queue = p_rss->rss_ind_table[i];
cee4d264 516
f29ffdb6
MY		 517 if (!p_queue)
518 return -EINVAL;
519
520 p_config->indirection_table[i] =
521 cpu_to_le16(p_queue->abs.queue_id);
522 }
523
524 DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP,
525 "Configured RSS indirection table [%d entries]:\n",
526 table_size);
527 for (i = 0; i < QED_RSS_IND_TABLE_SIZE; i += 0x10) {
528 DP_VERBOSE(p_hwfn,
529 NETIF_MSG_IFUP,
530 "%04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x\n",
531 le16_to_cpu(p_config->indirection_table[i]),
532 le16_to_cpu(p_config->indirection_table[i + 1]),
533 le16_to_cpu(p_config->indirection_table[i + 2]),
534 le16_to_cpu(p_config->indirection_table[i + 3]),
535 le16_to_cpu(p_config->indirection_table[i + 4]),
536 le16_to_cpu(p_config->indirection_table[i + 5]),
537 le16_to_cpu(p_config->indirection_table[i + 6]),
538 le16_to_cpu(p_config->indirection_table[i + 7]),
539 le16_to_cpu(p_config->indirection_table[i + 8]),
540 le16_to_cpu(p_config->indirection_table[i + 9]),
541 le16_to_cpu(p_config->indirection_table[i + 10]),
542 le16_to_cpu(p_config->indirection_table[i + 11]),
543 le16_to_cpu(p_config->indirection_table[i + 12]),
544 le16_to_cpu(p_config->indirection_table[i + 13]),
545 le16_to_cpu(p_config->indirection_table[i + 14]),
546 le16_to_cpu(p_config->indirection_table[i + 15]));
cee4d264
MC		 547 }
548
549 for (i = 0; i < 10; i++)
f29ffdb6 550 p_config->rss_key[i] = cpu_to_le32(p_rss->rss_key[i]);
cee4d264
MC		 551
552 return rc;
553}
554
555static void
556qed_sp_update_accept_mode(struct qed_hwfn *p_hwfn,
557 struct vport_update_ramrod_data *p_ramrod,
558 struct qed_filter_accept_flags accept_flags)
559{
560 p_ramrod->common.update_rx_mode_flg =
561 accept_flags.update_rx_mode_config;
562
563 p_ramrod->common.update_tx_mode_flg =
564 accept_flags.update_tx_mode_config;
565
566 /* Set Rx mode accept flags */
567 if (p_ramrod->common.update_rx_mode_flg) {
568 u8 accept_filter = accept_flags.rx_accept_filter;
569 u16 state = 0;
570
571 SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_DROP_ALL,
572 !(!!(accept_filter & QED_ACCEPT_UCAST_MATCHED) ||
573 !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED)));
574
575 SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED,
576 !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED));
577
578 SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_DROP_ALL,
579 !(!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) ||
580 !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED)));
581
582 SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL,
583 (!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) &&
584 !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED)));
585
586 SET_FIELD(state, ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL,
587 !!(accept_filter & QED_ACCEPT_BCAST));
588
d52c89f1
MK		 589 SET_FIELD(state, ETH_VPORT_RX_MODE_ACCEPT_ANY_VNI,
590 !!(accept_filter & QED_ACCEPT_ANY_VNI));
591
cee4d264
MC		 592 p_ramrod->rx_mode.state = cpu_to_le16(state);
593 DP_VERBOSE(p_hwfn, QED_MSG_SP,
594 "p_ramrod->rx_mode.state = 0x%x\n", state);
595 }
596
597 /* Set Tx mode accept flags */
598 if (p_ramrod->common.update_tx_mode_flg) {
599 u8 accept_filter = accept_flags.tx_accept_filter;
600 u16 state = 0;
601
602 SET_FIELD(state, ETH_VPORT_TX_MODE_UCAST_DROP_ALL,
603 !!(accept_filter & QED_ACCEPT_NONE));
604
cee4d264
MC		 605 SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_DROP_ALL,
606 !!(accept_filter & QED_ACCEPT_NONE));
607
608 SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL,
609 (!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) &&
610 !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED)));
611
9e71a15d
MC		 612 SET_FIELD(state, ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL,
613 (!!(accept_filter & QED_ACCEPT_UCAST_MATCHED) &&
614 !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED)));
615
cee4d264
MC		 616 SET_FIELD(state, ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL,
617 !!(accept_filter & QED_ACCEPT_BCAST));
618
619 p_ramrod->tx_mode.state = cpu_to_le16(state);
620 DP_VERBOSE(p_hwfn, QED_MSG_SP,
621 "p_ramrod->tx_mode.state = 0x%x\n", state);
622 }
623}
624
17b235c1
YM		 625static void
626qed_sp_vport_update_sge_tpa(struct qed_hwfn *p_hwfn,
627 struct vport_update_ramrod_data *p_ramrod,
628 struct qed_sge_tpa_params *p_params)
629{
630 struct eth_vport_tpa_param *p_tpa;
631
632 if (!p_params) {
633 p_ramrod->common.update_tpa_param_flg = 0;
634 p_ramrod->common.update_tpa_en_flg = 0;
635 p_ramrod->common.update_tpa_param_flg = 0;
636 return;
637 }
638
639 p_ramrod->common.update_tpa_en_flg = p_params->update_tpa_en_flg;
640 p_tpa = &p_ramrod->tpa_param;
641 p_tpa->tpa_ipv4_en_flg = p_params->tpa_ipv4_en_flg;
642 p_tpa->tpa_ipv6_en_flg = p_params->tpa_ipv6_en_flg;
643 p_tpa->tpa_ipv4_tunn_en_flg = p_params->tpa_ipv4_tunn_en_flg;
644 p_tpa->tpa_ipv6_tunn_en_flg = p_params->tpa_ipv6_tunn_en_flg;
645
646 p_ramrod->common.update_tpa_param_flg = p_params->update_tpa_param_flg;
647 p_tpa->max_buff_num = p_params->max_buffers_per_cqe;
648 p_tpa->tpa_pkt_split_flg = p_params->tpa_pkt_split_flg;
649 p_tpa->tpa_hdr_data_split_flg = p_params->tpa_hdr_data_split_flg;
650 p_tpa->tpa_gro_consistent_flg = p_params->tpa_gro_consistent_flg;
651 p_tpa->tpa_max_aggs_num = p_params->tpa_max_aggs_num;
652 p_tpa->tpa_max_size = p_params->tpa_max_size;
653 p_tpa->tpa_min_size_to_start = p_params->tpa_min_size_to_start;
654 p_tpa->tpa_min_size_to_cont = p_params->tpa_min_size_to_cont;
655}
656
cee4d264
MC		 657static void
658qed_sp_update_mcast_bin(struct qed_hwfn *p_hwfn,
659 struct vport_update_ramrod_data *p_ramrod,
660 struct qed_sp_vport_update_params *p_params)
661{
662 int i;
663
664 memset(&p_ramrod->approx_mcast.bins, 0,
665 sizeof(p_ramrod->approx_mcast.bins));
666
83aeb933
YM		 667 if (!p_params->update_approx_mcast_flg)
668 return;
cee4d264 669
83aeb933
YM		 670 p_ramrod->common.update_approx_mcast_flg = 1;
671 for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) {
25c020a9 672 u32 *p_bins = p_params->bins;
83aeb933
YM		 673
674 p_ramrod->approx_mcast.bins[i] = cpu_to_le32(p_bins[i]);
cee4d264
MC		 675 }
676}
677
dacd88d6
YM		 678int qed_sp_vport_update(struct qed_hwfn *p_hwfn,
679 struct qed_sp_vport_update_params *p_params,
680 enum spq_mode comp_mode,
681 struct qed_spq_comp_cb *p_comp_data)
cee4d264
MC		 682{
683 struct qed_rss_params *p_rss_params = p_params->rss_params;
684 struct vport_update_ramrod_data_cmn *p_cmn;
06f56b81 685 struct qed_sp_init_data init_data;
cee4d264
MC		 686 struct vport_update_ramrod_data *p_ramrod = NULL;
687 struct qed_spq_entry *p_ent = NULL;
17b235c1 688 u8 abs_vport_id = 0, val;
cee4d264
MC		 689 int rc = -EINVAL;
690
dacd88d6
YM		 691 if (IS_VF(p_hwfn->cdev)) {
692 rc = qed_vf_pf_vport_update(p_hwfn, p_params);
693 return rc;
694 }
695
cee4d264 696 rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
1a635e48 697 if (rc)
cee4d264
MC		 698 return rc;
699
06f56b81
YM		 700 memset(&init_data, 0, sizeof(init_data));
701 init_data.cid = qed_spq_get_cid(p_hwfn);
702 init_data.opaque_fid = p_params->opaque_fid;
703 init_data.comp_mode = comp_mode;
704 init_data.p_comp_data = p_comp_data;
cee4d264
MC		 705
706 rc = qed_sp_init_request(p_hwfn, &p_ent,
cee4d264 707 ETH_RAMROD_VPORT_UPDATE,
06f56b81 708 PROTOCOLID_ETH, &init_data);
cee4d264
MC		 709 if (rc)
710 return rc;
711
712 /* Copy input params to ramrod according to FW struct */
713 p_ramrod = &p_ent->ramrod.vport_update;
714 p_cmn = &p_ramrod->common;
715
716 p_cmn->vport_id = abs_vport_id;
717 p_cmn->rx_active_flg = p_params->vport_active_rx_flg;
718 p_cmn->update_rx_active_flg = p_params->update_vport_active_rx_flg;
719 p_cmn->tx_active_flg = p_params->vport_active_tx_flg;
720 p_cmn->update_tx_active_flg = p_params->update_vport_active_tx_flg;
3f9b4a69 721 p_cmn->accept_any_vlan = p_params->accept_any_vlan;
83aeb933
YM		 722 val = p_params->update_accept_any_vlan_flg;
723 p_cmn->update_accept_any_vlan_flg = val;
17b235c1
YM		 724
725 p_cmn->inner_vlan_removal_en = p_params->inner_vlan_removal_flg;
726 val = p_params->update_inner_vlan_removal_flg;
727 p_cmn->update_inner_vlan_removal_en_flg = val;
08feecd7
YM		 728
729 p_cmn->default_vlan_en = p_params->default_vlan_enable_flg;
730 val = p_params->update_default_vlan_enable_flg;
731 p_cmn->update_default_vlan_en_flg = val;
732
733 p_cmn->default_vlan = cpu_to_le16(p_params->default_vlan);
734 p_cmn->update_default_vlan_flg = p_params->update_default_vlan_flg;
735
736 p_cmn->silent_vlan_removal_en = p_params->silent_vlan_removal_flg;
737
17b235c1
YM		 738 p_ramrod->common.tx_switching_en = p_params->tx_switching_flg;
739 p_cmn->update_tx_switching_en_flg = p_params->update_tx_switching_flg;
740
6ddc7608
YM		 741 p_cmn->anti_spoofing_en = p_params->anti_spoofing_en;
742 val = p_params->update_anti_spoofing_en_flg;
743 p_ramrod->common.update_anti_spoofing_en_flg = val;
744
cee4d264
MC		 745 rc = qed_sp_vport_update_rss(p_hwfn, p_ramrod, p_rss_params);
746 if (rc) {
fb5e7438 747 qed_sp_destroy_request(p_hwfn, p_ent);
cee4d264
MC		 748 return rc;
749 }
750
ff929696
MC		 751 if (p_params->update_ctl_frame_check) {
752 p_cmn->ctl_frame_mac_check_en = p_params->mac_chk_en;
753 p_cmn->ctl_frame_ethtype_check_en = p_params->ethtype_chk_en;
754 }
755
cee4d264
MC		 756 /* Update mcast bins for VFs, PF doesn't use this functionality */
757 qed_sp_update_mcast_bin(p_hwfn, p_ramrod, p_params);
758
759 qed_sp_update_accept_mode(p_hwfn, p_ramrod, p_params->accept_flags);
17b235c1 760 qed_sp_vport_update_sge_tpa(p_hwfn, p_ramrod, p_params->sge_tpa_params);
cee4d264
MC		 761 return qed_spq_post(p_hwfn, p_ent, NULL);
762}
763
dacd88d6 764int qed_sp_vport_stop(struct qed_hwfn *p_hwfn, u16 opaque_fid, u8 vport_id)
cee4d264 765{
cee4d264 766 struct vport_stop_ramrod_data *p_ramrod;
06f56b81 767 struct qed_sp_init_data init_data;
cee4d264
MC		 768 struct qed_spq_entry *p_ent;
769 u8 abs_vport_id = 0;
770 int rc;
771
dacd88d6
YM		 772 if (IS_VF(p_hwfn->cdev))
773 return qed_vf_pf_vport_stop(p_hwfn);
774
cee4d264 775 rc = qed_fw_vport(p_hwfn, vport_id, &abs_vport_id);
1a635e48 776 if (rc)
cee4d264
MC		 777 return rc;
778
06f56b81
YM		 779 memset(&init_data, 0, sizeof(init_data));
780 init_data.cid = qed_spq_get_cid(p_hwfn);
781 init_data.opaque_fid = opaque_fid;
782 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
cee4d264
MC		 783
784 rc = qed_sp_init_request(p_hwfn, &p_ent,
cee4d264 785 ETH_RAMROD_VPORT_STOP,
06f56b81 786 PROTOCOLID_ETH, &init_data);
cee4d264
MC		 787 if (rc)
788 return rc;
789
790 p_ramrod = &p_ent->ramrod.vport_stop;
791 p_ramrod->vport_id = abs_vport_id;
792
793 return qed_spq_post(p_hwfn, p_ent, NULL);
794}
795
dacd88d6
YM		 796static int
797qed_vf_pf_accept_flags(struct qed_hwfn *p_hwfn,
798 struct qed_filter_accept_flags *p_accept_flags)
799{
800 struct qed_sp_vport_update_params s_params;
801
802 memset(&s_params, 0, sizeof(s_params));
803 memcpy(&s_params.accept_flags, p_accept_flags,
804 sizeof(struct qed_filter_accept_flags));
805
806 return qed_vf_pf_vport_update(p_hwfn, &s_params);
807}
808
cee4d264
MC		 809static int qed_filter_accept_cmd(struct qed_dev *cdev,
810 u8 vport,
811 struct qed_filter_accept_flags accept_flags,
3f9b4a69
YM		 812 u8 update_accept_any_vlan,
813 u8 accept_any_vlan,
dacd88d6
YM		 814 enum spq_mode comp_mode,
815 struct qed_spq_comp_cb *p_comp_data)
cee4d264
MC		 816{
817 struct qed_sp_vport_update_params vport_update_params;
818 int i, rc;
819
820 /* Prepare and send the vport rx_mode change */
821 memset(&vport_update_params, 0, sizeof(vport_update_params));
822 vport_update_params.vport_id = vport;
823 vport_update_params.accept_flags = accept_flags;
3f9b4a69
YM		 824 vport_update_params.update_accept_any_vlan_flg = update_accept_any_vlan;
825 vport_update_params.accept_any_vlan = accept_any_vlan;
cee4d264
MC		 826
827 for_each_hwfn(cdev, i) {
828 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
829
830 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
831
dacd88d6
YM		 832 if (IS_VF(cdev)) {
833 rc = qed_vf_pf_accept_flags(p_hwfn, &accept_flags);
834 if (rc)
835 return rc;
836 continue;
837 }
838
cee4d264
MC		 839 rc = qed_sp_vport_update(p_hwfn, &vport_update_params,
840 comp_mode, p_comp_data);
1a635e48 841 if (rc) {
cee4d264
MC		 842 DP_ERR(cdev, "Update rx_mode failed %d\n", rc);
843 return rc;
844 }
845
846 DP_VERBOSE(p_hwfn, QED_MSG_SP,
847 "Accept filter configured, flags = [Rx]%x [Tx]%x\n",
848 accept_flags.rx_accept_filter,
849 accept_flags.tx_accept_filter);
3f9b4a69
YM		 850 if (update_accept_any_vlan)
851 DP_VERBOSE(p_hwfn, QED_MSG_SP,
852 "accept_any_vlan=%d configured\n",
853 accept_any_vlan);
cee4d264
MC		 854 }
855
856 return 0;
857}
858
3da7a37a
MY		 859int qed_eth_rxq_start_ramrod(struct qed_hwfn *p_hwfn,
860 struct qed_queue_cid *p_cid,
861 u16 bd_max_bytes,
862 dma_addr_t bd_chain_phys_addr,
863 dma_addr_t cqe_pbl_addr, u16 cqe_pbl_size)
cee4d264
MC		 864{
865 struct rx_queue_start_ramrod_data *p_ramrod = NULL;
cee4d264 866 struct qed_spq_entry *p_ent = NULL;
06f56b81 867 struct qed_sp_init_data init_data;
cee4d264
MC		 868 int rc = -EINVAL;
869
cee4d264 870 DP_VERBOSE(p_hwfn, QED_MSG_SP,
3da7a37a
MY		 871 "opaque_fid=0x%x, cid=0x%x, rx_qzone=0x%x, vport_id=0x%x, sb_id=0x%x\n",
872 p_cid->opaque_fid, p_cid->cid,
f604b17d 873 p_cid->abs.queue_id, p_cid->abs.vport_id, p_cid->sb_igu_id);
cee4d264 874
06f56b81
YM		 875 /* Get SPQ entry */
876 memset(&init_data, 0, sizeof(init_data));
3da7a37a
MY		 877 init_data.cid = p_cid->cid;
878 init_data.opaque_fid = p_cid->opaque_fid;
06f56b81 879 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
cee4d264
MC		 880
881 rc = qed_sp_init_request(p_hwfn, &p_ent,
cee4d264 882 ETH_RAMROD_RX_QUEUE_START,
06f56b81 883 PROTOCOLID_ETH, &init_data);
cee4d264
MC		 884 if (rc)
885 return rc;
886
887 p_ramrod = &p_ent->ramrod.rx_queue_start;
888
f604b17d
MY		 889 p_ramrod->sb_id = cpu_to_le16(p_cid->sb_igu_id);
890 p_ramrod->sb_index = p_cid->sb_idx;
3da7a37a
MY		 891 p_ramrod->vport_id = p_cid->abs.vport_id;
892 p_ramrod->stats_counter_id = p_cid->abs.stats_id;
893 p_ramrod->rx_queue_id = cpu_to_le16(p_cid->abs.queue_id);
1a635e48
YM		 894 p_ramrod->complete_cqe_flg = 0;
895 p_ramrod->complete_event_flg = 1;
cee4d264 896
1a635e48 897 p_ramrod->bd_max_bytes = cpu_to_le16(bd_max_bytes);
94494598 898 DMA_REGPAIR_LE(p_ramrod->bd_base, bd_chain_phys_addr);
cee4d264 899
1a635e48 900 p_ramrod->num_of_pbl_pages = cpu_to_le16(cqe_pbl_size);
94494598 901 DMA_REGPAIR_LE(p_ramrod->cqe_pbl_addr, cqe_pbl_addr);
cee4d264 902
3946497a 903 if (p_cid->vfid != QED_QUEUE_CID_SELF) {
3b19f478
MY		 904 bool b_legacy_vf = !!(p_cid->vf_legacy &
905 QED_QCID_LEGACY_VF_RX_PROD);
906
3da7a37a 907 p_ramrod->vf_rx_prod_index = p_cid->vf_qid;
351a4ded 908 DP_VERBOSE(p_hwfn, QED_MSG_SP,
a044df83 909 "Queue%s is meant for VF rxq[%02x]\n",
3b19f478
MY		 910 b_legacy_vf ? " [legacy]" : "", p_cid->vf_qid);
911 p_ramrod->vf_rx_prod_use_zone_a = b_legacy_vf;
a044df83 912 }
cee4d264 913
351a4ded 914 return qed_spq_post(p_hwfn, p_ent, NULL);
cee4d264
MC		 915}
916
917static int
3da7a37a
MY		 918qed_eth_pf_rx_queue_start(struct qed_hwfn *p_hwfn,
919 struct qed_queue_cid *p_cid,
cee4d264
MC		 920 u16 bd_max_bytes,
921 dma_addr_t bd_chain_phys_addr,
922 dma_addr_t cqe_pbl_addr,
dacd88d6 923 u16 cqe_pbl_size, void __iomem **pp_prod)
cee4d264 924{
b21290b7 925 u32 init_prod_val = 0;
cee4d264 926
3da7a37a
MY		 927 *pp_prod = p_hwfn->regview +
928 GTT_BAR0_MAP_REG_MSDM_RAM +
929 MSTORM_ETH_PF_PRODS_OFFSET(p_cid->abs.queue_id);
cee4d264
MC		 930
931 /* Init the rcq, rx bd and rx sge (if valid) producers to 0 */
b21290b7 932 __internal_ram_wr(p_hwfn, *pp_prod, sizeof(u32),
cee4d264
MC		 933 (u32 *)(&init_prod_val));
934
3da7a37a
MY		 935 return qed_eth_rxq_start_ramrod(p_hwfn, p_cid,
936 bd_max_bytes,
937 bd_chain_phys_addr,
938 cqe_pbl_addr, cqe_pbl_size);
939}
940
941static int
942qed_eth_rx_queue_start(struct qed_hwfn *p_hwfn,
943 u16 opaque_fid,
944 struct qed_queue_start_common_params *p_params,
945 u16 bd_max_bytes,
946 dma_addr_t bd_chain_phys_addr,
947 dma_addr_t cqe_pbl_addr,
948 u16 cqe_pbl_size,
949 struct qed_rxq_start_ret_params *p_ret_params)
950{
951 struct qed_queue_cid *p_cid;
952 int rc;
953
cee4d264 954 /* Allocate a CID for the queue */
007bc371 955 p_cid = qed_eth_queue_to_cid_pf(p_hwfn, opaque_fid, true, p_params);
3da7a37a
MY		 956 if (!p_cid)
957 return -ENOMEM;
cee4d264 958
3da7a37a
MY		 959 if (IS_PF(p_hwfn->cdev)) {
960 rc = qed_eth_pf_rx_queue_start(p_hwfn, p_cid,
961 bd_max_bytes,
962 bd_chain_phys_addr,
963 cqe_pbl_addr, cqe_pbl_size,
964 &p_ret_params->p_prod);
965 } else {
966 rc = qed_vf_pf_rxq_start(p_hwfn, p_cid,
cee4d264
MC		 967 bd_max_bytes,
968 bd_chain_phys_addr,
3da7a37a
MY		 969 cqe_pbl_addr,
970 cqe_pbl_size, &p_ret_params->p_prod);
971 }
cee4d264 972
3da7a37a 973 /* Provide the caller with a reference to as handler */
1a635e48 974 if (rc)
3da7a37a
MY		 975 qed_eth_queue_cid_release(p_hwfn, p_cid);
976 else
977 p_ret_params->p_handle = (void *)p_cid;
cee4d264
MC		 978
979 return rc;
980}
981
17b235c1 982int qed_sp_eth_rx_queues_update(struct qed_hwfn *p_hwfn,
3da7a37a 983 void **pp_rxq_handles,
17b235c1
YM		 984 u8 num_rxqs,
985 u8 complete_cqe_flg,
986 u8 complete_event_flg,
987 enum spq_mode comp_mode,
988 struct qed_spq_comp_cb *p_comp_data)
989{
990 struct rx_queue_update_ramrod_data *p_ramrod = NULL;
991 struct qed_spq_entry *p_ent = NULL;
992 struct qed_sp_init_data init_data;
3da7a37a 993 struct qed_queue_cid *p_cid;
17b235c1
YM		 994 int rc = -EINVAL;
995 u8 i;
996
997 memset(&init_data, 0, sizeof(init_data));
998 init_data.comp_mode = comp_mode;
999 init_data.p_comp_data = p_comp_data;
1000
1001 for (i = 0; i < num_rxqs; i++) {
3da7a37a 1002 p_cid = ((struct qed_queue_cid **)pp_rxq_handles)[i];
17b235c1
YM		 1003
1004 /* Get SPQ entry */
3da7a37a
MY		 1005 init_data.cid = p_cid->cid;
1006 init_data.opaque_fid = p_cid->opaque_fid;
17b235c1
YM		 1007
1008 rc = qed_sp_init_request(p_hwfn, &p_ent,
1009 ETH_RAMROD_RX_QUEUE_UPDATE,
1010 PROTOCOLID_ETH, &init_data);
1011 if (rc)
1012 return rc;
1013
1014 p_ramrod = &p_ent->ramrod.rx_queue_update;
3da7a37a 1015 p_ramrod->vport_id = p_cid->abs.vport_id;
17b235c1 1016
3da7a37a 1017 p_ramrod->rx_queue_id = cpu_to_le16(p_cid->abs.queue_id);
17b235c1
YM		 1018 p_ramrod->complete_cqe_flg = complete_cqe_flg;
1019 p_ramrod->complete_event_flg = complete_event_flg;
1020
1021 rc = qed_spq_post(p_hwfn, p_ent, NULL);
1022 if (rc)
1023 return rc;
1024 }
1025
1026 return rc;
1027}
1028
3da7a37a
MY		 1029static int
1030qed_eth_pf_rx_queue_stop(struct qed_hwfn *p_hwfn,
1031 struct qed_queue_cid *p_cid,
1032 bool b_eq_completion_only, bool b_cqe_completion)
cee4d264 1033{
cee4d264 1034 struct rx_queue_stop_ramrod_data *p_ramrod = NULL;
cee4d264 1035 struct qed_spq_entry *p_ent = NULL;
06f56b81 1036 struct qed_sp_init_data init_data;
3da7a37a 1037 int rc;
dacd88d6 1038
06f56b81 1039 memset(&init_data, 0, sizeof(init_data));
3da7a37a
MY		 1040 init_data.cid = p_cid->cid;
1041 init_data.opaque_fid = p_cid->opaque_fid;
06f56b81 1042 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
cee4d264
MC		 1043
1044 rc = qed_sp_init_request(p_hwfn, &p_ent,
cee4d264 1045 ETH_RAMROD_RX_QUEUE_STOP,
06f56b81 1046 PROTOCOLID_ETH, &init_data);
cee4d264
MC		 1047 if (rc)
1048 return rc;
1049
1050 p_ramrod = &p_ent->ramrod.rx_queue_stop;
3da7a37a
MY		 1051 p_ramrod->vport_id = p_cid->abs.vport_id;
1052 p_ramrod->rx_queue_id = cpu_to_le16(p_cid->abs.queue_id);
cee4d264
MC		 1053
1054 /* Cleaning the queue requires the completion to arrive there.
1055 * In addition, VFs require the answer to come as eqe to PF.
1056 */
3946497a 1057 p_ramrod->complete_cqe_flg = ((p_cid->vfid == QED_QUEUE_CID_SELF) &&
3da7a37a
MY		 1058 !b_eq_completion_only) ||
1059 b_cqe_completion;
3946497a
MY		 1060 p_ramrod->complete_event_flg = (p_cid->vfid != QED_QUEUE_CID_SELF) ||
1061 b_eq_completion_only;
cee4d264 1062
3da7a37a
MY		 1063 return qed_spq_post(p_hwfn, p_ent, NULL);
1064}
1065
1066int qed_eth_rx_queue_stop(struct qed_hwfn *p_hwfn,
1067 void *p_rxq,
1068 bool eq_completion_only, bool cqe_completion)
1069{
1070 struct qed_queue_cid *p_cid = (struct qed_queue_cid *)p_rxq;
1071 int rc = -EINVAL;
cee4d264 1072
3da7a37a
MY		 1073 if (IS_PF(p_hwfn->cdev))
1074 rc = qed_eth_pf_rx_queue_stop(p_hwfn, p_cid,
1075 eq_completion_only,
1076 cqe_completion);
1077 else
1078 rc = qed_vf_pf_rxq_stop(p_hwfn, p_cid, cqe_completion);
1079
1080 if (!rc)
1081 qed_eth_queue_cid_release(p_hwfn, p_cid);
1082 return rc;
cee4d264
MC		 1083}
1084
3da7a37a
MY		 1085int
1086qed_eth_txq_start_ramrod(struct qed_hwfn *p_hwfn,
1087 struct qed_queue_cid *p_cid,
1088 dma_addr_t pbl_addr, u16 pbl_size, u16 pq_id)
cee4d264
MC		 1089{
1090 struct tx_queue_start_ramrod_data *p_ramrod = NULL;
cee4d264 1091 struct qed_spq_entry *p_ent = NULL;
06f56b81 1092 struct qed_sp_init_data init_data;
cee4d264 1093 int rc = -EINVAL;
351a4ded 1094
06f56b81
YM		 1095 /* Get SPQ entry */
1096 memset(&init_data, 0, sizeof(init_data));
3da7a37a
MY		 1097 init_data.cid = p_cid->cid;
1098 init_data.opaque_fid = p_cid->opaque_fid;
06f56b81 1099 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
cee4d264 1100
06f56b81 1101 rc = qed_sp_init_request(p_hwfn, &p_ent,
cee4d264 1102 ETH_RAMROD_TX_QUEUE_START,
06f56b81 1103 PROTOCOLID_ETH, &init_data);
cee4d264
MC		 1104 if (rc)
1105 return rc;
1106
1a635e48 1107 p_ramrod = &p_ent->ramrod.tx_queue_start;
3da7a37a 1108 p_ramrod->vport_id = p_cid->abs.vport_id;
1a635e48 1109
f604b17d
MY		 1110 p_ramrod->sb_id = cpu_to_le16(p_cid->sb_igu_id);
1111 p_ramrod->sb_index = p_cid->sb_idx;
3da7a37a 1112 p_ramrod->stats_counter_id = p_cid->abs.stats_id;
cee4d264 1113
3da7a37a
MY		 1114 p_ramrod->queue_zone_id = cpu_to_le16(p_cid->abs.queue_id);
1115 p_ramrod->same_as_last_id = cpu_to_le16(p_cid->abs.queue_id);
cee4d264 1116
1a635e48 1117 p_ramrod->pbl_size = cpu_to_le16(pbl_size);
94494598 1118 DMA_REGPAIR_LE(p_ramrod->pbl_base_addr, pbl_addr);
cee4d264 1119
1a635e48 1120 p_ramrod->qm_pq_id = cpu_to_le16(pq_id);
cee4d264
MC		 1121
1122 return qed_spq_post(p_hwfn, p_ent, NULL);
1123}
1124
1125static int
3da7a37a
MY		 1126qed_eth_pf_tx_queue_start(struct qed_hwfn *p_hwfn,
1127 struct qed_queue_cid *p_cid,
1128 u8 tc,
cee4d264 1129 dma_addr_t pbl_addr,
dacd88d6 1130 u16 pbl_size, void __iomem **pp_doorbell)
cee4d264 1131{
cee4d264
MC		 1132 int rc;
1133
dacd88d6 1134
3da7a37a
MY		 1135 rc = qed_eth_txq_start_ramrod(p_hwfn, p_cid,
1136 pbl_addr, pbl_size,
b5a9ee7c 1137 qed_get_cm_pq_idx_mcos(p_hwfn, tc));
cee4d264
MC		 1138 if (rc)
1139 return rc;
1140
3da7a37a
MY		 1141 /* Provide the caller with the necessary return values */
1142 *pp_doorbell = p_hwfn->doorbells +
1143 qed_db_addr(p_cid->cid, DQ_DEMS_LEGACY);
cee4d264 1144
3da7a37a
MY		 1145 return 0;
1146}
cee4d264 1147
3da7a37a
MY		 1148static int
1149qed_eth_tx_queue_start(struct qed_hwfn *p_hwfn,
1150 u16 opaque_fid,
1151 struct qed_queue_start_common_params *p_params,
1152 u8 tc,
1153 dma_addr_t pbl_addr,
1154 u16 pbl_size,
1155 struct qed_txq_start_ret_params *p_ret_params)
1156{
1157 struct qed_queue_cid *p_cid;
1158 int rc;
1159
007bc371 1160 p_cid = qed_eth_queue_to_cid_pf(p_hwfn, opaque_fid, false, p_params);
3da7a37a
MY		 1161 if (!p_cid)
1162 return -EINVAL;
1163
1164 if (IS_PF(p_hwfn->cdev))
1165 rc = qed_eth_pf_tx_queue_start(p_hwfn, p_cid, tc,
1166 pbl_addr, pbl_size,
1167 &p_ret_params->p_doorbell);
1168 else
1169 rc = qed_vf_pf_txq_start(p_hwfn, p_cid,
1170 pbl_addr, pbl_size,
1171 &p_ret_params->p_doorbell);
cee4d264
MC		 1172
1173 if (rc)
3da7a37a
MY		 1174 qed_eth_queue_cid_release(p_hwfn, p_cid);
1175 else
1176 p_ret_params->p_handle = (void *)p_cid;
cee4d264
MC		 1177
1178 return rc;
1179}
1180
3da7a37a
MY		 1181static int
1182qed_eth_pf_tx_queue_stop(struct qed_hwfn *p_hwfn, struct qed_queue_cid *p_cid)
cee4d264 1183{
cee4d264 1184 struct qed_spq_entry *p_ent = NULL;
06f56b81 1185 struct qed_sp_init_data init_data;
3da7a37a 1186 int rc;
dacd88d6 1187
06f56b81 1188 memset(&init_data, 0, sizeof(init_data));
3da7a37a
MY		 1189 init_data.cid = p_cid->cid;
1190 init_data.opaque_fid = p_cid->opaque_fid;
06f56b81 1191 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
cee4d264
MC		 1192
1193 rc = qed_sp_init_request(p_hwfn, &p_ent,
cee4d264 1194 ETH_RAMROD_TX_QUEUE_STOP,
06f56b81 1195 PROTOCOLID_ETH, &init_data);
cee4d264
MC		 1196 if (rc)
1197 return rc;
1198
3da7a37a
MY		 1199 return qed_spq_post(p_hwfn, p_ent, NULL);
1200}
1201
1202int qed_eth_tx_queue_stop(struct qed_hwfn *p_hwfn, void *p_handle)
1203{
1204 struct qed_queue_cid *p_cid = (struct qed_queue_cid *)p_handle;
1205 int rc;
1206
1207 if (IS_PF(p_hwfn->cdev))
1208 rc = qed_eth_pf_tx_queue_stop(p_hwfn, p_cid);
1209 else
1210 rc = qed_vf_pf_txq_stop(p_hwfn, p_cid);
cee4d264 1211
3da7a37a
MY		 1212 if (!rc)
1213 qed_eth_queue_cid_release(p_hwfn, p_cid);
1214 return rc;
cee4d264
MC		 1215}
1216
1a635e48 1217static enum eth_filter_action qed_filter_action(enum qed_filter_opcode opcode)
cee4d264
MC		 1218{
1219 enum eth_filter_action action = MAX_ETH_FILTER_ACTION;
1220
1221 switch (opcode) {
1222 case QED_FILTER_ADD:
1223 action = ETH_FILTER_ACTION_ADD;
1224 break;
1225 case QED_FILTER_REMOVE:
1226 action = ETH_FILTER_ACTION_REMOVE;
1227 break;
cee4d264 1228 case QED_FILTER_FLUSH:
fc48b7a6 1229 action = ETH_FILTER_ACTION_REMOVE_ALL;
cee4d264
MC		 1230 break;
1231 default:
1232 action = MAX_ETH_FILTER_ACTION;
1233 }
1234
1235 return action;
1236}
1237
cee4d264
MC		 1238static int
1239qed_filter_ucast_common(struct qed_hwfn *p_hwfn,
1240 u16 opaque_fid,
1241 struct qed_filter_ucast *p_filter_cmd,
1242 struct vport_filter_update_ramrod_data **pp_ramrod,
1243 struct qed_spq_entry **pp_ent,
1244 enum spq_mode comp_mode,
1245 struct qed_spq_comp_cb *p_comp_data)
1246{
1247 u8 vport_to_add_to = 0, vport_to_remove_from = 0;
1248 struct vport_filter_update_ramrod_data *p_ramrod;
cee4d264
MC		 1249 struct eth_filter_cmd *p_first_filter;
1250 struct eth_filter_cmd *p_second_filter;
06f56b81 1251 struct qed_sp_init_data init_data;
cee4d264
MC		 1252 enum eth_filter_action action;
1253 int rc;
1254
1255 rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from,
1256 &vport_to_remove_from);
1257 if (rc)
1258 return rc;
1259
1260 rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to,
1261 &vport_to_add_to);
1262 if (rc)
1263 return rc;
1264
06f56b81
YM		 1265 /* Get SPQ entry */
1266 memset(&init_data, 0, sizeof(init_data));
1267 init_data.cid = qed_spq_get_cid(p_hwfn);
1268 init_data.opaque_fid = opaque_fid;
1269 init_data.comp_mode = comp_mode;
1270 init_data.p_comp_data = p_comp_data;
cee4d264
MC		 1271
1272 rc = qed_sp_init_request(p_hwfn, pp_ent,
cee4d264 1273 ETH_RAMROD_FILTERS_UPDATE,
06f56b81 1274 PROTOCOLID_ETH, &init_data);
cee4d264
MC		 1275 if (rc)
1276 return rc;
1277
1278 *pp_ramrod = &(*pp_ent)->ramrod.vport_filter_update;
1279 p_ramrod = *pp_ramrod;
1280 p_ramrod->filter_cmd_hdr.rx = p_filter_cmd->is_rx_filter ? 1 : 0;
1281 p_ramrod->filter_cmd_hdr.tx = p_filter_cmd->is_tx_filter ? 1 : 0;
1282
1283 switch (p_filter_cmd->opcode) {
fc48b7a6 1284 case QED_FILTER_REPLACE:
cee4d264
MC		 1285 case QED_FILTER_MOVE:
1286 p_ramrod->filter_cmd_hdr.cmd_cnt = 2; break;
1287 default:
1288 p_ramrod->filter_cmd_hdr.cmd_cnt = 1; break;
1289 }
1290
1291 p_first_filter = &p_ramrod->filter_cmds[0];
1292 p_second_filter = &p_ramrod->filter_cmds[1];
1293
1294 switch (p_filter_cmd->type) {
1295 case QED_FILTER_MAC:
1296 p_first_filter->type = ETH_FILTER_TYPE_MAC; break;
1297 case QED_FILTER_VLAN:
1298 p_first_filter->type = ETH_FILTER_TYPE_VLAN; break;
1299 case QED_FILTER_MAC_VLAN:
1300 p_first_filter->type = ETH_FILTER_TYPE_PAIR; break;
1301 case QED_FILTER_INNER_MAC:
1302 p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC; break;
1303 case QED_FILTER_INNER_VLAN:
1304 p_first_filter->type = ETH_FILTER_TYPE_INNER_VLAN; break;
1305 case QED_FILTER_INNER_PAIR:
1306 p_first_filter->type = ETH_FILTER_TYPE_INNER_PAIR; break;
1307 case QED_FILTER_INNER_MAC_VNI_PAIR:
1308 p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR;
1309 break;
1310 case QED_FILTER_MAC_VNI_PAIR:
1311 p_first_filter->type = ETH_FILTER_TYPE_MAC_VNI_PAIR; break;
1312 case QED_FILTER_VNI:
1313 p_first_filter->type = ETH_FILTER_TYPE_VNI; break;
1314 }
1315
1316 if ((p_first_filter->type == ETH_FILTER_TYPE_MAC) ||
1317 (p_first_filter->type == ETH_FILTER_TYPE_PAIR) ||
1318 (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC) ||
1319 (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR) ||
1320 (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) ||
1321 (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR)) {
1322 qed_set_fw_mac_addr(&p_first_filter->mac_msb,
1323 &p_first_filter->mac_mid,
1324 &p_first_filter->mac_lsb,
1325 (u8 *)p_filter_cmd->mac);
1326 }
1327
1328 if ((p_first_filter->type == ETH_FILTER_TYPE_VLAN) ||
1329 (p_first_filter->type == ETH_FILTER_TYPE_PAIR) ||
1330 (p_first_filter->type == ETH_FILTER_TYPE_INNER_VLAN) ||
1331 (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR))
1332 p_first_filter->vlan_id = cpu_to_le16(p_filter_cmd->vlan);
1333
1334 if ((p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) ||
1335 (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR) ||
1336 (p_first_filter->type == ETH_FILTER_TYPE_VNI))
1337 p_first_filter->vni = cpu_to_le32(p_filter_cmd->vni);
1338
1339 if (p_filter_cmd->opcode == QED_FILTER_MOVE) {
1a635e48
YM		 1340 p_second_filter->type = p_first_filter->type;
1341 p_second_filter->mac_msb = p_first_filter->mac_msb;
1342 p_second_filter->mac_mid = p_first_filter->mac_mid;
1343 p_second_filter->mac_lsb = p_first_filter->mac_lsb;
1344 p_second_filter->vlan_id = p_first_filter->vlan_id;
1345 p_second_filter->vni = p_first_filter->vni;
cee4d264
MC		 1346
1347 p_first_filter->action = ETH_FILTER_ACTION_REMOVE;
1348
1349 p_first_filter->vport_id = vport_to_remove_from;
1350
1a635e48
YM		 1351 p_second_filter->action = ETH_FILTER_ACTION_ADD;
1352 p_second_filter->vport_id = vport_to_add_to;
fc48b7a6
YM		 1353 } else if (p_filter_cmd->opcode == QED_FILTER_REPLACE) {
1354 p_first_filter->vport_id = vport_to_add_to;
1355 memcpy(p_second_filter, p_first_filter,
1356 sizeof(*p_second_filter));
1357 p_first_filter->action = ETH_FILTER_ACTION_REMOVE_ALL;
1358 p_second_filter->action = ETH_FILTER_ACTION_ADD;
cee4d264
MC		 1359 } else {
1360 action = qed_filter_action(p_filter_cmd->opcode);
1361
1362 if (action == MAX_ETH_FILTER_ACTION) {
1363 DP_NOTICE(p_hwfn,
1364 "%d is not supported yet\n",
1365 p_filter_cmd->opcode);
fb5e7438 1366 qed_sp_destroy_request(p_hwfn, *pp_ent);
cee4d264
MC		 1367 return -EINVAL;
1368 }
1369
1370 p_first_filter->action = action;
1371 p_first_filter->vport_id = (p_filter_cmd->opcode ==
1372 QED_FILTER_REMOVE) ?
1373 vport_to_remove_from :
1374 vport_to_add_to;
1375 }
1376
1377 return 0;
1378}
1379
dacd88d6
YM		 1380int qed_sp_eth_filter_ucast(struct qed_hwfn *p_hwfn,
1381 u16 opaque_fid,
1382 struct qed_filter_ucast *p_filter_cmd,
1383 enum spq_mode comp_mode,
1384 struct qed_spq_comp_cb *p_comp_data)
cee4d264
MC		 1385{
1386 struct vport_filter_update_ramrod_data *p_ramrod = NULL;
1387 struct qed_spq_entry *p_ent = NULL;
1388 struct eth_filter_cmd_header *p_header;
1389 int rc;
1390
1391 rc = qed_filter_ucast_common(p_hwfn, opaque_fid, p_filter_cmd,
1392 &p_ramrod, &p_ent,
1393 comp_mode, p_comp_data);
1a635e48 1394 if (rc) {
cee4d264
MC		 1395 DP_ERR(p_hwfn, "Uni. filter command failed %d\n", rc);
1396 return rc;
1397 }
1398 p_header = &p_ramrod->filter_cmd_hdr;
1399 p_header->assert_on_error = p_filter_cmd->assert_on_error;
1400
1401 rc = qed_spq_post(p_hwfn, p_ent, NULL);
1a635e48
YM		 1402 if (rc) {
1403 DP_ERR(p_hwfn, "Unicast filter ADD command failed %d\n", rc);
cee4d264
MC		 1404 return rc;
1405 }
1406
1407 DP_VERBOSE(p_hwfn, QED_MSG_SP,
1408 "Unicast filter configured, opcode = %s, type = %s, cmd_cnt = %d, is_rx_filter = %d, is_tx_filter = %d\n",
1409 (p_filter_cmd->opcode == QED_FILTER_ADD) ? "ADD" :
1410 ((p_filter_cmd->opcode == QED_FILTER_REMOVE) ?
1411 "REMOVE" :
1412 ((p_filter_cmd->opcode == QED_FILTER_MOVE) ?
1413 "MOVE" : "REPLACE")),
1414 (p_filter_cmd->type == QED_FILTER_MAC) ? "MAC" :
1415 ((p_filter_cmd->type == QED_FILTER_VLAN) ?
1416 "VLAN" : "MAC & VLAN"),
1417 p_ramrod->filter_cmd_hdr.cmd_cnt,
1418 p_filter_cmd->is_rx_filter,
1419 p_filter_cmd->is_tx_filter);
1420 DP_VERBOSE(p_hwfn, QED_MSG_SP,
1421 "vport_to_add_to = %d, vport_to_remove_from = %d, mac = %2x:%2x:%2x:%2x:%2x:%2x, vlan = %d\n",
1422 p_filter_cmd->vport_to_add_to,
1423 p_filter_cmd->vport_to_remove_from,
1424 p_filter_cmd->mac[0],
1425 p_filter_cmd->mac[1],
1426 p_filter_cmd->mac[2],
1427 p_filter_cmd->mac[3],
1428 p_filter_cmd->mac[4],
1429 p_filter_cmd->mac[5],
1430 p_filter_cmd->vlan);
1431
1432 return 0;
1433}
1434
1435/*******************************************************************************
1436 * Description:
1437 * Calculates crc 32 on a buffer
1438 * Note: crc32_length MUST be aligned to 8
1439 * Return:
1440 ******************************************************************************/
1441static u32 qed_calc_crc32c(u8 *crc32_packet,
1a635e48 1442 u32 crc32_length, u32 crc32_seed, u8 complement)
cee4d264 1443{
1a635e48
YM		 1444 u32 byte = 0, bit = 0, crc32_result = crc32_seed;
1445 u8 msb = 0, current_byte = 0;
cee4d264
MC		 1446
1447 if ((!crc32_packet) ||
1448 (crc32_length == 0) ||
1449 ((crc32_length % 8) != 0))
1450 return crc32_result;
1451 for (byte = 0; byte < crc32_length; byte++) {
1452 current_byte = crc32_packet[byte];
1453 for (bit = 0; bit < 8; bit++) {
1454 msb = (u8)(crc32_result >> 31);
1455 crc32_result = crc32_result << 1;
1456 if (msb != (0x1 & (current_byte >> bit))) {
1457 crc32_result = crc32_result ^ CRC32_POLY;
1458 crc32_result |= 1; /*crc32_result[0] = 1;*/
1459 }
1460 }
1461 }
1462 return crc32_result;
1463}
1464
1a635e48 1465static u32 qed_crc32c_le(u32 seed, u8 *mac, u32 len)
cee4d264
MC		 1466{
1467 u32 packet_buf[2] = { 0 };
1468
1469 memcpy((u8 *)(&packet_buf[0]), &mac[0], 6);
1470 return qed_calc_crc32c((u8 *)packet_buf, 8, seed, 0);
1471}
1472
dacd88d6 1473u8 qed_mcast_bin_from_mac(u8 *mac)
cee4d264
MC		 1474{
1475 u32 crc = qed_crc32c_le(ETH_MULTICAST_BIN_FROM_MAC_SEED,
1476 mac, ETH_ALEN);
1477
1478 return crc & 0xff;
1479}
1480
1481static int
1482qed_sp_eth_filter_mcast(struct qed_hwfn *p_hwfn,
1483 u16 opaque_fid,
1484 struct qed_filter_mcast *p_filter_cmd,
1485 enum spq_mode comp_mode,
1486 struct qed_spq_comp_cb *p_comp_data)
1487{
cee4d264 1488 struct vport_update_ramrod_data *p_ramrod = NULL;
25c020a9 1489 u32 bins[ETH_MULTICAST_MAC_BINS_IN_REGS];
cee4d264 1490 struct qed_spq_entry *p_ent = NULL;
06f56b81 1491 struct qed_sp_init_data init_data;
cee4d264
MC		 1492 u8 abs_vport_id = 0;
1493 int rc, i;
1494
83aeb933 1495 if (p_filter_cmd->opcode == QED_FILTER_ADD)
cee4d264
MC		 1496 rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to,
1497 &abs_vport_id);
83aeb933 1498 else
cee4d264
MC		 1499 rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from,
1500 &abs_vport_id);
83aeb933
YM		 1501 if (rc)
1502 return rc;
cee4d264 1503
06f56b81
YM		 1504 /* Get SPQ entry */
1505 memset(&init_data, 0, sizeof(init_data));
1506 init_data.cid = qed_spq_get_cid(p_hwfn);
1507 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
1508 init_data.comp_mode = comp_mode;
1509 init_data.p_comp_data = p_comp_data;
cee4d264
MC		 1510
1511 rc = qed_sp_init_request(p_hwfn, &p_ent,
cee4d264 1512 ETH_RAMROD_VPORT_UPDATE,
06f56b81 1513 PROTOCOLID_ETH, &init_data);
cee4d264
MC		 1514 if (rc) {
1515 DP_ERR(p_hwfn, "Multi-cast command failed %d\n", rc);
1516 return rc;
1517 }
1518
1519 p_ramrod = &p_ent->ramrod.vport_update;
1520 p_ramrod->common.update_approx_mcast_flg = 1;
1521
1522 /* explicitly clear out the entire vector */
1523 memset(&p_ramrod->approx_mcast.bins, 0,
1524 sizeof(p_ramrod->approx_mcast.bins));
25c020a9 1525 memset(bins, 0, sizeof(bins));
cee4d264
MC		 1526 /* filter ADD op is explicit set op and it removes
1527 * any existing filters for the vport
1528 */
1529 if (p_filter_cmd->opcode == QED_FILTER_ADD) {
1530 for (i = 0; i < p_filter_cmd->num_mc_addrs; i++) {
25c020a9 1531 u32 bit, nbits;
cee4d264
MC		 1532
1533 bit = qed_mcast_bin_from_mac(p_filter_cmd->mac[i]);
25c020a9
SRK		 1534 nbits = sizeof(u32) * BITS_PER_BYTE;
1535 bins[bit / nbits] |= 1 << (bit % nbits);
cee4d264
MC		 1536 }
1537
1538 /* Convert to correct endianity */
1539 for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) {
1a635e48 1540 struct vport_update_ramrod_mcast *p_ramrod_bins;
cee4d264 1541
1a635e48 1542 p_ramrod_bins = &p_ramrod->approx_mcast;
25c020a9 1543 p_ramrod_bins->bins[i] = cpu_to_le32(bins[i]);
cee4d264
MC		 1544 }
1545 }
1546
1547 p_ramrod->common.vport_id = abs_vport_id;
1548
1549 return qed_spq_post(p_hwfn, p_ent, NULL);
1550}
1551
dacd88d6
YM		 1552static int qed_filter_mcast_cmd(struct qed_dev *cdev,
1553 struct qed_filter_mcast *p_filter_cmd,
1554 enum spq_mode comp_mode,
1555 struct qed_spq_comp_cb *p_comp_data)
cee4d264
MC		 1556{
1557 int rc = 0;
1558 int i;
1559
1560 /* only ADD and REMOVE operations are supported for multi-cast */
1561 if ((p_filter_cmd->opcode != QED_FILTER_ADD &&
1562 (p_filter_cmd->opcode != QED_FILTER_REMOVE)) ||
1563 (p_filter_cmd->num_mc_addrs > QED_MAX_MC_ADDRS))
1564 return -EINVAL;
1565
1566 for_each_hwfn(cdev, i) {
1567 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1568
1569 u16 opaque_fid;
1570
dacd88d6
YM		 1571 if (IS_VF(cdev)) {
1572 qed_vf_pf_filter_mcast(p_hwfn, p_filter_cmd);
1573 continue;
1574 }
cee4d264
MC		 1575
1576 opaque_fid = p_hwfn->hw_info.opaque_fid;
1577
1578 rc = qed_sp_eth_filter_mcast(p_hwfn,
1579 opaque_fid,
1580 p_filter_cmd,
1a635e48 1581 comp_mode, p_comp_data);
cee4d264
MC		 1582 }
1583 return rc;
1584}
1585
1586static int qed_filter_ucast_cmd(struct qed_dev *cdev,
1587 struct qed_filter_ucast *p_filter_cmd,
1588 enum spq_mode comp_mode,
1589 struct qed_spq_comp_cb *p_comp_data)
1590{
1591 int rc = 0;
1592 int i;
1593
1594 for_each_hwfn(cdev, i) {
1595 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1596 u16 opaque_fid;
1597
dacd88d6
YM		 1598 if (IS_VF(cdev)) {
1599 rc = qed_vf_pf_filter_ucast(p_hwfn, p_filter_cmd);
1600 continue;
1601 }
cee4d264
MC		 1602
1603 opaque_fid = p_hwfn->hw_info.opaque_fid;
1604
1605 rc = qed_sp_eth_filter_ucast(p_hwfn,
1606 opaque_fid,
1607 p_filter_cmd,
1a635e48
YM		 1608 comp_mode, p_comp_data);
1609 if (rc)
dacd88d6 1610 break;
cee4d264
MC		 1611 }
1612
1613 return rc;
1614}
1615
86622ee7
YM		 1616/* Statistics related code */
1617static void __qed_get_vport_pstats_addrlen(struct qed_hwfn *p_hwfn,
1618 u32 *p_addr,
dacd88d6 1619 u32 *p_len, u16 statistics_bin)
86622ee7 1620{
dacd88d6
YM		 1621 if (IS_PF(p_hwfn->cdev)) {
1622 *p_addr = BAR0_MAP_REG_PSDM_RAM +
1623 PSTORM_QUEUE_STAT_OFFSET(statistics_bin);
1624 *p_len = sizeof(struct eth_pstorm_per_queue_stat);
1625 } else {
1626 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
1627 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1628
1629 *p_addr = p_resp->pfdev_info.stats_info.pstats.address;
1630 *p_len = p_resp->pfdev_info.stats_info.pstats.len;
1631 }
86622ee7
YM		 1632}
1633
1634static void __qed_get_vport_pstats(struct qed_hwfn *p_hwfn,
1635 struct qed_ptt *p_ptt,
1636 struct qed_eth_stats *p_stats,
1637 u16 statistics_bin)
1638{
1639 struct eth_pstorm_per_queue_stat pstats;
1640 u32 pstats_addr = 0, pstats_len = 0;
1641
1642 __qed_get_vport_pstats_addrlen(p_hwfn, &pstats_addr, &pstats_len,
1643 statistics_bin);
1644
1645 memset(&pstats, 0, sizeof(pstats));
dacd88d6
YM		 1646 qed_memcpy_from(p_hwfn, p_ptt, &pstats, pstats_addr, pstats_len);
1647
9c79ddaa
MY		 1648 p_stats->common.tx_ucast_bytes +=
1649 HILO_64_REGPAIR(pstats.sent_ucast_bytes);
1650 p_stats->common.tx_mcast_bytes +=
1651 HILO_64_REGPAIR(pstats.sent_mcast_bytes);
1652 p_stats->common.tx_bcast_bytes +=
1653 HILO_64_REGPAIR(pstats.sent_bcast_bytes);
1654 p_stats->common.tx_ucast_pkts +=
1655 HILO_64_REGPAIR(pstats.sent_ucast_pkts);
1656 p_stats->common.tx_mcast_pkts +=
1657 HILO_64_REGPAIR(pstats.sent_mcast_pkts);
1658 p_stats->common.tx_bcast_pkts +=
1659 HILO_64_REGPAIR(pstats.sent_bcast_pkts);
1660 p_stats->common.tx_err_drop_pkts +=
1661 HILO_64_REGPAIR(pstats.error_drop_pkts);
86622ee7
YM		 1662}
1663
1664static void __qed_get_vport_tstats(struct qed_hwfn *p_hwfn,
1665 struct qed_ptt *p_ptt,
1666 struct qed_eth_stats *p_stats,
1667 u16 statistics_bin)
1668{
86622ee7 1669 struct tstorm_per_port_stat tstats;
dacd88d6 1670 u32 tstats_addr, tstats_len;
86622ee7 1671
dacd88d6
YM		 1672 if (IS_PF(p_hwfn->cdev)) {
1673 tstats_addr = BAR0_MAP_REG_TSDM_RAM +
1674 TSTORM_PORT_STAT_OFFSET(MFW_PORT(p_hwfn));
1675 tstats_len = sizeof(struct tstorm_per_port_stat);
1676 } else {
1677 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
1678 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1679
1680 tstats_addr = p_resp->pfdev_info.stats_info.tstats.address;
1681 tstats_len = p_resp->pfdev_info.stats_info.tstats.len;
1682 }
86622ee7
YM		 1683
1684 memset(&tstats, 0, sizeof(tstats));
dacd88d6 1685 qed_memcpy_from(p_hwfn, p_ptt, &tstats, tstats_addr, tstats_len);
86622ee7 1686
9c79ddaa
MY		 1687 p_stats->common.mftag_filter_discards +=
1688 HILO_64_REGPAIR(tstats.mftag_filter_discard);
1689 p_stats->common.mac_filter_discards +=
1690 HILO_64_REGPAIR(tstats.eth_mac_filter_discard);
608e00d0
MC		 1691 p_stats->common.gft_filter_drop +=
1692 HILO_64_REGPAIR(tstats.eth_gft_drop_pkt);
86622ee7
YM		 1693}
1694
1695static void __qed_get_vport_ustats_addrlen(struct qed_hwfn *p_hwfn,
1696 u32 *p_addr,
dacd88d6 1697 u32 *p_len, u16 statistics_bin)
86622ee7 1698{
dacd88d6
YM		 1699 if (IS_PF(p_hwfn->cdev)) {
1700 *p_addr = BAR0_MAP_REG_USDM_RAM +
1701 USTORM_QUEUE_STAT_OFFSET(statistics_bin);
1702 *p_len = sizeof(struct eth_ustorm_per_queue_stat);
1703 } else {
1704 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
1705 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1706
1707 *p_addr = p_resp->pfdev_info.stats_info.ustats.address;
1708 *p_len = p_resp->pfdev_info.stats_info.ustats.len;
1709 }
86622ee7
YM		 1710}
1711
1712static void __qed_get_vport_ustats(struct qed_hwfn *p_hwfn,
1713 struct qed_ptt *p_ptt,
1714 struct qed_eth_stats *p_stats,
1715 u16 statistics_bin)
1716{
1717 struct eth_ustorm_per_queue_stat ustats;
1718 u32 ustats_addr = 0, ustats_len = 0;
1719
1720 __qed_get_vport_ustats_addrlen(p_hwfn, &ustats_addr, &ustats_len,
1721 statistics_bin);
1722
1723 memset(&ustats, 0, sizeof(ustats));
dacd88d6
YM		 1724 qed_memcpy_from(p_hwfn, p_ptt, &ustats, ustats_addr, ustats_len);
1725
9c79ddaa
MY		 1726 p_stats->common.rx_ucast_bytes +=
1727 HILO_64_REGPAIR(ustats.rcv_ucast_bytes);
1728 p_stats->common.rx_mcast_bytes +=
1729 HILO_64_REGPAIR(ustats.rcv_mcast_bytes);
1730 p_stats->common.rx_bcast_bytes +=
1731 HILO_64_REGPAIR(ustats.rcv_bcast_bytes);
1732 p_stats->common.rx_ucast_pkts += HILO_64_REGPAIR(ustats.rcv_ucast_pkts);
1733 p_stats->common.rx_mcast_pkts += HILO_64_REGPAIR(ustats.rcv_mcast_pkts);
1734 p_stats->common.rx_bcast_pkts += HILO_64_REGPAIR(ustats.rcv_bcast_pkts);
86622ee7
YM		 1735}
1736
1737static void __qed_get_vport_mstats_addrlen(struct qed_hwfn *p_hwfn,
1738 u32 *p_addr,
dacd88d6 1739 u32 *p_len, u16 statistics_bin)
86622ee7 1740{
dacd88d6
YM		 1741 if (IS_PF(p_hwfn->cdev)) {
1742 *p_addr = BAR0_MAP_REG_MSDM_RAM +
1743 MSTORM_QUEUE_STAT_OFFSET(statistics_bin);
1744 *p_len = sizeof(struct eth_mstorm_per_queue_stat);
1745 } else {
1746 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
1747 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1748
1749 *p_addr = p_resp->pfdev_info.stats_info.mstats.address;
1750 *p_len = p_resp->pfdev_info.stats_info.mstats.len;
1751 }
86622ee7
YM		 1752}
1753
1754static void __qed_get_vport_mstats(struct qed_hwfn *p_hwfn,
1755 struct qed_ptt *p_ptt,
1756 struct qed_eth_stats *p_stats,
1757 u16 statistics_bin)
1758{
1759 struct eth_mstorm_per_queue_stat mstats;
1760 u32 mstats_addr = 0, mstats_len = 0;
1761
1762 __qed_get_vport_mstats_addrlen(p_hwfn, &mstats_addr, &mstats_len,
1763 statistics_bin);
1764
1765 memset(&mstats, 0, sizeof(mstats));
dacd88d6 1766 qed_memcpy_from(p_hwfn, p_ptt, &mstats, mstats_addr, mstats_len);
86622ee7 1767
9c79ddaa
MY		 1768 p_stats->common.no_buff_discards +=
1769 HILO_64_REGPAIR(mstats.no_buff_discard);
1770 p_stats->common.packet_too_big_discard +=
1771 HILO_64_REGPAIR(mstats.packet_too_big_discard);
1772 p_stats->common.ttl0_discard += HILO_64_REGPAIR(mstats.ttl0_discard);
1773 p_stats->common.tpa_coalesced_pkts +=
1774 HILO_64_REGPAIR(mstats.tpa_coalesced_pkts);
1775 p_stats->common.tpa_coalesced_events +=
1776 HILO_64_REGPAIR(mstats.tpa_coalesced_events);
1777 p_stats->common.tpa_aborts_num +=
1778 HILO_64_REGPAIR(mstats.tpa_aborts_num);
1779 p_stats->common.tpa_coalesced_bytes +=
1780 HILO_64_REGPAIR(mstats.tpa_coalesced_bytes);
86622ee7
YM		 1781}
1782
1783static void __qed_get_vport_port_stats(struct qed_hwfn *p_hwfn,
1784 struct qed_ptt *p_ptt,
1785 struct qed_eth_stats *p_stats)
1786{
9c79ddaa 1787 struct qed_eth_stats_common *p_common = &p_stats->common;
86622ee7
YM		 1788 struct port_stats port_stats;
1789 int j;
1790
1791 memset(&port_stats, 0, sizeof(port_stats));
1792
1793 qed_memcpy_from(p_hwfn, p_ptt, &port_stats,
1794 p_hwfn->mcp_info->port_addr +
1795 offsetof(struct public_port, stats),
1796 sizeof(port_stats));
1797
9c79ddaa
MY		 1798 p_common->rx_64_byte_packets += port_stats.eth.r64;
1799 p_common->rx_65_to_127_byte_packets += port_stats.eth.r127;
1800 p_common->rx_128_to_255_byte_packets += port_stats.eth.r255;
1801 p_common->rx_256_to_511_byte_packets += port_stats.eth.r511;
1802 p_common->rx_512_to_1023_byte_packets += port_stats.eth.r1023;
1803 p_common->rx_1024_to_1518_byte_packets += port_stats.eth.r1518;
1804 p_common->rx_crc_errors += port_stats.eth.rfcs;
1805 p_common->rx_mac_crtl_frames += port_stats.eth.rxcf;
1806 p_common->rx_pause_frames += port_stats.eth.rxpf;
1807 p_common->rx_pfc_frames += port_stats.eth.rxpp;
1808 p_common->rx_align_errors += port_stats.eth.raln;
1809 p_common->rx_carrier_errors += port_stats.eth.rfcr;
1810 p_common->rx_oversize_packets += port_stats.eth.rovr;
1811 p_common->rx_jabbers += port_stats.eth.rjbr;
1812 p_common->rx_undersize_packets += port_stats.eth.rund;
1813 p_common->rx_fragments += port_stats.eth.rfrg;
1814 p_common->tx_64_byte_packets += port_stats.eth.t64;
1815 p_common->tx_65_to_127_byte_packets += port_stats.eth.t127;
1816 p_common->tx_128_to_255_byte_packets += port_stats.eth.t255;
1817 p_common->tx_256_to_511_byte_packets += port_stats.eth.t511;
1818 p_common->tx_512_to_1023_byte_packets += port_stats.eth.t1023;
1819 p_common->tx_1024_to_1518_byte_packets += port_stats.eth.t1518;
1820 p_common->tx_pause_frames += port_stats.eth.txpf;
1821 p_common->tx_pfc_frames += port_stats.eth.txpp;
1822 p_common->rx_mac_bytes += port_stats.eth.rbyte;
1823 p_common->rx_mac_uc_packets += port_stats.eth.rxuca;
1824 p_common->rx_mac_mc_packets += port_stats.eth.rxmca;
1825 p_common->rx_mac_bc_packets += port_stats.eth.rxbca;
1826 p_common->rx_mac_frames_ok += port_stats.eth.rxpok;
1827 p_common->tx_mac_bytes += port_stats.eth.tbyte;
1828 p_common->tx_mac_uc_packets += port_stats.eth.txuca;
1829 p_common->tx_mac_mc_packets += port_stats.eth.txmca;
1830 p_common->tx_mac_bc_packets += port_stats.eth.txbca;
1831 p_common->tx_mac_ctrl_frames += port_stats.eth.txcf;
86622ee7 1832 for (j = 0; j < 8; j++) {
9c79ddaa
MY		 1833 p_common->brb_truncates += port_stats.brb.brb_truncate[j];
1834 p_common->brb_discards += port_stats.brb.brb_discard[j];
1835 }
1836
1837 if (QED_IS_BB(p_hwfn->cdev)) {
1838 struct qed_eth_stats_bb *p_bb = &p_stats->bb;
1839
1840 p_bb->rx_1519_to_1522_byte_packets +=
1841 port_stats.eth.u0.bb0.r1522;
1842 p_bb->rx_1519_to_2047_byte_packets +=
1843 port_stats.eth.u0.bb0.r2047;
1844 p_bb->rx_2048_to_4095_byte_packets +=
1845 port_stats.eth.u0.bb0.r4095;
1846 p_bb->rx_4096_to_9216_byte_packets +=
1847 port_stats.eth.u0.bb0.r9216;
1848 p_bb->rx_9217_to_16383_byte_packets +=
1849 port_stats.eth.u0.bb0.r16383;
1850 p_bb->tx_1519_to_2047_byte_packets +=
1851 port_stats.eth.u1.bb1.t2047;
1852 p_bb->tx_2048_to_4095_byte_packets +=
1853 port_stats.eth.u1.bb1.t4095;
1854 p_bb->tx_4096_to_9216_byte_packets +=
1855 port_stats.eth.u1.bb1.t9216;
1856 p_bb->tx_9217_to_16383_byte_packets +=
1857 port_stats.eth.u1.bb1.t16383;
1858 p_bb->tx_lpi_entry_count += port_stats.eth.u2.bb2.tlpiec;
1859 p_bb->tx_total_collisions += port_stats.eth.u2.bb2.tncl;
1860 } else {
1861 struct qed_eth_stats_ah *p_ah = &p_stats->ah;
1862
1863 p_ah->rx_1519_to_max_byte_packets +=
1864 port_stats.eth.u0.ah0.r1519_to_max;
1865 p_ah->tx_1519_to_max_byte_packets =
1866 port_stats.eth.u1.ah1.t1519_to_max;
86622ee7 1867 }
32d26a68
SRK		 1868
1869 p_common->link_change_count = qed_rd(p_hwfn, p_ptt,
1870 p_hwfn->mcp_info->port_addr +
1871 offsetof(struct public_port,
1872 link_change_count));
86622ee7
YM		 1873}
1874
1875static void __qed_get_vport_stats(struct qed_hwfn *p_hwfn,
1876 struct qed_ptt *p_ptt,
1877 struct qed_eth_stats *stats,
dacd88d6 1878 u16 statistics_bin, bool b_get_port_stats)
86622ee7
YM		 1879{
1880 __qed_get_vport_mstats(p_hwfn, p_ptt, stats, statistics_bin);
1881 __qed_get_vport_ustats(p_hwfn, p_ptt, stats, statistics_bin);
1882 __qed_get_vport_tstats(p_hwfn, p_ptt, stats, statistics_bin);
1883 __qed_get_vport_pstats(p_hwfn, p_ptt, stats, statistics_bin);
1884
dacd88d6 1885 if (b_get_port_stats && p_hwfn->mcp_info)
86622ee7
YM		 1886 __qed_get_vport_port_stats(p_hwfn, p_ptt, stats);
1887}
1888
1889static void _qed_get_vport_stats(struct qed_dev *cdev,
1890 struct qed_eth_stats *stats)
1891{
dacd88d6
YM		 1892 u8 fw_vport = 0;
1893 int i;
86622ee7
YM		 1894
1895 memset(stats, 0, sizeof(*stats));
1896
1897 for_each_hwfn(cdev, i) {
1898 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
dacd88d6
YM		 1899 struct qed_ptt *p_ptt = IS_PF(cdev) ? qed_ptt_acquire(p_hwfn)
1900 : NULL;
1901
1902 if (IS_PF(cdev)) {
1903 /* The main vport index is relative first */
1904 if (qed_fw_vport(p_hwfn, 0, &fw_vport)) {
1905 DP_ERR(p_hwfn, "No vport available!\n");
1906 goto out;
1907 }
86622ee7
YM		 1908 }
1909
dacd88d6 1910 if (IS_PF(cdev) && !p_ptt) {
86622ee7
YM		 1911 DP_ERR(p_hwfn, "Failed to acquire ptt\n");
1912 continue;
1913 }
1914
dacd88d6
YM		 1915 __qed_get_vport_stats(p_hwfn, p_ptt, stats, fw_vport,
1916 IS_PF(cdev) ? true : false);
86622ee7 1917
dacd88d6
YM		 1918out:
1919 if (IS_PF(cdev) && p_ptt)
1920 qed_ptt_release(p_hwfn, p_ptt);
86622ee7
YM		 1921 }
1922}
1923
1a635e48 1924void qed_get_vport_stats(struct qed_dev *cdev, struct qed_eth_stats *stats)
86622ee7
YM		 1925{
1926 u32 i;
1927
1928 if (!cdev) {
1929 memset(stats, 0, sizeof(*stats));
1930 return;
1931 }
1932
1933 _qed_get_vport_stats(cdev, stats);
1934
1935 if (!cdev->reset_stats)
1936 return;
1937
1938 /* Reduce the statistics baseline */
1939 for (i = 0; i < sizeof(struct qed_eth_stats) / sizeof(u64); i++)
1940 ((u64 *)stats)[i] -= ((u64 *)cdev->reset_stats)[i];
1941}
1942
1943/* zeroes V-PORT specific portion of stats (Port stats remains untouched) */
1944void qed_reset_vport_stats(struct qed_dev *cdev)
1945{
1946 int i;
1947
1948 for_each_hwfn(cdev, i) {
1949 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1950 struct eth_mstorm_per_queue_stat mstats;
1951 struct eth_ustorm_per_queue_stat ustats;
1952 struct eth_pstorm_per_queue_stat pstats;
dacd88d6
YM		 1953 struct qed_ptt *p_ptt = IS_PF(cdev) ? qed_ptt_acquire(p_hwfn)
1954 : NULL;
86622ee7
YM		 1955 u32 addr = 0, len = 0;
1956
dacd88d6 1957 if (IS_PF(cdev) && !p_ptt) {
86622ee7
YM		 1958 DP_ERR(p_hwfn, "Failed to acquire ptt\n");
1959 continue;
1960 }
1961
1962 memset(&mstats, 0, sizeof(mstats));
1963 __qed_get_vport_mstats_addrlen(p_hwfn, &addr, &len, 0);
1964 qed_memcpy_to(p_hwfn, p_ptt, addr, &mstats, len);
1965
1966 memset(&ustats, 0, sizeof(ustats));
1967 __qed_get_vport_ustats_addrlen(p_hwfn, &addr, &len, 0);
1968 qed_memcpy_to(p_hwfn, p_ptt, addr, &ustats, len);
1969
1970 memset(&pstats, 0, sizeof(pstats));
1971 __qed_get_vport_pstats_addrlen(p_hwfn, &addr, &len, 0);
1972 qed_memcpy_to(p_hwfn, p_ptt, addr, &pstats, len);
1973
dacd88d6
YM		 1974 if (IS_PF(cdev))
1975 qed_ptt_release(p_hwfn, p_ptt);
86622ee7
YM		 1976 }
1977
1978 /* PORT statistics are not necessarily reset, so we need to
1979 * read and create a baseline for future statistics.
32d26a68 1980 * Link change stat is maintained by MFW, return its value as is.
86622ee7 1981 */
32d26a68 1982 if (!cdev->reset_stats) {
86622ee7 1983 DP_INFO(cdev, "Reset stats not allocated\n");
32d26a68 1984 } else {
86622ee7 1985 _qed_get_vport_stats(cdev, cdev->reset_stats);
32d26a68
SRK		 1986 cdev->reset_stats->common.link_change_count = 0;
1987 }
86622ee7
YM		 1988}
1989
da090917
TT		 1990static enum gft_profile_type
1991qed_arfs_mode_to_hsi(enum qed_filter_config_mode mode)
1992{
1993 if (mode == QED_FILTER_CONFIG_MODE_5_TUPLE)
1994 return GFT_PROFILE_TYPE_4_TUPLE;
1995 if (mode == QED_FILTER_CONFIG_MODE_IP_DEST)
50bc60cb 1996 return GFT_PROFILE_TYPE_IP_DST_ADDR;
3893fc62
MC		 1997 if (mode == QED_FILTER_CONFIG_MODE_IP_SRC)
1998 return GFT_PROFILE_TYPE_IP_SRC_ADDR;
da090917
TT		 1999 return GFT_PROFILE_TYPE_L4_DST_PORT;
2000}
2001
2002void qed_arfs_mode_configure(struct qed_hwfn *p_hwfn,
2003 struct qed_ptt *p_ptt,
2004 struct qed_arfs_config_params *p_cfg_params)
2005{
2006 if (p_cfg_params->mode != QED_FILTER_CONFIG_MODE_DISABLE) {
2007 qed_gft_config(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
2008 p_cfg_params->tcp,
2009 p_cfg_params->udp,
2010 p_cfg_params->ipv4,
2011 p_cfg_params->ipv6,
2012 qed_arfs_mode_to_hsi(p_cfg_params->mode));
2013 DP_VERBOSE(p_hwfn,
2014 QED_MSG_SP,
2015 "Configured Filtering: tcp = %s, udp = %s, ipv4 = %s, ipv6 =%s mode=%08x\n",
d51e4af5
CM		 2016 p_cfg_params->tcp ? "Enable" : "Disable",
2017 p_cfg_params->udp ? "Enable" : "Disable",
2018 p_cfg_params->ipv4 ? "Enable" : "Disable",
da090917
TT		 2019 p_cfg_params->ipv6 ? "Enable" : "Disable",
2020 (u32)p_cfg_params->mode);
d51e4af5 2021 } else {
da090917
TT		 2022 DP_VERBOSE(p_hwfn, QED_MSG_SP, "Disabled Filtering\n");
2023 qed_gft_disable(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
d51e4af5 2024 }
d51e4af5
CM		 2025}
2026
da090917
TT		 2027int
2028qed_configure_rfs_ntuple_filter(struct qed_hwfn *p_hwfn,
d51e4af5 2029 struct qed_spq_comp_cb *p_cb,
da090917 2030 struct qed_ntuple_filter_params *p_params)
d51e4af5
CM		 2031{
2032 struct rx_update_gft_filter_data *p_ramrod = NULL;
2033 struct qed_spq_entry *p_ent = NULL;
2034 struct qed_sp_init_data init_data;
2035 u16 abs_rx_q_id = 0;
2036 u8 abs_vport_id = 0;
2037 int rc = -EINVAL;
2038
d51e4af5
CM		 2039 /* Get SPQ entry */
2040 memset(&init_data, 0, sizeof(init_data));
2041 init_data.cid = qed_spq_get_cid(p_hwfn);
2042
2043 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
2044
2045 if (p_cb) {
2046 init_data.comp_mode = QED_SPQ_MODE_CB;
2047 init_data.p_comp_data = p_cb;
2048 } else {
2049 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
2050 }
2051
2052 rc = qed_sp_init_request(p_hwfn, &p_ent,
2053 ETH_RAMROD_GFT_UPDATE_FILTER,
2054 PROTOCOLID_ETH, &init_data);
2055 if (rc)
2056 return rc;
2057
2058 p_ramrod = &p_ent->ramrod.rx_update_gft;
da090917
TT		 2059
2060 DMA_REGPAIR_LE(p_ramrod->pkt_hdr_addr, p_params->addr);
2061 p_ramrod->pkt_hdr_length = cpu_to_le16(p_params->length);
2062
608e00d0
MC		 2063 if (p_params->b_is_drop) {
2064 p_ramrod->vport_id = cpu_to_le16(ETH_GFT_TRASHCAN_VPORT);
2065 } else {
2066 rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
2067 if (rc)
fb5e7438 2068 goto err;
608e00d0
MC		 2069
2070 if (p_params->qid != QED_RFS_NTUPLE_QID_RSS) {
2071 rc = qed_fw_l2_queue(p_hwfn, p_params->qid,
2072 &abs_rx_q_id);
2073 if (rc)
fb5e7438 2074 goto err;
608e00d0
MC		 2075
2076 p_ramrod->rx_qid_valid = 1;
2077 p_ramrod->rx_qid = cpu_to_le16(abs_rx_q_id);
2078 }
2079
2080 p_ramrod->vport_id = cpu_to_le16((u16)abs_vport_id);
da090917
TT		 2081 }
2082
2083 p_ramrod->flow_id_valid = 0;
2084 p_ramrod->flow_id = 0;
da090917
TT		 2085 p_ramrod->filter_action = p_params->b_is_add ? GFT_ADD_FILTER
2086 : GFT_DELETE_FILTER;
d51e4af5
CM		 2087
2088 DP_VERBOSE(p_hwfn, QED_MSG_SP,
2089 "V[%0x], Q[%04x] - %s filter from 0x%llx [length %04xb]\n",
2090 abs_vport_id, abs_rx_q_id,
da090917
TT		 2091 p_params->b_is_add ? "Adding" : "Removing",
2092 (u64)p_params->addr, p_params->length);
d51e4af5
CM		 2093
2094 return qed_spq_post(p_hwfn, p_ent, NULL);
fb5e7438
DB		 2095
2096err:
2097 qed_sp_destroy_request(p_hwfn, p_ent);
2098 return rc;
d51e4af5
CM		 2099}
2100
bf5a94bf
RV		 2101int qed_get_rxq_coalesce(struct qed_hwfn *p_hwfn,
2102 struct qed_ptt *p_ptt,
2103 struct qed_queue_cid *p_cid, u16 *p_rx_coal)
2104{
2105 u32 coalesce, address, is_valid;
2106 struct cau_sb_entry sb_entry;
2107 u8 timer_res;
2108 int rc;
2109
2110 rc = qed_dmae_grc2host(p_hwfn, p_ptt, CAU_REG_SB_VAR_MEMORY +
2111 p_cid->sb_igu_id * sizeof(u64),
2112 (u64)(uintptr_t)&sb_entry, 2, 0);
2113 if (rc) {
2114 DP_ERR(p_hwfn, "dmae_grc2host failed %d\n", rc);
2115 return rc;
2116 }
2117
2118 timer_res = GET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES0);
2119
2120 address = BAR0_MAP_REG_USDM_RAM +
2121 USTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
2122 coalesce = qed_rd(p_hwfn, p_ptt, address);
2123
2124 is_valid = GET_FIELD(coalesce, COALESCING_TIMESET_VALID);
2125 if (!is_valid)
2126 return -EINVAL;
2127
2128 coalesce = GET_FIELD(coalesce, COALESCING_TIMESET_TIMESET);
2129 *p_rx_coal = (u16)(coalesce << timer_res);
2130
2131 return 0;
2132}
2133
2134int qed_get_txq_coalesce(struct qed_hwfn *p_hwfn,
2135 struct qed_ptt *p_ptt,
2136 struct qed_queue_cid *p_cid, u16 *p_tx_coal)
2137{
2138 u32 coalesce, address, is_valid;
2139 struct cau_sb_entry sb_entry;
2140 u8 timer_res;
2141 int rc;
2142
2143 rc = qed_dmae_grc2host(p_hwfn, p_ptt, CAU_REG_SB_VAR_MEMORY +
2144 p_cid->sb_igu_id * sizeof(u64),
2145 (u64)(uintptr_t)&sb_entry, 2, 0);
2146 if (rc) {
2147 DP_ERR(p_hwfn, "dmae_grc2host failed %d\n", rc);
2148 return rc;
2149 }
2150
2151 timer_res = GET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES1);
2152
2153 address = BAR0_MAP_REG_XSDM_RAM +
2154 XSTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
2155 coalesce = qed_rd(p_hwfn, p_ptt, address);
2156
2157 is_valid = GET_FIELD(coalesce, COALESCING_TIMESET_VALID);
2158 if (!is_valid)
2159 return -EINVAL;
2160
2161 coalesce = GET_FIELD(coalesce, COALESCING_TIMESET_TIMESET);
2162 *p_tx_coal = (u16)(coalesce << timer_res);
2163
2164 return 0;
2165}
2166
2167int qed_get_queue_coalesce(struct qed_hwfn *p_hwfn, u16 *p_coal, void *handle)
2168{
2169 struct qed_queue_cid *p_cid = handle;
2170 struct qed_ptt *p_ptt;
2171 int rc = 0;
2172
2173 if (IS_VF(p_hwfn->cdev)) {
2174 rc = qed_vf_pf_get_coalesce(p_hwfn, p_coal, p_cid);
2175 if (rc)
2176 DP_NOTICE(p_hwfn, "Unable to read queue coalescing\n");
2177
2178 return rc;
2179 }
2180
2181 p_ptt = qed_ptt_acquire(p_hwfn);
2182 if (!p_ptt)
2183 return -EAGAIN;
2184
2185 if (p_cid->b_is_rx) {
2186 rc = qed_get_rxq_coalesce(p_hwfn, p_ptt, p_cid, p_coal);
2187 if (rc)
2188 goto out;
2189 } else {
2190 rc = qed_get_txq_coalesce(p_hwfn, p_ptt, p_cid, p_coal);
2191 if (rc)
2192 goto out;
2193 }
2194
2195out:
2196 qed_ptt_release(p_hwfn, p_ptt);
2197
2198 return rc;
2199}
2200
25c089d7
YM		 2201static int qed_fill_eth_dev_info(struct qed_dev *cdev,
2202 struct qed_dev_eth_info *info)
2203{
5e7baf0f 2204 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
25c089d7
YM		 2205 int i;
2206
2207 memset(info, 0, sizeof(*info));
2208
1408cc1f 2209 if (IS_PF(cdev)) {
25eb8d46 2210 int max_vf_vlan_filters = 0;
7b7e70f9 2211 int max_vf_mac_filters = 0;
25eb8d46 2212
5e7baf0f
MC		 2213 info->num_tc = p_hwfn->hw_info.num_hw_tc;
2214
1408cc1f 2215 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
e1d32acb
MY		 2216 u16 num_queues = 0;
2217
2218 /* Since the feature controls only queue-zones,
fb1faab7 2219 * make sure we have the contexts [rx, xdp, tcs] to
e1d32acb
MY		 2220 * match.
2221 */
2222 for_each_hwfn(cdev, i) {
2223 struct qed_hwfn *hwfn = &cdev->hwfns[i];
2224 u16 l2_queues = (u16)FEAT_NUM(hwfn,
2225 QED_PF_L2_QUE);
2226 u16 cids;
2227
2228 cids = hwfn->pf_params.eth_pf_params.num_cons;
fb1faab7
SRK		 2229 cids /= (2 + info->num_tc);
2230 num_queues += min_t(u16, l2_queues, cids);
e1d32acb
MY		 2231 }
2232
2233 /* queues might theoretically be >256, but interrupts'
2234 * upper-limit guarantes that it would fit in a u8.
2235 */
2236 if (cdev->int_params.fp_msix_cnt) {
2237 u8 irqs = cdev->int_params.fp_msix_cnt;
2238
2239 info->num_queues = (u8)min_t(u16,
2240 num_queues, irqs);
2241 }
1408cc1f
YM		 2242 } else {
2243 info->num_queues = cdev->num_hwfns;
2244 }
2245
7b7e70f9 2246 if (IS_QED_SRIOV(cdev)) {
25eb8d46
YM		 2247 max_vf_vlan_filters = cdev->p_iov_info->total_vfs *
2248 QED_ETH_VF_NUM_VLAN_FILTERS;
7b7e70f9
YM		 2249 max_vf_mac_filters = cdev->p_iov_info->total_vfs *
2250 QED_ETH_VF_NUM_MAC_FILTERS;
2251 }
2252 info->num_vlan_filters = RESC_NUM(QED_LEADING_HWFN(cdev),
2253 QED_VLAN) -
25eb8d46 2254 max_vf_vlan_filters;
7b7e70f9
YM		 2255 info->num_mac_filters = RESC_NUM(QED_LEADING_HWFN(cdev),
2256 QED_MAC) -
2257 max_vf_mac_filters;
25eb8d46 2258
1408cc1f
YM		 2259 ether_addr_copy(info->port_mac,
2260 cdev->hwfns[0].hw_info.hw_mac_addr);
cbb8a12c
MY		 2261
2262 info->xdp_supported = true;
25c089d7 2263 } else {
cbb8a12c
MY		 2264 u16 total_cids = 0;
2265
5e7baf0f
MC		 2266 info->num_tc = 1;
2267
cbb8a12c
MY		 2268 /* Determine queues & XDP support */
2269 for_each_hwfn(cdev, i) {
2270 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2271 u8 queues, cids;
25c089d7 2272
cbb8a12c
MY		 2273 qed_vf_get_num_cids(p_hwfn, &cids);
2274 qed_vf_get_num_rxqs(p_hwfn, &queues);
1408cc1f 2275 info->num_queues += queues;
cbb8a12c 2276 total_cids += cids;
1408cc1f
YM		 2277 }
2278
cbb8a12c
MY		 2279 /* Enable VF XDP in case PF guarntees sufficient connections */
2280 if (total_cids >= info->num_queues * 3)
2281 info->xdp_supported = true;
2282
1408cc1f 2283 qed_vf_get_num_vlan_filters(&cdev->hwfns[0],
2edbff8d 2284 (u8 *)&info->num_vlan_filters);
b0fca312
MY		 2285 qed_vf_get_num_mac_filters(&cdev->hwfns[0],
2286 (u8 *)&info->num_mac_filters);
1408cc1f 2287 qed_vf_get_port_mac(&cdev->hwfns[0], info->port_mac);
d8c2c7e3
YM		 2288
2289 info->is_legacy = !!cdev->hwfns[0].vf_iov_info->b_pre_fp_hsi;
1408cc1f 2290 }
25c089d7
YM		 2291
2292 qed_fill_dev_info(cdev, &info->common);
2293
1408cc1f 2294 if (IS_VF(cdev))
0ee28e31 2295 eth_zero_addr(info->common.hw_mac);
1408cc1f 2296
25c089d7
YM		 2297 return 0;
2298}
2299
cc875c2e 2300static void qed_register_eth_ops(struct qed_dev *cdev,
1408cc1f 2301 struct qed_eth_cb_ops *ops, void *cookie)
cc875c2e 2302{
1408cc1f
YM		 2303 cdev->protocol_ops.eth = ops;
2304 cdev->ops_cookie = cookie;
2305
2306 /* For VF, we start bulletin reading */
2307 if (IS_VF(cdev))
2308 qed_vf_start_iov_wq(cdev);
cc875c2e
YM		 2309}
2310
eff16960
YM		 2311static bool qed_check_mac(struct qed_dev *cdev, u8 *mac)
2312{
2313 if (IS_PF(cdev))
2314 return true;
2315
2316 return qed_vf_check_mac(&cdev->hwfns[0], mac);
2317}
2318
cee4d264 2319static int qed_start_vport(struct qed_dev *cdev,
088c8618 2320 struct qed_start_vport_params *params)
cee4d264
MC		 2321{
2322 int rc, i;
2323
2324 for_each_hwfn(cdev, i) {
088c8618 2325 struct qed_sp_vport_start_params start = { 0 };
cee4d264
MC		 2326 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2327
088c8618
MC		 2328 start.tpa_mode = params->gro_enable ? QED_TPA_MODE_GRO :
2329 QED_TPA_MODE_NONE;
2330 start.remove_inner_vlan = params->remove_inner_vlan;
08feecd7 2331 start.only_untagged = true; /* untagged only */
088c8618
MC		 2332 start.drop_ttl0 = params->drop_ttl0;
2333 start.opaque_fid = p_hwfn->hw_info.opaque_fid;
2334 start.concrete_fid = p_hwfn->hw_info.concrete_fid;
c78c70fa 2335 start.handle_ptp_pkts = params->handle_ptp_pkts;
088c8618
MC		 2336 start.vport_id = params->vport_id;
2337 start.max_buffers_per_cqe = 16;
2338 start.mtu = params->mtu;
2339
2340 rc = qed_sp_vport_start(p_hwfn, &start);
cee4d264
MC		 2341 if (rc) {
2342 DP_ERR(cdev, "Failed to start VPORT\n");
2343 return rc;
2344 }
2345
15582962
RV		 2346 rc = qed_hw_start_fastpath(p_hwfn);
2347 if (rc) {
2348 DP_ERR(cdev, "Failed to start VPORT fastpath\n");
2349 return rc;
2350 }
cee4d264
MC		 2351
2352 DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
2353 "Started V-PORT %d with MTU %d\n",
088c8618 2354 start.vport_id, start.mtu);
cee4d264
MC		 2355 }
2356
a0d26d5a
YM		 2357 if (params->clear_stats)
2358 qed_reset_vport_stats(cdev);
9df2ed04 2359
cee4d264
MC		 2360 return 0;
2361}
2362
1a635e48 2363static int qed_stop_vport(struct qed_dev *cdev, u8 vport_id)
cee4d264
MC		 2364{
2365 int rc, i;
2366
2367 for_each_hwfn(cdev, i) {
2368 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2369
2370 rc = qed_sp_vport_stop(p_hwfn,
1a635e48 2371 p_hwfn->hw_info.opaque_fid, vport_id);
cee4d264
MC		 2372
2373 if (rc) {
2374 DP_ERR(cdev, "Failed to stop VPORT\n");
2375 return rc;
2376 }
2377 }
2378 return 0;
2379}
2380
f29ffdb6
MY		 2381static int qed_update_vport_rss(struct qed_dev *cdev,
2382 struct qed_update_vport_rss_params *input,
2383 struct qed_rss_params *rss)
2384{
2385 int i, fn;
2386
2387 /* Update configuration with what's correct regardless of CMT */
2388 rss->update_rss_config = 1;
2389 rss->rss_enable = 1;
2390 rss->update_rss_capabilities = 1;
2391 rss->update_rss_ind_table = 1;
2392 rss->update_rss_key = 1;
2393 rss->rss_caps = input->rss_caps;
2394 memcpy(rss->rss_key, input->rss_key, QED_RSS_KEY_SIZE * sizeof(u32));
2395
2396 /* In regular scenario, we'd simply need to take input handlers.
2397 * But in CMT, we'd have to split the handlers according to the
2398 * engine they were configured on. We'd then have to understand
2399 * whether RSS is really required, since 2-queues on CMT doesn't
2400 * require RSS.
2401 */
2402 if (cdev->num_hwfns == 1) {
2403 memcpy(rss->rss_ind_table,
2404 input->rss_ind_table,
2405 QED_RSS_IND_TABLE_SIZE * sizeof(void *));
2406 rss->rss_table_size_log = 7;
2407 return 0;
2408 }
2409
2410 /* Start by copying the non-spcific information to the 2nd copy */
2411 memcpy(&rss[1], &rss[0], sizeof(struct qed_rss_params));
2412
2413 /* CMT should be round-robin */
2414 for (i = 0; i < QED_RSS_IND_TABLE_SIZE; i++) {
2415 struct qed_queue_cid *cid = input->rss_ind_table[i];
2416 struct qed_rss_params *t_rss;
2417
2418 if (cid->p_owner == QED_LEADING_HWFN(cdev))
2419 t_rss = &rss[0];
2420 else
2421 t_rss = &rss[1];
2422
2423 t_rss->rss_ind_table[i / cdev->num_hwfns] = cid;
2424 }
2425
2426 /* Make sure RSS is actually required */
2427 for_each_hwfn(cdev, fn) {
2428 for (i = 1; i < QED_RSS_IND_TABLE_SIZE / cdev->num_hwfns; i++) {
2429 if (rss[fn].rss_ind_table[i] !=
2430 rss[fn].rss_ind_table[0])
2431 break;
2432 }
2433 if (i == QED_RSS_IND_TABLE_SIZE / cdev->num_hwfns) {
2434 DP_VERBOSE(cdev, NETIF_MSG_IFUP,
2435 "CMT - 1 queue per-hwfn; Disabling RSS\n");
2436 return -EINVAL;
2437 }
2438 rss[fn].rss_table_size_log = 6;
2439 }
2440
2441 return 0;
2442}
2443
cee4d264
MC		 2444static int qed_update_vport(struct qed_dev *cdev,
2445 struct qed_update_vport_params *params)
2446{
2447 struct qed_sp_vport_update_params sp_params;
f29ffdb6
MY		 2448 struct qed_rss_params *rss;
2449 int rc = 0, i;
cee4d264
MC		 2450
2451 if (!cdev)
2452 return -ENODEV;
2453
fad953ce 2454 rss = vzalloc(array_size(sizeof(*rss), cdev->num_hwfns));
f29ffdb6
MY		 2455 if (!rss)
2456 return -ENOMEM;
2457
cee4d264 2458 memset(&sp_params, 0, sizeof(sp_params));
cee4d264
MC		 2459
2460 /* Translate protocol params into sp params */
2461 sp_params.vport_id = params->vport_id;
1a635e48
YM		 2462 sp_params.update_vport_active_rx_flg = params->update_vport_active_flg;
2463 sp_params.update_vport_active_tx_flg = params->update_vport_active_flg;
cee4d264
MC		 2464 sp_params.vport_active_rx_flg = params->vport_active_flg;
2465 sp_params.vport_active_tx_flg = params->vport_active_flg;
831bfb0e
YM		 2466 sp_params.update_tx_switching_flg = params->update_tx_switching_flg;
2467 sp_params.tx_switching_flg = params->tx_switching_flg;
3f9b4a69
YM		 2468 sp_params.accept_any_vlan = params->accept_any_vlan;
2469 sp_params.update_accept_any_vlan_flg =
2470 params->update_accept_any_vlan_flg;
cee4d264 2471
f29ffdb6
MY		 2472 /* Prepare the RSS configuration */
2473 if (params->update_rss_flg)
2474 if (qed_update_vport_rss(cdev, &params->rss_params, rss))
cee4d264 2475 params->update_rss_flg = 0;
cee4d264
MC		 2476
2477 for_each_hwfn(cdev, i) {
2478 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2479
f29ffdb6
MY		 2480 if (params->update_rss_flg)
2481 sp_params.rss_params = &rss[i];
2482
cee4d264
MC		 2483 sp_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2484 rc = qed_sp_vport_update(p_hwfn, &sp_params,
2485 QED_SPQ_MODE_EBLOCK,
2486 NULL);
2487 if (rc) {
2488 DP_ERR(cdev, "Failed to update VPORT\n");
f29ffdb6 2489 goto out;
cee4d264
MC		 2490 }
2491
2492 DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
2493 "Updated V-PORT %d: active_flag %d [update %d]\n",
2494 params->vport_id, params->vport_active_flg,
2495 params->update_vport_active_flg);
2496 }
2497
f29ffdb6
MY		 2498out:
2499 vfree(rss);
2500 return rc;
cee4d264
MC		 2501}
2502
2503static int qed_start_rxq(struct qed_dev *cdev,
3da7a37a
MY		 2504 u8 rss_num,
2505 struct qed_queue_start_common_params *p_params,
cee4d264
MC		 2506 u16 bd_max_bytes,
2507 dma_addr_t bd_chain_phys_addr,
2508 dma_addr_t cqe_pbl_addr,
2509 u16 cqe_pbl_size,
3da7a37a 2510 struct qed_rxq_start_ret_params *ret_params)
cee4d264 2511{
cee4d264 2512 struct qed_hwfn *p_hwfn;
1a635e48 2513 int rc, hwfn_index;
cee4d264 2514
3da7a37a 2515 hwfn_index = rss_num % cdev->num_hwfns;
cee4d264
MC		 2516 p_hwfn = &cdev->hwfns[hwfn_index];
2517
3da7a37a
MY		 2518 p_params->queue_id = p_params->queue_id / cdev->num_hwfns;
2519 p_params->stats_id = p_params->vport_id;
cee4d264 2520
3da7a37a
MY		 2521 rc = qed_eth_rx_queue_start(p_hwfn,
2522 p_hwfn->hw_info.opaque_fid,
2523 p_params,
2524 bd_max_bytes,
2525 bd_chain_phys_addr,
2526 cqe_pbl_addr, cqe_pbl_size, ret_params);
cee4d264 2527 if (rc) {
3da7a37a 2528 DP_ERR(cdev, "Failed to start RXQ#%d\n", p_params->queue_id);
cee4d264
MC		 2529 return rc;
2530 }
2531
2532 DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
f604b17d 2533 "Started RX-Q %d [rss_num %d] on V-PORT %d and SB igu %d\n",
3da7a37a 2534 p_params->queue_id, rss_num, p_params->vport_id,
f604b17d 2535 p_params->p_sb->igu_sb_id);
cee4d264
MC		 2536
2537 return 0;
2538}
2539
3da7a37a 2540static int qed_stop_rxq(struct qed_dev *cdev, u8 rss_id, void *handle)
cee4d264
MC		 2541{
2542 int rc, hwfn_index;
2543 struct qed_hwfn *p_hwfn;
2544
3da7a37a
MY		 2545 hwfn_index = rss_id % cdev->num_hwfns;
2546 p_hwfn = &cdev->hwfns[hwfn_index];
cee4d264 2547
3da7a37a 2548 rc = qed_eth_rx_queue_stop(p_hwfn, handle, false, false);
cee4d264 2549 if (rc) {
3da7a37a 2550 DP_ERR(cdev, "Failed to stop RXQ#%02x\n", rss_id);
cee4d264
MC		 2551 return rc;
2552 }
2553
2554 return 0;
2555}
2556
2557static int qed_start_txq(struct qed_dev *cdev,
3da7a37a 2558 u8 rss_num,
cee4d264
MC		 2559 struct qed_queue_start_common_params *p_params,
2560 dma_addr_t pbl_addr,
2561 u16 pbl_size,
3da7a37a 2562 struct qed_txq_start_ret_params *ret_params)
cee4d264
MC		 2563{
2564 struct qed_hwfn *p_hwfn;
2565 int rc, hwfn_index;
2566
3da7a37a
MY		 2567 hwfn_index = rss_num % cdev->num_hwfns;
2568 p_hwfn = &cdev->hwfns[hwfn_index];
2569 p_params->queue_id = p_params->queue_id / cdev->num_hwfns;
2570 p_params->stats_id = p_params->vport_id;
cee4d264 2571
3da7a37a
MY		 2572 rc = qed_eth_tx_queue_start(p_hwfn,
2573 p_hwfn->hw_info.opaque_fid,
5e7baf0f 2574 p_params, p_params->tc,
3da7a37a 2575 pbl_addr, pbl_size, ret_params);
cee4d264
MC		 2576
2577 if (rc) {
2578 DP_ERR(cdev, "Failed to start TXQ#%d\n", p_params->queue_id);
2579 return rc;
2580 }
2581
2582 DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
f604b17d 2583 "Started TX-Q %d [rss_num %d] on V-PORT %d and SB igu %d\n",
3da7a37a 2584 p_params->queue_id, rss_num, p_params->vport_id,
f604b17d 2585 p_params->p_sb->igu_sb_id);
cee4d264
MC		 2586
2587 return 0;
2588}
2589
2590#define QED_HW_STOP_RETRY_LIMIT (10)
2591static int qed_fastpath_stop(struct qed_dev *cdev)
2592{
15582962
RV		 2593 int rc;
2594
2595 rc = qed_hw_stop_fastpath(cdev);
2596 if (rc) {
2597 DP_ERR(cdev, "Failed to stop Fastpath\n");
2598 return rc;
2599 }
cee4d264
MC		 2600
2601 return 0;
2602}
2603
3da7a37a 2604static int qed_stop_txq(struct qed_dev *cdev, u8 rss_id, void *handle)
cee4d264
MC		 2605{
2606 struct qed_hwfn *p_hwfn;
2607 int rc, hwfn_index;
2608
3da7a37a
MY		 2609 hwfn_index = rss_id % cdev->num_hwfns;
2610 p_hwfn = &cdev->hwfns[hwfn_index];
cee4d264 2611
3da7a37a 2612 rc = qed_eth_tx_queue_stop(p_hwfn, handle);
cee4d264 2613 if (rc) {
3da7a37a 2614 DP_ERR(cdev, "Failed to stop TXQ#%02x\n", rss_id);
cee4d264
MC		 2615 return rc;
2616 }
2617
2618 return 0;
2619}
2620
464f6645
MC		 2621static int qed_tunn_configure(struct qed_dev *cdev,
2622 struct qed_tunn_params *tunn_params)
2623{
19968430 2624 struct qed_tunnel_info tunn_info;
464f6645
MC		 2625 int i, rc;
2626
2627 memset(&tunn_info, 0, sizeof(tunn_info));
19968430
CM		 2628 if (tunn_params->update_vxlan_port) {
2629 tunn_info.vxlan_port.b_update_port = true;
2630 tunn_info.vxlan_port.port = tunn_params->vxlan_port;
464f6645
MC		 2631 }
2632
19968430
CM		 2633 if (tunn_params->update_geneve_port) {
2634 tunn_info.geneve_port.b_update_port = true;
2635 tunn_info.geneve_port.port = tunn_params->geneve_port;
464f6645
MC		 2636 }
2637
2638 for_each_hwfn(cdev, i) {
2639 struct qed_hwfn *hwfn = &cdev->hwfns[i];
4f64675f 2640 struct qed_ptt *p_ptt;
97379f15
CM		 2641 struct qed_tunnel_info *tun;
2642
2643 tun = &hwfn->cdev->tunnel;
4f64675f
MC		 2644 if (IS_PF(cdev)) {
2645 p_ptt = qed_ptt_acquire(hwfn);
2646 if (!p_ptt)
2647 return -EAGAIN;
2648 } else {
2649 p_ptt = NULL;
2650 }
464f6645 2651
4f64675f 2652 rc = qed_sp_pf_update_tunn_cfg(hwfn, p_ptt, &tunn_info,
464f6645 2653 QED_SPQ_MODE_EBLOCK, NULL);
4f64675f
MC		 2654 if (rc) {
2655 if (IS_PF(cdev))
2656 qed_ptt_release(hwfn, p_ptt);
464f6645 2657 return rc;
4f64675f 2658 }
97379f15
CM		 2659
2660 if (IS_PF_SRIOV(hwfn)) {
2661 u16 vxlan_port, geneve_port;
2662 int j;
2663
2664 vxlan_port = tun->vxlan_port.port;
2665 geneve_port = tun->geneve_port.port;
2666
2667 qed_for_each_vf(hwfn, j) {
2668 qed_iov_bulletin_set_udp_ports(hwfn, j,
2669 vxlan_port,
2670 geneve_port);
2671 }
2672
2673 qed_schedule_iov(hwfn, QED_IOV_WQ_BULLETIN_UPDATE_FLAG);
2674 }
4f64675f
MC		 2675 if (IS_PF(cdev))
2676 qed_ptt_release(hwfn, p_ptt);
464f6645
MC		 2677 }
2678
2679 return 0;
2680}
2681
cee4d264
MC		 2682static int qed_configure_filter_rx_mode(struct qed_dev *cdev,
2683 enum qed_filter_rx_mode_type type)
2684{
2685 struct qed_filter_accept_flags accept_flags;
2686
2687 memset(&accept_flags, 0, sizeof(accept_flags));
2688
1a635e48
YM		 2689 accept_flags.update_rx_mode_config = 1;
2690 accept_flags.update_tx_mode_config = 1;
2691 accept_flags.rx_accept_filter = QED_ACCEPT_UCAST_MATCHED |
2692 QED_ACCEPT_MCAST_MATCHED |
2693 QED_ACCEPT_BCAST;
cee4d264
MC		 2694 accept_flags.tx_accept_filter = QED_ACCEPT_UCAST_MATCHED |
2695 QED_ACCEPT_MCAST_MATCHED |
2696 QED_ACCEPT_BCAST;
2697
88067876 2698 if (type == QED_FILTER_RX_MODE_TYPE_PROMISC) {
cee4d264
MC		 2699 accept_flags.rx_accept_filter |= QED_ACCEPT_UCAST_UNMATCHED |
2700 QED_ACCEPT_MCAST_UNMATCHED;
9e71a15d
MC		 2701 accept_flags.tx_accept_filter |= QED_ACCEPT_UCAST_UNMATCHED |
2702 QED_ACCEPT_MCAST_UNMATCHED;
88067876 2703 } else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC) {
cee4d264 2704 accept_flags.rx_accept_filter |= QED_ACCEPT_MCAST_UNMATCHED;
88067876
MY		 2705 accept_flags.tx_accept_filter |= QED_ACCEPT_MCAST_UNMATCHED;
2706 }
cee4d264 2707
3f9b4a69 2708 return qed_filter_accept_cmd(cdev, 0, accept_flags, false, false,
cee4d264
MC		 2709 QED_SPQ_MODE_CB, NULL);
2710}
2711
2712static int qed_configure_filter_ucast(struct qed_dev *cdev,
2713 struct qed_filter_ucast_params *params)
2714{
2715 struct qed_filter_ucast ucast;
2716
2717 if (!params->vlan_valid && !params->mac_valid) {
1a635e48
YM		 2718 DP_NOTICE(cdev,
2719 "Tried configuring a unicast filter, but both MAC and VLAN are not set\n");
cee4d264
MC		 2720 return -EINVAL;
2721 }
2722
2723 memset(&ucast, 0, sizeof(ucast));
2724 switch (params->type) {
2725 case QED_FILTER_XCAST_TYPE_ADD:
2726 ucast.opcode = QED_FILTER_ADD;
2727 break;
2728 case QED_FILTER_XCAST_TYPE_DEL:
2729 ucast.opcode = QED_FILTER_REMOVE;
2730 break;
2731 case QED_FILTER_XCAST_TYPE_REPLACE:
2732 ucast.opcode = QED_FILTER_REPLACE;
2733 break;
2734 default:
2735 DP_NOTICE(cdev, "Unknown unicast filter type %d\n",
2736 params->type);
2737 }
2738
2739 if (params->vlan_valid && params->mac_valid) {
2740 ucast.type = QED_FILTER_MAC_VLAN;
2741 ether_addr_copy(ucast.mac, params->mac);
2742 ucast.vlan = params->vlan;
2743 } else if (params->mac_valid) {
2744 ucast.type = QED_FILTER_MAC;
2745 ether_addr_copy(ucast.mac, params->mac);
2746 } else {
2747 ucast.type = QED_FILTER_VLAN;
2748 ucast.vlan = params->vlan;
2749 }
2750
2751 ucast.is_rx_filter = true;
2752 ucast.is_tx_filter = true;
2753
2754 return qed_filter_ucast_cmd(cdev, &ucast, QED_SPQ_MODE_CB, NULL);
2755}
2756
2757static int qed_configure_filter_mcast(struct qed_dev *cdev,
2758 struct qed_filter_mcast_params *params)
2759{
2760 struct qed_filter_mcast mcast;
2761 int i;
2762
2763 memset(&mcast, 0, sizeof(mcast));
2764 switch (params->type) {
2765 case QED_FILTER_XCAST_TYPE_ADD:
2766 mcast.opcode = QED_FILTER_ADD;
2767 break;
2768 case QED_FILTER_XCAST_TYPE_DEL:
2769 mcast.opcode = QED_FILTER_REMOVE;
2770 break;
2771 default:
2772 DP_NOTICE(cdev, "Unknown multicast filter type %d\n",
2773 params->type);
2774 }
2775
2776 mcast.num_mc_addrs = params->num;
2777 for (i = 0; i < mcast.num_mc_addrs; i++)
2778 ether_addr_copy(mcast.mac[i], params->mac[i]);
2779
1a635e48 2780 return qed_filter_mcast_cmd(cdev, &mcast, QED_SPQ_MODE_CB, NULL);
cee4d264
MC		 2781}
2782
2783static int qed_configure_filter(struct qed_dev *cdev,
2784 struct qed_filter_params *params)
2785{
2786 enum qed_filter_rx_mode_type accept_flags;
2787
2788 switch (params->type) {
2789 case QED_FILTER_TYPE_UCAST:
2790 return qed_configure_filter_ucast(cdev, &params->filter.ucast);
2791 case QED_FILTER_TYPE_MCAST:
2792 return qed_configure_filter_mcast(cdev, &params->filter.mcast);
2793 case QED_FILTER_TYPE_RX_MODE:
2794 accept_flags = params->filter.accept_flags;
2795 return qed_configure_filter_rx_mode(cdev, accept_flags);
2796 default:
1a635e48 2797 DP_NOTICE(cdev, "Unknown filter type %d\n", (int)params->type);
cee4d264
MC		 2798 return -EINVAL;
2799 }
2800}
2801
da090917
TT		 2802static int qed_configure_arfs_searcher(struct qed_dev *cdev,
2803 enum qed_filter_config_mode mode)
d51e4af5
CM		 2804{
2805 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
2806 struct qed_arfs_config_params arfs_config_params;
2807
2808 memset(&arfs_config_params, 0, sizeof(arfs_config_params));
2809 arfs_config_params.tcp = true;
2810 arfs_config_params.udp = true;
2811 arfs_config_params.ipv4 = true;
2812 arfs_config_params.ipv6 = true;
da090917 2813 arfs_config_params.mode = mode;
d51e4af5
CM		 2814 qed_arfs_mode_configure(p_hwfn, p_hwfn->p_arfs_ptt,
2815 &arfs_config_params);
2816 return 0;
2817}
2818
2819static void
2820qed_arfs_sp_response_handler(struct qed_hwfn *p_hwfn,
da090917
TT		 2821 void *cookie,
2822 union event_ring_data *data, u8 fw_return_code)
d51e4af5
CM		 2823{
2824 struct qed_common_cb_ops *op = p_hwfn->cdev->protocol_ops.common;
2825 void *dev = p_hwfn->cdev->ops_cookie;
2826
2827 op->arfs_filter_op(dev, cookie, fw_return_code);
2828}
2829
da090917
TT		 2830static int
2831qed_ntuple_arfs_filter_config(struct qed_dev *cdev,
2832 void *cookie,
2833 struct qed_ntuple_filter_params *params)
d51e4af5
CM		 2834{
2835 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
2836 struct qed_spq_comp_cb cb;
2837 int rc = -EINVAL;
2838
2839 cb.function = qed_arfs_sp_response_handler;
2840 cb.cookie = cookie;
2841
da090917
TT		 2842 if (params->b_is_vf) {
2843 if (!qed_iov_is_valid_vfid(p_hwfn, params->vf_id, false,
2844 false)) {
2845 DP_INFO(p_hwfn, "vfid 0x%02x is out of bounds\n",
2846 params->vf_id);
2847 return rc;
2848 }
2849
2850 params->vport_id = params->vf_id + 1;
2851 params->qid = QED_RFS_NTUPLE_QID_RSS;
2852 }
2853
2854 rc = qed_configure_rfs_ntuple_filter(p_hwfn, &cb, params);
d51e4af5
CM		 2855 if (rc)
2856 DP_NOTICE(p_hwfn,
2857 "Failed to issue a-RFS filter configuration\n");
2858 else
2859 DP_VERBOSE(p_hwfn, NETIF_MSG_DRV,
2860 "Successfully issued a-RFS filter configuration\n");
2861
2862 return rc;
2863}
2864
bf5a94bf
RV		 2865static int qed_get_coalesce(struct qed_dev *cdev, u16 *coal, void *handle)
2866{
2867 struct qed_queue_cid *p_cid = handle;
2868 struct qed_hwfn *p_hwfn;
2869 int rc;
2870
2871 p_hwfn = p_cid->p_owner;
2872 rc = qed_get_queue_coalesce(p_hwfn, coal, handle);
2873 if (rc)
8c850253
RV		 2874 DP_VERBOSE(cdev, QED_MSG_DEBUG,
2875 "Unable to read queue coalescing\n");
bf5a94bf
RV		 2876
2877 return rc;
2878}
2879
cee4d264 2880static int qed_fp_cqe_completion(struct qed_dev *dev,
1a635e48 2881 u8 rss_id, struct eth_slow_path_rx_cqe *cqe)
cee4d264
MC		 2882{
2883 return qed_eth_cqe_completion(&dev->hwfns[rss_id % dev->num_hwfns],
2884 cqe);
2885}
2886
809c45a0
SS		 2887static int qed_req_bulletin_update_mac(struct qed_dev *cdev, u8 *mac)
2888{
2889 int i, ret;
2890
2891 if (IS_PF(cdev))
2892 return 0;
2893
2894 for_each_hwfn(cdev, i) {
2895 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2896
2897 ret = qed_vf_pf_bulletin_update_mac(p_hwfn, mac);
2898 if (ret)
2899 return ret;
2900 }
2901
2902 return 0;
2903}
2904
0b55e27d
YM		 2905#ifdef CONFIG_QED_SRIOV
2906extern const struct qed_iov_hv_ops qed_iov_ops_pass;
2907#endif
2908
a1d8d8a5
SRK		 2909#ifdef CONFIG_DCB
2910extern const struct qed_eth_dcbnl_ops qed_dcbnl_ops_pass;
2911#endif
2912
c78c70fa
SRK		 2913extern const struct qed_eth_ptp_ops qed_ptp_ops_pass;
2914
25c089d7
YM		 2915static const struct qed_eth_ops qed_eth_ops_pass = {
2916 .common = &qed_common_ops_pass,
0b55e27d
YM		 2917#ifdef CONFIG_QED_SRIOV
2918 .iov = &qed_iov_ops_pass,
a1d8d8a5
SRK		 2919#endif
2920#ifdef CONFIG_DCB
2921 .dcb = &qed_dcbnl_ops_pass,
0b55e27d 2922#endif
c78c70fa 2923 .ptp = &qed_ptp_ops_pass,
25c089d7 2924 .fill_dev_info = &qed_fill_eth_dev_info,
cc875c2e 2925 .register_ops = &qed_register_eth_ops,
eff16960 2926 .check_mac = &qed_check_mac,
cee4d264
MC		 2927 .vport_start = &qed_start_vport,
2928 .vport_stop = &qed_stop_vport,
2929 .vport_update = &qed_update_vport,
2930 .q_rx_start = &qed_start_rxq,
2931 .q_rx_stop = &qed_stop_rxq,
2932 .q_tx_start = &qed_start_txq,
2933 .q_tx_stop = &qed_stop_txq,
2934 .filter_config = &qed_configure_filter,
2935 .fastpath_stop = &qed_fastpath_stop,
2936 .eth_cqe_completion = &qed_fp_cqe_completion,
9df2ed04 2937 .get_vport_stats = &qed_get_vport_stats,
464f6645 2938 .tunn_config = &qed_tunn_configure,
d51e4af5
CM		 2939 .ntuple_filter_config = &qed_ntuple_arfs_filter_config,
2940 .configure_arfs_searcher = &qed_configure_arfs_searcher,
bf5a94bf 2941 .get_coalesce = &qed_get_coalesce,
809c45a0 2942 .req_bulletin_update_mac = &qed_req_bulletin_update_mac,
25c089d7
YM		 2943};
2944
95114344 2945const struct qed_eth_ops *qed_get_eth_ops(void)
25c089d7 2946{
25c089d7
YM		 2947 return &qed_eth_ops_pass;
2948}
2949EXPORT_SYMBOL(qed_get_eth_ops);
2950
2951void qed_put_eth_ops(void)
2952{
2953 /* TODO - reference count for module? */
2954}
2955EXPORT_SYMBOL(qed_put_eth_ops);
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