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25c089d7 YM |
1 | /* QLogic qed NIC Driver |
2 | * Copyright (c) 2015 QLogic Corporation | |
3 | * | |
4 | * This software is available under the terms of the GNU General Public License | |
5 | * (GPL) Version 2, available from the file COPYING in the main directory of | |
6 | * this source tree. | |
7 | */ | |
8 | ||
9 | #include <linux/types.h> | |
10 | #include <asm/byteorder.h> | |
11 | #include <asm/param.h> | |
12 | #include <linux/delay.h> | |
13 | #include <linux/dma-mapping.h> | |
14 | #include <linux/etherdevice.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/kernel.h> | |
17 | #include <linux/module.h> | |
18 | #include <linux/pci.h> | |
19 | #include <linux/slab.h> | |
20 | #include <linux/stddef.h> | |
21 | #include <linux/string.h> | |
22 | #include <linux/version.h> | |
23 | #include <linux/workqueue.h> | |
24 | #include <linux/bitops.h> | |
25 | #include <linux/bug.h> | |
26 | #include "qed.h" | |
27 | #include <linux/qed/qed_chain.h> | |
28 | #include "qed_cxt.h" | |
29 | #include "qed_dev_api.h" | |
30 | #include <linux/qed/qed_eth_if.h> | |
31 | #include "qed_hsi.h" | |
32 | #include "qed_hw.h" | |
33 | #include "qed_int.h" | |
dacd88d6 | 34 | #include "qed_l2.h" |
86622ee7 | 35 | #include "qed_mcp.h" |
25c089d7 YM |
36 | #include "qed_reg_addr.h" |
37 | #include "qed_sp.h" | |
1408cc1f | 38 | #include "qed_sriov.h" |
25c089d7 | 39 | |
088c8618 | 40 | |
cee4d264 MC |
41 | #define QED_MAX_SGES_NUM 16 |
42 | #define CRC32_POLY 0x1edc6f41 | |
43 | ||
dacd88d6 YM |
44 | int qed_sp_eth_vport_start(struct qed_hwfn *p_hwfn, |
45 | struct qed_sp_vport_start_params *p_params) | |
cee4d264 | 46 | { |
cee4d264 MC |
47 | struct vport_start_ramrod_data *p_ramrod = NULL; |
48 | struct qed_spq_entry *p_ent = NULL; | |
06f56b81 | 49 | struct qed_sp_init_data init_data; |
dacd88d6 | 50 | u8 abs_vport_id = 0; |
cee4d264 MC |
51 | int rc = -EINVAL; |
52 | u16 rx_mode = 0; | |
cee4d264 | 53 | |
088c8618 | 54 | rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id); |
1a635e48 | 55 | if (rc) |
cee4d264 MC |
56 | return rc; |
57 | ||
06f56b81 YM |
58 | memset(&init_data, 0, sizeof(init_data)); |
59 | init_data.cid = qed_spq_get_cid(p_hwfn); | |
088c8618 | 60 | init_data.opaque_fid = p_params->opaque_fid; |
06f56b81 | 61 | init_data.comp_mode = QED_SPQ_MODE_EBLOCK; |
cee4d264 MC |
62 | |
63 | rc = qed_sp_init_request(p_hwfn, &p_ent, | |
cee4d264 | 64 | ETH_RAMROD_VPORT_START, |
06f56b81 | 65 | PROTOCOLID_ETH, &init_data); |
cee4d264 MC |
66 | if (rc) |
67 | return rc; | |
68 | ||
69 | p_ramrod = &p_ent->ramrod.vport_start; | |
70 | p_ramrod->vport_id = abs_vport_id; | |
71 | ||
088c8618 MC |
72 | p_ramrod->mtu = cpu_to_le16(p_params->mtu); |
73 | p_ramrod->inner_vlan_removal_en = p_params->remove_inner_vlan; | |
74 | p_ramrod->drop_ttl0_en = p_params->drop_ttl0; | |
e6bd8923 | 75 | p_ramrod->untagged = p_params->only_untagged; |
cee4d264 MC |
76 | |
77 | SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_UCAST_DROP_ALL, 1); | |
78 | SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_MCAST_DROP_ALL, 1); | |
79 | ||
80 | p_ramrod->rx_mode.state = cpu_to_le16(rx_mode); | |
81 | ||
82 | /* TPA related fields */ | |
1a635e48 | 83 | memset(&p_ramrod->tpa_param, 0, sizeof(struct eth_vport_tpa_param)); |
cee4d264 | 84 | |
088c8618 MC |
85 | p_ramrod->tpa_param.max_buff_num = p_params->max_buffers_per_cqe; |
86 | ||
87 | switch (p_params->tpa_mode) { | |
88 | case QED_TPA_MODE_GRO: | |
89 | p_ramrod->tpa_param.tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM; | |
90 | p_ramrod->tpa_param.tpa_max_size = (u16)-1; | |
91 | p_ramrod->tpa_param.tpa_min_size_to_cont = p_params->mtu / 2; | |
92 | p_ramrod->tpa_param.tpa_min_size_to_start = p_params->mtu / 2; | |
93 | p_ramrod->tpa_param.tpa_ipv4_en_flg = 1; | |
94 | p_ramrod->tpa_param.tpa_ipv6_en_flg = 1; | |
95 | p_ramrod->tpa_param.tpa_pkt_split_flg = 1; | |
96 | p_ramrod->tpa_param.tpa_gro_consistent_flg = 1; | |
97 | break; | |
98 | default: | |
99 | break; | |
100 | } | |
101 | ||
831bfb0e YM |
102 | p_ramrod->tx_switching_en = p_params->tx_switching; |
103 | ||
11a85d75 YM |
104 | p_ramrod->ctl_frame_mac_check_en = !!p_params->check_mac; |
105 | p_ramrod->ctl_frame_ethtype_check_en = !!p_params->check_ethtype; | |
106 | ||
cee4d264 MC |
107 | /* Software Function ID in hwfn (PFs are 0 - 15, VFs are 16 - 135) */ |
108 | p_ramrod->sw_fid = qed_concrete_to_sw_fid(p_hwfn->cdev, | |
088c8618 | 109 | p_params->concrete_fid); |
cee4d264 MC |
110 | |
111 | return qed_spq_post(p_hwfn, p_ent, NULL); | |
112 | } | |
113 | ||
ba56947a BX |
114 | static int qed_sp_vport_start(struct qed_hwfn *p_hwfn, |
115 | struct qed_sp_vport_start_params *p_params) | |
dacd88d6 YM |
116 | { |
117 | if (IS_VF(p_hwfn->cdev)) { | |
118 | return qed_vf_pf_vport_start(p_hwfn, p_params->vport_id, | |
119 | p_params->mtu, | |
120 | p_params->remove_inner_vlan, | |
121 | p_params->tpa_mode, | |
08feecd7 YM |
122 | p_params->max_buffers_per_cqe, |
123 | p_params->only_untagged); | |
dacd88d6 YM |
124 | } |
125 | ||
126 | return qed_sp_eth_vport_start(p_hwfn, p_params); | |
127 | } | |
128 | ||
cee4d264 MC |
129 | static int |
130 | qed_sp_vport_update_rss(struct qed_hwfn *p_hwfn, | |
131 | struct vport_update_ramrod_data *p_ramrod, | |
132 | struct qed_rss_params *p_params) | |
133 | { | |
134 | struct eth_vport_rss_config *rss = &p_ramrod->rss_config; | |
135 | u16 abs_l2_queue = 0, capabilities = 0; | |
136 | int rc = 0, i; | |
137 | ||
138 | if (!p_params) { | |
139 | p_ramrod->common.update_rss_flg = 0; | |
140 | return rc; | |
141 | } | |
142 | ||
143 | BUILD_BUG_ON(QED_RSS_IND_TABLE_SIZE != | |
144 | ETH_RSS_IND_TABLE_ENTRIES_NUM); | |
145 | ||
146 | rc = qed_fw_rss_eng(p_hwfn, p_params->rss_eng_id, &rss->rss_id); | |
147 | if (rc) | |
148 | return rc; | |
149 | ||
150 | p_ramrod->common.update_rss_flg = p_params->update_rss_config; | |
151 | rss->update_rss_capabilities = p_params->update_rss_capabilities; | |
152 | rss->update_rss_ind_table = p_params->update_rss_ind_table; | |
153 | rss->update_rss_key = p_params->update_rss_key; | |
154 | ||
155 | rss->rss_mode = p_params->rss_enable ? | |
156 | ETH_VPORT_RSS_MODE_REGULAR : | |
157 | ETH_VPORT_RSS_MODE_DISABLED; | |
158 | ||
159 | SET_FIELD(capabilities, | |
160 | ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY, | |
161 | !!(p_params->rss_caps & QED_RSS_IPV4)); | |
162 | SET_FIELD(capabilities, | |
163 | ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY, | |
164 | !!(p_params->rss_caps & QED_RSS_IPV6)); | |
165 | SET_FIELD(capabilities, | |
166 | ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY, | |
167 | !!(p_params->rss_caps & QED_RSS_IPV4_TCP)); | |
168 | SET_FIELD(capabilities, | |
169 | ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY, | |
170 | !!(p_params->rss_caps & QED_RSS_IPV6_TCP)); | |
171 | SET_FIELD(capabilities, | |
172 | ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY, | |
173 | !!(p_params->rss_caps & QED_RSS_IPV4_UDP)); | |
174 | SET_FIELD(capabilities, | |
175 | ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY, | |
176 | !!(p_params->rss_caps & QED_RSS_IPV6_UDP)); | |
177 | rss->tbl_size = p_params->rss_table_size_log; | |
178 | ||
179 | rss->capabilities = cpu_to_le16(capabilities); | |
180 | ||
181 | DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP, | |
182 | "update rss flag %d, rss_mode = %d, update_caps = %d, capabilities = %d, update_ind = %d, update_rss_key = %d\n", | |
183 | p_ramrod->common.update_rss_flg, | |
184 | rss->rss_mode, rss->update_rss_capabilities, | |
185 | capabilities, rss->update_rss_ind_table, | |
186 | rss->update_rss_key); | |
187 | ||
188 | for (i = 0; i < QED_RSS_IND_TABLE_SIZE; i++) { | |
189 | rc = qed_fw_l2_queue(p_hwfn, | |
190 | (u8)p_params->rss_ind_table[i], | |
191 | &abs_l2_queue); | |
192 | if (rc) | |
193 | return rc; | |
194 | ||
195 | rss->indirection_table[i] = cpu_to_le16(abs_l2_queue); | |
196 | DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP, "i= %d, queue = %d\n", | |
197 | i, rss->indirection_table[i]); | |
198 | } | |
199 | ||
200 | for (i = 0; i < 10; i++) | |
201 | rss->rss_key[i] = cpu_to_le32(p_params->rss_key[i]); | |
202 | ||
203 | return rc; | |
204 | } | |
205 | ||
206 | static void | |
207 | qed_sp_update_accept_mode(struct qed_hwfn *p_hwfn, | |
208 | struct vport_update_ramrod_data *p_ramrod, | |
209 | struct qed_filter_accept_flags accept_flags) | |
210 | { | |
211 | p_ramrod->common.update_rx_mode_flg = | |
212 | accept_flags.update_rx_mode_config; | |
213 | ||
214 | p_ramrod->common.update_tx_mode_flg = | |
215 | accept_flags.update_tx_mode_config; | |
216 | ||
217 | /* Set Rx mode accept flags */ | |
218 | if (p_ramrod->common.update_rx_mode_flg) { | |
219 | u8 accept_filter = accept_flags.rx_accept_filter; | |
220 | u16 state = 0; | |
221 | ||
222 | SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_DROP_ALL, | |
223 | !(!!(accept_filter & QED_ACCEPT_UCAST_MATCHED) || | |
224 | !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED))); | |
225 | ||
226 | SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED, | |
227 | !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED)); | |
228 | ||
229 | SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_DROP_ALL, | |
230 | !(!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) || | |
231 | !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED))); | |
232 | ||
233 | SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL, | |
234 | (!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) && | |
235 | !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED))); | |
236 | ||
237 | SET_FIELD(state, ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL, | |
238 | !!(accept_filter & QED_ACCEPT_BCAST)); | |
239 | ||
240 | p_ramrod->rx_mode.state = cpu_to_le16(state); | |
241 | DP_VERBOSE(p_hwfn, QED_MSG_SP, | |
242 | "p_ramrod->rx_mode.state = 0x%x\n", state); | |
243 | } | |
244 | ||
245 | /* Set Tx mode accept flags */ | |
246 | if (p_ramrod->common.update_tx_mode_flg) { | |
247 | u8 accept_filter = accept_flags.tx_accept_filter; | |
248 | u16 state = 0; | |
249 | ||
250 | SET_FIELD(state, ETH_VPORT_TX_MODE_UCAST_DROP_ALL, | |
251 | !!(accept_filter & QED_ACCEPT_NONE)); | |
252 | ||
cee4d264 MC |
253 | SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_DROP_ALL, |
254 | !!(accept_filter & QED_ACCEPT_NONE)); | |
255 | ||
256 | SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL, | |
257 | (!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) && | |
258 | !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED))); | |
259 | ||
260 | SET_FIELD(state, ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL, | |
261 | !!(accept_filter & QED_ACCEPT_BCAST)); | |
262 | ||
263 | p_ramrod->tx_mode.state = cpu_to_le16(state); | |
264 | DP_VERBOSE(p_hwfn, QED_MSG_SP, | |
265 | "p_ramrod->tx_mode.state = 0x%x\n", state); | |
266 | } | |
267 | } | |
268 | ||
17b235c1 YM |
269 | static void |
270 | qed_sp_vport_update_sge_tpa(struct qed_hwfn *p_hwfn, | |
271 | struct vport_update_ramrod_data *p_ramrod, | |
272 | struct qed_sge_tpa_params *p_params) | |
273 | { | |
274 | struct eth_vport_tpa_param *p_tpa; | |
275 | ||
276 | if (!p_params) { | |
277 | p_ramrod->common.update_tpa_param_flg = 0; | |
278 | p_ramrod->common.update_tpa_en_flg = 0; | |
279 | p_ramrod->common.update_tpa_param_flg = 0; | |
280 | return; | |
281 | } | |
282 | ||
283 | p_ramrod->common.update_tpa_en_flg = p_params->update_tpa_en_flg; | |
284 | p_tpa = &p_ramrod->tpa_param; | |
285 | p_tpa->tpa_ipv4_en_flg = p_params->tpa_ipv4_en_flg; | |
286 | p_tpa->tpa_ipv6_en_flg = p_params->tpa_ipv6_en_flg; | |
287 | p_tpa->tpa_ipv4_tunn_en_flg = p_params->tpa_ipv4_tunn_en_flg; | |
288 | p_tpa->tpa_ipv6_tunn_en_flg = p_params->tpa_ipv6_tunn_en_flg; | |
289 | ||
290 | p_ramrod->common.update_tpa_param_flg = p_params->update_tpa_param_flg; | |
291 | p_tpa->max_buff_num = p_params->max_buffers_per_cqe; | |
292 | p_tpa->tpa_pkt_split_flg = p_params->tpa_pkt_split_flg; | |
293 | p_tpa->tpa_hdr_data_split_flg = p_params->tpa_hdr_data_split_flg; | |
294 | p_tpa->tpa_gro_consistent_flg = p_params->tpa_gro_consistent_flg; | |
295 | p_tpa->tpa_max_aggs_num = p_params->tpa_max_aggs_num; | |
296 | p_tpa->tpa_max_size = p_params->tpa_max_size; | |
297 | p_tpa->tpa_min_size_to_start = p_params->tpa_min_size_to_start; | |
298 | p_tpa->tpa_min_size_to_cont = p_params->tpa_min_size_to_cont; | |
299 | } | |
300 | ||
cee4d264 MC |
301 | static void |
302 | qed_sp_update_mcast_bin(struct qed_hwfn *p_hwfn, | |
303 | struct vport_update_ramrod_data *p_ramrod, | |
304 | struct qed_sp_vport_update_params *p_params) | |
305 | { | |
306 | int i; | |
307 | ||
308 | memset(&p_ramrod->approx_mcast.bins, 0, | |
309 | sizeof(p_ramrod->approx_mcast.bins)); | |
310 | ||
83aeb933 YM |
311 | if (!p_params->update_approx_mcast_flg) |
312 | return; | |
cee4d264 | 313 | |
83aeb933 YM |
314 | p_ramrod->common.update_approx_mcast_flg = 1; |
315 | for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) { | |
316 | u32 *p_bins = (u32 *)p_params->bins; | |
317 | ||
318 | p_ramrod->approx_mcast.bins[i] = cpu_to_le32(p_bins[i]); | |
cee4d264 MC |
319 | } |
320 | } | |
321 | ||
dacd88d6 YM |
322 | int qed_sp_vport_update(struct qed_hwfn *p_hwfn, |
323 | struct qed_sp_vport_update_params *p_params, | |
324 | enum spq_mode comp_mode, | |
325 | struct qed_spq_comp_cb *p_comp_data) | |
cee4d264 MC |
326 | { |
327 | struct qed_rss_params *p_rss_params = p_params->rss_params; | |
328 | struct vport_update_ramrod_data_cmn *p_cmn; | |
06f56b81 | 329 | struct qed_sp_init_data init_data; |
cee4d264 MC |
330 | struct vport_update_ramrod_data *p_ramrod = NULL; |
331 | struct qed_spq_entry *p_ent = NULL; | |
17b235c1 | 332 | u8 abs_vport_id = 0, val; |
cee4d264 MC |
333 | int rc = -EINVAL; |
334 | ||
dacd88d6 YM |
335 | if (IS_VF(p_hwfn->cdev)) { |
336 | rc = qed_vf_pf_vport_update(p_hwfn, p_params); | |
337 | return rc; | |
338 | } | |
339 | ||
cee4d264 | 340 | rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id); |
1a635e48 | 341 | if (rc) |
cee4d264 MC |
342 | return rc; |
343 | ||
06f56b81 YM |
344 | memset(&init_data, 0, sizeof(init_data)); |
345 | init_data.cid = qed_spq_get_cid(p_hwfn); | |
346 | init_data.opaque_fid = p_params->opaque_fid; | |
347 | init_data.comp_mode = comp_mode; | |
348 | init_data.p_comp_data = p_comp_data; | |
cee4d264 MC |
349 | |
350 | rc = qed_sp_init_request(p_hwfn, &p_ent, | |
cee4d264 | 351 | ETH_RAMROD_VPORT_UPDATE, |
06f56b81 | 352 | PROTOCOLID_ETH, &init_data); |
cee4d264 MC |
353 | if (rc) |
354 | return rc; | |
355 | ||
356 | /* Copy input params to ramrod according to FW struct */ | |
357 | p_ramrod = &p_ent->ramrod.vport_update; | |
358 | p_cmn = &p_ramrod->common; | |
359 | ||
360 | p_cmn->vport_id = abs_vport_id; | |
361 | p_cmn->rx_active_flg = p_params->vport_active_rx_flg; | |
362 | p_cmn->update_rx_active_flg = p_params->update_vport_active_rx_flg; | |
363 | p_cmn->tx_active_flg = p_params->vport_active_tx_flg; | |
364 | p_cmn->update_tx_active_flg = p_params->update_vport_active_tx_flg; | |
3f9b4a69 | 365 | p_cmn->accept_any_vlan = p_params->accept_any_vlan; |
83aeb933 YM |
366 | val = p_params->update_accept_any_vlan_flg; |
367 | p_cmn->update_accept_any_vlan_flg = val; | |
17b235c1 YM |
368 | |
369 | p_cmn->inner_vlan_removal_en = p_params->inner_vlan_removal_flg; | |
370 | val = p_params->update_inner_vlan_removal_flg; | |
371 | p_cmn->update_inner_vlan_removal_en_flg = val; | |
08feecd7 YM |
372 | |
373 | p_cmn->default_vlan_en = p_params->default_vlan_enable_flg; | |
374 | val = p_params->update_default_vlan_enable_flg; | |
375 | p_cmn->update_default_vlan_en_flg = val; | |
376 | ||
377 | p_cmn->default_vlan = cpu_to_le16(p_params->default_vlan); | |
378 | p_cmn->update_default_vlan_flg = p_params->update_default_vlan_flg; | |
379 | ||
380 | p_cmn->silent_vlan_removal_en = p_params->silent_vlan_removal_flg; | |
381 | ||
17b235c1 YM |
382 | p_ramrod->common.tx_switching_en = p_params->tx_switching_flg; |
383 | p_cmn->update_tx_switching_en_flg = p_params->update_tx_switching_flg; | |
384 | ||
6ddc7608 YM |
385 | p_cmn->anti_spoofing_en = p_params->anti_spoofing_en; |
386 | val = p_params->update_anti_spoofing_en_flg; | |
387 | p_ramrod->common.update_anti_spoofing_en_flg = val; | |
388 | ||
cee4d264 MC |
389 | rc = qed_sp_vport_update_rss(p_hwfn, p_ramrod, p_rss_params); |
390 | if (rc) { | |
391 | /* Return spq entry which is taken in qed_sp_init_request()*/ | |
392 | qed_spq_return_entry(p_hwfn, p_ent); | |
393 | return rc; | |
394 | } | |
395 | ||
396 | /* Update mcast bins for VFs, PF doesn't use this functionality */ | |
397 | qed_sp_update_mcast_bin(p_hwfn, p_ramrod, p_params); | |
398 | ||
399 | qed_sp_update_accept_mode(p_hwfn, p_ramrod, p_params->accept_flags); | |
17b235c1 | 400 | qed_sp_vport_update_sge_tpa(p_hwfn, p_ramrod, p_params->sge_tpa_params); |
cee4d264 MC |
401 | return qed_spq_post(p_hwfn, p_ent, NULL); |
402 | } | |
403 | ||
dacd88d6 | 404 | int qed_sp_vport_stop(struct qed_hwfn *p_hwfn, u16 opaque_fid, u8 vport_id) |
cee4d264 | 405 | { |
cee4d264 | 406 | struct vport_stop_ramrod_data *p_ramrod; |
06f56b81 | 407 | struct qed_sp_init_data init_data; |
cee4d264 MC |
408 | struct qed_spq_entry *p_ent; |
409 | u8 abs_vport_id = 0; | |
410 | int rc; | |
411 | ||
dacd88d6 YM |
412 | if (IS_VF(p_hwfn->cdev)) |
413 | return qed_vf_pf_vport_stop(p_hwfn); | |
414 | ||
cee4d264 | 415 | rc = qed_fw_vport(p_hwfn, vport_id, &abs_vport_id); |
1a635e48 | 416 | if (rc) |
cee4d264 MC |
417 | return rc; |
418 | ||
06f56b81 YM |
419 | memset(&init_data, 0, sizeof(init_data)); |
420 | init_data.cid = qed_spq_get_cid(p_hwfn); | |
421 | init_data.opaque_fid = opaque_fid; | |
422 | init_data.comp_mode = QED_SPQ_MODE_EBLOCK; | |
cee4d264 MC |
423 | |
424 | rc = qed_sp_init_request(p_hwfn, &p_ent, | |
cee4d264 | 425 | ETH_RAMROD_VPORT_STOP, |
06f56b81 | 426 | PROTOCOLID_ETH, &init_data); |
cee4d264 MC |
427 | if (rc) |
428 | return rc; | |
429 | ||
430 | p_ramrod = &p_ent->ramrod.vport_stop; | |
431 | p_ramrod->vport_id = abs_vport_id; | |
432 | ||
433 | return qed_spq_post(p_hwfn, p_ent, NULL); | |
434 | } | |
435 | ||
dacd88d6 YM |
436 | static int |
437 | qed_vf_pf_accept_flags(struct qed_hwfn *p_hwfn, | |
438 | struct qed_filter_accept_flags *p_accept_flags) | |
439 | { | |
440 | struct qed_sp_vport_update_params s_params; | |
441 | ||
442 | memset(&s_params, 0, sizeof(s_params)); | |
443 | memcpy(&s_params.accept_flags, p_accept_flags, | |
444 | sizeof(struct qed_filter_accept_flags)); | |
445 | ||
446 | return qed_vf_pf_vport_update(p_hwfn, &s_params); | |
447 | } | |
448 | ||
cee4d264 MC |
449 | static int qed_filter_accept_cmd(struct qed_dev *cdev, |
450 | u8 vport, | |
451 | struct qed_filter_accept_flags accept_flags, | |
3f9b4a69 YM |
452 | u8 update_accept_any_vlan, |
453 | u8 accept_any_vlan, | |
dacd88d6 YM |
454 | enum spq_mode comp_mode, |
455 | struct qed_spq_comp_cb *p_comp_data) | |
cee4d264 MC |
456 | { |
457 | struct qed_sp_vport_update_params vport_update_params; | |
458 | int i, rc; | |
459 | ||
460 | /* Prepare and send the vport rx_mode change */ | |
461 | memset(&vport_update_params, 0, sizeof(vport_update_params)); | |
462 | vport_update_params.vport_id = vport; | |
463 | vport_update_params.accept_flags = accept_flags; | |
3f9b4a69 YM |
464 | vport_update_params.update_accept_any_vlan_flg = update_accept_any_vlan; |
465 | vport_update_params.accept_any_vlan = accept_any_vlan; | |
cee4d264 MC |
466 | |
467 | for_each_hwfn(cdev, i) { | |
468 | struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; | |
469 | ||
470 | vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid; | |
471 | ||
dacd88d6 YM |
472 | if (IS_VF(cdev)) { |
473 | rc = qed_vf_pf_accept_flags(p_hwfn, &accept_flags); | |
474 | if (rc) | |
475 | return rc; | |
476 | continue; | |
477 | } | |
478 | ||
cee4d264 MC |
479 | rc = qed_sp_vport_update(p_hwfn, &vport_update_params, |
480 | comp_mode, p_comp_data); | |
1a635e48 | 481 | if (rc) { |
cee4d264 MC |
482 | DP_ERR(cdev, "Update rx_mode failed %d\n", rc); |
483 | return rc; | |
484 | } | |
485 | ||
486 | DP_VERBOSE(p_hwfn, QED_MSG_SP, | |
487 | "Accept filter configured, flags = [Rx]%x [Tx]%x\n", | |
488 | accept_flags.rx_accept_filter, | |
489 | accept_flags.tx_accept_filter); | |
3f9b4a69 YM |
490 | if (update_accept_any_vlan) |
491 | DP_VERBOSE(p_hwfn, QED_MSG_SP, | |
492 | "accept_any_vlan=%d configured\n", | |
493 | accept_any_vlan); | |
cee4d264 MC |
494 | } |
495 | ||
496 | return 0; | |
497 | } | |
498 | ||
499 | static int qed_sp_release_queue_cid( | |
500 | struct qed_hwfn *p_hwfn, | |
501 | struct qed_hw_cid_data *p_cid_data) | |
502 | { | |
503 | if (!p_cid_data->b_cid_allocated) | |
504 | return 0; | |
505 | ||
506 | qed_cxt_release_cid(p_hwfn, p_cid_data->cid); | |
507 | ||
508 | p_cid_data->b_cid_allocated = false; | |
509 | ||
510 | return 0; | |
511 | } | |
512 | ||
dacd88d6 YM |
513 | int qed_sp_eth_rxq_start_ramrod(struct qed_hwfn *p_hwfn, |
514 | u16 opaque_fid, | |
515 | u32 cid, | |
1a635e48 | 516 | struct qed_queue_start_common_params *p_params, |
dacd88d6 YM |
517 | u8 stats_id, |
518 | u16 bd_max_bytes, | |
519 | dma_addr_t bd_chain_phys_addr, | |
a044df83 YM |
520 | dma_addr_t cqe_pbl_addr, |
521 | u16 cqe_pbl_size, bool b_use_zone_a_prod) | |
cee4d264 MC |
522 | { |
523 | struct rx_queue_start_ramrod_data *p_ramrod = NULL; | |
cee4d264 | 524 | struct qed_spq_entry *p_ent = NULL; |
06f56b81 | 525 | struct qed_sp_init_data init_data; |
cee4d264 MC |
526 | struct qed_hw_cid_data *p_rx_cid; |
527 | u16 abs_rx_q_id = 0; | |
528 | u8 abs_vport_id = 0; | |
529 | int rc = -EINVAL; | |
530 | ||
531 | /* Store information for the stop */ | |
1a635e48 YM |
532 | p_rx_cid = &p_hwfn->p_rx_cids[p_params->queue_id]; |
533 | p_rx_cid->cid = cid; | |
534 | p_rx_cid->opaque_fid = opaque_fid; | |
535 | p_rx_cid->vport_id = p_params->vport_id; | |
cee4d264 | 536 | |
1a635e48 YM |
537 | rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id); |
538 | if (rc) | |
cee4d264 MC |
539 | return rc; |
540 | ||
1a635e48 YM |
541 | rc = qed_fw_l2_queue(p_hwfn, p_params->queue_id, &abs_rx_q_id); |
542 | if (rc) | |
cee4d264 MC |
543 | return rc; |
544 | ||
545 | DP_VERBOSE(p_hwfn, QED_MSG_SP, | |
546 | "opaque_fid=0x%x, cid=0x%x, rx_qid=0x%x, vport_id=0x%x, sb_id=0x%x\n", | |
1a635e48 YM |
547 | opaque_fid, |
548 | cid, p_params->queue_id, p_params->vport_id, p_params->sb); | |
cee4d264 | 549 | |
06f56b81 YM |
550 | /* Get SPQ entry */ |
551 | memset(&init_data, 0, sizeof(init_data)); | |
552 | init_data.cid = cid; | |
553 | init_data.opaque_fid = opaque_fid; | |
554 | init_data.comp_mode = QED_SPQ_MODE_EBLOCK; | |
cee4d264 MC |
555 | |
556 | rc = qed_sp_init_request(p_hwfn, &p_ent, | |
cee4d264 | 557 | ETH_RAMROD_RX_QUEUE_START, |
06f56b81 | 558 | PROTOCOLID_ETH, &init_data); |
cee4d264 MC |
559 | if (rc) |
560 | return rc; | |
561 | ||
562 | p_ramrod = &p_ent->ramrod.rx_queue_start; | |
563 | ||
1a635e48 YM |
564 | p_ramrod->sb_id = cpu_to_le16(p_params->sb); |
565 | p_ramrod->sb_index = p_params->sb_idx; | |
566 | p_ramrod->vport_id = abs_vport_id; | |
567 | p_ramrod->stats_counter_id = stats_id; | |
568 | p_ramrod->rx_queue_id = cpu_to_le16(abs_rx_q_id); | |
569 | p_ramrod->complete_cqe_flg = 0; | |
570 | p_ramrod->complete_event_flg = 1; | |
cee4d264 | 571 | |
1a635e48 | 572 | p_ramrod->bd_max_bytes = cpu_to_le16(bd_max_bytes); |
94494598 | 573 | DMA_REGPAIR_LE(p_ramrod->bd_base, bd_chain_phys_addr); |
cee4d264 | 574 | |
1a635e48 | 575 | p_ramrod->num_of_pbl_pages = cpu_to_le16(cqe_pbl_size); |
94494598 | 576 | DMA_REGPAIR_LE(p_ramrod->cqe_pbl_addr, cqe_pbl_addr); |
cee4d264 | 577 | |
a044df83 YM |
578 | if (p_params->vf_qid || b_use_zone_a_prod) { |
579 | p_ramrod->vf_rx_prod_index = p_params->vf_qid; | |
351a4ded | 580 | DP_VERBOSE(p_hwfn, QED_MSG_SP, |
a044df83 YM |
581 | "Queue%s is meant for VF rxq[%02x]\n", |
582 | b_use_zone_a_prod ? " [legacy]" : "", | |
1a635e48 | 583 | p_params->vf_qid); |
a044df83 YM |
584 | p_ramrod->vf_rx_prod_use_zone_a = b_use_zone_a_prod; |
585 | } | |
cee4d264 | 586 | |
351a4ded | 587 | return qed_spq_post(p_hwfn, p_ent, NULL); |
cee4d264 MC |
588 | } |
589 | ||
590 | static int | |
591 | qed_sp_eth_rx_queue_start(struct qed_hwfn *p_hwfn, | |
592 | u16 opaque_fid, | |
1a635e48 | 593 | struct qed_queue_start_common_params *p_params, |
cee4d264 MC |
594 | u16 bd_max_bytes, |
595 | dma_addr_t bd_chain_phys_addr, | |
596 | dma_addr_t cqe_pbl_addr, | |
dacd88d6 | 597 | u16 cqe_pbl_size, void __iomem **pp_prod) |
cee4d264 MC |
598 | { |
599 | struct qed_hw_cid_data *p_rx_cid; | |
b21290b7 | 600 | u32 init_prod_val = 0; |
cee4d264 MC |
601 | u16 abs_l2_queue = 0; |
602 | u8 abs_stats_id = 0; | |
603 | int rc; | |
604 | ||
dacd88d6 YM |
605 | if (IS_VF(p_hwfn->cdev)) { |
606 | return qed_vf_pf_rxq_start(p_hwfn, | |
1a635e48 YM |
607 | p_params->queue_id, |
608 | p_params->sb, | |
609 | (u8)p_params->sb_idx, | |
dacd88d6 YM |
610 | bd_max_bytes, |
611 | bd_chain_phys_addr, | |
612 | cqe_pbl_addr, cqe_pbl_size, pp_prod); | |
613 | } | |
614 | ||
1a635e48 YM |
615 | rc = qed_fw_l2_queue(p_hwfn, p_params->queue_id, &abs_l2_queue); |
616 | if (rc) | |
cee4d264 MC |
617 | return rc; |
618 | ||
1a635e48 YM |
619 | rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_stats_id); |
620 | if (rc) | |
cee4d264 MC |
621 | return rc; |
622 | ||
623 | *pp_prod = (u8 __iomem *)p_hwfn->regview + | |
624 | GTT_BAR0_MAP_REG_MSDM_RAM + | |
351a4ded | 625 | MSTORM_ETH_PF_PRODS_OFFSET(abs_l2_queue); |
cee4d264 MC |
626 | |
627 | /* Init the rcq, rx bd and rx sge (if valid) producers to 0 */ | |
b21290b7 | 628 | __internal_ram_wr(p_hwfn, *pp_prod, sizeof(u32), |
cee4d264 MC |
629 | (u32 *)(&init_prod_val)); |
630 | ||
631 | /* Allocate a CID for the queue */ | |
1a635e48 YM |
632 | p_rx_cid = &p_hwfn->p_rx_cids[p_params->queue_id]; |
633 | rc = qed_cxt_acquire_cid(p_hwfn, PROTOCOLID_ETH, &p_rx_cid->cid); | |
cee4d264 MC |
634 | if (rc) { |
635 | DP_NOTICE(p_hwfn, "Failed to acquire cid\n"); | |
636 | return rc; | |
637 | } | |
638 | p_rx_cid->b_cid_allocated = true; | |
639 | ||
640 | rc = qed_sp_eth_rxq_start_ramrod(p_hwfn, | |
641 | opaque_fid, | |
642 | p_rx_cid->cid, | |
1a635e48 | 643 | p_params, |
cee4d264 MC |
644 | abs_stats_id, |
645 | bd_max_bytes, | |
646 | bd_chain_phys_addr, | |
a044df83 | 647 | cqe_pbl_addr, cqe_pbl_size, false); |
cee4d264 | 648 | |
1a635e48 | 649 | if (rc) |
cee4d264 MC |
650 | qed_sp_release_queue_cid(p_hwfn, p_rx_cid); |
651 | ||
652 | return rc; | |
653 | } | |
654 | ||
17b235c1 YM |
655 | int qed_sp_eth_rx_queues_update(struct qed_hwfn *p_hwfn, |
656 | u16 rx_queue_id, | |
657 | u8 num_rxqs, | |
658 | u8 complete_cqe_flg, | |
659 | u8 complete_event_flg, | |
660 | enum spq_mode comp_mode, | |
661 | struct qed_spq_comp_cb *p_comp_data) | |
662 | { | |
663 | struct rx_queue_update_ramrod_data *p_ramrod = NULL; | |
664 | struct qed_spq_entry *p_ent = NULL; | |
665 | struct qed_sp_init_data init_data; | |
666 | struct qed_hw_cid_data *p_rx_cid; | |
667 | u16 qid, abs_rx_q_id = 0; | |
668 | int rc = -EINVAL; | |
669 | u8 i; | |
670 | ||
671 | memset(&init_data, 0, sizeof(init_data)); | |
672 | init_data.comp_mode = comp_mode; | |
673 | init_data.p_comp_data = p_comp_data; | |
674 | ||
675 | for (i = 0; i < num_rxqs; i++) { | |
676 | qid = rx_queue_id + i; | |
677 | p_rx_cid = &p_hwfn->p_rx_cids[qid]; | |
678 | ||
679 | /* Get SPQ entry */ | |
680 | init_data.cid = p_rx_cid->cid; | |
681 | init_data.opaque_fid = p_rx_cid->opaque_fid; | |
682 | ||
683 | rc = qed_sp_init_request(p_hwfn, &p_ent, | |
684 | ETH_RAMROD_RX_QUEUE_UPDATE, | |
685 | PROTOCOLID_ETH, &init_data); | |
686 | if (rc) | |
687 | return rc; | |
688 | ||
689 | p_ramrod = &p_ent->ramrod.rx_queue_update; | |
690 | ||
691 | qed_fw_vport(p_hwfn, p_rx_cid->vport_id, &p_ramrod->vport_id); | |
692 | qed_fw_l2_queue(p_hwfn, qid, &abs_rx_q_id); | |
693 | p_ramrod->rx_queue_id = cpu_to_le16(abs_rx_q_id); | |
694 | p_ramrod->complete_cqe_flg = complete_cqe_flg; | |
695 | p_ramrod->complete_event_flg = complete_event_flg; | |
696 | ||
697 | rc = qed_spq_post(p_hwfn, p_ent, NULL); | |
698 | if (rc) | |
699 | return rc; | |
700 | } | |
701 | ||
702 | return rc; | |
703 | } | |
704 | ||
dacd88d6 YM |
705 | int qed_sp_eth_rx_queue_stop(struct qed_hwfn *p_hwfn, |
706 | u16 rx_queue_id, | |
707 | bool eq_completion_only, bool cqe_completion) | |
cee4d264 MC |
708 | { |
709 | struct qed_hw_cid_data *p_rx_cid = &p_hwfn->p_rx_cids[rx_queue_id]; | |
710 | struct rx_queue_stop_ramrod_data *p_ramrod = NULL; | |
cee4d264 | 711 | struct qed_spq_entry *p_ent = NULL; |
06f56b81 | 712 | struct qed_sp_init_data init_data; |
cee4d264 MC |
713 | u16 abs_rx_q_id = 0; |
714 | int rc = -EINVAL; | |
715 | ||
dacd88d6 YM |
716 | if (IS_VF(p_hwfn->cdev)) |
717 | return qed_vf_pf_rxq_stop(p_hwfn, rx_queue_id, cqe_completion); | |
718 | ||
06f56b81 YM |
719 | /* Get SPQ entry */ |
720 | memset(&init_data, 0, sizeof(init_data)); | |
721 | init_data.cid = p_rx_cid->cid; | |
722 | init_data.opaque_fid = p_rx_cid->opaque_fid; | |
723 | init_data.comp_mode = QED_SPQ_MODE_EBLOCK; | |
cee4d264 MC |
724 | |
725 | rc = qed_sp_init_request(p_hwfn, &p_ent, | |
cee4d264 | 726 | ETH_RAMROD_RX_QUEUE_STOP, |
06f56b81 | 727 | PROTOCOLID_ETH, &init_data); |
cee4d264 MC |
728 | if (rc) |
729 | return rc; | |
730 | ||
731 | p_ramrod = &p_ent->ramrod.rx_queue_stop; | |
732 | ||
733 | qed_fw_vport(p_hwfn, p_rx_cid->vport_id, &p_ramrod->vport_id); | |
734 | qed_fw_l2_queue(p_hwfn, rx_queue_id, &abs_rx_q_id); | |
735 | p_ramrod->rx_queue_id = cpu_to_le16(abs_rx_q_id); | |
736 | ||
737 | /* Cleaning the queue requires the completion to arrive there. | |
738 | * In addition, VFs require the answer to come as eqe to PF. | |
739 | */ | |
740 | p_ramrod->complete_cqe_flg = | |
741 | (!!(p_rx_cid->opaque_fid == p_hwfn->hw_info.opaque_fid) && | |
742 | !eq_completion_only) || cqe_completion; | |
743 | p_ramrod->complete_event_flg = | |
744 | !(p_rx_cid->opaque_fid == p_hwfn->hw_info.opaque_fid) || | |
745 | eq_completion_only; | |
746 | ||
747 | rc = qed_spq_post(p_hwfn, p_ent, NULL); | |
748 | if (rc) | |
749 | return rc; | |
750 | ||
751 | return qed_sp_release_queue_cid(p_hwfn, p_rx_cid); | |
752 | } | |
753 | ||
dacd88d6 YM |
754 | int qed_sp_eth_txq_start_ramrod(struct qed_hwfn *p_hwfn, |
755 | u16 opaque_fid, | |
756 | u32 cid, | |
757 | struct qed_queue_start_common_params *p_params, | |
758 | u8 stats_id, | |
759 | dma_addr_t pbl_addr, | |
760 | u16 pbl_size, | |
761 | union qed_qm_pq_params *p_pq_params) | |
cee4d264 MC |
762 | { |
763 | struct tx_queue_start_ramrod_data *p_ramrod = NULL; | |
cee4d264 | 764 | struct qed_spq_entry *p_ent = NULL; |
06f56b81 | 765 | struct qed_sp_init_data init_data; |
cee4d264 | 766 | struct qed_hw_cid_data *p_tx_cid; |
351a4ded | 767 | u16 pq_id, abs_tx_q_id = 0; |
cee4d264 | 768 | int rc = -EINVAL; |
351a4ded | 769 | u8 abs_vport_id; |
cee4d264 MC |
770 | |
771 | /* Store information for the stop */ | |
772 | p_tx_cid = &p_hwfn->p_tx_cids[p_params->queue_id]; | |
773 | p_tx_cid->cid = cid; | |
774 | p_tx_cid->opaque_fid = opaque_fid; | |
775 | ||
776 | rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id); | |
777 | if (rc) | |
778 | return rc; | |
779 | ||
351a4ded YM |
780 | rc = qed_fw_l2_queue(p_hwfn, p_params->queue_id, &abs_tx_q_id); |
781 | if (rc) | |
782 | return rc; | |
783 | ||
06f56b81 YM |
784 | /* Get SPQ entry */ |
785 | memset(&init_data, 0, sizeof(init_data)); | |
786 | init_data.cid = cid; | |
787 | init_data.opaque_fid = opaque_fid; | |
788 | init_data.comp_mode = QED_SPQ_MODE_EBLOCK; | |
cee4d264 | 789 | |
06f56b81 | 790 | rc = qed_sp_init_request(p_hwfn, &p_ent, |
cee4d264 | 791 | ETH_RAMROD_TX_QUEUE_START, |
06f56b81 | 792 | PROTOCOLID_ETH, &init_data); |
cee4d264 MC |
793 | if (rc) |
794 | return rc; | |
795 | ||
1a635e48 YM |
796 | p_ramrod = &p_ent->ramrod.tx_queue_start; |
797 | p_ramrod->vport_id = abs_vport_id; | |
798 | ||
799 | p_ramrod->sb_id = cpu_to_le16(p_params->sb); | |
800 | p_ramrod->sb_index = p_params->sb_idx; | |
801 | p_ramrod->stats_counter_id = stats_id; | |
cee4d264 | 802 | |
1a635e48 | 803 | p_ramrod->queue_zone_id = cpu_to_le16(abs_tx_q_id); |
cee4d264 | 804 | |
1a635e48 | 805 | p_ramrod->pbl_size = cpu_to_le16(pbl_size); |
94494598 | 806 | DMA_REGPAIR_LE(p_ramrod->pbl_base_addr, pbl_addr); |
cee4d264 | 807 | |
1a635e48 YM |
808 | pq_id = qed_get_qm_pq(p_hwfn, PROTOCOLID_ETH, p_pq_params); |
809 | p_ramrod->qm_pq_id = cpu_to_le16(pq_id); | |
cee4d264 MC |
810 | |
811 | return qed_spq_post(p_hwfn, p_ent, NULL); | |
812 | } | |
813 | ||
814 | static int | |
815 | qed_sp_eth_tx_queue_start(struct qed_hwfn *p_hwfn, | |
816 | u16 opaque_fid, | |
817 | struct qed_queue_start_common_params *p_params, | |
818 | dma_addr_t pbl_addr, | |
dacd88d6 | 819 | u16 pbl_size, void __iomem **pp_doorbell) |
cee4d264 MC |
820 | { |
821 | struct qed_hw_cid_data *p_tx_cid; | |
822 | union qed_qm_pq_params pq_params; | |
823 | u8 abs_stats_id = 0; | |
824 | int rc; | |
825 | ||
dacd88d6 YM |
826 | if (IS_VF(p_hwfn->cdev)) { |
827 | return qed_vf_pf_txq_start(p_hwfn, | |
828 | p_params->queue_id, | |
829 | p_params->sb, | |
830 | p_params->sb_idx, | |
831 | pbl_addr, pbl_size, pp_doorbell); | |
832 | } | |
833 | ||
cee4d264 MC |
834 | rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_stats_id); |
835 | if (rc) | |
836 | return rc; | |
837 | ||
838 | p_tx_cid = &p_hwfn->p_tx_cids[p_params->queue_id]; | |
839 | memset(p_tx_cid, 0, sizeof(*p_tx_cid)); | |
840 | memset(&pq_params, 0, sizeof(pq_params)); | |
841 | ||
842 | /* Allocate a CID for the queue */ | |
1a635e48 | 843 | rc = qed_cxt_acquire_cid(p_hwfn, PROTOCOLID_ETH, &p_tx_cid->cid); |
cee4d264 MC |
844 | if (rc) { |
845 | DP_NOTICE(p_hwfn, "Failed to acquire cid\n"); | |
846 | return rc; | |
847 | } | |
848 | p_tx_cid->b_cid_allocated = true; | |
849 | ||
850 | DP_VERBOSE(p_hwfn, QED_MSG_SP, | |
851 | "opaque_fid=0x%x, cid=0x%x, tx_qid=0x%x, vport_id=0x%x, sb_id=0x%x\n", | |
852 | opaque_fid, p_tx_cid->cid, | |
853 | p_params->queue_id, p_params->vport_id, p_params->sb); | |
854 | ||
855 | rc = qed_sp_eth_txq_start_ramrod(p_hwfn, | |
856 | opaque_fid, | |
857 | p_tx_cid->cid, | |
858 | p_params, | |
859 | abs_stats_id, | |
860 | pbl_addr, | |
861 | pbl_size, | |
862 | &pq_params); | |
863 | ||
864 | *pp_doorbell = (u8 __iomem *)p_hwfn->doorbells + | |
865 | qed_db_addr(p_tx_cid->cid, DQ_DEMS_LEGACY); | |
866 | ||
867 | if (rc) | |
868 | qed_sp_release_queue_cid(p_hwfn, p_tx_cid); | |
869 | ||
870 | return rc; | |
871 | } | |
872 | ||
dacd88d6 | 873 | int qed_sp_eth_tx_queue_stop(struct qed_hwfn *p_hwfn, u16 tx_queue_id) |
cee4d264 MC |
874 | { |
875 | struct qed_hw_cid_data *p_tx_cid = &p_hwfn->p_tx_cids[tx_queue_id]; | |
cee4d264 | 876 | struct qed_spq_entry *p_ent = NULL; |
06f56b81 | 877 | struct qed_sp_init_data init_data; |
cee4d264 MC |
878 | int rc = -EINVAL; |
879 | ||
dacd88d6 YM |
880 | if (IS_VF(p_hwfn->cdev)) |
881 | return qed_vf_pf_txq_stop(p_hwfn, tx_queue_id); | |
882 | ||
06f56b81 YM |
883 | /* Get SPQ entry */ |
884 | memset(&init_data, 0, sizeof(init_data)); | |
885 | init_data.cid = p_tx_cid->cid; | |
886 | init_data.opaque_fid = p_tx_cid->opaque_fid; | |
887 | init_data.comp_mode = QED_SPQ_MODE_EBLOCK; | |
cee4d264 MC |
888 | |
889 | rc = qed_sp_init_request(p_hwfn, &p_ent, | |
cee4d264 | 890 | ETH_RAMROD_TX_QUEUE_STOP, |
06f56b81 | 891 | PROTOCOLID_ETH, &init_data); |
cee4d264 MC |
892 | if (rc) |
893 | return rc; | |
894 | ||
895 | rc = qed_spq_post(p_hwfn, p_ent, NULL); | |
896 | if (rc) | |
897 | return rc; | |
898 | ||
899 | return qed_sp_release_queue_cid(p_hwfn, p_tx_cid); | |
900 | } | |
901 | ||
1a635e48 | 902 | static enum eth_filter_action qed_filter_action(enum qed_filter_opcode opcode) |
cee4d264 MC |
903 | { |
904 | enum eth_filter_action action = MAX_ETH_FILTER_ACTION; | |
905 | ||
906 | switch (opcode) { | |
907 | case QED_FILTER_ADD: | |
908 | action = ETH_FILTER_ACTION_ADD; | |
909 | break; | |
910 | case QED_FILTER_REMOVE: | |
911 | action = ETH_FILTER_ACTION_REMOVE; | |
912 | break; | |
cee4d264 | 913 | case QED_FILTER_FLUSH: |
fc48b7a6 | 914 | action = ETH_FILTER_ACTION_REMOVE_ALL; |
cee4d264 MC |
915 | break; |
916 | default: | |
917 | action = MAX_ETH_FILTER_ACTION; | |
918 | } | |
919 | ||
920 | return action; | |
921 | } | |
922 | ||
923 | static void qed_set_fw_mac_addr(__le16 *fw_msb, | |
924 | __le16 *fw_mid, | |
925 | __le16 *fw_lsb, | |
926 | u8 *mac) | |
927 | { | |
928 | ((u8 *)fw_msb)[0] = mac[1]; | |
929 | ((u8 *)fw_msb)[1] = mac[0]; | |
930 | ((u8 *)fw_mid)[0] = mac[3]; | |
931 | ((u8 *)fw_mid)[1] = mac[2]; | |
932 | ((u8 *)fw_lsb)[0] = mac[5]; | |
933 | ((u8 *)fw_lsb)[1] = mac[4]; | |
934 | } | |
935 | ||
936 | static int | |
937 | qed_filter_ucast_common(struct qed_hwfn *p_hwfn, | |
938 | u16 opaque_fid, | |
939 | struct qed_filter_ucast *p_filter_cmd, | |
940 | struct vport_filter_update_ramrod_data **pp_ramrod, | |
941 | struct qed_spq_entry **pp_ent, | |
942 | enum spq_mode comp_mode, | |
943 | struct qed_spq_comp_cb *p_comp_data) | |
944 | { | |
945 | u8 vport_to_add_to = 0, vport_to_remove_from = 0; | |
946 | struct vport_filter_update_ramrod_data *p_ramrod; | |
cee4d264 MC |
947 | struct eth_filter_cmd *p_first_filter; |
948 | struct eth_filter_cmd *p_second_filter; | |
06f56b81 | 949 | struct qed_sp_init_data init_data; |
cee4d264 MC |
950 | enum eth_filter_action action; |
951 | int rc; | |
952 | ||
953 | rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from, | |
954 | &vport_to_remove_from); | |
955 | if (rc) | |
956 | return rc; | |
957 | ||
958 | rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to, | |
959 | &vport_to_add_to); | |
960 | if (rc) | |
961 | return rc; | |
962 | ||
06f56b81 YM |
963 | /* Get SPQ entry */ |
964 | memset(&init_data, 0, sizeof(init_data)); | |
965 | init_data.cid = qed_spq_get_cid(p_hwfn); | |
966 | init_data.opaque_fid = opaque_fid; | |
967 | init_data.comp_mode = comp_mode; | |
968 | init_data.p_comp_data = p_comp_data; | |
cee4d264 MC |
969 | |
970 | rc = qed_sp_init_request(p_hwfn, pp_ent, | |
cee4d264 | 971 | ETH_RAMROD_FILTERS_UPDATE, |
06f56b81 | 972 | PROTOCOLID_ETH, &init_data); |
cee4d264 MC |
973 | if (rc) |
974 | return rc; | |
975 | ||
976 | *pp_ramrod = &(*pp_ent)->ramrod.vport_filter_update; | |
977 | p_ramrod = *pp_ramrod; | |
978 | p_ramrod->filter_cmd_hdr.rx = p_filter_cmd->is_rx_filter ? 1 : 0; | |
979 | p_ramrod->filter_cmd_hdr.tx = p_filter_cmd->is_tx_filter ? 1 : 0; | |
980 | ||
981 | switch (p_filter_cmd->opcode) { | |
fc48b7a6 | 982 | case QED_FILTER_REPLACE: |
cee4d264 MC |
983 | case QED_FILTER_MOVE: |
984 | p_ramrod->filter_cmd_hdr.cmd_cnt = 2; break; | |
985 | default: | |
986 | p_ramrod->filter_cmd_hdr.cmd_cnt = 1; break; | |
987 | } | |
988 | ||
989 | p_first_filter = &p_ramrod->filter_cmds[0]; | |
990 | p_second_filter = &p_ramrod->filter_cmds[1]; | |
991 | ||
992 | switch (p_filter_cmd->type) { | |
993 | case QED_FILTER_MAC: | |
994 | p_first_filter->type = ETH_FILTER_TYPE_MAC; break; | |
995 | case QED_FILTER_VLAN: | |
996 | p_first_filter->type = ETH_FILTER_TYPE_VLAN; break; | |
997 | case QED_FILTER_MAC_VLAN: | |
998 | p_first_filter->type = ETH_FILTER_TYPE_PAIR; break; | |
999 | case QED_FILTER_INNER_MAC: | |
1000 | p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC; break; | |
1001 | case QED_FILTER_INNER_VLAN: | |
1002 | p_first_filter->type = ETH_FILTER_TYPE_INNER_VLAN; break; | |
1003 | case QED_FILTER_INNER_PAIR: | |
1004 | p_first_filter->type = ETH_FILTER_TYPE_INNER_PAIR; break; | |
1005 | case QED_FILTER_INNER_MAC_VNI_PAIR: | |
1006 | p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR; | |
1007 | break; | |
1008 | case QED_FILTER_MAC_VNI_PAIR: | |
1009 | p_first_filter->type = ETH_FILTER_TYPE_MAC_VNI_PAIR; break; | |
1010 | case QED_FILTER_VNI: | |
1011 | p_first_filter->type = ETH_FILTER_TYPE_VNI; break; | |
1012 | } | |
1013 | ||
1014 | if ((p_first_filter->type == ETH_FILTER_TYPE_MAC) || | |
1015 | (p_first_filter->type == ETH_FILTER_TYPE_PAIR) || | |
1016 | (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC) || | |
1017 | (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR) || | |
1018 | (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) || | |
1019 | (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR)) { | |
1020 | qed_set_fw_mac_addr(&p_first_filter->mac_msb, | |
1021 | &p_first_filter->mac_mid, | |
1022 | &p_first_filter->mac_lsb, | |
1023 | (u8 *)p_filter_cmd->mac); | |
1024 | } | |
1025 | ||
1026 | if ((p_first_filter->type == ETH_FILTER_TYPE_VLAN) || | |
1027 | (p_first_filter->type == ETH_FILTER_TYPE_PAIR) || | |
1028 | (p_first_filter->type == ETH_FILTER_TYPE_INNER_VLAN) || | |
1029 | (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR)) | |
1030 | p_first_filter->vlan_id = cpu_to_le16(p_filter_cmd->vlan); | |
1031 | ||
1032 | if ((p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) || | |
1033 | (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR) || | |
1034 | (p_first_filter->type == ETH_FILTER_TYPE_VNI)) | |
1035 | p_first_filter->vni = cpu_to_le32(p_filter_cmd->vni); | |
1036 | ||
1037 | if (p_filter_cmd->opcode == QED_FILTER_MOVE) { | |
1a635e48 YM |
1038 | p_second_filter->type = p_first_filter->type; |
1039 | p_second_filter->mac_msb = p_first_filter->mac_msb; | |
1040 | p_second_filter->mac_mid = p_first_filter->mac_mid; | |
1041 | p_second_filter->mac_lsb = p_first_filter->mac_lsb; | |
1042 | p_second_filter->vlan_id = p_first_filter->vlan_id; | |
1043 | p_second_filter->vni = p_first_filter->vni; | |
cee4d264 MC |
1044 | |
1045 | p_first_filter->action = ETH_FILTER_ACTION_REMOVE; | |
1046 | ||
1047 | p_first_filter->vport_id = vport_to_remove_from; | |
1048 | ||
1a635e48 YM |
1049 | p_second_filter->action = ETH_FILTER_ACTION_ADD; |
1050 | p_second_filter->vport_id = vport_to_add_to; | |
fc48b7a6 YM |
1051 | } else if (p_filter_cmd->opcode == QED_FILTER_REPLACE) { |
1052 | p_first_filter->vport_id = vport_to_add_to; | |
1053 | memcpy(p_second_filter, p_first_filter, | |
1054 | sizeof(*p_second_filter)); | |
1055 | p_first_filter->action = ETH_FILTER_ACTION_REMOVE_ALL; | |
1056 | p_second_filter->action = ETH_FILTER_ACTION_ADD; | |
cee4d264 MC |
1057 | } else { |
1058 | action = qed_filter_action(p_filter_cmd->opcode); | |
1059 | ||
1060 | if (action == MAX_ETH_FILTER_ACTION) { | |
1061 | DP_NOTICE(p_hwfn, | |
1062 | "%d is not supported yet\n", | |
1063 | p_filter_cmd->opcode); | |
1064 | return -EINVAL; | |
1065 | } | |
1066 | ||
1067 | p_first_filter->action = action; | |
1068 | p_first_filter->vport_id = (p_filter_cmd->opcode == | |
1069 | QED_FILTER_REMOVE) ? | |
1070 | vport_to_remove_from : | |
1071 | vport_to_add_to; | |
1072 | } | |
1073 | ||
1074 | return 0; | |
1075 | } | |
1076 | ||
dacd88d6 YM |
1077 | int qed_sp_eth_filter_ucast(struct qed_hwfn *p_hwfn, |
1078 | u16 opaque_fid, | |
1079 | struct qed_filter_ucast *p_filter_cmd, | |
1080 | enum spq_mode comp_mode, | |
1081 | struct qed_spq_comp_cb *p_comp_data) | |
cee4d264 MC |
1082 | { |
1083 | struct vport_filter_update_ramrod_data *p_ramrod = NULL; | |
1084 | struct qed_spq_entry *p_ent = NULL; | |
1085 | struct eth_filter_cmd_header *p_header; | |
1086 | int rc; | |
1087 | ||
1088 | rc = qed_filter_ucast_common(p_hwfn, opaque_fid, p_filter_cmd, | |
1089 | &p_ramrod, &p_ent, | |
1090 | comp_mode, p_comp_data); | |
1a635e48 | 1091 | if (rc) { |
cee4d264 MC |
1092 | DP_ERR(p_hwfn, "Uni. filter command failed %d\n", rc); |
1093 | return rc; | |
1094 | } | |
1095 | p_header = &p_ramrod->filter_cmd_hdr; | |
1096 | p_header->assert_on_error = p_filter_cmd->assert_on_error; | |
1097 | ||
1098 | rc = qed_spq_post(p_hwfn, p_ent, NULL); | |
1a635e48 YM |
1099 | if (rc) { |
1100 | DP_ERR(p_hwfn, "Unicast filter ADD command failed %d\n", rc); | |
cee4d264 MC |
1101 | return rc; |
1102 | } | |
1103 | ||
1104 | DP_VERBOSE(p_hwfn, QED_MSG_SP, | |
1105 | "Unicast filter configured, opcode = %s, type = %s, cmd_cnt = %d, is_rx_filter = %d, is_tx_filter = %d\n", | |
1106 | (p_filter_cmd->opcode == QED_FILTER_ADD) ? "ADD" : | |
1107 | ((p_filter_cmd->opcode == QED_FILTER_REMOVE) ? | |
1108 | "REMOVE" : | |
1109 | ((p_filter_cmd->opcode == QED_FILTER_MOVE) ? | |
1110 | "MOVE" : "REPLACE")), | |
1111 | (p_filter_cmd->type == QED_FILTER_MAC) ? "MAC" : | |
1112 | ((p_filter_cmd->type == QED_FILTER_VLAN) ? | |
1113 | "VLAN" : "MAC & VLAN"), | |
1114 | p_ramrod->filter_cmd_hdr.cmd_cnt, | |
1115 | p_filter_cmd->is_rx_filter, | |
1116 | p_filter_cmd->is_tx_filter); | |
1117 | DP_VERBOSE(p_hwfn, QED_MSG_SP, | |
1118 | "vport_to_add_to = %d, vport_to_remove_from = %d, mac = %2x:%2x:%2x:%2x:%2x:%2x, vlan = %d\n", | |
1119 | p_filter_cmd->vport_to_add_to, | |
1120 | p_filter_cmd->vport_to_remove_from, | |
1121 | p_filter_cmd->mac[0], | |
1122 | p_filter_cmd->mac[1], | |
1123 | p_filter_cmd->mac[2], | |
1124 | p_filter_cmd->mac[3], | |
1125 | p_filter_cmd->mac[4], | |
1126 | p_filter_cmd->mac[5], | |
1127 | p_filter_cmd->vlan); | |
1128 | ||
1129 | return 0; | |
1130 | } | |
1131 | ||
1132 | /******************************************************************************* | |
1133 | * Description: | |
1134 | * Calculates crc 32 on a buffer | |
1135 | * Note: crc32_length MUST be aligned to 8 | |
1136 | * Return: | |
1137 | ******************************************************************************/ | |
1138 | static u32 qed_calc_crc32c(u8 *crc32_packet, | |
1a635e48 | 1139 | u32 crc32_length, u32 crc32_seed, u8 complement) |
cee4d264 | 1140 | { |
1a635e48 YM |
1141 | u32 byte = 0, bit = 0, crc32_result = crc32_seed; |
1142 | u8 msb = 0, current_byte = 0; | |
cee4d264 MC |
1143 | |
1144 | if ((!crc32_packet) || | |
1145 | (crc32_length == 0) || | |
1146 | ((crc32_length % 8) != 0)) | |
1147 | return crc32_result; | |
1148 | for (byte = 0; byte < crc32_length; byte++) { | |
1149 | current_byte = crc32_packet[byte]; | |
1150 | for (bit = 0; bit < 8; bit++) { | |
1151 | msb = (u8)(crc32_result >> 31); | |
1152 | crc32_result = crc32_result << 1; | |
1153 | if (msb != (0x1 & (current_byte >> bit))) { | |
1154 | crc32_result = crc32_result ^ CRC32_POLY; | |
1155 | crc32_result |= 1; /*crc32_result[0] = 1;*/ | |
1156 | } | |
1157 | } | |
1158 | } | |
1159 | return crc32_result; | |
1160 | } | |
1161 | ||
1a635e48 | 1162 | static u32 qed_crc32c_le(u32 seed, u8 *mac, u32 len) |
cee4d264 MC |
1163 | { |
1164 | u32 packet_buf[2] = { 0 }; | |
1165 | ||
1166 | memcpy((u8 *)(&packet_buf[0]), &mac[0], 6); | |
1167 | return qed_calc_crc32c((u8 *)packet_buf, 8, seed, 0); | |
1168 | } | |
1169 | ||
dacd88d6 | 1170 | u8 qed_mcast_bin_from_mac(u8 *mac) |
cee4d264 MC |
1171 | { |
1172 | u32 crc = qed_crc32c_le(ETH_MULTICAST_BIN_FROM_MAC_SEED, | |
1173 | mac, ETH_ALEN); | |
1174 | ||
1175 | return crc & 0xff; | |
1176 | } | |
1177 | ||
1178 | static int | |
1179 | qed_sp_eth_filter_mcast(struct qed_hwfn *p_hwfn, | |
1180 | u16 opaque_fid, | |
1181 | struct qed_filter_mcast *p_filter_cmd, | |
1182 | enum spq_mode comp_mode, | |
1183 | struct qed_spq_comp_cb *p_comp_data) | |
1184 | { | |
1185 | unsigned long bins[ETH_MULTICAST_MAC_BINS_IN_REGS]; | |
1186 | struct vport_update_ramrod_data *p_ramrod = NULL; | |
cee4d264 | 1187 | struct qed_spq_entry *p_ent = NULL; |
06f56b81 | 1188 | struct qed_sp_init_data init_data; |
cee4d264 MC |
1189 | u8 abs_vport_id = 0; |
1190 | int rc, i; | |
1191 | ||
83aeb933 | 1192 | if (p_filter_cmd->opcode == QED_FILTER_ADD) |
cee4d264 MC |
1193 | rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to, |
1194 | &abs_vport_id); | |
83aeb933 | 1195 | else |
cee4d264 MC |
1196 | rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from, |
1197 | &abs_vport_id); | |
83aeb933 YM |
1198 | if (rc) |
1199 | return rc; | |
cee4d264 | 1200 | |
06f56b81 YM |
1201 | /* Get SPQ entry */ |
1202 | memset(&init_data, 0, sizeof(init_data)); | |
1203 | init_data.cid = qed_spq_get_cid(p_hwfn); | |
1204 | init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; | |
1205 | init_data.comp_mode = comp_mode; | |
1206 | init_data.p_comp_data = p_comp_data; | |
cee4d264 MC |
1207 | |
1208 | rc = qed_sp_init_request(p_hwfn, &p_ent, | |
cee4d264 | 1209 | ETH_RAMROD_VPORT_UPDATE, |
06f56b81 | 1210 | PROTOCOLID_ETH, &init_data); |
cee4d264 MC |
1211 | if (rc) { |
1212 | DP_ERR(p_hwfn, "Multi-cast command failed %d\n", rc); | |
1213 | return rc; | |
1214 | } | |
1215 | ||
1216 | p_ramrod = &p_ent->ramrod.vport_update; | |
1217 | p_ramrod->common.update_approx_mcast_flg = 1; | |
1218 | ||
1219 | /* explicitly clear out the entire vector */ | |
1220 | memset(&p_ramrod->approx_mcast.bins, 0, | |
1221 | sizeof(p_ramrod->approx_mcast.bins)); | |
1222 | memset(bins, 0, sizeof(unsigned long) * | |
1223 | ETH_MULTICAST_MAC_BINS_IN_REGS); | |
1224 | /* filter ADD op is explicit set op and it removes | |
1225 | * any existing filters for the vport | |
1226 | */ | |
1227 | if (p_filter_cmd->opcode == QED_FILTER_ADD) { | |
1228 | for (i = 0; i < p_filter_cmd->num_mc_addrs; i++) { | |
1229 | u32 bit; | |
1230 | ||
1231 | bit = qed_mcast_bin_from_mac(p_filter_cmd->mac[i]); | |
1232 | __set_bit(bit, bins); | |
1233 | } | |
1234 | ||
1235 | /* Convert to correct endianity */ | |
1236 | for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) { | |
1a635e48 | 1237 | struct vport_update_ramrod_mcast *p_ramrod_bins; |
cee4d264 | 1238 | u32 *p_bins = (u32 *)bins; |
cee4d264 | 1239 | |
1a635e48 YM |
1240 | p_ramrod_bins = &p_ramrod->approx_mcast; |
1241 | p_ramrod_bins->bins[i] = cpu_to_le32(p_bins[i]); | |
cee4d264 MC |
1242 | } |
1243 | } | |
1244 | ||
1245 | p_ramrod->common.vport_id = abs_vport_id; | |
1246 | ||
1247 | return qed_spq_post(p_hwfn, p_ent, NULL); | |
1248 | } | |
1249 | ||
dacd88d6 YM |
1250 | static int qed_filter_mcast_cmd(struct qed_dev *cdev, |
1251 | struct qed_filter_mcast *p_filter_cmd, | |
1252 | enum spq_mode comp_mode, | |
1253 | struct qed_spq_comp_cb *p_comp_data) | |
cee4d264 MC |
1254 | { |
1255 | int rc = 0; | |
1256 | int i; | |
1257 | ||
1258 | /* only ADD and REMOVE operations are supported for multi-cast */ | |
1259 | if ((p_filter_cmd->opcode != QED_FILTER_ADD && | |
1260 | (p_filter_cmd->opcode != QED_FILTER_REMOVE)) || | |
1261 | (p_filter_cmd->num_mc_addrs > QED_MAX_MC_ADDRS)) | |
1262 | return -EINVAL; | |
1263 | ||
1264 | for_each_hwfn(cdev, i) { | |
1265 | struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; | |
1266 | ||
1267 | u16 opaque_fid; | |
1268 | ||
dacd88d6 YM |
1269 | if (IS_VF(cdev)) { |
1270 | qed_vf_pf_filter_mcast(p_hwfn, p_filter_cmd); | |
1271 | continue; | |
1272 | } | |
cee4d264 MC |
1273 | |
1274 | opaque_fid = p_hwfn->hw_info.opaque_fid; | |
1275 | ||
1276 | rc = qed_sp_eth_filter_mcast(p_hwfn, | |
1277 | opaque_fid, | |
1278 | p_filter_cmd, | |
1a635e48 | 1279 | comp_mode, p_comp_data); |
cee4d264 MC |
1280 | } |
1281 | return rc; | |
1282 | } | |
1283 | ||
1284 | static int qed_filter_ucast_cmd(struct qed_dev *cdev, | |
1285 | struct qed_filter_ucast *p_filter_cmd, | |
1286 | enum spq_mode comp_mode, | |
1287 | struct qed_spq_comp_cb *p_comp_data) | |
1288 | { | |
1289 | int rc = 0; | |
1290 | int i; | |
1291 | ||
1292 | for_each_hwfn(cdev, i) { | |
1293 | struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; | |
1294 | u16 opaque_fid; | |
1295 | ||
dacd88d6 YM |
1296 | if (IS_VF(cdev)) { |
1297 | rc = qed_vf_pf_filter_ucast(p_hwfn, p_filter_cmd); | |
1298 | continue; | |
1299 | } | |
cee4d264 MC |
1300 | |
1301 | opaque_fid = p_hwfn->hw_info.opaque_fid; | |
1302 | ||
1303 | rc = qed_sp_eth_filter_ucast(p_hwfn, | |
1304 | opaque_fid, | |
1305 | p_filter_cmd, | |
1a635e48 YM |
1306 | comp_mode, p_comp_data); |
1307 | if (rc) | |
dacd88d6 | 1308 | break; |
cee4d264 MC |
1309 | } |
1310 | ||
1311 | return rc; | |
1312 | } | |
1313 | ||
86622ee7 YM |
1314 | /* Statistics related code */ |
1315 | static void __qed_get_vport_pstats_addrlen(struct qed_hwfn *p_hwfn, | |
1316 | u32 *p_addr, | |
dacd88d6 | 1317 | u32 *p_len, u16 statistics_bin) |
86622ee7 | 1318 | { |
dacd88d6 YM |
1319 | if (IS_PF(p_hwfn->cdev)) { |
1320 | *p_addr = BAR0_MAP_REG_PSDM_RAM + | |
1321 | PSTORM_QUEUE_STAT_OFFSET(statistics_bin); | |
1322 | *p_len = sizeof(struct eth_pstorm_per_queue_stat); | |
1323 | } else { | |
1324 | struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info; | |
1325 | struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp; | |
1326 | ||
1327 | *p_addr = p_resp->pfdev_info.stats_info.pstats.address; | |
1328 | *p_len = p_resp->pfdev_info.stats_info.pstats.len; | |
1329 | } | |
86622ee7 YM |
1330 | } |
1331 | ||
1332 | static void __qed_get_vport_pstats(struct qed_hwfn *p_hwfn, | |
1333 | struct qed_ptt *p_ptt, | |
1334 | struct qed_eth_stats *p_stats, | |
1335 | u16 statistics_bin) | |
1336 | { | |
1337 | struct eth_pstorm_per_queue_stat pstats; | |
1338 | u32 pstats_addr = 0, pstats_len = 0; | |
1339 | ||
1340 | __qed_get_vport_pstats_addrlen(p_hwfn, &pstats_addr, &pstats_len, | |
1341 | statistics_bin); | |
1342 | ||
1343 | memset(&pstats, 0, sizeof(pstats)); | |
dacd88d6 YM |
1344 | qed_memcpy_from(p_hwfn, p_ptt, &pstats, pstats_addr, pstats_len); |
1345 | ||
1346 | p_stats->tx_ucast_bytes += HILO_64_REGPAIR(pstats.sent_ucast_bytes); | |
1347 | p_stats->tx_mcast_bytes += HILO_64_REGPAIR(pstats.sent_mcast_bytes); | |
1348 | p_stats->tx_bcast_bytes += HILO_64_REGPAIR(pstats.sent_bcast_bytes); | |
1349 | p_stats->tx_ucast_pkts += HILO_64_REGPAIR(pstats.sent_ucast_pkts); | |
1350 | p_stats->tx_mcast_pkts += HILO_64_REGPAIR(pstats.sent_mcast_pkts); | |
1351 | p_stats->tx_bcast_pkts += HILO_64_REGPAIR(pstats.sent_bcast_pkts); | |
1352 | p_stats->tx_err_drop_pkts += HILO_64_REGPAIR(pstats.error_drop_pkts); | |
86622ee7 YM |
1353 | } |
1354 | ||
1355 | static void __qed_get_vport_tstats(struct qed_hwfn *p_hwfn, | |
1356 | struct qed_ptt *p_ptt, | |
1357 | struct qed_eth_stats *p_stats, | |
1358 | u16 statistics_bin) | |
1359 | { | |
86622ee7 | 1360 | struct tstorm_per_port_stat tstats; |
dacd88d6 | 1361 | u32 tstats_addr, tstats_len; |
86622ee7 | 1362 | |
dacd88d6 YM |
1363 | if (IS_PF(p_hwfn->cdev)) { |
1364 | tstats_addr = BAR0_MAP_REG_TSDM_RAM + | |
1365 | TSTORM_PORT_STAT_OFFSET(MFW_PORT(p_hwfn)); | |
1366 | tstats_len = sizeof(struct tstorm_per_port_stat); | |
1367 | } else { | |
1368 | struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info; | |
1369 | struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp; | |
1370 | ||
1371 | tstats_addr = p_resp->pfdev_info.stats_info.tstats.address; | |
1372 | tstats_len = p_resp->pfdev_info.stats_info.tstats.len; | |
1373 | } | |
86622ee7 YM |
1374 | |
1375 | memset(&tstats, 0, sizeof(tstats)); | |
dacd88d6 | 1376 | qed_memcpy_from(p_hwfn, p_ptt, &tstats, tstats_addr, tstats_len); |
86622ee7 YM |
1377 | |
1378 | p_stats->mftag_filter_discards += | |
1379 | HILO_64_REGPAIR(tstats.mftag_filter_discard); | |
1380 | p_stats->mac_filter_discards += | |
1381 | HILO_64_REGPAIR(tstats.eth_mac_filter_discard); | |
1382 | } | |
1383 | ||
1384 | static void __qed_get_vport_ustats_addrlen(struct qed_hwfn *p_hwfn, | |
1385 | u32 *p_addr, | |
dacd88d6 | 1386 | u32 *p_len, u16 statistics_bin) |
86622ee7 | 1387 | { |
dacd88d6 YM |
1388 | if (IS_PF(p_hwfn->cdev)) { |
1389 | *p_addr = BAR0_MAP_REG_USDM_RAM + | |
1390 | USTORM_QUEUE_STAT_OFFSET(statistics_bin); | |
1391 | *p_len = sizeof(struct eth_ustorm_per_queue_stat); | |
1392 | } else { | |
1393 | struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info; | |
1394 | struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp; | |
1395 | ||
1396 | *p_addr = p_resp->pfdev_info.stats_info.ustats.address; | |
1397 | *p_len = p_resp->pfdev_info.stats_info.ustats.len; | |
1398 | } | |
86622ee7 YM |
1399 | } |
1400 | ||
1401 | static void __qed_get_vport_ustats(struct qed_hwfn *p_hwfn, | |
1402 | struct qed_ptt *p_ptt, | |
1403 | struct qed_eth_stats *p_stats, | |
1404 | u16 statistics_bin) | |
1405 | { | |
1406 | struct eth_ustorm_per_queue_stat ustats; | |
1407 | u32 ustats_addr = 0, ustats_len = 0; | |
1408 | ||
1409 | __qed_get_vport_ustats_addrlen(p_hwfn, &ustats_addr, &ustats_len, | |
1410 | statistics_bin); | |
1411 | ||
1412 | memset(&ustats, 0, sizeof(ustats)); | |
dacd88d6 YM |
1413 | qed_memcpy_from(p_hwfn, p_ptt, &ustats, ustats_addr, ustats_len); |
1414 | ||
1415 | p_stats->rx_ucast_bytes += HILO_64_REGPAIR(ustats.rcv_ucast_bytes); | |
1416 | p_stats->rx_mcast_bytes += HILO_64_REGPAIR(ustats.rcv_mcast_bytes); | |
1417 | p_stats->rx_bcast_bytes += HILO_64_REGPAIR(ustats.rcv_bcast_bytes); | |
1418 | p_stats->rx_ucast_pkts += HILO_64_REGPAIR(ustats.rcv_ucast_pkts); | |
1419 | p_stats->rx_mcast_pkts += HILO_64_REGPAIR(ustats.rcv_mcast_pkts); | |
1420 | p_stats->rx_bcast_pkts += HILO_64_REGPAIR(ustats.rcv_bcast_pkts); | |
86622ee7 YM |
1421 | } |
1422 | ||
1423 | static void __qed_get_vport_mstats_addrlen(struct qed_hwfn *p_hwfn, | |
1424 | u32 *p_addr, | |
dacd88d6 | 1425 | u32 *p_len, u16 statistics_bin) |
86622ee7 | 1426 | { |
dacd88d6 YM |
1427 | if (IS_PF(p_hwfn->cdev)) { |
1428 | *p_addr = BAR0_MAP_REG_MSDM_RAM + | |
1429 | MSTORM_QUEUE_STAT_OFFSET(statistics_bin); | |
1430 | *p_len = sizeof(struct eth_mstorm_per_queue_stat); | |
1431 | } else { | |
1432 | struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info; | |
1433 | struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp; | |
1434 | ||
1435 | *p_addr = p_resp->pfdev_info.stats_info.mstats.address; | |
1436 | *p_len = p_resp->pfdev_info.stats_info.mstats.len; | |
1437 | } | |
86622ee7 YM |
1438 | } |
1439 | ||
1440 | static void __qed_get_vport_mstats(struct qed_hwfn *p_hwfn, | |
1441 | struct qed_ptt *p_ptt, | |
1442 | struct qed_eth_stats *p_stats, | |
1443 | u16 statistics_bin) | |
1444 | { | |
1445 | struct eth_mstorm_per_queue_stat mstats; | |
1446 | u32 mstats_addr = 0, mstats_len = 0; | |
1447 | ||
1448 | __qed_get_vport_mstats_addrlen(p_hwfn, &mstats_addr, &mstats_len, | |
1449 | statistics_bin); | |
1450 | ||
1451 | memset(&mstats, 0, sizeof(mstats)); | |
dacd88d6 | 1452 | qed_memcpy_from(p_hwfn, p_ptt, &mstats, mstats_addr, mstats_len); |
86622ee7 | 1453 | |
dacd88d6 | 1454 | p_stats->no_buff_discards += HILO_64_REGPAIR(mstats.no_buff_discard); |
86622ee7 YM |
1455 | p_stats->packet_too_big_discard += |
1456 | HILO_64_REGPAIR(mstats.packet_too_big_discard); | |
dacd88d6 | 1457 | p_stats->ttl0_discard += HILO_64_REGPAIR(mstats.ttl0_discard); |
86622ee7 YM |
1458 | p_stats->tpa_coalesced_pkts += |
1459 | HILO_64_REGPAIR(mstats.tpa_coalesced_pkts); | |
1460 | p_stats->tpa_coalesced_events += | |
1461 | HILO_64_REGPAIR(mstats.tpa_coalesced_events); | |
dacd88d6 | 1462 | p_stats->tpa_aborts_num += HILO_64_REGPAIR(mstats.tpa_aborts_num); |
86622ee7 YM |
1463 | p_stats->tpa_coalesced_bytes += |
1464 | HILO_64_REGPAIR(mstats.tpa_coalesced_bytes); | |
1465 | } | |
1466 | ||
1467 | static void __qed_get_vport_port_stats(struct qed_hwfn *p_hwfn, | |
1468 | struct qed_ptt *p_ptt, | |
1469 | struct qed_eth_stats *p_stats) | |
1470 | { | |
1471 | struct port_stats port_stats; | |
1472 | int j; | |
1473 | ||
1474 | memset(&port_stats, 0, sizeof(port_stats)); | |
1475 | ||
1476 | qed_memcpy_from(p_hwfn, p_ptt, &port_stats, | |
1477 | p_hwfn->mcp_info->port_addr + | |
1478 | offsetof(struct public_port, stats), | |
1479 | sizeof(port_stats)); | |
1480 | ||
351a4ded YM |
1481 | p_stats->rx_64_byte_packets += port_stats.eth.r64; |
1482 | p_stats->rx_65_to_127_byte_packets += port_stats.eth.r127; | |
1483 | p_stats->rx_128_to_255_byte_packets += port_stats.eth.r255; | |
1484 | p_stats->rx_256_to_511_byte_packets += port_stats.eth.r511; | |
1485 | p_stats->rx_512_to_1023_byte_packets += port_stats.eth.r1023; | |
1486 | p_stats->rx_1024_to_1518_byte_packets += port_stats.eth.r1518; | |
1487 | p_stats->rx_1519_to_1522_byte_packets += port_stats.eth.r1522; | |
1488 | p_stats->rx_1519_to_2047_byte_packets += port_stats.eth.r2047; | |
1489 | p_stats->rx_2048_to_4095_byte_packets += port_stats.eth.r4095; | |
1490 | p_stats->rx_4096_to_9216_byte_packets += port_stats.eth.r9216; | |
1491 | p_stats->rx_9217_to_16383_byte_packets += port_stats.eth.r16383; | |
1492 | p_stats->rx_crc_errors += port_stats.eth.rfcs; | |
1493 | p_stats->rx_mac_crtl_frames += port_stats.eth.rxcf; | |
1494 | p_stats->rx_pause_frames += port_stats.eth.rxpf; | |
1495 | p_stats->rx_pfc_frames += port_stats.eth.rxpp; | |
1496 | p_stats->rx_align_errors += port_stats.eth.raln; | |
1497 | p_stats->rx_carrier_errors += port_stats.eth.rfcr; | |
1498 | p_stats->rx_oversize_packets += port_stats.eth.rovr; | |
1499 | p_stats->rx_jabbers += port_stats.eth.rjbr; | |
1500 | p_stats->rx_undersize_packets += port_stats.eth.rund; | |
1501 | p_stats->rx_fragments += port_stats.eth.rfrg; | |
1502 | p_stats->tx_64_byte_packets += port_stats.eth.t64; | |
1503 | p_stats->tx_65_to_127_byte_packets += port_stats.eth.t127; | |
1504 | p_stats->tx_128_to_255_byte_packets += port_stats.eth.t255; | |
1505 | p_stats->tx_256_to_511_byte_packets += port_stats.eth.t511; | |
1506 | p_stats->tx_512_to_1023_byte_packets += port_stats.eth.t1023; | |
1507 | p_stats->tx_1024_to_1518_byte_packets += port_stats.eth.t1518; | |
1508 | p_stats->tx_1519_to_2047_byte_packets += port_stats.eth.t2047; | |
1509 | p_stats->tx_2048_to_4095_byte_packets += port_stats.eth.t4095; | |
1510 | p_stats->tx_4096_to_9216_byte_packets += port_stats.eth.t9216; | |
1511 | p_stats->tx_9217_to_16383_byte_packets += port_stats.eth.t16383; | |
1512 | p_stats->tx_pause_frames += port_stats.eth.txpf; | |
1513 | p_stats->tx_pfc_frames += port_stats.eth.txpp; | |
1514 | p_stats->tx_lpi_entry_count += port_stats.eth.tlpiec; | |
1515 | p_stats->tx_total_collisions += port_stats.eth.tncl; | |
1516 | p_stats->rx_mac_bytes += port_stats.eth.rbyte; | |
1517 | p_stats->rx_mac_uc_packets += port_stats.eth.rxuca; | |
1518 | p_stats->rx_mac_mc_packets += port_stats.eth.rxmca; | |
1519 | p_stats->rx_mac_bc_packets += port_stats.eth.rxbca; | |
1520 | p_stats->rx_mac_frames_ok += port_stats.eth.rxpok; | |
1521 | p_stats->tx_mac_bytes += port_stats.eth.tbyte; | |
1522 | p_stats->tx_mac_uc_packets += port_stats.eth.txuca; | |
1523 | p_stats->tx_mac_mc_packets += port_stats.eth.txmca; | |
1524 | p_stats->tx_mac_bc_packets += port_stats.eth.txbca; | |
1525 | p_stats->tx_mac_ctrl_frames += port_stats.eth.txcf; | |
86622ee7 YM |
1526 | for (j = 0; j < 8; j++) { |
1527 | p_stats->brb_truncates += port_stats.brb.brb_truncate[j]; | |
1528 | p_stats->brb_discards += port_stats.brb.brb_discard[j]; | |
1529 | } | |
1530 | } | |
1531 | ||
1532 | static void __qed_get_vport_stats(struct qed_hwfn *p_hwfn, | |
1533 | struct qed_ptt *p_ptt, | |
1534 | struct qed_eth_stats *stats, | |
dacd88d6 | 1535 | u16 statistics_bin, bool b_get_port_stats) |
86622ee7 YM |
1536 | { |
1537 | __qed_get_vport_mstats(p_hwfn, p_ptt, stats, statistics_bin); | |
1538 | __qed_get_vport_ustats(p_hwfn, p_ptt, stats, statistics_bin); | |
1539 | __qed_get_vport_tstats(p_hwfn, p_ptt, stats, statistics_bin); | |
1540 | __qed_get_vport_pstats(p_hwfn, p_ptt, stats, statistics_bin); | |
1541 | ||
dacd88d6 | 1542 | if (b_get_port_stats && p_hwfn->mcp_info) |
86622ee7 YM |
1543 | __qed_get_vport_port_stats(p_hwfn, p_ptt, stats); |
1544 | } | |
1545 | ||
1546 | static void _qed_get_vport_stats(struct qed_dev *cdev, | |
1547 | struct qed_eth_stats *stats) | |
1548 | { | |
dacd88d6 YM |
1549 | u8 fw_vport = 0; |
1550 | int i; | |
86622ee7 YM |
1551 | |
1552 | memset(stats, 0, sizeof(*stats)); | |
1553 | ||
1554 | for_each_hwfn(cdev, i) { | |
1555 | struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; | |
dacd88d6 YM |
1556 | struct qed_ptt *p_ptt = IS_PF(cdev) ? qed_ptt_acquire(p_hwfn) |
1557 | : NULL; | |
1558 | ||
1559 | if (IS_PF(cdev)) { | |
1560 | /* The main vport index is relative first */ | |
1561 | if (qed_fw_vport(p_hwfn, 0, &fw_vport)) { | |
1562 | DP_ERR(p_hwfn, "No vport available!\n"); | |
1563 | goto out; | |
1564 | } | |
86622ee7 YM |
1565 | } |
1566 | ||
dacd88d6 | 1567 | if (IS_PF(cdev) && !p_ptt) { |
86622ee7 YM |
1568 | DP_ERR(p_hwfn, "Failed to acquire ptt\n"); |
1569 | continue; | |
1570 | } | |
1571 | ||
dacd88d6 YM |
1572 | __qed_get_vport_stats(p_hwfn, p_ptt, stats, fw_vport, |
1573 | IS_PF(cdev) ? true : false); | |
86622ee7 | 1574 | |
dacd88d6 YM |
1575 | out: |
1576 | if (IS_PF(cdev) && p_ptt) | |
1577 | qed_ptt_release(p_hwfn, p_ptt); | |
86622ee7 YM |
1578 | } |
1579 | } | |
1580 | ||
1a635e48 | 1581 | void qed_get_vport_stats(struct qed_dev *cdev, struct qed_eth_stats *stats) |
86622ee7 YM |
1582 | { |
1583 | u32 i; | |
1584 | ||
1585 | if (!cdev) { | |
1586 | memset(stats, 0, sizeof(*stats)); | |
1587 | return; | |
1588 | } | |
1589 | ||
1590 | _qed_get_vport_stats(cdev, stats); | |
1591 | ||
1592 | if (!cdev->reset_stats) | |
1593 | return; | |
1594 | ||
1595 | /* Reduce the statistics baseline */ | |
1596 | for (i = 0; i < sizeof(struct qed_eth_stats) / sizeof(u64); i++) | |
1597 | ((u64 *)stats)[i] -= ((u64 *)cdev->reset_stats)[i]; | |
1598 | } | |
1599 | ||
1600 | /* zeroes V-PORT specific portion of stats (Port stats remains untouched) */ | |
1601 | void qed_reset_vport_stats(struct qed_dev *cdev) | |
1602 | { | |
1603 | int i; | |
1604 | ||
1605 | for_each_hwfn(cdev, i) { | |
1606 | struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; | |
1607 | struct eth_mstorm_per_queue_stat mstats; | |
1608 | struct eth_ustorm_per_queue_stat ustats; | |
1609 | struct eth_pstorm_per_queue_stat pstats; | |
dacd88d6 YM |
1610 | struct qed_ptt *p_ptt = IS_PF(cdev) ? qed_ptt_acquire(p_hwfn) |
1611 | : NULL; | |
86622ee7 YM |
1612 | u32 addr = 0, len = 0; |
1613 | ||
dacd88d6 | 1614 | if (IS_PF(cdev) && !p_ptt) { |
86622ee7 YM |
1615 | DP_ERR(p_hwfn, "Failed to acquire ptt\n"); |
1616 | continue; | |
1617 | } | |
1618 | ||
1619 | memset(&mstats, 0, sizeof(mstats)); | |
1620 | __qed_get_vport_mstats_addrlen(p_hwfn, &addr, &len, 0); | |
1621 | qed_memcpy_to(p_hwfn, p_ptt, addr, &mstats, len); | |
1622 | ||
1623 | memset(&ustats, 0, sizeof(ustats)); | |
1624 | __qed_get_vport_ustats_addrlen(p_hwfn, &addr, &len, 0); | |
1625 | qed_memcpy_to(p_hwfn, p_ptt, addr, &ustats, len); | |
1626 | ||
1627 | memset(&pstats, 0, sizeof(pstats)); | |
1628 | __qed_get_vport_pstats_addrlen(p_hwfn, &addr, &len, 0); | |
1629 | qed_memcpy_to(p_hwfn, p_ptt, addr, &pstats, len); | |
1630 | ||
dacd88d6 YM |
1631 | if (IS_PF(cdev)) |
1632 | qed_ptt_release(p_hwfn, p_ptt); | |
86622ee7 YM |
1633 | } |
1634 | ||
1635 | /* PORT statistics are not necessarily reset, so we need to | |
1636 | * read and create a baseline for future statistics. | |
1637 | */ | |
1638 | if (!cdev->reset_stats) | |
1639 | DP_INFO(cdev, "Reset stats not allocated\n"); | |
1640 | else | |
1641 | _qed_get_vport_stats(cdev, cdev->reset_stats); | |
1642 | } | |
1643 | ||
25c089d7 YM |
1644 | static int qed_fill_eth_dev_info(struct qed_dev *cdev, |
1645 | struct qed_dev_eth_info *info) | |
1646 | { | |
1647 | int i; | |
1648 | ||
1649 | memset(info, 0, sizeof(*info)); | |
1650 | ||
1651 | info->num_tc = 1; | |
1652 | ||
1408cc1f | 1653 | if (IS_PF(cdev)) { |
25eb8d46 | 1654 | int max_vf_vlan_filters = 0; |
7b7e70f9 | 1655 | int max_vf_mac_filters = 0; |
25eb8d46 | 1656 | |
1408cc1f YM |
1657 | if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) { |
1658 | for_each_hwfn(cdev, i) | |
1659 | info->num_queues += | |
1660 | FEAT_NUM(&cdev->hwfns[i], QED_PF_L2_QUE); | |
1661 | if (cdev->int_params.fp_msix_cnt) | |
1662 | info->num_queues = | |
1663 | min_t(u8, info->num_queues, | |
1664 | cdev->int_params.fp_msix_cnt); | |
1665 | } else { | |
1666 | info->num_queues = cdev->num_hwfns; | |
1667 | } | |
1668 | ||
7b7e70f9 | 1669 | if (IS_QED_SRIOV(cdev)) { |
25eb8d46 YM |
1670 | max_vf_vlan_filters = cdev->p_iov_info->total_vfs * |
1671 | QED_ETH_VF_NUM_VLAN_FILTERS; | |
7b7e70f9 YM |
1672 | max_vf_mac_filters = cdev->p_iov_info->total_vfs * |
1673 | QED_ETH_VF_NUM_MAC_FILTERS; | |
1674 | } | |
1675 | info->num_vlan_filters = RESC_NUM(QED_LEADING_HWFN(cdev), | |
1676 | QED_VLAN) - | |
25eb8d46 | 1677 | max_vf_vlan_filters; |
7b7e70f9 YM |
1678 | info->num_mac_filters = RESC_NUM(QED_LEADING_HWFN(cdev), |
1679 | QED_MAC) - | |
1680 | max_vf_mac_filters; | |
25eb8d46 | 1681 | |
1408cc1f YM |
1682 | ether_addr_copy(info->port_mac, |
1683 | cdev->hwfns[0].hw_info.hw_mac_addr); | |
25c089d7 | 1684 | } else { |
1408cc1f YM |
1685 | qed_vf_get_num_rxqs(QED_LEADING_HWFN(cdev), &info->num_queues); |
1686 | if (cdev->num_hwfns > 1) { | |
1687 | u8 queues = 0; | |
25c089d7 | 1688 | |
1408cc1f YM |
1689 | qed_vf_get_num_rxqs(&cdev->hwfns[1], &queues); |
1690 | info->num_queues += queues; | |
1691 | } | |
1692 | ||
1693 | qed_vf_get_num_vlan_filters(&cdev->hwfns[0], | |
2edbff8d | 1694 | (u8 *)&info->num_vlan_filters); |
b0fca312 MY |
1695 | qed_vf_get_num_mac_filters(&cdev->hwfns[0], |
1696 | (u8 *)&info->num_mac_filters); | |
1408cc1f | 1697 | qed_vf_get_port_mac(&cdev->hwfns[0], info->port_mac); |
d8c2c7e3 YM |
1698 | |
1699 | info->is_legacy = !!cdev->hwfns[0].vf_iov_info->b_pre_fp_hsi; | |
1408cc1f | 1700 | } |
25c089d7 YM |
1701 | |
1702 | qed_fill_dev_info(cdev, &info->common); | |
1703 | ||
1408cc1f YM |
1704 | if (IS_VF(cdev)) |
1705 | memset(info->common.hw_mac, 0, ETH_ALEN); | |
1706 | ||
25c089d7 YM |
1707 | return 0; |
1708 | } | |
1709 | ||
cc875c2e | 1710 | static void qed_register_eth_ops(struct qed_dev *cdev, |
1408cc1f | 1711 | struct qed_eth_cb_ops *ops, void *cookie) |
cc875c2e | 1712 | { |
1408cc1f YM |
1713 | cdev->protocol_ops.eth = ops; |
1714 | cdev->ops_cookie = cookie; | |
1715 | ||
1716 | /* For VF, we start bulletin reading */ | |
1717 | if (IS_VF(cdev)) | |
1718 | qed_vf_start_iov_wq(cdev); | |
cc875c2e YM |
1719 | } |
1720 | ||
eff16960 YM |
1721 | static bool qed_check_mac(struct qed_dev *cdev, u8 *mac) |
1722 | { | |
1723 | if (IS_PF(cdev)) | |
1724 | return true; | |
1725 | ||
1726 | return qed_vf_check_mac(&cdev->hwfns[0], mac); | |
1727 | } | |
1728 | ||
cee4d264 | 1729 | static int qed_start_vport(struct qed_dev *cdev, |
088c8618 | 1730 | struct qed_start_vport_params *params) |
cee4d264 MC |
1731 | { |
1732 | int rc, i; | |
1733 | ||
1734 | for_each_hwfn(cdev, i) { | |
088c8618 | 1735 | struct qed_sp_vport_start_params start = { 0 }; |
cee4d264 MC |
1736 | struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; |
1737 | ||
088c8618 MC |
1738 | start.tpa_mode = params->gro_enable ? QED_TPA_MODE_GRO : |
1739 | QED_TPA_MODE_NONE; | |
1740 | start.remove_inner_vlan = params->remove_inner_vlan; | |
08feecd7 | 1741 | start.only_untagged = true; /* untagged only */ |
088c8618 MC |
1742 | start.drop_ttl0 = params->drop_ttl0; |
1743 | start.opaque_fid = p_hwfn->hw_info.opaque_fid; | |
1744 | start.concrete_fid = p_hwfn->hw_info.concrete_fid; | |
1745 | start.vport_id = params->vport_id; | |
1746 | start.max_buffers_per_cqe = 16; | |
1747 | start.mtu = params->mtu; | |
1748 | ||
1749 | rc = qed_sp_vport_start(p_hwfn, &start); | |
cee4d264 MC |
1750 | if (rc) { |
1751 | DP_ERR(cdev, "Failed to start VPORT\n"); | |
1752 | return rc; | |
1753 | } | |
1754 | ||
1755 | qed_hw_start_fastpath(p_hwfn); | |
1756 | ||
1757 | DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP), | |
1758 | "Started V-PORT %d with MTU %d\n", | |
088c8618 | 1759 | start.vport_id, start.mtu); |
cee4d264 MC |
1760 | } |
1761 | ||
a0d26d5a YM |
1762 | if (params->clear_stats) |
1763 | qed_reset_vport_stats(cdev); | |
9df2ed04 | 1764 | |
cee4d264 MC |
1765 | return 0; |
1766 | } | |
1767 | ||
1a635e48 | 1768 | static int qed_stop_vport(struct qed_dev *cdev, u8 vport_id) |
cee4d264 MC |
1769 | { |
1770 | int rc, i; | |
1771 | ||
1772 | for_each_hwfn(cdev, i) { | |
1773 | struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; | |
1774 | ||
1775 | rc = qed_sp_vport_stop(p_hwfn, | |
1a635e48 | 1776 | p_hwfn->hw_info.opaque_fid, vport_id); |
cee4d264 MC |
1777 | |
1778 | if (rc) { | |
1779 | DP_ERR(cdev, "Failed to stop VPORT\n"); | |
1780 | return rc; | |
1781 | } | |
1782 | } | |
1783 | return 0; | |
1784 | } | |
1785 | ||
1786 | static int qed_update_vport(struct qed_dev *cdev, | |
1787 | struct qed_update_vport_params *params) | |
1788 | { | |
1789 | struct qed_sp_vport_update_params sp_params; | |
1790 | struct qed_rss_params sp_rss_params; | |
1791 | int rc, i; | |
1792 | ||
1793 | if (!cdev) | |
1794 | return -ENODEV; | |
1795 | ||
1796 | memset(&sp_params, 0, sizeof(sp_params)); | |
1797 | memset(&sp_rss_params, 0, sizeof(sp_rss_params)); | |
1798 | ||
1799 | /* Translate protocol params into sp params */ | |
1800 | sp_params.vport_id = params->vport_id; | |
1a635e48 YM |
1801 | sp_params.update_vport_active_rx_flg = params->update_vport_active_flg; |
1802 | sp_params.update_vport_active_tx_flg = params->update_vport_active_flg; | |
cee4d264 MC |
1803 | sp_params.vport_active_rx_flg = params->vport_active_flg; |
1804 | sp_params.vport_active_tx_flg = params->vport_active_flg; | |
831bfb0e YM |
1805 | sp_params.update_tx_switching_flg = params->update_tx_switching_flg; |
1806 | sp_params.tx_switching_flg = params->tx_switching_flg; | |
3f9b4a69 YM |
1807 | sp_params.accept_any_vlan = params->accept_any_vlan; |
1808 | sp_params.update_accept_any_vlan_flg = | |
1809 | params->update_accept_any_vlan_flg; | |
cee4d264 MC |
1810 | |
1811 | /* RSS - is a bit tricky, since upper-layer isn't familiar with hwfns. | |
1812 | * We need to re-fix the rss values per engine for CMT. | |
1813 | */ | |
1814 | if (cdev->num_hwfns > 1 && params->update_rss_flg) { | |
1a635e48 | 1815 | struct qed_update_vport_rss_params *rss = ¶ms->rss_params; |
cee4d264 MC |
1816 | int k, max = 0; |
1817 | ||
1818 | /* Find largest entry, since it's possible RSS needs to | |
1819 | * be disabled [in case only 1 queue per-hwfn] | |
1820 | */ | |
1821 | for (k = 0; k < QED_RSS_IND_TABLE_SIZE; k++) | |
1822 | max = (max > rss->rss_ind_table[k]) ? | |
1823 | max : rss->rss_ind_table[k]; | |
1824 | ||
1825 | /* Either fix RSS values or disable RSS */ | |
1826 | if (cdev->num_hwfns < max + 1) { | |
1827 | int divisor = (max + cdev->num_hwfns - 1) / | |
1828 | cdev->num_hwfns; | |
1829 | ||
1830 | DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP), | |
1831 | "CMT - fixing RSS values (modulo %02x)\n", | |
1832 | divisor); | |
1833 | ||
1834 | for (k = 0; k < QED_RSS_IND_TABLE_SIZE; k++) | |
1835 | rss->rss_ind_table[k] = | |
1836 | rss->rss_ind_table[k] % divisor; | |
1837 | } else { | |
1838 | DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP), | |
1839 | "CMT - 1 queue per-hwfn; Disabling RSS\n"); | |
1840 | params->update_rss_flg = 0; | |
1841 | } | |
1842 | } | |
1843 | ||
1844 | /* Now, update the RSS configuration for actual configuration */ | |
1845 | if (params->update_rss_flg) { | |
1846 | sp_rss_params.update_rss_config = 1; | |
1847 | sp_rss_params.rss_enable = 1; | |
1848 | sp_rss_params.update_rss_capabilities = 1; | |
1849 | sp_rss_params.update_rss_ind_table = 1; | |
1850 | sp_rss_params.update_rss_key = 1; | |
8c5ebd0c | 1851 | sp_rss_params.rss_caps = params->rss_params.rss_caps; |
cee4d264 MC |
1852 | sp_rss_params.rss_table_size_log = 7; /* 2^7 = 128 */ |
1853 | memcpy(sp_rss_params.rss_ind_table, | |
1854 | params->rss_params.rss_ind_table, | |
1855 | QED_RSS_IND_TABLE_SIZE * sizeof(u16)); | |
1856 | memcpy(sp_rss_params.rss_key, params->rss_params.rss_key, | |
1857 | QED_RSS_KEY_SIZE * sizeof(u32)); | |
83aeb933 | 1858 | sp_params.rss_params = &sp_rss_params; |
cee4d264 | 1859 | } |
cee4d264 MC |
1860 | |
1861 | for_each_hwfn(cdev, i) { | |
1862 | struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; | |
1863 | ||
1864 | sp_params.opaque_fid = p_hwfn->hw_info.opaque_fid; | |
1865 | rc = qed_sp_vport_update(p_hwfn, &sp_params, | |
1866 | QED_SPQ_MODE_EBLOCK, | |
1867 | NULL); | |
1868 | if (rc) { | |
1869 | DP_ERR(cdev, "Failed to update VPORT\n"); | |
1870 | return rc; | |
1871 | } | |
1872 | ||
1873 | DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP), | |
1874 | "Updated V-PORT %d: active_flag %d [update %d]\n", | |
1875 | params->vport_id, params->vport_active_flg, | |
1876 | params->update_vport_active_flg); | |
1877 | } | |
1878 | ||
1879 | return 0; | |
1880 | } | |
1881 | ||
1882 | static int qed_start_rxq(struct qed_dev *cdev, | |
1883 | struct qed_queue_start_common_params *params, | |
1884 | u16 bd_max_bytes, | |
1885 | dma_addr_t bd_chain_phys_addr, | |
1886 | dma_addr_t cqe_pbl_addr, | |
1887 | u16 cqe_pbl_size, | |
1888 | void __iomem **pp_prod) | |
1889 | { | |
cee4d264 | 1890 | struct qed_hwfn *p_hwfn; |
1a635e48 | 1891 | int rc, hwfn_index; |
cee4d264 MC |
1892 | |
1893 | hwfn_index = params->rss_id % cdev->num_hwfns; | |
1894 | p_hwfn = &cdev->hwfns[hwfn_index]; | |
1895 | ||
1896 | /* Fix queue ID in 100g mode */ | |
1897 | params->queue_id /= cdev->num_hwfns; | |
1898 | ||
1899 | rc = qed_sp_eth_rx_queue_start(p_hwfn, | |
1900 | p_hwfn->hw_info.opaque_fid, | |
1901 | params, | |
1902 | bd_max_bytes, | |
1903 | bd_chain_phys_addr, | |
1904 | cqe_pbl_addr, | |
1905 | cqe_pbl_size, | |
1906 | pp_prod); | |
1907 | ||
1908 | if (rc) { | |
1909 | DP_ERR(cdev, "Failed to start RXQ#%d\n", params->queue_id); | |
1910 | return rc; | |
1911 | } | |
1912 | ||
1913 | DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP), | |
1914 | "Started RX-Q %d [rss %d] on V-PORT %d and SB %d\n", | |
1915 | params->queue_id, params->rss_id, params->vport_id, | |
1916 | params->sb); | |
1917 | ||
1918 | return 0; | |
1919 | } | |
1920 | ||
1921 | static int qed_stop_rxq(struct qed_dev *cdev, | |
1922 | struct qed_stop_rxq_params *params) | |
1923 | { | |
1924 | int rc, hwfn_index; | |
1925 | struct qed_hwfn *p_hwfn; | |
1926 | ||
1927 | hwfn_index = params->rss_id % cdev->num_hwfns; | |
1928 | p_hwfn = &cdev->hwfns[hwfn_index]; | |
1929 | ||
1930 | rc = qed_sp_eth_rx_queue_stop(p_hwfn, | |
1931 | params->rx_queue_id / cdev->num_hwfns, | |
1a635e48 | 1932 | params->eq_completion_only, false); |
cee4d264 MC |
1933 | if (rc) { |
1934 | DP_ERR(cdev, "Failed to stop RXQ#%d\n", params->rx_queue_id); | |
1935 | return rc; | |
1936 | } | |
1937 | ||
1938 | return 0; | |
1939 | } | |
1940 | ||
1941 | static int qed_start_txq(struct qed_dev *cdev, | |
1942 | struct qed_queue_start_common_params *p_params, | |
1943 | dma_addr_t pbl_addr, | |
1944 | u16 pbl_size, | |
1945 | void __iomem **pp_doorbell) | |
1946 | { | |
1947 | struct qed_hwfn *p_hwfn; | |
1948 | int rc, hwfn_index; | |
1949 | ||
1950 | hwfn_index = p_params->rss_id % cdev->num_hwfns; | |
1951 | p_hwfn = &cdev->hwfns[hwfn_index]; | |
1952 | ||
1953 | /* Fix queue ID in 100g mode */ | |
1954 | p_params->queue_id /= cdev->num_hwfns; | |
1955 | ||
1956 | rc = qed_sp_eth_tx_queue_start(p_hwfn, | |
1957 | p_hwfn->hw_info.opaque_fid, | |
1958 | p_params, | |
1959 | pbl_addr, | |
1960 | pbl_size, | |
1961 | pp_doorbell); | |
1962 | ||
1963 | if (rc) { | |
1964 | DP_ERR(cdev, "Failed to start TXQ#%d\n", p_params->queue_id); | |
1965 | return rc; | |
1966 | } | |
1967 | ||
1968 | DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP), | |
1969 | "Started TX-Q %d [rss %d] on V-PORT %d and SB %d\n", | |
1970 | p_params->queue_id, p_params->rss_id, p_params->vport_id, | |
1971 | p_params->sb); | |
1972 | ||
1973 | return 0; | |
1974 | } | |
1975 | ||
1976 | #define QED_HW_STOP_RETRY_LIMIT (10) | |
1977 | static int qed_fastpath_stop(struct qed_dev *cdev) | |
1978 | { | |
1979 | qed_hw_stop_fastpath(cdev); | |
1980 | ||
1981 | return 0; | |
1982 | } | |
1983 | ||
1984 | static int qed_stop_txq(struct qed_dev *cdev, | |
1985 | struct qed_stop_txq_params *params) | |
1986 | { | |
1987 | struct qed_hwfn *p_hwfn; | |
1988 | int rc, hwfn_index; | |
1989 | ||
1990 | hwfn_index = params->rss_id % cdev->num_hwfns; | |
1991 | p_hwfn = &cdev->hwfns[hwfn_index]; | |
1992 | ||
1993 | rc = qed_sp_eth_tx_queue_stop(p_hwfn, | |
1994 | params->tx_queue_id / cdev->num_hwfns); | |
1995 | if (rc) { | |
1996 | DP_ERR(cdev, "Failed to stop TXQ#%d\n", params->tx_queue_id); | |
1997 | return rc; | |
1998 | } | |
1999 | ||
2000 | return 0; | |
2001 | } | |
2002 | ||
464f6645 MC |
2003 | static int qed_tunn_configure(struct qed_dev *cdev, |
2004 | struct qed_tunn_params *tunn_params) | |
2005 | { | |
2006 | struct qed_tunn_update_params tunn_info; | |
2007 | int i, rc; | |
2008 | ||
1408cc1f YM |
2009 | if (IS_VF(cdev)) |
2010 | return 0; | |
2011 | ||
464f6645 MC |
2012 | memset(&tunn_info, 0, sizeof(tunn_info)); |
2013 | if (tunn_params->update_vxlan_port == 1) { | |
2014 | tunn_info.update_vxlan_udp_port = 1; | |
2015 | tunn_info.vxlan_udp_port = tunn_params->vxlan_port; | |
2016 | } | |
2017 | ||
2018 | if (tunn_params->update_geneve_port == 1) { | |
2019 | tunn_info.update_geneve_udp_port = 1; | |
2020 | tunn_info.geneve_udp_port = tunn_params->geneve_port; | |
2021 | } | |
2022 | ||
2023 | for_each_hwfn(cdev, i) { | |
2024 | struct qed_hwfn *hwfn = &cdev->hwfns[i]; | |
2025 | ||
2026 | rc = qed_sp_pf_update_tunn_cfg(hwfn, &tunn_info, | |
2027 | QED_SPQ_MODE_EBLOCK, NULL); | |
2028 | ||
2029 | if (rc) | |
2030 | return rc; | |
2031 | } | |
2032 | ||
2033 | return 0; | |
2034 | } | |
2035 | ||
cee4d264 MC |
2036 | static int qed_configure_filter_rx_mode(struct qed_dev *cdev, |
2037 | enum qed_filter_rx_mode_type type) | |
2038 | { | |
2039 | struct qed_filter_accept_flags accept_flags; | |
2040 | ||
2041 | memset(&accept_flags, 0, sizeof(accept_flags)); | |
2042 | ||
1a635e48 YM |
2043 | accept_flags.update_rx_mode_config = 1; |
2044 | accept_flags.update_tx_mode_config = 1; | |
2045 | accept_flags.rx_accept_filter = QED_ACCEPT_UCAST_MATCHED | | |
2046 | QED_ACCEPT_MCAST_MATCHED | | |
2047 | QED_ACCEPT_BCAST; | |
cee4d264 MC |
2048 | accept_flags.tx_accept_filter = QED_ACCEPT_UCAST_MATCHED | |
2049 | QED_ACCEPT_MCAST_MATCHED | | |
2050 | QED_ACCEPT_BCAST; | |
2051 | ||
2052 | if (type == QED_FILTER_RX_MODE_TYPE_PROMISC) | |
2053 | accept_flags.rx_accept_filter |= QED_ACCEPT_UCAST_UNMATCHED | | |
2054 | QED_ACCEPT_MCAST_UNMATCHED; | |
2055 | else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC) | |
2056 | accept_flags.rx_accept_filter |= QED_ACCEPT_MCAST_UNMATCHED; | |
2057 | ||
3f9b4a69 | 2058 | return qed_filter_accept_cmd(cdev, 0, accept_flags, false, false, |
cee4d264 MC |
2059 | QED_SPQ_MODE_CB, NULL); |
2060 | } | |
2061 | ||
2062 | static int qed_configure_filter_ucast(struct qed_dev *cdev, | |
2063 | struct qed_filter_ucast_params *params) | |
2064 | { | |
2065 | struct qed_filter_ucast ucast; | |
2066 | ||
2067 | if (!params->vlan_valid && !params->mac_valid) { | |
1a635e48 YM |
2068 | DP_NOTICE(cdev, |
2069 | "Tried configuring a unicast filter, but both MAC and VLAN are not set\n"); | |
cee4d264 MC |
2070 | return -EINVAL; |
2071 | } | |
2072 | ||
2073 | memset(&ucast, 0, sizeof(ucast)); | |
2074 | switch (params->type) { | |
2075 | case QED_FILTER_XCAST_TYPE_ADD: | |
2076 | ucast.opcode = QED_FILTER_ADD; | |
2077 | break; | |
2078 | case QED_FILTER_XCAST_TYPE_DEL: | |
2079 | ucast.opcode = QED_FILTER_REMOVE; | |
2080 | break; | |
2081 | case QED_FILTER_XCAST_TYPE_REPLACE: | |
2082 | ucast.opcode = QED_FILTER_REPLACE; | |
2083 | break; | |
2084 | default: | |
2085 | DP_NOTICE(cdev, "Unknown unicast filter type %d\n", | |
2086 | params->type); | |
2087 | } | |
2088 | ||
2089 | if (params->vlan_valid && params->mac_valid) { | |
2090 | ucast.type = QED_FILTER_MAC_VLAN; | |
2091 | ether_addr_copy(ucast.mac, params->mac); | |
2092 | ucast.vlan = params->vlan; | |
2093 | } else if (params->mac_valid) { | |
2094 | ucast.type = QED_FILTER_MAC; | |
2095 | ether_addr_copy(ucast.mac, params->mac); | |
2096 | } else { | |
2097 | ucast.type = QED_FILTER_VLAN; | |
2098 | ucast.vlan = params->vlan; | |
2099 | } | |
2100 | ||
2101 | ucast.is_rx_filter = true; | |
2102 | ucast.is_tx_filter = true; | |
2103 | ||
2104 | return qed_filter_ucast_cmd(cdev, &ucast, QED_SPQ_MODE_CB, NULL); | |
2105 | } | |
2106 | ||
2107 | static int qed_configure_filter_mcast(struct qed_dev *cdev, | |
2108 | struct qed_filter_mcast_params *params) | |
2109 | { | |
2110 | struct qed_filter_mcast mcast; | |
2111 | int i; | |
2112 | ||
2113 | memset(&mcast, 0, sizeof(mcast)); | |
2114 | switch (params->type) { | |
2115 | case QED_FILTER_XCAST_TYPE_ADD: | |
2116 | mcast.opcode = QED_FILTER_ADD; | |
2117 | break; | |
2118 | case QED_FILTER_XCAST_TYPE_DEL: | |
2119 | mcast.opcode = QED_FILTER_REMOVE; | |
2120 | break; | |
2121 | default: | |
2122 | DP_NOTICE(cdev, "Unknown multicast filter type %d\n", | |
2123 | params->type); | |
2124 | } | |
2125 | ||
2126 | mcast.num_mc_addrs = params->num; | |
2127 | for (i = 0; i < mcast.num_mc_addrs; i++) | |
2128 | ether_addr_copy(mcast.mac[i], params->mac[i]); | |
2129 | ||
1a635e48 | 2130 | return qed_filter_mcast_cmd(cdev, &mcast, QED_SPQ_MODE_CB, NULL); |
cee4d264 MC |
2131 | } |
2132 | ||
2133 | static int qed_configure_filter(struct qed_dev *cdev, | |
2134 | struct qed_filter_params *params) | |
2135 | { | |
2136 | enum qed_filter_rx_mode_type accept_flags; | |
2137 | ||
2138 | switch (params->type) { | |
2139 | case QED_FILTER_TYPE_UCAST: | |
2140 | return qed_configure_filter_ucast(cdev, ¶ms->filter.ucast); | |
2141 | case QED_FILTER_TYPE_MCAST: | |
2142 | return qed_configure_filter_mcast(cdev, ¶ms->filter.mcast); | |
2143 | case QED_FILTER_TYPE_RX_MODE: | |
2144 | accept_flags = params->filter.accept_flags; | |
2145 | return qed_configure_filter_rx_mode(cdev, accept_flags); | |
2146 | default: | |
1a635e48 | 2147 | DP_NOTICE(cdev, "Unknown filter type %d\n", (int)params->type); |
cee4d264 MC |
2148 | return -EINVAL; |
2149 | } | |
2150 | } | |
2151 | ||
2152 | static int qed_fp_cqe_completion(struct qed_dev *dev, | |
1a635e48 | 2153 | u8 rss_id, struct eth_slow_path_rx_cqe *cqe) |
cee4d264 MC |
2154 | { |
2155 | return qed_eth_cqe_completion(&dev->hwfns[rss_id % dev->num_hwfns], | |
2156 | cqe); | |
2157 | } | |
2158 | ||
0b55e27d YM |
2159 | #ifdef CONFIG_QED_SRIOV |
2160 | extern const struct qed_iov_hv_ops qed_iov_ops_pass; | |
2161 | #endif | |
2162 | ||
a1d8d8a5 SRK |
2163 | #ifdef CONFIG_DCB |
2164 | extern const struct qed_eth_dcbnl_ops qed_dcbnl_ops_pass; | |
2165 | #endif | |
2166 | ||
25c089d7 YM |
2167 | static const struct qed_eth_ops qed_eth_ops_pass = { |
2168 | .common = &qed_common_ops_pass, | |
0b55e27d YM |
2169 | #ifdef CONFIG_QED_SRIOV |
2170 | .iov = &qed_iov_ops_pass, | |
a1d8d8a5 SRK |
2171 | #endif |
2172 | #ifdef CONFIG_DCB | |
2173 | .dcb = &qed_dcbnl_ops_pass, | |
0b55e27d | 2174 | #endif |
25c089d7 | 2175 | .fill_dev_info = &qed_fill_eth_dev_info, |
cc875c2e | 2176 | .register_ops = &qed_register_eth_ops, |
eff16960 | 2177 | .check_mac = &qed_check_mac, |
cee4d264 MC |
2178 | .vport_start = &qed_start_vport, |
2179 | .vport_stop = &qed_stop_vport, | |
2180 | .vport_update = &qed_update_vport, | |
2181 | .q_rx_start = &qed_start_rxq, | |
2182 | .q_rx_stop = &qed_stop_rxq, | |
2183 | .q_tx_start = &qed_start_txq, | |
2184 | .q_tx_stop = &qed_stop_txq, | |
2185 | .filter_config = &qed_configure_filter, | |
2186 | .fastpath_stop = &qed_fastpath_stop, | |
2187 | .eth_cqe_completion = &qed_fp_cqe_completion, | |
9df2ed04 | 2188 | .get_vport_stats = &qed_get_vport_stats, |
464f6645 | 2189 | .tunn_config = &qed_tunn_configure, |
25c089d7 YM |
2190 | }; |
2191 | ||
95114344 | 2192 | const struct qed_eth_ops *qed_get_eth_ops(void) |
25c089d7 | 2193 | { |
25c089d7 YM |
2194 | return &qed_eth_ops_pass; |
2195 | } | |
2196 | EXPORT_SYMBOL(qed_get_eth_ops); | |
2197 | ||
2198 | void qed_put_eth_ops(void) | |
2199 | { | |
2200 | /* TODO - reference count for module? */ | |
2201 | } | |
2202 | EXPORT_SYMBOL(qed_put_eth_ops); |