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qed: Align DP_ERR style with other DP macros
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / qlogic / qed / qed_l2.c
CommitLineData
25c089d7 1/* QLogic qed NIC Driver
e8f1cb50 2 * Copyright (c) 2015-2017 QLogic Corporation
25c089d7 3 *
e8f1cb50
MY		 4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
25c089d7
YM		 31 */
32
33#include <linux/types.h>
34#include <asm/byteorder.h>
35#include <asm/param.h>
36#include <linux/delay.h>
37#include <linux/dma-mapping.h>
38#include <linux/etherdevice.h>
39#include <linux/interrupt.h>
40#include <linux/kernel.h>
41#include <linux/module.h>
42#include <linux/pci.h>
43#include <linux/slab.h>
44#include <linux/stddef.h>
45#include <linux/string.h>
25c089d7
YM		 46#include <linux/workqueue.h>
47#include <linux/bitops.h>
48#include <linux/bug.h>
3da7a37a 49#include <linux/vmalloc.h>
25c089d7
YM		 50#include "qed.h"
51#include <linux/qed/qed_chain.h>
52#include "qed_cxt.h"
53#include "qed_dev_api.h"
54#include <linux/qed/qed_eth_if.h>
55#include "qed_hsi.h"
56#include "qed_hw.h"
57#include "qed_int.h"
dacd88d6 58#include "qed_l2.h"
86622ee7 59#include "qed_mcp.h"
25c089d7
YM		 60#include "qed_reg_addr.h"
61#include "qed_sp.h"
1408cc1f 62#include "qed_sriov.h"
25c089d7 63
088c8618 64
cee4d264
MC		 65#define QED_MAX_SGES_NUM 16
66#define CRC32_POLY 0x1edc6f41
67
3da7a37a
MY		 68void qed_eth_queue_cid_release(struct qed_hwfn *p_hwfn,
69 struct qed_queue_cid *p_cid)
70{
71 /* VFs' CIDs are 0-based in PF-view, and uninitialized on VF */
72 if (!p_cid->is_vf && IS_PF(p_hwfn->cdev))
73 qed_cxt_release_cid(p_hwfn, p_cid->cid);
74 vfree(p_cid);
75}
76
77/* The internal is only meant to be directly called by PFs initializeing CIDs
78 * for their VFs.
79 */
80struct qed_queue_cid *
81_qed_eth_queue_to_cid(struct qed_hwfn *p_hwfn,
82 u16 opaque_fid,
83 u32 cid,
84 u8 vf_qid,
85 struct qed_queue_start_common_params *p_params)
86{
87 bool b_is_same = (p_hwfn->hw_info.opaque_fid == opaque_fid);
88 struct qed_queue_cid *p_cid;
89 int rc;
90
91 p_cid = vmalloc(sizeof(*p_cid));
92 if (!p_cid)
93 return NULL;
94 memset(p_cid, 0, sizeof(*p_cid));
95
96 p_cid->opaque_fid = opaque_fid;
97 p_cid->cid = cid;
98 p_cid->vf_qid = vf_qid;
99 p_cid->rel = *p_params;
f29ffdb6 100 p_cid->p_owner = p_hwfn;
3da7a37a
MY		 101
102 /* Don't try calculating the absolute indices for VFs */
103 if (IS_VF(p_hwfn->cdev)) {
104 p_cid->abs = p_cid->rel;
105 goto out;
106 }
107
108 /* Calculate the engine-absolute indices of the resources.
109 * This would guarantee they're valid later on.
110 * In some cases [SBs] we already have the right values.
111 */
112 rc = qed_fw_vport(p_hwfn, p_cid->rel.vport_id, &p_cid->abs.vport_id);
113 if (rc)
114 goto fail;
115
116 rc = qed_fw_l2_queue(p_hwfn, p_cid->rel.queue_id, &p_cid->abs.queue_id);
117 if (rc)
118 goto fail;
119
120 /* In case of a PF configuring its VF's queues, the stats-id is already
121 * absolute [since there's a single index that's suitable per-VF].
122 */
123 if (b_is_same) {
124 rc = qed_fw_vport(p_hwfn, p_cid->rel.stats_id,
125 &p_cid->abs.stats_id);
126 if (rc)
127 goto fail;
128 } else {
129 p_cid->abs.stats_id = p_cid->rel.stats_id;
130 }
131
132 /* SBs relevant information was already provided as absolute */
133 p_cid->abs.sb = p_cid->rel.sb;
134 p_cid->abs.sb_idx = p_cid->rel.sb_idx;
135
136 /* This is tricky - we're actually interested in whehter this is a PF
137 * entry meant for the VF.
138 */
139 if (!b_is_same)
140 p_cid->is_vf = true;
141out:
142 DP_VERBOSE(p_hwfn,
143 QED_MSG_SP,
144 "opaque_fid: %04x CID %08x vport %02x [%02x] qzone %04x [%04x] stats %02x [%02x] SB %04x PI %02x\n",
145 p_cid->opaque_fid,
146 p_cid->cid,
147 p_cid->rel.vport_id,
148 p_cid->abs.vport_id,
149 p_cid->rel.queue_id,
150 p_cid->abs.queue_id,
151 p_cid->rel.stats_id,
152 p_cid->abs.stats_id, p_cid->abs.sb, p_cid->abs.sb_idx);
153
154 return p_cid;
155
156fail:
157 vfree(p_cid);
158 return NULL;
159}
160
161static struct qed_queue_cid *qed_eth_queue_to_cid(struct qed_hwfn *p_hwfn,
162 u16 opaque_fid, struct
163 qed_queue_start_common_params
164 *p_params)
165{
166 struct qed_queue_cid *p_cid;
167 u32 cid = 0;
168
169 /* Get a unique firmware CID for this queue, in case it's a PF.
170 * VF's don't need a CID as the queue configuration will be done
171 * by PF.
172 */
173 if (IS_PF(p_hwfn->cdev)) {
174 if (qed_cxt_acquire_cid(p_hwfn, PROTOCOLID_ETH, &cid)) {
175 DP_NOTICE(p_hwfn, "Failed to acquire cid\n");
176 return NULL;
177 }
178 }
179
180 p_cid = _qed_eth_queue_to_cid(p_hwfn, opaque_fid, cid, 0, p_params);
181 if (!p_cid && IS_PF(p_hwfn->cdev))
182 qed_cxt_release_cid(p_hwfn, cid);
183
184 return p_cid;
185}
186
dacd88d6
YM		 187int qed_sp_eth_vport_start(struct qed_hwfn *p_hwfn,
188 struct qed_sp_vport_start_params *p_params)
cee4d264 189{
cee4d264
MC		 190 struct vport_start_ramrod_data *p_ramrod = NULL;
191 struct qed_spq_entry *p_ent = NULL;
06f56b81 192 struct qed_sp_init_data init_data;
dacd88d6 193 u8 abs_vport_id = 0;
cee4d264
MC		 194 int rc = -EINVAL;
195 u16 rx_mode = 0;
cee4d264 196
088c8618 197 rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
1a635e48 198 if (rc)
cee4d264
MC		 199 return rc;
200
06f56b81
YM		 201 memset(&init_data, 0, sizeof(init_data));
202 init_data.cid = qed_spq_get_cid(p_hwfn);
088c8618 203 init_data.opaque_fid = p_params->opaque_fid;
06f56b81 204 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
cee4d264
MC		 205
206 rc = qed_sp_init_request(p_hwfn, &p_ent,
cee4d264 207 ETH_RAMROD_VPORT_START,
06f56b81 208 PROTOCOLID_ETH, &init_data);
cee4d264
MC		 209 if (rc)
210 return rc;
211
212 p_ramrod = &p_ent->ramrod.vport_start;
213 p_ramrod->vport_id = abs_vport_id;
214
088c8618 215 p_ramrod->mtu = cpu_to_le16(p_params->mtu);
c78c70fa 216 p_ramrod->handle_ptp_pkts = p_params->handle_ptp_pkts;
088c8618
MC		 217 p_ramrod->inner_vlan_removal_en = p_params->remove_inner_vlan;
218 p_ramrod->drop_ttl0_en = p_params->drop_ttl0;
e6bd8923 219 p_ramrod->untagged = p_params->only_untagged;
cee4d264
MC		 220
221 SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_UCAST_DROP_ALL, 1);
222 SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_MCAST_DROP_ALL, 1);
223
224 p_ramrod->rx_mode.state = cpu_to_le16(rx_mode);
225
226 /* TPA related fields */
1a635e48 227 memset(&p_ramrod->tpa_param, 0, sizeof(struct eth_vport_tpa_param));
cee4d264 228
088c8618
MC		 229 p_ramrod->tpa_param.max_buff_num = p_params->max_buffers_per_cqe;
230
231 switch (p_params->tpa_mode) {
232 case QED_TPA_MODE_GRO:
233 p_ramrod->tpa_param.tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
234 p_ramrod->tpa_param.tpa_max_size = (u16)-1;
235 p_ramrod->tpa_param.tpa_min_size_to_cont = p_params->mtu / 2;
236 p_ramrod->tpa_param.tpa_min_size_to_start = p_params->mtu / 2;
237 p_ramrod->tpa_param.tpa_ipv4_en_flg = 1;
238 p_ramrod->tpa_param.tpa_ipv6_en_flg = 1;
239 p_ramrod->tpa_param.tpa_pkt_split_flg = 1;
240 p_ramrod->tpa_param.tpa_gro_consistent_flg = 1;
241 break;
242 default:
243 break;
244 }
245
831bfb0e
YM		 246 p_ramrod->tx_switching_en = p_params->tx_switching;
247
11a85d75
YM		 248 p_ramrod->ctl_frame_mac_check_en = !!p_params->check_mac;
249 p_ramrod->ctl_frame_ethtype_check_en = !!p_params->check_ethtype;
250
cee4d264
MC		 251 /* Software Function ID in hwfn (PFs are 0 - 15, VFs are 16 - 135) */
252 p_ramrod->sw_fid = qed_concrete_to_sw_fid(p_hwfn->cdev,
088c8618 253 p_params->concrete_fid);
cee4d264
MC		 254
255 return qed_spq_post(p_hwfn, p_ent, NULL);
256}
257
ba56947a
BX		 258static int qed_sp_vport_start(struct qed_hwfn *p_hwfn,
259 struct qed_sp_vport_start_params *p_params)
dacd88d6
YM		 260{
261 if (IS_VF(p_hwfn->cdev)) {
262 return qed_vf_pf_vport_start(p_hwfn, p_params->vport_id,
263 p_params->mtu,
264 p_params->remove_inner_vlan,
265 p_params->tpa_mode,
08feecd7
YM		 266 p_params->max_buffers_per_cqe,
267 p_params->only_untagged);
dacd88d6
YM		 268 }
269
270 return qed_sp_eth_vport_start(p_hwfn, p_params);
271}
272
cee4d264
MC		 273static int
274qed_sp_vport_update_rss(struct qed_hwfn *p_hwfn,
275 struct vport_update_ramrod_data *p_ramrod,
f29ffdb6 276 struct qed_rss_params *p_rss)
cee4d264 277{
f29ffdb6
MY		 278 struct eth_vport_rss_config *p_config;
279 u16 capabilities = 0;
280 int i, table_size;
281 int rc = 0;
cee4d264 282
f29ffdb6 283 if (!p_rss) {
cee4d264
MC		 284 p_ramrod->common.update_rss_flg = 0;
285 return rc;
286 }
f29ffdb6 287 p_config = &p_ramrod->rss_config;
cee4d264 288
f29ffdb6 289 BUILD_BUG_ON(QED_RSS_IND_TABLE_SIZE != ETH_RSS_IND_TABLE_ENTRIES_NUM);
cee4d264 290
f29ffdb6 291 rc = qed_fw_rss_eng(p_hwfn, p_rss->rss_eng_id, &p_config->rss_id);
cee4d264
MC		 292 if (rc)
293 return rc;
294
f29ffdb6
MY		 295 p_ramrod->common.update_rss_flg = p_rss->update_rss_config;
296 p_config->update_rss_capabilities = p_rss->update_rss_capabilities;
297 p_config->update_rss_ind_table = p_rss->update_rss_ind_table;
298 p_config->update_rss_key = p_rss->update_rss_key;
cee4d264 299
f29ffdb6
MY		 300 p_config->rss_mode = p_rss->rss_enable ?
301 ETH_VPORT_RSS_MODE_REGULAR :
302 ETH_VPORT_RSS_MODE_DISABLED;
cee4d264
MC		 303
304 SET_FIELD(capabilities,
305 ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY,
f29ffdb6 306 !!(p_rss->rss_caps & QED_RSS_IPV4));
cee4d264
MC		 307 SET_FIELD(capabilities,
308 ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY,
f29ffdb6 309 !!(p_rss->rss_caps & QED_RSS_IPV6));
cee4d264
MC		 310 SET_FIELD(capabilities,
311 ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY,
f29ffdb6 312 !!(p_rss->rss_caps & QED_RSS_IPV4_TCP));
cee4d264
MC		 313 SET_FIELD(capabilities,
314 ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY,
f29ffdb6 315 !!(p_rss->rss_caps & QED_RSS_IPV6_TCP));
cee4d264
MC		 316 SET_FIELD(capabilities,
317 ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY,
f29ffdb6 318 !!(p_rss->rss_caps & QED_RSS_IPV4_UDP));
cee4d264
MC		 319 SET_FIELD(capabilities,
320 ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY,
f29ffdb6
MY		 321 !!(p_rss->rss_caps & QED_RSS_IPV6_UDP));
322 p_config->tbl_size = p_rss->rss_table_size_log;
cee4d264 323
f29ffdb6 324 p_config->capabilities = cpu_to_le16(capabilities);
cee4d264
MC		 325
326 DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP,
327 "update rss flag %d, rss_mode = %d, update_caps = %d, capabilities = %d, update_ind = %d, update_rss_key = %d\n",
328 p_ramrod->common.update_rss_flg,
f29ffdb6
MY		 329 p_config->rss_mode,
330 p_config->update_rss_capabilities,
331 p_config->capabilities,
332 p_config->update_rss_ind_table, p_config->update_rss_key);
cee4d264 333
f29ffdb6
MY		 334 table_size = min_t(int, QED_RSS_IND_TABLE_SIZE,
335 1 << p_config->tbl_size);
336 for (i = 0; i < table_size; i++) {
337 struct qed_queue_cid *p_queue = p_rss->rss_ind_table[i];
cee4d264 338
f29ffdb6
MY		 339 if (!p_queue)
340 return -EINVAL;
341
342 p_config->indirection_table[i] =
343 cpu_to_le16(p_queue->abs.queue_id);
344 }
345
346 DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP,
347 "Configured RSS indirection table [%d entries]:\n",
348 table_size);
349 for (i = 0; i < QED_RSS_IND_TABLE_SIZE; i += 0x10) {
350 DP_VERBOSE(p_hwfn,
351 NETIF_MSG_IFUP,
352 "%04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x\n",
353 le16_to_cpu(p_config->indirection_table[i]),
354 le16_to_cpu(p_config->indirection_table[i + 1]),
355 le16_to_cpu(p_config->indirection_table[i + 2]),
356 le16_to_cpu(p_config->indirection_table[i + 3]),
357 le16_to_cpu(p_config->indirection_table[i + 4]),
358 le16_to_cpu(p_config->indirection_table[i + 5]),
359 le16_to_cpu(p_config->indirection_table[i + 6]),
360 le16_to_cpu(p_config->indirection_table[i + 7]),
361 le16_to_cpu(p_config->indirection_table[i + 8]),
362 le16_to_cpu(p_config->indirection_table[i + 9]),
363 le16_to_cpu(p_config->indirection_table[i + 10]),
364 le16_to_cpu(p_config->indirection_table[i + 11]),
365 le16_to_cpu(p_config->indirection_table[i + 12]),
366 le16_to_cpu(p_config->indirection_table[i + 13]),
367 le16_to_cpu(p_config->indirection_table[i + 14]),
368 le16_to_cpu(p_config->indirection_table[i + 15]));
cee4d264
MC		 369 }
370
371 for (i = 0; i < 10; i++)
f29ffdb6 372 p_config->rss_key[i] = cpu_to_le32(p_rss->rss_key[i]);
cee4d264
MC		 373
374 return rc;
375}
376
377static void
378qed_sp_update_accept_mode(struct qed_hwfn *p_hwfn,
379 struct vport_update_ramrod_data *p_ramrod,
380 struct qed_filter_accept_flags accept_flags)
381{
382 p_ramrod->common.update_rx_mode_flg =
383 accept_flags.update_rx_mode_config;
384
385 p_ramrod->common.update_tx_mode_flg =
386 accept_flags.update_tx_mode_config;
387
388 /* Set Rx mode accept flags */
389 if (p_ramrod->common.update_rx_mode_flg) {
390 u8 accept_filter = accept_flags.rx_accept_filter;
391 u16 state = 0;
392
393 SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_DROP_ALL,
394 !(!!(accept_filter & QED_ACCEPT_UCAST_MATCHED) ||
395 !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED)));
396
397 SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED,
398 !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED));
399
400 SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_DROP_ALL,
401 !(!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) ||
402 !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED)));
403
404 SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL,
405 (!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) &&
406 !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED)));
407
408 SET_FIELD(state, ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL,
409 !!(accept_filter & QED_ACCEPT_BCAST));
410
411 p_ramrod->rx_mode.state = cpu_to_le16(state);
412 DP_VERBOSE(p_hwfn, QED_MSG_SP,
413 "p_ramrod->rx_mode.state = 0x%x\n", state);
414 }
415
416 /* Set Tx mode accept flags */
417 if (p_ramrod->common.update_tx_mode_flg) {
418 u8 accept_filter = accept_flags.tx_accept_filter;
419 u16 state = 0;
420
421 SET_FIELD(state, ETH_VPORT_TX_MODE_UCAST_DROP_ALL,
422 !!(accept_filter & QED_ACCEPT_NONE));
423
cee4d264
MC		 424 SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_DROP_ALL,
425 !!(accept_filter & QED_ACCEPT_NONE));
426
427 SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL,
428 (!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) &&
429 !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED)));
430
431 SET_FIELD(state, ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL,
432 !!(accept_filter & QED_ACCEPT_BCAST));
433
434 p_ramrod->tx_mode.state = cpu_to_le16(state);
435 DP_VERBOSE(p_hwfn, QED_MSG_SP,
436 "p_ramrod->tx_mode.state = 0x%x\n", state);
437 }
438}
439
17b235c1
YM		 440static void
441qed_sp_vport_update_sge_tpa(struct qed_hwfn *p_hwfn,
442 struct vport_update_ramrod_data *p_ramrod,
443 struct qed_sge_tpa_params *p_params)
444{
445 struct eth_vport_tpa_param *p_tpa;
446
447 if (!p_params) {
448 p_ramrod->common.update_tpa_param_flg = 0;
449 p_ramrod->common.update_tpa_en_flg = 0;
450 p_ramrod->common.update_tpa_param_flg = 0;
451 return;
452 }
453
454 p_ramrod->common.update_tpa_en_flg = p_params->update_tpa_en_flg;
455 p_tpa = &p_ramrod->tpa_param;
456 p_tpa->tpa_ipv4_en_flg = p_params->tpa_ipv4_en_flg;
457 p_tpa->tpa_ipv6_en_flg = p_params->tpa_ipv6_en_flg;
458 p_tpa->tpa_ipv4_tunn_en_flg = p_params->tpa_ipv4_tunn_en_flg;
459 p_tpa->tpa_ipv6_tunn_en_flg = p_params->tpa_ipv6_tunn_en_flg;
460
461 p_ramrod->common.update_tpa_param_flg = p_params->update_tpa_param_flg;
462 p_tpa->max_buff_num = p_params->max_buffers_per_cqe;
463 p_tpa->tpa_pkt_split_flg = p_params->tpa_pkt_split_flg;
464 p_tpa->tpa_hdr_data_split_flg = p_params->tpa_hdr_data_split_flg;
465 p_tpa->tpa_gro_consistent_flg = p_params->tpa_gro_consistent_flg;
466 p_tpa->tpa_max_aggs_num = p_params->tpa_max_aggs_num;
467 p_tpa->tpa_max_size = p_params->tpa_max_size;
468 p_tpa->tpa_min_size_to_start = p_params->tpa_min_size_to_start;
469 p_tpa->tpa_min_size_to_cont = p_params->tpa_min_size_to_cont;
470}
471
cee4d264
MC		 472static void
473qed_sp_update_mcast_bin(struct qed_hwfn *p_hwfn,
474 struct vport_update_ramrod_data *p_ramrod,
475 struct qed_sp_vport_update_params *p_params)
476{
477 int i;
478
479 memset(&p_ramrod->approx_mcast.bins, 0,
480 sizeof(p_ramrod->approx_mcast.bins));
481
83aeb933
YM		 482 if (!p_params->update_approx_mcast_flg)
483 return;
cee4d264 484
83aeb933
YM		 485 p_ramrod->common.update_approx_mcast_flg = 1;
486 for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) {
487 u32 *p_bins = (u32 *)p_params->bins;
488
489 p_ramrod->approx_mcast.bins[i] = cpu_to_le32(p_bins[i]);
cee4d264
MC		 490 }
491}
492
dacd88d6
YM		 493int qed_sp_vport_update(struct qed_hwfn *p_hwfn,
494 struct qed_sp_vport_update_params *p_params,
495 enum spq_mode comp_mode,
496 struct qed_spq_comp_cb *p_comp_data)
cee4d264
MC		 497{
498 struct qed_rss_params *p_rss_params = p_params->rss_params;
499 struct vport_update_ramrod_data_cmn *p_cmn;
06f56b81 500 struct qed_sp_init_data init_data;
cee4d264
MC		 501 struct vport_update_ramrod_data *p_ramrod = NULL;
502 struct qed_spq_entry *p_ent = NULL;
17b235c1 503 u8 abs_vport_id = 0, val;
cee4d264
MC		 504 int rc = -EINVAL;
505
dacd88d6
YM		 506 if (IS_VF(p_hwfn->cdev)) {
507 rc = qed_vf_pf_vport_update(p_hwfn, p_params);
508 return rc;
509 }
510
cee4d264 511 rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
1a635e48 512 if (rc)
cee4d264
MC		 513 return rc;
514
06f56b81
YM		 515 memset(&init_data, 0, sizeof(init_data));
516 init_data.cid = qed_spq_get_cid(p_hwfn);
517 init_data.opaque_fid = p_params->opaque_fid;
518 init_data.comp_mode = comp_mode;
519 init_data.p_comp_data = p_comp_data;
cee4d264
MC		 520
521 rc = qed_sp_init_request(p_hwfn, &p_ent,
cee4d264 522 ETH_RAMROD_VPORT_UPDATE,
06f56b81 523 PROTOCOLID_ETH, &init_data);
cee4d264
MC		 524 if (rc)
525 return rc;
526
527 /* Copy input params to ramrod according to FW struct */
528 p_ramrod = &p_ent->ramrod.vport_update;
529 p_cmn = &p_ramrod->common;
530
531 p_cmn->vport_id = abs_vport_id;
532 p_cmn->rx_active_flg = p_params->vport_active_rx_flg;
533 p_cmn->update_rx_active_flg = p_params->update_vport_active_rx_flg;
534 p_cmn->tx_active_flg = p_params->vport_active_tx_flg;
535 p_cmn->update_tx_active_flg = p_params->update_vport_active_tx_flg;
3f9b4a69 536 p_cmn->accept_any_vlan = p_params->accept_any_vlan;
83aeb933
YM		 537 val = p_params->update_accept_any_vlan_flg;
538 p_cmn->update_accept_any_vlan_flg = val;
17b235c1
YM		 539
540 p_cmn->inner_vlan_removal_en = p_params->inner_vlan_removal_flg;
541 val = p_params->update_inner_vlan_removal_flg;
542 p_cmn->update_inner_vlan_removal_en_flg = val;
08feecd7
YM		 543
544 p_cmn->default_vlan_en = p_params->default_vlan_enable_flg;
545 val = p_params->update_default_vlan_enable_flg;
546 p_cmn->update_default_vlan_en_flg = val;
547
548 p_cmn->default_vlan = cpu_to_le16(p_params->default_vlan);
549 p_cmn->update_default_vlan_flg = p_params->update_default_vlan_flg;
550
551 p_cmn->silent_vlan_removal_en = p_params->silent_vlan_removal_flg;
552
17b235c1
YM		 553 p_ramrod->common.tx_switching_en = p_params->tx_switching_flg;
554 p_cmn->update_tx_switching_en_flg = p_params->update_tx_switching_flg;
555
6ddc7608
YM		 556 p_cmn->anti_spoofing_en = p_params->anti_spoofing_en;
557 val = p_params->update_anti_spoofing_en_flg;
558 p_ramrod->common.update_anti_spoofing_en_flg = val;
559
cee4d264
MC		 560 rc = qed_sp_vport_update_rss(p_hwfn, p_ramrod, p_rss_params);
561 if (rc) {
562 /* Return spq entry which is taken in qed_sp_init_request()*/
563 qed_spq_return_entry(p_hwfn, p_ent);
564 return rc;
565 }
566
567 /* Update mcast bins for VFs, PF doesn't use this functionality */
568 qed_sp_update_mcast_bin(p_hwfn, p_ramrod, p_params);
569
570 qed_sp_update_accept_mode(p_hwfn, p_ramrod, p_params->accept_flags);
17b235c1 571 qed_sp_vport_update_sge_tpa(p_hwfn, p_ramrod, p_params->sge_tpa_params);
cee4d264
MC		 572 return qed_spq_post(p_hwfn, p_ent, NULL);
573}
574
dacd88d6 575int qed_sp_vport_stop(struct qed_hwfn *p_hwfn, u16 opaque_fid, u8 vport_id)
cee4d264 576{
cee4d264 577 struct vport_stop_ramrod_data *p_ramrod;
06f56b81 578 struct qed_sp_init_data init_data;
cee4d264
MC		 579 struct qed_spq_entry *p_ent;
580 u8 abs_vport_id = 0;
581 int rc;
582
dacd88d6
YM		 583 if (IS_VF(p_hwfn->cdev))
584 return qed_vf_pf_vport_stop(p_hwfn);
585
cee4d264 586 rc = qed_fw_vport(p_hwfn, vport_id, &abs_vport_id);
1a635e48 587 if (rc)
cee4d264
MC		 588 return rc;
589
06f56b81
YM		 590 memset(&init_data, 0, sizeof(init_data));
591 init_data.cid = qed_spq_get_cid(p_hwfn);
592 init_data.opaque_fid = opaque_fid;
593 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
cee4d264
MC		 594
595 rc = qed_sp_init_request(p_hwfn, &p_ent,
cee4d264 596 ETH_RAMROD_VPORT_STOP,
06f56b81 597 PROTOCOLID_ETH, &init_data);
cee4d264
MC		 598 if (rc)
599 return rc;
600
601 p_ramrod = &p_ent->ramrod.vport_stop;
602 p_ramrod->vport_id = abs_vport_id;
603
604 return qed_spq_post(p_hwfn, p_ent, NULL);
605}
606
dacd88d6
YM		 607static int
608qed_vf_pf_accept_flags(struct qed_hwfn *p_hwfn,
609 struct qed_filter_accept_flags *p_accept_flags)
610{
611 struct qed_sp_vport_update_params s_params;
612
613 memset(&s_params, 0, sizeof(s_params));
614 memcpy(&s_params.accept_flags, p_accept_flags,
615 sizeof(struct qed_filter_accept_flags));
616
617 return qed_vf_pf_vport_update(p_hwfn, &s_params);
618}
619
cee4d264
MC		 620static int qed_filter_accept_cmd(struct qed_dev *cdev,
621 u8 vport,
622 struct qed_filter_accept_flags accept_flags,
3f9b4a69
YM		 623 u8 update_accept_any_vlan,
624 u8 accept_any_vlan,
dacd88d6
YM		 625 enum spq_mode comp_mode,
626 struct qed_spq_comp_cb *p_comp_data)
cee4d264
MC		 627{
628 struct qed_sp_vport_update_params vport_update_params;
629 int i, rc;
630
631 /* Prepare and send the vport rx_mode change */
632 memset(&vport_update_params, 0, sizeof(vport_update_params));
633 vport_update_params.vport_id = vport;
634 vport_update_params.accept_flags = accept_flags;
3f9b4a69
YM		 635 vport_update_params.update_accept_any_vlan_flg = update_accept_any_vlan;
636 vport_update_params.accept_any_vlan = accept_any_vlan;
cee4d264
MC		 637
638 for_each_hwfn(cdev, i) {
639 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
640
641 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
642
dacd88d6
YM		 643 if (IS_VF(cdev)) {
644 rc = qed_vf_pf_accept_flags(p_hwfn, &accept_flags);
645 if (rc)
646 return rc;
647 continue;
648 }
649
cee4d264
MC		 650 rc = qed_sp_vport_update(p_hwfn, &vport_update_params,
651 comp_mode, p_comp_data);
1a635e48 652 if (rc) {
cee4d264
MC		 653 DP_ERR(cdev, "Update rx_mode failed %d\n", rc);
654 return rc;
655 }
656
657 DP_VERBOSE(p_hwfn, QED_MSG_SP,
658 "Accept filter configured, flags = [Rx]%x [Tx]%x\n",
659 accept_flags.rx_accept_filter,
660 accept_flags.tx_accept_filter);
3f9b4a69
YM		 661 if (update_accept_any_vlan)
662 DP_VERBOSE(p_hwfn, QED_MSG_SP,
663 "accept_any_vlan=%d configured\n",
664 accept_any_vlan);
cee4d264
MC		 665 }
666
667 return 0;
668}
669
3da7a37a
MY		 670int qed_eth_rxq_start_ramrod(struct qed_hwfn *p_hwfn,
671 struct qed_queue_cid *p_cid,
672 u16 bd_max_bytes,
673 dma_addr_t bd_chain_phys_addr,
674 dma_addr_t cqe_pbl_addr, u16 cqe_pbl_size)
cee4d264
MC		 675{
676 struct rx_queue_start_ramrod_data *p_ramrod = NULL;
cee4d264 677 struct qed_spq_entry *p_ent = NULL;
06f56b81 678 struct qed_sp_init_data init_data;
cee4d264
MC		 679 int rc = -EINVAL;
680
cee4d264 681 DP_VERBOSE(p_hwfn, QED_MSG_SP,
3da7a37a
MY		 682 "opaque_fid=0x%x, cid=0x%x, rx_qzone=0x%x, vport_id=0x%x, sb_id=0x%x\n",
683 p_cid->opaque_fid, p_cid->cid,
684 p_cid->abs.queue_id, p_cid->abs.vport_id, p_cid->abs.sb);
cee4d264 685
06f56b81
YM		 686 /* Get SPQ entry */
687 memset(&init_data, 0, sizeof(init_data));
3da7a37a
MY		 688 init_data.cid = p_cid->cid;
689 init_data.opaque_fid = p_cid->opaque_fid;
06f56b81 690 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
cee4d264
MC		 691
692 rc = qed_sp_init_request(p_hwfn, &p_ent,
cee4d264 693 ETH_RAMROD_RX_QUEUE_START,
06f56b81 694 PROTOCOLID_ETH, &init_data);
cee4d264
MC		 695 if (rc)
696 return rc;
697
698 p_ramrod = &p_ent->ramrod.rx_queue_start;
699
3da7a37a
MY		 700 p_ramrod->sb_id = cpu_to_le16(p_cid->abs.sb);
701 p_ramrod->sb_index = p_cid->abs.sb_idx;
702 p_ramrod->vport_id = p_cid->abs.vport_id;
703 p_ramrod->stats_counter_id = p_cid->abs.stats_id;
704 p_ramrod->rx_queue_id = cpu_to_le16(p_cid->abs.queue_id);
1a635e48
YM		 705 p_ramrod->complete_cqe_flg = 0;
706 p_ramrod->complete_event_flg = 1;
cee4d264 707
1a635e48 708 p_ramrod->bd_max_bytes = cpu_to_le16(bd_max_bytes);
94494598 709 DMA_REGPAIR_LE(p_ramrod->bd_base, bd_chain_phys_addr);
cee4d264 710
1a635e48 711 p_ramrod->num_of_pbl_pages = cpu_to_le16(cqe_pbl_size);
94494598 712 DMA_REGPAIR_LE(p_ramrod->cqe_pbl_addr, cqe_pbl_addr);
cee4d264 713
3da7a37a
MY		 714 if (p_cid->is_vf) {
715 p_ramrod->vf_rx_prod_index = p_cid->vf_qid;
351a4ded 716 DP_VERBOSE(p_hwfn, QED_MSG_SP,
a044df83 717 "Queue%s is meant for VF rxq[%02x]\n",
3da7a37a
MY		 718 !!p_cid->b_legacy_vf ? " [legacy]" : "",
719 p_cid->vf_qid);
720 p_ramrod->vf_rx_prod_use_zone_a = !!p_cid->b_legacy_vf;
a044df83 721 }
cee4d264 722
351a4ded 723 return qed_spq_post(p_hwfn, p_ent, NULL);
cee4d264
MC		 724}
725
726static int
3da7a37a
MY		 727qed_eth_pf_rx_queue_start(struct qed_hwfn *p_hwfn,
728 struct qed_queue_cid *p_cid,
cee4d264
MC		 729 u16 bd_max_bytes,
730 dma_addr_t bd_chain_phys_addr,
731 dma_addr_t cqe_pbl_addr,
dacd88d6 732 u16 cqe_pbl_size, void __iomem **pp_prod)
cee4d264 733{
b21290b7 734 u32 init_prod_val = 0;
cee4d264 735
3da7a37a
MY		 736 *pp_prod = p_hwfn->regview +
737 GTT_BAR0_MAP_REG_MSDM_RAM +
738 MSTORM_ETH_PF_PRODS_OFFSET(p_cid->abs.queue_id);
cee4d264
MC		 739
740 /* Init the rcq, rx bd and rx sge (if valid) producers to 0 */
b21290b7 741 __internal_ram_wr(p_hwfn, *pp_prod, sizeof(u32),
cee4d264
MC		 742 (u32 *)(&init_prod_val));
743
3da7a37a
MY		 744 return qed_eth_rxq_start_ramrod(p_hwfn, p_cid,
745 bd_max_bytes,
746 bd_chain_phys_addr,
747 cqe_pbl_addr, cqe_pbl_size);
748}
749
750static int
751qed_eth_rx_queue_start(struct qed_hwfn *p_hwfn,
752 u16 opaque_fid,
753 struct qed_queue_start_common_params *p_params,
754 u16 bd_max_bytes,
755 dma_addr_t bd_chain_phys_addr,
756 dma_addr_t cqe_pbl_addr,
757 u16 cqe_pbl_size,
758 struct qed_rxq_start_ret_params *p_ret_params)
759{
760 struct qed_queue_cid *p_cid;
761 int rc;
762
cee4d264 763 /* Allocate a CID for the queue */
3da7a37a
MY		 764 p_cid = qed_eth_queue_to_cid(p_hwfn, opaque_fid, p_params);
765 if (!p_cid)
766 return -ENOMEM;
cee4d264 767
3da7a37a
MY		 768 if (IS_PF(p_hwfn->cdev)) {
769 rc = qed_eth_pf_rx_queue_start(p_hwfn, p_cid,
770 bd_max_bytes,
771 bd_chain_phys_addr,
772 cqe_pbl_addr, cqe_pbl_size,
773 &p_ret_params->p_prod);
774 } else {
775 rc = qed_vf_pf_rxq_start(p_hwfn, p_cid,
cee4d264
MC		 776 bd_max_bytes,
777 bd_chain_phys_addr,
3da7a37a
MY		 778 cqe_pbl_addr,
779 cqe_pbl_size, &p_ret_params->p_prod);
780 }
cee4d264 781
3da7a37a 782 /* Provide the caller with a reference to as handler */
1a635e48 783 if (rc)
3da7a37a
MY		 784 qed_eth_queue_cid_release(p_hwfn, p_cid);
785 else
786 p_ret_params->p_handle = (void *)p_cid;
cee4d264
MC		 787
788 return rc;
789}
790
17b235c1 791int qed_sp_eth_rx_queues_update(struct qed_hwfn *p_hwfn,
3da7a37a 792 void **pp_rxq_handles,
17b235c1
YM		 793 u8 num_rxqs,
794 u8 complete_cqe_flg,
795 u8 complete_event_flg,
796 enum spq_mode comp_mode,
797 struct qed_spq_comp_cb *p_comp_data)
798{
799 struct rx_queue_update_ramrod_data *p_ramrod = NULL;
800 struct qed_spq_entry *p_ent = NULL;
801 struct qed_sp_init_data init_data;
3da7a37a 802 struct qed_queue_cid *p_cid;
17b235c1
YM		 803 int rc = -EINVAL;
804 u8 i;
805
806 memset(&init_data, 0, sizeof(init_data));
807 init_data.comp_mode = comp_mode;
808 init_data.p_comp_data = p_comp_data;
809
810 for (i = 0; i < num_rxqs; i++) {
3da7a37a 811 p_cid = ((struct qed_queue_cid **)pp_rxq_handles)[i];
17b235c1
YM		 812
813 /* Get SPQ entry */
3da7a37a
MY		 814 init_data.cid = p_cid->cid;
815 init_data.opaque_fid = p_cid->opaque_fid;
17b235c1
YM		 816
817 rc = qed_sp_init_request(p_hwfn, &p_ent,
818 ETH_RAMROD_RX_QUEUE_UPDATE,
819 PROTOCOLID_ETH, &init_data);
820 if (rc)
821 return rc;
822
823 p_ramrod = &p_ent->ramrod.rx_queue_update;
3da7a37a 824 p_ramrod->vport_id = p_cid->abs.vport_id;
17b235c1 825
3da7a37a 826 p_ramrod->rx_queue_id = cpu_to_le16(p_cid->abs.queue_id);
17b235c1
YM		 827 p_ramrod->complete_cqe_flg = complete_cqe_flg;
828 p_ramrod->complete_event_flg = complete_event_flg;
829
830 rc = qed_spq_post(p_hwfn, p_ent, NULL);
831 if (rc)
832 return rc;
833 }
834
835 return rc;
836}
837
3da7a37a
MY		 838static int
839qed_eth_pf_rx_queue_stop(struct qed_hwfn *p_hwfn,
840 struct qed_queue_cid *p_cid,
841 bool b_eq_completion_only, bool b_cqe_completion)
cee4d264 842{
cee4d264 843 struct rx_queue_stop_ramrod_data *p_ramrod = NULL;
cee4d264 844 struct qed_spq_entry *p_ent = NULL;
06f56b81 845 struct qed_sp_init_data init_data;
3da7a37a 846 int rc;
dacd88d6 847
06f56b81 848 memset(&init_data, 0, sizeof(init_data));
3da7a37a
MY		 849 init_data.cid = p_cid->cid;
850 init_data.opaque_fid = p_cid->opaque_fid;
06f56b81 851 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
cee4d264
MC		 852
853 rc = qed_sp_init_request(p_hwfn, &p_ent,
cee4d264 854 ETH_RAMROD_RX_QUEUE_STOP,
06f56b81 855 PROTOCOLID_ETH, &init_data);
cee4d264
MC		 856 if (rc)
857 return rc;
858
859 p_ramrod = &p_ent->ramrod.rx_queue_stop;
3da7a37a
MY		 860 p_ramrod->vport_id = p_cid->abs.vport_id;
861 p_ramrod->rx_queue_id = cpu_to_le16(p_cid->abs.queue_id);
cee4d264
MC		 862
863 /* Cleaning the queue requires the completion to arrive there.
864 * In addition, VFs require the answer to come as eqe to PF.
865 */
3da7a37a
MY		 866 p_ramrod->complete_cqe_flg = (!p_cid->is_vf &&
867 !b_eq_completion_only) ||
868 b_cqe_completion;
869 p_ramrod->complete_event_flg = p_cid->is_vf || b_eq_completion_only;
cee4d264 870
3da7a37a
MY		 871 return qed_spq_post(p_hwfn, p_ent, NULL);
872}
873
874int qed_eth_rx_queue_stop(struct qed_hwfn *p_hwfn,
875 void *p_rxq,
876 bool eq_completion_only, bool cqe_completion)
877{
878 struct qed_queue_cid *p_cid = (struct qed_queue_cid *)p_rxq;
879 int rc = -EINVAL;
cee4d264 880
3da7a37a
MY		 881 if (IS_PF(p_hwfn->cdev))
882 rc = qed_eth_pf_rx_queue_stop(p_hwfn, p_cid,
883 eq_completion_only,
884 cqe_completion);
885 else
886 rc = qed_vf_pf_rxq_stop(p_hwfn, p_cid, cqe_completion);
887
888 if (!rc)
889 qed_eth_queue_cid_release(p_hwfn, p_cid);
890 return rc;
cee4d264
MC		 891}
892
3da7a37a
MY		 893int
894qed_eth_txq_start_ramrod(struct qed_hwfn *p_hwfn,
895 struct qed_queue_cid *p_cid,
896 dma_addr_t pbl_addr, u16 pbl_size, u16 pq_id)
cee4d264
MC		 897{
898 struct tx_queue_start_ramrod_data *p_ramrod = NULL;
cee4d264 899 struct qed_spq_entry *p_ent = NULL;
06f56b81 900 struct qed_sp_init_data init_data;
cee4d264 901 int rc = -EINVAL;
351a4ded 902
06f56b81
YM		 903 /* Get SPQ entry */
904 memset(&init_data, 0, sizeof(init_data));
3da7a37a
MY		 905 init_data.cid = p_cid->cid;
906 init_data.opaque_fid = p_cid->opaque_fid;
06f56b81 907 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
cee4d264 908
06f56b81 909 rc = qed_sp_init_request(p_hwfn, &p_ent,
cee4d264 910 ETH_RAMROD_TX_QUEUE_START,
06f56b81 911 PROTOCOLID_ETH, &init_data);
cee4d264
MC		 912 if (rc)
913 return rc;
914
1a635e48 915 p_ramrod = &p_ent->ramrod.tx_queue_start;
3da7a37a 916 p_ramrod->vport_id = p_cid->abs.vport_id;
1a635e48 917
3da7a37a
MY		 918 p_ramrod->sb_id = cpu_to_le16(p_cid->abs.sb);
919 p_ramrod->sb_index = p_cid->abs.sb_idx;
920 p_ramrod->stats_counter_id = p_cid->abs.stats_id;
cee4d264 921
3da7a37a
MY		 922 p_ramrod->queue_zone_id = cpu_to_le16(p_cid->abs.queue_id);
923 p_ramrod->same_as_last_id = cpu_to_le16(p_cid->abs.queue_id);
cee4d264 924
1a635e48 925 p_ramrod->pbl_size = cpu_to_le16(pbl_size);
94494598 926 DMA_REGPAIR_LE(p_ramrod->pbl_base_addr, pbl_addr);
cee4d264 927
1a635e48 928 p_ramrod->qm_pq_id = cpu_to_le16(pq_id);
cee4d264
MC		 929
930 return qed_spq_post(p_hwfn, p_ent, NULL);
931}
932
933static int
3da7a37a
MY		 934qed_eth_pf_tx_queue_start(struct qed_hwfn *p_hwfn,
935 struct qed_queue_cid *p_cid,
936 u8 tc,
cee4d264 937 dma_addr_t pbl_addr,
dacd88d6 938 u16 pbl_size, void __iomem **pp_doorbell)
cee4d264 939{
cee4d264
MC		 940 int rc;
941
dacd88d6 942
3da7a37a
MY		 943 rc = qed_eth_txq_start_ramrod(p_hwfn, p_cid,
944 pbl_addr, pbl_size,
b5a9ee7c 945 qed_get_cm_pq_idx_mcos(p_hwfn, tc));
cee4d264
MC		 946 if (rc)
947 return rc;
948
3da7a37a
MY		 949 /* Provide the caller with the necessary return values */
950 *pp_doorbell = p_hwfn->doorbells +
951 qed_db_addr(p_cid->cid, DQ_DEMS_LEGACY);
cee4d264 952
3da7a37a
MY		 953 return 0;
954}
cee4d264 955
3da7a37a
MY		 956static int
957qed_eth_tx_queue_start(struct qed_hwfn *p_hwfn,
958 u16 opaque_fid,
959 struct qed_queue_start_common_params *p_params,
960 u8 tc,
961 dma_addr_t pbl_addr,
962 u16 pbl_size,
963 struct qed_txq_start_ret_params *p_ret_params)
964{
965 struct qed_queue_cid *p_cid;
966 int rc;
967
968 p_cid = qed_eth_queue_to_cid(p_hwfn, opaque_fid, p_params);
969 if (!p_cid)
970 return -EINVAL;
971
972 if (IS_PF(p_hwfn->cdev))
973 rc = qed_eth_pf_tx_queue_start(p_hwfn, p_cid, tc,
974 pbl_addr, pbl_size,
975 &p_ret_params->p_doorbell);
976 else
977 rc = qed_vf_pf_txq_start(p_hwfn, p_cid,
978 pbl_addr, pbl_size,
979 &p_ret_params->p_doorbell);
cee4d264
MC		 980
981 if (rc)
3da7a37a
MY		 982 qed_eth_queue_cid_release(p_hwfn, p_cid);
983 else
984 p_ret_params->p_handle = (void *)p_cid;
cee4d264
MC		 985
986 return rc;
987}
988
3da7a37a
MY		 989static int
990qed_eth_pf_tx_queue_stop(struct qed_hwfn *p_hwfn, struct qed_queue_cid *p_cid)
cee4d264 991{
cee4d264 992 struct qed_spq_entry *p_ent = NULL;
06f56b81 993 struct qed_sp_init_data init_data;
3da7a37a 994 int rc;
dacd88d6 995
06f56b81 996 memset(&init_data, 0, sizeof(init_data));
3da7a37a
MY		 997 init_data.cid = p_cid->cid;
998 init_data.opaque_fid = p_cid->opaque_fid;
06f56b81 999 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
cee4d264
MC		 1000
1001 rc = qed_sp_init_request(p_hwfn, &p_ent,
cee4d264 1002 ETH_RAMROD_TX_QUEUE_STOP,
06f56b81 1003 PROTOCOLID_ETH, &init_data);
cee4d264
MC		 1004 if (rc)
1005 return rc;
1006
3da7a37a
MY		 1007 return qed_spq_post(p_hwfn, p_ent, NULL);
1008}
1009
1010int qed_eth_tx_queue_stop(struct qed_hwfn *p_hwfn, void *p_handle)
1011{
1012 struct qed_queue_cid *p_cid = (struct qed_queue_cid *)p_handle;
1013 int rc;
1014
1015 if (IS_PF(p_hwfn->cdev))
1016 rc = qed_eth_pf_tx_queue_stop(p_hwfn, p_cid);
1017 else
1018 rc = qed_vf_pf_txq_stop(p_hwfn, p_cid);
cee4d264 1019
3da7a37a
MY		 1020 if (!rc)
1021 qed_eth_queue_cid_release(p_hwfn, p_cid);
1022 return rc;
cee4d264
MC		 1023}
1024
1a635e48 1025static enum eth_filter_action qed_filter_action(enum qed_filter_opcode opcode)
cee4d264
MC		 1026{
1027 enum eth_filter_action action = MAX_ETH_FILTER_ACTION;
1028
1029 switch (opcode) {
1030 case QED_FILTER_ADD:
1031 action = ETH_FILTER_ACTION_ADD;
1032 break;
1033 case QED_FILTER_REMOVE:
1034 action = ETH_FILTER_ACTION_REMOVE;
1035 break;
cee4d264 1036 case QED_FILTER_FLUSH:
fc48b7a6 1037 action = ETH_FILTER_ACTION_REMOVE_ALL;
cee4d264
MC		 1038 break;
1039 default:
1040 action = MAX_ETH_FILTER_ACTION;
1041 }
1042
1043 return action;
1044}
1045
1046static void qed_set_fw_mac_addr(__le16 *fw_msb,
1047 __le16 *fw_mid,
1048 __le16 *fw_lsb,
1049 u8 *mac)
1050{
1051 ((u8 *)fw_msb)[0] = mac[1];
1052 ((u8 *)fw_msb)[1] = mac[0];
1053 ((u8 *)fw_mid)[0] = mac[3];
1054 ((u8 *)fw_mid)[1] = mac[2];
1055 ((u8 *)fw_lsb)[0] = mac[5];
1056 ((u8 *)fw_lsb)[1] = mac[4];
1057}
1058
1059static int
1060qed_filter_ucast_common(struct qed_hwfn *p_hwfn,
1061 u16 opaque_fid,
1062 struct qed_filter_ucast *p_filter_cmd,
1063 struct vport_filter_update_ramrod_data **pp_ramrod,
1064 struct qed_spq_entry **pp_ent,
1065 enum spq_mode comp_mode,
1066 struct qed_spq_comp_cb *p_comp_data)
1067{
1068 u8 vport_to_add_to = 0, vport_to_remove_from = 0;
1069 struct vport_filter_update_ramrod_data *p_ramrod;
cee4d264
MC		 1070 struct eth_filter_cmd *p_first_filter;
1071 struct eth_filter_cmd *p_second_filter;
06f56b81 1072 struct qed_sp_init_data init_data;
cee4d264
MC		 1073 enum eth_filter_action action;
1074 int rc;
1075
1076 rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from,
1077 &vport_to_remove_from);
1078 if (rc)
1079 return rc;
1080
1081 rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to,
1082 &vport_to_add_to);
1083 if (rc)
1084 return rc;
1085
06f56b81
YM		 1086 /* Get SPQ entry */
1087 memset(&init_data, 0, sizeof(init_data));
1088 init_data.cid = qed_spq_get_cid(p_hwfn);
1089 init_data.opaque_fid = opaque_fid;
1090 init_data.comp_mode = comp_mode;
1091 init_data.p_comp_data = p_comp_data;
cee4d264
MC		 1092
1093 rc = qed_sp_init_request(p_hwfn, pp_ent,
cee4d264 1094 ETH_RAMROD_FILTERS_UPDATE,
06f56b81 1095 PROTOCOLID_ETH, &init_data);
cee4d264
MC		 1096 if (rc)
1097 return rc;
1098
1099 *pp_ramrod = &(*pp_ent)->ramrod.vport_filter_update;
1100 p_ramrod = *pp_ramrod;
1101 p_ramrod->filter_cmd_hdr.rx = p_filter_cmd->is_rx_filter ? 1 : 0;
1102 p_ramrod->filter_cmd_hdr.tx = p_filter_cmd->is_tx_filter ? 1 : 0;
1103
1104 switch (p_filter_cmd->opcode) {
fc48b7a6 1105 case QED_FILTER_REPLACE:
cee4d264
MC		 1106 case QED_FILTER_MOVE:
1107 p_ramrod->filter_cmd_hdr.cmd_cnt = 2; break;
1108 default:
1109 p_ramrod->filter_cmd_hdr.cmd_cnt = 1; break;
1110 }
1111
1112 p_first_filter = &p_ramrod->filter_cmds[0];
1113 p_second_filter = &p_ramrod->filter_cmds[1];
1114
1115 switch (p_filter_cmd->type) {
1116 case QED_FILTER_MAC:
1117 p_first_filter->type = ETH_FILTER_TYPE_MAC; break;
1118 case QED_FILTER_VLAN:
1119 p_first_filter->type = ETH_FILTER_TYPE_VLAN; break;
1120 case QED_FILTER_MAC_VLAN:
1121 p_first_filter->type = ETH_FILTER_TYPE_PAIR; break;
1122 case QED_FILTER_INNER_MAC:
1123 p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC; break;
1124 case QED_FILTER_INNER_VLAN:
1125 p_first_filter->type = ETH_FILTER_TYPE_INNER_VLAN; break;
1126 case QED_FILTER_INNER_PAIR:
1127 p_first_filter->type = ETH_FILTER_TYPE_INNER_PAIR; break;
1128 case QED_FILTER_INNER_MAC_VNI_PAIR:
1129 p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR;
1130 break;
1131 case QED_FILTER_MAC_VNI_PAIR:
1132 p_first_filter->type = ETH_FILTER_TYPE_MAC_VNI_PAIR; break;
1133 case QED_FILTER_VNI:
1134 p_first_filter->type = ETH_FILTER_TYPE_VNI; break;
1135 }
1136
1137 if ((p_first_filter->type == ETH_FILTER_TYPE_MAC) ||
1138 (p_first_filter->type == ETH_FILTER_TYPE_PAIR) ||
1139 (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC) ||
1140 (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR) ||
1141 (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) ||
1142 (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR)) {
1143 qed_set_fw_mac_addr(&p_first_filter->mac_msb,
1144 &p_first_filter->mac_mid,
1145 &p_first_filter->mac_lsb,
1146 (u8 *)p_filter_cmd->mac);
1147 }
1148
1149 if ((p_first_filter->type == ETH_FILTER_TYPE_VLAN) ||
1150 (p_first_filter->type == ETH_FILTER_TYPE_PAIR) ||
1151 (p_first_filter->type == ETH_FILTER_TYPE_INNER_VLAN) ||
1152 (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR))
1153 p_first_filter->vlan_id = cpu_to_le16(p_filter_cmd->vlan);
1154
1155 if ((p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) ||
1156 (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR) ||
1157 (p_first_filter->type == ETH_FILTER_TYPE_VNI))
1158 p_first_filter->vni = cpu_to_le32(p_filter_cmd->vni);
1159
1160 if (p_filter_cmd->opcode == QED_FILTER_MOVE) {
1a635e48
YM		 1161 p_second_filter->type = p_first_filter->type;
1162 p_second_filter->mac_msb = p_first_filter->mac_msb;
1163 p_second_filter->mac_mid = p_first_filter->mac_mid;
1164 p_second_filter->mac_lsb = p_first_filter->mac_lsb;
1165 p_second_filter->vlan_id = p_first_filter->vlan_id;
1166 p_second_filter->vni = p_first_filter->vni;
cee4d264
MC		 1167
1168 p_first_filter->action = ETH_FILTER_ACTION_REMOVE;
1169
1170 p_first_filter->vport_id = vport_to_remove_from;
1171
1a635e48
YM		 1172 p_second_filter->action = ETH_FILTER_ACTION_ADD;
1173 p_second_filter->vport_id = vport_to_add_to;
fc48b7a6
YM		 1174 } else if (p_filter_cmd->opcode == QED_FILTER_REPLACE) {
1175 p_first_filter->vport_id = vport_to_add_to;
1176 memcpy(p_second_filter, p_first_filter,
1177 sizeof(*p_second_filter));
1178 p_first_filter->action = ETH_FILTER_ACTION_REMOVE_ALL;
1179 p_second_filter->action = ETH_FILTER_ACTION_ADD;
cee4d264
MC		 1180 } else {
1181 action = qed_filter_action(p_filter_cmd->opcode);
1182
1183 if (action == MAX_ETH_FILTER_ACTION) {
1184 DP_NOTICE(p_hwfn,
1185 "%d is not supported yet\n",
1186 p_filter_cmd->opcode);
1187 return -EINVAL;
1188 }
1189
1190 p_first_filter->action = action;
1191 p_first_filter->vport_id = (p_filter_cmd->opcode ==
1192 QED_FILTER_REMOVE) ?
1193 vport_to_remove_from :
1194 vport_to_add_to;
1195 }
1196
1197 return 0;
1198}
1199
dacd88d6
YM		 1200int qed_sp_eth_filter_ucast(struct qed_hwfn *p_hwfn,
1201 u16 opaque_fid,
1202 struct qed_filter_ucast *p_filter_cmd,
1203 enum spq_mode comp_mode,
1204 struct qed_spq_comp_cb *p_comp_data)
cee4d264
MC		 1205{
1206 struct vport_filter_update_ramrod_data *p_ramrod = NULL;
1207 struct qed_spq_entry *p_ent = NULL;
1208 struct eth_filter_cmd_header *p_header;
1209 int rc;
1210
1211 rc = qed_filter_ucast_common(p_hwfn, opaque_fid, p_filter_cmd,
1212 &p_ramrod, &p_ent,
1213 comp_mode, p_comp_data);
1a635e48 1214 if (rc) {
cee4d264
MC		 1215 DP_ERR(p_hwfn, "Uni. filter command failed %d\n", rc);
1216 return rc;
1217 }
1218 p_header = &p_ramrod->filter_cmd_hdr;
1219 p_header->assert_on_error = p_filter_cmd->assert_on_error;
1220
1221 rc = qed_spq_post(p_hwfn, p_ent, NULL);
1a635e48
YM		 1222 if (rc) {
1223 DP_ERR(p_hwfn, "Unicast filter ADD command failed %d\n", rc);
cee4d264
MC		 1224 return rc;
1225 }
1226
1227 DP_VERBOSE(p_hwfn, QED_MSG_SP,
1228 "Unicast filter configured, opcode = %s, type = %s, cmd_cnt = %d, is_rx_filter = %d, is_tx_filter = %d\n",
1229 (p_filter_cmd->opcode == QED_FILTER_ADD) ? "ADD" :
1230 ((p_filter_cmd->opcode == QED_FILTER_REMOVE) ?
1231 "REMOVE" :
1232 ((p_filter_cmd->opcode == QED_FILTER_MOVE) ?
1233 "MOVE" : "REPLACE")),
1234 (p_filter_cmd->type == QED_FILTER_MAC) ? "MAC" :
1235 ((p_filter_cmd->type == QED_FILTER_VLAN) ?
1236 "VLAN" : "MAC & VLAN"),
1237 p_ramrod->filter_cmd_hdr.cmd_cnt,
1238 p_filter_cmd->is_rx_filter,
1239 p_filter_cmd->is_tx_filter);
1240 DP_VERBOSE(p_hwfn, QED_MSG_SP,
1241 "vport_to_add_to = %d, vport_to_remove_from = %d, mac = %2x:%2x:%2x:%2x:%2x:%2x, vlan = %d\n",
1242 p_filter_cmd->vport_to_add_to,
1243 p_filter_cmd->vport_to_remove_from,
1244 p_filter_cmd->mac[0],
1245 p_filter_cmd->mac[1],
1246 p_filter_cmd->mac[2],
1247 p_filter_cmd->mac[3],
1248 p_filter_cmd->mac[4],
1249 p_filter_cmd->mac[5],
1250 p_filter_cmd->vlan);
1251
1252 return 0;
1253}
1254
1255/*******************************************************************************
1256 * Description:
1257 * Calculates crc 32 on a buffer
1258 * Note: crc32_length MUST be aligned to 8
1259 * Return:
1260 ******************************************************************************/
1261static u32 qed_calc_crc32c(u8 *crc32_packet,
1a635e48 1262 u32 crc32_length, u32 crc32_seed, u8 complement)
cee4d264 1263{
1a635e48
YM		 1264 u32 byte = 0, bit = 0, crc32_result = crc32_seed;
1265 u8 msb = 0, current_byte = 0;
cee4d264
MC		 1266
1267 if ((!crc32_packet) ||
1268 (crc32_length == 0) ||
1269 ((crc32_length % 8) != 0))
1270 return crc32_result;
1271 for (byte = 0; byte < crc32_length; byte++) {
1272 current_byte = crc32_packet[byte];
1273 for (bit = 0; bit < 8; bit++) {
1274 msb = (u8)(crc32_result >> 31);
1275 crc32_result = crc32_result << 1;
1276 if (msb != (0x1 & (current_byte >> bit))) {
1277 crc32_result = crc32_result ^ CRC32_POLY;
1278 crc32_result |= 1; /*crc32_result[0] = 1;*/
1279 }
1280 }
1281 }
1282 return crc32_result;
1283}
1284
1a635e48 1285static u32 qed_crc32c_le(u32 seed, u8 *mac, u32 len)
cee4d264
MC		 1286{
1287 u32 packet_buf[2] = { 0 };
1288
1289 memcpy((u8 *)(&packet_buf[0]), &mac[0], 6);
1290 return qed_calc_crc32c((u8 *)packet_buf, 8, seed, 0);
1291}
1292
dacd88d6 1293u8 qed_mcast_bin_from_mac(u8 *mac)
cee4d264
MC		 1294{
1295 u32 crc = qed_crc32c_le(ETH_MULTICAST_BIN_FROM_MAC_SEED,
1296 mac, ETH_ALEN);
1297
1298 return crc & 0xff;
1299}
1300
1301static int
1302qed_sp_eth_filter_mcast(struct qed_hwfn *p_hwfn,
1303 u16 opaque_fid,
1304 struct qed_filter_mcast *p_filter_cmd,
1305 enum spq_mode comp_mode,
1306 struct qed_spq_comp_cb *p_comp_data)
1307{
1308 unsigned long bins[ETH_MULTICAST_MAC_BINS_IN_REGS];
1309 struct vport_update_ramrod_data *p_ramrod = NULL;
cee4d264 1310 struct qed_spq_entry *p_ent = NULL;
06f56b81 1311 struct qed_sp_init_data init_data;
cee4d264
MC		 1312 u8 abs_vport_id = 0;
1313 int rc, i;
1314
83aeb933 1315 if (p_filter_cmd->opcode == QED_FILTER_ADD)
cee4d264
MC		 1316 rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to,
1317 &abs_vport_id);
83aeb933 1318 else
cee4d264
MC		 1319 rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from,
1320 &abs_vport_id);
83aeb933
YM		 1321 if (rc)
1322 return rc;
cee4d264 1323
06f56b81
YM		 1324 /* Get SPQ entry */
1325 memset(&init_data, 0, sizeof(init_data));
1326 init_data.cid = qed_spq_get_cid(p_hwfn);
1327 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
1328 init_data.comp_mode = comp_mode;
1329 init_data.p_comp_data = p_comp_data;
cee4d264
MC		 1330
1331 rc = qed_sp_init_request(p_hwfn, &p_ent,
cee4d264 1332 ETH_RAMROD_VPORT_UPDATE,
06f56b81 1333 PROTOCOLID_ETH, &init_data);
cee4d264
MC		 1334 if (rc) {
1335 DP_ERR(p_hwfn, "Multi-cast command failed %d\n", rc);
1336 return rc;
1337 }
1338
1339 p_ramrod = &p_ent->ramrod.vport_update;
1340 p_ramrod->common.update_approx_mcast_flg = 1;
1341
1342 /* explicitly clear out the entire vector */
1343 memset(&p_ramrod->approx_mcast.bins, 0,
1344 sizeof(p_ramrod->approx_mcast.bins));
1345 memset(bins, 0, sizeof(unsigned long) *
1346 ETH_MULTICAST_MAC_BINS_IN_REGS);
1347 /* filter ADD op is explicit set op and it removes
1348 * any existing filters for the vport
1349 */
1350 if (p_filter_cmd->opcode == QED_FILTER_ADD) {
1351 for (i = 0; i < p_filter_cmd->num_mc_addrs; i++) {
1352 u32 bit;
1353
1354 bit = qed_mcast_bin_from_mac(p_filter_cmd->mac[i]);
1355 __set_bit(bit, bins);
1356 }
1357
1358 /* Convert to correct endianity */
1359 for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) {
1a635e48 1360 struct vport_update_ramrod_mcast *p_ramrod_bins;
cee4d264 1361 u32 *p_bins = (u32 *)bins;
cee4d264 1362
1a635e48
YM		 1363 p_ramrod_bins = &p_ramrod->approx_mcast;
1364 p_ramrod_bins->bins[i] = cpu_to_le32(p_bins[i]);
cee4d264
MC		 1365 }
1366 }
1367
1368 p_ramrod->common.vport_id = abs_vport_id;
1369
1370 return qed_spq_post(p_hwfn, p_ent, NULL);
1371}
1372
dacd88d6
YM		 1373static int qed_filter_mcast_cmd(struct qed_dev *cdev,
1374 struct qed_filter_mcast *p_filter_cmd,
1375 enum spq_mode comp_mode,
1376 struct qed_spq_comp_cb *p_comp_data)
cee4d264
MC		 1377{
1378 int rc = 0;
1379 int i;
1380
1381 /* only ADD and REMOVE operations are supported for multi-cast */
1382 if ((p_filter_cmd->opcode != QED_FILTER_ADD &&
1383 (p_filter_cmd->opcode != QED_FILTER_REMOVE)) ||
1384 (p_filter_cmd->num_mc_addrs > QED_MAX_MC_ADDRS))
1385 return -EINVAL;
1386
1387 for_each_hwfn(cdev, i) {
1388 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1389
1390 u16 opaque_fid;
1391
dacd88d6
YM		 1392 if (IS_VF(cdev)) {
1393 qed_vf_pf_filter_mcast(p_hwfn, p_filter_cmd);
1394 continue;
1395 }
cee4d264
MC		 1396
1397 opaque_fid = p_hwfn->hw_info.opaque_fid;
1398
1399 rc = qed_sp_eth_filter_mcast(p_hwfn,
1400 opaque_fid,
1401 p_filter_cmd,
1a635e48 1402 comp_mode, p_comp_data);
cee4d264
MC		 1403 }
1404 return rc;
1405}
1406
1407static int qed_filter_ucast_cmd(struct qed_dev *cdev,
1408 struct qed_filter_ucast *p_filter_cmd,
1409 enum spq_mode comp_mode,
1410 struct qed_spq_comp_cb *p_comp_data)
1411{
1412 int rc = 0;
1413 int i;
1414
1415 for_each_hwfn(cdev, i) {
1416 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1417 u16 opaque_fid;
1418
dacd88d6
YM		 1419 if (IS_VF(cdev)) {
1420 rc = qed_vf_pf_filter_ucast(p_hwfn, p_filter_cmd);
1421 continue;
1422 }
cee4d264
MC		 1423
1424 opaque_fid = p_hwfn->hw_info.opaque_fid;
1425
1426 rc = qed_sp_eth_filter_ucast(p_hwfn,
1427 opaque_fid,
1428 p_filter_cmd,
1a635e48
YM		 1429 comp_mode, p_comp_data);
1430 if (rc)
dacd88d6 1431 break;
cee4d264
MC		 1432 }
1433
1434 return rc;
1435}
1436
86622ee7
YM		 1437/* Statistics related code */
1438static void __qed_get_vport_pstats_addrlen(struct qed_hwfn *p_hwfn,
1439 u32 *p_addr,
dacd88d6 1440 u32 *p_len, u16 statistics_bin)
86622ee7 1441{
dacd88d6
YM		 1442 if (IS_PF(p_hwfn->cdev)) {
1443 *p_addr = BAR0_MAP_REG_PSDM_RAM +
1444 PSTORM_QUEUE_STAT_OFFSET(statistics_bin);
1445 *p_len = sizeof(struct eth_pstorm_per_queue_stat);
1446 } else {
1447 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
1448 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1449
1450 *p_addr = p_resp->pfdev_info.stats_info.pstats.address;
1451 *p_len = p_resp->pfdev_info.stats_info.pstats.len;
1452 }
86622ee7
YM		 1453}
1454
1455static void __qed_get_vport_pstats(struct qed_hwfn *p_hwfn,
1456 struct qed_ptt *p_ptt,
1457 struct qed_eth_stats *p_stats,
1458 u16 statistics_bin)
1459{
1460 struct eth_pstorm_per_queue_stat pstats;
1461 u32 pstats_addr = 0, pstats_len = 0;
1462
1463 __qed_get_vport_pstats_addrlen(p_hwfn, &pstats_addr, &pstats_len,
1464 statistics_bin);
1465
1466 memset(&pstats, 0, sizeof(pstats));
dacd88d6
YM		 1467 qed_memcpy_from(p_hwfn, p_ptt, &pstats, pstats_addr, pstats_len);
1468
9c79ddaa
MY		 1469 p_stats->common.tx_ucast_bytes +=
1470 HILO_64_REGPAIR(pstats.sent_ucast_bytes);
1471 p_stats->common.tx_mcast_bytes +=
1472 HILO_64_REGPAIR(pstats.sent_mcast_bytes);
1473 p_stats->common.tx_bcast_bytes +=
1474 HILO_64_REGPAIR(pstats.sent_bcast_bytes);
1475 p_stats->common.tx_ucast_pkts +=
1476 HILO_64_REGPAIR(pstats.sent_ucast_pkts);
1477 p_stats->common.tx_mcast_pkts +=
1478 HILO_64_REGPAIR(pstats.sent_mcast_pkts);
1479 p_stats->common.tx_bcast_pkts +=
1480 HILO_64_REGPAIR(pstats.sent_bcast_pkts);
1481 p_stats->common.tx_err_drop_pkts +=
1482 HILO_64_REGPAIR(pstats.error_drop_pkts);
86622ee7
YM		 1483}
1484
1485static void __qed_get_vport_tstats(struct qed_hwfn *p_hwfn,
1486 struct qed_ptt *p_ptt,
1487 struct qed_eth_stats *p_stats,
1488 u16 statistics_bin)
1489{
86622ee7 1490 struct tstorm_per_port_stat tstats;
dacd88d6 1491 u32 tstats_addr, tstats_len;
86622ee7 1492
dacd88d6
YM		 1493 if (IS_PF(p_hwfn->cdev)) {
1494 tstats_addr = BAR0_MAP_REG_TSDM_RAM +
1495 TSTORM_PORT_STAT_OFFSET(MFW_PORT(p_hwfn));
1496 tstats_len = sizeof(struct tstorm_per_port_stat);
1497 } else {
1498 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
1499 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1500
1501 tstats_addr = p_resp->pfdev_info.stats_info.tstats.address;
1502 tstats_len = p_resp->pfdev_info.stats_info.tstats.len;
1503 }
86622ee7
YM		 1504
1505 memset(&tstats, 0, sizeof(tstats));
dacd88d6 1506 qed_memcpy_from(p_hwfn, p_ptt, &tstats, tstats_addr, tstats_len);
86622ee7 1507
9c79ddaa
MY		 1508 p_stats->common.mftag_filter_discards +=
1509 HILO_64_REGPAIR(tstats.mftag_filter_discard);
1510 p_stats->common.mac_filter_discards +=
1511 HILO_64_REGPAIR(tstats.eth_mac_filter_discard);
86622ee7
YM		 1512}
1513
1514static void __qed_get_vport_ustats_addrlen(struct qed_hwfn *p_hwfn,
1515 u32 *p_addr,
dacd88d6 1516 u32 *p_len, u16 statistics_bin)
86622ee7 1517{
dacd88d6
YM		 1518 if (IS_PF(p_hwfn->cdev)) {
1519 *p_addr = BAR0_MAP_REG_USDM_RAM +
1520 USTORM_QUEUE_STAT_OFFSET(statistics_bin);
1521 *p_len = sizeof(struct eth_ustorm_per_queue_stat);
1522 } else {
1523 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
1524 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1525
1526 *p_addr = p_resp->pfdev_info.stats_info.ustats.address;
1527 *p_len = p_resp->pfdev_info.stats_info.ustats.len;
1528 }
86622ee7
YM		 1529}
1530
1531static void __qed_get_vport_ustats(struct qed_hwfn *p_hwfn,
1532 struct qed_ptt *p_ptt,
1533 struct qed_eth_stats *p_stats,
1534 u16 statistics_bin)
1535{
1536 struct eth_ustorm_per_queue_stat ustats;
1537 u32 ustats_addr = 0, ustats_len = 0;
1538
1539 __qed_get_vport_ustats_addrlen(p_hwfn, &ustats_addr, &ustats_len,
1540 statistics_bin);
1541
1542 memset(&ustats, 0, sizeof(ustats));
dacd88d6
YM		 1543 qed_memcpy_from(p_hwfn, p_ptt, &ustats, ustats_addr, ustats_len);
1544
9c79ddaa
MY		 1545 p_stats->common.rx_ucast_bytes +=
1546 HILO_64_REGPAIR(ustats.rcv_ucast_bytes);
1547 p_stats->common.rx_mcast_bytes +=
1548 HILO_64_REGPAIR(ustats.rcv_mcast_bytes);
1549 p_stats->common.rx_bcast_bytes +=
1550 HILO_64_REGPAIR(ustats.rcv_bcast_bytes);
1551 p_stats->common.rx_ucast_pkts += HILO_64_REGPAIR(ustats.rcv_ucast_pkts);
1552 p_stats->common.rx_mcast_pkts += HILO_64_REGPAIR(ustats.rcv_mcast_pkts);
1553 p_stats->common.rx_bcast_pkts += HILO_64_REGPAIR(ustats.rcv_bcast_pkts);
86622ee7
YM		 1554}
1555
1556static void __qed_get_vport_mstats_addrlen(struct qed_hwfn *p_hwfn,
1557 u32 *p_addr,
dacd88d6 1558 u32 *p_len, u16 statistics_bin)
86622ee7 1559{
dacd88d6
YM		 1560 if (IS_PF(p_hwfn->cdev)) {
1561 *p_addr = BAR0_MAP_REG_MSDM_RAM +
1562 MSTORM_QUEUE_STAT_OFFSET(statistics_bin);
1563 *p_len = sizeof(struct eth_mstorm_per_queue_stat);
1564 } else {
1565 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
1566 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1567
1568 *p_addr = p_resp->pfdev_info.stats_info.mstats.address;
1569 *p_len = p_resp->pfdev_info.stats_info.mstats.len;
1570 }
86622ee7
YM		 1571}
1572
1573static void __qed_get_vport_mstats(struct qed_hwfn *p_hwfn,
1574 struct qed_ptt *p_ptt,
1575 struct qed_eth_stats *p_stats,
1576 u16 statistics_bin)
1577{
1578 struct eth_mstorm_per_queue_stat mstats;
1579 u32 mstats_addr = 0, mstats_len = 0;
1580
1581 __qed_get_vport_mstats_addrlen(p_hwfn, &mstats_addr, &mstats_len,
1582 statistics_bin);
1583
1584 memset(&mstats, 0, sizeof(mstats));
dacd88d6 1585 qed_memcpy_from(p_hwfn, p_ptt, &mstats, mstats_addr, mstats_len);
86622ee7 1586
9c79ddaa
MY		 1587 p_stats->common.no_buff_discards +=
1588 HILO_64_REGPAIR(mstats.no_buff_discard);
1589 p_stats->common.packet_too_big_discard +=
1590 HILO_64_REGPAIR(mstats.packet_too_big_discard);
1591 p_stats->common.ttl0_discard += HILO_64_REGPAIR(mstats.ttl0_discard);
1592 p_stats->common.tpa_coalesced_pkts +=
1593 HILO_64_REGPAIR(mstats.tpa_coalesced_pkts);
1594 p_stats->common.tpa_coalesced_events +=
1595 HILO_64_REGPAIR(mstats.tpa_coalesced_events);
1596 p_stats->common.tpa_aborts_num +=
1597 HILO_64_REGPAIR(mstats.tpa_aborts_num);
1598 p_stats->common.tpa_coalesced_bytes +=
1599 HILO_64_REGPAIR(mstats.tpa_coalesced_bytes);
86622ee7
YM		 1600}
1601
1602static void __qed_get_vport_port_stats(struct qed_hwfn *p_hwfn,
1603 struct qed_ptt *p_ptt,
1604 struct qed_eth_stats *p_stats)
1605{
9c79ddaa 1606 struct qed_eth_stats_common *p_common = &p_stats->common;
86622ee7
YM		 1607 struct port_stats port_stats;
1608 int j;
1609
1610 memset(&port_stats, 0, sizeof(port_stats));
1611
1612 qed_memcpy_from(p_hwfn, p_ptt, &port_stats,
1613 p_hwfn->mcp_info->port_addr +
1614 offsetof(struct public_port, stats),
1615 sizeof(port_stats));
1616
9c79ddaa
MY		 1617 p_common->rx_64_byte_packets += port_stats.eth.r64;
1618 p_common->rx_65_to_127_byte_packets += port_stats.eth.r127;
1619 p_common->rx_128_to_255_byte_packets += port_stats.eth.r255;
1620 p_common->rx_256_to_511_byte_packets += port_stats.eth.r511;
1621 p_common->rx_512_to_1023_byte_packets += port_stats.eth.r1023;
1622 p_common->rx_1024_to_1518_byte_packets += port_stats.eth.r1518;
1623 p_common->rx_crc_errors += port_stats.eth.rfcs;
1624 p_common->rx_mac_crtl_frames += port_stats.eth.rxcf;
1625 p_common->rx_pause_frames += port_stats.eth.rxpf;
1626 p_common->rx_pfc_frames += port_stats.eth.rxpp;
1627 p_common->rx_align_errors += port_stats.eth.raln;
1628 p_common->rx_carrier_errors += port_stats.eth.rfcr;
1629 p_common->rx_oversize_packets += port_stats.eth.rovr;
1630 p_common->rx_jabbers += port_stats.eth.rjbr;
1631 p_common->rx_undersize_packets += port_stats.eth.rund;
1632 p_common->rx_fragments += port_stats.eth.rfrg;
1633 p_common->tx_64_byte_packets += port_stats.eth.t64;
1634 p_common->tx_65_to_127_byte_packets += port_stats.eth.t127;
1635 p_common->tx_128_to_255_byte_packets += port_stats.eth.t255;
1636 p_common->tx_256_to_511_byte_packets += port_stats.eth.t511;
1637 p_common->tx_512_to_1023_byte_packets += port_stats.eth.t1023;
1638 p_common->tx_1024_to_1518_byte_packets += port_stats.eth.t1518;
1639 p_common->tx_pause_frames += port_stats.eth.txpf;
1640 p_common->tx_pfc_frames += port_stats.eth.txpp;
1641 p_common->rx_mac_bytes += port_stats.eth.rbyte;
1642 p_common->rx_mac_uc_packets += port_stats.eth.rxuca;
1643 p_common->rx_mac_mc_packets += port_stats.eth.rxmca;
1644 p_common->rx_mac_bc_packets += port_stats.eth.rxbca;
1645 p_common->rx_mac_frames_ok += port_stats.eth.rxpok;
1646 p_common->tx_mac_bytes += port_stats.eth.tbyte;
1647 p_common->tx_mac_uc_packets += port_stats.eth.txuca;
1648 p_common->tx_mac_mc_packets += port_stats.eth.txmca;
1649 p_common->tx_mac_bc_packets += port_stats.eth.txbca;
1650 p_common->tx_mac_ctrl_frames += port_stats.eth.txcf;
86622ee7 1651 for (j = 0; j < 8; j++) {
9c79ddaa
MY		 1652 p_common->brb_truncates += port_stats.brb.brb_truncate[j];
1653 p_common->brb_discards += port_stats.brb.brb_discard[j];
1654 }
1655
1656 if (QED_IS_BB(p_hwfn->cdev)) {
1657 struct qed_eth_stats_bb *p_bb = &p_stats->bb;
1658
1659 p_bb->rx_1519_to_1522_byte_packets +=
1660 port_stats.eth.u0.bb0.r1522;
1661 p_bb->rx_1519_to_2047_byte_packets +=
1662 port_stats.eth.u0.bb0.r2047;
1663 p_bb->rx_2048_to_4095_byte_packets +=
1664 port_stats.eth.u0.bb0.r4095;
1665 p_bb->rx_4096_to_9216_byte_packets +=
1666 port_stats.eth.u0.bb0.r9216;
1667 p_bb->rx_9217_to_16383_byte_packets +=
1668 port_stats.eth.u0.bb0.r16383;
1669 p_bb->tx_1519_to_2047_byte_packets +=
1670 port_stats.eth.u1.bb1.t2047;
1671 p_bb->tx_2048_to_4095_byte_packets +=
1672 port_stats.eth.u1.bb1.t4095;
1673 p_bb->tx_4096_to_9216_byte_packets +=
1674 port_stats.eth.u1.bb1.t9216;
1675 p_bb->tx_9217_to_16383_byte_packets +=
1676 port_stats.eth.u1.bb1.t16383;
1677 p_bb->tx_lpi_entry_count += port_stats.eth.u2.bb2.tlpiec;
1678 p_bb->tx_total_collisions += port_stats.eth.u2.bb2.tncl;
1679 } else {
1680 struct qed_eth_stats_ah *p_ah = &p_stats->ah;
1681
1682 p_ah->rx_1519_to_max_byte_packets +=
1683 port_stats.eth.u0.ah0.r1519_to_max;
1684 p_ah->tx_1519_to_max_byte_packets =
1685 port_stats.eth.u1.ah1.t1519_to_max;
86622ee7
YM		 1686 }
1687}
1688
1689static void __qed_get_vport_stats(struct qed_hwfn *p_hwfn,
1690 struct qed_ptt *p_ptt,
1691 struct qed_eth_stats *stats,
dacd88d6 1692 u16 statistics_bin, bool b_get_port_stats)
86622ee7
YM		 1693{
1694 __qed_get_vport_mstats(p_hwfn, p_ptt, stats, statistics_bin);
1695 __qed_get_vport_ustats(p_hwfn, p_ptt, stats, statistics_bin);
1696 __qed_get_vport_tstats(p_hwfn, p_ptt, stats, statistics_bin);
1697 __qed_get_vport_pstats(p_hwfn, p_ptt, stats, statistics_bin);
1698
dacd88d6 1699 if (b_get_port_stats && p_hwfn->mcp_info)
86622ee7
YM		 1700 __qed_get_vport_port_stats(p_hwfn, p_ptt, stats);
1701}
1702
1703static void _qed_get_vport_stats(struct qed_dev *cdev,
1704 struct qed_eth_stats *stats)
1705{
dacd88d6
YM		 1706 u8 fw_vport = 0;
1707 int i;
86622ee7
YM		 1708
1709 memset(stats, 0, sizeof(*stats));
1710
1711 for_each_hwfn(cdev, i) {
1712 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
dacd88d6
YM		 1713 struct qed_ptt *p_ptt = IS_PF(cdev) ? qed_ptt_acquire(p_hwfn)
1714 : NULL;
1715
1716 if (IS_PF(cdev)) {
1717 /* The main vport index is relative first */
1718 if (qed_fw_vport(p_hwfn, 0, &fw_vport)) {
1719 DP_ERR(p_hwfn, "No vport available!\n");
1720 goto out;
1721 }
86622ee7
YM		 1722 }
1723
dacd88d6 1724 if (IS_PF(cdev) && !p_ptt) {
86622ee7
YM		 1725 DP_ERR(p_hwfn, "Failed to acquire ptt\n");
1726 continue;
1727 }
1728
dacd88d6
YM		 1729 __qed_get_vport_stats(p_hwfn, p_ptt, stats, fw_vport,
1730 IS_PF(cdev) ? true : false);
86622ee7 1731
dacd88d6
YM		 1732out:
1733 if (IS_PF(cdev) && p_ptt)
1734 qed_ptt_release(p_hwfn, p_ptt);
86622ee7
YM		 1735 }
1736}
1737
1a635e48 1738void qed_get_vport_stats(struct qed_dev *cdev, struct qed_eth_stats *stats)
86622ee7
YM		 1739{
1740 u32 i;
1741
1742 if (!cdev) {
1743 memset(stats, 0, sizeof(*stats));
1744 return;
1745 }
1746
1747 _qed_get_vport_stats(cdev, stats);
1748
1749 if (!cdev->reset_stats)
1750 return;
1751
1752 /* Reduce the statistics baseline */
1753 for (i = 0; i < sizeof(struct qed_eth_stats) / sizeof(u64); i++)
1754 ((u64 *)stats)[i] -= ((u64 *)cdev->reset_stats)[i];
1755}
1756
1757/* zeroes V-PORT specific portion of stats (Port stats remains untouched) */
1758void qed_reset_vport_stats(struct qed_dev *cdev)
1759{
1760 int i;
1761
1762 for_each_hwfn(cdev, i) {
1763 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1764 struct eth_mstorm_per_queue_stat mstats;
1765 struct eth_ustorm_per_queue_stat ustats;
1766 struct eth_pstorm_per_queue_stat pstats;
dacd88d6
YM		 1767 struct qed_ptt *p_ptt = IS_PF(cdev) ? qed_ptt_acquire(p_hwfn)
1768 : NULL;
86622ee7
YM		 1769 u32 addr = 0, len = 0;
1770
dacd88d6 1771 if (IS_PF(cdev) && !p_ptt) {
86622ee7
YM		 1772 DP_ERR(p_hwfn, "Failed to acquire ptt\n");
1773 continue;
1774 }
1775
1776 memset(&mstats, 0, sizeof(mstats));
1777 __qed_get_vport_mstats_addrlen(p_hwfn, &addr, &len, 0);
1778 qed_memcpy_to(p_hwfn, p_ptt, addr, &mstats, len);
1779
1780 memset(&ustats, 0, sizeof(ustats));
1781 __qed_get_vport_ustats_addrlen(p_hwfn, &addr, &len, 0);
1782 qed_memcpy_to(p_hwfn, p_ptt, addr, &ustats, len);
1783
1784 memset(&pstats, 0, sizeof(pstats));
1785 __qed_get_vport_pstats_addrlen(p_hwfn, &addr, &len, 0);
1786 qed_memcpy_to(p_hwfn, p_ptt, addr, &pstats, len);
1787
dacd88d6
YM		 1788 if (IS_PF(cdev))
1789 qed_ptt_release(p_hwfn, p_ptt);
86622ee7
YM		 1790 }
1791
1792 /* PORT statistics are not necessarily reset, so we need to
1793 * read and create a baseline for future statistics.
1794 */
1795 if (!cdev->reset_stats)
1796 DP_INFO(cdev, "Reset stats not allocated\n");
1797 else
1798 _qed_get_vport_stats(cdev, cdev->reset_stats);
1799}
1800
d51e4af5
CM		 1801static void
1802qed_arfs_mode_configure(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
1803 struct qed_arfs_config_params *p_cfg_params)
1804{
1805 if (p_cfg_params->arfs_enable) {
1806 qed_set_rfs_mode_enable(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
1807 p_cfg_params->tcp, p_cfg_params->udp,
1808 p_cfg_params->ipv4, p_cfg_params->ipv6);
1809 DP_VERBOSE(p_hwfn, QED_MSG_SP,
1810 "tcp = %s, udp = %s, ipv4 = %s, ipv6 =%s\n",
1811 p_cfg_params->tcp ? "Enable" : "Disable",
1812 p_cfg_params->udp ? "Enable" : "Disable",
1813 p_cfg_params->ipv4 ? "Enable" : "Disable",
1814 p_cfg_params->ipv6 ? "Enable" : "Disable");
1815 } else {
1816 qed_set_rfs_mode_disable(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1817 }
1818
1819 DP_VERBOSE(p_hwfn, QED_MSG_SP, "Configured ARFS mode : %s\n",
1820 p_cfg_params->arfs_enable ? "Enable" : "Disable");
1821}
1822
1823static int
1824qed_configure_rfs_ntuple_filter(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
1825 struct qed_spq_comp_cb *p_cb,
1826 dma_addr_t p_addr, u16 length, u16 qid,
1827 u8 vport_id, bool b_is_add)
1828{
1829 struct rx_update_gft_filter_data *p_ramrod = NULL;
1830 struct qed_spq_entry *p_ent = NULL;
1831 struct qed_sp_init_data init_data;
1832 u16 abs_rx_q_id = 0;
1833 u8 abs_vport_id = 0;
1834 int rc = -EINVAL;
1835
1836 rc = qed_fw_vport(p_hwfn, vport_id, &abs_vport_id);
1837 if (rc)
1838 return rc;
1839
1840 rc = qed_fw_l2_queue(p_hwfn, qid, &abs_rx_q_id);
1841 if (rc)
1842 return rc;
1843
1844 /* Get SPQ entry */
1845 memset(&init_data, 0, sizeof(init_data));
1846 init_data.cid = qed_spq_get_cid(p_hwfn);
1847
1848 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
1849
1850 if (p_cb) {
1851 init_data.comp_mode = QED_SPQ_MODE_CB;
1852 init_data.p_comp_data = p_cb;
1853 } else {
1854 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
1855 }
1856
1857 rc = qed_sp_init_request(p_hwfn, &p_ent,
1858 ETH_RAMROD_GFT_UPDATE_FILTER,
1859 PROTOCOLID_ETH, &init_data);
1860 if (rc)
1861 return rc;
1862
1863 p_ramrod = &p_ent->ramrod.rx_update_gft;
1864 DMA_REGPAIR_LE(p_ramrod->pkt_hdr_addr, p_addr);
1865 p_ramrod->pkt_hdr_length = cpu_to_le16(length);
1866 p_ramrod->rx_qid_or_action_icid = cpu_to_le16(abs_rx_q_id);
1867 p_ramrod->vport_id = abs_vport_id;
1868 p_ramrod->filter_type = RFS_FILTER_TYPE;
1869 p_ramrod->filter_action = b_is_add ? GFT_ADD_FILTER : GFT_DELETE_FILTER;
1870
1871 DP_VERBOSE(p_hwfn, QED_MSG_SP,
1872 "V[%0x], Q[%04x] - %s filter from 0x%llx [length %04xb]\n",
1873 abs_vport_id, abs_rx_q_id,
1874 b_is_add ? "Adding" : "Removing", (u64)p_addr, length);
1875
1876 return qed_spq_post(p_hwfn, p_ent, NULL);
1877}
1878
25c089d7
YM		 1879static int qed_fill_eth_dev_info(struct qed_dev *cdev,
1880 struct qed_dev_eth_info *info)
1881{
1882 int i;
1883
1884 memset(info, 0, sizeof(*info));
1885
1886 info->num_tc = 1;
1887
1408cc1f 1888 if (IS_PF(cdev)) {
25eb8d46 1889 int max_vf_vlan_filters = 0;
7b7e70f9 1890 int max_vf_mac_filters = 0;
25eb8d46 1891
1408cc1f 1892 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
e1d32acb
MY		 1893 u16 num_queues = 0;
1894
1895 /* Since the feature controls only queue-zones,
1896 * make sure we have the contexts [rx, tx, xdp] to
1897 * match.
1898 */
1899 for_each_hwfn(cdev, i) {
1900 struct qed_hwfn *hwfn = &cdev->hwfns[i];
1901 u16 l2_queues = (u16)FEAT_NUM(hwfn,
1902 QED_PF_L2_QUE);
1903 u16 cids;
1904
1905 cids = hwfn->pf_params.eth_pf_params.num_cons;
1906 num_queues += min_t(u16, l2_queues, cids / 3);
1907 }
1908
1909 /* queues might theoretically be >256, but interrupts'
1910 * upper-limit guarantes that it would fit in a u8.
1911 */
1912 if (cdev->int_params.fp_msix_cnt) {
1913 u8 irqs = cdev->int_params.fp_msix_cnt;
1914
1915 info->num_queues = (u8)min_t(u16,
1916 num_queues, irqs);
1917 }
1408cc1f
YM		 1918 } else {
1919 info->num_queues = cdev->num_hwfns;
1920 }
1921
7b7e70f9 1922 if (IS_QED_SRIOV(cdev)) {
25eb8d46
YM		 1923 max_vf_vlan_filters = cdev->p_iov_info->total_vfs *
1924 QED_ETH_VF_NUM_VLAN_FILTERS;
7b7e70f9
YM		 1925 max_vf_mac_filters = cdev->p_iov_info->total_vfs *
1926 QED_ETH_VF_NUM_MAC_FILTERS;
1927 }
1928 info->num_vlan_filters = RESC_NUM(QED_LEADING_HWFN(cdev),
1929 QED_VLAN) -
25eb8d46 1930 max_vf_vlan_filters;
7b7e70f9
YM		 1931 info->num_mac_filters = RESC_NUM(QED_LEADING_HWFN(cdev),
1932 QED_MAC) -
1933 max_vf_mac_filters;
25eb8d46 1934
1408cc1f
YM		 1935 ether_addr_copy(info->port_mac,
1936 cdev->hwfns[0].hw_info.hw_mac_addr);
25c089d7 1937 } else {
1408cc1f
YM		 1938 qed_vf_get_num_rxqs(QED_LEADING_HWFN(cdev), &info->num_queues);
1939 if (cdev->num_hwfns > 1) {
1940 u8 queues = 0;
25c089d7 1941
1408cc1f
YM		 1942 qed_vf_get_num_rxqs(&cdev->hwfns[1], &queues);
1943 info->num_queues += queues;
1944 }
1945
1946 qed_vf_get_num_vlan_filters(&cdev->hwfns[0],
2edbff8d 1947 (u8 *)&info->num_vlan_filters);
b0fca312
MY		 1948 qed_vf_get_num_mac_filters(&cdev->hwfns[0],
1949 (u8 *)&info->num_mac_filters);
1408cc1f 1950 qed_vf_get_port_mac(&cdev->hwfns[0], info->port_mac);
d8c2c7e3
YM		 1951
1952 info->is_legacy = !!cdev->hwfns[0].vf_iov_info->b_pre_fp_hsi;
1408cc1f 1953 }
25c089d7
YM		 1954
1955 qed_fill_dev_info(cdev, &info->common);
1956
1408cc1f 1957 if (IS_VF(cdev))
0ee28e31 1958 eth_zero_addr(info->common.hw_mac);
1408cc1f 1959
25c089d7
YM		 1960 return 0;
1961}
1962
cc875c2e 1963static void qed_register_eth_ops(struct qed_dev *cdev,
1408cc1f 1964 struct qed_eth_cb_ops *ops, void *cookie)
cc875c2e 1965{
1408cc1f
YM		 1966 cdev->protocol_ops.eth = ops;
1967 cdev->ops_cookie = cookie;
1968
1969 /* For VF, we start bulletin reading */
1970 if (IS_VF(cdev))
1971 qed_vf_start_iov_wq(cdev);
cc875c2e
YM		 1972}
1973
eff16960
YM		 1974static bool qed_check_mac(struct qed_dev *cdev, u8 *mac)
1975{
1976 if (IS_PF(cdev))
1977 return true;
1978
1979 return qed_vf_check_mac(&cdev->hwfns[0], mac);
1980}
1981
cee4d264 1982static int qed_start_vport(struct qed_dev *cdev,
088c8618 1983 struct qed_start_vport_params *params)
cee4d264
MC		 1984{
1985 int rc, i;
1986
1987 for_each_hwfn(cdev, i) {
088c8618 1988 struct qed_sp_vport_start_params start = { 0 };
cee4d264
MC		 1989 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1990
088c8618
MC		 1991 start.tpa_mode = params->gro_enable ? QED_TPA_MODE_GRO :
1992 QED_TPA_MODE_NONE;
1993 start.remove_inner_vlan = params->remove_inner_vlan;
08feecd7 1994 start.only_untagged = true; /* untagged only */
088c8618
MC		 1995 start.drop_ttl0 = params->drop_ttl0;
1996 start.opaque_fid = p_hwfn->hw_info.opaque_fid;
1997 start.concrete_fid = p_hwfn->hw_info.concrete_fid;
c78c70fa 1998 start.handle_ptp_pkts = params->handle_ptp_pkts;
088c8618
MC		 1999 start.vport_id = params->vport_id;
2000 start.max_buffers_per_cqe = 16;
2001 start.mtu = params->mtu;
2002
2003 rc = qed_sp_vport_start(p_hwfn, &start);
cee4d264
MC		 2004 if (rc) {
2005 DP_ERR(cdev, "Failed to start VPORT\n");
2006 return rc;
2007 }
2008
15582962
RV		 2009 rc = qed_hw_start_fastpath(p_hwfn);
2010 if (rc) {
2011 DP_ERR(cdev, "Failed to start VPORT fastpath\n");
2012 return rc;
2013 }
cee4d264
MC		 2014
2015 DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
2016 "Started V-PORT %d with MTU %d\n",
088c8618 2017 start.vport_id, start.mtu);
cee4d264
MC		 2018 }
2019
a0d26d5a
YM		 2020 if (params->clear_stats)
2021 qed_reset_vport_stats(cdev);
9df2ed04 2022
cee4d264
MC		 2023 return 0;
2024}
2025
1a635e48 2026static int qed_stop_vport(struct qed_dev *cdev, u8 vport_id)
cee4d264
MC		 2027{
2028 int rc, i;
2029
2030 for_each_hwfn(cdev, i) {
2031 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2032
2033 rc = qed_sp_vport_stop(p_hwfn,
1a635e48 2034 p_hwfn->hw_info.opaque_fid, vport_id);
cee4d264
MC		 2035
2036 if (rc) {
2037 DP_ERR(cdev, "Failed to stop VPORT\n");
2038 return rc;
2039 }
2040 }
2041 return 0;
2042}
2043
f29ffdb6
MY		 2044static int qed_update_vport_rss(struct qed_dev *cdev,
2045 struct qed_update_vport_rss_params *input,
2046 struct qed_rss_params *rss)
2047{
2048 int i, fn;
2049
2050 /* Update configuration with what's correct regardless of CMT */
2051 rss->update_rss_config = 1;
2052 rss->rss_enable = 1;
2053 rss->update_rss_capabilities = 1;
2054 rss->update_rss_ind_table = 1;
2055 rss->update_rss_key = 1;
2056 rss->rss_caps = input->rss_caps;
2057 memcpy(rss->rss_key, input->rss_key, QED_RSS_KEY_SIZE * sizeof(u32));
2058
2059 /* In regular scenario, we'd simply need to take input handlers.
2060 * But in CMT, we'd have to split the handlers according to the
2061 * engine they were configured on. We'd then have to understand
2062 * whether RSS is really required, since 2-queues on CMT doesn't
2063 * require RSS.
2064 */
2065 if (cdev->num_hwfns == 1) {
2066 memcpy(rss->rss_ind_table,
2067 input->rss_ind_table,
2068 QED_RSS_IND_TABLE_SIZE * sizeof(void *));
2069 rss->rss_table_size_log = 7;
2070 return 0;
2071 }
2072
2073 /* Start by copying the non-spcific information to the 2nd copy */
2074 memcpy(&rss[1], &rss[0], sizeof(struct qed_rss_params));
2075
2076 /* CMT should be round-robin */
2077 for (i = 0; i < QED_RSS_IND_TABLE_SIZE; i++) {
2078 struct qed_queue_cid *cid = input->rss_ind_table[i];
2079 struct qed_rss_params *t_rss;
2080
2081 if (cid->p_owner == QED_LEADING_HWFN(cdev))
2082 t_rss = &rss[0];
2083 else
2084 t_rss = &rss[1];
2085
2086 t_rss->rss_ind_table[i / cdev->num_hwfns] = cid;
2087 }
2088
2089 /* Make sure RSS is actually required */
2090 for_each_hwfn(cdev, fn) {
2091 for (i = 1; i < QED_RSS_IND_TABLE_SIZE / cdev->num_hwfns; i++) {
2092 if (rss[fn].rss_ind_table[i] !=
2093 rss[fn].rss_ind_table[0])
2094 break;
2095 }
2096 if (i == QED_RSS_IND_TABLE_SIZE / cdev->num_hwfns) {
2097 DP_VERBOSE(cdev, NETIF_MSG_IFUP,
2098 "CMT - 1 queue per-hwfn; Disabling RSS\n");
2099 return -EINVAL;
2100 }
2101 rss[fn].rss_table_size_log = 6;
2102 }
2103
2104 return 0;
2105}
2106
cee4d264
MC		 2107static int qed_update_vport(struct qed_dev *cdev,
2108 struct qed_update_vport_params *params)
2109{
2110 struct qed_sp_vport_update_params sp_params;
f29ffdb6
MY		 2111 struct qed_rss_params *rss;
2112 int rc = 0, i;
cee4d264
MC		 2113
2114 if (!cdev)
2115 return -ENODEV;
2116
f29ffdb6
MY		 2117 rss = vzalloc(sizeof(*rss) * cdev->num_hwfns);
2118 if (!rss)
2119 return -ENOMEM;
2120
cee4d264 2121 memset(&sp_params, 0, sizeof(sp_params));
cee4d264
MC		 2122
2123 /* Translate protocol params into sp params */
2124 sp_params.vport_id = params->vport_id;
1a635e48
YM		 2125 sp_params.update_vport_active_rx_flg = params->update_vport_active_flg;
2126 sp_params.update_vport_active_tx_flg = params->update_vport_active_flg;
cee4d264
MC		 2127 sp_params.vport_active_rx_flg = params->vport_active_flg;
2128 sp_params.vport_active_tx_flg = params->vport_active_flg;
831bfb0e
YM		 2129 sp_params.update_tx_switching_flg = params->update_tx_switching_flg;
2130 sp_params.tx_switching_flg = params->tx_switching_flg;
3f9b4a69
YM		 2131 sp_params.accept_any_vlan = params->accept_any_vlan;
2132 sp_params.update_accept_any_vlan_flg =
2133 params->update_accept_any_vlan_flg;
cee4d264 2134
f29ffdb6
MY		 2135 /* Prepare the RSS configuration */
2136 if (params->update_rss_flg)
2137 if (qed_update_vport_rss(cdev, &params->rss_params, rss))
cee4d264 2138 params->update_rss_flg = 0;
cee4d264
MC		 2139
2140 for_each_hwfn(cdev, i) {
2141 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2142
f29ffdb6
MY		 2143 if (params->update_rss_flg)
2144 sp_params.rss_params = &rss[i];
2145
cee4d264
MC		 2146 sp_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2147 rc = qed_sp_vport_update(p_hwfn, &sp_params,
2148 QED_SPQ_MODE_EBLOCK,
2149 NULL);
2150 if (rc) {
2151 DP_ERR(cdev, "Failed to update VPORT\n");
f29ffdb6 2152 goto out;
cee4d264
MC		 2153 }
2154
2155 DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
2156 "Updated V-PORT %d: active_flag %d [update %d]\n",
2157 params->vport_id, params->vport_active_flg,
2158 params->update_vport_active_flg);
2159 }
2160
f29ffdb6
MY		 2161out:
2162 vfree(rss);
2163 return rc;
cee4d264
MC		 2164}
2165
2166static int qed_start_rxq(struct qed_dev *cdev,
3da7a37a
MY		 2167 u8 rss_num,
2168 struct qed_queue_start_common_params *p_params,
cee4d264
MC		 2169 u16 bd_max_bytes,
2170 dma_addr_t bd_chain_phys_addr,
2171 dma_addr_t cqe_pbl_addr,
2172 u16 cqe_pbl_size,
3da7a37a 2173 struct qed_rxq_start_ret_params *ret_params)
cee4d264 2174{
cee4d264 2175 struct qed_hwfn *p_hwfn;
1a635e48 2176 int rc, hwfn_index;
cee4d264 2177
3da7a37a 2178 hwfn_index = rss_num % cdev->num_hwfns;
cee4d264
MC		 2179 p_hwfn = &cdev->hwfns[hwfn_index];
2180
3da7a37a
MY		 2181 p_params->queue_id = p_params->queue_id / cdev->num_hwfns;
2182 p_params->stats_id = p_params->vport_id;
cee4d264 2183
3da7a37a
MY		 2184 rc = qed_eth_rx_queue_start(p_hwfn,
2185 p_hwfn->hw_info.opaque_fid,
2186 p_params,
2187 bd_max_bytes,
2188 bd_chain_phys_addr,
2189 cqe_pbl_addr, cqe_pbl_size, ret_params);
cee4d264 2190 if (rc) {
3da7a37a 2191 DP_ERR(cdev, "Failed to start RXQ#%d\n", p_params->queue_id);
cee4d264
MC		 2192 return rc;
2193 }
2194
2195 DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
3da7a37a
MY		 2196 "Started RX-Q %d [rss_num %d] on V-PORT %d and SB %d\n",
2197 p_params->queue_id, rss_num, p_params->vport_id,
2198 p_params->sb);
cee4d264
MC		 2199
2200 return 0;
2201}
2202
3da7a37a 2203static int qed_stop_rxq(struct qed_dev *cdev, u8 rss_id, void *handle)
cee4d264
MC		 2204{
2205 int rc, hwfn_index;
2206 struct qed_hwfn *p_hwfn;
2207
3da7a37a
MY		 2208 hwfn_index = rss_id % cdev->num_hwfns;
2209 p_hwfn = &cdev->hwfns[hwfn_index];
cee4d264 2210
3da7a37a 2211 rc = qed_eth_rx_queue_stop(p_hwfn, handle, false, false);
cee4d264 2212 if (rc) {
3da7a37a 2213 DP_ERR(cdev, "Failed to stop RXQ#%02x\n", rss_id);
cee4d264
MC		 2214 return rc;
2215 }
2216
2217 return 0;
2218}
2219
2220static int qed_start_txq(struct qed_dev *cdev,
3da7a37a 2221 u8 rss_num,
cee4d264
MC		 2222 struct qed_queue_start_common_params *p_params,
2223 dma_addr_t pbl_addr,
2224 u16 pbl_size,
3da7a37a 2225 struct qed_txq_start_ret_params *ret_params)
cee4d264
MC		 2226{
2227 struct qed_hwfn *p_hwfn;
2228 int rc, hwfn_index;
2229
3da7a37a
MY		 2230 hwfn_index = rss_num % cdev->num_hwfns;
2231 p_hwfn = &cdev->hwfns[hwfn_index];
2232 p_params->queue_id = p_params->queue_id / cdev->num_hwfns;
2233 p_params->stats_id = p_params->vport_id;
cee4d264 2234
3da7a37a
MY		 2235 rc = qed_eth_tx_queue_start(p_hwfn,
2236 p_hwfn->hw_info.opaque_fid,
2237 p_params, 0,
2238 pbl_addr, pbl_size, ret_params);
cee4d264
MC		 2239
2240 if (rc) {
2241 DP_ERR(cdev, "Failed to start TXQ#%d\n", p_params->queue_id);
2242 return rc;
2243 }
2244
2245 DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
3da7a37a
MY		 2246 "Started TX-Q %d [rss_num %d] on V-PORT %d and SB %d\n",
2247 p_params->queue_id, rss_num, p_params->vport_id,
cee4d264
MC		 2248 p_params->sb);
2249
2250 return 0;
2251}
2252
2253#define QED_HW_STOP_RETRY_LIMIT (10)
2254static int qed_fastpath_stop(struct qed_dev *cdev)
2255{
15582962
RV		 2256 int rc;
2257
2258 rc = qed_hw_stop_fastpath(cdev);
2259 if (rc) {
2260 DP_ERR(cdev, "Failed to stop Fastpath\n");
2261 return rc;
2262 }
cee4d264
MC		 2263
2264 return 0;
2265}
2266
3da7a37a 2267static int qed_stop_txq(struct qed_dev *cdev, u8 rss_id, void *handle)
cee4d264
MC		 2268{
2269 struct qed_hwfn *p_hwfn;
2270 int rc, hwfn_index;
2271
3da7a37a
MY		 2272 hwfn_index = rss_id % cdev->num_hwfns;
2273 p_hwfn = &cdev->hwfns[hwfn_index];
cee4d264 2274
3da7a37a 2275 rc = qed_eth_tx_queue_stop(p_hwfn, handle);
cee4d264 2276 if (rc) {
3da7a37a 2277 DP_ERR(cdev, "Failed to stop TXQ#%02x\n", rss_id);
cee4d264
MC		 2278 return rc;
2279 }
2280
2281 return 0;
2282}
2283
464f6645
MC		 2284static int qed_tunn_configure(struct qed_dev *cdev,
2285 struct qed_tunn_params *tunn_params)
2286{
19968430 2287 struct qed_tunnel_info tunn_info;
464f6645
MC		 2288 int i, rc;
2289
2290 memset(&tunn_info, 0, sizeof(tunn_info));
19968430
CM		 2291 if (tunn_params->update_vxlan_port) {
2292 tunn_info.vxlan_port.b_update_port = true;
2293 tunn_info.vxlan_port.port = tunn_params->vxlan_port;
464f6645
MC		 2294 }
2295
19968430
CM		 2296 if (tunn_params->update_geneve_port) {
2297 tunn_info.geneve_port.b_update_port = true;
2298 tunn_info.geneve_port.port = tunn_params->geneve_port;
464f6645
MC		 2299 }
2300
2301 for_each_hwfn(cdev, i) {
2302 struct qed_hwfn *hwfn = &cdev->hwfns[i];
97379f15
CM		 2303 struct qed_tunnel_info *tun;
2304
2305 tun = &hwfn->cdev->tunnel;
464f6645
MC		 2306
2307 rc = qed_sp_pf_update_tunn_cfg(hwfn, &tunn_info,
2308 QED_SPQ_MODE_EBLOCK, NULL);
464f6645
MC		 2309 if (rc)
2310 return rc;
97379f15
CM		 2311
2312 if (IS_PF_SRIOV(hwfn)) {
2313 u16 vxlan_port, geneve_port;
2314 int j;
2315
2316 vxlan_port = tun->vxlan_port.port;
2317 geneve_port = tun->geneve_port.port;
2318
2319 qed_for_each_vf(hwfn, j) {
2320 qed_iov_bulletin_set_udp_ports(hwfn, j,
2321 vxlan_port,
2322 geneve_port);
2323 }
2324
2325 qed_schedule_iov(hwfn, QED_IOV_WQ_BULLETIN_UPDATE_FLAG);
2326 }
464f6645
MC		 2327 }
2328
2329 return 0;
2330}
2331
cee4d264
MC		 2332static int qed_configure_filter_rx_mode(struct qed_dev *cdev,
2333 enum qed_filter_rx_mode_type type)
2334{
2335 struct qed_filter_accept_flags accept_flags;
2336
2337 memset(&accept_flags, 0, sizeof(accept_flags));
2338
1a635e48
YM		 2339 accept_flags.update_rx_mode_config = 1;
2340 accept_flags.update_tx_mode_config = 1;
2341 accept_flags.rx_accept_filter = QED_ACCEPT_UCAST_MATCHED |
2342 QED_ACCEPT_MCAST_MATCHED |
2343 QED_ACCEPT_BCAST;
cee4d264
MC		 2344 accept_flags.tx_accept_filter = QED_ACCEPT_UCAST_MATCHED |
2345 QED_ACCEPT_MCAST_MATCHED |
2346 QED_ACCEPT_BCAST;
2347
88067876 2348 if (type == QED_FILTER_RX_MODE_TYPE_PROMISC) {
cee4d264
MC		 2349 accept_flags.rx_accept_filter |= QED_ACCEPT_UCAST_UNMATCHED |
2350 QED_ACCEPT_MCAST_UNMATCHED;
88067876
MY		 2351 accept_flags.tx_accept_filter |= QED_ACCEPT_MCAST_UNMATCHED;
2352 } else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC) {
cee4d264 2353 accept_flags.rx_accept_filter |= QED_ACCEPT_MCAST_UNMATCHED;
88067876
MY		 2354 accept_flags.tx_accept_filter |= QED_ACCEPT_MCAST_UNMATCHED;
2355 }
cee4d264 2356
3f9b4a69 2357 return qed_filter_accept_cmd(cdev, 0, accept_flags, false, false,
cee4d264
MC		 2358 QED_SPQ_MODE_CB, NULL);
2359}
2360
2361static int qed_configure_filter_ucast(struct qed_dev *cdev,
2362 struct qed_filter_ucast_params *params)
2363{
2364 struct qed_filter_ucast ucast;
2365
2366 if (!params->vlan_valid && !params->mac_valid) {
1a635e48
YM		 2367 DP_NOTICE(cdev,
2368 "Tried configuring a unicast filter, but both MAC and VLAN are not set\n");
cee4d264
MC		 2369 return -EINVAL;
2370 }
2371
2372 memset(&ucast, 0, sizeof(ucast));
2373 switch (params->type) {
2374 case QED_FILTER_XCAST_TYPE_ADD:
2375 ucast.opcode = QED_FILTER_ADD;
2376 break;
2377 case QED_FILTER_XCAST_TYPE_DEL:
2378 ucast.opcode = QED_FILTER_REMOVE;
2379 break;
2380 case QED_FILTER_XCAST_TYPE_REPLACE:
2381 ucast.opcode = QED_FILTER_REPLACE;
2382 break;
2383 default:
2384 DP_NOTICE(cdev, "Unknown unicast filter type %d\n",
2385 params->type);
2386 }
2387
2388 if (params->vlan_valid && params->mac_valid) {
2389 ucast.type = QED_FILTER_MAC_VLAN;
2390 ether_addr_copy(ucast.mac, params->mac);
2391 ucast.vlan = params->vlan;
2392 } else if (params->mac_valid) {
2393 ucast.type = QED_FILTER_MAC;
2394 ether_addr_copy(ucast.mac, params->mac);
2395 } else {
2396 ucast.type = QED_FILTER_VLAN;
2397 ucast.vlan = params->vlan;
2398 }
2399
2400 ucast.is_rx_filter = true;
2401 ucast.is_tx_filter = true;
2402
2403 return qed_filter_ucast_cmd(cdev, &ucast, QED_SPQ_MODE_CB, NULL);
2404}
2405
2406static int qed_configure_filter_mcast(struct qed_dev *cdev,
2407 struct qed_filter_mcast_params *params)
2408{
2409 struct qed_filter_mcast mcast;
2410 int i;
2411
2412 memset(&mcast, 0, sizeof(mcast));
2413 switch (params->type) {
2414 case QED_FILTER_XCAST_TYPE_ADD:
2415 mcast.opcode = QED_FILTER_ADD;
2416 break;
2417 case QED_FILTER_XCAST_TYPE_DEL:
2418 mcast.opcode = QED_FILTER_REMOVE;
2419 break;
2420 default:
2421 DP_NOTICE(cdev, "Unknown multicast filter type %d\n",
2422 params->type);
2423 }
2424
2425 mcast.num_mc_addrs = params->num;
2426 for (i = 0; i < mcast.num_mc_addrs; i++)
2427 ether_addr_copy(mcast.mac[i], params->mac[i]);
2428
1a635e48 2429 return qed_filter_mcast_cmd(cdev, &mcast, QED_SPQ_MODE_CB, NULL);
cee4d264
MC		 2430}
2431
2432static int qed_configure_filter(struct qed_dev *cdev,
2433 struct qed_filter_params *params)
2434{
2435 enum qed_filter_rx_mode_type accept_flags;
2436
2437 switch (params->type) {
2438 case QED_FILTER_TYPE_UCAST:
2439 return qed_configure_filter_ucast(cdev, &params->filter.ucast);
2440 case QED_FILTER_TYPE_MCAST:
2441 return qed_configure_filter_mcast(cdev, &params->filter.mcast);
2442 case QED_FILTER_TYPE_RX_MODE:
2443 accept_flags = params->filter.accept_flags;
2444 return qed_configure_filter_rx_mode(cdev, accept_flags);
2445 default:
1a635e48 2446 DP_NOTICE(cdev, "Unknown filter type %d\n", (int)params->type);
cee4d264
MC		 2447 return -EINVAL;
2448 }
2449}
2450
d51e4af5
CM		 2451static int qed_configure_arfs_searcher(struct qed_dev *cdev, bool en_searcher)
2452{
2453 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
2454 struct qed_arfs_config_params arfs_config_params;
2455
2456 memset(&arfs_config_params, 0, sizeof(arfs_config_params));
2457 arfs_config_params.tcp = true;
2458 arfs_config_params.udp = true;
2459 arfs_config_params.ipv4 = true;
2460 arfs_config_params.ipv6 = true;
2461 arfs_config_params.arfs_enable = en_searcher;
2462
2463 qed_arfs_mode_configure(p_hwfn, p_hwfn->p_arfs_ptt,
2464 &arfs_config_params);
2465 return 0;
2466}
2467
2468static void
2469qed_arfs_sp_response_handler(struct qed_hwfn *p_hwfn,
2470 void *cookie, union event_ring_data *data,
2471 u8 fw_return_code)
2472{
2473 struct qed_common_cb_ops *op = p_hwfn->cdev->protocol_ops.common;
2474 void *dev = p_hwfn->cdev->ops_cookie;
2475
2476 op->arfs_filter_op(dev, cookie, fw_return_code);
2477}
2478
2479static int qed_ntuple_arfs_filter_config(struct qed_dev *cdev, void *cookie,
2480 dma_addr_t mapping, u16 length,
2481 u16 vport_id, u16 rx_queue_id,
2482 bool add_filter)
2483{
2484 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
2485 struct qed_spq_comp_cb cb;
2486 int rc = -EINVAL;
2487
2488 cb.function = qed_arfs_sp_response_handler;
2489 cb.cookie = cookie;
2490
2491 rc = qed_configure_rfs_ntuple_filter(p_hwfn, p_hwfn->p_arfs_ptt,
2492 &cb, mapping, length, rx_queue_id,
2493 vport_id, add_filter);
2494 if (rc)
2495 DP_NOTICE(p_hwfn,
2496 "Failed to issue a-RFS filter configuration\n");
2497 else
2498 DP_VERBOSE(p_hwfn, NETIF_MSG_DRV,
2499 "Successfully issued a-RFS filter configuration\n");
2500
2501 return rc;
2502}
2503
cee4d264 2504static int qed_fp_cqe_completion(struct qed_dev *dev,
1a635e48 2505 u8 rss_id, struct eth_slow_path_rx_cqe *cqe)
cee4d264
MC		 2506{
2507 return qed_eth_cqe_completion(&dev->hwfns[rss_id % dev->num_hwfns],
2508 cqe);
2509}
2510
0b55e27d
YM		 2511#ifdef CONFIG_QED_SRIOV
2512extern const struct qed_iov_hv_ops qed_iov_ops_pass;
2513#endif
2514
a1d8d8a5
SRK		 2515#ifdef CONFIG_DCB
2516extern const struct qed_eth_dcbnl_ops qed_dcbnl_ops_pass;
2517#endif
2518
c78c70fa
SRK		 2519extern const struct qed_eth_ptp_ops qed_ptp_ops_pass;
2520
25c089d7
YM		 2521static const struct qed_eth_ops qed_eth_ops_pass = {
2522 .common = &qed_common_ops_pass,
0b55e27d
YM		 2523#ifdef CONFIG_QED_SRIOV
2524 .iov = &qed_iov_ops_pass,
a1d8d8a5
SRK		 2525#endif
2526#ifdef CONFIG_DCB
2527 .dcb = &qed_dcbnl_ops_pass,
0b55e27d 2528#endif
c78c70fa 2529 .ptp = &qed_ptp_ops_pass,
25c089d7 2530 .fill_dev_info = &qed_fill_eth_dev_info,
cc875c2e 2531 .register_ops = &qed_register_eth_ops,
eff16960 2532 .check_mac = &qed_check_mac,
cee4d264
MC		 2533 .vport_start = &qed_start_vport,
2534 .vport_stop = &qed_stop_vport,
2535 .vport_update = &qed_update_vport,
2536 .q_rx_start = &qed_start_rxq,
2537 .q_rx_stop = &qed_stop_rxq,
2538 .q_tx_start = &qed_start_txq,
2539 .q_tx_stop = &qed_stop_txq,
2540 .filter_config = &qed_configure_filter,
2541 .fastpath_stop = &qed_fastpath_stop,
2542 .eth_cqe_completion = &qed_fp_cqe_completion,
9df2ed04 2543 .get_vport_stats = &qed_get_vport_stats,
464f6645 2544 .tunn_config = &qed_tunn_configure,
d51e4af5
CM		 2545 .ntuple_filter_config = &qed_ntuple_arfs_filter_config,
2546 .configure_arfs_searcher = &qed_configure_arfs_searcher,
25c089d7
YM		 2547};
2548
95114344 2549const struct qed_eth_ops *qed_get_eth_ops(void)
25c089d7 2550{
25c089d7
YM		 2551 return &qed_eth_ops_pass;
2552}
2553EXPORT_SYMBOL(qed_get_eth_ops);
2554
2555void qed_put_eth_ops(void)
2556{
2557 /* TODO - reference count for module? */
2558}
2559EXPORT_SYMBOL(qed_put_eth_ops);
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