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qed: Assign a unique per-queue index to queue-cid
[mirror_ubuntu-focal-kernel.git] / drivers / net / ethernet / qlogic / qed / qed_l2.c
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25c089d7 1/* QLogic qed NIC Driver
e8f1cb50 2 * Copyright (c) 2015-2017 QLogic Corporation
25c089d7 3 *
e8f1cb50
MY		 4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
25c089d7
YM		 31 */
32
33#include <linux/types.h>
34#include <asm/byteorder.h>
35#include <asm/param.h>
36#include <linux/delay.h>
37#include <linux/dma-mapping.h>
38#include <linux/etherdevice.h>
39#include <linux/interrupt.h>
40#include <linux/kernel.h>
41#include <linux/module.h>
42#include <linux/pci.h>
43#include <linux/slab.h>
44#include <linux/stddef.h>
45#include <linux/string.h>
25c089d7
YM		 46#include <linux/workqueue.h>
47#include <linux/bitops.h>
48#include <linux/bug.h>
3da7a37a 49#include <linux/vmalloc.h>
25c089d7
YM		 50#include "qed.h"
51#include <linux/qed/qed_chain.h>
52#include "qed_cxt.h"
53#include "qed_dev_api.h"
54#include <linux/qed/qed_eth_if.h>
55#include "qed_hsi.h"
56#include "qed_hw.h"
57#include "qed_int.h"
dacd88d6 58#include "qed_l2.h"
86622ee7 59#include "qed_mcp.h"
25c089d7
YM		 60#include "qed_reg_addr.h"
61#include "qed_sp.h"
1408cc1f 62#include "qed_sriov.h"
25c089d7 63
088c8618 64
cee4d264
MC		 65#define QED_MAX_SGES_NUM 16
66#define CRC32_POLY 0x1edc6f41
67
0db711bb
MY		 68struct qed_l2_info {
69 u32 queues;
70 unsigned long **pp_qid_usage;
71
72 /* The lock is meant to synchronize access to the qid usage */
73 struct mutex lock;
74};
75
76int qed_l2_alloc(struct qed_hwfn *p_hwfn)
77{
78 struct qed_l2_info *p_l2_info;
79 unsigned long **pp_qids;
80 u32 i;
81
82 if (p_hwfn->hw_info.personality != QED_PCI_ETH &&
83 p_hwfn->hw_info.personality != QED_PCI_ETH_ROCE)
84 return 0;
85
86 p_l2_info = kzalloc(sizeof(*p_l2_info), GFP_KERNEL);
87 if (!p_l2_info)
88 return -ENOMEM;
89 p_hwfn->p_l2_info = p_l2_info;
90
91 if (IS_PF(p_hwfn->cdev)) {
92 p_l2_info->queues = RESC_NUM(p_hwfn, QED_L2_QUEUE);
93 } else {
94 u8 rx = 0, tx = 0;
95
96 qed_vf_get_num_rxqs(p_hwfn, &rx);
97 qed_vf_get_num_txqs(p_hwfn, &tx);
98
99 p_l2_info->queues = max_t(u8, rx, tx);
100 }
101
102 pp_qids = kzalloc(sizeof(unsigned long *) * p_l2_info->queues,
103 GFP_KERNEL);
104 if (!pp_qids)
105 return -ENOMEM;
106 p_l2_info->pp_qid_usage = pp_qids;
107
108 for (i = 0; i < p_l2_info->queues; i++) {
109 pp_qids[i] = kzalloc(MAX_QUEUES_PER_QZONE / 8, GFP_KERNEL);
110 if (!pp_qids[i])
111 return -ENOMEM;
112 }
113
114 return 0;
115}
116
117void qed_l2_setup(struct qed_hwfn *p_hwfn)
118{
119 if (p_hwfn->hw_info.personality != QED_PCI_ETH &&
120 p_hwfn->hw_info.personality != QED_PCI_ETH_ROCE)
121 return;
122
123 mutex_init(&p_hwfn->p_l2_info->lock);
124}
125
126void qed_l2_free(struct qed_hwfn *p_hwfn)
127{
128 u32 i;
129
130 if (p_hwfn->hw_info.personality != QED_PCI_ETH &&
131 p_hwfn->hw_info.personality != QED_PCI_ETH_ROCE)
132 return;
133
134 if (!p_hwfn->p_l2_info)
135 return;
136
137 if (!p_hwfn->p_l2_info->pp_qid_usage)
138 goto out_l2_info;
139
140 /* Free until hit first uninitialized entry */
141 for (i = 0; i < p_hwfn->p_l2_info->queues; i++) {
142 if (!p_hwfn->p_l2_info->pp_qid_usage[i])
143 break;
144 kfree(p_hwfn->p_l2_info->pp_qid_usage[i]);
145 }
146
147 kfree(p_hwfn->p_l2_info->pp_qid_usage);
148
149out_l2_info:
150 kfree(p_hwfn->p_l2_info);
151 p_hwfn->p_l2_info = NULL;
152}
153
bbe3f233
MY		 154static bool qed_eth_queue_qid_usage_add(struct qed_hwfn *p_hwfn,
155 struct qed_queue_cid *p_cid)
156{
157 struct qed_l2_info *p_l2_info = p_hwfn->p_l2_info;
158 u16 queue_id = p_cid->rel.queue_id;
159 bool b_rc = true;
160 u8 first;
161
162 mutex_lock(&p_l2_info->lock);
163
164 if (queue_id > p_l2_info->queues) {
165 DP_NOTICE(p_hwfn,
166 "Requested to increase usage for qzone %04x out of %08x\n",
167 queue_id, p_l2_info->queues);
168 b_rc = false;
169 goto out;
170 }
171
172 first = (u8)find_first_zero_bit(p_l2_info->pp_qid_usage[queue_id],
173 MAX_QUEUES_PER_QZONE);
174 if (first >= MAX_QUEUES_PER_QZONE) {
175 b_rc = false;
176 goto out;
177 }
178
179 __set_bit(first, p_l2_info->pp_qid_usage[queue_id]);
180 p_cid->qid_usage_idx = first;
181
182out:
183 mutex_unlock(&p_l2_info->lock);
184 return b_rc;
185}
186
187static void qed_eth_queue_qid_usage_del(struct qed_hwfn *p_hwfn,
188 struct qed_queue_cid *p_cid)
189{
190 mutex_lock(&p_hwfn->p_l2_info->lock);
191
192 clear_bit(p_cid->qid_usage_idx,
193 p_hwfn->p_l2_info->pp_qid_usage[p_cid->rel.queue_id]);
194
195 mutex_unlock(&p_hwfn->p_l2_info->lock);
196}
197
3da7a37a
MY		 198void qed_eth_queue_cid_release(struct qed_hwfn *p_hwfn,
199 struct qed_queue_cid *p_cid)
200{
201 /* VFs' CIDs are 0-based in PF-view, and uninitialized on VF */
3946497a
MY		 202 if ((p_cid->vfid == QED_QUEUE_CID_SELF) &&
203 IS_PF(p_hwfn->cdev))
3da7a37a 204 qed_cxt_release_cid(p_hwfn, p_cid->cid);
bbe3f233
MY		 205
206 /* For PF's VFs we maintain the index inside queue-zone in IOV */
207 if (p_cid->vfid == QED_QUEUE_CID_SELF)
208 qed_eth_queue_qid_usage_del(p_hwfn, p_cid);
209
3da7a37a
MY		 210 vfree(p_cid);
211}
212
213/* The internal is only meant to be directly called by PFs initializeing CIDs
214 * for their VFs.
215 */
3946497a 216static struct qed_queue_cid *
3da7a37a
MY		 217_qed_eth_queue_to_cid(struct qed_hwfn *p_hwfn,
218 u16 opaque_fid,
219 u32 cid,
3946497a
MY		 220 struct qed_queue_start_common_params *p_params,
221 struct qed_queue_cid_vf_params *p_vf_params)
3da7a37a 222{
3da7a37a
MY		 223 struct qed_queue_cid *p_cid;
224 int rc;
225
226 p_cid = vmalloc(sizeof(*p_cid));
227 if (!p_cid)
228 return NULL;
229 memset(p_cid, 0, sizeof(*p_cid));
230
231 p_cid->opaque_fid = opaque_fid;
232 p_cid->cid = cid;
f29ffdb6 233 p_cid->p_owner = p_hwfn;
3da7a37a 234
f604b17d
MY		 235 /* Fill in parameters */
236 p_cid->rel.vport_id = p_params->vport_id;
237 p_cid->rel.queue_id = p_params->queue_id;
238 p_cid->rel.stats_id = p_params->stats_id;
239 p_cid->sb_igu_id = p_params->p_sb->igu_sb_id;
240 p_cid->sb_idx = p_params->sb_idx;
241
3946497a
MY		 242 /* Fill-in bits related to VFs' queues if information was provided */
243 if (p_vf_params) {
244 p_cid->vfid = p_vf_params->vfid;
245 p_cid->vf_qid = p_vf_params->vf_qid;
246 p_cid->b_legacy_vf = p_vf_params->vf_legacy;
247 } else {
248 p_cid->vfid = QED_QUEUE_CID_SELF;
249 }
250
3da7a37a
MY		 251 /* Don't try calculating the absolute indices for VFs */
252 if (IS_VF(p_hwfn->cdev)) {
253 p_cid->abs = p_cid->rel;
254 goto out;
255 }
256
257 /* Calculate the engine-absolute indices of the resources.
258 * This would guarantee they're valid later on.
259 * In some cases [SBs] we already have the right values.
260 */
261 rc = qed_fw_vport(p_hwfn, p_cid->rel.vport_id, &p_cid->abs.vport_id);
262 if (rc)
263 goto fail;
264
265 rc = qed_fw_l2_queue(p_hwfn, p_cid->rel.queue_id, &p_cid->abs.queue_id);
266 if (rc)
267 goto fail;
268
269 /* In case of a PF configuring its VF's queues, the stats-id is already
270 * absolute [since there's a single index that's suitable per-VF].
271 */
3946497a 272 if (p_cid->vfid == QED_QUEUE_CID_SELF) {
3da7a37a
MY		 273 rc = qed_fw_vport(p_hwfn, p_cid->rel.stats_id,
274 &p_cid->abs.stats_id);
275 if (rc)
276 goto fail;
277 } else {
278 p_cid->abs.stats_id = p_cid->rel.stats_id;
279 }
280
3da7a37a 281out:
bbe3f233
MY		 282 /* VF-images have provided the qid_usage_idx on their own.
283 * Otherwise, we need to allocate a unique one.
284 */
285 if (!p_vf_params) {
286 if (!qed_eth_queue_qid_usage_add(p_hwfn, p_cid))
287 goto fail;
288 } else {
289 p_cid->qid_usage_idx = p_vf_params->qid_usage_idx;
290 }
291
3da7a37a
MY		 292 DP_VERBOSE(p_hwfn,
293 QED_MSG_SP,
bbe3f233 294 "opaque_fid: %04x CID %08x vport %02x [%02x] qzone %04x.%02x [%04x] stats %02x [%02x] SB %04x PI %02x\n",
3da7a37a
MY		 295 p_cid->opaque_fid,
296 p_cid->cid,
297 p_cid->rel.vport_id,
298 p_cid->abs.vport_id,
299 p_cid->rel.queue_id,
bbe3f233 300 p_cid->qid_usage_idx,
3da7a37a
MY		 301 p_cid->abs.queue_id,
302 p_cid->rel.stats_id,
f604b17d 303 p_cid->abs.stats_id, p_cid->sb_igu_id, p_cid->sb_idx);
3da7a37a
MY		 304
305 return p_cid;
306
307fail:
308 vfree(p_cid);
309 return NULL;
310}
311
3946497a
MY		 312struct qed_queue_cid *
313qed_eth_queue_to_cid(struct qed_hwfn *p_hwfn,
314 u16 opaque_fid,
315 struct qed_queue_start_common_params *p_params,
316 struct qed_queue_cid_vf_params *p_vf_params)
3da7a37a
MY		 317{
318 struct qed_queue_cid *p_cid;
3946497a 319 bool b_legacy_vf = false;
3da7a37a
MY		 320 u32 cid = 0;
321
3946497a
MY		 322 /* Currently, PF doesn't need to allocate CIDs for any VF */
323 if (p_vf_params)
324 b_legacy_vf = true;
3da7a37a
MY		 325 /* Get a unique firmware CID for this queue, in case it's a PF.
326 * VF's don't need a CID as the queue configuration will be done
327 * by PF.
328 */
3946497a 329 if (IS_PF(p_hwfn->cdev) && !b_legacy_vf) {
3da7a37a
MY		 330 if (qed_cxt_acquire_cid(p_hwfn, PROTOCOLID_ETH, &cid)) {
331 DP_NOTICE(p_hwfn, "Failed to acquire cid\n");
332 return NULL;
333 }
334 }
335
3946497a
MY		 336 p_cid = _qed_eth_queue_to_cid(p_hwfn, opaque_fid, cid,
337 p_params, p_vf_params);
338 if (!p_cid && IS_PF(p_hwfn->cdev) && !b_legacy_vf)
3da7a37a
MY		 339 qed_cxt_release_cid(p_hwfn, cid);
340
341 return p_cid;
342}
343
3946497a
MY		 344static struct qed_queue_cid *
345qed_eth_queue_to_cid_pf(struct qed_hwfn *p_hwfn,
346 u16 opaque_fid,
347 struct qed_queue_start_common_params *p_params)
348{
349 return qed_eth_queue_to_cid(p_hwfn, opaque_fid, p_params,
350 NULL);
351}
352
dacd88d6
YM		 353int qed_sp_eth_vport_start(struct qed_hwfn *p_hwfn,
354 struct qed_sp_vport_start_params *p_params)
cee4d264 355{
cee4d264
MC		 356 struct vport_start_ramrod_data *p_ramrod = NULL;
357 struct qed_spq_entry *p_ent = NULL;
06f56b81 358 struct qed_sp_init_data init_data;
dacd88d6 359 u8 abs_vport_id = 0;
cee4d264
MC		 360 int rc = -EINVAL;
361 u16 rx_mode = 0;
cee4d264 362
088c8618 363 rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
1a635e48 364 if (rc)
cee4d264
MC		 365 return rc;
366
06f56b81
YM		 367 memset(&init_data, 0, sizeof(init_data));
368 init_data.cid = qed_spq_get_cid(p_hwfn);
088c8618 369 init_data.opaque_fid = p_params->opaque_fid;
06f56b81 370 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
cee4d264
MC		 371
372 rc = qed_sp_init_request(p_hwfn, &p_ent,
cee4d264 373 ETH_RAMROD_VPORT_START,
06f56b81 374 PROTOCOLID_ETH, &init_data);
cee4d264
MC		 375 if (rc)
376 return rc;
377
378 p_ramrod = &p_ent->ramrod.vport_start;
379 p_ramrod->vport_id = abs_vport_id;
380
088c8618 381 p_ramrod->mtu = cpu_to_le16(p_params->mtu);
c78c70fa 382 p_ramrod->handle_ptp_pkts = p_params->handle_ptp_pkts;
088c8618
MC		 383 p_ramrod->inner_vlan_removal_en = p_params->remove_inner_vlan;
384 p_ramrod->drop_ttl0_en = p_params->drop_ttl0;
e6bd8923 385 p_ramrod->untagged = p_params->only_untagged;
cee4d264
MC		 386
387 SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_UCAST_DROP_ALL, 1);
388 SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_MCAST_DROP_ALL, 1);
389
390 p_ramrod->rx_mode.state = cpu_to_le16(rx_mode);
391
392 /* TPA related fields */
1a635e48 393 memset(&p_ramrod->tpa_param, 0, sizeof(struct eth_vport_tpa_param));
cee4d264 394
088c8618
MC		 395 p_ramrod->tpa_param.max_buff_num = p_params->max_buffers_per_cqe;
396
397 switch (p_params->tpa_mode) {
398 case QED_TPA_MODE_GRO:
399 p_ramrod->tpa_param.tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
400 p_ramrod->tpa_param.tpa_max_size = (u16)-1;
401 p_ramrod->tpa_param.tpa_min_size_to_cont = p_params->mtu / 2;
402 p_ramrod->tpa_param.tpa_min_size_to_start = p_params->mtu / 2;
403 p_ramrod->tpa_param.tpa_ipv4_en_flg = 1;
404 p_ramrod->tpa_param.tpa_ipv6_en_flg = 1;
405 p_ramrod->tpa_param.tpa_pkt_split_flg = 1;
406 p_ramrod->tpa_param.tpa_gro_consistent_flg = 1;
407 break;
408 default:
409 break;
410 }
411
831bfb0e
YM		 412 p_ramrod->tx_switching_en = p_params->tx_switching;
413
11a85d75
YM		 414 p_ramrod->ctl_frame_mac_check_en = !!p_params->check_mac;
415 p_ramrod->ctl_frame_ethtype_check_en = !!p_params->check_ethtype;
416
cee4d264
MC		 417 /* Software Function ID in hwfn (PFs are 0 - 15, VFs are 16 - 135) */
418 p_ramrod->sw_fid = qed_concrete_to_sw_fid(p_hwfn->cdev,
088c8618 419 p_params->concrete_fid);
cee4d264
MC		 420
421 return qed_spq_post(p_hwfn, p_ent, NULL);
422}
423
ba56947a
BX		 424static int qed_sp_vport_start(struct qed_hwfn *p_hwfn,
425 struct qed_sp_vport_start_params *p_params)
dacd88d6
YM		 426{
427 if (IS_VF(p_hwfn->cdev)) {
428 return qed_vf_pf_vport_start(p_hwfn, p_params->vport_id,
429 p_params->mtu,
430 p_params->remove_inner_vlan,
431 p_params->tpa_mode,
08feecd7
YM		 432 p_params->max_buffers_per_cqe,
433 p_params->only_untagged);
dacd88d6
YM		 434 }
435
436 return qed_sp_eth_vport_start(p_hwfn, p_params);
437}
438
cee4d264
MC		 439static int
440qed_sp_vport_update_rss(struct qed_hwfn *p_hwfn,
441 struct vport_update_ramrod_data *p_ramrod,
f29ffdb6 442 struct qed_rss_params *p_rss)
cee4d264 443{
f29ffdb6
MY		 444 struct eth_vport_rss_config *p_config;
445 u16 capabilities = 0;
446 int i, table_size;
447 int rc = 0;
cee4d264 448
f29ffdb6 449 if (!p_rss) {
cee4d264
MC		 450 p_ramrod->common.update_rss_flg = 0;
451 return rc;
452 }
f29ffdb6 453 p_config = &p_ramrod->rss_config;
cee4d264 454
f29ffdb6 455 BUILD_BUG_ON(QED_RSS_IND_TABLE_SIZE != ETH_RSS_IND_TABLE_ENTRIES_NUM);
cee4d264 456
f29ffdb6 457 rc = qed_fw_rss_eng(p_hwfn, p_rss->rss_eng_id, &p_config->rss_id);
cee4d264
MC		 458 if (rc)
459 return rc;
460
f29ffdb6
MY		 461 p_ramrod->common.update_rss_flg = p_rss->update_rss_config;
462 p_config->update_rss_capabilities = p_rss->update_rss_capabilities;
463 p_config->update_rss_ind_table = p_rss->update_rss_ind_table;
464 p_config->update_rss_key = p_rss->update_rss_key;
cee4d264 465
f29ffdb6
MY		 466 p_config->rss_mode = p_rss->rss_enable ?
467 ETH_VPORT_RSS_MODE_REGULAR :
468 ETH_VPORT_RSS_MODE_DISABLED;
cee4d264
MC		 469
470 SET_FIELD(capabilities,
471 ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY,
f29ffdb6 472 !!(p_rss->rss_caps & QED_RSS_IPV4));
cee4d264
MC		 473 SET_FIELD(capabilities,
474 ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY,
f29ffdb6 475 !!(p_rss->rss_caps & QED_RSS_IPV6));
cee4d264
MC		 476 SET_FIELD(capabilities,
477 ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY,
f29ffdb6 478 !!(p_rss->rss_caps & QED_RSS_IPV4_TCP));
cee4d264
MC		 479 SET_FIELD(capabilities,
480 ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY,
f29ffdb6 481 !!(p_rss->rss_caps & QED_RSS_IPV6_TCP));
cee4d264
MC		 482 SET_FIELD(capabilities,
483 ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY,
f29ffdb6 484 !!(p_rss->rss_caps & QED_RSS_IPV4_UDP));
cee4d264
MC		 485 SET_FIELD(capabilities,
486 ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY,
f29ffdb6
MY		 487 !!(p_rss->rss_caps & QED_RSS_IPV6_UDP));
488 p_config->tbl_size = p_rss->rss_table_size_log;
cee4d264 489
f29ffdb6 490 p_config->capabilities = cpu_to_le16(capabilities);
cee4d264
MC		 491
492 DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP,
493 "update rss flag %d, rss_mode = %d, update_caps = %d, capabilities = %d, update_ind = %d, update_rss_key = %d\n",
494 p_ramrod->common.update_rss_flg,
f29ffdb6
MY		 495 p_config->rss_mode,
496 p_config->update_rss_capabilities,
497 p_config->capabilities,
498 p_config->update_rss_ind_table, p_config->update_rss_key);
cee4d264 499
f29ffdb6
MY		 500 table_size = min_t(int, QED_RSS_IND_TABLE_SIZE,
501 1 << p_config->tbl_size);
502 for (i = 0; i < table_size; i++) {
503 struct qed_queue_cid *p_queue = p_rss->rss_ind_table[i];
cee4d264 504
f29ffdb6
MY		 505 if (!p_queue)
506 return -EINVAL;
507
508 p_config->indirection_table[i] =
509 cpu_to_le16(p_queue->abs.queue_id);
510 }
511
512 DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP,
513 "Configured RSS indirection table [%d entries]:\n",
514 table_size);
515 for (i = 0; i < QED_RSS_IND_TABLE_SIZE; i += 0x10) {
516 DP_VERBOSE(p_hwfn,
517 NETIF_MSG_IFUP,
518 "%04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x\n",
519 le16_to_cpu(p_config->indirection_table[i]),
520 le16_to_cpu(p_config->indirection_table[i + 1]),
521 le16_to_cpu(p_config->indirection_table[i + 2]),
522 le16_to_cpu(p_config->indirection_table[i + 3]),
523 le16_to_cpu(p_config->indirection_table[i + 4]),
524 le16_to_cpu(p_config->indirection_table[i + 5]),
525 le16_to_cpu(p_config->indirection_table[i + 6]),
526 le16_to_cpu(p_config->indirection_table[i + 7]),
527 le16_to_cpu(p_config->indirection_table[i + 8]),
528 le16_to_cpu(p_config->indirection_table[i + 9]),
529 le16_to_cpu(p_config->indirection_table[i + 10]),
530 le16_to_cpu(p_config->indirection_table[i + 11]),
531 le16_to_cpu(p_config->indirection_table[i + 12]),
532 le16_to_cpu(p_config->indirection_table[i + 13]),
533 le16_to_cpu(p_config->indirection_table[i + 14]),
534 le16_to_cpu(p_config->indirection_table[i + 15]));
cee4d264
MC		 535 }
536
537 for (i = 0; i < 10; i++)
f29ffdb6 538 p_config->rss_key[i] = cpu_to_le32(p_rss->rss_key[i]);
cee4d264
MC		 539
540 return rc;
541}
542
543static void
544qed_sp_update_accept_mode(struct qed_hwfn *p_hwfn,
545 struct vport_update_ramrod_data *p_ramrod,
546 struct qed_filter_accept_flags accept_flags)
547{
548 p_ramrod->common.update_rx_mode_flg =
549 accept_flags.update_rx_mode_config;
550
551 p_ramrod->common.update_tx_mode_flg =
552 accept_flags.update_tx_mode_config;
553
554 /* Set Rx mode accept flags */
555 if (p_ramrod->common.update_rx_mode_flg) {
556 u8 accept_filter = accept_flags.rx_accept_filter;
557 u16 state = 0;
558
559 SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_DROP_ALL,
560 !(!!(accept_filter & QED_ACCEPT_UCAST_MATCHED) ||
561 !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED)));
562
563 SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED,
564 !!(accept_filter & QED_ACCEPT_UCAST_UNMATCHED));
565
566 SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_DROP_ALL,
567 !(!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) ||
568 !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED)));
569
570 SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL,
571 (!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) &&
572 !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED)));
573
574 SET_FIELD(state, ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL,
575 !!(accept_filter & QED_ACCEPT_BCAST));
576
577 p_ramrod->rx_mode.state = cpu_to_le16(state);
578 DP_VERBOSE(p_hwfn, QED_MSG_SP,
579 "p_ramrod->rx_mode.state = 0x%x\n", state);
580 }
581
582 /* Set Tx mode accept flags */
583 if (p_ramrod->common.update_tx_mode_flg) {
584 u8 accept_filter = accept_flags.tx_accept_filter;
585 u16 state = 0;
586
587 SET_FIELD(state, ETH_VPORT_TX_MODE_UCAST_DROP_ALL,
588 !!(accept_filter & QED_ACCEPT_NONE));
589
cee4d264
MC		 590 SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_DROP_ALL,
591 !!(accept_filter & QED_ACCEPT_NONE));
592
593 SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL,
594 (!!(accept_filter & QED_ACCEPT_MCAST_MATCHED) &&
595 !!(accept_filter & QED_ACCEPT_MCAST_UNMATCHED)));
596
597 SET_FIELD(state, ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL,
598 !!(accept_filter & QED_ACCEPT_BCAST));
599
600 p_ramrod->tx_mode.state = cpu_to_le16(state);
601 DP_VERBOSE(p_hwfn, QED_MSG_SP,
602 "p_ramrod->tx_mode.state = 0x%x\n", state);
603 }
604}
605
17b235c1
YM		 606static void
607qed_sp_vport_update_sge_tpa(struct qed_hwfn *p_hwfn,
608 struct vport_update_ramrod_data *p_ramrod,
609 struct qed_sge_tpa_params *p_params)
610{
611 struct eth_vport_tpa_param *p_tpa;
612
613 if (!p_params) {
614 p_ramrod->common.update_tpa_param_flg = 0;
615 p_ramrod->common.update_tpa_en_flg = 0;
616 p_ramrod->common.update_tpa_param_flg = 0;
617 return;
618 }
619
620 p_ramrod->common.update_tpa_en_flg = p_params->update_tpa_en_flg;
621 p_tpa = &p_ramrod->tpa_param;
622 p_tpa->tpa_ipv4_en_flg = p_params->tpa_ipv4_en_flg;
623 p_tpa->tpa_ipv6_en_flg = p_params->tpa_ipv6_en_flg;
624 p_tpa->tpa_ipv4_tunn_en_flg = p_params->tpa_ipv4_tunn_en_flg;
625 p_tpa->tpa_ipv6_tunn_en_flg = p_params->tpa_ipv6_tunn_en_flg;
626
627 p_ramrod->common.update_tpa_param_flg = p_params->update_tpa_param_flg;
628 p_tpa->max_buff_num = p_params->max_buffers_per_cqe;
629 p_tpa->tpa_pkt_split_flg = p_params->tpa_pkt_split_flg;
630 p_tpa->tpa_hdr_data_split_flg = p_params->tpa_hdr_data_split_flg;
631 p_tpa->tpa_gro_consistent_flg = p_params->tpa_gro_consistent_flg;
632 p_tpa->tpa_max_aggs_num = p_params->tpa_max_aggs_num;
633 p_tpa->tpa_max_size = p_params->tpa_max_size;
634 p_tpa->tpa_min_size_to_start = p_params->tpa_min_size_to_start;
635 p_tpa->tpa_min_size_to_cont = p_params->tpa_min_size_to_cont;
636}
637
cee4d264
MC		 638static void
639qed_sp_update_mcast_bin(struct qed_hwfn *p_hwfn,
640 struct vport_update_ramrod_data *p_ramrod,
641 struct qed_sp_vport_update_params *p_params)
642{
643 int i;
644
645 memset(&p_ramrod->approx_mcast.bins, 0,
646 sizeof(p_ramrod->approx_mcast.bins));
647
83aeb933
YM		 648 if (!p_params->update_approx_mcast_flg)
649 return;
cee4d264 650
83aeb933
YM		 651 p_ramrod->common.update_approx_mcast_flg = 1;
652 for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) {
653 u32 *p_bins = (u32 *)p_params->bins;
654
655 p_ramrod->approx_mcast.bins[i] = cpu_to_le32(p_bins[i]);
cee4d264
MC		 656 }
657}
658
dacd88d6
YM		 659int qed_sp_vport_update(struct qed_hwfn *p_hwfn,
660 struct qed_sp_vport_update_params *p_params,
661 enum spq_mode comp_mode,
662 struct qed_spq_comp_cb *p_comp_data)
cee4d264
MC		 663{
664 struct qed_rss_params *p_rss_params = p_params->rss_params;
665 struct vport_update_ramrod_data_cmn *p_cmn;
06f56b81 666 struct qed_sp_init_data init_data;
cee4d264
MC		 667 struct vport_update_ramrod_data *p_ramrod = NULL;
668 struct qed_spq_entry *p_ent = NULL;
17b235c1 669 u8 abs_vport_id = 0, val;
cee4d264
MC		 670 int rc = -EINVAL;
671
dacd88d6
YM		 672 if (IS_VF(p_hwfn->cdev)) {
673 rc = qed_vf_pf_vport_update(p_hwfn, p_params);
674 return rc;
675 }
676
cee4d264 677 rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
1a635e48 678 if (rc)
cee4d264
MC		 679 return rc;
680
06f56b81
YM		 681 memset(&init_data, 0, sizeof(init_data));
682 init_data.cid = qed_spq_get_cid(p_hwfn);
683 init_data.opaque_fid = p_params->opaque_fid;
684 init_data.comp_mode = comp_mode;
685 init_data.p_comp_data = p_comp_data;
cee4d264
MC		 686
687 rc = qed_sp_init_request(p_hwfn, &p_ent,
cee4d264 688 ETH_RAMROD_VPORT_UPDATE,
06f56b81 689 PROTOCOLID_ETH, &init_data);
cee4d264
MC		 690 if (rc)
691 return rc;
692
693 /* Copy input params to ramrod according to FW struct */
694 p_ramrod = &p_ent->ramrod.vport_update;
695 p_cmn = &p_ramrod->common;
696
697 p_cmn->vport_id = abs_vport_id;
698 p_cmn->rx_active_flg = p_params->vport_active_rx_flg;
699 p_cmn->update_rx_active_flg = p_params->update_vport_active_rx_flg;
700 p_cmn->tx_active_flg = p_params->vport_active_tx_flg;
701 p_cmn->update_tx_active_flg = p_params->update_vport_active_tx_flg;
3f9b4a69 702 p_cmn->accept_any_vlan = p_params->accept_any_vlan;
83aeb933
YM		 703 val = p_params->update_accept_any_vlan_flg;
704 p_cmn->update_accept_any_vlan_flg = val;
17b235c1
YM		 705
706 p_cmn->inner_vlan_removal_en = p_params->inner_vlan_removal_flg;
707 val = p_params->update_inner_vlan_removal_flg;
708 p_cmn->update_inner_vlan_removal_en_flg = val;
08feecd7
YM		 709
710 p_cmn->default_vlan_en = p_params->default_vlan_enable_flg;
711 val = p_params->update_default_vlan_enable_flg;
712 p_cmn->update_default_vlan_en_flg = val;
713
714 p_cmn->default_vlan = cpu_to_le16(p_params->default_vlan);
715 p_cmn->update_default_vlan_flg = p_params->update_default_vlan_flg;
716
717 p_cmn->silent_vlan_removal_en = p_params->silent_vlan_removal_flg;
718
17b235c1
YM		 719 p_ramrod->common.tx_switching_en = p_params->tx_switching_flg;
720 p_cmn->update_tx_switching_en_flg = p_params->update_tx_switching_flg;
721
6ddc7608
YM		 722 p_cmn->anti_spoofing_en = p_params->anti_spoofing_en;
723 val = p_params->update_anti_spoofing_en_flg;
724 p_ramrod->common.update_anti_spoofing_en_flg = val;
725
cee4d264
MC		 726 rc = qed_sp_vport_update_rss(p_hwfn, p_ramrod, p_rss_params);
727 if (rc) {
728 /* Return spq entry which is taken in qed_sp_init_request()*/
729 qed_spq_return_entry(p_hwfn, p_ent);
730 return rc;
731 }
732
733 /* Update mcast bins for VFs, PF doesn't use this functionality */
734 qed_sp_update_mcast_bin(p_hwfn, p_ramrod, p_params);
735
736 qed_sp_update_accept_mode(p_hwfn, p_ramrod, p_params->accept_flags);
17b235c1 737 qed_sp_vport_update_sge_tpa(p_hwfn, p_ramrod, p_params->sge_tpa_params);
cee4d264
MC		 738 return qed_spq_post(p_hwfn, p_ent, NULL);
739}
740
dacd88d6 741int qed_sp_vport_stop(struct qed_hwfn *p_hwfn, u16 opaque_fid, u8 vport_id)
cee4d264 742{
cee4d264 743 struct vport_stop_ramrod_data *p_ramrod;
06f56b81 744 struct qed_sp_init_data init_data;
cee4d264
MC		 745 struct qed_spq_entry *p_ent;
746 u8 abs_vport_id = 0;
747 int rc;
748
dacd88d6
YM		 749 if (IS_VF(p_hwfn->cdev))
750 return qed_vf_pf_vport_stop(p_hwfn);
751
cee4d264 752 rc = qed_fw_vport(p_hwfn, vport_id, &abs_vport_id);
1a635e48 753 if (rc)
cee4d264
MC		 754 return rc;
755
06f56b81
YM		 756 memset(&init_data, 0, sizeof(init_data));
757 init_data.cid = qed_spq_get_cid(p_hwfn);
758 init_data.opaque_fid = opaque_fid;
759 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
cee4d264
MC		 760
761 rc = qed_sp_init_request(p_hwfn, &p_ent,
cee4d264 762 ETH_RAMROD_VPORT_STOP,
06f56b81 763 PROTOCOLID_ETH, &init_data);
cee4d264
MC		 764 if (rc)
765 return rc;
766
767 p_ramrod = &p_ent->ramrod.vport_stop;
768 p_ramrod->vport_id = abs_vport_id;
769
770 return qed_spq_post(p_hwfn, p_ent, NULL);
771}
772
dacd88d6
YM		 773static int
774qed_vf_pf_accept_flags(struct qed_hwfn *p_hwfn,
775 struct qed_filter_accept_flags *p_accept_flags)
776{
777 struct qed_sp_vport_update_params s_params;
778
779 memset(&s_params, 0, sizeof(s_params));
780 memcpy(&s_params.accept_flags, p_accept_flags,
781 sizeof(struct qed_filter_accept_flags));
782
783 return qed_vf_pf_vport_update(p_hwfn, &s_params);
784}
785
cee4d264
MC		 786static int qed_filter_accept_cmd(struct qed_dev *cdev,
787 u8 vport,
788 struct qed_filter_accept_flags accept_flags,
3f9b4a69
YM		 789 u8 update_accept_any_vlan,
790 u8 accept_any_vlan,
dacd88d6
YM		 791 enum spq_mode comp_mode,
792 struct qed_spq_comp_cb *p_comp_data)
cee4d264
MC		 793{
794 struct qed_sp_vport_update_params vport_update_params;
795 int i, rc;
796
797 /* Prepare and send the vport rx_mode change */
798 memset(&vport_update_params, 0, sizeof(vport_update_params));
799 vport_update_params.vport_id = vport;
800 vport_update_params.accept_flags = accept_flags;
3f9b4a69
YM		 801 vport_update_params.update_accept_any_vlan_flg = update_accept_any_vlan;
802 vport_update_params.accept_any_vlan = accept_any_vlan;
cee4d264
MC		 803
804 for_each_hwfn(cdev, i) {
805 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
806
807 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
808
dacd88d6
YM		 809 if (IS_VF(cdev)) {
810 rc = qed_vf_pf_accept_flags(p_hwfn, &accept_flags);
811 if (rc)
812 return rc;
813 continue;
814 }
815
cee4d264
MC		 816 rc = qed_sp_vport_update(p_hwfn, &vport_update_params,
817 comp_mode, p_comp_data);
1a635e48 818 if (rc) {
cee4d264
MC		 819 DP_ERR(cdev, "Update rx_mode failed %d\n", rc);
820 return rc;
821 }
822
823 DP_VERBOSE(p_hwfn, QED_MSG_SP,
824 "Accept filter configured, flags = [Rx]%x [Tx]%x\n",
825 accept_flags.rx_accept_filter,
826 accept_flags.tx_accept_filter);
3f9b4a69
YM		 827 if (update_accept_any_vlan)
828 DP_VERBOSE(p_hwfn, QED_MSG_SP,
829 "accept_any_vlan=%d configured\n",
830 accept_any_vlan);
cee4d264
MC		 831 }
832
833 return 0;
834}
835
3da7a37a
MY		 836int qed_eth_rxq_start_ramrod(struct qed_hwfn *p_hwfn,
837 struct qed_queue_cid *p_cid,
838 u16 bd_max_bytes,
839 dma_addr_t bd_chain_phys_addr,
840 dma_addr_t cqe_pbl_addr, u16 cqe_pbl_size)
cee4d264
MC		 841{
842 struct rx_queue_start_ramrod_data *p_ramrod = NULL;
cee4d264 843 struct qed_spq_entry *p_ent = NULL;
06f56b81 844 struct qed_sp_init_data init_data;
cee4d264
MC		 845 int rc = -EINVAL;
846
cee4d264 847 DP_VERBOSE(p_hwfn, QED_MSG_SP,
3da7a37a
MY		 848 "opaque_fid=0x%x, cid=0x%x, rx_qzone=0x%x, vport_id=0x%x, sb_id=0x%x\n",
849 p_cid->opaque_fid, p_cid->cid,
f604b17d 850 p_cid->abs.queue_id, p_cid->abs.vport_id, p_cid->sb_igu_id);
cee4d264 851
06f56b81
YM		 852 /* Get SPQ entry */
853 memset(&init_data, 0, sizeof(init_data));
3da7a37a
MY		 854 init_data.cid = p_cid->cid;
855 init_data.opaque_fid = p_cid->opaque_fid;
06f56b81 856 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
cee4d264
MC		 857
858 rc = qed_sp_init_request(p_hwfn, &p_ent,
cee4d264 859 ETH_RAMROD_RX_QUEUE_START,
06f56b81 860 PROTOCOLID_ETH, &init_data);
cee4d264
MC		 861 if (rc)
862 return rc;
863
864 p_ramrod = &p_ent->ramrod.rx_queue_start;
865
f604b17d
MY		 866 p_ramrod->sb_id = cpu_to_le16(p_cid->sb_igu_id);
867 p_ramrod->sb_index = p_cid->sb_idx;
3da7a37a
MY		 868 p_ramrod->vport_id = p_cid->abs.vport_id;
869 p_ramrod->stats_counter_id = p_cid->abs.stats_id;
870 p_ramrod->rx_queue_id = cpu_to_le16(p_cid->abs.queue_id);
1a635e48
YM		 871 p_ramrod->complete_cqe_flg = 0;
872 p_ramrod->complete_event_flg = 1;
cee4d264 873
1a635e48 874 p_ramrod->bd_max_bytes = cpu_to_le16(bd_max_bytes);
94494598 875 DMA_REGPAIR_LE(p_ramrod->bd_base, bd_chain_phys_addr);
cee4d264 876
1a635e48 877 p_ramrod->num_of_pbl_pages = cpu_to_le16(cqe_pbl_size);
94494598 878 DMA_REGPAIR_LE(p_ramrod->cqe_pbl_addr, cqe_pbl_addr);
cee4d264 879
3946497a 880 if (p_cid->vfid != QED_QUEUE_CID_SELF) {
3da7a37a 881 p_ramrod->vf_rx_prod_index = p_cid->vf_qid;
351a4ded 882 DP_VERBOSE(p_hwfn, QED_MSG_SP,
a044df83 883 "Queue%s is meant for VF rxq[%02x]\n",
3da7a37a
MY		 884 !!p_cid->b_legacy_vf ? " [legacy]" : "",
885 p_cid->vf_qid);
886 p_ramrod->vf_rx_prod_use_zone_a = !!p_cid->b_legacy_vf;
a044df83 887 }
cee4d264 888
351a4ded 889 return qed_spq_post(p_hwfn, p_ent, NULL);
cee4d264
MC		 890}
891
892static int
3da7a37a
MY		 893qed_eth_pf_rx_queue_start(struct qed_hwfn *p_hwfn,
894 struct qed_queue_cid *p_cid,
cee4d264
MC		 895 u16 bd_max_bytes,
896 dma_addr_t bd_chain_phys_addr,
897 dma_addr_t cqe_pbl_addr,
dacd88d6 898 u16 cqe_pbl_size, void __iomem **pp_prod)
cee4d264 899{
b21290b7 900 u32 init_prod_val = 0;
cee4d264 901
3da7a37a
MY		 902 *pp_prod = p_hwfn->regview +
903 GTT_BAR0_MAP_REG_MSDM_RAM +
904 MSTORM_ETH_PF_PRODS_OFFSET(p_cid->abs.queue_id);
cee4d264
MC		 905
906 /* Init the rcq, rx bd and rx sge (if valid) producers to 0 */
b21290b7 907 __internal_ram_wr(p_hwfn, *pp_prod, sizeof(u32),
cee4d264
MC		 908 (u32 *)(&init_prod_val));
909
3da7a37a
MY		 910 return qed_eth_rxq_start_ramrod(p_hwfn, p_cid,
911 bd_max_bytes,
912 bd_chain_phys_addr,
913 cqe_pbl_addr, cqe_pbl_size);
914}
915
916static int
917qed_eth_rx_queue_start(struct qed_hwfn *p_hwfn,
918 u16 opaque_fid,
919 struct qed_queue_start_common_params *p_params,
920 u16 bd_max_bytes,
921 dma_addr_t bd_chain_phys_addr,
922 dma_addr_t cqe_pbl_addr,
923 u16 cqe_pbl_size,
924 struct qed_rxq_start_ret_params *p_ret_params)
925{
926 struct qed_queue_cid *p_cid;
927 int rc;
928
cee4d264 929 /* Allocate a CID for the queue */
3946497a 930 p_cid = qed_eth_queue_to_cid_pf(p_hwfn, opaque_fid, p_params);
3da7a37a
MY		 931 if (!p_cid)
932 return -ENOMEM;
cee4d264 933
3da7a37a
MY		 934 if (IS_PF(p_hwfn->cdev)) {
935 rc = qed_eth_pf_rx_queue_start(p_hwfn, p_cid,
936 bd_max_bytes,
937 bd_chain_phys_addr,
938 cqe_pbl_addr, cqe_pbl_size,
939 &p_ret_params->p_prod);
940 } else {
941 rc = qed_vf_pf_rxq_start(p_hwfn, p_cid,
cee4d264
MC		 942 bd_max_bytes,
943 bd_chain_phys_addr,
3da7a37a
MY		 944 cqe_pbl_addr,
945 cqe_pbl_size, &p_ret_params->p_prod);
946 }
cee4d264 947
3da7a37a 948 /* Provide the caller with a reference to as handler */
1a635e48 949 if (rc)
3da7a37a
MY		 950 qed_eth_queue_cid_release(p_hwfn, p_cid);
951 else
952 p_ret_params->p_handle = (void *)p_cid;
cee4d264
MC		 953
954 return rc;
955}
956
17b235c1 957int qed_sp_eth_rx_queues_update(struct qed_hwfn *p_hwfn,
3da7a37a 958 void **pp_rxq_handles,
17b235c1
YM		 959 u8 num_rxqs,
960 u8 complete_cqe_flg,
961 u8 complete_event_flg,
962 enum spq_mode comp_mode,
963 struct qed_spq_comp_cb *p_comp_data)
964{
965 struct rx_queue_update_ramrod_data *p_ramrod = NULL;
966 struct qed_spq_entry *p_ent = NULL;
967 struct qed_sp_init_data init_data;
3da7a37a 968 struct qed_queue_cid *p_cid;
17b235c1
YM		 969 int rc = -EINVAL;
970 u8 i;
971
972 memset(&init_data, 0, sizeof(init_data));
973 init_data.comp_mode = comp_mode;
974 init_data.p_comp_data = p_comp_data;
975
976 for (i = 0; i < num_rxqs; i++) {
3da7a37a 977 p_cid = ((struct qed_queue_cid **)pp_rxq_handles)[i];
17b235c1
YM		 978
979 /* Get SPQ entry */
3da7a37a
MY		 980 init_data.cid = p_cid->cid;
981 init_data.opaque_fid = p_cid->opaque_fid;
17b235c1
YM		 982
983 rc = qed_sp_init_request(p_hwfn, &p_ent,
984 ETH_RAMROD_RX_QUEUE_UPDATE,
985 PROTOCOLID_ETH, &init_data);
986 if (rc)
987 return rc;
988
989 p_ramrod = &p_ent->ramrod.rx_queue_update;
3da7a37a 990 p_ramrod->vport_id = p_cid->abs.vport_id;
17b235c1 991
3da7a37a 992 p_ramrod->rx_queue_id = cpu_to_le16(p_cid->abs.queue_id);
17b235c1
YM		 993 p_ramrod->complete_cqe_flg = complete_cqe_flg;
994 p_ramrod->complete_event_flg = complete_event_flg;
995
996 rc = qed_spq_post(p_hwfn, p_ent, NULL);
997 if (rc)
998 return rc;
999 }
1000
1001 return rc;
1002}
1003
3da7a37a
MY		 1004static int
1005qed_eth_pf_rx_queue_stop(struct qed_hwfn *p_hwfn,
1006 struct qed_queue_cid *p_cid,
1007 bool b_eq_completion_only, bool b_cqe_completion)
cee4d264 1008{
cee4d264 1009 struct rx_queue_stop_ramrod_data *p_ramrod = NULL;
cee4d264 1010 struct qed_spq_entry *p_ent = NULL;
06f56b81 1011 struct qed_sp_init_data init_data;
3da7a37a 1012 int rc;
dacd88d6 1013
06f56b81 1014 memset(&init_data, 0, sizeof(init_data));
3da7a37a
MY		 1015 init_data.cid = p_cid->cid;
1016 init_data.opaque_fid = p_cid->opaque_fid;
06f56b81 1017 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
cee4d264
MC		 1018
1019 rc = qed_sp_init_request(p_hwfn, &p_ent,
cee4d264 1020 ETH_RAMROD_RX_QUEUE_STOP,
06f56b81 1021 PROTOCOLID_ETH, &init_data);
cee4d264
MC		 1022 if (rc)
1023 return rc;
1024
1025 p_ramrod = &p_ent->ramrod.rx_queue_stop;
3da7a37a
MY		 1026 p_ramrod->vport_id = p_cid->abs.vport_id;
1027 p_ramrod->rx_queue_id = cpu_to_le16(p_cid->abs.queue_id);
cee4d264
MC		 1028
1029 /* Cleaning the queue requires the completion to arrive there.
1030 * In addition, VFs require the answer to come as eqe to PF.
1031 */
3946497a 1032 p_ramrod->complete_cqe_flg = ((p_cid->vfid == QED_QUEUE_CID_SELF) &&
3da7a37a
MY		 1033 !b_eq_completion_only) ||
1034 b_cqe_completion;
3946497a
MY		 1035 p_ramrod->complete_event_flg = (p_cid->vfid != QED_QUEUE_CID_SELF) ||
1036 b_eq_completion_only;
cee4d264 1037
3da7a37a
MY		 1038 return qed_spq_post(p_hwfn, p_ent, NULL);
1039}
1040
1041int qed_eth_rx_queue_stop(struct qed_hwfn *p_hwfn,
1042 void *p_rxq,
1043 bool eq_completion_only, bool cqe_completion)
1044{
1045 struct qed_queue_cid *p_cid = (struct qed_queue_cid *)p_rxq;
1046 int rc = -EINVAL;
cee4d264 1047
3da7a37a
MY		 1048 if (IS_PF(p_hwfn->cdev))
1049 rc = qed_eth_pf_rx_queue_stop(p_hwfn, p_cid,
1050 eq_completion_only,
1051 cqe_completion);
1052 else
1053 rc = qed_vf_pf_rxq_stop(p_hwfn, p_cid, cqe_completion);
1054
1055 if (!rc)
1056 qed_eth_queue_cid_release(p_hwfn, p_cid);
1057 return rc;
cee4d264
MC		 1058}
1059
3da7a37a
MY		 1060int
1061qed_eth_txq_start_ramrod(struct qed_hwfn *p_hwfn,
1062 struct qed_queue_cid *p_cid,
1063 dma_addr_t pbl_addr, u16 pbl_size, u16 pq_id)
cee4d264
MC		 1064{
1065 struct tx_queue_start_ramrod_data *p_ramrod = NULL;
cee4d264 1066 struct qed_spq_entry *p_ent = NULL;
06f56b81 1067 struct qed_sp_init_data init_data;
cee4d264 1068 int rc = -EINVAL;
351a4ded 1069
06f56b81
YM		 1070 /* Get SPQ entry */
1071 memset(&init_data, 0, sizeof(init_data));
3da7a37a
MY		 1072 init_data.cid = p_cid->cid;
1073 init_data.opaque_fid = p_cid->opaque_fid;
06f56b81 1074 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
cee4d264 1075
06f56b81 1076 rc = qed_sp_init_request(p_hwfn, &p_ent,
cee4d264 1077 ETH_RAMROD_TX_QUEUE_START,
06f56b81 1078 PROTOCOLID_ETH, &init_data);
cee4d264
MC		 1079 if (rc)
1080 return rc;
1081
1a635e48 1082 p_ramrod = &p_ent->ramrod.tx_queue_start;
3da7a37a 1083 p_ramrod->vport_id = p_cid->abs.vport_id;
1a635e48 1084
f604b17d
MY		 1085 p_ramrod->sb_id = cpu_to_le16(p_cid->sb_igu_id);
1086 p_ramrod->sb_index = p_cid->sb_idx;
3da7a37a 1087 p_ramrod->stats_counter_id = p_cid->abs.stats_id;
cee4d264 1088
3da7a37a
MY		 1089 p_ramrod->queue_zone_id = cpu_to_le16(p_cid->abs.queue_id);
1090 p_ramrod->same_as_last_id = cpu_to_le16(p_cid->abs.queue_id);
cee4d264 1091
1a635e48 1092 p_ramrod->pbl_size = cpu_to_le16(pbl_size);
94494598 1093 DMA_REGPAIR_LE(p_ramrod->pbl_base_addr, pbl_addr);
cee4d264 1094
1a635e48 1095 p_ramrod->qm_pq_id = cpu_to_le16(pq_id);
cee4d264
MC		 1096
1097 return qed_spq_post(p_hwfn, p_ent, NULL);
1098}
1099
1100static int
3da7a37a
MY		 1101qed_eth_pf_tx_queue_start(struct qed_hwfn *p_hwfn,
1102 struct qed_queue_cid *p_cid,
1103 u8 tc,
cee4d264 1104 dma_addr_t pbl_addr,
dacd88d6 1105 u16 pbl_size, void __iomem **pp_doorbell)
cee4d264 1106{
cee4d264
MC		 1107 int rc;
1108
dacd88d6 1109
3da7a37a
MY		 1110 rc = qed_eth_txq_start_ramrod(p_hwfn, p_cid,
1111 pbl_addr, pbl_size,
b5a9ee7c 1112 qed_get_cm_pq_idx_mcos(p_hwfn, tc));
cee4d264
MC		 1113 if (rc)
1114 return rc;
1115
3da7a37a
MY		 1116 /* Provide the caller with the necessary return values */
1117 *pp_doorbell = p_hwfn->doorbells +
1118 qed_db_addr(p_cid->cid, DQ_DEMS_LEGACY);
cee4d264 1119
3da7a37a
MY		 1120 return 0;
1121}
cee4d264 1122
3da7a37a
MY		 1123static int
1124qed_eth_tx_queue_start(struct qed_hwfn *p_hwfn,
1125 u16 opaque_fid,
1126 struct qed_queue_start_common_params *p_params,
1127 u8 tc,
1128 dma_addr_t pbl_addr,
1129 u16 pbl_size,
1130 struct qed_txq_start_ret_params *p_ret_params)
1131{
1132 struct qed_queue_cid *p_cid;
1133 int rc;
1134
3946497a 1135 p_cid = qed_eth_queue_to_cid_pf(p_hwfn, opaque_fid, p_params);
3da7a37a
MY		 1136 if (!p_cid)
1137 return -EINVAL;
1138
1139 if (IS_PF(p_hwfn->cdev))
1140 rc = qed_eth_pf_tx_queue_start(p_hwfn, p_cid, tc,
1141 pbl_addr, pbl_size,
1142 &p_ret_params->p_doorbell);
1143 else
1144 rc = qed_vf_pf_txq_start(p_hwfn, p_cid,
1145 pbl_addr, pbl_size,
1146 &p_ret_params->p_doorbell);
cee4d264
MC		 1147
1148 if (rc)
3da7a37a
MY		 1149 qed_eth_queue_cid_release(p_hwfn, p_cid);
1150 else
1151 p_ret_params->p_handle = (void *)p_cid;
cee4d264
MC		 1152
1153 return rc;
1154}
1155
3da7a37a
MY		 1156static int
1157qed_eth_pf_tx_queue_stop(struct qed_hwfn *p_hwfn, struct qed_queue_cid *p_cid)
cee4d264 1158{
cee4d264 1159 struct qed_spq_entry *p_ent = NULL;
06f56b81 1160 struct qed_sp_init_data init_data;
3da7a37a 1161 int rc;
dacd88d6 1162
06f56b81 1163 memset(&init_data, 0, sizeof(init_data));
3da7a37a
MY		 1164 init_data.cid = p_cid->cid;
1165 init_data.opaque_fid = p_cid->opaque_fid;
06f56b81 1166 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
cee4d264
MC		 1167
1168 rc = qed_sp_init_request(p_hwfn, &p_ent,
cee4d264 1169 ETH_RAMROD_TX_QUEUE_STOP,
06f56b81 1170 PROTOCOLID_ETH, &init_data);
cee4d264
MC		 1171 if (rc)
1172 return rc;
1173
3da7a37a
MY		 1174 return qed_spq_post(p_hwfn, p_ent, NULL);
1175}
1176
1177int qed_eth_tx_queue_stop(struct qed_hwfn *p_hwfn, void *p_handle)
1178{
1179 struct qed_queue_cid *p_cid = (struct qed_queue_cid *)p_handle;
1180 int rc;
1181
1182 if (IS_PF(p_hwfn->cdev))
1183 rc = qed_eth_pf_tx_queue_stop(p_hwfn, p_cid);
1184 else
1185 rc = qed_vf_pf_txq_stop(p_hwfn, p_cid);
cee4d264 1186
3da7a37a
MY		 1187 if (!rc)
1188 qed_eth_queue_cid_release(p_hwfn, p_cid);
1189 return rc;
cee4d264
MC		 1190}
1191
1a635e48 1192static enum eth_filter_action qed_filter_action(enum qed_filter_opcode opcode)
cee4d264
MC		 1193{
1194 enum eth_filter_action action = MAX_ETH_FILTER_ACTION;
1195
1196 switch (opcode) {
1197 case QED_FILTER_ADD:
1198 action = ETH_FILTER_ACTION_ADD;
1199 break;
1200 case QED_FILTER_REMOVE:
1201 action = ETH_FILTER_ACTION_REMOVE;
1202 break;
cee4d264 1203 case QED_FILTER_FLUSH:
fc48b7a6 1204 action = ETH_FILTER_ACTION_REMOVE_ALL;
cee4d264
MC		 1205 break;
1206 default:
1207 action = MAX_ETH_FILTER_ACTION;
1208 }
1209
1210 return action;
1211}
1212
1213static void qed_set_fw_mac_addr(__le16 *fw_msb,
1214 __le16 *fw_mid,
1215 __le16 *fw_lsb,
1216 u8 *mac)
1217{
1218 ((u8 *)fw_msb)[0] = mac[1];
1219 ((u8 *)fw_msb)[1] = mac[0];
1220 ((u8 *)fw_mid)[0] = mac[3];
1221 ((u8 *)fw_mid)[1] = mac[2];
1222 ((u8 *)fw_lsb)[0] = mac[5];
1223 ((u8 *)fw_lsb)[1] = mac[4];
1224}
1225
1226static int
1227qed_filter_ucast_common(struct qed_hwfn *p_hwfn,
1228 u16 opaque_fid,
1229 struct qed_filter_ucast *p_filter_cmd,
1230 struct vport_filter_update_ramrod_data **pp_ramrod,
1231 struct qed_spq_entry **pp_ent,
1232 enum spq_mode comp_mode,
1233 struct qed_spq_comp_cb *p_comp_data)
1234{
1235 u8 vport_to_add_to = 0, vport_to_remove_from = 0;
1236 struct vport_filter_update_ramrod_data *p_ramrod;
cee4d264
MC		 1237 struct eth_filter_cmd *p_first_filter;
1238 struct eth_filter_cmd *p_second_filter;
06f56b81 1239 struct qed_sp_init_data init_data;
cee4d264
MC		 1240 enum eth_filter_action action;
1241 int rc;
1242
1243 rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from,
1244 &vport_to_remove_from);
1245 if (rc)
1246 return rc;
1247
1248 rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to,
1249 &vport_to_add_to);
1250 if (rc)
1251 return rc;
1252
06f56b81
YM		 1253 /* Get SPQ entry */
1254 memset(&init_data, 0, sizeof(init_data));
1255 init_data.cid = qed_spq_get_cid(p_hwfn);
1256 init_data.opaque_fid = opaque_fid;
1257 init_data.comp_mode = comp_mode;
1258 init_data.p_comp_data = p_comp_data;
cee4d264
MC		 1259
1260 rc = qed_sp_init_request(p_hwfn, pp_ent,
cee4d264 1261 ETH_RAMROD_FILTERS_UPDATE,
06f56b81 1262 PROTOCOLID_ETH, &init_data);
cee4d264
MC		 1263 if (rc)
1264 return rc;
1265
1266 *pp_ramrod = &(*pp_ent)->ramrod.vport_filter_update;
1267 p_ramrod = *pp_ramrod;
1268 p_ramrod->filter_cmd_hdr.rx = p_filter_cmd->is_rx_filter ? 1 : 0;
1269 p_ramrod->filter_cmd_hdr.tx = p_filter_cmd->is_tx_filter ? 1 : 0;
1270
1271 switch (p_filter_cmd->opcode) {
fc48b7a6 1272 case QED_FILTER_REPLACE:
cee4d264
MC		 1273 case QED_FILTER_MOVE:
1274 p_ramrod->filter_cmd_hdr.cmd_cnt = 2; break;
1275 default:
1276 p_ramrod->filter_cmd_hdr.cmd_cnt = 1; break;
1277 }
1278
1279 p_first_filter = &p_ramrod->filter_cmds[0];
1280 p_second_filter = &p_ramrod->filter_cmds[1];
1281
1282 switch (p_filter_cmd->type) {
1283 case QED_FILTER_MAC:
1284 p_first_filter->type = ETH_FILTER_TYPE_MAC; break;
1285 case QED_FILTER_VLAN:
1286 p_first_filter->type = ETH_FILTER_TYPE_VLAN; break;
1287 case QED_FILTER_MAC_VLAN:
1288 p_first_filter->type = ETH_FILTER_TYPE_PAIR; break;
1289 case QED_FILTER_INNER_MAC:
1290 p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC; break;
1291 case QED_FILTER_INNER_VLAN:
1292 p_first_filter->type = ETH_FILTER_TYPE_INNER_VLAN; break;
1293 case QED_FILTER_INNER_PAIR:
1294 p_first_filter->type = ETH_FILTER_TYPE_INNER_PAIR; break;
1295 case QED_FILTER_INNER_MAC_VNI_PAIR:
1296 p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR;
1297 break;
1298 case QED_FILTER_MAC_VNI_PAIR:
1299 p_first_filter->type = ETH_FILTER_TYPE_MAC_VNI_PAIR; break;
1300 case QED_FILTER_VNI:
1301 p_first_filter->type = ETH_FILTER_TYPE_VNI; break;
1302 }
1303
1304 if ((p_first_filter->type == ETH_FILTER_TYPE_MAC) ||
1305 (p_first_filter->type == ETH_FILTER_TYPE_PAIR) ||
1306 (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC) ||
1307 (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR) ||
1308 (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) ||
1309 (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR)) {
1310 qed_set_fw_mac_addr(&p_first_filter->mac_msb,
1311 &p_first_filter->mac_mid,
1312 &p_first_filter->mac_lsb,
1313 (u8 *)p_filter_cmd->mac);
1314 }
1315
1316 if ((p_first_filter->type == ETH_FILTER_TYPE_VLAN) ||
1317 (p_first_filter->type == ETH_FILTER_TYPE_PAIR) ||
1318 (p_first_filter->type == ETH_FILTER_TYPE_INNER_VLAN) ||
1319 (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR))
1320 p_first_filter->vlan_id = cpu_to_le16(p_filter_cmd->vlan);
1321
1322 if ((p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) ||
1323 (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR) ||
1324 (p_first_filter->type == ETH_FILTER_TYPE_VNI))
1325 p_first_filter->vni = cpu_to_le32(p_filter_cmd->vni);
1326
1327 if (p_filter_cmd->opcode == QED_FILTER_MOVE) {
1a635e48
YM		 1328 p_second_filter->type = p_first_filter->type;
1329 p_second_filter->mac_msb = p_first_filter->mac_msb;
1330 p_second_filter->mac_mid = p_first_filter->mac_mid;
1331 p_second_filter->mac_lsb = p_first_filter->mac_lsb;
1332 p_second_filter->vlan_id = p_first_filter->vlan_id;
1333 p_second_filter->vni = p_first_filter->vni;
cee4d264
MC		 1334
1335 p_first_filter->action = ETH_FILTER_ACTION_REMOVE;
1336
1337 p_first_filter->vport_id = vport_to_remove_from;
1338
1a635e48
YM		 1339 p_second_filter->action = ETH_FILTER_ACTION_ADD;
1340 p_second_filter->vport_id = vport_to_add_to;
fc48b7a6
YM		 1341 } else if (p_filter_cmd->opcode == QED_FILTER_REPLACE) {
1342 p_first_filter->vport_id = vport_to_add_to;
1343 memcpy(p_second_filter, p_first_filter,
1344 sizeof(*p_second_filter));
1345 p_first_filter->action = ETH_FILTER_ACTION_REMOVE_ALL;
1346 p_second_filter->action = ETH_FILTER_ACTION_ADD;
cee4d264
MC		 1347 } else {
1348 action = qed_filter_action(p_filter_cmd->opcode);
1349
1350 if (action == MAX_ETH_FILTER_ACTION) {
1351 DP_NOTICE(p_hwfn,
1352 "%d is not supported yet\n",
1353 p_filter_cmd->opcode);
1354 return -EINVAL;
1355 }
1356
1357 p_first_filter->action = action;
1358 p_first_filter->vport_id = (p_filter_cmd->opcode ==
1359 QED_FILTER_REMOVE) ?
1360 vport_to_remove_from :
1361 vport_to_add_to;
1362 }
1363
1364 return 0;
1365}
1366
dacd88d6
YM		 1367int qed_sp_eth_filter_ucast(struct qed_hwfn *p_hwfn,
1368 u16 opaque_fid,
1369 struct qed_filter_ucast *p_filter_cmd,
1370 enum spq_mode comp_mode,
1371 struct qed_spq_comp_cb *p_comp_data)
cee4d264
MC		 1372{
1373 struct vport_filter_update_ramrod_data *p_ramrod = NULL;
1374 struct qed_spq_entry *p_ent = NULL;
1375 struct eth_filter_cmd_header *p_header;
1376 int rc;
1377
1378 rc = qed_filter_ucast_common(p_hwfn, opaque_fid, p_filter_cmd,
1379 &p_ramrod, &p_ent,
1380 comp_mode, p_comp_data);
1a635e48 1381 if (rc) {
cee4d264
MC		 1382 DP_ERR(p_hwfn, "Uni. filter command failed %d\n", rc);
1383 return rc;
1384 }
1385 p_header = &p_ramrod->filter_cmd_hdr;
1386 p_header->assert_on_error = p_filter_cmd->assert_on_error;
1387
1388 rc = qed_spq_post(p_hwfn, p_ent, NULL);
1a635e48
YM		 1389 if (rc) {
1390 DP_ERR(p_hwfn, "Unicast filter ADD command failed %d\n", rc);
cee4d264
MC		 1391 return rc;
1392 }
1393
1394 DP_VERBOSE(p_hwfn, QED_MSG_SP,
1395 "Unicast filter configured, opcode = %s, type = %s, cmd_cnt = %d, is_rx_filter = %d, is_tx_filter = %d\n",
1396 (p_filter_cmd->opcode == QED_FILTER_ADD) ? "ADD" :
1397 ((p_filter_cmd->opcode == QED_FILTER_REMOVE) ?
1398 "REMOVE" :
1399 ((p_filter_cmd->opcode == QED_FILTER_MOVE) ?
1400 "MOVE" : "REPLACE")),
1401 (p_filter_cmd->type == QED_FILTER_MAC) ? "MAC" :
1402 ((p_filter_cmd->type == QED_FILTER_VLAN) ?
1403 "VLAN" : "MAC & VLAN"),
1404 p_ramrod->filter_cmd_hdr.cmd_cnt,
1405 p_filter_cmd->is_rx_filter,
1406 p_filter_cmd->is_tx_filter);
1407 DP_VERBOSE(p_hwfn, QED_MSG_SP,
1408 "vport_to_add_to = %d, vport_to_remove_from = %d, mac = %2x:%2x:%2x:%2x:%2x:%2x, vlan = %d\n",
1409 p_filter_cmd->vport_to_add_to,
1410 p_filter_cmd->vport_to_remove_from,
1411 p_filter_cmd->mac[0],
1412 p_filter_cmd->mac[1],
1413 p_filter_cmd->mac[2],
1414 p_filter_cmd->mac[3],
1415 p_filter_cmd->mac[4],
1416 p_filter_cmd->mac[5],
1417 p_filter_cmd->vlan);
1418
1419 return 0;
1420}
1421
1422/*******************************************************************************
1423 * Description:
1424 * Calculates crc 32 on a buffer
1425 * Note: crc32_length MUST be aligned to 8
1426 * Return:
1427 ******************************************************************************/
1428static u32 qed_calc_crc32c(u8 *crc32_packet,
1a635e48 1429 u32 crc32_length, u32 crc32_seed, u8 complement)
cee4d264 1430{
1a635e48
YM		 1431 u32 byte = 0, bit = 0, crc32_result = crc32_seed;
1432 u8 msb = 0, current_byte = 0;
cee4d264
MC		 1433
1434 if ((!crc32_packet) ||
1435 (crc32_length == 0) ||
1436 ((crc32_length % 8) != 0))
1437 return crc32_result;
1438 for (byte = 0; byte < crc32_length; byte++) {
1439 current_byte = crc32_packet[byte];
1440 for (bit = 0; bit < 8; bit++) {
1441 msb = (u8)(crc32_result >> 31);
1442 crc32_result = crc32_result << 1;
1443 if (msb != (0x1 & (current_byte >> bit))) {
1444 crc32_result = crc32_result ^ CRC32_POLY;
1445 crc32_result |= 1; /*crc32_result[0] = 1;*/
1446 }
1447 }
1448 }
1449 return crc32_result;
1450}
1451
1a635e48 1452static u32 qed_crc32c_le(u32 seed, u8 *mac, u32 len)
cee4d264
MC		 1453{
1454 u32 packet_buf[2] = { 0 };
1455
1456 memcpy((u8 *)(&packet_buf[0]), &mac[0], 6);
1457 return qed_calc_crc32c((u8 *)packet_buf, 8, seed, 0);
1458}
1459
dacd88d6 1460u8 qed_mcast_bin_from_mac(u8 *mac)
cee4d264
MC		 1461{
1462 u32 crc = qed_crc32c_le(ETH_MULTICAST_BIN_FROM_MAC_SEED,
1463 mac, ETH_ALEN);
1464
1465 return crc & 0xff;
1466}
1467
1468static int
1469qed_sp_eth_filter_mcast(struct qed_hwfn *p_hwfn,
1470 u16 opaque_fid,
1471 struct qed_filter_mcast *p_filter_cmd,
1472 enum spq_mode comp_mode,
1473 struct qed_spq_comp_cb *p_comp_data)
1474{
1475 unsigned long bins[ETH_MULTICAST_MAC_BINS_IN_REGS];
1476 struct vport_update_ramrod_data *p_ramrod = NULL;
cee4d264 1477 struct qed_spq_entry *p_ent = NULL;
06f56b81 1478 struct qed_sp_init_data init_data;
cee4d264
MC		 1479 u8 abs_vport_id = 0;
1480 int rc, i;
1481
83aeb933 1482 if (p_filter_cmd->opcode == QED_FILTER_ADD)
cee4d264
MC		 1483 rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to,
1484 &abs_vport_id);
83aeb933 1485 else
cee4d264
MC		 1486 rc = qed_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from,
1487 &abs_vport_id);
83aeb933
YM		 1488 if (rc)
1489 return rc;
cee4d264 1490
06f56b81
YM		 1491 /* Get SPQ entry */
1492 memset(&init_data, 0, sizeof(init_data));
1493 init_data.cid = qed_spq_get_cid(p_hwfn);
1494 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
1495 init_data.comp_mode = comp_mode;
1496 init_data.p_comp_data = p_comp_data;
cee4d264
MC		 1497
1498 rc = qed_sp_init_request(p_hwfn, &p_ent,
cee4d264 1499 ETH_RAMROD_VPORT_UPDATE,
06f56b81 1500 PROTOCOLID_ETH, &init_data);
cee4d264
MC		 1501 if (rc) {
1502 DP_ERR(p_hwfn, "Multi-cast command failed %d\n", rc);
1503 return rc;
1504 }
1505
1506 p_ramrod = &p_ent->ramrod.vport_update;
1507 p_ramrod->common.update_approx_mcast_flg = 1;
1508
1509 /* explicitly clear out the entire vector */
1510 memset(&p_ramrod->approx_mcast.bins, 0,
1511 sizeof(p_ramrod->approx_mcast.bins));
1512 memset(bins, 0, sizeof(unsigned long) *
1513 ETH_MULTICAST_MAC_BINS_IN_REGS);
1514 /* filter ADD op is explicit set op and it removes
1515 * any existing filters for the vport
1516 */
1517 if (p_filter_cmd->opcode == QED_FILTER_ADD) {
1518 for (i = 0; i < p_filter_cmd->num_mc_addrs; i++) {
1519 u32 bit;
1520
1521 bit = qed_mcast_bin_from_mac(p_filter_cmd->mac[i]);
1522 __set_bit(bit, bins);
1523 }
1524
1525 /* Convert to correct endianity */
1526 for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) {
1a635e48 1527 struct vport_update_ramrod_mcast *p_ramrod_bins;
cee4d264 1528 u32 *p_bins = (u32 *)bins;
cee4d264 1529
1a635e48
YM		 1530 p_ramrod_bins = &p_ramrod->approx_mcast;
1531 p_ramrod_bins->bins[i] = cpu_to_le32(p_bins[i]);
cee4d264
MC		 1532 }
1533 }
1534
1535 p_ramrod->common.vport_id = abs_vport_id;
1536
1537 return qed_spq_post(p_hwfn, p_ent, NULL);
1538}
1539
dacd88d6
YM		 1540static int qed_filter_mcast_cmd(struct qed_dev *cdev,
1541 struct qed_filter_mcast *p_filter_cmd,
1542 enum spq_mode comp_mode,
1543 struct qed_spq_comp_cb *p_comp_data)
cee4d264
MC		 1544{
1545 int rc = 0;
1546 int i;
1547
1548 /* only ADD and REMOVE operations are supported for multi-cast */
1549 if ((p_filter_cmd->opcode != QED_FILTER_ADD &&
1550 (p_filter_cmd->opcode != QED_FILTER_REMOVE)) ||
1551 (p_filter_cmd->num_mc_addrs > QED_MAX_MC_ADDRS))
1552 return -EINVAL;
1553
1554 for_each_hwfn(cdev, i) {
1555 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1556
1557 u16 opaque_fid;
1558
dacd88d6
YM		 1559 if (IS_VF(cdev)) {
1560 qed_vf_pf_filter_mcast(p_hwfn, p_filter_cmd);
1561 continue;
1562 }
cee4d264
MC		 1563
1564 opaque_fid = p_hwfn->hw_info.opaque_fid;
1565
1566 rc = qed_sp_eth_filter_mcast(p_hwfn,
1567 opaque_fid,
1568 p_filter_cmd,
1a635e48 1569 comp_mode, p_comp_data);
cee4d264
MC		 1570 }
1571 return rc;
1572}
1573
1574static int qed_filter_ucast_cmd(struct qed_dev *cdev,
1575 struct qed_filter_ucast *p_filter_cmd,
1576 enum spq_mode comp_mode,
1577 struct qed_spq_comp_cb *p_comp_data)
1578{
1579 int rc = 0;
1580 int i;
1581
1582 for_each_hwfn(cdev, i) {
1583 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1584 u16 opaque_fid;
1585
dacd88d6
YM		 1586 if (IS_VF(cdev)) {
1587 rc = qed_vf_pf_filter_ucast(p_hwfn, p_filter_cmd);
1588 continue;
1589 }
cee4d264
MC		 1590
1591 opaque_fid = p_hwfn->hw_info.opaque_fid;
1592
1593 rc = qed_sp_eth_filter_ucast(p_hwfn,
1594 opaque_fid,
1595 p_filter_cmd,
1a635e48
YM		 1596 comp_mode, p_comp_data);
1597 if (rc)
dacd88d6 1598 break;
cee4d264
MC		 1599 }
1600
1601 return rc;
1602}
1603
86622ee7
YM		 1604/* Statistics related code */
1605static void __qed_get_vport_pstats_addrlen(struct qed_hwfn *p_hwfn,
1606 u32 *p_addr,
dacd88d6 1607 u32 *p_len, u16 statistics_bin)
86622ee7 1608{
dacd88d6
YM		 1609 if (IS_PF(p_hwfn->cdev)) {
1610 *p_addr = BAR0_MAP_REG_PSDM_RAM +
1611 PSTORM_QUEUE_STAT_OFFSET(statistics_bin);
1612 *p_len = sizeof(struct eth_pstorm_per_queue_stat);
1613 } else {
1614 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
1615 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1616
1617 *p_addr = p_resp->pfdev_info.stats_info.pstats.address;
1618 *p_len = p_resp->pfdev_info.stats_info.pstats.len;
1619 }
86622ee7
YM		 1620}
1621
1622static void __qed_get_vport_pstats(struct qed_hwfn *p_hwfn,
1623 struct qed_ptt *p_ptt,
1624 struct qed_eth_stats *p_stats,
1625 u16 statistics_bin)
1626{
1627 struct eth_pstorm_per_queue_stat pstats;
1628 u32 pstats_addr = 0, pstats_len = 0;
1629
1630 __qed_get_vport_pstats_addrlen(p_hwfn, &pstats_addr, &pstats_len,
1631 statistics_bin);
1632
1633 memset(&pstats, 0, sizeof(pstats));
dacd88d6
YM		 1634 qed_memcpy_from(p_hwfn, p_ptt, &pstats, pstats_addr, pstats_len);
1635
9c79ddaa
MY		 1636 p_stats->common.tx_ucast_bytes +=
1637 HILO_64_REGPAIR(pstats.sent_ucast_bytes);
1638 p_stats->common.tx_mcast_bytes +=
1639 HILO_64_REGPAIR(pstats.sent_mcast_bytes);
1640 p_stats->common.tx_bcast_bytes +=
1641 HILO_64_REGPAIR(pstats.sent_bcast_bytes);
1642 p_stats->common.tx_ucast_pkts +=
1643 HILO_64_REGPAIR(pstats.sent_ucast_pkts);
1644 p_stats->common.tx_mcast_pkts +=
1645 HILO_64_REGPAIR(pstats.sent_mcast_pkts);
1646 p_stats->common.tx_bcast_pkts +=
1647 HILO_64_REGPAIR(pstats.sent_bcast_pkts);
1648 p_stats->common.tx_err_drop_pkts +=
1649 HILO_64_REGPAIR(pstats.error_drop_pkts);
86622ee7
YM		 1650}
1651
1652static void __qed_get_vport_tstats(struct qed_hwfn *p_hwfn,
1653 struct qed_ptt *p_ptt,
1654 struct qed_eth_stats *p_stats,
1655 u16 statistics_bin)
1656{
86622ee7 1657 struct tstorm_per_port_stat tstats;
dacd88d6 1658 u32 tstats_addr, tstats_len;
86622ee7 1659
dacd88d6
YM		 1660 if (IS_PF(p_hwfn->cdev)) {
1661 tstats_addr = BAR0_MAP_REG_TSDM_RAM +
1662 TSTORM_PORT_STAT_OFFSET(MFW_PORT(p_hwfn));
1663 tstats_len = sizeof(struct tstorm_per_port_stat);
1664 } else {
1665 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
1666 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1667
1668 tstats_addr = p_resp->pfdev_info.stats_info.tstats.address;
1669 tstats_len = p_resp->pfdev_info.stats_info.tstats.len;
1670 }
86622ee7
YM		 1671
1672 memset(&tstats, 0, sizeof(tstats));
dacd88d6 1673 qed_memcpy_from(p_hwfn, p_ptt, &tstats, tstats_addr, tstats_len);
86622ee7 1674
9c79ddaa
MY		 1675 p_stats->common.mftag_filter_discards +=
1676 HILO_64_REGPAIR(tstats.mftag_filter_discard);
1677 p_stats->common.mac_filter_discards +=
1678 HILO_64_REGPAIR(tstats.eth_mac_filter_discard);
86622ee7
YM		 1679}
1680
1681static void __qed_get_vport_ustats_addrlen(struct qed_hwfn *p_hwfn,
1682 u32 *p_addr,
dacd88d6 1683 u32 *p_len, u16 statistics_bin)
86622ee7 1684{
dacd88d6
YM		 1685 if (IS_PF(p_hwfn->cdev)) {
1686 *p_addr = BAR0_MAP_REG_USDM_RAM +
1687 USTORM_QUEUE_STAT_OFFSET(statistics_bin);
1688 *p_len = sizeof(struct eth_ustorm_per_queue_stat);
1689 } else {
1690 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
1691 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1692
1693 *p_addr = p_resp->pfdev_info.stats_info.ustats.address;
1694 *p_len = p_resp->pfdev_info.stats_info.ustats.len;
1695 }
86622ee7
YM		 1696}
1697
1698static void __qed_get_vport_ustats(struct qed_hwfn *p_hwfn,
1699 struct qed_ptt *p_ptt,
1700 struct qed_eth_stats *p_stats,
1701 u16 statistics_bin)
1702{
1703 struct eth_ustorm_per_queue_stat ustats;
1704 u32 ustats_addr = 0, ustats_len = 0;
1705
1706 __qed_get_vport_ustats_addrlen(p_hwfn, &ustats_addr, &ustats_len,
1707 statistics_bin);
1708
1709 memset(&ustats, 0, sizeof(ustats));
dacd88d6
YM		 1710 qed_memcpy_from(p_hwfn, p_ptt, &ustats, ustats_addr, ustats_len);
1711
9c79ddaa
MY		 1712 p_stats->common.rx_ucast_bytes +=
1713 HILO_64_REGPAIR(ustats.rcv_ucast_bytes);
1714 p_stats->common.rx_mcast_bytes +=
1715 HILO_64_REGPAIR(ustats.rcv_mcast_bytes);
1716 p_stats->common.rx_bcast_bytes +=
1717 HILO_64_REGPAIR(ustats.rcv_bcast_bytes);
1718 p_stats->common.rx_ucast_pkts += HILO_64_REGPAIR(ustats.rcv_ucast_pkts);
1719 p_stats->common.rx_mcast_pkts += HILO_64_REGPAIR(ustats.rcv_mcast_pkts);
1720 p_stats->common.rx_bcast_pkts += HILO_64_REGPAIR(ustats.rcv_bcast_pkts);
86622ee7
YM		 1721}
1722
1723static void __qed_get_vport_mstats_addrlen(struct qed_hwfn *p_hwfn,
1724 u32 *p_addr,
dacd88d6 1725 u32 *p_len, u16 statistics_bin)
86622ee7 1726{
dacd88d6
YM		 1727 if (IS_PF(p_hwfn->cdev)) {
1728 *p_addr = BAR0_MAP_REG_MSDM_RAM +
1729 MSTORM_QUEUE_STAT_OFFSET(statistics_bin);
1730 *p_len = sizeof(struct eth_mstorm_per_queue_stat);
1731 } else {
1732 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
1733 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1734
1735 *p_addr = p_resp->pfdev_info.stats_info.mstats.address;
1736 *p_len = p_resp->pfdev_info.stats_info.mstats.len;
1737 }
86622ee7
YM		 1738}
1739
1740static void __qed_get_vport_mstats(struct qed_hwfn *p_hwfn,
1741 struct qed_ptt *p_ptt,
1742 struct qed_eth_stats *p_stats,
1743 u16 statistics_bin)
1744{
1745 struct eth_mstorm_per_queue_stat mstats;
1746 u32 mstats_addr = 0, mstats_len = 0;
1747
1748 __qed_get_vport_mstats_addrlen(p_hwfn, &mstats_addr, &mstats_len,
1749 statistics_bin);
1750
1751 memset(&mstats, 0, sizeof(mstats));
dacd88d6 1752 qed_memcpy_from(p_hwfn, p_ptt, &mstats, mstats_addr, mstats_len);
86622ee7 1753
9c79ddaa
MY		 1754 p_stats->common.no_buff_discards +=
1755 HILO_64_REGPAIR(mstats.no_buff_discard);
1756 p_stats->common.packet_too_big_discard +=
1757 HILO_64_REGPAIR(mstats.packet_too_big_discard);
1758 p_stats->common.ttl0_discard += HILO_64_REGPAIR(mstats.ttl0_discard);
1759 p_stats->common.tpa_coalesced_pkts +=
1760 HILO_64_REGPAIR(mstats.tpa_coalesced_pkts);
1761 p_stats->common.tpa_coalesced_events +=
1762 HILO_64_REGPAIR(mstats.tpa_coalesced_events);
1763 p_stats->common.tpa_aborts_num +=
1764 HILO_64_REGPAIR(mstats.tpa_aborts_num);
1765 p_stats->common.tpa_coalesced_bytes +=
1766 HILO_64_REGPAIR(mstats.tpa_coalesced_bytes);
86622ee7
YM		 1767}
1768
1769static void __qed_get_vport_port_stats(struct qed_hwfn *p_hwfn,
1770 struct qed_ptt *p_ptt,
1771 struct qed_eth_stats *p_stats)
1772{
9c79ddaa 1773 struct qed_eth_stats_common *p_common = &p_stats->common;
86622ee7
YM		 1774 struct port_stats port_stats;
1775 int j;
1776
1777 memset(&port_stats, 0, sizeof(port_stats));
1778
1779 qed_memcpy_from(p_hwfn, p_ptt, &port_stats,
1780 p_hwfn->mcp_info->port_addr +
1781 offsetof(struct public_port, stats),
1782 sizeof(port_stats));
1783
9c79ddaa
MY		 1784 p_common->rx_64_byte_packets += port_stats.eth.r64;
1785 p_common->rx_65_to_127_byte_packets += port_stats.eth.r127;
1786 p_common->rx_128_to_255_byte_packets += port_stats.eth.r255;
1787 p_common->rx_256_to_511_byte_packets += port_stats.eth.r511;
1788 p_common->rx_512_to_1023_byte_packets += port_stats.eth.r1023;
1789 p_common->rx_1024_to_1518_byte_packets += port_stats.eth.r1518;
1790 p_common->rx_crc_errors += port_stats.eth.rfcs;
1791 p_common->rx_mac_crtl_frames += port_stats.eth.rxcf;
1792 p_common->rx_pause_frames += port_stats.eth.rxpf;
1793 p_common->rx_pfc_frames += port_stats.eth.rxpp;
1794 p_common->rx_align_errors += port_stats.eth.raln;
1795 p_common->rx_carrier_errors += port_stats.eth.rfcr;
1796 p_common->rx_oversize_packets += port_stats.eth.rovr;
1797 p_common->rx_jabbers += port_stats.eth.rjbr;
1798 p_common->rx_undersize_packets += port_stats.eth.rund;
1799 p_common->rx_fragments += port_stats.eth.rfrg;
1800 p_common->tx_64_byte_packets += port_stats.eth.t64;
1801 p_common->tx_65_to_127_byte_packets += port_stats.eth.t127;
1802 p_common->tx_128_to_255_byte_packets += port_stats.eth.t255;
1803 p_common->tx_256_to_511_byte_packets += port_stats.eth.t511;
1804 p_common->tx_512_to_1023_byte_packets += port_stats.eth.t1023;
1805 p_common->tx_1024_to_1518_byte_packets += port_stats.eth.t1518;
1806 p_common->tx_pause_frames += port_stats.eth.txpf;
1807 p_common->tx_pfc_frames += port_stats.eth.txpp;
1808 p_common->rx_mac_bytes += port_stats.eth.rbyte;
1809 p_common->rx_mac_uc_packets += port_stats.eth.rxuca;
1810 p_common->rx_mac_mc_packets += port_stats.eth.rxmca;
1811 p_common->rx_mac_bc_packets += port_stats.eth.rxbca;
1812 p_common->rx_mac_frames_ok += port_stats.eth.rxpok;
1813 p_common->tx_mac_bytes += port_stats.eth.tbyte;
1814 p_common->tx_mac_uc_packets += port_stats.eth.txuca;
1815 p_common->tx_mac_mc_packets += port_stats.eth.txmca;
1816 p_common->tx_mac_bc_packets += port_stats.eth.txbca;
1817 p_common->tx_mac_ctrl_frames += port_stats.eth.txcf;
86622ee7 1818 for (j = 0; j < 8; j++) {
9c79ddaa
MY		 1819 p_common->brb_truncates += port_stats.brb.brb_truncate[j];
1820 p_common->brb_discards += port_stats.brb.brb_discard[j];
1821 }
1822
1823 if (QED_IS_BB(p_hwfn->cdev)) {
1824 struct qed_eth_stats_bb *p_bb = &p_stats->bb;
1825
1826 p_bb->rx_1519_to_1522_byte_packets +=
1827 port_stats.eth.u0.bb0.r1522;
1828 p_bb->rx_1519_to_2047_byte_packets +=
1829 port_stats.eth.u0.bb0.r2047;
1830 p_bb->rx_2048_to_4095_byte_packets +=
1831 port_stats.eth.u0.bb0.r4095;
1832 p_bb->rx_4096_to_9216_byte_packets +=
1833 port_stats.eth.u0.bb0.r9216;
1834 p_bb->rx_9217_to_16383_byte_packets +=
1835 port_stats.eth.u0.bb0.r16383;
1836 p_bb->tx_1519_to_2047_byte_packets +=
1837 port_stats.eth.u1.bb1.t2047;
1838 p_bb->tx_2048_to_4095_byte_packets +=
1839 port_stats.eth.u1.bb1.t4095;
1840 p_bb->tx_4096_to_9216_byte_packets +=
1841 port_stats.eth.u1.bb1.t9216;
1842 p_bb->tx_9217_to_16383_byte_packets +=
1843 port_stats.eth.u1.bb1.t16383;
1844 p_bb->tx_lpi_entry_count += port_stats.eth.u2.bb2.tlpiec;
1845 p_bb->tx_total_collisions += port_stats.eth.u2.bb2.tncl;
1846 } else {
1847 struct qed_eth_stats_ah *p_ah = &p_stats->ah;
1848
1849 p_ah->rx_1519_to_max_byte_packets +=
1850 port_stats.eth.u0.ah0.r1519_to_max;
1851 p_ah->tx_1519_to_max_byte_packets =
1852 port_stats.eth.u1.ah1.t1519_to_max;
86622ee7
YM		 1853 }
1854}
1855
1856static void __qed_get_vport_stats(struct qed_hwfn *p_hwfn,
1857 struct qed_ptt *p_ptt,
1858 struct qed_eth_stats *stats,
dacd88d6 1859 u16 statistics_bin, bool b_get_port_stats)
86622ee7
YM		 1860{
1861 __qed_get_vport_mstats(p_hwfn, p_ptt, stats, statistics_bin);
1862 __qed_get_vport_ustats(p_hwfn, p_ptt, stats, statistics_bin);
1863 __qed_get_vport_tstats(p_hwfn, p_ptt, stats, statistics_bin);
1864 __qed_get_vport_pstats(p_hwfn, p_ptt, stats, statistics_bin);
1865
dacd88d6 1866 if (b_get_port_stats && p_hwfn->mcp_info)
86622ee7
YM		 1867 __qed_get_vport_port_stats(p_hwfn, p_ptt, stats);
1868}
1869
1870static void _qed_get_vport_stats(struct qed_dev *cdev,
1871 struct qed_eth_stats *stats)
1872{
dacd88d6
YM		 1873 u8 fw_vport = 0;
1874 int i;
86622ee7
YM		 1875
1876 memset(stats, 0, sizeof(*stats));
1877
1878 for_each_hwfn(cdev, i) {
1879 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
dacd88d6
YM		 1880 struct qed_ptt *p_ptt = IS_PF(cdev) ? qed_ptt_acquire(p_hwfn)
1881 : NULL;
1882
1883 if (IS_PF(cdev)) {
1884 /* The main vport index is relative first */
1885 if (qed_fw_vport(p_hwfn, 0, &fw_vport)) {
1886 DP_ERR(p_hwfn, "No vport available!\n");
1887 goto out;
1888 }
86622ee7
YM		 1889 }
1890
dacd88d6 1891 if (IS_PF(cdev) && !p_ptt) {
86622ee7
YM		 1892 DP_ERR(p_hwfn, "Failed to acquire ptt\n");
1893 continue;
1894 }
1895
dacd88d6
YM		 1896 __qed_get_vport_stats(p_hwfn, p_ptt, stats, fw_vport,
1897 IS_PF(cdev) ? true : false);
86622ee7 1898
dacd88d6
YM		 1899out:
1900 if (IS_PF(cdev) && p_ptt)
1901 qed_ptt_release(p_hwfn, p_ptt);
86622ee7
YM		 1902 }
1903}
1904
1a635e48 1905void qed_get_vport_stats(struct qed_dev *cdev, struct qed_eth_stats *stats)
86622ee7
YM		 1906{
1907 u32 i;
1908
1909 if (!cdev) {
1910 memset(stats, 0, sizeof(*stats));
1911 return;
1912 }
1913
1914 _qed_get_vport_stats(cdev, stats);
1915
1916 if (!cdev->reset_stats)
1917 return;
1918
1919 /* Reduce the statistics baseline */
1920 for (i = 0; i < sizeof(struct qed_eth_stats) / sizeof(u64); i++)
1921 ((u64 *)stats)[i] -= ((u64 *)cdev->reset_stats)[i];
1922}
1923
1924/* zeroes V-PORT specific portion of stats (Port stats remains untouched) */
1925void qed_reset_vport_stats(struct qed_dev *cdev)
1926{
1927 int i;
1928
1929 for_each_hwfn(cdev, i) {
1930 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1931 struct eth_mstorm_per_queue_stat mstats;
1932 struct eth_ustorm_per_queue_stat ustats;
1933 struct eth_pstorm_per_queue_stat pstats;
dacd88d6
YM		 1934 struct qed_ptt *p_ptt = IS_PF(cdev) ? qed_ptt_acquire(p_hwfn)
1935 : NULL;
86622ee7
YM		 1936 u32 addr = 0, len = 0;
1937
dacd88d6 1938 if (IS_PF(cdev) && !p_ptt) {
86622ee7
YM		 1939 DP_ERR(p_hwfn, "Failed to acquire ptt\n");
1940 continue;
1941 }
1942
1943 memset(&mstats, 0, sizeof(mstats));
1944 __qed_get_vport_mstats_addrlen(p_hwfn, &addr, &len, 0);
1945 qed_memcpy_to(p_hwfn, p_ptt, addr, &mstats, len);
1946
1947 memset(&ustats, 0, sizeof(ustats));
1948 __qed_get_vport_ustats_addrlen(p_hwfn, &addr, &len, 0);
1949 qed_memcpy_to(p_hwfn, p_ptt, addr, &ustats, len);
1950
1951 memset(&pstats, 0, sizeof(pstats));
1952 __qed_get_vport_pstats_addrlen(p_hwfn, &addr, &len, 0);
1953 qed_memcpy_to(p_hwfn, p_ptt, addr, &pstats, len);
1954
dacd88d6
YM		 1955 if (IS_PF(cdev))
1956 qed_ptt_release(p_hwfn, p_ptt);
86622ee7
YM		 1957 }
1958
1959 /* PORT statistics are not necessarily reset, so we need to
1960 * read and create a baseline for future statistics.
1961 */
1962 if (!cdev->reset_stats)
1963 DP_INFO(cdev, "Reset stats not allocated\n");
1964 else
1965 _qed_get_vport_stats(cdev, cdev->reset_stats);
1966}
1967
d51e4af5
CM		 1968static void
1969qed_arfs_mode_configure(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
1970 struct qed_arfs_config_params *p_cfg_params)
1971{
1972 if (p_cfg_params->arfs_enable) {
1973 qed_set_rfs_mode_enable(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
1974 p_cfg_params->tcp, p_cfg_params->udp,
1975 p_cfg_params->ipv4, p_cfg_params->ipv6);
1976 DP_VERBOSE(p_hwfn, QED_MSG_SP,
1977 "tcp = %s, udp = %s, ipv4 = %s, ipv6 =%s\n",
1978 p_cfg_params->tcp ? "Enable" : "Disable",
1979 p_cfg_params->udp ? "Enable" : "Disable",
1980 p_cfg_params->ipv4 ? "Enable" : "Disable",
1981 p_cfg_params->ipv6 ? "Enable" : "Disable");
1982 } else {
1983 qed_set_rfs_mode_disable(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1984 }
1985
1986 DP_VERBOSE(p_hwfn, QED_MSG_SP, "Configured ARFS mode : %s\n",
1987 p_cfg_params->arfs_enable ? "Enable" : "Disable");
1988}
1989
1990static int
1991qed_configure_rfs_ntuple_filter(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
1992 struct qed_spq_comp_cb *p_cb,
1993 dma_addr_t p_addr, u16 length, u16 qid,
1994 u8 vport_id, bool b_is_add)
1995{
1996 struct rx_update_gft_filter_data *p_ramrod = NULL;
1997 struct qed_spq_entry *p_ent = NULL;
1998 struct qed_sp_init_data init_data;
1999 u16 abs_rx_q_id = 0;
2000 u8 abs_vport_id = 0;
2001 int rc = -EINVAL;
2002
2003 rc = qed_fw_vport(p_hwfn, vport_id, &abs_vport_id);
2004 if (rc)
2005 return rc;
2006
2007 rc = qed_fw_l2_queue(p_hwfn, qid, &abs_rx_q_id);
2008 if (rc)
2009 return rc;
2010
2011 /* Get SPQ entry */
2012 memset(&init_data, 0, sizeof(init_data));
2013 init_data.cid = qed_spq_get_cid(p_hwfn);
2014
2015 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
2016
2017 if (p_cb) {
2018 init_data.comp_mode = QED_SPQ_MODE_CB;
2019 init_data.p_comp_data = p_cb;
2020 } else {
2021 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
2022 }
2023
2024 rc = qed_sp_init_request(p_hwfn, &p_ent,
2025 ETH_RAMROD_GFT_UPDATE_FILTER,
2026 PROTOCOLID_ETH, &init_data);
2027 if (rc)
2028 return rc;
2029
2030 p_ramrod = &p_ent->ramrod.rx_update_gft;
2031 DMA_REGPAIR_LE(p_ramrod->pkt_hdr_addr, p_addr);
2032 p_ramrod->pkt_hdr_length = cpu_to_le16(length);
2033 p_ramrod->rx_qid_or_action_icid = cpu_to_le16(abs_rx_q_id);
2034 p_ramrod->vport_id = abs_vport_id;
2035 p_ramrod->filter_type = RFS_FILTER_TYPE;
2036 p_ramrod->filter_action = b_is_add ? GFT_ADD_FILTER : GFT_DELETE_FILTER;
2037
2038 DP_VERBOSE(p_hwfn, QED_MSG_SP,
2039 "V[%0x], Q[%04x] - %s filter from 0x%llx [length %04xb]\n",
2040 abs_vport_id, abs_rx_q_id,
2041 b_is_add ? "Adding" : "Removing", (u64)p_addr, length);
2042
2043 return qed_spq_post(p_hwfn, p_ent, NULL);
2044}
2045
25c089d7
YM		 2046static int qed_fill_eth_dev_info(struct qed_dev *cdev,
2047 struct qed_dev_eth_info *info)
2048{
2049 int i;
2050
2051 memset(info, 0, sizeof(*info));
2052
2053 info->num_tc = 1;
2054
1408cc1f 2055 if (IS_PF(cdev)) {
25eb8d46 2056 int max_vf_vlan_filters = 0;
7b7e70f9 2057 int max_vf_mac_filters = 0;
25eb8d46 2058
1408cc1f 2059 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
e1d32acb
MY		 2060 u16 num_queues = 0;
2061
2062 /* Since the feature controls only queue-zones,
2063 * make sure we have the contexts [rx, tx, xdp] to
2064 * match.
2065 */
2066 for_each_hwfn(cdev, i) {
2067 struct qed_hwfn *hwfn = &cdev->hwfns[i];
2068 u16 l2_queues = (u16)FEAT_NUM(hwfn,
2069 QED_PF_L2_QUE);
2070 u16 cids;
2071
2072 cids = hwfn->pf_params.eth_pf_params.num_cons;
2073 num_queues += min_t(u16, l2_queues, cids / 3);
2074 }
2075
2076 /* queues might theoretically be >256, but interrupts'
2077 * upper-limit guarantes that it would fit in a u8.
2078 */
2079 if (cdev->int_params.fp_msix_cnt) {
2080 u8 irqs = cdev->int_params.fp_msix_cnt;
2081
2082 info->num_queues = (u8)min_t(u16,
2083 num_queues, irqs);
2084 }
1408cc1f
YM		 2085 } else {
2086 info->num_queues = cdev->num_hwfns;
2087 }
2088
7b7e70f9 2089 if (IS_QED_SRIOV(cdev)) {
25eb8d46
YM		 2090 max_vf_vlan_filters = cdev->p_iov_info->total_vfs *
2091 QED_ETH_VF_NUM_VLAN_FILTERS;
7b7e70f9
YM		 2092 max_vf_mac_filters = cdev->p_iov_info->total_vfs *
2093 QED_ETH_VF_NUM_MAC_FILTERS;
2094 }
2095 info->num_vlan_filters = RESC_NUM(QED_LEADING_HWFN(cdev),
2096 QED_VLAN) -
25eb8d46 2097 max_vf_vlan_filters;
7b7e70f9
YM		 2098 info->num_mac_filters = RESC_NUM(QED_LEADING_HWFN(cdev),
2099 QED_MAC) -
2100 max_vf_mac_filters;
25eb8d46 2101
1408cc1f
YM		 2102 ether_addr_copy(info->port_mac,
2103 cdev->hwfns[0].hw_info.hw_mac_addr);
25c089d7 2104 } else {
1408cc1f
YM		 2105 qed_vf_get_num_rxqs(QED_LEADING_HWFN(cdev), &info->num_queues);
2106 if (cdev->num_hwfns > 1) {
2107 u8 queues = 0;
25c089d7 2108
1408cc1f
YM		 2109 qed_vf_get_num_rxqs(&cdev->hwfns[1], &queues);
2110 info->num_queues += queues;
2111 }
2112
2113 qed_vf_get_num_vlan_filters(&cdev->hwfns[0],
2edbff8d 2114 (u8 *)&info->num_vlan_filters);
b0fca312
MY		 2115 qed_vf_get_num_mac_filters(&cdev->hwfns[0],
2116 (u8 *)&info->num_mac_filters);
1408cc1f 2117 qed_vf_get_port_mac(&cdev->hwfns[0], info->port_mac);
d8c2c7e3
YM		 2118
2119 info->is_legacy = !!cdev->hwfns[0].vf_iov_info->b_pre_fp_hsi;
1408cc1f 2120 }
25c089d7
YM		 2121
2122 qed_fill_dev_info(cdev, &info->common);
2123
1408cc1f 2124 if (IS_VF(cdev))
0ee28e31 2125 eth_zero_addr(info->common.hw_mac);
1408cc1f 2126
25c089d7
YM		 2127 return 0;
2128}
2129
cc875c2e 2130static void qed_register_eth_ops(struct qed_dev *cdev,
1408cc1f 2131 struct qed_eth_cb_ops *ops, void *cookie)
cc875c2e 2132{
1408cc1f
YM		 2133 cdev->protocol_ops.eth = ops;
2134 cdev->ops_cookie = cookie;
2135
2136 /* For VF, we start bulletin reading */
2137 if (IS_VF(cdev))
2138 qed_vf_start_iov_wq(cdev);
cc875c2e
YM		 2139}
2140
eff16960
YM		 2141static bool qed_check_mac(struct qed_dev *cdev, u8 *mac)
2142{
2143 if (IS_PF(cdev))
2144 return true;
2145
2146 return qed_vf_check_mac(&cdev->hwfns[0], mac);
2147}
2148
cee4d264 2149static int qed_start_vport(struct qed_dev *cdev,
088c8618 2150 struct qed_start_vport_params *params)
cee4d264
MC		 2151{
2152 int rc, i;
2153
2154 for_each_hwfn(cdev, i) {
088c8618 2155 struct qed_sp_vport_start_params start = { 0 };
cee4d264
MC		 2156 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2157
088c8618
MC		 2158 start.tpa_mode = params->gro_enable ? QED_TPA_MODE_GRO :
2159 QED_TPA_MODE_NONE;
2160 start.remove_inner_vlan = params->remove_inner_vlan;
08feecd7 2161 start.only_untagged = true; /* untagged only */
088c8618
MC		 2162 start.drop_ttl0 = params->drop_ttl0;
2163 start.opaque_fid = p_hwfn->hw_info.opaque_fid;
2164 start.concrete_fid = p_hwfn->hw_info.concrete_fid;
c78c70fa 2165 start.handle_ptp_pkts = params->handle_ptp_pkts;
088c8618
MC		 2166 start.vport_id = params->vport_id;
2167 start.max_buffers_per_cqe = 16;
2168 start.mtu = params->mtu;
2169
2170 rc = qed_sp_vport_start(p_hwfn, &start);
cee4d264
MC		 2171 if (rc) {
2172 DP_ERR(cdev, "Failed to start VPORT\n");
2173 return rc;
2174 }
2175
15582962
RV		 2176 rc = qed_hw_start_fastpath(p_hwfn);
2177 if (rc) {
2178 DP_ERR(cdev, "Failed to start VPORT fastpath\n");
2179 return rc;
2180 }
cee4d264
MC		 2181
2182 DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
2183 "Started V-PORT %d with MTU %d\n",
088c8618 2184 start.vport_id, start.mtu);
cee4d264
MC		 2185 }
2186
a0d26d5a
YM		 2187 if (params->clear_stats)
2188 qed_reset_vport_stats(cdev);
9df2ed04 2189
cee4d264
MC		 2190 return 0;
2191}
2192
1a635e48 2193static int qed_stop_vport(struct qed_dev *cdev, u8 vport_id)
cee4d264
MC		 2194{
2195 int rc, i;
2196
2197 for_each_hwfn(cdev, i) {
2198 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2199
2200 rc = qed_sp_vport_stop(p_hwfn,
1a635e48 2201 p_hwfn->hw_info.opaque_fid, vport_id);
cee4d264
MC		 2202
2203 if (rc) {
2204 DP_ERR(cdev, "Failed to stop VPORT\n");
2205 return rc;
2206 }
2207 }
2208 return 0;
2209}
2210
f29ffdb6
MY		 2211static int qed_update_vport_rss(struct qed_dev *cdev,
2212 struct qed_update_vport_rss_params *input,
2213 struct qed_rss_params *rss)
2214{
2215 int i, fn;
2216
2217 /* Update configuration with what's correct regardless of CMT */
2218 rss->update_rss_config = 1;
2219 rss->rss_enable = 1;
2220 rss->update_rss_capabilities = 1;
2221 rss->update_rss_ind_table = 1;
2222 rss->update_rss_key = 1;
2223 rss->rss_caps = input->rss_caps;
2224 memcpy(rss->rss_key, input->rss_key, QED_RSS_KEY_SIZE * sizeof(u32));
2225
2226 /* In regular scenario, we'd simply need to take input handlers.
2227 * But in CMT, we'd have to split the handlers according to the
2228 * engine they were configured on. We'd then have to understand
2229 * whether RSS is really required, since 2-queues on CMT doesn't
2230 * require RSS.
2231 */
2232 if (cdev->num_hwfns == 1) {
2233 memcpy(rss->rss_ind_table,
2234 input->rss_ind_table,
2235 QED_RSS_IND_TABLE_SIZE * sizeof(void *));
2236 rss->rss_table_size_log = 7;
2237 return 0;
2238 }
2239
2240 /* Start by copying the non-spcific information to the 2nd copy */
2241 memcpy(&rss[1], &rss[0], sizeof(struct qed_rss_params));
2242
2243 /* CMT should be round-robin */
2244 for (i = 0; i < QED_RSS_IND_TABLE_SIZE; i++) {
2245 struct qed_queue_cid *cid = input->rss_ind_table[i];
2246 struct qed_rss_params *t_rss;
2247
2248 if (cid->p_owner == QED_LEADING_HWFN(cdev))
2249 t_rss = &rss[0];
2250 else
2251 t_rss = &rss[1];
2252
2253 t_rss->rss_ind_table[i / cdev->num_hwfns] = cid;
2254 }
2255
2256 /* Make sure RSS is actually required */
2257 for_each_hwfn(cdev, fn) {
2258 for (i = 1; i < QED_RSS_IND_TABLE_SIZE / cdev->num_hwfns; i++) {
2259 if (rss[fn].rss_ind_table[i] !=
2260 rss[fn].rss_ind_table[0])
2261 break;
2262 }
2263 if (i == QED_RSS_IND_TABLE_SIZE / cdev->num_hwfns) {
2264 DP_VERBOSE(cdev, NETIF_MSG_IFUP,
2265 "CMT - 1 queue per-hwfn; Disabling RSS\n");
2266 return -EINVAL;
2267 }
2268 rss[fn].rss_table_size_log = 6;
2269 }
2270
2271 return 0;
2272}
2273
cee4d264
MC		 2274static int qed_update_vport(struct qed_dev *cdev,
2275 struct qed_update_vport_params *params)
2276{
2277 struct qed_sp_vport_update_params sp_params;
f29ffdb6
MY		 2278 struct qed_rss_params *rss;
2279 int rc = 0, i;
cee4d264
MC		 2280
2281 if (!cdev)
2282 return -ENODEV;
2283
f29ffdb6
MY		 2284 rss = vzalloc(sizeof(*rss) * cdev->num_hwfns);
2285 if (!rss)
2286 return -ENOMEM;
2287
cee4d264 2288 memset(&sp_params, 0, sizeof(sp_params));
cee4d264
MC		 2289
2290 /* Translate protocol params into sp params */
2291 sp_params.vport_id = params->vport_id;
1a635e48
YM		 2292 sp_params.update_vport_active_rx_flg = params->update_vport_active_flg;
2293 sp_params.update_vport_active_tx_flg = params->update_vport_active_flg;
cee4d264
MC		 2294 sp_params.vport_active_rx_flg = params->vport_active_flg;
2295 sp_params.vport_active_tx_flg = params->vport_active_flg;
831bfb0e
YM		 2296 sp_params.update_tx_switching_flg = params->update_tx_switching_flg;
2297 sp_params.tx_switching_flg = params->tx_switching_flg;
3f9b4a69
YM		 2298 sp_params.accept_any_vlan = params->accept_any_vlan;
2299 sp_params.update_accept_any_vlan_flg =
2300 params->update_accept_any_vlan_flg;
cee4d264 2301
f29ffdb6
MY		 2302 /* Prepare the RSS configuration */
2303 if (params->update_rss_flg)
2304 if (qed_update_vport_rss(cdev, &params->rss_params, rss))
cee4d264 2305 params->update_rss_flg = 0;
cee4d264
MC		 2306
2307 for_each_hwfn(cdev, i) {
2308 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2309
f29ffdb6
MY		 2310 if (params->update_rss_flg)
2311 sp_params.rss_params = &rss[i];
2312
cee4d264
MC		 2313 sp_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2314 rc = qed_sp_vport_update(p_hwfn, &sp_params,
2315 QED_SPQ_MODE_EBLOCK,
2316 NULL);
2317 if (rc) {
2318 DP_ERR(cdev, "Failed to update VPORT\n");
f29ffdb6 2319 goto out;
cee4d264
MC		 2320 }
2321
2322 DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
2323 "Updated V-PORT %d: active_flag %d [update %d]\n",
2324 params->vport_id, params->vport_active_flg,
2325 params->update_vport_active_flg);
2326 }
2327
f29ffdb6
MY		 2328out:
2329 vfree(rss);
2330 return rc;
cee4d264
MC		 2331}
2332
2333static int qed_start_rxq(struct qed_dev *cdev,
3da7a37a
MY		 2334 u8 rss_num,
2335 struct qed_queue_start_common_params *p_params,
cee4d264
MC		 2336 u16 bd_max_bytes,
2337 dma_addr_t bd_chain_phys_addr,
2338 dma_addr_t cqe_pbl_addr,
2339 u16 cqe_pbl_size,
3da7a37a 2340 struct qed_rxq_start_ret_params *ret_params)
cee4d264 2341{
cee4d264 2342 struct qed_hwfn *p_hwfn;
1a635e48 2343 int rc, hwfn_index;
cee4d264 2344
3da7a37a 2345 hwfn_index = rss_num % cdev->num_hwfns;
cee4d264
MC		 2346 p_hwfn = &cdev->hwfns[hwfn_index];
2347
3da7a37a
MY		 2348 p_params->queue_id = p_params->queue_id / cdev->num_hwfns;
2349 p_params->stats_id = p_params->vport_id;
cee4d264 2350
3da7a37a
MY		 2351 rc = qed_eth_rx_queue_start(p_hwfn,
2352 p_hwfn->hw_info.opaque_fid,
2353 p_params,
2354 bd_max_bytes,
2355 bd_chain_phys_addr,
2356 cqe_pbl_addr, cqe_pbl_size, ret_params);
cee4d264 2357 if (rc) {
3da7a37a 2358 DP_ERR(cdev, "Failed to start RXQ#%d\n", p_params->queue_id);
cee4d264
MC		 2359 return rc;
2360 }
2361
2362 DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
f604b17d 2363 "Started RX-Q %d [rss_num %d] on V-PORT %d and SB igu %d\n",
3da7a37a 2364 p_params->queue_id, rss_num, p_params->vport_id,
f604b17d 2365 p_params->p_sb->igu_sb_id);
cee4d264
MC		 2366
2367 return 0;
2368}
2369
3da7a37a 2370static int qed_stop_rxq(struct qed_dev *cdev, u8 rss_id, void *handle)
cee4d264
MC		 2371{
2372 int rc, hwfn_index;
2373 struct qed_hwfn *p_hwfn;
2374
3da7a37a
MY		 2375 hwfn_index = rss_id % cdev->num_hwfns;
2376 p_hwfn = &cdev->hwfns[hwfn_index];
cee4d264 2377
3da7a37a 2378 rc = qed_eth_rx_queue_stop(p_hwfn, handle, false, false);
cee4d264 2379 if (rc) {
3da7a37a 2380 DP_ERR(cdev, "Failed to stop RXQ#%02x\n", rss_id);
cee4d264
MC		 2381 return rc;
2382 }
2383
2384 return 0;
2385}
2386
2387static int qed_start_txq(struct qed_dev *cdev,
3da7a37a 2388 u8 rss_num,
cee4d264
MC		 2389 struct qed_queue_start_common_params *p_params,
2390 dma_addr_t pbl_addr,
2391 u16 pbl_size,
3da7a37a 2392 struct qed_txq_start_ret_params *ret_params)
cee4d264
MC		 2393{
2394 struct qed_hwfn *p_hwfn;
2395 int rc, hwfn_index;
2396
3da7a37a
MY		 2397 hwfn_index = rss_num % cdev->num_hwfns;
2398 p_hwfn = &cdev->hwfns[hwfn_index];
2399 p_params->queue_id = p_params->queue_id / cdev->num_hwfns;
2400 p_params->stats_id = p_params->vport_id;
cee4d264 2401
3da7a37a
MY		 2402 rc = qed_eth_tx_queue_start(p_hwfn,
2403 p_hwfn->hw_info.opaque_fid,
2404 p_params, 0,
2405 pbl_addr, pbl_size, ret_params);
cee4d264
MC		 2406
2407 if (rc) {
2408 DP_ERR(cdev, "Failed to start TXQ#%d\n", p_params->queue_id);
2409 return rc;
2410 }
2411
2412 DP_VERBOSE(cdev, (QED_MSG_SPQ | NETIF_MSG_IFUP),
f604b17d 2413 "Started TX-Q %d [rss_num %d] on V-PORT %d and SB igu %d\n",
3da7a37a 2414 p_params->queue_id, rss_num, p_params->vport_id,
f604b17d 2415 p_params->p_sb->igu_sb_id);
cee4d264
MC		 2416
2417 return 0;
2418}
2419
2420#define QED_HW_STOP_RETRY_LIMIT (10)
2421static int qed_fastpath_stop(struct qed_dev *cdev)
2422{
15582962
RV		 2423 int rc;
2424
2425 rc = qed_hw_stop_fastpath(cdev);
2426 if (rc) {
2427 DP_ERR(cdev, "Failed to stop Fastpath\n");
2428 return rc;
2429 }
cee4d264
MC		 2430
2431 return 0;
2432}
2433
3da7a37a 2434static int qed_stop_txq(struct qed_dev *cdev, u8 rss_id, void *handle)
cee4d264
MC		 2435{
2436 struct qed_hwfn *p_hwfn;
2437 int rc, hwfn_index;
2438
3da7a37a
MY		 2439 hwfn_index = rss_id % cdev->num_hwfns;
2440 p_hwfn = &cdev->hwfns[hwfn_index];
cee4d264 2441
3da7a37a 2442 rc = qed_eth_tx_queue_stop(p_hwfn, handle);
cee4d264 2443 if (rc) {
3da7a37a 2444 DP_ERR(cdev, "Failed to stop TXQ#%02x\n", rss_id);
cee4d264
MC		 2445 return rc;
2446 }
2447
2448 return 0;
2449}
2450
464f6645
MC		 2451static int qed_tunn_configure(struct qed_dev *cdev,
2452 struct qed_tunn_params *tunn_params)
2453{
19968430 2454 struct qed_tunnel_info tunn_info;
464f6645
MC		 2455 int i, rc;
2456
2457 memset(&tunn_info, 0, sizeof(tunn_info));
19968430
CM		 2458 if (tunn_params->update_vxlan_port) {
2459 tunn_info.vxlan_port.b_update_port = true;
2460 tunn_info.vxlan_port.port = tunn_params->vxlan_port;
464f6645
MC		 2461 }
2462
19968430
CM		 2463 if (tunn_params->update_geneve_port) {
2464 tunn_info.geneve_port.b_update_port = true;
2465 tunn_info.geneve_port.port = tunn_params->geneve_port;
464f6645
MC		 2466 }
2467
2468 for_each_hwfn(cdev, i) {
2469 struct qed_hwfn *hwfn = &cdev->hwfns[i];
4f64675f 2470 struct qed_ptt *p_ptt;
97379f15
CM		 2471 struct qed_tunnel_info *tun;
2472
2473 tun = &hwfn->cdev->tunnel;
4f64675f
MC		 2474 if (IS_PF(cdev)) {
2475 p_ptt = qed_ptt_acquire(hwfn);
2476 if (!p_ptt)
2477 return -EAGAIN;
2478 } else {
2479 p_ptt = NULL;
2480 }
464f6645 2481
4f64675f 2482 rc = qed_sp_pf_update_tunn_cfg(hwfn, p_ptt, &tunn_info,
464f6645 2483 QED_SPQ_MODE_EBLOCK, NULL);
4f64675f
MC		 2484 if (rc) {
2485 if (IS_PF(cdev))
2486 qed_ptt_release(hwfn, p_ptt);
464f6645 2487 return rc;
4f64675f 2488 }
97379f15
CM		 2489
2490 if (IS_PF_SRIOV(hwfn)) {
2491 u16 vxlan_port, geneve_port;
2492 int j;
2493
2494 vxlan_port = tun->vxlan_port.port;
2495 geneve_port = tun->geneve_port.port;
2496
2497 qed_for_each_vf(hwfn, j) {
2498 qed_iov_bulletin_set_udp_ports(hwfn, j,
2499 vxlan_port,
2500 geneve_port);
2501 }
2502
2503 qed_schedule_iov(hwfn, QED_IOV_WQ_BULLETIN_UPDATE_FLAG);
2504 }
4f64675f
MC		 2505 if (IS_PF(cdev))
2506 qed_ptt_release(hwfn, p_ptt);
464f6645
MC		 2507 }
2508
2509 return 0;
2510}
2511
cee4d264
MC		 2512static int qed_configure_filter_rx_mode(struct qed_dev *cdev,
2513 enum qed_filter_rx_mode_type type)
2514{
2515 struct qed_filter_accept_flags accept_flags;
2516
2517 memset(&accept_flags, 0, sizeof(accept_flags));
2518
1a635e48
YM		 2519 accept_flags.update_rx_mode_config = 1;
2520 accept_flags.update_tx_mode_config = 1;
2521 accept_flags.rx_accept_filter = QED_ACCEPT_UCAST_MATCHED |
2522 QED_ACCEPT_MCAST_MATCHED |
2523 QED_ACCEPT_BCAST;
cee4d264
MC		 2524 accept_flags.tx_accept_filter = QED_ACCEPT_UCAST_MATCHED |
2525 QED_ACCEPT_MCAST_MATCHED |
2526 QED_ACCEPT_BCAST;
2527
88067876 2528 if (type == QED_FILTER_RX_MODE_TYPE_PROMISC) {
cee4d264
MC		 2529 accept_flags.rx_accept_filter |= QED_ACCEPT_UCAST_UNMATCHED |
2530 QED_ACCEPT_MCAST_UNMATCHED;
88067876
MY		 2531 accept_flags.tx_accept_filter |= QED_ACCEPT_MCAST_UNMATCHED;
2532 } else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC) {
cee4d264 2533 accept_flags.rx_accept_filter |= QED_ACCEPT_MCAST_UNMATCHED;
88067876
MY		 2534 accept_flags.tx_accept_filter |= QED_ACCEPT_MCAST_UNMATCHED;
2535 }
cee4d264 2536
3f9b4a69 2537 return qed_filter_accept_cmd(cdev, 0, accept_flags, false, false,
cee4d264
MC		 2538 QED_SPQ_MODE_CB, NULL);
2539}
2540
2541static int qed_configure_filter_ucast(struct qed_dev *cdev,
2542 struct qed_filter_ucast_params *params)
2543{
2544 struct qed_filter_ucast ucast;
2545
2546 if (!params->vlan_valid && !params->mac_valid) {
1a635e48
YM		 2547 DP_NOTICE(cdev,
2548 "Tried configuring a unicast filter, but both MAC and VLAN are not set\n");
cee4d264
MC		 2549 return -EINVAL;
2550 }
2551
2552 memset(&ucast, 0, sizeof(ucast));
2553 switch (params->type) {
2554 case QED_FILTER_XCAST_TYPE_ADD:
2555 ucast.opcode = QED_FILTER_ADD;
2556 break;
2557 case QED_FILTER_XCAST_TYPE_DEL:
2558 ucast.opcode = QED_FILTER_REMOVE;
2559 break;
2560 case QED_FILTER_XCAST_TYPE_REPLACE:
2561 ucast.opcode = QED_FILTER_REPLACE;
2562 break;
2563 default:
2564 DP_NOTICE(cdev, "Unknown unicast filter type %d\n",
2565 params->type);
2566 }
2567
2568 if (params->vlan_valid && params->mac_valid) {
2569 ucast.type = QED_FILTER_MAC_VLAN;
2570 ether_addr_copy(ucast.mac, params->mac);
2571 ucast.vlan = params->vlan;
2572 } else if (params->mac_valid) {
2573 ucast.type = QED_FILTER_MAC;
2574 ether_addr_copy(ucast.mac, params->mac);
2575 } else {
2576 ucast.type = QED_FILTER_VLAN;
2577 ucast.vlan = params->vlan;
2578 }
2579
2580 ucast.is_rx_filter = true;
2581 ucast.is_tx_filter = true;
2582
2583 return qed_filter_ucast_cmd(cdev, &ucast, QED_SPQ_MODE_CB, NULL);
2584}
2585
2586static int qed_configure_filter_mcast(struct qed_dev *cdev,
2587 struct qed_filter_mcast_params *params)
2588{
2589 struct qed_filter_mcast mcast;
2590 int i;
2591
2592 memset(&mcast, 0, sizeof(mcast));
2593 switch (params->type) {
2594 case QED_FILTER_XCAST_TYPE_ADD:
2595 mcast.opcode = QED_FILTER_ADD;
2596 break;
2597 case QED_FILTER_XCAST_TYPE_DEL:
2598 mcast.opcode = QED_FILTER_REMOVE;
2599 break;
2600 default:
2601 DP_NOTICE(cdev, "Unknown multicast filter type %d\n",
2602 params->type);
2603 }
2604
2605 mcast.num_mc_addrs = params->num;
2606 for (i = 0; i < mcast.num_mc_addrs; i++)
2607 ether_addr_copy(mcast.mac[i], params->mac[i]);
2608
1a635e48 2609 return qed_filter_mcast_cmd(cdev, &mcast, QED_SPQ_MODE_CB, NULL);
cee4d264
MC		 2610}
2611
2612static int qed_configure_filter(struct qed_dev *cdev,
2613 struct qed_filter_params *params)
2614{
2615 enum qed_filter_rx_mode_type accept_flags;
2616
2617 switch (params->type) {
2618 case QED_FILTER_TYPE_UCAST:
2619 return qed_configure_filter_ucast(cdev, &params->filter.ucast);
2620 case QED_FILTER_TYPE_MCAST:
2621 return qed_configure_filter_mcast(cdev, &params->filter.mcast);
2622 case QED_FILTER_TYPE_RX_MODE:
2623 accept_flags = params->filter.accept_flags;
2624 return qed_configure_filter_rx_mode(cdev, accept_flags);
2625 default:
1a635e48 2626 DP_NOTICE(cdev, "Unknown filter type %d\n", (int)params->type);
cee4d264
MC		 2627 return -EINVAL;
2628 }
2629}
2630
d51e4af5
CM		 2631static int qed_configure_arfs_searcher(struct qed_dev *cdev, bool en_searcher)
2632{
2633 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
2634 struct qed_arfs_config_params arfs_config_params;
2635
2636 memset(&arfs_config_params, 0, sizeof(arfs_config_params));
2637 arfs_config_params.tcp = true;
2638 arfs_config_params.udp = true;
2639 arfs_config_params.ipv4 = true;
2640 arfs_config_params.ipv6 = true;
2641 arfs_config_params.arfs_enable = en_searcher;
2642
2643 qed_arfs_mode_configure(p_hwfn, p_hwfn->p_arfs_ptt,
2644 &arfs_config_params);
2645 return 0;
2646}
2647
2648static void
2649qed_arfs_sp_response_handler(struct qed_hwfn *p_hwfn,
2650 void *cookie, union event_ring_data *data,
2651 u8 fw_return_code)
2652{
2653 struct qed_common_cb_ops *op = p_hwfn->cdev->protocol_ops.common;
2654 void *dev = p_hwfn->cdev->ops_cookie;
2655
2656 op->arfs_filter_op(dev, cookie, fw_return_code);
2657}
2658
2659static int qed_ntuple_arfs_filter_config(struct qed_dev *cdev, void *cookie,
2660 dma_addr_t mapping, u16 length,
2661 u16 vport_id, u16 rx_queue_id,
2662 bool add_filter)
2663{
2664 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
2665 struct qed_spq_comp_cb cb;
2666 int rc = -EINVAL;
2667
2668 cb.function = qed_arfs_sp_response_handler;
2669 cb.cookie = cookie;
2670
2671 rc = qed_configure_rfs_ntuple_filter(p_hwfn, p_hwfn->p_arfs_ptt,
2672 &cb, mapping, length, rx_queue_id,
2673 vport_id, add_filter);
2674 if (rc)
2675 DP_NOTICE(p_hwfn,
2676 "Failed to issue a-RFS filter configuration\n");
2677 else
2678 DP_VERBOSE(p_hwfn, NETIF_MSG_DRV,
2679 "Successfully issued a-RFS filter configuration\n");
2680
2681 return rc;
2682}
2683
cee4d264 2684static int qed_fp_cqe_completion(struct qed_dev *dev,
1a635e48 2685 u8 rss_id, struct eth_slow_path_rx_cqe *cqe)
cee4d264
MC		 2686{
2687 return qed_eth_cqe_completion(&dev->hwfns[rss_id % dev->num_hwfns],
2688 cqe);
2689}
2690
0b55e27d
YM		 2691#ifdef CONFIG_QED_SRIOV
2692extern const struct qed_iov_hv_ops qed_iov_ops_pass;
2693#endif
2694
a1d8d8a5
SRK		 2695#ifdef CONFIG_DCB
2696extern const struct qed_eth_dcbnl_ops qed_dcbnl_ops_pass;
2697#endif
2698
c78c70fa
SRK		 2699extern const struct qed_eth_ptp_ops qed_ptp_ops_pass;
2700
25c089d7
YM		 2701static const struct qed_eth_ops qed_eth_ops_pass = {
2702 .common = &qed_common_ops_pass,
0b55e27d
YM		 2703#ifdef CONFIG_QED_SRIOV
2704 .iov = &qed_iov_ops_pass,
a1d8d8a5
SRK		 2705#endif
2706#ifdef CONFIG_DCB
2707 .dcb = &qed_dcbnl_ops_pass,
0b55e27d 2708#endif
c78c70fa 2709 .ptp = &qed_ptp_ops_pass,
25c089d7 2710 .fill_dev_info = &qed_fill_eth_dev_info,
cc875c2e 2711 .register_ops = &qed_register_eth_ops,
eff16960 2712 .check_mac = &qed_check_mac,
cee4d264
MC		 2713 .vport_start = &qed_start_vport,
2714 .vport_stop = &qed_stop_vport,
2715 .vport_update = &qed_update_vport,
2716 .q_rx_start = &qed_start_rxq,
2717 .q_rx_stop = &qed_stop_rxq,
2718 .q_tx_start = &qed_start_txq,
2719 .q_tx_stop = &qed_stop_txq,
2720 .filter_config = &qed_configure_filter,
2721 .fastpath_stop = &qed_fastpath_stop,
2722 .eth_cqe_completion = &qed_fp_cqe_completion,
9df2ed04 2723 .get_vport_stats = &qed_get_vport_stats,
464f6645 2724 .tunn_config = &qed_tunn_configure,
d51e4af5
CM		 2725 .ntuple_filter_config = &qed_ntuple_arfs_filter_config,
2726 .configure_arfs_searcher = &qed_configure_arfs_searcher,
25c089d7
YM		 2727};
2728
95114344 2729const struct qed_eth_ops *qed_get_eth_ops(void)
25c089d7 2730{
25c089d7
YM		 2731 return &qed_eth_ops_pass;
2732}
2733EXPORT_SYMBOL(qed_get_eth_ops);
2734
2735void qed_put_eth_ops(void)
2736{
2737 /* TODO - reference count for module? */
2738}
2739EXPORT_SYMBOL(qed_put_eth_ops);
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