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qed: Add cleanup in qed_slowpath_start()
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / qlogic / qed / qed_main.c
CommitLineData
fe56b9e6 1/* QLogic qed NIC Driver
e8f1cb50 2 * Copyright (c) 2015-2017 QLogic Corporation
fe56b9e6 3 *
e8f1cb50
MY		 4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
fe56b9e6
YM		 31 */
32
33#include <linux/stddef.h>
34#include <linux/pci.h>
35#include <linux/kernel.h>
36#include <linux/slab.h>
fe56b9e6
YM		 37#include <linux/delay.h>
38#include <asm/byteorder.h>
39#include <linux/dma-mapping.h>
40#include <linux/string.h>
41#include <linux/module.h>
42#include <linux/interrupt.h>
43#include <linux/workqueue.h>
44#include <linux/ethtool.h>
45#include <linux/etherdevice.h>
46#include <linux/vmalloc.h>
5d24bcf1 47#include <linux/crash_dump.h>
fe56b9e6 48#include <linux/qed/qed_if.h>
0a7fb11c 49#include <linux/qed/qed_ll2_if.h>
fe56b9e6
YM		 50
51#include "qed.h"
37bff2b9 52#include "qed_sriov.h"
fe56b9e6
YM		 53#include "qed_sp.h"
54#include "qed_dev_api.h"
0a7fb11c 55#include "qed_ll2.h"
1e128c81 56#include "qed_fcoe.h"
2f2b2614
MY		 57#include "qed_iscsi.h"
58
fe56b9e6
YM		 59#include "qed_mcp.h"
60#include "qed_hw.h"
03dc76ca 61#include "qed_selftest.h"
1e128c81 62#include "qed_debug.h"
fe56b9e6 63
51ff1725
RA		 64#define QED_ROCE_QPS (8192)
65#define QED_ROCE_DPIS (8)
51ff1725 66
5abd7e92
YM		 67static char version[] =
68 "QLogic FastLinQ 4xxxx Core Module qed " DRV_MODULE_VERSION "\n";
fe56b9e6 69
5abd7e92 70MODULE_DESCRIPTION("QLogic FastLinQ 4xxxx Core Module");
fe56b9e6
YM		 71MODULE_LICENSE("GPL");
72MODULE_VERSION(DRV_MODULE_VERSION);
73
74#define FW_FILE_VERSION \
75 __stringify(FW_MAJOR_VERSION) "." \
76 __stringify(FW_MINOR_VERSION) "." \
77 __stringify(FW_REVISION_VERSION) "." \
78 __stringify(FW_ENGINEERING_VERSION)
79
80#define QED_FW_FILE_NAME \
81 "qed/qed_init_values_zipped-" FW_FILE_VERSION ".bin"
82
d43d3f0f
YM		 83MODULE_FIRMWARE(QED_FW_FILE_NAME);
84
fe56b9e6
YM		 85static int __init qed_init(void)
86{
fe56b9e6
YM		 87 pr_info("%s", version);
88
89 return 0;
90}
91
92static void __exit qed_cleanup(void)
93{
94 pr_notice("qed_cleanup called\n");
95}
96
97module_init(qed_init);
98module_exit(qed_cleanup);
99
100/* Check if the DMA controller on the machine can properly handle the DMA
101 * addressing required by the device.
102*/
103static int qed_set_coherency_mask(struct qed_dev *cdev)
104{
105 struct device *dev = &cdev->pdev->dev;
106
107 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) {
108 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) {
109 DP_NOTICE(cdev,
110 "Can't request 64-bit consistent allocations\n");
111 return -EIO;
112 }
113 } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) {
114 DP_NOTICE(cdev, "Can't request 64b/32b DMA addresses\n");
115 return -EIO;
116 }
117
118 return 0;
119}
120
121static void qed_free_pci(struct qed_dev *cdev)
122{
123 struct pci_dev *pdev = cdev->pdev;
124
1a850bfc 125 if (cdev->doorbells && cdev->db_size)
fe56b9e6
YM		 126 iounmap(cdev->doorbells);
127 if (cdev->regview)
128 iounmap(cdev->regview);
129 if (atomic_read(&pdev->enable_cnt) == 1)
130 pci_release_regions(pdev);
131
132 pci_disable_device(pdev);
133}
134
0dfaba6d
YM		 135#define PCI_REVISION_ID_ERROR_VAL 0xff
136
fe56b9e6
YM		 137/* Performs PCI initializations as well as initializing PCI-related parameters
138 * in the device structrue. Returns 0 in case of success.
139 */
1a635e48 140static int qed_init_pci(struct qed_dev *cdev, struct pci_dev *pdev)
fe56b9e6 141{
0dfaba6d 142 u8 rev_id;
fe56b9e6
YM		 143 int rc;
144
145 cdev->pdev = pdev;
146
147 rc = pci_enable_device(pdev);
148 if (rc) {
149 DP_NOTICE(cdev, "Cannot enable PCI device\n");
150 goto err0;
151 }
152
153 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
154 DP_NOTICE(cdev, "No memory region found in bar #0\n");
155 rc = -EIO;
156 goto err1;
157 }
158
1408cc1f 159 if (IS_PF(cdev) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
fe56b9e6
YM		 160 DP_NOTICE(cdev, "No memory region found in bar #2\n");
161 rc = -EIO;
162 goto err1;
163 }
164
165 if (atomic_read(&pdev->enable_cnt) == 1) {
166 rc = pci_request_regions(pdev, "qed");
167 if (rc) {
168 DP_NOTICE(cdev,
169 "Failed to request PCI memory resources\n");
170 goto err1;
171 }
172 pci_set_master(pdev);
173 pci_save_state(pdev);
174 }
175
0dfaba6d
YM		 176 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
177 if (rev_id == PCI_REVISION_ID_ERROR_VAL) {
178 DP_NOTICE(cdev,
179 "Detected PCI device error [rev_id 0x%x]. Probably due to prior indication. Aborting.\n",
180 rev_id);
181 rc = -ENODEV;
182 goto err2;
183 }
fe56b9e6
YM		 184 if (!pci_is_pcie(pdev)) {
185 DP_NOTICE(cdev, "The bus is not PCI Express\n");
186 rc = -EIO;
187 goto err2;
188 }
189
190 cdev->pci_params.pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
416cdf06 191 if (IS_PF(cdev) && !cdev->pci_params.pm_cap)
fe56b9e6
YM		 192 DP_NOTICE(cdev, "Cannot find power management capability\n");
193
194 rc = qed_set_coherency_mask(cdev);
195 if (rc)
196 goto err2;
197
198 cdev->pci_params.mem_start = pci_resource_start(pdev, 0);
199 cdev->pci_params.mem_end = pci_resource_end(pdev, 0);
200 cdev->pci_params.irq = pdev->irq;
201
202 cdev->regview = pci_ioremap_bar(pdev, 0);
203 if (!cdev->regview) {
204 DP_NOTICE(cdev, "Cannot map register space, aborting\n");
205 rc = -ENOMEM;
206 goto err2;
207 }
208
1a850bfc
MY		 209 cdev->db_phys_addr = pci_resource_start(cdev->pdev, 2);
210 cdev->db_size = pci_resource_len(cdev->pdev, 2);
211 if (!cdev->db_size) {
212 if (IS_PF(cdev)) {
213 DP_NOTICE(cdev, "No Doorbell bar available\n");
214 return -EINVAL;
215 } else {
216 return 0;
1408cc1f 217 }
fe56b9e6
YM		 218 }
219
1a850bfc
MY		 220 cdev->doorbells = ioremap_wc(cdev->db_phys_addr, cdev->db_size);
221
222 if (!cdev->doorbells) {
223 DP_NOTICE(cdev, "Cannot map doorbell space\n");
224 return -ENOMEM;
225 }
226
fe56b9e6
YM		 227 return 0;
228
229err2:
230 pci_release_regions(pdev);
231err1:
232 pci_disable_device(pdev);
233err0:
234 return rc;
235}
236
237int qed_fill_dev_info(struct qed_dev *cdev,
238 struct qed_dev_info *dev_info)
239{
c851a9dc
KM		 240 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
241 struct qed_hw_info *hw_info = &p_hwfn->hw_info;
19489c7f 242 struct qed_tunnel_info *tun = &cdev->tunnel;
cee4d264
MC		 243 struct qed_ptt *ptt;
244
fe56b9e6
YM		 245 memset(dev_info, 0, sizeof(struct qed_dev_info));
246
19489c7f
CM		 247 if (tun->vxlan.tun_cls == QED_TUNN_CLSS_MAC_VLAN &&
248 tun->vxlan.b_mode_enabled)
249 dev_info->vxlan_enable = true;
250
251 if (tun->l2_gre.b_mode_enabled && tun->ip_gre.b_mode_enabled &&
252 tun->l2_gre.tun_cls == QED_TUNN_CLSS_MAC_VLAN &&
253 tun->ip_gre.tun_cls == QED_TUNN_CLSS_MAC_VLAN)
254 dev_info->gre_enable = true;
255
256 if (tun->l2_geneve.b_mode_enabled && tun->ip_geneve.b_mode_enabled &&
257 tun->l2_geneve.tun_cls == QED_TUNN_CLSS_MAC_VLAN &&
258 tun->ip_geneve.tun_cls == QED_TUNN_CLSS_MAC_VLAN)
259 dev_info->geneve_enable = true;
260
fe56b9e6
YM		 261 dev_info->num_hwfns = cdev->num_hwfns;
262 dev_info->pci_mem_start = cdev->pci_params.mem_start;
263 dev_info->pci_mem_end = cdev->pci_params.mem_end;
264 dev_info->pci_irq = cdev->pci_params.irq;
c851a9dc 265 dev_info->rdma_supported = QED_IS_RDMA_PERSONALITY(p_hwfn);
fc48b7a6 266 dev_info->is_mf_default = IS_MF_DEFAULT(&cdev->hwfns[0]);
9c79ddaa 267 dev_info->dev_type = cdev->type;
c851a9dc 268 ether_addr_copy(dev_info->hw_mac, hw_info->hw_mac_addr);
fe56b9e6 269
1408cc1f
YM		 270 if (IS_PF(cdev)) {
271 dev_info->fw_major = FW_MAJOR_VERSION;
272 dev_info->fw_minor = FW_MINOR_VERSION;
273 dev_info->fw_rev = FW_REVISION_VERSION;
274 dev_info->fw_eng = FW_ENGINEERING_VERSION;
275 dev_info->mf_mode = cdev->mf_mode;
831bfb0e 276 dev_info->tx_switching = true;
14d39648 277
c851a9dc 278 if (hw_info->b_wol_support == QED_WOL_SUPPORT_PME)
14d39648 279 dev_info->wol_support = true;
3c5da942
MY		 280
281 dev_info->abs_pf_id = QED_LEADING_HWFN(cdev)->abs_pf_id;
1408cc1f
YM		 282 } else {
283 qed_vf_get_fw_version(&cdev->hwfns[0], &dev_info->fw_major,
284 &dev_info->fw_minor, &dev_info->fw_rev,
285 &dev_info->fw_eng);
286 }
fe56b9e6 287
1408cc1f
YM		 288 if (IS_PF(cdev)) {
289 ptt = qed_ptt_acquire(QED_LEADING_HWFN(cdev));
290 if (ptt) {
291 qed_mcp_get_mfw_ver(QED_LEADING_HWFN(cdev), ptt,
292 &dev_info->mfw_rev, NULL);
fe56b9e6 293
ae33666a
TT		 294 qed_mcp_get_mbi_ver(QED_LEADING_HWFN(cdev), ptt,
295 &dev_info->mbi_version);
296
1408cc1f
YM		 297 qed_mcp_get_flash_size(QED_LEADING_HWFN(cdev), ptt,
298 &dev_info->flash_size);
cee4d264 299
1408cc1f
YM		 300 qed_ptt_release(QED_LEADING_HWFN(cdev), ptt);
301 }
302 } else {
303 qed_mcp_get_mfw_ver(QED_LEADING_HWFN(cdev), NULL,
304 &dev_info->mfw_rev, NULL);
cee4d264
MC		 305 }
306
c851a9dc 307 dev_info->mtu = hw_info->mtu;
0fefbfba 308
fe56b9e6
YM		 309 return 0;
310}
311
312static void qed_free_cdev(struct qed_dev *cdev)
313{
314 kfree((void *)cdev);
315}
316
317static struct qed_dev *qed_alloc_cdev(struct pci_dev *pdev)
318{
319 struct qed_dev *cdev;
320
321 cdev = kzalloc(sizeof(*cdev), GFP_KERNEL);
322 if (!cdev)
323 return cdev;
324
325 qed_init_struct(cdev);
326
327 return cdev;
328}
329
330/* Sets the requested power state */
1a635e48 331static int qed_set_power_state(struct qed_dev *cdev, pci_power_t state)
fe56b9e6
YM		 332{
333 if (!cdev)
334 return -ENODEV;
335
336 DP_VERBOSE(cdev, NETIF_MSG_DRV, "Omitting Power state change\n");
337 return 0;
338}
339
340/* probing */
341static struct qed_dev *qed_probe(struct pci_dev *pdev,
1408cc1f 342 struct qed_probe_params *params)
fe56b9e6
YM		 343{
344 struct qed_dev *cdev;
345 int rc;
346
347 cdev = qed_alloc_cdev(pdev);
348 if (!cdev)
349 goto err0;
350
712c3cbf 351 cdev->drv_type = DRV_ID_DRV_TYPE_LINUX;
1408cc1f 352 cdev->protocol = params->protocol;
fe56b9e6 353
1408cc1f
YM		 354 if (params->is_vf)
355 cdev->b_is_vf = true;
356
357 qed_init_dp(cdev, params->dp_module, params->dp_level);
fe56b9e6
YM		 358
359 rc = qed_init_pci(cdev, pdev);
360 if (rc) {
361 DP_ERR(cdev, "init pci failed\n");
362 goto err1;
363 }
364 DP_INFO(cdev, "PCI init completed successfully\n");
365
366 rc = qed_hw_prepare(cdev, QED_PCI_DEFAULT);
367 if (rc) {
368 DP_ERR(cdev, "hw prepare failed\n");
369 goto err2;
370 }
371
372 DP_INFO(cdev, "qed_probe completed successffuly\n");
373
374 return cdev;
375
376err2:
377 qed_free_pci(cdev);
378err1:
379 qed_free_cdev(cdev);
380err0:
381 return NULL;
382}
383
384static void qed_remove(struct qed_dev *cdev)
385{
386 if (!cdev)
387 return;
388
389 qed_hw_remove(cdev);
390
391 qed_free_pci(cdev);
392
393 qed_set_power_state(cdev, PCI_D3hot);
394
395 qed_free_cdev(cdev);
396}
397
398static void qed_disable_msix(struct qed_dev *cdev)
399{
400 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
401 pci_disable_msix(cdev->pdev);
402 kfree(cdev->int_params.msix_table);
403 } else if (cdev->int_params.out.int_mode == QED_INT_MODE_MSI) {
404 pci_disable_msi(cdev->pdev);
405 }
406
407 memset(&cdev->int_params.out, 0, sizeof(struct qed_int_param));
408}
409
410static int qed_enable_msix(struct qed_dev *cdev,
411 struct qed_int_params *int_params)
412{
413 int i, rc, cnt;
414
415 cnt = int_params->in.num_vectors;
416
417 for (i = 0; i < cnt; i++)
418 int_params->msix_table[i].entry = i;
419
420 rc = pci_enable_msix_range(cdev->pdev, int_params->msix_table,
421 int_params->in.min_msix_cnt, cnt);
422 if (rc < cnt && rc >= int_params->in.min_msix_cnt &&
423 (rc % cdev->num_hwfns)) {
424 pci_disable_msix(cdev->pdev);
425
426 /* If fastpath is initialized, we need at least one interrupt
427 * per hwfn [and the slow path interrupts]. New requested number
428 * should be a multiple of the number of hwfns.
429 */
430 cnt = (rc / cdev->num_hwfns) * cdev->num_hwfns;
431 DP_NOTICE(cdev,
432 "Trying to enable MSI-X with less vectors (%d out of %d)\n",
433 cnt, int_params->in.num_vectors);
1a635e48
YM		 434 rc = pci_enable_msix_exact(cdev->pdev, int_params->msix_table,
435 cnt);
fe56b9e6
YM		 436 if (!rc)
437 rc = cnt;
438 }
439
440 if (rc > 0) {
441 /* MSI-x configuration was achieved */
442 int_params->out.int_mode = QED_INT_MODE_MSIX;
443 int_params->out.num_vectors = rc;
444 rc = 0;
445 } else {
446 DP_NOTICE(cdev,
447 "Failed to enable MSI-X [Requested %d vectors][rc %d]\n",
448 cnt, rc);
449 }
450
451 return rc;
452}
453
454/* This function outputs the int mode and the number of enabled msix vector */
455static int qed_set_int_mode(struct qed_dev *cdev, bool force_mode)
456{
457 struct qed_int_params *int_params = &cdev->int_params;
458 struct msix_entry *tbl;
459 int rc = 0, cnt;
460
461 switch (int_params->in.int_mode) {
462 case QED_INT_MODE_MSIX:
463 /* Allocate MSIX table */
464 cnt = int_params->in.num_vectors;
465 int_params->msix_table = kcalloc(cnt, sizeof(*tbl), GFP_KERNEL);
466 if (!int_params->msix_table) {
467 rc = -ENOMEM;
468 goto out;
469 }
470
471 /* Enable MSIX */
472 rc = qed_enable_msix(cdev, int_params);
473 if (!rc)
474 goto out;
475
476 DP_NOTICE(cdev, "Failed to enable MSI-X\n");
477 kfree(int_params->msix_table);
478 if (force_mode)
479 goto out;
480 /* Fallthrough */
481
482 case QED_INT_MODE_MSI:
bb13ace7
SRK		 483 if (cdev->num_hwfns == 1) {
484 rc = pci_enable_msi(cdev->pdev);
485 if (!rc) {
486 int_params->out.int_mode = QED_INT_MODE_MSI;
487 goto out;
488 }
489
490 DP_NOTICE(cdev, "Failed to enable MSI\n");
491 if (force_mode)
492 goto out;
fe56b9e6 493 }
fe56b9e6
YM		 494 /* Fallthrough */
495
496 case QED_INT_MODE_INTA:
497 int_params->out.int_mode = QED_INT_MODE_INTA;
498 rc = 0;
499 goto out;
500 default:
501 DP_NOTICE(cdev, "Unknown int_mode value %d\n",
502 int_params->in.int_mode);
503 rc = -EINVAL;
504 }
505
506out:
525ef5c0
YM		 507 if (!rc)
508 DP_INFO(cdev, "Using %s interrupts\n",
509 int_params->out.int_mode == QED_INT_MODE_INTA ?
510 "INTa" : int_params->out.int_mode == QED_INT_MODE_MSI ?
511 "MSI" : "MSIX");
fe56b9e6
YM		 512 cdev->int_coalescing_mode = QED_COAL_MODE_ENABLE;
513
514 return rc;
515}
516
517static void qed_simd_handler_config(struct qed_dev *cdev, void *token,
518 int index, void(*handler)(void *))
519{
520 struct qed_hwfn *hwfn = &cdev->hwfns[index % cdev->num_hwfns];
521 int relative_idx = index / cdev->num_hwfns;
522
523 hwfn->simd_proto_handler[relative_idx].func = handler;
524 hwfn->simd_proto_handler[relative_idx].token = token;
525}
526
527static void qed_simd_handler_clean(struct qed_dev *cdev, int index)
528{
529 struct qed_hwfn *hwfn = &cdev->hwfns[index % cdev->num_hwfns];
530 int relative_idx = index / cdev->num_hwfns;
531
532 memset(&hwfn->simd_proto_handler[relative_idx], 0,
533 sizeof(struct qed_simd_fp_handler));
534}
535
536static irqreturn_t qed_msix_sp_int(int irq, void *tasklet)
537{
538 tasklet_schedule((struct tasklet_struct *)tasklet);
539 return IRQ_HANDLED;
540}
541
542static irqreturn_t qed_single_int(int irq, void *dev_instance)
543{
544 struct qed_dev *cdev = (struct qed_dev *)dev_instance;
545 struct qed_hwfn *hwfn;
546 irqreturn_t rc = IRQ_NONE;
547 u64 status;
548 int i, j;
549
550 for (i = 0; i < cdev->num_hwfns; i++) {
551 status = qed_int_igu_read_sisr_reg(&cdev->hwfns[i]);
552
553 if (!status)
554 continue;
555
556 hwfn = &cdev->hwfns[i];
557
558 /* Slowpath interrupt */
559 if (unlikely(status & 0x1)) {
560 tasklet_schedule(hwfn->sp_dpc);
561 status &= ~0x1;
562 rc = IRQ_HANDLED;
563 }
564
565 /* Fastpath interrupts */
566 for (j = 0; j < 64; j++) {
567 if ((0x2ULL << j) & status) {
2d5c8847
SRK		 568 struct qed_simd_fp_handler *p_handler =
569 &hwfn->simd_proto_handler[j];
570
571 if (p_handler->func)
572 p_handler->func(p_handler->token);
573 else
574 DP_NOTICE(hwfn,
575 "Not calling fastpath handler as it is NULL [handler #%d, status 0x%llx]\n",
576 j, status);
577
fe56b9e6
YM		 578 status &= ~(0x2ULL << j);
579 rc = IRQ_HANDLED;
580 }
581 }
582
583 if (unlikely(status))
584 DP_VERBOSE(hwfn, NETIF_MSG_INTR,
585 "got an unknown interrupt status 0x%llx\n",
586 status);
587 }
588
589 return rc;
590}
591
8f16bc97 592int qed_slowpath_irq_req(struct qed_hwfn *hwfn)
fe56b9e6 593{
8f16bc97 594 struct qed_dev *cdev = hwfn->cdev;
525ef5c0 595 u32 int_mode;
8f16bc97
SK		 596 int rc = 0;
597 u8 id;
fe56b9e6 598
525ef5c0
YM		 599 int_mode = cdev->int_params.out.int_mode;
600 if (int_mode == QED_INT_MODE_MSIX) {
8f16bc97
SK		 601 id = hwfn->my_id;
602 snprintf(hwfn->name, NAME_SIZE, "sp-%d-%02x:%02x.%02x",
603 id, cdev->pdev->bus->number,
604 PCI_SLOT(cdev->pdev->devfn), hwfn->abs_pf_id);
605 rc = request_irq(cdev->int_params.msix_table[id].vector,
606 qed_msix_sp_int, 0, hwfn->name, hwfn->sp_dpc);
fe56b9e6
YM		 607 } else {
608 unsigned long flags = 0;
609
610 snprintf(cdev->name, NAME_SIZE, "%02x:%02x.%02x",
611 cdev->pdev->bus->number, PCI_SLOT(cdev->pdev->devfn),
612 PCI_FUNC(cdev->pdev->devfn));
613
614 if (cdev->int_params.out.int_mode == QED_INT_MODE_INTA)
615 flags |= IRQF_SHARED;
616
617 rc = request_irq(cdev->pdev->irq, qed_single_int,
618 flags, cdev->name, cdev);
619 }
620
525ef5c0
YM		 621 if (rc)
622 DP_NOTICE(cdev, "request_irq failed, rc = %d\n", rc);
623 else
624 DP_VERBOSE(hwfn, (NETIF_MSG_INTR | QED_MSG_SP),
625 "Requested slowpath %s\n",
626 (int_mode == QED_INT_MODE_MSIX) ? "MSI-X" : "IRQ");
627
fe56b9e6
YM		 628 return rc;
629}
630
06892f2e
TT		 631static void qed_slowpath_tasklet_flush(struct qed_hwfn *p_hwfn)
632{
633 /* Calling the disable function will make sure that any
634 * currently-running function is completed. The following call to the
635 * enable function makes this sequence a flush-like operation.
636 */
637 if (p_hwfn->b_sp_dpc_enabled) {
638 tasklet_disable(p_hwfn->sp_dpc);
639 tasklet_enable(p_hwfn->sp_dpc);
640 }
641}
642
1226337a
TT		 643void qed_slowpath_irq_sync(struct qed_hwfn *p_hwfn)
644{
645 struct qed_dev *cdev = p_hwfn->cdev;
646 u8 id = p_hwfn->my_id;
647 u32 int_mode;
648
649 int_mode = cdev->int_params.out.int_mode;
650 if (int_mode == QED_INT_MODE_MSIX)
651 synchronize_irq(cdev->int_params.msix_table[id].vector);
652 else
653 synchronize_irq(cdev->pdev->irq);
06892f2e
TT		 654
655 qed_slowpath_tasklet_flush(p_hwfn);
1226337a
TT		 656}
657
fe56b9e6
YM		 658static void qed_slowpath_irq_free(struct qed_dev *cdev)
659{
660 int i;
661
662 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
663 for_each_hwfn(cdev, i) {
8f16bc97
SK		 664 if (!cdev->hwfns[i].b_int_requested)
665 break;
fe56b9e6
YM		 666 synchronize_irq(cdev->int_params.msix_table[i].vector);
667 free_irq(cdev->int_params.msix_table[i].vector,
668 cdev->hwfns[i].sp_dpc);
669 }
670 } else {
8f16bc97
SK		 671 if (QED_LEADING_HWFN(cdev)->b_int_requested)
672 free_irq(cdev->pdev->irq, cdev);
fe56b9e6 673 }
8f16bc97 674 qed_int_disable_post_isr_release(cdev);
fe56b9e6
YM		 675}
676
677static int qed_nic_stop(struct qed_dev *cdev)
678{
679 int i, rc;
680
681 rc = qed_hw_stop(cdev);
682
683 for (i = 0; i < cdev->num_hwfns; i++) {
684 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
685
686 if (p_hwfn->b_sp_dpc_enabled) {
687 tasklet_disable(p_hwfn->sp_dpc);
688 p_hwfn->b_sp_dpc_enabled = false;
689 DP_VERBOSE(cdev, NETIF_MSG_IFDOWN,
690 "Disabled sp taskelt [hwfn %d] at %p\n",
691 i, p_hwfn->sp_dpc);
692 }
693 }
694
c965db44
TT		 695 qed_dbg_pf_exit(cdev);
696
fe56b9e6
YM		 697 return rc;
698}
699
fe56b9e6
YM		 700static int qed_nic_setup(struct qed_dev *cdev)
701{
0a7fb11c
YM		 702 int rc, i;
703
704 /* Determine if interface is going to require LL2 */
705 if (QED_LEADING_HWFN(cdev)->hw_info.personality != QED_PCI_ETH) {
706 for (i = 0; i < cdev->num_hwfns; i++) {
707 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
708
709 p_hwfn->using_ll2 = true;
710 }
711 }
fe56b9e6
YM		 712
713 rc = qed_resc_alloc(cdev);
714 if (rc)
715 return rc;
716
717 DP_INFO(cdev, "Allocated qed resources\n");
718
719 qed_resc_setup(cdev);
720
721 return rc;
722}
723
724static int qed_set_int_fp(struct qed_dev *cdev, u16 cnt)
725{
726 int limit = 0;
727
728 /* Mark the fastpath as free/used */
729 cdev->int_params.fp_initialized = cnt ? true : false;
730
731 if (cdev->int_params.out.int_mode != QED_INT_MODE_MSIX)
732 limit = cdev->num_hwfns * 63;
733 else if (cdev->int_params.fp_msix_cnt)
734 limit = cdev->int_params.fp_msix_cnt;
735
736 if (!limit)
737 return -ENOMEM;
738
739 return min_t(int, cnt, limit);
740}
741
742static int qed_get_int_fp(struct qed_dev *cdev, struct qed_int_info *info)
743{
744 memset(info, 0, sizeof(struct qed_int_info));
745
746 if (!cdev->int_params.fp_initialized) {
747 DP_INFO(cdev,
748 "Protocol driver requested interrupt information, but its support is not yet configured\n");
749 return -EINVAL;
750 }
751
752 /* Need to expose only MSI-X information; Single IRQ is handled solely
753 * by qed.
754 */
755 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
756 int msix_base = cdev->int_params.fp_msix_base;
757
758 info->msix_cnt = cdev->int_params.fp_msix_cnt;
759 info->msix = &cdev->int_params.msix_table[msix_base];
760 }
761
762 return 0;
763}
764
765static int qed_slowpath_setup_int(struct qed_dev *cdev,
766 enum qed_int_mode int_mode)
767{
4ac801b7 768 struct qed_sb_cnt_info sb_cnt_info;
0189efb8 769 int num_l2_queues = 0;
4ac801b7
YM		 770 int rc;
771 int i;
fe56b9e6 772
1d2c2024
SRK		 773 if ((int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) {
774 DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n");
775 return -EINVAL;
776 }
777
778 memset(&cdev->int_params, 0, sizeof(struct qed_int_params));
fe56b9e6 779 cdev->int_params.in.int_mode = int_mode;
4ac801b7
YM		 780 for_each_hwfn(cdev, i) {
781 memset(&sb_cnt_info, 0, sizeof(sb_cnt_info));
782 qed_int_get_num_sbs(&cdev->hwfns[i], &sb_cnt_info);
726fdbe9 783 cdev->int_params.in.num_vectors += sb_cnt_info.cnt;
4ac801b7
YM		 784 cdev->int_params.in.num_vectors++; /* slowpath */
785 }
fe56b9e6
YM		 786
787 /* We want a minimum of one slowpath and one fastpath vector per hwfn */
788 cdev->int_params.in.min_msix_cnt = cdev->num_hwfns * 2;
789
67688337
SRK		 790 if (is_kdump_kernel()) {
791 DP_INFO(cdev,
792 "Kdump kernel: Limit the max number of requested MSI-X vectors to %hd\n",
793 cdev->int_params.in.min_msix_cnt);
794 cdev->int_params.in.num_vectors =
795 cdev->int_params.in.min_msix_cnt;
796 }
797
fe56b9e6
YM		 798 rc = qed_set_int_mode(cdev, false);
799 if (rc) {
800 DP_ERR(cdev, "qed_slowpath_setup_int ERR\n");
801 return rc;
802 }
803
804 cdev->int_params.fp_msix_base = cdev->num_hwfns;
805 cdev->int_params.fp_msix_cnt = cdev->int_params.out.num_vectors -
806 cdev->num_hwfns;
807
2f782278 808 if (!IS_ENABLED(CONFIG_QED_RDMA) ||
c851a9dc 809 !QED_IS_RDMA_PERSONALITY(QED_LEADING_HWFN(cdev)))
0189efb8
YM		 810 return 0;
811
51ff1725
RA		 812 for_each_hwfn(cdev, i)
813 num_l2_queues += FEAT_NUM(&cdev->hwfns[i], QED_PF_L2_QUE);
814
815 DP_VERBOSE(cdev, QED_MSG_RDMA,
816 "cdev->int_params.fp_msix_cnt=%d num_l2_queues=%d\n",
817 cdev->int_params.fp_msix_cnt, num_l2_queues);
818
819 if (cdev->int_params.fp_msix_cnt > num_l2_queues) {
820 cdev->int_params.rdma_msix_cnt =
821 (cdev->int_params.fp_msix_cnt - num_l2_queues)
822 / cdev->num_hwfns;
823 cdev->int_params.rdma_msix_base =
824 cdev->int_params.fp_msix_base + num_l2_queues;
825 cdev->int_params.fp_msix_cnt = num_l2_queues;
826 } else {
827 cdev->int_params.rdma_msix_cnt = 0;
828 }
829
830 DP_VERBOSE(cdev, QED_MSG_RDMA, "roce_msix_cnt=%d roce_msix_base=%d\n",
831 cdev->int_params.rdma_msix_cnt,
832 cdev->int_params.rdma_msix_base);
51ff1725 833
fe56b9e6
YM		 834 return 0;
835}
836
1408cc1f
YM		 837static int qed_slowpath_vf_setup_int(struct qed_dev *cdev)
838{
839 int rc;
840
841 memset(&cdev->int_params, 0, sizeof(struct qed_int_params));
842 cdev->int_params.in.int_mode = QED_INT_MODE_MSIX;
843
844 qed_vf_get_num_rxqs(QED_LEADING_HWFN(cdev),
845 &cdev->int_params.in.num_vectors);
846 if (cdev->num_hwfns > 1) {
847 u8 vectors = 0;
848
849 qed_vf_get_num_rxqs(&cdev->hwfns[1], &vectors);
850 cdev->int_params.in.num_vectors += vectors;
851 }
852
853 /* We want a minimum of one fastpath vector per vf hwfn */
854 cdev->int_params.in.min_msix_cnt = cdev->num_hwfns;
855
856 rc = qed_set_int_mode(cdev, true);
857 if (rc)
858 return rc;
859
860 cdev->int_params.fp_msix_base = 0;
861 cdev->int_params.fp_msix_cnt = cdev->int_params.out.num_vectors;
862
863 return 0;
864}
865
fe56b9e6
YM		 866u32 qed_unzip_data(struct qed_hwfn *p_hwfn, u32 input_len,
867 u8 *input_buf, u32 max_size, u8 *unzip_buf)
868{
869 int rc;
870
871 p_hwfn->stream->next_in = input_buf;
872 p_hwfn->stream->avail_in = input_len;
873 p_hwfn->stream->next_out = unzip_buf;
874 p_hwfn->stream->avail_out = max_size;
875
876 rc = zlib_inflateInit2(p_hwfn->stream, MAX_WBITS);
877
878 if (rc != Z_OK) {
879 DP_VERBOSE(p_hwfn, NETIF_MSG_DRV, "zlib init failed, rc = %d\n",
880 rc);
881 return 0;
882 }
883
884 rc = zlib_inflate(p_hwfn->stream, Z_FINISH);
885 zlib_inflateEnd(p_hwfn->stream);
886
887 if (rc != Z_OK && rc != Z_STREAM_END) {
888 DP_VERBOSE(p_hwfn, NETIF_MSG_DRV, "FW unzip error: %s, rc=%d\n",
889 p_hwfn->stream->msg, rc);
890 return 0;
891 }
892
893 return p_hwfn->stream->total_out / 4;
894}
895
896static int qed_alloc_stream_mem(struct qed_dev *cdev)
897{
898 int i;
899 void *workspace;
900
901 for_each_hwfn(cdev, i) {
902 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
903
904 p_hwfn->stream = kzalloc(sizeof(*p_hwfn->stream), GFP_KERNEL);
905 if (!p_hwfn->stream)
906 return -ENOMEM;
907
908 workspace = vzalloc(zlib_inflate_workspacesize());
909 if (!workspace)
910 return -ENOMEM;
911 p_hwfn->stream->workspace = workspace;
912 }
913
914 return 0;
915}
916
917static void qed_free_stream_mem(struct qed_dev *cdev)
918{
919 int i;
920
921 for_each_hwfn(cdev, i) {
922 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
923
924 if (!p_hwfn->stream)
925 return;
926
927 vfree(p_hwfn->stream->workspace);
928 kfree(p_hwfn->stream);
929 }
930}
931
932static void qed_update_pf_params(struct qed_dev *cdev,
933 struct qed_pf_params *params)
934{
935 int i;
936
5c5f2609
RA		 937 if (IS_ENABLED(CONFIG_QED_RDMA)) {
938 params->rdma_pf_params.num_qps = QED_ROCE_QPS;
939 params->rdma_pf_params.min_dpis = QED_ROCE_DPIS;
940 /* divide by 3 the MRs to avoid MF ILT overflow */
5c5f2609
RA		 941 params->rdma_pf_params.gl_pi = QED_ROCE_PROTOCOL_INDEX;
942 }
943
d51e4af5
CM		 944 if (cdev->num_hwfns > 1 || IS_VF(cdev))
945 params->eth_pf_params.num_arfs_filters = 0;
946
e1d32acb
MY		 947 /* In case we might support RDMA, don't allow qede to be greedy
948 * with the L2 contexts. Allow for 64 queues [rx, tx, xdp] per hwfn.
949 */
c851a9dc 950 if (QED_IS_RDMA_PERSONALITY(QED_LEADING_HWFN(cdev))) {
e1d32acb
MY		 951 u16 *num_cons;
952
953 num_cons = &params->eth_pf_params.num_cons;
954 *num_cons = min_t(u16, *num_cons, 192);
955 }
956
fe56b9e6
YM		 957 for (i = 0; i < cdev->num_hwfns; i++) {
958 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
959
960 p_hwfn->pf_params = *params;
961 }
962}
963
964static int qed_slowpath_start(struct qed_dev *cdev,
965 struct qed_slowpath_params *params)
966{
5d24bcf1 967 struct qed_drv_load_params drv_load_params;
c0c2d0b4 968 struct qed_hw_init_params hw_init_params;
fe56b9e6 969 struct qed_mcp_drv_version drv_version;
19968430 970 struct qed_tunnel_info tunn_info;
fe56b9e6
YM		 971 const u8 *data = NULL;
972 struct qed_hwfn *hwfn;
c78c70fa 973 struct qed_ptt *p_ptt;
37bff2b9
YM		 974 int rc = -EINVAL;
975
976 if (qed_iov_wq_start(cdev))
977 goto err;
fe56b9e6 978
1408cc1f
YM		 979 if (IS_PF(cdev)) {
980 rc = request_firmware(&cdev->firmware, QED_FW_FILE_NAME,
981 &cdev->pdev->dev);
982 if (rc) {
983 DP_NOTICE(cdev,
984 "Failed to find fw file - /lib/firmware/%s\n",
985 QED_FW_FILE_NAME);
986 goto err;
987 }
c78c70fa 988
d51e4af5
CM		 989 if (cdev->num_hwfns == 1) {
990 p_ptt = qed_ptt_acquire(QED_LEADING_HWFN(cdev));
991 if (p_ptt) {
992 QED_LEADING_HWFN(cdev)->p_arfs_ptt = p_ptt;
993 } else {
994 DP_NOTICE(cdev,
995 "Failed to acquire PTT for aRFS\n");
996 goto err;
997 }
998 }
fe56b9e6
YM		 999 }
1000
0e191827 1001 cdev->rx_coalesce_usecs = QED_DEFAULT_RX_USECS;
fe56b9e6
YM		 1002 rc = qed_nic_setup(cdev);
1003 if (rc)
1004 goto err;
1005
1408cc1f
YM		 1006 if (IS_PF(cdev))
1007 rc = qed_slowpath_setup_int(cdev, params->int_mode);
1008 else
1009 rc = qed_slowpath_vf_setup_int(cdev);
fe56b9e6
YM		 1010 if (rc)
1011 goto err1;
1012
1408cc1f
YM		 1013 if (IS_PF(cdev)) {
1014 /* Allocate stream for unzipping */
1015 rc = qed_alloc_stream_mem(cdev);
2591c280 1016 if (rc)
1408cc1f 1017 goto err2;
fe56b9e6 1018
8ac1ed79 1019 /* First Dword used to differentiate between various sources */
351a4ded 1020 data = cdev->firmware->data + sizeof(u32);
c965db44
TT		 1021
1022 qed_dbg_pf_init(cdev);
1408cc1f 1023 }
fe56b9e6 1024
1408cc1f 1025 /* Start the slowpath */
c0c2d0b4 1026 memset(&hw_init_params, 0, sizeof(hw_init_params));
19968430
CM		 1027 memset(&tunn_info, 0, sizeof(tunn_info));
1028 tunn_info.vxlan.b_mode_enabled = true;
1029 tunn_info.l2_gre.b_mode_enabled = true;
1030 tunn_info.ip_gre.b_mode_enabled = true;
1031 tunn_info.l2_geneve.b_mode_enabled = true;
1032 tunn_info.ip_geneve.b_mode_enabled = true;
1033 tunn_info.vxlan.tun_cls = QED_TUNN_CLSS_MAC_VLAN;
1034 tunn_info.l2_gre.tun_cls = QED_TUNN_CLSS_MAC_VLAN;
1035 tunn_info.ip_gre.tun_cls = QED_TUNN_CLSS_MAC_VLAN;
1036 tunn_info.l2_geneve.tun_cls = QED_TUNN_CLSS_MAC_VLAN;
1037 tunn_info.ip_geneve.tun_cls = QED_TUNN_CLSS_MAC_VLAN;
c0c2d0b4
MY		 1038 hw_init_params.p_tunn = &tunn_info;
1039 hw_init_params.b_hw_start = true;
1040 hw_init_params.int_mode = cdev->int_params.out.int_mode;
1041 hw_init_params.allow_npar_tx_switch = true;
1042 hw_init_params.bin_fw_data = data;
1043
5d24bcf1
TT		 1044 memset(&drv_load_params, 0, sizeof(drv_load_params));
1045 drv_load_params.is_crash_kernel = is_kdump_kernel();
1046 drv_load_params.mfw_timeout_val = QED_LOAD_REQ_LOCK_TO_DEFAULT;
1047 drv_load_params.avoid_eng_reset = false;
1048 drv_load_params.override_force_load = QED_OVERRIDE_FORCE_LOAD_NONE;
1049 hw_init_params.p_drv_load_params = &drv_load_params;
1050
c0c2d0b4 1051 rc = qed_hw_init(cdev, &hw_init_params);
fe56b9e6 1052 if (rc)
8c925c44 1053 goto err2;
fe56b9e6
YM		 1054
1055 DP_INFO(cdev,
1056 "HW initialization and function start completed successfully\n");
1057
eaf3c0c6
CM		 1058 if (IS_PF(cdev)) {
1059 cdev->tunn_feature_mask = (BIT(QED_MODE_VXLAN_TUNN) |
1060 BIT(QED_MODE_L2GENEVE_TUNN) |
1061 BIT(QED_MODE_IPGENEVE_TUNN) |
1062 BIT(QED_MODE_L2GRE_TUNN) |
1063 BIT(QED_MODE_IPGRE_TUNN));
1064 }
1065
0a7fb11c
YM		 1066 /* Allocate LL2 interface if needed */
1067 if (QED_LEADING_HWFN(cdev)->using_ll2) {
1068 rc = qed_ll2_alloc_if(cdev);
1069 if (rc)
1070 goto err3;
1071 }
1408cc1f
YM		 1072 if (IS_PF(cdev)) {
1073 hwfn = QED_LEADING_HWFN(cdev);
1074 drv_version.version = (params->drv_major << 24) |
1075 (params->drv_minor << 16) |
1076 (params->drv_rev << 8) |
1077 (params->drv_eng);
1078 strlcpy(drv_version.name, params->name,
1079 MCP_DRV_VER_STR_SIZE - 4);
1080 rc = qed_mcp_send_drv_version(hwfn, hwfn->p_main_ptt,
1081 &drv_version);
1082 if (rc) {
1083 DP_NOTICE(cdev, "Failed sending drv version command\n");
19df21e5 1084 goto err4;
1408cc1f 1085 }
fe56b9e6
YM		 1086 }
1087
8c925c44
YM		 1088 qed_reset_vport_stats(cdev);
1089
fe56b9e6
YM		 1090 return 0;
1091
19df21e5
WW		 1092err4:
1093 qed_ll2_dealloc_if(cdev);
0a7fb11c
YM		 1094err3:
1095 qed_hw_stop(cdev);
fe56b9e6 1096err2:
8c925c44 1097 qed_hw_timers_stop_all(cdev);
1408cc1f
YM		 1098 if (IS_PF(cdev))
1099 qed_slowpath_irq_free(cdev);
8c925c44 1100 qed_free_stream_mem(cdev);
fe56b9e6
YM		 1101 qed_disable_msix(cdev);
1102err1:
1103 qed_resc_free(cdev);
1104err:
1408cc1f
YM		 1105 if (IS_PF(cdev))
1106 release_firmware(cdev->firmware);
fe56b9e6 1107
d51e4af5
CM		 1108 if (IS_PF(cdev) && (cdev->num_hwfns == 1) &&
1109 QED_LEADING_HWFN(cdev)->p_arfs_ptt)
1110 qed_ptt_release(QED_LEADING_HWFN(cdev),
1111 QED_LEADING_HWFN(cdev)->p_arfs_ptt);
c78c70fa 1112
37bff2b9
YM		 1113 qed_iov_wq_stop(cdev, false);
1114
fe56b9e6
YM		 1115 return rc;
1116}
1117
1118static int qed_slowpath_stop(struct qed_dev *cdev)
1119{
1120 if (!cdev)
1121 return -ENODEV;
1122
0a7fb11c
YM		 1123 qed_ll2_dealloc_if(cdev);
1124
1408cc1f 1125 if (IS_PF(cdev)) {
d51e4af5
CM		 1126 if (cdev->num_hwfns == 1)
1127 qed_ptt_release(QED_LEADING_HWFN(cdev),
1128 QED_LEADING_HWFN(cdev)->p_arfs_ptt);
1408cc1f 1129 qed_free_stream_mem(cdev);
c5ac9319
YM		 1130 if (IS_QED_ETH_IF(cdev))
1131 qed_sriov_disable(cdev, true);
5f027d7a
MY		 1132 }
1133
1134 qed_nic_stop(cdev);
fe56b9e6 1135
5f027d7a 1136 if (IS_PF(cdev))
1408cc1f 1137 qed_slowpath_irq_free(cdev);
fe56b9e6
YM		 1138
1139 qed_disable_msix(cdev);
1226337a
TT		 1140
1141 qed_resc_free(cdev);
fe56b9e6 1142
37bff2b9
YM		 1143 qed_iov_wq_stop(cdev, true);
1144
1408cc1f
YM		 1145 if (IS_PF(cdev))
1146 release_firmware(cdev->firmware);
fe56b9e6
YM		 1147
1148 return 0;
1149}
1150
712c3cbf 1151static void qed_set_name(struct qed_dev *cdev, char name[NAME_SIZE])
fe56b9e6
YM		 1152{
1153 int i;
1154
1155 memcpy(cdev->name, name, NAME_SIZE);
1156 for_each_hwfn(cdev, i)
1157 snprintf(cdev->hwfns[i].name, NAME_SIZE, "%s-%d", name, i);
fe56b9e6
YM		 1158}
1159
1160static u32 qed_sb_init(struct qed_dev *cdev,
1161 struct qed_sb_info *sb_info,
1162 void *sb_virt_addr,
1163 dma_addr_t sb_phy_addr, u16 sb_id,
1164 enum qed_sb_type type)
1165{
1166 struct qed_hwfn *p_hwfn;
85750d74 1167 struct qed_ptt *p_ptt;
fe56b9e6
YM		 1168 int hwfn_index;
1169 u16 rel_sb_id;
1170 u8 n_hwfns;
1171 u32 rc;
1172
1173 /* RoCE uses single engine and CMT uses two engines. When using both
1174 * we force only a single engine. Storage uses only engine 0 too.
1175 */
1176 if (type == QED_SB_TYPE_L2_QUEUE)
1177 n_hwfns = cdev->num_hwfns;
1178 else
1179 n_hwfns = 1;
1180
1181 hwfn_index = sb_id % n_hwfns;
1182 p_hwfn = &cdev->hwfns[hwfn_index];
1183 rel_sb_id = sb_id / n_hwfns;
1184
1185 DP_VERBOSE(cdev, NETIF_MSG_INTR,
1186 "hwfn [%d] <--[init]-- SB %04x [0x%04x upper]\n",
1187 hwfn_index, rel_sb_id, sb_id);
1188
85750d74
MY		 1189 if (IS_PF(p_hwfn->cdev)) {
1190 p_ptt = qed_ptt_acquire(p_hwfn);
1191 if (!p_ptt)
1192 return -EBUSY;
1193
1194 rc = qed_int_sb_init(p_hwfn, p_ptt, sb_info, sb_virt_addr,
1195 sb_phy_addr, rel_sb_id);
1196 qed_ptt_release(p_hwfn, p_ptt);
1197 } else {
1198 rc = qed_int_sb_init(p_hwfn, NULL, sb_info, sb_virt_addr,
1199 sb_phy_addr, rel_sb_id);
1200 }
fe56b9e6
YM		 1201
1202 return rc;
1203}
1204
1205static u32 qed_sb_release(struct qed_dev *cdev,
1a635e48 1206 struct qed_sb_info *sb_info, u16 sb_id)
fe56b9e6
YM		 1207{
1208 struct qed_hwfn *p_hwfn;
1209 int hwfn_index;
1210 u16 rel_sb_id;
1211 u32 rc;
1212
1213 hwfn_index = sb_id % cdev->num_hwfns;
1214 p_hwfn = &cdev->hwfns[hwfn_index];
1215 rel_sb_id = sb_id / cdev->num_hwfns;
1216
1217 DP_VERBOSE(cdev, NETIF_MSG_INTR,
1218 "hwfn [%d] <--[init]-- SB %04x [0x%04x upper]\n",
1219 hwfn_index, rel_sb_id, sb_id);
1220
1221 rc = qed_int_sb_release(p_hwfn, sb_info, rel_sb_id);
1222
1223 return rc;
1224}
1225
fe7cd2bf
YM		 1226static bool qed_can_link_change(struct qed_dev *cdev)
1227{
1228 return true;
1229}
1230
351a4ded 1231static int qed_set_link(struct qed_dev *cdev, struct qed_link_params *params)
cc875c2e
YM		 1232{
1233 struct qed_hwfn *hwfn;
1234 struct qed_mcp_link_params *link_params;
1235 struct qed_ptt *ptt;
1236 int rc;
1237
1238 if (!cdev)
1239 return -ENODEV;
1240
1241 /* The link should be set only once per PF */
1242 hwfn = &cdev->hwfns[0];
1243
65ed2ffd
MY		 1244 /* When VF wants to set link, force it to read the bulletin instead.
1245 * This mimics the PF behavior, where a noitification [both immediate
1246 * and possible later] would be generated when changing properties.
1247 */
1248 if (IS_VF(cdev)) {
1249 qed_schedule_iov(hwfn, QED_IOV_WQ_VF_FORCE_LINK_QUERY_FLAG);
1250 return 0;
1251 }
1252
cc875c2e
YM		 1253 ptt = qed_ptt_acquire(hwfn);
1254 if (!ptt)
1255 return -EBUSY;
1256
1257 link_params = qed_mcp_get_link_params(hwfn);
1258 if (params->override_flags & QED_LINK_OVERRIDE_SPEED_AUTONEG)
1259 link_params->speed.autoneg = params->autoneg;
1260 if (params->override_flags & QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS) {
1261 link_params->speed.advertised_speeds = 0;
054c67d1
SRK		 1262 if ((params->adv_speeds & QED_LM_1000baseT_Half_BIT) ||
1263 (params->adv_speeds & QED_LM_1000baseT_Full_BIT))
cc875c2e 1264 link_params->speed.advertised_speeds |=
054c67d1
SRK		 1265 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G;
1266 if (params->adv_speeds & QED_LM_10000baseKR_Full_BIT)
cc875c2e 1267 link_params->speed.advertised_speeds |=
054c67d1
SRK		 1268 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G;
1269 if (params->adv_speeds & QED_LM_25000baseKR_Full_BIT)
cc875c2e 1270 link_params->speed.advertised_speeds |=
054c67d1
SRK		 1271 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G;
1272 if (params->adv_speeds & QED_LM_40000baseLR4_Full_BIT)
cc875c2e 1273 link_params->speed.advertised_speeds |=
054c67d1
SRK		 1274 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G;
1275 if (params->adv_speeds & QED_LM_50000baseKR2_Full_BIT)
1276 link_params->speed.advertised_speeds |=
1277 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G;
1278 if (params->adv_speeds & QED_LM_100000baseKR4_Full_BIT)
cc875c2e 1279 link_params->speed.advertised_speeds |=
351a4ded 1280 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G;
cc875c2e
YM		 1281 }
1282 if (params->override_flags & QED_LINK_OVERRIDE_SPEED_FORCED_SPEED)
1283 link_params->speed.forced_speed = params->forced_speed;
a43f235f
SRK		 1284 if (params->override_flags & QED_LINK_OVERRIDE_PAUSE_CONFIG) {
1285 if (params->pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE)
1286 link_params->pause.autoneg = true;
1287 else
1288 link_params->pause.autoneg = false;
1289 if (params->pause_config & QED_LINK_PAUSE_RX_ENABLE)
1290 link_params->pause.forced_rx = true;
1291 else
1292 link_params->pause.forced_rx = false;
1293 if (params->pause_config & QED_LINK_PAUSE_TX_ENABLE)
1294 link_params->pause.forced_tx = true;
1295 else
1296 link_params->pause.forced_tx = false;
1297 }
03dc76ca
SRK		 1298 if (params->override_flags & QED_LINK_OVERRIDE_LOOPBACK_MODE) {
1299 switch (params->loopback_mode) {
1300 case QED_LINK_LOOPBACK_INT_PHY:
351a4ded 1301 link_params->loopback_mode = ETH_LOOPBACK_INT_PHY;
03dc76ca
SRK		 1302 break;
1303 case QED_LINK_LOOPBACK_EXT_PHY:
351a4ded 1304 link_params->loopback_mode = ETH_LOOPBACK_EXT_PHY;
03dc76ca
SRK		 1305 break;
1306 case QED_LINK_LOOPBACK_EXT:
351a4ded 1307 link_params->loopback_mode = ETH_LOOPBACK_EXT;
03dc76ca
SRK		 1308 break;
1309 case QED_LINK_LOOPBACK_MAC:
351a4ded 1310 link_params->loopback_mode = ETH_LOOPBACK_MAC;
03dc76ca
SRK		 1311 break;
1312 default:
351a4ded 1313 link_params->loopback_mode = ETH_LOOPBACK_NONE;
03dc76ca
SRK		 1314 break;
1315 }
1316 }
cc875c2e 1317
645874e5
SRK		 1318 if (params->override_flags & QED_LINK_OVERRIDE_EEE_CONFIG)
1319 memcpy(&link_params->eee, &params->eee,
1320 sizeof(link_params->eee));
1321
cc875c2e
YM		 1322 rc = qed_mcp_set_link(hwfn, ptt, params->link_up);
1323
1324 qed_ptt_release(hwfn, ptt);
1325
1326 return rc;
1327}
1328
1329static int qed_get_port_type(u32 media_type)
1330{
1331 int port_type;
1332
1333 switch (media_type) {
1334 case MEDIA_SFPP_10G_FIBER:
1335 case MEDIA_SFP_1G_FIBER:
1336 case MEDIA_XFP_FIBER:
b639f197 1337 case MEDIA_MODULE_FIBER:
cc875c2e
YM		 1338 case MEDIA_KR:
1339 port_type = PORT_FIBRE;
1340 break;
1341 case MEDIA_DA_TWINAX:
1342 port_type = PORT_DA;
1343 break;
1344 case MEDIA_BASE_T:
1345 port_type = PORT_TP;
1346 break;
1347 case MEDIA_NOT_PRESENT:
1348 port_type = PORT_NONE;
1349 break;
1350 case MEDIA_UNSPECIFIED:
1351 default:
1352 port_type = PORT_OTHER;
1353 break;
1354 }
1355 return port_type;
1356}
1357
14b84e86
AB		 1358static int qed_get_link_data(struct qed_hwfn *hwfn,
1359 struct qed_mcp_link_params *params,
1360 struct qed_mcp_link_state *link,
1361 struct qed_mcp_link_capabilities *link_caps)
1362{
1363 void *p;
1364
1365 if (!IS_PF(hwfn->cdev)) {
1366 qed_vf_get_link_params(hwfn, params);
1367 qed_vf_get_link_state(hwfn, link);
1368 qed_vf_get_link_caps(hwfn, link_caps);
1369
1370 return 0;
1371 }
1372
1373 p = qed_mcp_get_link_params(hwfn);
1374 if (!p)
1375 return -ENXIO;
1376 memcpy(params, p, sizeof(*params));
1377
1378 p = qed_mcp_get_link_state(hwfn);
1379 if (!p)
1380 return -ENXIO;
1381 memcpy(link, p, sizeof(*link));
1382
1383 p = qed_mcp_get_link_capabilities(hwfn);
1384 if (!p)
1385 return -ENXIO;
1386 memcpy(link_caps, p, sizeof(*link_caps));
1387
1388 return 0;
1389}
1390
cc875c2e
YM		 1391static void qed_fill_link(struct qed_hwfn *hwfn,
1392 struct qed_link_output *if_link)
1393{
1394 struct qed_mcp_link_params params;
1395 struct qed_mcp_link_state link;
1396 struct qed_mcp_link_capabilities link_caps;
1397 u32 media_type;
1398
1399 memset(if_link, 0, sizeof(*if_link));
1400
1401 /* Prepare source inputs */
14b84e86
AB		 1402 if (qed_get_link_data(hwfn, &params, &link, &link_caps)) {
1403 dev_warn(&hwfn->cdev->pdev->dev, "no link data available\n");
1404 return;
1408cc1f 1405 }
cc875c2e
YM		 1406
1407 /* Set the link parameters to pass to protocol driver */
1408 if (link.link_up)
1409 if_link->link_up = true;
1410
1411 /* TODO - at the moment assume supported and advertised speed equal */
054c67d1 1412 if_link->supported_caps = QED_LM_FIBRE_BIT;
34f9199c 1413 if (link_caps.default_speed_autoneg)
054c67d1 1414 if_link->supported_caps |= QED_LM_Autoneg_BIT;
cc875c2e
YM		 1415 if (params.pause.autoneg ||
1416 (params.pause.forced_rx && params.pause.forced_tx))
054c67d1 1417 if_link->supported_caps |= QED_LM_Asym_Pause_BIT;
cc875c2e
YM		 1418 if (params.pause.autoneg || params.pause.forced_rx ||
1419 params.pause.forced_tx)
054c67d1 1420 if_link->supported_caps |= QED_LM_Pause_BIT;
cc875c2e
YM		 1421
1422 if_link->advertised_caps = if_link->supported_caps;
34f9199c 1423 if (params.speed.autoneg)
1424 if_link->advertised_caps |= QED_LM_Autoneg_BIT;
1425 else
1426 if_link->advertised_caps &= ~QED_LM_Autoneg_BIT;
cc875c2e
YM		 1427 if (params.speed.advertised_speeds &
1428 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
054c67d1
SRK		 1429 if_link->advertised_caps |= QED_LM_1000baseT_Half_BIT |
1430 QED_LM_1000baseT_Full_BIT;
cc875c2e
YM		 1431 if (params.speed.advertised_speeds &
1432 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
054c67d1
SRK		 1433 if_link->advertised_caps |= QED_LM_10000baseKR_Full_BIT;
1434 if (params.speed.advertised_speeds &
1435 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
1436 if_link->advertised_caps |= QED_LM_25000baseKR_Full_BIT;
cc875c2e 1437 if (params.speed.advertised_speeds &
054c67d1
SRK		 1438 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
1439 if_link->advertised_caps |= QED_LM_40000baseLR4_Full_BIT;
cc875c2e 1440 if (params.speed.advertised_speeds &
054c67d1
SRK		 1441 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
1442 if_link->advertised_caps |= QED_LM_50000baseKR2_Full_BIT;
cc875c2e 1443 if (params.speed.advertised_speeds &
351a4ded 1444 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
054c67d1 1445 if_link->advertised_caps |= QED_LM_100000baseKR4_Full_BIT;
cc875c2e
YM		 1446
1447 if (link_caps.speed_capabilities &
1448 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
054c67d1
SRK		 1449 if_link->supported_caps |= QED_LM_1000baseT_Half_BIT |
1450 QED_LM_1000baseT_Full_BIT;
cc875c2e
YM		 1451 if (link_caps.speed_capabilities &
1452 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
054c67d1
SRK		 1453 if_link->supported_caps |= QED_LM_10000baseKR_Full_BIT;
1454 if (link_caps.speed_capabilities &
1455 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
1456 if_link->supported_caps |= QED_LM_25000baseKR_Full_BIT;
cc875c2e 1457 if (link_caps.speed_capabilities &
054c67d1
SRK		 1458 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
1459 if_link->supported_caps |= QED_LM_40000baseLR4_Full_BIT;
cc875c2e 1460 if (link_caps.speed_capabilities &
054c67d1
SRK		 1461 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
1462 if_link->supported_caps |= QED_LM_50000baseKR2_Full_BIT;
cc875c2e 1463 if (link_caps.speed_capabilities &
351a4ded 1464 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
054c67d1 1465 if_link->supported_caps |= QED_LM_100000baseKR4_Full_BIT;
cc875c2e
YM		 1466
1467 if (link.link_up)
1468 if_link->speed = link.speed;
1469
1470 /* TODO - fill duplex properly */
1471 if_link->duplex = DUPLEX_FULL;
1472 qed_mcp_get_media_type(hwfn->cdev, &media_type);
1473 if_link->port = qed_get_port_type(media_type);
1474
1475 if_link->autoneg = params.speed.autoneg;
1476
1477 if (params.pause.autoneg)
1478 if_link->pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE;
1479 if (params.pause.forced_rx)
1480 if_link->pause_config |= QED_LINK_PAUSE_RX_ENABLE;
1481 if (params.pause.forced_tx)
1482 if_link->pause_config |= QED_LINK_PAUSE_TX_ENABLE;
1483
1484 /* Link partner capabilities */
054c67d1
SRK		 1485 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_1G_HD)
1486 if_link->lp_caps |= QED_LM_1000baseT_Half_BIT;
1487 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_1G_FD)
1488 if_link->lp_caps |= QED_LM_1000baseT_Full_BIT;
1489 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_10G)
1490 if_link->lp_caps |= QED_LM_10000baseKR_Full_BIT;
1491 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_25G)
1492 if_link->lp_caps |= QED_LM_25000baseKR_Full_BIT;
1493 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_40G)
1494 if_link->lp_caps |= QED_LM_40000baseLR4_Full_BIT;
1495 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_50G)
1496 if_link->lp_caps |= QED_LM_50000baseKR2_Full_BIT;
1497 if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_100G)
1498 if_link->lp_caps |= QED_LM_100000baseKR4_Full_BIT;
cc875c2e
YM		 1499
1500 if (link.an_complete)
054c67d1 1501 if_link->lp_caps |= QED_LM_Autoneg_BIT;
cc875c2e
YM		 1502
1503 if (link.partner_adv_pause)
054c67d1 1504 if_link->lp_caps |= QED_LM_Pause_BIT;
cc875c2e
YM		 1505 if (link.partner_adv_pause == QED_LINK_PARTNER_ASYMMETRIC_PAUSE ||
1506 link.partner_adv_pause == QED_LINK_PARTNER_BOTH_PAUSE)
054c67d1 1507 if_link->lp_caps |= QED_LM_Asym_Pause_BIT;
645874e5
SRK		 1508
1509 if (link_caps.default_eee == QED_MCP_EEE_UNSUPPORTED) {
1510 if_link->eee_supported = false;
1511 } else {
1512 if_link->eee_supported = true;
1513 if_link->eee_active = link.eee_active;
1514 if_link->sup_caps = link_caps.eee_speed_caps;
1515 /* MFW clears adv_caps on eee disable; use configured value */
1516 if_link->eee.adv_caps = link.eee_adv_caps ? link.eee_adv_caps :
1517 params.eee.adv_caps;
1518 if_link->eee.lp_adv_caps = link.eee_lp_adv_caps;
1519 if_link->eee.enable = params.eee.enable;
1520 if_link->eee.tx_lpi_enable = params.eee.tx_lpi_enable;
1521 if_link->eee.tx_lpi_timer = params.eee.tx_lpi_timer;
1522 }
cc875c2e
YM		 1523}
1524
1525static void qed_get_current_link(struct qed_dev *cdev,
1526 struct qed_link_output *if_link)
1527{
36558c3d
YM		 1528 int i;
1529
cc875c2e 1530 qed_fill_link(&cdev->hwfns[0], if_link);
36558c3d
YM		 1531
1532 for_each_hwfn(cdev, i)
1533 qed_inform_vf_link_state(&cdev->hwfns[i]);
cc875c2e
YM		 1534}
1535
1536void qed_link_update(struct qed_hwfn *hwfn)
1537{
1538 void *cookie = hwfn->cdev->ops_cookie;
1539 struct qed_common_cb_ops *op = hwfn->cdev->protocol_ops.common;
1540 struct qed_link_output if_link;
1541
1542 qed_fill_link(hwfn, &if_link);
36558c3d 1543 qed_inform_vf_link_state(hwfn);
cc875c2e
YM		 1544
1545 if (IS_LEAD_HWFN(hwfn) && cookie)
1546 op->link_update(cookie, &if_link);
1547}
1548
fe56b9e6
YM		 1549static int qed_drain(struct qed_dev *cdev)
1550{
1551 struct qed_hwfn *hwfn;
1552 struct qed_ptt *ptt;
1553 int i, rc;
1554
1408cc1f
YM		 1555 if (IS_VF(cdev))
1556 return 0;
1557
fe56b9e6
YM		 1558 for_each_hwfn(cdev, i) {
1559 hwfn = &cdev->hwfns[i];
1560 ptt = qed_ptt_acquire(hwfn);
1561 if (!ptt) {
1562 DP_NOTICE(hwfn, "Failed to drain NIG; No PTT\n");
1563 return -EBUSY;
1564 }
1565 rc = qed_mcp_drain(hwfn, ptt);
3aaafac7 1566 qed_ptt_release(hwfn, ptt);
fe56b9e6
YM		 1567 if (rc)
1568 return rc;
fe56b9e6
YM		 1569 }
1570
1571 return 0;
1572}
1573
20675b37
MY		 1574static int qed_nvm_get_image(struct qed_dev *cdev, enum qed_nvm_images type,
1575 u8 *buf, u16 len)
1576{
1577 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
1578 struct qed_ptt *ptt = qed_ptt_acquire(hwfn);
1579 int rc;
1580
1581 if (!ptt)
1582 return -EAGAIN;
1583
1584 rc = qed_mcp_get_nvm_image(hwfn, ptt, type, buf, len);
1585 qed_ptt_release(hwfn, ptt);
1586 return rc;
1587}
1588
722003ac 1589static int qed_set_coalesce(struct qed_dev *cdev, u16 rx_coal, u16 tx_coal,
477f2d14 1590 void *handle)
722003ac 1591{
477f2d14 1592 return qed_set_queue_coalesce(rx_coal, tx_coal, handle);
722003ac
SRK		 1593}
1594
91420b83
SK		 1595static int qed_set_led(struct qed_dev *cdev, enum qed_led_mode mode)
1596{
1597 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
1598 struct qed_ptt *ptt;
1599 int status = 0;
1600
1601 ptt = qed_ptt_acquire(hwfn);
1602 if (!ptt)
1603 return -EAGAIN;
1604
1605 status = qed_mcp_set_led(hwfn, ptt, mode);
1606
1607 qed_ptt_release(hwfn, ptt);
1608
1609 return status;
1610}
1611
14d39648
MY		 1612static int qed_update_wol(struct qed_dev *cdev, bool enabled)
1613{
1614 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
1615 struct qed_ptt *ptt;
1616 int rc = 0;
1617
1618 if (IS_VF(cdev))
1619 return 0;
1620
1621 ptt = qed_ptt_acquire(hwfn);
1622 if (!ptt)
1623 return -EAGAIN;
1624
1625 rc = qed_mcp_ov_update_wol(hwfn, ptt, enabled ? QED_OV_WOL_ENABLED
1626 : QED_OV_WOL_DISABLED);
1627 if (rc)
1628 goto out;
1629 rc = qed_mcp_ov_update_current_config(hwfn, ptt, QED_OV_CLIENT_DRV);
1630
1631out:
1632 qed_ptt_release(hwfn, ptt);
1633 return rc;
1634}
1635
0fefbfba
SK		 1636static int qed_update_drv_state(struct qed_dev *cdev, bool active)
1637{
1638 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
1639 struct qed_ptt *ptt;
1640 int status = 0;
1641
1642 if (IS_VF(cdev))
1643 return 0;
1644
1645 ptt = qed_ptt_acquire(hwfn);
1646 if (!ptt)
1647 return -EAGAIN;
1648
1649 status = qed_mcp_ov_update_driver_state(hwfn, ptt, active ?
1650 QED_OV_DRIVER_STATE_ACTIVE :
1651 QED_OV_DRIVER_STATE_DISABLED);
1652
1653 qed_ptt_release(hwfn, ptt);
1654
1655 return status;
1656}
1657
1658static int qed_update_mac(struct qed_dev *cdev, u8 *mac)
1659{
1660 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
1661 struct qed_ptt *ptt;
1662 int status = 0;
1663
1664 if (IS_VF(cdev))
1665 return 0;
1666
1667 ptt = qed_ptt_acquire(hwfn);
1668 if (!ptt)
1669 return -EAGAIN;
1670
1671 status = qed_mcp_ov_update_mac(hwfn, ptt, mac);
1672 if (status)
1673 goto out;
1674
1675 status = qed_mcp_ov_update_current_config(hwfn, ptt, QED_OV_CLIENT_DRV);
1676
1677out:
1678 qed_ptt_release(hwfn, ptt);
1679 return status;
1680}
1681
1682static int qed_update_mtu(struct qed_dev *cdev, u16 mtu)
1683{
1684 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
1685 struct qed_ptt *ptt;
1686 int status = 0;
1687
1688 if (IS_VF(cdev))
1689 return 0;
1690
1691 ptt = qed_ptt_acquire(hwfn);
1692 if (!ptt)
1693 return -EAGAIN;
1694
1695 status = qed_mcp_ov_update_mtu(hwfn, ptt, mtu);
1696 if (status)
1697 goto out;
1698
1699 status = qed_mcp_ov_update_current_config(hwfn, ptt, QED_OV_CLIENT_DRV);
1700
1701out:
1702 qed_ptt_release(hwfn, ptt);
1703 return status;
1704}
1705
8c93beaf 1706static struct qed_selftest_ops qed_selftest_ops_pass = {
03dc76ca
SRK		 1707 .selftest_memory = &qed_selftest_memory,
1708 .selftest_interrupt = &qed_selftest_interrupt,
1709 .selftest_register = &qed_selftest_register,
1710 .selftest_clock = &qed_selftest_clock,
7a4b21b7 1711 .selftest_nvram = &qed_selftest_nvram,
03dc76ca
SRK		 1712};
1713
fe56b9e6 1714const struct qed_common_ops qed_common_ops_pass = {
03dc76ca 1715 .selftest = &qed_selftest_ops_pass,
fe56b9e6
YM		 1716 .probe = &qed_probe,
1717 .remove = &qed_remove,
1718 .set_power_state = &qed_set_power_state,
712c3cbf 1719 .set_name = &qed_set_name,
fe56b9e6
YM		 1720 .update_pf_params = &qed_update_pf_params,
1721 .slowpath_start = &qed_slowpath_start,
1722 .slowpath_stop = &qed_slowpath_stop,
1723 .set_fp_int = &qed_set_int_fp,
1724 .get_fp_int = &qed_get_int_fp,
1725 .sb_init = &qed_sb_init,
1726 .sb_release = &qed_sb_release,
1727 .simd_handler_config = &qed_simd_handler_config,
1728 .simd_handler_clean = &qed_simd_handler_clean,
1e128c81
AE		 1729 .dbg_grc = &qed_dbg_grc,
1730 .dbg_grc_size = &qed_dbg_grc_size,
fe7cd2bf 1731 .can_link_change = &qed_can_link_change,
cc875c2e
YM		 1732 .set_link = &qed_set_link,
1733 .get_link = &qed_get_current_link,
fe56b9e6
YM		 1734 .drain = &qed_drain,
1735 .update_msglvl = &qed_init_dp,
e0971c83
TT		 1736 .dbg_all_data = &qed_dbg_all_data,
1737 .dbg_all_data_size = &qed_dbg_all_data_size,
fe56b9e6
YM		 1738 .chain_alloc = &qed_chain_alloc,
1739 .chain_free = &qed_chain_free,
20675b37 1740 .nvm_get_image = &qed_nvm_get_image,
722003ac 1741 .set_coalesce = &qed_set_coalesce,
91420b83 1742 .set_led = &qed_set_led,
0fefbfba
SK		 1743 .update_drv_state = &qed_update_drv_state,
1744 .update_mac = &qed_update_mac,
1745 .update_mtu = &qed_update_mtu,
14d39648 1746 .update_wol = &qed_update_wol,
fe56b9e6 1747};
6c754246
SRK		 1748
1749void qed_get_protocol_stats(struct qed_dev *cdev,
1750 enum qed_mcp_protocol_type type,
1751 union qed_mcp_protocol_stats *stats)
1752{
1753 struct qed_eth_stats eth_stats;
1754
1755 memset(stats, 0, sizeof(*stats));
1756
1757 switch (type) {
1758 case QED_MCP_LAN_STATS:
1759 qed_get_vport_stats(cdev, &eth_stats);
9c79ddaa
MY		 1760 stats->lan_stats.ucast_rx_pkts =
1761 eth_stats.common.rx_ucast_pkts;
1762 stats->lan_stats.ucast_tx_pkts =
1763 eth_stats.common.tx_ucast_pkts;
6c754246
SRK		 1764 stats->lan_stats.fcs_err = -1;
1765 break;
1e128c81
AE		 1766 case QED_MCP_FCOE_STATS:
1767 qed_get_protocol_stats_fcoe(cdev, &stats->fcoe_stats);
1768 break;
2f2b2614
MY		 1769 case QED_MCP_ISCSI_STATS:
1770 qed_get_protocol_stats_iscsi(cdev, &stats->iscsi_stats);
1771 break;
6c754246 1772 default:
512c7840
MY		 1773 DP_VERBOSE(cdev, QED_MSG_SP,
1774 "Invalid protocol type = %d\n", type);
6c754246
SRK		 1775 return;
1776 }
1777}
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