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qed: Learn of RDMA capabilities per-device
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / qlogic / qed / qed_mcp.c
CommitLineData
fe56b9e6
YM		 1/* QLogic qed NIC Driver
2 * Copyright (c) 2015 QLogic Corporation
3 *
4 * This software is available under the terms of the GNU General Public License
5 * (GPL) Version 2, available from the file COPYING in the main directory of
6 * this source tree.
7 */
8
9#include <linux/types.h>
10#include <asm/byteorder.h>
11#include <linux/delay.h>
12#include <linux/errno.h>
13#include <linux/kernel.h>
fe56b9e6 14#include <linux/slab.h>
5529bad9 15#include <linux/spinlock.h>
fe56b9e6 16#include <linux/string.h>
0fefbfba 17#include <linux/etherdevice.h>
fe56b9e6 18#include "qed.h"
39651abd 19#include "qed_dcbx.h"
fe56b9e6
YM		 20#include "qed_hsi.h"
21#include "qed_hw.h"
22#include "qed_mcp.h"
23#include "qed_reg_addr.h"
1408cc1f
YM		 24#include "qed_sriov.h"
25
fe56b9e6
YM		 26#define CHIP_MCP_RESP_ITER_US 10
27
28#define QED_DRV_MB_MAX_RETRIES (500 * 1000) /* Account for 5 sec */
29#define QED_MCP_RESET_RETRIES (50 * 1000) /* Account for 500 msec */
30
31#define DRV_INNER_WR(_p_hwfn, _p_ptt, _ptr, _offset, _val) \
32 qed_wr(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset), \
33 _val)
34
35#define DRV_INNER_RD(_p_hwfn, _p_ptt, _ptr, _offset) \
36 qed_rd(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset))
37
38#define DRV_MB_WR(_p_hwfn, _p_ptt, _field, _val) \
39 DRV_INNER_WR(p_hwfn, _p_ptt, drv_mb_addr, \
40 offsetof(struct public_drv_mb, _field), _val)
41
42#define DRV_MB_RD(_p_hwfn, _p_ptt, _field) \
43 DRV_INNER_RD(_p_hwfn, _p_ptt, drv_mb_addr, \
44 offsetof(struct public_drv_mb, _field))
45
46#define PDA_COMP (((FW_MAJOR_VERSION) + (FW_MINOR_VERSION << 8)) << \
47 DRV_ID_PDA_COMP_VER_SHIFT)
48
49#define MCP_BYTES_PER_MBIT_SHIFT 17
50
51bool qed_mcp_is_init(struct qed_hwfn *p_hwfn)
52{
53 if (!p_hwfn->mcp_info || !p_hwfn->mcp_info->public_base)
54 return false;
55 return true;
56}
57
1a635e48 58void qed_mcp_cmd_port_init(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
fe56b9e6
YM		 59{
60 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
61 PUBLIC_PORT);
62 u32 mfw_mb_offsize = qed_rd(p_hwfn, p_ptt, addr);
63
64 p_hwfn->mcp_info->port_addr = SECTION_ADDR(mfw_mb_offsize,
65 MFW_PORT(p_hwfn));
66 DP_VERBOSE(p_hwfn, QED_MSG_SP,
67 "port_addr = 0x%x, port_id 0x%02x\n",
68 p_hwfn->mcp_info->port_addr, MFW_PORT(p_hwfn));
69}
70
1a635e48 71void qed_mcp_read_mb(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
fe56b9e6
YM		 72{
73 u32 length = MFW_DRV_MSG_MAX_DWORDS(p_hwfn->mcp_info->mfw_mb_length);
74 u32 tmp, i;
75
76 if (!p_hwfn->mcp_info->public_base)
77 return;
78
79 for (i = 0; i < length; i++) {
80 tmp = qed_rd(p_hwfn, p_ptt,
81 p_hwfn->mcp_info->mfw_mb_addr +
82 (i << 2) + sizeof(u32));
83
84 /* The MB data is actually BE; Need to force it to cpu */
85 ((u32 *)p_hwfn->mcp_info->mfw_mb_cur)[i] =
86 be32_to_cpu((__force __be32)tmp);
87 }
88}
89
90int qed_mcp_free(struct qed_hwfn *p_hwfn)
91{
92 if (p_hwfn->mcp_info) {
93 kfree(p_hwfn->mcp_info->mfw_mb_cur);
94 kfree(p_hwfn->mcp_info->mfw_mb_shadow);
95 }
96 kfree(p_hwfn->mcp_info);
97
98 return 0;
99}
100
1a635e48 101static int qed_load_mcp_offsets(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
fe56b9e6
YM		 102{
103 struct qed_mcp_info *p_info = p_hwfn->mcp_info;
104 u32 drv_mb_offsize, mfw_mb_offsize;
105 u32 mcp_pf_id = MCP_PF_ID(p_hwfn);
106
107 p_info->public_base = qed_rd(p_hwfn, p_ptt, MISC_REG_SHARED_MEM_ADDR);
108 if (!p_info->public_base)
109 return 0;
110
111 p_info->public_base |= GRCBASE_MCP;
112
113 /* Calculate the driver and MFW mailbox address */
114 drv_mb_offsize = qed_rd(p_hwfn, p_ptt,
115 SECTION_OFFSIZE_ADDR(p_info->public_base,
116 PUBLIC_DRV_MB));
117 p_info->drv_mb_addr = SECTION_ADDR(drv_mb_offsize, mcp_pf_id);
118 DP_VERBOSE(p_hwfn, QED_MSG_SP,
119 "drv_mb_offsiz = 0x%x, drv_mb_addr = 0x%x mcp_pf_id = 0x%x\n",
120 drv_mb_offsize, p_info->drv_mb_addr, mcp_pf_id);
121
122 /* Set the MFW MB address */
123 mfw_mb_offsize = qed_rd(p_hwfn, p_ptt,
124 SECTION_OFFSIZE_ADDR(p_info->public_base,
125 PUBLIC_MFW_MB));
126 p_info->mfw_mb_addr = SECTION_ADDR(mfw_mb_offsize, mcp_pf_id);
127 p_info->mfw_mb_length = (u16)qed_rd(p_hwfn, p_ptt, p_info->mfw_mb_addr);
128
129 /* Get the current driver mailbox sequence before sending
130 * the first command
131 */
132 p_info->drv_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) &
133 DRV_MSG_SEQ_NUMBER_MASK;
134
135 /* Get current FW pulse sequence */
136 p_info->drv_pulse_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_pulse_mb) &
137 DRV_PULSE_SEQ_MASK;
138
139 p_info->mcp_hist = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
140
141 return 0;
142}
143
1a635e48 144int qed_mcp_cmd_init(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
fe56b9e6
YM		 145{
146 struct qed_mcp_info *p_info;
147 u32 size;
148
149 /* Allocate mcp_info structure */
60fffb3b 150 p_hwfn->mcp_info = kzalloc(sizeof(*p_hwfn->mcp_info), GFP_KERNEL);
fe56b9e6
YM		 151 if (!p_hwfn->mcp_info)
152 goto err;
153 p_info = p_hwfn->mcp_info;
154
155 if (qed_load_mcp_offsets(p_hwfn, p_ptt) != 0) {
156 DP_NOTICE(p_hwfn, "MCP is not initialized\n");
157 /* Do not free mcp_info here, since public_base indicate that
158 * the MCP is not initialized
159 */
160 return 0;
161 }
162
163 size = MFW_DRV_MSG_MAX_DWORDS(p_info->mfw_mb_length) * sizeof(u32);
60fffb3b 164 p_info->mfw_mb_cur = kzalloc(size, GFP_KERNEL);
83aeb933 165 p_info->mfw_mb_shadow = kzalloc(size, GFP_KERNEL);
fe56b9e6
YM		 166 if (!p_info->mfw_mb_shadow || !p_info->mfw_mb_addr)
167 goto err;
168
5529bad9
TT		 169 /* Initialize the MFW spinlock */
170 spin_lock_init(&p_info->lock);
fe56b9e6
YM		 171
172 return 0;
173
174err:
fe56b9e6
YM		 175 qed_mcp_free(p_hwfn);
176 return -ENOMEM;
177}
178
5529bad9
TT		 179/* Locks the MFW mailbox of a PF to ensure a single access.
180 * The lock is achieved in most cases by holding a spinlock, causing other
181 * threads to wait till a previous access is done.
182 * In some cases (currently when a [UN]LOAD_REQ commands are sent), the single
183 * access is achieved by setting a blocking flag, which will fail other
184 * competing contexts to send their mailboxes.
185 */
1a635e48 186static int qed_mcp_mb_lock(struct qed_hwfn *p_hwfn, u32 cmd)
5529bad9
TT		 187{
188 spin_lock_bh(&p_hwfn->mcp_info->lock);
189
190 /* The spinlock shouldn't be acquired when the mailbox command is
191 * [UN]LOAD_REQ, since the engine is locked by the MFW, and a parallel
192 * pending [UN]LOAD_REQ command of another PF together with a spinlock
193 * (i.e. interrupts are disabled) - can lead to a deadlock.
194 * It is assumed that for a single PF, no other mailbox commands can be
195 * sent from another context while sending LOAD_REQ, and that any
196 * parallel commands to UNLOAD_REQ can be cancelled.
197 */
198 if (cmd == DRV_MSG_CODE_LOAD_DONE || cmd == DRV_MSG_CODE_UNLOAD_DONE)
199 p_hwfn->mcp_info->block_mb_sending = false;
200
201 if (p_hwfn->mcp_info->block_mb_sending) {
202 DP_NOTICE(p_hwfn,
203 "Trying to send a MFW mailbox command [0x%x] in parallel to [UN]LOAD_REQ. Aborting.\n",
204 cmd);
205 spin_unlock_bh(&p_hwfn->mcp_info->lock);
206 return -EBUSY;
207 }
208
209 if (cmd == DRV_MSG_CODE_LOAD_REQ || cmd == DRV_MSG_CODE_UNLOAD_REQ) {
210 p_hwfn->mcp_info->block_mb_sending = true;
211 spin_unlock_bh(&p_hwfn->mcp_info->lock);
212 }
213
214 return 0;
215}
216
1a635e48 217static void qed_mcp_mb_unlock(struct qed_hwfn *p_hwfn, u32 cmd)
5529bad9
TT		 218{
219 if (cmd != DRV_MSG_CODE_LOAD_REQ && cmd != DRV_MSG_CODE_UNLOAD_REQ)
220 spin_unlock_bh(&p_hwfn->mcp_info->lock);
221}
222
1a635e48 223int qed_mcp_reset(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
fe56b9e6
YM		 224{
225 u32 seq = ++p_hwfn->mcp_info->drv_mb_seq;
226 u8 delay = CHIP_MCP_RESP_ITER_US;
227 u32 org_mcp_reset_seq, cnt = 0;
228 int rc = 0;
229
5529bad9
TT		 230 /* Ensure that only a single thread is accessing the mailbox at a
231 * certain time.
232 */
233 rc = qed_mcp_mb_lock(p_hwfn, DRV_MSG_CODE_MCP_RESET);
234 if (rc != 0)
235 return rc;
236
fe56b9e6
YM		 237 /* Set drv command along with the updated sequence */
238 org_mcp_reset_seq = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
239 DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header,
240 (DRV_MSG_CODE_MCP_RESET | seq));
241
242 do {
243 /* Wait for MFW response */
244 udelay(delay);
245 /* Give the FW up to 500 second (50*1000*10usec) */
246 } while ((org_mcp_reset_seq == qed_rd(p_hwfn, p_ptt,
247 MISCS_REG_GENERIC_POR_0)) &&
248 (cnt++ < QED_MCP_RESET_RETRIES));
249
250 if (org_mcp_reset_seq !=
251 qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) {
252 DP_VERBOSE(p_hwfn, QED_MSG_SP,
253 "MCP was reset after %d usec\n", cnt * delay);
254 } else {
255 DP_ERR(p_hwfn, "Failed to reset MCP\n");
256 rc = -EAGAIN;
257 }
258
5529bad9
TT		 259 qed_mcp_mb_unlock(p_hwfn, DRV_MSG_CODE_MCP_RESET);
260
fe56b9e6
YM		 261 return rc;
262}
263
264static int qed_do_mcp_cmd(struct qed_hwfn *p_hwfn,
265 struct qed_ptt *p_ptt,
266 u32 cmd,
267 u32 param,
268 u32 *o_mcp_resp,
269 u32 *o_mcp_param)
270{
271 u8 delay = CHIP_MCP_RESP_ITER_US;
272 u32 seq, cnt = 1, actual_mb_seq;
273 int rc = 0;
274
275 /* Get actual driver mailbox sequence */
276 actual_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) &
277 DRV_MSG_SEQ_NUMBER_MASK;
278
279 /* Use MCP history register to check if MCP reset occurred between
280 * init time and now.
281 */
282 if (p_hwfn->mcp_info->mcp_hist !=
283 qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) {
284 DP_VERBOSE(p_hwfn, QED_MSG_SP, "Rereading MCP offsets\n");
285 qed_load_mcp_offsets(p_hwfn, p_ptt);
286 qed_mcp_cmd_port_init(p_hwfn, p_ptt);
287 }
288 seq = ++p_hwfn->mcp_info->drv_mb_seq;
289
290 /* Set drv param */
291 DRV_MB_WR(p_hwfn, p_ptt, drv_mb_param, param);
292
293 /* Set drv command along with the updated sequence */
294 DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (cmd | seq));
295
296 DP_VERBOSE(p_hwfn, QED_MSG_SP,
297 "wrote command (%x) to MFW MB param 0x%08x\n",
298 (cmd | seq), param);
299
300 do {
301 /* Wait for MFW response */
302 udelay(delay);
303 *o_mcp_resp = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_header);
304
305 /* Give the FW up to 5 second (500*10ms) */
306 } while ((seq != (*o_mcp_resp & FW_MSG_SEQ_NUMBER_MASK)) &&
307 (cnt++ < QED_DRV_MB_MAX_RETRIES));
308
309 DP_VERBOSE(p_hwfn, QED_MSG_SP,
310 "[after %d ms] read (%x) seq is (%x) from FW MB\n",
311 cnt * delay, *o_mcp_resp, seq);
312
313 /* Is this a reply to our command? */
314 if (seq == (*o_mcp_resp & FW_MSG_SEQ_NUMBER_MASK)) {
315 *o_mcp_resp &= FW_MSG_CODE_MASK;
316 /* Get the MCP param */
317 *o_mcp_param = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_param);
318 } else {
319 /* FW BUG! */
525ef5c0
YM		 320 DP_ERR(p_hwfn, "MFW failed to respond [cmd 0x%x param 0x%x]\n",
321 cmd, param);
fe56b9e6
YM		 322 *o_mcp_resp = 0;
323 rc = -EAGAIN;
324 }
325 return rc;
326}
327
5529bad9
TT		 328static int qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn,
329 struct qed_ptt *p_ptt,
330 struct qed_mcp_mb_params *p_mb_params)
fe56b9e6 331{
5529bad9 332 u32 union_data_addr;
14d39648 333
5529bad9 334 int rc;
fe56b9e6
YM		 335
336 /* MCP not initialized */
337 if (!qed_mcp_is_init(p_hwfn)) {
525ef5c0 338 DP_NOTICE(p_hwfn, "MFW is not initialized!\n");
fe56b9e6
YM		 339 return -EBUSY;
340 }
341
5529bad9
TT		 342 union_data_addr = p_hwfn->mcp_info->drv_mb_addr +
343 offsetof(struct public_drv_mb, union_data);
344
345 /* Ensure that only a single thread is accessing the mailbox at a
346 * certain time.
fe56b9e6 347 */
5529bad9
TT		 348 rc = qed_mcp_mb_lock(p_hwfn, p_mb_params->cmd);
349 if (rc)
350 return rc;
351
352 if (p_mb_params->p_data_src != NULL)
353 qed_memcpy_to(p_hwfn, p_ptt, union_data_addr,
354 p_mb_params->p_data_src,
355 sizeof(*p_mb_params->p_data_src));
356
357 rc = qed_do_mcp_cmd(p_hwfn, p_ptt, p_mb_params->cmd,
358 p_mb_params->param, &p_mb_params->mcp_resp,
359 &p_mb_params->mcp_param);
360
361 if (p_mb_params->p_data_dst != NULL)
362 qed_memcpy_from(p_hwfn, p_ptt, p_mb_params->p_data_dst,
363 union_data_addr,
364 sizeof(*p_mb_params->p_data_dst));
365
366 qed_mcp_mb_unlock(p_hwfn, p_mb_params->cmd);
fe56b9e6
YM		 367
368 return rc;
369}
370
5529bad9
TT		 371int qed_mcp_cmd(struct qed_hwfn *p_hwfn,
372 struct qed_ptt *p_ptt,
373 u32 cmd,
374 u32 param,
375 u32 *o_mcp_resp,
376 u32 *o_mcp_param)
fe56b9e6 377{
5529bad9 378 struct qed_mcp_mb_params mb_params;
14d39648 379 union drv_union_data data_src;
5529bad9
TT		 380 int rc;
381
382 memset(&mb_params, 0, sizeof(mb_params));
14d39648 383 memset(&data_src, 0, sizeof(data_src));
5529bad9
TT		 384 mb_params.cmd = cmd;
385 mb_params.param = param;
14d39648
MY		 386
387 /* In case of UNLOAD_DONE, set the primary MAC */
388 if ((cmd == DRV_MSG_CODE_UNLOAD_DONE) &&
389 (p_hwfn->cdev->wol_config == QED_OV_WOL_ENABLED)) {
390 u8 *p_mac = p_hwfn->cdev->wol_mac;
391
392 data_src.wol_mac.mac_upper = p_mac[0] << 8 | p_mac[1];
393 data_src.wol_mac.mac_lower = p_mac[2] << 24 | p_mac[3] << 16 |
394 p_mac[4] << 8 | p_mac[5];
395
396 DP_VERBOSE(p_hwfn,
397 (QED_MSG_SP | NETIF_MSG_IFDOWN),
398 "Setting WoL MAC: %pM --> [%08x,%08x]\n",
399 p_mac, data_src.wol_mac.mac_upper,
400 data_src.wol_mac.mac_lower);
401
402 mb_params.p_data_src = &data_src;
403 }
404
5529bad9
TT		 405 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
406 if (rc)
407 return rc;
408
409 *o_mcp_resp = mb_params.mcp_resp;
410 *o_mcp_param = mb_params.mcp_param;
fe56b9e6 411
5529bad9 412 return 0;
fe56b9e6
YM		 413}
414
4102426f
TT		 415int qed_mcp_nvm_rd_cmd(struct qed_hwfn *p_hwfn,
416 struct qed_ptt *p_ptt,
417 u32 cmd,
418 u32 param,
419 u32 *o_mcp_resp,
420 u32 *o_mcp_param, u32 *o_txn_size, u32 *o_buf)
421{
422 struct qed_mcp_mb_params mb_params;
423 union drv_union_data union_data;
424 int rc;
425
426 memset(&mb_params, 0, sizeof(mb_params));
427 mb_params.cmd = cmd;
428 mb_params.param = param;
429 mb_params.p_data_dst = &union_data;
430 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
431 if (rc)
432 return rc;
433
434 *o_mcp_resp = mb_params.mcp_resp;
435 *o_mcp_param = mb_params.mcp_param;
436
437 *o_txn_size = *o_mcp_param;
438 memcpy(o_buf, &union_data.raw_data, *o_txn_size);
439
440 return 0;
441}
442
fe56b9e6 443int qed_mcp_load_req(struct qed_hwfn *p_hwfn,
1a635e48 444 struct qed_ptt *p_ptt, u32 *p_load_code)
fe56b9e6
YM		 445{
446 struct qed_dev *cdev = p_hwfn->cdev;
5529bad9
TT		 447 struct qed_mcp_mb_params mb_params;
448 union drv_union_data union_data;
fe56b9e6
YM		 449 int rc;
450
5529bad9 451 memset(&mb_params, 0, sizeof(mb_params));
fe56b9e6 452 /* Load Request */
5529bad9
TT		 453 mb_params.cmd = DRV_MSG_CODE_LOAD_REQ;
454 mb_params.param = PDA_COMP | DRV_ID_MCP_HSI_VER_CURRENT |
455 cdev->drv_type;
456 memcpy(&union_data.ver_str, cdev->ver_str, MCP_DRV_VER_STR_SIZE);
457 mb_params.p_data_src = &union_data;
458 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
fe56b9e6
YM		 459
460 /* if mcp fails to respond we must abort */
461 if (rc) {
462 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
463 return rc;
464 }
465
5529bad9
TT		 466 *p_load_code = mb_params.mcp_resp;
467
fe56b9e6
YM		 468 /* If MFW refused (e.g. other port is in diagnostic mode) we
469 * must abort. This can happen in the following cases:
470 * - Other port is in diagnostic mode
471 * - Previously loaded function on the engine is not compliant with
472 * the requester.
473 * - MFW cannot cope with the requester's DRV_MFW_HSI_VERSION.
474 * -
475 */
476 if (!(*p_load_code) ||
477 ((*p_load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED_HSI) ||
478 ((*p_load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED_PDA) ||
479 ((*p_load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED_DIAG)) {
480 DP_ERR(p_hwfn, "MCP refused load request, aborting\n");
481 return -EBUSY;
482 }
483
484 return 0;
485}
486
0b55e27d
YM		 487static void qed_mcp_handle_vf_flr(struct qed_hwfn *p_hwfn,
488 struct qed_ptt *p_ptt)
489{
490 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
491 PUBLIC_PATH);
492 u32 mfw_path_offsize = qed_rd(p_hwfn, p_ptt, addr);
493 u32 path_addr = SECTION_ADDR(mfw_path_offsize,
494 QED_PATH_ID(p_hwfn));
495 u32 disabled_vfs[VF_MAX_STATIC / 32];
496 int i;
497
498 DP_VERBOSE(p_hwfn,
499 QED_MSG_SP,
500 "Reading Disabled VF information from [offset %08x], path_addr %08x\n",
501 mfw_path_offsize, path_addr);
502
503 for (i = 0; i < (VF_MAX_STATIC / 32); i++) {
504 disabled_vfs[i] = qed_rd(p_hwfn, p_ptt,
505 path_addr +
506 offsetof(struct public_path,
507 mcp_vf_disabled) +
508 sizeof(u32) * i);
509 DP_VERBOSE(p_hwfn, (QED_MSG_SP | QED_MSG_IOV),
510 "FLR-ed VFs [%08x,...,%08x] - %08x\n",
511 i * 32, (i + 1) * 32 - 1, disabled_vfs[i]);
512 }
513
514 if (qed_iov_mark_vf_flr(p_hwfn, disabled_vfs))
515 qed_schedule_iov(p_hwfn, QED_IOV_WQ_FLR_FLAG);
516}
517
518int qed_mcp_ack_vf_flr(struct qed_hwfn *p_hwfn,
519 struct qed_ptt *p_ptt, u32 *vfs_to_ack)
520{
521 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
522 PUBLIC_FUNC);
523 u32 mfw_func_offsize = qed_rd(p_hwfn, p_ptt, addr);
524 u32 func_addr = SECTION_ADDR(mfw_func_offsize,
525 MCP_PF_ID(p_hwfn));
526 struct qed_mcp_mb_params mb_params;
527 union drv_union_data union_data;
528 int rc;
529 int i;
530
531 for (i = 0; i < (VF_MAX_STATIC / 32); i++)
532 DP_VERBOSE(p_hwfn, (QED_MSG_SP | QED_MSG_IOV),
533 "Acking VFs [%08x,...,%08x] - %08x\n",
534 i * 32, (i + 1) * 32 - 1, vfs_to_ack[i]);
535
536 memset(&mb_params, 0, sizeof(mb_params));
537 mb_params.cmd = DRV_MSG_CODE_VF_DISABLED_DONE;
538 memcpy(&union_data.ack_vf_disabled, vfs_to_ack, VF_MAX_STATIC / 8);
539 mb_params.p_data_src = &union_data;
540 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
541 if (rc) {
542 DP_NOTICE(p_hwfn, "Failed to pass ACK for VF flr to MFW\n");
543 return -EBUSY;
544 }
545
546 /* Clear the ACK bits */
547 for (i = 0; i < (VF_MAX_STATIC / 32); i++)
548 qed_wr(p_hwfn, p_ptt,
549 func_addr +
550 offsetof(struct public_func, drv_ack_vf_disabled) +
551 i * sizeof(u32), 0);
552
553 return rc;
554}
555
334c03b5
ZN		 556static void qed_mcp_handle_transceiver_change(struct qed_hwfn *p_hwfn,
557 struct qed_ptt *p_ptt)
558{
559 u32 transceiver_state;
560
561 transceiver_state = qed_rd(p_hwfn, p_ptt,
562 p_hwfn->mcp_info->port_addr +
563 offsetof(struct public_port,
564 transceiver_data));
565
566 DP_VERBOSE(p_hwfn,
567 (NETIF_MSG_HW | QED_MSG_SP),
568 "Received transceiver state update [0x%08x] from mfw [Addr 0x%x]\n",
569 transceiver_state,
570 (u32)(p_hwfn->mcp_info->port_addr +
1a635e48 571 offsetof(struct public_port, transceiver_data)));
334c03b5
ZN		 572
573 transceiver_state = GET_FIELD(transceiver_state,
351a4ded 574 ETH_TRANSCEIVER_STATE);
334c03b5 575
351a4ded 576 if (transceiver_state == ETH_TRANSCEIVER_STATE_PRESENT)
334c03b5
ZN		 577 DP_NOTICE(p_hwfn, "Transceiver is present.\n");
578 else
579 DP_NOTICE(p_hwfn, "Transceiver is unplugged.\n");
580}
581
cc875c2e 582static void qed_mcp_handle_link_change(struct qed_hwfn *p_hwfn,
1a635e48 583 struct qed_ptt *p_ptt, bool b_reset)
cc875c2e
YM		 584{
585 struct qed_mcp_link_state *p_link;
a64b02d5 586 u8 max_bw, min_bw;
cc875c2e
YM		 587 u32 status = 0;
588
589 p_link = &p_hwfn->mcp_info->link_output;
590 memset(p_link, 0, sizeof(*p_link));
591 if (!b_reset) {
592 status = qed_rd(p_hwfn, p_ptt,
593 p_hwfn->mcp_info->port_addr +
594 offsetof(struct public_port, link_status));
595 DP_VERBOSE(p_hwfn, (NETIF_MSG_LINK | QED_MSG_SP),
596 "Received link update [0x%08x] from mfw [Addr 0x%x]\n",
597 status,
598 (u32)(p_hwfn->mcp_info->port_addr +
1a635e48 599 offsetof(struct public_port, link_status)));
cc875c2e
YM		 600 } else {
601 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
602 "Resetting link indications\n");
603 return;
604 }
605
fc916ff2
SRK		 606 if (p_hwfn->b_drv_link_init)
607 p_link->link_up = !!(status & LINK_STATUS_LINK_UP);
608 else
609 p_link->link_up = false;
cc875c2e
YM		 610
611 p_link->full_duplex = true;
612 switch ((status & LINK_STATUS_SPEED_AND_DUPLEX_MASK)) {
613 case LINK_STATUS_SPEED_AND_DUPLEX_100G:
614 p_link->speed = 100000;
615 break;
616 case LINK_STATUS_SPEED_AND_DUPLEX_50G:
617 p_link->speed = 50000;
618 break;
619 case LINK_STATUS_SPEED_AND_DUPLEX_40G:
620 p_link->speed = 40000;
621 break;
622 case LINK_STATUS_SPEED_AND_DUPLEX_25G:
623 p_link->speed = 25000;
624 break;
625 case LINK_STATUS_SPEED_AND_DUPLEX_20G:
626 p_link->speed = 20000;
627 break;
628 case LINK_STATUS_SPEED_AND_DUPLEX_10G:
629 p_link->speed = 10000;
630 break;
631 case LINK_STATUS_SPEED_AND_DUPLEX_1000THD:
632 p_link->full_duplex = false;
633 /* Fall-through */
634 case LINK_STATUS_SPEED_AND_DUPLEX_1000TFD:
635 p_link->speed = 1000;
636 break;
637 default:
638 p_link->speed = 0;
639 }
640
4b01e519
MC		 641 if (p_link->link_up && p_link->speed)
642 p_link->line_speed = p_link->speed;
643 else
644 p_link->line_speed = 0;
645
646 max_bw = p_hwfn->mcp_info->func_info.bandwidth_max;
a64b02d5 647 min_bw = p_hwfn->mcp_info->func_info.bandwidth_min;
4b01e519 648
a64b02d5 649 /* Max bandwidth configuration */
4b01e519 650 __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt, p_link, max_bw);
cc875c2e 651
a64b02d5
MC		 652 /* Min bandwidth configuration */
653 __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt, p_link, min_bw);
654 qed_configure_vp_wfq_on_link_change(p_hwfn->cdev, p_link->min_pf_rate);
655
cc875c2e
YM		 656 p_link->an = !!(status & LINK_STATUS_AUTO_NEGOTIATE_ENABLED);
657 p_link->an_complete = !!(status &
658 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE);
659 p_link->parallel_detection = !!(status &
660 LINK_STATUS_PARALLEL_DETECTION_USED);
661 p_link->pfc_enabled = !!(status & LINK_STATUS_PFC_ENABLED);
662
663 p_link->partner_adv_speed |=
664 (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) ?
665 QED_LINK_PARTNER_SPEED_1G_FD : 0;
666 p_link->partner_adv_speed |=
667 (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) ?
668 QED_LINK_PARTNER_SPEED_1G_HD : 0;
669 p_link->partner_adv_speed |=
670 (status & LINK_STATUS_LINK_PARTNER_10G_CAPABLE) ?
671 QED_LINK_PARTNER_SPEED_10G : 0;
672 p_link->partner_adv_speed |=
673 (status & LINK_STATUS_LINK_PARTNER_20G_CAPABLE) ?
674 QED_LINK_PARTNER_SPEED_20G : 0;
054c67d1
SRK		 675 p_link->partner_adv_speed |=
676 (status & LINK_STATUS_LINK_PARTNER_25G_CAPABLE) ?
677 QED_LINK_PARTNER_SPEED_25G : 0;
cc875c2e
YM		 678 p_link->partner_adv_speed |=
679 (status & LINK_STATUS_LINK_PARTNER_40G_CAPABLE) ?
680 QED_LINK_PARTNER_SPEED_40G : 0;
681 p_link->partner_adv_speed |=
682 (status & LINK_STATUS_LINK_PARTNER_50G_CAPABLE) ?
683 QED_LINK_PARTNER_SPEED_50G : 0;
684 p_link->partner_adv_speed |=
685 (status & LINK_STATUS_LINK_PARTNER_100G_CAPABLE) ?
686 QED_LINK_PARTNER_SPEED_100G : 0;
687
688 p_link->partner_tx_flow_ctrl_en =
689 !!(status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED);
690 p_link->partner_rx_flow_ctrl_en =
691 !!(status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED);
692
693 switch (status & LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK) {
694 case LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE:
695 p_link->partner_adv_pause = QED_LINK_PARTNER_SYMMETRIC_PAUSE;
696 break;
697 case LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE:
698 p_link->partner_adv_pause = QED_LINK_PARTNER_ASYMMETRIC_PAUSE;
699 break;
700 case LINK_STATUS_LINK_PARTNER_BOTH_PAUSE:
701 p_link->partner_adv_pause = QED_LINK_PARTNER_BOTH_PAUSE;
702 break;
703 default:
704 p_link->partner_adv_pause = 0;
705 }
706
707 p_link->sfp_tx_fault = !!(status & LINK_STATUS_SFP_TX_FAULT);
708
709 qed_link_update(p_hwfn);
710}
711
351a4ded 712int qed_mcp_set_link(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, bool b_up)
cc875c2e
YM		 713{
714 struct qed_mcp_link_params *params = &p_hwfn->mcp_info->link_input;
5529bad9
TT		 715 struct qed_mcp_mb_params mb_params;
716 union drv_union_data union_data;
351a4ded 717 struct eth_phy_cfg *phy_cfg;
cc875c2e 718 int rc = 0;
5529bad9 719 u32 cmd;
cc875c2e
YM		 720
721 /* Set the shmem configuration according to params */
5529bad9
TT		 722 phy_cfg = &union_data.drv_phy_cfg;
723 memset(phy_cfg, 0, sizeof(*phy_cfg));
cc875c2e
YM		 724 cmd = b_up ? DRV_MSG_CODE_INIT_PHY : DRV_MSG_CODE_LINK_RESET;
725 if (!params->speed.autoneg)
5529bad9 726 phy_cfg->speed = params->speed.forced_speed;
351a4ded
YM		 727 phy_cfg->pause |= (params->pause.autoneg) ? ETH_PAUSE_AUTONEG : 0;
728 phy_cfg->pause |= (params->pause.forced_rx) ? ETH_PAUSE_RX : 0;
729 phy_cfg->pause |= (params->pause.forced_tx) ? ETH_PAUSE_TX : 0;
5529bad9
TT		 730 phy_cfg->adv_speed = params->speed.advertised_speeds;
731 phy_cfg->loopback_mode = params->loopback_mode;
cc875c2e 732
fc916ff2
SRK		 733 p_hwfn->b_drv_link_init = b_up;
734
cc875c2e
YM		 735 if (b_up) {
736 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
737 "Configuring Link: Speed 0x%08x, Pause 0x%08x, adv_speed 0x%08x, loopback 0x%08x, features 0x%08x\n",
5529bad9
TT		 738 phy_cfg->speed,
739 phy_cfg->pause,
740 phy_cfg->adv_speed,
741 phy_cfg->loopback_mode,
742 phy_cfg->feature_config_flags);
cc875c2e
YM		 743 } else {
744 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
745 "Resetting link\n");
746 }
747
5529bad9
TT		 748 memset(&mb_params, 0, sizeof(mb_params));
749 mb_params.cmd = cmd;
750 mb_params.p_data_src = &union_data;
751 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
cc875c2e
YM		 752
753 /* if mcp fails to respond we must abort */
754 if (rc) {
755 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
756 return rc;
757 }
758
759 /* Reset the link status if needed */
760 if (!b_up)
761 qed_mcp_handle_link_change(p_hwfn, p_ptt, true);
762
763 return 0;
764}
765
6c754246
SRK		 766static void qed_mcp_send_protocol_stats(struct qed_hwfn *p_hwfn,
767 struct qed_ptt *p_ptt,
768 enum MFW_DRV_MSG_TYPE type)
769{
770 enum qed_mcp_protocol_type stats_type;
771 union qed_mcp_protocol_stats stats;
772 struct qed_mcp_mb_params mb_params;
773 union drv_union_data union_data;
774 u32 hsi_param;
775
776 switch (type) {
777 case MFW_DRV_MSG_GET_LAN_STATS:
778 stats_type = QED_MCP_LAN_STATS;
779 hsi_param = DRV_MSG_CODE_STATS_TYPE_LAN;
780 break;
781 case MFW_DRV_MSG_GET_FCOE_STATS:
782 stats_type = QED_MCP_FCOE_STATS;
783 hsi_param = DRV_MSG_CODE_STATS_TYPE_FCOE;
784 break;
785 case MFW_DRV_MSG_GET_ISCSI_STATS:
786 stats_type = QED_MCP_ISCSI_STATS;
787 hsi_param = DRV_MSG_CODE_STATS_TYPE_ISCSI;
788 break;
789 case MFW_DRV_MSG_GET_RDMA_STATS:
790 stats_type = QED_MCP_RDMA_STATS;
791 hsi_param = DRV_MSG_CODE_STATS_TYPE_RDMA;
792 break;
793 default:
794 DP_NOTICE(p_hwfn, "Invalid protocol type %d\n", type);
795 return;
796 }
797
798 qed_get_protocol_stats(p_hwfn->cdev, stats_type, &stats);
799
800 memset(&mb_params, 0, sizeof(mb_params));
801 mb_params.cmd = DRV_MSG_CODE_GET_STATS;
802 mb_params.param = hsi_param;
803 memcpy(&union_data, &stats, sizeof(stats));
804 mb_params.p_data_src = &union_data;
805 qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
806}
807
4b01e519
MC		 808static void qed_read_pf_bandwidth(struct qed_hwfn *p_hwfn,
809 struct public_func *p_shmem_info)
810{
811 struct qed_mcp_function_info *p_info;
812
813 p_info = &p_hwfn->mcp_info->func_info;
814
815 p_info->bandwidth_min = (p_shmem_info->config &
816 FUNC_MF_CFG_MIN_BW_MASK) >>
817 FUNC_MF_CFG_MIN_BW_SHIFT;
818 if (p_info->bandwidth_min < 1 || p_info->bandwidth_min > 100) {
819 DP_INFO(p_hwfn,
820 "bandwidth minimum out of bounds [%02x]. Set to 1\n",
821 p_info->bandwidth_min);
822 p_info->bandwidth_min = 1;
823 }
824
825 p_info->bandwidth_max = (p_shmem_info->config &
826 FUNC_MF_CFG_MAX_BW_MASK) >>
827 FUNC_MF_CFG_MAX_BW_SHIFT;
828 if (p_info->bandwidth_max < 1 || p_info->bandwidth_max > 100) {
829 DP_INFO(p_hwfn,
830 "bandwidth maximum out of bounds [%02x]. Set to 100\n",
831 p_info->bandwidth_max);
832 p_info->bandwidth_max = 100;
833 }
834}
835
836static u32 qed_mcp_get_shmem_func(struct qed_hwfn *p_hwfn,
837 struct qed_ptt *p_ptt,
1a635e48 838 struct public_func *p_data, int pfid)
4b01e519
MC		 839{
840 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
841 PUBLIC_FUNC);
842 u32 mfw_path_offsize = qed_rd(p_hwfn, p_ptt, addr);
843 u32 func_addr = SECTION_ADDR(mfw_path_offsize, pfid);
844 u32 i, size;
845
846 memset(p_data, 0, sizeof(*p_data));
847
1a635e48 848 size = min_t(u32, sizeof(*p_data), QED_SECTION_SIZE(mfw_path_offsize));
4b01e519
MC		 849 for (i = 0; i < size / sizeof(u32); i++)
850 ((u32 *)p_data)[i] = qed_rd(p_hwfn, p_ptt,
851 func_addr + (i << 2));
852 return size;
853}
854
1a635e48 855static void qed_mcp_update_bw(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
4b01e519
MC		 856{
857 struct qed_mcp_function_info *p_info;
858 struct public_func shmem_info;
859 u32 resp = 0, param = 0;
860
1a635e48 861 qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
4b01e519
MC		 862
863 qed_read_pf_bandwidth(p_hwfn, &shmem_info);
864
865 p_info = &p_hwfn->mcp_info->func_info;
866
a64b02d5 867 qed_configure_pf_min_bandwidth(p_hwfn->cdev, p_info->bandwidth_min);
4b01e519
MC		 868 qed_configure_pf_max_bandwidth(p_hwfn->cdev, p_info->bandwidth_max);
869
870 /* Acknowledge the MFW */
871 qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BW_UPDATE_ACK, 0, &resp,
872 &param);
873}
874
cc875c2e
YM		 875int qed_mcp_handle_events(struct qed_hwfn *p_hwfn,
876 struct qed_ptt *p_ptt)
877{
878 struct qed_mcp_info *info = p_hwfn->mcp_info;
879 int rc = 0;
880 bool found = false;
881 u16 i;
882
883 DP_VERBOSE(p_hwfn, QED_MSG_SP, "Received message from MFW\n");
884
885 /* Read Messages from MFW */
886 qed_mcp_read_mb(p_hwfn, p_ptt);
887
888 /* Compare current messages to old ones */
889 for (i = 0; i < info->mfw_mb_length; i++) {
890 if (info->mfw_mb_cur[i] == info->mfw_mb_shadow[i])
891 continue;
892
893 found = true;
894
895 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
896 "Msg [%d] - old CMD 0x%02x, new CMD 0x%02x\n",
897 i, info->mfw_mb_shadow[i], info->mfw_mb_cur[i]);
898
899 switch (i) {
900 case MFW_DRV_MSG_LINK_CHANGE:
901 qed_mcp_handle_link_change(p_hwfn, p_ptt, false);
902 break;
0b55e27d
YM		 903 case MFW_DRV_MSG_VF_DISABLED:
904 qed_mcp_handle_vf_flr(p_hwfn, p_ptt);
905 break;
39651abd
SRK		 906 case MFW_DRV_MSG_LLDP_DATA_UPDATED:
907 qed_dcbx_mib_update_event(p_hwfn, p_ptt,
908 QED_DCBX_REMOTE_LLDP_MIB);
909 break;
910 case MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED:
911 qed_dcbx_mib_update_event(p_hwfn, p_ptt,
912 QED_DCBX_REMOTE_MIB);
913 break;
914 case MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED:
915 qed_dcbx_mib_update_event(p_hwfn, p_ptt,
916 QED_DCBX_OPERATIONAL_MIB);
917 break;
334c03b5
ZN		 918 case MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE:
919 qed_mcp_handle_transceiver_change(p_hwfn, p_ptt);
920 break;
6c754246
SRK		 921 case MFW_DRV_MSG_GET_LAN_STATS:
922 case MFW_DRV_MSG_GET_FCOE_STATS:
923 case MFW_DRV_MSG_GET_ISCSI_STATS:
924 case MFW_DRV_MSG_GET_RDMA_STATS:
925 qed_mcp_send_protocol_stats(p_hwfn, p_ptt, i);
926 break;
4b01e519
MC		 927 case MFW_DRV_MSG_BW_UPDATE:
928 qed_mcp_update_bw(p_hwfn, p_ptt);
929 break;
cc875c2e
YM		 930 default:
931 DP_NOTICE(p_hwfn, "Unimplemented MFW message %d\n", i);
932 rc = -EINVAL;
933 }
934 }
935
936 /* ACK everything */
937 for (i = 0; i < MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length); i++) {
938 __be32 val = cpu_to_be32(((u32 *)info->mfw_mb_cur)[i]);
939
940 /* MFW expect answer in BE, so we force write in that format */
941 qed_wr(p_hwfn, p_ptt,
942 info->mfw_mb_addr + sizeof(u32) +
943 MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length) *
944 sizeof(u32) + i * sizeof(u32),
945 (__force u32)val);
946 }
947
948 if (!found) {
949 DP_NOTICE(p_hwfn,
950 "Received an MFW message indication but no new message!\n");
951 rc = -EINVAL;
952 }
953
954 /* Copy the new mfw messages into the shadow */
955 memcpy(info->mfw_mb_shadow, info->mfw_mb_cur, info->mfw_mb_length);
956
957 return rc;
958}
959
1408cc1f
YM		 960int qed_mcp_get_mfw_ver(struct qed_hwfn *p_hwfn,
961 struct qed_ptt *p_ptt,
962 u32 *p_mfw_ver, u32 *p_running_bundle_id)
fe56b9e6 963{
fe56b9e6
YM		 964 u32 global_offsize;
965
1408cc1f
YM		 966 if (IS_VF(p_hwfn->cdev)) {
967 if (p_hwfn->vf_iov_info) {
968 struct pfvf_acquire_resp_tlv *p_resp;
969
970 p_resp = &p_hwfn->vf_iov_info->acquire_resp;
971 *p_mfw_ver = p_resp->pfdev_info.mfw_ver;
972 return 0;
973 } else {
974 DP_VERBOSE(p_hwfn,
975 QED_MSG_IOV,
976 "VF requested MFW version prior to ACQUIRE\n");
977 return -EINVAL;
978 }
979 }
fe56b9e6
YM		 980
981 global_offsize = qed_rd(p_hwfn, p_ptt,
1408cc1f
YM		 982 SECTION_OFFSIZE_ADDR(p_hwfn->
983 mcp_info->public_base,
fe56b9e6 984 PUBLIC_GLOBAL));
1408cc1f
YM		 985 *p_mfw_ver =
986 qed_rd(p_hwfn, p_ptt,
987 SECTION_ADDR(global_offsize,
988 0) + offsetof(struct public_global, mfw_ver));
989
990 if (p_running_bundle_id != NULL) {
991 *p_running_bundle_id = qed_rd(p_hwfn, p_ptt,
992 SECTION_ADDR(global_offsize, 0) +
993 offsetof(struct public_global,
994 running_bundle_id));
995 }
fe56b9e6
YM		 996
997 return 0;
998}
999
1a635e48 1000int qed_mcp_get_media_type(struct qed_dev *cdev, u32 *p_media_type)
cc875c2e
YM		 1001{
1002 struct qed_hwfn *p_hwfn = &cdev->hwfns[0];
1003 struct qed_ptt *p_ptt;
1004
1408cc1f
YM		 1005 if (IS_VF(cdev))
1006 return -EINVAL;
1007
cc875c2e 1008 if (!qed_mcp_is_init(p_hwfn)) {
525ef5c0 1009 DP_NOTICE(p_hwfn, "MFW is not initialized!\n");
cc875c2e
YM		 1010 return -EBUSY;
1011 }
1012
1013 *p_media_type = MEDIA_UNSPECIFIED;
1014
1015 p_ptt = qed_ptt_acquire(p_hwfn);
1016 if (!p_ptt)
1017 return -EBUSY;
1018
1019 *p_media_type = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
1020 offsetof(struct public_port, media_type));
1021
1022 qed_ptt_release(p_hwfn, p_ptt);
1023
1024 return 0;
1025}
1026
6927e826
MY		 1027/* Old MFW has a global configuration for all PFs regarding RDMA support */
1028static void
1029qed_mcp_get_shmem_proto_legacy(struct qed_hwfn *p_hwfn,
1030 enum qed_pci_personality *p_proto)
1031{
1032 /* There wasn't ever a legacy MFW that published iwarp.
1033 * So at this point, this is either plain l2 or RoCE.
1034 */
1035 if (test_bit(QED_DEV_CAP_ROCE, &p_hwfn->hw_info.device_capabilities))
1036 *p_proto = QED_PCI_ETH_ROCE;
1037 else
1038 *p_proto = QED_PCI_ETH;
1039
1040 DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP,
1041 "According to Legacy capabilities, L2 personality is %08x\n",
1042 (u32) *p_proto);
1043}
1044
1045static int
1046qed_mcp_get_shmem_proto_mfw(struct qed_hwfn *p_hwfn,
1047 struct qed_ptt *p_ptt,
1048 enum qed_pci_personality *p_proto)
1049{
1050 u32 resp = 0, param = 0;
1051 int rc;
1052
1053 rc = qed_mcp_cmd(p_hwfn, p_ptt,
1054 DRV_MSG_CODE_GET_PF_RDMA_PROTOCOL, 0, &resp, &param);
1055 if (rc)
1056 return rc;
1057 if (resp != FW_MSG_CODE_OK) {
1058 DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP,
1059 "MFW lacks support for command; Returns %08x\n",
1060 resp);
1061 return -EINVAL;
1062 }
1063
1064 switch (param) {
1065 case FW_MB_PARAM_GET_PF_RDMA_NONE:
1066 *p_proto = QED_PCI_ETH;
1067 break;
1068 case FW_MB_PARAM_GET_PF_RDMA_ROCE:
1069 *p_proto = QED_PCI_ETH_ROCE;
1070 break;
1071 case FW_MB_PARAM_GET_PF_RDMA_BOTH:
1072 DP_NOTICE(p_hwfn,
1073 "Current day drivers don't support RoCE & iWARP. Default to RoCE-only\n");
1074 *p_proto = QED_PCI_ETH_ROCE;
1075 break;
1076 case FW_MB_PARAM_GET_PF_RDMA_IWARP:
1077 default:
1078 DP_NOTICE(p_hwfn,
1079 "MFW answers GET_PF_RDMA_PROTOCOL but param is %08x\n",
1080 param);
1081 return -EINVAL;
1082 }
1083
1084 DP_VERBOSE(p_hwfn,
1085 NETIF_MSG_IFUP,
1086 "According to capabilities, L2 personality is %08x [resp %08x param %08x]\n",
1087 (u32) *p_proto, resp, param);
1088 return 0;
1089}
1090
fe56b9e6
YM		 1091static int
1092qed_mcp_get_shmem_proto(struct qed_hwfn *p_hwfn,
1093 struct public_func *p_info,
6927e826 1094 struct qed_ptt *p_ptt,
fe56b9e6
YM		 1095 enum qed_pci_personality *p_proto)
1096{
1097 int rc = 0;
1098
1099 switch (p_info->config & FUNC_MF_CFG_PROTOCOL_MASK) {
1100 case FUNC_MF_CFG_PROTOCOL_ETHERNET:
6927e826
MY		 1101 if (qed_mcp_get_shmem_proto_mfw(p_hwfn, p_ptt, p_proto))
1102 qed_mcp_get_shmem_proto_legacy(p_hwfn, p_proto);
c5ac9319
YM		 1103 break;
1104 case FUNC_MF_CFG_PROTOCOL_ISCSI:
1105 *p_proto = QED_PCI_ISCSI;
1106 break;
1107 case FUNC_MF_CFG_PROTOCOL_ROCE:
1108 DP_NOTICE(p_hwfn, "RoCE personality is not a valid value!\n");
6927e826 1109 /* Fallthrough */
fe56b9e6
YM		 1110 default:
1111 rc = -EINVAL;
1112 }
1113
1114 return rc;
1115}
1116
1117int qed_mcp_fill_shmem_func_info(struct qed_hwfn *p_hwfn,
1118 struct qed_ptt *p_ptt)
1119{
1120 struct qed_mcp_function_info *info;
1121 struct public_func shmem_info;
1122
1a635e48 1123 qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
fe56b9e6
YM		 1124 info = &p_hwfn->mcp_info->func_info;
1125
1126 info->pause_on_host = (shmem_info.config &
1127 FUNC_MF_CFG_PAUSE_ON_HOST_RING) ? 1 : 0;
1128
6927e826
MY		 1129 if (qed_mcp_get_shmem_proto(p_hwfn, &shmem_info, p_ptt,
1130 &info->protocol)) {
fe56b9e6
YM		 1131 DP_ERR(p_hwfn, "Unknown personality %08x\n",
1132 (u32)(shmem_info.config & FUNC_MF_CFG_PROTOCOL_MASK));
1133 return -EINVAL;
1134 }
1135
4b01e519 1136 qed_read_pf_bandwidth(p_hwfn, &shmem_info);
fe56b9e6
YM		 1137
1138 if (shmem_info.mac_upper || shmem_info.mac_lower) {
1139 info->mac[0] = (u8)(shmem_info.mac_upper >> 8);
1140 info->mac[1] = (u8)(shmem_info.mac_upper);
1141 info->mac[2] = (u8)(shmem_info.mac_lower >> 24);
1142 info->mac[3] = (u8)(shmem_info.mac_lower >> 16);
1143 info->mac[4] = (u8)(shmem_info.mac_lower >> 8);
1144 info->mac[5] = (u8)(shmem_info.mac_lower);
14d39648
MY		 1145
1146 /* Store primary MAC for later possible WoL */
1147 memcpy(&p_hwfn->cdev->wol_mac, info->mac, ETH_ALEN);
fe56b9e6
YM		 1148 } else {
1149 DP_NOTICE(p_hwfn, "MAC is 0 in shmem\n");
1150 }
1151
1152 info->wwn_port = (u64)shmem_info.fcoe_wwn_port_name_upper |
1153 (((u64)shmem_info.fcoe_wwn_port_name_lower) << 32);
1154 info->wwn_node = (u64)shmem_info.fcoe_wwn_node_name_upper |
1155 (((u64)shmem_info.fcoe_wwn_node_name_lower) << 32);
1156
1157 info->ovlan = (u16)(shmem_info.ovlan_stag & FUNC_MF_CFG_OV_STAG_MASK);
1158
0fefbfba
SK		 1159 info->mtu = (u16)shmem_info.mtu_size;
1160
14d39648
MY		 1161 p_hwfn->hw_info.b_wol_support = QED_WOL_SUPPORT_NONE;
1162 p_hwfn->cdev->wol_config = (u8)QED_OV_WOL_DEFAULT;
1163 if (qed_mcp_is_init(p_hwfn)) {
1164 u32 resp = 0, param = 0;
1165 int rc;
1166
1167 rc = qed_mcp_cmd(p_hwfn, p_ptt,
1168 DRV_MSG_CODE_OS_WOL, 0, &resp, &param);
1169 if (rc)
1170 return rc;
1171 if (resp == FW_MSG_CODE_OS_WOL_SUPPORTED)
1172 p_hwfn->hw_info.b_wol_support = QED_WOL_SUPPORT_PME;
1173 }
1174
fe56b9e6 1175 DP_VERBOSE(p_hwfn, (QED_MSG_SP | NETIF_MSG_IFUP),
14d39648 1176 "Read configuration from shmem: pause_on_host %02x protocol %02x BW [%02x - %02x] MAC %02x:%02x:%02x:%02x:%02x:%02x wwn port %llx node %llx ovlan %04x wol %02x\n",
fe56b9e6
YM		 1177 info->pause_on_host, info->protocol,
1178 info->bandwidth_min, info->bandwidth_max,
1179 info->mac[0], info->mac[1], info->mac[2],
1180 info->mac[3], info->mac[4], info->mac[5],
14d39648
MY		 1181 info->wwn_port, info->wwn_node,
1182 info->ovlan, (u8)p_hwfn->hw_info.b_wol_support);
fe56b9e6
YM		 1183
1184 return 0;
1185}
1186
cc875c2e
YM		 1187struct qed_mcp_link_params
1188*qed_mcp_get_link_params(struct qed_hwfn *p_hwfn)
1189{
1190 if (!p_hwfn || !p_hwfn->mcp_info)
1191 return NULL;
1192 return &p_hwfn->mcp_info->link_input;
1193}
1194
1195struct qed_mcp_link_state
1196*qed_mcp_get_link_state(struct qed_hwfn *p_hwfn)
1197{
1198 if (!p_hwfn || !p_hwfn->mcp_info)
1199 return NULL;
1200 return &p_hwfn->mcp_info->link_output;
1201}
1202
1203struct qed_mcp_link_capabilities
1204*qed_mcp_get_link_capabilities(struct qed_hwfn *p_hwfn)
1205{
1206 if (!p_hwfn || !p_hwfn->mcp_info)
1207 return NULL;
1208 return &p_hwfn->mcp_info->link_capabilities;
1209}
1210
1a635e48 1211int qed_mcp_drain(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
fe56b9e6
YM		 1212{
1213 u32 resp = 0, param = 0;
1214 int rc;
1215
1216 rc = qed_mcp_cmd(p_hwfn, p_ptt,
1a635e48 1217 DRV_MSG_CODE_NIG_DRAIN, 1000, &resp, &param);
fe56b9e6
YM		 1218
1219 /* Wait for the drain to complete before returning */
8f60bafe 1220 msleep(1020);
fe56b9e6
YM		 1221
1222 return rc;
1223}
1224
cee4d264 1225int qed_mcp_get_flash_size(struct qed_hwfn *p_hwfn,
1a635e48 1226 struct qed_ptt *p_ptt, u32 *p_flash_size)
cee4d264
MC		 1227{
1228 u32 flash_size;
1229
1408cc1f
YM		 1230 if (IS_VF(p_hwfn->cdev))
1231 return -EINVAL;
1232
cee4d264
MC		 1233 flash_size = qed_rd(p_hwfn, p_ptt, MCP_REG_NVM_CFG4);
1234 flash_size = (flash_size & MCP_REG_NVM_CFG4_FLASH_SIZE) >>
1235 MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT;
1236 flash_size = (1 << (flash_size + MCP_BYTES_PER_MBIT_SHIFT));
1237
1238 *p_flash_size = flash_size;
1239
1240 return 0;
1241}
1242
1408cc1f
YM		 1243int qed_mcp_config_vf_msix(struct qed_hwfn *p_hwfn,
1244 struct qed_ptt *p_ptt, u8 vf_id, u8 num)
1245{
1246 u32 resp = 0, param = 0, rc_param = 0;
1247 int rc;
1248
1249 /* Only Leader can configure MSIX, and need to take CMT into account */
1250 if (!IS_LEAD_HWFN(p_hwfn))
1251 return 0;
1252 num *= p_hwfn->cdev->num_hwfns;
1253
1254 param |= (vf_id << DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT) &
1255 DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK;
1256 param |= (num << DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT) &
1257 DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK;
1258
1259 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_VF_MSIX, param,
1260 &resp, &rc_param);
1261
1262 if (resp != FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE) {
1263 DP_NOTICE(p_hwfn, "VF[%d]: MFW failed to set MSI-X\n", vf_id);
1264 rc = -EINVAL;
1265 } else {
1266 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
1267 "Requested 0x%02x MSI-x interrupts from VF 0x%02x\n",
1268 num, vf_id);
1269 }
1270
1271 return rc;
1272}
1273
fe56b9e6
YM		 1274int
1275qed_mcp_send_drv_version(struct qed_hwfn *p_hwfn,
1276 struct qed_ptt *p_ptt,
1277 struct qed_mcp_drv_version *p_ver)
1278{
5529bad9
TT		 1279 struct drv_version_stc *p_drv_version;
1280 struct qed_mcp_mb_params mb_params;
1281 union drv_union_data union_data;
1282 __be32 val;
1283 u32 i;
1284 int rc;
fe56b9e6 1285
5529bad9
TT		 1286 p_drv_version = &union_data.drv_version;
1287 p_drv_version->version = p_ver->version;
4b01e519 1288
67a99b70
YM		 1289 for (i = 0; i < (MCP_DRV_VER_STR_SIZE - 4) / sizeof(u32); i++) {
1290 val = cpu_to_be32(*((u32 *)&p_ver->name[i * sizeof(u32)]));
4b01e519 1291 *(__be32 *)&p_drv_version->name[i * sizeof(u32)] = val;
fe56b9e6
YM		 1292 }
1293
5529bad9
TT		 1294 memset(&mb_params, 0, sizeof(mb_params));
1295 mb_params.cmd = DRV_MSG_CODE_SET_VERSION;
1296 mb_params.p_data_src = &union_data;
1297 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1298 if (rc)
fe56b9e6 1299 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
fe56b9e6 1300
5529bad9 1301 return rc;
fe56b9e6 1302}
91420b83 1303
4102426f
TT		 1304int qed_mcp_halt(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1305{
1306 u32 resp = 0, param = 0;
1307 int rc;
1308
1309 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MCP_HALT, 0, &resp,
1310 &param);
1311 if (rc)
1312 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1313
1314 return rc;
1315}
1316
1317int qed_mcp_resume(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1318{
1319 u32 value, cpu_mode;
1320
1321 qed_wr(p_hwfn, p_ptt, MCP_REG_CPU_STATE, 0xffffffff);
1322
1323 value = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE);
1324 value &= ~MCP_REG_CPU_MODE_SOFT_HALT;
1325 qed_wr(p_hwfn, p_ptt, MCP_REG_CPU_MODE, value);
1326 cpu_mode = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE);
1327
1328 return (cpu_mode & MCP_REG_CPU_MODE_SOFT_HALT) ? -EAGAIN : 0;
1329}
1330
0fefbfba
SK		 1331int qed_mcp_ov_update_current_config(struct qed_hwfn *p_hwfn,
1332 struct qed_ptt *p_ptt,
1333 enum qed_ov_client client)
1334{
1335 u32 resp = 0, param = 0;
1336 u32 drv_mb_param;
1337 int rc;
1338
1339 switch (client) {
1340 case QED_OV_CLIENT_DRV:
1341 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OS;
1342 break;
1343 case QED_OV_CLIENT_USER:
1344 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OTHER;
1345 break;
1346 case QED_OV_CLIENT_VENDOR_SPEC:
1347 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC;
1348 break;
1349 default:
1350 DP_NOTICE(p_hwfn, "Invalid client type %d\n", client);
1351 return -EINVAL;
1352 }
1353
1354 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_CURR_CFG,
1355 drv_mb_param, &resp, &param);
1356 if (rc)
1357 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1358
1359 return rc;
1360}
1361
1362int qed_mcp_ov_update_driver_state(struct qed_hwfn *p_hwfn,
1363 struct qed_ptt *p_ptt,
1364 enum qed_ov_driver_state drv_state)
1365{
1366 u32 resp = 0, param = 0;
1367 u32 drv_mb_param;
1368 int rc;
1369
1370 switch (drv_state) {
1371 case QED_OV_DRIVER_STATE_NOT_LOADED:
1372 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED;
1373 break;
1374 case QED_OV_DRIVER_STATE_DISABLED:
1375 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED;
1376 break;
1377 case QED_OV_DRIVER_STATE_ACTIVE:
1378 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE;
1379 break;
1380 default:
1381 DP_NOTICE(p_hwfn, "Invalid driver state %d\n", drv_state);
1382 return -EINVAL;
1383 }
1384
1385 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE,
1386 drv_mb_param, &resp, &param);
1387 if (rc)
1388 DP_ERR(p_hwfn, "Failed to send driver state\n");
1389
1390 return rc;
1391}
1392
1393int qed_mcp_ov_update_mtu(struct qed_hwfn *p_hwfn,
1394 struct qed_ptt *p_ptt, u16 mtu)
1395{
1396 u32 resp = 0, param = 0;
1397 u32 drv_mb_param;
1398 int rc;
1399
1400 drv_mb_param = (u32)mtu << DRV_MB_PARAM_OV_MTU_SIZE_SHIFT;
1401 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_MTU,
1402 drv_mb_param, &resp, &param);
1403 if (rc)
1404 DP_ERR(p_hwfn, "Failed to send mtu value, rc = %d\n", rc);
1405
1406 return rc;
1407}
1408
1409int qed_mcp_ov_update_mac(struct qed_hwfn *p_hwfn,
1410 struct qed_ptt *p_ptt, u8 *mac)
1411{
1412 struct qed_mcp_mb_params mb_params;
1413 union drv_union_data union_data;
1414 int rc;
1415
1416 memset(&mb_params, 0, sizeof(mb_params));
1417 mb_params.cmd = DRV_MSG_CODE_SET_VMAC;
1418 mb_params.param = DRV_MSG_CODE_VMAC_TYPE_MAC <<
1419 DRV_MSG_CODE_VMAC_TYPE_SHIFT;
1420 mb_params.param |= MCP_PF_ID(p_hwfn);
1421 ether_addr_copy(&union_data.raw_data[0], mac);
1422 mb_params.p_data_src = &union_data;
1423 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1424 if (rc)
1425 DP_ERR(p_hwfn, "Failed to send mac address, rc = %d\n", rc);
1426
14d39648
MY		 1427 /* Store primary MAC for later possible WoL */
1428 memcpy(p_hwfn->cdev->wol_mac, mac, ETH_ALEN);
1429
0fefbfba
SK		 1430 return rc;
1431}
1432
1433int qed_mcp_ov_update_wol(struct qed_hwfn *p_hwfn,
1434 struct qed_ptt *p_ptt, enum qed_ov_wol wol)
1435{
1436 u32 resp = 0, param = 0;
1437 u32 drv_mb_param;
1438 int rc;
1439
14d39648
MY		 1440 if (p_hwfn->hw_info.b_wol_support == QED_WOL_SUPPORT_NONE) {
1441 DP_VERBOSE(p_hwfn, QED_MSG_SP,
1442 "Can't change WoL configuration when WoL isn't supported\n");
1443 return -EINVAL;
1444 }
1445
0fefbfba
SK		 1446 switch (wol) {
1447 case QED_OV_WOL_DEFAULT:
1448 drv_mb_param = DRV_MB_PARAM_WOL_DEFAULT;
1449 break;
1450 case QED_OV_WOL_DISABLED:
1451 drv_mb_param = DRV_MB_PARAM_WOL_DISABLED;
1452 break;
1453 case QED_OV_WOL_ENABLED:
1454 drv_mb_param = DRV_MB_PARAM_WOL_ENABLED;
1455 break;
1456 default:
1457 DP_ERR(p_hwfn, "Invalid wol state %d\n", wol);
1458 return -EINVAL;
1459 }
1460
1461 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_WOL,
1462 drv_mb_param, &resp, &param);
1463 if (rc)
1464 DP_ERR(p_hwfn, "Failed to send wol mode, rc = %d\n", rc);
1465
14d39648
MY		 1466 /* Store the WoL update for a future unload */
1467 p_hwfn->cdev->wol_config = (u8)wol;
1468
0fefbfba
SK		 1469 return rc;
1470}
1471
1472int qed_mcp_ov_update_eswitch(struct qed_hwfn *p_hwfn,
1473 struct qed_ptt *p_ptt,
1474 enum qed_ov_eswitch eswitch)
1475{
1476 u32 resp = 0, param = 0;
1477 u32 drv_mb_param;
1478 int rc;
1479
1480 switch (eswitch) {
1481 case QED_OV_ESWITCH_NONE:
1482 drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_NONE;
1483 break;
1484 case QED_OV_ESWITCH_VEB:
1485 drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_VEB;
1486 break;
1487 case QED_OV_ESWITCH_VEPA:
1488 drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_VEPA;
1489 break;
1490 default:
1491 DP_ERR(p_hwfn, "Invalid eswitch mode %d\n", eswitch);
1492 return -EINVAL;
1493 }
1494
1495 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_ESWITCH_MODE,
1496 drv_mb_param, &resp, &param);
1497 if (rc)
1498 DP_ERR(p_hwfn, "Failed to send eswitch mode, rc = %d\n", rc);
1499
1500 return rc;
1501}
1502
1a635e48
YM		 1503int qed_mcp_set_led(struct qed_hwfn *p_hwfn,
1504 struct qed_ptt *p_ptt, enum qed_led_mode mode)
91420b83
SK		 1505{
1506 u32 resp = 0, param = 0, drv_mb_param;
1507 int rc;
1508
1509 switch (mode) {
1510 case QED_LED_MODE_ON:
1511 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_ON;
1512 break;
1513 case QED_LED_MODE_OFF:
1514 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OFF;
1515 break;
1516 case QED_LED_MODE_RESTORE:
1517 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OPER;
1518 break;
1519 default:
1520 DP_NOTICE(p_hwfn, "Invalid LED mode %d\n", mode);
1521 return -EINVAL;
1522 }
1523
1524 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_LED_MODE,
1525 drv_mb_param, &resp, &param);
1526
1527 return rc;
1528}
03dc76ca 1529
4102426f
TT		 1530int qed_mcp_mask_parities(struct qed_hwfn *p_hwfn,
1531 struct qed_ptt *p_ptt, u32 mask_parities)
1532{
1533 u32 resp = 0, param = 0;
1534 int rc;
1535
1536 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MASK_PARITIES,
1537 mask_parities, &resp, &param);
1538
1539 if (rc) {
1540 DP_ERR(p_hwfn,
1541 "MCP response failure for mask parities, aborting\n");
1542 } else if (resp != FW_MSG_CODE_OK) {
1543 DP_ERR(p_hwfn,
1544 "MCP did not acknowledge mask parity request. Old MFW?\n");
1545 rc = -EINVAL;
1546 }
1547
1548 return rc;
1549}
1550
7a4b21b7
MY		 1551int qed_mcp_nvm_read(struct qed_dev *cdev, u32 addr, u8 *p_buf, u32 len)
1552{
1553 u32 bytes_left = len, offset = 0, bytes_to_copy, read_len = 0;
1554 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
1555 u32 resp = 0, resp_param = 0;
1556 struct qed_ptt *p_ptt;
1557 int rc = 0;
1558
1559 p_ptt = qed_ptt_acquire(p_hwfn);
1560 if (!p_ptt)
1561 return -EBUSY;
1562
1563 while (bytes_left > 0) {
1564 bytes_to_copy = min_t(u32, bytes_left, MCP_DRV_NVM_BUF_LEN);
1565
1566 rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt,
1567 DRV_MSG_CODE_NVM_READ_NVRAM,
1568 addr + offset +
1569 (bytes_to_copy <<
1570 DRV_MB_PARAM_NVM_LEN_SHIFT),
1571 &resp, &resp_param,
1572 &read_len,
1573 (u32 *)(p_buf + offset));
1574
1575 if (rc || (resp != FW_MSG_CODE_NVM_OK)) {
1576 DP_NOTICE(cdev, "MCP command rc = %d\n", rc);
1577 break;
1578 }
1579
1580 /* This can be a lengthy process, and it's possible scheduler
1581 * isn't preemptable. Sleep a bit to prevent CPU hogging.
1582 */
1583 if (bytes_left % 0x1000 <
1584 (bytes_left - read_len) % 0x1000)
1585 usleep_range(1000, 2000);
1586
1587 offset += read_len;
1588 bytes_left -= read_len;
1589 }
1590
1591 cdev->mcp_nvm_resp = resp;
1592 qed_ptt_release(p_hwfn, p_ptt);
1593
1594 return rc;
1595}
1596
03dc76ca
SRK		 1597int qed_mcp_bist_register_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1598{
1599 u32 drv_mb_param = 0, rsp, param;
1600 int rc = 0;
1601
1602 drv_mb_param = (DRV_MB_PARAM_BIST_REGISTER_TEST <<
1603 DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
1604
1605 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
1606 drv_mb_param, &rsp, &param);
1607
1608 if (rc)
1609 return rc;
1610
1611 if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
1612 (param != DRV_MB_PARAM_BIST_RC_PASSED))
1613 rc = -EAGAIN;
1614
1615 return rc;
1616}
1617
1618int qed_mcp_bist_clock_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1619{
1620 u32 drv_mb_param, rsp, param;
1621 int rc = 0;
1622
1623 drv_mb_param = (DRV_MB_PARAM_BIST_CLOCK_TEST <<
1624 DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
1625
1626 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
1627 drv_mb_param, &rsp, &param);
1628
1629 if (rc)
1630 return rc;
1631
1632 if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
1633 (param != DRV_MB_PARAM_BIST_RC_PASSED))
1634 rc = -EAGAIN;
1635
1636 return rc;
1637}
7a4b21b7
MY		 1638
1639int qed_mcp_bist_nvm_test_get_num_images(struct qed_hwfn *p_hwfn,
1640 struct qed_ptt *p_ptt,
1641 u32 *num_images)
1642{
1643 u32 drv_mb_param = 0, rsp;
1644 int rc = 0;
1645
1646 drv_mb_param = (DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES <<
1647 DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
1648
1649 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
1650 drv_mb_param, &rsp, num_images);
1651 if (rc)
1652 return rc;
1653
1654 if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK))
1655 rc = -EINVAL;
1656
1657 return rc;
1658}
1659
1660int qed_mcp_bist_nvm_test_get_image_att(struct qed_hwfn *p_hwfn,
1661 struct qed_ptt *p_ptt,
1662 struct bist_nvm_image_att *p_image_att,
1663 u32 image_index)
1664{
1665 u32 buf_size = 0, param, resp = 0, resp_param = 0;
1666 int rc;
1667
1668 param = DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX <<
1669 DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT;
1670 param |= image_index << DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT;
1671
1672 rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt,
1673 DRV_MSG_CODE_BIST_TEST, param,
1674 &resp, &resp_param,
1675 &buf_size,
1676 (u32 *)p_image_att);
1677 if (rc)
1678 return rc;
1679
1680 if (((resp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
1681 (p_image_att->return_code != 1))
1682 rc = -EINVAL;
1683
1684 return rc;
1685}
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