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fe56b9e6 | 1 | /* QLogic qed NIC Driver |
e8f1cb50 | 2 | * Copyright (c) 2015-2017 QLogic Corporation |
fe56b9e6 | 3 | * |
e8f1cb50 MY |
4 | * This software is available to you under a choice of one of two |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and /or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
fe56b9e6 YM |
31 | */ |
32 | ||
33 | #include <linux/types.h> | |
34 | #include <asm/byteorder.h> | |
35 | #include <linux/delay.h> | |
36 | #include <linux/errno.h> | |
37 | #include <linux/kernel.h> | |
fe56b9e6 | 38 | #include <linux/slab.h> |
5529bad9 | 39 | #include <linux/spinlock.h> |
fe56b9e6 | 40 | #include <linux/string.h> |
0fefbfba | 41 | #include <linux/etherdevice.h> |
fe56b9e6 | 42 | #include "qed.h" |
39651abd | 43 | #include "qed_dcbx.h" |
fe56b9e6 YM |
44 | #include "qed_hsi.h" |
45 | #include "qed_hw.h" | |
46 | #include "qed_mcp.h" | |
47 | #include "qed_reg_addr.h" | |
1408cc1f YM |
48 | #include "qed_sriov.h" |
49 | ||
fe56b9e6 YM |
50 | #define CHIP_MCP_RESP_ITER_US 10 |
51 | ||
52 | #define QED_DRV_MB_MAX_RETRIES (500 * 1000) /* Account for 5 sec */ | |
53 | #define QED_MCP_RESET_RETRIES (50 * 1000) /* Account for 500 msec */ | |
54 | ||
55 | #define DRV_INNER_WR(_p_hwfn, _p_ptt, _ptr, _offset, _val) \ | |
56 | qed_wr(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset), \ | |
57 | _val) | |
58 | ||
59 | #define DRV_INNER_RD(_p_hwfn, _p_ptt, _ptr, _offset) \ | |
60 | qed_rd(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset)) | |
61 | ||
62 | #define DRV_MB_WR(_p_hwfn, _p_ptt, _field, _val) \ | |
63 | DRV_INNER_WR(p_hwfn, _p_ptt, drv_mb_addr, \ | |
64 | offsetof(struct public_drv_mb, _field), _val) | |
65 | ||
66 | #define DRV_MB_RD(_p_hwfn, _p_ptt, _field) \ | |
67 | DRV_INNER_RD(_p_hwfn, _p_ptt, drv_mb_addr, \ | |
68 | offsetof(struct public_drv_mb, _field)) | |
69 | ||
70 | #define PDA_COMP (((FW_MAJOR_VERSION) + (FW_MINOR_VERSION << 8)) << \ | |
71 | DRV_ID_PDA_COMP_VER_SHIFT) | |
72 | ||
73 | #define MCP_BYTES_PER_MBIT_SHIFT 17 | |
74 | ||
75 | bool qed_mcp_is_init(struct qed_hwfn *p_hwfn) | |
76 | { | |
77 | if (!p_hwfn->mcp_info || !p_hwfn->mcp_info->public_base) | |
78 | return false; | |
79 | return true; | |
80 | } | |
81 | ||
1a635e48 | 82 | void qed_mcp_cmd_port_init(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) |
fe56b9e6 YM |
83 | { |
84 | u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, | |
85 | PUBLIC_PORT); | |
86 | u32 mfw_mb_offsize = qed_rd(p_hwfn, p_ptt, addr); | |
87 | ||
88 | p_hwfn->mcp_info->port_addr = SECTION_ADDR(mfw_mb_offsize, | |
89 | MFW_PORT(p_hwfn)); | |
90 | DP_VERBOSE(p_hwfn, QED_MSG_SP, | |
91 | "port_addr = 0x%x, port_id 0x%02x\n", | |
92 | p_hwfn->mcp_info->port_addr, MFW_PORT(p_hwfn)); | |
93 | } | |
94 | ||
1a635e48 | 95 | void qed_mcp_read_mb(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) |
fe56b9e6 YM |
96 | { |
97 | u32 length = MFW_DRV_MSG_MAX_DWORDS(p_hwfn->mcp_info->mfw_mb_length); | |
98 | u32 tmp, i; | |
99 | ||
100 | if (!p_hwfn->mcp_info->public_base) | |
101 | return; | |
102 | ||
103 | for (i = 0; i < length; i++) { | |
104 | tmp = qed_rd(p_hwfn, p_ptt, | |
105 | p_hwfn->mcp_info->mfw_mb_addr + | |
106 | (i << 2) + sizeof(u32)); | |
107 | ||
108 | /* The MB data is actually BE; Need to force it to cpu */ | |
109 | ((u32 *)p_hwfn->mcp_info->mfw_mb_cur)[i] = | |
110 | be32_to_cpu((__force __be32)tmp); | |
111 | } | |
112 | } | |
113 | ||
4ed1eea8 TT |
114 | struct qed_mcp_cmd_elem { |
115 | struct list_head list; | |
116 | struct qed_mcp_mb_params *p_mb_params; | |
117 | u16 expected_seq_num; | |
118 | bool b_is_completed; | |
119 | }; | |
120 | ||
121 | /* Must be called while cmd_lock is acquired */ | |
122 | static struct qed_mcp_cmd_elem * | |
123 | qed_mcp_cmd_add_elem(struct qed_hwfn *p_hwfn, | |
124 | struct qed_mcp_mb_params *p_mb_params, | |
125 | u16 expected_seq_num) | |
126 | { | |
127 | struct qed_mcp_cmd_elem *p_cmd_elem = NULL; | |
128 | ||
129 | p_cmd_elem = kzalloc(sizeof(*p_cmd_elem), GFP_ATOMIC); | |
130 | if (!p_cmd_elem) | |
131 | goto out; | |
132 | ||
133 | p_cmd_elem->p_mb_params = p_mb_params; | |
134 | p_cmd_elem->expected_seq_num = expected_seq_num; | |
135 | list_add(&p_cmd_elem->list, &p_hwfn->mcp_info->cmd_list); | |
136 | out: | |
137 | return p_cmd_elem; | |
138 | } | |
139 | ||
140 | /* Must be called while cmd_lock is acquired */ | |
141 | static void qed_mcp_cmd_del_elem(struct qed_hwfn *p_hwfn, | |
142 | struct qed_mcp_cmd_elem *p_cmd_elem) | |
143 | { | |
144 | list_del(&p_cmd_elem->list); | |
145 | kfree(p_cmd_elem); | |
146 | } | |
147 | ||
148 | /* Must be called while cmd_lock is acquired */ | |
149 | static struct qed_mcp_cmd_elem *qed_mcp_cmd_get_elem(struct qed_hwfn *p_hwfn, | |
150 | u16 seq_num) | |
151 | { | |
152 | struct qed_mcp_cmd_elem *p_cmd_elem = NULL; | |
153 | ||
154 | list_for_each_entry(p_cmd_elem, &p_hwfn->mcp_info->cmd_list, list) { | |
155 | if (p_cmd_elem->expected_seq_num == seq_num) | |
156 | return p_cmd_elem; | |
157 | } | |
158 | ||
159 | return NULL; | |
160 | } | |
161 | ||
fe56b9e6 YM |
162 | int qed_mcp_free(struct qed_hwfn *p_hwfn) |
163 | { | |
164 | if (p_hwfn->mcp_info) { | |
4ed1eea8 TT |
165 | struct qed_mcp_cmd_elem *p_cmd_elem, *p_tmp; |
166 | ||
fe56b9e6 YM |
167 | kfree(p_hwfn->mcp_info->mfw_mb_cur); |
168 | kfree(p_hwfn->mcp_info->mfw_mb_shadow); | |
4ed1eea8 TT |
169 | |
170 | spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); | |
171 | list_for_each_entry_safe(p_cmd_elem, | |
172 | p_tmp, | |
173 | &p_hwfn->mcp_info->cmd_list, list) { | |
174 | qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem); | |
175 | } | |
176 | spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); | |
fe56b9e6 | 177 | } |
4ed1eea8 | 178 | |
fe56b9e6 | 179 | kfree(p_hwfn->mcp_info); |
3587cb87 | 180 | p_hwfn->mcp_info = NULL; |
fe56b9e6 YM |
181 | |
182 | return 0; | |
183 | } | |
184 | ||
1a635e48 | 185 | static int qed_load_mcp_offsets(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) |
fe56b9e6 YM |
186 | { |
187 | struct qed_mcp_info *p_info = p_hwfn->mcp_info; | |
188 | u32 drv_mb_offsize, mfw_mb_offsize; | |
189 | u32 mcp_pf_id = MCP_PF_ID(p_hwfn); | |
190 | ||
191 | p_info->public_base = qed_rd(p_hwfn, p_ptt, MISC_REG_SHARED_MEM_ADDR); | |
192 | if (!p_info->public_base) | |
193 | return 0; | |
194 | ||
195 | p_info->public_base |= GRCBASE_MCP; | |
196 | ||
197 | /* Calculate the driver and MFW mailbox address */ | |
198 | drv_mb_offsize = qed_rd(p_hwfn, p_ptt, | |
199 | SECTION_OFFSIZE_ADDR(p_info->public_base, | |
200 | PUBLIC_DRV_MB)); | |
201 | p_info->drv_mb_addr = SECTION_ADDR(drv_mb_offsize, mcp_pf_id); | |
202 | DP_VERBOSE(p_hwfn, QED_MSG_SP, | |
203 | "drv_mb_offsiz = 0x%x, drv_mb_addr = 0x%x mcp_pf_id = 0x%x\n", | |
204 | drv_mb_offsize, p_info->drv_mb_addr, mcp_pf_id); | |
205 | ||
206 | /* Set the MFW MB address */ | |
207 | mfw_mb_offsize = qed_rd(p_hwfn, p_ptt, | |
208 | SECTION_OFFSIZE_ADDR(p_info->public_base, | |
209 | PUBLIC_MFW_MB)); | |
210 | p_info->mfw_mb_addr = SECTION_ADDR(mfw_mb_offsize, mcp_pf_id); | |
211 | p_info->mfw_mb_length = (u16)qed_rd(p_hwfn, p_ptt, p_info->mfw_mb_addr); | |
212 | ||
213 | /* Get the current driver mailbox sequence before sending | |
214 | * the first command | |
215 | */ | |
216 | p_info->drv_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) & | |
217 | DRV_MSG_SEQ_NUMBER_MASK; | |
218 | ||
219 | /* Get current FW pulse sequence */ | |
220 | p_info->drv_pulse_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_pulse_mb) & | |
221 | DRV_PULSE_SEQ_MASK; | |
222 | ||
4ed1eea8 | 223 | p_info->mcp_hist = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0); |
fe56b9e6 YM |
224 | |
225 | return 0; | |
226 | } | |
227 | ||
1a635e48 | 228 | int qed_mcp_cmd_init(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) |
fe56b9e6 YM |
229 | { |
230 | struct qed_mcp_info *p_info; | |
231 | u32 size; | |
232 | ||
233 | /* Allocate mcp_info structure */ | |
60fffb3b | 234 | p_hwfn->mcp_info = kzalloc(sizeof(*p_hwfn->mcp_info), GFP_KERNEL); |
fe56b9e6 YM |
235 | if (!p_hwfn->mcp_info) |
236 | goto err; | |
237 | p_info = p_hwfn->mcp_info; | |
238 | ||
4ed1eea8 TT |
239 | /* Initialize the MFW spinlock */ |
240 | spin_lock_init(&p_info->cmd_lock); | |
241 | spin_lock_init(&p_info->link_lock); | |
242 | ||
243 | INIT_LIST_HEAD(&p_info->cmd_list); | |
244 | ||
fe56b9e6 YM |
245 | if (qed_load_mcp_offsets(p_hwfn, p_ptt) != 0) { |
246 | DP_NOTICE(p_hwfn, "MCP is not initialized\n"); | |
247 | /* Do not free mcp_info here, since public_base indicate that | |
248 | * the MCP is not initialized | |
249 | */ | |
250 | return 0; | |
251 | } | |
252 | ||
253 | size = MFW_DRV_MSG_MAX_DWORDS(p_info->mfw_mb_length) * sizeof(u32); | |
60fffb3b | 254 | p_info->mfw_mb_cur = kzalloc(size, GFP_KERNEL); |
83aeb933 | 255 | p_info->mfw_mb_shadow = kzalloc(size, GFP_KERNEL); |
eb2a6b80 | 256 | if (!p_info->mfw_mb_cur || !p_info->mfw_mb_shadow) |
fe56b9e6 YM |
257 | goto err; |
258 | ||
fe56b9e6 YM |
259 | return 0; |
260 | ||
261 | err: | |
fe56b9e6 YM |
262 | qed_mcp_free(p_hwfn); |
263 | return -ENOMEM; | |
264 | } | |
265 | ||
4ed1eea8 TT |
266 | static void qed_mcp_reread_offsets(struct qed_hwfn *p_hwfn, |
267 | struct qed_ptt *p_ptt) | |
5529bad9 | 268 | { |
4ed1eea8 | 269 | u32 generic_por_0 = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0); |
5529bad9 | 270 | |
4ed1eea8 TT |
271 | /* Use MCP history register to check if MCP reset occurred between init |
272 | * time and now. | |
273 | */ | |
274 | if (p_hwfn->mcp_info->mcp_hist != generic_por_0) { | |
275 | DP_VERBOSE(p_hwfn, | |
276 | QED_MSG_SP, | |
277 | "Rereading MCP offsets [mcp_hist 0x%08x, generic_por_0 0x%08x]\n", | |
278 | p_hwfn->mcp_info->mcp_hist, generic_por_0); | |
5529bad9 | 279 | |
4ed1eea8 TT |
280 | qed_load_mcp_offsets(p_hwfn, p_ptt); |
281 | qed_mcp_cmd_port_init(p_hwfn, p_ptt); | |
5529bad9 | 282 | } |
5529bad9 TT |
283 | } |
284 | ||
1a635e48 | 285 | int qed_mcp_reset(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) |
fe56b9e6 | 286 | { |
4ed1eea8 | 287 | u32 org_mcp_reset_seq, seq, delay = CHIP_MCP_RESP_ITER_US, cnt = 0; |
fe56b9e6 YM |
288 | int rc = 0; |
289 | ||
4ed1eea8 TT |
290 | /* Ensure that only a single thread is accessing the mailbox */ |
291 | spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); | |
5529bad9 | 292 | |
fe56b9e6 | 293 | org_mcp_reset_seq = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0); |
4ed1eea8 TT |
294 | |
295 | /* Set drv command along with the updated sequence */ | |
296 | qed_mcp_reread_offsets(p_hwfn, p_ptt); | |
297 | seq = ++p_hwfn->mcp_info->drv_mb_seq; | |
298 | DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (DRV_MSG_CODE_MCP_RESET | seq)); | |
fe56b9e6 YM |
299 | |
300 | do { | |
301 | /* Wait for MFW response */ | |
302 | udelay(delay); | |
303 | /* Give the FW up to 500 second (50*1000*10usec) */ | |
304 | } while ((org_mcp_reset_seq == qed_rd(p_hwfn, p_ptt, | |
305 | MISCS_REG_GENERIC_POR_0)) && | |
306 | (cnt++ < QED_MCP_RESET_RETRIES)); | |
307 | ||
308 | if (org_mcp_reset_seq != | |
309 | qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) { | |
310 | DP_VERBOSE(p_hwfn, QED_MSG_SP, | |
311 | "MCP was reset after %d usec\n", cnt * delay); | |
312 | } else { | |
313 | DP_ERR(p_hwfn, "Failed to reset MCP\n"); | |
314 | rc = -EAGAIN; | |
315 | } | |
316 | ||
4ed1eea8 | 317 | spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); |
5529bad9 | 318 | |
fe56b9e6 YM |
319 | return rc; |
320 | } | |
321 | ||
4ed1eea8 TT |
322 | /* Must be called while cmd_lock is acquired */ |
323 | static bool qed_mcp_has_pending_cmd(struct qed_hwfn *p_hwfn) | |
fe56b9e6 | 324 | { |
4ed1eea8 | 325 | struct qed_mcp_cmd_elem *p_cmd_elem; |
fe56b9e6 | 326 | |
4ed1eea8 TT |
327 | /* There is at most one pending command at a certain time, and if it |
328 | * exists - it is placed at the HEAD of the list. | |
fe56b9e6 | 329 | */ |
4ed1eea8 TT |
330 | if (!list_empty(&p_hwfn->mcp_info->cmd_list)) { |
331 | p_cmd_elem = list_first_entry(&p_hwfn->mcp_info->cmd_list, | |
332 | struct qed_mcp_cmd_elem, list); | |
333 | return !p_cmd_elem->b_is_completed; | |
fe56b9e6 | 334 | } |
fe56b9e6 | 335 | |
4ed1eea8 TT |
336 | return false; |
337 | } | |
fe56b9e6 | 338 | |
4ed1eea8 TT |
339 | /* Must be called while cmd_lock is acquired */ |
340 | static int | |
341 | qed_mcp_update_pending_cmd(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) | |
342 | { | |
343 | struct qed_mcp_mb_params *p_mb_params; | |
344 | struct qed_mcp_cmd_elem *p_cmd_elem; | |
345 | u32 mcp_resp; | |
346 | u16 seq_num; | |
347 | ||
348 | mcp_resp = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_header); | |
349 | seq_num = (u16)(mcp_resp & FW_MSG_SEQ_NUMBER_MASK); | |
350 | ||
351 | /* Return if no new non-handled response has been received */ | |
352 | if (seq_num != p_hwfn->mcp_info->drv_mb_seq) | |
353 | return -EAGAIN; | |
354 | ||
355 | p_cmd_elem = qed_mcp_cmd_get_elem(p_hwfn, seq_num); | |
356 | if (!p_cmd_elem) { | |
357 | DP_ERR(p_hwfn, | |
358 | "Failed to find a pending mailbox cmd that expects sequence number %d\n", | |
359 | seq_num); | |
360 | return -EINVAL; | |
361 | } | |
362 | ||
363 | p_mb_params = p_cmd_elem->p_mb_params; | |
364 | ||
365 | /* Get the MFW response along with the sequence number */ | |
366 | p_mb_params->mcp_resp = mcp_resp; | |
367 | ||
368 | /* Get the MFW param */ | |
369 | p_mb_params->mcp_param = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_param); | |
370 | ||
371 | /* Get the union data */ | |
2f67af8c | 372 | if (p_mb_params->p_data_dst != NULL && p_mb_params->data_dst_size) { |
4ed1eea8 TT |
373 | u32 union_data_addr = p_hwfn->mcp_info->drv_mb_addr + |
374 | offsetof(struct public_drv_mb, | |
375 | union_data); | |
376 | qed_memcpy_from(p_hwfn, p_ptt, p_mb_params->p_data_dst, | |
2f67af8c | 377 | union_data_addr, p_mb_params->data_dst_size); |
4ed1eea8 TT |
378 | } |
379 | ||
380 | p_cmd_elem->b_is_completed = true; | |
381 | ||
382 | return 0; | |
383 | } | |
384 | ||
385 | /* Must be called while cmd_lock is acquired */ | |
386 | static void __qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn, | |
387 | struct qed_ptt *p_ptt, | |
388 | struct qed_mcp_mb_params *p_mb_params, | |
389 | u16 seq_num) | |
390 | { | |
391 | union drv_union_data union_data; | |
392 | u32 union_data_addr; | |
393 | ||
394 | /* Set the union data */ | |
395 | union_data_addr = p_hwfn->mcp_info->drv_mb_addr + | |
396 | offsetof(struct public_drv_mb, union_data); | |
397 | memset(&union_data, 0, sizeof(union_data)); | |
2f67af8c | 398 | if (p_mb_params->p_data_src != NULL && p_mb_params->data_src_size) |
4ed1eea8 | 399 | memcpy(&union_data, p_mb_params->p_data_src, |
2f67af8c | 400 | p_mb_params->data_src_size); |
4ed1eea8 TT |
401 | qed_memcpy_to(p_hwfn, p_ptt, union_data_addr, &union_data, |
402 | sizeof(union_data)); | |
403 | ||
404 | /* Set the drv param */ | |
405 | DRV_MB_WR(p_hwfn, p_ptt, drv_mb_param, p_mb_params->param); | |
406 | ||
407 | /* Set the drv command along with the sequence number */ | |
408 | DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (p_mb_params->cmd | seq_num)); | |
fe56b9e6 YM |
409 | |
410 | DP_VERBOSE(p_hwfn, QED_MSG_SP, | |
4ed1eea8 TT |
411 | "MFW mailbox: command 0x%08x param 0x%08x\n", |
412 | (p_mb_params->cmd | seq_num), p_mb_params->param); | |
413 | } | |
414 | ||
415 | static int | |
416 | _qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn, | |
417 | struct qed_ptt *p_ptt, | |
418 | struct qed_mcp_mb_params *p_mb_params, | |
419 | u32 max_retries, u32 delay) | |
420 | { | |
421 | struct qed_mcp_cmd_elem *p_cmd_elem; | |
422 | u32 cnt = 0; | |
423 | u16 seq_num; | |
424 | int rc = 0; | |
fe56b9e6 | 425 | |
4ed1eea8 | 426 | /* Wait until the mailbox is non-occupied */ |
fe56b9e6 | 427 | do { |
4ed1eea8 TT |
428 | /* Exit the loop if there is no pending command, or if the |
429 | * pending command is completed during this iteration. | |
430 | * The spinlock stays locked until the command is sent. | |
431 | */ | |
432 | ||
433 | spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); | |
434 | ||
435 | if (!qed_mcp_has_pending_cmd(p_hwfn)) | |
436 | break; | |
437 | ||
438 | rc = qed_mcp_update_pending_cmd(p_hwfn, p_ptt); | |
439 | if (!rc) | |
440 | break; | |
441 | else if (rc != -EAGAIN) | |
442 | goto err; | |
443 | ||
444 | spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); | |
fe56b9e6 | 445 | udelay(delay); |
4ed1eea8 | 446 | } while (++cnt < max_retries); |
fe56b9e6 | 447 | |
4ed1eea8 TT |
448 | if (cnt >= max_retries) { |
449 | DP_NOTICE(p_hwfn, | |
450 | "The MFW mailbox is occupied by an uncompleted command. Failed to send command 0x%08x [param 0x%08x].\n", | |
451 | p_mb_params->cmd, p_mb_params->param); | |
452 | return -EAGAIN; | |
453 | } | |
fe56b9e6 | 454 | |
4ed1eea8 TT |
455 | /* Send the mailbox command */ |
456 | qed_mcp_reread_offsets(p_hwfn, p_ptt); | |
457 | seq_num = ++p_hwfn->mcp_info->drv_mb_seq; | |
458 | p_cmd_elem = qed_mcp_cmd_add_elem(p_hwfn, p_mb_params, seq_num); | |
c8004600 DC |
459 | if (!p_cmd_elem) { |
460 | rc = -ENOMEM; | |
4ed1eea8 | 461 | goto err; |
c8004600 | 462 | } |
4ed1eea8 TT |
463 | |
464 | __qed_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, seq_num); | |
465 | spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); | |
466 | ||
467 | /* Wait for the MFW response */ | |
468 | do { | |
469 | /* Exit the loop if the command is already completed, or if the | |
470 | * command is completed during this iteration. | |
471 | * The spinlock stays locked until the list element is removed. | |
472 | */ | |
473 | ||
474 | udelay(delay); | |
475 | spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); | |
476 | ||
477 | if (p_cmd_elem->b_is_completed) | |
478 | break; | |
479 | ||
480 | rc = qed_mcp_update_pending_cmd(p_hwfn, p_ptt); | |
481 | if (!rc) | |
482 | break; | |
483 | else if (rc != -EAGAIN) | |
484 | goto err; | |
485 | ||
486 | spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); | |
487 | } while (++cnt < max_retries); | |
488 | ||
489 | if (cnt >= max_retries) { | |
490 | DP_NOTICE(p_hwfn, | |
491 | "The MFW failed to respond to command 0x%08x [param 0x%08x].\n", | |
492 | p_mb_params->cmd, p_mb_params->param); | |
493 | ||
494 | spin_lock_bh(&p_hwfn->mcp_info->cmd_lock); | |
495 | qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem); | |
496 | spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); | |
497 | ||
498 | return -EAGAIN; | |
fe56b9e6 | 499 | } |
4ed1eea8 TT |
500 | |
501 | qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem); | |
502 | spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); | |
503 | ||
504 | DP_VERBOSE(p_hwfn, | |
505 | QED_MSG_SP, | |
506 | "MFW mailbox: response 0x%08x param 0x%08x [after %d.%03d ms]\n", | |
507 | p_mb_params->mcp_resp, | |
508 | p_mb_params->mcp_param, | |
509 | (cnt * delay) / 1000, (cnt * delay) % 1000); | |
510 | ||
511 | /* Clear the sequence number from the MFW response */ | |
512 | p_mb_params->mcp_resp &= FW_MSG_CODE_MASK; | |
513 | ||
514 | return 0; | |
515 | ||
516 | err: | |
517 | spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock); | |
fe56b9e6 YM |
518 | return rc; |
519 | } | |
520 | ||
5529bad9 TT |
521 | static int qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn, |
522 | struct qed_ptt *p_ptt, | |
523 | struct qed_mcp_mb_params *p_mb_params) | |
fe56b9e6 | 524 | { |
2f67af8c | 525 | size_t union_data_size = sizeof(union drv_union_data); |
4ed1eea8 TT |
526 | u32 max_retries = QED_DRV_MB_MAX_RETRIES; |
527 | u32 delay = CHIP_MCP_RESP_ITER_US; | |
fe56b9e6 YM |
528 | |
529 | /* MCP not initialized */ | |
530 | if (!qed_mcp_is_init(p_hwfn)) { | |
525ef5c0 | 531 | DP_NOTICE(p_hwfn, "MFW is not initialized!\n"); |
fe56b9e6 YM |
532 | return -EBUSY; |
533 | } | |
534 | ||
2f67af8c TT |
535 | if (p_mb_params->data_src_size > union_data_size || |
536 | p_mb_params->data_dst_size > union_data_size) { | |
537 | DP_ERR(p_hwfn, | |
538 | "The provided size is larger than the union data size [src_size %u, dst_size %u, union_data_size %zu]\n", | |
539 | p_mb_params->data_src_size, | |
540 | p_mb_params->data_dst_size, union_data_size); | |
541 | return -EINVAL; | |
542 | } | |
543 | ||
4ed1eea8 TT |
544 | return _qed_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, max_retries, |
545 | delay); | |
fe56b9e6 YM |
546 | } |
547 | ||
5529bad9 TT |
548 | int qed_mcp_cmd(struct qed_hwfn *p_hwfn, |
549 | struct qed_ptt *p_ptt, | |
550 | u32 cmd, | |
551 | u32 param, | |
552 | u32 *o_mcp_resp, | |
553 | u32 *o_mcp_param) | |
fe56b9e6 | 554 | { |
5529bad9 TT |
555 | struct qed_mcp_mb_params mb_params; |
556 | int rc; | |
557 | ||
558 | memset(&mb_params, 0, sizeof(mb_params)); | |
559 | mb_params.cmd = cmd; | |
560 | mb_params.param = param; | |
14d39648 | 561 | |
5529bad9 TT |
562 | rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); |
563 | if (rc) | |
564 | return rc; | |
565 | ||
566 | *o_mcp_resp = mb_params.mcp_resp; | |
567 | *o_mcp_param = mb_params.mcp_param; | |
fe56b9e6 | 568 | |
5529bad9 | 569 | return 0; |
fe56b9e6 YM |
570 | } |
571 | ||
4102426f TT |
572 | int qed_mcp_nvm_rd_cmd(struct qed_hwfn *p_hwfn, |
573 | struct qed_ptt *p_ptt, | |
574 | u32 cmd, | |
575 | u32 param, | |
576 | u32 *o_mcp_resp, | |
577 | u32 *o_mcp_param, u32 *o_txn_size, u32 *o_buf) | |
578 | { | |
579 | struct qed_mcp_mb_params mb_params; | |
2f67af8c | 580 | u8 raw_data[MCP_DRV_NVM_BUF_LEN]; |
4102426f TT |
581 | int rc; |
582 | ||
583 | memset(&mb_params, 0, sizeof(mb_params)); | |
584 | mb_params.cmd = cmd; | |
585 | mb_params.param = param; | |
2f67af8c TT |
586 | mb_params.p_data_dst = raw_data; |
587 | ||
588 | /* Use the maximal value since the actual one is part of the response */ | |
589 | mb_params.data_dst_size = MCP_DRV_NVM_BUF_LEN; | |
590 | ||
4102426f TT |
591 | rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); |
592 | if (rc) | |
593 | return rc; | |
594 | ||
595 | *o_mcp_resp = mb_params.mcp_resp; | |
596 | *o_mcp_param = mb_params.mcp_param; | |
597 | ||
598 | *o_txn_size = *o_mcp_param; | |
2f67af8c | 599 | memcpy(o_buf, raw_data, *o_txn_size); |
4102426f TT |
600 | |
601 | return 0; | |
602 | } | |
603 | ||
5d24bcf1 TT |
604 | static bool |
605 | qed_mcp_can_force_load(u8 drv_role, | |
606 | u8 exist_drv_role, | |
607 | enum qed_override_force_load override_force_load) | |
608 | { | |
609 | bool can_force_load = false; | |
610 | ||
611 | switch (override_force_load) { | |
612 | case QED_OVERRIDE_FORCE_LOAD_ALWAYS: | |
613 | can_force_load = true; | |
614 | break; | |
615 | case QED_OVERRIDE_FORCE_LOAD_NEVER: | |
616 | can_force_load = false; | |
617 | break; | |
618 | default: | |
619 | can_force_load = (drv_role == DRV_ROLE_OS && | |
620 | exist_drv_role == DRV_ROLE_PREBOOT) || | |
621 | (drv_role == DRV_ROLE_KDUMP && | |
622 | exist_drv_role == DRV_ROLE_OS); | |
623 | break; | |
624 | } | |
625 | ||
626 | return can_force_load; | |
627 | } | |
628 | ||
629 | static int qed_mcp_cancel_load_req(struct qed_hwfn *p_hwfn, | |
630 | struct qed_ptt *p_ptt) | |
631 | { | |
632 | u32 resp = 0, param = 0; | |
633 | int rc; | |
634 | ||
635 | rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CANCEL_LOAD_REQ, 0, | |
636 | &resp, ¶m); | |
637 | if (rc) | |
638 | DP_NOTICE(p_hwfn, | |
639 | "Failed to send cancel load request, rc = %d\n", rc); | |
640 | ||
641 | return rc; | |
642 | } | |
643 | ||
644 | #define CONFIG_QEDE_BITMAP_IDX BIT(0) | |
645 | #define CONFIG_QED_SRIOV_BITMAP_IDX BIT(1) | |
646 | #define CONFIG_QEDR_BITMAP_IDX BIT(2) | |
647 | #define CONFIG_QEDF_BITMAP_IDX BIT(4) | |
648 | #define CONFIG_QEDI_BITMAP_IDX BIT(5) | |
649 | #define CONFIG_QED_LL2_BITMAP_IDX BIT(6) | |
650 | ||
651 | static u32 qed_get_config_bitmap(void) | |
652 | { | |
653 | u32 config_bitmap = 0x0; | |
654 | ||
655 | if (IS_ENABLED(CONFIG_QEDE)) | |
656 | config_bitmap |= CONFIG_QEDE_BITMAP_IDX; | |
657 | ||
658 | if (IS_ENABLED(CONFIG_QED_SRIOV)) | |
659 | config_bitmap |= CONFIG_QED_SRIOV_BITMAP_IDX; | |
660 | ||
661 | if (IS_ENABLED(CONFIG_QED_RDMA)) | |
662 | config_bitmap |= CONFIG_QEDR_BITMAP_IDX; | |
663 | ||
664 | if (IS_ENABLED(CONFIG_QED_FCOE)) | |
665 | config_bitmap |= CONFIG_QEDF_BITMAP_IDX; | |
666 | ||
667 | if (IS_ENABLED(CONFIG_QED_ISCSI)) | |
668 | config_bitmap |= CONFIG_QEDI_BITMAP_IDX; | |
669 | ||
670 | if (IS_ENABLED(CONFIG_QED_LL2)) | |
671 | config_bitmap |= CONFIG_QED_LL2_BITMAP_IDX; | |
672 | ||
673 | return config_bitmap; | |
674 | } | |
675 | ||
676 | struct qed_load_req_in_params { | |
677 | u8 hsi_ver; | |
678 | #define QED_LOAD_REQ_HSI_VER_DEFAULT 0 | |
679 | #define QED_LOAD_REQ_HSI_VER_1 1 | |
680 | u32 drv_ver_0; | |
681 | u32 drv_ver_1; | |
682 | u32 fw_ver; | |
683 | u8 drv_role; | |
684 | u8 timeout_val; | |
685 | u8 force_cmd; | |
686 | bool avoid_eng_reset; | |
687 | }; | |
688 | ||
689 | struct qed_load_req_out_params { | |
690 | u32 load_code; | |
691 | u32 exist_drv_ver_0; | |
692 | u32 exist_drv_ver_1; | |
693 | u32 exist_fw_ver; | |
694 | u8 exist_drv_role; | |
695 | u8 mfw_hsi_ver; | |
696 | bool drv_exists; | |
697 | }; | |
698 | ||
699 | static int | |
700 | __qed_mcp_load_req(struct qed_hwfn *p_hwfn, | |
701 | struct qed_ptt *p_ptt, | |
702 | struct qed_load_req_in_params *p_in_params, | |
703 | struct qed_load_req_out_params *p_out_params) | |
fe56b9e6 | 704 | { |
5529bad9 | 705 | struct qed_mcp_mb_params mb_params; |
5d24bcf1 TT |
706 | struct load_req_stc load_req; |
707 | struct load_rsp_stc load_rsp; | |
708 | u32 hsi_ver; | |
fe56b9e6 YM |
709 | int rc; |
710 | ||
5d24bcf1 TT |
711 | memset(&load_req, 0, sizeof(load_req)); |
712 | load_req.drv_ver_0 = p_in_params->drv_ver_0; | |
713 | load_req.drv_ver_1 = p_in_params->drv_ver_1; | |
714 | load_req.fw_ver = p_in_params->fw_ver; | |
715 | QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_ROLE, p_in_params->drv_role); | |
716 | QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_LOCK_TO, | |
717 | p_in_params->timeout_val); | |
718 | QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_FORCE, | |
719 | p_in_params->force_cmd); | |
720 | QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_FLAGS0, | |
721 | p_in_params->avoid_eng_reset); | |
722 | ||
723 | hsi_ver = (p_in_params->hsi_ver == QED_LOAD_REQ_HSI_VER_DEFAULT) ? | |
724 | DRV_ID_MCP_HSI_VER_CURRENT : | |
725 | (p_in_params->hsi_ver << DRV_ID_MCP_HSI_VER_SHIFT); | |
726 | ||
5529bad9 | 727 | memset(&mb_params, 0, sizeof(mb_params)); |
5529bad9 | 728 | mb_params.cmd = DRV_MSG_CODE_LOAD_REQ; |
5d24bcf1 TT |
729 | mb_params.param = PDA_COMP | hsi_ver | p_hwfn->cdev->drv_type; |
730 | mb_params.p_data_src = &load_req; | |
731 | mb_params.data_src_size = sizeof(load_req); | |
732 | mb_params.p_data_dst = &load_rsp; | |
733 | mb_params.data_dst_size = sizeof(load_rsp); | |
734 | ||
735 | DP_VERBOSE(p_hwfn, QED_MSG_SP, | |
736 | "Load Request: param 0x%08x [init_hw %d, drv_type %d, hsi_ver %d, pda 0x%04x]\n", | |
737 | mb_params.param, | |
738 | QED_MFW_GET_FIELD(mb_params.param, DRV_ID_DRV_INIT_HW), | |
739 | QED_MFW_GET_FIELD(mb_params.param, DRV_ID_DRV_TYPE), | |
740 | QED_MFW_GET_FIELD(mb_params.param, DRV_ID_MCP_HSI_VER), | |
741 | QED_MFW_GET_FIELD(mb_params.param, DRV_ID_PDA_COMP_VER)); | |
742 | ||
743 | if (p_in_params->hsi_ver != QED_LOAD_REQ_HSI_VER_1) { | |
744 | DP_VERBOSE(p_hwfn, QED_MSG_SP, | |
745 | "Load Request: drv_ver 0x%08x_0x%08x, fw_ver 0x%08x, misc0 0x%08x [role %d, timeout %d, force %d, flags0 0x%x]\n", | |
746 | load_req.drv_ver_0, | |
747 | load_req.drv_ver_1, | |
748 | load_req.fw_ver, | |
749 | load_req.misc0, | |
750 | QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_ROLE), | |
751 | QED_MFW_GET_FIELD(load_req.misc0, | |
752 | LOAD_REQ_LOCK_TO), | |
753 | QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_FORCE), | |
754 | QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_FLAGS0)); | |
755 | } | |
fe56b9e6 | 756 | |
5d24bcf1 | 757 | rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); |
fe56b9e6 | 758 | if (rc) { |
5d24bcf1 | 759 | DP_NOTICE(p_hwfn, "Failed to send load request, rc = %d\n", rc); |
fe56b9e6 YM |
760 | return rc; |
761 | } | |
762 | ||
5d24bcf1 TT |
763 | DP_VERBOSE(p_hwfn, QED_MSG_SP, |
764 | "Load Response: resp 0x%08x\n", mb_params.mcp_resp); | |
765 | p_out_params->load_code = mb_params.mcp_resp; | |
5529bad9 | 766 | |
5d24bcf1 TT |
767 | if (p_in_params->hsi_ver != QED_LOAD_REQ_HSI_VER_1 && |
768 | p_out_params->load_code != FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) { | |
769 | DP_VERBOSE(p_hwfn, | |
770 | QED_MSG_SP, | |
771 | "Load Response: exist_drv_ver 0x%08x_0x%08x, exist_fw_ver 0x%08x, misc0 0x%08x [exist_role %d, mfw_hsi %d, flags0 0x%x]\n", | |
772 | load_rsp.drv_ver_0, | |
773 | load_rsp.drv_ver_1, | |
774 | load_rsp.fw_ver, | |
775 | load_rsp.misc0, | |
776 | QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_ROLE), | |
777 | QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_HSI), | |
778 | QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0)); | |
779 | ||
780 | p_out_params->exist_drv_ver_0 = load_rsp.drv_ver_0; | |
781 | p_out_params->exist_drv_ver_1 = load_rsp.drv_ver_1; | |
782 | p_out_params->exist_fw_ver = load_rsp.fw_ver; | |
783 | p_out_params->exist_drv_role = | |
784 | QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_ROLE); | |
785 | p_out_params->mfw_hsi_ver = | |
786 | QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_HSI); | |
787 | p_out_params->drv_exists = | |
788 | QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0) & | |
789 | LOAD_RSP_FLAGS0_DRV_EXISTS; | |
790 | } | |
791 | ||
792 | return 0; | |
793 | } | |
794 | ||
795 | static int eocre_get_mfw_drv_role(struct qed_hwfn *p_hwfn, | |
796 | enum qed_drv_role drv_role, | |
797 | u8 *p_mfw_drv_role) | |
798 | { | |
799 | switch (drv_role) { | |
800 | case QED_DRV_ROLE_OS: | |
801 | *p_mfw_drv_role = DRV_ROLE_OS; | |
802 | break; | |
803 | case QED_DRV_ROLE_KDUMP: | |
804 | *p_mfw_drv_role = DRV_ROLE_KDUMP; | |
805 | break; | |
806 | default: | |
807 | DP_ERR(p_hwfn, "Unexpected driver role %d\n", drv_role); | |
808 | return -EINVAL; | |
809 | } | |
810 | ||
811 | return 0; | |
812 | } | |
813 | ||
814 | enum qed_load_req_force { | |
815 | QED_LOAD_REQ_FORCE_NONE, | |
816 | QED_LOAD_REQ_FORCE_PF, | |
817 | QED_LOAD_REQ_FORCE_ALL, | |
818 | }; | |
819 | ||
820 | static void qed_get_mfw_force_cmd(struct qed_hwfn *p_hwfn, | |
821 | ||
822 | enum qed_load_req_force force_cmd, | |
823 | u8 *p_mfw_force_cmd) | |
824 | { | |
825 | switch (force_cmd) { | |
826 | case QED_LOAD_REQ_FORCE_NONE: | |
827 | *p_mfw_force_cmd = LOAD_REQ_FORCE_NONE; | |
828 | break; | |
829 | case QED_LOAD_REQ_FORCE_PF: | |
830 | *p_mfw_force_cmd = LOAD_REQ_FORCE_PF; | |
831 | break; | |
832 | case QED_LOAD_REQ_FORCE_ALL: | |
833 | *p_mfw_force_cmd = LOAD_REQ_FORCE_ALL; | |
834 | break; | |
835 | } | |
836 | } | |
837 | ||
838 | int qed_mcp_load_req(struct qed_hwfn *p_hwfn, | |
839 | struct qed_ptt *p_ptt, | |
840 | struct qed_load_req_params *p_params) | |
841 | { | |
842 | struct qed_load_req_out_params out_params; | |
843 | struct qed_load_req_in_params in_params; | |
844 | u8 mfw_drv_role, mfw_force_cmd; | |
845 | int rc; | |
846 | ||
847 | memset(&in_params, 0, sizeof(in_params)); | |
848 | in_params.hsi_ver = QED_LOAD_REQ_HSI_VER_DEFAULT; | |
849 | in_params.drv_ver_0 = QED_VERSION; | |
850 | in_params.drv_ver_1 = qed_get_config_bitmap(); | |
851 | in_params.fw_ver = STORM_FW_VERSION; | |
852 | rc = eocre_get_mfw_drv_role(p_hwfn, p_params->drv_role, &mfw_drv_role); | |
853 | if (rc) | |
854 | return rc; | |
855 | ||
856 | in_params.drv_role = mfw_drv_role; | |
857 | in_params.timeout_val = p_params->timeout_val; | |
858 | qed_get_mfw_force_cmd(p_hwfn, | |
859 | QED_LOAD_REQ_FORCE_NONE, &mfw_force_cmd); | |
860 | ||
861 | in_params.force_cmd = mfw_force_cmd; | |
862 | in_params.avoid_eng_reset = p_params->avoid_eng_reset; | |
863 | ||
864 | memset(&out_params, 0, sizeof(out_params)); | |
865 | rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params, &out_params); | |
866 | if (rc) | |
867 | return rc; | |
868 | ||
869 | /* First handle cases where another load request should/might be sent: | |
870 | * - MFW expects the old interface [HSI version = 1] | |
871 | * - MFW responds that a force load request is required | |
872 | */ | |
873 | if (out_params.load_code == FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) { | |
874 | DP_INFO(p_hwfn, | |
875 | "MFW refused a load request due to HSI > 1. Resending with HSI = 1\n"); | |
876 | ||
877 | in_params.hsi_ver = QED_LOAD_REQ_HSI_VER_1; | |
878 | memset(&out_params, 0, sizeof(out_params)); | |
879 | rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params, &out_params); | |
880 | if (rc) | |
881 | return rc; | |
882 | } else if (out_params.load_code == | |
883 | FW_MSG_CODE_DRV_LOAD_REFUSED_REQUIRES_FORCE) { | |
884 | if (qed_mcp_can_force_load(in_params.drv_role, | |
885 | out_params.exist_drv_role, | |
886 | p_params->override_force_load)) { | |
887 | DP_INFO(p_hwfn, | |
888 | "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, x%08x_0x%08x}, existing={%d, 0x%08x, 0x%08x_0x%08x}]\n", | |
889 | in_params.drv_role, in_params.fw_ver, | |
890 | in_params.drv_ver_0, in_params.drv_ver_1, | |
891 | out_params.exist_drv_role, | |
892 | out_params.exist_fw_ver, | |
893 | out_params.exist_drv_ver_0, | |
894 | out_params.exist_drv_ver_1); | |
895 | ||
896 | qed_get_mfw_force_cmd(p_hwfn, | |
897 | QED_LOAD_REQ_FORCE_ALL, | |
898 | &mfw_force_cmd); | |
899 | ||
900 | in_params.force_cmd = mfw_force_cmd; | |
901 | memset(&out_params, 0, sizeof(out_params)); | |
902 | rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params, | |
903 | &out_params); | |
904 | if (rc) | |
905 | return rc; | |
906 | } else { | |
907 | DP_NOTICE(p_hwfn, | |
908 | "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, x%08x_0x%08x}, existing={%d, 0x%08x, 0x%08x_0x%08x}] - Avoid\n", | |
909 | in_params.drv_role, in_params.fw_ver, | |
910 | in_params.drv_ver_0, in_params.drv_ver_1, | |
911 | out_params.exist_drv_role, | |
912 | out_params.exist_fw_ver, | |
913 | out_params.exist_drv_ver_0, | |
914 | out_params.exist_drv_ver_1); | |
915 | DP_NOTICE(p_hwfn, | |
916 | "Avoid sending a force load request to prevent disruption of active PFs\n"); | |
917 | ||
918 | qed_mcp_cancel_load_req(p_hwfn, p_ptt); | |
919 | return -EBUSY; | |
920 | } | |
921 | } | |
922 | ||
923 | /* Now handle the other types of responses. | |
924 | * The "REFUSED_HSI_1" and "REFUSED_REQUIRES_FORCE" responses are not | |
925 | * expected here after the additional revised load requests were sent. | |
fe56b9e6 | 926 | */ |
5d24bcf1 TT |
927 | switch (out_params.load_code) { |
928 | case FW_MSG_CODE_DRV_LOAD_ENGINE: | |
929 | case FW_MSG_CODE_DRV_LOAD_PORT: | |
930 | case FW_MSG_CODE_DRV_LOAD_FUNCTION: | |
931 | if (out_params.mfw_hsi_ver != QED_LOAD_REQ_HSI_VER_1 && | |
932 | out_params.drv_exists) { | |
933 | /* The role and fw/driver version match, but the PF is | |
934 | * already loaded and has not been unloaded gracefully. | |
935 | */ | |
936 | DP_NOTICE(p_hwfn, | |
937 | "PF is already loaded\n"); | |
938 | return -EINVAL; | |
939 | } | |
940 | break; | |
941 | default: | |
942 | DP_NOTICE(p_hwfn, | |
943 | "Unexpected refusal to load request [resp 0x%08x]. Aborting.\n", | |
944 | out_params.load_code); | |
fe56b9e6 YM |
945 | return -EBUSY; |
946 | } | |
947 | ||
5d24bcf1 TT |
948 | p_params->load_code = out_params.load_code; |
949 | ||
fe56b9e6 YM |
950 | return 0; |
951 | } | |
952 | ||
1226337a TT |
953 | int qed_mcp_unload_req(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) |
954 | { | |
955 | u32 wol_param, mcp_resp, mcp_param; | |
956 | ||
957 | switch (p_hwfn->cdev->wol_config) { | |
958 | case QED_OV_WOL_DISABLED: | |
959 | wol_param = DRV_MB_PARAM_UNLOAD_WOL_DISABLED; | |
960 | break; | |
961 | case QED_OV_WOL_ENABLED: | |
962 | wol_param = DRV_MB_PARAM_UNLOAD_WOL_ENABLED; | |
963 | break; | |
964 | default: | |
965 | DP_NOTICE(p_hwfn, | |
966 | "Unknown WoL configuration %02x\n", | |
967 | p_hwfn->cdev->wol_config); | |
968 | /* Fallthrough */ | |
969 | case QED_OV_WOL_DEFAULT: | |
970 | wol_param = DRV_MB_PARAM_UNLOAD_WOL_MCP; | |
971 | } | |
972 | ||
973 | return qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_UNLOAD_REQ, wol_param, | |
974 | &mcp_resp, &mcp_param); | |
975 | } | |
976 | ||
977 | int qed_mcp_unload_done(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) | |
978 | { | |
979 | struct qed_mcp_mb_params mb_params; | |
980 | struct mcp_mac wol_mac; | |
981 | ||
982 | memset(&mb_params, 0, sizeof(mb_params)); | |
983 | mb_params.cmd = DRV_MSG_CODE_UNLOAD_DONE; | |
984 | ||
985 | /* Set the primary MAC if WoL is enabled */ | |
986 | if (p_hwfn->cdev->wol_config == QED_OV_WOL_ENABLED) { | |
987 | u8 *p_mac = p_hwfn->cdev->wol_mac; | |
988 | ||
989 | memset(&wol_mac, 0, sizeof(wol_mac)); | |
990 | wol_mac.mac_upper = p_mac[0] << 8 | p_mac[1]; | |
991 | wol_mac.mac_lower = p_mac[2] << 24 | p_mac[3] << 16 | | |
992 | p_mac[4] << 8 | p_mac[5]; | |
993 | ||
994 | DP_VERBOSE(p_hwfn, | |
995 | (QED_MSG_SP | NETIF_MSG_IFDOWN), | |
996 | "Setting WoL MAC: %pM --> [%08x,%08x]\n", | |
997 | p_mac, wol_mac.mac_upper, wol_mac.mac_lower); | |
998 | ||
999 | mb_params.p_data_src = &wol_mac; | |
1000 | mb_params.data_src_size = sizeof(wol_mac); | |
1001 | } | |
1002 | ||
1003 | return qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); | |
1004 | } | |
1005 | ||
0b55e27d YM |
1006 | static void qed_mcp_handle_vf_flr(struct qed_hwfn *p_hwfn, |
1007 | struct qed_ptt *p_ptt) | |
1008 | { | |
1009 | u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, | |
1010 | PUBLIC_PATH); | |
1011 | u32 mfw_path_offsize = qed_rd(p_hwfn, p_ptt, addr); | |
1012 | u32 path_addr = SECTION_ADDR(mfw_path_offsize, | |
1013 | QED_PATH_ID(p_hwfn)); | |
1014 | u32 disabled_vfs[VF_MAX_STATIC / 32]; | |
1015 | int i; | |
1016 | ||
1017 | DP_VERBOSE(p_hwfn, | |
1018 | QED_MSG_SP, | |
1019 | "Reading Disabled VF information from [offset %08x], path_addr %08x\n", | |
1020 | mfw_path_offsize, path_addr); | |
1021 | ||
1022 | for (i = 0; i < (VF_MAX_STATIC / 32); i++) { | |
1023 | disabled_vfs[i] = qed_rd(p_hwfn, p_ptt, | |
1024 | path_addr + | |
1025 | offsetof(struct public_path, | |
1026 | mcp_vf_disabled) + | |
1027 | sizeof(u32) * i); | |
1028 | DP_VERBOSE(p_hwfn, (QED_MSG_SP | QED_MSG_IOV), | |
1029 | "FLR-ed VFs [%08x,...,%08x] - %08x\n", | |
1030 | i * 32, (i + 1) * 32 - 1, disabled_vfs[i]); | |
1031 | } | |
1032 | ||
1033 | if (qed_iov_mark_vf_flr(p_hwfn, disabled_vfs)) | |
1034 | qed_schedule_iov(p_hwfn, QED_IOV_WQ_FLR_FLAG); | |
1035 | } | |
1036 | ||
1037 | int qed_mcp_ack_vf_flr(struct qed_hwfn *p_hwfn, | |
1038 | struct qed_ptt *p_ptt, u32 *vfs_to_ack) | |
1039 | { | |
1040 | u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, | |
1041 | PUBLIC_FUNC); | |
1042 | u32 mfw_func_offsize = qed_rd(p_hwfn, p_ptt, addr); | |
1043 | u32 func_addr = SECTION_ADDR(mfw_func_offsize, | |
1044 | MCP_PF_ID(p_hwfn)); | |
1045 | struct qed_mcp_mb_params mb_params; | |
0b55e27d YM |
1046 | int rc; |
1047 | int i; | |
1048 | ||
1049 | for (i = 0; i < (VF_MAX_STATIC / 32); i++) | |
1050 | DP_VERBOSE(p_hwfn, (QED_MSG_SP | QED_MSG_IOV), | |
1051 | "Acking VFs [%08x,...,%08x] - %08x\n", | |
1052 | i * 32, (i + 1) * 32 - 1, vfs_to_ack[i]); | |
1053 | ||
1054 | memset(&mb_params, 0, sizeof(mb_params)); | |
1055 | mb_params.cmd = DRV_MSG_CODE_VF_DISABLED_DONE; | |
2f67af8c TT |
1056 | mb_params.p_data_src = vfs_to_ack; |
1057 | mb_params.data_src_size = VF_MAX_STATIC / 8; | |
0b55e27d YM |
1058 | rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); |
1059 | if (rc) { | |
1060 | DP_NOTICE(p_hwfn, "Failed to pass ACK for VF flr to MFW\n"); | |
1061 | return -EBUSY; | |
1062 | } | |
1063 | ||
1064 | /* Clear the ACK bits */ | |
1065 | for (i = 0; i < (VF_MAX_STATIC / 32); i++) | |
1066 | qed_wr(p_hwfn, p_ptt, | |
1067 | func_addr + | |
1068 | offsetof(struct public_func, drv_ack_vf_disabled) + | |
1069 | i * sizeof(u32), 0); | |
1070 | ||
1071 | return rc; | |
1072 | } | |
1073 | ||
334c03b5 ZN |
1074 | static void qed_mcp_handle_transceiver_change(struct qed_hwfn *p_hwfn, |
1075 | struct qed_ptt *p_ptt) | |
1076 | { | |
1077 | u32 transceiver_state; | |
1078 | ||
1079 | transceiver_state = qed_rd(p_hwfn, p_ptt, | |
1080 | p_hwfn->mcp_info->port_addr + | |
1081 | offsetof(struct public_port, | |
1082 | transceiver_data)); | |
1083 | ||
1084 | DP_VERBOSE(p_hwfn, | |
1085 | (NETIF_MSG_HW | QED_MSG_SP), | |
1086 | "Received transceiver state update [0x%08x] from mfw [Addr 0x%x]\n", | |
1087 | transceiver_state, | |
1088 | (u32)(p_hwfn->mcp_info->port_addr + | |
1a635e48 | 1089 | offsetof(struct public_port, transceiver_data))); |
334c03b5 ZN |
1090 | |
1091 | transceiver_state = GET_FIELD(transceiver_state, | |
351a4ded | 1092 | ETH_TRANSCEIVER_STATE); |
334c03b5 | 1093 | |
351a4ded | 1094 | if (transceiver_state == ETH_TRANSCEIVER_STATE_PRESENT) |
334c03b5 ZN |
1095 | DP_NOTICE(p_hwfn, "Transceiver is present.\n"); |
1096 | else | |
1097 | DP_NOTICE(p_hwfn, "Transceiver is unplugged.\n"); | |
1098 | } | |
1099 | ||
cc875c2e | 1100 | static void qed_mcp_handle_link_change(struct qed_hwfn *p_hwfn, |
1a635e48 | 1101 | struct qed_ptt *p_ptt, bool b_reset) |
cc875c2e YM |
1102 | { |
1103 | struct qed_mcp_link_state *p_link; | |
a64b02d5 | 1104 | u8 max_bw, min_bw; |
cc875c2e YM |
1105 | u32 status = 0; |
1106 | ||
65ed2ffd MY |
1107 | /* Prevent SW/attentions from doing this at the same time */ |
1108 | spin_lock_bh(&p_hwfn->mcp_info->link_lock); | |
1109 | ||
cc875c2e YM |
1110 | p_link = &p_hwfn->mcp_info->link_output; |
1111 | memset(p_link, 0, sizeof(*p_link)); | |
1112 | if (!b_reset) { | |
1113 | status = qed_rd(p_hwfn, p_ptt, | |
1114 | p_hwfn->mcp_info->port_addr + | |
1115 | offsetof(struct public_port, link_status)); | |
1116 | DP_VERBOSE(p_hwfn, (NETIF_MSG_LINK | QED_MSG_SP), | |
1117 | "Received link update [0x%08x] from mfw [Addr 0x%x]\n", | |
1118 | status, | |
1119 | (u32)(p_hwfn->mcp_info->port_addr + | |
1a635e48 | 1120 | offsetof(struct public_port, link_status))); |
cc875c2e YM |
1121 | } else { |
1122 | DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, | |
1123 | "Resetting link indications\n"); | |
65ed2ffd | 1124 | goto out; |
cc875c2e YM |
1125 | } |
1126 | ||
fc916ff2 SRK |
1127 | if (p_hwfn->b_drv_link_init) |
1128 | p_link->link_up = !!(status & LINK_STATUS_LINK_UP); | |
1129 | else | |
1130 | p_link->link_up = false; | |
cc875c2e YM |
1131 | |
1132 | p_link->full_duplex = true; | |
1133 | switch ((status & LINK_STATUS_SPEED_AND_DUPLEX_MASK)) { | |
1134 | case LINK_STATUS_SPEED_AND_DUPLEX_100G: | |
1135 | p_link->speed = 100000; | |
1136 | break; | |
1137 | case LINK_STATUS_SPEED_AND_DUPLEX_50G: | |
1138 | p_link->speed = 50000; | |
1139 | break; | |
1140 | case LINK_STATUS_SPEED_AND_DUPLEX_40G: | |
1141 | p_link->speed = 40000; | |
1142 | break; | |
1143 | case LINK_STATUS_SPEED_AND_DUPLEX_25G: | |
1144 | p_link->speed = 25000; | |
1145 | break; | |
1146 | case LINK_STATUS_SPEED_AND_DUPLEX_20G: | |
1147 | p_link->speed = 20000; | |
1148 | break; | |
1149 | case LINK_STATUS_SPEED_AND_DUPLEX_10G: | |
1150 | p_link->speed = 10000; | |
1151 | break; | |
1152 | case LINK_STATUS_SPEED_AND_DUPLEX_1000THD: | |
1153 | p_link->full_duplex = false; | |
1154 | /* Fall-through */ | |
1155 | case LINK_STATUS_SPEED_AND_DUPLEX_1000TFD: | |
1156 | p_link->speed = 1000; | |
1157 | break; | |
1158 | default: | |
1159 | p_link->speed = 0; | |
1160 | } | |
1161 | ||
4b01e519 MC |
1162 | if (p_link->link_up && p_link->speed) |
1163 | p_link->line_speed = p_link->speed; | |
1164 | else | |
1165 | p_link->line_speed = 0; | |
1166 | ||
1167 | max_bw = p_hwfn->mcp_info->func_info.bandwidth_max; | |
a64b02d5 | 1168 | min_bw = p_hwfn->mcp_info->func_info.bandwidth_min; |
4b01e519 | 1169 | |
a64b02d5 | 1170 | /* Max bandwidth configuration */ |
4b01e519 | 1171 | __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt, p_link, max_bw); |
cc875c2e | 1172 | |
a64b02d5 MC |
1173 | /* Min bandwidth configuration */ |
1174 | __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt, p_link, min_bw); | |
6f437d43 MY |
1175 | qed_configure_vp_wfq_on_link_change(p_hwfn->cdev, p_ptt, |
1176 | p_link->min_pf_rate); | |
a64b02d5 | 1177 | |
cc875c2e YM |
1178 | p_link->an = !!(status & LINK_STATUS_AUTO_NEGOTIATE_ENABLED); |
1179 | p_link->an_complete = !!(status & | |
1180 | LINK_STATUS_AUTO_NEGOTIATE_COMPLETE); | |
1181 | p_link->parallel_detection = !!(status & | |
1182 | LINK_STATUS_PARALLEL_DETECTION_USED); | |
1183 | p_link->pfc_enabled = !!(status & LINK_STATUS_PFC_ENABLED); | |
1184 | ||
1185 | p_link->partner_adv_speed |= | |
1186 | (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) ? | |
1187 | QED_LINK_PARTNER_SPEED_1G_FD : 0; | |
1188 | p_link->partner_adv_speed |= | |
1189 | (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) ? | |
1190 | QED_LINK_PARTNER_SPEED_1G_HD : 0; | |
1191 | p_link->partner_adv_speed |= | |
1192 | (status & LINK_STATUS_LINK_PARTNER_10G_CAPABLE) ? | |
1193 | QED_LINK_PARTNER_SPEED_10G : 0; | |
1194 | p_link->partner_adv_speed |= | |
1195 | (status & LINK_STATUS_LINK_PARTNER_20G_CAPABLE) ? | |
1196 | QED_LINK_PARTNER_SPEED_20G : 0; | |
054c67d1 SRK |
1197 | p_link->partner_adv_speed |= |
1198 | (status & LINK_STATUS_LINK_PARTNER_25G_CAPABLE) ? | |
1199 | QED_LINK_PARTNER_SPEED_25G : 0; | |
cc875c2e YM |
1200 | p_link->partner_adv_speed |= |
1201 | (status & LINK_STATUS_LINK_PARTNER_40G_CAPABLE) ? | |
1202 | QED_LINK_PARTNER_SPEED_40G : 0; | |
1203 | p_link->partner_adv_speed |= | |
1204 | (status & LINK_STATUS_LINK_PARTNER_50G_CAPABLE) ? | |
1205 | QED_LINK_PARTNER_SPEED_50G : 0; | |
1206 | p_link->partner_adv_speed |= | |
1207 | (status & LINK_STATUS_LINK_PARTNER_100G_CAPABLE) ? | |
1208 | QED_LINK_PARTNER_SPEED_100G : 0; | |
1209 | ||
1210 | p_link->partner_tx_flow_ctrl_en = | |
1211 | !!(status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED); | |
1212 | p_link->partner_rx_flow_ctrl_en = | |
1213 | !!(status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED); | |
1214 | ||
1215 | switch (status & LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK) { | |
1216 | case LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE: | |
1217 | p_link->partner_adv_pause = QED_LINK_PARTNER_SYMMETRIC_PAUSE; | |
1218 | break; | |
1219 | case LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE: | |
1220 | p_link->partner_adv_pause = QED_LINK_PARTNER_ASYMMETRIC_PAUSE; | |
1221 | break; | |
1222 | case LINK_STATUS_LINK_PARTNER_BOTH_PAUSE: | |
1223 | p_link->partner_adv_pause = QED_LINK_PARTNER_BOTH_PAUSE; | |
1224 | break; | |
1225 | default: | |
1226 | p_link->partner_adv_pause = 0; | |
1227 | } | |
1228 | ||
1229 | p_link->sfp_tx_fault = !!(status & LINK_STATUS_SFP_TX_FAULT); | |
1230 | ||
1231 | qed_link_update(p_hwfn); | |
65ed2ffd MY |
1232 | out: |
1233 | spin_unlock_bh(&p_hwfn->mcp_info->link_lock); | |
cc875c2e YM |
1234 | } |
1235 | ||
351a4ded | 1236 | int qed_mcp_set_link(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, bool b_up) |
cc875c2e YM |
1237 | { |
1238 | struct qed_mcp_link_params *params = &p_hwfn->mcp_info->link_input; | |
5529bad9 | 1239 | struct qed_mcp_mb_params mb_params; |
2f67af8c | 1240 | struct eth_phy_cfg phy_cfg; |
cc875c2e | 1241 | int rc = 0; |
5529bad9 | 1242 | u32 cmd; |
cc875c2e YM |
1243 | |
1244 | /* Set the shmem configuration according to params */ | |
2f67af8c | 1245 | memset(&phy_cfg, 0, sizeof(phy_cfg)); |
cc875c2e YM |
1246 | cmd = b_up ? DRV_MSG_CODE_INIT_PHY : DRV_MSG_CODE_LINK_RESET; |
1247 | if (!params->speed.autoneg) | |
2f67af8c TT |
1248 | phy_cfg.speed = params->speed.forced_speed; |
1249 | phy_cfg.pause |= (params->pause.autoneg) ? ETH_PAUSE_AUTONEG : 0; | |
1250 | phy_cfg.pause |= (params->pause.forced_rx) ? ETH_PAUSE_RX : 0; | |
1251 | phy_cfg.pause |= (params->pause.forced_tx) ? ETH_PAUSE_TX : 0; | |
1252 | phy_cfg.adv_speed = params->speed.advertised_speeds; | |
1253 | phy_cfg.loopback_mode = params->loopback_mode; | |
cc875c2e | 1254 | |
fc916ff2 SRK |
1255 | p_hwfn->b_drv_link_init = b_up; |
1256 | ||
cc875c2e YM |
1257 | if (b_up) { |
1258 | DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, | |
1259 | "Configuring Link: Speed 0x%08x, Pause 0x%08x, adv_speed 0x%08x, loopback 0x%08x, features 0x%08x\n", | |
2f67af8c TT |
1260 | phy_cfg.speed, |
1261 | phy_cfg.pause, | |
1262 | phy_cfg.adv_speed, | |
1263 | phy_cfg.loopback_mode, | |
1264 | phy_cfg.feature_config_flags); | |
cc875c2e YM |
1265 | } else { |
1266 | DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, | |
1267 | "Resetting link\n"); | |
1268 | } | |
1269 | ||
5529bad9 TT |
1270 | memset(&mb_params, 0, sizeof(mb_params)); |
1271 | mb_params.cmd = cmd; | |
2f67af8c TT |
1272 | mb_params.p_data_src = &phy_cfg; |
1273 | mb_params.data_src_size = sizeof(phy_cfg); | |
5529bad9 | 1274 | rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); |
cc875c2e YM |
1275 | |
1276 | /* if mcp fails to respond we must abort */ | |
1277 | if (rc) { | |
1278 | DP_ERR(p_hwfn, "MCP response failure, aborting\n"); | |
1279 | return rc; | |
1280 | } | |
1281 | ||
65ed2ffd MY |
1282 | /* Mimic link-change attention, done for several reasons: |
1283 | * - On reset, there's no guarantee MFW would trigger | |
1284 | * an attention. | |
1285 | * - On initialization, older MFWs might not indicate link change | |
1286 | * during LFA, so we'll never get an UP indication. | |
1287 | */ | |
1288 | qed_mcp_handle_link_change(p_hwfn, p_ptt, !b_up); | |
cc875c2e YM |
1289 | |
1290 | return 0; | |
1291 | } | |
1292 | ||
6c754246 SRK |
1293 | static void qed_mcp_send_protocol_stats(struct qed_hwfn *p_hwfn, |
1294 | struct qed_ptt *p_ptt, | |
1295 | enum MFW_DRV_MSG_TYPE type) | |
1296 | { | |
1297 | enum qed_mcp_protocol_type stats_type; | |
1298 | union qed_mcp_protocol_stats stats; | |
1299 | struct qed_mcp_mb_params mb_params; | |
6c754246 SRK |
1300 | u32 hsi_param; |
1301 | ||
1302 | switch (type) { | |
1303 | case MFW_DRV_MSG_GET_LAN_STATS: | |
1304 | stats_type = QED_MCP_LAN_STATS; | |
1305 | hsi_param = DRV_MSG_CODE_STATS_TYPE_LAN; | |
1306 | break; | |
1307 | case MFW_DRV_MSG_GET_FCOE_STATS: | |
1308 | stats_type = QED_MCP_FCOE_STATS; | |
1309 | hsi_param = DRV_MSG_CODE_STATS_TYPE_FCOE; | |
1310 | break; | |
1311 | case MFW_DRV_MSG_GET_ISCSI_STATS: | |
1312 | stats_type = QED_MCP_ISCSI_STATS; | |
1313 | hsi_param = DRV_MSG_CODE_STATS_TYPE_ISCSI; | |
1314 | break; | |
1315 | case MFW_DRV_MSG_GET_RDMA_STATS: | |
1316 | stats_type = QED_MCP_RDMA_STATS; | |
1317 | hsi_param = DRV_MSG_CODE_STATS_TYPE_RDMA; | |
1318 | break; | |
1319 | default: | |
1320 | DP_NOTICE(p_hwfn, "Invalid protocol type %d\n", type); | |
1321 | return; | |
1322 | } | |
1323 | ||
1324 | qed_get_protocol_stats(p_hwfn->cdev, stats_type, &stats); | |
1325 | ||
1326 | memset(&mb_params, 0, sizeof(mb_params)); | |
1327 | mb_params.cmd = DRV_MSG_CODE_GET_STATS; | |
1328 | mb_params.param = hsi_param; | |
2f67af8c TT |
1329 | mb_params.p_data_src = &stats; |
1330 | mb_params.data_src_size = sizeof(stats); | |
6c754246 SRK |
1331 | qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); |
1332 | } | |
1333 | ||
4b01e519 MC |
1334 | static void qed_read_pf_bandwidth(struct qed_hwfn *p_hwfn, |
1335 | struct public_func *p_shmem_info) | |
1336 | { | |
1337 | struct qed_mcp_function_info *p_info; | |
1338 | ||
1339 | p_info = &p_hwfn->mcp_info->func_info; | |
1340 | ||
1341 | p_info->bandwidth_min = (p_shmem_info->config & | |
1342 | FUNC_MF_CFG_MIN_BW_MASK) >> | |
1343 | FUNC_MF_CFG_MIN_BW_SHIFT; | |
1344 | if (p_info->bandwidth_min < 1 || p_info->bandwidth_min > 100) { | |
1345 | DP_INFO(p_hwfn, | |
1346 | "bandwidth minimum out of bounds [%02x]. Set to 1\n", | |
1347 | p_info->bandwidth_min); | |
1348 | p_info->bandwidth_min = 1; | |
1349 | } | |
1350 | ||
1351 | p_info->bandwidth_max = (p_shmem_info->config & | |
1352 | FUNC_MF_CFG_MAX_BW_MASK) >> | |
1353 | FUNC_MF_CFG_MAX_BW_SHIFT; | |
1354 | if (p_info->bandwidth_max < 1 || p_info->bandwidth_max > 100) { | |
1355 | DP_INFO(p_hwfn, | |
1356 | "bandwidth maximum out of bounds [%02x]. Set to 100\n", | |
1357 | p_info->bandwidth_max); | |
1358 | p_info->bandwidth_max = 100; | |
1359 | } | |
1360 | } | |
1361 | ||
1362 | static u32 qed_mcp_get_shmem_func(struct qed_hwfn *p_hwfn, | |
1363 | struct qed_ptt *p_ptt, | |
1a635e48 | 1364 | struct public_func *p_data, int pfid) |
4b01e519 MC |
1365 | { |
1366 | u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, | |
1367 | PUBLIC_FUNC); | |
1368 | u32 mfw_path_offsize = qed_rd(p_hwfn, p_ptt, addr); | |
1369 | u32 func_addr = SECTION_ADDR(mfw_path_offsize, pfid); | |
1370 | u32 i, size; | |
1371 | ||
1372 | memset(p_data, 0, sizeof(*p_data)); | |
1373 | ||
1a635e48 | 1374 | size = min_t(u32, sizeof(*p_data), QED_SECTION_SIZE(mfw_path_offsize)); |
4b01e519 MC |
1375 | for (i = 0; i < size / sizeof(u32); i++) |
1376 | ((u32 *)p_data)[i] = qed_rd(p_hwfn, p_ptt, | |
1377 | func_addr + (i << 2)); | |
1378 | return size; | |
1379 | } | |
1380 | ||
1a635e48 | 1381 | static void qed_mcp_update_bw(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) |
4b01e519 MC |
1382 | { |
1383 | struct qed_mcp_function_info *p_info; | |
1384 | struct public_func shmem_info; | |
1385 | u32 resp = 0, param = 0; | |
1386 | ||
1a635e48 | 1387 | qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn)); |
4b01e519 MC |
1388 | |
1389 | qed_read_pf_bandwidth(p_hwfn, &shmem_info); | |
1390 | ||
1391 | p_info = &p_hwfn->mcp_info->func_info; | |
1392 | ||
a64b02d5 | 1393 | qed_configure_pf_min_bandwidth(p_hwfn->cdev, p_info->bandwidth_min); |
4b01e519 MC |
1394 | qed_configure_pf_max_bandwidth(p_hwfn->cdev, p_info->bandwidth_max); |
1395 | ||
1396 | /* Acknowledge the MFW */ | |
1397 | qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BW_UPDATE_ACK, 0, &resp, | |
1398 | ¶m); | |
1399 | } | |
1400 | ||
2a351fd9 MY |
1401 | static void qed_mcp_update_stag(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) |
1402 | { | |
1403 | struct public_func shmem_info; | |
1404 | u32 resp = 0, param = 0; | |
1405 | ||
1406 | qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn)); | |
1407 | ||
1408 | p_hwfn->mcp_info->func_info.ovlan = (u16)shmem_info.ovlan_stag & | |
1409 | FUNC_MF_CFG_OV_STAG_MASK; | |
1410 | p_hwfn->hw_info.ovlan = p_hwfn->mcp_info->func_info.ovlan; | |
1411 | if ((p_hwfn->hw_info.hw_mode & BIT(MODE_MF_SD)) && | |
1412 | (p_hwfn->hw_info.ovlan != QED_MCP_VLAN_UNSET)) { | |
1413 | qed_wr(p_hwfn, p_ptt, | |
1414 | NIG_REG_LLH_FUNC_TAG_VALUE, p_hwfn->hw_info.ovlan); | |
1415 | qed_sp_pf_update_stag(p_hwfn); | |
1416 | } | |
1417 | ||
1418 | /* Acknowledge the MFW */ | |
1419 | qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_S_TAG_UPDATE_ACK, 0, | |
1420 | &resp, ¶m); | |
1421 | } | |
1422 | ||
cc875c2e YM |
1423 | int qed_mcp_handle_events(struct qed_hwfn *p_hwfn, |
1424 | struct qed_ptt *p_ptt) | |
1425 | { | |
1426 | struct qed_mcp_info *info = p_hwfn->mcp_info; | |
1427 | int rc = 0; | |
1428 | bool found = false; | |
1429 | u16 i; | |
1430 | ||
1431 | DP_VERBOSE(p_hwfn, QED_MSG_SP, "Received message from MFW\n"); | |
1432 | ||
1433 | /* Read Messages from MFW */ | |
1434 | qed_mcp_read_mb(p_hwfn, p_ptt); | |
1435 | ||
1436 | /* Compare current messages to old ones */ | |
1437 | for (i = 0; i < info->mfw_mb_length; i++) { | |
1438 | if (info->mfw_mb_cur[i] == info->mfw_mb_shadow[i]) | |
1439 | continue; | |
1440 | ||
1441 | found = true; | |
1442 | ||
1443 | DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, | |
1444 | "Msg [%d] - old CMD 0x%02x, new CMD 0x%02x\n", | |
1445 | i, info->mfw_mb_shadow[i], info->mfw_mb_cur[i]); | |
1446 | ||
1447 | switch (i) { | |
1448 | case MFW_DRV_MSG_LINK_CHANGE: | |
1449 | qed_mcp_handle_link_change(p_hwfn, p_ptt, false); | |
1450 | break; | |
0b55e27d YM |
1451 | case MFW_DRV_MSG_VF_DISABLED: |
1452 | qed_mcp_handle_vf_flr(p_hwfn, p_ptt); | |
1453 | break; | |
39651abd SRK |
1454 | case MFW_DRV_MSG_LLDP_DATA_UPDATED: |
1455 | qed_dcbx_mib_update_event(p_hwfn, p_ptt, | |
1456 | QED_DCBX_REMOTE_LLDP_MIB); | |
1457 | break; | |
1458 | case MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED: | |
1459 | qed_dcbx_mib_update_event(p_hwfn, p_ptt, | |
1460 | QED_DCBX_REMOTE_MIB); | |
1461 | break; | |
1462 | case MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED: | |
1463 | qed_dcbx_mib_update_event(p_hwfn, p_ptt, | |
1464 | QED_DCBX_OPERATIONAL_MIB); | |
1465 | break; | |
334c03b5 ZN |
1466 | case MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE: |
1467 | qed_mcp_handle_transceiver_change(p_hwfn, p_ptt); | |
1468 | break; | |
6c754246 SRK |
1469 | case MFW_DRV_MSG_GET_LAN_STATS: |
1470 | case MFW_DRV_MSG_GET_FCOE_STATS: | |
1471 | case MFW_DRV_MSG_GET_ISCSI_STATS: | |
1472 | case MFW_DRV_MSG_GET_RDMA_STATS: | |
1473 | qed_mcp_send_protocol_stats(p_hwfn, p_ptt, i); | |
1474 | break; | |
4b01e519 MC |
1475 | case MFW_DRV_MSG_BW_UPDATE: |
1476 | qed_mcp_update_bw(p_hwfn, p_ptt); | |
1477 | break; | |
2a351fd9 MY |
1478 | case MFW_DRV_MSG_S_TAG_UPDATE: |
1479 | qed_mcp_update_stag(p_hwfn, p_ptt); | |
1480 | break; | |
1481 | break; | |
cc875c2e | 1482 | default: |
39815944 | 1483 | DP_INFO(p_hwfn, "Unimplemented MFW message %d\n", i); |
cc875c2e YM |
1484 | rc = -EINVAL; |
1485 | } | |
1486 | } | |
1487 | ||
1488 | /* ACK everything */ | |
1489 | for (i = 0; i < MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length); i++) { | |
1490 | __be32 val = cpu_to_be32(((u32 *)info->mfw_mb_cur)[i]); | |
1491 | ||
1492 | /* MFW expect answer in BE, so we force write in that format */ | |
1493 | qed_wr(p_hwfn, p_ptt, | |
1494 | info->mfw_mb_addr + sizeof(u32) + | |
1495 | MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length) * | |
1496 | sizeof(u32) + i * sizeof(u32), | |
1497 | (__force u32)val); | |
1498 | } | |
1499 | ||
1500 | if (!found) { | |
1501 | DP_NOTICE(p_hwfn, | |
1502 | "Received an MFW message indication but no new message!\n"); | |
1503 | rc = -EINVAL; | |
1504 | } | |
1505 | ||
1506 | /* Copy the new mfw messages into the shadow */ | |
1507 | memcpy(info->mfw_mb_shadow, info->mfw_mb_cur, info->mfw_mb_length); | |
1508 | ||
1509 | return rc; | |
1510 | } | |
1511 | ||
1408cc1f YM |
1512 | int qed_mcp_get_mfw_ver(struct qed_hwfn *p_hwfn, |
1513 | struct qed_ptt *p_ptt, | |
1514 | u32 *p_mfw_ver, u32 *p_running_bundle_id) | |
fe56b9e6 | 1515 | { |
fe56b9e6 YM |
1516 | u32 global_offsize; |
1517 | ||
1408cc1f YM |
1518 | if (IS_VF(p_hwfn->cdev)) { |
1519 | if (p_hwfn->vf_iov_info) { | |
1520 | struct pfvf_acquire_resp_tlv *p_resp; | |
1521 | ||
1522 | p_resp = &p_hwfn->vf_iov_info->acquire_resp; | |
1523 | *p_mfw_ver = p_resp->pfdev_info.mfw_ver; | |
1524 | return 0; | |
1525 | } else { | |
1526 | DP_VERBOSE(p_hwfn, | |
1527 | QED_MSG_IOV, | |
1528 | "VF requested MFW version prior to ACQUIRE\n"); | |
1529 | return -EINVAL; | |
1530 | } | |
1531 | } | |
fe56b9e6 YM |
1532 | |
1533 | global_offsize = qed_rd(p_hwfn, p_ptt, | |
1408cc1f YM |
1534 | SECTION_OFFSIZE_ADDR(p_hwfn-> |
1535 | mcp_info->public_base, | |
fe56b9e6 | 1536 | PUBLIC_GLOBAL)); |
1408cc1f YM |
1537 | *p_mfw_ver = |
1538 | qed_rd(p_hwfn, p_ptt, | |
1539 | SECTION_ADDR(global_offsize, | |
1540 | 0) + offsetof(struct public_global, mfw_ver)); | |
1541 | ||
1542 | if (p_running_bundle_id != NULL) { | |
1543 | *p_running_bundle_id = qed_rd(p_hwfn, p_ptt, | |
1544 | SECTION_ADDR(global_offsize, 0) + | |
1545 | offsetof(struct public_global, | |
1546 | running_bundle_id)); | |
1547 | } | |
fe56b9e6 YM |
1548 | |
1549 | return 0; | |
1550 | } | |
1551 | ||
ae33666a TT |
1552 | int qed_mcp_get_mbi_ver(struct qed_hwfn *p_hwfn, |
1553 | struct qed_ptt *p_ptt, u32 *p_mbi_ver) | |
1554 | { | |
1555 | u32 nvm_cfg_addr, nvm_cfg1_offset, mbi_ver_addr; | |
1556 | ||
1557 | if (IS_VF(p_hwfn->cdev)) | |
1558 | return -EINVAL; | |
1559 | ||
1560 | /* Read the address of the nvm_cfg */ | |
1561 | nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0); | |
1562 | if (!nvm_cfg_addr) { | |
1563 | DP_NOTICE(p_hwfn, "Shared memory not initialized\n"); | |
1564 | return -EINVAL; | |
1565 | } | |
1566 | ||
1567 | /* Read the offset of nvm_cfg1 */ | |
1568 | nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4); | |
1569 | ||
1570 | mbi_ver_addr = MCP_REG_SCRATCH + nvm_cfg1_offset + | |
1571 | offsetof(struct nvm_cfg1, glob) + | |
1572 | offsetof(struct nvm_cfg1_glob, mbi_version); | |
1573 | *p_mbi_ver = qed_rd(p_hwfn, p_ptt, | |
1574 | mbi_ver_addr) & | |
1575 | (NVM_CFG1_GLOB_MBI_VERSION_0_MASK | | |
1576 | NVM_CFG1_GLOB_MBI_VERSION_1_MASK | | |
1577 | NVM_CFG1_GLOB_MBI_VERSION_2_MASK); | |
1578 | ||
1579 | return 0; | |
1580 | } | |
1581 | ||
1a635e48 | 1582 | int qed_mcp_get_media_type(struct qed_dev *cdev, u32 *p_media_type) |
cc875c2e YM |
1583 | { |
1584 | struct qed_hwfn *p_hwfn = &cdev->hwfns[0]; | |
1585 | struct qed_ptt *p_ptt; | |
1586 | ||
1408cc1f YM |
1587 | if (IS_VF(cdev)) |
1588 | return -EINVAL; | |
1589 | ||
cc875c2e | 1590 | if (!qed_mcp_is_init(p_hwfn)) { |
525ef5c0 | 1591 | DP_NOTICE(p_hwfn, "MFW is not initialized!\n"); |
cc875c2e YM |
1592 | return -EBUSY; |
1593 | } | |
1594 | ||
1595 | *p_media_type = MEDIA_UNSPECIFIED; | |
1596 | ||
1597 | p_ptt = qed_ptt_acquire(p_hwfn); | |
1598 | if (!p_ptt) | |
1599 | return -EBUSY; | |
1600 | ||
1601 | *p_media_type = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr + | |
1602 | offsetof(struct public_port, media_type)); | |
1603 | ||
1604 | qed_ptt_release(p_hwfn, p_ptt); | |
1605 | ||
1606 | return 0; | |
1607 | } | |
1608 | ||
6927e826 MY |
1609 | /* Old MFW has a global configuration for all PFs regarding RDMA support */ |
1610 | static void | |
1611 | qed_mcp_get_shmem_proto_legacy(struct qed_hwfn *p_hwfn, | |
1612 | enum qed_pci_personality *p_proto) | |
1613 | { | |
1614 | /* There wasn't ever a legacy MFW that published iwarp. | |
1615 | * So at this point, this is either plain l2 or RoCE. | |
1616 | */ | |
1617 | if (test_bit(QED_DEV_CAP_ROCE, &p_hwfn->hw_info.device_capabilities)) | |
1618 | *p_proto = QED_PCI_ETH_ROCE; | |
1619 | else | |
1620 | *p_proto = QED_PCI_ETH; | |
1621 | ||
1622 | DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP, | |
1623 | "According to Legacy capabilities, L2 personality is %08x\n", | |
1624 | (u32) *p_proto); | |
1625 | } | |
1626 | ||
1627 | static int | |
1628 | qed_mcp_get_shmem_proto_mfw(struct qed_hwfn *p_hwfn, | |
1629 | struct qed_ptt *p_ptt, | |
1630 | enum qed_pci_personality *p_proto) | |
1631 | { | |
1632 | u32 resp = 0, param = 0; | |
1633 | int rc; | |
1634 | ||
1635 | rc = qed_mcp_cmd(p_hwfn, p_ptt, | |
1636 | DRV_MSG_CODE_GET_PF_RDMA_PROTOCOL, 0, &resp, ¶m); | |
1637 | if (rc) | |
1638 | return rc; | |
1639 | if (resp != FW_MSG_CODE_OK) { | |
1640 | DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP, | |
1641 | "MFW lacks support for command; Returns %08x\n", | |
1642 | resp); | |
1643 | return -EINVAL; | |
1644 | } | |
1645 | ||
1646 | switch (param) { | |
1647 | case FW_MB_PARAM_GET_PF_RDMA_NONE: | |
1648 | *p_proto = QED_PCI_ETH; | |
1649 | break; | |
1650 | case FW_MB_PARAM_GET_PF_RDMA_ROCE: | |
1651 | *p_proto = QED_PCI_ETH_ROCE; | |
1652 | break; | |
1653 | case FW_MB_PARAM_GET_PF_RDMA_BOTH: | |
1654 | DP_NOTICE(p_hwfn, | |
1655 | "Current day drivers don't support RoCE & iWARP. Default to RoCE-only\n"); | |
1656 | *p_proto = QED_PCI_ETH_ROCE; | |
1657 | break; | |
1658 | case FW_MB_PARAM_GET_PF_RDMA_IWARP: | |
1659 | default: | |
1660 | DP_NOTICE(p_hwfn, | |
1661 | "MFW answers GET_PF_RDMA_PROTOCOL but param is %08x\n", | |
1662 | param); | |
1663 | return -EINVAL; | |
1664 | } | |
1665 | ||
1666 | DP_VERBOSE(p_hwfn, | |
1667 | NETIF_MSG_IFUP, | |
1668 | "According to capabilities, L2 personality is %08x [resp %08x param %08x]\n", | |
1669 | (u32) *p_proto, resp, param); | |
1670 | return 0; | |
1671 | } | |
1672 | ||
fe56b9e6 YM |
1673 | static int |
1674 | qed_mcp_get_shmem_proto(struct qed_hwfn *p_hwfn, | |
1675 | struct public_func *p_info, | |
6927e826 | 1676 | struct qed_ptt *p_ptt, |
fe56b9e6 YM |
1677 | enum qed_pci_personality *p_proto) |
1678 | { | |
1679 | int rc = 0; | |
1680 | ||
1681 | switch (p_info->config & FUNC_MF_CFG_PROTOCOL_MASK) { | |
1682 | case FUNC_MF_CFG_PROTOCOL_ETHERNET: | |
1fe582ec RA |
1683 | if (!IS_ENABLED(CONFIG_QED_RDMA)) |
1684 | *p_proto = QED_PCI_ETH; | |
1685 | else if (qed_mcp_get_shmem_proto_mfw(p_hwfn, p_ptt, p_proto)) | |
6927e826 | 1686 | qed_mcp_get_shmem_proto_legacy(p_hwfn, p_proto); |
c5ac9319 YM |
1687 | break; |
1688 | case FUNC_MF_CFG_PROTOCOL_ISCSI: | |
1689 | *p_proto = QED_PCI_ISCSI; | |
1690 | break; | |
1e128c81 AE |
1691 | case FUNC_MF_CFG_PROTOCOL_FCOE: |
1692 | *p_proto = QED_PCI_FCOE; | |
1693 | break; | |
c5ac9319 YM |
1694 | case FUNC_MF_CFG_PROTOCOL_ROCE: |
1695 | DP_NOTICE(p_hwfn, "RoCE personality is not a valid value!\n"); | |
6927e826 | 1696 | /* Fallthrough */ |
fe56b9e6 YM |
1697 | default: |
1698 | rc = -EINVAL; | |
1699 | } | |
1700 | ||
1701 | return rc; | |
1702 | } | |
1703 | ||
1704 | int qed_mcp_fill_shmem_func_info(struct qed_hwfn *p_hwfn, | |
1705 | struct qed_ptt *p_ptt) | |
1706 | { | |
1707 | struct qed_mcp_function_info *info; | |
1708 | struct public_func shmem_info; | |
1709 | ||
1a635e48 | 1710 | qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn)); |
fe56b9e6 YM |
1711 | info = &p_hwfn->mcp_info->func_info; |
1712 | ||
1713 | info->pause_on_host = (shmem_info.config & | |
1714 | FUNC_MF_CFG_PAUSE_ON_HOST_RING) ? 1 : 0; | |
1715 | ||
6927e826 MY |
1716 | if (qed_mcp_get_shmem_proto(p_hwfn, &shmem_info, p_ptt, |
1717 | &info->protocol)) { | |
fe56b9e6 YM |
1718 | DP_ERR(p_hwfn, "Unknown personality %08x\n", |
1719 | (u32)(shmem_info.config & FUNC_MF_CFG_PROTOCOL_MASK)); | |
1720 | return -EINVAL; | |
1721 | } | |
1722 | ||
4b01e519 | 1723 | qed_read_pf_bandwidth(p_hwfn, &shmem_info); |
fe56b9e6 YM |
1724 | |
1725 | if (shmem_info.mac_upper || shmem_info.mac_lower) { | |
1726 | info->mac[0] = (u8)(shmem_info.mac_upper >> 8); | |
1727 | info->mac[1] = (u8)(shmem_info.mac_upper); | |
1728 | info->mac[2] = (u8)(shmem_info.mac_lower >> 24); | |
1729 | info->mac[3] = (u8)(shmem_info.mac_lower >> 16); | |
1730 | info->mac[4] = (u8)(shmem_info.mac_lower >> 8); | |
1731 | info->mac[5] = (u8)(shmem_info.mac_lower); | |
14d39648 MY |
1732 | |
1733 | /* Store primary MAC for later possible WoL */ | |
1734 | memcpy(&p_hwfn->cdev->wol_mac, info->mac, ETH_ALEN); | |
fe56b9e6 YM |
1735 | } else { |
1736 | DP_NOTICE(p_hwfn, "MAC is 0 in shmem\n"); | |
1737 | } | |
1738 | ||
57796759 MY |
1739 | info->wwn_port = (u64)shmem_info.fcoe_wwn_port_name_lower | |
1740 | (((u64)shmem_info.fcoe_wwn_port_name_upper) << 32); | |
1741 | info->wwn_node = (u64)shmem_info.fcoe_wwn_node_name_lower | | |
1742 | (((u64)shmem_info.fcoe_wwn_node_name_upper) << 32); | |
fe56b9e6 YM |
1743 | |
1744 | info->ovlan = (u16)(shmem_info.ovlan_stag & FUNC_MF_CFG_OV_STAG_MASK); | |
1745 | ||
0fefbfba SK |
1746 | info->mtu = (u16)shmem_info.mtu_size; |
1747 | ||
14d39648 MY |
1748 | p_hwfn->hw_info.b_wol_support = QED_WOL_SUPPORT_NONE; |
1749 | p_hwfn->cdev->wol_config = (u8)QED_OV_WOL_DEFAULT; | |
1750 | if (qed_mcp_is_init(p_hwfn)) { | |
1751 | u32 resp = 0, param = 0; | |
1752 | int rc; | |
1753 | ||
1754 | rc = qed_mcp_cmd(p_hwfn, p_ptt, | |
1755 | DRV_MSG_CODE_OS_WOL, 0, &resp, ¶m); | |
1756 | if (rc) | |
1757 | return rc; | |
1758 | if (resp == FW_MSG_CODE_OS_WOL_SUPPORTED) | |
1759 | p_hwfn->hw_info.b_wol_support = QED_WOL_SUPPORT_PME; | |
1760 | } | |
1761 | ||
fe56b9e6 | 1762 | DP_VERBOSE(p_hwfn, (QED_MSG_SP | NETIF_MSG_IFUP), |
14d39648 | 1763 | "Read configuration from shmem: pause_on_host %02x protocol %02x BW [%02x - %02x] MAC %02x:%02x:%02x:%02x:%02x:%02x wwn port %llx node %llx ovlan %04x wol %02x\n", |
fe56b9e6 YM |
1764 | info->pause_on_host, info->protocol, |
1765 | info->bandwidth_min, info->bandwidth_max, | |
1766 | info->mac[0], info->mac[1], info->mac[2], | |
1767 | info->mac[3], info->mac[4], info->mac[5], | |
14d39648 MY |
1768 | info->wwn_port, info->wwn_node, |
1769 | info->ovlan, (u8)p_hwfn->hw_info.b_wol_support); | |
fe56b9e6 YM |
1770 | |
1771 | return 0; | |
1772 | } | |
1773 | ||
cc875c2e YM |
1774 | struct qed_mcp_link_params |
1775 | *qed_mcp_get_link_params(struct qed_hwfn *p_hwfn) | |
1776 | { | |
1777 | if (!p_hwfn || !p_hwfn->mcp_info) | |
1778 | return NULL; | |
1779 | return &p_hwfn->mcp_info->link_input; | |
1780 | } | |
1781 | ||
1782 | struct qed_mcp_link_state | |
1783 | *qed_mcp_get_link_state(struct qed_hwfn *p_hwfn) | |
1784 | { | |
1785 | if (!p_hwfn || !p_hwfn->mcp_info) | |
1786 | return NULL; | |
1787 | return &p_hwfn->mcp_info->link_output; | |
1788 | } | |
1789 | ||
1790 | struct qed_mcp_link_capabilities | |
1791 | *qed_mcp_get_link_capabilities(struct qed_hwfn *p_hwfn) | |
1792 | { | |
1793 | if (!p_hwfn || !p_hwfn->mcp_info) | |
1794 | return NULL; | |
1795 | return &p_hwfn->mcp_info->link_capabilities; | |
1796 | } | |
1797 | ||
1a635e48 | 1798 | int qed_mcp_drain(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) |
fe56b9e6 YM |
1799 | { |
1800 | u32 resp = 0, param = 0; | |
1801 | int rc; | |
1802 | ||
1803 | rc = qed_mcp_cmd(p_hwfn, p_ptt, | |
1a635e48 | 1804 | DRV_MSG_CODE_NIG_DRAIN, 1000, &resp, ¶m); |
fe56b9e6 YM |
1805 | |
1806 | /* Wait for the drain to complete before returning */ | |
8f60bafe | 1807 | msleep(1020); |
fe56b9e6 YM |
1808 | |
1809 | return rc; | |
1810 | } | |
1811 | ||
cee4d264 | 1812 | int qed_mcp_get_flash_size(struct qed_hwfn *p_hwfn, |
1a635e48 | 1813 | struct qed_ptt *p_ptt, u32 *p_flash_size) |
cee4d264 MC |
1814 | { |
1815 | u32 flash_size; | |
1816 | ||
1408cc1f YM |
1817 | if (IS_VF(p_hwfn->cdev)) |
1818 | return -EINVAL; | |
1819 | ||
cee4d264 MC |
1820 | flash_size = qed_rd(p_hwfn, p_ptt, MCP_REG_NVM_CFG4); |
1821 | flash_size = (flash_size & MCP_REG_NVM_CFG4_FLASH_SIZE) >> | |
1822 | MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT; | |
1823 | flash_size = (1 << (flash_size + MCP_BYTES_PER_MBIT_SHIFT)); | |
1824 | ||
1825 | *p_flash_size = flash_size; | |
1826 | ||
1827 | return 0; | |
1828 | } | |
1829 | ||
88072fd4 MY |
1830 | static int |
1831 | qed_mcp_config_vf_msix_bb(struct qed_hwfn *p_hwfn, | |
1832 | struct qed_ptt *p_ptt, u8 vf_id, u8 num) | |
1408cc1f YM |
1833 | { |
1834 | u32 resp = 0, param = 0, rc_param = 0; | |
1835 | int rc; | |
1836 | ||
1837 | /* Only Leader can configure MSIX, and need to take CMT into account */ | |
1838 | if (!IS_LEAD_HWFN(p_hwfn)) | |
1839 | return 0; | |
1840 | num *= p_hwfn->cdev->num_hwfns; | |
1841 | ||
1842 | param |= (vf_id << DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT) & | |
1843 | DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK; | |
1844 | param |= (num << DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT) & | |
1845 | DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK; | |
1846 | ||
1847 | rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_VF_MSIX, param, | |
1848 | &resp, &rc_param); | |
1849 | ||
1850 | if (resp != FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE) { | |
1851 | DP_NOTICE(p_hwfn, "VF[%d]: MFW failed to set MSI-X\n", vf_id); | |
1852 | rc = -EINVAL; | |
1853 | } else { | |
1854 | DP_VERBOSE(p_hwfn, QED_MSG_IOV, | |
1855 | "Requested 0x%02x MSI-x interrupts from VF 0x%02x\n", | |
1856 | num, vf_id); | |
1857 | } | |
1858 | ||
1859 | return rc; | |
1860 | } | |
1861 | ||
88072fd4 MY |
1862 | static int |
1863 | qed_mcp_config_vf_msix_ah(struct qed_hwfn *p_hwfn, | |
1864 | struct qed_ptt *p_ptt, u8 num) | |
1865 | { | |
1866 | u32 resp = 0, param = num, rc_param = 0; | |
1867 | int rc; | |
1868 | ||
1869 | rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_PF_VFS_MSIX, | |
1870 | param, &resp, &rc_param); | |
1871 | ||
1872 | if (resp != FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_DONE) { | |
1873 | DP_NOTICE(p_hwfn, "MFW failed to set MSI-X for VFs\n"); | |
1874 | rc = -EINVAL; | |
1875 | } else { | |
1876 | DP_VERBOSE(p_hwfn, QED_MSG_IOV, | |
1877 | "Requested 0x%02x MSI-x interrupts for VFs\n", num); | |
1878 | } | |
1879 | ||
1880 | return rc; | |
1881 | } | |
1882 | ||
1883 | int qed_mcp_config_vf_msix(struct qed_hwfn *p_hwfn, | |
1884 | struct qed_ptt *p_ptt, u8 vf_id, u8 num) | |
1885 | { | |
1886 | if (QED_IS_BB(p_hwfn->cdev)) | |
1887 | return qed_mcp_config_vf_msix_bb(p_hwfn, p_ptt, vf_id, num); | |
1888 | else | |
1889 | return qed_mcp_config_vf_msix_ah(p_hwfn, p_ptt, num); | |
1890 | } | |
1891 | ||
fe56b9e6 YM |
1892 | int |
1893 | qed_mcp_send_drv_version(struct qed_hwfn *p_hwfn, | |
1894 | struct qed_ptt *p_ptt, | |
1895 | struct qed_mcp_drv_version *p_ver) | |
1896 | { | |
5529bad9 | 1897 | struct qed_mcp_mb_params mb_params; |
2f67af8c | 1898 | struct drv_version_stc drv_version; |
5529bad9 TT |
1899 | __be32 val; |
1900 | u32 i; | |
1901 | int rc; | |
fe56b9e6 | 1902 | |
2f67af8c TT |
1903 | memset(&drv_version, 0, sizeof(drv_version)); |
1904 | drv_version.version = p_ver->version; | |
67a99b70 YM |
1905 | for (i = 0; i < (MCP_DRV_VER_STR_SIZE - 4) / sizeof(u32); i++) { |
1906 | val = cpu_to_be32(*((u32 *)&p_ver->name[i * sizeof(u32)])); | |
2f67af8c | 1907 | *(__be32 *)&drv_version.name[i * sizeof(u32)] = val; |
fe56b9e6 YM |
1908 | } |
1909 | ||
5529bad9 TT |
1910 | memset(&mb_params, 0, sizeof(mb_params)); |
1911 | mb_params.cmd = DRV_MSG_CODE_SET_VERSION; | |
2f67af8c TT |
1912 | mb_params.p_data_src = &drv_version; |
1913 | mb_params.data_src_size = sizeof(drv_version); | |
5529bad9 TT |
1914 | rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); |
1915 | if (rc) | |
fe56b9e6 | 1916 | DP_ERR(p_hwfn, "MCP response failure, aborting\n"); |
fe56b9e6 | 1917 | |
5529bad9 | 1918 | return rc; |
fe56b9e6 | 1919 | } |
91420b83 | 1920 | |
4102426f TT |
1921 | int qed_mcp_halt(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) |
1922 | { | |
1923 | u32 resp = 0, param = 0; | |
1924 | int rc; | |
1925 | ||
1926 | rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MCP_HALT, 0, &resp, | |
1927 | ¶m); | |
1928 | if (rc) | |
1929 | DP_ERR(p_hwfn, "MCP response failure, aborting\n"); | |
1930 | ||
1931 | return rc; | |
1932 | } | |
1933 | ||
1934 | int qed_mcp_resume(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) | |
1935 | { | |
1936 | u32 value, cpu_mode; | |
1937 | ||
1938 | qed_wr(p_hwfn, p_ptt, MCP_REG_CPU_STATE, 0xffffffff); | |
1939 | ||
1940 | value = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE); | |
1941 | value &= ~MCP_REG_CPU_MODE_SOFT_HALT; | |
1942 | qed_wr(p_hwfn, p_ptt, MCP_REG_CPU_MODE, value); | |
1943 | cpu_mode = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE); | |
1944 | ||
1945 | return (cpu_mode & MCP_REG_CPU_MODE_SOFT_HALT) ? -EAGAIN : 0; | |
1946 | } | |
1947 | ||
0fefbfba SK |
1948 | int qed_mcp_ov_update_current_config(struct qed_hwfn *p_hwfn, |
1949 | struct qed_ptt *p_ptt, | |
1950 | enum qed_ov_client client) | |
1951 | { | |
1952 | u32 resp = 0, param = 0; | |
1953 | u32 drv_mb_param; | |
1954 | int rc; | |
1955 | ||
1956 | switch (client) { | |
1957 | case QED_OV_CLIENT_DRV: | |
1958 | drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OS; | |
1959 | break; | |
1960 | case QED_OV_CLIENT_USER: | |
1961 | drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OTHER; | |
1962 | break; | |
1963 | case QED_OV_CLIENT_VENDOR_SPEC: | |
1964 | drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC; | |
1965 | break; | |
1966 | default: | |
1967 | DP_NOTICE(p_hwfn, "Invalid client type %d\n", client); | |
1968 | return -EINVAL; | |
1969 | } | |
1970 | ||
1971 | rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_CURR_CFG, | |
1972 | drv_mb_param, &resp, ¶m); | |
1973 | if (rc) | |
1974 | DP_ERR(p_hwfn, "MCP response failure, aborting\n"); | |
1975 | ||
1976 | return rc; | |
1977 | } | |
1978 | ||
1979 | int qed_mcp_ov_update_driver_state(struct qed_hwfn *p_hwfn, | |
1980 | struct qed_ptt *p_ptt, | |
1981 | enum qed_ov_driver_state drv_state) | |
1982 | { | |
1983 | u32 resp = 0, param = 0; | |
1984 | u32 drv_mb_param; | |
1985 | int rc; | |
1986 | ||
1987 | switch (drv_state) { | |
1988 | case QED_OV_DRIVER_STATE_NOT_LOADED: | |
1989 | drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED; | |
1990 | break; | |
1991 | case QED_OV_DRIVER_STATE_DISABLED: | |
1992 | drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED; | |
1993 | break; | |
1994 | case QED_OV_DRIVER_STATE_ACTIVE: | |
1995 | drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE; | |
1996 | break; | |
1997 | default: | |
1998 | DP_NOTICE(p_hwfn, "Invalid driver state %d\n", drv_state); | |
1999 | return -EINVAL; | |
2000 | } | |
2001 | ||
2002 | rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE, | |
2003 | drv_mb_param, &resp, ¶m); | |
2004 | if (rc) | |
2005 | DP_ERR(p_hwfn, "Failed to send driver state\n"); | |
2006 | ||
2007 | return rc; | |
2008 | } | |
2009 | ||
2010 | int qed_mcp_ov_update_mtu(struct qed_hwfn *p_hwfn, | |
2011 | struct qed_ptt *p_ptt, u16 mtu) | |
2012 | { | |
2013 | u32 resp = 0, param = 0; | |
2014 | u32 drv_mb_param; | |
2015 | int rc; | |
2016 | ||
2017 | drv_mb_param = (u32)mtu << DRV_MB_PARAM_OV_MTU_SIZE_SHIFT; | |
2018 | rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_MTU, | |
2019 | drv_mb_param, &resp, ¶m); | |
2020 | if (rc) | |
2021 | DP_ERR(p_hwfn, "Failed to send mtu value, rc = %d\n", rc); | |
2022 | ||
2023 | return rc; | |
2024 | } | |
2025 | ||
2026 | int qed_mcp_ov_update_mac(struct qed_hwfn *p_hwfn, | |
2027 | struct qed_ptt *p_ptt, u8 *mac) | |
2028 | { | |
2029 | struct qed_mcp_mb_params mb_params; | |
17991002 | 2030 | u32 mfw_mac[2]; |
0fefbfba SK |
2031 | int rc; |
2032 | ||
2033 | memset(&mb_params, 0, sizeof(mb_params)); | |
2034 | mb_params.cmd = DRV_MSG_CODE_SET_VMAC; | |
2035 | mb_params.param = DRV_MSG_CODE_VMAC_TYPE_MAC << | |
2036 | DRV_MSG_CODE_VMAC_TYPE_SHIFT; | |
2037 | mb_params.param |= MCP_PF_ID(p_hwfn); | |
2f67af8c | 2038 | |
17991002 MY |
2039 | /* MCP is BE, and on LE platforms PCI would swap access to SHMEM |
2040 | * in 32-bit granularity. | |
2041 | * So the MAC has to be set in native order [and not byte order], | |
2042 | * otherwise it would be read incorrectly by MFW after swap. | |
2043 | */ | |
2044 | mfw_mac[0] = mac[0] << 24 | mac[1] << 16 | mac[2] << 8 | mac[3]; | |
2045 | mfw_mac[1] = mac[4] << 24 | mac[5] << 16; | |
2046 | ||
2047 | mb_params.p_data_src = (u8 *)mfw_mac; | |
2048 | mb_params.data_src_size = 8; | |
0fefbfba SK |
2049 | rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); |
2050 | if (rc) | |
2051 | DP_ERR(p_hwfn, "Failed to send mac address, rc = %d\n", rc); | |
2052 | ||
14d39648 MY |
2053 | /* Store primary MAC for later possible WoL */ |
2054 | memcpy(p_hwfn->cdev->wol_mac, mac, ETH_ALEN); | |
2055 | ||
0fefbfba SK |
2056 | return rc; |
2057 | } | |
2058 | ||
2059 | int qed_mcp_ov_update_wol(struct qed_hwfn *p_hwfn, | |
2060 | struct qed_ptt *p_ptt, enum qed_ov_wol wol) | |
2061 | { | |
2062 | u32 resp = 0, param = 0; | |
2063 | u32 drv_mb_param; | |
2064 | int rc; | |
2065 | ||
14d39648 MY |
2066 | if (p_hwfn->hw_info.b_wol_support == QED_WOL_SUPPORT_NONE) { |
2067 | DP_VERBOSE(p_hwfn, QED_MSG_SP, | |
2068 | "Can't change WoL configuration when WoL isn't supported\n"); | |
2069 | return -EINVAL; | |
2070 | } | |
2071 | ||
0fefbfba SK |
2072 | switch (wol) { |
2073 | case QED_OV_WOL_DEFAULT: | |
2074 | drv_mb_param = DRV_MB_PARAM_WOL_DEFAULT; | |
2075 | break; | |
2076 | case QED_OV_WOL_DISABLED: | |
2077 | drv_mb_param = DRV_MB_PARAM_WOL_DISABLED; | |
2078 | break; | |
2079 | case QED_OV_WOL_ENABLED: | |
2080 | drv_mb_param = DRV_MB_PARAM_WOL_ENABLED; | |
2081 | break; | |
2082 | default: | |
2083 | DP_ERR(p_hwfn, "Invalid wol state %d\n", wol); | |
2084 | return -EINVAL; | |
2085 | } | |
2086 | ||
2087 | rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_WOL, | |
2088 | drv_mb_param, &resp, ¶m); | |
2089 | if (rc) | |
2090 | DP_ERR(p_hwfn, "Failed to send wol mode, rc = %d\n", rc); | |
2091 | ||
14d39648 MY |
2092 | /* Store the WoL update for a future unload */ |
2093 | p_hwfn->cdev->wol_config = (u8)wol; | |
2094 | ||
0fefbfba SK |
2095 | return rc; |
2096 | } | |
2097 | ||
2098 | int qed_mcp_ov_update_eswitch(struct qed_hwfn *p_hwfn, | |
2099 | struct qed_ptt *p_ptt, | |
2100 | enum qed_ov_eswitch eswitch) | |
2101 | { | |
2102 | u32 resp = 0, param = 0; | |
2103 | u32 drv_mb_param; | |
2104 | int rc; | |
2105 | ||
2106 | switch (eswitch) { | |
2107 | case QED_OV_ESWITCH_NONE: | |
2108 | drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_NONE; | |
2109 | break; | |
2110 | case QED_OV_ESWITCH_VEB: | |
2111 | drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_VEB; | |
2112 | break; | |
2113 | case QED_OV_ESWITCH_VEPA: | |
2114 | drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_VEPA; | |
2115 | break; | |
2116 | default: | |
2117 | DP_ERR(p_hwfn, "Invalid eswitch mode %d\n", eswitch); | |
2118 | return -EINVAL; | |
2119 | } | |
2120 | ||
2121 | rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_ESWITCH_MODE, | |
2122 | drv_mb_param, &resp, ¶m); | |
2123 | if (rc) | |
2124 | DP_ERR(p_hwfn, "Failed to send eswitch mode, rc = %d\n", rc); | |
2125 | ||
2126 | return rc; | |
2127 | } | |
2128 | ||
1a635e48 YM |
2129 | int qed_mcp_set_led(struct qed_hwfn *p_hwfn, |
2130 | struct qed_ptt *p_ptt, enum qed_led_mode mode) | |
91420b83 SK |
2131 | { |
2132 | u32 resp = 0, param = 0, drv_mb_param; | |
2133 | int rc; | |
2134 | ||
2135 | switch (mode) { | |
2136 | case QED_LED_MODE_ON: | |
2137 | drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_ON; | |
2138 | break; | |
2139 | case QED_LED_MODE_OFF: | |
2140 | drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OFF; | |
2141 | break; | |
2142 | case QED_LED_MODE_RESTORE: | |
2143 | drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OPER; | |
2144 | break; | |
2145 | default: | |
2146 | DP_NOTICE(p_hwfn, "Invalid LED mode %d\n", mode); | |
2147 | return -EINVAL; | |
2148 | } | |
2149 | ||
2150 | rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_LED_MODE, | |
2151 | drv_mb_param, &resp, ¶m); | |
2152 | ||
2153 | return rc; | |
2154 | } | |
03dc76ca | 2155 | |
4102426f TT |
2156 | int qed_mcp_mask_parities(struct qed_hwfn *p_hwfn, |
2157 | struct qed_ptt *p_ptt, u32 mask_parities) | |
2158 | { | |
2159 | u32 resp = 0, param = 0; | |
2160 | int rc; | |
2161 | ||
2162 | rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MASK_PARITIES, | |
2163 | mask_parities, &resp, ¶m); | |
2164 | ||
2165 | if (rc) { | |
2166 | DP_ERR(p_hwfn, | |
2167 | "MCP response failure for mask parities, aborting\n"); | |
2168 | } else if (resp != FW_MSG_CODE_OK) { | |
2169 | DP_ERR(p_hwfn, | |
2170 | "MCP did not acknowledge mask parity request. Old MFW?\n"); | |
2171 | rc = -EINVAL; | |
2172 | } | |
2173 | ||
2174 | return rc; | |
2175 | } | |
2176 | ||
7a4b21b7 MY |
2177 | int qed_mcp_nvm_read(struct qed_dev *cdev, u32 addr, u8 *p_buf, u32 len) |
2178 | { | |
2179 | u32 bytes_left = len, offset = 0, bytes_to_copy, read_len = 0; | |
2180 | struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); | |
2181 | u32 resp = 0, resp_param = 0; | |
2182 | struct qed_ptt *p_ptt; | |
2183 | int rc = 0; | |
2184 | ||
2185 | p_ptt = qed_ptt_acquire(p_hwfn); | |
2186 | if (!p_ptt) | |
2187 | return -EBUSY; | |
2188 | ||
2189 | while (bytes_left > 0) { | |
2190 | bytes_to_copy = min_t(u32, bytes_left, MCP_DRV_NVM_BUF_LEN); | |
2191 | ||
2192 | rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt, | |
2193 | DRV_MSG_CODE_NVM_READ_NVRAM, | |
2194 | addr + offset + | |
2195 | (bytes_to_copy << | |
2196 | DRV_MB_PARAM_NVM_LEN_SHIFT), | |
2197 | &resp, &resp_param, | |
2198 | &read_len, | |
2199 | (u32 *)(p_buf + offset)); | |
2200 | ||
2201 | if (rc || (resp != FW_MSG_CODE_NVM_OK)) { | |
2202 | DP_NOTICE(cdev, "MCP command rc = %d\n", rc); | |
2203 | break; | |
2204 | } | |
2205 | ||
2206 | /* This can be a lengthy process, and it's possible scheduler | |
2207 | * isn't preemptable. Sleep a bit to prevent CPU hogging. | |
2208 | */ | |
2209 | if (bytes_left % 0x1000 < | |
2210 | (bytes_left - read_len) % 0x1000) | |
2211 | usleep_range(1000, 2000); | |
2212 | ||
2213 | offset += read_len; | |
2214 | bytes_left -= read_len; | |
2215 | } | |
2216 | ||
2217 | cdev->mcp_nvm_resp = resp; | |
2218 | qed_ptt_release(p_hwfn, p_ptt); | |
2219 | ||
2220 | return rc; | |
2221 | } | |
2222 | ||
03dc76ca SRK |
2223 | int qed_mcp_bist_register_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) |
2224 | { | |
2225 | u32 drv_mb_param = 0, rsp, param; | |
2226 | int rc = 0; | |
2227 | ||
2228 | drv_mb_param = (DRV_MB_PARAM_BIST_REGISTER_TEST << | |
2229 | DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT); | |
2230 | ||
2231 | rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST, | |
2232 | drv_mb_param, &rsp, ¶m); | |
2233 | ||
2234 | if (rc) | |
2235 | return rc; | |
2236 | ||
2237 | if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) || | |
2238 | (param != DRV_MB_PARAM_BIST_RC_PASSED)) | |
2239 | rc = -EAGAIN; | |
2240 | ||
2241 | return rc; | |
2242 | } | |
2243 | ||
2244 | int qed_mcp_bist_clock_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) | |
2245 | { | |
2246 | u32 drv_mb_param, rsp, param; | |
2247 | int rc = 0; | |
2248 | ||
2249 | drv_mb_param = (DRV_MB_PARAM_BIST_CLOCK_TEST << | |
2250 | DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT); | |
2251 | ||
2252 | rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST, | |
2253 | drv_mb_param, &rsp, ¶m); | |
2254 | ||
2255 | if (rc) | |
2256 | return rc; | |
2257 | ||
2258 | if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) || | |
2259 | (param != DRV_MB_PARAM_BIST_RC_PASSED)) | |
2260 | rc = -EAGAIN; | |
2261 | ||
2262 | return rc; | |
2263 | } | |
7a4b21b7 MY |
2264 | |
2265 | int qed_mcp_bist_nvm_test_get_num_images(struct qed_hwfn *p_hwfn, | |
2266 | struct qed_ptt *p_ptt, | |
2267 | u32 *num_images) | |
2268 | { | |
2269 | u32 drv_mb_param = 0, rsp; | |
2270 | int rc = 0; | |
2271 | ||
2272 | drv_mb_param = (DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES << | |
2273 | DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT); | |
2274 | ||
2275 | rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST, | |
2276 | drv_mb_param, &rsp, num_images); | |
2277 | if (rc) | |
2278 | return rc; | |
2279 | ||
2280 | if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK)) | |
2281 | rc = -EINVAL; | |
2282 | ||
2283 | return rc; | |
2284 | } | |
2285 | ||
2286 | int qed_mcp_bist_nvm_test_get_image_att(struct qed_hwfn *p_hwfn, | |
2287 | struct qed_ptt *p_ptt, | |
2288 | struct bist_nvm_image_att *p_image_att, | |
2289 | u32 image_index) | |
2290 | { | |
2291 | u32 buf_size = 0, param, resp = 0, resp_param = 0; | |
2292 | int rc; | |
2293 | ||
2294 | param = DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX << | |
2295 | DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT; | |
2296 | param |= image_index << DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT; | |
2297 | ||
2298 | rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt, | |
2299 | DRV_MSG_CODE_BIST_TEST, param, | |
2300 | &resp, &resp_param, | |
2301 | &buf_size, | |
2302 | (u32 *)p_image_att); | |
2303 | if (rc) | |
2304 | return rc; | |
2305 | ||
2306 | if (((resp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) || | |
2307 | (p_image_att->return_code != 1)) | |
2308 | rc = -EINVAL; | |
2309 | ||
2310 | return rc; | |
2311 | } | |
2edbff8d | 2312 | |
20675b37 MY |
2313 | static int |
2314 | qed_mcp_get_nvm_image_att(struct qed_hwfn *p_hwfn, | |
2315 | struct qed_ptt *p_ptt, | |
2316 | enum qed_nvm_images image_id, | |
2317 | struct qed_nvm_image_att *p_image_att) | |
2318 | { | |
2319 | struct bist_nvm_image_att mfw_image_att; | |
2320 | enum nvm_image_type type; | |
2321 | u32 num_images, i; | |
2322 | int rc; | |
2323 | ||
2324 | /* Translate image_id into MFW definitions */ | |
2325 | switch (image_id) { | |
2326 | case QED_NVM_IMAGE_ISCSI_CFG: | |
2327 | type = NVM_TYPE_ISCSI_CFG; | |
2328 | break; | |
2329 | case QED_NVM_IMAGE_FCOE_CFG: | |
2330 | type = NVM_TYPE_FCOE_CFG; | |
2331 | break; | |
2332 | default: | |
2333 | DP_NOTICE(p_hwfn, "Unknown request of image_id %08x\n", | |
2334 | image_id); | |
2335 | return -EINVAL; | |
2336 | } | |
2337 | ||
2338 | /* Learn number of images, then traverse and see if one fits */ | |
2339 | rc = qed_mcp_bist_nvm_test_get_num_images(p_hwfn, p_ptt, &num_images); | |
2340 | if (rc || !num_images) | |
2341 | return -EINVAL; | |
2342 | ||
2343 | for (i = 0; i < num_images; i++) { | |
2344 | rc = qed_mcp_bist_nvm_test_get_image_att(p_hwfn, p_ptt, | |
2345 | &mfw_image_att, i); | |
2346 | if (rc) | |
2347 | return rc; | |
2348 | ||
2349 | if (type == mfw_image_att.image_type) | |
2350 | break; | |
2351 | } | |
2352 | if (i == num_images) { | |
2353 | DP_VERBOSE(p_hwfn, QED_MSG_STORAGE, | |
2354 | "Failed to find nvram image of type %08x\n", | |
2355 | image_id); | |
2356 | return -EINVAL; | |
2357 | } | |
2358 | ||
2359 | p_image_att->start_addr = mfw_image_att.nvm_start_addr; | |
2360 | p_image_att->length = mfw_image_att.len; | |
2361 | ||
2362 | return 0; | |
2363 | } | |
2364 | ||
2365 | int qed_mcp_get_nvm_image(struct qed_hwfn *p_hwfn, | |
2366 | struct qed_ptt *p_ptt, | |
2367 | enum qed_nvm_images image_id, | |
2368 | u8 *p_buffer, u32 buffer_len) | |
2369 | { | |
2370 | struct qed_nvm_image_att image_att; | |
2371 | int rc; | |
2372 | ||
2373 | memset(p_buffer, 0, buffer_len); | |
2374 | ||
2375 | rc = qed_mcp_get_nvm_image_att(p_hwfn, p_ptt, image_id, &image_att); | |
2376 | if (rc) | |
2377 | return rc; | |
2378 | ||
2379 | /* Validate sizes - both the image's and the supplied buffer's */ | |
2380 | if (image_att.length <= 4) { | |
2381 | DP_VERBOSE(p_hwfn, QED_MSG_STORAGE, | |
2382 | "Image [%d] is too small - only %d bytes\n", | |
2383 | image_id, image_att.length); | |
2384 | return -EINVAL; | |
2385 | } | |
2386 | ||
2387 | /* Each NVM image is suffixed by CRC; Upper-layer has no need for it */ | |
2388 | image_att.length -= 4; | |
2389 | ||
2390 | if (image_att.length > buffer_len) { | |
2391 | DP_VERBOSE(p_hwfn, | |
2392 | QED_MSG_STORAGE, | |
2393 | "Image [%d] is too big - %08x bytes where only %08x are available\n", | |
2394 | image_id, image_att.length, buffer_len); | |
2395 | return -ENOMEM; | |
2396 | } | |
2397 | ||
2398 | return qed_mcp_nvm_read(p_hwfn->cdev, image_att.start_addr, | |
2399 | p_buffer, image_att.length); | |
2400 | } | |
2401 | ||
9c8517c4 TT |
2402 | static enum resource_id_enum qed_mcp_get_mfw_res_id(enum qed_resources res_id) |
2403 | { | |
2404 | enum resource_id_enum mfw_res_id = RESOURCE_NUM_INVALID; | |
2405 | ||
2406 | switch (res_id) { | |
2407 | case QED_SB: | |
2408 | mfw_res_id = RESOURCE_NUM_SB_E; | |
2409 | break; | |
2410 | case QED_L2_QUEUE: | |
2411 | mfw_res_id = RESOURCE_NUM_L2_QUEUE_E; | |
2412 | break; | |
2413 | case QED_VPORT: | |
2414 | mfw_res_id = RESOURCE_NUM_VPORT_E; | |
2415 | break; | |
2416 | case QED_RSS_ENG: | |
2417 | mfw_res_id = RESOURCE_NUM_RSS_ENGINES_E; | |
2418 | break; | |
2419 | case QED_PQ: | |
2420 | mfw_res_id = RESOURCE_NUM_PQ_E; | |
2421 | break; | |
2422 | case QED_RL: | |
2423 | mfw_res_id = RESOURCE_NUM_RL_E; | |
2424 | break; | |
2425 | case QED_MAC: | |
2426 | case QED_VLAN: | |
2427 | /* Each VFC resource can accommodate both a MAC and a VLAN */ | |
2428 | mfw_res_id = RESOURCE_VFC_FILTER_E; | |
2429 | break; | |
2430 | case QED_ILT: | |
2431 | mfw_res_id = RESOURCE_ILT_E; | |
2432 | break; | |
2433 | case QED_LL2_QUEUE: | |
2434 | mfw_res_id = RESOURCE_LL2_QUEUE_E; | |
2435 | break; | |
2436 | case QED_RDMA_CNQ_RAM: | |
2437 | case QED_CMDQS_CQS: | |
2438 | /* CNQ/CMDQS are the same resource */ | |
2439 | mfw_res_id = RESOURCE_CQS_E; | |
2440 | break; | |
2441 | case QED_RDMA_STATS_QUEUE: | |
2442 | mfw_res_id = RESOURCE_RDMA_STATS_QUEUE_E; | |
2443 | break; | |
2444 | case QED_BDQ: | |
2445 | mfw_res_id = RESOURCE_BDQ_E; | |
2446 | break; | |
2447 | default: | |
2448 | break; | |
2449 | } | |
2450 | ||
2451 | return mfw_res_id; | |
2452 | } | |
2453 | ||
2454 | #define QED_RESC_ALLOC_VERSION_MAJOR 2 | |
2edbff8d TT |
2455 | #define QED_RESC_ALLOC_VERSION_MINOR 0 |
2456 | #define QED_RESC_ALLOC_VERSION \ | |
2457 | ((QED_RESC_ALLOC_VERSION_MAJOR << \ | |
2458 | DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT) | \ | |
2459 | (QED_RESC_ALLOC_VERSION_MINOR << \ | |
2460 | DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT)) | |
9c8517c4 TT |
2461 | |
2462 | struct qed_resc_alloc_in_params { | |
2463 | u32 cmd; | |
2464 | enum qed_resources res_id; | |
2465 | u32 resc_max_val; | |
2466 | }; | |
2467 | ||
2468 | struct qed_resc_alloc_out_params { | |
2469 | u32 mcp_resp; | |
2470 | u32 mcp_param; | |
2471 | u32 resc_num; | |
2472 | u32 resc_start; | |
2473 | u32 vf_resc_num; | |
2474 | u32 vf_resc_start; | |
2475 | u32 flags; | |
2476 | }; | |
2477 | ||
2478 | static int | |
2479 | qed_mcp_resc_allocation_msg(struct qed_hwfn *p_hwfn, | |
2480 | struct qed_ptt *p_ptt, | |
2481 | struct qed_resc_alloc_in_params *p_in_params, | |
2482 | struct qed_resc_alloc_out_params *p_out_params) | |
2edbff8d TT |
2483 | { |
2484 | struct qed_mcp_mb_params mb_params; | |
9c8517c4 | 2485 | struct resource_info mfw_resc_info; |
2edbff8d TT |
2486 | int rc; |
2487 | ||
9c8517c4 TT |
2488 | memset(&mfw_resc_info, 0, sizeof(mfw_resc_info)); |
2489 | ||
2490 | mfw_resc_info.res_id = qed_mcp_get_mfw_res_id(p_in_params->res_id); | |
2491 | if (mfw_resc_info.res_id == RESOURCE_NUM_INVALID) { | |
2492 | DP_ERR(p_hwfn, | |
2493 | "Failed to match resource %d [%s] with the MFW resources\n", | |
2494 | p_in_params->res_id, | |
2495 | qed_hw_get_resc_name(p_in_params->res_id)); | |
2496 | return -EINVAL; | |
2497 | } | |
2498 | ||
2499 | switch (p_in_params->cmd) { | |
2500 | case DRV_MSG_SET_RESOURCE_VALUE_MSG: | |
2501 | mfw_resc_info.size = p_in_params->resc_max_val; | |
2502 | /* Fallthrough */ | |
2503 | case DRV_MSG_GET_RESOURCE_ALLOC_MSG: | |
2504 | break; | |
2505 | default: | |
2506 | DP_ERR(p_hwfn, "Unexpected resource alloc command [0x%08x]\n", | |
2507 | p_in_params->cmd); | |
2508 | return -EINVAL; | |
2509 | } | |
2510 | ||
2edbff8d | 2511 | memset(&mb_params, 0, sizeof(mb_params)); |
9c8517c4 | 2512 | mb_params.cmd = p_in_params->cmd; |
2edbff8d | 2513 | mb_params.param = QED_RESC_ALLOC_VERSION; |
9c8517c4 TT |
2514 | mb_params.p_data_src = &mfw_resc_info; |
2515 | mb_params.data_src_size = sizeof(mfw_resc_info); | |
2516 | mb_params.p_data_dst = mb_params.p_data_src; | |
2517 | mb_params.data_dst_size = mb_params.data_src_size; | |
2518 | ||
2519 | DP_VERBOSE(p_hwfn, | |
2520 | QED_MSG_SP, | |
2521 | "Resource message request: cmd 0x%08x, res_id %d [%s], hsi_version %d.%d, val 0x%x\n", | |
2522 | p_in_params->cmd, | |
2523 | p_in_params->res_id, | |
2524 | qed_hw_get_resc_name(p_in_params->res_id), | |
2525 | QED_MFW_GET_FIELD(mb_params.param, | |
2526 | DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR), | |
2527 | QED_MFW_GET_FIELD(mb_params.param, | |
2528 | DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR), | |
2529 | p_in_params->resc_max_val); | |
bb480242 | 2530 | |
2edbff8d TT |
2531 | rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params); |
2532 | if (rc) | |
2533 | return rc; | |
2534 | ||
9c8517c4 TT |
2535 | p_out_params->mcp_resp = mb_params.mcp_resp; |
2536 | p_out_params->mcp_param = mb_params.mcp_param; | |
2537 | p_out_params->resc_num = mfw_resc_info.size; | |
2538 | p_out_params->resc_start = mfw_resc_info.offset; | |
2539 | p_out_params->vf_resc_num = mfw_resc_info.vf_size; | |
2540 | p_out_params->vf_resc_start = mfw_resc_info.vf_offset; | |
2541 | p_out_params->flags = mfw_resc_info.flags; | |
2edbff8d TT |
2542 | |
2543 | DP_VERBOSE(p_hwfn, | |
2544 | QED_MSG_SP, | |
9c8517c4 TT |
2545 | "Resource message response: mfw_hsi_version %d.%d, num 0x%x, start 0x%x, vf_num 0x%x, vf_start 0x%x, flags 0x%08x\n", |
2546 | QED_MFW_GET_FIELD(p_out_params->mcp_param, | |
2547 | FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR), | |
2548 | QED_MFW_GET_FIELD(p_out_params->mcp_param, | |
2549 | FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR), | |
2550 | p_out_params->resc_num, | |
2551 | p_out_params->resc_start, | |
2552 | p_out_params->vf_resc_num, | |
2553 | p_out_params->vf_resc_start, p_out_params->flags); | |
2554 | ||
2555 | return 0; | |
2556 | } | |
2557 | ||
2558 | int | |
2559 | qed_mcp_set_resc_max_val(struct qed_hwfn *p_hwfn, | |
2560 | struct qed_ptt *p_ptt, | |
2561 | enum qed_resources res_id, | |
2562 | u32 resc_max_val, u32 *p_mcp_resp) | |
2563 | { | |
2564 | struct qed_resc_alloc_out_params out_params; | |
2565 | struct qed_resc_alloc_in_params in_params; | |
2566 | int rc; | |
2567 | ||
2568 | memset(&in_params, 0, sizeof(in_params)); | |
2569 | in_params.cmd = DRV_MSG_SET_RESOURCE_VALUE_MSG; | |
2570 | in_params.res_id = res_id; | |
2571 | in_params.resc_max_val = resc_max_val; | |
2572 | memset(&out_params, 0, sizeof(out_params)); | |
2573 | rc = qed_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params, | |
2574 | &out_params); | |
2575 | if (rc) | |
2576 | return rc; | |
2577 | ||
2578 | *p_mcp_resp = out_params.mcp_resp; | |
2579 | ||
2580 | return 0; | |
2581 | } | |
2582 | ||
2583 | int | |
2584 | qed_mcp_get_resc_info(struct qed_hwfn *p_hwfn, | |
2585 | struct qed_ptt *p_ptt, | |
2586 | enum qed_resources res_id, | |
2587 | u32 *p_mcp_resp, u32 *p_resc_num, u32 *p_resc_start) | |
2588 | { | |
2589 | struct qed_resc_alloc_out_params out_params; | |
2590 | struct qed_resc_alloc_in_params in_params; | |
2591 | int rc; | |
2592 | ||
2593 | memset(&in_params, 0, sizeof(in_params)); | |
2594 | in_params.cmd = DRV_MSG_GET_RESOURCE_ALLOC_MSG; | |
2595 | in_params.res_id = res_id; | |
2596 | memset(&out_params, 0, sizeof(out_params)); | |
2597 | rc = qed_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params, | |
2598 | &out_params); | |
2599 | if (rc) | |
2600 | return rc; | |
2601 | ||
2602 | *p_mcp_resp = out_params.mcp_resp; | |
2603 | ||
2604 | if (*p_mcp_resp == FW_MSG_CODE_RESOURCE_ALLOC_OK) { | |
2605 | *p_resc_num = out_params.resc_num; | |
2606 | *p_resc_start = out_params.resc_start; | |
2607 | } | |
2edbff8d TT |
2608 | |
2609 | return 0; | |
2610 | } | |
18a69e36 MY |
2611 | |
2612 | int qed_mcp_initiate_pf_flr(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) | |
2613 | { | |
2614 | u32 mcp_resp, mcp_param; | |
2615 | ||
2616 | return qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_INITIATE_PF_FLR, 0, | |
2617 | &mcp_resp, &mcp_param); | |
2618 | } | |
95691c9c TT |
2619 | |
2620 | static int qed_mcp_resource_cmd(struct qed_hwfn *p_hwfn, | |
2621 | struct qed_ptt *p_ptt, | |
2622 | u32 param, u32 *p_mcp_resp, u32 *p_mcp_param) | |
2623 | { | |
2624 | int rc; | |
2625 | ||
2626 | rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_RESOURCE_CMD, param, | |
2627 | p_mcp_resp, p_mcp_param); | |
2628 | if (rc) | |
2629 | return rc; | |
2630 | ||
2631 | if (*p_mcp_resp == FW_MSG_CODE_UNSUPPORTED) { | |
2632 | DP_INFO(p_hwfn, | |
2633 | "The resource command is unsupported by the MFW\n"); | |
2634 | return -EINVAL; | |
2635 | } | |
2636 | ||
2637 | if (*p_mcp_param == RESOURCE_OPCODE_UNKNOWN_CMD) { | |
2638 | u8 opcode = QED_MFW_GET_FIELD(param, RESOURCE_CMD_REQ_OPCODE); | |
2639 | ||
2640 | DP_NOTICE(p_hwfn, | |
2641 | "The resource command is unknown to the MFW [param 0x%08x, opcode %d]\n", | |
2642 | param, opcode); | |
2643 | return -EINVAL; | |
2644 | } | |
2645 | ||
2646 | return rc; | |
2647 | } | |
2648 | ||
2649 | int | |
2650 | __qed_mcp_resc_lock(struct qed_hwfn *p_hwfn, | |
2651 | struct qed_ptt *p_ptt, | |
2652 | struct qed_resc_lock_params *p_params) | |
2653 | { | |
2654 | u32 param = 0, mcp_resp, mcp_param; | |
2655 | u8 opcode; | |
2656 | int rc; | |
2657 | ||
2658 | switch (p_params->timeout) { | |
2659 | case QED_MCP_RESC_LOCK_TO_DEFAULT: | |
2660 | opcode = RESOURCE_OPCODE_REQ; | |
2661 | p_params->timeout = 0; | |
2662 | break; | |
2663 | case QED_MCP_RESC_LOCK_TO_NONE: | |
2664 | opcode = RESOURCE_OPCODE_REQ_WO_AGING; | |
2665 | p_params->timeout = 0; | |
2666 | break; | |
2667 | default: | |
2668 | opcode = RESOURCE_OPCODE_REQ_W_AGING; | |
2669 | break; | |
2670 | } | |
2671 | ||
2672 | QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource); | |
2673 | QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode); | |
2674 | QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_AGE, p_params->timeout); | |
2675 | ||
2676 | DP_VERBOSE(p_hwfn, | |
2677 | QED_MSG_SP, | |
2678 | "Resource lock request: param 0x%08x [age %d, opcode %d, resource %d]\n", | |
2679 | param, p_params->timeout, opcode, p_params->resource); | |
2680 | ||
2681 | /* Attempt to acquire the resource */ | |
2682 | rc = qed_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp, &mcp_param); | |
2683 | if (rc) | |
2684 | return rc; | |
2685 | ||
2686 | /* Analyze the response */ | |
2687 | p_params->owner = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OWNER); | |
2688 | opcode = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE); | |
2689 | ||
2690 | DP_VERBOSE(p_hwfn, | |
2691 | QED_MSG_SP, | |
2692 | "Resource lock response: mcp_param 0x%08x [opcode %d, owner %d]\n", | |
2693 | mcp_param, opcode, p_params->owner); | |
2694 | ||
2695 | switch (opcode) { | |
2696 | case RESOURCE_OPCODE_GNT: | |
2697 | p_params->b_granted = true; | |
2698 | break; | |
2699 | case RESOURCE_OPCODE_BUSY: | |
2700 | p_params->b_granted = false; | |
2701 | break; | |
2702 | default: | |
2703 | DP_NOTICE(p_hwfn, | |
2704 | "Unexpected opcode in resource lock response [mcp_param 0x%08x, opcode %d]\n", | |
2705 | mcp_param, opcode); | |
2706 | return -EINVAL; | |
2707 | } | |
2708 | ||
2709 | return 0; | |
2710 | } | |
2711 | ||
2712 | int | |
2713 | qed_mcp_resc_lock(struct qed_hwfn *p_hwfn, | |
2714 | struct qed_ptt *p_ptt, struct qed_resc_lock_params *p_params) | |
2715 | { | |
2716 | u32 retry_cnt = 0; | |
2717 | int rc; | |
2718 | ||
2719 | do { | |
2720 | /* No need for an interval before the first iteration */ | |
2721 | if (retry_cnt) { | |
2722 | if (p_params->sleep_b4_retry) { | |
2723 | u16 retry_interval_in_ms = | |
2724 | DIV_ROUND_UP(p_params->retry_interval, | |
2725 | 1000); | |
2726 | ||
2727 | msleep(retry_interval_in_ms); | |
2728 | } else { | |
2729 | udelay(p_params->retry_interval); | |
2730 | } | |
2731 | } | |
2732 | ||
2733 | rc = __qed_mcp_resc_lock(p_hwfn, p_ptt, p_params); | |
2734 | if (rc) | |
2735 | return rc; | |
2736 | ||
2737 | if (p_params->b_granted) | |
2738 | break; | |
2739 | } while (retry_cnt++ < p_params->retry_num); | |
2740 | ||
2741 | return 0; | |
2742 | } | |
2743 | ||
2744 | int | |
2745 | qed_mcp_resc_unlock(struct qed_hwfn *p_hwfn, | |
2746 | struct qed_ptt *p_ptt, | |
2747 | struct qed_resc_unlock_params *p_params) | |
2748 | { | |
2749 | u32 param = 0, mcp_resp, mcp_param; | |
2750 | u8 opcode; | |
2751 | int rc; | |
2752 | ||
2753 | opcode = p_params->b_force ? RESOURCE_OPCODE_FORCE_RELEASE | |
2754 | : RESOURCE_OPCODE_RELEASE; | |
2755 | QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource); | |
2756 | QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode); | |
2757 | ||
2758 | DP_VERBOSE(p_hwfn, QED_MSG_SP, | |
2759 | "Resource unlock request: param 0x%08x [opcode %d, resource %d]\n", | |
2760 | param, opcode, p_params->resource); | |
2761 | ||
2762 | /* Attempt to release the resource */ | |
2763 | rc = qed_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp, &mcp_param); | |
2764 | if (rc) | |
2765 | return rc; | |
2766 | ||
2767 | /* Analyze the response */ | |
2768 | opcode = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE); | |
2769 | ||
2770 | DP_VERBOSE(p_hwfn, QED_MSG_SP, | |
2771 | "Resource unlock response: mcp_param 0x%08x [opcode %d]\n", | |
2772 | mcp_param, opcode); | |
2773 | ||
2774 | switch (opcode) { | |
2775 | case RESOURCE_OPCODE_RELEASED_PREVIOUS: | |
2776 | DP_INFO(p_hwfn, | |
2777 | "Resource unlock request for an already released resource [%d]\n", | |
2778 | p_params->resource); | |
2779 | /* Fallthrough */ | |
2780 | case RESOURCE_OPCODE_RELEASED: | |
2781 | p_params->b_released = true; | |
2782 | break; | |
2783 | case RESOURCE_OPCODE_WRONG_OWNER: | |
2784 | p_params->b_released = false; | |
2785 | break; | |
2786 | default: | |
2787 | DP_NOTICE(p_hwfn, | |
2788 | "Unexpected opcode in resource unlock response [mcp_param 0x%08x, opcode %d]\n", | |
2789 | mcp_param, opcode); | |
2790 | return -EINVAL; | |
2791 | } | |
2792 | ||
2793 | return 0; | |
2794 | } | |
f470f22c | 2795 | |
2796 | void qed_mcp_resc_lock_default_init(struct qed_resc_lock_params *p_lock, | |
2797 | struct qed_resc_unlock_params *p_unlock, | |
2798 | enum qed_resc_lock | |
2799 | resource, bool b_is_permanent) | |
2800 | { | |
2801 | if (p_lock) { | |
2802 | memset(p_lock, 0, sizeof(*p_lock)); | |
2803 | ||
2804 | /* Permanent resources don't require aging, and there's no | |
2805 | * point in trying to acquire them more than once since it's | |
2806 | * unexpected another entity would release them. | |
2807 | */ | |
2808 | if (b_is_permanent) { | |
2809 | p_lock->timeout = QED_MCP_RESC_LOCK_TO_NONE; | |
2810 | } else { | |
2811 | p_lock->retry_num = QED_MCP_RESC_LOCK_RETRY_CNT_DFLT; | |
2812 | p_lock->retry_interval = | |
2813 | QED_MCP_RESC_LOCK_RETRY_VAL_DFLT; | |
2814 | p_lock->sleep_b4_retry = true; | |
2815 | } | |
2816 | ||
2817 | p_lock->resource = resource; | |
2818 | } | |
2819 | ||
2820 | if (p_unlock) { | |
2821 | memset(p_unlock, 0, sizeof(*p_unlock)); | |
2822 | p_unlock->resource = resource; | |
2823 | } | |
2824 | } |