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qed*: Utilize Firmware 8.15.3.0
[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / qlogic / qed / qed_roce.c
CommitLineData
51ff1725 1/* QLogic qed NIC Driver
e8f1cb50 2 * Copyright (c) 2015-2017 QLogic Corporation
51ff1725
RA		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32#include <linux/types.h>
33#include <asm/byteorder.h>
34#include <linux/bitops.h>
35#include <linux/delay.h>
36#include <linux/dma-mapping.h>
37#include <linux/errno.h>
38#include <linux/etherdevice.h>
39#include <linux/if_ether.h>
40#include <linux/if_vlan.h>
41#include <linux/io.h>
42#include <linux/ip.h>
43#include <linux/ipv6.h>
44#include <linux/kernel.h>
45#include <linux/list.h>
46#include <linux/module.h>
47#include <linux/mutex.h>
48#include <linux/pci.h>
49#include <linux/slab.h>
50#include <linux/spinlock.h>
51#include <linux/string.h>
52#include <linux/tcp.h>
53#include <linux/bitops.h>
54#include <linux/qed/qed_roce_if.h>
55#include <linux/qed/qed_roce_if.h>
56#include "qed.h"
57#include "qed_cxt.h"
58#include "qed_hsi.h"
59#include "qed_hw.h"
60#include "qed_init_ops.h"
61#include "qed_int.h"
62#include "qed_ll2.h"
63#include "qed_mcp.h"
64#include "qed_reg_addr.h"
65#include "qed_sp.h"
66#include "qed_roce.h"
abd49676 67#include "qed_ll2.h"
51ff1725 68
be086e7c
MY		 69static void qed_roce_free_real_icid(struct qed_hwfn *p_hwfn, u16 icid);
70
71void qed_roce_async_event(struct qed_hwfn *p_hwfn,
72 u8 fw_event_code, union rdma_eqe_data *rdma_data)
51ff1725 73{
be086e7c
MY		 74 if (fw_event_code == ROCE_ASYNC_EVENT_DESTROY_QP_DONE) {
75 u16 icid =
76 (u16)le32_to_cpu(rdma_data->rdma_destroy_qp_data.cid);
77
78 /* icid release in this async event can occur only if the icid
79 * was offloaded to the FW. In case it wasn't offloaded this is
80 * handled in qed_roce_sp_destroy_qp.
81 */
82 qed_roce_free_real_icid(p_hwfn, icid);
83 } else {
84 struct qed_rdma_events *events = &p_hwfn->p_rdma_info->events;
51ff1725 85
be086e7c
MY		 86 events->affiliated_event(p_hwfn->p_rdma_info->events.context,
87 fw_event_code,
88 &rdma_data->async_handle);
89 }
51ff1725
RA		 90}
91
92static int qed_rdma_bmap_alloc(struct qed_hwfn *p_hwfn,
93 struct qed_bmap *bmap, u32 max_count)
94{
95 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "max_count = %08x\n", max_count);
96
97 bmap->max_count = max_count;
98
99 bmap->bitmap = kzalloc(BITS_TO_LONGS(max_count) * sizeof(long),
100 GFP_KERNEL);
101 if (!bmap->bitmap) {
102 DP_NOTICE(p_hwfn,
103 "qed bmap alloc failed: cannot allocate memory (bitmap)\n");
104 return -ENOMEM;
105 }
106
107 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Allocated bitmap %p\n",
108 bmap->bitmap);
109 return 0;
110}
111
112static int qed_rdma_bmap_alloc_id(struct qed_hwfn *p_hwfn,
113 struct qed_bmap *bmap, u32 *id_num)
114{
115 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "bmap = %p\n", bmap);
116
117 *id_num = find_first_zero_bit(bmap->bitmap, bmap->max_count);
118
119 if (*id_num >= bmap->max_count) {
120 DP_NOTICE(p_hwfn, "no id available max_count=%d\n",
121 bmap->max_count);
122 return -EINVAL;
123 }
124
125 __set_bit(*id_num, bmap->bitmap);
126
127 return 0;
128}
129
be086e7c
MY		 130static void qed_bmap_set_id(struct qed_hwfn *p_hwfn,
131 struct qed_bmap *bmap, u32 id_num)
132{
133 if (id_num >= bmap->max_count)
134 return;
135
136 __set_bit(id_num, bmap->bitmap);
137}
138
51ff1725
RA		 139static void qed_bmap_release_id(struct qed_hwfn *p_hwfn,
140 struct qed_bmap *bmap, u32 id_num)
141{
142 bool b_acquired;
143
144 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "id_num = %08x", id_num);
145 if (id_num >= bmap->max_count)
146 return;
147
148 b_acquired = test_and_clear_bit(id_num, bmap->bitmap);
149 if (!b_acquired) {
150 DP_NOTICE(p_hwfn, "ID %d already released\n", id_num);
151 return;
152 }
153}
154
be086e7c
MY		 155static int qed_bmap_test_id(struct qed_hwfn *p_hwfn,
156 struct qed_bmap *bmap, u32 id_num)
157{
158 if (id_num >= bmap->max_count)
159 return -1;
160
161 return test_bit(id_num, bmap->bitmap);
162}
163
0189efb8 164static u32 qed_rdma_get_sb_id(void *p_hwfn, u32 rel_sb_id)
51ff1725
RA		 165{
166 /* First sb id for RoCE is after all the l2 sb */
167 return FEAT_NUM((struct qed_hwfn *)p_hwfn, QED_PF_L2_QUE) + rel_sb_id;
168}
169
51ff1725
RA		 170static int qed_rdma_alloc(struct qed_hwfn *p_hwfn,
171 struct qed_ptt *p_ptt,
172 struct qed_rdma_start_in_params *params)
173{
174 struct qed_rdma_info *p_rdma_info;
175 u32 num_cons, num_tasks;
176 int rc = -ENOMEM;
177
178 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Allocating RDMA\n");
179
180 /* Allocate a struct with current pf rdma info */
181 p_rdma_info = kzalloc(sizeof(*p_rdma_info), GFP_KERNEL);
182 if (!p_rdma_info) {
183 DP_NOTICE(p_hwfn,
184 "qed rdma alloc failed: cannot allocate memory (rdma info). rc = %d\n",
185 rc);
186 return rc;
187 }
188
189 p_hwfn->p_rdma_info = p_rdma_info;
190 p_rdma_info->proto = PROTOCOLID_ROCE;
191
8c93beaf
YM		 192 num_cons = qed_cxt_get_proto_cid_count(p_hwfn, p_rdma_info->proto,
193 NULL);
51ff1725
RA		 194
195 p_rdma_info->num_qps = num_cons / 2;
196
197 num_tasks = qed_cxt_get_proto_tid_count(p_hwfn, PROTOCOLID_ROCE);
198
199 /* Each MR uses a single task */
200 p_rdma_info->num_mrs = num_tasks;
201
202 /* Queue zone lines are shared between RoCE and L2 in such a way that
203 * they can be used by each without obstructing the other.
204 */
be086e7c
MY		 205 p_rdma_info->queue_zone_base = (u16)RESC_START(p_hwfn, QED_L2_QUEUE);
206 p_rdma_info->max_queue_zones = (u16)RESC_NUM(p_hwfn, QED_L2_QUEUE);
51ff1725
RA		 207
208 /* Allocate a struct with device params and fill it */
209 p_rdma_info->dev = kzalloc(sizeof(*p_rdma_info->dev), GFP_KERNEL);
210 if (!p_rdma_info->dev) {
211 DP_NOTICE(p_hwfn,
212 "qed rdma alloc failed: cannot allocate memory (rdma info dev). rc = %d\n",
213 rc);
214 goto free_rdma_info;
215 }
216
217 /* Allocate a struct with port params and fill it */
218 p_rdma_info->port = kzalloc(sizeof(*p_rdma_info->port), GFP_KERNEL);
219 if (!p_rdma_info->port) {
220 DP_NOTICE(p_hwfn,
221 "qed rdma alloc failed: cannot allocate memory (rdma info port). rc = %d\n",
222 rc);
223 goto free_rdma_dev;
224 }
225
226 /* Allocate bit map for pd's */
227 rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->pd_map, RDMA_MAX_PDS);
228 if (rc) {
229 DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
230 "Failed to allocate pd_map, rc = %d\n",
231 rc);
232 goto free_rdma_port;
233 }
234
235 /* Allocate DPI bitmap */
236 rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->dpi_map,
237 p_hwfn->dpi_count);
238 if (rc) {
239 DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
240 "Failed to allocate DPI bitmap, rc = %d\n", rc);
241 goto free_pd_map;
242 }
243
244 /* Allocate bitmap for cq's. The maximum number of CQs is bounded to
245 * twice the number of QPs.
246 */
247 rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->cq_map,
248 p_rdma_info->num_qps * 2);
249 if (rc) {
250 DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
251 "Failed to allocate cq bitmap, rc = %d\n", rc);
252 goto free_dpi_map;
253 }
254
255 /* Allocate bitmap for toggle bit for cq icids
256 * We toggle the bit every time we create or resize cq for a given icid.
257 * The maximum number of CQs is bounded to twice the number of QPs.
258 */
259 rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->toggle_bits,
260 p_rdma_info->num_qps * 2);
261 if (rc) {
262 DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
263 "Failed to allocate toogle bits, rc = %d\n", rc);
264 goto free_cq_map;
265 }
266
267 /* Allocate bitmap for itids */
268 rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->tid_map,
269 p_rdma_info->num_mrs);
270 if (rc) {
271 DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
272 "Failed to allocate itids bitmaps, rc = %d\n", rc);
273 goto free_toggle_map;
274 }
275
276 /* Allocate bitmap for cids used for qps. */
277 rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->cid_map, num_cons);
278 if (rc) {
279 DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
280 "Failed to allocate cid bitmap, rc = %d\n", rc);
281 goto free_tid_map;
282 }
283
be086e7c
MY		 284 /* Allocate bitmap for cids used for responders/requesters. */
285 rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->real_cid_map, num_cons);
286 if (rc) {
287 DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
288 "Failed to allocate real cid bitmap, rc = %d\n", rc);
289 goto free_cid_map;
290 }
51ff1725
RA		 291 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Allocation successful\n");
292 return 0;
293
be086e7c
MY		 294free_cid_map:
295 kfree(p_rdma_info->cid_map.bitmap);
51ff1725
RA		 296free_tid_map:
297 kfree(p_rdma_info->tid_map.bitmap);
298free_toggle_map:
299 kfree(p_rdma_info->toggle_bits.bitmap);
300free_cq_map:
301 kfree(p_rdma_info->cq_map.bitmap);
302free_dpi_map:
303 kfree(p_rdma_info->dpi_map.bitmap);
304free_pd_map:
305 kfree(p_rdma_info->pd_map.bitmap);
306free_rdma_port:
307 kfree(p_rdma_info->port);
308free_rdma_dev:
309 kfree(p_rdma_info->dev);
310free_rdma_info:
311 kfree(p_rdma_info);
312
313 return rc;
314}
315
0189efb8 316static void qed_rdma_resc_free(struct qed_hwfn *p_hwfn)
51ff1725 317{
be086e7c 318 struct qed_bmap *rcid_map = &p_hwfn->p_rdma_info->real_cid_map;
51ff1725 319 struct qed_rdma_info *p_rdma_info = p_hwfn->p_rdma_info;
be086e7c
MY		 320 int wait_count = 0;
321
322 /* when destroying a_RoCE QP the control is returned to the user after
323 * the synchronous part. The asynchronous part may take a little longer.
324 * We delay for a short while if an async destroy QP is still expected.
325 * Beyond the added delay we clear the bitmap anyway.
326 */
327 while (bitmap_weight(rcid_map->bitmap, rcid_map->max_count)) {
328 msleep(100);
329 if (wait_count++ > 20) {
330 DP_NOTICE(p_hwfn, "cid bitmap wait timed out\n");
331 break;
332 }
333 }
51ff1725
RA		 334
335 kfree(p_rdma_info->cid_map.bitmap);
336 kfree(p_rdma_info->tid_map.bitmap);
337 kfree(p_rdma_info->toggle_bits.bitmap);
338 kfree(p_rdma_info->cq_map.bitmap);
339 kfree(p_rdma_info->dpi_map.bitmap);
340 kfree(p_rdma_info->pd_map.bitmap);
341
342 kfree(p_rdma_info->port);
343 kfree(p_rdma_info->dev);
344
345 kfree(p_rdma_info);
346}
347
348static void qed_rdma_free(struct qed_hwfn *p_hwfn)
349{
350 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Freeing RDMA\n");
351
352 qed_rdma_resc_free(p_hwfn);
353}
354
355static void qed_rdma_get_guid(struct qed_hwfn *p_hwfn, u8 *guid)
356{
357 guid[0] = p_hwfn->hw_info.hw_mac_addr[0] ^ 2;
358 guid[1] = p_hwfn->hw_info.hw_mac_addr[1];
359 guid[2] = p_hwfn->hw_info.hw_mac_addr[2];
360 guid[3] = 0xff;
361 guid[4] = 0xfe;
362 guid[5] = p_hwfn->hw_info.hw_mac_addr[3];
363 guid[6] = p_hwfn->hw_info.hw_mac_addr[4];
364 guid[7] = p_hwfn->hw_info.hw_mac_addr[5];
365}
366
367static void qed_rdma_init_events(struct qed_hwfn *p_hwfn,
368 struct qed_rdma_start_in_params *params)
369{
370 struct qed_rdma_events *events;
371
372 events = &p_hwfn->p_rdma_info->events;
373
374 events->unaffiliated_event = params->events->unaffiliated_event;
375 events->affiliated_event = params->events->affiliated_event;
376 events->context = params->events->context;
377}
378
379static void qed_rdma_init_devinfo(struct qed_hwfn *p_hwfn,
380 struct qed_rdma_start_in_params *params)
381{
382 struct qed_rdma_device *dev = p_hwfn->p_rdma_info->dev;
383 struct qed_dev *cdev = p_hwfn->cdev;
384 u32 pci_status_control;
385 u32 num_qps;
386
387 /* Vendor specific information */
388 dev->vendor_id = cdev->vendor_id;
389 dev->vendor_part_id = cdev->device_id;
390 dev->hw_ver = 0;
391 dev->fw_ver = (FW_MAJOR_VERSION << 24) | (FW_MINOR_VERSION << 16) |
392 (FW_REVISION_VERSION << 8) | (FW_ENGINEERING_VERSION);
393
394 qed_rdma_get_guid(p_hwfn, (u8 *)&dev->sys_image_guid);
395 dev->node_guid = dev->sys_image_guid;
396
397 dev->max_sge = min_t(u32, RDMA_MAX_SGE_PER_SQ_WQE,
398 RDMA_MAX_SGE_PER_RQ_WQE);
399
400 if (cdev->rdma_max_sge)
401 dev->max_sge = min_t(u32, cdev->rdma_max_sge, dev->max_sge);
402
403 dev->max_inline = ROCE_REQ_MAX_INLINE_DATA_SIZE;
404
405 dev->max_inline = (cdev->rdma_max_inline) ?
406 min_t(u32, cdev->rdma_max_inline, dev->max_inline) :
407 dev->max_inline;
408
409 dev->max_wqe = QED_RDMA_MAX_WQE;
410 dev->max_cnq = (u8)FEAT_NUM(p_hwfn, QED_RDMA_CNQ);
411
412 /* The number of QPs may be higher than QED_ROCE_MAX_QPS, because
413 * it is up-aligned to 16 and then to ILT page size within qed cxt.
414 * This is OK in terms of ILT but we don't want to configure the FW
415 * above its abilities
416 */
417 num_qps = ROCE_MAX_QPS;
418 num_qps = min_t(u64, num_qps, p_hwfn->p_rdma_info->num_qps);
419 dev->max_qp = num_qps;
420
421 /* CQs uses the same icids that QPs use hence they are limited by the
422 * number of icids. There are two icids per QP.
423 */
424 dev->max_cq = num_qps * 2;
425
426 /* The number of mrs is smaller by 1 since the first is reserved */
427 dev->max_mr = p_hwfn->p_rdma_info->num_mrs - 1;
428 dev->max_mr_size = QED_RDMA_MAX_MR_SIZE;
429
430 /* The maximum CQE capacity per CQ supported.
431 * max number of cqes will be in two layer pbl,
432 * 8 is the pointer size in bytes
433 * 32 is the size of cq element in bytes
434 */
435 if (params->cq_mode == QED_RDMA_CQ_MODE_32_BITS)
436 dev->max_cqe = QED_RDMA_MAX_CQE_32_BIT;
437 else
438 dev->max_cqe = QED_RDMA_MAX_CQE_16_BIT;
439
440 dev->max_mw = 0;
441 dev->max_fmr = QED_RDMA_MAX_FMR;
442 dev->max_mr_mw_fmr_pbl = (PAGE_SIZE / 8) * (PAGE_SIZE / 8);
443 dev->max_mr_mw_fmr_size = dev->max_mr_mw_fmr_pbl * PAGE_SIZE;
444 dev->max_pkey = QED_RDMA_MAX_P_KEY;
445
446 dev->max_qp_resp_rd_atomic_resc = RDMA_RING_PAGE_SIZE /
447 (RDMA_RESP_RD_ATOMIC_ELM_SIZE * 2);
448 dev->max_qp_req_rd_atomic_resc = RDMA_RING_PAGE_SIZE /
449 RDMA_REQ_RD_ATOMIC_ELM_SIZE;
450 dev->max_dev_resp_rd_atomic_resc = dev->max_qp_resp_rd_atomic_resc *
451 p_hwfn->p_rdma_info->num_qps;
452 dev->page_size_caps = QED_RDMA_PAGE_SIZE_CAPS;
453 dev->dev_ack_delay = QED_RDMA_ACK_DELAY;
454 dev->max_pd = RDMA_MAX_PDS;
455 dev->max_ah = p_hwfn->p_rdma_info->num_qps;
456 dev->max_stats_queues = (u8)RESC_NUM(p_hwfn, QED_RDMA_STATS_QUEUE);
457
458 /* Set capablities */
459 dev->dev_caps = 0;
460 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_RNR_NAK, 1);
461 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_PORT_ACTIVE_EVENT, 1);
462 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_PORT_CHANGE_EVENT, 1);
463 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_RESIZE_CQ, 1);
464 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_BASE_MEMORY_EXT, 1);
465 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_BASE_QUEUE_EXT, 1);
466 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_ZBVA, 1);
467 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_LOCAL_INV_FENCE, 1);
468
469 /* Check atomic operations support in PCI configuration space. */
470 pci_read_config_dword(cdev->pdev,
471 cdev->pdev->pcie_cap + PCI_EXP_DEVCTL2,
472 &pci_status_control);
473
474 if (pci_status_control & PCI_EXP_DEVCTL2_LTR_EN)
475 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_ATOMIC_OP, 1);
476}
477
478static void qed_rdma_init_port(struct qed_hwfn *p_hwfn)
479{
480 struct qed_rdma_port *port = p_hwfn->p_rdma_info->port;
481 struct qed_rdma_device *dev = p_hwfn->p_rdma_info->dev;
482
483 port->port_state = p_hwfn->mcp_info->link_output.link_up ?
484 QED_RDMA_PORT_UP : QED_RDMA_PORT_DOWN;
485
486 port->max_msg_size = min_t(u64,
487 (dev->max_mr_mw_fmr_size *
488 p_hwfn->cdev->rdma_max_sge),
489 BIT(31));
490
491 port->pkey_bad_counter = 0;
492}
493
494static int qed_rdma_init_hw(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
495{
496 u32 ll2_ethertype_en;
497
498 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Initializing HW\n");
499 p_hwfn->b_rdma_enabled_in_prs = false;
500
501 qed_wr(p_hwfn, p_ptt, PRS_REG_ROCE_DEST_QP_MAX_PF, 0);
502
503 p_hwfn->rdma_prs_search_reg = PRS_REG_SEARCH_ROCE;
504
505 /* We delay writing to this reg until first cid is allocated. See
506 * qed_cxt_dynamic_ilt_alloc function for more details
507 */
508 ll2_ethertype_en = qed_rd(p_hwfn, p_ptt, PRS_REG_LIGHT_L2_ETHERTYPE_EN);
509 qed_wr(p_hwfn, p_ptt, PRS_REG_LIGHT_L2_ETHERTYPE_EN,
510 (ll2_ethertype_en | 0x01));
511
512 if (qed_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_ROCE) % 2) {
513 DP_NOTICE(p_hwfn, "The first RoCE's cid should be even\n");
514 return -EINVAL;
515 }
516
517 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Initializing HW - Done\n");
518 return 0;
519}
520
521static int qed_rdma_start_fw(struct qed_hwfn *p_hwfn,
522 struct qed_rdma_start_in_params *params,
523 struct qed_ptt *p_ptt)
524{
525 struct rdma_init_func_ramrod_data *p_ramrod;
526 struct qed_rdma_cnq_params *p_cnq_pbl_list;
527 struct rdma_init_func_hdr *p_params_header;
528 struct rdma_cnq_params *p_cnq_params;
529 struct qed_sp_init_data init_data;
530 struct qed_spq_entry *p_ent;
531 u32 cnq_id, sb_id;
532 int rc;
533
534 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Starting FW\n");
535
536 /* Save the number of cnqs for the function close ramrod */
537 p_hwfn->p_rdma_info->num_cnqs = params->desired_cnq;
538
539 /* Get SPQ entry */
540 memset(&init_data, 0, sizeof(init_data));
541 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
542 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
543
544 rc = qed_sp_init_request(p_hwfn, &p_ent, RDMA_RAMROD_FUNC_INIT,
545 p_hwfn->p_rdma_info->proto, &init_data);
546 if (rc)
547 return rc;
548
549 p_ramrod = &p_ent->ramrod.roce_init_func.rdma;
550
551 p_params_header = &p_ramrod->params_header;
552 p_params_header->cnq_start_offset = (u8)RESC_START(p_hwfn,
553 QED_RDMA_CNQ_RAM);
554 p_params_header->num_cnqs = params->desired_cnq;
555
556 if (params->cq_mode == QED_RDMA_CQ_MODE_16_BITS)
557 p_params_header->cq_ring_mode = 1;
558 else
559 p_params_header->cq_ring_mode = 0;
560
561 for (cnq_id = 0; cnq_id < params->desired_cnq; cnq_id++) {
562 sb_id = qed_rdma_get_sb_id(p_hwfn, cnq_id);
563 p_cnq_params = &p_ramrod->cnq_params[cnq_id];
564 p_cnq_pbl_list = &params->cnq_pbl_list[cnq_id];
565 p_cnq_params->sb_num =
566 cpu_to_le16(p_hwfn->sbs_info[sb_id]->igu_sb_id);
567
568 p_cnq_params->sb_index = p_hwfn->pf_params.rdma_pf_params.gl_pi;
569 p_cnq_params->num_pbl_pages = p_cnq_pbl_list->num_pbl_pages;
570
571 DMA_REGPAIR_LE(p_cnq_params->pbl_base_addr,
572 p_cnq_pbl_list->pbl_ptr);
573
574 /* we assume here that cnq_id and qz_offset are the same */
575 p_cnq_params->queue_zone_num =
576 cpu_to_le16(p_hwfn->p_rdma_info->queue_zone_base +
577 cnq_id);
578 }
579
580 return qed_spq_post(p_hwfn, p_ent, NULL);
581}
582
0189efb8
YM		 583static int qed_rdma_alloc_tid(void *rdma_cxt, u32 *itid)
584{
585 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
586 int rc;
587
588 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Allocate TID\n");
589
590 spin_lock_bh(&p_hwfn->p_rdma_info->lock);
591 rc = qed_rdma_bmap_alloc_id(p_hwfn,
592 &p_hwfn->p_rdma_info->tid_map, itid);
593 spin_unlock_bh(&p_hwfn->p_rdma_info->lock);
594 if (rc)
595 goto out;
596
597 rc = qed_cxt_dynamic_ilt_alloc(p_hwfn, QED_ELEM_TASK, *itid);
598out:
599 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Allocate TID - done, rc = %d\n", rc);
600 return rc;
601}
602
51ff1725
RA		 603static int qed_rdma_reserve_lkey(struct qed_hwfn *p_hwfn)
604{
605 struct qed_rdma_device *dev = p_hwfn->p_rdma_info->dev;
606
607 /* The first DPI is reserved for the Kernel */
608 __set_bit(0, p_hwfn->p_rdma_info->dpi_map.bitmap);
609
610 /* Tid 0 will be used as the key for "reserved MR".
611 * The driver should allocate memory for it so it can be loaded but no
612 * ramrod should be passed on it.
613 */
614 qed_rdma_alloc_tid(p_hwfn, &dev->reserved_lkey);
615 if (dev->reserved_lkey != RDMA_RESERVED_LKEY) {
616 DP_NOTICE(p_hwfn,
617 "Reserved lkey should be equal to RDMA_RESERVED_LKEY\n");
618 return -EINVAL;
619 }
620
621 return 0;
622}
623
624static int qed_rdma_setup(struct qed_hwfn *p_hwfn,
625 struct qed_ptt *p_ptt,
626 struct qed_rdma_start_in_params *params)
627{
628 int rc;
629
630 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "RDMA setup\n");
631
632 spin_lock_init(&p_hwfn->p_rdma_info->lock);
633
634 qed_rdma_init_devinfo(p_hwfn, params);
635 qed_rdma_init_port(p_hwfn);
636 qed_rdma_init_events(p_hwfn, params);
637
638 rc = qed_rdma_reserve_lkey(p_hwfn);
639 if (rc)
640 return rc;
641
642 rc = qed_rdma_init_hw(p_hwfn, p_ptt);
643 if (rc)
644 return rc;
645
646 return qed_rdma_start_fw(p_hwfn, params, p_ptt);
647}
648
0189efb8 649static int qed_rdma_stop(void *rdma_cxt)
51ff1725
RA		 650{
651 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
652 struct rdma_close_func_ramrod_data *p_ramrod;
653 struct qed_sp_init_data init_data;
654 struct qed_spq_entry *p_ent;
655 struct qed_ptt *p_ptt;
656 u32 ll2_ethertype_en;
657 int rc = -EBUSY;
658
659 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "RDMA stop\n");
660
661 p_ptt = qed_ptt_acquire(p_hwfn);
662 if (!p_ptt) {
663 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Failed to acquire PTT\n");
664 return rc;
665 }
666
667 /* Disable RoCE search */
668 qed_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 0);
669 p_hwfn->b_rdma_enabled_in_prs = false;
670
671 qed_wr(p_hwfn, p_ptt, PRS_REG_ROCE_DEST_QP_MAX_PF, 0);
672
673 ll2_ethertype_en = qed_rd(p_hwfn, p_ptt, PRS_REG_LIGHT_L2_ETHERTYPE_EN);
674
675 qed_wr(p_hwfn, p_ptt, PRS_REG_LIGHT_L2_ETHERTYPE_EN,
676 (ll2_ethertype_en & 0xFFFE));
677
678 qed_ptt_release(p_hwfn, p_ptt);
679
680 /* Get SPQ entry */
681 memset(&init_data, 0, sizeof(init_data));
682 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
683 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
684
685 /* Stop RoCE */
686 rc = qed_sp_init_request(p_hwfn, &p_ent, RDMA_RAMROD_FUNC_CLOSE,
687 p_hwfn->p_rdma_info->proto, &init_data);
688 if (rc)
689 goto out;
690
691 p_ramrod = &p_ent->ramrod.rdma_close_func;
692
693 p_ramrod->num_cnqs = p_hwfn->p_rdma_info->num_cnqs;
694 p_ramrod->cnq_start_offset = (u8)RESC_START(p_hwfn, QED_RDMA_CNQ_RAM);
695
696 rc = qed_spq_post(p_hwfn, p_ent, NULL);
697
698out:
699 qed_rdma_free(p_hwfn);
700
701 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "RDMA stop done, rc = %d\n", rc);
702 return rc;
703}
704
0189efb8
YM		 705static int qed_rdma_add_user(void *rdma_cxt,
706 struct qed_rdma_add_user_out_params *out_params)
51ff1725
RA		 707{
708 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
709 u32 dpi_start_offset;
710 u32 returned_id = 0;
711 int rc;
712
713 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Adding User\n");
714
715 /* Allocate DPI */
716 spin_lock_bh(&p_hwfn->p_rdma_info->lock);
717 rc = qed_rdma_bmap_alloc_id(p_hwfn, &p_hwfn->p_rdma_info->dpi_map,
718 &returned_id);
719 spin_unlock_bh(&p_hwfn->p_rdma_info->lock);
720
721 out_params->dpi = (u16)returned_id;
722
723 /* Calculate the corresponding DPI address */
724 dpi_start_offset = p_hwfn->dpi_start_offset;
725
726 out_params->dpi_addr = (u64)((u8 __iomem *)p_hwfn->doorbells +
727 dpi_start_offset +
728 ((out_params->dpi) * p_hwfn->dpi_size));
729
730 out_params->dpi_phys_addr = p_hwfn->cdev->db_phys_addr +
731 dpi_start_offset +
732 ((out_params->dpi) * p_hwfn->dpi_size);
733
734 out_params->dpi_size = p_hwfn->dpi_size;
735
736 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Adding user - done, rc = %d\n", rc);
737 return rc;
738}
739
0189efb8 740static struct qed_rdma_port *qed_rdma_query_port(void *rdma_cxt)
c295f86e
RA		 741{
742 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
743 struct qed_rdma_port *p_port = p_hwfn->p_rdma_info->port;
744
745 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "RDMA Query port\n");
746
747 /* Link may have changed */
748 p_port->port_state = p_hwfn->mcp_info->link_output.link_up ?
749 QED_RDMA_PORT_UP : QED_RDMA_PORT_DOWN;
750
751 p_port->link_speed = p_hwfn->mcp_info->link_output.speed;
752
753 return p_port;
754}
755
0189efb8 756static struct qed_rdma_device *qed_rdma_query_device(void *rdma_cxt)
51ff1725
RA		 757{
758 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
759
760 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Query device\n");
761
762 /* Return struct with device parameters */
763 return p_hwfn->p_rdma_info->dev;
764}
765
0189efb8 766static void qed_rdma_free_tid(void *rdma_cxt, u32 itid)
ee8eaea3
RA		 767{
768 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
769
770 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "itid = %08x\n", itid);
771
772 spin_lock_bh(&p_hwfn->p_rdma_info->lock);
773 qed_bmap_release_id(p_hwfn, &p_hwfn->p_rdma_info->tid_map, itid);
774 spin_unlock_bh(&p_hwfn->p_rdma_info->lock);
775}
776
0189efb8 777static void qed_rdma_cnq_prod_update(void *rdma_cxt, u8 qz_offset, u16 prod)
51ff1725
RA		 778{
779 struct qed_hwfn *p_hwfn;
780 u16 qz_num;
781 u32 addr;
782
783 p_hwfn = (struct qed_hwfn *)rdma_cxt;
be086e7c
MY		 784
785 if (qz_offset > p_hwfn->p_rdma_info->max_queue_zones) {
786 DP_NOTICE(p_hwfn,
787 "queue zone offset %d is too large (max is %d)\n",
788 qz_offset, p_hwfn->p_rdma_info->max_queue_zones);
789 return;
790 }
791
51ff1725
RA		 792 qz_num = p_hwfn->p_rdma_info->queue_zone_base + qz_offset;
793 addr = GTT_BAR0_MAP_REG_USDM_RAM +
794 USTORM_COMMON_QUEUE_CONS_OFFSET(qz_num);
795
796 REG_WR16(p_hwfn, addr, prod);
797
798 /* keep prod updates ordered */
799 wmb();
800}
801
802static int qed_fill_rdma_dev_info(struct qed_dev *cdev,
803 struct qed_dev_rdma_info *info)
804{
805 memset(info, 0, sizeof(*info));
806
807 info->rdma_type = QED_RDMA_TYPE_ROCE;
808
809 qed_fill_dev_info(cdev, &info->common);
810
811 return 0;
812}
813
814static int qed_rdma_get_sb_start(struct qed_dev *cdev)
815{
816 int feat_num;
817
818 if (cdev->num_hwfns > 1)
819 feat_num = FEAT_NUM(QED_LEADING_HWFN(cdev), QED_PF_L2_QUE);
820 else
821 feat_num = FEAT_NUM(QED_LEADING_HWFN(cdev), QED_PF_L2_QUE) *
822 cdev->num_hwfns;
823
824 return feat_num;
825}
826
827static int qed_rdma_get_min_cnq_msix(struct qed_dev *cdev)
828{
829 int n_cnq = FEAT_NUM(QED_LEADING_HWFN(cdev), QED_RDMA_CNQ);
830 int n_msix = cdev->int_params.rdma_msix_cnt;
831
832 return min_t(int, n_cnq, n_msix);
833}
834
835static int qed_rdma_set_int(struct qed_dev *cdev, u16 cnt)
836{
837 int limit = 0;
838
839 /* Mark the fastpath as free/used */
840 cdev->int_params.fp_initialized = cnt ? true : false;
841
842 if (cdev->int_params.out.int_mode != QED_INT_MODE_MSIX) {
843 DP_ERR(cdev,
844 "qed roce supports only MSI-X interrupts (detected %d).\n",
845 cdev->int_params.out.int_mode);
846 return -EINVAL;
847 } else if (cdev->int_params.fp_msix_cnt) {
848 limit = cdev->int_params.rdma_msix_cnt;
849 }
850
851 if (!limit)
852 return -ENOMEM;
853
854 return min_t(int, cnt, limit);
855}
856
857static int qed_rdma_get_int(struct qed_dev *cdev, struct qed_int_info *info)
858{
859 memset(info, 0, sizeof(*info));
860
861 if (!cdev->int_params.fp_initialized) {
862 DP_INFO(cdev,
863 "Protocol driver requested interrupt information, but its support is not yet configured\n");
864 return -EINVAL;
865 }
866
867 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
868 int msix_base = cdev->int_params.rdma_msix_base;
869
870 info->msix_cnt = cdev->int_params.rdma_msix_cnt;
871 info->msix = &cdev->int_params.msix_table[msix_base];
872
873 DP_VERBOSE(cdev, QED_MSG_RDMA, "msix_cnt = %d msix_base=%d\n",
874 info->msix_cnt, msix_base);
875 }
876
877 return 0;
878}
879
0189efb8 880static int qed_rdma_alloc_pd(void *rdma_cxt, u16 *pd)
c295f86e
RA		 881{
882 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
883 u32 returned_id;
884 int rc;
885
886 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Alloc PD\n");
887
888 /* Allocates an unused protection domain */
889 spin_lock_bh(&p_hwfn->p_rdma_info->lock);
890 rc = qed_rdma_bmap_alloc_id(p_hwfn,
891 &p_hwfn->p_rdma_info->pd_map, &returned_id);
892 spin_unlock_bh(&p_hwfn->p_rdma_info->lock);
893
894 *pd = (u16)returned_id;
895
896 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Alloc PD - done, rc = %d\n", rc);
897 return rc;
898}
899
8c93beaf 900static void qed_rdma_free_pd(void *rdma_cxt, u16 pd)
c295f86e
RA		 901{
902 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
903
904 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "pd = %08x\n", pd);
905
906 /* Returns a previously allocated protection domain for reuse */
907 spin_lock_bh(&p_hwfn->p_rdma_info->lock);
908 qed_bmap_release_id(p_hwfn, &p_hwfn->p_rdma_info->pd_map, pd);
909 spin_unlock_bh(&p_hwfn->p_rdma_info->lock);
910}
911
912static enum qed_rdma_toggle_bit
913qed_rdma_toggle_bit_create_resize_cq(struct qed_hwfn *p_hwfn, u16 icid)
914{
915 struct qed_rdma_info *p_info = p_hwfn->p_rdma_info;
916 enum qed_rdma_toggle_bit toggle_bit;
917 u32 bmap_id;
918
919 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", icid);
920
921 /* the function toggle the bit that is related to a given icid
922 * and returns the new toggle bit's value
923 */
924 bmap_id = icid - qed_cxt_get_proto_cid_start(p_hwfn, p_info->proto);
925
926 spin_lock_bh(&p_info->lock);
927 toggle_bit = !test_and_change_bit(bmap_id,
928 p_info->toggle_bits.bitmap);
929 spin_unlock_bh(&p_info->lock);
930
931 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "QED_RDMA_TOGGLE_BIT_= %d\n",
932 toggle_bit);
933
934 return toggle_bit;
935}
936
8c93beaf
YM		 937static int qed_rdma_create_cq(void *rdma_cxt,
938 struct qed_rdma_create_cq_in_params *params,
939 u16 *icid)
c295f86e
RA		 940{
941 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
942 struct qed_rdma_info *p_info = p_hwfn->p_rdma_info;
943 struct rdma_create_cq_ramrod_data *p_ramrod;
944 enum qed_rdma_toggle_bit toggle_bit;
945 struct qed_sp_init_data init_data;
946 struct qed_spq_entry *p_ent;
947 u32 returned_id, start_cid;
948 int rc;
949
950 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "cq_handle = %08x%08x\n",
951 params->cq_handle_hi, params->cq_handle_lo);
952
953 /* Allocate icid */
954 spin_lock_bh(&p_info->lock);
955 rc = qed_rdma_bmap_alloc_id(p_hwfn,
956 &p_info->cq_map, &returned_id);
957 spin_unlock_bh(&p_info->lock);
958
959 if (rc) {
960 DP_NOTICE(p_hwfn, "Can't create CQ, rc = %d\n", rc);
961 return rc;
962 }
963
964 start_cid = qed_cxt_get_proto_cid_start(p_hwfn,
965 p_info->proto);
966 *icid = returned_id + start_cid;
967
968 /* Check if icid requires a page allocation */
969 rc = qed_cxt_dynamic_ilt_alloc(p_hwfn, QED_ELEM_CXT, *icid);
970 if (rc)
971 goto err;
972
973 /* Get SPQ entry */
974 memset(&init_data, 0, sizeof(init_data));
975 init_data.cid = *icid;
976 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
977 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
978
979 /* Send create CQ ramrod */
980 rc = qed_sp_init_request(p_hwfn, &p_ent,
981 RDMA_RAMROD_CREATE_CQ,
982 p_info->proto, &init_data);
983 if (rc)
984 goto err;
985
986 p_ramrod = &p_ent->ramrod.rdma_create_cq;
987
988 p_ramrod->cq_handle.hi = cpu_to_le32(params->cq_handle_hi);
989 p_ramrod->cq_handle.lo = cpu_to_le32(params->cq_handle_lo);
990 p_ramrod->dpi = cpu_to_le16(params->dpi);
991 p_ramrod->is_two_level_pbl = params->pbl_two_level;
992 p_ramrod->max_cqes = cpu_to_le32(params->cq_size);
993 DMA_REGPAIR_LE(p_ramrod->pbl_addr, params->pbl_ptr);
994 p_ramrod->pbl_num_pages = cpu_to_le16(params->pbl_num_pages);
995 p_ramrod->cnq_id = (u8)RESC_START(p_hwfn, QED_RDMA_CNQ_RAM) +
996 params->cnq_id;
997 p_ramrod->int_timeout = params->int_timeout;
998
999 /* toggle the bit for every resize or create cq for a given icid */
1000 toggle_bit = qed_rdma_toggle_bit_create_resize_cq(p_hwfn, *icid);
1001
1002 p_ramrod->toggle_bit = toggle_bit;
1003
1004 rc = qed_spq_post(p_hwfn, p_ent, NULL);
1005 if (rc) {
1006 /* restore toggle bit */
1007 qed_rdma_toggle_bit_create_resize_cq(p_hwfn, *icid);
1008 goto err;
1009 }
1010
1011 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Created CQ, rc = %d\n", rc);
1012 return rc;
1013
1014err:
1015 /* release allocated icid */
670dde55 1016 spin_lock_bh(&p_info->lock);
c295f86e 1017 qed_bmap_release_id(p_hwfn, &p_info->cq_map, returned_id);
670dde55 1018 spin_unlock_bh(&p_info->lock);
c295f86e
RA		 1019 DP_NOTICE(p_hwfn, "Create CQ failed, rc = %d\n", rc);
1020
1021 return rc;
1022}
1023
8c93beaf
YM		 1024static int
1025qed_rdma_destroy_cq(void *rdma_cxt,
1026 struct qed_rdma_destroy_cq_in_params *in_params,
1027 struct qed_rdma_destroy_cq_out_params *out_params)
c295f86e
RA		 1028{
1029 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
1030 struct rdma_destroy_cq_output_params *p_ramrod_res;
1031 struct rdma_destroy_cq_ramrod_data *p_ramrod;
1032 struct qed_sp_init_data init_data;
1033 struct qed_spq_entry *p_ent;
1034 dma_addr_t ramrod_res_phys;
1035 int rc = -ENOMEM;
1036
1037 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", in_params->icid);
1038
1039 p_ramrod_res =
1040 (struct rdma_destroy_cq_output_params *)
1041 dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
1042 sizeof(struct rdma_destroy_cq_output_params),
1043 &ramrod_res_phys, GFP_KERNEL);
1044 if (!p_ramrod_res) {
1045 DP_NOTICE(p_hwfn,
1046 "qed destroy cq failed: cannot allocate memory (ramrod)\n");
1047 return rc;
1048 }
1049
1050 /* Get SPQ entry */
1051 memset(&init_data, 0, sizeof(init_data));
1052 init_data.cid = in_params->icid;
1053 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
1054 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
1055
1056 /* Send destroy CQ ramrod */
1057 rc = qed_sp_init_request(p_hwfn, &p_ent,
1058 RDMA_RAMROD_DESTROY_CQ,
1059 p_hwfn->p_rdma_info->proto, &init_data);
1060 if (rc)
1061 goto err;
1062
1063 p_ramrod = &p_ent->ramrod.rdma_destroy_cq;
1064 DMA_REGPAIR_LE(p_ramrod->output_params_addr, ramrod_res_phys);
1065
1066 rc = qed_spq_post(p_hwfn, p_ent, NULL);
1067 if (rc)
1068 goto err;
1069
1070 out_params->num_cq_notif = le16_to_cpu(p_ramrod_res->cnq_num);
1071
1072 dma_free_coherent(&p_hwfn->cdev->pdev->dev,
1073 sizeof(struct rdma_destroy_cq_output_params),
1074 p_ramrod_res, ramrod_res_phys);
1075
1076 /* Free icid */
1077 spin_lock_bh(&p_hwfn->p_rdma_info->lock);
1078
1079 qed_bmap_release_id(p_hwfn,
1080 &p_hwfn->p_rdma_info->cq_map,
1081 (in_params->icid -
1082 qed_cxt_get_proto_cid_start(p_hwfn,
1083 p_hwfn->
1084 p_rdma_info->proto)));
1085
1086 spin_unlock_bh(&p_hwfn->p_rdma_info->lock);
1087
1088 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Destroyed CQ, rc = %d\n", rc);
1089 return rc;
1090
1091err: dma_free_coherent(&p_hwfn->cdev->pdev->dev,
1092 sizeof(struct rdma_destroy_cq_output_params),
1093 p_ramrod_res, ramrod_res_phys);
1094
1095 return rc;
1096}
1097
f1093940
RA		 1098static void qed_rdma_set_fw_mac(u16 *p_fw_mac, u8 *p_qed_mac)
1099{
1100 p_fw_mac[0] = cpu_to_le16((p_qed_mac[0] << 8) + p_qed_mac[1]);
1101 p_fw_mac[1] = cpu_to_le16((p_qed_mac[2] << 8) + p_qed_mac[3]);
1102 p_fw_mac[2] = cpu_to_le16((p_qed_mac[4] << 8) + p_qed_mac[5]);
1103}
1104
1105static void qed_rdma_copy_gids(struct qed_rdma_qp *qp, __le32 *src_gid,
1106 __le32 *dst_gid)
1107{
1108 u32 i;
1109
1110 if (qp->roce_mode == ROCE_V2_IPV4) {
1111 /* The IPv4 addresses shall be aligned to the highest word.
1112 * The lower words must be zero.
1113 */
1114 memset(src_gid, 0, sizeof(union qed_gid));
1115 memset(dst_gid, 0, sizeof(union qed_gid));
1116 src_gid[3] = cpu_to_le32(qp->sgid.ipv4_addr);
1117 dst_gid[3] = cpu_to_le32(qp->dgid.ipv4_addr);
1118 } else {
1119 /* GIDs and IPv6 addresses coincide in location and size */
1120 for (i = 0; i < ARRAY_SIZE(qp->sgid.dwords); i++) {
1121 src_gid[i] = cpu_to_le32(qp->sgid.dwords[i]);
1122 dst_gid[i] = cpu_to_le32(qp->dgid.dwords[i]);
1123 }
1124 }
1125}
1126
1127static enum roce_flavor qed_roce_mode_to_flavor(enum roce_mode roce_mode)
1128{
1129 enum roce_flavor flavor;
1130
1131 switch (roce_mode) {
1132 case ROCE_V1:
1133 flavor = PLAIN_ROCE;
1134 break;
1135 case ROCE_V2_IPV4:
1136 flavor = RROCE_IPV4;
1137 break;
1138 case ROCE_V2_IPV6:
1139 flavor = ROCE_V2_IPV6;
1140 break;
1141 default:
1142 flavor = MAX_ROCE_MODE;
1143 break;
1144 }
1145 return flavor;
1146}
1147
be086e7c
MY		 1148void qed_roce_free_cid_pair(struct qed_hwfn *p_hwfn, u16 cid)
1149{
1150 spin_lock_bh(&p_hwfn->p_rdma_info->lock);
1151 qed_bmap_release_id(p_hwfn, &p_hwfn->p_rdma_info->cid_map, cid);
1152 qed_bmap_release_id(p_hwfn, &p_hwfn->p_rdma_info->cid_map, cid + 1);
1153 spin_unlock_bh(&p_hwfn->p_rdma_info->lock);
1154}
1155
8c93beaf 1156static int qed_roce_alloc_cid(struct qed_hwfn *p_hwfn, u16 *cid)
f1093940
RA		 1157{
1158 struct qed_rdma_info *p_rdma_info = p_hwfn->p_rdma_info;
1159 u32 responder_icid;
1160 u32 requester_icid;
1161 int rc;
1162
1163 spin_lock_bh(&p_hwfn->p_rdma_info->lock);
1164 rc = qed_rdma_bmap_alloc_id(p_hwfn, &p_rdma_info->cid_map,
1165 &responder_icid);
1166 if (rc) {
1167 spin_unlock_bh(&p_rdma_info->lock);
1168 return rc;
1169 }
1170
1171 rc = qed_rdma_bmap_alloc_id(p_hwfn, &p_rdma_info->cid_map,
1172 &requester_icid);
1173
1174 spin_unlock_bh(&p_rdma_info->lock);
1175 if (rc)
1176 goto err;
1177
1178 /* the two icid's should be adjacent */
1179 if ((requester_icid - responder_icid) != 1) {
1180 DP_NOTICE(p_hwfn, "Failed to allocate two adjacent qp's'\n");
1181 rc = -EINVAL;
1182 goto err;
1183 }
1184
1185 responder_icid += qed_cxt_get_proto_cid_start(p_hwfn,
1186 p_rdma_info->proto);
1187 requester_icid += qed_cxt_get_proto_cid_start(p_hwfn,
1188 p_rdma_info->proto);
1189
1190 /* If these icids require a new ILT line allocate DMA-able context for
1191 * an ILT page
1192 */
1193 rc = qed_cxt_dynamic_ilt_alloc(p_hwfn, QED_ELEM_CXT, responder_icid);
1194 if (rc)
1195 goto err;
1196
1197 rc = qed_cxt_dynamic_ilt_alloc(p_hwfn, QED_ELEM_CXT, requester_icid);
1198 if (rc)
1199 goto err;
1200
1201 *cid = (u16)responder_icid;
1202 return rc;
1203
1204err:
1205 spin_lock_bh(&p_rdma_info->lock);
1206 qed_bmap_release_id(p_hwfn, &p_rdma_info->cid_map, responder_icid);
1207 qed_bmap_release_id(p_hwfn, &p_rdma_info->cid_map, requester_icid);
1208
1209 spin_unlock_bh(&p_rdma_info->lock);
1210 DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
1211 "Allocate CID - failed, rc = %d\n", rc);
1212 return rc;
1213}
1214
be086e7c
MY		 1215static void qed_roce_set_real_cid(struct qed_hwfn *p_hwfn, u32 cid)
1216{
1217 spin_lock_bh(&p_hwfn->p_rdma_info->lock);
1218 qed_bmap_set_id(p_hwfn, &p_hwfn->p_rdma_info->real_cid_map, cid);
1219 spin_unlock_bh(&p_hwfn->p_rdma_info->lock);
1220}
1221
f1093940
RA		 1222static int qed_roce_sp_create_responder(struct qed_hwfn *p_hwfn,
1223 struct qed_rdma_qp *qp)
1224{
1225 struct roce_create_qp_resp_ramrod_data *p_ramrod;
1226 struct qed_sp_init_data init_data;
1227 union qed_qm_pq_params qm_params;
1228 enum roce_flavor roce_flavor;
1229 struct qed_spq_entry *p_ent;
be086e7c
MY		 1230 u16 regular_latency_queue;
1231 enum protocol_type proto;
f1093940
RA		 1232 int rc;
1233
1234 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid);
1235
1236 /* Allocate DMA-able memory for IRQ */
1237 qp->irq_num_pages = 1;
1238 qp->irq = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
1239 RDMA_RING_PAGE_SIZE,
1240 &qp->irq_phys_addr, GFP_KERNEL);
1241 if (!qp->irq) {
1242 rc = -ENOMEM;
1243 DP_NOTICE(p_hwfn,
1244 "qed create responder failed: cannot allocate memory (irq). rc = %d\n",
1245 rc);
1246 return rc;
1247 }
1248
1249 /* Get SPQ entry */
1250 memset(&init_data, 0, sizeof(init_data));
1251 init_data.cid = qp->icid;
1252 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
1253 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
1254
1255 rc = qed_sp_init_request(p_hwfn, &p_ent, ROCE_RAMROD_CREATE_QP,
1256 PROTOCOLID_ROCE, &init_data);
1257 if (rc)
1258 goto err;
1259
1260 p_ramrod = &p_ent->ramrod.roce_create_qp_resp;
1261
1262 p_ramrod->flags = 0;
1263
1264 roce_flavor = qed_roce_mode_to_flavor(qp->roce_mode);
1265 SET_FIELD(p_ramrod->flags,
1266 ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR, roce_flavor);
1267
1268 SET_FIELD(p_ramrod->flags,
1269 ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN,
1270 qp->incoming_rdma_read_en);
1271
1272 SET_FIELD(p_ramrod->flags,
1273 ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN,
1274 qp->incoming_rdma_write_en);
1275
1276 SET_FIELD(p_ramrod->flags,
1277 ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN,
1278 qp->incoming_atomic_en);
1279
1280 SET_FIELD(p_ramrod->flags,
1281 ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN,
1282 qp->e2e_flow_control_en);
1283
1284 SET_FIELD(p_ramrod->flags,
1285 ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG, qp->use_srq);
1286
1287 SET_FIELD(p_ramrod->flags,
1288 ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN,
1289 qp->fmr_and_reserved_lkey);
1290
1291 SET_FIELD(p_ramrod->flags,
1292 ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER,
1293 qp->min_rnr_nak_timer);
1294
1295 p_ramrod->max_ird = qp->max_rd_atomic_resp;
1296 p_ramrod->traffic_class = qp->traffic_class_tos;
1297 p_ramrod->hop_limit = qp->hop_limit_ttl;
1298 p_ramrod->irq_num_pages = qp->irq_num_pages;
1299 p_ramrod->p_key = cpu_to_le16(qp->pkey);
1300 p_ramrod->flow_label = cpu_to_le32(qp->flow_label);
1301 p_ramrod->dst_qp_id = cpu_to_le32(qp->dest_qp);
1302 p_ramrod->mtu = cpu_to_le16(qp->mtu);
1303 p_ramrod->initial_psn = cpu_to_le32(qp->rq_psn);
1304 p_ramrod->pd = cpu_to_le16(qp->pd);
1305 p_ramrod->rq_num_pages = cpu_to_le16(qp->rq_num_pages);
1306 DMA_REGPAIR_LE(p_ramrod->rq_pbl_addr, qp->rq_pbl_ptr);
1307 DMA_REGPAIR_LE(p_ramrod->irq_pbl_addr, qp->irq_phys_addr);
1308 qed_rdma_copy_gids(qp, p_ramrod->src_gid, p_ramrod->dst_gid);
1309 p_ramrod->qp_handle_for_async.hi = cpu_to_le32(qp->qp_handle_async.hi);
1310 p_ramrod->qp_handle_for_async.lo = cpu_to_le32(qp->qp_handle_async.lo);
1311 p_ramrod->qp_handle_for_cqe.hi = cpu_to_le32(qp->qp_handle.hi);
1312 p_ramrod->qp_handle_for_cqe.lo = cpu_to_le32(qp->qp_handle.lo);
f1093940
RA		 1313 p_ramrod->cq_cid = cpu_to_le32((p_hwfn->hw_info.opaque_fid << 16) |
1314 qp->rq_cq_id);
1315
1316 memset(&qm_params, 0, sizeof(qm_params));
1317 qm_params.roce.qpid = qp->icid >> 1;
be086e7c
MY		 1318 regular_latency_queue = qed_get_qm_pq(p_hwfn, PROTOCOLID_ROCE,
1319 &qm_params);
1320
1321 p_ramrod->regular_latency_phy_queue =
1322 cpu_to_le16(regular_latency_queue);
1323 p_ramrod->low_latency_phy_queue =
1324 cpu_to_le16(regular_latency_queue);
f1093940 1325
f1093940
RA		 1326 p_ramrod->dpi = cpu_to_le16(qp->dpi);
1327
1328 qed_rdma_set_fw_mac(p_ramrod->remote_mac_addr, qp->remote_mac_addr);
1329 qed_rdma_set_fw_mac(p_ramrod->local_mac_addr, qp->local_mac_addr);
1330
1331 p_ramrod->udp_src_port = qp->udp_src_port;
1332 p_ramrod->vlan_id = cpu_to_le16(qp->vlan_id);
1333 p_ramrod->srq_id.srq_idx = cpu_to_le16(qp->srq_id);
1334 p_ramrod->srq_id.opaque_fid = cpu_to_le16(p_hwfn->hw_info.opaque_fid);
1335
1336 p_ramrod->stats_counter_id = RESC_START(p_hwfn, QED_RDMA_STATS_QUEUE) +
1337 qp->stats_queue;
1338
1339 rc = qed_spq_post(p_hwfn, p_ent, NULL);
1340
be086e7c
MY		 1341 DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
1342 "rc = %d regular physical queue = 0x%x\n", rc,
1343 regular_latency_queue);
f1093940
RA		 1344
1345 if (rc)
1346 goto err;
1347
1348 qp->resp_offloaded = true;
be086e7c
MY		 1349 qp->cq_prod = 0;
1350
1351 proto = p_hwfn->p_rdma_info->proto;
1352 qed_roce_set_real_cid(p_hwfn, qp->icid -
1353 qed_cxt_get_proto_cid_start(p_hwfn, proto));
f1093940
RA		 1354
1355 return rc;
1356
1357err:
1358 DP_NOTICE(p_hwfn, "create responder - failed, rc = %d\n", rc);
1359 dma_free_coherent(&p_hwfn->cdev->pdev->dev,
1360 qp->irq_num_pages * RDMA_RING_PAGE_SIZE,
1361 qp->irq, qp->irq_phys_addr);
1362
1363 return rc;
1364}
1365
1366static int qed_roce_sp_create_requester(struct qed_hwfn *p_hwfn,
1367 struct qed_rdma_qp *qp)
1368{
1369 struct roce_create_qp_req_ramrod_data *p_ramrod;
1370 struct qed_sp_init_data init_data;
1371 union qed_qm_pq_params qm_params;
1372 enum roce_flavor roce_flavor;
1373 struct qed_spq_entry *p_ent;
be086e7c
MY		 1374 u16 regular_latency_queue;
1375 enum protocol_type proto;
f1093940
RA		 1376 int rc;
1377
1378 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid);
1379
1380 /* Allocate DMA-able memory for ORQ */
1381 qp->orq_num_pages = 1;
1382 qp->orq = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
1383 RDMA_RING_PAGE_SIZE,
1384 &qp->orq_phys_addr, GFP_KERNEL);
1385 if (!qp->orq) {
1386 rc = -ENOMEM;
1387 DP_NOTICE(p_hwfn,
1388 "qed create requester failed: cannot allocate memory (orq). rc = %d\n",
1389 rc);
1390 return rc;
1391 }
1392
1393 /* Get SPQ entry */
1394 memset(&init_data, 0, sizeof(init_data));
1395 init_data.cid = qp->icid + 1;
1396 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
1397 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
1398
1399 rc = qed_sp_init_request(p_hwfn, &p_ent,
1400 ROCE_RAMROD_CREATE_QP,
1401 PROTOCOLID_ROCE, &init_data);
1402 if (rc)
1403 goto err;
1404
1405 p_ramrod = &p_ent->ramrod.roce_create_qp_req;
1406
1407 p_ramrod->flags = 0;
1408
1409 roce_flavor = qed_roce_mode_to_flavor(qp->roce_mode);
1410 SET_FIELD(p_ramrod->flags,
1411 ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR, roce_flavor);
1412
1413 SET_FIELD(p_ramrod->flags,
1414 ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN,
1415 qp->fmr_and_reserved_lkey);
1416
1417 SET_FIELD(p_ramrod->flags,
1418 ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP, qp->signal_all);
1419
1420 SET_FIELD(p_ramrod->flags,
1421 ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT, qp->retry_cnt);
1422
1423 SET_FIELD(p_ramrod->flags,
1424 ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT,
1425 qp->rnr_retry_cnt);
1426
1427 p_ramrod->max_ord = qp->max_rd_atomic_req;
1428 p_ramrod->traffic_class = qp->traffic_class_tos;
1429 p_ramrod->hop_limit = qp->hop_limit_ttl;
1430 p_ramrod->orq_num_pages = qp->orq_num_pages;
1431 p_ramrod->p_key = cpu_to_le16(qp->pkey);
1432 p_ramrod->flow_label = cpu_to_le32(qp->flow_label);
1433 p_ramrod->dst_qp_id = cpu_to_le32(qp->dest_qp);
1434 p_ramrod->ack_timeout_val = cpu_to_le32(qp->ack_timeout);
1435 p_ramrod->mtu = cpu_to_le16(qp->mtu);
1436 p_ramrod->initial_psn = cpu_to_le32(qp->sq_psn);
1437 p_ramrod->pd = cpu_to_le16(qp->pd);
1438 p_ramrod->sq_num_pages = cpu_to_le16(qp->sq_num_pages);
1439 DMA_REGPAIR_LE(p_ramrod->sq_pbl_addr, qp->sq_pbl_ptr);
1440 DMA_REGPAIR_LE(p_ramrod->orq_pbl_addr, qp->orq_phys_addr);
1441 qed_rdma_copy_gids(qp, p_ramrod->src_gid, p_ramrod->dst_gid);
1442 p_ramrod->qp_handle_for_async.hi = cpu_to_le32(qp->qp_handle_async.hi);
1443 p_ramrod->qp_handle_for_async.lo = cpu_to_le32(qp->qp_handle_async.lo);
1444 p_ramrod->qp_handle_for_cqe.hi = cpu_to_le32(qp->qp_handle.hi);
1445 p_ramrod->qp_handle_for_cqe.lo = cpu_to_le32(qp->qp_handle.lo);
be086e7c
MY		 1446 p_ramrod->cq_cid =
1447 cpu_to_le32((p_hwfn->hw_info.opaque_fid << 16) | qp->sq_cq_id);
f1093940
RA		 1448
1449 memset(&qm_params, 0, sizeof(qm_params));
1450 qm_params.roce.qpid = qp->icid >> 1;
be086e7c
MY		 1451 regular_latency_queue = qed_get_qm_pq(p_hwfn, PROTOCOLID_ROCE,
1452 &qm_params);
1453
1454 p_ramrod->regular_latency_phy_queue =
1455 cpu_to_le16(regular_latency_queue);
1456 p_ramrod->low_latency_phy_queue =
1457 cpu_to_le16(regular_latency_queue);
f1093940 1458
f1093940
RA		 1459 p_ramrod->dpi = cpu_to_le16(qp->dpi);
1460
1461 qed_rdma_set_fw_mac(p_ramrod->remote_mac_addr, qp->remote_mac_addr);
1462 qed_rdma_set_fw_mac(p_ramrod->local_mac_addr, qp->local_mac_addr);
1463
1464 p_ramrod->udp_src_port = qp->udp_src_port;
1465 p_ramrod->vlan_id = cpu_to_le16(qp->vlan_id);
1466 p_ramrod->stats_counter_id = RESC_START(p_hwfn, QED_RDMA_STATS_QUEUE) +
1467 qp->stats_queue;
1468
1469 rc = qed_spq_post(p_hwfn, p_ent, NULL);
1470
1471 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "rc = %d\n", rc);
1472
1473 if (rc)
1474 goto err;
1475
1476 qp->req_offloaded = true;
be086e7c
MY		 1477 proto = p_hwfn->p_rdma_info->proto;
1478 qed_roce_set_real_cid(p_hwfn,
1479 qp->icid + 1 -
1480 qed_cxt_get_proto_cid_start(p_hwfn, proto));
f1093940
RA		 1481
1482 return rc;
1483
1484err:
1485 DP_NOTICE(p_hwfn, "Create requested - failed, rc = %d\n", rc);
1486 dma_free_coherent(&p_hwfn->cdev->pdev->dev,
1487 qp->orq_num_pages * RDMA_RING_PAGE_SIZE,
1488 qp->orq, qp->orq_phys_addr);
1489 return rc;
1490}
1491
1492static int qed_roce_sp_modify_responder(struct qed_hwfn *p_hwfn,
1493 struct qed_rdma_qp *qp,
1494 bool move_to_err, u32 modify_flags)
1495{
1496 struct roce_modify_qp_resp_ramrod_data *p_ramrod;
1497 struct qed_sp_init_data init_data;
1498 struct qed_spq_entry *p_ent;
1499 int rc;
1500
1501 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid);
1502
1503 if (move_to_err && !qp->resp_offloaded)
1504 return 0;
1505
1506 /* Get SPQ entry */
1507 memset(&init_data, 0, sizeof(init_data));
1508 init_data.cid = qp->icid;
1509 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
1510 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
1511
1512 rc = qed_sp_init_request(p_hwfn, &p_ent,
1513 ROCE_EVENT_MODIFY_QP,
1514 PROTOCOLID_ROCE, &init_data);
1515 if (rc) {
1516 DP_NOTICE(p_hwfn, "rc = %d\n", rc);
1517 return rc;
1518 }
1519
1520 p_ramrod = &p_ent->ramrod.roce_modify_qp_resp;
1521
1522 p_ramrod->flags = 0;
1523
1524 SET_FIELD(p_ramrod->flags,
1525 ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG, move_to_err);
1526
1527 SET_FIELD(p_ramrod->flags,
1528 ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN,
1529 qp->incoming_rdma_read_en);
1530
1531 SET_FIELD(p_ramrod->flags,
1532 ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN,
1533 qp->incoming_rdma_write_en);
1534
1535 SET_FIELD(p_ramrod->flags,
1536 ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN,
1537 qp->incoming_atomic_en);
1538
1539 SET_FIELD(p_ramrod->flags,
1540 ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN,
1541 qp->e2e_flow_control_en);
1542
1543 SET_FIELD(p_ramrod->flags,
1544 ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG,
1545 GET_FIELD(modify_flags,
1546 QED_RDMA_MODIFY_QP_VALID_RDMA_OPS_EN));
1547
1548 SET_FIELD(p_ramrod->flags,
1549 ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG,
1550 GET_FIELD(modify_flags, QED_ROCE_MODIFY_QP_VALID_PKEY));
1551
1552 SET_FIELD(p_ramrod->flags,
1553 ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG,
1554 GET_FIELD(modify_flags,
1555 QED_ROCE_MODIFY_QP_VALID_ADDRESS_VECTOR));
1556
1557 SET_FIELD(p_ramrod->flags,
1558 ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG,
1559 GET_FIELD(modify_flags,
1560 QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_RESP));
1561
1562 SET_FIELD(p_ramrod->flags,
1563 ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG,
1564 GET_FIELD(modify_flags,
1565 QED_ROCE_MODIFY_QP_VALID_MIN_RNR_NAK_TIMER));
1566
1567 p_ramrod->fields = 0;
1568 SET_FIELD(p_ramrod->fields,
1569 ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER,
1570 qp->min_rnr_nak_timer);
1571
1572 p_ramrod->max_ird = qp->max_rd_atomic_resp;
1573 p_ramrod->traffic_class = qp->traffic_class_tos;
1574 p_ramrod->hop_limit = qp->hop_limit_ttl;
1575 p_ramrod->p_key = cpu_to_le16(qp->pkey);
1576 p_ramrod->flow_label = cpu_to_le32(qp->flow_label);
1577 p_ramrod->mtu = cpu_to_le16(qp->mtu);
1578 qed_rdma_copy_gids(qp, p_ramrod->src_gid, p_ramrod->dst_gid);
1579 rc = qed_spq_post(p_hwfn, p_ent, NULL);
1580
1581 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Modify responder, rc = %d\n", rc);
1582 return rc;
1583}
1584
1585static int qed_roce_sp_modify_requester(struct qed_hwfn *p_hwfn,
1586 struct qed_rdma_qp *qp,
1587 bool move_to_sqd,
1588 bool move_to_err, u32 modify_flags)
1589{
1590 struct roce_modify_qp_req_ramrod_data *p_ramrod;
1591 struct qed_sp_init_data init_data;
1592 struct qed_spq_entry *p_ent;
1593 int rc;
1594
1595 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid);
1596
1597 if (move_to_err && !(qp->req_offloaded))
1598 return 0;
1599
1600 /* Get SPQ entry */
1601 memset(&init_data, 0, sizeof(init_data));
1602 init_data.cid = qp->icid + 1;
1603 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
1604 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
1605
1606 rc = qed_sp_init_request(p_hwfn, &p_ent,
1607 ROCE_EVENT_MODIFY_QP,
1608 PROTOCOLID_ROCE, &init_data);
1609 if (rc) {
1610 DP_NOTICE(p_hwfn, "rc = %d\n", rc);
1611 return rc;
1612 }
1613
1614 p_ramrod = &p_ent->ramrod.roce_modify_qp_req;
1615
1616 p_ramrod->flags = 0;
1617
1618 SET_FIELD(p_ramrod->flags,
1619 ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG, move_to_err);
1620
1621 SET_FIELD(p_ramrod->flags,
1622 ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG, move_to_sqd);
1623
1624 SET_FIELD(p_ramrod->flags,
1625 ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY,
1626 qp->sqd_async);
1627
1628 SET_FIELD(p_ramrod->flags,
1629 ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG,
1630 GET_FIELD(modify_flags, QED_ROCE_MODIFY_QP_VALID_PKEY));
1631
1632 SET_FIELD(p_ramrod->flags,
1633 ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG,
1634 GET_FIELD(modify_flags,
1635 QED_ROCE_MODIFY_QP_VALID_ADDRESS_VECTOR));
1636
1637 SET_FIELD(p_ramrod->flags,
1638 ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG,
1639 GET_FIELD(modify_flags,
1640 QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_REQ));
1641
1642 SET_FIELD(p_ramrod->flags,
1643 ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG,
1644 GET_FIELD(modify_flags,
1645 QED_ROCE_MODIFY_QP_VALID_RNR_RETRY_CNT));
1646
1647 SET_FIELD(p_ramrod->flags,
1648 ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG,
1649 GET_FIELD(modify_flags, QED_ROCE_MODIFY_QP_VALID_RETRY_CNT));
1650
1651 SET_FIELD(p_ramrod->flags,
1652 ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG,
1653 GET_FIELD(modify_flags,
1654 QED_ROCE_MODIFY_QP_VALID_ACK_TIMEOUT));
1655
1656 p_ramrod->fields = 0;
1657 SET_FIELD(p_ramrod->fields,
1658 ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT, qp->retry_cnt);
1659
1660 SET_FIELD(p_ramrod->fields,
1661 ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT,
1662 qp->rnr_retry_cnt);
1663
1664 p_ramrod->max_ord = qp->max_rd_atomic_req;
1665 p_ramrod->traffic_class = qp->traffic_class_tos;
1666 p_ramrod->hop_limit = qp->hop_limit_ttl;
1667 p_ramrod->p_key = cpu_to_le16(qp->pkey);
1668 p_ramrod->flow_label = cpu_to_le32(qp->flow_label);
1669 p_ramrod->ack_timeout_val = cpu_to_le32(qp->ack_timeout);
1670 p_ramrod->mtu = cpu_to_le16(qp->mtu);
1671 qed_rdma_copy_gids(qp, p_ramrod->src_gid, p_ramrod->dst_gid);
1672 rc = qed_spq_post(p_hwfn, p_ent, NULL);
1673
1674 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Modify requester, rc = %d\n", rc);
1675 return rc;
1676}
1677
1678static int qed_roce_sp_destroy_qp_responder(struct qed_hwfn *p_hwfn,
1679 struct qed_rdma_qp *qp,
be086e7c
MY		 1680 u32 *num_invalidated_mw,
1681 u32 *cq_prod)
f1093940
RA		 1682{
1683 struct roce_destroy_qp_resp_output_params *p_ramrod_res;
1684 struct roce_destroy_qp_resp_ramrod_data *p_ramrod;
1685 struct qed_sp_init_data init_data;
1686 struct qed_spq_entry *p_ent;
1687 dma_addr_t ramrod_res_phys;
1688 int rc;
1689
1690 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid);
1691
be086e7c
MY		 1692 *num_invalidated_mw = 0;
1693 *cq_prod = qp->cq_prod;
1694
1695 if (!qp->resp_offloaded) {
1696 /* If a responder was never offload, we need to free the cids
1697 * allocated in create_qp as a FW async event will never arrive
1698 */
1699 u32 cid;
1700
1701 cid = qp->icid -
1702 qed_cxt_get_proto_cid_start(p_hwfn,
1703 p_hwfn->p_rdma_info->proto);
1704 qed_roce_free_cid_pair(p_hwfn, (u16)cid);
1705
f1093940 1706 return 0;
be086e7c 1707 }
f1093940
RA		 1708
1709 /* Get SPQ entry */
1710 memset(&init_data, 0, sizeof(init_data));
1711 init_data.cid = qp->icid;
1712 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
1713 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
1714
1715 rc = qed_sp_init_request(p_hwfn, &p_ent,
1716 ROCE_RAMROD_DESTROY_QP,
1717 PROTOCOLID_ROCE, &init_data);
1718 if (rc)
1719 return rc;
1720
1721 p_ramrod = &p_ent->ramrod.roce_destroy_qp_resp;
1722
1723 p_ramrod_res = (struct roce_destroy_qp_resp_output_params *)
1724 dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_ramrod_res),
1725 &ramrod_res_phys, GFP_KERNEL);
1726
1727 if (!p_ramrod_res) {
1728 rc = -ENOMEM;
1729 DP_NOTICE(p_hwfn,
1730 "qed destroy responder failed: cannot allocate memory (ramrod). rc = %d\n",
1731 rc);
1732 return rc;
1733 }
1734
1735 DMA_REGPAIR_LE(p_ramrod->output_params_addr, ramrod_res_phys);
1736
1737 rc = qed_spq_post(p_hwfn, p_ent, NULL);
1738 if (rc)
1739 goto err;
1740
1741 *num_invalidated_mw = le32_to_cpu(p_ramrod_res->num_invalidated_mw);
be086e7c
MY		 1742 *cq_prod = le32_to_cpu(p_ramrod_res->cq_prod);
1743 qp->cq_prod = *cq_prod;
f1093940
RA		 1744
1745 /* Free IRQ - only if ramrod succeeded, in case FW is still using it */
1746 dma_free_coherent(&p_hwfn->cdev->pdev->dev,
1747 qp->irq_num_pages * RDMA_RING_PAGE_SIZE,
1748 qp->irq, qp->irq_phys_addr);
1749
1750 qp->resp_offloaded = false;
1751
1752 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Destroy responder, rc = %d\n", rc);
1753
1754err:
1755 dma_free_coherent(&p_hwfn->cdev->pdev->dev,
1756 sizeof(struct roce_destroy_qp_resp_output_params),
1757 p_ramrod_res, ramrod_res_phys);
1758
1759 return rc;
1760}
1761
1762static int qed_roce_sp_destroy_qp_requester(struct qed_hwfn *p_hwfn,
1763 struct qed_rdma_qp *qp,
1764 u32 *num_bound_mw)
1765{
1766 struct roce_destroy_qp_req_output_params *p_ramrod_res;
1767 struct roce_destroy_qp_req_ramrod_data *p_ramrod;
1768 struct qed_sp_init_data init_data;
1769 struct qed_spq_entry *p_ent;
1770 dma_addr_t ramrod_res_phys;
1771 int rc = -ENOMEM;
1772
1773 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid);
1774
1775 if (!qp->req_offloaded)
1776 return 0;
1777
1778 p_ramrod_res = (struct roce_destroy_qp_req_output_params *)
1779 dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
1780 sizeof(*p_ramrod_res),
1781 &ramrod_res_phys, GFP_KERNEL);
1782 if (!p_ramrod_res) {
1783 DP_NOTICE(p_hwfn,
1784 "qed destroy requester failed: cannot allocate memory (ramrod)\n");
1785 return rc;
1786 }
1787
1788 /* Get SPQ entry */
1789 memset(&init_data, 0, sizeof(init_data));
1790 init_data.cid = qp->icid + 1;
1791 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
1792 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
1793
1794 rc = qed_sp_init_request(p_hwfn, &p_ent, ROCE_RAMROD_DESTROY_QP,
1795 PROTOCOLID_ROCE, &init_data);
1796 if (rc)
1797 goto err;
1798
1799 p_ramrod = &p_ent->ramrod.roce_destroy_qp_req;
1800 DMA_REGPAIR_LE(p_ramrod->output_params_addr, ramrod_res_phys);
1801
1802 rc = qed_spq_post(p_hwfn, p_ent, NULL);
1803 if (rc)
1804 goto err;
1805
1806 *num_bound_mw = le32_to_cpu(p_ramrod_res->num_bound_mw);
1807
1808 /* Free ORQ - only if ramrod succeeded, in case FW is still using it */
1809 dma_free_coherent(&p_hwfn->cdev->pdev->dev,
1810 qp->orq_num_pages * RDMA_RING_PAGE_SIZE,
1811 qp->orq, qp->orq_phys_addr);
1812
1813 qp->req_offloaded = false;
1814
1815 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Destroy requester, rc = %d\n", rc);
1816
1817err:
1818 dma_free_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_ramrod_res),
1819 p_ramrod_res, ramrod_res_phys);
1820
1821 return rc;
1822}
1823
8c93beaf
YM		 1824static int qed_roce_query_qp(struct qed_hwfn *p_hwfn,
1825 struct qed_rdma_qp *qp,
1826 struct qed_rdma_query_qp_out_params *out_params)
f1093940
RA		 1827{
1828 struct roce_query_qp_resp_output_params *p_resp_ramrod_res;
1829 struct roce_query_qp_req_output_params *p_req_ramrod_res;
1830 struct roce_query_qp_resp_ramrod_data *p_resp_ramrod;
1831 struct roce_query_qp_req_ramrod_data *p_req_ramrod;
1832 struct qed_sp_init_data init_data;
1833 dma_addr_t resp_ramrod_res_phys;
1834 dma_addr_t req_ramrod_res_phys;
1835 struct qed_spq_entry *p_ent;
1836 bool rq_err_state;
1837 bool sq_err_state;
1838 bool sq_draining;
1839 int rc = -ENOMEM;
1840
1841 if ((!(qp->resp_offloaded)) && (!(qp->req_offloaded))) {
1842 /* We can't send ramrod to the fw since this qp wasn't offloaded
1843 * to the fw yet
1844 */
1845 out_params->draining = false;
1846 out_params->rq_psn = qp->rq_psn;
1847 out_params->sq_psn = qp->sq_psn;
1848 out_params->state = qp->cur_state;
1849
1850 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "No QPs as no offload\n");
1851 return 0;
1852 }
1853
1854 if (!(qp->resp_offloaded)) {
1855 DP_NOTICE(p_hwfn,
1856 "The responder's qp should be offloded before requester's\n");
1857 return -EINVAL;
1858 }
1859
1860 /* Send a query responder ramrod to FW to get RQ-PSN and state */
1861 p_resp_ramrod_res = (struct roce_query_qp_resp_output_params *)
1862 dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
1863 sizeof(*p_resp_ramrod_res),
1864 &resp_ramrod_res_phys, GFP_KERNEL);
1865 if (!p_resp_ramrod_res) {
1866 DP_NOTICE(p_hwfn,
1867 "qed query qp failed: cannot allocate memory (ramrod)\n");
1868 return rc;
1869 }
1870
1871 /* Get SPQ entry */
1872 memset(&init_data, 0, sizeof(init_data));
1873 init_data.cid = qp->icid;
1874 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
1875 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
1876 rc = qed_sp_init_request(p_hwfn, &p_ent, ROCE_RAMROD_QUERY_QP,
1877 PROTOCOLID_ROCE, &init_data);
1878 if (rc)
1879 goto err_resp;
1880
1881 p_resp_ramrod = &p_ent->ramrod.roce_query_qp_resp;
1882 DMA_REGPAIR_LE(p_resp_ramrod->output_params_addr, resp_ramrod_res_phys);
1883
1884 rc = qed_spq_post(p_hwfn, p_ent, NULL);
1885 if (rc)
1886 goto err_resp;
1887
f1093940
RA		 1888 out_params->rq_psn = le32_to_cpu(p_resp_ramrod_res->psn);
1889 rq_err_state = GET_FIELD(le32_to_cpu(p_resp_ramrod_res->err_flag),
1890 ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG);
1891
c5212b94
RA		 1892 dma_free_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_resp_ramrod_res),
1893 p_resp_ramrod_res, resp_ramrod_res_phys);
1894
f1093940
RA		 1895 if (!(qp->req_offloaded)) {
1896 /* Don't send query qp for the requester */
1897 out_params->sq_psn = qp->sq_psn;
1898 out_params->draining = false;
1899
1900 if (rq_err_state)
1901 qp->cur_state = QED_ROCE_QP_STATE_ERR;
1902
1903 out_params->state = qp->cur_state;
1904
1905 return 0;
1906 }
1907
1908 /* Send a query requester ramrod to FW to get SQ-PSN and state */
1909 p_req_ramrod_res = (struct roce_query_qp_req_output_params *)
1910 dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
1911 sizeof(*p_req_ramrod_res),
1912 &req_ramrod_res_phys,
1913 GFP_KERNEL);
1914 if (!p_req_ramrod_res) {
1915 rc = -ENOMEM;
1916 DP_NOTICE(p_hwfn,
1917 "qed query qp failed: cannot allocate memory (ramrod)\n");
1918 return rc;
1919 }
1920
1921 /* Get SPQ entry */
1922 init_data.cid = qp->icid + 1;
1923 rc = qed_sp_init_request(p_hwfn, &p_ent, ROCE_RAMROD_QUERY_QP,
1924 PROTOCOLID_ROCE, &init_data);
1925 if (rc)
1926 goto err_req;
1927
1928 p_req_ramrod = &p_ent->ramrod.roce_query_qp_req;
1929 DMA_REGPAIR_LE(p_req_ramrod->output_params_addr, req_ramrod_res_phys);
1930
1931 rc = qed_spq_post(p_hwfn, p_ent, NULL);
1932 if (rc)
1933 goto err_req;
1934
f1093940
RA		 1935 out_params->sq_psn = le32_to_cpu(p_req_ramrod_res->psn);
1936 sq_err_state = GET_FIELD(le32_to_cpu(p_req_ramrod_res->flags),
1937 ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG);
1938 sq_draining =
1939 GET_FIELD(le32_to_cpu(p_req_ramrod_res->flags),
1940 ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG);
1941
c5212b94
RA		 1942 dma_free_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_req_ramrod_res),
1943 p_req_ramrod_res, req_ramrod_res_phys);
1944
f1093940
RA		 1945 out_params->draining = false;
1946
be086e7c 1947 if (rq_err_state || sq_err_state)
f1093940 1948 qp->cur_state = QED_ROCE_QP_STATE_ERR;
f1093940
RA		 1949 else if (sq_draining)
1950 out_params->draining = true;
1951 out_params->state = qp->cur_state;
1952
1953 return 0;
1954
1955err_req:
1956 dma_free_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_req_ramrod_res),
1957 p_req_ramrod_res, req_ramrod_res_phys);
1958 return rc;
1959err_resp:
1960 dma_free_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_resp_ramrod_res),
1961 p_resp_ramrod_res, resp_ramrod_res_phys);
1962 return rc;
1963}
1964
8c93beaf 1965static int qed_roce_destroy_qp(struct qed_hwfn *p_hwfn, struct qed_rdma_qp *qp)
f1093940
RA		 1966{
1967 u32 num_invalidated_mw = 0;
1968 u32 num_bound_mw = 0;
be086e7c 1969 u32 cq_prod;
f1093940
RA		 1970 int rc;
1971
1972 /* Destroys the specified QP */
1973 if ((qp->cur_state != QED_ROCE_QP_STATE_RESET) &&
1974 (qp->cur_state != QED_ROCE_QP_STATE_ERR) &&
1975 (qp->cur_state != QED_ROCE_QP_STATE_INIT)) {
1976 DP_NOTICE(p_hwfn,
1977 "QP must be in error, reset or init state before destroying it\n");
1978 return -EINVAL;
1979 }
1980
300c0d7c
RA		 1981 if (qp->cur_state != QED_ROCE_QP_STATE_RESET) {
1982 rc = qed_roce_sp_destroy_qp_responder(p_hwfn, qp,
be086e7c
MY		 1983 &num_invalidated_mw,
1984 &cq_prod);
300c0d7c
RA		 1985 if (rc)
1986 return rc;
1987
1988 /* Send destroy requester ramrod */
1989 rc = qed_roce_sp_destroy_qp_requester(p_hwfn, qp,
1990 &num_bound_mw);
1991 if (rc)
1992 return rc;
1993
1994 if (num_invalidated_mw != num_bound_mw) {
1995 DP_NOTICE(p_hwfn,
1996 "number of invalidate memory windows is different from bounded ones\n");
1997 return -EINVAL;
1998 }
300c0d7c 1999 }
f1093940
RA		 2000
2001 return 0;
2002}
2003
0189efb8
YM		 2004static int qed_rdma_query_qp(void *rdma_cxt,
2005 struct qed_rdma_qp *qp,
2006 struct qed_rdma_query_qp_out_params *out_params)
f1093940
RA		 2007{
2008 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
2009 int rc;
2010
2011 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid);
2012
2013 /* The following fields are filled in from qp and not FW as they can't
2014 * be modified by FW
2015 */
2016 out_params->mtu = qp->mtu;
2017 out_params->dest_qp = qp->dest_qp;
2018 out_params->incoming_atomic_en = qp->incoming_atomic_en;
2019 out_params->e2e_flow_control_en = qp->e2e_flow_control_en;
2020 out_params->incoming_rdma_read_en = qp->incoming_rdma_read_en;
2021 out_params->incoming_rdma_write_en = qp->incoming_rdma_write_en;
2022 out_params->dgid = qp->dgid;
2023 out_params->flow_label = qp->flow_label;
2024 out_params->hop_limit_ttl = qp->hop_limit_ttl;
2025 out_params->traffic_class_tos = qp->traffic_class_tos;
2026 out_params->timeout = qp->ack_timeout;
2027 out_params->rnr_retry = qp->rnr_retry_cnt;
2028 out_params->retry_cnt = qp->retry_cnt;
2029 out_params->min_rnr_nak_timer = qp->min_rnr_nak_timer;
2030 out_params->pkey_index = 0;
2031 out_params->max_rd_atomic = qp->max_rd_atomic_req;
2032 out_params->max_dest_rd_atomic = qp->max_rd_atomic_resp;
2033 out_params->sqd_async = qp->sqd_async;
2034
2035 rc = qed_roce_query_qp(p_hwfn, qp, out_params);
2036
2037 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Query QP, rc = %d\n", rc);
2038 return rc;
2039}
2040
0189efb8 2041static int qed_rdma_destroy_qp(void *rdma_cxt, struct qed_rdma_qp *qp)
f1093940
RA		 2042{
2043 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
2044 int rc = 0;
2045
2046 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid);
2047
2048 rc = qed_roce_destroy_qp(p_hwfn, qp);
2049
2050 /* free qp params struct */
2051 kfree(qp);
2052
2053 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "QP destroyed\n");
2054 return rc;
2055}
2056
8c93beaf 2057static struct qed_rdma_qp *
f1093940
RA		 2058qed_rdma_create_qp(void *rdma_cxt,
2059 struct qed_rdma_create_qp_in_params *in_params,
2060 struct qed_rdma_create_qp_out_params *out_params)
2061{
2062 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
2063 struct qed_rdma_qp *qp;
2064 u8 max_stats_queues;
2065 int rc;
2066
2067 if (!rdma_cxt || !in_params || !out_params || !p_hwfn->p_rdma_info) {
2068 DP_ERR(p_hwfn->cdev,
2069 "qed roce create qp failed due to NULL entry (rdma_cxt=%p, in=%p, out=%p, roce_info=?\n",
2070 rdma_cxt, in_params, out_params);
2071 return NULL;
2072 }
2073
2074 DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
2075 "qed rdma create qp called with qp_handle = %08x%08x\n",
2076 in_params->qp_handle_hi, in_params->qp_handle_lo);
2077
2078 /* Some sanity checks... */
2079 max_stats_queues = p_hwfn->p_rdma_info->dev->max_stats_queues;
2080 if (in_params->stats_queue >= max_stats_queues) {
2081 DP_ERR(p_hwfn->cdev,
2082 "qed rdma create qp failed due to invalid statistics queue %d. maximum is %d\n",
2083 in_params->stats_queue, max_stats_queues);
2084 return NULL;
2085 }
2086
2087 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2088 if (!qp) {
2089 DP_NOTICE(p_hwfn, "Failed to allocate qed_rdma_qp\n");
2090 return NULL;
2091 }
2092
2093 rc = qed_roce_alloc_cid(p_hwfn, &qp->icid);
2094 qp->qpid = ((0xFF << 16) | qp->icid);
2095
2096 DP_INFO(p_hwfn, "ROCE qpid=%x\n", qp->qpid);
2097
2098 if (rc) {
2099 kfree(qp);
2100 return NULL;
2101 }
2102
2103 qp->cur_state = QED_ROCE_QP_STATE_RESET;
2104 qp->qp_handle.hi = cpu_to_le32(in_params->qp_handle_hi);
2105 qp->qp_handle.lo = cpu_to_le32(in_params->qp_handle_lo);
2106 qp->qp_handle_async.hi = cpu_to_le32(in_params->qp_handle_async_hi);
2107 qp->qp_handle_async.lo = cpu_to_le32(in_params->qp_handle_async_lo);
2108 qp->use_srq = in_params->use_srq;
2109 qp->signal_all = in_params->signal_all;
2110 qp->fmr_and_reserved_lkey = in_params->fmr_and_reserved_lkey;
2111 qp->pd = in_params->pd;
2112 qp->dpi = in_params->dpi;
2113 qp->sq_cq_id = in_params->sq_cq_id;
2114 qp->sq_num_pages = in_params->sq_num_pages;
2115 qp->sq_pbl_ptr = in_params->sq_pbl_ptr;
2116 qp->rq_cq_id = in_params->rq_cq_id;
2117 qp->rq_num_pages = in_params->rq_num_pages;
2118 qp->rq_pbl_ptr = in_params->rq_pbl_ptr;
2119 qp->srq_id = in_params->srq_id;
2120 qp->req_offloaded = false;
2121 qp->resp_offloaded = false;
2122 qp->e2e_flow_control_en = qp->use_srq ? false : true;
2123 qp->stats_queue = in_params->stats_queue;
2124
2125 out_params->icid = qp->icid;
2126 out_params->qp_id = qp->qpid;
2127
2128 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Create QP, rc = %d\n", rc);
2129 return qp;
2130}
2131
2132static int qed_roce_modify_qp(struct qed_hwfn *p_hwfn,
2133 struct qed_rdma_qp *qp,
2134 enum qed_roce_qp_state prev_state,
2135 struct qed_rdma_modify_qp_in_params *params)
2136{
2137 u32 num_invalidated_mw = 0, num_bound_mw = 0;
2138 int rc = 0;
2139
2140 /* Perform additional operations according to the current state and the
2141 * next state
2142 */
2143 if (((prev_state == QED_ROCE_QP_STATE_INIT) ||
2144 (prev_state == QED_ROCE_QP_STATE_RESET)) &&
2145 (qp->cur_state == QED_ROCE_QP_STATE_RTR)) {
2146 /* Init->RTR or Reset->RTR */
2147 rc = qed_roce_sp_create_responder(p_hwfn, qp);
2148 return rc;
2149 } else if ((prev_state == QED_ROCE_QP_STATE_RTR) &&
2150 (qp->cur_state == QED_ROCE_QP_STATE_RTS)) {
2151 /* RTR-> RTS */
2152 rc = qed_roce_sp_create_requester(p_hwfn, qp);
2153 if (rc)
2154 return rc;
2155
2156 /* Send modify responder ramrod */
2157 rc = qed_roce_sp_modify_responder(p_hwfn, qp, false,
2158 params->modify_flags);
2159 return rc;
2160 } else if ((prev_state == QED_ROCE_QP_STATE_RTS) &&
2161 (qp->cur_state == QED_ROCE_QP_STATE_RTS)) {
2162 /* RTS->RTS */
2163 rc = qed_roce_sp_modify_responder(p_hwfn, qp, false,
2164 params->modify_flags);
2165 if (rc)
2166 return rc;
2167
2168 rc = qed_roce_sp_modify_requester(p_hwfn, qp, false, false,
2169 params->modify_flags);
2170 return rc;
2171 } else if ((prev_state == QED_ROCE_QP_STATE_RTS) &&
2172 (qp->cur_state == QED_ROCE_QP_STATE_SQD)) {
2173 /* RTS->SQD */
2174 rc = qed_roce_sp_modify_requester(p_hwfn, qp, true, false,
2175 params->modify_flags);
2176 return rc;
2177 } else if ((prev_state == QED_ROCE_QP_STATE_SQD) &&
2178 (qp->cur_state == QED_ROCE_QP_STATE_SQD)) {
2179 /* SQD->SQD */
2180 rc = qed_roce_sp_modify_responder(p_hwfn, qp, false,
2181 params->modify_flags);
2182 if (rc)
2183 return rc;
2184
2185 rc = qed_roce_sp_modify_requester(p_hwfn, qp, false, false,
2186 params->modify_flags);
2187 return rc;
2188 } else if ((prev_state == QED_ROCE_QP_STATE_SQD) &&
2189 (qp->cur_state == QED_ROCE_QP_STATE_RTS)) {
2190 /* SQD->RTS */
2191 rc = qed_roce_sp_modify_responder(p_hwfn, qp, false,
2192 params->modify_flags);
2193 if (rc)
2194 return rc;
2195
2196 rc = qed_roce_sp_modify_requester(p_hwfn, qp, false, false,
2197 params->modify_flags);
2198
2199 return rc;
2200 } else if (qp->cur_state == QED_ROCE_QP_STATE_ERR ||
2201 qp->cur_state == QED_ROCE_QP_STATE_SQE) {
2202 /* ->ERR */
2203 rc = qed_roce_sp_modify_responder(p_hwfn, qp, true,
2204 params->modify_flags);
2205 if (rc)
2206 return rc;
2207
2208 rc = qed_roce_sp_modify_requester(p_hwfn, qp, false, true,
2209 params->modify_flags);
2210 return rc;
2211 } else if (qp->cur_state == QED_ROCE_QP_STATE_RESET) {
2212 /* Any state -> RESET */
be086e7c
MY		 2213 u32 cq_prod;
2214
2215 /* Send destroy responder ramrod */
2216 rc = qed_roce_sp_destroy_qp_responder(p_hwfn,
2217 qp,
2218 &num_invalidated_mw,
2219 &cq_prod);
f1093940 2220
f1093940
RA		 2221 if (rc)
2222 return rc;
2223
be086e7c
MY		 2224 qp->cq_prod = cq_prod;
2225
f1093940
RA		 2226 rc = qed_roce_sp_destroy_qp_requester(p_hwfn, qp,
2227 &num_bound_mw);
2228
2229 if (num_invalidated_mw != num_bound_mw) {
2230 DP_NOTICE(p_hwfn,
2231 "number of invalidate memory windows is different from bounded ones\n");
2232 return -EINVAL;
2233 }
2234 } else {
2235 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "0\n");
2236 }
2237
2238 return rc;
2239}
2240
0189efb8
YM		 2241static int qed_rdma_modify_qp(void *rdma_cxt,
2242 struct qed_rdma_qp *qp,
2243 struct qed_rdma_modify_qp_in_params *params)
f1093940
RA		 2244{
2245 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
2246 enum qed_roce_qp_state prev_state;
2247 int rc = 0;
2248
2249 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x params->new_state=%d\n",
2250 qp->icid, params->new_state);
2251
2252 if (rc) {
2253 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "rc = %d\n", rc);
2254 return rc;
2255 }
2256
2257 if (GET_FIELD(params->modify_flags,
2258 QED_RDMA_MODIFY_QP_VALID_RDMA_OPS_EN)) {
2259 qp->incoming_rdma_read_en = params->incoming_rdma_read_en;
2260 qp->incoming_rdma_write_en = params->incoming_rdma_write_en;
2261 qp->incoming_atomic_en = params->incoming_atomic_en;
2262 }
2263
2264 /* Update QP structure with the updated values */
2265 if (GET_FIELD(params->modify_flags, QED_ROCE_MODIFY_QP_VALID_ROCE_MODE))
2266 qp->roce_mode = params->roce_mode;
2267 if (GET_FIELD(params->modify_flags, QED_ROCE_MODIFY_QP_VALID_PKEY))
2268 qp->pkey = params->pkey;
2269 if (GET_FIELD(params->modify_flags,
2270 QED_ROCE_MODIFY_QP_VALID_E2E_FLOW_CONTROL_EN))
2271 qp->e2e_flow_control_en = params->e2e_flow_control_en;
2272 if (GET_FIELD(params->modify_flags, QED_ROCE_MODIFY_QP_VALID_DEST_QP))
2273 qp->dest_qp = params->dest_qp;
2274 if (GET_FIELD(params->modify_flags,
2275 QED_ROCE_MODIFY_QP_VALID_ADDRESS_VECTOR)) {
2276 /* Indicates that the following parameters have changed:
2277 * Traffic class, flow label, hop limit, source GID,
2278 * destination GID, loopback indicator
2279 */
2280 qp->traffic_class_tos = params->traffic_class_tos;
2281 qp->flow_label = params->flow_label;
2282 qp->hop_limit_ttl = params->hop_limit_ttl;
2283
2284 qp->sgid = params->sgid;
2285 qp->dgid = params->dgid;
2286 qp->udp_src_port = 0;
2287 qp->vlan_id = params->vlan_id;
2288 qp->mtu = params->mtu;
2289 qp->lb_indication = params->lb_indication;
2290 memcpy((u8 *)&qp->remote_mac_addr[0],
2291 (u8 *)&params->remote_mac_addr[0], ETH_ALEN);
2292 if (params->use_local_mac) {
2293 memcpy((u8 *)&qp->local_mac_addr[0],
2294 (u8 *)&params->local_mac_addr[0], ETH_ALEN);
2295 } else {
2296 memcpy((u8 *)&qp->local_mac_addr[0],
2297 (u8 *)&p_hwfn->hw_info.hw_mac_addr, ETH_ALEN);
2298 }
2299 }
2300 if (GET_FIELD(params->modify_flags, QED_ROCE_MODIFY_QP_VALID_RQ_PSN))
2301 qp->rq_psn = params->rq_psn;
2302 if (GET_FIELD(params->modify_flags, QED_ROCE_MODIFY_QP_VALID_SQ_PSN))
2303 qp->sq_psn = params->sq_psn;
2304 if (GET_FIELD(params->modify_flags,
2305 QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_REQ))
2306 qp->max_rd_atomic_req = params->max_rd_atomic_req;
2307 if (GET_FIELD(params->modify_flags,
2308 QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_RESP))
2309 qp->max_rd_atomic_resp = params->max_rd_atomic_resp;
2310 if (GET_FIELD(params->modify_flags,
2311 QED_ROCE_MODIFY_QP_VALID_ACK_TIMEOUT))
2312 qp->ack_timeout = params->ack_timeout;
2313 if (GET_FIELD(params->modify_flags, QED_ROCE_MODIFY_QP_VALID_RETRY_CNT))
2314 qp->retry_cnt = params->retry_cnt;
2315 if (GET_FIELD(params->modify_flags,
2316 QED_ROCE_MODIFY_QP_VALID_RNR_RETRY_CNT))
2317 qp->rnr_retry_cnt = params->rnr_retry_cnt;
2318 if (GET_FIELD(params->modify_flags,
2319 QED_ROCE_MODIFY_QP_VALID_MIN_RNR_NAK_TIMER))
2320 qp->min_rnr_nak_timer = params->min_rnr_nak_timer;
2321
2322 qp->sqd_async = params->sqd_async;
2323
2324 prev_state = qp->cur_state;
2325 if (GET_FIELD(params->modify_flags,
2326 QED_RDMA_MODIFY_QP_VALID_NEW_STATE)) {
2327 qp->cur_state = params->new_state;
2328 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "qp->cur_state=%d\n",
2329 qp->cur_state);
2330 }
2331
2332 rc = qed_roce_modify_qp(p_hwfn, qp, prev_state, params);
2333
2334 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Modify QP, rc = %d\n", rc);
2335 return rc;
2336}
2337
0189efb8
YM		 2338static int
2339qed_rdma_register_tid(void *rdma_cxt,
2340 struct qed_rdma_register_tid_in_params *params)
ee8eaea3
RA		 2341{
2342 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
2343 struct rdma_register_tid_ramrod_data *p_ramrod;
2344 struct qed_sp_init_data init_data;
2345 struct qed_spq_entry *p_ent;
2346 enum rdma_tid_type tid_type;
2347 u8 fw_return_code;
2348 int rc;
2349
2350 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "itid = %08x\n", params->itid);
2351
2352 /* Get SPQ entry */
2353 memset(&init_data, 0, sizeof(init_data));
2354 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
2355 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
2356
2357 rc = qed_sp_init_request(p_hwfn, &p_ent, RDMA_RAMROD_REGISTER_MR,
2358 p_hwfn->p_rdma_info->proto, &init_data);
2359 if (rc) {
2360 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "rc = %d\n", rc);
2361 return rc;
2362 }
2363
2364 if (p_hwfn->p_rdma_info->last_tid < params->itid)
2365 p_hwfn->p_rdma_info->last_tid = params->itid;
2366
2367 p_ramrod = &p_ent->ramrod.rdma_register_tid;
2368
2369 p_ramrod->flags = 0;
2370 SET_FIELD(p_ramrod->flags,
2371 RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL,
2372 params->pbl_two_level);
2373
2374 SET_FIELD(p_ramrod->flags,
2375 RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED, params->zbva);
2376
2377 SET_FIELD(p_ramrod->flags,
2378 RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR, params->phy_mr);
2379
2380 /* Don't initialize D/C field, as it may override other bits. */
2381 if (!(params->tid_type == QED_RDMA_TID_FMR) && !(params->dma_mr))
2382 SET_FIELD(p_ramrod->flags,
2383 RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG,
2384 params->page_size_log - 12);
2385
2386 SET_FIELD(p_ramrod->flags,
2387 RDMA_REGISTER_TID_RAMROD_DATA_MAX_ID,
2388 p_hwfn->p_rdma_info->last_tid);
2389
2390 SET_FIELD(p_ramrod->flags,
2391 RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ,
2392 params->remote_read);
2393
2394 SET_FIELD(p_ramrod->flags,
2395 RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE,
2396 params->remote_write);
2397
2398 SET_FIELD(p_ramrod->flags,
2399 RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC,
2400 params->remote_atomic);
2401
2402 SET_FIELD(p_ramrod->flags,
2403 RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE,
2404 params->local_write);
2405
2406 SET_FIELD(p_ramrod->flags,
2407 RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ, params->local_read);
2408
2409 SET_FIELD(p_ramrod->flags,
2410 RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND,
2411 params->mw_bind);
2412
2413 SET_FIELD(p_ramrod->flags1,
2414 RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG,
2415 params->pbl_page_size_log - 12);
2416
2417 SET_FIELD(p_ramrod->flags2,
2418 RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR, params->dma_mr);
2419
2420 switch (params->tid_type) {
2421 case QED_RDMA_TID_REGISTERED_MR:
2422 tid_type = RDMA_TID_REGISTERED_MR;
2423 break;
2424 case QED_RDMA_TID_FMR:
2425 tid_type = RDMA_TID_FMR;
2426 break;
2427 case QED_RDMA_TID_MW_TYPE1:
2428 tid_type = RDMA_TID_MW_TYPE1;
2429 break;
2430 case QED_RDMA_TID_MW_TYPE2A:
2431 tid_type = RDMA_TID_MW_TYPE2A;
2432 break;
2433 default:
2434 rc = -EINVAL;
2435 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "rc = %d\n", rc);
2436 return rc;
2437 }
2438 SET_FIELD(p_ramrod->flags1,
2439 RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE, tid_type);
2440
2441 p_ramrod->itid = cpu_to_le32(params->itid);
2442 p_ramrod->key = params->key;
2443 p_ramrod->pd = cpu_to_le16(params->pd);
2444 p_ramrod->length_hi = (u8)(params->length >> 32);
2445 p_ramrod->length_lo = DMA_LO_LE(params->length);
2446 if (params->zbva) {
2447 /* Lower 32 bits of the registered MR address.
2448 * In case of zero based MR, will hold FBO
2449 */
2450 p_ramrod->va.hi = 0;
2451 p_ramrod->va.lo = cpu_to_le32(params->fbo);
2452 } else {
2453 DMA_REGPAIR_LE(p_ramrod->va, params->vaddr);
2454 }
2455 DMA_REGPAIR_LE(p_ramrod->pbl_base, params->pbl_ptr);
2456
2457 /* DIF */
2458 if (params->dif_enabled) {
2459 SET_FIELD(p_ramrod->flags2,
2460 RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG, 1);
2461 DMA_REGPAIR_LE(p_ramrod->dif_error_addr,
2462 params->dif_error_addr);
2463 DMA_REGPAIR_LE(p_ramrod->dif_runt_addr, params->dif_runt_addr);
2464 }
2465
2466 rc = qed_spq_post(p_hwfn, p_ent, &fw_return_code);
2467
2468 if (fw_return_code != RDMA_RETURN_OK) {
2469 DP_NOTICE(p_hwfn, "fw_return_code = %d\n", fw_return_code);
2470 return -EINVAL;
2471 }
2472
2473 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Register TID, rc = %d\n", rc);
2474 return rc;
2475}
2476
0189efb8 2477static int qed_rdma_deregister_tid(void *rdma_cxt, u32 itid)
ee8eaea3
RA		 2478{
2479 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
2480 struct rdma_deregister_tid_ramrod_data *p_ramrod;
2481 struct qed_sp_init_data init_data;
2482 struct qed_spq_entry *p_ent;
2483 struct qed_ptt *p_ptt;
2484 u8 fw_return_code;
2485 int rc;
2486
2487 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "itid = %08x\n", itid);
2488
2489 /* Get SPQ entry */
2490 memset(&init_data, 0, sizeof(init_data));
2491 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
2492 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
2493
2494 rc = qed_sp_init_request(p_hwfn, &p_ent, RDMA_RAMROD_DEREGISTER_MR,
2495 p_hwfn->p_rdma_info->proto, &init_data);
2496 if (rc) {
2497 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "rc = %d\n", rc);
2498 return rc;
2499 }
2500
2501 p_ramrod = &p_ent->ramrod.rdma_deregister_tid;
2502 p_ramrod->itid = cpu_to_le32(itid);
2503
2504 rc = qed_spq_post(p_hwfn, p_ent, &fw_return_code);
2505 if (rc) {
2506 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "rc = %d\n", rc);
2507 return rc;
2508 }
2509
2510 if (fw_return_code == RDMA_RETURN_DEREGISTER_MR_BAD_STATE_ERR) {
2511 DP_NOTICE(p_hwfn, "fw_return_code = %d\n", fw_return_code);
2512 return -EINVAL;
2513 } else if (fw_return_code == RDMA_RETURN_NIG_DRAIN_REQ) {
2514 /* Bit indicating that the TID is in use and a nig drain is
2515 * required before sending the ramrod again
2516 */
2517 p_ptt = qed_ptt_acquire(p_hwfn);
2518 if (!p_ptt) {
2519 rc = -EBUSY;
2520 DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
2521 "Failed to acquire PTT\n");
2522 return rc;
2523 }
2524
2525 rc = qed_mcp_drain(p_hwfn, p_ptt);
2526 if (rc) {
2527 qed_ptt_release(p_hwfn, p_ptt);
2528 DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
2529 "Drain failed\n");
2530 return rc;
2531 }
2532
2533 qed_ptt_release(p_hwfn, p_ptt);
2534
2535 /* Resend the ramrod */
2536 rc = qed_sp_init_request(p_hwfn, &p_ent,
2537 RDMA_RAMROD_DEREGISTER_MR,
2538 p_hwfn->p_rdma_info->proto,
2539 &init_data);
2540 if (rc) {
2541 DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
2542 "Failed to init sp-element\n");
2543 return rc;
2544 }
2545
2546 rc = qed_spq_post(p_hwfn, p_ent, &fw_return_code);
2547 if (rc) {
2548 DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
2549 "Ramrod failed\n");
2550 return rc;
2551 }
2552
2553 if (fw_return_code != RDMA_RETURN_OK) {
2554 DP_NOTICE(p_hwfn, "fw_return_code = %d\n",
2555 fw_return_code);
2556 return rc;
2557 }
2558 }
2559
2560 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "De-registered TID, rc = %d\n", rc);
2561 return rc;
2562}
2563
be086e7c
MY		 2564static void qed_roce_free_real_icid(struct qed_hwfn *p_hwfn, u16 icid)
2565{
2566 struct qed_rdma_info *p_rdma_info = p_hwfn->p_rdma_info;
2567 u32 start_cid, cid, xcid;
2568
2569 /* an even icid belongs to a responder while an odd icid belongs to a
2570 * requester. The 'cid' received as an input can be either. We calculate
2571 * the "partner" icid and call it xcid. Only if both are free then the
2572 * "cid" map can be cleared.
2573 */
2574 start_cid = qed_cxt_get_proto_cid_start(p_hwfn, p_rdma_info->proto);
2575 cid = icid - start_cid;
2576 xcid = cid ^ 1;
2577
2578 spin_lock_bh(&p_rdma_info->lock);
2579
2580 qed_bmap_release_id(p_hwfn, &p_rdma_info->real_cid_map, cid);
2581 if (qed_bmap_test_id(p_hwfn, &p_rdma_info->real_cid_map, xcid) == 0) {
2582 qed_bmap_release_id(p_hwfn, &p_rdma_info->cid_map, cid);
2583 qed_bmap_release_id(p_hwfn, &p_rdma_info->cid_map, xcid);
2584 }
2585
2586 spin_unlock_bh(&p_hwfn->p_rdma_info->lock);
2587}
2588
51ff1725
RA		 2589static void *qed_rdma_get_rdma_ctx(struct qed_dev *cdev)
2590{
2591 return QED_LEADING_HWFN(cdev);
2592}
2593
2594static void qed_rdma_dpm_conf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2595{
2596 u32 val;
2597
2598 val = (p_hwfn->dcbx_no_edpm || p_hwfn->db_bar_no_edpm) ? 0 : 1;
2599
2600 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPM_ENABLE, val);
2601 DP_VERBOSE(p_hwfn, (QED_MSG_DCB | QED_MSG_RDMA),
2602 "Changing DPM_EN state to %d (DCBX=%d, DB_BAR=%d)\n",
2603 val, p_hwfn->dcbx_no_edpm, p_hwfn->db_bar_no_edpm);
2604}
2605
2606void qed_rdma_dpm_bar(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2607{
2608 p_hwfn->db_bar_no_edpm = true;
2609
2610 qed_rdma_dpm_conf(p_hwfn, p_ptt);
2611}
2612
0189efb8
YM		 2613static int qed_rdma_start(void *rdma_cxt,
2614 struct qed_rdma_start_in_params *params)
51ff1725
RA		 2615{
2616 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
2617 struct qed_ptt *p_ptt;
2618 int rc = -EBUSY;
2619
2620 DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
2621 "desired_cnq = %08x\n", params->desired_cnq);
2622
2623 p_ptt = qed_ptt_acquire(p_hwfn);
2624 if (!p_ptt)
2625 goto err;
2626
2627 rc = qed_rdma_alloc(p_hwfn, p_ptt, params);
2628 if (rc)
2629 goto err1;
2630
2631 rc = qed_rdma_setup(p_hwfn, p_ptt, params);
2632 if (rc)
2633 goto err2;
2634
2635 qed_ptt_release(p_hwfn, p_ptt);
2636
2637 return rc;
2638
2639err2:
2640 qed_rdma_free(p_hwfn);
2641err1:
2642 qed_ptt_release(p_hwfn, p_ptt);
2643err:
2644 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "RDMA start - error, rc = %d\n", rc);
2645 return rc;
2646}
2647
2648static int qed_rdma_init(struct qed_dev *cdev,
2649 struct qed_rdma_start_in_params *params)
2650{
2651 return qed_rdma_start(QED_LEADING_HWFN(cdev), params);
2652}
2653
0189efb8 2654static void qed_rdma_remove_user(void *rdma_cxt, u16 dpi)
51ff1725
RA		 2655{
2656 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
2657
2658 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "dpi = %08x\n", dpi);
2659
2660 spin_lock_bh(&p_hwfn->p_rdma_info->lock);
2661 qed_bmap_release_id(p_hwfn, &p_hwfn->p_rdma_info->dpi_map, dpi);
2662 spin_unlock_bh(&p_hwfn->p_rdma_info->lock);
2663}
2664
abd49676
RA		 2665void qed_ll2b_complete_tx_gsi_packet(struct qed_hwfn *p_hwfn,
2666 u8 connection_handle,
2667 void *cookie,
2668 dma_addr_t first_frag_addr,
2669 bool b_last_fragment, bool b_last_packet)
2670{
2671 struct qed_roce_ll2_packet *packet = cookie;
2672 struct qed_roce_ll2_info *roce_ll2 = p_hwfn->ll2;
2673
2674 roce_ll2->cbs.tx_cb(roce_ll2->cb_cookie, packet);
2675}
2676
2677void qed_ll2b_release_tx_gsi_packet(struct qed_hwfn *p_hwfn,
2678 u8 connection_handle,
2679 void *cookie,
2680 dma_addr_t first_frag_addr,
2681 bool b_last_fragment, bool b_last_packet)
2682{
2683 qed_ll2b_complete_tx_gsi_packet(p_hwfn, connection_handle,
2684 cookie, first_frag_addr,
2685 b_last_fragment, b_last_packet);
2686}
2687
2688void qed_ll2b_complete_rx_gsi_packet(struct qed_hwfn *p_hwfn,
2689 u8 connection_handle,
2690 void *cookie,
2691 dma_addr_t rx_buf_addr,
2692 u16 data_length,
2693 u8 data_length_error,
2694 u16 parse_flags,
2695 u16 vlan,
2696 u32 src_mac_addr_hi,
2697 u16 src_mac_addr_lo, bool b_last_packet)
2698{
2699 struct qed_roce_ll2_info *roce_ll2 = p_hwfn->ll2;
2700 struct qed_roce_ll2_rx_params params;
2701 struct qed_dev *cdev = p_hwfn->cdev;
2702 struct qed_roce_ll2_packet pkt;
2703
2704 DP_VERBOSE(cdev,
2705 QED_MSG_LL2,
2706 "roce ll2 rx complete: bus_addr=%p, len=%d, data_len_err=%d\n",
2707 (void *)(uintptr_t)rx_buf_addr,
2708 data_length, data_length_error);
2709
2710 memset(&pkt, 0, sizeof(pkt));
2711 pkt.n_seg = 1;
2712 pkt.payload[0].baddr = rx_buf_addr;
2713 pkt.payload[0].len = data_length;
2714
2715 memset(&params, 0, sizeof(params));
2716 params.vlan_id = vlan;
2717 *((u32 *)&params.smac[0]) = ntohl(src_mac_addr_hi);
2718 *((u16 *)&params.smac[4]) = ntohs(src_mac_addr_lo);
2719
2720 if (data_length_error) {
2721 DP_ERR(cdev,
2722 "roce ll2 rx complete: data length error %d, length=%d\n",
2723 data_length_error, data_length);
2724 params.rc = -EINVAL;
2725 }
2726
2727 roce_ll2->cbs.rx_cb(roce_ll2->cb_cookie, &pkt, &params);
2728}
2729
2730static int qed_roce_ll2_set_mac_filter(struct qed_dev *cdev,
2731 u8 *old_mac_address,
2732 u8 *new_mac_address)
2733{
2734 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
2735 struct qed_ptt *p_ptt;
2736 int rc = 0;
2737
2738 if (!hwfn->ll2 || hwfn->ll2->handle == QED_LL2_UNUSED_HANDLE) {
2739 DP_ERR(cdev,
2740 "qed roce mac filter failed - roce_info/ll2 NULL\n");
2741 return -EINVAL;
2742 }
2743
2744 p_ptt = qed_ptt_acquire(QED_LEADING_HWFN(cdev));
2745 if (!p_ptt) {
2746 DP_ERR(cdev,
2747 "qed roce ll2 mac filter set: failed to acquire PTT\n");
2748 return -EINVAL;
2749 }
2750
2751 mutex_lock(&hwfn->ll2->lock);
2752 if (old_mac_address)
2753 qed_llh_remove_mac_filter(QED_LEADING_HWFN(cdev), p_ptt,
2754 old_mac_address);
2755 if (new_mac_address)
2756 rc = qed_llh_add_mac_filter(QED_LEADING_HWFN(cdev), p_ptt,
2757 new_mac_address);
2758 mutex_unlock(&hwfn->ll2->lock);
2759
2760 qed_ptt_release(QED_LEADING_HWFN(cdev), p_ptt);
2761
2762 if (rc)
2763 DP_ERR(cdev,
2764 "qed roce ll2 mac filter set: failed to add mac filter\n");
2765
2766 return rc;
2767}
2768
2769static int qed_roce_ll2_start(struct qed_dev *cdev,
2770 struct qed_roce_ll2_params *params)
2771{
2772 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
2773 struct qed_roce_ll2_info *roce_ll2;
0629a330 2774 struct qed_ll2_conn ll2_params;
abd49676
RA		 2775 int rc;
2776
2777 if (!params) {
2778 DP_ERR(cdev, "qed roce ll2 start: failed due to NULL params\n");
2779 return -EINVAL;
2780 }
2781 if (!params->cbs.tx_cb || !params->cbs.rx_cb) {
2782 DP_ERR(cdev,
2783 "qed roce ll2 start: failed due to NULL tx/rx. tx_cb=%p, rx_cb=%p\n",
2784 params->cbs.tx_cb, params->cbs.rx_cb);
2785 return -EINVAL;
2786 }
2787 if (!is_valid_ether_addr(params->mac_address)) {
2788 DP_ERR(cdev,
2789 "qed roce ll2 start: failed due to invalid Ethernet address %pM\n",
2790 params->mac_address);
2791 return -EINVAL;
2792 }
2793
2794 /* Initialize */
2795 roce_ll2 = kzalloc(sizeof(*roce_ll2), GFP_ATOMIC);
2796 if (!roce_ll2) {
2797 DP_ERR(cdev, "qed roce ll2 start: failed memory allocation\n");
2798 return -ENOMEM;
2799 }
abd49676
RA		 2800 roce_ll2->handle = QED_LL2_UNUSED_HANDLE;
2801 roce_ll2->cbs = params->cbs;
2802 roce_ll2->cb_cookie = params->cb_cookie;
2803 mutex_init(&roce_ll2->lock);
2804
2805 memset(&ll2_params, 0, sizeof(ll2_params));
2806 ll2_params.conn_type = QED_LL2_TYPE_ROCE;
2807 ll2_params.mtu = params->mtu;
2808 ll2_params.rx_drop_ttl0_flg = true;
2809 ll2_params.rx_vlan_removal_en = false;
2810 ll2_params.tx_dest = CORE_TX_DEST_NW;
2811 ll2_params.ai_err_packet_too_big = LL2_DROP_PACKET;
2812 ll2_params.ai_err_no_buf = LL2_DROP_PACKET;
2813 ll2_params.gsi_enable = true;
2814
2815 rc = qed_ll2_acquire_connection(QED_LEADING_HWFN(cdev), &ll2_params,
2816 params->max_rx_buffers,
2817 params->max_tx_buffers,
2818 &roce_ll2->handle);
2819 if (rc) {
2820 DP_ERR(cdev,
2821 "qed roce ll2 start: failed to acquire LL2 connection (rc=%d)\n",
2822 rc);
2823 goto err;
2824 }
2825
2826 rc = qed_ll2_establish_connection(QED_LEADING_HWFN(cdev),
2827 roce_ll2->handle);
2828 if (rc) {
2829 DP_ERR(cdev,
2830 "qed roce ll2 start: failed to establish LL2 connection (rc=%d)\n",
2831 rc);
2832 goto err1;
2833 }
2834
2835 hwfn->ll2 = roce_ll2;
2836
2837 rc = qed_roce_ll2_set_mac_filter(cdev, NULL, params->mac_address);
2838 if (rc) {
2839 hwfn->ll2 = NULL;
2840 goto err2;
2841 }
2842 ether_addr_copy(roce_ll2->mac_address, params->mac_address);
2843
2844 return 0;
2845
2846err2:
2847 qed_ll2_terminate_connection(QED_LEADING_HWFN(cdev), roce_ll2->handle);
2848err1:
2849 qed_ll2_release_connection(QED_LEADING_HWFN(cdev), roce_ll2->handle);
2850err:
2851 kfree(roce_ll2);
2852 return rc;
2853}
2854
2855static int qed_roce_ll2_stop(struct qed_dev *cdev)
2856{
2857 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
2858 struct qed_roce_ll2_info *roce_ll2 = hwfn->ll2;
2859 int rc;
2860
abd49676
RA		 2861 if (roce_ll2->handle == QED_LL2_UNUSED_HANDLE) {
2862 DP_ERR(cdev, "qed roce ll2 stop: cannot stop an unused LL2\n");
2863 return -EINVAL;
2864 }
2865
2866 /* remove LL2 MAC address filter */
2867 rc = qed_roce_ll2_set_mac_filter(cdev, roce_ll2->mac_address, NULL);
2868 eth_zero_addr(roce_ll2->mac_address);
2869
2870 rc = qed_ll2_terminate_connection(QED_LEADING_HWFN(cdev),
2871 roce_ll2->handle);
2872 if (rc)
2873 DP_ERR(cdev,
2874 "qed roce ll2 stop: failed to terminate LL2 connection (rc=%d)\n",
2875 rc);
2876
2877 qed_ll2_release_connection(QED_LEADING_HWFN(cdev), roce_ll2->handle);
2878
2879 roce_ll2->handle = QED_LL2_UNUSED_HANDLE;
2880
2881 kfree(roce_ll2);
2882
2883 return rc;
2884}
2885
2886static int qed_roce_ll2_tx(struct qed_dev *cdev,
2887 struct qed_roce_ll2_packet *pkt,
2888 struct qed_roce_ll2_tx_params *params)
2889{
2890 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
2891 struct qed_roce_ll2_info *roce_ll2 = hwfn->ll2;
2892 enum qed_ll2_roce_flavor_type qed_roce_flavor;
2893 u8 flags = 0;
2894 int rc;
2895 int i;
2896
ce6b04ee 2897 if (!pkt || !params) {
abd49676
RA		 2898 DP_ERR(cdev,
2899 "roce ll2 tx: failed tx because one of the following is NULL - drv=%p, pkt=%p, params=%p\n",
2900 cdev, pkt, params);
2901 return -EINVAL;
2902 }
2903
2904 qed_roce_flavor = (pkt->roce_mode == ROCE_V1) ? QED_LL2_ROCE
2905 : QED_LL2_RROCE;
2906
2907 if (pkt->roce_mode == ROCE_V2_IPV4)
be086e7c 2908 flags |= BIT(CORE_TX_BD_DATA_IP_CSUM_SHIFT);
abd49676
RA		 2909
2910 /* Tx header */
2911 rc = qed_ll2_prepare_tx_packet(QED_LEADING_HWFN(cdev), roce_ll2->handle,
2912 1 + pkt->n_seg, 0, flags, 0,
1d6cff4f 2913 QED_LL2_TX_DEST_NW,
abd49676
RA		 2914 qed_roce_flavor, pkt->header.baddr,
2915 pkt->header.len, pkt, 1);
2916 if (rc) {
2917 DP_ERR(cdev, "roce ll2 tx: header failed (rc=%d)\n", rc);
2918 return QED_ROCE_TX_HEAD_FAILURE;
2919 }
2920
2921 /* Tx payload */
2922 for (i = 0; i < pkt->n_seg; i++) {
2923 rc = qed_ll2_set_fragment_of_tx_packet(QED_LEADING_HWFN(cdev),
2924 roce_ll2->handle,
2925 pkt->payload[i].baddr,
2926 pkt->payload[i].len);
2927 if (rc) {
2928 /* If failed not much to do here, partial packet has
2929 * been posted * we can't free memory, will need to wait
2930 * for completion
2931 */
2932 DP_ERR(cdev,
2933 "roce ll2 tx: payload failed (rc=%d)\n", rc);
2934 return QED_ROCE_TX_FRAG_FAILURE;
2935 }
2936 }
2937
2938 return 0;
2939}
2940
2941static int qed_roce_ll2_post_rx_buffer(struct qed_dev *cdev,
2942 struct qed_roce_ll2_buffer *buf,
2943 u64 cookie, u8 notify_fw)
2944{
2945 return qed_ll2_post_rx_buffer(QED_LEADING_HWFN(cdev),
2946 QED_LEADING_HWFN(cdev)->ll2->handle,
2947 buf->baddr, buf->len,
2948 (void *)(uintptr_t)cookie, notify_fw);
2949}
2950
2951static int qed_roce_ll2_stats(struct qed_dev *cdev, struct qed_ll2_stats *stats)
2952{
2953 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
2954 struct qed_roce_ll2_info *roce_ll2 = hwfn->ll2;
2955
2956 return qed_ll2_get_stats(QED_LEADING_HWFN(cdev),
2957 roce_ll2->handle, stats);
2958}
2959
51ff1725
RA		 2960static const struct qed_rdma_ops qed_rdma_ops_pass = {
2961 .common = &qed_common_ops_pass,
2962 .fill_dev_info = &qed_fill_rdma_dev_info,
2963 .rdma_get_rdma_ctx = &qed_rdma_get_rdma_ctx,
2964 .rdma_init = &qed_rdma_init,
2965 .rdma_add_user = &qed_rdma_add_user,
2966 .rdma_remove_user = &qed_rdma_remove_user,
2967 .rdma_stop = &qed_rdma_stop,
c295f86e 2968 .rdma_query_port = &qed_rdma_query_port,
51ff1725
RA		 2969 .rdma_query_device = &qed_rdma_query_device,
2970 .rdma_get_start_sb = &qed_rdma_get_sb_start,
2971 .rdma_get_rdma_int = &qed_rdma_get_int,
2972 .rdma_set_rdma_int = &qed_rdma_set_int,
2973 .rdma_get_min_cnq_msix = &qed_rdma_get_min_cnq_msix,
2974 .rdma_cnq_prod_update = &qed_rdma_cnq_prod_update,
c295f86e
RA		 2975 .rdma_alloc_pd = &qed_rdma_alloc_pd,
2976 .rdma_dealloc_pd = &qed_rdma_free_pd,
2977 .rdma_create_cq = &qed_rdma_create_cq,
2978 .rdma_destroy_cq = &qed_rdma_destroy_cq,
f1093940
RA		 2979 .rdma_create_qp = &qed_rdma_create_qp,
2980 .rdma_modify_qp = &qed_rdma_modify_qp,
2981 .rdma_query_qp = &qed_rdma_query_qp,
2982 .rdma_destroy_qp = &qed_rdma_destroy_qp,
ee8eaea3
RA		 2983 .rdma_alloc_tid = &qed_rdma_alloc_tid,
2984 .rdma_free_tid = &qed_rdma_free_tid,
2985 .rdma_register_tid = &qed_rdma_register_tid,
2986 .rdma_deregister_tid = &qed_rdma_deregister_tid,
abd49676
RA		 2987 .roce_ll2_start = &qed_roce_ll2_start,
2988 .roce_ll2_stop = &qed_roce_ll2_stop,
2989 .roce_ll2_tx = &qed_roce_ll2_tx,
2990 .roce_ll2_post_rx_buffer = &qed_roce_ll2_post_rx_buffer,
2991 .roce_ll2_set_mac_filter = &qed_roce_ll2_set_mac_filter,
2992 .roce_ll2_stats = &qed_roce_ll2_stats,
51ff1725
RA		 2993};
2994
d4e99131 2995const struct qed_rdma_ops *qed_get_rdma_ops(void)
51ff1725
RA		 2996{
2997 return &qed_rdma_ops_pass;
2998}
2999EXPORT_SYMBOL(qed_get_rdma_ops);
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