[mirror_ubuntu-hirsute-kernel.git] / drivers / net / ethernet / qlogic / qede / qede.h

/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
/* QLogic qede NIC Driver
 * Copyright (c) 2015-2017  QLogic Corporation
 * Copyright (c) 2019-2020 Marvell International Ltd.
 */

#ifndef _QEDE_H_
#define _QEDE_H_
#include <linux/compiler.h>
#include <linux/version.h>
#include <linux/workqueue.h>
#include <linux/netdevice.h>
#include <linux/interrupt.h>
#include <linux/bitmap.h>
#include <linux/kernel.h>
#include <linux/mutex.h>
#include <linux/bpf.h>
#include <net/xdp.h>
#include <linux/qed/qede_rdma.h>
#include <linux/io.h>
#ifdef CONFIG_RFS_ACCEL
#include <linux/cpu_rmap.h>
#endif
#include <linux/qed/common_hsi.h>
#include <linux/qed/eth_common.h>
#include <linux/qed/qed_if.h>
#include <linux/qed/qed_chain.h>
#include <linux/qed/qed_eth_if.h>

#include <net/pkt_cls.h>
#include <net/tc_act/tc_gact.h>

#define QEDE_MAJOR_VERSION		8
#define QEDE_MINOR_VERSION		37
#define QEDE_REVISION_VERSION		0
#define QEDE_ENGINEERING_VERSION	20
#define DRV_MODULE_VERSION __stringify(QEDE_MAJOR_VERSION) "."	\
		__stringify(QEDE_MINOR_VERSION) "."		\
		__stringify(QEDE_REVISION_VERSION) "."		\
		__stringify(QEDE_ENGINEERING_VERSION)

#define DRV_MODULE_SYM		qede

struct qede_stats_common {
	u64 no_buff_discards;
	u64 packet_too_big_discard;
	u64 ttl0_discard;
	u64 rx_ucast_bytes;
	u64 rx_mcast_bytes;
	u64 rx_bcast_bytes;
	u64 rx_ucast_pkts;
	u64 rx_mcast_pkts;
	u64 rx_bcast_pkts;
	u64 mftag_filter_discards;
	u64 mac_filter_discards;
	u64 gft_filter_drop;
	u64 tx_ucast_bytes;
	u64 tx_mcast_bytes;
	u64 tx_bcast_bytes;
	u64 tx_ucast_pkts;
	u64 tx_mcast_pkts;
	u64 tx_bcast_pkts;
	u64 tx_err_drop_pkts;
	u64 coalesced_pkts;
	u64 coalesced_events;
	u64 coalesced_aborts_num;
	u64 non_coalesced_pkts;
	u64 coalesced_bytes;
	u64 link_change_count;
	u64 ptp_skip_txts;

	/* port */
	u64 rx_64_byte_packets;
	u64 rx_65_to_127_byte_packets;
	u64 rx_128_to_255_byte_packets;
	u64 rx_256_to_511_byte_packets;
	u64 rx_512_to_1023_byte_packets;
	u64 rx_1024_to_1518_byte_packets;
	u64 rx_crc_errors;
	u64 rx_mac_crtl_frames;
	u64 rx_pause_frames;
	u64 rx_pfc_frames;
	u64 rx_align_errors;
	u64 rx_carrier_errors;
	u64 rx_oversize_packets;
	u64 rx_jabbers;
	u64 rx_undersize_packets;
	u64 rx_fragments;
	u64 tx_64_byte_packets;
	u64 tx_65_to_127_byte_packets;
	u64 tx_128_to_255_byte_packets;
	u64 tx_256_to_511_byte_packets;
	u64 tx_512_to_1023_byte_packets;
	u64 tx_1024_to_1518_byte_packets;
	u64 tx_pause_frames;
	u64 tx_pfc_frames;
	u64 brb_truncates;
	u64 brb_discards;
	u64 tx_mac_ctrl_frames;
};

struct qede_stats_bb {
	u64 rx_1519_to_1522_byte_packets;
	u64 rx_1519_to_2047_byte_packets;
	u64 rx_2048_to_4095_byte_packets;
	u64 rx_4096_to_9216_byte_packets;
	u64 rx_9217_to_16383_byte_packets;
	u64 tx_1519_to_2047_byte_packets;
	u64 tx_2048_to_4095_byte_packets;
	u64 tx_4096_to_9216_byte_packets;
	u64 tx_9217_to_16383_byte_packets;
	u64 tx_lpi_entry_count;
	u64 tx_total_collisions;
};

struct qede_stats_ah {
	u64 rx_1519_to_max_byte_packets;
	u64 tx_1519_to_max_byte_packets;
};

struct qede_stats {
	struct qede_stats_common common;

	union {
		struct qede_stats_bb bb;
		struct qede_stats_ah ah;
	};
};

struct qede_vlan {
	struct list_head list;
	u16 vid;
	bool configured;
};

struct qede_rdma_dev {
	struct qedr_dev *qedr_dev;
	struct list_head entry;
	struct list_head rdma_event_list;
	struct workqueue_struct *rdma_wq;
	struct kref refcnt;
	struct completion event_comp;
	bool exp_recovery;
};

struct qede_ptp;

#define QEDE_RFS_MAX_FLTR	256

enum qede_flags_bit {
	QEDE_FLAGS_IS_VF = 0,
	QEDE_FLAGS_LINK_REQUESTED,
	QEDE_FLAGS_PTP_TX_IN_PRORGESS,
	QEDE_FLAGS_TX_TIMESTAMPING_EN
};

#define QEDE_DUMP_MAX_ARGS 4
enum qede_dump_cmd {
	QEDE_DUMP_CMD_NONE = 0,
	QEDE_DUMP_CMD_NVM_CFG,
	QEDE_DUMP_CMD_GRCDUMP,
	QEDE_DUMP_CMD_MAX
};

struct qede_dump_info {
	enum qede_dump_cmd cmd;
	u8 num_args;
	u32 args[QEDE_DUMP_MAX_ARGS];
};

struct qede_dev {
	struct qed_dev			*cdev;
	struct net_device		*ndev;
	struct pci_dev			*pdev;
	struct devlink			*devlink;

	u32				dp_module;
	u8				dp_level;

	unsigned long			flags;
#define IS_VF(edev)			test_bit(QEDE_FLAGS_IS_VF, \
						 &(edev)->flags)

	const struct qed_eth_ops	*ops;
	struct qede_ptp			*ptp;
	u64				ptp_skip_txts;

	struct qed_dev_eth_info		dev_info;
#define QEDE_MAX_RSS_CNT(edev)		((edev)->dev_info.num_queues)
#define QEDE_MAX_TSS_CNT(edev)		((edev)->dev_info.num_queues)
#define QEDE_IS_BB(edev) \
	((edev)->dev_info.common.dev_type == QED_DEV_TYPE_BB)
#define QEDE_IS_AH(edev) \
	((edev)->dev_info.common.dev_type == QED_DEV_TYPE_AH)

	struct qede_fastpath		*fp_array;
	u8				req_num_tx;
	u8				fp_num_tx;
	u8				req_num_rx;
	u8				fp_num_rx;
	u16				req_queues;
	u16				num_queues;
	u16				total_xdp_queues;

#define QEDE_QUEUE_CNT(edev)		((edev)->num_queues)
#define QEDE_RSS_COUNT(edev)		((edev)->num_queues - (edev)->fp_num_tx)
#define QEDE_RX_QUEUE_IDX(edev, i)	(i)
#define QEDE_TSS_COUNT(edev)		((edev)->num_queues - (edev)->fp_num_rx)

	struct qed_int_info		int_info;

	/* Smaller private variant of the RTNL lock */
	struct mutex			qede_lock;
	u32				state; /* Protected by qede_lock */
	u16				rx_buf_size;
	u32				rx_copybreak;

	/* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
#define ETH_OVERHEAD			(ETH_HLEN + 8 + 8)
	/* Max supported alignment is 256 (8 shift)
	 * minimal alignment shift 6 is optimal for 57xxx HW performance
	 */
#define QEDE_RX_ALIGN_SHIFT		max(6, min(8, L1_CACHE_SHIFT))
	/* We assume skb_build() uses sizeof(struct skb_shared_info) bytes
	 * at the end of skb->data, to avoid wasting a full cache line.
	 * This reduces memory use (skb->truesize).
	 */
#define QEDE_FW_RX_ALIGN_END					\
	max_t(u64, 1UL << QEDE_RX_ALIGN_SHIFT,			\
	      SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))

	struct qede_stats		stats;

	/* Bitfield to track initialized RSS params */
	u32				rss_params_inited;
#define QEDE_RSS_INDIR_INITED		BIT(0)
#define QEDE_RSS_KEY_INITED		BIT(1)
#define QEDE_RSS_CAPS_INITED		BIT(2)

	u16				rss_ind_table[128];
	u32				rss_key[10];
	u8				rss_caps;

	/* Both must be a power of two */
	u16				q_num_rx_buffers;
	u16				q_num_tx_buffers;

	bool				gro_disable;

	struct list_head		vlan_list;
	u16				configured_vlans;
	u16				non_configured_vlans;
	bool				accept_any_vlan;

	struct delayed_work		sp_task;
	unsigned long			sp_flags;
	u16				vxlan_dst_port;
	u16				geneve_dst_port;

	struct qede_arfs		*arfs;
	bool				wol_enabled;

	struct qede_rdma_dev		rdma_info;

	struct bpf_prog			*xdp_prog;

	enum qed_hw_err_type		last_err_type;
	unsigned long			err_flags;
#define QEDE_ERR_IS_HANDLED		31
#define QEDE_ERR_ATTN_CLR_EN		0
#define QEDE_ERR_GET_DBG_INFO		1
#define QEDE_ERR_IS_RECOVERABLE		2
#define QEDE_ERR_WARN			3

	struct qede_dump_info		dump_info;
};

enum QEDE_STATE {
	QEDE_STATE_CLOSED,
	QEDE_STATE_OPEN,
	QEDE_STATE_RECOVERY,
};

#define HILO_U64(hi, lo)		((((u64)(hi)) << 32) + (lo))

#define	MAX_NUM_TC	8
#define	MAX_NUM_PRI	8

/* The driver supports the new build_skb() API:
 * RX ring buffer contains pointer to kmalloc() data only,
 * skb are built only after the frame was DMA-ed.
 */
struct sw_rx_data {
	struct page *data;
	dma_addr_t mapping;
	unsigned int page_offset;
};

enum qede_agg_state {
	QEDE_AGG_STATE_NONE  = 0,
	QEDE_AGG_STATE_START = 1,
	QEDE_AGG_STATE_ERROR = 2
};

struct qede_agg_info {
	/* rx_buf is a data buffer that can be placed / consumed from rx bd
	 * chain. It has two purposes: We will preallocate the data buffer
	 * for each aggregation when we open the interface and will place this
	 * buffer on the rx-bd-ring when we receive TPA_START. We don't want
	 * to be in a state where allocation fails, as we can't reuse the
	 * consumer buffer in the rx-chain since FW may still be writing to it
	 * (since header needs to be modified for TPA).
	 * The second purpose is to keep a pointer to the bd buffer during
	 * aggregation.
	 */
	struct sw_rx_data buffer;
	struct sk_buff *skb;

	/* We need some structs from the start cookie until termination */
	u16 vlan_tag;

	bool tpa_start_fail;
	u8 state;
	u8 frag_id;

	u8 tunnel_type;
};

struct qede_rx_queue {
	__le16 *hw_cons_ptr;
	void __iomem *hw_rxq_prod_addr;

	/* Required for the allocation of replacement buffers */
	struct device *dev;

	struct bpf_prog *xdp_prog;

	u16 sw_rx_cons;
	u16 sw_rx_prod;

	u16 filled_buffers;
	u8 data_direction;
	u8 rxq_id;

	/* Used once per each NAPI run */
	u16 num_rx_buffers;

	u16 rx_headroom;

	u32 rx_buf_size;
	u32 rx_buf_seg_size;

	struct sw_rx_data *sw_rx_ring;
	struct qed_chain rx_bd_ring;
	struct qed_chain rx_comp_ring ____cacheline_aligned;

	/* GRO */
	struct qede_agg_info tpa_info[ETH_TPA_MAX_AGGS_NUM];

	/* Used once per each NAPI run */
	u64 rcv_pkts;

	u64 rx_hw_errors;
	u64 rx_alloc_errors;
	u64 rx_ip_frags;

	u64 xdp_no_pass;

	void *handle;
	struct xdp_rxq_info xdp_rxq;
};

union db_prod {
	struct eth_db_data data;
	u32		raw;
};

struct sw_tx_bd {
	struct sk_buff *skb;
	u8 flags;
/* Set on the first BD descriptor when there is a split BD */
#define QEDE_TSO_SPLIT_BD		BIT(0)
};

struct sw_tx_xdp {
	struct page			*page;
	struct xdp_frame		*xdpf;
	dma_addr_t			mapping;
};

struct qede_tx_queue {
	u8				is_xdp;
	bool				is_legacy;
	u16				sw_tx_cons;
	u16				sw_tx_prod;
	u16				num_tx_buffers; /* Slowpath only */

	u64				xmit_pkts;
	u64				stopped_cnt;
	u64				tx_mem_alloc_err;

	__le16				*hw_cons_ptr;

	/* Needed for the mapping of packets */
	struct device			*dev;

	void __iomem			*doorbell_addr;
	union db_prod			tx_db;

	/* Spinlock for XDP queues in case of XDP_REDIRECT */
	spinlock_t			xdp_tx_lock;

	int				index; /* Slowpath only */
#define QEDE_TXQ_XDP_TO_IDX(edev, txq)	((txq)->index - \
					 QEDE_MAX_TSS_CNT(edev))
#define QEDE_TXQ_IDX_TO_XDP(edev, idx)	((idx) + QEDE_MAX_TSS_CNT(edev))
#define QEDE_NDEV_TXQ_ID_TO_FP_ID(edev, idx)	((edev)->fp_num_rx + \
						 ((idx) % QEDE_TSS_COUNT(edev)))
#define QEDE_NDEV_TXQ_ID_TO_TXQ_COS(edev, idx)	((idx) / QEDE_TSS_COUNT(edev))
#define QEDE_TXQ_TO_NDEV_TXQ_ID(edev, txq)	((QEDE_TSS_COUNT(edev) * \
						 (txq)->cos) + (txq)->index)
#define QEDE_NDEV_TXQ_ID_TO_TXQ(edev, idx)	\
	(&((edev)->fp_array[QEDE_NDEV_TXQ_ID_TO_FP_ID(edev, idx)].txq \
	[QEDE_NDEV_TXQ_ID_TO_TXQ_COS(edev, idx)]))
#define QEDE_FP_TC0_TXQ(fp)		(&((fp)->txq[0]))

	/* Regular Tx requires skb + metadata for release purpose,
	 * while XDP requires the pages and the mapped address.
	 */
	union {
		struct sw_tx_bd		*skbs;
		struct sw_tx_xdp	*xdp;
	}				sw_tx_ring;

	struct qed_chain		tx_pbl;

	/* Slowpath; Should be kept in end [unless missing padding] */
	void				*handle;
	u16				cos;
	u16				ndev_txq_id;
};

#define BD_UNMAP_ADDR(bd)		HILO_U64(le32_to_cpu((bd)->addr.hi), \
						 le32_to_cpu((bd)->addr.lo))
#define BD_SET_UNMAP_ADDR_LEN(bd, maddr, len)				\
	do {								\
		(bd)->addr.hi = cpu_to_le32(upper_32_bits(maddr));	\
		(bd)->addr.lo = cpu_to_le32(lower_32_bits(maddr));	\
		(bd)->nbytes = cpu_to_le16(len);			\
	} while (0)
#define BD_UNMAP_LEN(bd)		(le16_to_cpu((bd)->nbytes))

struct qede_fastpath {
	struct qede_dev			*edev;

	u8				type;
#define QEDE_FASTPATH_TX		BIT(0)
#define QEDE_FASTPATH_RX		BIT(1)
#define QEDE_FASTPATH_XDP		BIT(2)
#define QEDE_FASTPATH_COMBINED		(QEDE_FASTPATH_TX | QEDE_FASTPATH_RX)

	u8				id;

	u8				xdp_xmit;
#define QEDE_XDP_TX			BIT(0)
#define QEDE_XDP_REDIRECT		BIT(1)

	struct napi_struct		napi;
	struct qed_sb_info		*sb_info;
	struct qede_rx_queue		*rxq;
	struct qede_tx_queue		*txq;
	struct qede_tx_queue		*xdp_tx;

	char				name[IFNAMSIZ + 8];
};

/* Debug print definitions */
#define DP_NAME(edev)			netdev_name((edev)->ndev)

#define XMIT_PLAIN			0
#define XMIT_L4_CSUM			BIT(0)
#define XMIT_LSO			BIT(1)
#define XMIT_ENC			BIT(2)
#define XMIT_ENC_GSO_L4_CSUM		BIT(3)

#define QEDE_CSUM_ERROR			BIT(0)
#define QEDE_CSUM_UNNECESSARY		BIT(1)
#define QEDE_TUNN_CSUM_UNNECESSARY	BIT(2)

#define QEDE_SP_RECOVERY		0
#define QEDE_SP_RX_MODE			1
#define QEDE_SP_RSVD1                   2
#define QEDE_SP_RSVD2                   3
#define QEDE_SP_HW_ERR                  4
#define QEDE_SP_ARFS_CONFIG             5
#define QEDE_SP_AER			7

#ifdef CONFIG_RFS_ACCEL
int qede_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
		       u16 rxq_index, u32 flow_id);
#define QEDE_SP_TASK_POLL_DELAY	(5 * HZ)
#endif

void qede_process_arfs_filters(struct qede_dev *edev, bool free_fltr);
void qede_poll_for_freeing_arfs_filters(struct qede_dev *edev);
void qede_arfs_filter_op(void *dev, void *filter, u8 fw_rc);
void qede_free_arfs(struct qede_dev *edev);
int qede_alloc_arfs(struct qede_dev *edev);
int qede_add_cls_rule(struct qede_dev *edev, struct ethtool_rxnfc *info);
int qede_delete_flow_filter(struct qede_dev *edev, u64 cookie);
int qede_get_cls_rule_entry(struct qede_dev *edev, struct ethtool_rxnfc *cmd);
int qede_get_cls_rule_all(struct qede_dev *edev, struct ethtool_rxnfc *info,
			  u32 *rule_locs);
int qede_get_arfs_filter_count(struct qede_dev *edev);

struct qede_reload_args {
	void (*func)(struct qede_dev *edev, struct qede_reload_args *args);
	union {
		netdev_features_t features;
		struct bpf_prog *new_prog;
		u16 mtu;
	} u;
};

/* Datapath functions definition */
netdev_tx_t qede_start_xmit(struct sk_buff *skb, struct net_device *ndev);
int qede_xdp_transmit(struct net_device *dev, int n_frames,
		      struct xdp_frame **frames, u32 flags);
u16 qede_select_queue(struct net_device *dev, struct sk_buff *skb,
		      struct net_device *sb_dev);
netdev_features_t qede_features_check(struct sk_buff *skb,
				      struct net_device *dev,
				      netdev_features_t features);
int qede_alloc_rx_buffer(struct qede_rx_queue *rxq, bool allow_lazy);
int qede_free_tx_pkt(struct qede_dev *edev,
		     struct qede_tx_queue *txq, int *len);
int qede_poll(struct napi_struct *napi, int budget);
irqreturn_t qede_msix_fp_int(int irq, void *fp_cookie);

/* Filtering function definitions */
void qede_force_mac(void *dev, u8 *mac, bool forced);
void qede_udp_ports_update(void *dev, u16 vxlan_port, u16 geneve_port);
int qede_set_mac_addr(struct net_device *ndev, void *p);

int qede_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid);
int qede_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid);
void qede_vlan_mark_nonconfigured(struct qede_dev *edev);
int qede_configure_vlan_filters(struct qede_dev *edev);

netdev_features_t qede_fix_features(struct net_device *dev,
				    netdev_features_t features);
int qede_set_features(struct net_device *dev, netdev_features_t features);
void qede_set_rx_mode(struct net_device *ndev);
void qede_config_rx_mode(struct net_device *ndev);
void qede_fill_rss_params(struct qede_dev *edev,
			  struct qed_update_vport_rss_params *rss, u8 *update);

void qede_udp_tunnel_add(struct net_device *dev, struct udp_tunnel_info *ti);
void qede_udp_tunnel_del(struct net_device *dev, struct udp_tunnel_info *ti);

int qede_xdp(struct net_device *dev, struct netdev_bpf *xdp);

#ifdef CONFIG_DCB
void qede_set_dcbnl_ops(struct net_device *ndev);
#endif

void qede_config_debug(uint debug, u32 *p_dp_module, u8 *p_dp_level);
void qede_set_ethtool_ops(struct net_device *netdev);
void qede_set_udp_tunnels(struct qede_dev *edev);
void qede_reload(struct qede_dev *edev,
		 struct qede_reload_args *args, bool is_locked);
int qede_change_mtu(struct net_device *dev, int new_mtu);
void qede_fill_by_demand_stats(struct qede_dev *edev);
void __qede_lock(struct qede_dev *edev);
void __qede_unlock(struct qede_dev *edev);
bool qede_has_rx_work(struct qede_rx_queue *rxq);
int qede_txq_has_work(struct qede_tx_queue *txq);
void qede_recycle_rx_bd_ring(struct qede_rx_queue *rxq, u8 count);
void qede_update_rx_prod(struct qede_dev *edev, struct qede_rx_queue *rxq);
int qede_add_tc_flower_fltr(struct qede_dev *edev, __be16 proto,
			    struct flow_cls_offload *f);

void qede_forced_speed_maps_init(void);

#define RX_RING_SIZE_POW	13
#define RX_RING_SIZE		((u16)BIT(RX_RING_SIZE_POW))
#define NUM_RX_BDS_MAX		(RX_RING_SIZE - 1)
#define NUM_RX_BDS_MIN		128
#define NUM_RX_BDS_KDUMP_MIN	63
#define NUM_RX_BDS_DEF		((u16)BIT(10) - 1)

#define TX_RING_SIZE_POW	13
#define TX_RING_SIZE		((u16)BIT(TX_RING_SIZE_POW))
#define NUM_TX_BDS_MAX		(TX_RING_SIZE - 1)
#define NUM_TX_BDS_MIN		128
#define NUM_TX_BDS_KDUMP_MIN	63
#define NUM_TX_BDS_DEF		NUM_TX_BDS_MAX

#define QEDE_MIN_PKT_LEN		64
#define QEDE_RX_HDR_SIZE		256
#define QEDE_MAX_JUMBO_PACKET_SIZE	9600
#define	for_each_queue(i) for (i = 0; i < edev->num_queues; i++)
#define for_each_cos_in_txq(edev, var) \
	for ((var) = 0; (var) < (edev)->dev_info.num_tc; (var)++)

#endif /* _QEDE_H_ */
Commit	Line	Data
7268f33e	1	/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
e712d52b	2	/* QLogic qede NIC Driver
e8f1cb50	3	* Copyright (c) 2015-2017 QLogic Corporation
c4fad2a5	4	* Copyright (c) 2019-2020 Marvell International Ltd.
e8f1cb50	5	*/
7268f33e	6
e712d52b YM	7	#ifndef _QEDE_H_
	8	#define _QEDE_H_
	9	#include <linux/compiler.h>
	10	#include <linux/version.h>
	11	#include <linux/workqueue.h>
	12	#include <linux/netdevice.h>
	13	#include <linux/interrupt.h>
	14	#include <linux/bitmap.h>
	15	#include <linux/kernel.h>
	16	#include <linux/mutex.h>
496e0517	17	#include <linux/bpf.h>
c0124f32	18	#include <net/xdp.h>
b262a06e	19	#include <linux/qed/qede_rdma.h>
e712d52b	20	#include <linux/io.h>
e4917d46 CM	21	#ifdef CONFIG_RFS_ACCEL
	22	#include <linux/cpu_rmap.h>
	23	#endif
e712d52b YM	24	#include <linux/qed/common_hsi.h>
	25	#include <linux/qed/eth_common.h>
	26	#include <linux/qed/qed_if.h>
	27	#include <linux/qed/qed_chain.h>
	28	#include <linux/qed/qed_eth_if.h>
	29
2ce9c93e MC	30	#include <net/pkt_cls.h>
	31	#include <net/tc_act/tc_gact.h>
	32
e712d52b	33	#define QEDE_MAJOR_VERSION 8
42dbcd6b	34	#define QEDE_MINOR_VERSION 37
41e87c91 TT	35	#define QEDE_REVISION_VERSION 0
41e87c91 TT	36	#define QEDE_ENGINEERING_VERSION 20
e712d52b YM	37	#define DRV_MODULE_VERSION __stringify(QEDE_MAJOR_VERSION) "." \
	38	__stringify(QEDE_MINOR_VERSION) "." \
	39	__stringify(QEDE_REVISION_VERSION) "." \
	40	__stringify(QEDE_ENGINEERING_VERSION)
	41
e712d52b YM	42	#define DRV_MODULE_SYM qede
e712d52b YM	43
9c79ddaa	44	struct qede_stats_common {
133fac0e	45	u64 no_buff_discards;
1a5a366f SRK	46	u64 packet_too_big_discard;
1a5a366f SRK	47	u64 ttl0_discard;
133fac0e SK	48	u64 rx_ucast_bytes;
	49	u64 rx_mcast_bytes;
	50	u64 rx_bcast_bytes;
	51	u64 rx_ucast_pkts;
	52	u64 rx_mcast_pkts;
	53	u64 rx_bcast_pkts;
	54	u64 mftag_filter_discards;
	55	u64 mac_filter_discards;
608e00d0	56	u64 gft_filter_drop;
133fac0e SK	57	u64 tx_ucast_bytes;
	58	u64 tx_mcast_bytes;
	59	u64 tx_bcast_bytes;
	60	u64 tx_ucast_pkts;
	61	u64 tx_mcast_pkts;
	62	u64 tx_bcast_pkts;
	63	u64 tx_err_drop_pkts;
	64	u64 coalesced_pkts;
	65	u64 coalesced_events;
	66	u64 coalesced_aborts_num;
	67	u64 non_coalesced_pkts;
	68	u64 coalesced_bytes;
32d26a68	69	u64 link_change_count;
9adebac3	70	u64 ptp_skip_txts;
133fac0e SK	71
	72	/* port */
	73	u64 rx_64_byte_packets;
d4967cf3 YM	74	u64 rx_65_to_127_byte_packets;
	75	u64 rx_128_to_255_byte_packets;
	76	u64 rx_256_to_511_byte_packets;
	77	u64 rx_512_to_1023_byte_packets;
	78	u64 rx_1024_to_1518_byte_packets;
133fac0e SK	79	u64 rx_crc_errors;
	80	u64 rx_mac_crtl_frames;
	81	u64 rx_pause_frames;
	82	u64 rx_pfc_frames;
	83	u64 rx_align_errors;
	84	u64 rx_carrier_errors;
	85	u64 rx_oversize_packets;
	86	u64 rx_jabbers;
	87	u64 rx_undersize_packets;
	88	u64 rx_fragments;
	89	u64 tx_64_byte_packets;
	90	u64 tx_65_to_127_byte_packets;
	91	u64 tx_128_to_255_byte_packets;
	92	u64 tx_256_to_511_byte_packets;
	93	u64 tx_512_to_1023_byte_packets;
	94	u64 tx_1024_to_1518_byte_packets;
9c79ddaa MY	95	u64 tx_pause_frames;
	96	u64 tx_pfc_frames;
	97	u64 brb_truncates;
	98	u64 brb_discards;
	99	u64 tx_mac_ctrl_frames;
	100	};
	101
	102	struct qede_stats_bb {
	103	u64 rx_1519_to_1522_byte_packets;
	104	u64 rx_1519_to_2047_byte_packets;
	105	u64 rx_2048_to_4095_byte_packets;
	106	u64 rx_4096_to_9216_byte_packets;
	107	u64 rx_9217_to_16383_byte_packets;
133fac0e SK	108	u64 tx_1519_to_2047_byte_packets;
	109	u64 tx_2048_to_4095_byte_packets;
	110	u64 tx_4096_to_9216_byte_packets;
	111	u64 tx_9217_to_16383_byte_packets;
133fac0e SK	112	u64 tx_lpi_entry_count;
133fac0e SK	113	u64 tx_total_collisions;
9c79ddaa MY	114	};
	115
	116	struct qede_stats_ah {
	117	u64 rx_1519_to_max_byte_packets;
	118	u64 tx_1519_to_max_byte_packets;
	119	};
	120
	121	struct qede_stats {
	122	struct qede_stats_common common;
	123
	124	union {
	125	struct qede_stats_bb bb;
	126	struct qede_stats_ah ah;
	127	};
133fac0e SK	128	};
133fac0e SK	129
7c1bfcad SRK	130	struct qede_vlan {
	131	struct list_head list;
	132	u16 vid;
	133	bool configured;
	134	};
	135
cee9fbd8 RA	136	struct qede_rdma_dev {
	137	struct qedr_dev *qedr_dev;
	138	struct list_head entry;
bbfcd1e8 MK	139	struct list_head rdma_event_list;
bbfcd1e8 MK	140	struct workqueue_struct *rdma_wq;
af6565ad MK	141	struct kref refcnt;
af6565ad MK	142	struct completion event_comp;
ccc67ef5	143	bool exp_recovery;
cee9fbd8 RA	144	};
cee9fbd8 RA	145
4c55215c SRK	146	struct qede_ptp;
4c55215c SRK	147
ec9b8dbd CM	148	#define QEDE_RFS_MAX_FLTR 256
ec9b8dbd CM	149
149d3775 SRK	150	enum qede_flags_bit {
149d3775 SRK	151	QEDE_FLAGS_IS_VF = 0,
f04e48db	152	QEDE_FLAGS_LINK_REQUESTED,
149d3775 SRK	153	QEDE_FLAGS_PTP_TX_IN_PRORGESS,
	154	QEDE_FLAGS_TX_TIMESTAMPING_EN
	155	};
	156
d44a3ced SRK	157	#define QEDE_DUMP_MAX_ARGS 4
	158	enum qede_dump_cmd {
	159	QEDE_DUMP_CMD_NONE = 0,
	160	QEDE_DUMP_CMD_NVM_CFG,
849dbf09	161	QEDE_DUMP_CMD_GRCDUMP,
d44a3ced SRK	162	QEDE_DUMP_CMD_MAX
	163	};
	164
	165	struct qede_dump_info {
	166	enum qede_dump_cmd cmd;
	167	u8 num_args;
	168	u32 args[QEDE_DUMP_MAX_ARGS];
	169	};
	170
e712d52b YM	171	struct qede_dev {
	172	struct qed_dev *cdev;
	173	struct net_device *ndev;
	174	struct pci_dev *pdev;
755f982b	175	struct devlink *devlink;
e712d52b YM	176
	177	u32 dp_module;
	178	u8 dp_level;
	179
f35535f7 AL	180	unsigned long flags;
	181	#define IS_VF(edev) test_bit(QEDE_FLAGS_IS_VF, \
	182	&(edev)->flags)
fefb0202	183
e712d52b	184	const struct qed_eth_ops *ops;
4c55215c	185	struct qede_ptp *ptp;
9adebac3	186	u64 ptp_skip_txts;
e712d52b	187
f35535f7 AL	188	struct qed_dev_eth_info dev_info;
	189	#define QEDE_MAX_RSS_CNT(edev) ((edev)->dev_info.num_queues)
	190	#define QEDE_MAX_TSS_CNT(edev) ((edev)->dev_info.num_queues)
9c79ddaa MY	191	#define QEDE_IS_BB(edev) \
	192	((edev)->dev_info.common.dev_type == QED_DEV_TYPE_BB)
	193	#define QEDE_IS_AH(edev) \
	194	((edev)->dev_info.common.dev_type == QED_DEV_TYPE_AH)
e712d52b	195
2950219d	196	struct qede_fastpath *fp_array;
9a4d7e86 SRK	197	u8 req_num_tx;
	198	u8 fp_num_tx;
	199	u8 req_num_rx;
	200	u8 fp_num_rx;
	201	u16 req_queues;
	202	u16 num_queues;
d1b25b79	203	u16 total_xdp_queues;
f35535f7 AL	204
	205	#define QEDE_QUEUE_CNT(edev) ((edev)->num_queues)
	206	#define QEDE_RSS_COUNT(edev) ((edev)->num_queues - (edev)->fp_num_tx)
f29ffdb6	207	#define QEDE_RX_QUEUE_IDX(edev, i) (i)
f35535f7	208	#define QEDE_TSS_COUNT(edev) ((edev)->num_queues - (edev)->fp_num_rx)
e712d52b YM	209
e712d52b YM	210	struct qed_int_info int_info;
e712d52b	211
f35535f7	212	/* Smaller private variant of the RTNL lock */
e712d52b YM	213	struct mutex qede_lock;
e712d52b YM	214	u32 state; /* Protected by qede_lock */
2950219d	215	u16 rx_buf_size;
3d789994 MC	216	u32 rx_copybreak;
3d789994 MC	217
2950219d YM	218	/* L2 header size + 2VLANs (8 bytes) + LLC SNAP (8 bytes) /
	219	#define ETH_OVERHEAD (ETH_HLEN + 8 + 8)
	220	/* Max supported alignment is 256 (8 shift)
	221	* minimal alignment shift 6 is optimal for 57xxx HW performance
	222	*/
	223	#define QEDE_RX_ALIGN_SHIFT max(6, min(8, L1_CACHE_SHIFT))
	224	/* We assume skb_build() uses sizeof(struct skb_shared_info) bytes
	225	* at the end of skb->data, to avoid wasting a full cache line.
	226	* This reduces memory use (skb->truesize).
	227	*/
	228	#define QEDE_FW_RX_ALIGN_END \
	229	max_t(u64, 1UL << QEDE_RX_ALIGN_SHIFT, \
	230	SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
	231
133fac0e	232	struct qede_stats stats;
f35535f7 AL	233
	234	/* Bitfield to track initialized RSS params */
	235	u32 rss_params_inited;
	236	#define QEDE_RSS_INDIR_INITED BIT(0)
	237	#define QEDE_RSS_KEY_INITED BIT(1)
	238	#define QEDE_RSS_CAPS_INITED BIT(2)
	239
	240	u16 rss_ind_table[128];
	241	u32 rss_key[10];
	242	u8 rss_caps;
	243
	244	/* Both must be a power of two */
	245	u16 q_num_rx_buffers;
	246	u16 q_num_tx_buffers;
	247
	248	bool gro_disable;
	249
	250	struct list_head vlan_list;
	251	u16 configured_vlans;
	252	u16 non_configured_vlans;
	253	bool accept_any_vlan;
	254
0d8e0aa0 SK	255	struct delayed_work sp_task;
0d8e0aa0 SK	256	unsigned long sp_flags;
b18e170c	257	u16 vxlan_dst_port;
9a109dd0	258	u16 geneve_dst_port;
cee9fbd8	259
e4917d46	260	struct qede_arfs *arfs;
e4917d46	261	bool wol_enabled;
14d39648	262
cee9fbd8	263	struct qede_rdma_dev rdma_info;
496e0517	264
f35535f7	265	struct bpf_prog *xdp_prog;
a8736ea8	266
4f5a8db2	267	enum qed_hw_err_type last_err_type;
f35535f7 AL	268	unsigned long err_flags;
	269	#define QEDE_ERR_IS_HANDLED 31
	270	#define QEDE_ERR_ATTN_CLR_EN 0
	271	#define QEDE_ERR_GET_DBG_INFO 1
	272	#define QEDE_ERR_IS_RECOVERABLE 2
	273	#define QEDE_ERR_WARN 3
a8736ea8	274
d44a3ced	275	struct qede_dump_info dump_info;
2950219d YM	276	};
	277
	278	enum QEDE_STATE {
	279	QEDE_STATE_CLOSED,
	280	QEDE_STATE_OPEN,
ccc67ef5	281	QEDE_STATE_RECOVERY,
2950219d YM	282	};
	283
	284	#define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
	285
	286	#define MAX_NUM_TC 8
	287	#define MAX_NUM_PRI 8
	288
	289	/* The driver supports the new build_skb() API:
	290	* RX ring buffer contains pointer to kmalloc() data only,
	291	* skb are built only after the frame was DMA-ed.
	292	*/
	293	struct sw_rx_data {
fc48b7a6 YM	294	struct page *data;
	295	dma_addr_t mapping;
	296	unsigned int page_offset;
2950219d YM	297	};
2950219d YM	298
55482edc MC	299	enum qede_agg_state {
	300	QEDE_AGG_STATE_NONE = 0,
	301	QEDE_AGG_STATE_START = 1,
	302	QEDE_AGG_STATE_ERROR = 2
	303	};
	304
	305	struct qede_agg_info {
01e23015 MY	306	/* rx_buf is a data buffer that can be placed / consumed from rx bd
	307	* chain. It has two purposes: We will preallocate the data buffer
	308	* for each aggregation when we open the interface and will place this
	309	* buffer on the rx-bd-ring when we receive TPA_START. We don't want
	310	* to be in a state where allocation fails, as we can't reuse the
	311	* consumer buffer in the rx-chain since FW may still be writing to it
	312	* (since header needs to be modified for TPA).
	313	* The second purpose is to keep a pointer to the bd buffer during
	314	* aggregation.
	315	*/
	316	struct sw_rx_data buffer;
55482edc	317	struct sk_buff *skb;
01e23015 MY	318
01e23015 MY	319	/* We need some structs from the start cookie until termination */
55482edc	320	u16 vlan_tag;
01e23015	321
8a863397	322	bool tpa_start_fail;
01e23015 MY	323	u8 state;
	324	u8 frag_id;
	325
	326	u8 tunnel_type;
55482edc MC	327	};
55482edc MC	328
2950219d	329	struct qede_rx_queue {
9eb22357 MY	330	__le16 *hw_cons_ptr;
9eb22357 MY	331	void __iomem *hw_rxq_prod_addr;
2950219d	332
9eb22357 MY	333	/* Required for the allocation of replacement buffers */
	334	struct device *dev;
	335
496e0517 MY	336	struct bpf_prog *xdp_prog;
496e0517 MY	337
9eb22357 MY	338	u16 sw_rx_cons;
9eb22357 MY	339	u16 sw_rx_prod;
55482edc	340
e3eef7ee	341	u16 filled_buffers;
cb6aeb07	342	u8 data_direction;
9eb22357	343	u8 rxq_id;
2950219d	344
15ed8a47 MY	345	/* Used once per each NAPI run */
	346	u16 num_rx_buffers;
	347
	348	u16 rx_headroom;
	349
9eb22357 MY	350	u32 rx_buf_size;
9eb22357 MY	351	u32 rx_buf_seg_size;
2950219d	352
9eb22357 MY	353	struct sw_rx_data *sw_rx_ring;
	354	struct qed_chain rx_bd_ring;
	355	struct qed_chain rx_comp_ring ____cacheline_aligned;
	356
	357	/* GRO */
	358	struct qede_agg_info tpa_info[ETH_TPA_MAX_AGGS_NUM];
	359
15ed8a47 MY	360	/* Used once per each NAPI run */
	361	u64 rcv_pkts;
	362
9eb22357 MY	363	u64 rx_hw_errors;
	364	u64 rx_alloc_errors;
	365	u64 rx_ip_frags;
3da7a37a	366
496e0517 MY	367	u64 xdp_no_pass;
496e0517 MY	368
3da7a37a	369	void *handle;
c0124f32	370	struct xdp_rxq_info xdp_rxq;
2950219d YM	371	};
	372
	373	union db_prod {
	374	struct eth_db_data data;
	375	u32 raw;
	376	};
	377
	378	struct sw_tx_bd {
	379	struct sk_buff *skb;
	380	u8 flags;
	381	/* Set on the first BD descriptor when there is a split BD */
	382	#define QEDE_TSO_SPLIT_BD BIT(0)
	383	};
	384
89e1afc4	385	struct sw_tx_xdp {
f35535f7	386	struct page *page;
d1b25b79	387	struct xdp_frame *xdpf;
f35535f7	388	dma_addr_t mapping;
89e1afc4 MY	389	};
89e1afc4 MY	390
2950219d	391	struct qede_tx_queue {
f35535f7 AL	392	u8 is_xdp;
	393	bool is_legacy;
	394	u16 sw_tx_cons;
	395	u16 sw_tx_prod;
	396	u16 num_tx_buffers; /* Slowpath only */
3da7a37a	397
f35535f7 AL	398	u64 xmit_pkts;
	399	u64 stopped_cnt;
	400	u64 tx_mem_alloc_err;
9eb22357	401
f35535f7	402	__le16 *hw_cons_ptr;
9eb22357 MY	403
9eb22357 MY	404	/* Needed for the mapping of packets */
f35535f7 AL	405	struct device *dev;
	406
	407	void __iomem *doorbell_addr;
	408	union db_prod tx_db;
9eb22357	409
d1b25b79 AL	410	/* Spinlock for XDP queues in case of XDP_REDIRECT */
	411	spinlock_t xdp_tx_lock;
	412
f35535f7	413	int index; /* Slowpath only */
cb6aeb07 MY	414	#define QEDE_TXQ_XDP_TO_IDX(edev, txq) ((txq)->index - \
	415	QEDE_MAX_TSS_CNT(edev))
	416	#define QEDE_TXQ_IDX_TO_XDP(edev, idx) ((idx) + QEDE_MAX_TSS_CNT(edev))
5e7baf0f MC	417	#define QEDE_NDEV_TXQ_ID_TO_FP_ID(edev, idx) ((edev)->fp_num_rx + \
	418	((idx) % QEDE_TSS_COUNT(edev)))
	419	#define QEDE_NDEV_TXQ_ID_TO_TXQ_COS(edev, idx) ((idx) / QEDE_TSS_COUNT(edev))
	420	#define QEDE_TXQ_TO_NDEV_TXQ_ID(edev, txq) ((QEDE_TSS_COUNT(edev) * \
	421	(txq)->cos) + (txq)->index)
	422	#define QEDE_NDEV_TXQ_ID_TO_TXQ(edev, idx) \
	423	(&((edev)->fp_array[QEDE_NDEV_TXQ_ID_TO_FP_ID(edev, idx)].txq \
	424	[QEDE_NDEV_TXQ_ID_TO_TXQ_COS(edev, idx)]))
f35535f7	425	#define QEDE_FP_TC0_TXQ(fp) (&((fp)->txq[0]))
cb6aeb07 MY	426
cb6aeb07 MY	427	/* Regular Tx requires skb + metadata for release purpose,
89e1afc4	428	* while XDP requires the pages and the mapped address.
cb6aeb07 MY	429	*/
cb6aeb07 MY	430	union {
f35535f7 AL	431	struct sw_tx_bd *skbs;
	432	struct sw_tx_xdp *xdp;
	433	} sw_tx_ring;
9eb22357	434
f35535f7	435	struct qed_chain tx_pbl;
9eb22357 MY	436
9eb22357 MY	437	/* Slowpath; Should be kept in end [unless missing padding] */
f35535f7 AL	438	void *handle;
	439	u16 cos;
	440	u16 ndev_txq_id;
2950219d YM	441	};
	442
	443	#define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr.hi), \
	444	le32_to_cpu((bd)->addr.lo))
	445	#define BD_SET_UNMAP_ADDR_LEN(bd, maddr, len) \
	446	do { \
	447	(bd)->addr.hi = cpu_to_le32(upper_32_bits(maddr)); \
	448	(bd)->addr.lo = cpu_to_le32(lower_32_bits(maddr)); \
	449	(bd)->nbytes = cpu_to_le16(len); \
	450	} while (0)
	451	#define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes))
	452
	453	struct qede_fastpath {
f35535f7 AL	454	struct qede_dev *edev;
	455
	456	u8 type;
	457	#define QEDE_FASTPATH_TX BIT(0)
	458	#define QEDE_FASTPATH_RX BIT(1)
	459	#define QEDE_FASTPATH_XDP BIT(2)
	460	#define QEDE_FASTPATH_COMBINED (QEDE_FASTPATH_TX \| QEDE_FASTPATH_RX)
	461
	462	u8 id;
	463
	464	u8 xdp_xmit;
4c2bacbe	465	#define QEDE_XDP_TX BIT(0)
d1b25b79	466	#define QEDE_XDP_REDIRECT BIT(1)
f35535f7 AL	467
	468	struct napi_struct napi;
	469	struct qed_sb_info *sb_info;
	470	struct qede_rx_queue *rxq;
	471	struct qede_tx_queue *txq;
	472	struct qede_tx_queue *xdp_tx;
	473
	474	char name[IFNAMSIZ + 8];
e712d52b YM	475	};
	476
	477	/* Debug print definitions */
f35535f7	478	#define DP_NAME(edev) netdev_name((edev)->ndev)
e712d52b	479
f35535f7 AL	480	#define XMIT_PLAIN 0
	481	#define XMIT_L4_CSUM BIT(0)
	482	#define XMIT_LSO BIT(1)
	483	#define XMIT_ENC BIT(2)
	484	#define XMIT_ENC_GSO_L4_CSUM BIT(3)
2950219d YM	485
	486	#define QEDE_CSUM_ERROR BIT(0)
	487	#define QEDE_CSUM_UNNECESSARY BIT(1)
14db81de	488	#define QEDE_TUNN_CSUM_UNNECESSARY BIT(2)
0d8e0aa0	489
ccc67ef5	490	#define QEDE_SP_RECOVERY 0
b18e170c	491	#define QEDE_SP_RX_MODE 1
a8736ea8 IR	492	#define QEDE_SP_RSVD1 2
	493	#define QEDE_SP_RSVD2 3
	494	#define QEDE_SP_HW_ERR 4
	495	#define QEDE_SP_ARFS_CONFIG 5
731815e7	496	#define QEDE_SP_AER 7
0d8e0aa0	497
e4917d46 CM	498	#ifdef CONFIG_RFS_ACCEL
	499	int qede_rx_flow_steer(struct net_device dev, const struct sk_buff skb,
	500	u16 rxq_index, u32 flow_id);
3f2a2b8b CM	501	#define QEDE_SP_TASK_POLL_DELAY (5 * HZ)
	502	#endif
	503
e4917d46 CM	504	void qede_process_arfs_filters(struct qede_dev *edev, bool free_fltr);
	505	void qede_poll_for_freeing_arfs_filters(struct qede_dev *edev);
	506	void qede_arfs_filter_op(void dev, void filter, u8 fw_rc);
	507	void qede_free_arfs(struct qede_dev *edev);
	508	int qede_alloc_arfs(struct qede_dev *edev);
3f2a2b8b	509	int qede_add_cls_rule(struct qede_dev edev, struct ethtool_rxnfc info);
2ce9c93e	510	int qede_delete_flow_filter(struct qede_dev *edev, u64 cookie);
ec9b8dbd CM	511	int qede_get_cls_rule_entry(struct qede_dev edev, struct ethtool_rxnfc cmd);
	512	int qede_get_cls_rule_all(struct qede_dev edev, struct ethtool_rxnfc info,
	513	u32 *rule_locs);
	514	int qede_get_arfs_filter_count(struct qede_dev *edev);
	515
567b3c12 MY	516	struct qede_reload_args {
	517	void (func)(struct qede_dev edev, struct qede_reload_args *args);
	518	union {
	519	netdev_features_t features;
496e0517	520	struct bpf_prog *new_prog;
567b3c12 MY	521	u16 mtu;
567b3c12 MY	522	} u;
0d8e0aa0 SK	523	};
0d8e0aa0 SK	524
cdda926d MY	525	/* Datapath functions definition */
cdda926d MY	526	netdev_tx_t qede_start_xmit(struct sk_buff skb, struct net_device ndev);
d1b25b79 AL	527	int qede_xdp_transmit(struct net_device *dev, int n_frames,
d1b25b79 AL	528	struct xdp_frame **frames, u32 flags);
0aa4febb	529	u16 qede_select_queue(struct net_device dev, struct sk_buff skb,
a350ecce	530	struct net_device *sb_dev);
cdda926d MY	531	netdev_features_t qede_features_check(struct sk_buff *skb,
	532	struct net_device *dev,
	533	netdev_features_t features);
e3eef7ee	534	int qede_alloc_rx_buffer(struct qede_rx_queue *rxq, bool allow_lazy);
cdda926d MY	535	int qede_free_tx_pkt(struct qede_dev *edev,
	536	struct qede_tx_queue txq, int len);
	537	int qede_poll(struct napi_struct *napi, int budget);
	538	irqreturn_t qede_msix_fp_int(int irq, void *fp_cookie);
aed284c7 MY	539
	540	/* Filtering function definitions */
	541	void qede_force_mac(void dev, u8 mac, bool forced);
97379f15	542	void qede_udp_ports_update(void *dev, u16 vxlan_port, u16 geneve_port);
aed284c7 MY	543	int qede_set_mac_addr(struct net_device ndev, void p);
	544
	545	int qede_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid);
	546	int qede_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid);
	547	void qede_vlan_mark_nonconfigured(struct qede_dev *edev);
	548	int qede_configure_vlan_filters(struct qede_dev *edev);
	549
18c602de MC	550	netdev_features_t qede_fix_features(struct net_device *dev,
18c602de MC	551	netdev_features_t features);
aed284c7 MY	552	int qede_set_features(struct net_device *dev, netdev_features_t features);
	553	void qede_set_rx_mode(struct net_device *ndev);
	554	void qede_config_rx_mode(struct net_device *ndev);
	555	void qede_fill_rss_params(struct qede_dev *edev,
	556	struct qed_update_vport_rss_params rss, u8 update);
	557
	558	void qede_udp_tunnel_add(struct net_device dev, struct udp_tunnel_info ti);
	559	void qede_udp_tunnel_del(struct net_device dev, struct udp_tunnel_info ti);
	560
f4e63525	561	int qede_xdp(struct net_device dev, struct netdev_bpf xdp);
aed284c7	562
489e45ae SRK	563	#ifdef CONFIG_DCB
	564	void qede_set_dcbnl_ops(struct net_device *ndev);
	565	#endif
aed284c7	566
133fac0e SK	567	void qede_config_debug(uint debug, u32 p_dp_module, u8 p_dp_level);
133fac0e SK	568	void qede_set_ethtool_ops(struct net_device *netdev);
8cd160a2	569	void qede_set_udp_tunnels(struct qede_dev *edev);
133fac0e	570	void qede_reload(struct qede_dev *edev,
567b3c12	571	struct qede_reload_args *args, bool is_locked);
133fac0e SK	572	int qede_change_mtu(struct net_device *dev, int new_mtu);
133fac0e SK	573	void qede_fill_by_demand_stats(struct qede_dev *edev);
567b3c12 MY	574	void __qede_lock(struct qede_dev *edev);
567b3c12 MY	575	void __qede_unlock(struct qede_dev *edev);
16f46bf0 SRK	576	bool qede_has_rx_work(struct qede_rx_queue *rxq);
16f46bf0 SRK	577	int qede_txq_has_work(struct qede_tx_queue *txq);
9eb22357	578	void qede_recycle_rx_bd_ring(struct qede_rx_queue *rxq, u8 count);
837d4eb6	579	void qede_update_rx_prod(struct qede_dev edev, struct qede_rx_queue rxq);
2ce9c93e	580	int qede_add_tc_flower_fltr(struct qede_dev *edev, __be16 proto,
f9e30088	581	struct flow_cls_offload *f);
133fac0e	582
1d4e4ecc AL	583	void qede_forced_speed_maps_init(void);
1d4e4ecc AL	584
2950219d	585	#define RX_RING_SIZE_POW 13
01ef7e05	586	#define RX_RING_SIZE ((u16)BIT(RX_RING_SIZE_POW))
2950219d YM	587	#define NUM_RX_BDS_MAX (RX_RING_SIZE - 1)
2950219d YM	588	#define NUM_RX_BDS_MIN 128
73e03097	589	#define NUM_RX_BDS_KDUMP_MIN 63
0e191827	590	#define NUM_RX_BDS_DEF ((u16)BIT(10) - 1)
2950219d YM	591
2950219d YM	592	#define TX_RING_SIZE_POW 13
01ef7e05	593	#define TX_RING_SIZE ((u16)BIT(TX_RING_SIZE_POW))
2950219d YM	594	#define NUM_TX_BDS_MAX (TX_RING_SIZE - 1)
2950219d YM	595	#define NUM_TX_BDS_MIN 128
73e03097	596	#define NUM_TX_BDS_KDUMP_MIN 63
2950219d YM	597	#define NUM_TX_BDS_DEF NUM_TX_BDS_MAX
2950219d YM	598
caff2a87 JW	599	#define QEDE_MIN_PKT_LEN 64
	600	#define QEDE_RX_HDR_SIZE 256
	601	#define QEDE_MAX_JUMBO_PACKET_SIZE 9600
9a4d7e86	602	#define for_each_queue(i) for (i = 0; i < edev->num_queues; i++)
5e7baf0f MC	603	#define for_each_cos_in_txq(edev, var) \
5e7baf0f MC	604	for ((var) = 0; (var) < (edev)->dev_info.num_tc; (var)++)
2950219d	605
e712d52b	606	#endif /* _QEDE_H_ */