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Merge tag 'sh-pfc-for-v5.1-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git...
[mirror_ubuntu-focal-kernel.git] / drivers / net / ethernet / qlogic / qede / qede_main.c
CommitLineData
e712d52b 1/* QLogic qede NIC Driver
e8f1cb50
MY		 2 * Copyright (c) 2015-2017 QLogic Corporation
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
e712d52b
YM		 32#include <linux/module.h>
33#include <linux/pci.h>
34#include <linux/version.h>
35#include <linux/device.h>
36#include <linux/netdevice.h>
37#include <linux/etherdevice.h>
38#include <linux/skbuff.h>
39#include <linux/errno.h>
40#include <linux/list.h>
41#include <linux/string.h>
42#include <linux/dma-mapping.h>
43#include <linux/interrupt.h>
44#include <asm/byteorder.h>
45#include <asm/param.h>
46#include <linux/io.h>
47#include <linux/netdev_features.h>
48#include <linux/udp.h>
49#include <linux/tcp.h>
f9f082a9 50#include <net/udp_tunnel.h>
e712d52b
YM		 51#include <linux/ip.h>
52#include <net/ipv6.h>
53#include <net/tcp.h>
54#include <linux/if_ether.h>
55#include <linux/if_vlan.h>
56#include <linux/pkt_sched.h>
57#include <linux/ethtool.h>
58#include <linux/in.h>
59#include <linux/random.h>
60#include <net/ip6_checksum.h>
61#include <linux/bitops.h>
f29ffdb6 62#include <linux/vmalloc.h>
e712d52b 63#include "qede.h"
4c55215c 64#include "qede_ptp.h"
e712d52b 65
5abd7e92
YM		 66static char version[] =
67 "QLogic FastLinQ 4xxxx Ethernet Driver qede " DRV_MODULE_VERSION "\n";
e712d52b 68
5abd7e92 69MODULE_DESCRIPTION("QLogic FastLinQ 4xxxx Ethernet Driver");
e712d52b
YM		 70MODULE_LICENSE("GPL");
71MODULE_VERSION(DRV_MODULE_VERSION);
72
73static uint debug;
74module_param(debug, uint, 0);
75MODULE_PARM_DESC(debug, " Default debug msglevel");
76
77static const struct qed_eth_ops *qed_ops;
78
79#define CHIP_NUM_57980S_40 0x1634
0e7441d7 80#define CHIP_NUM_57980S_10 0x1666
e712d52b
YM		 81#define CHIP_NUM_57980S_MF 0x1636
82#define CHIP_NUM_57980S_100 0x1644
83#define CHIP_NUM_57980S_50 0x1654
84#define CHIP_NUM_57980S_25 0x1656
fefb0202 85#define CHIP_NUM_57980S_IOV 0x1664
9c79ddaa
MY		 86#define CHIP_NUM_AH 0x8070
87#define CHIP_NUM_AH_IOV 0x8090
e712d52b
YM		 88
89#ifndef PCI_DEVICE_ID_NX2_57980E
90#define PCI_DEVICE_ID_57980S_40 CHIP_NUM_57980S_40
91#define PCI_DEVICE_ID_57980S_10 CHIP_NUM_57980S_10
92#define PCI_DEVICE_ID_57980S_MF CHIP_NUM_57980S_MF
93#define PCI_DEVICE_ID_57980S_100 CHIP_NUM_57980S_100
94#define PCI_DEVICE_ID_57980S_50 CHIP_NUM_57980S_50
95#define PCI_DEVICE_ID_57980S_25 CHIP_NUM_57980S_25
fefb0202 96#define PCI_DEVICE_ID_57980S_IOV CHIP_NUM_57980S_IOV
9c79ddaa
MY		 97#define PCI_DEVICE_ID_AH CHIP_NUM_AH
98#define PCI_DEVICE_ID_AH_IOV CHIP_NUM_AH_IOV
99
e712d52b
YM		 100#endif
101
fefb0202
YM		 102enum qede_pci_private {
103 QEDE_PRIVATE_PF,
104 QEDE_PRIVATE_VF
105};
106
e712d52b 107static const struct pci_device_id qede_pci_tbl[] = {
fefb0202
YM		 108 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_40), QEDE_PRIVATE_PF},
109 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_10), QEDE_PRIVATE_PF},
110 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_MF), QEDE_PRIVATE_PF},
111 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_100), QEDE_PRIVATE_PF},
112 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_50), QEDE_PRIVATE_PF},
113 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_25), QEDE_PRIVATE_PF},
14b84e86 114#ifdef CONFIG_QED_SRIOV
fefb0202 115 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_IOV), QEDE_PRIVATE_VF},
9c79ddaa
MY		 116#endif
117 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_AH), QEDE_PRIVATE_PF},
118#ifdef CONFIG_QED_SRIOV
119 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_AH_IOV), QEDE_PRIVATE_VF},
14b84e86 120#endif
e712d52b
YM		 121 { 0 }
122};
123
124MODULE_DEVICE_TABLE(pci, qede_pci_tbl);
125
126static int qede_probe(struct pci_dev *pdev, const struct pci_device_id *id);
127
128#define TX_TIMEOUT (5 * HZ)
129
cb6aeb07
MY		 130/* Utilize last protocol index for XDP */
131#define XDP_PI 11
132
e712d52b 133static void qede_remove(struct pci_dev *pdev);
14d39648 134static void qede_shutdown(struct pci_dev *pdev);
a2ec6172 135static void qede_link_update(void *dev, struct qed_link_output *link);
d25b859c
SRK		 136static void qede_get_eth_tlv_data(void *edev, void *data);
137static void qede_get_generic_tlv_data(void *edev,
138 struct qed_generic_tlvs *data);
e712d52b 139
567b3c12
MY		 140/* The qede lock is used to protect driver state change and driver flows that
141 * are not reentrant.
142 */
143void __qede_lock(struct qede_dev *edev)
144{
145 mutex_lock(&edev->qede_lock);
146}
147
148void __qede_unlock(struct qede_dev *edev)
149{
150 mutex_unlock(&edev->qede_lock);
151}
152
fefb0202 153#ifdef CONFIG_QED_SRIOV
79aab093
MS		 154static int qede_set_vf_vlan(struct net_device *ndev, int vf, u16 vlan, u8 qos,
155 __be16 vlan_proto)
08feecd7
YM		 156{
157 struct qede_dev *edev = netdev_priv(ndev);
158
159 if (vlan > 4095) {
160 DP_NOTICE(edev, "Illegal vlan value %d\n", vlan);
161 return -EINVAL;
162 }
163
79aab093
MS		 164 if (vlan_proto != htons(ETH_P_8021Q))
165 return -EPROTONOSUPPORT;
166
08feecd7
YM		 167 DP_VERBOSE(edev, QED_MSG_IOV, "Setting Vlan 0x%04x to VF [%d]\n",
168 vlan, vf);
169
170 return edev->ops->iov->set_vlan(edev->cdev, vlan, vf);
171}
172
eff16960
YM		 173static int qede_set_vf_mac(struct net_device *ndev, int vfidx, u8 *mac)
174{
175 struct qede_dev *edev = netdev_priv(ndev);
176
177 DP_VERBOSE(edev, QED_MSG_IOV,
178 "Setting MAC %02x:%02x:%02x:%02x:%02x:%02x to VF [%d]\n",
179 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5], vfidx);
180
181 if (!is_valid_ether_addr(mac)) {
182 DP_VERBOSE(edev, QED_MSG_IOV, "MAC address isn't valid\n");
183 return -EINVAL;
184 }
185
186 return edev->ops->iov->set_mac(edev->cdev, mac, vfidx);
187}
188
fefb0202
YM		 189static int qede_sriov_configure(struct pci_dev *pdev, int num_vfs_param)
190{
191 struct qede_dev *edev = netdev_priv(pci_get_drvdata(pdev));
831bfb0e 192 struct qed_dev_info *qed_info = &edev->dev_info.common;
f29ffdb6 193 struct qed_update_vport_params *vport_params;
831bfb0e 194 int rc;
fefb0202 195
f29ffdb6
MY		 196 vport_params = vzalloc(sizeof(*vport_params));
197 if (!vport_params)
198 return -ENOMEM;
fefb0202
YM		 199 DP_VERBOSE(edev, QED_MSG_IOV, "Requested %d VFs\n", num_vfs_param);
200
831bfb0e
YM		 201 rc = edev->ops->iov->configure(edev->cdev, num_vfs_param);
202
203 /* Enable/Disable Tx switching for PF */
204 if ((rc == num_vfs_param) && netif_running(edev->ndev) &&
0bc5fe85 205 !qed_info->b_inter_pf_switch && qed_info->tx_switching) {
f29ffdb6
MY		 206 vport_params->vport_id = 0;
207 vport_params->update_tx_switching_flg = 1;
208 vport_params->tx_switching_flg = num_vfs_param ? 1 : 0;
209 edev->ops->vport_update(edev->cdev, vport_params);
831bfb0e
YM		 210 }
211
f29ffdb6 212 vfree(vport_params);
831bfb0e 213 return rc;
fefb0202
YM		 214}
215#endif
216
e712d52b
YM		 217static struct pci_driver qede_pci_driver = {
218 .name = "qede",
219 .id_table = qede_pci_tbl,
220 .probe = qede_probe,
221 .remove = qede_remove,
14d39648 222 .shutdown = qede_shutdown,
fefb0202
YM		 223#ifdef CONFIG_QED_SRIOV
224 .sriov_configure = qede_sriov_configure,
225#endif
e712d52b
YM		 226};
227
a2ec6172
SK		 228static struct qed_eth_cb_ops qede_ll_ops = {
229 {
e4917d46
CM		 230#ifdef CONFIG_RFS_ACCEL
231 .arfs_filter_op = qede_arfs_filter_op,
232#endif
a2ec6172 233 .link_update = qede_link_update,
d25b859c
SRK		 234 .get_generic_tlv_data = qede_get_generic_tlv_data,
235 .get_protocol_tlv_data = qede_get_eth_tlv_data,
a2ec6172 236 },
eff16960 237 .force_mac = qede_force_mac,
97379f15 238 .ports_update = qede_udp_ports_update,
a2ec6172
SK		 239};
240
2950219d
YM		 241static int qede_netdev_event(struct notifier_block *this, unsigned long event,
242 void *ptr)
243{
244 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
245 struct ethtool_drvinfo drvinfo;
246 struct qede_dev *edev;
247
cee9fbd8 248 if (event != NETDEV_CHANGENAME && event != NETDEV_CHANGEADDR)
2950219d
YM		 249 goto done;
250
251 /* Check whether this is a qede device */
252 if (!ndev || !ndev->ethtool_ops || !ndev->ethtool_ops->get_drvinfo)
253 goto done;
254
255 memset(&drvinfo, 0, sizeof(drvinfo));
256 ndev->ethtool_ops->get_drvinfo(ndev, &drvinfo);
257 if (strcmp(drvinfo.driver, "qede"))
258 goto done;
259 edev = netdev_priv(ndev);
260
cee9fbd8
RA		 261 switch (event) {
262 case NETDEV_CHANGENAME:
263 /* Notify qed of the name change */
264 if (!edev->ops || !edev->ops->common)
265 goto done;
712c3cbf 266 edev->ops->common->set_name(edev->cdev, edev->ndev->name);
cee9fbd8
RA		 267 break;
268 case NETDEV_CHANGEADDR:
269 edev = netdev_priv(ndev);
bbfcd1e8 270 qede_rdma_event_changeaddr(edev);
cee9fbd8
RA		 271 break;
272 }
2950219d
YM		 273
274done:
275 return NOTIFY_DONE;
276}
277
278static struct notifier_block qede_netdev_notifier = {
279 .notifier_call = qede_netdev_event,
280};
281
e712d52b
YM		 282static
283int __init qede_init(void)
284{
285 int ret;
e712d52b 286
525ef5c0 287 pr_info("qede_init: %s\n", version);
e712d52b 288
95114344 289 qed_ops = qed_get_eth_ops();
e712d52b
YM		 290 if (!qed_ops) {
291 pr_notice("Failed to get qed ethtool operations\n");
292 return -EINVAL;
293 }
294
2950219d 295 /* Must register notifier before pci ops, since we might miss
3f2176dd 296 * interface rename after pci probe and netdev registration.
2950219d
YM		 297 */
298 ret = register_netdevice_notifier(&qede_netdev_notifier);
299 if (ret) {
300 pr_notice("Failed to register netdevice_notifier\n");
301 qed_put_eth_ops();
302 return -EINVAL;
303 }
304
e712d52b
YM		 305 ret = pci_register_driver(&qede_pci_driver);
306 if (ret) {
307 pr_notice("Failed to register driver\n");
2950219d 308 unregister_netdevice_notifier(&qede_netdev_notifier);
e712d52b
YM		 309 qed_put_eth_ops();
310 return -EINVAL;
311 }
312
313 return 0;
314}
315
316static void __exit qede_cleanup(void)
317{
525ef5c0
YM		 318 if (debug & QED_LOG_INFO_MASK)
319 pr_info("qede_cleanup called\n");
e712d52b 320
2950219d 321 unregister_netdevice_notifier(&qede_netdev_notifier);
e712d52b
YM		 322 pci_unregister_driver(&qede_pci_driver);
323 qed_put_eth_ops();
324}
325
326module_init(qede_init);
327module_exit(qede_cleanup);
328
2950219d
YM		 329static int qede_open(struct net_device *ndev);
330static int qede_close(struct net_device *ndev);
7c1bfcad 331
133fac0e
SK		 332void qede_fill_by_demand_stats(struct qede_dev *edev)
333{
9c79ddaa 334 struct qede_stats_common *p_common = &edev->stats.common;
133fac0e
SK		 335 struct qed_eth_stats stats;
336
337 edev->ops->get_vport_stats(edev->cdev, &stats);
9c79ddaa
MY		 338
339 p_common->no_buff_discards = stats.common.no_buff_discards;
340 p_common->packet_too_big_discard = stats.common.packet_too_big_discard;
341 p_common->ttl0_discard = stats.common.ttl0_discard;
342 p_common->rx_ucast_bytes = stats.common.rx_ucast_bytes;
343 p_common->rx_mcast_bytes = stats.common.rx_mcast_bytes;
344 p_common->rx_bcast_bytes = stats.common.rx_bcast_bytes;
345 p_common->rx_ucast_pkts = stats.common.rx_ucast_pkts;
346 p_common->rx_mcast_pkts = stats.common.rx_mcast_pkts;
347 p_common->rx_bcast_pkts = stats.common.rx_bcast_pkts;
348 p_common->mftag_filter_discards = stats.common.mftag_filter_discards;
349 p_common->mac_filter_discards = stats.common.mac_filter_discards;
608e00d0 350 p_common->gft_filter_drop = stats.common.gft_filter_drop;
9c79ddaa
MY		 351
352 p_common->tx_ucast_bytes = stats.common.tx_ucast_bytes;
353 p_common->tx_mcast_bytes = stats.common.tx_mcast_bytes;
354 p_common->tx_bcast_bytes = stats.common.tx_bcast_bytes;
355 p_common->tx_ucast_pkts = stats.common.tx_ucast_pkts;
356 p_common->tx_mcast_pkts = stats.common.tx_mcast_pkts;
357 p_common->tx_bcast_pkts = stats.common.tx_bcast_pkts;
358 p_common->tx_err_drop_pkts = stats.common.tx_err_drop_pkts;
359 p_common->coalesced_pkts = stats.common.tpa_coalesced_pkts;
360 p_common->coalesced_events = stats.common.tpa_coalesced_events;
361 p_common->coalesced_aborts_num = stats.common.tpa_aborts_num;
362 p_common->non_coalesced_pkts = stats.common.tpa_not_coalesced_pkts;
363 p_common->coalesced_bytes = stats.common.tpa_coalesced_bytes;
364
365 p_common->rx_64_byte_packets = stats.common.rx_64_byte_packets;
366 p_common->rx_65_to_127_byte_packets =
367 stats.common.rx_65_to_127_byte_packets;
368 p_common->rx_128_to_255_byte_packets =
369 stats.common.rx_128_to_255_byte_packets;
370 p_common->rx_256_to_511_byte_packets =
371 stats.common.rx_256_to_511_byte_packets;
372 p_common->rx_512_to_1023_byte_packets =
373 stats.common.rx_512_to_1023_byte_packets;
374 p_common->rx_1024_to_1518_byte_packets =
375 stats.common.rx_1024_to_1518_byte_packets;
376 p_common->rx_crc_errors = stats.common.rx_crc_errors;
377 p_common->rx_mac_crtl_frames = stats.common.rx_mac_crtl_frames;
378 p_common->rx_pause_frames = stats.common.rx_pause_frames;
379 p_common->rx_pfc_frames = stats.common.rx_pfc_frames;
380 p_common->rx_align_errors = stats.common.rx_align_errors;
381 p_common->rx_carrier_errors = stats.common.rx_carrier_errors;
382 p_common->rx_oversize_packets = stats.common.rx_oversize_packets;
383 p_common->rx_jabbers = stats.common.rx_jabbers;
384 p_common->rx_undersize_packets = stats.common.rx_undersize_packets;
385 p_common->rx_fragments = stats.common.rx_fragments;
386 p_common->tx_64_byte_packets = stats.common.tx_64_byte_packets;
387 p_common->tx_65_to_127_byte_packets =
388 stats.common.tx_65_to_127_byte_packets;
389 p_common->tx_128_to_255_byte_packets =
390 stats.common.tx_128_to_255_byte_packets;
391 p_common->tx_256_to_511_byte_packets =
392 stats.common.tx_256_to_511_byte_packets;
393 p_common->tx_512_to_1023_byte_packets =
394 stats.common.tx_512_to_1023_byte_packets;
395 p_common->tx_1024_to_1518_byte_packets =
396 stats.common.tx_1024_to_1518_byte_packets;
397 p_common->tx_pause_frames = stats.common.tx_pause_frames;
398 p_common->tx_pfc_frames = stats.common.tx_pfc_frames;
399 p_common->brb_truncates = stats.common.brb_truncates;
400 p_common->brb_discards = stats.common.brb_discards;
401 p_common->tx_mac_ctrl_frames = stats.common.tx_mac_ctrl_frames;
32d26a68 402 p_common->link_change_count = stats.common.link_change_count;
9c79ddaa
MY		 403
404 if (QEDE_IS_BB(edev)) {
405 struct qede_stats_bb *p_bb = &edev->stats.bb;
406
407 p_bb->rx_1519_to_1522_byte_packets =
408 stats.bb.rx_1519_to_1522_byte_packets;
409 p_bb->rx_1519_to_2047_byte_packets =
410 stats.bb.rx_1519_to_2047_byte_packets;
411 p_bb->rx_2048_to_4095_byte_packets =
412 stats.bb.rx_2048_to_4095_byte_packets;
413 p_bb->rx_4096_to_9216_byte_packets =
414 stats.bb.rx_4096_to_9216_byte_packets;
415 p_bb->rx_9217_to_16383_byte_packets =
416 stats.bb.rx_9217_to_16383_byte_packets;
417 p_bb->tx_1519_to_2047_byte_packets =
418 stats.bb.tx_1519_to_2047_byte_packets;
419 p_bb->tx_2048_to_4095_byte_packets =
420 stats.bb.tx_2048_to_4095_byte_packets;
421 p_bb->tx_4096_to_9216_byte_packets =
422 stats.bb.tx_4096_to_9216_byte_packets;
423 p_bb->tx_9217_to_16383_byte_packets =
424 stats.bb.tx_9217_to_16383_byte_packets;
425 p_bb->tx_lpi_entry_count = stats.bb.tx_lpi_entry_count;
426 p_bb->tx_total_collisions = stats.bb.tx_total_collisions;
427 } else {
428 struct qede_stats_ah *p_ah = &edev->stats.ah;
429
430 p_ah->rx_1519_to_max_byte_packets =
431 stats.ah.rx_1519_to_max_byte_packets;
432 p_ah->tx_1519_to_max_byte_packets =
433 stats.ah.tx_1519_to_max_byte_packets;
434 }
133fac0e
SK		 435}
436
bc1f4470 437static void qede_get_stats64(struct net_device *dev,
438 struct rtnl_link_stats64 *stats)
133fac0e
SK		 439{
440 struct qede_dev *edev = netdev_priv(dev);
9c79ddaa 441 struct qede_stats_common *p_common;
133fac0e
SK		 442
443 qede_fill_by_demand_stats(edev);
9c79ddaa 444 p_common = &edev->stats.common;
133fac0e 445
9c79ddaa
MY		 446 stats->rx_packets = p_common->rx_ucast_pkts + p_common->rx_mcast_pkts +
447 p_common->rx_bcast_pkts;
448 stats->tx_packets = p_common->tx_ucast_pkts + p_common->tx_mcast_pkts +
449 p_common->tx_bcast_pkts;
133fac0e 450
9c79ddaa
MY		 451 stats->rx_bytes = p_common->rx_ucast_bytes + p_common->rx_mcast_bytes +
452 p_common->rx_bcast_bytes;
453 stats->tx_bytes = p_common->tx_ucast_bytes + p_common->tx_mcast_bytes +
454 p_common->tx_bcast_bytes;
133fac0e 455
9c79ddaa
MY		 456 stats->tx_errors = p_common->tx_err_drop_pkts;
457 stats->multicast = p_common->rx_mcast_pkts + p_common->rx_bcast_pkts;
133fac0e 458
9c79ddaa 459 stats->rx_fifo_errors = p_common->no_buff_discards;
133fac0e 460
9c79ddaa
MY		 461 if (QEDE_IS_BB(edev))
462 stats->collisions = edev->stats.bb.tx_total_collisions;
463 stats->rx_crc_errors = p_common->rx_crc_errors;
464 stats->rx_frame_errors = p_common->rx_align_errors;
133fac0e
SK		 465}
466
733def6a 467#ifdef CONFIG_QED_SRIOV
73390ac9
YM		 468static int qede_get_vf_config(struct net_device *dev, int vfidx,
469 struct ifla_vf_info *ivi)
470{
471 struct qede_dev *edev = netdev_priv(dev);
472
473 if (!edev->ops)
474 return -EINVAL;
475
476 return edev->ops->iov->get_config(edev->cdev, vfidx, ivi);
477}
478
733def6a
YM		 479static int qede_set_vf_rate(struct net_device *dev, int vfidx,
480 int min_tx_rate, int max_tx_rate)
481{
482 struct qede_dev *edev = netdev_priv(dev);
483
be7b6d64 484 return edev->ops->iov->set_rate(edev->cdev, vfidx, min_tx_rate,
733def6a
YM		 485 max_tx_rate);
486}
487
6ddc7608
YM		 488static int qede_set_vf_spoofchk(struct net_device *dev, int vfidx, bool val)
489{
490 struct qede_dev *edev = netdev_priv(dev);
491
492 if (!edev->ops)
493 return -EINVAL;
494
495 return edev->ops->iov->set_spoof(edev->cdev, vfidx, val);
496}
497
733def6a
YM		 498static int qede_set_vf_link_state(struct net_device *dev, int vfidx,
499 int link_state)
500{
501 struct qede_dev *edev = netdev_priv(dev);
502
503 if (!edev->ops)
504 return -EINVAL;
505
506 return edev->ops->iov->set_link_state(edev->cdev, vfidx, link_state);
507}
f990c82c
MY		 508
509static int qede_set_vf_trust(struct net_device *dev, int vfidx, bool setting)
510{
511 struct qede_dev *edev = netdev_priv(dev);
512
513 if (!edev->ops)
514 return -EINVAL;
515
516 return edev->ops->iov->set_trust(edev->cdev, vfidx, setting);
517}
733def6a
YM		 518#endif
519
4c55215c
SRK		 520static int qede_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
521{
522 struct qede_dev *edev = netdev_priv(dev);
523
524 if (!netif_running(dev))
525 return -EAGAIN;
526
527 switch (cmd) {
528 case SIOCSHWTSTAMP:
529 return qede_ptp_hw_ts(edev, ifr);
530 default:
531 DP_VERBOSE(edev, QED_MSG_DEBUG,
532 "default IOCTL cmd 0x%x\n", cmd);
533 return -EOPNOTSUPP;
534 }
535
536 return 0;
537}
538
1e7953bc 539static int qede_setup_tc(struct net_device *ndev, u8 num_tc)
5e7baf0f
MC		 540{
541 struct qede_dev *edev = netdev_priv(ndev);
542 int cos, count, offset;
543
544 if (num_tc > edev->dev_info.num_tc)
545 return -EINVAL;
546
547 netdev_reset_tc(ndev);
548 netdev_set_num_tc(ndev, num_tc);
549
550 for_each_cos_in_txq(edev, cos) {
551 count = QEDE_TSS_COUNT(edev);
552 offset = cos * QEDE_TSS_COUNT(edev);
553 netdev_set_tc_queue(ndev, cos, count, offset);
554 }
555
556 return 0;
557}
558
2ce9c93e
MC		 559static int
560qede_set_flower(struct qede_dev *edev, struct tc_cls_flower_offload *f,
561 __be16 proto)
562{
563 switch (f->command) {
564 case TC_CLSFLOWER_REPLACE:
565 return qede_add_tc_flower_fltr(edev, proto, f);
566 case TC_CLSFLOWER_DESTROY:
567 return qede_delete_flow_filter(edev, f->cookie);
568 default:
569 return -EOPNOTSUPP;
570 }
571}
572
573static int qede_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
574 void *cb_priv)
575{
576 struct tc_cls_flower_offload *f;
577 struct qede_dev *edev = cb_priv;
578
579 if (!tc_cls_can_offload_and_chain0(edev->ndev, type_data))
580 return -EOPNOTSUPP;
581
582 switch (type) {
583 case TC_SETUP_CLSFLOWER:
584 f = type_data;
585 return qede_set_flower(edev, f, f->common.protocol);
586 default:
587 return -EOPNOTSUPP;
588 }
589}
590
591static int qede_setup_tc_block(struct qede_dev *edev,
592 struct tc_block_offload *f)
593{
594 if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
595 return -EOPNOTSUPP;
596
597 switch (f->command) {
598 case TC_BLOCK_BIND:
599 return tcf_block_cb_register(f->block,
600 qede_setup_tc_block_cb,
601 edev, edev, f->extack);
602 case TC_BLOCK_UNBIND:
603 tcf_block_cb_unregister(f->block, qede_setup_tc_block_cb, edev);
604 return 0;
605 default:
606 return -EOPNOTSUPP;
607 }
608}
609
5e7baf0f
MC		 610static int
611qede_setup_tc_offload(struct net_device *dev, enum tc_setup_type type,
612 void *type_data)
613{
2ce9c93e 614 struct qede_dev *edev = netdev_priv(dev);
5e7baf0f
MC		 615 struct tc_mqprio_qopt *mqprio;
616
617 switch (type) {
2ce9c93e
MC		 618 case TC_SETUP_BLOCK:
619 return qede_setup_tc_block(edev, type_data);
5e7baf0f
MC		 620 case TC_SETUP_QDISC_MQPRIO:
621 mqprio = type_data;
622
623 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
624 return qede_setup_tc(dev, mqprio->num_tc);
625 default:
626 return -EOPNOTSUPP;
627 }
628}
629
2950219d
YM		 630static const struct net_device_ops qede_netdev_ops = {
631 .ndo_open = qede_open,
632 .ndo_stop = qede_close,
633 .ndo_start_xmit = qede_start_xmit,
0aa4febb 634 .ndo_select_queue = qede_select_queue,
0d8e0aa0
SK		 635 .ndo_set_rx_mode = qede_set_rx_mode,
636 .ndo_set_mac_address = qede_set_mac_addr,
2950219d 637 .ndo_validate_addr = eth_validate_addr,
133fac0e 638 .ndo_change_mtu = qede_change_mtu,
4c55215c 639 .ndo_do_ioctl = qede_ioctl,
08feecd7 640#ifdef CONFIG_QED_SRIOV
eff16960 641 .ndo_set_vf_mac = qede_set_vf_mac,
08feecd7 642 .ndo_set_vf_vlan = qede_set_vf_vlan,
f990c82c 643 .ndo_set_vf_trust = qede_set_vf_trust,
08feecd7 644#endif
7c1bfcad
SRK		 645 .ndo_vlan_rx_add_vid = qede_vlan_rx_add_vid,
646 .ndo_vlan_rx_kill_vid = qede_vlan_rx_kill_vid,
18c602de 647 .ndo_fix_features = qede_fix_features,
ce2b885c 648 .ndo_set_features = qede_set_features,
133fac0e 649 .ndo_get_stats64 = qede_get_stats64,
733def6a
YM		 650#ifdef CONFIG_QED_SRIOV
651 .ndo_set_vf_link_state = qede_set_vf_link_state,
6ddc7608 652 .ndo_set_vf_spoofchk = qede_set_vf_spoofchk,
73390ac9 653 .ndo_get_vf_config = qede_get_vf_config,
733def6a
YM		 654 .ndo_set_vf_rate = qede_set_vf_rate,
655#endif
f9f082a9
AD		 656 .ndo_udp_tunnel_add = qede_udp_tunnel_add,
657 .ndo_udp_tunnel_del = qede_udp_tunnel_del,
25695853 658 .ndo_features_check = qede_features_check,
f4e63525 659 .ndo_bpf = qede_xdp,
e4917d46
CM		 660#ifdef CONFIG_RFS_ACCEL
661 .ndo_rx_flow_steer = qede_rx_flow_steer,
662#endif
5e7baf0f 663 .ndo_setup_tc = qede_setup_tc_offload,
2950219d
YM		 664};
665
be47c555
MY		 666static const struct net_device_ops qede_netdev_vf_ops = {
667 .ndo_open = qede_open,
668 .ndo_stop = qede_close,
669 .ndo_start_xmit = qede_start_xmit,
0aa4febb 670 .ndo_select_queue = qede_select_queue,
be47c555
MY		 671 .ndo_set_rx_mode = qede_set_rx_mode,
672 .ndo_set_mac_address = qede_set_mac_addr,
673 .ndo_validate_addr = eth_validate_addr,
674 .ndo_change_mtu = qede_change_mtu,
675 .ndo_vlan_rx_add_vid = qede_vlan_rx_add_vid,
676 .ndo_vlan_rx_kill_vid = qede_vlan_rx_kill_vid,
18c602de 677 .ndo_fix_features = qede_fix_features,
be47c555
MY		 678 .ndo_set_features = qede_set_features,
679 .ndo_get_stats64 = qede_get_stats64,
680 .ndo_udp_tunnel_add = qede_udp_tunnel_add,
681 .ndo_udp_tunnel_del = qede_udp_tunnel_del,
682 .ndo_features_check = qede_features_check,
683};
684
e7b80dec
MY		 685static const struct net_device_ops qede_netdev_vf_xdp_ops = {
686 .ndo_open = qede_open,
687 .ndo_stop = qede_close,
688 .ndo_start_xmit = qede_start_xmit,
0aa4febb 689 .ndo_select_queue = qede_select_queue,
e7b80dec
MY		 690 .ndo_set_rx_mode = qede_set_rx_mode,
691 .ndo_set_mac_address = qede_set_mac_addr,
692 .ndo_validate_addr = eth_validate_addr,
693 .ndo_change_mtu = qede_change_mtu,
694 .ndo_vlan_rx_add_vid = qede_vlan_rx_add_vid,
695 .ndo_vlan_rx_kill_vid = qede_vlan_rx_kill_vid,
18c602de 696 .ndo_fix_features = qede_fix_features,
e7b80dec
MY		 697 .ndo_set_features = qede_set_features,
698 .ndo_get_stats64 = qede_get_stats64,
699 .ndo_udp_tunnel_add = qede_udp_tunnel_add,
700 .ndo_udp_tunnel_del = qede_udp_tunnel_del,
701 .ndo_features_check = qede_features_check,
f4e63525 702 .ndo_bpf = qede_xdp,
e7b80dec
MY		 703};
704
e712d52b
YM		 705/* -------------------------------------------------------------------------
706 * START OF PROBE / REMOVE
707 * -------------------------------------------------------------------------
708 */
709
710static struct qede_dev *qede_alloc_etherdev(struct qed_dev *cdev,
711 struct pci_dev *pdev,
712 struct qed_dev_eth_info *info,
1a635e48 713 u32 dp_module, u8 dp_level)
e712d52b
YM		 714{
715 struct net_device *ndev;
716 struct qede_dev *edev;
717
718 ndev = alloc_etherdev_mqs(sizeof(*edev),
5e7baf0f
MC		 719 info->num_queues * info->num_tc,
720 info->num_queues);
e712d52b
YM		 721 if (!ndev) {
722 pr_err("etherdev allocation failed\n");
723 return NULL;
724 }
725
726 edev = netdev_priv(ndev);
727 edev->ndev = ndev;
728 edev->cdev = cdev;
729 edev->pdev = pdev;
730 edev->dp_module = dp_module;
731 edev->dp_level = dp_level;
732 edev->ops = qed_ops;
2950219d
YM		 733 edev->q_num_rx_buffers = NUM_RX_BDS_DEF;
734 edev->q_num_tx_buffers = NUM_TX_BDS_DEF;
e712d52b 735
525ef5c0
YM		 736 DP_INFO(edev, "Allocated netdev with %d tx queues and %d rx queues\n",
737 info->num_queues, info->num_queues);
738
e712d52b
YM		 739 SET_NETDEV_DEV(ndev, &pdev->dev);
740
133fac0e 741 memset(&edev->stats, 0, sizeof(edev->stats));
e712d52b
YM		 742 memcpy(&edev->dev_info, info, sizeof(*info));
743
ba798b5b
MY		 744 /* As ethtool doesn't have the ability to show WoL behavior as
745 * 'default', if device supports it declare it's enabled.
746 */
747 if (edev->dev_info.common.wol_support)
748 edev->wol_enabled = true;
749
7c1bfcad
SRK		 750 INIT_LIST_HEAD(&edev->vlan_list);
751
e712d52b
YM		 752 return edev;
753}
754
755static void qede_init_ndev(struct qede_dev *edev)
756{
757 struct net_device *ndev = edev->ndev;
758 struct pci_dev *pdev = edev->pdev;
19489c7f 759 bool udp_tunnel_enable = false;
e4917d46 760 netdev_features_t hw_features;
e712d52b
YM		 761
762 pci_set_drvdata(pdev, ndev);
763
764 ndev->mem_start = edev->dev_info.common.pci_mem_start;
765 ndev->base_addr = ndev->mem_start;
766 ndev->mem_end = edev->dev_info.common.pci_mem_end;
767 ndev->irq = edev->dev_info.common.pci_irq;
768
769 ndev->watchdog_timeo = TX_TIMEOUT;
770
e7b80dec
MY		 771 if (IS_VF(edev)) {
772 if (edev->dev_info.xdp_supported)
773 ndev->netdev_ops = &qede_netdev_vf_xdp_ops;
774 else
775 ndev->netdev_ops = &qede_netdev_vf_ops;
776 } else {
be47c555 777 ndev->netdev_ops = &qede_netdev_ops;
e7b80dec 778 }
2950219d 779
133fac0e
SK		 780 qede_set_ethtool_ops(ndev);
781
0183eb1c 782 ndev->priv_flags |= IFF_UNICAST_FLT;
7b7e70f9 783
e712d52b 784 /* user-changeble features */
18c602de 785 hw_features = NETIF_F_GRO | NETIF_F_GRO_HW | NETIF_F_SG |
e712d52b 786 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2ce9c93e 787 NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_HW_TC;
e712d52b 788
e4917d46
CM		 789 if (!IS_VF(edev) && edev->dev_info.common.num_hwfns == 1)
790 hw_features |= NETIF_F_NTUPLE;
791
19489c7f
CM		 792 if (edev->dev_info.common.vxlan_enable ||
793 edev->dev_info.common.geneve_enable)
794 udp_tunnel_enable = true;
795
796 if (udp_tunnel_enable || edev->dev_info.common.gre_enable) {
797 hw_features |= NETIF_F_TSO_ECN;
798 ndev->hw_enc_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
799 NETIF_F_SG | NETIF_F_TSO |
800 NETIF_F_TSO_ECN | NETIF_F_TSO6 |
801 NETIF_F_RXCSUM;
802 }
803
804 if (udp_tunnel_enable) {
805 hw_features |= (NETIF_F_GSO_UDP_TUNNEL |
806 NETIF_F_GSO_UDP_TUNNEL_CSUM);
807 ndev->hw_enc_features |= (NETIF_F_GSO_UDP_TUNNEL |
808 NETIF_F_GSO_UDP_TUNNEL_CSUM);
809 }
810
811 if (edev->dev_info.common.gre_enable) {
812 hw_features |= (NETIF_F_GSO_GRE | NETIF_F_GSO_GRE_CSUM);
813 ndev->hw_enc_features |= (NETIF_F_GSO_GRE |
814 NETIF_F_GSO_GRE_CSUM);
815 }
14db81de 816
e712d52b
YM		 817 ndev->vlan_features = hw_features | NETIF_F_RXHASH | NETIF_F_RXCSUM |
818 NETIF_F_HIGHDMA;
819 ndev->features = hw_features | NETIF_F_RXHASH | NETIF_F_RXCSUM |
820 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HIGHDMA |
7c1bfcad 821 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_VLAN_CTAG_TX;
e712d52b
YM		 822
823 ndev->hw_features = hw_features;
824
caff2a87
JW		 825 /* MTU range: 46 - 9600 */
826 ndev->min_mtu = ETH_ZLEN - ETH_HLEN;
827 ndev->max_mtu = QEDE_MAX_JUMBO_PACKET_SIZE;
828
e712d52b
YM		 829 /* Set network device HW mac */
830 ether_addr_copy(edev->ndev->dev_addr, edev->dev_info.common.hw_mac);
0fefbfba
SK		 831
832 ndev->mtu = edev->dev_info.common.mtu;
e712d52b
YM		 833}
834
835/* This function converts from 32b param to two params of level and module
836 * Input 32b decoding:
837 * b31 - enable all NOTICE prints. NOTICE prints are for deviation from the
838 * 'happy' flow, e.g. memory allocation failed.
839 * b30 - enable all INFO prints. INFO prints are for major steps in the flow
840 * and provide important parameters.
841 * b29-b0 - per-module bitmap, where each bit enables VERBOSE prints of that
842 * module. VERBOSE prints are for tracking the specific flow in low level.
843 *
844 * Notice that the level should be that of the lowest required logs.
845 */
133fac0e 846void qede_config_debug(uint debug, u32 *p_dp_module, u8 *p_dp_level)
e712d52b
YM		 847{
848 *p_dp_level = QED_LEVEL_NOTICE;
849 *p_dp_module = 0;
850
851 if (debug & QED_LOG_VERBOSE_MASK) {
852 *p_dp_level = QED_LEVEL_VERBOSE;
853 *p_dp_module = (debug & 0x3FFFFFFF);
854 } else if (debug & QED_LOG_INFO_MASK) {
855 *p_dp_level = QED_LEVEL_INFO;
856 } else if (debug & QED_LOG_NOTICE_MASK) {
857 *p_dp_level = QED_LEVEL_NOTICE;
858 }
859}
860
2950219d
YM		 861static void qede_free_fp_array(struct qede_dev *edev)
862{
863 if (edev->fp_array) {
864 struct qede_fastpath *fp;
865 int i;
866
9a4d7e86 867 for_each_queue(i) {
2950219d
YM		 868 fp = &edev->fp_array[i];
869
870 kfree(fp->sb_info);
c0124f32
JDB		 871 /* Handle mem alloc failure case where qede_init_fp
872 * didn't register xdp_rxq_info yet.
873 * Implicit only (fp->type & QEDE_FASTPATH_RX)
874 */
875 if (fp->rxq && xdp_rxq_info_is_reg(&fp->rxq->xdp_rxq))
876 xdp_rxq_info_unreg(&fp->rxq->xdp_rxq);
2950219d 877 kfree(fp->rxq);
cb6aeb07 878 kfree(fp->xdp_tx);
80439a17 879 kfree(fp->txq);
2950219d
YM		 880 }
881 kfree(edev->fp_array);
882 }
9a4d7e86
SRK		 883
884 edev->num_queues = 0;
885 edev->fp_num_tx = 0;
886 edev->fp_num_rx = 0;
2950219d
YM		 887}
888
889static int qede_alloc_fp_array(struct qede_dev *edev)
890{
9a4d7e86 891 u8 fp_combined, fp_rx = edev->fp_num_rx;
2950219d
YM		 892 struct qede_fastpath *fp;
893 int i;
894
9a4d7e86 895 edev->fp_array = kcalloc(QEDE_QUEUE_CNT(edev),
2950219d
YM		 896 sizeof(*edev->fp_array), GFP_KERNEL);
897 if (!edev->fp_array) {
898 DP_NOTICE(edev, "fp array allocation failed\n");
899 goto err;
900 }
901
9a4d7e86
SRK		 902 fp_combined = QEDE_QUEUE_CNT(edev) - fp_rx - edev->fp_num_tx;
903
904 /* Allocate the FP elements for Rx queues followed by combined and then
905 * the Tx. This ordering should be maintained so that the respective
906 * queues (Rx or Tx) will be together in the fastpath array and the
907 * associated ids will be sequential.
908 */
909 for_each_queue(i) {
2950219d
YM		 910 fp = &edev->fp_array[i];
911
80439a17 912 fp->sb_info = kzalloc(sizeof(*fp->sb_info), GFP_KERNEL);
2950219d
YM		 913 if (!fp->sb_info) {
914 DP_NOTICE(edev, "sb info struct allocation failed\n");
915 goto err;
916 }
917
9a4d7e86
SRK		 918 if (fp_rx) {
919 fp->type = QEDE_FASTPATH_RX;
920 fp_rx--;
921 } else if (fp_combined) {
922 fp->type = QEDE_FASTPATH_COMBINED;
923 fp_combined--;
924 } else {
925 fp->type = QEDE_FASTPATH_TX;
2950219d
YM		 926 }
927
9a4d7e86 928 if (fp->type & QEDE_FASTPATH_TX) {
5e7baf0f
MC		 929 fp->txq = kcalloc(edev->dev_info.num_tc,
930 sizeof(*fp->txq), GFP_KERNEL);
80439a17 931 if (!fp->txq)
9a4d7e86 932 goto err;
9a4d7e86
SRK		 933 }
934
935 if (fp->type & QEDE_FASTPATH_RX) {
80439a17
MY		 936 fp->rxq = kzalloc(sizeof(*fp->rxq), GFP_KERNEL);
937 if (!fp->rxq)
9a4d7e86 938 goto err;
496e0517 939
cb6aeb07
MY		 940 if (edev->xdp_prog) {
941 fp->xdp_tx = kzalloc(sizeof(*fp->xdp_tx),
942 GFP_KERNEL);
943 if (!fp->xdp_tx)
944 goto err;
496e0517 945 fp->type |= QEDE_FASTPATH_XDP;
cb6aeb07 946 }
2950219d
YM		 947 }
948 }
949
950 return 0;
951err:
952 qede_free_fp_array(edev);
953 return -ENOMEM;
954}
955
0d8e0aa0
SK		 956static void qede_sp_task(struct work_struct *work)
957{
958 struct qede_dev *edev = container_of(work, struct qede_dev,
959 sp_task.work);
b18e170c 960
567b3c12 961 __qede_lock(edev);
0d8e0aa0 962
567b3c12
MY		 963 if (test_and_clear_bit(QEDE_SP_RX_MODE, &edev->sp_flags))
964 if (edev->state == QEDE_STATE_OPEN)
0d8e0aa0 965 qede_config_rx_mode(edev->ndev);
0d8e0aa0 966
e4917d46
CM		 967#ifdef CONFIG_RFS_ACCEL
968 if (test_and_clear_bit(QEDE_SP_ARFS_CONFIG, &edev->sp_flags)) {
969 if (edev->state == QEDE_STATE_OPEN)
970 qede_process_arfs_filters(edev, false);
971 }
972#endif
567b3c12 973 __qede_unlock(edev);
0d8e0aa0
SK		 974}
975
e712d52b
YM		 976static void qede_update_pf_params(struct qed_dev *cdev)
977{
978 struct qed_pf_params pf_params;
5e7baf0f 979 u16 num_cons;
e712d52b 980
cb6aeb07 981 /* 64 rx + 64 tx + 64 XDP */
e712d52b 982 memset(&pf_params, 0, sizeof(struct qed_pf_params));
5e7baf0f
MC		 983
984 /* 1 rx + 1 xdp + max tx cos */
985 num_cons = QED_MIN_L2_CONS;
986
987 pf_params.eth_pf_params.num_cons = (MAX_SB_PER_PF_MIMD - 1) * num_cons;
e7b80dec
MY		 988
989 /* Same for VFs - make sure they'll have sufficient connections
990 * to support XDP Tx queues.
991 */
992 pf_params.eth_pf_params.num_vf_cons = 48;
993
e4917d46 994 pf_params.eth_pf_params.num_arfs_filters = QEDE_RFS_MAX_FLTR;
e712d52b
YM		 995 qed_ops->common->update_pf_params(cdev, &pf_params);
996}
997
6bc9f234
MY		 998#define QEDE_FW_VER_STR_SIZE 80
999
1000static void qede_log_probe(struct qede_dev *edev)
1001{
1002 struct qed_dev_info *p_dev_info = &edev->dev_info.common;
1003 u8 buf[QEDE_FW_VER_STR_SIZE];
1004 size_t left_size;
1005
1006 snprintf(buf, QEDE_FW_VER_STR_SIZE,
1007 "Storm FW %d.%d.%d.%d, Management FW %d.%d.%d.%d",
1008 p_dev_info->fw_major, p_dev_info->fw_minor, p_dev_info->fw_rev,
1009 p_dev_info->fw_eng,
1010 (p_dev_info->mfw_rev & QED_MFW_VERSION_3_MASK) >>
1011 QED_MFW_VERSION_3_OFFSET,
1012 (p_dev_info->mfw_rev & QED_MFW_VERSION_2_MASK) >>
1013 QED_MFW_VERSION_2_OFFSET,
1014 (p_dev_info->mfw_rev & QED_MFW_VERSION_1_MASK) >>
1015 QED_MFW_VERSION_1_OFFSET,
1016 (p_dev_info->mfw_rev & QED_MFW_VERSION_0_MASK) >>
1017 QED_MFW_VERSION_0_OFFSET);
1018
1019 left_size = QEDE_FW_VER_STR_SIZE - strlen(buf);
1020 if (p_dev_info->mbi_version && left_size)
1021 snprintf(buf + strlen(buf), left_size,
1022 " [MBI %d.%d.%d]",
1023 (p_dev_info->mbi_version & QED_MBI_VERSION_2_MASK) >>
1024 QED_MBI_VERSION_2_OFFSET,
1025 (p_dev_info->mbi_version & QED_MBI_VERSION_1_MASK) >>
1026 QED_MBI_VERSION_1_OFFSET,
1027 (p_dev_info->mbi_version & QED_MBI_VERSION_0_MASK) >>
1028 QED_MBI_VERSION_0_OFFSET);
1029
1030 pr_info("qede %02x:%02x.%02x: %s [%s]\n", edev->pdev->bus->number,
1031 PCI_SLOT(edev->pdev->devfn), PCI_FUNC(edev->pdev->devfn),
1032 buf, edev->ndev->name);
1033}
1034
e712d52b
YM		 1035enum qede_probe_mode {
1036 QEDE_PROBE_NORMAL,
1037};
1038
1039static int __qede_probe(struct pci_dev *pdev, u32 dp_module, u8 dp_level,
1408cc1f 1040 bool is_vf, enum qede_probe_mode mode)
e712d52b 1041{
1408cc1f 1042 struct qed_probe_params probe_params;
1a635e48 1043 struct qed_slowpath_params sp_params;
e712d52b
YM		 1044 struct qed_dev_eth_info dev_info;
1045 struct qede_dev *edev;
1046 struct qed_dev *cdev;
1047 int rc;
1048
1049 if (unlikely(dp_level & QED_LEVEL_INFO))
1050 pr_notice("Starting qede probe\n");
1051
1408cc1f
YM		 1052 memset(&probe_params, 0, sizeof(probe_params));
1053 probe_params.protocol = QED_PROTOCOL_ETH;
1054 probe_params.dp_module = dp_module;
1055 probe_params.dp_level = dp_level;
1056 probe_params.is_vf = is_vf;
1057 cdev = qed_ops->common->probe(pdev, &probe_params);
e712d52b
YM		 1058 if (!cdev) {
1059 rc = -ENODEV;
1060 goto err0;
1061 }
1062
1063 qede_update_pf_params(cdev);
1064
1065 /* Start the Slowpath-process */
1a635e48
YM		 1066 memset(&sp_params, 0, sizeof(sp_params));
1067 sp_params.int_mode = QED_INT_MODE_MSIX;
1068 sp_params.drv_major = QEDE_MAJOR_VERSION;
1069 sp_params.drv_minor = QEDE_MINOR_VERSION;
1070 sp_params.drv_rev = QEDE_REVISION_VERSION;
1071 sp_params.drv_eng = QEDE_ENGINEERING_VERSION;
1072 strlcpy(sp_params.name, "qede LAN", QED_DRV_VER_STR_SIZE);
1073 rc = qed_ops->common->slowpath_start(cdev, &sp_params);
e712d52b
YM		 1074 if (rc) {
1075 pr_notice("Cannot start slowpath\n");
1076 goto err1;
1077 }
1078
1079 /* Learn information crucial for qede to progress */
1080 rc = qed_ops->fill_dev_info(cdev, &dev_info);
1081 if (rc)
1082 goto err2;
1083
1084 edev = qede_alloc_etherdev(cdev, pdev, &dev_info, dp_module,
1085 dp_level);
1086 if (!edev) {
1087 rc = -ENOMEM;
1088 goto err2;
1089 }
1090
fefb0202 1091 if (is_vf)
149d3775 1092 set_bit(QEDE_FLAGS_IS_VF, &edev->flags);
fefb0202 1093
e712d52b
YM		 1094 qede_init_ndev(edev);
1095
bbfcd1e8 1096 rc = qede_rdma_dev_add(edev);
cee9fbd8
RA		 1097 if (rc)
1098 goto err3;
1099
3f2176dd 1100 /* Prepare the lock prior to the registration of the netdev,
0e0b80a9
MY		 1101 * as once it's registered we might reach flows requiring it
1102 * [it's even possible to reach a flow needing it directly
1103 * from there, although it's unlikely].
1104 */
1105 INIT_DELAYED_WORK(&edev->sp_task, qede_sp_task);
1106 mutex_init(&edev->qede_lock);
2950219d
YM		 1107 rc = register_netdev(edev->ndev);
1108 if (rc) {
1109 DP_NOTICE(edev, "Cannot register net-device\n");
cee9fbd8 1110 goto err4;
2950219d
YM		 1111 }
1112
712c3cbf 1113 edev->ops->common->set_name(cdev, edev->ndev->name);
e712d52b 1114
4c55215c 1115 /* PTP not supported on VFs */
03574497 1116 if (!is_vf)
1117 qede_ptp_enable(edev, true);
4c55215c 1118
a2ec6172
SK		 1119 edev->ops->register_ops(cdev, &qede_ll_ops, edev);
1120
489e45ae 1121#ifdef CONFIG_DCB
5fe118c9
SRK		 1122 if (!IS_VF(edev))
1123 qede_set_dcbnl_ops(edev->ndev);
489e45ae
SRK		 1124#endif
1125
3d789994 1126 edev->rx_copybreak = QEDE_RX_HDR_SIZE;
0d8e0aa0 1127
6bc9f234 1128 qede_log_probe(edev);
e712d52b
YM		 1129 return 0;
1130
cee9fbd8 1131err4:
bbfcd1e8 1132 qede_rdma_dev_remove(edev);
2950219d
YM		 1133err3:
1134 free_netdev(edev->ndev);
e712d52b
YM		 1135err2:
1136 qed_ops->common->slowpath_stop(cdev);
1137err1:
1138 qed_ops->common->remove(cdev);
1139err0:
1140 return rc;
1141}
1142
1143static int qede_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1144{
fefb0202 1145 bool is_vf = false;
e712d52b
YM		 1146 u32 dp_module = 0;
1147 u8 dp_level = 0;
1148
fefb0202
YM		 1149 switch ((enum qede_pci_private)id->driver_data) {
1150 case QEDE_PRIVATE_VF:
1151 if (debug & QED_LOG_VERBOSE_MASK)
1152 dev_err(&pdev->dev, "Probing a VF\n");
1153 is_vf = true;
1154 break;
1155 default:
1156 if (debug & QED_LOG_VERBOSE_MASK)
1157 dev_err(&pdev->dev, "Probing a PF\n");
1158 }
1159
e712d52b
YM		 1160 qede_config_debug(debug, &dp_module, &dp_level);
1161
fefb0202 1162 return __qede_probe(pdev, dp_module, dp_level, is_vf,
e712d52b
YM		 1163 QEDE_PROBE_NORMAL);
1164}
1165
1166enum qede_remove_mode {
1167 QEDE_REMOVE_NORMAL,
1168};
1169
1170static void __qede_remove(struct pci_dev *pdev, enum qede_remove_mode mode)
1171{
1172 struct net_device *ndev = pci_get_drvdata(pdev);
1173 struct qede_dev *edev = netdev_priv(ndev);
1174 struct qed_dev *cdev = edev->cdev;
1175
1176 DP_INFO(edev, "Starting qede_remove\n");
1177
91dfd02b 1178 qede_rdma_dev_remove(edev);
2950219d 1179 unregister_netdev(ndev);
e4917d46 1180 cancel_delayed_work_sync(&edev->sp_task);
2950219d 1181
03574497 1182 qede_ptp_disable(edev);
4c55215c 1183
e712d52b
YM		 1184 edev->ops->common->set_power_state(cdev, PCI_D0);
1185
1186 pci_set_drvdata(pdev, NULL);
1187
e712d52b
YM		 1188 /* Use global ops since we've freed edev */
1189 qed_ops->common->slowpath_stop(cdev);
14d39648
MY		 1190 if (system_state == SYSTEM_POWER_OFF)
1191 return;
e712d52b
YM		 1192 qed_ops->common->remove(cdev);
1193
885185df
MY		 1194 /* Since this can happen out-of-sync with other flows,
1195 * don't release the netdevice until after slowpath stop
1196 * has been called to guarantee various other contexts
1197 * [e.g., QED register callbacks] won't break anything when
1198 * accessing the netdevice.
1199 */
1200 free_netdev(ndev);
1201
525ef5c0 1202 dev_info(&pdev->dev, "Ending qede_remove successfully\n");
e712d52b
YM		 1203}
1204
1205static void qede_remove(struct pci_dev *pdev)
1206{
1207 __qede_remove(pdev, QEDE_REMOVE_NORMAL);
1208}
2950219d 1209
14d39648
MY		 1210static void qede_shutdown(struct pci_dev *pdev)
1211{
1212 __qede_remove(pdev, QEDE_REMOVE_NORMAL);
1213}
1214
2950219d
YM		 1215/* -------------------------------------------------------------------------
1216 * START OF LOAD / UNLOAD
1217 * -------------------------------------------------------------------------
1218 */
1219
1220static int qede_set_num_queues(struct qede_dev *edev)
1221{
1222 int rc;
1223 u16 rss_num;
1224
1225 /* Setup queues according to possible resources*/
9a4d7e86
SRK		 1226 if (edev->req_queues)
1227 rss_num = edev->req_queues;
8edf049d
SK		 1228 else
1229 rss_num = netif_get_num_default_rss_queues() *
1230 edev->dev_info.common.num_hwfns;
2950219d
YM		 1231
1232 rss_num = min_t(u16, QEDE_MAX_RSS_CNT(edev), rss_num);
1233
1234 rc = edev->ops->common->set_fp_int(edev->cdev, rss_num);
1235 if (rc > 0) {
1236 /* Managed to request interrupts for our queues */
9a4d7e86 1237 edev->num_queues = rc;
2950219d 1238 DP_INFO(edev, "Managed %d [of %d] RSS queues\n",
9a4d7e86 1239 QEDE_QUEUE_CNT(edev), rss_num);
2950219d
YM		 1240 rc = 0;
1241 }
9a4d7e86
SRK		 1242
1243 edev->fp_num_tx = edev->req_num_tx;
1244 edev->fp_num_rx = edev->req_num_rx;
1245
2950219d
YM		 1246 return rc;
1247}
1248
71851ea5
SRK		 1249static void qede_free_mem_sb(struct qede_dev *edev, struct qed_sb_info *sb_info,
1250 u16 sb_id)
2950219d 1251{
71851ea5
SRK		 1252 if (sb_info->sb_virt) {
1253 edev->ops->common->sb_release(edev->cdev, sb_info, sb_id);
2950219d
YM		 1254 dma_free_coherent(&edev->pdev->dev, sizeof(*sb_info->sb_virt),
1255 (void *)sb_info->sb_virt, sb_info->sb_phys);
71851ea5
SRK		 1256 memset(sb_info, 0, sizeof(*sb_info));
1257 }
2950219d
YM		 1258}
1259
1260/* This function allocates fast-path status block memory */
1261static int qede_alloc_mem_sb(struct qede_dev *edev,
1a635e48 1262 struct qed_sb_info *sb_info, u16 sb_id)
2950219d 1263{
21dd79e8 1264 struct status_block_e4 *sb_virt;
2950219d
YM		 1265 dma_addr_t sb_phys;
1266 int rc;
1267
1268 sb_virt = dma_alloc_coherent(&edev->pdev->dev,
1a635e48 1269 sizeof(*sb_virt), &sb_phys, GFP_KERNEL);
2950219d
YM		 1270 if (!sb_virt) {
1271 DP_ERR(edev, "Status block allocation failed\n");
1272 return -ENOMEM;
1273 }
1274
1275 rc = edev->ops->common->sb_init(edev->cdev, sb_info,
1276 sb_virt, sb_phys, sb_id,
1277 QED_SB_TYPE_L2_QUEUE);
1278 if (rc) {
1279 DP_ERR(edev, "Status block initialization failed\n");
1280 dma_free_coherent(&edev->pdev->dev, sizeof(*sb_virt),
1281 sb_virt, sb_phys);
1282 return rc;
1283 }
1284
1285 return 0;
1286}
1287
1288static void qede_free_rx_buffers(struct qede_dev *edev,
1289 struct qede_rx_queue *rxq)
1290{
1291 u16 i;
1292
1293 for (i = rxq->sw_rx_cons; i != rxq->sw_rx_prod; i++) {
1294 struct sw_rx_data *rx_buf;
fc48b7a6 1295 struct page *data;
2950219d
YM		 1296
1297 rx_buf = &rxq->sw_rx_ring[i & NUM_RX_BDS_MAX];
1298 data = rx_buf->data;
1299
fc48b7a6 1300 dma_unmap_page(&edev->pdev->dev,
cb6aeb07 1301 rx_buf->mapping, PAGE_SIZE, rxq->data_direction);
2950219d
YM		 1302
1303 rx_buf->data = NULL;
fc48b7a6 1304 __free_page(data);
2950219d
YM		 1305 }
1306}
1307
1a635e48 1308static void qede_free_mem_rxq(struct qede_dev *edev, struct qede_rx_queue *rxq)
2950219d
YM		 1309{
1310 /* Free rx buffers */
1311 qede_free_rx_buffers(edev, rxq);
1312
1313 /* Free the parallel SW ring */
1314 kfree(rxq->sw_rx_ring);
1315
1316 /* Free the real RQ ring used by FW */
1317 edev->ops->common->chain_free(edev->cdev, &rxq->rx_bd_ring);
1318 edev->ops->common->chain_free(edev->cdev, &rxq->rx_comp_ring);
1319}
1320
8a863397 1321static void qede_set_tpa_param(struct qede_rx_queue *rxq)
55482edc 1322{
55482edc
MC		 1323 int i;
1324
55482edc
MC		 1325 for (i = 0; i < ETH_TPA_MAX_AGGS_NUM; i++) {
1326 struct qede_agg_info *tpa_info = &rxq->tpa_info[i];
55482edc 1327
01e23015 1328 tpa_info->state = QEDE_AGG_STATE_NONE;
55482edc 1329 }
55482edc
MC		 1330}
1331
2950219d 1332/* This function allocates all memory needed per Rx queue */
1a635e48 1333static int qede_alloc_mem_rxq(struct qede_dev *edev, struct qede_rx_queue *rxq)
2950219d 1334{
f86af2df 1335 int i, rc, size;
2950219d
YM		 1336
1337 rxq->num_rx_buffers = edev->q_num_rx_buffers;
1338
1a635e48 1339 rxq->rx_buf_size = NET_IP_ALIGN + ETH_OVERHEAD + edev->ndev->mtu;
8a863397
MC		 1340
1341 rxq->rx_headroom = edev->xdp_prog ? XDP_PACKET_HEADROOM : NET_SKB_PAD;
1342 size = rxq->rx_headroom +
1343 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
1a635e48 1344
15ed8a47 1345 /* Make sure that the headroom and payload fit in a single page */
8a863397
MC		 1346 if (rxq->rx_buf_size + size > PAGE_SIZE)
1347 rxq->rx_buf_size = PAGE_SIZE - size;
fc48b7a6 1348
8a863397 1349 /* Segment size to spilt a page in multiple equal parts ,
496e0517
MY		 1350 * unless XDP is used in which case we'd use the entire page.
1351 */
8a863397
MC		 1352 if (!edev->xdp_prog) {
1353 size = size + rxq->rx_buf_size;
1354 rxq->rx_buf_seg_size = roundup_pow_of_two(size);
1355 } else {
496e0517 1356 rxq->rx_buf_seg_size = PAGE_SIZE;
8a863397 1357 }
2950219d
YM		 1358
1359 /* Allocate the parallel driver ring for Rx buffers */
fc48b7a6 1360 size = sizeof(*rxq->sw_rx_ring) * RX_RING_SIZE;
2950219d
YM		 1361 rxq->sw_rx_ring = kzalloc(size, GFP_KERNEL);
1362 if (!rxq->sw_rx_ring) {
1363 DP_ERR(edev, "Rx buffers ring allocation failed\n");
f86af2df 1364 rc = -ENOMEM;
2950219d
YM		 1365 goto err;
1366 }
1367
1368 /* Allocate FW Rx ring */
1369 rc = edev->ops->common->chain_alloc(edev->cdev,
1370 QED_CHAIN_USE_TO_CONSUME_PRODUCE,
1371 QED_CHAIN_MODE_NEXT_PTR,
a91eb52a 1372 QED_CHAIN_CNT_TYPE_U16,
fc48b7a6 1373 RX_RING_SIZE,
2950219d 1374 sizeof(struct eth_rx_bd),
1a4a6975 1375 &rxq->rx_bd_ring, NULL);
2950219d
YM		 1376 if (rc)
1377 goto err;
1378
1379 /* Allocate FW completion ring */
1380 rc = edev->ops->common->chain_alloc(edev->cdev,
1381 QED_CHAIN_USE_TO_CONSUME,
1382 QED_CHAIN_MODE_PBL,
a91eb52a 1383 QED_CHAIN_CNT_TYPE_U16,
fc48b7a6 1384 RX_RING_SIZE,
2950219d 1385 sizeof(union eth_rx_cqe),
1a4a6975 1386 &rxq->rx_comp_ring, NULL);
2950219d
YM		 1387 if (rc)
1388 goto err;
1389
1390 /* Allocate buffers for the Rx ring */
e3eef7ee 1391 rxq->filled_buffers = 0;
2950219d 1392 for (i = 0; i < rxq->num_rx_buffers; i++) {
e3eef7ee 1393 rc = qede_alloc_rx_buffer(rxq, false);
f86af2df
MC		 1394 if (rc) {
1395 DP_ERR(edev,
1396 "Rx buffers allocation failed at index %d\n", i);
1397 goto err;
1398 }
2950219d
YM		 1399 }
1400
8a863397
MC		 1401 if (!edev->gro_disable)
1402 qede_set_tpa_param(rxq);
2950219d 1403err:
f86af2df 1404 return rc;
2950219d
YM		 1405}
1406
1a635e48 1407static void qede_free_mem_txq(struct qede_dev *edev, struct qede_tx_queue *txq)
2950219d
YM		 1408{
1409 /* Free the parallel SW ring */
cb6aeb07 1410 if (txq->is_xdp)
89e1afc4 1411 kfree(txq->sw_tx_ring.xdp);
cb6aeb07
MY		 1412 else
1413 kfree(txq->sw_tx_ring.skbs);
2950219d
YM		 1414
1415 /* Free the real RQ ring used by FW */
1416 edev->ops->common->chain_free(edev->cdev, &txq->tx_pbl);
1417}
1418
1419/* This function allocates all memory needed per Tx queue */
1a635e48 1420static int qede_alloc_mem_txq(struct qede_dev *edev, struct qede_tx_queue *txq)
2950219d 1421{
2950219d 1422 union eth_tx_bd_types *p_virt;
cb6aeb07 1423 int size, rc;
2950219d
YM		 1424
1425 txq->num_tx_buffers = edev->q_num_tx_buffers;
1426
1427 /* Allocate the parallel driver ring for Tx buffers */
cb6aeb07 1428 if (txq->is_xdp) {
5a052d62 1429 size = sizeof(*txq->sw_tx_ring.xdp) * txq->num_tx_buffers;
89e1afc4
MY		 1430 txq->sw_tx_ring.xdp = kzalloc(size, GFP_KERNEL);
1431 if (!txq->sw_tx_ring.xdp)
cb6aeb07
MY		 1432 goto err;
1433 } else {
5a052d62 1434 size = sizeof(*txq->sw_tx_ring.skbs) * txq->num_tx_buffers;
cb6aeb07
MY		 1435 txq->sw_tx_ring.skbs = kzalloc(size, GFP_KERNEL);
1436 if (!txq->sw_tx_ring.skbs)
1437 goto err;
2950219d
YM		 1438 }
1439
1440 rc = edev->ops->common->chain_alloc(edev->cdev,
1441 QED_CHAIN_USE_TO_CONSUME_PRODUCE,
1442 QED_CHAIN_MODE_PBL,
a91eb52a 1443 QED_CHAIN_CNT_TYPE_U16,
5a052d62 1444 txq->num_tx_buffers,
1a4a6975
MY		 1445 sizeof(*p_virt),
1446 &txq->tx_pbl, NULL);
2950219d
YM		 1447 if (rc)
1448 goto err;
1449
1450 return 0;
1451
1452err:
1453 qede_free_mem_txq(edev, txq);
1454 return -ENOMEM;
1455}
1456
1457/* This function frees all memory of a single fp */
1a635e48 1458static void qede_free_mem_fp(struct qede_dev *edev, struct qede_fastpath *fp)
2950219d 1459{
71851ea5 1460 qede_free_mem_sb(edev, fp->sb_info, fp->id);
2950219d 1461
9a4d7e86
SRK		 1462 if (fp->type & QEDE_FASTPATH_RX)
1463 qede_free_mem_rxq(edev, fp->rxq);
2950219d 1464
92c43eb4
SRK		 1465 if (fp->type & QEDE_FASTPATH_XDP)
1466 qede_free_mem_txq(edev, fp->xdp_tx);
1467
5e7baf0f
MC		 1468 if (fp->type & QEDE_FASTPATH_TX) {
1469 int cos;
1470
1471 for_each_cos_in_txq(edev, cos)
1472 qede_free_mem_txq(edev, &fp->txq[cos]);
1473 }
2950219d
YM		 1474}
1475
1476/* This function allocates all memory needed for a single fp (i.e. an entity
9a4d7e86 1477 * which contains status block, one rx queue and/or multiple per-TC tx queues.
2950219d 1478 */
1a635e48 1479static int qede_alloc_mem_fp(struct qede_dev *edev, struct qede_fastpath *fp)
2950219d 1480{
cb6aeb07 1481 int rc = 0;
2950219d 1482
9a4d7e86 1483 rc = qede_alloc_mem_sb(edev, fp->sb_info, fp->id);
2950219d 1484 if (rc)
cb6aeb07 1485 goto out;
2950219d 1486
9a4d7e86
SRK		 1487 if (fp->type & QEDE_FASTPATH_RX) {
1488 rc = qede_alloc_mem_rxq(edev, fp->rxq);
2950219d 1489 if (rc)
cb6aeb07
MY		 1490 goto out;
1491 }
1492
1493 if (fp->type & QEDE_FASTPATH_XDP) {
1494 rc = qede_alloc_mem_txq(edev, fp->xdp_tx);
1495 if (rc)
1496 goto out;
2950219d
YM		 1497 }
1498
9a4d7e86 1499 if (fp->type & QEDE_FASTPATH_TX) {
5e7baf0f
MC		 1500 int cos;
1501
1502 for_each_cos_in_txq(edev, cos) {
1503 rc = qede_alloc_mem_txq(edev, &fp->txq[cos]);
1504 if (rc)
1505 goto out;
1506 }
9a4d7e86
SRK		 1507 }
1508
cb6aeb07 1509out:
f86af2df 1510 return rc;
2950219d
YM		 1511}
1512
1513static void qede_free_mem_load(struct qede_dev *edev)
1514{
1515 int i;
1516
9a4d7e86 1517 for_each_queue(i) {
2950219d
YM		 1518 struct qede_fastpath *fp = &edev->fp_array[i];
1519
1520 qede_free_mem_fp(edev, fp);
1521 }
1522}
1523
1524/* This function allocates all qede memory at NIC load. */
1525static int qede_alloc_mem_load(struct qede_dev *edev)
1526{
9a4d7e86 1527 int rc = 0, queue_id;
2950219d 1528
9a4d7e86
SRK		 1529 for (queue_id = 0; queue_id < QEDE_QUEUE_CNT(edev); queue_id++) {
1530 struct qede_fastpath *fp = &edev->fp_array[queue_id];
2950219d
YM		 1531
1532 rc = qede_alloc_mem_fp(edev, fp);
f86af2df 1533 if (rc) {
2950219d 1534 DP_ERR(edev,
f86af2df 1535 "Failed to allocate memory for fastpath - rss id = %d\n",
9a4d7e86 1536 queue_id);
f86af2df
MC		 1537 qede_free_mem_load(edev);
1538 return rc;
2950219d 1539 }
2950219d
YM		 1540 }
1541
1542 return 0;
1543}
1544
1545/* This function inits fp content and resets the SB, RXQ and TXQ structures */
1546static void qede_init_fp(struct qede_dev *edev)
1547{
80439a17 1548 int queue_id, rxq_index = 0, txq_index = 0;
2950219d
YM		 1549 struct qede_fastpath *fp;
1550
9a4d7e86
SRK		 1551 for_each_queue(queue_id) {
1552 fp = &edev->fp_array[queue_id];
2950219d
YM		 1553
1554 fp->edev = edev;
9a4d7e86 1555 fp->id = queue_id;
2950219d 1556
cb6aeb07
MY		 1557 if (fp->type & QEDE_FASTPATH_XDP) {
1558 fp->xdp_tx->index = QEDE_TXQ_IDX_TO_XDP(edev,
1559 rxq_index);
1560 fp->xdp_tx->is_xdp = 1;
1561 }
2950219d 1562
9a4d7e86 1563 if (fp->type & QEDE_FASTPATH_RX) {
9a4d7e86 1564 fp->rxq->rxq_id = rxq_index++;
cb6aeb07
MY		 1565
1566 /* Determine how to map buffers for this queue */
1567 if (fp->type & QEDE_FASTPATH_XDP)
1568 fp->rxq->data_direction = DMA_BIDIRECTIONAL;
1569 else
1570 fp->rxq->data_direction = DMA_FROM_DEVICE;
9eb22357 1571 fp->rxq->dev = &edev->pdev->dev;
c0124f32
JDB		 1572
1573 /* Driver have no error path from here */
1574 WARN_ON(xdp_rxq_info_reg(&fp->rxq->xdp_rxq, edev->ndev,
1575 fp->rxq->rxq_id) < 0);
9a4d7e86 1576 }
2950219d 1577
9a4d7e86 1578 if (fp->type & QEDE_FASTPATH_TX) {
5e7baf0f
MC		 1579 int cos;
1580
1581 for_each_cos_in_txq(edev, cos) {
1582 struct qede_tx_queue *txq = &fp->txq[cos];
1583 u16 ndev_tx_id;
1584
1585 txq->cos = cos;
1586 txq->index = txq_index;
1587 ndev_tx_id = QEDE_TXQ_TO_NDEV_TXQ_ID(edev, txq);
1588 txq->ndev_txq_id = ndev_tx_id;
1589
1590 if (edev->dev_info.is_legacy)
1591 txq->is_legacy = 1;
1592 txq->dev = &edev->pdev->dev;
1593 }
1594
1595 txq_index++;
2950219d
YM		 1596 }
1597
1598 snprintf(fp->name, sizeof(fp->name), "%s-fp-%d",
9a4d7e86 1599 edev->ndev->name, queue_id);
2950219d 1600 }
55482edc 1601
18c602de 1602 edev->gro_disable = !(edev->ndev->features & NETIF_F_GRO_HW);
2950219d
YM		 1603}
1604
1605static int qede_set_real_num_queues(struct qede_dev *edev)
1606{
1607 int rc = 0;
1608
5e7baf0f
MC		 1609 rc = netif_set_real_num_tx_queues(edev->ndev,
1610 QEDE_TSS_COUNT(edev) *
1611 edev->dev_info.num_tc);
2950219d
YM		 1612 if (rc) {
1613 DP_NOTICE(edev, "Failed to set real number of Tx queues\n");
1614 return rc;
1615 }
9a4d7e86
SRK		 1616
1617 rc = netif_set_real_num_rx_queues(edev->ndev, QEDE_RSS_COUNT(edev));
2950219d
YM		 1618 if (rc) {
1619 DP_NOTICE(edev, "Failed to set real number of Rx queues\n");
1620 return rc;
1621 }
1622
1623 return 0;
1624}
1625
1626static void qede_napi_disable_remove(struct qede_dev *edev)
1627{
1628 int i;
1629
9a4d7e86 1630 for_each_queue(i) {
2950219d
YM		 1631 napi_disable(&edev->fp_array[i].napi);
1632
1633 netif_napi_del(&edev->fp_array[i].napi);
1634 }
1635}
1636
1637static void qede_napi_add_enable(struct qede_dev *edev)
1638{
1639 int i;
1640
1641 /* Add NAPI objects */
9a4d7e86 1642 for_each_queue(i) {
2950219d
YM		 1643 netif_napi_add(edev->ndev, &edev->fp_array[i].napi,
1644 qede_poll, NAPI_POLL_WEIGHT);
1645 napi_enable(&edev->fp_array[i].napi);
1646 }
1647}
1648
1649static void qede_sync_free_irqs(struct qede_dev *edev)
1650{
1651 int i;
1652
1653 for (i = 0; i < edev->int_info.used_cnt; i++) {
1654 if (edev->int_info.msix_cnt) {
1655 synchronize_irq(edev->int_info.msix[i].vector);
1656 free_irq(edev->int_info.msix[i].vector,
1657 &edev->fp_array[i]);
1658 } else {
1659 edev->ops->common->simd_handler_clean(edev->cdev, i);
1660 }
1661 }
1662
1663 edev->int_info.used_cnt = 0;
1664}
1665
1666static int qede_req_msix_irqs(struct qede_dev *edev)
1667{
1668 int i, rc;
1669
1670 /* Sanitize number of interrupts == number of prepared RSS queues */
9a4d7e86 1671 if (QEDE_QUEUE_CNT(edev) > edev->int_info.msix_cnt) {
2950219d
YM		 1672 DP_ERR(edev,
1673 "Interrupt mismatch: %d RSS queues > %d MSI-x vectors\n",
9a4d7e86 1674 QEDE_QUEUE_CNT(edev), edev->int_info.msix_cnt);
2950219d
YM		 1675 return -EINVAL;
1676 }
1677
9a4d7e86 1678 for (i = 0; i < QEDE_QUEUE_CNT(edev); i++) {
e4917d46
CM		 1679#ifdef CONFIG_RFS_ACCEL
1680 struct qede_fastpath *fp = &edev->fp_array[i];
1681
1682 if (edev->ndev->rx_cpu_rmap && (fp->type & QEDE_FASTPATH_RX)) {
1683 rc = irq_cpu_rmap_add(edev->ndev->rx_cpu_rmap,
1684 edev->int_info.msix[i].vector);
1685 if (rc) {
1686 DP_ERR(edev, "Failed to add CPU rmap\n");
1687 qede_free_arfs(edev);
1688 }
1689 }
1690#endif
2950219d
YM		 1691 rc = request_irq(edev->int_info.msix[i].vector,
1692 qede_msix_fp_int, 0, edev->fp_array[i].name,
1693 &edev->fp_array[i]);
1694 if (rc) {
1695 DP_ERR(edev, "Request fp %d irq failed\n", i);
1696 qede_sync_free_irqs(edev);
1697 return rc;
1698 }
1699 DP_VERBOSE(edev, NETIF_MSG_INTR,
1700 "Requested fp irq for %s [entry %d]. Cookie is at %p\n",
1701 edev->fp_array[i].name, i,
1702 &edev->fp_array[i]);
1703 edev->int_info.used_cnt++;
1704 }
1705
1706 return 0;
1707}
1708
1709static void qede_simd_fp_handler(void *cookie)
1710{
1711 struct qede_fastpath *fp = (struct qede_fastpath *)cookie;
1712
1713 napi_schedule_irqoff(&fp->napi);
1714}
1715
1716static int qede_setup_irqs(struct qede_dev *edev)
1717{
1718 int i, rc = 0;
1719
1720 /* Learn Interrupt configuration */
1721 rc = edev->ops->common->get_fp_int(edev->cdev, &edev->int_info);
1722 if (rc)
1723 return rc;
1724
1725 if (edev->int_info.msix_cnt) {
1726 rc = qede_req_msix_irqs(edev);
1727 if (rc)
1728 return rc;
1729 edev->ndev->irq = edev->int_info.msix[0].vector;
1730 } else {
1731 const struct qed_common_ops *ops;
1732
1733 /* qed should learn receive the RSS ids and callbacks */
1734 ops = edev->ops->common;
9a4d7e86 1735 for (i = 0; i < QEDE_QUEUE_CNT(edev); i++)
2950219d
YM		 1736 ops->simd_handler_config(edev->cdev,
1737 &edev->fp_array[i], i,
1738 qede_simd_fp_handler);
9a4d7e86 1739 edev->int_info.used_cnt = QEDE_QUEUE_CNT(edev);
2950219d
YM		 1740 }
1741 return 0;
1742}
1743
1744static int qede_drain_txq(struct qede_dev *edev,
1a635e48 1745 struct qede_tx_queue *txq, bool allow_drain)
2950219d
YM		 1746{
1747 int rc, cnt = 1000;
1748
1749 while (txq->sw_tx_cons != txq->sw_tx_prod) {
1750 if (!cnt) {
1751 if (allow_drain) {
1752 DP_NOTICE(edev,
1753 "Tx queue[%d] is stuck, requesting MCP to drain\n",
1754 txq->index);
1755 rc = edev->ops->common->drain(edev->cdev);
1756 if (rc)
1757 return rc;
1758 return qede_drain_txq(edev, txq, false);
1759 }
1760 DP_NOTICE(edev,
1761 "Timeout waiting for tx queue[%d]: PROD=%d, CONS=%d\n",
1762 txq->index, txq->sw_tx_prod,
1763 txq->sw_tx_cons);
1764 return -ENODEV;
1765 }
1766 cnt--;
1767 usleep_range(1000, 2000);
1768 barrier();
1769 }
1770
1771 /* FW finished processing, wait for HW to transmit all tx packets */
1772 usleep_range(1000, 2000);
1773
1774 return 0;
1775}
1776
3da7a37a
MY		 1777static int qede_stop_txq(struct qede_dev *edev,
1778 struct qede_tx_queue *txq, int rss_id)
1779{
bd4db888
AE		 1780 /* delete doorbell from doorbell recovery mechanism */
1781 edev->ops->common->db_recovery_del(edev->cdev, txq->doorbell_addr,
1782 &txq->tx_db);
1783
3da7a37a
MY		 1784 return edev->ops->q_tx_stop(edev->cdev, rss_id, txq->handle);
1785}
1786
2950219d
YM		 1787static int qede_stop_queues(struct qede_dev *edev)
1788{
f29ffdb6 1789 struct qed_update_vport_params *vport_update_params;
2950219d 1790 struct qed_dev *cdev = edev->cdev;
80439a17
MY		 1791 struct qede_fastpath *fp;
1792 int rc, i;
2950219d
YM		 1793
1794 /* Disable the vport */
f29ffdb6
MY		 1795 vport_update_params = vzalloc(sizeof(*vport_update_params));
1796 if (!vport_update_params)
1797 return -ENOMEM;
1798
1799 vport_update_params->vport_id = 0;
1800 vport_update_params->update_vport_active_flg = 1;
1801 vport_update_params->vport_active_flg = 0;
1802 vport_update_params->update_rss_flg = 0;
1803
1804 rc = edev->ops->vport_update(cdev, vport_update_params);
1805 vfree(vport_update_params);
2950219d 1806
2950219d
YM		 1807 if (rc) {
1808 DP_ERR(edev, "Failed to update vport\n");
1809 return rc;
1810 }
1811
1812 /* Flush Tx queues. If needed, request drain from MCP */
9a4d7e86 1813 for_each_queue(i) {
80439a17 1814 fp = &edev->fp_array[i];
2950219d 1815
9a4d7e86 1816 if (fp->type & QEDE_FASTPATH_TX) {
5e7baf0f
MC		 1817 int cos;
1818
1819 for_each_cos_in_txq(edev, cos) {
1820 rc = qede_drain_txq(edev, &fp->txq[cos], true);
1821 if (rc)
1822 return rc;
1823 }
2950219d 1824 }
cb6aeb07
MY		 1825
1826 if (fp->type & QEDE_FASTPATH_XDP) {
1827 rc = qede_drain_txq(edev, fp->xdp_tx, true);
1828 if (rc)
1829 return rc;
1830 }
2950219d
YM		 1831 }
1832
9a4d7e86
SRK		 1833 /* Stop all Queues in reverse order */
1834 for (i = QEDE_QUEUE_CNT(edev) - 1; i >= 0; i--) {
80439a17
MY		 1835 fp = &edev->fp_array[i];
1836
9a4d7e86 1837 /* Stop the Tx Queue(s) */
80439a17 1838 if (fp->type & QEDE_FASTPATH_TX) {
5e7baf0f
MC		 1839 int cos;
1840
1841 for_each_cos_in_txq(edev, cos) {
1842 rc = qede_stop_txq(edev, &fp->txq[cos], i);
1843 if (rc)
1844 return rc;
1845 }
2950219d
YM		 1846 }
1847
9a4d7e86 1848 /* Stop the Rx Queue */
80439a17 1849 if (fp->type & QEDE_FASTPATH_RX) {
3da7a37a 1850 rc = edev->ops->q_rx_stop(cdev, i, fp->rxq->handle);
9a4d7e86
SRK		 1851 if (rc) {
1852 DP_ERR(edev, "Failed to stop RXQ #%d\n", i);
1853 return rc;
1854 }
2950219d 1855 }
496e0517 1856
cb6aeb07
MY		 1857 /* Stop the XDP forwarding queue */
1858 if (fp->type & QEDE_FASTPATH_XDP) {
1859 rc = qede_stop_txq(edev, fp->xdp_tx, i);
1860 if (rc)
1861 return rc;
1862
496e0517 1863 bpf_prog_put(fp->rxq->xdp_prog);
cb6aeb07 1864 }
2950219d
YM		 1865 }
1866
1867 /* Stop the vport */
1868 rc = edev->ops->vport_stop(cdev, 0);
1869 if (rc)
1870 DP_ERR(edev, "Failed to stop VPORT\n");
1871
1872 return rc;
1873}
1874
3da7a37a
MY		 1875static int qede_start_txq(struct qede_dev *edev,
1876 struct qede_fastpath *fp,
1877 struct qede_tx_queue *txq, u8 rss_id, u16 sb_idx)
1878{
1879 dma_addr_t phys_table = qed_chain_get_pbl_phys(&txq->tx_pbl);
1880 u32 page_cnt = qed_chain_get_page_cnt(&txq->tx_pbl);
1881 struct qed_queue_start_common_params params;
1882 struct qed_txq_start_ret_params ret_params;
1883 int rc;
1884
1885 memset(&params, 0, sizeof(params));
1886 memset(&ret_params, 0, sizeof(ret_params));
1887
cb6aeb07
MY		 1888 /* Let the XDP queue share the queue-zone with one of the regular txq.
1889 * We don't really care about its coalescing.
1890 */
1891 if (txq->is_xdp)
1892 params.queue_id = QEDE_TXQ_XDP_TO_IDX(edev, txq);
1893 else
1894 params.queue_id = txq->index;
1895
f604b17d 1896 params.p_sb = fp->sb_info;
3da7a37a 1897 params.sb_idx = sb_idx;
5e7baf0f 1898 params.tc = txq->cos;
3da7a37a
MY		 1899
1900 rc = edev->ops->q_tx_start(edev->cdev, rss_id, &params, phys_table,
1901 page_cnt, &ret_params);
1902 if (rc) {
1903 DP_ERR(edev, "Start TXQ #%d failed %d\n", txq->index, rc);
1904 return rc;
1905 }
1906
1907 txq->doorbell_addr = ret_params.p_doorbell;
1908 txq->handle = ret_params.p_handle;
1909
1910 /* Determine the FW consumer address associated */
1911 txq->hw_cons_ptr = &fp->sb_info->sb_virt->pi_array[sb_idx];
1912
1913 /* Prepare the doorbell parameters */
1914 SET_FIELD(txq->tx_db.data.params, ETH_DB_DATA_DEST, DB_DEST_XCM);
1915 SET_FIELD(txq->tx_db.data.params, ETH_DB_DATA_AGG_CMD, DB_AGG_CMD_SET);
1916 SET_FIELD(txq->tx_db.data.params, ETH_DB_DATA_AGG_VAL_SEL,
1917 DQ_XCM_ETH_TX_BD_PROD_CMD);
1918 txq->tx_db.data.agg_flags = DQ_XCM_ETH_DQ_CF_CMD;
1919
bd4db888
AE		 1920 /* register doorbell with doorbell recovery mechanism */
1921 rc = edev->ops->common->db_recovery_add(edev->cdev, txq->doorbell_addr,
1922 &txq->tx_db, DB_REC_WIDTH_32B,
1923 DB_REC_KERNEL);
1924
3da7a37a
MY		 1925 return rc;
1926}
1927
a0d26d5a 1928static int qede_start_queues(struct qede_dev *edev, bool clear_stats)
2950219d 1929{
088c8618 1930 int vlan_removal_en = 1;
2950219d 1931 struct qed_dev *cdev = edev->cdev;
fefb0202 1932 struct qed_dev_info *qed_info = &edev->dev_info.common;
f29ffdb6
MY		 1933 struct qed_update_vport_params *vport_update_params;
1934 struct qed_queue_start_common_params q_params;
088c8618 1935 struct qed_start_vport_params start = {0};
80439a17 1936 int rc, i;
2950219d 1937
9a4d7e86 1938 if (!edev->num_queues) {
2950219d
YM		 1939 DP_ERR(edev,
1940 "Cannot update V-VPORT as active as there are no Rx queues\n");
1941 return -EINVAL;
1942 }
1943
f29ffdb6
MY		 1944 vport_update_params = vzalloc(sizeof(*vport_update_params));
1945 if (!vport_update_params)
1946 return -ENOMEM;
1947
4c55215c 1948 start.handle_ptp_pkts = !!(edev->ptp);
55482edc 1949 start.gro_enable = !edev->gro_disable;
088c8618
MC		 1950 start.mtu = edev->ndev->mtu;
1951 start.vport_id = 0;
1952 start.drop_ttl0 = true;
1953 start.remove_inner_vlan = vlan_removal_en;
7f7a144f 1954 start.clear_stats = clear_stats;
088c8618
MC		 1955
1956 rc = edev->ops->vport_start(cdev, &start);
2950219d
YM		 1957
1958 if (rc) {
1959 DP_ERR(edev, "Start V-PORT failed %d\n", rc);
f29ffdb6 1960 goto out;
2950219d
YM		 1961 }
1962
1963 DP_VERBOSE(edev, NETIF_MSG_IFUP,
1964 "Start vport ramrod passed, vport_id = %d, MTU = %d, vlan_removal_en = %d\n",
088c8618 1965 start.vport_id, edev->ndev->mtu + 0xe, vlan_removal_en);
2950219d 1966
9a4d7e86 1967 for_each_queue(i) {
2950219d 1968 struct qede_fastpath *fp = &edev->fp_array[i];
9a4d7e86
SRK		 1969 dma_addr_t p_phys_table;
1970 u32 page_cnt;
2950219d 1971
9a4d7e86 1972 if (fp->type & QEDE_FASTPATH_RX) {
3da7a37a 1973 struct qed_rxq_start_ret_params ret_params;
9a4d7e86
SRK		 1974 struct qede_rx_queue *rxq = fp->rxq;
1975 __le16 *val;
2950219d 1976
3da7a37a 1977 memset(&ret_params, 0, sizeof(ret_params));
9a4d7e86 1978 memset(&q_params, 0, sizeof(q_params));
9a4d7e86
SRK		 1979 q_params.queue_id = rxq->rxq_id;
1980 q_params.vport_id = 0;
f604b17d 1981 q_params.p_sb = fp->sb_info;
9a4d7e86
SRK		 1982 q_params.sb_idx = RX_PI;
1983
1984 p_phys_table =
1985 qed_chain_get_pbl_phys(&rxq->rx_comp_ring);
1986 page_cnt = qed_chain_get_page_cnt(&rxq->rx_comp_ring);
1987
3da7a37a 1988 rc = edev->ops->q_rx_start(cdev, i, &q_params,
9a4d7e86
SRK		 1989 rxq->rx_buf_size,
1990 rxq->rx_bd_ring.p_phys_addr,
1991 p_phys_table,
3da7a37a 1992 page_cnt, &ret_params);
9a4d7e86
SRK		 1993 if (rc) {
1994 DP_ERR(edev, "Start RXQ #%d failed %d\n", i,
1995 rc);
f29ffdb6 1996 goto out;
9a4d7e86
SRK		 1997 }
1998
3da7a37a
MY		 1999 /* Use the return parameters */
2000 rxq->hw_rxq_prod_addr = ret_params.p_prod;
2001 rxq->handle = ret_params.p_handle;
2002
9a4d7e86
SRK		 2003 val = &fp->sb_info->sb_virt->pi_array[RX_PI];
2004 rxq->hw_cons_ptr = val;
2005
2006 qede_update_rx_prod(edev, rxq);
2007 }
2008
496e0517 2009 if (fp->type & QEDE_FASTPATH_XDP) {
cb6aeb07
MY		 2010 rc = qede_start_txq(edev, fp, fp->xdp_tx, i, XDP_PI);
2011 if (rc)
f29ffdb6 2012 goto out;
cb6aeb07 2013
496e0517
MY		 2014 fp->rxq->xdp_prog = bpf_prog_add(edev->xdp_prog, 1);
2015 if (IS_ERR(fp->rxq->xdp_prog)) {
2016 rc = PTR_ERR(fp->rxq->xdp_prog);
2017 fp->rxq->xdp_prog = NULL;
f29ffdb6 2018 goto out;
496e0517
MY		 2019 }
2020 }
2021
80439a17 2022 if (fp->type & QEDE_FASTPATH_TX) {
5e7baf0f
MC		 2023 int cos;
2024
2025 for_each_cos_in_txq(edev, cos) {
2026 rc = qede_start_txq(edev, fp, &fp->txq[cos], i,
2027 TX_PI(cos));
2028 if (rc)
2029 goto out;
2030 }
2950219d
YM		 2031 }
2032 }
2033
2034 /* Prepare and send the vport enable */
f29ffdb6
MY		 2035 vport_update_params->vport_id = start.vport_id;
2036 vport_update_params->update_vport_active_flg = 1;
2037 vport_update_params->vport_active_flg = 1;
2950219d 2038
0bc5fe85 2039 if ((qed_info->b_inter_pf_switch || pci_num_vf(edev->pdev)) &&
831bfb0e 2040 qed_info->tx_switching) {
f29ffdb6
MY		 2041 vport_update_params->update_tx_switching_flg = 1;
2042 vport_update_params->tx_switching_flg = 1;
831bfb0e
YM		 2043 }
2044
f29ffdb6
MY		 2045 qede_fill_rss_params(edev, &vport_update_params->rss_params,
2046 &vport_update_params->update_rss_flg);
961acdea 2047
f29ffdb6
MY		 2048 rc = edev->ops->vport_update(cdev, vport_update_params);
2049 if (rc)
2950219d 2050 DP_ERR(edev, "Update V-PORT failed %d\n", rc);
2950219d 2051
f29ffdb6
MY		 2052out:
2053 vfree(vport_update_params);
2054 return rc;
2950219d
YM		 2055}
2056
2057enum qede_unload_mode {
2058 QEDE_UNLOAD_NORMAL,
2059};
2060
567b3c12
MY		 2061static void qede_unload(struct qede_dev *edev, enum qede_unload_mode mode,
2062 bool is_locked)
2950219d 2063{
a2ec6172 2064 struct qed_link_params link_params;
2950219d
YM		 2065 int rc;
2066
2067 DP_INFO(edev, "Starting qede unload\n");
2068
567b3c12
MY		 2069 if (!is_locked)
2070 __qede_lock(edev);
2071
f04e48db
SRK		 2072 clear_bit(QEDE_FLAGS_LINK_REQUESTED, &edev->flags);
2073
0d8e0aa0
SK		 2074 edev->state = QEDE_STATE_CLOSED;
2075
bbfcd1e8 2076 qede_rdma_dev_event_close(edev);
2e7022d6 2077
2950219d
YM		 2078 /* Close OS Tx */
2079 netif_tx_disable(edev->ndev);
2080 netif_carrier_off(edev->ndev);
2081
a2ec6172
SK		 2082 /* Reset the link */
2083 memset(&link_params, 0, sizeof(link_params));
2084 link_params.link_up = false;
2085 edev->ops->common->set_link(edev->cdev, &link_params);
2950219d
YM		 2086 rc = qede_stop_queues(edev);
2087 if (rc) {
2088 qede_sync_free_irqs(edev);
2089 goto out;
2090 }
2091
2092 DP_INFO(edev, "Stopped Queues\n");
2093
7c1bfcad 2094 qede_vlan_mark_nonconfigured(edev);
2950219d 2095 edev->ops->fastpath_stop(edev->cdev);
3f2a2b8b 2096
e4917d46
CM		 2097 if (!IS_VF(edev) && edev->dev_info.common.num_hwfns == 1) {
2098 qede_poll_for_freeing_arfs_filters(edev);
2099 qede_free_arfs(edev);
2100 }
3f2a2b8b 2101
2950219d
YM		 2102 /* Release the interrupts */
2103 qede_sync_free_irqs(edev);
2104 edev->ops->common->set_fp_int(edev->cdev, 0);
2105
2106 qede_napi_disable_remove(edev);
2107
2108 qede_free_mem_load(edev);
2109 qede_free_fp_array(edev);
2110
2111out:
567b3c12
MY		 2112 if (!is_locked)
2113 __qede_unlock(edev);
2950219d
YM		 2114 DP_INFO(edev, "Ending qede unload\n");
2115}
2116
2117enum qede_load_mode {
2118 QEDE_LOAD_NORMAL,
a0d26d5a 2119 QEDE_LOAD_RELOAD,
2950219d
YM		 2120};
2121
567b3c12
MY		 2122static int qede_load(struct qede_dev *edev, enum qede_load_mode mode,
2123 bool is_locked)
2950219d 2124{
a2ec6172 2125 struct qed_link_params link_params;
5e7baf0f 2126 u8 num_tc;
2950219d
YM		 2127 int rc;
2128
2129 DP_INFO(edev, "Starting qede load\n");
2130
567b3c12
MY		 2131 if (!is_locked)
2132 __qede_lock(edev);
2133
2950219d
YM		 2134 rc = qede_set_num_queues(edev);
2135 if (rc)
567b3c12 2136 goto out;
2950219d
YM		 2137
2138 rc = qede_alloc_fp_array(edev);
2139 if (rc)
567b3c12 2140 goto out;
2950219d
YM		 2141
2142 qede_init_fp(edev);
2143
2144 rc = qede_alloc_mem_load(edev);
2145 if (rc)
2146 goto err1;
80439a17
MY		 2147 DP_INFO(edev, "Allocated %d Rx, %d Tx queues\n",
2148 QEDE_RSS_COUNT(edev), QEDE_TSS_COUNT(edev));
2950219d
YM		 2149
2150 rc = qede_set_real_num_queues(edev);
2151 if (rc)
2152 goto err2;
2153
e4917d46
CM		 2154 if (!IS_VF(edev) && edev->dev_info.common.num_hwfns == 1) {
2155 rc = qede_alloc_arfs(edev);
2156 if (rc)
2157 DP_NOTICE(edev, "aRFS memory allocation failed\n");
2158 }
3f2a2b8b 2159
2950219d
YM		 2160 qede_napi_add_enable(edev);
2161 DP_INFO(edev, "Napi added and enabled\n");
2162
2163 rc = qede_setup_irqs(edev);
2164 if (rc)
2165 goto err3;
2166 DP_INFO(edev, "Setup IRQs succeeded\n");
2167
a0d26d5a 2168 rc = qede_start_queues(edev, mode != QEDE_LOAD_RELOAD);
2950219d
YM		 2169 if (rc)
2170 goto err4;
2171 DP_INFO(edev, "Start VPORT, RXQ and TXQ succeeded\n");
2172
5e7baf0f
MC		 2173 num_tc = netdev_get_num_tc(edev->ndev);
2174 num_tc = num_tc ? num_tc : edev->dev_info.num_tc;
2175 qede_setup_tc(edev->ndev, num_tc);
2176
7c1bfcad
SRK		 2177 /* Program un-configured VLANs */
2178 qede_configure_vlan_filters(edev);
2179
f04e48db
SRK		 2180 set_bit(QEDE_FLAGS_LINK_REQUESTED, &edev->flags);
2181
a2ec6172
SK		 2182 /* Ask for link-up using current configuration */
2183 memset(&link_params, 0, sizeof(link_params));
2184 link_params.link_up = true;
2185 edev->ops->common->set_link(edev->cdev, &link_params);
2186
567b3c12
MY		 2187 edev->state = QEDE_STATE_OPEN;
2188
2950219d
YM		 2189 DP_INFO(edev, "Ending successfully qede load\n");
2190
567b3c12 2191 goto out;
2950219d
YM		 2192err4:
2193 qede_sync_free_irqs(edev);
2194 memset(&edev->int_info.msix_cnt, 0, sizeof(struct qed_int_info));
2195err3:
2196 qede_napi_disable_remove(edev);
2197err2:
2198 qede_free_mem_load(edev);
2199err1:
2200 edev->ops->common->set_fp_int(edev->cdev, 0);
2201 qede_free_fp_array(edev);
9a4d7e86
SRK		 2202 edev->num_queues = 0;
2203 edev->fp_num_tx = 0;
2204 edev->fp_num_rx = 0;
567b3c12
MY		 2205out:
2206 if (!is_locked)
2207 __qede_unlock(edev);
2208
2950219d
YM		 2209 return rc;
2210}
2211
567b3c12
MY		 2212/* 'func' should be able to run between unload and reload assuming interface
2213 * is actually running, or afterwards in case it's currently DOWN.
2214 */
133fac0e 2215void qede_reload(struct qede_dev *edev,
567b3c12 2216 struct qede_reload_args *args, bool is_locked)
133fac0e 2217{
567b3c12
MY		 2218 if (!is_locked)
2219 __qede_lock(edev);
2220
2221 /* Since qede_lock is held, internal state wouldn't change even
2222 * if netdev state would start transitioning. Check whether current
2223 * internal configuration indicates device is up, then reload.
133fac0e 2224 */
567b3c12
MY		 2225 if (edev->state == QEDE_STATE_OPEN) {
2226 qede_unload(edev, QEDE_UNLOAD_NORMAL, true);
2227 if (args)
2228 args->func(edev, args);
2229 qede_load(edev, QEDE_LOAD_RELOAD, true);
133fac0e 2230
567b3c12
MY		 2231 /* Since no one is going to do it for us, re-configure */
2232 qede_config_rx_mode(edev->ndev);
2233 } else if (args) {
2234 args->func(edev, args);
2235 }
133fac0e 2236
567b3c12
MY		 2237 if (!is_locked)
2238 __qede_unlock(edev);
133fac0e
SK		 2239}
2240
2950219d
YM		 2241/* called with rtnl_lock */
2242static int qede_open(struct net_device *ndev)
2243{
2244 struct qede_dev *edev = netdev_priv(ndev);
b18e170c 2245 int rc;
2950219d
YM		 2246
2247 netif_carrier_off(ndev);
2248
2249 edev->ops->common->set_power_state(edev->cdev, PCI_D0);
2250
567b3c12 2251 rc = qede_load(edev, QEDE_LOAD_NORMAL, false);
b18e170c
MC		 2252 if (rc)
2253 return rc;
2254
f9f082a9
AD		 2255 udp_tunnel_get_rx_info(ndev);
2256
0fefbfba
SK		 2257 edev->ops->common->update_drv_state(edev->cdev, true);
2258
b18e170c 2259 return 0;
2950219d
YM		 2260}
2261
2262static int qede_close(struct net_device *ndev)
2263{
2264 struct qede_dev *edev = netdev_priv(ndev);
2265
567b3c12 2266 qede_unload(edev, QEDE_UNLOAD_NORMAL, false);
2950219d 2267
0fefbfba
SK		 2268 edev->ops->common->update_drv_state(edev->cdev, false);
2269
2950219d
YM		 2270 return 0;
2271}
0d8e0aa0 2272
a2ec6172
SK		 2273static void qede_link_update(void *dev, struct qed_link_output *link)
2274{
2275 struct qede_dev *edev = dev;
2276
f04e48db
SRK		 2277 if (!test_bit(QEDE_FLAGS_LINK_REQUESTED, &edev->flags)) {
2278 DP_VERBOSE(edev, NETIF_MSG_LINK, "Interface is not ready\n");
a2ec6172
SK		 2279 return;
2280 }
2281
2282 if (link->link_up) {
8e025ae2
YM		 2283 if (!netif_carrier_ok(edev->ndev)) {
2284 DP_NOTICE(edev, "Link is up\n");
2285 netif_tx_start_all_queues(edev->ndev);
2286 netif_carrier_on(edev->ndev);
4609adc2 2287 qede_rdma_dev_event_open(edev);
8e025ae2 2288 }
a2ec6172 2289 } else {
8e025ae2
YM		 2290 if (netif_carrier_ok(edev->ndev)) {
2291 DP_NOTICE(edev, "Link is down\n");
2292 netif_tx_disable(edev->ndev);
2293 netif_carrier_off(edev->ndev);
4609adc2 2294 qede_rdma_dev_event_close(edev);
8e025ae2 2295 }
a2ec6172
SK		 2296 }
2297}
d25b859c
SRK		 2298
2299static bool qede_is_txq_full(struct qede_dev *edev, struct qede_tx_queue *txq)
2300{
2301 struct netdev_queue *netdev_txq;
2302
5e7baf0f 2303 netdev_txq = netdev_get_tx_queue(edev->ndev, txq->ndev_txq_id);
d25b859c
SRK		 2304 if (netif_xmit_stopped(netdev_txq))
2305 return true;
2306
2307 return false;
2308}
2309
2310static void qede_get_generic_tlv_data(void *dev, struct qed_generic_tlvs *data)
2311{
2312 struct qede_dev *edev = dev;
2313 struct netdev_hw_addr *ha;
2314 int i;
2315
2316 if (edev->ndev->features & NETIF_F_IP_CSUM)
2317 data->feat_flags |= QED_TLV_IP_CSUM;
2318 if (edev->ndev->features & NETIF_F_TSO)
2319 data->feat_flags |= QED_TLV_LSO;
2320
2321 ether_addr_copy(data->mac[0], edev->ndev->dev_addr);
2322 memset(data->mac[1], 0, ETH_ALEN);
2323 memset(data->mac[2], 0, ETH_ALEN);
2324 /* Copy the first two UC macs */
2325 netif_addr_lock_bh(edev->ndev);
2326 i = 1;
2327 netdev_for_each_uc_addr(ha, edev->ndev) {
2328 ether_addr_copy(data->mac[i++], ha->addr);
2329 if (i == QED_TLV_MAC_COUNT)
2330 break;
2331 }
2332
2333 netif_addr_unlock_bh(edev->ndev);
2334}
2335
2336static void qede_get_eth_tlv_data(void *dev, void *data)
2337{
2338 struct qed_mfw_tlv_eth *etlv = data;
2339 struct qede_dev *edev = dev;
2340 struct qede_fastpath *fp;
2341 int i;
2342
2343 etlv->lso_maxoff_size = 0XFFFF;
2344 etlv->lso_maxoff_size_set = true;
2345 etlv->lso_minseg_size = (u16)ETH_TX_LSO_WINDOW_MIN_LEN;
2346 etlv->lso_minseg_size_set = true;
2347 etlv->prom_mode = !!(edev->ndev->flags & IFF_PROMISC);
2348 etlv->prom_mode_set = true;
2349 etlv->tx_descr_size = QEDE_TSS_COUNT(edev);
2350 etlv->tx_descr_size_set = true;
2351 etlv->rx_descr_size = QEDE_RSS_COUNT(edev);
2352 etlv->rx_descr_size_set = true;
2353 etlv->iov_offload = QED_MFW_TLV_IOV_OFFLOAD_VEB;
2354 etlv->iov_offload_set = true;
2355
2356 /* Fill information regarding queues; Should be done under the qede
2357 * lock to guarantee those don't change beneath our feet.
2358 */
2359 etlv->txqs_empty = true;
2360 etlv->rxqs_empty = true;
2361 etlv->num_txqs_full = 0;
2362 etlv->num_rxqs_full = 0;
2363
2364 __qede_lock(edev);
2365 for_each_queue(i) {
2366 fp = &edev->fp_array[i];
2367 if (fp->type & QEDE_FASTPATH_TX) {
5e7baf0f
MC		 2368 struct qede_tx_queue *txq = QEDE_FP_TC0_TXQ(fp);
2369
2370 if (txq->sw_tx_cons != txq->sw_tx_prod)
d25b859c 2371 etlv->txqs_empty = false;
5e7baf0f 2372 if (qede_is_txq_full(edev, txq))
d25b859c
SRK		 2373 etlv->num_txqs_full++;
2374 }
2375 if (fp->type & QEDE_FASTPATH_RX) {
2376 if (qede_has_rx_work(fp->rxq))
2377 etlv->rxqs_empty = false;
2378
2379 /* This one is a bit tricky; Firmware might stop
2380 * placing packets if ring is not yet full.
2381 * Give an approximation.
2382 */
2383 if (le16_to_cpu(*fp->rxq->hw_cons_ptr) -
2384 qed_chain_get_cons_idx(&fp->rxq->rx_comp_ring) >
2385 RX_RING_SIZE - 100)
2386 etlv->num_rxqs_full++;
2387 }
2388 }
2389 __qede_unlock(edev);
2390
2391 etlv->txqs_empty_set = true;
2392 etlv->rxqs_empty_set = true;
2393 etlv->num_txqs_full_set = true;
2394 etlv->num_rxqs_full_set = true;
2395}
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