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[mirror_ubuntu-focal-kernel.git] / drivers / net / ethernet / qlogic / qede / qede_main.c
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e712d52b 1/* QLogic qede NIC Driver
e8f1cb50
MY		 2 * Copyright (c) 2015-2017 QLogic Corporation
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
e712d52b
YM		 32#include <linux/module.h>
33#include <linux/pci.h>
34#include <linux/version.h>
35#include <linux/device.h>
36#include <linux/netdevice.h>
37#include <linux/etherdevice.h>
38#include <linux/skbuff.h>
39#include <linux/errno.h>
40#include <linux/list.h>
41#include <linux/string.h>
42#include <linux/dma-mapping.h>
43#include <linux/interrupt.h>
44#include <asm/byteorder.h>
45#include <asm/param.h>
46#include <linux/io.h>
47#include <linux/netdev_features.h>
48#include <linux/udp.h>
49#include <linux/tcp.h>
f9f082a9 50#include <net/udp_tunnel.h>
e712d52b
YM		 51#include <linux/ip.h>
52#include <net/ipv6.h>
53#include <net/tcp.h>
54#include <linux/if_ether.h>
55#include <linux/if_vlan.h>
56#include <linux/pkt_sched.h>
57#include <linux/ethtool.h>
58#include <linux/in.h>
59#include <linux/random.h>
60#include <net/ip6_checksum.h>
61#include <linux/bitops.h>
f29ffdb6 62#include <linux/vmalloc.h>
e712d52b 63#include "qede.h"
4c55215c 64#include "qede_ptp.h"
e712d52b 65
5abd7e92
YM		 66static char version[] =
67 "QLogic FastLinQ 4xxxx Ethernet Driver qede " DRV_MODULE_VERSION "\n";
e712d52b 68
5abd7e92 69MODULE_DESCRIPTION("QLogic FastLinQ 4xxxx Ethernet Driver");
e712d52b
YM		 70MODULE_LICENSE("GPL");
71MODULE_VERSION(DRV_MODULE_VERSION);
72
73static uint debug;
74module_param(debug, uint, 0);
75MODULE_PARM_DESC(debug, " Default debug msglevel");
76
77static const struct qed_eth_ops *qed_ops;
78
79#define CHIP_NUM_57980S_40 0x1634
0e7441d7 80#define CHIP_NUM_57980S_10 0x1666
e712d52b
YM		 81#define CHIP_NUM_57980S_MF 0x1636
82#define CHIP_NUM_57980S_100 0x1644
83#define CHIP_NUM_57980S_50 0x1654
84#define CHIP_NUM_57980S_25 0x1656
fefb0202 85#define CHIP_NUM_57980S_IOV 0x1664
9c79ddaa
MY		 86#define CHIP_NUM_AH 0x8070
87#define CHIP_NUM_AH_IOV 0x8090
e712d52b
YM		 88
89#ifndef PCI_DEVICE_ID_NX2_57980E
90#define PCI_DEVICE_ID_57980S_40 CHIP_NUM_57980S_40
91#define PCI_DEVICE_ID_57980S_10 CHIP_NUM_57980S_10
92#define PCI_DEVICE_ID_57980S_MF CHIP_NUM_57980S_MF
93#define PCI_DEVICE_ID_57980S_100 CHIP_NUM_57980S_100
94#define PCI_DEVICE_ID_57980S_50 CHIP_NUM_57980S_50
95#define PCI_DEVICE_ID_57980S_25 CHIP_NUM_57980S_25
fefb0202 96#define PCI_DEVICE_ID_57980S_IOV CHIP_NUM_57980S_IOV
9c79ddaa
MY		 97#define PCI_DEVICE_ID_AH CHIP_NUM_AH
98#define PCI_DEVICE_ID_AH_IOV CHIP_NUM_AH_IOV
99
e712d52b
YM		 100#endif
101
fefb0202
YM		 102enum qede_pci_private {
103 QEDE_PRIVATE_PF,
104 QEDE_PRIVATE_VF
105};
106
e712d52b 107static const struct pci_device_id qede_pci_tbl[] = {
fefb0202
YM		 108 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_40), QEDE_PRIVATE_PF},
109 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_10), QEDE_PRIVATE_PF},
110 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_MF), QEDE_PRIVATE_PF},
111 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_100), QEDE_PRIVATE_PF},
112 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_50), QEDE_PRIVATE_PF},
113 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_25), QEDE_PRIVATE_PF},
14b84e86 114#ifdef CONFIG_QED_SRIOV
fefb0202 115 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_IOV), QEDE_PRIVATE_VF},
9c79ddaa
MY		 116#endif
117 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_AH), QEDE_PRIVATE_PF},
118#ifdef CONFIG_QED_SRIOV
119 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_AH_IOV), QEDE_PRIVATE_VF},
14b84e86 120#endif
e712d52b
YM		 121 { 0 }
122};
123
124MODULE_DEVICE_TABLE(pci, qede_pci_tbl);
125
126static int qede_probe(struct pci_dev *pdev, const struct pci_device_id *id);
127
128#define TX_TIMEOUT (5 * HZ)
129
cb6aeb07
MY		 130/* Utilize last protocol index for XDP */
131#define XDP_PI 11
132
e712d52b 133static void qede_remove(struct pci_dev *pdev);
14d39648 134static void qede_shutdown(struct pci_dev *pdev);
a2ec6172 135static void qede_link_update(void *dev, struct qed_link_output *link);
d25b859c
SRK		 136static void qede_get_eth_tlv_data(void *edev, void *data);
137static void qede_get_generic_tlv_data(void *edev,
138 struct qed_generic_tlvs *data);
e712d52b 139
567b3c12
MY		 140/* The qede lock is used to protect driver state change and driver flows that
141 * are not reentrant.
142 */
143void __qede_lock(struct qede_dev *edev)
144{
145 mutex_lock(&edev->qede_lock);
146}
147
148void __qede_unlock(struct qede_dev *edev)
149{
150 mutex_unlock(&edev->qede_lock);
151}
152
fefb0202 153#ifdef CONFIG_QED_SRIOV
79aab093
MS		 154static int qede_set_vf_vlan(struct net_device *ndev, int vf, u16 vlan, u8 qos,
155 __be16 vlan_proto)
08feecd7
YM		 156{
157 struct qede_dev *edev = netdev_priv(ndev);
158
159 if (vlan > 4095) {
160 DP_NOTICE(edev, "Illegal vlan value %d\n", vlan);
161 return -EINVAL;
162 }
163
79aab093
MS		 164 if (vlan_proto != htons(ETH_P_8021Q))
165 return -EPROTONOSUPPORT;
166
08feecd7
YM		 167 DP_VERBOSE(edev, QED_MSG_IOV, "Setting Vlan 0x%04x to VF [%d]\n",
168 vlan, vf);
169
170 return edev->ops->iov->set_vlan(edev->cdev, vlan, vf);
171}
172
eff16960
YM		 173static int qede_set_vf_mac(struct net_device *ndev, int vfidx, u8 *mac)
174{
175 struct qede_dev *edev = netdev_priv(ndev);
176
177 DP_VERBOSE(edev, QED_MSG_IOV,
178 "Setting MAC %02x:%02x:%02x:%02x:%02x:%02x to VF [%d]\n",
179 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5], vfidx);
180
181 if (!is_valid_ether_addr(mac)) {
182 DP_VERBOSE(edev, QED_MSG_IOV, "MAC address isn't valid\n");
183 return -EINVAL;
184 }
185
186 return edev->ops->iov->set_mac(edev->cdev, mac, vfidx);
187}
188
fefb0202
YM		 189static int qede_sriov_configure(struct pci_dev *pdev, int num_vfs_param)
190{
191 struct qede_dev *edev = netdev_priv(pci_get_drvdata(pdev));
831bfb0e 192 struct qed_dev_info *qed_info = &edev->dev_info.common;
f29ffdb6 193 struct qed_update_vport_params *vport_params;
831bfb0e 194 int rc;
fefb0202 195
f29ffdb6
MY		 196 vport_params = vzalloc(sizeof(*vport_params));
197 if (!vport_params)
198 return -ENOMEM;
fefb0202
YM		 199 DP_VERBOSE(edev, QED_MSG_IOV, "Requested %d VFs\n", num_vfs_param);
200
831bfb0e
YM		 201 rc = edev->ops->iov->configure(edev->cdev, num_vfs_param);
202
203 /* Enable/Disable Tx switching for PF */
204 if ((rc == num_vfs_param) && netif_running(edev->ndev) &&
0bc5fe85 205 !qed_info->b_inter_pf_switch && qed_info->tx_switching) {
f29ffdb6
MY		 206 vport_params->vport_id = 0;
207 vport_params->update_tx_switching_flg = 1;
208 vport_params->tx_switching_flg = num_vfs_param ? 1 : 0;
209 edev->ops->vport_update(edev->cdev, vport_params);
831bfb0e
YM		 210 }
211
f29ffdb6 212 vfree(vport_params);
831bfb0e 213 return rc;
fefb0202
YM		 214}
215#endif
216
e712d52b
YM		 217static struct pci_driver qede_pci_driver = {
218 .name = "qede",
219 .id_table = qede_pci_tbl,
220 .probe = qede_probe,
221 .remove = qede_remove,
14d39648 222 .shutdown = qede_shutdown,
fefb0202
YM		 223#ifdef CONFIG_QED_SRIOV
224 .sriov_configure = qede_sriov_configure,
225#endif
e712d52b
YM		 226};
227
a2ec6172
SK		 228static struct qed_eth_cb_ops qede_ll_ops = {
229 {
e4917d46
CM		 230#ifdef CONFIG_RFS_ACCEL
231 .arfs_filter_op = qede_arfs_filter_op,
232#endif
a2ec6172 233 .link_update = qede_link_update,
d25b859c
SRK		 234 .get_generic_tlv_data = qede_get_generic_tlv_data,
235 .get_protocol_tlv_data = qede_get_eth_tlv_data,
a2ec6172 236 },
eff16960 237 .force_mac = qede_force_mac,
97379f15 238 .ports_update = qede_udp_ports_update,
a2ec6172
SK		 239};
240
2950219d
YM		 241static int qede_netdev_event(struct notifier_block *this, unsigned long event,
242 void *ptr)
243{
244 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
245 struct ethtool_drvinfo drvinfo;
246 struct qede_dev *edev;
247
cee9fbd8 248 if (event != NETDEV_CHANGENAME && event != NETDEV_CHANGEADDR)
2950219d
YM		 249 goto done;
250
251 /* Check whether this is a qede device */
252 if (!ndev || !ndev->ethtool_ops || !ndev->ethtool_ops->get_drvinfo)
253 goto done;
254
255 memset(&drvinfo, 0, sizeof(drvinfo));
256 ndev->ethtool_ops->get_drvinfo(ndev, &drvinfo);
257 if (strcmp(drvinfo.driver, "qede"))
258 goto done;
259 edev = netdev_priv(ndev);
260
cee9fbd8
RA		 261 switch (event) {
262 case NETDEV_CHANGENAME:
263 /* Notify qed of the name change */
264 if (!edev->ops || !edev->ops->common)
265 goto done;
712c3cbf 266 edev->ops->common->set_name(edev->cdev, edev->ndev->name);
cee9fbd8
RA		 267 break;
268 case NETDEV_CHANGEADDR:
269 edev = netdev_priv(ndev);
bbfcd1e8 270 qede_rdma_event_changeaddr(edev);
cee9fbd8
RA		 271 break;
272 }
2950219d
YM		 273
274done:
275 return NOTIFY_DONE;
276}
277
278static struct notifier_block qede_netdev_notifier = {
279 .notifier_call = qede_netdev_event,
280};
281
e712d52b
YM		 282static
283int __init qede_init(void)
284{
285 int ret;
e712d52b 286
525ef5c0 287 pr_info("qede_init: %s\n", version);
e712d52b 288
95114344 289 qed_ops = qed_get_eth_ops();
e712d52b
YM		 290 if (!qed_ops) {
291 pr_notice("Failed to get qed ethtool operations\n");
292 return -EINVAL;
293 }
294
2950219d 295 /* Must register notifier before pci ops, since we might miss
3f2176dd 296 * interface rename after pci probe and netdev registration.
2950219d
YM		 297 */
298 ret = register_netdevice_notifier(&qede_netdev_notifier);
299 if (ret) {
300 pr_notice("Failed to register netdevice_notifier\n");
301 qed_put_eth_ops();
302 return -EINVAL;
303 }
304
e712d52b
YM		 305 ret = pci_register_driver(&qede_pci_driver);
306 if (ret) {
307 pr_notice("Failed to register driver\n");
2950219d 308 unregister_netdevice_notifier(&qede_netdev_notifier);
e712d52b
YM		 309 qed_put_eth_ops();
310 return -EINVAL;
311 }
312
313 return 0;
314}
315
316static void __exit qede_cleanup(void)
317{
525ef5c0
YM		 318 if (debug & QED_LOG_INFO_MASK)
319 pr_info("qede_cleanup called\n");
e712d52b 320
2950219d 321 unregister_netdevice_notifier(&qede_netdev_notifier);
e712d52b
YM		 322 pci_unregister_driver(&qede_pci_driver);
323 qed_put_eth_ops();
324}
325
326module_init(qede_init);
327module_exit(qede_cleanup);
328
2950219d
YM		 329static int qede_open(struct net_device *ndev);
330static int qede_close(struct net_device *ndev);
7c1bfcad 331
133fac0e
SK		 332void qede_fill_by_demand_stats(struct qede_dev *edev)
333{
9c79ddaa 334 struct qede_stats_common *p_common = &edev->stats.common;
133fac0e
SK		 335 struct qed_eth_stats stats;
336
337 edev->ops->get_vport_stats(edev->cdev, &stats);
9c79ddaa
MY		 338
339 p_common->no_buff_discards = stats.common.no_buff_discards;
340 p_common->packet_too_big_discard = stats.common.packet_too_big_discard;
341 p_common->ttl0_discard = stats.common.ttl0_discard;
342 p_common->rx_ucast_bytes = stats.common.rx_ucast_bytes;
343 p_common->rx_mcast_bytes = stats.common.rx_mcast_bytes;
344 p_common->rx_bcast_bytes = stats.common.rx_bcast_bytes;
345 p_common->rx_ucast_pkts = stats.common.rx_ucast_pkts;
346 p_common->rx_mcast_pkts = stats.common.rx_mcast_pkts;
347 p_common->rx_bcast_pkts = stats.common.rx_bcast_pkts;
348 p_common->mftag_filter_discards = stats.common.mftag_filter_discards;
349 p_common->mac_filter_discards = stats.common.mac_filter_discards;
608e00d0 350 p_common->gft_filter_drop = stats.common.gft_filter_drop;
9c79ddaa
MY		 351
352 p_common->tx_ucast_bytes = stats.common.tx_ucast_bytes;
353 p_common->tx_mcast_bytes = stats.common.tx_mcast_bytes;
354 p_common->tx_bcast_bytes = stats.common.tx_bcast_bytes;
355 p_common->tx_ucast_pkts = stats.common.tx_ucast_pkts;
356 p_common->tx_mcast_pkts = stats.common.tx_mcast_pkts;
357 p_common->tx_bcast_pkts = stats.common.tx_bcast_pkts;
358 p_common->tx_err_drop_pkts = stats.common.tx_err_drop_pkts;
359 p_common->coalesced_pkts = stats.common.tpa_coalesced_pkts;
360 p_common->coalesced_events = stats.common.tpa_coalesced_events;
361 p_common->coalesced_aborts_num = stats.common.tpa_aborts_num;
362 p_common->non_coalesced_pkts = stats.common.tpa_not_coalesced_pkts;
363 p_common->coalesced_bytes = stats.common.tpa_coalesced_bytes;
364
365 p_common->rx_64_byte_packets = stats.common.rx_64_byte_packets;
366 p_common->rx_65_to_127_byte_packets =
367 stats.common.rx_65_to_127_byte_packets;
368 p_common->rx_128_to_255_byte_packets =
369 stats.common.rx_128_to_255_byte_packets;
370 p_common->rx_256_to_511_byte_packets =
371 stats.common.rx_256_to_511_byte_packets;
372 p_common->rx_512_to_1023_byte_packets =
373 stats.common.rx_512_to_1023_byte_packets;
374 p_common->rx_1024_to_1518_byte_packets =
375 stats.common.rx_1024_to_1518_byte_packets;
376 p_common->rx_crc_errors = stats.common.rx_crc_errors;
377 p_common->rx_mac_crtl_frames = stats.common.rx_mac_crtl_frames;
378 p_common->rx_pause_frames = stats.common.rx_pause_frames;
379 p_common->rx_pfc_frames = stats.common.rx_pfc_frames;
380 p_common->rx_align_errors = stats.common.rx_align_errors;
381 p_common->rx_carrier_errors = stats.common.rx_carrier_errors;
382 p_common->rx_oversize_packets = stats.common.rx_oversize_packets;
383 p_common->rx_jabbers = stats.common.rx_jabbers;
384 p_common->rx_undersize_packets = stats.common.rx_undersize_packets;
385 p_common->rx_fragments = stats.common.rx_fragments;
386 p_common->tx_64_byte_packets = stats.common.tx_64_byte_packets;
387 p_common->tx_65_to_127_byte_packets =
388 stats.common.tx_65_to_127_byte_packets;
389 p_common->tx_128_to_255_byte_packets =
390 stats.common.tx_128_to_255_byte_packets;
391 p_common->tx_256_to_511_byte_packets =
392 stats.common.tx_256_to_511_byte_packets;
393 p_common->tx_512_to_1023_byte_packets =
394 stats.common.tx_512_to_1023_byte_packets;
395 p_common->tx_1024_to_1518_byte_packets =
396 stats.common.tx_1024_to_1518_byte_packets;
397 p_common->tx_pause_frames = stats.common.tx_pause_frames;
398 p_common->tx_pfc_frames = stats.common.tx_pfc_frames;
399 p_common->brb_truncates = stats.common.brb_truncates;
400 p_common->brb_discards = stats.common.brb_discards;
401 p_common->tx_mac_ctrl_frames = stats.common.tx_mac_ctrl_frames;
32d26a68 402 p_common->link_change_count = stats.common.link_change_count;
9c79ddaa
MY		 403
404 if (QEDE_IS_BB(edev)) {
405 struct qede_stats_bb *p_bb = &edev->stats.bb;
406
407 p_bb->rx_1519_to_1522_byte_packets =
408 stats.bb.rx_1519_to_1522_byte_packets;
409 p_bb->rx_1519_to_2047_byte_packets =
410 stats.bb.rx_1519_to_2047_byte_packets;
411 p_bb->rx_2048_to_4095_byte_packets =
412 stats.bb.rx_2048_to_4095_byte_packets;
413 p_bb->rx_4096_to_9216_byte_packets =
414 stats.bb.rx_4096_to_9216_byte_packets;
415 p_bb->rx_9217_to_16383_byte_packets =
416 stats.bb.rx_9217_to_16383_byte_packets;
417 p_bb->tx_1519_to_2047_byte_packets =
418 stats.bb.tx_1519_to_2047_byte_packets;
419 p_bb->tx_2048_to_4095_byte_packets =
420 stats.bb.tx_2048_to_4095_byte_packets;
421 p_bb->tx_4096_to_9216_byte_packets =
422 stats.bb.tx_4096_to_9216_byte_packets;
423 p_bb->tx_9217_to_16383_byte_packets =
424 stats.bb.tx_9217_to_16383_byte_packets;
425 p_bb->tx_lpi_entry_count = stats.bb.tx_lpi_entry_count;
426 p_bb->tx_total_collisions = stats.bb.tx_total_collisions;
427 } else {
428 struct qede_stats_ah *p_ah = &edev->stats.ah;
429
430 p_ah->rx_1519_to_max_byte_packets =
431 stats.ah.rx_1519_to_max_byte_packets;
432 p_ah->tx_1519_to_max_byte_packets =
433 stats.ah.tx_1519_to_max_byte_packets;
434 }
133fac0e
SK		 435}
436
bc1f4470 437static void qede_get_stats64(struct net_device *dev,
438 struct rtnl_link_stats64 *stats)
133fac0e
SK		 439{
440 struct qede_dev *edev = netdev_priv(dev);
9c79ddaa 441 struct qede_stats_common *p_common;
133fac0e
SK		 442
443 qede_fill_by_demand_stats(edev);
9c79ddaa 444 p_common = &edev->stats.common;
133fac0e 445
9c79ddaa
MY		 446 stats->rx_packets = p_common->rx_ucast_pkts + p_common->rx_mcast_pkts +
447 p_common->rx_bcast_pkts;
448 stats->tx_packets = p_common->tx_ucast_pkts + p_common->tx_mcast_pkts +
449 p_common->tx_bcast_pkts;
133fac0e 450
9c79ddaa
MY		 451 stats->rx_bytes = p_common->rx_ucast_bytes + p_common->rx_mcast_bytes +
452 p_common->rx_bcast_bytes;
453 stats->tx_bytes = p_common->tx_ucast_bytes + p_common->tx_mcast_bytes +
454 p_common->tx_bcast_bytes;
133fac0e 455
9c79ddaa
MY		 456 stats->tx_errors = p_common->tx_err_drop_pkts;
457 stats->multicast = p_common->rx_mcast_pkts + p_common->rx_bcast_pkts;
133fac0e 458
9c79ddaa 459 stats->rx_fifo_errors = p_common->no_buff_discards;
133fac0e 460
9c79ddaa
MY		 461 if (QEDE_IS_BB(edev))
462 stats->collisions = edev->stats.bb.tx_total_collisions;
463 stats->rx_crc_errors = p_common->rx_crc_errors;
464 stats->rx_frame_errors = p_common->rx_align_errors;
133fac0e
SK		 465}
466
733def6a 467#ifdef CONFIG_QED_SRIOV
73390ac9
YM		 468static int qede_get_vf_config(struct net_device *dev, int vfidx,
469 struct ifla_vf_info *ivi)
470{
471 struct qede_dev *edev = netdev_priv(dev);
472
473 if (!edev->ops)
474 return -EINVAL;
475
476 return edev->ops->iov->get_config(edev->cdev, vfidx, ivi);
477}
478
733def6a
YM		 479static int qede_set_vf_rate(struct net_device *dev, int vfidx,
480 int min_tx_rate, int max_tx_rate)
481{
482 struct qede_dev *edev = netdev_priv(dev);
483
be7b6d64 484 return edev->ops->iov->set_rate(edev->cdev, vfidx, min_tx_rate,
733def6a
YM		 485 max_tx_rate);
486}
487
6ddc7608
YM		 488static int qede_set_vf_spoofchk(struct net_device *dev, int vfidx, bool val)
489{
490 struct qede_dev *edev = netdev_priv(dev);
491
492 if (!edev->ops)
493 return -EINVAL;
494
495 return edev->ops->iov->set_spoof(edev->cdev, vfidx, val);
496}
497
733def6a
YM		 498static int qede_set_vf_link_state(struct net_device *dev, int vfidx,
499 int link_state)
500{
501 struct qede_dev *edev = netdev_priv(dev);
502
503 if (!edev->ops)
504 return -EINVAL;
505
506 return edev->ops->iov->set_link_state(edev->cdev, vfidx, link_state);
507}
f990c82c
MY		 508
509static int qede_set_vf_trust(struct net_device *dev, int vfidx, bool setting)
510{
511 struct qede_dev *edev = netdev_priv(dev);
512
513 if (!edev->ops)
514 return -EINVAL;
515
516 return edev->ops->iov->set_trust(edev->cdev, vfidx, setting);
517}
733def6a
YM		 518#endif
519
4c55215c
SRK		 520static int qede_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
521{
522 struct qede_dev *edev = netdev_priv(dev);
523
524 if (!netif_running(dev))
525 return -EAGAIN;
526
527 switch (cmd) {
528 case SIOCSHWTSTAMP:
529 return qede_ptp_hw_ts(edev, ifr);
530 default:
531 DP_VERBOSE(edev, QED_MSG_DEBUG,
532 "default IOCTL cmd 0x%x\n", cmd);
533 return -EOPNOTSUPP;
534 }
535
536 return 0;
537}
538
5e7baf0f
MC		 539int qede_setup_tc(struct net_device *ndev, u8 num_tc)
540{
541 struct qede_dev *edev = netdev_priv(ndev);
542 int cos, count, offset;
543
544 if (num_tc > edev->dev_info.num_tc)
545 return -EINVAL;
546
547 netdev_reset_tc(ndev);
548 netdev_set_num_tc(ndev, num_tc);
549
550 for_each_cos_in_txq(edev, cos) {
551 count = QEDE_TSS_COUNT(edev);
552 offset = cos * QEDE_TSS_COUNT(edev);
553 netdev_set_tc_queue(ndev, cos, count, offset);
554 }
555
556 return 0;
557}
558
2ce9c93e
MC		 559static int
560qede_set_flower(struct qede_dev *edev, struct tc_cls_flower_offload *f,
561 __be16 proto)
562{
563 switch (f->command) {
564 case TC_CLSFLOWER_REPLACE:
565 return qede_add_tc_flower_fltr(edev, proto, f);
566 case TC_CLSFLOWER_DESTROY:
567 return qede_delete_flow_filter(edev, f->cookie);
568 default:
569 return -EOPNOTSUPP;
570 }
571}
572
573static int qede_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
574 void *cb_priv)
575{
576 struct tc_cls_flower_offload *f;
577 struct qede_dev *edev = cb_priv;
578
579 if (!tc_cls_can_offload_and_chain0(edev->ndev, type_data))
580 return -EOPNOTSUPP;
581
582 switch (type) {
583 case TC_SETUP_CLSFLOWER:
584 f = type_data;
585 return qede_set_flower(edev, f, f->common.protocol);
586 default:
587 return -EOPNOTSUPP;
588 }
589}
590
591static int qede_setup_tc_block(struct qede_dev *edev,
592 struct tc_block_offload *f)
593{
594 if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
595 return -EOPNOTSUPP;
596
597 switch (f->command) {
598 case TC_BLOCK_BIND:
599 return tcf_block_cb_register(f->block,
600 qede_setup_tc_block_cb,
601 edev, edev, f->extack);
602 case TC_BLOCK_UNBIND:
603 tcf_block_cb_unregister(f->block, qede_setup_tc_block_cb, edev);
604 return 0;
605 default:
606 return -EOPNOTSUPP;
607 }
608}
609
5e7baf0f
MC		 610static int
611qede_setup_tc_offload(struct net_device *dev, enum tc_setup_type type,
612 void *type_data)
613{
2ce9c93e 614 struct qede_dev *edev = netdev_priv(dev);
5e7baf0f
MC		 615 struct tc_mqprio_qopt *mqprio;
616
617 switch (type) {
2ce9c93e
MC		 618 case TC_SETUP_BLOCK:
619 return qede_setup_tc_block(edev, type_data);
5e7baf0f
MC		 620 case TC_SETUP_QDISC_MQPRIO:
621 mqprio = type_data;
622
623 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
624 return qede_setup_tc(dev, mqprio->num_tc);
625 default:
626 return -EOPNOTSUPP;
627 }
628}
629
2950219d
YM		 630static const struct net_device_ops qede_netdev_ops = {
631 .ndo_open = qede_open,
632 .ndo_stop = qede_close,
633 .ndo_start_xmit = qede_start_xmit,
0d8e0aa0
SK		 634 .ndo_set_rx_mode = qede_set_rx_mode,
635 .ndo_set_mac_address = qede_set_mac_addr,
2950219d 636 .ndo_validate_addr = eth_validate_addr,
133fac0e 637 .ndo_change_mtu = qede_change_mtu,
4c55215c 638 .ndo_do_ioctl = qede_ioctl,
08feecd7 639#ifdef CONFIG_QED_SRIOV
eff16960 640 .ndo_set_vf_mac = qede_set_vf_mac,
08feecd7 641 .ndo_set_vf_vlan = qede_set_vf_vlan,
f990c82c 642 .ndo_set_vf_trust = qede_set_vf_trust,
08feecd7 643#endif
7c1bfcad
SRK		 644 .ndo_vlan_rx_add_vid = qede_vlan_rx_add_vid,
645 .ndo_vlan_rx_kill_vid = qede_vlan_rx_kill_vid,
18c602de 646 .ndo_fix_features = qede_fix_features,
ce2b885c 647 .ndo_set_features = qede_set_features,
133fac0e 648 .ndo_get_stats64 = qede_get_stats64,
733def6a
YM		 649#ifdef CONFIG_QED_SRIOV
650 .ndo_set_vf_link_state = qede_set_vf_link_state,
6ddc7608 651 .ndo_set_vf_spoofchk = qede_set_vf_spoofchk,
73390ac9 652 .ndo_get_vf_config = qede_get_vf_config,
733def6a
YM		 653 .ndo_set_vf_rate = qede_set_vf_rate,
654#endif
f9f082a9
AD		 655 .ndo_udp_tunnel_add = qede_udp_tunnel_add,
656 .ndo_udp_tunnel_del = qede_udp_tunnel_del,
25695853 657 .ndo_features_check = qede_features_check,
f4e63525 658 .ndo_bpf = qede_xdp,
e4917d46
CM		 659#ifdef CONFIG_RFS_ACCEL
660 .ndo_rx_flow_steer = qede_rx_flow_steer,
661#endif
5e7baf0f 662 .ndo_setup_tc = qede_setup_tc_offload,
2950219d
YM		 663};
664
be47c555
MY		 665static const struct net_device_ops qede_netdev_vf_ops = {
666 .ndo_open = qede_open,
667 .ndo_stop = qede_close,
668 .ndo_start_xmit = qede_start_xmit,
669 .ndo_set_rx_mode = qede_set_rx_mode,
670 .ndo_set_mac_address = qede_set_mac_addr,
671 .ndo_validate_addr = eth_validate_addr,
672 .ndo_change_mtu = qede_change_mtu,
673 .ndo_vlan_rx_add_vid = qede_vlan_rx_add_vid,
674 .ndo_vlan_rx_kill_vid = qede_vlan_rx_kill_vid,
18c602de 675 .ndo_fix_features = qede_fix_features,
be47c555
MY		 676 .ndo_set_features = qede_set_features,
677 .ndo_get_stats64 = qede_get_stats64,
678 .ndo_udp_tunnel_add = qede_udp_tunnel_add,
679 .ndo_udp_tunnel_del = qede_udp_tunnel_del,
680 .ndo_features_check = qede_features_check,
681};
682
e7b80dec
MY		 683static const struct net_device_ops qede_netdev_vf_xdp_ops = {
684 .ndo_open = qede_open,
685 .ndo_stop = qede_close,
686 .ndo_start_xmit = qede_start_xmit,
687 .ndo_set_rx_mode = qede_set_rx_mode,
688 .ndo_set_mac_address = qede_set_mac_addr,
689 .ndo_validate_addr = eth_validate_addr,
690 .ndo_change_mtu = qede_change_mtu,
691 .ndo_vlan_rx_add_vid = qede_vlan_rx_add_vid,
692 .ndo_vlan_rx_kill_vid = qede_vlan_rx_kill_vid,
18c602de 693 .ndo_fix_features = qede_fix_features,
e7b80dec
MY		 694 .ndo_set_features = qede_set_features,
695 .ndo_get_stats64 = qede_get_stats64,
696 .ndo_udp_tunnel_add = qede_udp_tunnel_add,
697 .ndo_udp_tunnel_del = qede_udp_tunnel_del,
698 .ndo_features_check = qede_features_check,
f4e63525 699 .ndo_bpf = qede_xdp,
e7b80dec
MY		 700};
701
e712d52b
YM		 702/* -------------------------------------------------------------------------
703 * START OF PROBE / REMOVE
704 * -------------------------------------------------------------------------
705 */
706
707static struct qede_dev *qede_alloc_etherdev(struct qed_dev *cdev,
708 struct pci_dev *pdev,
709 struct qed_dev_eth_info *info,
1a635e48 710 u32 dp_module, u8 dp_level)
e712d52b
YM		 711{
712 struct net_device *ndev;
713 struct qede_dev *edev;
714
715 ndev = alloc_etherdev_mqs(sizeof(*edev),
5e7baf0f
MC		 716 info->num_queues * info->num_tc,
717 info->num_queues);
e712d52b
YM		 718 if (!ndev) {
719 pr_err("etherdev allocation failed\n");
720 return NULL;
721 }
722
723 edev = netdev_priv(ndev);
724 edev->ndev = ndev;
725 edev->cdev = cdev;
726 edev->pdev = pdev;
727 edev->dp_module = dp_module;
728 edev->dp_level = dp_level;
729 edev->ops = qed_ops;
2950219d
YM		 730 edev->q_num_rx_buffers = NUM_RX_BDS_DEF;
731 edev->q_num_tx_buffers = NUM_TX_BDS_DEF;
e712d52b 732
525ef5c0
YM		 733 DP_INFO(edev, "Allocated netdev with %d tx queues and %d rx queues\n",
734 info->num_queues, info->num_queues);
735
e712d52b
YM		 736 SET_NETDEV_DEV(ndev, &pdev->dev);
737
133fac0e 738 memset(&edev->stats, 0, sizeof(edev->stats));
e712d52b
YM		 739 memcpy(&edev->dev_info, info, sizeof(*info));
740
ba798b5b
MY		 741 /* As ethtool doesn't have the ability to show WoL behavior as
742 * 'default', if device supports it declare it's enabled.
743 */
744 if (edev->dev_info.common.wol_support)
745 edev->wol_enabled = true;
746
7c1bfcad
SRK		 747 INIT_LIST_HEAD(&edev->vlan_list);
748
e712d52b
YM		 749 return edev;
750}
751
752static void qede_init_ndev(struct qede_dev *edev)
753{
754 struct net_device *ndev = edev->ndev;
755 struct pci_dev *pdev = edev->pdev;
19489c7f 756 bool udp_tunnel_enable = false;
e4917d46 757 netdev_features_t hw_features;
e712d52b
YM		 758
759 pci_set_drvdata(pdev, ndev);
760
761 ndev->mem_start = edev->dev_info.common.pci_mem_start;
762 ndev->base_addr = ndev->mem_start;
763 ndev->mem_end = edev->dev_info.common.pci_mem_end;
764 ndev->irq = edev->dev_info.common.pci_irq;
765
766 ndev->watchdog_timeo = TX_TIMEOUT;
767
e7b80dec
MY		 768 if (IS_VF(edev)) {
769 if (edev->dev_info.xdp_supported)
770 ndev->netdev_ops = &qede_netdev_vf_xdp_ops;
771 else
772 ndev->netdev_ops = &qede_netdev_vf_ops;
773 } else {
be47c555 774 ndev->netdev_ops = &qede_netdev_ops;
e7b80dec 775 }
2950219d 776
133fac0e
SK		 777 qede_set_ethtool_ops(ndev);
778
0183eb1c 779 ndev->priv_flags |= IFF_UNICAST_FLT;
7b7e70f9 780
e712d52b 781 /* user-changeble features */
18c602de 782 hw_features = NETIF_F_GRO | NETIF_F_GRO_HW | NETIF_F_SG |
e712d52b 783 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2ce9c93e 784 NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_HW_TC;
e712d52b 785
e4917d46
CM		 786 if (!IS_VF(edev) && edev->dev_info.common.num_hwfns == 1)
787 hw_features |= NETIF_F_NTUPLE;
788
19489c7f
CM		 789 if (edev->dev_info.common.vxlan_enable ||
790 edev->dev_info.common.geneve_enable)
791 udp_tunnel_enable = true;
792
793 if (udp_tunnel_enable || edev->dev_info.common.gre_enable) {
794 hw_features |= NETIF_F_TSO_ECN;
795 ndev->hw_enc_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
796 NETIF_F_SG | NETIF_F_TSO |
797 NETIF_F_TSO_ECN | NETIF_F_TSO6 |
798 NETIF_F_RXCSUM;
799 }
800
801 if (udp_tunnel_enable) {
802 hw_features |= (NETIF_F_GSO_UDP_TUNNEL |
803 NETIF_F_GSO_UDP_TUNNEL_CSUM);
804 ndev->hw_enc_features |= (NETIF_F_GSO_UDP_TUNNEL |
805 NETIF_F_GSO_UDP_TUNNEL_CSUM);
806 }
807
808 if (edev->dev_info.common.gre_enable) {
809 hw_features |= (NETIF_F_GSO_GRE | NETIF_F_GSO_GRE_CSUM);
810 ndev->hw_enc_features |= (NETIF_F_GSO_GRE |
811 NETIF_F_GSO_GRE_CSUM);
812 }
14db81de 813
e712d52b
YM		 814 ndev->vlan_features = hw_features | NETIF_F_RXHASH | NETIF_F_RXCSUM |
815 NETIF_F_HIGHDMA;
816 ndev->features = hw_features | NETIF_F_RXHASH | NETIF_F_RXCSUM |
817 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HIGHDMA |
7c1bfcad 818 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_VLAN_CTAG_TX;
e712d52b
YM		 819
820 ndev->hw_features = hw_features;
821
caff2a87
JW		 822 /* MTU range: 46 - 9600 */
823 ndev->min_mtu = ETH_ZLEN - ETH_HLEN;
824 ndev->max_mtu = QEDE_MAX_JUMBO_PACKET_SIZE;
825
e712d52b
YM		 826 /* Set network device HW mac */
827 ether_addr_copy(edev->ndev->dev_addr, edev->dev_info.common.hw_mac);
0fefbfba
SK		 828
829 ndev->mtu = edev->dev_info.common.mtu;
e712d52b
YM		 830}
831
832/* This function converts from 32b param to two params of level and module
833 * Input 32b decoding:
834 * b31 - enable all NOTICE prints. NOTICE prints are for deviation from the
835 * 'happy' flow, e.g. memory allocation failed.
836 * b30 - enable all INFO prints. INFO prints are for major steps in the flow
837 * and provide important parameters.
838 * b29-b0 - per-module bitmap, where each bit enables VERBOSE prints of that
839 * module. VERBOSE prints are for tracking the specific flow in low level.
840 *
841 * Notice that the level should be that of the lowest required logs.
842 */
133fac0e 843void qede_config_debug(uint debug, u32 *p_dp_module, u8 *p_dp_level)
e712d52b
YM		 844{
845 *p_dp_level = QED_LEVEL_NOTICE;
846 *p_dp_module = 0;
847
848 if (debug & QED_LOG_VERBOSE_MASK) {
849 *p_dp_level = QED_LEVEL_VERBOSE;
850 *p_dp_module = (debug & 0x3FFFFFFF);
851 } else if (debug & QED_LOG_INFO_MASK) {
852 *p_dp_level = QED_LEVEL_INFO;
853 } else if (debug & QED_LOG_NOTICE_MASK) {
854 *p_dp_level = QED_LEVEL_NOTICE;
855 }
856}
857
2950219d
YM		 858static void qede_free_fp_array(struct qede_dev *edev)
859{
860 if (edev->fp_array) {
861 struct qede_fastpath *fp;
862 int i;
863
9a4d7e86 864 for_each_queue(i) {
2950219d
YM		 865 fp = &edev->fp_array[i];
866
867 kfree(fp->sb_info);
c0124f32
JDB		 868 /* Handle mem alloc failure case where qede_init_fp
869 * didn't register xdp_rxq_info yet.
870 * Implicit only (fp->type & QEDE_FASTPATH_RX)
871 */
872 if (fp->rxq && xdp_rxq_info_is_reg(&fp->rxq->xdp_rxq))
873 xdp_rxq_info_unreg(&fp->rxq->xdp_rxq);
2950219d 874 kfree(fp->rxq);
cb6aeb07 875 kfree(fp->xdp_tx);
80439a17 876 kfree(fp->txq);
2950219d
YM		 877 }
878 kfree(edev->fp_array);
879 }
9a4d7e86
SRK		 880
881 edev->num_queues = 0;
882 edev->fp_num_tx = 0;
883 edev->fp_num_rx = 0;
2950219d
YM		 884}
885
886static int qede_alloc_fp_array(struct qede_dev *edev)
887{
9a4d7e86 888 u8 fp_combined, fp_rx = edev->fp_num_rx;
2950219d
YM		 889 struct qede_fastpath *fp;
890 int i;
891
9a4d7e86 892 edev->fp_array = kcalloc(QEDE_QUEUE_CNT(edev),
2950219d
YM		 893 sizeof(*edev->fp_array), GFP_KERNEL);
894 if (!edev->fp_array) {
895 DP_NOTICE(edev, "fp array allocation failed\n");
896 goto err;
897 }
898
9a4d7e86
SRK		 899 fp_combined = QEDE_QUEUE_CNT(edev) - fp_rx - edev->fp_num_tx;
900
901 /* Allocate the FP elements for Rx queues followed by combined and then
902 * the Tx. This ordering should be maintained so that the respective
903 * queues (Rx or Tx) will be together in the fastpath array and the
904 * associated ids will be sequential.
905 */
906 for_each_queue(i) {
2950219d
YM		 907 fp = &edev->fp_array[i];
908
80439a17 909 fp->sb_info = kzalloc(sizeof(*fp->sb_info), GFP_KERNEL);
2950219d
YM		 910 if (!fp->sb_info) {
911 DP_NOTICE(edev, "sb info struct allocation failed\n");
912 goto err;
913 }
914
9a4d7e86
SRK		 915 if (fp_rx) {
916 fp->type = QEDE_FASTPATH_RX;
917 fp_rx--;
918 } else if (fp_combined) {
919 fp->type = QEDE_FASTPATH_COMBINED;
920 fp_combined--;
921 } else {
922 fp->type = QEDE_FASTPATH_TX;
2950219d
YM		 923 }
924
9a4d7e86 925 if (fp->type & QEDE_FASTPATH_TX) {
5e7baf0f
MC		 926 fp->txq = kcalloc(edev->dev_info.num_tc,
927 sizeof(*fp->txq), GFP_KERNEL);
80439a17 928 if (!fp->txq)
9a4d7e86 929 goto err;
9a4d7e86
SRK		 930 }
931
932 if (fp->type & QEDE_FASTPATH_RX) {
80439a17
MY		 933 fp->rxq = kzalloc(sizeof(*fp->rxq), GFP_KERNEL);
934 if (!fp->rxq)
9a4d7e86 935 goto err;
496e0517 936
cb6aeb07
MY		 937 if (edev->xdp_prog) {
938 fp->xdp_tx = kzalloc(sizeof(*fp->xdp_tx),
939 GFP_KERNEL);
940 if (!fp->xdp_tx)
941 goto err;
496e0517 942 fp->type |= QEDE_FASTPATH_XDP;
cb6aeb07 943 }
2950219d
YM		 944 }
945 }
946
947 return 0;
948err:
949 qede_free_fp_array(edev);
950 return -ENOMEM;
951}
952
0d8e0aa0
SK		 953static void qede_sp_task(struct work_struct *work)
954{
955 struct qede_dev *edev = container_of(work, struct qede_dev,
956 sp_task.work);
b18e170c 957
567b3c12 958 __qede_lock(edev);
0d8e0aa0 959
567b3c12
MY		 960 if (test_and_clear_bit(QEDE_SP_RX_MODE, &edev->sp_flags))
961 if (edev->state == QEDE_STATE_OPEN)
0d8e0aa0 962 qede_config_rx_mode(edev->ndev);
0d8e0aa0 963
e4917d46
CM		 964#ifdef CONFIG_RFS_ACCEL
965 if (test_and_clear_bit(QEDE_SP_ARFS_CONFIG, &edev->sp_flags)) {
966 if (edev->state == QEDE_STATE_OPEN)
967 qede_process_arfs_filters(edev, false);
968 }
969#endif
567b3c12 970 __qede_unlock(edev);
0d8e0aa0
SK		 971}
972
e712d52b
YM		 973static void qede_update_pf_params(struct qed_dev *cdev)
974{
975 struct qed_pf_params pf_params;
5e7baf0f 976 u16 num_cons;
e712d52b 977
cb6aeb07 978 /* 64 rx + 64 tx + 64 XDP */
e712d52b 979 memset(&pf_params, 0, sizeof(struct qed_pf_params));
5e7baf0f
MC		 980
981 /* 1 rx + 1 xdp + max tx cos */
982 num_cons = QED_MIN_L2_CONS;
983
984 pf_params.eth_pf_params.num_cons = (MAX_SB_PER_PF_MIMD - 1) * num_cons;
e7b80dec
MY		 985
986 /* Same for VFs - make sure they'll have sufficient connections
987 * to support XDP Tx queues.
988 */
989 pf_params.eth_pf_params.num_vf_cons = 48;
990
e4917d46 991 pf_params.eth_pf_params.num_arfs_filters = QEDE_RFS_MAX_FLTR;
e712d52b
YM		 992 qed_ops->common->update_pf_params(cdev, &pf_params);
993}
994
6bc9f234
MY		 995#define QEDE_FW_VER_STR_SIZE 80
996
997static void qede_log_probe(struct qede_dev *edev)
998{
999 struct qed_dev_info *p_dev_info = &edev->dev_info.common;
1000 u8 buf[QEDE_FW_VER_STR_SIZE];
1001 size_t left_size;
1002
1003 snprintf(buf, QEDE_FW_VER_STR_SIZE,
1004 "Storm FW %d.%d.%d.%d, Management FW %d.%d.%d.%d",
1005 p_dev_info->fw_major, p_dev_info->fw_minor, p_dev_info->fw_rev,
1006 p_dev_info->fw_eng,
1007 (p_dev_info->mfw_rev & QED_MFW_VERSION_3_MASK) >>
1008 QED_MFW_VERSION_3_OFFSET,
1009 (p_dev_info->mfw_rev & QED_MFW_VERSION_2_MASK) >>
1010 QED_MFW_VERSION_2_OFFSET,
1011 (p_dev_info->mfw_rev & QED_MFW_VERSION_1_MASK) >>
1012 QED_MFW_VERSION_1_OFFSET,
1013 (p_dev_info->mfw_rev & QED_MFW_VERSION_0_MASK) >>
1014 QED_MFW_VERSION_0_OFFSET);
1015
1016 left_size = QEDE_FW_VER_STR_SIZE - strlen(buf);
1017 if (p_dev_info->mbi_version && left_size)
1018 snprintf(buf + strlen(buf), left_size,
1019 " [MBI %d.%d.%d]",
1020 (p_dev_info->mbi_version & QED_MBI_VERSION_2_MASK) >>
1021 QED_MBI_VERSION_2_OFFSET,
1022 (p_dev_info->mbi_version & QED_MBI_VERSION_1_MASK) >>
1023 QED_MBI_VERSION_1_OFFSET,
1024 (p_dev_info->mbi_version & QED_MBI_VERSION_0_MASK) >>
1025 QED_MBI_VERSION_0_OFFSET);
1026
1027 pr_info("qede %02x:%02x.%02x: %s [%s]\n", edev->pdev->bus->number,
1028 PCI_SLOT(edev->pdev->devfn), PCI_FUNC(edev->pdev->devfn),
1029 buf, edev->ndev->name);
1030}
1031
e712d52b
YM		 1032enum qede_probe_mode {
1033 QEDE_PROBE_NORMAL,
1034};
1035
1036static int __qede_probe(struct pci_dev *pdev, u32 dp_module, u8 dp_level,
1408cc1f 1037 bool is_vf, enum qede_probe_mode mode)
e712d52b 1038{
1408cc1f 1039 struct qed_probe_params probe_params;
1a635e48 1040 struct qed_slowpath_params sp_params;
e712d52b
YM		 1041 struct qed_dev_eth_info dev_info;
1042 struct qede_dev *edev;
1043 struct qed_dev *cdev;
1044 int rc;
1045
1046 if (unlikely(dp_level & QED_LEVEL_INFO))
1047 pr_notice("Starting qede probe\n");
1048
1408cc1f
YM		 1049 memset(&probe_params, 0, sizeof(probe_params));
1050 probe_params.protocol = QED_PROTOCOL_ETH;
1051 probe_params.dp_module = dp_module;
1052 probe_params.dp_level = dp_level;
1053 probe_params.is_vf = is_vf;
1054 cdev = qed_ops->common->probe(pdev, &probe_params);
e712d52b
YM		 1055 if (!cdev) {
1056 rc = -ENODEV;
1057 goto err0;
1058 }
1059
1060 qede_update_pf_params(cdev);
1061
1062 /* Start the Slowpath-process */
1a635e48
YM		 1063 memset(&sp_params, 0, sizeof(sp_params));
1064 sp_params.int_mode = QED_INT_MODE_MSIX;
1065 sp_params.drv_major = QEDE_MAJOR_VERSION;
1066 sp_params.drv_minor = QEDE_MINOR_VERSION;
1067 sp_params.drv_rev = QEDE_REVISION_VERSION;
1068 sp_params.drv_eng = QEDE_ENGINEERING_VERSION;
1069 strlcpy(sp_params.name, "qede LAN", QED_DRV_VER_STR_SIZE);
1070 rc = qed_ops->common->slowpath_start(cdev, &sp_params);
e712d52b
YM		 1071 if (rc) {
1072 pr_notice("Cannot start slowpath\n");
1073 goto err1;
1074 }
1075
1076 /* Learn information crucial for qede to progress */
1077 rc = qed_ops->fill_dev_info(cdev, &dev_info);
1078 if (rc)
1079 goto err2;
1080
1081 edev = qede_alloc_etherdev(cdev, pdev, &dev_info, dp_module,
1082 dp_level);
1083 if (!edev) {
1084 rc = -ENOMEM;
1085 goto err2;
1086 }
1087
fefb0202
YM		 1088 if (is_vf)
1089 edev->flags |= QEDE_FLAG_IS_VF;
1090
e712d52b
YM		 1091 qede_init_ndev(edev);
1092
bbfcd1e8 1093 rc = qede_rdma_dev_add(edev);
cee9fbd8
RA		 1094 if (rc)
1095 goto err3;
1096
3f2176dd 1097 /* Prepare the lock prior to the registration of the netdev,
0e0b80a9
MY		 1098 * as once it's registered we might reach flows requiring it
1099 * [it's even possible to reach a flow needing it directly
1100 * from there, although it's unlikely].
1101 */
1102 INIT_DELAYED_WORK(&edev->sp_task, qede_sp_task);
1103 mutex_init(&edev->qede_lock);
2950219d
YM		 1104 rc = register_netdev(edev->ndev);
1105 if (rc) {
1106 DP_NOTICE(edev, "Cannot register net-device\n");
cee9fbd8 1107 goto err4;
2950219d
YM		 1108 }
1109
712c3cbf 1110 edev->ops->common->set_name(cdev, edev->ndev->name);
e712d52b 1111
4c55215c 1112 /* PTP not supported on VFs */
03574497 1113 if (!is_vf)
1114 qede_ptp_enable(edev, true);
4c55215c 1115
a2ec6172
SK		 1116 edev->ops->register_ops(cdev, &qede_ll_ops, edev);
1117
489e45ae 1118#ifdef CONFIG_DCB
5fe118c9
SRK		 1119 if (!IS_VF(edev))
1120 qede_set_dcbnl_ops(edev->ndev);
489e45ae
SRK		 1121#endif
1122
3d789994 1123 edev->rx_copybreak = QEDE_RX_HDR_SIZE;
0d8e0aa0 1124
6bc9f234 1125 qede_log_probe(edev);
e712d52b
YM		 1126 return 0;
1127
cee9fbd8 1128err4:
bbfcd1e8 1129 qede_rdma_dev_remove(edev);
2950219d
YM		 1130err3:
1131 free_netdev(edev->ndev);
e712d52b
YM		 1132err2:
1133 qed_ops->common->slowpath_stop(cdev);
1134err1:
1135 qed_ops->common->remove(cdev);
1136err0:
1137 return rc;
1138}
1139
1140static int qede_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1141{
fefb0202 1142 bool is_vf = false;
e712d52b
YM		 1143 u32 dp_module = 0;
1144 u8 dp_level = 0;
1145
fefb0202
YM		 1146 switch ((enum qede_pci_private)id->driver_data) {
1147 case QEDE_PRIVATE_VF:
1148 if (debug & QED_LOG_VERBOSE_MASK)
1149 dev_err(&pdev->dev, "Probing a VF\n");
1150 is_vf = true;
1151 break;
1152 default:
1153 if (debug & QED_LOG_VERBOSE_MASK)
1154 dev_err(&pdev->dev, "Probing a PF\n");
1155 }
1156
e712d52b
YM		 1157 qede_config_debug(debug, &dp_module, &dp_level);
1158
fefb0202 1159 return __qede_probe(pdev, dp_module, dp_level, is_vf,
e712d52b
YM		 1160 QEDE_PROBE_NORMAL);
1161}
1162
1163enum qede_remove_mode {
1164 QEDE_REMOVE_NORMAL,
1165};
1166
1167static void __qede_remove(struct pci_dev *pdev, enum qede_remove_mode mode)
1168{
1169 struct net_device *ndev = pci_get_drvdata(pdev);
1170 struct qede_dev *edev = netdev_priv(ndev);
1171 struct qed_dev *cdev = edev->cdev;
1172
1173 DP_INFO(edev, "Starting qede_remove\n");
1174
91dfd02b 1175 qede_rdma_dev_remove(edev);
2950219d 1176 unregister_netdev(ndev);
e4917d46 1177 cancel_delayed_work_sync(&edev->sp_task);
2950219d 1178
03574497 1179 qede_ptp_disable(edev);
4c55215c 1180
e712d52b
YM		 1181 edev->ops->common->set_power_state(cdev, PCI_D0);
1182
1183 pci_set_drvdata(pdev, NULL);
1184
e712d52b
YM		 1185 /* Use global ops since we've freed edev */
1186 qed_ops->common->slowpath_stop(cdev);
14d39648
MY		 1187 if (system_state == SYSTEM_POWER_OFF)
1188 return;
e712d52b
YM		 1189 qed_ops->common->remove(cdev);
1190
885185df
MY		 1191 /* Since this can happen out-of-sync with other flows,
1192 * don't release the netdevice until after slowpath stop
1193 * has been called to guarantee various other contexts
1194 * [e.g., QED register callbacks] won't break anything when
1195 * accessing the netdevice.
1196 */
1197 free_netdev(ndev);
1198
525ef5c0 1199 dev_info(&pdev->dev, "Ending qede_remove successfully\n");
e712d52b
YM		 1200}
1201
1202static void qede_remove(struct pci_dev *pdev)
1203{
1204 __qede_remove(pdev, QEDE_REMOVE_NORMAL);
1205}
2950219d 1206
14d39648
MY		 1207static void qede_shutdown(struct pci_dev *pdev)
1208{
1209 __qede_remove(pdev, QEDE_REMOVE_NORMAL);
1210}
1211
2950219d
YM		 1212/* -------------------------------------------------------------------------
1213 * START OF LOAD / UNLOAD
1214 * -------------------------------------------------------------------------
1215 */
1216
1217static int qede_set_num_queues(struct qede_dev *edev)
1218{
1219 int rc;
1220 u16 rss_num;
1221
1222 /* Setup queues according to possible resources*/
9a4d7e86
SRK		 1223 if (edev->req_queues)
1224 rss_num = edev->req_queues;
8edf049d
SK		 1225 else
1226 rss_num = netif_get_num_default_rss_queues() *
1227 edev->dev_info.common.num_hwfns;
2950219d
YM		 1228
1229 rss_num = min_t(u16, QEDE_MAX_RSS_CNT(edev), rss_num);
1230
1231 rc = edev->ops->common->set_fp_int(edev->cdev, rss_num);
1232 if (rc > 0) {
1233 /* Managed to request interrupts for our queues */
9a4d7e86 1234 edev->num_queues = rc;
2950219d 1235 DP_INFO(edev, "Managed %d [of %d] RSS queues\n",
9a4d7e86 1236 QEDE_QUEUE_CNT(edev), rss_num);
2950219d
YM		 1237 rc = 0;
1238 }
9a4d7e86
SRK		 1239
1240 edev->fp_num_tx = edev->req_num_tx;
1241 edev->fp_num_rx = edev->req_num_rx;
1242
2950219d
YM		 1243 return rc;
1244}
1245
71851ea5
SRK		 1246static void qede_free_mem_sb(struct qede_dev *edev, struct qed_sb_info *sb_info,
1247 u16 sb_id)
2950219d 1248{
71851ea5
SRK		 1249 if (sb_info->sb_virt) {
1250 edev->ops->common->sb_release(edev->cdev, sb_info, sb_id);
2950219d
YM		 1251 dma_free_coherent(&edev->pdev->dev, sizeof(*sb_info->sb_virt),
1252 (void *)sb_info->sb_virt, sb_info->sb_phys);
71851ea5
SRK		 1253 memset(sb_info, 0, sizeof(*sb_info));
1254 }
2950219d
YM		 1255}
1256
1257/* This function allocates fast-path status block memory */
1258static int qede_alloc_mem_sb(struct qede_dev *edev,
1a635e48 1259 struct qed_sb_info *sb_info, u16 sb_id)
2950219d 1260{
21dd79e8 1261 struct status_block_e4 *sb_virt;
2950219d
YM		 1262 dma_addr_t sb_phys;
1263 int rc;
1264
1265 sb_virt = dma_alloc_coherent(&edev->pdev->dev,
1a635e48 1266 sizeof(*sb_virt), &sb_phys, GFP_KERNEL);
2950219d
YM		 1267 if (!sb_virt) {
1268 DP_ERR(edev, "Status block allocation failed\n");
1269 return -ENOMEM;
1270 }
1271
1272 rc = edev->ops->common->sb_init(edev->cdev, sb_info,
1273 sb_virt, sb_phys, sb_id,
1274 QED_SB_TYPE_L2_QUEUE);
1275 if (rc) {
1276 DP_ERR(edev, "Status block initialization failed\n");
1277 dma_free_coherent(&edev->pdev->dev, sizeof(*sb_virt),
1278 sb_virt, sb_phys);
1279 return rc;
1280 }
1281
1282 return 0;
1283}
1284
1285static void qede_free_rx_buffers(struct qede_dev *edev,
1286 struct qede_rx_queue *rxq)
1287{
1288 u16 i;
1289
1290 for (i = rxq->sw_rx_cons; i != rxq->sw_rx_prod; i++) {
1291 struct sw_rx_data *rx_buf;
fc48b7a6 1292 struct page *data;
2950219d
YM		 1293
1294 rx_buf = &rxq->sw_rx_ring[i & NUM_RX_BDS_MAX];
1295 data = rx_buf->data;
1296
fc48b7a6 1297 dma_unmap_page(&edev->pdev->dev,
cb6aeb07 1298 rx_buf->mapping, PAGE_SIZE, rxq->data_direction);
2950219d
YM		 1299
1300 rx_buf->data = NULL;
fc48b7a6 1301 __free_page(data);
2950219d
YM		 1302 }
1303}
1304
1a635e48 1305static void qede_free_mem_rxq(struct qede_dev *edev, struct qede_rx_queue *rxq)
2950219d
YM		 1306{
1307 /* Free rx buffers */
1308 qede_free_rx_buffers(edev, rxq);
1309
1310 /* Free the parallel SW ring */
1311 kfree(rxq->sw_rx_ring);
1312
1313 /* Free the real RQ ring used by FW */
1314 edev->ops->common->chain_free(edev->cdev, &rxq->rx_bd_ring);
1315 edev->ops->common->chain_free(edev->cdev, &rxq->rx_comp_ring);
1316}
1317
8a863397 1318static void qede_set_tpa_param(struct qede_rx_queue *rxq)
55482edc 1319{
55482edc
MC		 1320 int i;
1321
55482edc
MC		 1322 for (i = 0; i < ETH_TPA_MAX_AGGS_NUM; i++) {
1323 struct qede_agg_info *tpa_info = &rxq->tpa_info[i];
55482edc 1324
01e23015 1325 tpa_info->state = QEDE_AGG_STATE_NONE;
55482edc 1326 }
55482edc
MC		 1327}
1328
2950219d 1329/* This function allocates all memory needed per Rx queue */
1a635e48 1330static int qede_alloc_mem_rxq(struct qede_dev *edev, struct qede_rx_queue *rxq)
2950219d 1331{
f86af2df 1332 int i, rc, size;
2950219d
YM		 1333
1334 rxq->num_rx_buffers = edev->q_num_rx_buffers;
1335
1a635e48 1336 rxq->rx_buf_size = NET_IP_ALIGN + ETH_OVERHEAD + edev->ndev->mtu;
8a863397
MC		 1337
1338 rxq->rx_headroom = edev->xdp_prog ? XDP_PACKET_HEADROOM : NET_SKB_PAD;
1339 size = rxq->rx_headroom +
1340 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
1a635e48 1341
15ed8a47 1342 /* Make sure that the headroom and payload fit in a single page */
8a863397
MC		 1343 if (rxq->rx_buf_size + size > PAGE_SIZE)
1344 rxq->rx_buf_size = PAGE_SIZE - size;
fc48b7a6 1345
8a863397 1346 /* Segment size to spilt a page in multiple equal parts ,
496e0517
MY		 1347 * unless XDP is used in which case we'd use the entire page.
1348 */
8a863397
MC		 1349 if (!edev->xdp_prog) {
1350 size = size + rxq->rx_buf_size;
1351 rxq->rx_buf_seg_size = roundup_pow_of_two(size);
1352 } else {
496e0517 1353 rxq->rx_buf_seg_size = PAGE_SIZE;
8a863397 1354 }
2950219d
YM		 1355
1356 /* Allocate the parallel driver ring for Rx buffers */
fc48b7a6 1357 size = sizeof(*rxq->sw_rx_ring) * RX_RING_SIZE;
2950219d
YM		 1358 rxq->sw_rx_ring = kzalloc(size, GFP_KERNEL);
1359 if (!rxq->sw_rx_ring) {
1360 DP_ERR(edev, "Rx buffers ring allocation failed\n");
f86af2df 1361 rc = -ENOMEM;
2950219d
YM		 1362 goto err;
1363 }
1364
1365 /* Allocate FW Rx ring */
1366 rc = edev->ops->common->chain_alloc(edev->cdev,
1367 QED_CHAIN_USE_TO_CONSUME_PRODUCE,
1368 QED_CHAIN_MODE_NEXT_PTR,
a91eb52a 1369 QED_CHAIN_CNT_TYPE_U16,
fc48b7a6 1370 RX_RING_SIZE,
2950219d 1371 sizeof(struct eth_rx_bd),
1a4a6975 1372 &rxq->rx_bd_ring, NULL);
2950219d
YM		 1373 if (rc)
1374 goto err;
1375
1376 /* Allocate FW completion ring */
1377 rc = edev->ops->common->chain_alloc(edev->cdev,
1378 QED_CHAIN_USE_TO_CONSUME,
1379 QED_CHAIN_MODE_PBL,
a91eb52a 1380 QED_CHAIN_CNT_TYPE_U16,
fc48b7a6 1381 RX_RING_SIZE,
2950219d 1382 sizeof(union eth_rx_cqe),
1a4a6975 1383 &rxq->rx_comp_ring, NULL);
2950219d
YM		 1384 if (rc)
1385 goto err;
1386
1387 /* Allocate buffers for the Rx ring */
e3eef7ee 1388 rxq->filled_buffers = 0;
2950219d 1389 for (i = 0; i < rxq->num_rx_buffers; i++) {
e3eef7ee 1390 rc = qede_alloc_rx_buffer(rxq, false);
f86af2df
MC		 1391 if (rc) {
1392 DP_ERR(edev,
1393 "Rx buffers allocation failed at index %d\n", i);
1394 goto err;
1395 }
2950219d
YM		 1396 }
1397
8a863397
MC		 1398 if (!edev->gro_disable)
1399 qede_set_tpa_param(rxq);
2950219d 1400err:
f86af2df 1401 return rc;
2950219d
YM		 1402}
1403
1a635e48 1404static void qede_free_mem_txq(struct qede_dev *edev, struct qede_tx_queue *txq)
2950219d
YM		 1405{
1406 /* Free the parallel SW ring */
cb6aeb07 1407 if (txq->is_xdp)
89e1afc4 1408 kfree(txq->sw_tx_ring.xdp);
cb6aeb07
MY		 1409 else
1410 kfree(txq->sw_tx_ring.skbs);
2950219d
YM		 1411
1412 /* Free the real RQ ring used by FW */
1413 edev->ops->common->chain_free(edev->cdev, &txq->tx_pbl);
1414}
1415
1416/* This function allocates all memory needed per Tx queue */
1a635e48 1417static int qede_alloc_mem_txq(struct qede_dev *edev, struct qede_tx_queue *txq)
2950219d 1418{
2950219d 1419 union eth_tx_bd_types *p_virt;
cb6aeb07 1420 int size, rc;
2950219d
YM		 1421
1422 txq->num_tx_buffers = edev->q_num_tx_buffers;
1423
1424 /* Allocate the parallel driver ring for Tx buffers */
cb6aeb07 1425 if (txq->is_xdp) {
5a052d62 1426 size = sizeof(*txq->sw_tx_ring.xdp) * txq->num_tx_buffers;
89e1afc4
MY		 1427 txq->sw_tx_ring.xdp = kzalloc(size, GFP_KERNEL);
1428 if (!txq->sw_tx_ring.xdp)
cb6aeb07
MY		 1429 goto err;
1430 } else {
5a052d62 1431 size = sizeof(*txq->sw_tx_ring.skbs) * txq->num_tx_buffers;
cb6aeb07
MY		 1432 txq->sw_tx_ring.skbs = kzalloc(size, GFP_KERNEL);
1433 if (!txq->sw_tx_ring.skbs)
1434 goto err;
2950219d
YM		 1435 }
1436
1437 rc = edev->ops->common->chain_alloc(edev->cdev,
1438 QED_CHAIN_USE_TO_CONSUME_PRODUCE,
1439 QED_CHAIN_MODE_PBL,
a91eb52a 1440 QED_CHAIN_CNT_TYPE_U16,
5a052d62 1441 txq->num_tx_buffers,
1a4a6975
MY		 1442 sizeof(*p_virt),
1443 &txq->tx_pbl, NULL);
2950219d
YM		 1444 if (rc)
1445 goto err;
1446
1447 return 0;
1448
1449err:
1450 qede_free_mem_txq(edev, txq);
1451 return -ENOMEM;
1452}
1453
1454/* This function frees all memory of a single fp */
1a635e48 1455static void qede_free_mem_fp(struct qede_dev *edev, struct qede_fastpath *fp)
2950219d 1456{
71851ea5 1457 qede_free_mem_sb(edev, fp->sb_info, fp->id);
2950219d 1458
9a4d7e86
SRK		 1459 if (fp->type & QEDE_FASTPATH_RX)
1460 qede_free_mem_rxq(edev, fp->rxq);
2950219d 1461
92c43eb4
SRK		 1462 if (fp->type & QEDE_FASTPATH_XDP)
1463 qede_free_mem_txq(edev, fp->xdp_tx);
1464
5e7baf0f
MC		 1465 if (fp->type & QEDE_FASTPATH_TX) {
1466 int cos;
1467
1468 for_each_cos_in_txq(edev, cos)
1469 qede_free_mem_txq(edev, &fp->txq[cos]);
1470 }
2950219d
YM		 1471}
1472
1473/* This function allocates all memory needed for a single fp (i.e. an entity
9a4d7e86 1474 * which contains status block, one rx queue and/or multiple per-TC tx queues.
2950219d 1475 */
1a635e48 1476static int qede_alloc_mem_fp(struct qede_dev *edev, struct qede_fastpath *fp)
2950219d 1477{
cb6aeb07 1478 int rc = 0;
2950219d 1479
9a4d7e86 1480 rc = qede_alloc_mem_sb(edev, fp->sb_info, fp->id);
2950219d 1481 if (rc)
cb6aeb07 1482 goto out;
2950219d 1483
9a4d7e86
SRK		 1484 if (fp->type & QEDE_FASTPATH_RX) {
1485 rc = qede_alloc_mem_rxq(edev, fp->rxq);
2950219d 1486 if (rc)
cb6aeb07
MY		 1487 goto out;
1488 }
1489
1490 if (fp->type & QEDE_FASTPATH_XDP) {
1491 rc = qede_alloc_mem_txq(edev, fp->xdp_tx);
1492 if (rc)
1493 goto out;
2950219d
YM		 1494 }
1495
9a4d7e86 1496 if (fp->type & QEDE_FASTPATH_TX) {
5e7baf0f
MC		 1497 int cos;
1498
1499 for_each_cos_in_txq(edev, cos) {
1500 rc = qede_alloc_mem_txq(edev, &fp->txq[cos]);
1501 if (rc)
1502 goto out;
1503 }
9a4d7e86
SRK		 1504 }
1505
cb6aeb07 1506out:
f86af2df 1507 return rc;
2950219d
YM		 1508}
1509
1510static void qede_free_mem_load(struct qede_dev *edev)
1511{
1512 int i;
1513
9a4d7e86 1514 for_each_queue(i) {
2950219d
YM		 1515 struct qede_fastpath *fp = &edev->fp_array[i];
1516
1517 qede_free_mem_fp(edev, fp);
1518 }
1519}
1520
1521/* This function allocates all qede memory at NIC load. */
1522static int qede_alloc_mem_load(struct qede_dev *edev)
1523{
9a4d7e86 1524 int rc = 0, queue_id;
2950219d 1525
9a4d7e86
SRK		 1526 for (queue_id = 0; queue_id < QEDE_QUEUE_CNT(edev); queue_id++) {
1527 struct qede_fastpath *fp = &edev->fp_array[queue_id];
2950219d
YM		 1528
1529 rc = qede_alloc_mem_fp(edev, fp);
f86af2df 1530 if (rc) {
2950219d 1531 DP_ERR(edev,
f86af2df 1532 "Failed to allocate memory for fastpath - rss id = %d\n",
9a4d7e86 1533 queue_id);
f86af2df
MC		 1534 qede_free_mem_load(edev);
1535 return rc;
2950219d 1536 }
2950219d
YM		 1537 }
1538
1539 return 0;
1540}
1541
1542/* This function inits fp content and resets the SB, RXQ and TXQ structures */
1543static void qede_init_fp(struct qede_dev *edev)
1544{
80439a17 1545 int queue_id, rxq_index = 0, txq_index = 0;
2950219d
YM		 1546 struct qede_fastpath *fp;
1547
9a4d7e86
SRK		 1548 for_each_queue(queue_id) {
1549 fp = &edev->fp_array[queue_id];
2950219d
YM		 1550
1551 fp->edev = edev;
9a4d7e86 1552 fp->id = queue_id;
2950219d 1553
cb6aeb07
MY		 1554 if (fp->type & QEDE_FASTPATH_XDP) {
1555 fp->xdp_tx->index = QEDE_TXQ_IDX_TO_XDP(edev,
1556 rxq_index);
1557 fp->xdp_tx->is_xdp = 1;
1558 }
2950219d 1559
9a4d7e86 1560 if (fp->type & QEDE_FASTPATH_RX) {
9a4d7e86 1561 fp->rxq->rxq_id = rxq_index++;
cb6aeb07
MY		 1562
1563 /* Determine how to map buffers for this queue */
1564 if (fp->type & QEDE_FASTPATH_XDP)
1565 fp->rxq->data_direction = DMA_BIDIRECTIONAL;
1566 else
1567 fp->rxq->data_direction = DMA_FROM_DEVICE;
9eb22357 1568 fp->rxq->dev = &edev->pdev->dev;
c0124f32
JDB		 1569
1570 /* Driver have no error path from here */
1571 WARN_ON(xdp_rxq_info_reg(&fp->rxq->xdp_rxq, edev->ndev,
1572 fp->rxq->rxq_id) < 0);
9a4d7e86 1573 }
2950219d 1574
9a4d7e86 1575 if (fp->type & QEDE_FASTPATH_TX) {
5e7baf0f
MC		 1576 int cos;
1577
1578 for_each_cos_in_txq(edev, cos) {
1579 struct qede_tx_queue *txq = &fp->txq[cos];
1580 u16 ndev_tx_id;
1581
1582 txq->cos = cos;
1583 txq->index = txq_index;
1584 ndev_tx_id = QEDE_TXQ_TO_NDEV_TXQ_ID(edev, txq);
1585 txq->ndev_txq_id = ndev_tx_id;
1586
1587 if (edev->dev_info.is_legacy)
1588 txq->is_legacy = 1;
1589 txq->dev = &edev->pdev->dev;
1590 }
1591
1592 txq_index++;
2950219d
YM		 1593 }
1594
1595 snprintf(fp->name, sizeof(fp->name), "%s-fp-%d",
9a4d7e86 1596 edev->ndev->name, queue_id);
2950219d 1597 }
55482edc 1598
18c602de 1599 edev->gro_disable = !(edev->ndev->features & NETIF_F_GRO_HW);
2950219d
YM		 1600}
1601
1602static int qede_set_real_num_queues(struct qede_dev *edev)
1603{
1604 int rc = 0;
1605
5e7baf0f
MC		 1606 rc = netif_set_real_num_tx_queues(edev->ndev,
1607 QEDE_TSS_COUNT(edev) *
1608 edev->dev_info.num_tc);
2950219d
YM		 1609 if (rc) {
1610 DP_NOTICE(edev, "Failed to set real number of Tx queues\n");
1611 return rc;
1612 }
9a4d7e86
SRK		 1613
1614 rc = netif_set_real_num_rx_queues(edev->ndev, QEDE_RSS_COUNT(edev));
2950219d
YM		 1615 if (rc) {
1616 DP_NOTICE(edev, "Failed to set real number of Rx queues\n");
1617 return rc;
1618 }
1619
1620 return 0;
1621}
1622
1623static void qede_napi_disable_remove(struct qede_dev *edev)
1624{
1625 int i;
1626
9a4d7e86 1627 for_each_queue(i) {
2950219d
YM		 1628 napi_disable(&edev->fp_array[i].napi);
1629
1630 netif_napi_del(&edev->fp_array[i].napi);
1631 }
1632}
1633
1634static void qede_napi_add_enable(struct qede_dev *edev)
1635{
1636 int i;
1637
1638 /* Add NAPI objects */
9a4d7e86 1639 for_each_queue(i) {
2950219d
YM		 1640 netif_napi_add(edev->ndev, &edev->fp_array[i].napi,
1641 qede_poll, NAPI_POLL_WEIGHT);
1642 napi_enable(&edev->fp_array[i].napi);
1643 }
1644}
1645
1646static void qede_sync_free_irqs(struct qede_dev *edev)
1647{
1648 int i;
1649
1650 for (i = 0; i < edev->int_info.used_cnt; i++) {
1651 if (edev->int_info.msix_cnt) {
1652 synchronize_irq(edev->int_info.msix[i].vector);
1653 free_irq(edev->int_info.msix[i].vector,
1654 &edev->fp_array[i]);
1655 } else {
1656 edev->ops->common->simd_handler_clean(edev->cdev, i);
1657 }
1658 }
1659
1660 edev->int_info.used_cnt = 0;
1661}
1662
1663static int qede_req_msix_irqs(struct qede_dev *edev)
1664{
1665 int i, rc;
1666
1667 /* Sanitize number of interrupts == number of prepared RSS queues */
9a4d7e86 1668 if (QEDE_QUEUE_CNT(edev) > edev->int_info.msix_cnt) {
2950219d
YM		 1669 DP_ERR(edev,
1670 "Interrupt mismatch: %d RSS queues > %d MSI-x vectors\n",
9a4d7e86 1671 QEDE_QUEUE_CNT(edev), edev->int_info.msix_cnt);
2950219d
YM		 1672 return -EINVAL;
1673 }
1674
9a4d7e86 1675 for (i = 0; i < QEDE_QUEUE_CNT(edev); i++) {
e4917d46
CM		 1676#ifdef CONFIG_RFS_ACCEL
1677 struct qede_fastpath *fp = &edev->fp_array[i];
1678
1679 if (edev->ndev->rx_cpu_rmap && (fp->type & QEDE_FASTPATH_RX)) {
1680 rc = irq_cpu_rmap_add(edev->ndev->rx_cpu_rmap,
1681 edev->int_info.msix[i].vector);
1682 if (rc) {
1683 DP_ERR(edev, "Failed to add CPU rmap\n");
1684 qede_free_arfs(edev);
1685 }
1686 }
1687#endif
2950219d
YM		 1688 rc = request_irq(edev->int_info.msix[i].vector,
1689 qede_msix_fp_int, 0, edev->fp_array[i].name,
1690 &edev->fp_array[i]);
1691 if (rc) {
1692 DP_ERR(edev, "Request fp %d irq failed\n", i);
1693 qede_sync_free_irqs(edev);
1694 return rc;
1695 }
1696 DP_VERBOSE(edev, NETIF_MSG_INTR,
1697 "Requested fp irq for %s [entry %d]. Cookie is at %p\n",
1698 edev->fp_array[i].name, i,
1699 &edev->fp_array[i]);
1700 edev->int_info.used_cnt++;
1701 }
1702
1703 return 0;
1704}
1705
1706static void qede_simd_fp_handler(void *cookie)
1707{
1708 struct qede_fastpath *fp = (struct qede_fastpath *)cookie;
1709
1710 napi_schedule_irqoff(&fp->napi);
1711}
1712
1713static int qede_setup_irqs(struct qede_dev *edev)
1714{
1715 int i, rc = 0;
1716
1717 /* Learn Interrupt configuration */
1718 rc = edev->ops->common->get_fp_int(edev->cdev, &edev->int_info);
1719 if (rc)
1720 return rc;
1721
1722 if (edev->int_info.msix_cnt) {
1723 rc = qede_req_msix_irqs(edev);
1724 if (rc)
1725 return rc;
1726 edev->ndev->irq = edev->int_info.msix[0].vector;
1727 } else {
1728 const struct qed_common_ops *ops;
1729
1730 /* qed should learn receive the RSS ids and callbacks */
1731 ops = edev->ops->common;
9a4d7e86 1732 for (i = 0; i < QEDE_QUEUE_CNT(edev); i++)
2950219d
YM		 1733 ops->simd_handler_config(edev->cdev,
1734 &edev->fp_array[i], i,
1735 qede_simd_fp_handler);
9a4d7e86 1736 edev->int_info.used_cnt = QEDE_QUEUE_CNT(edev);
2950219d
YM		 1737 }
1738 return 0;
1739}
1740
1741static int qede_drain_txq(struct qede_dev *edev,
1a635e48 1742 struct qede_tx_queue *txq, bool allow_drain)
2950219d
YM		 1743{
1744 int rc, cnt = 1000;
1745
1746 while (txq->sw_tx_cons != txq->sw_tx_prod) {
1747 if (!cnt) {
1748 if (allow_drain) {
1749 DP_NOTICE(edev,
1750 "Tx queue[%d] is stuck, requesting MCP to drain\n",
1751 txq->index);
1752 rc = edev->ops->common->drain(edev->cdev);
1753 if (rc)
1754 return rc;
1755 return qede_drain_txq(edev, txq, false);
1756 }
1757 DP_NOTICE(edev,
1758 "Timeout waiting for tx queue[%d]: PROD=%d, CONS=%d\n",
1759 txq->index, txq->sw_tx_prod,
1760 txq->sw_tx_cons);
1761 return -ENODEV;
1762 }
1763 cnt--;
1764 usleep_range(1000, 2000);
1765 barrier();
1766 }
1767
1768 /* FW finished processing, wait for HW to transmit all tx packets */
1769 usleep_range(1000, 2000);
1770
1771 return 0;
1772}
1773
3da7a37a
MY		 1774static int qede_stop_txq(struct qede_dev *edev,
1775 struct qede_tx_queue *txq, int rss_id)
1776{
1777 return edev->ops->q_tx_stop(edev->cdev, rss_id, txq->handle);
1778}
1779
2950219d
YM		 1780static int qede_stop_queues(struct qede_dev *edev)
1781{
f29ffdb6 1782 struct qed_update_vport_params *vport_update_params;
2950219d 1783 struct qed_dev *cdev = edev->cdev;
80439a17
MY		 1784 struct qede_fastpath *fp;
1785 int rc, i;
2950219d
YM		 1786
1787 /* Disable the vport */
f29ffdb6
MY		 1788 vport_update_params = vzalloc(sizeof(*vport_update_params));
1789 if (!vport_update_params)
1790 return -ENOMEM;
1791
1792 vport_update_params->vport_id = 0;
1793 vport_update_params->update_vport_active_flg = 1;
1794 vport_update_params->vport_active_flg = 0;
1795 vport_update_params->update_rss_flg = 0;
1796
1797 rc = edev->ops->vport_update(cdev, vport_update_params);
1798 vfree(vport_update_params);
2950219d 1799
2950219d
YM		 1800 if (rc) {
1801 DP_ERR(edev, "Failed to update vport\n");
1802 return rc;
1803 }
1804
1805 /* Flush Tx queues. If needed, request drain from MCP */
9a4d7e86 1806 for_each_queue(i) {
80439a17 1807 fp = &edev->fp_array[i];
2950219d 1808
9a4d7e86 1809 if (fp->type & QEDE_FASTPATH_TX) {
5e7baf0f
MC		 1810 int cos;
1811
1812 for_each_cos_in_txq(edev, cos) {
1813 rc = qede_drain_txq(edev, &fp->txq[cos], true);
1814 if (rc)
1815 return rc;
1816 }
2950219d 1817 }
cb6aeb07
MY		 1818
1819 if (fp->type & QEDE_FASTPATH_XDP) {
1820 rc = qede_drain_txq(edev, fp->xdp_tx, true);
1821 if (rc)
1822 return rc;
1823 }
2950219d
YM		 1824 }
1825
9a4d7e86
SRK		 1826 /* Stop all Queues in reverse order */
1827 for (i = QEDE_QUEUE_CNT(edev) - 1; i >= 0; i--) {
80439a17
MY		 1828 fp = &edev->fp_array[i];
1829
9a4d7e86 1830 /* Stop the Tx Queue(s) */
80439a17 1831 if (fp->type & QEDE_FASTPATH_TX) {
5e7baf0f
MC		 1832 int cos;
1833
1834 for_each_cos_in_txq(edev, cos) {
1835 rc = qede_stop_txq(edev, &fp->txq[cos], i);
1836 if (rc)
1837 return rc;
1838 }
2950219d
YM		 1839 }
1840
9a4d7e86 1841 /* Stop the Rx Queue */
80439a17 1842 if (fp->type & QEDE_FASTPATH_RX) {
3da7a37a 1843 rc = edev->ops->q_rx_stop(cdev, i, fp->rxq->handle);
9a4d7e86
SRK		 1844 if (rc) {
1845 DP_ERR(edev, "Failed to stop RXQ #%d\n", i);
1846 return rc;
1847 }
2950219d 1848 }
496e0517 1849
cb6aeb07
MY		 1850 /* Stop the XDP forwarding queue */
1851 if (fp->type & QEDE_FASTPATH_XDP) {
1852 rc = qede_stop_txq(edev, fp->xdp_tx, i);
1853 if (rc)
1854 return rc;
1855
496e0517 1856 bpf_prog_put(fp->rxq->xdp_prog);
cb6aeb07 1857 }
2950219d
YM		 1858 }
1859
1860 /* Stop the vport */
1861 rc = edev->ops->vport_stop(cdev, 0);
1862 if (rc)
1863 DP_ERR(edev, "Failed to stop VPORT\n");
1864
1865 return rc;
1866}
1867
3da7a37a
MY		 1868static int qede_start_txq(struct qede_dev *edev,
1869 struct qede_fastpath *fp,
1870 struct qede_tx_queue *txq, u8 rss_id, u16 sb_idx)
1871{
1872 dma_addr_t phys_table = qed_chain_get_pbl_phys(&txq->tx_pbl);
1873 u32 page_cnt = qed_chain_get_page_cnt(&txq->tx_pbl);
1874 struct qed_queue_start_common_params params;
1875 struct qed_txq_start_ret_params ret_params;
1876 int rc;
1877
1878 memset(&params, 0, sizeof(params));
1879 memset(&ret_params, 0, sizeof(ret_params));
1880
cb6aeb07
MY		 1881 /* Let the XDP queue share the queue-zone with one of the regular txq.
1882 * We don't really care about its coalescing.
1883 */
1884 if (txq->is_xdp)
1885 params.queue_id = QEDE_TXQ_XDP_TO_IDX(edev, txq);
1886 else
1887 params.queue_id = txq->index;
1888
f604b17d 1889 params.p_sb = fp->sb_info;
3da7a37a 1890 params.sb_idx = sb_idx;
5e7baf0f 1891 params.tc = txq->cos;
3da7a37a
MY		 1892
1893 rc = edev->ops->q_tx_start(edev->cdev, rss_id, &params, phys_table,
1894 page_cnt, &ret_params);
1895 if (rc) {
1896 DP_ERR(edev, "Start TXQ #%d failed %d\n", txq->index, rc);
1897 return rc;
1898 }
1899
1900 txq->doorbell_addr = ret_params.p_doorbell;
1901 txq->handle = ret_params.p_handle;
1902
1903 /* Determine the FW consumer address associated */
1904 txq->hw_cons_ptr = &fp->sb_info->sb_virt->pi_array[sb_idx];
1905
1906 /* Prepare the doorbell parameters */
1907 SET_FIELD(txq->tx_db.data.params, ETH_DB_DATA_DEST, DB_DEST_XCM);
1908 SET_FIELD(txq->tx_db.data.params, ETH_DB_DATA_AGG_CMD, DB_AGG_CMD_SET);
1909 SET_FIELD(txq->tx_db.data.params, ETH_DB_DATA_AGG_VAL_SEL,
1910 DQ_XCM_ETH_TX_BD_PROD_CMD);
1911 txq->tx_db.data.agg_flags = DQ_XCM_ETH_DQ_CF_CMD;
1912
1913 return rc;
1914}
1915
a0d26d5a 1916static int qede_start_queues(struct qede_dev *edev, bool clear_stats)
2950219d 1917{
088c8618 1918 int vlan_removal_en = 1;
2950219d 1919 struct qed_dev *cdev = edev->cdev;
fefb0202 1920 struct qed_dev_info *qed_info = &edev->dev_info.common;
f29ffdb6
MY		 1921 struct qed_update_vport_params *vport_update_params;
1922 struct qed_queue_start_common_params q_params;
088c8618 1923 struct qed_start_vport_params start = {0};
80439a17 1924 int rc, i;
2950219d 1925
9a4d7e86 1926 if (!edev->num_queues) {
2950219d
YM		 1927 DP_ERR(edev,
1928 "Cannot update V-VPORT as active as there are no Rx queues\n");
1929 return -EINVAL;
1930 }
1931
f29ffdb6
MY		 1932 vport_update_params = vzalloc(sizeof(*vport_update_params));
1933 if (!vport_update_params)
1934 return -ENOMEM;
1935
4c55215c 1936 start.handle_ptp_pkts = !!(edev->ptp);
55482edc 1937 start.gro_enable = !edev->gro_disable;
088c8618
MC		 1938 start.mtu = edev->ndev->mtu;
1939 start.vport_id = 0;
1940 start.drop_ttl0 = true;
1941 start.remove_inner_vlan = vlan_removal_en;
7f7a144f 1942 start.clear_stats = clear_stats;
088c8618
MC		 1943
1944 rc = edev->ops->vport_start(cdev, &start);
2950219d
YM		 1945
1946 if (rc) {
1947 DP_ERR(edev, "Start V-PORT failed %d\n", rc);
f29ffdb6 1948 goto out;
2950219d
YM		 1949 }
1950
1951 DP_VERBOSE(edev, NETIF_MSG_IFUP,
1952 "Start vport ramrod passed, vport_id = %d, MTU = %d, vlan_removal_en = %d\n",
088c8618 1953 start.vport_id, edev->ndev->mtu + 0xe, vlan_removal_en);
2950219d 1954
9a4d7e86 1955 for_each_queue(i) {
2950219d 1956 struct qede_fastpath *fp = &edev->fp_array[i];
9a4d7e86
SRK		 1957 dma_addr_t p_phys_table;
1958 u32 page_cnt;
2950219d 1959
9a4d7e86 1960 if (fp->type & QEDE_FASTPATH_RX) {
3da7a37a 1961 struct qed_rxq_start_ret_params ret_params;
9a4d7e86
SRK		 1962 struct qede_rx_queue *rxq = fp->rxq;
1963 __le16 *val;
2950219d 1964
3da7a37a 1965 memset(&ret_params, 0, sizeof(ret_params));
9a4d7e86 1966 memset(&q_params, 0, sizeof(q_params));
9a4d7e86
SRK		 1967 q_params.queue_id = rxq->rxq_id;
1968 q_params.vport_id = 0;
f604b17d 1969 q_params.p_sb = fp->sb_info;
9a4d7e86
SRK		 1970 q_params.sb_idx = RX_PI;
1971
1972 p_phys_table =
1973 qed_chain_get_pbl_phys(&rxq->rx_comp_ring);
1974 page_cnt = qed_chain_get_page_cnt(&rxq->rx_comp_ring);
1975
3da7a37a 1976 rc = edev->ops->q_rx_start(cdev, i, &q_params,
9a4d7e86
SRK		 1977 rxq->rx_buf_size,
1978 rxq->rx_bd_ring.p_phys_addr,
1979 p_phys_table,
3da7a37a 1980 page_cnt, &ret_params);
9a4d7e86
SRK		 1981 if (rc) {
1982 DP_ERR(edev, "Start RXQ #%d failed %d\n", i,
1983 rc);
f29ffdb6 1984 goto out;
9a4d7e86
SRK		 1985 }
1986
3da7a37a
MY		 1987 /* Use the return parameters */
1988 rxq->hw_rxq_prod_addr = ret_params.p_prod;
1989 rxq->handle = ret_params.p_handle;
1990
9a4d7e86
SRK		 1991 val = &fp->sb_info->sb_virt->pi_array[RX_PI];
1992 rxq->hw_cons_ptr = val;
1993
1994 qede_update_rx_prod(edev, rxq);
1995 }
1996
496e0517 1997 if (fp->type & QEDE_FASTPATH_XDP) {
cb6aeb07
MY		 1998 rc = qede_start_txq(edev, fp, fp->xdp_tx, i, XDP_PI);
1999 if (rc)
f29ffdb6 2000 goto out;
cb6aeb07 2001
496e0517
MY		 2002 fp->rxq->xdp_prog = bpf_prog_add(edev->xdp_prog, 1);
2003 if (IS_ERR(fp->rxq->xdp_prog)) {
2004 rc = PTR_ERR(fp->rxq->xdp_prog);
2005 fp->rxq->xdp_prog = NULL;
f29ffdb6 2006 goto out;
496e0517
MY		 2007 }
2008 }
2009
80439a17 2010 if (fp->type & QEDE_FASTPATH_TX) {
5e7baf0f
MC		 2011 int cos;
2012
2013 for_each_cos_in_txq(edev, cos) {
2014 rc = qede_start_txq(edev, fp, &fp->txq[cos], i,
2015 TX_PI(cos));
2016 if (rc)
2017 goto out;
2018 }
2950219d
YM		 2019 }
2020 }
2021
2022 /* Prepare and send the vport enable */
f29ffdb6
MY		 2023 vport_update_params->vport_id = start.vport_id;
2024 vport_update_params->update_vport_active_flg = 1;
2025 vport_update_params->vport_active_flg = 1;
2950219d 2026
0bc5fe85 2027 if ((qed_info->b_inter_pf_switch || pci_num_vf(edev->pdev)) &&
831bfb0e 2028 qed_info->tx_switching) {
f29ffdb6
MY		 2029 vport_update_params->update_tx_switching_flg = 1;
2030 vport_update_params->tx_switching_flg = 1;
831bfb0e
YM		 2031 }
2032
f29ffdb6
MY		 2033 qede_fill_rss_params(edev, &vport_update_params->rss_params,
2034 &vport_update_params->update_rss_flg);
961acdea 2035
f29ffdb6
MY		 2036 rc = edev->ops->vport_update(cdev, vport_update_params);
2037 if (rc)
2950219d 2038 DP_ERR(edev, "Update V-PORT failed %d\n", rc);
2950219d 2039
f29ffdb6
MY		 2040out:
2041 vfree(vport_update_params);
2042 return rc;
2950219d
YM		 2043}
2044
2045enum qede_unload_mode {
2046 QEDE_UNLOAD_NORMAL,
2047};
2048
567b3c12
MY		 2049static void qede_unload(struct qede_dev *edev, enum qede_unload_mode mode,
2050 bool is_locked)
2950219d 2051{
a2ec6172 2052 struct qed_link_params link_params;
2950219d
YM		 2053 int rc;
2054
2055 DP_INFO(edev, "Starting qede unload\n");
2056
567b3c12
MY		 2057 if (!is_locked)
2058 __qede_lock(edev);
2059
0d8e0aa0
SK		 2060 edev->state = QEDE_STATE_CLOSED;
2061
bbfcd1e8 2062 qede_rdma_dev_event_close(edev);
2e7022d6 2063
2950219d
YM		 2064 /* Close OS Tx */
2065 netif_tx_disable(edev->ndev);
2066 netif_carrier_off(edev->ndev);
2067
a2ec6172
SK		 2068 /* Reset the link */
2069 memset(&link_params, 0, sizeof(link_params));
2070 link_params.link_up = false;
2071 edev->ops->common->set_link(edev->cdev, &link_params);
2950219d
YM		 2072 rc = qede_stop_queues(edev);
2073 if (rc) {
2074 qede_sync_free_irqs(edev);
2075 goto out;
2076 }
2077
2078 DP_INFO(edev, "Stopped Queues\n");
2079
7c1bfcad 2080 qede_vlan_mark_nonconfigured(edev);
2950219d 2081 edev->ops->fastpath_stop(edev->cdev);
3f2a2b8b 2082
e4917d46
CM		 2083 if (!IS_VF(edev) && edev->dev_info.common.num_hwfns == 1) {
2084 qede_poll_for_freeing_arfs_filters(edev);
2085 qede_free_arfs(edev);
2086 }
3f2a2b8b 2087
2950219d
YM		 2088 /* Release the interrupts */
2089 qede_sync_free_irqs(edev);
2090 edev->ops->common->set_fp_int(edev->cdev, 0);
2091
2092 qede_napi_disable_remove(edev);
2093
2094 qede_free_mem_load(edev);
2095 qede_free_fp_array(edev);
2096
2097out:
567b3c12
MY		 2098 if (!is_locked)
2099 __qede_unlock(edev);
2950219d
YM		 2100 DP_INFO(edev, "Ending qede unload\n");
2101}
2102
2103enum qede_load_mode {
2104 QEDE_LOAD_NORMAL,
a0d26d5a 2105 QEDE_LOAD_RELOAD,
2950219d
YM		 2106};
2107
567b3c12
MY		 2108static int qede_load(struct qede_dev *edev, enum qede_load_mode mode,
2109 bool is_locked)
2950219d 2110{
a2ec6172 2111 struct qed_link_params link_params;
5e7baf0f 2112 u8 num_tc;
2950219d
YM		 2113 int rc;
2114
2115 DP_INFO(edev, "Starting qede load\n");
2116
567b3c12
MY		 2117 if (!is_locked)
2118 __qede_lock(edev);
2119
2950219d
YM		 2120 rc = qede_set_num_queues(edev);
2121 if (rc)
567b3c12 2122 goto out;
2950219d
YM		 2123
2124 rc = qede_alloc_fp_array(edev);
2125 if (rc)
567b3c12 2126 goto out;
2950219d
YM		 2127
2128 qede_init_fp(edev);
2129
2130 rc = qede_alloc_mem_load(edev);
2131 if (rc)
2132 goto err1;
80439a17
MY		 2133 DP_INFO(edev, "Allocated %d Rx, %d Tx queues\n",
2134 QEDE_RSS_COUNT(edev), QEDE_TSS_COUNT(edev));
2950219d
YM		 2135
2136 rc = qede_set_real_num_queues(edev);
2137 if (rc)
2138 goto err2;
2139
e4917d46
CM		 2140 if (!IS_VF(edev) && edev->dev_info.common.num_hwfns == 1) {
2141 rc = qede_alloc_arfs(edev);
2142 if (rc)
2143 DP_NOTICE(edev, "aRFS memory allocation failed\n");
2144 }
3f2a2b8b 2145
2950219d
YM		 2146 qede_napi_add_enable(edev);
2147 DP_INFO(edev, "Napi added and enabled\n");
2148
2149 rc = qede_setup_irqs(edev);
2150 if (rc)
2151 goto err3;
2152 DP_INFO(edev, "Setup IRQs succeeded\n");
2153
a0d26d5a 2154 rc = qede_start_queues(edev, mode != QEDE_LOAD_RELOAD);
2950219d
YM		 2155 if (rc)
2156 goto err4;
2157 DP_INFO(edev, "Start VPORT, RXQ and TXQ succeeded\n");
2158
5e7baf0f
MC		 2159 num_tc = netdev_get_num_tc(edev->ndev);
2160 num_tc = num_tc ? num_tc : edev->dev_info.num_tc;
2161 qede_setup_tc(edev->ndev, num_tc);
2162
7c1bfcad
SRK		 2163 /* Program un-configured VLANs */
2164 qede_configure_vlan_filters(edev);
2165
a2ec6172
SK		 2166 /* Ask for link-up using current configuration */
2167 memset(&link_params, 0, sizeof(link_params));
2168 link_params.link_up = true;
2169 edev->ops->common->set_link(edev->cdev, &link_params);
2170
567b3c12
MY		 2171 edev->state = QEDE_STATE_OPEN;
2172
2950219d
YM		 2173 DP_INFO(edev, "Ending successfully qede load\n");
2174
567b3c12 2175 goto out;
2950219d
YM		 2176err4:
2177 qede_sync_free_irqs(edev);
2178 memset(&edev->int_info.msix_cnt, 0, sizeof(struct qed_int_info));
2179err3:
2180 qede_napi_disable_remove(edev);
2181err2:
2182 qede_free_mem_load(edev);
2183err1:
2184 edev->ops->common->set_fp_int(edev->cdev, 0);
2185 qede_free_fp_array(edev);
9a4d7e86
SRK		 2186 edev->num_queues = 0;
2187 edev->fp_num_tx = 0;
2188 edev->fp_num_rx = 0;
567b3c12
MY		 2189out:
2190 if (!is_locked)
2191 __qede_unlock(edev);
2192
2950219d
YM		 2193 return rc;
2194}
2195
567b3c12
MY		 2196/* 'func' should be able to run between unload and reload assuming interface
2197 * is actually running, or afterwards in case it's currently DOWN.
2198 */
133fac0e 2199void qede_reload(struct qede_dev *edev,
567b3c12 2200 struct qede_reload_args *args, bool is_locked)
133fac0e 2201{
567b3c12
MY		 2202 if (!is_locked)
2203 __qede_lock(edev);
2204
2205 /* Since qede_lock is held, internal state wouldn't change even
2206 * if netdev state would start transitioning. Check whether current
2207 * internal configuration indicates device is up, then reload.
133fac0e 2208 */
567b3c12
MY		 2209 if (edev->state == QEDE_STATE_OPEN) {
2210 qede_unload(edev, QEDE_UNLOAD_NORMAL, true);
2211 if (args)
2212 args->func(edev, args);
2213 qede_load(edev, QEDE_LOAD_RELOAD, true);
133fac0e 2214
567b3c12
MY		 2215 /* Since no one is going to do it for us, re-configure */
2216 qede_config_rx_mode(edev->ndev);
2217 } else if (args) {
2218 args->func(edev, args);
2219 }
133fac0e 2220
567b3c12
MY		 2221 if (!is_locked)
2222 __qede_unlock(edev);
133fac0e
SK		 2223}
2224
2950219d
YM		 2225/* called with rtnl_lock */
2226static int qede_open(struct net_device *ndev)
2227{
2228 struct qede_dev *edev = netdev_priv(ndev);
b18e170c 2229 int rc;
2950219d
YM		 2230
2231 netif_carrier_off(ndev);
2232
2233 edev->ops->common->set_power_state(edev->cdev, PCI_D0);
2234
567b3c12 2235 rc = qede_load(edev, QEDE_LOAD_NORMAL, false);
b18e170c
MC		 2236 if (rc)
2237 return rc;
2238
f9f082a9
AD		 2239 udp_tunnel_get_rx_info(ndev);
2240
0fefbfba
SK		 2241 edev->ops->common->update_drv_state(edev->cdev, true);
2242
b18e170c 2243 return 0;
2950219d
YM		 2244}
2245
2246static int qede_close(struct net_device *ndev)
2247{
2248 struct qede_dev *edev = netdev_priv(ndev);
2249
567b3c12 2250 qede_unload(edev, QEDE_UNLOAD_NORMAL, false);
2950219d 2251
0fefbfba
SK		 2252 edev->ops->common->update_drv_state(edev->cdev, false);
2253
2950219d
YM		 2254 return 0;
2255}
0d8e0aa0 2256
a2ec6172
SK		 2257static void qede_link_update(void *dev, struct qed_link_output *link)
2258{
2259 struct qede_dev *edev = dev;
2260
2261 if (!netif_running(edev->ndev)) {
2262 DP_VERBOSE(edev, NETIF_MSG_LINK, "Interface is not running\n");
2263 return;
2264 }
2265
2266 if (link->link_up) {
8e025ae2
YM		 2267 if (!netif_carrier_ok(edev->ndev)) {
2268 DP_NOTICE(edev, "Link is up\n");
2269 netif_tx_start_all_queues(edev->ndev);
2270 netif_carrier_on(edev->ndev);
4609adc2 2271 qede_rdma_dev_event_open(edev);
8e025ae2 2272 }
a2ec6172 2273 } else {
8e025ae2
YM		 2274 if (netif_carrier_ok(edev->ndev)) {
2275 DP_NOTICE(edev, "Link is down\n");
2276 netif_tx_disable(edev->ndev);
2277 netif_carrier_off(edev->ndev);
4609adc2 2278 qede_rdma_dev_event_close(edev);
8e025ae2 2279 }
a2ec6172
SK		 2280 }
2281}
d25b859c
SRK		 2282
2283static bool qede_is_txq_full(struct qede_dev *edev, struct qede_tx_queue *txq)
2284{
2285 struct netdev_queue *netdev_txq;
2286
5e7baf0f 2287 netdev_txq = netdev_get_tx_queue(edev->ndev, txq->ndev_txq_id);
d25b859c
SRK		 2288 if (netif_xmit_stopped(netdev_txq))
2289 return true;
2290
2291 return false;
2292}
2293
2294static void qede_get_generic_tlv_data(void *dev, struct qed_generic_tlvs *data)
2295{
2296 struct qede_dev *edev = dev;
2297 struct netdev_hw_addr *ha;
2298 int i;
2299
2300 if (edev->ndev->features & NETIF_F_IP_CSUM)
2301 data->feat_flags |= QED_TLV_IP_CSUM;
2302 if (edev->ndev->features & NETIF_F_TSO)
2303 data->feat_flags |= QED_TLV_LSO;
2304
2305 ether_addr_copy(data->mac[0], edev->ndev->dev_addr);
2306 memset(data->mac[1], 0, ETH_ALEN);
2307 memset(data->mac[2], 0, ETH_ALEN);
2308 /* Copy the first two UC macs */
2309 netif_addr_lock_bh(edev->ndev);
2310 i = 1;
2311 netdev_for_each_uc_addr(ha, edev->ndev) {
2312 ether_addr_copy(data->mac[i++], ha->addr);
2313 if (i == QED_TLV_MAC_COUNT)
2314 break;
2315 }
2316
2317 netif_addr_unlock_bh(edev->ndev);
2318}
2319
2320static void qede_get_eth_tlv_data(void *dev, void *data)
2321{
2322 struct qed_mfw_tlv_eth *etlv = data;
2323 struct qede_dev *edev = dev;
2324 struct qede_fastpath *fp;
2325 int i;
2326
2327 etlv->lso_maxoff_size = 0XFFFF;
2328 etlv->lso_maxoff_size_set = true;
2329 etlv->lso_minseg_size = (u16)ETH_TX_LSO_WINDOW_MIN_LEN;
2330 etlv->lso_minseg_size_set = true;
2331 etlv->prom_mode = !!(edev->ndev->flags & IFF_PROMISC);
2332 etlv->prom_mode_set = true;
2333 etlv->tx_descr_size = QEDE_TSS_COUNT(edev);
2334 etlv->tx_descr_size_set = true;
2335 etlv->rx_descr_size = QEDE_RSS_COUNT(edev);
2336 etlv->rx_descr_size_set = true;
2337 etlv->iov_offload = QED_MFW_TLV_IOV_OFFLOAD_VEB;
2338 etlv->iov_offload_set = true;
2339
2340 /* Fill information regarding queues; Should be done under the qede
2341 * lock to guarantee those don't change beneath our feet.
2342 */
2343 etlv->txqs_empty = true;
2344 etlv->rxqs_empty = true;
2345 etlv->num_txqs_full = 0;
2346 etlv->num_rxqs_full = 0;
2347
2348 __qede_lock(edev);
2349 for_each_queue(i) {
2350 fp = &edev->fp_array[i];
2351 if (fp->type & QEDE_FASTPATH_TX) {
5e7baf0f
MC		 2352 struct qede_tx_queue *txq = QEDE_FP_TC0_TXQ(fp);
2353
2354 if (txq->sw_tx_cons != txq->sw_tx_prod)
d25b859c 2355 etlv->txqs_empty = false;
5e7baf0f 2356 if (qede_is_txq_full(edev, txq))
d25b859c
SRK		 2357 etlv->num_txqs_full++;
2358 }
2359 if (fp->type & QEDE_FASTPATH_RX) {
2360 if (qede_has_rx_work(fp->rxq))
2361 etlv->rxqs_empty = false;
2362
2363 /* This one is a bit tricky; Firmware might stop
2364 * placing packets if ring is not yet full.
2365 * Give an approximation.
2366 */
2367 if (le16_to_cpu(*fp->rxq->hw_cons_ptr) -
2368 qed_chain_get_cons_idx(&fp->rxq->rx_comp_ring) >
2369 RX_RING_SIZE - 100)
2370 etlv->num_rxqs_full++;
2371 }
2372 }
2373 __qede_unlock(edev);
2374
2375 etlv->txqs_empty_set = true;
2376 etlv->rxqs_empty_set = true;
2377 etlv->num_txqs_full_set = true;
2378 etlv->num_rxqs_full_set = true;
2379}
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