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qede: Refactor data-path Rx flow
[mirror_ubuntu-focal-kernel.git] / drivers / net / ethernet / qlogic / qede / qede_main.c
CommitLineData
e712d52b
YM		 1/* QLogic qede NIC Driver
2* Copyright (c) 2015 QLogic Corporation
3*
4* This software is available under the terms of the GNU General Public License
5* (GPL) Version 2, available from the file COPYING in the main directory of
6* this source tree.
7*/
8
9#include <linux/module.h>
10#include <linux/pci.h>
11#include <linux/version.h>
12#include <linux/device.h>
13#include <linux/netdevice.h>
14#include <linux/etherdevice.h>
15#include <linux/skbuff.h>
16#include <linux/errno.h>
17#include <linux/list.h>
18#include <linux/string.h>
19#include <linux/dma-mapping.h>
20#include <linux/interrupt.h>
21#include <asm/byteorder.h>
22#include <asm/param.h>
23#include <linux/io.h>
24#include <linux/netdev_features.h>
25#include <linux/udp.h>
26#include <linux/tcp.h>
f9f082a9 27#include <net/udp_tunnel.h>
e712d52b
YM		 28#include <linux/ip.h>
29#include <net/ipv6.h>
30#include <net/tcp.h>
31#include <linux/if_ether.h>
32#include <linux/if_vlan.h>
33#include <linux/pkt_sched.h>
34#include <linux/ethtool.h>
35#include <linux/in.h>
36#include <linux/random.h>
37#include <net/ip6_checksum.h>
38#include <linux/bitops.h>
cee9fbd8 39#include <linux/qed/qede_roce.h>
e712d52b
YM		 40#include "qede.h"
41
5abd7e92
YM		 42static char version[] =
43 "QLogic FastLinQ 4xxxx Ethernet Driver qede " DRV_MODULE_VERSION "\n";
e712d52b 44
5abd7e92 45MODULE_DESCRIPTION("QLogic FastLinQ 4xxxx Ethernet Driver");
e712d52b
YM		 46MODULE_LICENSE("GPL");
47MODULE_VERSION(DRV_MODULE_VERSION);
48
49static uint debug;
50module_param(debug, uint, 0);
51MODULE_PARM_DESC(debug, " Default debug msglevel");
52
53static const struct qed_eth_ops *qed_ops;
54
55#define CHIP_NUM_57980S_40 0x1634
0e7441d7 56#define CHIP_NUM_57980S_10 0x1666
e712d52b
YM		 57#define CHIP_NUM_57980S_MF 0x1636
58#define CHIP_NUM_57980S_100 0x1644
59#define CHIP_NUM_57980S_50 0x1654
60#define CHIP_NUM_57980S_25 0x1656
fefb0202 61#define CHIP_NUM_57980S_IOV 0x1664
e712d52b
YM		 62
63#ifndef PCI_DEVICE_ID_NX2_57980E
64#define PCI_DEVICE_ID_57980S_40 CHIP_NUM_57980S_40
65#define PCI_DEVICE_ID_57980S_10 CHIP_NUM_57980S_10
66#define PCI_DEVICE_ID_57980S_MF CHIP_NUM_57980S_MF
67#define PCI_DEVICE_ID_57980S_100 CHIP_NUM_57980S_100
68#define PCI_DEVICE_ID_57980S_50 CHIP_NUM_57980S_50
69#define PCI_DEVICE_ID_57980S_25 CHIP_NUM_57980S_25
fefb0202 70#define PCI_DEVICE_ID_57980S_IOV CHIP_NUM_57980S_IOV
e712d52b
YM		 71#endif
72
fefb0202
YM		 73enum qede_pci_private {
74 QEDE_PRIVATE_PF,
75 QEDE_PRIVATE_VF
76};
77
e712d52b 78static const struct pci_device_id qede_pci_tbl[] = {
fefb0202
YM		 79 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_40), QEDE_PRIVATE_PF},
80 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_10), QEDE_PRIVATE_PF},
81 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_MF), QEDE_PRIVATE_PF},
82 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_100), QEDE_PRIVATE_PF},
83 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_50), QEDE_PRIVATE_PF},
84 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_25), QEDE_PRIVATE_PF},
14b84e86 85#ifdef CONFIG_QED_SRIOV
fefb0202 86 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_IOV), QEDE_PRIVATE_VF},
14b84e86 87#endif
e712d52b
YM		 88 { 0 }
89};
90
91MODULE_DEVICE_TABLE(pci, qede_pci_tbl);
92
93static int qede_probe(struct pci_dev *pdev, const struct pci_device_id *id);
94
95#define TX_TIMEOUT (5 * HZ)
96
97static void qede_remove(struct pci_dev *pdev);
14d39648 98static void qede_shutdown(struct pci_dev *pdev);
2950219d
YM		 99static int qede_alloc_rx_buffer(struct qede_dev *edev,
100 struct qede_rx_queue *rxq);
a2ec6172 101static void qede_link_update(void *dev, struct qed_link_output *link);
e712d52b 102
fefb0202 103#ifdef CONFIG_QED_SRIOV
79aab093
MS		 104static int qede_set_vf_vlan(struct net_device *ndev, int vf, u16 vlan, u8 qos,
105 __be16 vlan_proto)
08feecd7
YM		 106{
107 struct qede_dev *edev = netdev_priv(ndev);
108
109 if (vlan > 4095) {
110 DP_NOTICE(edev, "Illegal vlan value %d\n", vlan);
111 return -EINVAL;
112 }
113
79aab093
MS		 114 if (vlan_proto != htons(ETH_P_8021Q))
115 return -EPROTONOSUPPORT;
116
08feecd7
YM		 117 DP_VERBOSE(edev, QED_MSG_IOV, "Setting Vlan 0x%04x to VF [%d]\n",
118 vlan, vf);
119
120 return edev->ops->iov->set_vlan(edev->cdev, vlan, vf);
121}
122
eff16960
YM		 123static int qede_set_vf_mac(struct net_device *ndev, int vfidx, u8 *mac)
124{
125 struct qede_dev *edev = netdev_priv(ndev);
126
127 DP_VERBOSE(edev, QED_MSG_IOV,
128 "Setting MAC %02x:%02x:%02x:%02x:%02x:%02x to VF [%d]\n",
129 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5], vfidx);
130
131 if (!is_valid_ether_addr(mac)) {
132 DP_VERBOSE(edev, QED_MSG_IOV, "MAC address isn't valid\n");
133 return -EINVAL;
134 }
135
136 return edev->ops->iov->set_mac(edev->cdev, mac, vfidx);
137}
138
fefb0202
YM		 139static int qede_sriov_configure(struct pci_dev *pdev, int num_vfs_param)
140{
141 struct qede_dev *edev = netdev_priv(pci_get_drvdata(pdev));
831bfb0e
YM		 142 struct qed_dev_info *qed_info = &edev->dev_info.common;
143 int rc;
fefb0202
YM		 144
145 DP_VERBOSE(edev, QED_MSG_IOV, "Requested %d VFs\n", num_vfs_param);
146
831bfb0e
YM		 147 rc = edev->ops->iov->configure(edev->cdev, num_vfs_param);
148
149 /* Enable/Disable Tx switching for PF */
150 if ((rc == num_vfs_param) && netif_running(edev->ndev) &&
151 qed_info->mf_mode != QED_MF_NPAR && qed_info->tx_switching) {
152 struct qed_update_vport_params params;
153
154 memset(&params, 0, sizeof(params));
155 params.vport_id = 0;
156 params.update_tx_switching_flg = 1;
157 params.tx_switching_flg = num_vfs_param ? 1 : 0;
158 edev->ops->vport_update(edev->cdev, &params);
159 }
160
161 return rc;
fefb0202
YM		 162}
163#endif
164
e712d52b
YM		 165static struct pci_driver qede_pci_driver = {
166 .name = "qede",
167 .id_table = qede_pci_tbl,
168 .probe = qede_probe,
169 .remove = qede_remove,
14d39648 170 .shutdown = qede_shutdown,
fefb0202
YM		 171#ifdef CONFIG_QED_SRIOV
172 .sriov_configure = qede_sriov_configure,
173#endif
e712d52b
YM		 174};
175
c3aaa403 176static void qede_force_mac(void *dev, u8 *mac, bool forced)
eff16960
YM		 177{
178 struct qede_dev *edev = dev;
179
c3aaa403
YM		 180 /* MAC hints take effect only if we haven't set one already */
181 if (is_valid_ether_addr(edev->ndev->dev_addr) && !forced)
182 return;
183
eff16960
YM		 184 ether_addr_copy(edev->ndev->dev_addr, mac);
185 ether_addr_copy(edev->primary_mac, mac);
186}
187
a2ec6172
SK		 188static struct qed_eth_cb_ops qede_ll_ops = {
189 {
190 .link_update = qede_link_update,
191 },
eff16960 192 .force_mac = qede_force_mac,
a2ec6172
SK		 193};
194
2950219d
YM		 195static int qede_netdev_event(struct notifier_block *this, unsigned long event,
196 void *ptr)
197{
198 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
199 struct ethtool_drvinfo drvinfo;
200 struct qede_dev *edev;
201
cee9fbd8 202 if (event != NETDEV_CHANGENAME && event != NETDEV_CHANGEADDR)
2950219d
YM		 203 goto done;
204
205 /* Check whether this is a qede device */
206 if (!ndev || !ndev->ethtool_ops || !ndev->ethtool_ops->get_drvinfo)
207 goto done;
208
209 memset(&drvinfo, 0, sizeof(drvinfo));
210 ndev->ethtool_ops->get_drvinfo(ndev, &drvinfo);
211 if (strcmp(drvinfo.driver, "qede"))
212 goto done;
213 edev = netdev_priv(ndev);
214
cee9fbd8
RA		 215 switch (event) {
216 case NETDEV_CHANGENAME:
217 /* Notify qed of the name change */
218 if (!edev->ops || !edev->ops->common)
219 goto done;
220 edev->ops->common->set_id(edev->cdev, edev->ndev->name, "qede");
221 break;
222 case NETDEV_CHANGEADDR:
223 edev = netdev_priv(ndev);
224 qede_roce_event_changeaddr(edev);
225 break;
226 }
2950219d
YM		 227
228done:
229 return NOTIFY_DONE;
230}
231
232static struct notifier_block qede_netdev_notifier = {
233 .notifier_call = qede_netdev_event,
234};
235
e712d52b
YM		 236static
237int __init qede_init(void)
238{
239 int ret;
e712d52b 240
525ef5c0 241 pr_info("qede_init: %s\n", version);
e712d52b 242
95114344 243 qed_ops = qed_get_eth_ops();
e712d52b
YM		 244 if (!qed_ops) {
245 pr_notice("Failed to get qed ethtool operations\n");
246 return -EINVAL;
247 }
248
2950219d
YM		 249 /* Must register notifier before pci ops, since we might miss
250 * interface rename after pci probe and netdev registeration.
251 */
252 ret = register_netdevice_notifier(&qede_netdev_notifier);
253 if (ret) {
254 pr_notice("Failed to register netdevice_notifier\n");
255 qed_put_eth_ops();
256 return -EINVAL;
257 }
258
e712d52b
YM		 259 ret = pci_register_driver(&qede_pci_driver);
260 if (ret) {
261 pr_notice("Failed to register driver\n");
2950219d 262 unregister_netdevice_notifier(&qede_netdev_notifier);
e712d52b
YM		 263 qed_put_eth_ops();
264 return -EINVAL;
265 }
266
267 return 0;
268}
269
270static void __exit qede_cleanup(void)
271{
525ef5c0
YM		 272 if (debug & QED_LOG_INFO_MASK)
273 pr_info("qede_cleanup called\n");
e712d52b 274
2950219d 275 unregister_netdevice_notifier(&qede_netdev_notifier);
e712d52b
YM		 276 pci_unregister_driver(&qede_pci_driver);
277 qed_put_eth_ops();
278}
279
280module_init(qede_init);
281module_exit(qede_cleanup);
282
2950219d
YM		 283/* -------------------------------------------------------------------------
284 * START OF FAST-PATH
285 * -------------------------------------------------------------------------
286 */
287
288/* Unmap the data and free skb */
289static int qede_free_tx_pkt(struct qede_dev *edev,
1a635e48 290 struct qede_tx_queue *txq, int *len)
2950219d
YM		 291{
292 u16 idx = txq->sw_tx_cons & NUM_TX_BDS_MAX;
293 struct sk_buff *skb = txq->sw_tx_ring[idx].skb;
294 struct eth_tx_1st_bd *first_bd;
295 struct eth_tx_bd *tx_data_bd;
296 int bds_consumed = 0;
297 int nbds;
298 bool data_split = txq->sw_tx_ring[idx].flags & QEDE_TSO_SPLIT_BD;
299 int i, split_bd_len = 0;
300
301 if (unlikely(!skb)) {
302 DP_ERR(edev,
303 "skb is null for txq idx=%d txq->sw_tx_cons=%d txq->sw_tx_prod=%d\n",
304 idx, txq->sw_tx_cons, txq->sw_tx_prod);
305 return -1;
306 }
307
308 *len = skb->len;
309
310 first_bd = (struct eth_tx_1st_bd *)qed_chain_consume(&txq->tx_pbl);
311
312 bds_consumed++;
313
314 nbds = first_bd->data.nbds;
315
316 if (data_split) {
317 struct eth_tx_bd *split = (struct eth_tx_bd *)
318 qed_chain_consume(&txq->tx_pbl);
319 split_bd_len = BD_UNMAP_LEN(split);
320 bds_consumed++;
321 }
fabd545c
MC		 322 dma_unmap_single(&edev->pdev->dev, BD_UNMAP_ADDR(first_bd),
323 BD_UNMAP_LEN(first_bd) + split_bd_len, DMA_TO_DEVICE);
2950219d
YM		 324
325 /* Unmap the data of the skb frags */
326 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++, bds_consumed++) {
327 tx_data_bd = (struct eth_tx_bd *)
328 qed_chain_consume(&txq->tx_pbl);
329 dma_unmap_page(&edev->pdev->dev, BD_UNMAP_ADDR(tx_data_bd),
330 BD_UNMAP_LEN(tx_data_bd), DMA_TO_DEVICE);
331 }
332
333 while (bds_consumed++ < nbds)
334 qed_chain_consume(&txq->tx_pbl);
335
336 /* Free skb */
337 dev_kfree_skb_any(skb);
338 txq->sw_tx_ring[idx].skb = NULL;
339 txq->sw_tx_ring[idx].flags = 0;
340
341 return 0;
342}
343
344/* Unmap the data and free skb when mapping failed during start_xmit */
345static void qede_free_failed_tx_pkt(struct qede_dev *edev,
346 struct qede_tx_queue *txq,
347 struct eth_tx_1st_bd *first_bd,
1a635e48 348 int nbd, bool data_split)
2950219d
YM		 349{
350 u16 idx = txq->sw_tx_prod & NUM_TX_BDS_MAX;
351 struct sk_buff *skb = txq->sw_tx_ring[idx].skb;
352 struct eth_tx_bd *tx_data_bd;
353 int i, split_bd_len = 0;
354
355 /* Return prod to its position before this skb was handled */
356 qed_chain_set_prod(&txq->tx_pbl,
1a635e48 357 le16_to_cpu(txq->tx_db.data.bd_prod), first_bd);
2950219d
YM		 358
359 first_bd = (struct eth_tx_1st_bd *)qed_chain_produce(&txq->tx_pbl);
360
361 if (data_split) {
362 struct eth_tx_bd *split = (struct eth_tx_bd *)
363 qed_chain_produce(&txq->tx_pbl);
364 split_bd_len = BD_UNMAP_LEN(split);
365 nbd--;
366 }
367
fabd545c
MC		 368 dma_unmap_single(&edev->pdev->dev, BD_UNMAP_ADDR(first_bd),
369 BD_UNMAP_LEN(first_bd) + split_bd_len, DMA_TO_DEVICE);
2950219d
YM		 370
371 /* Unmap the data of the skb frags */
372 for (i = 0; i < nbd; i++) {
373 tx_data_bd = (struct eth_tx_bd *)
374 qed_chain_produce(&txq->tx_pbl);
375 if (tx_data_bd->nbytes)
376 dma_unmap_page(&edev->pdev->dev,
377 BD_UNMAP_ADDR(tx_data_bd),
378 BD_UNMAP_LEN(tx_data_bd), DMA_TO_DEVICE);
379 }
380
381 /* Return again prod to its position before this skb was handled */
382 qed_chain_set_prod(&txq->tx_pbl,
1a635e48 383 le16_to_cpu(txq->tx_db.data.bd_prod), first_bd);
2950219d
YM		 384
385 /* Free skb */
386 dev_kfree_skb_any(skb);
387 txq->sw_tx_ring[idx].skb = NULL;
388 txq->sw_tx_ring[idx].flags = 0;
389}
390
391static u32 qede_xmit_type(struct qede_dev *edev,
1a635e48 392 struct sk_buff *skb, int *ipv6_ext)
2950219d
YM		 393{
394 u32 rc = XMIT_L4_CSUM;
395 __be16 l3_proto;
396
397 if (skb->ip_summed != CHECKSUM_PARTIAL)
398 return XMIT_PLAIN;
399
400 l3_proto = vlan_get_protocol(skb);
401 if (l3_proto == htons(ETH_P_IPV6) &&
402 (ipv6_hdr(skb)->nexthdr == NEXTHDR_IPV6))
403 *ipv6_ext = 1;
404
a150241c 405 if (skb->encapsulation) {
14db81de 406 rc |= XMIT_ENC;
a150241c
MC		 407 if (skb_is_gso(skb)) {
408 unsigned short gso_type = skb_shinfo(skb)->gso_type;
409
410 if ((gso_type & SKB_GSO_UDP_TUNNEL_CSUM) ||
411 (gso_type & SKB_GSO_GRE_CSUM))
412 rc |= XMIT_ENC_GSO_L4_CSUM;
413
414 rc |= XMIT_LSO;
415 return rc;
416 }
417 }
14db81de 418
2950219d
YM		 419 if (skb_is_gso(skb))
420 rc |= XMIT_LSO;
421
422 return rc;
423}
424
425static void qede_set_params_for_ipv6_ext(struct sk_buff *skb,
426 struct eth_tx_2nd_bd *second_bd,
427 struct eth_tx_3rd_bd *third_bd)
428{
429 u8 l4_proto;
fc48b7a6 430 u16 bd2_bits1 = 0, bd2_bits2 = 0;
2950219d 431
fc48b7a6 432 bd2_bits1 |= (1 << ETH_TX_DATA_2ND_BD_IPV6_EXT_SHIFT);
2950219d 433
fc48b7a6 434 bd2_bits2 |= ((((u8 *)skb_transport_header(skb) - skb->data) >> 1) &
2950219d
YM		 435 ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_MASK)
436 << ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_SHIFT;
437
fc48b7a6 438 bd2_bits1 |= (ETH_L4_PSEUDO_CSUM_CORRECT_LENGTH <<
2950219d
YM		 439 ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_SHIFT);
440
441 if (vlan_get_protocol(skb) == htons(ETH_P_IPV6))
442 l4_proto = ipv6_hdr(skb)->nexthdr;
443 else
444 l4_proto = ip_hdr(skb)->protocol;
445
446 if (l4_proto == IPPROTO_UDP)
fc48b7a6 447 bd2_bits1 |= 1 << ETH_TX_DATA_2ND_BD_L4_UDP_SHIFT;
2950219d 448
fc48b7a6 449 if (third_bd)
2950219d 450 third_bd->data.bitfields |=
fc48b7a6
YM		 451 cpu_to_le16(((tcp_hdrlen(skb) / 4) &
452 ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_MASK) <<
453 ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_SHIFT);
2950219d 454
fc48b7a6 455 second_bd->data.bitfields1 = cpu_to_le16(bd2_bits1);
2950219d
YM		 456 second_bd->data.bitfields2 = cpu_to_le16(bd2_bits2);
457}
458
459static int map_frag_to_bd(struct qede_dev *edev,
1a635e48 460 skb_frag_t *frag, struct eth_tx_bd *bd)
2950219d
YM		 461{
462 dma_addr_t mapping;
463
464 /* Map skb non-linear frag data for DMA */
465 mapping = skb_frag_dma_map(&edev->pdev->dev, frag, 0,
1a635e48 466 skb_frag_size(frag), DMA_TO_DEVICE);
2950219d
YM		 467 if (unlikely(dma_mapping_error(&edev->pdev->dev, mapping))) {
468 DP_NOTICE(edev, "Unable to map frag - dropping packet\n");
469 return -ENOMEM;
470 }
471
472 /* Setup the data pointer of the frag data */
473 BD_SET_UNMAP_ADDR_LEN(bd, mapping, skb_frag_size(frag));
474
475 return 0;
476}
477
14db81de
MC		 478static u16 qede_get_skb_hlen(struct sk_buff *skb, bool is_encap_pkt)
479{
480 if (is_encap_pkt)
481 return (skb_inner_transport_header(skb) +
482 inner_tcp_hdrlen(skb) - skb->data);
483 else
484 return (skb_transport_header(skb) +
485 tcp_hdrlen(skb) - skb->data);
486}
487
b1199b10
YM		 488/* +2 for 1st BD for headers and 2nd BD for headlen (if required) */
489#if ((MAX_SKB_FRAGS + 2) > ETH_TX_MAX_BDS_PER_NON_LSO_PACKET)
490static bool qede_pkt_req_lin(struct qede_dev *edev, struct sk_buff *skb,
491 u8 xmit_type)
492{
493 int allowed_frags = ETH_TX_MAX_BDS_PER_NON_LSO_PACKET - 1;
494
495 if (xmit_type & XMIT_LSO) {
496 int hlen;
497
14db81de 498 hlen = qede_get_skb_hlen(skb, xmit_type & XMIT_ENC);
b1199b10
YM		 499
500 /* linear payload would require its own BD */
501 if (skb_headlen(skb) > hlen)
502 allowed_frags--;
503 }
504
505 return (skb_shinfo(skb)->nr_frags > allowed_frags);
506}
507#endif
508
312e0676
MC		 509static inline void qede_update_tx_producer(struct qede_tx_queue *txq)
510{
511 /* wmb makes sure that the BDs data is updated before updating the
512 * producer, otherwise FW may read old data from the BDs.
513 */
514 wmb();
515 barrier();
516 writel(txq->tx_db.raw, txq->doorbell_addr);
517
518 /* mmiowb is needed to synchronize doorbell writes from more than one
519 * processor. It guarantees that the write arrives to the device before
520 * the queue lock is released and another start_xmit is called (possibly
521 * on another CPU). Without this barrier, the next doorbell can bypass
522 * this doorbell. This is applicable to IA64/Altix systems.
523 */
524 mmiowb();
525}
526
2950219d 527/* Main transmit function */
1a635e48
YM		 528static netdev_tx_t qede_start_xmit(struct sk_buff *skb,
529 struct net_device *ndev)
2950219d
YM		 530{
531 struct qede_dev *edev = netdev_priv(ndev);
532 struct netdev_queue *netdev_txq;
533 struct qede_tx_queue *txq;
534 struct eth_tx_1st_bd *first_bd;
535 struct eth_tx_2nd_bd *second_bd = NULL;
536 struct eth_tx_3rd_bd *third_bd = NULL;
537 struct eth_tx_bd *tx_data_bd = NULL;
538 u16 txq_index;
539 u8 nbd = 0;
540 dma_addr_t mapping;
541 int rc, frag_idx = 0, ipv6_ext = 0;
542 u8 xmit_type;
543 u16 idx;
544 u16 hlen;
810810ff 545 bool data_split = false;
2950219d
YM		 546
547 /* Get tx-queue context and netdev index */
548 txq_index = skb_get_queue_mapping(skb);
9a4d7e86 549 WARN_ON(txq_index >= QEDE_TSS_COUNT(edev));
80439a17 550 txq = edev->fp_array[edev->fp_num_rx + txq_index].txq;
2950219d
YM		 551 netdev_txq = netdev_get_tx_queue(ndev, txq_index);
552
1a635e48 553 WARN_ON(qed_chain_get_elem_left(&txq->tx_pbl) < (MAX_SKB_FRAGS + 1));
2950219d
YM		 554
555 xmit_type = qede_xmit_type(edev, skb, &ipv6_ext);
556
b1199b10
YM		 557#if ((MAX_SKB_FRAGS + 2) > ETH_TX_MAX_BDS_PER_NON_LSO_PACKET)
558 if (qede_pkt_req_lin(edev, skb, xmit_type)) {
559 if (skb_linearize(skb)) {
560 DP_NOTICE(edev,
561 "SKB linearization failed - silently dropping this SKB\n");
562 dev_kfree_skb_any(skb);
563 return NETDEV_TX_OK;
564 }
565 }
566#endif
567
2950219d
YM		 568 /* Fill the entry in the SW ring and the BDs in the FW ring */
569 idx = txq->sw_tx_prod & NUM_TX_BDS_MAX;
570 txq->sw_tx_ring[idx].skb = skb;
571 first_bd = (struct eth_tx_1st_bd *)
572 qed_chain_produce(&txq->tx_pbl);
573 memset(first_bd, 0, sizeof(*first_bd));
574 first_bd->data.bd_flags.bitfields =
575 1 << ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT;
576
577 /* Map skb linear data for DMA and set in the first BD */
578 mapping = dma_map_single(&edev->pdev->dev, skb->data,
579 skb_headlen(skb), DMA_TO_DEVICE);
580 if (unlikely(dma_mapping_error(&edev->pdev->dev, mapping))) {
581 DP_NOTICE(edev, "SKB mapping failed\n");
582 qede_free_failed_tx_pkt(edev, txq, first_bd, 0, false);
312e0676 583 qede_update_tx_producer(txq);
2950219d
YM		 584 return NETDEV_TX_OK;
585 }
586 nbd++;
587 BD_SET_UNMAP_ADDR_LEN(first_bd, mapping, skb_headlen(skb));
588
589 /* In case there is IPv6 with extension headers or LSO we need 2nd and
590 * 3rd BDs.
591 */
592 if (unlikely((xmit_type & XMIT_LSO) | ipv6_ext)) {
593 second_bd = (struct eth_tx_2nd_bd *)
594 qed_chain_produce(&txq->tx_pbl);
595 memset(second_bd, 0, sizeof(*second_bd));
596
597 nbd++;
598 third_bd = (struct eth_tx_3rd_bd *)
599 qed_chain_produce(&txq->tx_pbl);
600 memset(third_bd, 0, sizeof(*third_bd));
601
602 nbd++;
603 /* We need to fill in additional data in second_bd... */
604 tx_data_bd = (struct eth_tx_bd *)second_bd;
605 }
606
607 if (skb_vlan_tag_present(skb)) {
608 first_bd->data.vlan = cpu_to_le16(skb_vlan_tag_get(skb));
609 first_bd->data.bd_flags.bitfields |=
610 1 << ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_SHIFT;
611 }
612
613 /* Fill the parsing flags & params according to the requested offload */
614 if (xmit_type & XMIT_L4_CSUM) {
615 /* We don't re-calculate IP checksum as it is already done by
616 * the upper stack
617 */
618 first_bd->data.bd_flags.bitfields |=
619 1 << ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT;
620
14db81de
MC		 621 if (xmit_type & XMIT_ENC) {
622 first_bd->data.bd_flags.bitfields |=
623 1 << ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT;
351a4ded
YM		 624 first_bd->data.bitfields |=
625 1 << ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT;
14db81de 626 }
fc48b7a6 627
d8c2c7e3
YM		 628 /* Legacy FW had flipped behavior in regard to this bit -
629 * I.e., needed to set to prevent FW from touching encapsulated
630 * packets when it didn't need to.
631 */
632 if (unlikely(txq->is_legacy))
633 first_bd->data.bitfields ^=
634 1 << ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT;
635
2950219d
YM		 636 /* If the packet is IPv6 with extension header, indicate that
637 * to FW and pass few params, since the device cracker doesn't
638 * support parsing IPv6 with extension header/s.
639 */
640 if (unlikely(ipv6_ext))
641 qede_set_params_for_ipv6_ext(skb, second_bd, third_bd);
642 }
643
644 if (xmit_type & XMIT_LSO) {
645 first_bd->data.bd_flags.bitfields |=
646 (1 << ETH_TX_1ST_BD_FLAGS_LSO_SHIFT);
647 third_bd->data.lso_mss =
648 cpu_to_le16(skb_shinfo(skb)->gso_size);
649
14db81de
MC		 650 if (unlikely(xmit_type & XMIT_ENC)) {
651 first_bd->data.bd_flags.bitfields |=
652 1 << ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_SHIFT;
a150241c
MC		 653
654 if (xmit_type & XMIT_ENC_GSO_L4_CSUM) {
655 u8 tmp = ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_SHIFT;
656
657 first_bd->data.bd_flags.bitfields |= 1 << tmp;
658 }
14db81de
MC		 659 hlen = qede_get_skb_hlen(skb, true);
660 } else {
661 first_bd->data.bd_flags.bitfields |=
662 1 << ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT;
663 hlen = qede_get_skb_hlen(skb, false);
664 }
2950219d
YM		 665
666 /* @@@TBD - if will not be removed need to check */
667 third_bd->data.bitfields |=
fc48b7a6 668 cpu_to_le16((1 << ETH_TX_DATA_3RD_BD_HDR_NBD_SHIFT));
2950219d
YM		 669
670 /* Make life easier for FW guys who can't deal with header and
671 * data on same BD. If we need to split, use the second bd...
672 */
673 if (unlikely(skb_headlen(skb) > hlen)) {
674 DP_VERBOSE(edev, NETIF_MSG_TX_QUEUED,
675 "TSO split header size is %d (%x:%x)\n",
676 first_bd->nbytes, first_bd->addr.hi,
677 first_bd->addr.lo);
678
679 mapping = HILO_U64(le32_to_cpu(first_bd->addr.hi),
680 le32_to_cpu(first_bd->addr.lo)) +
681 hlen;
682
683 BD_SET_UNMAP_ADDR_LEN(tx_data_bd, mapping,
684 le16_to_cpu(first_bd->nbytes) -
685 hlen);
686
687 /* this marks the BD as one that has no
688 * individual mapping
689 */
690 txq->sw_tx_ring[idx].flags |= QEDE_TSO_SPLIT_BD;
691
692 first_bd->nbytes = cpu_to_le16(hlen);
693
694 tx_data_bd = (struct eth_tx_bd *)third_bd;
695 data_split = true;
696 }
351a4ded
YM		 697 } else {
698 first_bd->data.bitfields |=
699 (skb->len & ETH_TX_DATA_1ST_BD_PKT_LEN_MASK) <<
700 ETH_TX_DATA_1ST_BD_PKT_LEN_SHIFT;
2950219d
YM		 701 }
702
703 /* Handle fragmented skb */
704 /* special handle for frags inside 2nd and 3rd bds.. */
705 while (tx_data_bd && frag_idx < skb_shinfo(skb)->nr_frags) {
706 rc = map_frag_to_bd(edev,
707 &skb_shinfo(skb)->frags[frag_idx],
708 tx_data_bd);
709 if (rc) {
710 qede_free_failed_tx_pkt(edev, txq, first_bd, nbd,
711 data_split);
312e0676 712 qede_update_tx_producer(txq);
2950219d
YM		 713 return NETDEV_TX_OK;
714 }
715
716 if (tx_data_bd == (struct eth_tx_bd *)second_bd)
717 tx_data_bd = (struct eth_tx_bd *)third_bd;
718 else
719 tx_data_bd = NULL;
720
721 frag_idx++;
722 }
723
724 /* map last frags into 4th, 5th .... */
725 for (; frag_idx < skb_shinfo(skb)->nr_frags; frag_idx++, nbd++) {
726 tx_data_bd = (struct eth_tx_bd *)
727 qed_chain_produce(&txq->tx_pbl);
728
729 memset(tx_data_bd, 0, sizeof(*tx_data_bd));
730
731 rc = map_frag_to_bd(edev,
732 &skb_shinfo(skb)->frags[frag_idx],
733 tx_data_bd);
734 if (rc) {
735 qede_free_failed_tx_pkt(edev, txq, first_bd, nbd,
736 data_split);
312e0676 737 qede_update_tx_producer(txq);
2950219d
YM		 738 return NETDEV_TX_OK;
739 }
740 }
741
742 /* update the first BD with the actual num BDs */
743 first_bd->data.nbds = nbd;
744
745 netdev_tx_sent_queue(netdev_txq, skb->len);
746
747 skb_tx_timestamp(skb);
748
749 /* Advance packet producer only before sending the packet since mapping
750 * of pages may fail.
751 */
752 txq->sw_tx_prod++;
753
754 /* 'next page' entries are counted in the producer value */
755 txq->tx_db.data.bd_prod =
756 cpu_to_le16(qed_chain_get_prod_idx(&txq->tx_pbl));
757
039a3927 758 if (!skb->xmit_more || netif_xmit_stopped(netdev_txq))
312e0676 759 qede_update_tx_producer(txq);
2950219d
YM		 760
761 if (unlikely(qed_chain_get_elem_left(&txq->tx_pbl)
762 < (MAX_SKB_FRAGS + 1))) {
039a3927
YM		 763 if (skb->xmit_more)
764 qede_update_tx_producer(txq);
765
2950219d 766 netif_tx_stop_queue(netdev_txq);
68db9ec2 767 txq->stopped_cnt++;
2950219d
YM		 768 DP_VERBOSE(edev, NETIF_MSG_TX_QUEUED,
769 "Stop queue was called\n");
770 /* paired memory barrier is in qede_tx_int(), we have to keep
771 * ordering of set_bit() in netif_tx_stop_queue() and read of
772 * fp->bd_tx_cons
773 */
774 smp_mb();
775
776 if (qed_chain_get_elem_left(&txq->tx_pbl)
777 >= (MAX_SKB_FRAGS + 1) &&
778 (edev->state == QEDE_STATE_OPEN)) {
779 netif_tx_wake_queue(netdev_txq);
780 DP_VERBOSE(edev, NETIF_MSG_TX_QUEUED,
781 "Wake queue was called\n");
782 }
783 }
784
785 return NETDEV_TX_OK;
786}
787
16f46bf0 788int qede_txq_has_work(struct qede_tx_queue *txq)
2950219d
YM		 789{
790 u16 hw_bd_cons;
791
792 /* Tell compiler that consumer and producer can change */
793 barrier();
794 hw_bd_cons = le16_to_cpu(*txq->hw_cons_ptr);
795 if (qed_chain_get_cons_idx(&txq->tx_pbl) == hw_bd_cons + 1)
796 return 0;
797
798 return hw_bd_cons != qed_chain_get_cons_idx(&txq->tx_pbl);
799}
800
1a635e48 801static int qede_tx_int(struct qede_dev *edev, struct qede_tx_queue *txq)
2950219d
YM		 802{
803 struct netdev_queue *netdev_txq;
804 u16 hw_bd_cons;
805 unsigned int pkts_compl = 0, bytes_compl = 0;
806 int rc;
807
808 netdev_txq = netdev_get_tx_queue(edev->ndev, txq->index);
809
810 hw_bd_cons = le16_to_cpu(*txq->hw_cons_ptr);
811 barrier();
812
813 while (hw_bd_cons != qed_chain_get_cons_idx(&txq->tx_pbl)) {
814 int len = 0;
815
816 rc = qede_free_tx_pkt(edev, txq, &len);
817 if (rc) {
818 DP_NOTICE(edev, "hw_bd_cons = %d, chain_cons=%d\n",
819 hw_bd_cons,
820 qed_chain_get_cons_idx(&txq->tx_pbl));
821 break;
822 }
823
824 bytes_compl += len;
825 pkts_compl++;
826 txq->sw_tx_cons++;
68db9ec2 827 txq->xmit_pkts++;
2950219d
YM		 828 }
829
830 netdev_tx_completed_queue(netdev_txq, pkts_compl, bytes_compl);
831
832 /* Need to make the tx_bd_cons update visible to start_xmit()
833 * before checking for netif_tx_queue_stopped(). Without the
834 * memory barrier, there is a small possibility that
835 * start_xmit() will miss it and cause the queue to be stopped
836 * forever.
837 * On the other hand we need an rmb() here to ensure the proper
838 * ordering of bit testing in the following
839 * netif_tx_queue_stopped(txq) call.
840 */
841 smp_mb();
842
843 if (unlikely(netif_tx_queue_stopped(netdev_txq))) {
844 /* Taking tx_lock is needed to prevent reenabling the queue
845 * while it's empty. This could have happen if rx_action() gets
846 * suspended in qede_tx_int() after the condition before
847 * netif_tx_wake_queue(), while tx_action (qede_start_xmit()):
848 *
849 * stops the queue->sees fresh tx_bd_cons->releases the queue->
850 * sends some packets consuming the whole queue again->
851 * stops the queue
852 */
853
854 __netif_tx_lock(netdev_txq, smp_processor_id());
855
856 if ((netif_tx_queue_stopped(netdev_txq)) &&
857 (edev->state == QEDE_STATE_OPEN) &&
858 (qed_chain_get_elem_left(&txq->tx_pbl)
859 >= (MAX_SKB_FRAGS + 1))) {
860 netif_tx_wake_queue(netdev_txq);
861 DP_VERBOSE(edev, NETIF_MSG_TX_DONE,
862 "Wake queue was called\n");
863 }
864
865 __netif_tx_unlock(netdev_txq);
866 }
867
868 return 0;
869}
870
16f46bf0 871bool qede_has_rx_work(struct qede_rx_queue *rxq)
2950219d
YM		 872{
873 u16 hw_comp_cons, sw_comp_cons;
874
875 /* Tell compiler that status block fields can change */
876 barrier();
877
878 hw_comp_cons = le16_to_cpu(*rxq->hw_cons_ptr);
879 sw_comp_cons = qed_chain_get_cons_idx(&rxq->rx_comp_ring);
880
881 return hw_comp_cons != sw_comp_cons;
882}
883
f86af2df
MC		 884static inline void qede_rx_bd_ring_consume(struct qede_rx_queue *rxq)
885{
886 qed_chain_consume(&rxq->rx_bd_ring);
887 rxq->sw_rx_cons++;
888}
889
fc48b7a6
YM		 890/* This function reuses the buffer(from an offset) from
891 * consumer index to producer index in the bd ring
2950219d 892 */
fc48b7a6
YM		 893static inline void qede_reuse_page(struct qede_dev *edev,
894 struct qede_rx_queue *rxq,
895 struct sw_rx_data *curr_cons)
2950219d 896{
2950219d 897 struct eth_rx_bd *rx_bd_prod = qed_chain_produce(&rxq->rx_bd_ring);
fc48b7a6
YM		 898 struct sw_rx_data *curr_prod;
899 dma_addr_t new_mapping;
2950219d 900
fc48b7a6
YM		 901 curr_prod = &rxq->sw_rx_ring[rxq->sw_rx_prod & NUM_RX_BDS_MAX];
902 *curr_prod = *curr_cons;
2950219d 903
fc48b7a6
YM		 904 new_mapping = curr_prod->mapping + curr_prod->page_offset;
905
906 rx_bd_prod->addr.hi = cpu_to_le32(upper_32_bits(new_mapping));
907 rx_bd_prod->addr.lo = cpu_to_le32(lower_32_bits(new_mapping));
2950219d 908
2950219d 909 rxq->sw_rx_prod++;
fc48b7a6
YM		 910 curr_cons->data = NULL;
911}
912
f86af2df
MC		 913/* In case of allocation failures reuse buffers
914 * from consumer index to produce buffers for firmware
915 */
16f46bf0
SRK		 916void qede_recycle_rx_bd_ring(struct qede_rx_queue *rxq,
917 struct qede_dev *edev, u8 count)
f86af2df
MC		 918{
919 struct sw_rx_data *curr_cons;
920
921 for (; count > 0; count--) {
922 curr_cons = &rxq->sw_rx_ring[rxq->sw_rx_cons & NUM_RX_BDS_MAX];
923 qede_reuse_page(edev, rxq, curr_cons);
924 qede_rx_bd_ring_consume(rxq);
925 }
926}
927
fc48b7a6
YM		 928static inline int qede_realloc_rx_buffer(struct qede_dev *edev,
929 struct qede_rx_queue *rxq,
930 struct sw_rx_data *curr_cons)
931{
932 /* Move to the next segment in the page */
933 curr_cons->page_offset += rxq->rx_buf_seg_size;
934
935 if (curr_cons->page_offset == PAGE_SIZE) {
f86af2df
MC		 936 if (unlikely(qede_alloc_rx_buffer(edev, rxq))) {
937 /* Since we failed to allocate new buffer
938 * current buffer can be used again.
939 */
940 curr_cons->page_offset -= rxq->rx_buf_seg_size;
941
fc48b7a6 942 return -ENOMEM;
f86af2df 943 }
fc48b7a6
YM		 944
945 dma_unmap_page(&edev->pdev->dev, curr_cons->mapping,
946 PAGE_SIZE, DMA_FROM_DEVICE);
947 } else {
948 /* Increment refcount of the page as we don't want
949 * network stack to take the ownership of the page
950 * which can be recycled multiple times by the driver.
951 */
6d061f9f 952 page_ref_inc(curr_cons->data);
fc48b7a6
YM		 953 qede_reuse_page(edev, rxq, curr_cons);
954 }
955
956 return 0;
2950219d
YM		 957}
958
837d4eb6 959void qede_update_rx_prod(struct qede_dev *edev, struct qede_rx_queue *rxq)
2950219d
YM		 960{
961 u16 bd_prod = qed_chain_get_prod_idx(&rxq->rx_bd_ring);
962 u16 cqe_prod = qed_chain_get_prod_idx(&rxq->rx_comp_ring);
963 struct eth_rx_prod_data rx_prods = {0};
964
965 /* Update producers */
966 rx_prods.bd_prod = cpu_to_le16(bd_prod);
967 rx_prods.cqe_prod = cpu_to_le16(cqe_prod);
968
969 /* Make sure that the BD and SGE data is updated before updating the
970 * producers since FW might read the BD/SGE right after the producer
971 * is updated.
972 */
973 wmb();
974
975 internal_ram_wr(rxq->hw_rxq_prod_addr, sizeof(rx_prods),
976 (u32 *)&rx_prods);
977
978 /* mmiowb is needed to synchronize doorbell writes from more than one
979 * processor. It guarantees that the write arrives to the device before
980 * the napi lock is released and another qede_poll is called (possibly
981 * on another CPU). Without this barrier, the next doorbell can bypass
982 * this doorbell. This is applicable to IA64/Altix systems.
983 */
984 mmiowb();
985}
986
987static u32 qede_get_rxhash(struct qede_dev *edev,
988 u8 bitfields,
1a635e48 989 __le32 rss_hash, enum pkt_hash_types *rxhash_type)
2950219d
YM		 990{
991 enum rss_hash_type htype;
992
993 htype = GET_FIELD(bitfields, ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE);
994
995 if ((edev->ndev->features & NETIF_F_RXHASH) && htype) {
996 *rxhash_type = ((htype == RSS_HASH_TYPE_IPV4) ||
997 (htype == RSS_HASH_TYPE_IPV6)) ?
998 PKT_HASH_TYPE_L3 : PKT_HASH_TYPE_L4;
999 return le32_to_cpu(rss_hash);
1000 }
1001 *rxhash_type = PKT_HASH_TYPE_NONE;
1002 return 0;
1003}
1004
1005static void qede_set_skb_csum(struct sk_buff *skb, u8 csum_flag)
1006{
1007 skb_checksum_none_assert(skb);
1008
1009 if (csum_flag & QEDE_CSUM_UNNECESSARY)
1010 skb->ip_summed = CHECKSUM_UNNECESSARY;
14db81de
MC		 1011
1012 if (csum_flag & QEDE_TUNN_CSUM_UNNECESSARY)
1013 skb->csum_level = 1;
2950219d
YM		 1014}
1015
1016static inline void qede_skb_receive(struct qede_dev *edev,
1017 struct qede_fastpath *fp,
1a635e48 1018 struct sk_buff *skb, u16 vlan_tag)
2950219d
YM		 1019{
1020 if (vlan_tag)
1a635e48 1021 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag);
2950219d
YM		 1022
1023 napi_gro_receive(&fp->napi, skb);
f4fad34c 1024 fp->rxq->rcv_pkts++;
2950219d
YM		 1025}
1026
55482edc
MC		 1027static void qede_set_gro_params(struct qede_dev *edev,
1028 struct sk_buff *skb,
1029 struct eth_fast_path_rx_tpa_start_cqe *cqe)
1030{
1031 u16 parsing_flags = le16_to_cpu(cqe->pars_flags.flags);
1032
1033 if (((parsing_flags >> PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT) &
1034 PARSING_AND_ERR_FLAGS_L3TYPE_MASK) == 2)
1035 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
1036 else
1037 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
1038
1039 skb_shinfo(skb)->gso_size = __le16_to_cpu(cqe->len_on_first_bd) -
1040 cqe->header_len;
1041}
1042
1043static int qede_fill_frag_skb(struct qede_dev *edev,
1044 struct qede_rx_queue *rxq,
1a635e48 1045 u8 tpa_agg_index, u16 len_on_bd)
55482edc
MC		 1046{
1047 struct sw_rx_data *current_bd = &rxq->sw_rx_ring[rxq->sw_rx_cons &
1048 NUM_RX_BDS_MAX];
1049 struct qede_agg_info *tpa_info = &rxq->tpa_info[tpa_agg_index];
1050 struct sk_buff *skb = tpa_info->skb;
1051
01e23015 1052 if (unlikely(tpa_info->state != QEDE_AGG_STATE_START))
55482edc
MC		 1053 goto out;
1054
1055 /* Add one frag and update the appropriate fields in the skb */
1056 skb_fill_page_desc(skb, tpa_info->frag_id++,
1057 current_bd->data, current_bd->page_offset,
1058 len_on_bd);
1059
1060 if (unlikely(qede_realloc_rx_buffer(edev, rxq, current_bd))) {
f86af2df
MC		 1061 /* Incr page ref count to reuse on allocation failure
1062 * so that it doesn't get freed while freeing SKB.
1063 */
0139aa7b 1064 page_ref_inc(current_bd->data);
55482edc
MC		 1065 goto out;
1066 }
1067
1068 qed_chain_consume(&rxq->rx_bd_ring);
1069 rxq->sw_rx_cons++;
1070
1071 skb->data_len += len_on_bd;
1072 skb->truesize += rxq->rx_buf_seg_size;
1073 skb->len += len_on_bd;
1074
1075 return 0;
1076
1077out:
01e23015 1078 tpa_info->state = QEDE_AGG_STATE_ERROR;
f86af2df 1079 qede_recycle_rx_bd_ring(rxq, edev, 1);
55482edc
MC		 1080 return -ENOMEM;
1081}
1082
1083static void qede_tpa_start(struct qede_dev *edev,
1084 struct qede_rx_queue *rxq,
1085 struct eth_fast_path_rx_tpa_start_cqe *cqe)
1086{
1087 struct qede_agg_info *tpa_info = &rxq->tpa_info[cqe->tpa_agg_index];
1088 struct eth_rx_bd *rx_bd_cons = qed_chain_consume(&rxq->rx_bd_ring);
1089 struct eth_rx_bd *rx_bd_prod = qed_chain_produce(&rxq->rx_bd_ring);
01e23015
MY		 1090 struct sw_rx_data *replace_buf = &tpa_info->buffer;
1091 dma_addr_t mapping = tpa_info->buffer_mapping;
55482edc
MC		 1092 struct sw_rx_data *sw_rx_data_cons;
1093 struct sw_rx_data *sw_rx_data_prod;
1094 enum pkt_hash_types rxhash_type;
1095 u32 rxhash;
1096
1097 sw_rx_data_cons = &rxq->sw_rx_ring[rxq->sw_rx_cons & NUM_RX_BDS_MAX];
1098 sw_rx_data_prod = &rxq->sw_rx_ring[rxq->sw_rx_prod & NUM_RX_BDS_MAX];
1099
1100 /* Use pre-allocated replacement buffer - we can't release the agg.
1101 * start until its over and we don't want to risk allocation failing
1102 * here, so re-allocate when aggregation will be over.
1103 */
09ec8e7f 1104 sw_rx_data_prod->mapping = replace_buf->mapping;
55482edc
MC		 1105
1106 sw_rx_data_prod->data = replace_buf->data;
1107 rx_bd_prod->addr.hi = cpu_to_le32(upper_32_bits(mapping));
1108 rx_bd_prod->addr.lo = cpu_to_le32(lower_32_bits(mapping));
1109 sw_rx_data_prod->page_offset = replace_buf->page_offset;
1110
1111 rxq->sw_rx_prod++;
1112
1113 /* move partial skb from cons to pool (don't unmap yet)
1114 * save mapping, incase we drop the packet later on.
1115 */
01e23015 1116 tpa_info->buffer = *sw_rx_data_cons;
55482edc
MC		 1117 mapping = HILO_U64(le32_to_cpu(rx_bd_cons->addr.hi),
1118 le32_to_cpu(rx_bd_cons->addr.lo));
1119
01e23015 1120 tpa_info->buffer_mapping = mapping;
55482edc
MC		 1121 rxq->sw_rx_cons++;
1122
1123 /* set tpa state to start only if we are able to allocate skb
1124 * for this aggregation, otherwise mark as error and aggregation will
1125 * be dropped
1126 */
1127 tpa_info->skb = netdev_alloc_skb(edev->ndev,
1128 le16_to_cpu(cqe->len_on_first_bd));
1129 if (unlikely(!tpa_info->skb)) {
f86af2df 1130 DP_NOTICE(edev, "Failed to allocate SKB for gro\n");
01e23015 1131 tpa_info->state = QEDE_AGG_STATE_ERROR;
f86af2df 1132 goto cons_buf;
55482edc
MC		 1133 }
1134
55482edc 1135 /* Start filling in the aggregation info */
01e23015 1136 skb_put(tpa_info->skb, le16_to_cpu(cqe->len_on_first_bd));
55482edc 1137 tpa_info->frag_id = 0;
01e23015 1138 tpa_info->state = QEDE_AGG_STATE_START;
55482edc
MC		 1139
1140 rxhash = qede_get_rxhash(edev, cqe->bitfields,
1141 cqe->rss_hash, &rxhash_type);
1142 skb_set_hash(tpa_info->skb, rxhash, rxhash_type);
01e23015
MY		 1143
1144 /* Store some information from first CQE */
1145 tpa_info->start_cqe_placement_offset = cqe->placement_offset;
1146 tpa_info->start_cqe_bd_len = le16_to_cpu(cqe->len_on_first_bd);
55482edc
MC		 1147 if ((le16_to_cpu(cqe->pars_flags.flags) >>
1148 PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT) &
01e23015 1149 PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK)
55482edc
MC		 1150 tpa_info->vlan_tag = le16_to_cpu(cqe->vlan_tag);
1151 else
1152 tpa_info->vlan_tag = 0;
1153
1154 /* This is needed in order to enable forwarding support */
1155 qede_set_gro_params(edev, tpa_info->skb, cqe);
1156
f86af2df 1157cons_buf: /* We still need to handle bd_len_list to consume buffers */
55482edc
MC		 1158 if (likely(cqe->ext_bd_len_list[0]))
1159 qede_fill_frag_skb(edev, rxq, cqe->tpa_agg_index,
1160 le16_to_cpu(cqe->ext_bd_len_list[0]));
1161
1162 if (unlikely(cqe->ext_bd_len_list[1])) {
1163 DP_ERR(edev,
1164 "Unlikely - got a TPA aggregation with more than one ext_bd_len_list entry in the TPA start\n");
01e23015 1165 tpa_info->state = QEDE_AGG_STATE_ERROR;
55482edc
MC		 1166 }
1167}
1168
88f09bd5 1169#ifdef CONFIG_INET
55482edc
MC		 1170static void qede_gro_ip_csum(struct sk_buff *skb)
1171{
1172 const struct iphdr *iph = ip_hdr(skb);
1173 struct tcphdr *th;
1174
55482edc
MC		 1175 skb_set_transport_header(skb, sizeof(struct iphdr));
1176 th = tcp_hdr(skb);
1177
1178 th->check = ~tcp_v4_check(skb->len - skb_transport_offset(skb),
1179 iph->saddr, iph->daddr, 0);
1180
1181 tcp_gro_complete(skb);
1182}
1183
1184static void qede_gro_ipv6_csum(struct sk_buff *skb)
1185{
1186 struct ipv6hdr *iph = ipv6_hdr(skb);
1187 struct tcphdr *th;
1188
55482edc
MC		 1189 skb_set_transport_header(skb, sizeof(struct ipv6hdr));
1190 th = tcp_hdr(skb);
1191
1192 th->check = ~tcp_v6_check(skb->len - skb_transport_offset(skb),
1193 &iph->saddr, &iph->daddr, 0);
1194 tcp_gro_complete(skb);
1195}
88f09bd5 1196#endif
55482edc
MC		 1197
1198static void qede_gro_receive(struct qede_dev *edev,
1199 struct qede_fastpath *fp,
1200 struct sk_buff *skb,
1201 u16 vlan_tag)
1202{
ee2fa8e6
MC		 1203 /* FW can send a single MTU sized packet from gro flow
1204 * due to aggregation timeout/last segment etc. which
1205 * is not expected to be a gro packet. If a skb has zero
1206 * frags then simply push it in the stack as non gso skb.
1207 */
1208 if (unlikely(!skb->data_len)) {
1209 skb_shinfo(skb)->gso_type = 0;
1210 skb_shinfo(skb)->gso_size = 0;
1211 goto send_skb;
1212 }
1213
88f09bd5 1214#ifdef CONFIG_INET
55482edc 1215 if (skb_shinfo(skb)->gso_size) {
aad94c04
MC		 1216 skb_set_network_header(skb, 0);
1217
55482edc
MC		 1218 switch (skb->protocol) {
1219 case htons(ETH_P_IP):
1220 qede_gro_ip_csum(skb);
1221 break;
1222 case htons(ETH_P_IPV6):
1223 qede_gro_ipv6_csum(skb);
1224 break;
1225 default:
1226 DP_ERR(edev,
1227 "Error: FW GRO supports only IPv4/IPv6, not 0x%04x\n",
1228 ntohs(skb->protocol));
1229 }
1230 }
88f09bd5 1231#endif
ee2fa8e6
MC		 1232
1233send_skb:
9a4d7e86 1234 skb_record_rx_queue(skb, fp->rxq->rxq_id);
55482edc
MC		 1235 qede_skb_receive(edev, fp, skb, vlan_tag);
1236}
1237
1238static inline void qede_tpa_cont(struct qede_dev *edev,
1239 struct qede_rx_queue *rxq,
1240 struct eth_fast_path_rx_tpa_cont_cqe *cqe)
1241{
1242 int i;
1243
1244 for (i = 0; cqe->len_list[i]; i++)
1245 qede_fill_frag_skb(edev, rxq, cqe->tpa_agg_index,
1246 le16_to_cpu(cqe->len_list[i]));
1247
1248 if (unlikely(i > 1))
1249 DP_ERR(edev,
1250 "Strange - TPA cont with more than a single len_list entry\n");
1251}
1252
1253static void qede_tpa_end(struct qede_dev *edev,
1254 struct qede_fastpath *fp,
1255 struct eth_fast_path_rx_tpa_end_cqe *cqe)
1256{
1257 struct qede_rx_queue *rxq = fp->rxq;
1258 struct qede_agg_info *tpa_info;
1259 struct sk_buff *skb;
1260 int i;
1261
1262 tpa_info = &rxq->tpa_info[cqe->tpa_agg_index];
1263 skb = tpa_info->skb;
1264
1265 for (i = 0; cqe->len_list[i]; i++)
1266 qede_fill_frag_skb(edev, rxq, cqe->tpa_agg_index,
1267 le16_to_cpu(cqe->len_list[i]));
1268 if (unlikely(i > 1))
1269 DP_ERR(edev,
1270 "Strange - TPA emd with more than a single len_list entry\n");
1271
01e23015 1272 if (unlikely(tpa_info->state != QEDE_AGG_STATE_START))
55482edc
MC		 1273 goto err;
1274
1275 /* Sanity */
1276 if (unlikely(cqe->num_of_bds != tpa_info->frag_id + 1))
1277 DP_ERR(edev,
1278 "Strange - TPA had %02x BDs, but SKB has only %d frags\n",
1279 cqe->num_of_bds, tpa_info->frag_id);
1280 if (unlikely(skb->len != le16_to_cpu(cqe->total_packet_len)))
1281 DP_ERR(edev,
1282 "Strange - total packet len [cqe] is %4x but SKB has len %04x\n",
1283 le16_to_cpu(cqe->total_packet_len), skb->len);
1284
1285 memcpy(skb->data,
01e23015
MY		 1286 page_address(tpa_info->buffer.data) +
1287 tpa_info->start_cqe_placement_offset +
1288 tpa_info->buffer.page_offset, tpa_info->start_cqe_bd_len);
55482edc
MC		 1289
1290 /* Finalize the SKB */
1291 skb->protocol = eth_type_trans(skb, edev->ndev);
1292 skb->ip_summed = CHECKSUM_UNNECESSARY;
1293
1294 /* tcp_gro_complete() will copy NAPI_GRO_CB(skb)->count
1295 * to skb_shinfo(skb)->gso_segs
1296 */
1297 NAPI_GRO_CB(skb)->count = le16_to_cpu(cqe->num_of_coalesced_segs);
1298
1299 qede_gro_receive(edev, fp, skb, tpa_info->vlan_tag);
1300
01e23015 1301 tpa_info->state = QEDE_AGG_STATE_NONE;
55482edc
MC		 1302
1303 return;
1304err:
01e23015 1305 tpa_info->state = QEDE_AGG_STATE_NONE;
55482edc
MC		 1306 dev_kfree_skb_any(tpa_info->skb);
1307 tpa_info->skb = NULL;
1308}
1309
14db81de
MC		 1310static bool qede_tunn_exist(u16 flag)
1311{
1312 return !!(flag & (PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK <<
1313 PARSING_AND_ERR_FLAGS_TUNNELEXIST_SHIFT));
1314}
1315
1316static u8 qede_check_tunn_csum(u16 flag)
1317{
1318 u16 csum_flag = 0;
1319 u8 tcsum = 0;
1320
1321 if (flag & (PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK <<
1322 PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_SHIFT))
1323 csum_flag |= PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK <<
1324 PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT;
1325
1326 if (flag & (PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK <<
1327 PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT)) {
1328 csum_flag |= PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK <<
1329 PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT;
1330 tcsum = QEDE_TUNN_CSUM_UNNECESSARY;
1331 }
1332
1333 csum_flag |= PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_MASK <<
1334 PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_SHIFT |
1335 PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK <<
1336 PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT;
1337
1338 if (csum_flag & flag)
1339 return QEDE_CSUM_ERROR;
1340
1341 return QEDE_CSUM_UNNECESSARY | tcsum;
1342}
1343
1344static u8 qede_check_notunn_csum(u16 flag)
2950219d
YM		 1345{
1346 u16 csum_flag = 0;
1347 u8 csum = 0;
1348
14db81de
MC		 1349 if (flag & (PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK <<
1350 PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT)) {
2950219d
YM		 1351 csum_flag |= PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK <<
1352 PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT;
1353 csum = QEDE_CSUM_UNNECESSARY;
1354 }
1355
1356 csum_flag |= PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK <<
1357 PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT;
1358
1359 if (csum_flag & flag)
1360 return QEDE_CSUM_ERROR;
1361
1362 return csum;
1363}
1364
14db81de
MC		 1365static u8 qede_check_csum(u16 flag)
1366{
1367 if (!qede_tunn_exist(flag))
1368 return qede_check_notunn_csum(flag);
1369 else
1370 return qede_check_tunn_csum(flag);
1371}
1372
c72a6125
MC		 1373static bool qede_pkt_is_ip_fragmented(struct eth_fast_path_rx_reg_cqe *cqe,
1374 u16 flag)
1375{
1376 u8 tun_pars_flg = cqe->tunnel_pars_flags.flags;
1377
1378 if ((tun_pars_flg & (ETH_TUNNEL_PARSING_FLAGS_IPV4_FRAGMENT_MASK <<
1379 ETH_TUNNEL_PARSING_FLAGS_IPV4_FRAGMENT_SHIFT)) ||
1380 (flag & (PARSING_AND_ERR_FLAGS_IPV4FRAG_MASK <<
1381 PARSING_AND_ERR_FLAGS_IPV4FRAG_SHIFT)))
1382 return true;
1383
1384 return false;
1385}
1386
f4fad34c
MY		 1387static struct sk_buff *qede_rx_allocate_skb(struct qede_dev *edev,
1388 struct qede_rx_queue *rxq,
1389 struct sw_rx_data *bd, u16 len,
1390 u16 pad)
2950219d 1391{
f4fad34c
MY		 1392 unsigned int offset = bd->page_offset;
1393 struct skb_frag_struct *frag;
1394 struct page *page = bd->data;
1395 unsigned int pull_len;
1396 struct sk_buff *skb;
1397 unsigned char *va;
2950219d 1398
f4fad34c
MY		 1399 /* Allocate a new SKB with a sufficient large header len */
1400 skb = netdev_alloc_skb(edev->ndev, QEDE_RX_HDR_SIZE);
1401 if (unlikely(!skb))
1402 return NULL;
2950219d 1403
f4fad34c
MY		 1404 /* Copy data into SKB - if it's small, we can simply copy it and
1405 * re-use the already allcoated & mapped memory.
2950219d 1406 */
f4fad34c
MY		 1407 if (len + pad <= edev->rx_copybreak) {
1408 memcpy(skb_put(skb, len),
1409 page_address(page) + pad + offset, len);
1410 qede_reuse_page(edev, rxq, bd);
1411 goto out;
1412 }
2950219d 1413
f4fad34c 1414 frag = &skb_shinfo(skb)->frags[0];
2950219d 1415
f4fad34c
MY		 1416 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
1417 page, pad + offset, len, rxq->rx_buf_seg_size);
55482edc 1418
f4fad34c
MY		 1419 va = skb_frag_address(frag);
1420 pull_len = eth_get_headlen(va, QEDE_RX_HDR_SIZE);
c72a6125 1421
f4fad34c
MY		 1422 /* Align the pull_len to optimize memcpy */
1423 memcpy(skb->data, va, ALIGN(pull_len, sizeof(long)));
2950219d 1424
f4fad34c
MY		 1425 /* Correct the skb & frag sizes offset after the pull */
1426 skb_frag_size_sub(frag, pull_len);
1427 frag->page_offset += pull_len;
1428 skb->data_len -= pull_len;
1429 skb->tail += pull_len;
1430
1431 if (unlikely(qede_realloc_rx_buffer(edev, rxq, bd))) {
1432 /* Incr page ref count to reuse on allocation failure so
1433 * that it doesn't get freed while freeing SKB [as its
1434 * already mapped there].
1435 */
1436 page_ref_inc(page);
1437 dev_kfree_skb_any(skb);
1438 return NULL;
1439 }
1440
1441out:
1442 /* We've consumed the first BD and prepared an SKB */
1443 qede_rx_bd_ring_consume(rxq);
1444 return skb;
1445}
1446
1447static int qede_rx_build_jumbo(struct qede_dev *edev,
1448 struct qede_rx_queue *rxq,
1449 struct sk_buff *skb,
1450 struct eth_fast_path_rx_reg_cqe *cqe,
1451 u16 first_bd_len)
1452{
1453 u16 pkt_len = le16_to_cpu(cqe->pkt_len);
1454 struct sw_rx_data *bd;
1455 u16 bd_cons_idx;
1456 u8 num_frags;
1457
1458 pkt_len -= first_bd_len;
1459
1460 /* We've already used one BD for the SKB. Now take care of the rest */
1461 for (num_frags = cqe->bd_num - 1; num_frags > 0; num_frags--) {
1462 u16 cur_size = pkt_len > rxq->rx_buf_size ? rxq->rx_buf_size :
1463 pkt_len;
1464
1465 if (unlikely(!cur_size)) {
1466 DP_ERR(edev,
1467 "Still got %d BDs for mapping jumbo, but length became 0\n",
1468 num_frags);
1469 goto out;
fc48b7a6
YM		 1470 }
1471
f4fad34c
MY		 1472 /* We need a replacement buffer for each BD */
1473 if (unlikely(qede_alloc_rx_buffer(edev, rxq)))
1474 goto out;
1475
1476 /* Now that we've allocated the replacement buffer,
1477 * we can safely consume the next BD and map it to the SKB.
1478 */
1479 bd_cons_idx = rxq->sw_rx_cons & NUM_RX_BDS_MAX;
1480 bd = &rxq->sw_rx_ring[bd_cons_idx];
1481 qede_rx_bd_ring_consume(rxq);
1482
1483 dma_unmap_page(&edev->pdev->dev, bd->mapping,
1484 PAGE_SIZE, DMA_FROM_DEVICE);
1485
1486 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags++,
1487 bd->data, 0, cur_size);
1488
1489 skb->truesize += PAGE_SIZE;
1490 skb->data_len += cur_size;
1491 skb->len += cur_size;
1492 pkt_len -= cur_size;
1493 }
1494
1495 if (unlikely(pkt_len))
1496 DP_ERR(edev,
1497 "Mapped all BDs of jumbo, but still have %d bytes\n",
1498 pkt_len);
1499
1500out:
1501 return num_frags;
1502}
1503
1504static int qede_rx_process_tpa_cqe(struct qede_dev *edev,
1505 struct qede_fastpath *fp,
1506 struct qede_rx_queue *rxq,
1507 union eth_rx_cqe *cqe,
1508 enum eth_rx_cqe_type type)
1509{
1510 switch (type) {
1511 case ETH_RX_CQE_TYPE_TPA_START:
1512 qede_tpa_start(edev, rxq, &cqe->fast_path_tpa_start);
1513 return 0;
1514 case ETH_RX_CQE_TYPE_TPA_CONT:
1515 qede_tpa_cont(edev, rxq, &cqe->fast_path_tpa_cont);
1516 return 0;
1517 case ETH_RX_CQE_TYPE_TPA_END:
1518 qede_tpa_end(edev, fp, &cqe->fast_path_tpa_end);
1519 return 1;
1520 default:
1521 return 0;
1522 }
1523}
1524
1525static int qede_rx_process_cqe(struct qede_dev *edev,
1526 struct qede_fastpath *fp,
1527 struct qede_rx_queue *rxq)
1528{
1529 struct eth_fast_path_rx_reg_cqe *fp_cqe;
1530 u16 len, pad, bd_cons_idx, parse_flag;
1531 enum pkt_hash_types rxhash_type;
1532 enum eth_rx_cqe_type cqe_type;
1533 union eth_rx_cqe *cqe;
1534 struct sw_rx_data *bd;
1535 struct sk_buff *skb;
1536 __le16 flags;
1537 u8 csum_flag;
1538 u32 rx_hash;
1539
1540 /* Get the CQE from the completion ring */
1541 cqe = (union eth_rx_cqe *)qed_chain_consume(&rxq->rx_comp_ring);
1542 cqe_type = cqe->fast_path_regular.type;
1543
1544 /* Process an unlikely slowpath event */
1545 if (unlikely(cqe_type == ETH_RX_CQE_TYPE_SLOW_PATH)) {
1546 struct eth_slow_path_rx_cqe *sp_cqe;
1547
1548 sp_cqe = (struct eth_slow_path_rx_cqe *)cqe;
1549 edev->ops->eth_cqe_completion(edev->cdev, fp->id, sp_cqe);
1550 return 0;
1551 }
1552
1553 /* Handle TPA cqes */
1554 if (cqe_type != ETH_RX_CQE_TYPE_REGULAR)
1555 return qede_rx_process_tpa_cqe(edev, fp, rxq, cqe, cqe_type);
1556
1557 /* Get the data from the SW ring; Consume it only after it's evident
1558 * we wouldn't recycle it.
1559 */
1560 bd_cons_idx = rxq->sw_rx_cons & NUM_RX_BDS_MAX;
1561 bd = &rxq->sw_rx_ring[bd_cons_idx];
1562
1563 fp_cqe = &cqe->fast_path_regular;
1564 len = le16_to_cpu(fp_cqe->len_on_first_bd);
1565 pad = fp_cqe->placement_offset;
1566
1567 /* If this is an error packet then drop it */
1568 flags = cqe->fast_path_regular.pars_flags.flags;
1569 parse_flag = le16_to_cpu(flags);
1570
1571 csum_flag = qede_check_csum(parse_flag);
1572 if (unlikely(csum_flag == QEDE_CSUM_ERROR)) {
1573 if (qede_pkt_is_ip_fragmented(fp_cqe, parse_flag)) {
1574 rxq->rx_ip_frags++;
fc48b7a6 1575 } else {
f4fad34c
MY		 1576 DP_NOTICE(edev,
1577 "CQE has error, flags = %x, dropping incoming packet\n",
1578 parse_flag);
1579 rxq->rx_hw_errors++;
1580 qede_recycle_rx_bd_ring(rxq, edev, fp_cqe->bd_num);
1581 return 0;
2950219d 1582 }
f4fad34c 1583 }
2950219d 1584
f4fad34c
MY		 1585 /* Basic validation passed; Need to prepare an SKB. This would also
1586 * guarantee to finally consume the first BD upon success.
1587 */
1588 skb = qede_rx_allocate_skb(edev, rxq, bd, len, pad);
1589 if (!skb) {
1590 rxq->rx_alloc_errors++;
1591 qede_recycle_rx_bd_ring(rxq, edev, fp_cqe->bd_num);
1592 return 0;
1593 }
f86af2df 1594
f4fad34c
MY		 1595 /* In case of Jumbo packet, several PAGE_SIZEd buffers will be pointed
1596 * by a single cqe.
1597 */
1598 if (fp_cqe->bd_num > 1) {
1599 u16 unmapped_frags = qede_rx_build_jumbo(edev, rxq, skb,
1600 fp_cqe, len);
2950219d 1601
f4fad34c
MY		 1602 if (unlikely(unmapped_frags > 0)) {
1603 qede_recycle_rx_bd_ring(rxq, edev, unmapped_frags);
1604 dev_kfree_skb_any(skb);
1605 return 0;
fc48b7a6 1606 }
f4fad34c 1607 }
2950219d 1608
f4fad34c
MY		 1609 /* The SKB contains all the data. Now prepare meta-magic */
1610 skb->protocol = eth_type_trans(skb, edev->ndev);
1611 rx_hash = qede_get_rxhash(edev, fp_cqe->bitfields,
1612 fp_cqe->rss_hash, &rxhash_type);
1613 skb_set_hash(skb, rx_hash, rxhash_type);
1614 qede_set_skb_csum(skb, csum_flag);
1615 skb_record_rx_queue(skb, rxq->rxq_id);
2950219d 1616
f4fad34c
MY		 1617 /* SKB is prepared - pass it to stack */
1618 qede_skb_receive(edev, fp, skb, le16_to_cpu(fp_cqe->vlan_tag));
2950219d 1619
f4fad34c
MY		 1620 return 1;
1621}
2950219d 1622
f4fad34c
MY		 1623static int qede_rx_int(struct qede_fastpath *fp, int budget)
1624{
1625 struct qede_rx_queue *rxq = fp->rxq;
1626 struct qede_dev *edev = fp->edev;
1627 u16 hw_comp_cons, sw_comp_cons;
1628 int work_done = 0;
2950219d 1629
f4fad34c
MY		 1630 hw_comp_cons = le16_to_cpu(*rxq->hw_cons_ptr);
1631 sw_comp_cons = qed_chain_get_cons_idx(&rxq->rx_comp_ring);
2950219d 1632
f4fad34c
MY		 1633 /* Memory barrier to prevent the CPU from doing speculative reads of CQE
1634 * / BD in the while-loop before reading hw_comp_cons. If the CQE is
1635 * read before it is written by FW, then FW writes CQE and SB, and then
1636 * the CPU reads the hw_comp_cons, it will use an old CQE.
1637 */
1638 rmb();
2950219d 1639
f4fad34c
MY		 1640 /* Loop to complete all indicated BDs */
1641 while ((sw_comp_cons != hw_comp_cons) && (work_done < budget)) {
1642 qede_rx_process_cqe(edev, fp, rxq);
2950219d
YM		 1643 qed_chain_recycle_consumed(&rxq->rx_comp_ring);
1644 sw_comp_cons = qed_chain_get_cons_idx(&rxq->rx_comp_ring);
f4fad34c
MY		 1645 work_done++;
1646 }
2950219d
YM		 1647
1648 /* Update producers */
1649 qede_update_rx_prod(edev, rxq);
1650
f4fad34c
MY		 1651 return work_done;
1652}
1653
1654static bool qede_poll_is_more_work(struct qede_fastpath *fp)
1655{
1656 qed_sb_update_sb_idx(fp->sb_info);
1657
1658 /* *_has_*_work() reads the status block, thus we need to ensure that
1659 * status block indices have been actually read (qed_sb_update_sb_idx)
1660 * prior to this check (*_has_*_work) so that we won't write the
1661 * "newer" value of the status block to HW (if there was a DMA right
1662 * after qede_has_rx_work and if there is no rmb, the memory reading
1663 * (qed_sb_update_sb_idx) may be postponed to right before *_ack_sb).
1664 * In this case there will never be another interrupt until there is
1665 * another update of the status block, while there is still unhandled
1666 * work.
1667 */
1668 rmb();
1669
1670 if (likely(fp->type & QEDE_FASTPATH_RX))
1671 if (qede_has_rx_work(fp->rxq))
1672 return true;
1673
1674 if (likely(fp->type & QEDE_FASTPATH_TX))
1675 if (qede_txq_has_work(fp->txq))
1676 return true;
68db9ec2 1677
f4fad34c 1678 return false;
2950219d
YM		 1679}
1680
1681static int qede_poll(struct napi_struct *napi, int budget)
1682{
2950219d 1683 struct qede_fastpath *fp = container_of(napi, struct qede_fastpath,
c774169d 1684 napi);
2950219d 1685 struct qede_dev *edev = fp->edev;
c774169d 1686 int rx_work_done = 0;
2950219d 1687
80439a17
MY		 1688 if (likely(fp->type & QEDE_FASTPATH_TX) && qede_txq_has_work(fp->txq))
1689 qede_tx_int(edev, fp->txq);
c774169d 1690
9a4d7e86
SRK		 1691 rx_work_done = (likely(fp->type & QEDE_FASTPATH_RX) &&
1692 qede_has_rx_work(fp->rxq)) ?
c774169d
MC		 1693 qede_rx_int(fp, budget) : 0;
1694 if (rx_work_done < budget) {
f4fad34c 1695 if (!qede_poll_is_more_work(fp)) {
c774169d
MC		 1696 napi_complete(napi);
1697
1698 /* Update and reenable interrupts */
f4fad34c 1699 qed_sb_ack(fp->sb_info, IGU_INT_ENABLE, 1);
c774169d
MC		 1700 } else {
1701 rx_work_done = budget;
2950219d
YM		 1702 }
1703 }
1704
c774169d 1705 return rx_work_done;
2950219d
YM		 1706}
1707
1708static irqreturn_t qede_msix_fp_int(int irq, void *fp_cookie)
1709{
1710 struct qede_fastpath *fp = fp_cookie;
1711
1712 qed_sb_ack(fp->sb_info, IGU_INT_DISABLE, 0 /*do not update*/);
1713
1714 napi_schedule_irqoff(&fp->napi);
1715 return IRQ_HANDLED;
1716}
1717
1718/* -------------------------------------------------------------------------
1719 * END OF FAST-PATH
1720 * -------------------------------------------------------------------------
1721 */
1722
1723static int qede_open(struct net_device *ndev);
1724static int qede_close(struct net_device *ndev);
0d8e0aa0
SK		 1725static int qede_set_mac_addr(struct net_device *ndev, void *p);
1726static void qede_set_rx_mode(struct net_device *ndev);
1727static void qede_config_rx_mode(struct net_device *ndev);
1728
1729static int qede_set_ucast_rx_mac(struct qede_dev *edev,
1730 enum qed_filter_xcast_params_type opcode,
1731 unsigned char mac[ETH_ALEN])
1732{
1733 struct qed_filter_params filter_cmd;
1734
1735 memset(&filter_cmd, 0, sizeof(filter_cmd));
1736 filter_cmd.type = QED_FILTER_TYPE_UCAST;
1737 filter_cmd.filter.ucast.type = opcode;
1738 filter_cmd.filter.ucast.mac_valid = 1;
1739 ether_addr_copy(filter_cmd.filter.ucast.mac, mac);
1740
1741 return edev->ops->filter_config(edev->cdev, &filter_cmd);
1742}
1743
7c1bfcad
SRK		 1744static int qede_set_ucast_rx_vlan(struct qede_dev *edev,
1745 enum qed_filter_xcast_params_type opcode,
1746 u16 vid)
1747{
1748 struct qed_filter_params filter_cmd;
1749
1750 memset(&filter_cmd, 0, sizeof(filter_cmd));
1751 filter_cmd.type = QED_FILTER_TYPE_UCAST;
1752 filter_cmd.filter.ucast.type = opcode;
1753 filter_cmd.filter.ucast.vlan_valid = 1;
1754 filter_cmd.filter.ucast.vlan = vid;
1755
1756 return edev->ops->filter_config(edev->cdev, &filter_cmd);
1757}
1758
133fac0e
SK		 1759void qede_fill_by_demand_stats(struct qede_dev *edev)
1760{
1761 struct qed_eth_stats stats;
1762
1763 edev->ops->get_vport_stats(edev->cdev, &stats);
1764 edev->stats.no_buff_discards = stats.no_buff_discards;
1a5a366f
SRK		 1765 edev->stats.packet_too_big_discard = stats.packet_too_big_discard;
1766 edev->stats.ttl0_discard = stats.ttl0_discard;
133fac0e
SK		 1767 edev->stats.rx_ucast_bytes = stats.rx_ucast_bytes;
1768 edev->stats.rx_mcast_bytes = stats.rx_mcast_bytes;
1769 edev->stats.rx_bcast_bytes = stats.rx_bcast_bytes;
1770 edev->stats.rx_ucast_pkts = stats.rx_ucast_pkts;
1771 edev->stats.rx_mcast_pkts = stats.rx_mcast_pkts;
1772 edev->stats.rx_bcast_pkts = stats.rx_bcast_pkts;
1773 edev->stats.mftag_filter_discards = stats.mftag_filter_discards;
1774 edev->stats.mac_filter_discards = stats.mac_filter_discards;
1775
1776 edev->stats.tx_ucast_bytes = stats.tx_ucast_bytes;
1777 edev->stats.tx_mcast_bytes = stats.tx_mcast_bytes;
1778 edev->stats.tx_bcast_bytes = stats.tx_bcast_bytes;
1779 edev->stats.tx_ucast_pkts = stats.tx_ucast_pkts;
1780 edev->stats.tx_mcast_pkts = stats.tx_mcast_pkts;
1781 edev->stats.tx_bcast_pkts = stats.tx_bcast_pkts;
1782 edev->stats.tx_err_drop_pkts = stats.tx_err_drop_pkts;
1783 edev->stats.coalesced_pkts = stats.tpa_coalesced_pkts;
1784 edev->stats.coalesced_events = stats.tpa_coalesced_events;
1785 edev->stats.coalesced_aborts_num = stats.tpa_aborts_num;
1786 edev->stats.non_coalesced_pkts = stats.tpa_not_coalesced_pkts;
1787 edev->stats.coalesced_bytes = stats.tpa_coalesced_bytes;
1788
1789 edev->stats.rx_64_byte_packets = stats.rx_64_byte_packets;
d4967cf3
YM		 1790 edev->stats.rx_65_to_127_byte_packets = stats.rx_65_to_127_byte_packets;
1791 edev->stats.rx_128_to_255_byte_packets =
1792 stats.rx_128_to_255_byte_packets;
1793 edev->stats.rx_256_to_511_byte_packets =
1794 stats.rx_256_to_511_byte_packets;
1795 edev->stats.rx_512_to_1023_byte_packets =
1796 stats.rx_512_to_1023_byte_packets;
1797 edev->stats.rx_1024_to_1518_byte_packets =
1798 stats.rx_1024_to_1518_byte_packets;
1799 edev->stats.rx_1519_to_1522_byte_packets =
1800 stats.rx_1519_to_1522_byte_packets;
1801 edev->stats.rx_1519_to_2047_byte_packets =
1802 stats.rx_1519_to_2047_byte_packets;
1803 edev->stats.rx_2048_to_4095_byte_packets =
1804 stats.rx_2048_to_4095_byte_packets;
1805 edev->stats.rx_4096_to_9216_byte_packets =
1806 stats.rx_4096_to_9216_byte_packets;
1807 edev->stats.rx_9217_to_16383_byte_packets =
1808 stats.rx_9217_to_16383_byte_packets;
133fac0e
SK		 1809 edev->stats.rx_crc_errors = stats.rx_crc_errors;
1810 edev->stats.rx_mac_crtl_frames = stats.rx_mac_crtl_frames;
1811 edev->stats.rx_pause_frames = stats.rx_pause_frames;
1812 edev->stats.rx_pfc_frames = stats.rx_pfc_frames;
1813 edev->stats.rx_align_errors = stats.rx_align_errors;
1814 edev->stats.rx_carrier_errors = stats.rx_carrier_errors;
1815 edev->stats.rx_oversize_packets = stats.rx_oversize_packets;
1816 edev->stats.rx_jabbers = stats.rx_jabbers;
1817 edev->stats.rx_undersize_packets = stats.rx_undersize_packets;
1818 edev->stats.rx_fragments = stats.rx_fragments;
1819 edev->stats.tx_64_byte_packets = stats.tx_64_byte_packets;
1820 edev->stats.tx_65_to_127_byte_packets = stats.tx_65_to_127_byte_packets;
1821 edev->stats.tx_128_to_255_byte_packets =
1822 stats.tx_128_to_255_byte_packets;
1823 edev->stats.tx_256_to_511_byte_packets =
1824 stats.tx_256_to_511_byte_packets;
1825 edev->stats.tx_512_to_1023_byte_packets =
1826 stats.tx_512_to_1023_byte_packets;
1827 edev->stats.tx_1024_to_1518_byte_packets =
1828 stats.tx_1024_to_1518_byte_packets;
1829 edev->stats.tx_1519_to_2047_byte_packets =
1830 stats.tx_1519_to_2047_byte_packets;
1831 edev->stats.tx_2048_to_4095_byte_packets =
1832 stats.tx_2048_to_4095_byte_packets;
1833 edev->stats.tx_4096_to_9216_byte_packets =
1834 stats.tx_4096_to_9216_byte_packets;
1835 edev->stats.tx_9217_to_16383_byte_packets =
1836 stats.tx_9217_to_16383_byte_packets;
1837 edev->stats.tx_pause_frames = stats.tx_pause_frames;
1838 edev->stats.tx_pfc_frames = stats.tx_pfc_frames;
1839 edev->stats.tx_lpi_entry_count = stats.tx_lpi_entry_count;
1840 edev->stats.tx_total_collisions = stats.tx_total_collisions;
1841 edev->stats.brb_truncates = stats.brb_truncates;
1842 edev->stats.brb_discards = stats.brb_discards;
1843 edev->stats.tx_mac_ctrl_frames = stats.tx_mac_ctrl_frames;
1844}
1845
1a635e48
YM		 1846static
1847struct rtnl_link_stats64 *qede_get_stats64(struct net_device *dev,
1848 struct rtnl_link_stats64 *stats)
133fac0e
SK		 1849{
1850 struct qede_dev *edev = netdev_priv(dev);
1851
1852 qede_fill_by_demand_stats(edev);
1853
1854 stats->rx_packets = edev->stats.rx_ucast_pkts +
1855 edev->stats.rx_mcast_pkts +
1856 edev->stats.rx_bcast_pkts;
1857 stats->tx_packets = edev->stats.tx_ucast_pkts +
1858 edev->stats.tx_mcast_pkts +
1859 edev->stats.tx_bcast_pkts;
1860
1861 stats->rx_bytes = edev->stats.rx_ucast_bytes +
1862 edev->stats.rx_mcast_bytes +
1863 edev->stats.rx_bcast_bytes;
1864
1865 stats->tx_bytes = edev->stats.tx_ucast_bytes +
1866 edev->stats.tx_mcast_bytes +
1867 edev->stats.tx_bcast_bytes;
1868
1869 stats->tx_errors = edev->stats.tx_err_drop_pkts;
1870 stats->multicast = edev->stats.rx_mcast_pkts +
1871 edev->stats.rx_bcast_pkts;
1872
1873 stats->rx_fifo_errors = edev->stats.no_buff_discards;
1874
1875 stats->collisions = edev->stats.tx_total_collisions;
1876 stats->rx_crc_errors = edev->stats.rx_crc_errors;
1877 stats->rx_frame_errors = edev->stats.rx_align_errors;
1878
1879 return stats;
1880}
1881
733def6a 1882#ifdef CONFIG_QED_SRIOV
73390ac9
YM		 1883static int qede_get_vf_config(struct net_device *dev, int vfidx,
1884 struct ifla_vf_info *ivi)
1885{
1886 struct qede_dev *edev = netdev_priv(dev);
1887
1888 if (!edev->ops)
1889 return -EINVAL;
1890
1891 return edev->ops->iov->get_config(edev->cdev, vfidx, ivi);
1892}
1893
733def6a
YM		 1894static int qede_set_vf_rate(struct net_device *dev, int vfidx,
1895 int min_tx_rate, int max_tx_rate)
1896{
1897 struct qede_dev *edev = netdev_priv(dev);
1898
be7b6d64 1899 return edev->ops->iov->set_rate(edev->cdev, vfidx, min_tx_rate,
733def6a
YM		 1900 max_tx_rate);
1901}
1902
6ddc7608
YM		 1903static int qede_set_vf_spoofchk(struct net_device *dev, int vfidx, bool val)
1904{
1905 struct qede_dev *edev = netdev_priv(dev);
1906
1907 if (!edev->ops)
1908 return -EINVAL;
1909
1910 return edev->ops->iov->set_spoof(edev->cdev, vfidx, val);
1911}
1912
733def6a
YM		 1913static int qede_set_vf_link_state(struct net_device *dev, int vfidx,
1914 int link_state)
1915{
1916 struct qede_dev *edev = netdev_priv(dev);
1917
1918 if (!edev->ops)
1919 return -EINVAL;
1920
1921 return edev->ops->iov->set_link_state(edev->cdev, vfidx, link_state);
1922}
1923#endif
1924
7c1bfcad
SRK		 1925static void qede_config_accept_any_vlan(struct qede_dev *edev, bool action)
1926{
1927 struct qed_update_vport_params params;
1928 int rc;
1929
1930 /* Proceed only if action actually needs to be performed */
1931 if (edev->accept_any_vlan == action)
1932 return;
1933
1934 memset(&params, 0, sizeof(params));
1935
1936 params.vport_id = 0;
1937 params.accept_any_vlan = action;
1938 params.update_accept_any_vlan_flg = 1;
1939
1940 rc = edev->ops->vport_update(edev->cdev, &params);
1941 if (rc) {
1942 DP_ERR(edev, "Failed to %s accept-any-vlan\n",
1943 action ? "enable" : "disable");
1944 } else {
1945 DP_INFO(edev, "%s accept-any-vlan\n",
1946 action ? "enabled" : "disabled");
1947 edev->accept_any_vlan = action;
1948 }
1949}
1950
1951static int qede_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid)
1952{
1953 struct qede_dev *edev = netdev_priv(dev);
1954 struct qede_vlan *vlan, *tmp;
1955 int rc;
1956
1957 DP_VERBOSE(edev, NETIF_MSG_IFUP, "Adding vlan 0x%04x\n", vid);
1958
1959 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
1960 if (!vlan) {
1961 DP_INFO(edev, "Failed to allocate struct for vlan\n");
1962 return -ENOMEM;
1963 }
1964 INIT_LIST_HEAD(&vlan->list);
1965 vlan->vid = vid;
1966 vlan->configured = false;
1967
1968 /* Verify vlan isn't already configured */
1969 list_for_each_entry(tmp, &edev->vlan_list, list) {
1970 if (tmp->vid == vlan->vid) {
1971 DP_VERBOSE(edev, (NETIF_MSG_IFUP | NETIF_MSG_IFDOWN),
1972 "vlan already configured\n");
1973 kfree(vlan);
1974 return -EEXIST;
1975 }
1976 }
1977
1978 /* If interface is down, cache this VLAN ID and return */
1979 if (edev->state != QEDE_STATE_OPEN) {
1980 DP_VERBOSE(edev, NETIF_MSG_IFDOWN,
1981 "Interface is down, VLAN %d will be configured when interface is up\n",
1982 vid);
1983 if (vid != 0)
1984 edev->non_configured_vlans++;
1985 list_add(&vlan->list, &edev->vlan_list);
1986
1987 return 0;
1988 }
1989
1990 /* Check for the filter limit.
1991 * Note - vlan0 has a reserved filter and can be added without
1992 * worrying about quota
1993 */
1994 if ((edev->configured_vlans < edev->dev_info.num_vlan_filters) ||
1995 (vlan->vid == 0)) {
1996 rc = qede_set_ucast_rx_vlan(edev,
1997 QED_FILTER_XCAST_TYPE_ADD,
1998 vlan->vid);
1999 if (rc) {
2000 DP_ERR(edev, "Failed to configure VLAN %d\n",
2001 vlan->vid);
2002 kfree(vlan);
2003 return -EINVAL;
2004 }
2005 vlan->configured = true;
2006
2007 /* vlan0 filter isn't consuming out of our quota */
2008 if (vlan->vid != 0)
2009 edev->configured_vlans++;
2010 } else {
2011 /* Out of quota; Activate accept-any-VLAN mode */
2012 if (!edev->non_configured_vlans)
2013 qede_config_accept_any_vlan(edev, true);
2014
2015 edev->non_configured_vlans++;
2016 }
2017
2018 list_add(&vlan->list, &edev->vlan_list);
2019
2020 return 0;
2021}
2022
2023static void qede_del_vlan_from_list(struct qede_dev *edev,
2024 struct qede_vlan *vlan)
2025{
2026 /* vlan0 filter isn't consuming out of our quota */
2027 if (vlan->vid != 0) {
2028 if (vlan->configured)
2029 edev->configured_vlans--;
2030 else
2031 edev->non_configured_vlans--;
2032 }
2033
2034 list_del(&vlan->list);
2035 kfree(vlan);
2036}
2037
2038static int qede_configure_vlan_filters(struct qede_dev *edev)
2039{
2040 int rc = 0, real_rc = 0, accept_any_vlan = 0;
2041 struct qed_dev_eth_info *dev_info;
2042 struct qede_vlan *vlan = NULL;
2043
2044 if (list_empty(&edev->vlan_list))
2045 return 0;
2046
2047 dev_info = &edev->dev_info;
2048
2049 /* Configure non-configured vlans */
2050 list_for_each_entry(vlan, &edev->vlan_list, list) {
2051 if (vlan->configured)
2052 continue;
2053
2054 /* We have used all our credits, now enable accept_any_vlan */
2055 if ((vlan->vid != 0) &&
2056 (edev->configured_vlans == dev_info->num_vlan_filters)) {
2057 accept_any_vlan = 1;
2058 continue;
2059 }
2060
2061 DP_VERBOSE(edev, NETIF_MSG_IFUP, "Adding vlan %d\n", vlan->vid);
2062
2063 rc = qede_set_ucast_rx_vlan(edev, QED_FILTER_XCAST_TYPE_ADD,
2064 vlan->vid);
2065 if (rc) {
2066 DP_ERR(edev, "Failed to configure VLAN %u\n",
2067 vlan->vid);
2068 real_rc = rc;
2069 continue;
2070 }
2071
2072 vlan->configured = true;
2073 /* vlan0 filter doesn't consume our VLAN filter's quota */
2074 if (vlan->vid != 0) {
2075 edev->non_configured_vlans--;
2076 edev->configured_vlans++;
2077 }
2078 }
2079
2080 /* enable accept_any_vlan mode if we have more VLANs than credits,
2081 * or remove accept_any_vlan mode if we've actually removed
2082 * a non-configured vlan, and all remaining vlans are truly configured.
2083 */
2084
2085 if (accept_any_vlan)
2086 qede_config_accept_any_vlan(edev, true);
2087 else if (!edev->non_configured_vlans)
2088 qede_config_accept_any_vlan(edev, false);
2089
2090 return real_rc;
2091}
2092
2093static int qede_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid)
2094{
2095 struct qede_dev *edev = netdev_priv(dev);
2096 struct qede_vlan *vlan = NULL;
2097 int rc;
2098
2099 DP_VERBOSE(edev, NETIF_MSG_IFDOWN, "Removing vlan 0x%04x\n", vid);
2100
2101 /* Find whether entry exists */
2102 list_for_each_entry(vlan, &edev->vlan_list, list)
2103 if (vlan->vid == vid)
2104 break;
2105
2106 if (!vlan || (vlan->vid != vid)) {
2107 DP_VERBOSE(edev, (NETIF_MSG_IFUP | NETIF_MSG_IFDOWN),
2108 "Vlan isn't configured\n");
2109 return 0;
2110 }
2111
2112 if (edev->state != QEDE_STATE_OPEN) {
2113 /* As interface is already down, we don't have a VPORT
2114 * instance to remove vlan filter. So just update vlan list
2115 */
2116 DP_VERBOSE(edev, NETIF_MSG_IFDOWN,
2117 "Interface is down, removing VLAN from list only\n");
2118 qede_del_vlan_from_list(edev, vlan);
2119 return 0;
2120 }
2121
2122 /* Remove vlan */
c524e2f5
YM		 2123 if (vlan->configured) {
2124 rc = qede_set_ucast_rx_vlan(edev, QED_FILTER_XCAST_TYPE_DEL,
2125 vid);
2126 if (rc) {
2127 DP_ERR(edev, "Failed to remove VLAN %d\n", vid);
2128 return -EINVAL;
2129 }
7c1bfcad
SRK		 2130 }
2131
2132 qede_del_vlan_from_list(edev, vlan);
2133
2134 /* We have removed a VLAN - try to see if we can
2135 * configure non-configured VLAN from the list.
2136 */
2137 rc = qede_configure_vlan_filters(edev);
2138
2139 return rc;
2140}
2141
2142static void qede_vlan_mark_nonconfigured(struct qede_dev *edev)
2143{
2144 struct qede_vlan *vlan = NULL;
2145
2146 if (list_empty(&edev->vlan_list))
2147 return;
2148
2149 list_for_each_entry(vlan, &edev->vlan_list, list) {
2150 if (!vlan->configured)
2151 continue;
2152
2153 vlan->configured = false;
2154
2155 /* vlan0 filter isn't consuming out of our quota */
2156 if (vlan->vid != 0) {
2157 edev->non_configured_vlans++;
2158 edev->configured_vlans--;
2159 }
2160
2161 DP_VERBOSE(edev, NETIF_MSG_IFDOWN,
1a635e48 2162 "marked vlan %d as non-configured\n", vlan->vid);
7c1bfcad
SRK		 2163 }
2164
2165 edev->accept_any_vlan = false;
2166}
2167
9438451e 2168static int qede_set_features(struct net_device *dev, netdev_features_t features)
ce2b885c
YM		 2169{
2170 struct qede_dev *edev = netdev_priv(dev);
2171 netdev_features_t changes = features ^ dev->features;
2172 bool need_reload = false;
2173
2174 /* No action needed if hardware GRO is disabled during driver load */
2175 if (changes & NETIF_F_GRO) {
2176 if (dev->features & NETIF_F_GRO)
2177 need_reload = !edev->gro_disable;
2178 else
2179 need_reload = edev->gro_disable;
2180 }
2181
2182 if (need_reload && netif_running(edev->ndev)) {
2183 dev->features = features;
2184 qede_reload(edev, NULL, NULL);
2185 return 1;
2186 }
2187
2188 return 0;
2189}
2190
f9f082a9
AD		 2191static void qede_udp_tunnel_add(struct net_device *dev,
2192 struct udp_tunnel_info *ti)
b18e170c
MC		 2193{
2194 struct qede_dev *edev = netdev_priv(dev);
f9f082a9 2195 u16 t_port = ntohs(ti->port);
b18e170c 2196
f9f082a9
AD		 2197 switch (ti->type) {
2198 case UDP_TUNNEL_TYPE_VXLAN:
2199 if (edev->vxlan_dst_port)
2200 return;
b18e170c 2201
f9f082a9 2202 edev->vxlan_dst_port = t_port;
b18e170c 2203
525ef5c0 2204 DP_VERBOSE(edev, QED_MSG_DEBUG, "Added vxlan port=%d\n",
f9f082a9 2205 t_port);
b18e170c 2206
f9f082a9
AD		 2207 set_bit(QEDE_SP_VXLAN_PORT_CONFIG, &edev->sp_flags);
2208 break;
2209 case UDP_TUNNEL_TYPE_GENEVE:
2210 if (edev->geneve_dst_port)
2211 return;
b18e170c 2212
f9f082a9 2213 edev->geneve_dst_port = t_port;
b18e170c 2214
525ef5c0 2215 DP_VERBOSE(edev, QED_MSG_DEBUG, "Added geneve port=%d\n",
f9f082a9
AD		 2216 t_port);
2217 set_bit(QEDE_SP_GENEVE_PORT_CONFIG, &edev->sp_flags);
2218 break;
2219 default:
b18e170c 2220 return;
f9f082a9 2221 }
b18e170c 2222
b18e170c
MC		 2223 schedule_delayed_work(&edev->sp_task, 0);
2224}
b18e170c 2225
f9f082a9
AD		 2226static void qede_udp_tunnel_del(struct net_device *dev,
2227 struct udp_tunnel_info *ti)
9a109dd0
MC		 2228{
2229 struct qede_dev *edev = netdev_priv(dev);
f9f082a9 2230 u16 t_port = ntohs(ti->port);
9a109dd0 2231
f9f082a9
AD		 2232 switch (ti->type) {
2233 case UDP_TUNNEL_TYPE_VXLAN:
2234 if (t_port != edev->vxlan_dst_port)
2235 return;
9a109dd0 2236
f9f082a9 2237 edev->vxlan_dst_port = 0;
9a109dd0 2238
525ef5c0 2239 DP_VERBOSE(edev, QED_MSG_DEBUG, "Deleted vxlan port=%d\n",
f9f082a9 2240 t_port);
9a109dd0 2241
f9f082a9
AD		 2242 set_bit(QEDE_SP_VXLAN_PORT_CONFIG, &edev->sp_flags);
2243 break;
2244 case UDP_TUNNEL_TYPE_GENEVE:
2245 if (t_port != edev->geneve_dst_port)
2246 return;
9a109dd0 2247
f9f082a9 2248 edev->geneve_dst_port = 0;
9a109dd0 2249
525ef5c0 2250 DP_VERBOSE(edev, QED_MSG_DEBUG, "Deleted geneve port=%d\n",
f9f082a9
AD		 2251 t_port);
2252 set_bit(QEDE_SP_GENEVE_PORT_CONFIG, &edev->sp_flags);
2253 break;
2254 default:
2255 return;
2256 }
9a109dd0 2257
9a109dd0
MC		 2258 schedule_delayed_work(&edev->sp_task, 0);
2259}
9a109dd0 2260
25695853
MC		 2261/* 8B udp header + 8B base tunnel header + 32B option length */
2262#define QEDE_MAX_TUN_HDR_LEN 48
2263
2264static netdev_features_t qede_features_check(struct sk_buff *skb,
2265 struct net_device *dev,
2266 netdev_features_t features)
2267{
2268 if (skb->encapsulation) {
2269 u8 l4_proto = 0;
2270
2271 switch (vlan_get_protocol(skb)) {
2272 case htons(ETH_P_IP):
2273 l4_proto = ip_hdr(skb)->protocol;
2274 break;
2275 case htons(ETH_P_IPV6):
2276 l4_proto = ipv6_hdr(skb)->nexthdr;
2277 break;
2278 default:
2279 return features;
2280 }
2281
2282 /* Disable offloads for geneve tunnels, as HW can't parse
2283 * the geneve header which has option length greater than 32B.
2284 */
2285 if ((l4_proto == IPPROTO_UDP) &&
2286 ((skb_inner_mac_header(skb) -
2287 skb_transport_header(skb)) > QEDE_MAX_TUN_HDR_LEN))
2288 return features & ~(NETIF_F_CSUM_MASK |
2289 NETIF_F_GSO_MASK);
2290 }
2291
2292 return features;
2293}
2294
2950219d
YM		 2295static const struct net_device_ops qede_netdev_ops = {
2296 .ndo_open = qede_open,
2297 .ndo_stop = qede_close,
2298 .ndo_start_xmit = qede_start_xmit,
0d8e0aa0
SK		 2299 .ndo_set_rx_mode = qede_set_rx_mode,
2300 .ndo_set_mac_address = qede_set_mac_addr,
2950219d 2301 .ndo_validate_addr = eth_validate_addr,
133fac0e 2302 .ndo_change_mtu = qede_change_mtu,
08feecd7 2303#ifdef CONFIG_QED_SRIOV
eff16960 2304 .ndo_set_vf_mac = qede_set_vf_mac,
08feecd7
YM		 2305 .ndo_set_vf_vlan = qede_set_vf_vlan,
2306#endif
7c1bfcad
SRK		 2307 .ndo_vlan_rx_add_vid = qede_vlan_rx_add_vid,
2308 .ndo_vlan_rx_kill_vid = qede_vlan_rx_kill_vid,
ce2b885c 2309 .ndo_set_features = qede_set_features,
133fac0e 2310 .ndo_get_stats64 = qede_get_stats64,
733def6a
YM		 2311#ifdef CONFIG_QED_SRIOV
2312 .ndo_set_vf_link_state = qede_set_vf_link_state,
6ddc7608 2313 .ndo_set_vf_spoofchk = qede_set_vf_spoofchk,
73390ac9 2314 .ndo_get_vf_config = qede_get_vf_config,
733def6a
YM		 2315 .ndo_set_vf_rate = qede_set_vf_rate,
2316#endif
f9f082a9
AD		 2317 .ndo_udp_tunnel_add = qede_udp_tunnel_add,
2318 .ndo_udp_tunnel_del = qede_udp_tunnel_del,
25695853 2319 .ndo_features_check = qede_features_check,
2950219d
YM		 2320};
2321
e712d52b
YM		 2322/* -------------------------------------------------------------------------
2323 * START OF PROBE / REMOVE
2324 * -------------------------------------------------------------------------
2325 */
2326
2327static struct qede_dev *qede_alloc_etherdev(struct qed_dev *cdev,
2328 struct pci_dev *pdev,
2329 struct qed_dev_eth_info *info,
1a635e48 2330 u32 dp_module, u8 dp_level)
e712d52b
YM		 2331{
2332 struct net_device *ndev;
2333 struct qede_dev *edev;
2334
2335 ndev = alloc_etherdev_mqs(sizeof(*edev),
1a635e48 2336 info->num_queues, info->num_queues);
e712d52b
YM		 2337 if (!ndev) {
2338 pr_err("etherdev allocation failed\n");
2339 return NULL;
2340 }
2341
2342 edev = netdev_priv(ndev);
2343 edev->ndev = ndev;
2344 edev->cdev = cdev;
2345 edev->pdev = pdev;
2346 edev->dp_module = dp_module;
2347 edev->dp_level = dp_level;
2348 edev->ops = qed_ops;
2950219d
YM		 2349 edev->q_num_rx_buffers = NUM_RX_BDS_DEF;
2350 edev->q_num_tx_buffers = NUM_TX_BDS_DEF;
e712d52b 2351
525ef5c0
YM		 2352 DP_INFO(edev, "Allocated netdev with %d tx queues and %d rx queues\n",
2353 info->num_queues, info->num_queues);
2354
e712d52b
YM		 2355 SET_NETDEV_DEV(ndev, &pdev->dev);
2356
133fac0e 2357 memset(&edev->stats, 0, sizeof(edev->stats));
e712d52b
YM		 2358 memcpy(&edev->dev_info, info, sizeof(*info));
2359
7c1bfcad
SRK		 2360 INIT_LIST_HEAD(&edev->vlan_list);
2361
e712d52b
YM		 2362 return edev;
2363}
2364
2365static void qede_init_ndev(struct qede_dev *edev)
2366{
2367 struct net_device *ndev = edev->ndev;
2368 struct pci_dev *pdev = edev->pdev;
2369 u32 hw_features;
2370
2371 pci_set_drvdata(pdev, ndev);
2372
2373 ndev->mem_start = edev->dev_info.common.pci_mem_start;
2374 ndev->base_addr = ndev->mem_start;
2375 ndev->mem_end = edev->dev_info.common.pci_mem_end;
2376 ndev->irq = edev->dev_info.common.pci_irq;
2377
2378 ndev->watchdog_timeo = TX_TIMEOUT;
2379
2950219d
YM		 2380 ndev->netdev_ops = &qede_netdev_ops;
2381
133fac0e
SK		 2382 qede_set_ethtool_ops(ndev);
2383
0183eb1c 2384 ndev->priv_flags |= IFF_UNICAST_FLT;
7b7e70f9 2385
e712d52b
YM		 2386 /* user-changeble features */
2387 hw_features = NETIF_F_GRO | NETIF_F_SG |
2388 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2389 NETIF_F_TSO | NETIF_F_TSO6;
2390
14db81de
MC		 2391 /* Encap features*/
2392 hw_features |= NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL |
a150241c
MC		 2393 NETIF_F_TSO_ECN | NETIF_F_GSO_UDP_TUNNEL_CSUM |
2394 NETIF_F_GSO_GRE_CSUM;
14db81de
MC		 2395 ndev->hw_enc_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2396 NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO_ECN |
2397 NETIF_F_TSO6 | NETIF_F_GSO_GRE |
a150241c
MC		 2398 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_RXCSUM |
2399 NETIF_F_GSO_UDP_TUNNEL_CSUM |
2400 NETIF_F_GSO_GRE_CSUM;
14db81de 2401
e712d52b
YM		 2402 ndev->vlan_features = hw_features | NETIF_F_RXHASH | NETIF_F_RXCSUM |
2403 NETIF_F_HIGHDMA;
2404 ndev->features = hw_features | NETIF_F_RXHASH | NETIF_F_RXCSUM |
2405 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HIGHDMA |
7c1bfcad 2406 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_VLAN_CTAG_TX;
e712d52b
YM		 2407
2408 ndev->hw_features = hw_features;
2409
caff2a87
JW		 2410 /* MTU range: 46 - 9600 */
2411 ndev->min_mtu = ETH_ZLEN - ETH_HLEN;
2412 ndev->max_mtu = QEDE_MAX_JUMBO_PACKET_SIZE;
2413
e712d52b
YM		 2414 /* Set network device HW mac */
2415 ether_addr_copy(edev->ndev->dev_addr, edev->dev_info.common.hw_mac);
0fefbfba
SK		 2416
2417 ndev->mtu = edev->dev_info.common.mtu;
e712d52b
YM		 2418}
2419
2420/* This function converts from 32b param to two params of level and module
2421 * Input 32b decoding:
2422 * b31 - enable all NOTICE prints. NOTICE prints are for deviation from the
2423 * 'happy' flow, e.g. memory allocation failed.
2424 * b30 - enable all INFO prints. INFO prints are for major steps in the flow
2425 * and provide important parameters.
2426 * b29-b0 - per-module bitmap, where each bit enables VERBOSE prints of that
2427 * module. VERBOSE prints are for tracking the specific flow in low level.
2428 *
2429 * Notice that the level should be that of the lowest required logs.
2430 */
133fac0e 2431void qede_config_debug(uint debug, u32 *p_dp_module, u8 *p_dp_level)
e712d52b
YM		 2432{
2433 *p_dp_level = QED_LEVEL_NOTICE;
2434 *p_dp_module = 0;
2435
2436 if (debug & QED_LOG_VERBOSE_MASK) {
2437 *p_dp_level = QED_LEVEL_VERBOSE;
2438 *p_dp_module = (debug & 0x3FFFFFFF);
2439 } else if (debug & QED_LOG_INFO_MASK) {
2440 *p_dp_level = QED_LEVEL_INFO;
2441 } else if (debug & QED_LOG_NOTICE_MASK) {
2442 *p_dp_level = QED_LEVEL_NOTICE;
2443 }
2444}
2445
2950219d
YM		 2446static void qede_free_fp_array(struct qede_dev *edev)
2447{
2448 if (edev->fp_array) {
2449 struct qede_fastpath *fp;
2450 int i;
2451
9a4d7e86 2452 for_each_queue(i) {
2950219d
YM		 2453 fp = &edev->fp_array[i];
2454
2455 kfree(fp->sb_info);
2456 kfree(fp->rxq);
80439a17 2457 kfree(fp->txq);
2950219d
YM		 2458 }
2459 kfree(edev->fp_array);
2460 }
9a4d7e86
SRK		 2461
2462 edev->num_queues = 0;
2463 edev->fp_num_tx = 0;
2464 edev->fp_num_rx = 0;
2950219d
YM		 2465}
2466
2467static int qede_alloc_fp_array(struct qede_dev *edev)
2468{
9a4d7e86 2469 u8 fp_combined, fp_rx = edev->fp_num_rx;
2950219d
YM		 2470 struct qede_fastpath *fp;
2471 int i;
2472
9a4d7e86 2473 edev->fp_array = kcalloc(QEDE_QUEUE_CNT(edev),
2950219d
YM		 2474 sizeof(*edev->fp_array), GFP_KERNEL);
2475 if (!edev->fp_array) {
2476 DP_NOTICE(edev, "fp array allocation failed\n");
2477 goto err;
2478 }
2479
9a4d7e86
SRK		 2480 fp_combined = QEDE_QUEUE_CNT(edev) - fp_rx - edev->fp_num_tx;
2481
2482 /* Allocate the FP elements for Rx queues followed by combined and then
2483 * the Tx. This ordering should be maintained so that the respective
2484 * queues (Rx or Tx) will be together in the fastpath array and the
2485 * associated ids will be sequential.
2486 */
2487 for_each_queue(i) {
2950219d
YM		 2488 fp = &edev->fp_array[i];
2489
80439a17 2490 fp->sb_info = kzalloc(sizeof(*fp->sb_info), GFP_KERNEL);
2950219d
YM		 2491 if (!fp->sb_info) {
2492 DP_NOTICE(edev, "sb info struct allocation failed\n");
2493 goto err;
2494 }
2495
9a4d7e86
SRK		 2496 if (fp_rx) {
2497 fp->type = QEDE_FASTPATH_RX;
2498 fp_rx--;
2499 } else if (fp_combined) {
2500 fp->type = QEDE_FASTPATH_COMBINED;
2501 fp_combined--;
2502 } else {
2503 fp->type = QEDE_FASTPATH_TX;
2950219d
YM		 2504 }
2505
9a4d7e86 2506 if (fp->type & QEDE_FASTPATH_TX) {
80439a17
MY		 2507 fp->txq = kzalloc(sizeof(*fp->txq), GFP_KERNEL);
2508 if (!fp->txq)
9a4d7e86 2509 goto err;
9a4d7e86
SRK		 2510 }
2511
2512 if (fp->type & QEDE_FASTPATH_RX) {
80439a17
MY		 2513 fp->rxq = kzalloc(sizeof(*fp->rxq), GFP_KERNEL);
2514 if (!fp->rxq)
9a4d7e86 2515 goto err;
2950219d
YM		 2516 }
2517 }
2518
2519 return 0;
2520err:
2521 qede_free_fp_array(edev);
2522 return -ENOMEM;
2523}
2524
0d8e0aa0
SK		 2525static void qede_sp_task(struct work_struct *work)
2526{
2527 struct qede_dev *edev = container_of(work, struct qede_dev,
2528 sp_task.work);
b18e170c
MC		 2529 struct qed_dev *cdev = edev->cdev;
2530
0d8e0aa0
SK		 2531 mutex_lock(&edev->qede_lock);
2532
2533 if (edev->state == QEDE_STATE_OPEN) {
2534 if (test_and_clear_bit(QEDE_SP_RX_MODE, &edev->sp_flags))
2535 qede_config_rx_mode(edev->ndev);
2536 }
2537
b18e170c
MC		 2538 if (test_and_clear_bit(QEDE_SP_VXLAN_PORT_CONFIG, &edev->sp_flags)) {
2539 struct qed_tunn_params tunn_params;
2540
2541 memset(&tunn_params, 0, sizeof(tunn_params));
2542 tunn_params.update_vxlan_port = 1;
2543 tunn_params.vxlan_port = edev->vxlan_dst_port;
2544 qed_ops->tunn_config(cdev, &tunn_params);
2545 }
2546
9a109dd0
MC		 2547 if (test_and_clear_bit(QEDE_SP_GENEVE_PORT_CONFIG, &edev->sp_flags)) {
2548 struct qed_tunn_params tunn_params;
2549
2550 memset(&tunn_params, 0, sizeof(tunn_params));
2551 tunn_params.update_geneve_port = 1;
2552 tunn_params.geneve_port = edev->geneve_dst_port;
2553 qed_ops->tunn_config(cdev, &tunn_params);
2554 }
2555
0d8e0aa0
SK		 2556 mutex_unlock(&edev->qede_lock);
2557}
2558
e712d52b
YM		 2559static void qede_update_pf_params(struct qed_dev *cdev)
2560{
2561 struct qed_pf_params pf_params;
2562
8e0ddc04 2563 /* 64 rx + 64 tx */
e712d52b 2564 memset(&pf_params, 0, sizeof(struct qed_pf_params));
8e0ddc04 2565 pf_params.eth_pf_params.num_cons = 128;
e712d52b
YM		 2566 qed_ops->common->update_pf_params(cdev, &pf_params);
2567}
2568
2569enum qede_probe_mode {
2570 QEDE_PROBE_NORMAL,
2571};
2572
2573static int __qede_probe(struct pci_dev *pdev, u32 dp_module, u8 dp_level,
1408cc1f 2574 bool is_vf, enum qede_probe_mode mode)
e712d52b 2575{
1408cc1f 2576 struct qed_probe_params probe_params;
1a635e48 2577 struct qed_slowpath_params sp_params;
e712d52b
YM		 2578 struct qed_dev_eth_info dev_info;
2579 struct qede_dev *edev;
2580 struct qed_dev *cdev;
2581 int rc;
2582
2583 if (unlikely(dp_level & QED_LEVEL_INFO))
2584 pr_notice("Starting qede probe\n");
2585
1408cc1f
YM		 2586 memset(&probe_params, 0, sizeof(probe_params));
2587 probe_params.protocol = QED_PROTOCOL_ETH;
2588 probe_params.dp_module = dp_module;
2589 probe_params.dp_level = dp_level;
2590 probe_params.is_vf = is_vf;
2591 cdev = qed_ops->common->probe(pdev, &probe_params);
e712d52b
YM		 2592 if (!cdev) {
2593 rc = -ENODEV;
2594 goto err0;
2595 }
2596
2597 qede_update_pf_params(cdev);
2598
2599 /* Start the Slowpath-process */
1a635e48
YM		 2600 memset(&sp_params, 0, sizeof(sp_params));
2601 sp_params.int_mode = QED_INT_MODE_MSIX;
2602 sp_params.drv_major = QEDE_MAJOR_VERSION;
2603 sp_params.drv_minor = QEDE_MINOR_VERSION;
2604 sp_params.drv_rev = QEDE_REVISION_VERSION;
2605 sp_params.drv_eng = QEDE_ENGINEERING_VERSION;
2606 strlcpy(sp_params.name, "qede LAN", QED_DRV_VER_STR_SIZE);
2607 rc = qed_ops->common->slowpath_start(cdev, &sp_params);
e712d52b
YM		 2608 if (rc) {
2609 pr_notice("Cannot start slowpath\n");
2610 goto err1;
2611 }
2612
2613 /* Learn information crucial for qede to progress */
2614 rc = qed_ops->fill_dev_info(cdev, &dev_info);
2615 if (rc)
2616 goto err2;
2617
2618 edev = qede_alloc_etherdev(cdev, pdev, &dev_info, dp_module,
2619 dp_level);
2620 if (!edev) {
2621 rc = -ENOMEM;
2622 goto err2;
2623 }
2624
fefb0202
YM		 2625 if (is_vf)
2626 edev->flags |= QEDE_FLAG_IS_VF;
2627
e712d52b
YM		 2628 qede_init_ndev(edev);
2629
cee9fbd8
RA		 2630 rc = qede_roce_dev_add(edev);
2631 if (rc)
2632 goto err3;
2633
2950219d
YM		 2634 rc = register_netdev(edev->ndev);
2635 if (rc) {
2636 DP_NOTICE(edev, "Cannot register net-device\n");
cee9fbd8 2637 goto err4;
2950219d
YM		 2638 }
2639
e712d52b
YM		 2640 edev->ops->common->set_id(cdev, edev->ndev->name, DRV_MODULE_VERSION);
2641
a2ec6172
SK		 2642 edev->ops->register_ops(cdev, &qede_ll_ops, edev);
2643
489e45ae 2644#ifdef CONFIG_DCB
5fe118c9
SRK		 2645 if (!IS_VF(edev))
2646 qede_set_dcbnl_ops(edev->ndev);
489e45ae
SRK		 2647#endif
2648
0d8e0aa0
SK		 2649 INIT_DELAYED_WORK(&edev->sp_task, qede_sp_task);
2650 mutex_init(&edev->qede_lock);
3d789994 2651 edev->rx_copybreak = QEDE_RX_HDR_SIZE;
0d8e0aa0 2652
e712d52b
YM		 2653 DP_INFO(edev, "Ending successfully qede probe\n");
2654
2655 return 0;
2656
cee9fbd8
RA		 2657err4:
2658 qede_roce_dev_remove(edev);
2950219d
YM		 2659err3:
2660 free_netdev(edev->ndev);
e712d52b
YM		 2661err2:
2662 qed_ops->common->slowpath_stop(cdev);
2663err1:
2664 qed_ops->common->remove(cdev);
2665err0:
2666 return rc;
2667}
2668
2669static int qede_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2670{
fefb0202 2671 bool is_vf = false;
e712d52b
YM		 2672 u32 dp_module = 0;
2673 u8 dp_level = 0;
2674
fefb0202
YM		 2675 switch ((enum qede_pci_private)id->driver_data) {
2676 case QEDE_PRIVATE_VF:
2677 if (debug & QED_LOG_VERBOSE_MASK)
2678 dev_err(&pdev->dev, "Probing a VF\n");
2679 is_vf = true;
2680 break;
2681 default:
2682 if (debug & QED_LOG_VERBOSE_MASK)
2683 dev_err(&pdev->dev, "Probing a PF\n");
2684 }
2685
e712d52b
YM		 2686 qede_config_debug(debug, &dp_module, &dp_level);
2687
fefb0202 2688 return __qede_probe(pdev, dp_module, dp_level, is_vf,
e712d52b
YM		 2689 QEDE_PROBE_NORMAL);
2690}
2691
2692enum qede_remove_mode {
2693 QEDE_REMOVE_NORMAL,
2694};
2695
2696static void __qede_remove(struct pci_dev *pdev, enum qede_remove_mode mode)
2697{
2698 struct net_device *ndev = pci_get_drvdata(pdev);
2699 struct qede_dev *edev = netdev_priv(ndev);
2700 struct qed_dev *cdev = edev->cdev;
2701
2702 DP_INFO(edev, "Starting qede_remove\n");
2703
0d8e0aa0 2704 cancel_delayed_work_sync(&edev->sp_task);
cee9fbd8 2705
2950219d
YM		 2706 unregister_netdev(ndev);
2707
cee9fbd8
RA		 2708 qede_roce_dev_remove(edev);
2709
e712d52b
YM		 2710 edev->ops->common->set_power_state(cdev, PCI_D0);
2711
2712 pci_set_drvdata(pdev, NULL);
2713
2714 free_netdev(ndev);
2715
2716 /* Use global ops since we've freed edev */
2717 qed_ops->common->slowpath_stop(cdev);
14d39648
MY		 2718 if (system_state == SYSTEM_POWER_OFF)
2719 return;
e712d52b
YM		 2720 qed_ops->common->remove(cdev);
2721
525ef5c0 2722 dev_info(&pdev->dev, "Ending qede_remove successfully\n");
e712d52b
YM		 2723}
2724
2725static void qede_remove(struct pci_dev *pdev)
2726{
2727 __qede_remove(pdev, QEDE_REMOVE_NORMAL);
2728}
2950219d 2729
14d39648
MY		 2730static void qede_shutdown(struct pci_dev *pdev)
2731{
2732 __qede_remove(pdev, QEDE_REMOVE_NORMAL);
2733}
2734
2950219d
YM		 2735/* -------------------------------------------------------------------------
2736 * START OF LOAD / UNLOAD
2737 * -------------------------------------------------------------------------
2738 */
2739
2740static int qede_set_num_queues(struct qede_dev *edev)
2741{
2742 int rc;
2743 u16 rss_num;
2744
2745 /* Setup queues according to possible resources*/
9a4d7e86
SRK		 2746 if (edev->req_queues)
2747 rss_num = edev->req_queues;
8edf049d
SK		 2748 else
2749 rss_num = netif_get_num_default_rss_queues() *
2750 edev->dev_info.common.num_hwfns;
2950219d
YM		 2751
2752 rss_num = min_t(u16, QEDE_MAX_RSS_CNT(edev), rss_num);
2753
2754 rc = edev->ops->common->set_fp_int(edev->cdev, rss_num);
2755 if (rc > 0) {
2756 /* Managed to request interrupts for our queues */
9a4d7e86 2757 edev->num_queues = rc;
2950219d 2758 DP_INFO(edev, "Managed %d [of %d] RSS queues\n",
9a4d7e86 2759 QEDE_QUEUE_CNT(edev), rss_num);
2950219d
YM		 2760 rc = 0;
2761 }
9a4d7e86
SRK		 2762
2763 edev->fp_num_tx = edev->req_num_tx;
2764 edev->fp_num_rx = edev->req_num_rx;
2765
2950219d
YM		 2766 return rc;
2767}
2768
2769static void qede_free_mem_sb(struct qede_dev *edev,
2770 struct qed_sb_info *sb_info)
2771{
2772 if (sb_info->sb_virt)
2773 dma_free_coherent(&edev->pdev->dev, sizeof(*sb_info->sb_virt),
2774 (void *)sb_info->sb_virt, sb_info->sb_phys);
2775}
2776
2777/* This function allocates fast-path status block memory */
2778static int qede_alloc_mem_sb(struct qede_dev *edev,
1a635e48 2779 struct qed_sb_info *sb_info, u16 sb_id)
2950219d
YM		 2780{
2781 struct status_block *sb_virt;
2782 dma_addr_t sb_phys;
2783 int rc;
2784
2785 sb_virt = dma_alloc_coherent(&edev->pdev->dev,
1a635e48 2786 sizeof(*sb_virt), &sb_phys, GFP_KERNEL);
2950219d
YM		 2787 if (!sb_virt) {
2788 DP_ERR(edev, "Status block allocation failed\n");
2789 return -ENOMEM;
2790 }
2791
2792 rc = edev->ops->common->sb_init(edev->cdev, sb_info,
2793 sb_virt, sb_phys, sb_id,
2794 QED_SB_TYPE_L2_QUEUE);
2795 if (rc) {
2796 DP_ERR(edev, "Status block initialization failed\n");
2797 dma_free_coherent(&edev->pdev->dev, sizeof(*sb_virt),
2798 sb_virt, sb_phys);
2799 return rc;
2800 }
2801
2802 return 0;
2803}
2804
2805static void qede_free_rx_buffers(struct qede_dev *edev,
2806 struct qede_rx_queue *rxq)
2807{
2808 u16 i;
2809
2810 for (i = rxq->sw_rx_cons; i != rxq->sw_rx_prod; i++) {
2811 struct sw_rx_data *rx_buf;
fc48b7a6 2812 struct page *data;
2950219d
YM		 2813
2814 rx_buf = &rxq->sw_rx_ring[i & NUM_RX_BDS_MAX];
2815 data = rx_buf->data;
2816
fc48b7a6 2817 dma_unmap_page(&edev->pdev->dev,
1a635e48 2818 rx_buf->mapping, PAGE_SIZE, DMA_FROM_DEVICE);
2950219d
YM		 2819
2820 rx_buf->data = NULL;
fc48b7a6 2821 __free_page(data);
2950219d
YM		 2822 }
2823}
2824
1a635e48
YM		 2825static void qede_free_sge_mem(struct qede_dev *edev, struct qede_rx_queue *rxq)
2826{
55482edc
MC		 2827 int i;
2828
2829 if (edev->gro_disable)
2830 return;
2831
2832 for (i = 0; i < ETH_TPA_MAX_AGGS_NUM; i++) {
2833 struct qede_agg_info *tpa_info = &rxq->tpa_info[i];
01e23015 2834 struct sw_rx_data *replace_buf = &tpa_info->buffer;
55482edc 2835
f86af2df 2836 if (replace_buf->data) {
55482edc 2837 dma_unmap_page(&edev->pdev->dev,
09ec8e7f 2838 replace_buf->mapping,
55482edc
MC		 2839 PAGE_SIZE, DMA_FROM_DEVICE);
2840 __free_page(replace_buf->data);
2841 }
2842 }
2843}
2844
1a635e48 2845static void qede_free_mem_rxq(struct qede_dev *edev, struct qede_rx_queue *rxq)
2950219d 2846{
55482edc
MC		 2847 qede_free_sge_mem(edev, rxq);
2848
2950219d
YM		 2849 /* Free rx buffers */
2850 qede_free_rx_buffers(edev, rxq);
2851
2852 /* Free the parallel SW ring */
2853 kfree(rxq->sw_rx_ring);
2854
2855 /* Free the real RQ ring used by FW */
2856 edev->ops->common->chain_free(edev->cdev, &rxq->rx_bd_ring);
2857 edev->ops->common->chain_free(edev->cdev, &rxq->rx_comp_ring);
2858}
2859
2860static int qede_alloc_rx_buffer(struct qede_dev *edev,
2861 struct qede_rx_queue *rxq)
2862{
2863 struct sw_rx_data *sw_rx_data;
2864 struct eth_rx_bd *rx_bd;
2865 dma_addr_t mapping;
fc48b7a6 2866 struct page *data;
2950219d 2867
fc48b7a6 2868 data = alloc_pages(GFP_ATOMIC, 0);
2950219d 2869 if (unlikely(!data)) {
fc48b7a6 2870 DP_NOTICE(edev, "Failed to allocate Rx data [page]\n");
2950219d
YM		 2871 return -ENOMEM;
2872 }
2873
fc48b7a6
YM		 2874 /* Map the entire page as it would be used
2875 * for multiple RX buffer segment size mapping.
2876 */
2877 mapping = dma_map_page(&edev->pdev->dev, data, 0,
2878 PAGE_SIZE, DMA_FROM_DEVICE);
2950219d 2879 if (unlikely(dma_mapping_error(&edev->pdev->dev, mapping))) {
fc48b7a6 2880 __free_page(data);
2950219d
YM		 2881 DP_NOTICE(edev, "Failed to map Rx buffer\n");
2882 return -ENOMEM;
2883 }
2884
2885 sw_rx_data = &rxq->sw_rx_ring[rxq->sw_rx_prod & NUM_RX_BDS_MAX];
fc48b7a6 2886 sw_rx_data->page_offset = 0;
2950219d 2887 sw_rx_data->data = data;
fc48b7a6 2888 sw_rx_data->mapping = mapping;
2950219d
YM		 2889
2890 /* Advance PROD and get BD pointer */
2891 rx_bd = (struct eth_rx_bd *)qed_chain_produce(&rxq->rx_bd_ring);
2892 WARN_ON(!rx_bd);
2893 rx_bd->addr.hi = cpu_to_le32(upper_32_bits(mapping));
2894 rx_bd->addr.lo = cpu_to_le32(lower_32_bits(mapping));
2895
2896 rxq->sw_rx_prod++;
2897
2898 return 0;
2899}
2900
1a635e48 2901static int qede_alloc_sge_mem(struct qede_dev *edev, struct qede_rx_queue *rxq)
55482edc
MC		 2902{
2903 dma_addr_t mapping;
2904 int i;
2905
2906 if (edev->gro_disable)
2907 return 0;
2908
2909 if (edev->ndev->mtu > PAGE_SIZE) {
2910 edev->gro_disable = 1;
2911 return 0;
2912 }
2913
2914 for (i = 0; i < ETH_TPA_MAX_AGGS_NUM; i++) {
2915 struct qede_agg_info *tpa_info = &rxq->tpa_info[i];
01e23015 2916 struct sw_rx_data *replace_buf = &tpa_info->buffer;
55482edc
MC		 2917
2918 replace_buf->data = alloc_pages(GFP_ATOMIC, 0);
2919 if (unlikely(!replace_buf->data)) {
2920 DP_NOTICE(edev,
2921 "Failed to allocate TPA skb pool [replacement buffer]\n");
2922 goto err;
2923 }
2924
2925 mapping = dma_map_page(&edev->pdev->dev, replace_buf->data, 0,
9512925a 2926 PAGE_SIZE, DMA_FROM_DEVICE);
55482edc
MC		 2927 if (unlikely(dma_mapping_error(&edev->pdev->dev, mapping))) {
2928 DP_NOTICE(edev,
2929 "Failed to map TPA replacement buffer\n");
2930 goto err;
2931 }
2932
09ec8e7f 2933 replace_buf->mapping = mapping;
01e23015
MY		 2934 tpa_info->buffer.page_offset = 0;
2935 tpa_info->buffer_mapping = mapping;
2936 tpa_info->state = QEDE_AGG_STATE_NONE;
55482edc
MC		 2937 }
2938
2939 return 0;
2940err:
2941 qede_free_sge_mem(edev, rxq);
2942 edev->gro_disable = 1;
2943 return -ENOMEM;
2944}
2945
2950219d 2946/* This function allocates all memory needed per Rx queue */
1a635e48 2947static int qede_alloc_mem_rxq(struct qede_dev *edev, struct qede_rx_queue *rxq)
2950219d 2948{
f86af2df 2949 int i, rc, size;
2950219d
YM		 2950
2951 rxq->num_rx_buffers = edev->q_num_rx_buffers;
2952
1a635e48
YM		 2953 rxq->rx_buf_size = NET_IP_ALIGN + ETH_OVERHEAD + edev->ndev->mtu;
2954
fc48b7a6
YM		 2955 if (rxq->rx_buf_size > PAGE_SIZE)
2956 rxq->rx_buf_size = PAGE_SIZE;
2957
2958 /* Segment size to spilt a page in multiple equal parts */
2959 rxq->rx_buf_seg_size = roundup_pow_of_two(rxq->rx_buf_size);
2950219d
YM		 2960
2961 /* Allocate the parallel driver ring for Rx buffers */
fc48b7a6 2962 size = sizeof(*rxq->sw_rx_ring) * RX_RING_SIZE;
2950219d
YM		 2963 rxq->sw_rx_ring = kzalloc(size, GFP_KERNEL);
2964 if (!rxq->sw_rx_ring) {
2965 DP_ERR(edev, "Rx buffers ring allocation failed\n");
f86af2df 2966 rc = -ENOMEM;
2950219d
YM		 2967 goto err;
2968 }
2969
2970 /* Allocate FW Rx ring */
2971 rc = edev->ops->common->chain_alloc(edev->cdev,
2972 QED_CHAIN_USE_TO_CONSUME_PRODUCE,
2973 QED_CHAIN_MODE_NEXT_PTR,
a91eb52a 2974 QED_CHAIN_CNT_TYPE_U16,
fc48b7a6 2975 RX_RING_SIZE,
2950219d
YM		 2976 sizeof(struct eth_rx_bd),
2977 &rxq->rx_bd_ring);
2978
2979 if (rc)
2980 goto err;
2981
2982 /* Allocate FW completion ring */
2983 rc = edev->ops->common->chain_alloc(edev->cdev,
2984 QED_CHAIN_USE_TO_CONSUME,
2985 QED_CHAIN_MODE_PBL,
a91eb52a 2986 QED_CHAIN_CNT_TYPE_U16,
fc48b7a6 2987 RX_RING_SIZE,
2950219d
YM		 2988 sizeof(union eth_rx_cqe),
2989 &rxq->rx_comp_ring);
2990 if (rc)
2991 goto err;
2992
2993 /* Allocate buffers for the Rx ring */
2994 for (i = 0; i < rxq->num_rx_buffers; i++) {
2995 rc = qede_alloc_rx_buffer(edev, rxq);
f86af2df
MC		 2996 if (rc) {
2997 DP_ERR(edev,
2998 "Rx buffers allocation failed at index %d\n", i);
2999 goto err;
3000 }
2950219d
YM		 3001 }
3002
f86af2df 3003 rc = qede_alloc_sge_mem(edev, rxq);
2950219d 3004err:
f86af2df 3005 return rc;
2950219d
YM		 3006}
3007
1a635e48 3008static void qede_free_mem_txq(struct qede_dev *edev, struct qede_tx_queue *txq)
2950219d
YM		 3009{
3010 /* Free the parallel SW ring */
3011 kfree(txq->sw_tx_ring);
3012
3013 /* Free the real RQ ring used by FW */
3014 edev->ops->common->chain_free(edev->cdev, &txq->tx_pbl);
3015}
3016
3017/* This function allocates all memory needed per Tx queue */
1a635e48 3018static int qede_alloc_mem_txq(struct qede_dev *edev, struct qede_tx_queue *txq)
2950219d
YM		 3019{
3020 int size, rc;
3021 union eth_tx_bd_types *p_virt;
3022
3023 txq->num_tx_buffers = edev->q_num_tx_buffers;
3024
3025 /* Allocate the parallel driver ring for Tx buffers */
087892d2 3026 size = sizeof(*txq->sw_tx_ring) * TX_RING_SIZE;
2950219d
YM		 3027 txq->sw_tx_ring = kzalloc(size, GFP_KERNEL);
3028 if (!txq->sw_tx_ring) {
3029 DP_NOTICE(edev, "Tx buffers ring allocation failed\n");
3030 goto err;
3031 }
3032
3033 rc = edev->ops->common->chain_alloc(edev->cdev,
3034 QED_CHAIN_USE_TO_CONSUME_PRODUCE,
3035 QED_CHAIN_MODE_PBL,
a91eb52a 3036 QED_CHAIN_CNT_TYPE_U16,
087892d2 3037 TX_RING_SIZE,
a91eb52a 3038 sizeof(*p_virt), &txq->tx_pbl);
2950219d
YM		 3039 if (rc)
3040 goto err;
3041
3042 return 0;
3043
3044err:
3045 qede_free_mem_txq(edev, txq);
3046 return -ENOMEM;
3047}
3048
3049/* This function frees all memory of a single fp */
1a635e48 3050static void qede_free_mem_fp(struct qede_dev *edev, struct qede_fastpath *fp)
2950219d 3051{
2950219d
YM		 3052 qede_free_mem_sb(edev, fp->sb_info);
3053
9a4d7e86
SRK		 3054 if (fp->type & QEDE_FASTPATH_RX)
3055 qede_free_mem_rxq(edev, fp->rxq);
2950219d 3056
9a4d7e86 3057 if (fp->type & QEDE_FASTPATH_TX)
80439a17 3058 qede_free_mem_txq(edev, fp->txq);
2950219d
YM		 3059}
3060
3061/* This function allocates all memory needed for a single fp (i.e. an entity
9a4d7e86 3062 * which contains status block, one rx queue and/or multiple per-TC tx queues.
2950219d 3063 */
1a635e48 3064static int qede_alloc_mem_fp(struct qede_dev *edev, struct qede_fastpath *fp)
2950219d 3065{
80439a17 3066 int rc;
2950219d 3067
9a4d7e86 3068 rc = qede_alloc_mem_sb(edev, fp->sb_info, fp->id);
2950219d
YM		 3069 if (rc)
3070 goto err;
3071
9a4d7e86
SRK		 3072 if (fp->type & QEDE_FASTPATH_RX) {
3073 rc = qede_alloc_mem_rxq(edev, fp->rxq);
2950219d
YM		 3074 if (rc)
3075 goto err;
3076 }
3077
9a4d7e86 3078 if (fp->type & QEDE_FASTPATH_TX) {
80439a17
MY		 3079 rc = qede_alloc_mem_txq(edev, fp->txq);
3080 if (rc)
3081 goto err;
9a4d7e86
SRK		 3082 }
3083
2950219d 3084 return 0;
2950219d 3085err:
f86af2df 3086 return rc;
2950219d
YM		 3087}
3088
3089static void qede_free_mem_load(struct qede_dev *edev)
3090{
3091 int i;
3092
9a4d7e86 3093 for_each_queue(i) {
2950219d
YM		 3094 struct qede_fastpath *fp = &edev->fp_array[i];
3095
3096 qede_free_mem_fp(edev, fp);
3097 }
3098}
3099
3100/* This function allocates all qede memory at NIC load. */
3101static int qede_alloc_mem_load(struct qede_dev *edev)
3102{
9a4d7e86 3103 int rc = 0, queue_id;
2950219d 3104
9a4d7e86
SRK		 3105 for (queue_id = 0; queue_id < QEDE_QUEUE_CNT(edev); queue_id++) {
3106 struct qede_fastpath *fp = &edev->fp_array[queue_id];
2950219d
YM		 3107
3108 rc = qede_alloc_mem_fp(edev, fp);
f86af2df 3109 if (rc) {
2950219d 3110 DP_ERR(edev,
f86af2df 3111 "Failed to allocate memory for fastpath - rss id = %d\n",
9a4d7e86 3112 queue_id);
f86af2df
MC		 3113 qede_free_mem_load(edev);
3114 return rc;
2950219d 3115 }
2950219d
YM		 3116 }
3117
3118 return 0;
3119}
3120
3121/* This function inits fp content and resets the SB, RXQ and TXQ structures */
3122static void qede_init_fp(struct qede_dev *edev)
3123{
80439a17 3124 int queue_id, rxq_index = 0, txq_index = 0;
2950219d
YM		 3125 struct qede_fastpath *fp;
3126
9a4d7e86
SRK		 3127 for_each_queue(queue_id) {
3128 fp = &edev->fp_array[queue_id];
2950219d
YM		 3129
3130 fp->edev = edev;
9a4d7e86 3131 fp->id = queue_id;
2950219d 3132
2950219d 3133
9a4d7e86 3134 if (fp->type & QEDE_FASTPATH_RX) {
9a4d7e86
SRK		 3135 fp->rxq->rxq_id = rxq_index++;
3136 }
2950219d 3137
9a4d7e86 3138 if (fp->type & QEDE_FASTPATH_TX) {
80439a17
MY		 3139 fp->txq->index = txq_index++;
3140 if (edev->dev_info.is_legacy)
3141 fp->txq->is_legacy = 1;
2950219d
YM		 3142 }
3143
3144 snprintf(fp->name, sizeof(fp->name), "%s-fp-%d",
9a4d7e86 3145 edev->ndev->name, queue_id);
2950219d 3146 }
55482edc
MC		 3147
3148 edev->gro_disable = !(edev->ndev->features & NETIF_F_GRO);
2950219d
YM		 3149}
3150
3151static int qede_set_real_num_queues(struct qede_dev *edev)
3152{
3153 int rc = 0;
3154
9a4d7e86 3155 rc = netif_set_real_num_tx_queues(edev->ndev, QEDE_TSS_COUNT(edev));
2950219d
YM		 3156 if (rc) {
3157 DP_NOTICE(edev, "Failed to set real number of Tx queues\n");
3158 return rc;
3159 }
9a4d7e86
SRK		 3160
3161 rc = netif_set_real_num_rx_queues(edev->ndev, QEDE_RSS_COUNT(edev));
2950219d
YM		 3162 if (rc) {
3163 DP_NOTICE(edev, "Failed to set real number of Rx queues\n");
3164 return rc;
3165 }
3166
3167 return 0;
3168}
3169
3170static void qede_napi_disable_remove(struct qede_dev *edev)
3171{
3172 int i;
3173
9a4d7e86 3174 for_each_queue(i) {
2950219d
YM		 3175 napi_disable(&edev->fp_array[i].napi);
3176
3177 netif_napi_del(&edev->fp_array[i].napi);
3178 }
3179}
3180
3181static void qede_napi_add_enable(struct qede_dev *edev)
3182{
3183 int i;
3184
3185 /* Add NAPI objects */
9a4d7e86 3186 for_each_queue(i) {
2950219d
YM		 3187 netif_napi_add(edev->ndev, &edev->fp_array[i].napi,
3188 qede_poll, NAPI_POLL_WEIGHT);
3189 napi_enable(&edev->fp_array[i].napi);
3190 }
3191}
3192
3193static void qede_sync_free_irqs(struct qede_dev *edev)
3194{
3195 int i;
3196
3197 for (i = 0; i < edev->int_info.used_cnt; i++) {
3198 if (edev->int_info.msix_cnt) {
3199 synchronize_irq(edev->int_info.msix[i].vector);
3200 free_irq(edev->int_info.msix[i].vector,
3201 &edev->fp_array[i]);
3202 } else {
3203 edev->ops->common->simd_handler_clean(edev->cdev, i);
3204 }
3205 }
3206
3207 edev->int_info.used_cnt = 0;
3208}
3209
3210static int qede_req_msix_irqs(struct qede_dev *edev)
3211{
3212 int i, rc;
3213
3214 /* Sanitize number of interrupts == number of prepared RSS queues */
9a4d7e86 3215 if (QEDE_QUEUE_CNT(edev) > edev->int_info.msix_cnt) {
2950219d
YM		 3216 DP_ERR(edev,
3217 "Interrupt mismatch: %d RSS queues > %d MSI-x vectors\n",
9a4d7e86 3218 QEDE_QUEUE_CNT(edev), edev->int_info.msix_cnt);
2950219d
YM		 3219 return -EINVAL;
3220 }
3221
9a4d7e86 3222 for (i = 0; i < QEDE_QUEUE_CNT(edev); i++) {
2950219d
YM		 3223 rc = request_irq(edev->int_info.msix[i].vector,
3224 qede_msix_fp_int, 0, edev->fp_array[i].name,
3225 &edev->fp_array[i]);
3226 if (rc) {
3227 DP_ERR(edev, "Request fp %d irq failed\n", i);
3228 qede_sync_free_irqs(edev);
3229 return rc;
3230 }
3231 DP_VERBOSE(edev, NETIF_MSG_INTR,
3232 "Requested fp irq for %s [entry %d]. Cookie is at %p\n",
3233 edev->fp_array[i].name, i,
3234 &edev->fp_array[i]);
3235 edev->int_info.used_cnt++;
3236 }
3237
3238 return 0;
3239}
3240
3241static void qede_simd_fp_handler(void *cookie)
3242{
3243 struct qede_fastpath *fp = (struct qede_fastpath *)cookie;
3244
3245 napi_schedule_irqoff(&fp->napi);
3246}
3247
3248static int qede_setup_irqs(struct qede_dev *edev)
3249{
3250 int i, rc = 0;
3251
3252 /* Learn Interrupt configuration */
3253 rc = edev->ops->common->get_fp_int(edev->cdev, &edev->int_info);
3254 if (rc)
3255 return rc;
3256
3257 if (edev->int_info.msix_cnt) {
3258 rc = qede_req_msix_irqs(edev);
3259 if (rc)
3260 return rc;
3261 edev->ndev->irq = edev->int_info.msix[0].vector;
3262 } else {
3263 const struct qed_common_ops *ops;
3264
3265 /* qed should learn receive the RSS ids and callbacks */
3266 ops = edev->ops->common;
9a4d7e86 3267 for (i = 0; i < QEDE_QUEUE_CNT(edev); i++)
2950219d
YM		 3268 ops->simd_handler_config(edev->cdev,
3269 &edev->fp_array[i], i,
3270 qede_simd_fp_handler);
9a4d7e86 3271 edev->int_info.used_cnt = QEDE_QUEUE_CNT(edev);
2950219d
YM		 3272 }
3273 return 0;
3274}
3275
3276static int qede_drain_txq(struct qede_dev *edev,
1a635e48 3277 struct qede_tx_queue *txq, bool allow_drain)
2950219d
YM		 3278{
3279 int rc, cnt = 1000;
3280
3281 while (txq->sw_tx_cons != txq->sw_tx_prod) {
3282 if (!cnt) {
3283 if (allow_drain) {
3284 DP_NOTICE(edev,
3285 "Tx queue[%d] is stuck, requesting MCP to drain\n",
3286 txq->index);
3287 rc = edev->ops->common->drain(edev->cdev);
3288 if (rc)
3289 return rc;
3290 return qede_drain_txq(edev, txq, false);
3291 }
3292 DP_NOTICE(edev,
3293 "Timeout waiting for tx queue[%d]: PROD=%d, CONS=%d\n",
3294 txq->index, txq->sw_tx_prod,
3295 txq->sw_tx_cons);
3296 return -ENODEV;
3297 }
3298 cnt--;
3299 usleep_range(1000, 2000);
3300 barrier();
3301 }
3302
3303 /* FW finished processing, wait for HW to transmit all tx packets */
3304 usleep_range(1000, 2000);
3305
3306 return 0;
3307}
3308
3309static int qede_stop_queues(struct qede_dev *edev)
3310{
3311 struct qed_update_vport_params vport_update_params;
3312 struct qed_dev *cdev = edev->cdev;
80439a17
MY		 3313 struct qede_fastpath *fp;
3314 int rc, i;
2950219d
YM		 3315
3316 /* Disable the vport */
3317 memset(&vport_update_params, 0, sizeof(vport_update_params));
3318 vport_update_params.vport_id = 0;
3319 vport_update_params.update_vport_active_flg = 1;
3320 vport_update_params.vport_active_flg = 0;
3321 vport_update_params.update_rss_flg = 0;
3322
3323 rc = edev->ops->vport_update(cdev, &vport_update_params);
3324 if (rc) {
3325 DP_ERR(edev, "Failed to update vport\n");
3326 return rc;
3327 }
3328
3329 /* Flush Tx queues. If needed, request drain from MCP */
9a4d7e86 3330 for_each_queue(i) {
80439a17 3331 fp = &edev->fp_array[i];
2950219d 3332
9a4d7e86 3333 if (fp->type & QEDE_FASTPATH_TX) {
80439a17
MY		 3334 rc = qede_drain_txq(edev, fp->txq, true);
3335 if (rc)
3336 return rc;
2950219d
YM		 3337 }
3338 }
3339
9a4d7e86
SRK		 3340 /* Stop all Queues in reverse order */
3341 for (i = QEDE_QUEUE_CNT(edev) - 1; i >= 0; i--) {
2950219d
YM		 3342 struct qed_stop_rxq_params rx_params;
3343
80439a17
MY		 3344 fp = &edev->fp_array[i];
3345
9a4d7e86 3346 /* Stop the Tx Queue(s) */
80439a17
MY		 3347 if (fp->type & QEDE_FASTPATH_TX) {
3348 struct qed_stop_txq_params tx_params;
3349
3350 tx_params.rss_id = i;
3351 tx_params.tx_queue_id = fp->txq->index;
9a4d7e86 3352 rc = edev->ops->q_tx_stop(cdev, &tx_params);
80439a17 3353 if (rc)
9a4d7e86 3354 return rc;
2950219d
YM		 3355 }
3356
9a4d7e86 3357 /* Stop the Rx Queue */
80439a17 3358 if (fp->type & QEDE_FASTPATH_RX) {
9a4d7e86
SRK		 3359 memset(&rx_params, 0, sizeof(rx_params));
3360 rx_params.rss_id = i;
80439a17 3361 rx_params.rx_queue_id = fp->rxq->rxq_id;
2950219d 3362
9a4d7e86
SRK		 3363 rc = edev->ops->q_rx_stop(cdev, &rx_params);
3364 if (rc) {
3365 DP_ERR(edev, "Failed to stop RXQ #%d\n", i);
3366 return rc;
3367 }
2950219d
YM		 3368 }
3369 }
3370
3371 /* Stop the vport */
3372 rc = edev->ops->vport_stop(cdev, 0);
3373 if (rc)
3374 DP_ERR(edev, "Failed to stop VPORT\n");
3375
3376 return rc;
3377}
3378
a0d26d5a 3379static int qede_start_queues(struct qede_dev *edev, bool clear_stats)
2950219d 3380{
088c8618 3381 int vlan_removal_en = 1;
2950219d 3382 struct qed_dev *cdev = edev->cdev;
2950219d
YM		 3383 struct qed_update_vport_params vport_update_params;
3384 struct qed_queue_start_common_params q_params;
fefb0202 3385 struct qed_dev_info *qed_info = &edev->dev_info.common;
088c8618 3386 struct qed_start_vport_params start = {0};
961acdea 3387 bool reset_rss_indir = false;
80439a17 3388 int rc, i;
2950219d 3389
9a4d7e86 3390 if (!edev->num_queues) {
2950219d
YM		 3391 DP_ERR(edev,
3392 "Cannot update V-VPORT as active as there are no Rx queues\n");
3393 return -EINVAL;
3394 }
3395
55482edc 3396 start.gro_enable = !edev->gro_disable;
088c8618
MC		 3397 start.mtu = edev->ndev->mtu;
3398 start.vport_id = 0;
3399 start.drop_ttl0 = true;
3400 start.remove_inner_vlan = vlan_removal_en;
7f7a144f 3401 start.clear_stats = clear_stats;
088c8618
MC		 3402
3403 rc = edev->ops->vport_start(cdev, &start);
2950219d
YM		 3404
3405 if (rc) {
3406 DP_ERR(edev, "Start V-PORT failed %d\n", rc);
3407 return rc;
3408 }
3409
3410 DP_VERBOSE(edev, NETIF_MSG_IFUP,
3411 "Start vport ramrod passed, vport_id = %d, MTU = %d, vlan_removal_en = %d\n",
088c8618 3412 start.vport_id, edev->ndev->mtu + 0xe, vlan_removal_en);
2950219d 3413
9a4d7e86 3414 for_each_queue(i) {
2950219d 3415 struct qede_fastpath *fp = &edev->fp_array[i];
9a4d7e86
SRK		 3416 dma_addr_t p_phys_table;
3417 u32 page_cnt;
2950219d 3418
9a4d7e86
SRK		 3419 if (fp->type & QEDE_FASTPATH_RX) {
3420 struct qede_rx_queue *rxq = fp->rxq;
3421 __le16 *val;
2950219d 3422
9a4d7e86
SRK		 3423 memset(&q_params, 0, sizeof(q_params));
3424 q_params.rss_id = i;
3425 q_params.queue_id = rxq->rxq_id;
3426 q_params.vport_id = 0;
3427 q_params.sb = fp->sb_info->igu_sb_id;
3428 q_params.sb_idx = RX_PI;
3429
3430 p_phys_table =
3431 qed_chain_get_pbl_phys(&rxq->rx_comp_ring);
3432 page_cnt = qed_chain_get_page_cnt(&rxq->rx_comp_ring);
3433
3434 rc = edev->ops->q_rx_start(cdev, &q_params,
3435 rxq->rx_buf_size,
3436 rxq->rx_bd_ring.p_phys_addr,
3437 p_phys_table,
3438 page_cnt,
3439 &rxq->hw_rxq_prod_addr);
3440 if (rc) {
3441 DP_ERR(edev, "Start RXQ #%d failed %d\n", i,
3442 rc);
3443 return rc;
3444 }
3445
3446 val = &fp->sb_info->sb_virt->pi_array[RX_PI];
3447 rxq->hw_cons_ptr = val;
3448
3449 qede_update_rx_prod(edev, rxq);
3450 }
3451
80439a17
MY		 3452 if (fp->type & QEDE_FASTPATH_TX) {
3453 struct qede_tx_queue *txq = fp->txq;
9a4d7e86
SRK		 3454
3455 p_phys_table = qed_chain_get_pbl_phys(&txq->tx_pbl);
3456 page_cnt = qed_chain_get_page_cnt(&txq->tx_pbl);
2950219d
YM		 3457
3458 memset(&q_params, 0, sizeof(q_params));
3459 q_params.rss_id = i;
9a4d7e86 3460 q_params.queue_id = txq->index;
2950219d
YM		 3461 q_params.vport_id = 0;
3462 q_params.sb = fp->sb_info->igu_sb_id;
80439a17 3463 q_params.sb_idx = TX_PI(0);
2950219d
YM		 3464
3465 rc = edev->ops->q_tx_start(cdev, &q_params,
9a4d7e86 3466 p_phys_table, page_cnt,
2950219d
YM		 3467 &txq->doorbell_addr);
3468 if (rc) {
3469 DP_ERR(edev, "Start TXQ #%d failed %d\n",
9a4d7e86 3470 txq->index, rc);
2950219d
YM		 3471 return rc;
3472 }
3473
3474 txq->hw_cons_ptr =
80439a17 3475 &fp->sb_info->sb_virt->pi_array[TX_PI(0)];
2950219d
YM		 3476 SET_FIELD(txq->tx_db.data.params,
3477 ETH_DB_DATA_DEST, DB_DEST_XCM);
3478 SET_FIELD(txq->tx_db.data.params, ETH_DB_DATA_AGG_CMD,
3479 DB_AGG_CMD_SET);
3480 SET_FIELD(txq->tx_db.data.params,
3481 ETH_DB_DATA_AGG_VAL_SEL,
3482 DQ_XCM_ETH_TX_BD_PROD_CMD);
3483
3484 txq->tx_db.data.agg_flags = DQ_XCM_ETH_DQ_CF_CMD;
3485 }
3486 }
3487
3488 /* Prepare and send the vport enable */
3489 memset(&vport_update_params, 0, sizeof(vport_update_params));
088c8618 3490 vport_update_params.vport_id = start.vport_id;
2950219d
YM		 3491 vport_update_params.update_vport_active_flg = 1;
3492 vport_update_params.vport_active_flg = 1;
3493
831bfb0e
YM		 3494 if ((qed_info->mf_mode == QED_MF_NPAR || pci_num_vf(edev->pdev)) &&
3495 qed_info->tx_switching) {
3496 vport_update_params.update_tx_switching_flg = 1;
3497 vport_update_params.tx_switching_flg = 1;
3498 }
3499
2950219d 3500 /* Fill struct with RSS params */
9a4d7e86 3501 if (QEDE_RSS_COUNT(edev) > 1) {
2950219d 3502 vport_update_params.update_rss_flg = 1;
961acdea
SRK		 3503
3504 /* Need to validate current RSS config uses valid entries */
3505 for (i = 0; i < QED_RSS_IND_TABLE_SIZE; i++) {
3506 if (edev->rss_params.rss_ind_table[i] >=
9a4d7e86 3507 QEDE_RSS_COUNT(edev)) {
961acdea
SRK		 3508 reset_rss_indir = true;
3509 break;
3510 }
3511 }
3512
3513 if (!(edev->rss_params_inited & QEDE_RSS_INDIR_INITED) ||
3514 reset_rss_indir) {
3515 u16 val;
3516
3517 for (i = 0; i < QED_RSS_IND_TABLE_SIZE; i++) {
3518 u16 indir_val;
3519
9a4d7e86 3520 val = QEDE_RSS_COUNT(edev);
961acdea
SRK		 3521 indir_val = ethtool_rxfh_indir_default(i, val);
3522 edev->rss_params.rss_ind_table[i] = indir_val;
3523 }
3524 edev->rss_params_inited |= QEDE_RSS_INDIR_INITED;
3525 }
3526
3527 if (!(edev->rss_params_inited & QEDE_RSS_KEY_INITED)) {
3528 netdev_rss_key_fill(edev->rss_params.rss_key,
3529 sizeof(edev->rss_params.rss_key));
3530 edev->rss_params_inited |= QEDE_RSS_KEY_INITED;
3531 }
3532
3533 if (!(edev->rss_params_inited & QEDE_RSS_CAPS_INITED)) {
3534 edev->rss_params.rss_caps = QED_RSS_IPV4 |
3535 QED_RSS_IPV6 |
3536 QED_RSS_IPV4_TCP |
3537 QED_RSS_IPV6_TCP;
3538 edev->rss_params_inited |= QEDE_RSS_CAPS_INITED;
3539 }
3540
3541 memcpy(&vport_update_params.rss_params, &edev->rss_params,
3542 sizeof(vport_update_params.rss_params));
2950219d 3543 } else {
961acdea
SRK		 3544 memset(&vport_update_params.rss_params, 0,
3545 sizeof(vport_update_params.rss_params));
2950219d 3546 }
2950219d
YM		 3547
3548 rc = edev->ops->vport_update(cdev, &vport_update_params);
3549 if (rc) {
3550 DP_ERR(edev, "Update V-PORT failed %d\n", rc);
3551 return rc;
3552 }
3553
3554 return 0;
3555}
3556
0d8e0aa0
SK		 3557static int qede_set_mcast_rx_mac(struct qede_dev *edev,
3558 enum qed_filter_xcast_params_type opcode,
3559 unsigned char *mac, int num_macs)
3560{
3561 struct qed_filter_params filter_cmd;
3562 int i;
3563
3564 memset(&filter_cmd, 0, sizeof(filter_cmd));
3565 filter_cmd.type = QED_FILTER_TYPE_MCAST;
3566 filter_cmd.filter.mcast.type = opcode;
3567 filter_cmd.filter.mcast.num = num_macs;
3568
3569 for (i = 0; i < num_macs; i++, mac += ETH_ALEN)
3570 ether_addr_copy(filter_cmd.filter.mcast.mac[i], mac);
3571
3572 return edev->ops->filter_config(edev->cdev, &filter_cmd);
3573}
3574
2950219d
YM		 3575enum qede_unload_mode {
3576 QEDE_UNLOAD_NORMAL,
3577};
3578
3579static void qede_unload(struct qede_dev *edev, enum qede_unload_mode mode)
3580{
a2ec6172 3581 struct qed_link_params link_params;
2950219d
YM		 3582 int rc;
3583
3584 DP_INFO(edev, "Starting qede unload\n");
3585
cee9fbd8 3586 qede_roce_dev_event_close(edev);
0d8e0aa0
SK		 3587 mutex_lock(&edev->qede_lock);
3588 edev->state = QEDE_STATE_CLOSED;
3589
2950219d
YM		 3590 /* Close OS Tx */
3591 netif_tx_disable(edev->ndev);
3592 netif_carrier_off(edev->ndev);
3593
a2ec6172
SK		 3594 /* Reset the link */
3595 memset(&link_params, 0, sizeof(link_params));
3596 link_params.link_up = false;
3597 edev->ops->common->set_link(edev->cdev, &link_params);
2950219d
YM		 3598 rc = qede_stop_queues(edev);
3599 if (rc) {
3600 qede_sync_free_irqs(edev);
3601 goto out;
3602 }
3603
3604 DP_INFO(edev, "Stopped Queues\n");
3605
7c1bfcad 3606 qede_vlan_mark_nonconfigured(edev);
2950219d
YM		 3607 edev->ops->fastpath_stop(edev->cdev);
3608
3609 /* Release the interrupts */
3610 qede_sync_free_irqs(edev);
3611 edev->ops->common->set_fp_int(edev->cdev, 0);
3612
3613 qede_napi_disable_remove(edev);
3614
3615 qede_free_mem_load(edev);
3616 qede_free_fp_array(edev);
3617
3618out:
3619 mutex_unlock(&edev->qede_lock);
3620 DP_INFO(edev, "Ending qede unload\n");
3621}
3622
3623enum qede_load_mode {
3624 QEDE_LOAD_NORMAL,
a0d26d5a 3625 QEDE_LOAD_RELOAD,
2950219d
YM		 3626};
3627
3628static int qede_load(struct qede_dev *edev, enum qede_load_mode mode)
3629{
a2ec6172
SK		 3630 struct qed_link_params link_params;
3631 struct qed_link_output link_output;
2950219d
YM		 3632 int rc;
3633
3634 DP_INFO(edev, "Starting qede load\n");
3635
3636 rc = qede_set_num_queues(edev);
3637 if (rc)
3638 goto err0;
3639
3640 rc = qede_alloc_fp_array(edev);
3641 if (rc)
3642 goto err0;
3643
3644 qede_init_fp(edev);
3645
3646 rc = qede_alloc_mem_load(edev);
3647 if (rc)
3648 goto err1;
80439a17
MY		 3649 DP_INFO(edev, "Allocated %d Rx, %d Tx queues\n",
3650 QEDE_RSS_COUNT(edev), QEDE_TSS_COUNT(edev));
2950219d
YM		 3651
3652 rc = qede_set_real_num_queues(edev);
3653 if (rc)
3654 goto err2;
3655
3656 qede_napi_add_enable(edev);
3657 DP_INFO(edev, "Napi added and enabled\n");
3658
3659 rc = qede_setup_irqs(edev);
3660 if (rc)
3661 goto err3;
3662 DP_INFO(edev, "Setup IRQs succeeded\n");
3663
a0d26d5a 3664 rc = qede_start_queues(edev, mode != QEDE_LOAD_RELOAD);
2950219d
YM		 3665 if (rc)
3666 goto err4;
3667 DP_INFO(edev, "Start VPORT, RXQ and TXQ succeeded\n");
3668
3669 /* Add primary mac and set Rx filters */
3670 ether_addr_copy(edev->primary_mac, edev->ndev->dev_addr);
3671
0d8e0aa0
SK		 3672 mutex_lock(&edev->qede_lock);
3673 edev->state = QEDE_STATE_OPEN;
3674 mutex_unlock(&edev->qede_lock);
a2ec6172 3675
7c1bfcad
SRK		 3676 /* Program un-configured VLANs */
3677 qede_configure_vlan_filters(edev);
3678
a2ec6172
SK		 3679 /* Ask for link-up using current configuration */
3680 memset(&link_params, 0, sizeof(link_params));
3681 link_params.link_up = true;
3682 edev->ops->common->set_link(edev->cdev, &link_params);
3683
3684 /* Query whether link is already-up */
3685 memset(&link_output, 0, sizeof(link_output));
3686 edev->ops->common->get_link(edev->cdev, &link_output);
cee9fbd8 3687 qede_roce_dev_event_open(edev);
a2ec6172
SK		 3688 qede_link_update(edev, &link_output);
3689
2950219d
YM		 3690 DP_INFO(edev, "Ending successfully qede load\n");
3691
3692 return 0;
3693
3694err4:
3695 qede_sync_free_irqs(edev);
3696 memset(&edev->int_info.msix_cnt, 0, sizeof(struct qed_int_info));
3697err3:
3698 qede_napi_disable_remove(edev);
3699err2:
3700 qede_free_mem_load(edev);
3701err1:
3702 edev->ops->common->set_fp_int(edev->cdev, 0);
3703 qede_free_fp_array(edev);
9a4d7e86
SRK		 3704 edev->num_queues = 0;
3705 edev->fp_num_tx = 0;
3706 edev->fp_num_rx = 0;
2950219d
YM		 3707err0:
3708 return rc;
3709}
3710
133fac0e
SK		 3711void qede_reload(struct qede_dev *edev,
3712 void (*func)(struct qede_dev *, union qede_reload_args *),
3713 union qede_reload_args *args)
3714{
3715 qede_unload(edev, QEDE_UNLOAD_NORMAL);
3716 /* Call function handler to update parameters
3717 * needed for function load.
3718 */
3719 if (func)
3720 func(edev, args);
3721
a0d26d5a 3722 qede_load(edev, QEDE_LOAD_RELOAD);
133fac0e
SK		 3723
3724 mutex_lock(&edev->qede_lock);
3725 qede_config_rx_mode(edev->ndev);
3726 mutex_unlock(&edev->qede_lock);
3727}
3728
2950219d
YM		 3729/* called with rtnl_lock */
3730static int qede_open(struct net_device *ndev)
3731{
3732 struct qede_dev *edev = netdev_priv(ndev);
b18e170c 3733 int rc;
2950219d
YM		 3734
3735 netif_carrier_off(ndev);
3736
3737 edev->ops->common->set_power_state(edev->cdev, PCI_D0);
3738
b18e170c
MC		 3739 rc = qede_load(edev, QEDE_LOAD_NORMAL);
3740
3741 if (rc)
3742 return rc;
3743
f9f082a9
AD		 3744 udp_tunnel_get_rx_info(ndev);
3745
0fefbfba
SK		 3746 edev->ops->common->update_drv_state(edev->cdev, true);
3747
b18e170c 3748 return 0;
2950219d
YM		 3749}
3750
3751static int qede_close(struct net_device *ndev)
3752{
3753 struct qede_dev *edev = netdev_priv(ndev);
3754
3755 qede_unload(edev, QEDE_UNLOAD_NORMAL);
3756
0fefbfba
SK		 3757 edev->ops->common->update_drv_state(edev->cdev, false);
3758
2950219d
YM		 3759 return 0;
3760}
0d8e0aa0 3761
a2ec6172
SK		 3762static void qede_link_update(void *dev, struct qed_link_output *link)
3763{
3764 struct qede_dev *edev = dev;
3765
3766 if (!netif_running(edev->ndev)) {
3767 DP_VERBOSE(edev, NETIF_MSG_LINK, "Interface is not running\n");
3768 return;
3769 }
3770
3771 if (link->link_up) {
8e025ae2
YM		 3772 if (!netif_carrier_ok(edev->ndev)) {
3773 DP_NOTICE(edev, "Link is up\n");
3774 netif_tx_start_all_queues(edev->ndev);
3775 netif_carrier_on(edev->ndev);
3776 }
a2ec6172 3777 } else {
8e025ae2
YM		 3778 if (netif_carrier_ok(edev->ndev)) {
3779 DP_NOTICE(edev, "Link is down\n");
3780 netif_tx_disable(edev->ndev);
3781 netif_carrier_off(edev->ndev);
3782 }
a2ec6172
SK		 3783 }
3784}
3785
0d8e0aa0
SK		 3786static int qede_set_mac_addr(struct net_device *ndev, void *p)
3787{
3788 struct qede_dev *edev = netdev_priv(ndev);
3789 struct sockaddr *addr = p;
3790 int rc;
3791
3792 ASSERT_RTNL(); /* @@@TBD To be removed */
3793
3794 DP_INFO(edev, "Set_mac_addr called\n");
3795
3796 if (!is_valid_ether_addr(addr->sa_data)) {
3797 DP_NOTICE(edev, "The MAC address is not valid\n");
3798 return -EFAULT;
3799 }
3800
eff16960
YM		 3801 if (!edev->ops->check_mac(edev->cdev, addr->sa_data)) {
3802 DP_NOTICE(edev, "qed prevents setting MAC\n");
3803 return -EINVAL;
3804 }
3805
0d8e0aa0
SK		 3806 ether_addr_copy(ndev->dev_addr, addr->sa_data);
3807
3808 if (!netif_running(ndev)) {
3809 DP_NOTICE(edev, "The device is currently down\n");
3810 return 0;
3811 }
3812
3813 /* Remove the previous primary mac */
3814 rc = qede_set_ucast_rx_mac(edev, QED_FILTER_XCAST_TYPE_DEL,
3815 edev->primary_mac);
3816 if (rc)
3817 return rc;
3818
0fefbfba
SK		 3819 edev->ops->common->update_mac(edev->cdev, addr->sa_data);
3820
0d8e0aa0
SK		 3821 /* Add MAC filter according to the new unicast HW MAC address */
3822 ether_addr_copy(edev->primary_mac, ndev->dev_addr);
3823 return qede_set_ucast_rx_mac(edev, QED_FILTER_XCAST_TYPE_ADD,
3824 edev->primary_mac);
3825}
3826
3827static int
3828qede_configure_mcast_filtering(struct net_device *ndev,
3829 enum qed_filter_rx_mode_type *accept_flags)
3830{
3831 struct qede_dev *edev = netdev_priv(ndev);
3832 unsigned char *mc_macs, *temp;
3833 struct netdev_hw_addr *ha;
3834 int rc = 0, mc_count;
3835 size_t size;
3836
3837 size = 64 * ETH_ALEN;
3838
3839 mc_macs = kzalloc(size, GFP_KERNEL);
3840 if (!mc_macs) {
3841 DP_NOTICE(edev,
3842 "Failed to allocate memory for multicast MACs\n");
3843 rc = -ENOMEM;
3844 goto exit;
3845 }
3846
3847 temp = mc_macs;
3848
3849 /* Remove all previously configured MAC filters */
3850 rc = qede_set_mcast_rx_mac(edev, QED_FILTER_XCAST_TYPE_DEL,
3851 mc_macs, 1);
3852 if (rc)
3853 goto exit;
3854
3855 netif_addr_lock_bh(ndev);
3856
3857 mc_count = netdev_mc_count(ndev);
3858 if (mc_count < 64) {
3859 netdev_for_each_mc_addr(ha, ndev) {
3860 ether_addr_copy(temp, ha->addr);
3861 temp += ETH_ALEN;
3862 }
3863 }
3864
3865 netif_addr_unlock_bh(ndev);
3866
3867 /* Check for all multicast @@@TBD resource allocation */
3868 if ((ndev->flags & IFF_ALLMULTI) ||
3869 (mc_count > 64)) {
3870 if (*accept_flags == QED_FILTER_RX_MODE_TYPE_REGULAR)
3871 *accept_flags = QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
3872 } else {
3873 /* Add all multicast MAC filters */
3874 rc = qede_set_mcast_rx_mac(edev, QED_FILTER_XCAST_TYPE_ADD,
3875 mc_macs, mc_count);
3876 }
3877
3878exit:
3879 kfree(mc_macs);
3880 return rc;
3881}
3882
3883static void qede_set_rx_mode(struct net_device *ndev)
3884{
3885 struct qede_dev *edev = netdev_priv(ndev);
3886
3887 DP_INFO(edev, "qede_set_rx_mode called\n");
3888
3889 if (edev->state != QEDE_STATE_OPEN) {
3890 DP_INFO(edev,
3891 "qede_set_rx_mode called while interface is down\n");
3892 } else {
3893 set_bit(QEDE_SP_RX_MODE, &edev->sp_flags);
3894 schedule_delayed_work(&edev->sp_task, 0);
3895 }
3896}
3897
3898/* Must be called with qede_lock held */
3899static void qede_config_rx_mode(struct net_device *ndev)
3900{
3901 enum qed_filter_rx_mode_type accept_flags = QED_FILTER_TYPE_UCAST;
3902 struct qede_dev *edev = netdev_priv(ndev);
3903 struct qed_filter_params rx_mode;
3904 unsigned char *uc_macs, *temp;
3905 struct netdev_hw_addr *ha;
3906 int rc, uc_count;
3907 size_t size;
3908
3909 netif_addr_lock_bh(ndev);
3910
3911 uc_count = netdev_uc_count(ndev);
3912 size = uc_count * ETH_ALEN;
3913
3914 uc_macs = kzalloc(size, GFP_ATOMIC);
3915 if (!uc_macs) {
3916 DP_NOTICE(edev, "Failed to allocate memory for unicast MACs\n");
3917 netif_addr_unlock_bh(ndev);
3918 return;
3919 }
3920
3921 temp = uc_macs;
3922 netdev_for_each_uc_addr(ha, ndev) {
3923 ether_addr_copy(temp, ha->addr);
3924 temp += ETH_ALEN;
3925 }
3926
3927 netif_addr_unlock_bh(ndev);
3928
3929 /* Configure the struct for the Rx mode */
3930 memset(&rx_mode, 0, sizeof(struct qed_filter_params));
3931 rx_mode.type = QED_FILTER_TYPE_RX_MODE;
3932
3933 /* Remove all previous unicast secondary macs and multicast macs
3934 * (configrue / leave the primary mac)
3935 */
3936 rc = qede_set_ucast_rx_mac(edev, QED_FILTER_XCAST_TYPE_REPLACE,
3937 edev->primary_mac);
3938 if (rc)
3939 goto out;
3940
3941 /* Check for promiscuous */
3942 if ((ndev->flags & IFF_PROMISC) ||
7b7e70f9 3943 (uc_count > edev->dev_info.num_mac_filters - 1)) {
0d8e0aa0
SK		 3944 accept_flags = QED_FILTER_RX_MODE_TYPE_PROMISC;
3945 } else {
3946 /* Add MAC filters according to the unicast secondary macs */
3947 int i;
3948
3949 temp = uc_macs;
3950 for (i = 0; i < uc_count; i++) {
3951 rc = qede_set_ucast_rx_mac(edev,
3952 QED_FILTER_XCAST_TYPE_ADD,
3953 temp);
3954 if (rc)
3955 goto out;
3956
3957 temp += ETH_ALEN;
3958 }
3959
3960 rc = qede_configure_mcast_filtering(ndev, &accept_flags);
3961 if (rc)
3962 goto out;
3963 }
3964
7c1bfcad
SRK		 3965 /* take care of VLAN mode */
3966 if (ndev->flags & IFF_PROMISC) {
3967 qede_config_accept_any_vlan(edev, true);
3968 } else if (!edev->non_configured_vlans) {
3969 /* It's possible that accept_any_vlan mode is set due to a
3970 * previous setting of IFF_PROMISC. If vlan credits are
3971 * sufficient, disable accept_any_vlan.
3972 */
3973 qede_config_accept_any_vlan(edev, false);
3974 }
3975
0d8e0aa0
SK		 3976 rx_mode.filter.accept_flags = accept_flags;
3977 edev->ops->filter_config(edev->cdev, &rx_mode);
3978out:
3979 kfree(uc_macs);
3980}
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