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Commit | Line | Data |
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af19b491 | 1 | /* |
40839129 SV |
2 | * QLogic qlcnic NIC Driver |
3 | * Copyright (c) 2009-2010 QLogic Corporation | |
af19b491 | 4 | * |
40839129 | 5 | * See LICENSE.qlcnic for copyright and licensing details. |
af19b491 AKS |
6 | */ |
7 | ||
8 | #ifndef _QLCNIC_H_ | |
9 | #define _QLCNIC_H_ | |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/kernel.h> | |
13 | #include <linux/types.h> | |
14 | #include <linux/ioport.h> | |
15 | #include <linux/pci.h> | |
16 | #include <linux/netdevice.h> | |
17 | #include <linux/etherdevice.h> | |
18 | #include <linux/ip.h> | |
19 | #include <linux/in.h> | |
20 | #include <linux/tcp.h> | |
21 | #include <linux/skbuff.h> | |
22 | #include <linux/firmware.h> | |
23 | ||
24 | #include <linux/ethtool.h> | |
25 | #include <linux/mii.h> | |
26 | #include <linux/timer.h> | |
27 | ||
28 | #include <linux/vmalloc.h> | |
29 | ||
30 | #include <linux/io.h> | |
31 | #include <asm/byteorder.h> | |
b9796a14 AC |
32 | #include <linux/bitops.h> |
33 | #include <linux/if_vlan.h> | |
af19b491 AKS |
34 | |
35 | #include "qlcnic_hdr.h" | |
36 | ||
37 | #define _QLCNIC_LINUX_MAJOR 5 | |
38 | #define _QLCNIC_LINUX_MINOR 0 | |
0bb79565 RB |
39 | #define _QLCNIC_LINUX_SUBVERSION 29 |
40 | #define QLCNIC_LINUX_VERSIONID "5.0.29" | |
96f8118c | 41 | #define QLCNIC_DRV_IDC_VER 0x01 |
d4066833 SC |
42 | #define QLCNIC_DRIVER_VERSION ((_QLCNIC_LINUX_MAJOR << 16) |\ |
43 | (_QLCNIC_LINUX_MINOR << 8) | (_QLCNIC_LINUX_SUBVERSION)) | |
af19b491 AKS |
44 | |
45 | #define QLCNIC_VERSION_CODE(a, b, c) (((a) << 24) + ((b) << 16) + (c)) | |
46 | #define _major(v) (((v) >> 24) & 0xff) | |
47 | #define _minor(v) (((v) >> 16) & 0xff) | |
48 | #define _build(v) ((v) & 0xffff) | |
49 | ||
50 | /* version in image has weird encoding: | |
51 | * 7:0 - major | |
52 | * 15:8 - minor | |
53 | * 31:16 - build (little endian) | |
54 | */ | |
55 | #define QLCNIC_DECODE_VERSION(v) \ | |
56 | QLCNIC_VERSION_CODE(((v) & 0xff), (((v) >> 8) & 0xff), ((v) >> 16)) | |
57 | ||
8f891387 | 58 | #define QLCNIC_MIN_FW_VERSION QLCNIC_VERSION_CODE(4, 4, 2) |
af19b491 AKS |
59 | #define QLCNIC_NUM_FLASH_SECTORS (64) |
60 | #define QLCNIC_FLASH_SECTOR_SIZE (64 * 1024) | |
61 | #define QLCNIC_FLASH_TOTAL_SIZE (QLCNIC_NUM_FLASH_SECTORS \ | |
62 | * QLCNIC_FLASH_SECTOR_SIZE) | |
63 | ||
64 | #define RCV_DESC_RINGSIZE(rds_ring) \ | |
65 | (sizeof(struct rcv_desc) * (rds_ring)->num_desc) | |
66 | #define RCV_BUFF_RINGSIZE(rds_ring) \ | |
67 | (sizeof(struct qlcnic_rx_buffer) * rds_ring->num_desc) | |
68 | #define STATUS_DESC_RINGSIZE(sds_ring) \ | |
69 | (sizeof(struct status_desc) * (sds_ring)->num_desc) | |
70 | #define TX_BUFF_RINGSIZE(tx_ring) \ | |
71 | (sizeof(struct qlcnic_cmd_buffer) * tx_ring->num_desc) | |
72 | #define TX_DESC_RINGSIZE(tx_ring) \ | |
73 | (sizeof(struct cmd_desc_type0) * tx_ring->num_desc) | |
74 | ||
75 | #define QLCNIC_P3P_A0 0x50 | |
a2050c7e | 76 | #define QLCNIC_P3P_C0 0x58 |
af19b491 AKS |
77 | |
78 | #define QLCNIC_IS_REVISION_P3P(REVISION) (REVISION >= QLCNIC_P3P_A0) | |
79 | ||
80 | #define FIRST_PAGE_GROUP_START 0 | |
81 | #define FIRST_PAGE_GROUP_END 0x100000 | |
82 | ||
ff1b1bf8 SV |
83 | #define P3P_MAX_MTU (9600) |
84 | #define P3P_MIN_MTU (68) | |
af19b491 AKS |
85 | #define QLCNIC_MAX_ETHERHDR 32 /* This contains some padding */ |
86 | ||
ff1b1bf8 SV |
87 | #define QLCNIC_P3P_RX_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + ETH_DATA_LEN) |
88 | #define QLCNIC_P3P_RX_JUMBO_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + P3P_MAX_MTU) | |
af19b491 AKS |
89 | #define QLCNIC_CT_DEFAULT_RX_BUF_LEN 2048 |
90 | #define QLCNIC_LRO_BUFFER_EXTRA 2048 | |
91 | ||
af19b491 | 92 | /* Tx defines */ |
91a403ca | 93 | #define QLCNIC_MAX_FRAGS_PER_TX 14 |
ef71ff83 RB |
94 | #define MAX_TSO_HEADER_DESC 2 |
95 | #define MGMT_CMD_DESC_RESV 4 | |
96 | #define TX_STOP_THRESH ((MAX_SKB_FRAGS >> 2) + MAX_TSO_HEADER_DESC \ | |
97 | + MGMT_CMD_DESC_RESV) | |
af19b491 AKS |
98 | #define QLCNIC_MAX_TX_TIMEOUTS 2 |
99 | ||
100 | /* | |
101 | * Following are the states of the Phantom. Phantom will set them and | |
102 | * Host will read to check if the fields are correct. | |
103 | */ | |
104 | #define PHAN_INITIALIZE_FAILED 0xffff | |
105 | #define PHAN_INITIALIZE_COMPLETE 0xff01 | |
106 | ||
107 | /* Host writes the following to notify that it has done the init-handshake */ | |
108 | #define PHAN_INITIALIZE_ACK 0xf00f | |
109 | #define PHAN_PEG_RCV_INITIALIZED 0xff01 | |
110 | ||
111 | #define NUM_RCV_DESC_RINGS 3 | |
af19b491 AKS |
112 | |
113 | #define RCV_RING_NORMAL 0 | |
114 | #define RCV_RING_JUMBO 1 | |
af19b491 AKS |
115 | |
116 | #define MIN_CMD_DESCRIPTORS 64 | |
117 | #define MIN_RCV_DESCRIPTORS 64 | |
118 | #define MIN_JUMBO_DESCRIPTORS 32 | |
119 | ||
120 | #define MAX_CMD_DESCRIPTORS 1024 | |
121 | #define MAX_RCV_DESCRIPTORS_1G 4096 | |
122 | #define MAX_RCV_DESCRIPTORS_10G 8192 | |
90d19005 | 123 | #define MAX_RCV_DESCRIPTORS_VF 2048 |
af19b491 AKS |
124 | #define MAX_JUMBO_RCV_DESCRIPTORS_1G 512 |
125 | #define MAX_JUMBO_RCV_DESCRIPTORS_10G 1024 | |
af19b491 AKS |
126 | |
127 | #define DEFAULT_RCV_DESCRIPTORS_1G 2048 | |
128 | #define DEFAULT_RCV_DESCRIPTORS_10G 4096 | |
90d19005 | 129 | #define DEFAULT_RCV_DESCRIPTORS_VF 1024 |
251b036a | 130 | #define MAX_RDS_RINGS 2 |
af19b491 AKS |
131 | |
132 | #define get_next_index(index, length) \ | |
133 | (((index) + 1) & ((length) - 1)) | |
134 | ||
af19b491 AKS |
135 | /* |
136 | * Following data structures describe the descriptors that will be used. | |
137 | * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when | |
138 | * we are doing LSO (above the 1500 size packet) only. | |
139 | */ | |
af19b491 AKS |
140 | struct cmd_desc_type0 { |
141 | u8 tcp_hdr_offset; /* For LSO only */ | |
142 | u8 ip_hdr_offset; /* For LSO only */ | |
143 | __le16 flags_opcode; /* 15:13 unused, 12:7 opcode, 6:0 flags */ | |
144 | __le32 nfrags__length; /* 31:8 total len, 7:0 frag count */ | |
145 | ||
146 | __le64 addr_buffer2; | |
147 | ||
148 | __le16 reference_handle; | |
149 | __le16 mss; | |
150 | u8 port_ctxid; /* 7:4 ctxid 3:0 port */ | |
151 | u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */ | |
152 | __le16 conn_id; /* IPSec offoad only */ | |
153 | ||
154 | __le64 addr_buffer3; | |
155 | __le64 addr_buffer1; | |
156 | ||
157 | __le16 buffer_length[4]; | |
158 | ||
159 | __le64 addr_buffer4; | |
160 | ||
2e9d722d | 161 | u8 eth_addr[ETH_ALEN]; |
af19b491 AKS |
162 | __le16 vlan_TCI; |
163 | ||
164 | } __attribute__ ((aligned(64))); | |
165 | ||
166 | /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */ | |
167 | struct rcv_desc { | |
168 | __le16 reference_handle; | |
169 | __le16 reserved; | |
170 | __le32 buffer_length; /* allocated buffer length (usually 2K) */ | |
171 | __le64 addr_buffer; | |
b1fc6d3c | 172 | } __packed; |
af19b491 | 173 | |
af19b491 AKS |
174 | struct status_desc { |
175 | __le64 status_desc_data[2]; | |
176 | } __attribute__ ((aligned(16))); | |
177 | ||
178 | /* UNIFIED ROMIMAGE */ | |
179 | #define QLCNIC_UNI_FW_MIN_SIZE 0xc8000 | |
180 | #define QLCNIC_UNI_DIR_SECT_PRODUCT_TBL 0x0 | |
181 | #define QLCNIC_UNI_DIR_SECT_BOOTLD 0x6 | |
182 | #define QLCNIC_UNI_DIR_SECT_FW 0x7 | |
183 | ||
184 | /*Offsets */ | |
185 | #define QLCNIC_UNI_CHIP_REV_OFF 10 | |
186 | #define QLCNIC_UNI_FLAGS_OFF 11 | |
187 | #define QLCNIC_UNI_BIOS_VERSION_OFF 12 | |
188 | #define QLCNIC_UNI_BOOTLD_IDX_OFF 27 | |
189 | #define QLCNIC_UNI_FIRMWARE_IDX_OFF 29 | |
190 | ||
191 | struct uni_table_desc{ | |
63507592 SS |
192 | __le32 findex; |
193 | __le32 num_entries; | |
194 | __le32 entry_size; | |
195 | __le32 reserved[5]; | |
af19b491 AKS |
196 | }; |
197 | ||
198 | struct uni_data_desc{ | |
63507592 SS |
199 | __le32 findex; |
200 | __le32 size; | |
201 | __le32 reserved[5]; | |
af19b491 AKS |
202 | }; |
203 | ||
0e5f20b6 | 204 | /* Flash Defines and Structures */ |
205 | #define QLCNIC_FLT_LOCATION 0x3F1000 | |
a2050c7e SV |
206 | #define QLCNIC_B0_FW_IMAGE_REGION 0x74 |
207 | #define QLCNIC_C0_FW_IMAGE_REGION 0x97 | |
f8d54811 | 208 | #define QLCNIC_BOOTLD_REGION 0X72 |
0e5f20b6 | 209 | struct qlcnic_flt_header { |
210 | u16 version; | |
211 | u16 len; | |
212 | u16 checksum; | |
213 | u16 reserved; | |
214 | }; | |
215 | ||
216 | struct qlcnic_flt_entry { | |
217 | u8 region; | |
218 | u8 reserved0; | |
219 | u8 attrib; | |
220 | u8 reserved1; | |
221 | u32 size; | |
222 | u32 start_addr; | |
f8d54811 | 223 | u32 end_addr; |
0e5f20b6 | 224 | }; |
225 | ||
af19b491 AKS |
226 | /* Magic number to let user know flash is programmed */ |
227 | #define QLCNIC_BDINFO_MAGIC 0x12345678 | |
228 | ||
ff1b1bf8 SV |
229 | #define QLCNIC_BRDTYPE_P3P_REF_QG 0x0021 |
230 | #define QLCNIC_BRDTYPE_P3P_HMEZ 0x0022 | |
231 | #define QLCNIC_BRDTYPE_P3P_10G_CX4_LP 0x0023 | |
232 | #define QLCNIC_BRDTYPE_P3P_4_GB 0x0024 | |
233 | #define QLCNIC_BRDTYPE_P3P_IMEZ 0x0025 | |
234 | #define QLCNIC_BRDTYPE_P3P_10G_SFP_PLUS 0x0026 | |
235 | #define QLCNIC_BRDTYPE_P3P_10000_BASE_T 0x0027 | |
236 | #define QLCNIC_BRDTYPE_P3P_XG_LOM 0x0028 | |
237 | #define QLCNIC_BRDTYPE_P3P_4_GB_MM 0x0029 | |
238 | #define QLCNIC_BRDTYPE_P3P_10G_SFP_CT 0x002a | |
239 | #define QLCNIC_BRDTYPE_P3P_10G_SFP_QT 0x002b | |
240 | #define QLCNIC_BRDTYPE_P3P_10G_CX4 0x0031 | |
241 | #define QLCNIC_BRDTYPE_P3P_10G_XFP 0x0032 | |
242 | #define QLCNIC_BRDTYPE_P3P_10G_TP 0x0080 | |
af19b491 | 243 | |
2e9d722d AC |
244 | #define QLCNIC_MSIX_TABLE_OFFSET 0x44 |
245 | ||
af19b491 AKS |
246 | /* Flash memory map */ |
247 | #define QLCNIC_BRDCFG_START 0x4000 /* board config */ | |
248 | #define QLCNIC_BOOTLD_START 0x10000 /* bootld */ | |
249 | #define QLCNIC_IMAGE_START 0x43000 /* compressed image */ | |
250 | #define QLCNIC_USER_START 0x3E8000 /* Firmare info */ | |
251 | ||
252 | #define QLCNIC_FW_VERSION_OFFSET (QLCNIC_USER_START+0x408) | |
253 | #define QLCNIC_FW_SIZE_OFFSET (QLCNIC_USER_START+0x40c) | |
254 | #define QLCNIC_FW_SERIAL_NUM_OFFSET (QLCNIC_USER_START+0x81c) | |
255 | #define QLCNIC_BIOS_VERSION_OFFSET (QLCNIC_USER_START+0x83c) | |
256 | ||
257 | #define QLCNIC_BRDTYPE_OFFSET (QLCNIC_BRDCFG_START+0x8) | |
258 | #define QLCNIC_FW_MAGIC_OFFSET (QLCNIC_BRDCFG_START+0x128) | |
259 | ||
260 | #define QLCNIC_FW_MIN_SIZE (0x3fffff) | |
261 | #define QLCNIC_UNIFIED_ROMIMAGE 0 | |
262 | #define QLCNIC_FLASH_ROMIMAGE 1 | |
263 | #define QLCNIC_UNKNOWN_ROMIMAGE 0xff | |
264 | ||
265 | #define QLCNIC_UNIFIED_ROMIMAGE_NAME "phanfw.bin" | |
266 | #define QLCNIC_FLASH_ROMIMAGE_NAME "flash" | |
267 | ||
268 | extern char qlcnic_driver_name[]; | |
269 | ||
270 | /* Number of status descriptors to handle per interrupt */ | |
271 | #define MAX_STATUS_HANDLE (64) | |
272 | ||
273 | /* | |
274 | * qlcnic_skb_frag{} is to contain mapping info for each SG list. This | |
275 | * has to be freed when DMA is complete. This is part of qlcnic_tx_buffer{}. | |
276 | */ | |
277 | struct qlcnic_skb_frag { | |
278 | u64 dma; | |
279 | u64 length; | |
280 | }; | |
281 | ||
af19b491 AKS |
282 | /* Following defines are for the state of the buffers */ |
283 | #define QLCNIC_BUFFER_FREE 0 | |
284 | #define QLCNIC_BUFFER_BUSY 1 | |
285 | ||
286 | /* | |
287 | * There will be one qlcnic_buffer per skb packet. These will be | |
288 | * used to save the dma info for pci_unmap_page() | |
289 | */ | |
290 | struct qlcnic_cmd_buffer { | |
291 | struct sk_buff *skb; | |
ef71ff83 | 292 | struct qlcnic_skb_frag frag_array[MAX_SKB_FRAGS + 1]; |
af19b491 AKS |
293 | u32 frag_count; |
294 | }; | |
295 | ||
296 | /* In rx_buffer, we do not need multiple fragments as is a single buffer */ | |
297 | struct qlcnic_rx_buffer { | |
b1fc6d3c | 298 | u16 ref_handle; |
af19b491 | 299 | struct sk_buff *skb; |
b1fc6d3c | 300 | struct list_head list; |
af19b491 | 301 | u64 dma; |
af19b491 AKS |
302 | }; |
303 | ||
304 | /* Board types */ | |
305 | #define QLCNIC_GBE 0x01 | |
306 | #define QLCNIC_XGBE 0x02 | |
307 | ||
8816d009 AC |
308 | /* |
309 | * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is | |
310 | * adjusted based on configured MTU. | |
311 | */ | |
312 | #define QLCNIC_DEFAULT_INTR_COALESCE_RX_TIME_US 3 | |
313 | #define QLCNIC_DEFAULT_INTR_COALESCE_RX_PACKETS 256 | |
314 | ||
315 | #define QLCNIC_INTR_DEFAULT 0x04 | |
316 | #define QLCNIC_CONFIG_INTR_COALESCE 3 | |
317 | ||
318 | struct qlcnic_nic_intr_coalesce { | |
319 | u8 type; | |
320 | u8 sts_ring_mask; | |
321 | u16 rx_packets; | |
322 | u16 rx_time_us; | |
323 | u16 flag; | |
324 | u32 timer_out; | |
325 | }; | |
326 | ||
18f2f616 | 327 | struct qlcnic_dump_template_hdr { |
63507592 SS |
328 | u32 type; |
329 | u32 offset; | |
330 | u32 size; | |
331 | u32 cap_mask; | |
332 | u32 num_entries; | |
333 | u32 version; | |
334 | u32 timestamp; | |
335 | u32 checksum; | |
336 | u32 drv_cap_mask; | |
337 | u32 sys_info[3]; | |
338 | u32 saved_state[16]; | |
339 | u32 cap_sizes[8]; | |
340 | u32 rsvd[0]; | |
18f2f616 AC |
341 | }; |
342 | ||
343 | struct qlcnic_fw_dump { | |
344 | u8 clr; /* flag to indicate if dump is cleared */ | |
9d6a6440 | 345 | u8 enable; /* enable/disable dump */ |
18f2f616 AC |
346 | u32 size; /* total size of the dump */ |
347 | void *data; /* dump data area */ | |
348 | struct qlcnic_dump_template_hdr *tmpl_hdr; | |
349 | }; | |
350 | ||
af19b491 AKS |
351 | /* |
352 | * One hardware_context{} per adapter | |
353 | * contains interrupt info as well shared hardware info. | |
354 | */ | |
355 | struct qlcnic_hardware_context { | |
356 | void __iomem *pci_base0; | |
357 | void __iomem *ocm_win_crb; | |
358 | ||
359 | unsigned long pci_len0; | |
360 | ||
af19b491 AKS |
361 | rwlock_t crb_lock; |
362 | struct mutex mem_lock; | |
363 | ||
af19b491 AKS |
364 | u8 revision_id; |
365 | u8 pci_func; | |
366 | u8 linkup; | |
22c8c934 | 367 | u8 loopback_state; |
af19b491 AKS |
368 | u16 port_type; |
369 | u16 board_type; | |
8816d009 | 370 | |
728a98b8 SC |
371 | u8 beacon_state; |
372 | ||
8816d009 | 373 | struct qlcnic_nic_intr_coalesce coal; |
18f2f616 | 374 | struct qlcnic_fw_dump fw_dump; |
af19b491 AKS |
375 | }; |
376 | ||
377 | struct qlcnic_adapter_stats { | |
378 | u64 xmitcalled; | |
379 | u64 xmitfinished; | |
380 | u64 rxdropped; | |
381 | u64 txdropped; | |
382 | u64 csummed; | |
383 | u64 rx_pkts; | |
384 | u64 lro_pkts; | |
385 | u64 rxbytes; | |
386 | u64 txbytes; | |
8bfe8b91 SC |
387 | u64 lrobytes; |
388 | u64 lso_frames; | |
389 | u64 xmit_on; | |
390 | u64 xmit_off; | |
391 | u64 skb_alloc_failure; | |
8ae6df97 AKS |
392 | u64 null_rxbuf; |
393 | u64 rx_dma_map_error; | |
394 | u64 tx_dma_map_error; | |
af19b491 AKS |
395 | }; |
396 | ||
397 | /* | |
398 | * Rcv Descriptor Context. One such per Rcv Descriptor. There may | |
399 | * be one Rcv Descriptor for normal packets, one for jumbo and may be others. | |
400 | */ | |
401 | struct qlcnic_host_rds_ring { | |
036d61f0 AC |
402 | void __iomem *crb_rcv_producer; |
403 | struct rcv_desc *desc_head; | |
404 | struct qlcnic_rx_buffer *rx_buf_arr; | |
af19b491 | 405 | u32 num_desc; |
036d61f0 | 406 | u32 producer; |
af19b491 AKS |
407 | u32 dma_size; |
408 | u32 skb_size; | |
409 | u32 flags; | |
af19b491 AKS |
410 | struct list_head free_list; |
411 | spinlock_t lock; | |
412 | dma_addr_t phys_addr; | |
036d61f0 | 413 | } ____cacheline_internodealigned_in_smp; |
af19b491 AKS |
414 | |
415 | struct qlcnic_host_sds_ring { | |
416 | u32 consumer; | |
417 | u32 num_desc; | |
418 | void __iomem *crb_sts_consumer; | |
af19b491 AKS |
419 | |
420 | struct status_desc *desc_head; | |
421 | struct qlcnic_adapter *adapter; | |
422 | struct napi_struct napi; | |
423 | struct list_head free_list[NUM_RCV_DESC_RINGS]; | |
424 | ||
036d61f0 | 425 | void __iomem *crb_intr_mask; |
af19b491 AKS |
426 | int irq; |
427 | ||
428 | dma_addr_t phys_addr; | |
429 | char name[IFNAMSIZ+4]; | |
036d61f0 | 430 | } ____cacheline_internodealigned_in_smp; |
af19b491 AKS |
431 | |
432 | struct qlcnic_host_tx_ring { | |
433 | u32 producer; | |
af19b491 | 434 | u32 sw_consumer; |
af19b491 | 435 | u32 num_desc; |
036d61f0 | 436 | void __iomem *crb_cmd_producer; |
af19b491 | 437 | struct cmd_desc_type0 *desc_head; |
036d61f0 AC |
438 | struct qlcnic_cmd_buffer *cmd_buf_arr; |
439 | __le32 *hw_consumer; | |
440 | ||
af19b491 AKS |
441 | dma_addr_t phys_addr; |
442 | dma_addr_t hw_cons_phys_addr; | |
036d61f0 AC |
443 | struct netdev_queue *txq; |
444 | } ____cacheline_internodealigned_in_smp; | |
af19b491 AKS |
445 | |
446 | /* | |
447 | * Receive context. There is one such structure per instance of the | |
448 | * receive processing. Any state information that is relevant to | |
449 | * the receive, and is must be in this structure. The global data may be | |
450 | * present elsewhere. | |
451 | */ | |
452 | struct qlcnic_recv_context { | |
b1fc6d3c AC |
453 | struct qlcnic_host_rds_ring *rds_rings; |
454 | struct qlcnic_host_sds_ring *sds_rings; | |
af19b491 AKS |
455 | u32 state; |
456 | u16 context_id; | |
457 | u16 virt_port; | |
458 | ||
af19b491 AKS |
459 | }; |
460 | ||
461 | /* HW context creation */ | |
462 | ||
463 | #define QLCNIC_OS_CRB_RETRY_COUNT 4000 | |
464 | #define QLCNIC_CDRP_SIGNATURE_MAKE(pcifn, version) \ | |
465 | (((pcifn) & 0xff) | (((version) & 0xff) << 8) | (0xcafe << 16)) | |
466 | ||
467 | #define QLCNIC_CDRP_CMD_BIT 0x80000000 | |
468 | ||
469 | /* | |
470 | * All responses must have the QLCNIC_CDRP_CMD_BIT cleared | |
471 | * in the crb QLCNIC_CDRP_CRB_OFFSET. | |
472 | */ | |
473 | #define QLCNIC_CDRP_FORM_RSP(rsp) (rsp) | |
474 | #define QLCNIC_CDRP_IS_RSP(rsp) (((rsp) & QLCNIC_CDRP_CMD_BIT) == 0) | |
475 | ||
476 | #define QLCNIC_CDRP_RSP_OK 0x00000001 | |
477 | #define QLCNIC_CDRP_RSP_FAIL 0x00000002 | |
478 | #define QLCNIC_CDRP_RSP_TIMEOUT 0x00000003 | |
479 | ||
480 | /* | |
481 | * All commands must have the QLCNIC_CDRP_CMD_BIT set in | |
482 | * the crb QLCNIC_CDRP_CRB_OFFSET. | |
483 | */ | |
484 | #define QLCNIC_CDRP_FORM_CMD(cmd) (QLCNIC_CDRP_CMD_BIT | (cmd)) | |
485 | #define QLCNIC_CDRP_IS_CMD(cmd) (((cmd) & QLCNIC_CDRP_CMD_BIT) != 0) | |
486 | ||
487 | #define QLCNIC_CDRP_CMD_SUBMIT_CAPABILITIES 0x00000001 | |
488 | #define QLCNIC_CDRP_CMD_READ_MAX_RDS_PER_CTX 0x00000002 | |
489 | #define QLCNIC_CDRP_CMD_READ_MAX_SDS_PER_CTX 0x00000003 | |
490 | #define QLCNIC_CDRP_CMD_READ_MAX_RULES_PER_CTX 0x00000004 | |
491 | #define QLCNIC_CDRP_CMD_READ_MAX_RX_CTX 0x00000005 | |
492 | #define QLCNIC_CDRP_CMD_READ_MAX_TX_CTX 0x00000006 | |
493 | #define QLCNIC_CDRP_CMD_CREATE_RX_CTX 0x00000007 | |
494 | #define QLCNIC_CDRP_CMD_DESTROY_RX_CTX 0x00000008 | |
495 | #define QLCNIC_CDRP_CMD_CREATE_TX_CTX 0x00000009 | |
496 | #define QLCNIC_CDRP_CMD_DESTROY_TX_CTX 0x0000000a | |
7777de9a | 497 | #define QLCNIC_CDRP_CMD_INTRPT_TEST 0x00000011 |
af19b491 AKS |
498 | #define QLCNIC_CDRP_CMD_SET_MTU 0x00000012 |
499 | #define QLCNIC_CDRP_CMD_READ_PHY 0x00000013 | |
500 | #define QLCNIC_CDRP_CMD_WRITE_PHY 0x00000014 | |
501 | #define QLCNIC_CDRP_CMD_READ_HW_REG 0x00000015 | |
502 | #define QLCNIC_CDRP_CMD_GET_FLOW_CTL 0x00000016 | |
503 | #define QLCNIC_CDRP_CMD_SET_FLOW_CTL 0x00000017 | |
504 | #define QLCNIC_CDRP_CMD_READ_MAX_MTU 0x00000018 | |
505 | #define QLCNIC_CDRP_CMD_READ_MAX_LRO 0x00000019 | |
2e9d722d AC |
506 | #define QLCNIC_CDRP_CMD_MAC_ADDRESS 0x0000001f |
507 | ||
508 | #define QLCNIC_CDRP_CMD_GET_PCI_INFO 0x00000020 | |
509 | #define QLCNIC_CDRP_CMD_GET_NIC_INFO 0x00000021 | |
510 | #define QLCNIC_CDRP_CMD_SET_NIC_INFO 0x00000022 | |
2e9d722d AC |
511 | #define QLCNIC_CDRP_CMD_GET_ESWITCH_CAPABILITY 0x00000024 |
512 | #define QLCNIC_CDRP_CMD_TOGGLE_ESWITCH 0x00000025 | |
513 | #define QLCNIC_CDRP_CMD_GET_ESWITCH_STATUS 0x00000026 | |
514 | #define QLCNIC_CDRP_CMD_SET_PORTMIRRORING 0x00000027 | |
515 | #define QLCNIC_CDRP_CMD_CONFIGURE_ESWITCH 0x00000028 | |
4e8acb01 | 516 | #define QLCNIC_CDRP_CMD_GET_ESWITCH_PORT_CONFIG 0x00000029 |
b6021212 | 517 | #define QLCNIC_CDRP_CMD_GET_ESWITCH_STATS 0x0000002a |
7e610caa | 518 | #define QLCNIC_CDRP_CMD_CONFIG_PORT 0x0000002E |
18f2f616 AC |
519 | #define QLCNIC_CDRP_CMD_TEMP_SIZE 0x0000002f |
520 | #define QLCNIC_CDRP_CMD_GET_TEMP_HDR 0x00000030 | |
54a8997c | 521 | #define QLCNIC_CDRP_CMD_GET_MAC_STATS 0x00000037 |
af19b491 AKS |
522 | |
523 | #define QLCNIC_RCODE_SUCCESS 0 | |
e42ede22 | 524 | #define QLCNIC_RCODE_INVALID_ARGS 6 |
7e610caa | 525 | #define QLCNIC_RCODE_NOT_SUPPORTED 9 |
e42ede22 JK |
526 | #define QLCNIC_RCODE_NOT_PERMITTED 10 |
527 | #define QLCNIC_RCODE_NOT_IMPL 15 | |
528 | #define QLCNIC_RCODE_INVALID 16 | |
af19b491 AKS |
529 | #define QLCNIC_RCODE_TIMEOUT 17 |
530 | #define QLCNIC_DESTROY_CTX_RESET 0 | |
531 | ||
532 | /* | |
533 | * Capabilities Announced | |
534 | */ | |
535 | #define QLCNIC_CAP0_LEGACY_CONTEXT (1) | |
536 | #define QLCNIC_CAP0_LEGACY_MN (1 << 2) | |
537 | #define QLCNIC_CAP0_LSO (1 << 6) | |
538 | #define QLCNIC_CAP0_JUMBO_CONTIGUOUS (1 << 7) | |
539 | #define QLCNIC_CAP0_LRO_CONTIGUOUS (1 << 8) | |
8f891387 | 540 | #define QLCNIC_CAP0_VALIDOFF (1 << 11) |
cae82d49 | 541 | #define QLCNIC_CAP0_LRO_MSS (1 << 21) |
af19b491 AKS |
542 | |
543 | /* | |
544 | * Context state | |
545 | */ | |
d626ad4d | 546 | #define QLCNIC_HOST_CTX_STATE_FREED 0 |
af19b491 AKS |
547 | #define QLCNIC_HOST_CTX_STATE_ACTIVE 2 |
548 | ||
549 | /* | |
550 | * Rx context | |
551 | */ | |
552 | ||
553 | struct qlcnic_hostrq_sds_ring { | |
554 | __le64 host_phys_addr; /* Ring base addr */ | |
555 | __le32 ring_size; /* Ring entries */ | |
556 | __le16 msi_index; | |
557 | __le16 rsvd; /* Padding */ | |
b1fc6d3c | 558 | } __packed; |
af19b491 AKS |
559 | |
560 | struct qlcnic_hostrq_rds_ring { | |
561 | __le64 host_phys_addr; /* Ring base addr */ | |
562 | __le64 buff_size; /* Packet buffer size */ | |
563 | __le32 ring_size; /* Ring entries */ | |
564 | __le32 ring_kind; /* Class of ring */ | |
b1fc6d3c | 565 | } __packed; |
af19b491 AKS |
566 | |
567 | struct qlcnic_hostrq_rx_ctx { | |
568 | __le64 host_rsp_dma_addr; /* Response dma'd here */ | |
569 | __le32 capabilities[4]; /* Flag bit vector */ | |
570 | __le32 host_int_crb_mode; /* Interrupt crb usage */ | |
571 | __le32 host_rds_crb_mode; /* RDS crb usage */ | |
572 | /* These ring offsets are relative to data[0] below */ | |
573 | __le32 rds_ring_offset; /* Offset to RDS config */ | |
574 | __le32 sds_ring_offset; /* Offset to SDS config */ | |
575 | __le16 num_rds_rings; /* Count of RDS rings */ | |
576 | __le16 num_sds_rings; /* Count of SDS rings */ | |
8f891387 | 577 | __le16 valid_field_offset; |
578 | u8 txrx_sds_binding; | |
579 | u8 msix_handler; | |
580 | u8 reserved[128]; /* reserve space for future expansion*/ | |
af19b491 AKS |
581 | /* MUST BE 64-bit aligned. |
582 | The following is packed: | |
583 | - N hostrq_rds_rings | |
584 | - N hostrq_sds_rings */ | |
585 | char data[0]; | |
b1fc6d3c | 586 | } __packed; |
af19b491 AKS |
587 | |
588 | struct qlcnic_cardrsp_rds_ring{ | |
589 | __le32 host_producer_crb; /* Crb to use */ | |
590 | __le32 rsvd1; /* Padding */ | |
b1fc6d3c | 591 | } __packed; |
af19b491 AKS |
592 | |
593 | struct qlcnic_cardrsp_sds_ring { | |
594 | __le32 host_consumer_crb; /* Crb to use */ | |
595 | __le32 interrupt_crb; /* Crb to use */ | |
b1fc6d3c | 596 | } __packed; |
af19b491 AKS |
597 | |
598 | struct qlcnic_cardrsp_rx_ctx { | |
599 | /* These ring offsets are relative to data[0] below */ | |
600 | __le32 rds_ring_offset; /* Offset to RDS config */ | |
601 | __le32 sds_ring_offset; /* Offset to SDS config */ | |
602 | __le32 host_ctx_state; /* Starting State */ | |
603 | __le32 num_fn_per_port; /* How many PCI fn share the port */ | |
604 | __le16 num_rds_rings; /* Count of RDS rings */ | |
605 | __le16 num_sds_rings; /* Count of SDS rings */ | |
606 | __le16 context_id; /* Handle for context */ | |
607 | u8 phys_port; /* Physical id of port */ | |
608 | u8 virt_port; /* Virtual/Logical id of port */ | |
609 | u8 reserved[128]; /* save space for future expansion */ | |
610 | /* MUST BE 64-bit aligned. | |
611 | The following is packed: | |
612 | - N cardrsp_rds_rings | |
613 | - N cardrs_sds_rings */ | |
614 | char data[0]; | |
b1fc6d3c | 615 | } __packed; |
af19b491 AKS |
616 | |
617 | #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \ | |
618 | (sizeof(HOSTRQ_RX) + \ | |
619 | (rds_rings)*(sizeof(struct qlcnic_hostrq_rds_ring)) + \ | |
620 | (sds_rings)*(sizeof(struct qlcnic_hostrq_sds_ring))) | |
621 | ||
622 | #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \ | |
623 | (sizeof(CARDRSP_RX) + \ | |
624 | (rds_rings)*(sizeof(struct qlcnic_cardrsp_rds_ring)) + \ | |
625 | (sds_rings)*(sizeof(struct qlcnic_cardrsp_sds_ring))) | |
626 | ||
627 | /* | |
628 | * Tx context | |
629 | */ | |
630 | ||
631 | struct qlcnic_hostrq_cds_ring { | |
632 | __le64 host_phys_addr; /* Ring base addr */ | |
633 | __le32 ring_size; /* Ring entries */ | |
634 | __le32 rsvd; /* Padding */ | |
b1fc6d3c | 635 | } __packed; |
af19b491 AKS |
636 | |
637 | struct qlcnic_hostrq_tx_ctx { | |
638 | __le64 host_rsp_dma_addr; /* Response dma'd here */ | |
639 | __le64 cmd_cons_dma_addr; /* */ | |
640 | __le64 dummy_dma_addr; /* */ | |
641 | __le32 capabilities[4]; /* Flag bit vector */ | |
642 | __le32 host_int_crb_mode; /* Interrupt crb usage */ | |
643 | __le32 rsvd1; /* Padding */ | |
644 | __le16 rsvd2; /* Padding */ | |
645 | __le16 interrupt_ctl; | |
646 | __le16 msi_index; | |
647 | __le16 rsvd3; /* Padding */ | |
648 | struct qlcnic_hostrq_cds_ring cds_ring; /* Desc of cds ring */ | |
649 | u8 reserved[128]; /* future expansion */ | |
b1fc6d3c | 650 | } __packed; |
af19b491 AKS |
651 | |
652 | struct qlcnic_cardrsp_cds_ring { | |
653 | __le32 host_producer_crb; /* Crb to use */ | |
654 | __le32 interrupt_crb; /* Crb to use */ | |
b1fc6d3c | 655 | } __packed; |
af19b491 AKS |
656 | |
657 | struct qlcnic_cardrsp_tx_ctx { | |
658 | __le32 host_ctx_state; /* Starting state */ | |
659 | __le16 context_id; /* Handle for context */ | |
660 | u8 phys_port; /* Physical id of port */ | |
661 | u8 virt_port; /* Virtual/Logical id of port */ | |
662 | struct qlcnic_cardrsp_cds_ring cds_ring; /* Card cds settings */ | |
663 | u8 reserved[128]; /* future expansion */ | |
b1fc6d3c | 664 | } __packed; |
af19b491 AKS |
665 | |
666 | #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX)) | |
667 | #define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX)) | |
668 | ||
669 | /* CRB */ | |
670 | ||
671 | #define QLCNIC_HOST_RDS_CRB_MODE_UNIQUE 0 | |
672 | #define QLCNIC_HOST_RDS_CRB_MODE_SHARED 1 | |
673 | #define QLCNIC_HOST_RDS_CRB_MODE_CUSTOM 2 | |
674 | #define QLCNIC_HOST_RDS_CRB_MODE_MAX 3 | |
675 | ||
676 | #define QLCNIC_HOST_INT_CRB_MODE_UNIQUE 0 | |
677 | #define QLCNIC_HOST_INT_CRB_MODE_SHARED 1 | |
678 | #define QLCNIC_HOST_INT_CRB_MODE_NORX 2 | |
679 | #define QLCNIC_HOST_INT_CRB_MODE_NOTX 3 | |
680 | #define QLCNIC_HOST_INT_CRB_MODE_NORXTX 4 | |
681 | ||
682 | ||
683 | /* MAC */ | |
684 | ||
ff1b1bf8 | 685 | #define MC_COUNT_P3P 38 |
af19b491 AKS |
686 | |
687 | #define QLCNIC_MAC_NOOP 0 | |
688 | #define QLCNIC_MAC_ADD 1 | |
689 | #define QLCNIC_MAC_DEL 2 | |
03c5d770 AKS |
690 | #define QLCNIC_MAC_VLAN_ADD 3 |
691 | #define QLCNIC_MAC_VLAN_DEL 4 | |
af19b491 AKS |
692 | |
693 | struct qlcnic_mac_list_s { | |
694 | struct list_head list; | |
695 | uint8_t mac_addr[ETH_ALEN+2]; | |
696 | }; | |
697 | ||
af19b491 AKS |
698 | #define QLCNIC_HOST_REQUEST 0x13 |
699 | #define QLCNIC_REQUEST 0x14 | |
700 | ||
701 | #define QLCNIC_MAC_EVENT 0x1 | |
702 | ||
703 | #define QLCNIC_IP_UP 2 | |
704 | #define QLCNIC_IP_DOWN 3 | |
705 | ||
22c8c934 | 706 | #define QLCNIC_ILB_MODE 0x1 |
e1428d26 | 707 | #define QLCNIC_ELB_MODE 0x2 |
22c8c934 SC |
708 | |
709 | #define QLCNIC_LINKEVENT 0x1 | |
710 | #define QLCNIC_LB_RESPONSE 0x2 | |
711 | #define QLCNIC_IS_LB_CONFIGURED(VAL) \ | |
712 | (VAL == (QLCNIC_LINKEVENT | QLCNIC_LB_RESPONSE)) | |
713 | ||
af19b491 AKS |
714 | /* |
715 | * Driver --> Firmware | |
716 | */ | |
b1fc6d3c AC |
717 | #define QLCNIC_H2C_OPCODE_CONFIG_RSS 0x1 |
718 | #define QLCNIC_H2C_OPCODE_CONFIG_INTR_COALESCE 0x3 | |
719 | #define QLCNIC_H2C_OPCODE_CONFIG_LED 0x4 | |
720 | #define QLCNIC_H2C_OPCODE_LRO_REQUEST 0x7 | |
721 | #define QLCNIC_H2C_OPCODE_SET_MAC_RECEIVE_MODE 0xc | |
722 | #define QLCNIC_H2C_OPCODE_CONFIG_IPADDR 0x12 | |
22c8c934 | 723 | |
b1fc6d3c AC |
724 | #define QLCNIC_H2C_OPCODE_GET_LINKEVENT 0x15 |
725 | #define QLCNIC_H2C_OPCODE_CONFIG_BRIDGING 0x17 | |
726 | #define QLCNIC_H2C_OPCODE_CONFIG_HW_LRO 0x18 | |
22c8c934 SC |
727 | #define QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK 0x13 |
728 | ||
af19b491 AKS |
729 | /* |
730 | * Firmware --> Driver | |
731 | */ | |
732 | ||
22c8c934 | 733 | #define QLCNIC_C2H_OPCODE_CONFIG_LOOPBACK 0x8f |
af19b491 | 734 | #define QLCNIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE 141 |
af19b491 AKS |
735 | |
736 | #define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */ | |
737 | #define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */ | |
738 | #define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */ | |
739 | ||
740 | #define QLCNIC_LRO_REQUEST_CLEANUP 4 | |
741 | ||
742 | /* Capabilites received */ | |
ac8d0c4f AC |
743 | #define QLCNIC_FW_CAPABILITY_TSO BIT_1 |
744 | #define QLCNIC_FW_CAPABILITY_BDG BIT_8 | |
745 | #define QLCNIC_FW_CAPABILITY_FVLANTX BIT_9 | |
746 | #define QLCNIC_FW_CAPABILITY_HW_LRO BIT_10 | |
fef0c060 | 747 | #define QLCNIC_FW_CAPABILITY_MULTI_LOOPBACK BIT_27 |
cae82d49 RB |
748 | #define QLCNIC_FW_CAPABILITY_MORE_CAPS BIT_31 |
749 | ||
750 | #define QLCNIC_FW_CAPABILITY_2_LRO_MAX_TCP_SEG BIT_2 | |
af19b491 AKS |
751 | |
752 | /* module types */ | |
753 | #define LINKEVENT_MODULE_NOT_PRESENT 1 | |
754 | #define LINKEVENT_MODULE_OPTICAL_UNKNOWN 2 | |
755 | #define LINKEVENT_MODULE_OPTICAL_SRLR 3 | |
756 | #define LINKEVENT_MODULE_OPTICAL_LRM 4 | |
757 | #define LINKEVENT_MODULE_OPTICAL_SFP_1G 5 | |
758 | #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE 6 | |
759 | #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN 7 | |
760 | #define LINKEVENT_MODULE_TWINAX 8 | |
761 | ||
762 | #define LINKSPEED_10GBPS 10000 | |
763 | #define LINKSPEED_1GBPS 1000 | |
764 | #define LINKSPEED_100MBPS 100 | |
765 | #define LINKSPEED_10MBPS 10 | |
766 | ||
767 | #define LINKSPEED_ENCODED_10MBPS 0 | |
768 | #define LINKSPEED_ENCODED_100MBPS 1 | |
769 | #define LINKSPEED_ENCODED_1GBPS 2 | |
770 | ||
771 | #define LINKEVENT_AUTONEG_DISABLED 0 | |
772 | #define LINKEVENT_AUTONEG_ENABLED 1 | |
773 | ||
774 | #define LINKEVENT_HALF_DUPLEX 0 | |
775 | #define LINKEVENT_FULL_DUPLEX 1 | |
776 | ||
777 | #define LINKEVENT_LINKSPEED_MBPS 0 | |
778 | #define LINKEVENT_LINKSPEED_ENCODED 1 | |
779 | ||
af19b491 AKS |
780 | /* firmware response header: |
781 | * 63:58 - message type | |
782 | * 57:56 - owner | |
783 | * 55:53 - desc count | |
784 | * 52:48 - reserved | |
785 | * 47:40 - completion id | |
786 | * 39:32 - opcode | |
787 | * 31:16 - error code | |
788 | * 15:00 - reserved | |
789 | */ | |
790 | #define qlcnic_get_nic_msg_opcode(msg_hdr) \ | |
791 | ((msg_hdr >> 32) & 0xFF) | |
792 | ||
793 | struct qlcnic_fw_msg { | |
794 | union { | |
795 | struct { | |
796 | u64 hdr; | |
797 | u64 body[7]; | |
798 | }; | |
799 | u64 words[8]; | |
800 | }; | |
801 | }; | |
802 | ||
803 | struct qlcnic_nic_req { | |
804 | __le64 qhdr; | |
805 | __le64 req_hdr; | |
806 | __le64 words[6]; | |
b1fc6d3c | 807 | } __packed; |
af19b491 AKS |
808 | |
809 | struct qlcnic_mac_req { | |
810 | u8 op; | |
811 | u8 tag; | |
812 | u8 mac_addr[6]; | |
813 | }; | |
814 | ||
7e56cac4 SC |
815 | struct qlcnic_vlan_req { |
816 | __le16 vlan_id; | |
817 | __le16 rsvd[3]; | |
b1fc6d3c | 818 | } __packed; |
7e56cac4 | 819 | |
b501595c SC |
820 | struct qlcnic_ipaddr { |
821 | __be32 ipv4; | |
822 | __be32 ipv6[4]; | |
823 | }; | |
824 | ||
af19b491 AKS |
825 | #define QLCNIC_MSI_ENABLED 0x02 |
826 | #define QLCNIC_MSIX_ENABLED 0x04 | |
827 | #define QLCNIC_LRO_ENABLED 0x08 | |
24763d80 | 828 | #define QLCNIC_LRO_DISABLED 0x00 |
af19b491 AKS |
829 | #define QLCNIC_BRIDGE_ENABLED 0X10 |
830 | #define QLCNIC_DIAG_ENABLED 0x20 | |
0e33c664 | 831 | #define QLCNIC_ESWITCH_ENABLED 0x40 |
0866d96d | 832 | #define QLCNIC_ADAPTER_INITIALIZED 0x80 |
8cf61f89 | 833 | #define QLCNIC_TAGGING_ENABLED 0x100 |
fe4d434d | 834 | #define QLCNIC_MACSPOOF 0x200 |
7373373d | 835 | #define QLCNIC_MAC_OVERRIDE_DISABLED 0x400 |
ee07c1a7 | 836 | #define QLCNIC_PROMISC_DISABLED 0x800 |
b0044bcf | 837 | #define QLCNIC_NEED_FLR 0x1000 |
602ca6f0 | 838 | #define QLCNIC_FW_RESET_OWNER 0x2000 |
032a13c7 | 839 | #define QLCNIC_FW_HANG 0x4000 |
cae82d49 | 840 | #define QLCNIC_FW_LRO_MSS_CAP 0x8000 |
af19b491 AKS |
841 | #define QLCNIC_IS_MSI_FAMILY(adapter) \ |
842 | ((adapter)->flags & (QLCNIC_MSI_ENABLED | QLCNIC_MSIX_ENABLED)) | |
843 | ||
f94bc1e7 | 844 | #define QLCNIC_DEF_NUM_STS_DESC_RINGS 4 |
af19b491 AKS |
845 | #define QLCNIC_MSIX_TBL_SPACE 8192 |
846 | #define QLCNIC_PCI_REG_MSIX_TBL 0x44 | |
2e9d722d | 847 | #define QLCNIC_MSIX_TBL_PGSIZE 4096 |
af19b491 AKS |
848 | |
849 | #define QLCNIC_NETDEV_WEIGHT 128 | |
850 | #define QLCNIC_ADAPTER_UP_MAGIC 777 | |
851 | ||
852 | #define __QLCNIC_FW_ATTACHED 0 | |
853 | #define __QLCNIC_DEV_UP 1 | |
854 | #define __QLCNIC_RESETTING 2 | |
855 | #define __QLCNIC_START_FW 4 | |
451724c8 | 856 | #define __QLCNIC_AER 5 |
89b4208e | 857 | #define __QLCNIC_DIAG_RES_ALLOC 6 |
728a98b8 | 858 | #define __QLCNIC_LED_ENABLE 7 |
af19b491 | 859 | |
7eb9855d | 860 | #define QLCNIC_INTERRUPT_TEST 1 |
cdaff185 | 861 | #define QLCNIC_LOOPBACK_TEST 2 |
c75822a3 | 862 | #define QLCNIC_LED_TEST 3 |
7eb9855d | 863 | |
b5e5492c | 864 | #define QLCNIC_FILTER_AGE 80 |
e5edb7b1 | 865 | #define QLCNIC_READD_AGE 20 |
b5e5492c AKS |
866 | #define QLCNIC_LB_MAX_FILTERS 64 |
867 | ||
fef0c060 AKS |
868 | /* QLCNIC Driver Error Code */ |
869 | #define QLCNIC_FW_NOT_RESPOND 51 | |
870 | #define QLCNIC_TEST_IN_PROGRESS 52 | |
871 | #define QLCNIC_UNDEFINED_ERROR 53 | |
872 | #define QLCNIC_LB_CABLE_NOT_CONN 54 | |
873 | ||
b5e5492c AKS |
874 | struct qlcnic_filter { |
875 | struct hlist_node fnode; | |
876 | u8 faddr[ETH_ALEN]; | |
7e56cac4 | 877 | __le16 vlan_id; |
b5e5492c AKS |
878 | unsigned long ftime; |
879 | }; | |
880 | ||
881 | struct qlcnic_filter_hash { | |
882 | struct hlist_head *fhead; | |
883 | u8 fnum; | |
884 | u8 fmax; | |
885 | }; | |
886 | ||
af19b491 | 887 | struct qlcnic_adapter { |
b1fc6d3c AC |
888 | struct qlcnic_hardware_context *ahw; |
889 | struct qlcnic_recv_context *recv_ctx; | |
890 | struct qlcnic_host_tx_ring *tx_ring; | |
af19b491 AKS |
891 | struct net_device *netdev; |
892 | struct pci_dev *pdev; | |
af19b491 | 893 | |
b1fc6d3c AC |
894 | unsigned long state; |
895 | u32 flags; | |
af19b491 AKS |
896 | |
897 | u16 num_txd; | |
898 | u16 num_rxd; | |
899 | u16 num_jumbo_rxd; | |
90d19005 SC |
900 | u16 max_rxd; |
901 | u16 max_jumbo_rxd; | |
af19b491 AKS |
902 | |
903 | u8 max_rds_rings; | |
904 | u8 max_sds_rings; | |
af19b491 | 905 | u8 msix_supported; |
af19b491 AKS |
906 | u8 portnum; |
907 | u8 physical_port; | |
68bf1c68 | 908 | u8 reset_context; |
af19b491 AKS |
909 | |
910 | u8 mc_enabled; | |
911 | u8 max_mc_count; | |
af19b491 AKS |
912 | u8 fw_wait_cnt; |
913 | u8 fw_fail_cnt; | |
914 | u8 tx_timeo_cnt; | |
915 | u8 need_fw_reset; | |
916 | ||
917 | u8 has_link_events; | |
918 | u8 fw_type; | |
919 | u16 tx_context_id; | |
af19b491 AKS |
920 | u16 is_up; |
921 | ||
922 | u16 link_speed; | |
923 | u16 link_duplex; | |
924 | u16 link_autoneg; | |
925 | u16 module_type; | |
926 | ||
2e9d722d AC |
927 | u16 op_mode; |
928 | u16 switch_mode; | |
929 | u16 max_tx_ques; | |
930 | u16 max_rx_ques; | |
2e9d722d | 931 | u16 max_mtu; |
8cf61f89 | 932 | u16 pvid; |
2e9d722d AC |
933 | |
934 | u32 fw_hal_version; | |
af19b491 | 935 | u32 capabilities; |
af19b491 AKS |
936 | u32 irq; |
937 | u32 temp; | |
938 | ||
939 | u32 int_vec_bit; | |
4e70812b | 940 | u32 heartbeat; |
af19b491 | 941 | |
2e9d722d | 942 | u8 max_mac_filters; |
af19b491 | 943 | u8 dev_state; |
7eb9855d | 944 | u8 diag_test; |
fef0c060 | 945 | char diag_cnt; |
aa5e18c0 SC |
946 | u8 reset_ack_timeo; |
947 | u8 dev_init_timeo; | |
65b5b420 | 948 | u16 msg_enable; |
af19b491 AKS |
949 | |
950 | u8 mac_addr[ETH_ALEN]; | |
951 | ||
6df900e9 | 952 | u64 dev_rst_time; |
e5dcf6dc | 953 | u8 mac_learn; |
b9796a14 | 954 | unsigned long vlans[BITS_TO_LONGS(VLAN_N_VID)]; |
6df900e9 | 955 | |
346fe763 | 956 | struct qlcnic_npar_info *npars; |
2e9d722d AC |
957 | struct qlcnic_eswitch *eswitch; |
958 | struct qlcnic_nic_template *nic_ops; | |
959 | ||
af19b491 | 960 | struct qlcnic_adapter_stats stats; |
b1fc6d3c | 961 | struct list_head mac_list; |
af19b491 AKS |
962 | |
963 | void __iomem *tgt_mask_reg; | |
964 | void __iomem *tgt_status_reg; | |
965 | void __iomem *crb_int_state_reg; | |
966 | void __iomem *isr_int_vec; | |
967 | ||
f94bc1e7 | 968 | struct msix_entry *msix_entries; |
af19b491 AKS |
969 | |
970 | struct delayed_work fw_work; | |
971 | ||
af19b491 | 972 | |
b5e5492c AKS |
973 | struct qlcnic_filter_hash fhash; |
974 | ||
b1fc6d3c AC |
975 | spinlock_t tx_clean_lock; |
976 | spinlock_t mac_learn_lock; | |
63507592 | 977 | u32 file_prd_off; /*File fw product offset*/ |
af19b491 AKS |
978 | u32 fw_version; |
979 | const struct firmware *fw; | |
980 | }; | |
981 | ||
63507592 | 982 | struct qlcnic_info_le { |
2e9d722d | 983 | __le16 pci_func; |
63507592 | 984 | __le16 op_mode; /* 1 = Priv, 2 = NP, 3 = NP passthru */ |
2e9d722d | 985 | __le16 phys_port; |
63507592 | 986 | __le16 switch_mode; /* 0 = disabled, 1 = int, 2 = ext */ |
2e9d722d AC |
987 | |
988 | __le32 capabilities; | |
989 | u8 max_mac_filters; | |
990 | u8 reserved1; | |
991 | __le16 max_mtu; | |
992 | ||
993 | __le16 max_tx_ques; | |
994 | __le16 max_rx_ques; | |
995 | __le16 min_tx_bw; | |
996 | __le16 max_tx_bw; | |
997 | u8 reserved2[104]; | |
b1fc6d3c | 998 | } __packed; |
2e9d722d | 999 | |
63507592 SS |
1000 | struct qlcnic_info { |
1001 | u16 pci_func; | |
1002 | u16 op_mode; | |
1003 | u16 phys_port; | |
1004 | u16 switch_mode; | |
1005 | u32 capabilities; | |
1006 | u8 max_mac_filters; | |
1007 | u8 reserved1; | |
1008 | u16 max_mtu; | |
1009 | u16 max_tx_ques; | |
1010 | u16 max_rx_ques; | |
1011 | u16 min_tx_bw; | |
1012 | u16 max_tx_bw; | |
1013 | }; | |
2e9d722d | 1014 | |
63507592 SS |
1015 | struct qlcnic_pci_info_le { |
1016 | __le16 id; /* pci function id */ | |
1017 | __le16 active; /* 1 = Enabled */ | |
1018 | __le16 type; /* 1 = NIC, 2 = FCoE, 3 = iSCSI */ | |
1019 | __le16 default_port; /* default port number */ | |
1020 | ||
1021 | __le16 tx_min_bw; /* Multiple of 100mbpc */ | |
2e9d722d AC |
1022 | __le16 tx_max_bw; |
1023 | __le16 reserved1[2]; | |
1024 | ||
1025 | u8 mac[ETH_ALEN]; | |
1026 | u8 reserved2[106]; | |
b1fc6d3c | 1027 | } __packed; |
2e9d722d | 1028 | |
63507592 SS |
1029 | struct qlcnic_pci_info { |
1030 | u16 id; | |
1031 | u16 active; | |
1032 | u16 type; | |
1033 | u16 default_port; | |
1034 | u16 tx_min_bw; | |
1035 | u16 tx_max_bw; | |
1036 | u8 mac[ETH_ALEN]; | |
1037 | }; | |
1038 | ||
346fe763 | 1039 | struct qlcnic_npar_info { |
4e8acb01 | 1040 | u16 pvid; |
cea8975e AC |
1041 | u16 min_bw; |
1042 | u16 max_bw; | |
346fe763 RB |
1043 | u8 phy_port; |
1044 | u8 type; | |
1045 | u8 active; | |
1046 | u8 enable_pm; | |
1047 | u8 dest_npar; | |
346fe763 | 1048 | u8 discard_tagged; |
7373373d | 1049 | u8 mac_override; |
4e8acb01 RB |
1050 | u8 mac_anti_spoof; |
1051 | u8 promisc_mode; | |
1052 | u8 offload_flags; | |
346fe763 | 1053 | }; |
4e8acb01 | 1054 | |
2e9d722d AC |
1055 | struct qlcnic_eswitch { |
1056 | u8 port; | |
1057 | u8 active_vports; | |
1058 | u8 active_vlans; | |
1059 | u8 active_ucast_filters; | |
1060 | u8 max_ucast_filters; | |
1061 | u8 max_active_vlans; | |
1062 | ||
1063 | u32 flags; | |
1064 | #define QLCNIC_SWITCH_ENABLE BIT_1 | |
1065 | #define QLCNIC_SWITCH_VLAN_FILTERING BIT_2 | |
1066 | #define QLCNIC_SWITCH_PROMISC_MODE BIT_3 | |
1067 | #define QLCNIC_SWITCH_PORT_MIRRORING BIT_4 | |
1068 | }; | |
1069 | ||
346fe763 RB |
1070 | |
1071 | /* Return codes for Error handling */ | |
1072 | #define QL_STATUS_INVALID_PARAM -1 | |
1073 | ||
2abea2f0 | 1074 | #define MAX_BW 100 /* % of link speed */ |
346fe763 RB |
1075 | #define MAX_VLAN_ID 4095 |
1076 | #define MIN_VLAN_ID 2 | |
346fe763 RB |
1077 | #define DEFAULT_MAC_LEARN 1 |
1078 | ||
0184bbba | 1079 | #define IS_VALID_VLAN(vlan) (vlan >= MIN_VLAN_ID && vlan < MAX_VLAN_ID) |
2abea2f0 | 1080 | #define IS_VALID_BW(bw) (bw <= MAX_BW) |
346fe763 RB |
1081 | |
1082 | struct qlcnic_pci_func_cfg { | |
1083 | u16 func_type; | |
1084 | u16 min_bw; | |
1085 | u16 max_bw; | |
1086 | u16 port_num; | |
1087 | u8 pci_func; | |
1088 | u8 func_state; | |
1089 | u8 def_mac_addr[6]; | |
1090 | }; | |
1091 | ||
1092 | struct qlcnic_npar_func_cfg { | |
1093 | u32 fw_capab; | |
1094 | u16 port_num; | |
1095 | u16 min_bw; | |
1096 | u16 max_bw; | |
1097 | u16 max_tx_queues; | |
1098 | u16 max_rx_queues; | |
1099 | u8 pci_func; | |
1100 | u8 op_mode; | |
1101 | }; | |
1102 | ||
1103 | struct qlcnic_pm_func_cfg { | |
1104 | u8 pci_func; | |
1105 | u8 action; | |
1106 | u8 dest_npar; | |
1107 | u8 reserved[5]; | |
1108 | }; | |
1109 | ||
1110 | struct qlcnic_esw_func_cfg { | |
1111 | u16 vlan_id; | |
4e8acb01 RB |
1112 | u8 op_mode; |
1113 | u8 op_type; | |
346fe763 RB |
1114 | u8 pci_func; |
1115 | u8 host_vlan_tag; | |
1116 | u8 promisc_mode; | |
1117 | u8 discard_tagged; | |
7373373d | 1118 | u8 mac_override; |
4e8acb01 RB |
1119 | u8 mac_anti_spoof; |
1120 | u8 offload_flags; | |
1121 | u8 reserved[5]; | |
346fe763 RB |
1122 | }; |
1123 | ||
b6021212 AKS |
1124 | #define QLCNIC_STATS_VERSION 1 |
1125 | #define QLCNIC_STATS_PORT 1 | |
1126 | #define QLCNIC_STATS_ESWITCH 2 | |
1127 | #define QLCNIC_QUERY_RX_COUNTER 0 | |
1128 | #define QLCNIC_QUERY_TX_COUNTER 1 | |
54a8997c JK |
1129 | #define QLCNIC_STATS_NOT_AVAIL 0xffffffffffffffffULL |
1130 | #define QLCNIC_FILL_STATS(VAL1) \ | |
1131 | (((VAL1) == QLCNIC_STATS_NOT_AVAIL) ? 0 : VAL1) | |
1132 | #define QLCNIC_MAC_STATS 1 | |
1133 | #define QLCNIC_ESW_STATS 2 | |
ef182805 AKS |
1134 | |
1135 | #define QLCNIC_ADD_ESW_STATS(VAL1, VAL2)\ | |
1136 | do { \ | |
54a8997c JK |
1137 | if (((VAL1) == QLCNIC_STATS_NOT_AVAIL) && \ |
1138 | ((VAL2) != QLCNIC_STATS_NOT_AVAIL)) \ | |
ef182805 | 1139 | (VAL1) = (VAL2); \ |
54a8997c JK |
1140 | else if (((VAL1) != QLCNIC_STATS_NOT_AVAIL) && \ |
1141 | ((VAL2) != QLCNIC_STATS_NOT_AVAIL)) \ | |
ef182805 AKS |
1142 | (VAL1) += (VAL2); \ |
1143 | } while (0) | |
1144 | ||
63507592 | 1145 | struct qlcnic_mac_statistics_le { |
54a8997c JK |
1146 | __le64 mac_tx_frames; |
1147 | __le64 mac_tx_bytes; | |
1148 | __le64 mac_tx_mcast_pkts; | |
1149 | __le64 mac_tx_bcast_pkts; | |
1150 | __le64 mac_tx_pause_cnt; | |
1151 | __le64 mac_tx_ctrl_pkt; | |
1152 | __le64 mac_tx_lt_64b_pkts; | |
1153 | __le64 mac_tx_lt_127b_pkts; | |
1154 | __le64 mac_tx_lt_255b_pkts; | |
1155 | __le64 mac_tx_lt_511b_pkts; | |
1156 | __le64 mac_tx_lt_1023b_pkts; | |
1157 | __le64 mac_tx_lt_1518b_pkts; | |
1158 | __le64 mac_tx_gt_1518b_pkts; | |
1159 | __le64 rsvd1[3]; | |
1160 | ||
1161 | __le64 mac_rx_frames; | |
1162 | __le64 mac_rx_bytes; | |
1163 | __le64 mac_rx_mcast_pkts; | |
1164 | __le64 mac_rx_bcast_pkts; | |
1165 | __le64 mac_rx_pause_cnt; | |
1166 | __le64 mac_rx_ctrl_pkt; | |
1167 | __le64 mac_rx_lt_64b_pkts; | |
1168 | __le64 mac_rx_lt_127b_pkts; | |
1169 | __le64 mac_rx_lt_255b_pkts; | |
1170 | __le64 mac_rx_lt_511b_pkts; | |
1171 | __le64 mac_rx_lt_1023b_pkts; | |
1172 | __le64 mac_rx_lt_1518b_pkts; | |
1173 | __le64 mac_rx_gt_1518b_pkts; | |
1174 | __le64 rsvd2[3]; | |
1175 | ||
1176 | __le64 mac_rx_length_error; | |
1177 | __le64 mac_rx_length_small; | |
1178 | __le64 mac_rx_length_large; | |
1179 | __le64 mac_rx_jabber; | |
1180 | __le64 mac_rx_dropped; | |
1181 | __le64 mac_rx_crc_error; | |
1182 | __le64 mac_align_error; | |
1183 | } __packed; | |
1184 | ||
63507592 SS |
1185 | struct qlcnic_mac_statistics { |
1186 | u64 mac_tx_frames; | |
1187 | u64 mac_tx_bytes; | |
1188 | u64 mac_tx_mcast_pkts; | |
1189 | u64 mac_tx_bcast_pkts; | |
1190 | u64 mac_tx_pause_cnt; | |
1191 | u64 mac_tx_ctrl_pkt; | |
1192 | u64 mac_tx_lt_64b_pkts; | |
1193 | u64 mac_tx_lt_127b_pkts; | |
1194 | u64 mac_tx_lt_255b_pkts; | |
1195 | u64 mac_tx_lt_511b_pkts; | |
1196 | u64 mac_tx_lt_1023b_pkts; | |
1197 | u64 mac_tx_lt_1518b_pkts; | |
1198 | u64 mac_tx_gt_1518b_pkts; | |
1199 | u64 rsvd1[3]; | |
1200 | u64 mac_rx_frames; | |
1201 | u64 mac_rx_bytes; | |
1202 | u64 mac_rx_mcast_pkts; | |
1203 | u64 mac_rx_bcast_pkts; | |
1204 | u64 mac_rx_pause_cnt; | |
1205 | u64 mac_rx_ctrl_pkt; | |
1206 | u64 mac_rx_lt_64b_pkts; | |
1207 | u64 mac_rx_lt_127b_pkts; | |
1208 | u64 mac_rx_lt_255b_pkts; | |
1209 | u64 mac_rx_lt_511b_pkts; | |
1210 | u64 mac_rx_lt_1023b_pkts; | |
1211 | u64 mac_rx_lt_1518b_pkts; | |
1212 | u64 mac_rx_gt_1518b_pkts; | |
1213 | u64 rsvd2[3]; | |
1214 | u64 mac_rx_length_error; | |
1215 | u64 mac_rx_length_small; | |
1216 | u64 mac_rx_length_large; | |
1217 | u64 mac_rx_jabber; | |
1218 | u64 mac_rx_dropped; | |
1219 | u64 mac_rx_crc_error; | |
1220 | u64 mac_align_error; | |
1221 | }; | |
1222 | ||
1223 | struct qlcnic_esw_stats_le { | |
b6021212 AKS |
1224 | __le16 context_id; |
1225 | __le16 version; | |
1226 | __le16 size; | |
1227 | __le16 unused; | |
1228 | __le64 unicast_frames; | |
1229 | __le64 multicast_frames; | |
1230 | __le64 broadcast_frames; | |
1231 | __le64 dropped_frames; | |
1232 | __le64 errors; | |
1233 | __le64 local_frames; | |
1234 | __le64 numbytes; | |
1235 | __le64 rsvd[3]; | |
b1fc6d3c | 1236 | } __packed; |
b6021212 | 1237 | |
63507592 SS |
1238 | struct __qlcnic_esw_statistics { |
1239 | u16 context_id; | |
1240 | u16 version; | |
1241 | u16 size; | |
1242 | u16 unused; | |
1243 | u64 unicast_frames; | |
1244 | u64 multicast_frames; | |
1245 | u64 broadcast_frames; | |
1246 | u64 dropped_frames; | |
1247 | u64 errors; | |
1248 | u64 local_frames; | |
1249 | u64 numbytes; | |
1250 | u64 rsvd[3]; | |
1251 | }; | |
1252 | ||
b6021212 AKS |
1253 | struct qlcnic_esw_statistics { |
1254 | struct __qlcnic_esw_statistics rx; | |
1255 | struct __qlcnic_esw_statistics tx; | |
1256 | }; | |
1257 | ||
40522998 | 1258 | #define QLCNIC_DUMP_MASK_DEF 0x1f |
18f2f616 | 1259 | #define QLCNIC_FORCE_FW_DUMP_KEY 0xdeadfeed |
9d6a6440 AC |
1260 | #define QLCNIC_ENABLE_FW_DUMP 0xaddfeed |
1261 | #define QLCNIC_DISABLE_FW_DUMP 0xbadfeed | |
3d46512c | 1262 | #define QLCNIC_FORCE_FW_RESET 0xdeaddead |
b43e5ee7 SC |
1263 | #define QLCNIC_SET_QUIESCENT 0xadd00010 |
1264 | #define QLCNIC_RESET_QUIESCENT 0xadd00020 | |
18f2f616 | 1265 | |
7777de9a AC |
1266 | struct _cdrp_cmd { |
1267 | u32 cmd; | |
1268 | u32 arg1; | |
1269 | u32 arg2; | |
1270 | u32 arg3; | |
1271 | }; | |
1272 | ||
1273 | struct qlcnic_cmd_args { | |
1274 | struct _cdrp_cmd req; | |
1275 | struct _cdrp_cmd rsp; | |
1276 | }; | |
1277 | ||
18f2f616 | 1278 | int qlcnic_fw_cmd_get_minidump_temp(struct qlcnic_adapter *adapter); |
7e610caa | 1279 | int qlcnic_fw_cmd_set_port(struct qlcnic_adapter *adapter, u32 config); |
af19b491 AKS |
1280 | |
1281 | u32 qlcnic_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong off); | |
1282 | int qlcnic_hw_write_wx_2M(struct qlcnic_adapter *, ulong off, u32 data); | |
1283 | int qlcnic_pci_mem_write_2M(struct qlcnic_adapter *, u64 off, u64 data); | |
1284 | int qlcnic_pci_mem_read_2M(struct qlcnic_adapter *, u64 off, u64 *data); | |
897e8c7c DP |
1285 | void qlcnic_pci_camqm_read_2M(struct qlcnic_adapter *, u64, u64 *); |
1286 | void qlcnic_pci_camqm_write_2M(struct qlcnic_adapter *, u64, u64); | |
1287 | ||
1288 | #define ADDR_IN_RANGE(addr, low, high) \ | |
1289 | (((addr) < (high)) && ((addr) >= (low))) | |
af19b491 AKS |
1290 | |
1291 | #define QLCRD32(adapter, off) \ | |
1292 | (qlcnic_hw_read_wx_2M(adapter, off)) | |
1293 | #define QLCWR32(adapter, off, val) \ | |
1294 | (qlcnic_hw_write_wx_2M(adapter, off, val)) | |
1295 | ||
1296 | int qlcnic_pcie_sem_lock(struct qlcnic_adapter *, int, u32); | |
1297 | void qlcnic_pcie_sem_unlock(struct qlcnic_adapter *, int); | |
1298 | ||
1299 | #define qlcnic_rom_lock(a) \ | |
1300 | qlcnic_pcie_sem_lock((a), 2, QLCNIC_ROM_LOCK_ID) | |
1301 | #define qlcnic_rom_unlock(a) \ | |
1302 | qlcnic_pcie_sem_unlock((a), 2) | |
1303 | #define qlcnic_phy_lock(a) \ | |
1304 | qlcnic_pcie_sem_lock((a), 3, QLCNIC_PHY_LOCK_ID) | |
1305 | #define qlcnic_phy_unlock(a) \ | |
1306 | qlcnic_pcie_sem_unlock((a), 3) | |
1307 | #define qlcnic_api_lock(a) \ | |
1308 | qlcnic_pcie_sem_lock((a), 5, 0) | |
1309 | #define qlcnic_api_unlock(a) \ | |
1310 | qlcnic_pcie_sem_unlock((a), 5) | |
1311 | #define qlcnic_sw_lock(a) \ | |
1312 | qlcnic_pcie_sem_lock((a), 6, 0) | |
1313 | #define qlcnic_sw_unlock(a) \ | |
1314 | qlcnic_pcie_sem_unlock((a), 6) | |
1315 | #define crb_win_lock(a) \ | |
1316 | qlcnic_pcie_sem_lock((a), 7, QLCNIC_CRB_WIN_LOCK_ID) | |
1317 | #define crb_win_unlock(a) \ | |
1318 | qlcnic_pcie_sem_unlock((a), 7) | |
1319 | ||
728a98b8 SC |
1320 | #define __QLCNIC_MAX_LED_RATE 0xf |
1321 | #define __QLCNIC_MAX_LED_STATE 0x2 | |
1322 | ||
58634e74 SC |
1323 | #define MAX_CTL_CHECK 1000 |
1324 | ||
af19b491 AKS |
1325 | int qlcnic_get_board_info(struct qlcnic_adapter *adapter); |
1326 | int qlcnic_wol_supported(struct qlcnic_adapter *adapter); | |
897d3596 | 1327 | int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state, u32 rate); |
b5e5492c AKS |
1328 | void qlcnic_prune_lb_filters(struct qlcnic_adapter *adapter); |
1329 | void qlcnic_delete_lb_filters(struct qlcnic_adapter *adapter); | |
18f2f616 | 1330 | int qlcnic_dump_fw(struct qlcnic_adapter *); |
af19b491 AKS |
1331 | |
1332 | /* Functions from qlcnic_init.c */ | |
af19b491 AKS |
1333 | int qlcnic_load_firmware(struct qlcnic_adapter *adapter); |
1334 | int qlcnic_need_fw_reset(struct qlcnic_adapter *adapter); | |
1335 | void qlcnic_request_firmware(struct qlcnic_adapter *adapter); | |
1336 | void qlcnic_release_firmware(struct qlcnic_adapter *adapter); | |
1337 | int qlcnic_pinit_from_rom(struct qlcnic_adapter *adapter); | |
b3a24649 | 1338 | int qlcnic_setup_idc_param(struct qlcnic_adapter *adapter); |
8f891387 | 1339 | int qlcnic_check_flash_fw_ver(struct qlcnic_adapter *adapter); |
af19b491 | 1340 | |
18f2f616 | 1341 | int qlcnic_rom_fast_read(struct qlcnic_adapter *adapter, u32 addr, u32 *valp); |
af19b491 AKS |
1342 | int qlcnic_rom_fast_read_words(struct qlcnic_adapter *adapter, int addr, |
1343 | u8 *bytes, size_t size); | |
1344 | int qlcnic_alloc_sw_resources(struct qlcnic_adapter *adapter); | |
1345 | void qlcnic_free_sw_resources(struct qlcnic_adapter *adapter); | |
1346 | ||
1347 | void __iomem *qlcnic_get_ioaddr(struct qlcnic_adapter *, u32); | |
1348 | ||
1349 | int qlcnic_alloc_hw_resources(struct qlcnic_adapter *adapter); | |
1350 | void qlcnic_free_hw_resources(struct qlcnic_adapter *adapter); | |
1351 | ||
8a15ad1f AKS |
1352 | int qlcnic_fw_create_ctx(struct qlcnic_adapter *adapter); |
1353 | void qlcnic_fw_destroy_ctx(struct qlcnic_adapter *adapter); | |
1354 | ||
1355 | void qlcnic_reset_rx_buffers_list(struct qlcnic_adapter *adapter); | |
af19b491 AKS |
1356 | void qlcnic_release_rx_buffers(struct qlcnic_adapter *adapter); |
1357 | void qlcnic_release_tx_buffers(struct qlcnic_adapter *adapter); | |
1358 | ||
d4066833 | 1359 | int qlcnic_check_fw_status(struct qlcnic_adapter *adapter); |
af19b491 | 1360 | void qlcnic_watchdog_task(struct work_struct *work); |
b1fc6d3c | 1361 | void qlcnic_post_rx_buffers(struct qlcnic_adapter *adapter, |
af19b491 AKS |
1362 | struct qlcnic_host_rds_ring *rds_ring); |
1363 | int qlcnic_process_rcv_ring(struct qlcnic_host_sds_ring *sds_ring, int max); | |
1364 | void qlcnic_set_multi(struct net_device *netdev); | |
1365 | void qlcnic_free_mac_list(struct qlcnic_adapter *adapter); | |
1366 | int qlcnic_nic_set_promisc(struct qlcnic_adapter *adapter, u32); | |
1367 | int qlcnic_config_intr_coalesce(struct qlcnic_adapter *adapter); | |
1368 | int qlcnic_config_rss(struct qlcnic_adapter *adapter, int enable); | |
b501595c | 1369 | int qlcnic_config_ipaddr(struct qlcnic_adapter *adapter, __be32 ip, int cmd); |
af19b491 AKS |
1370 | int qlcnic_linkevent_request(struct qlcnic_adapter *adapter, int enable); |
1371 | void qlcnic_advert_link_change(struct qlcnic_adapter *adapter, int linkup); | |
1372 | ||
1373 | int qlcnic_fw_cmd_set_mtu(struct qlcnic_adapter *adapter, int mtu); | |
1374 | int qlcnic_change_mtu(struct net_device *netdev, int new_mtu); | |
c8f44aff MM |
1375 | netdev_features_t qlcnic_fix_features(struct net_device *netdev, |
1376 | netdev_features_t features); | |
1377 | int qlcnic_set_features(struct net_device *netdev, netdev_features_t features); | |
af19b491 | 1378 | int qlcnic_config_hw_lro(struct qlcnic_adapter *adapter, int enable); |
2e9d722d | 1379 | int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable); |
af19b491 | 1380 | int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter); |
5ad6ff9d SC |
1381 | void qlcnic_update_cmd_producer(struct qlcnic_host_tx_ring *); |
1382 | void qlcnic_fetch_mac(u32, u32, u8, u8 *); | |
22c8c934 SC |
1383 | void qlcnic_process_rcv_ring_diag(struct qlcnic_host_sds_ring *sds_ring); |
1384 | void qlcnic_clear_lb_mode(struct qlcnic_adapter *adapter); | |
1385 | int qlcnic_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode); | |
1386 | ||
1387 | /* Functions from qlcnic_ethtool.c */ | |
1388 | int qlcnic_check_loopback_buff(unsigned char *data, u8 mac[]); | |
af19b491 AKS |
1389 | |
1390 | /* Functions from qlcnic_main.c */ | |
1391 | int qlcnic_reset_context(struct qlcnic_adapter *); | |
7777de9a | 1392 | void qlcnic_issue_cmd(struct qlcnic_adapter *adapter, struct qlcnic_cmd_args *); |
7eb9855d AKS |
1393 | void qlcnic_diag_free_res(struct net_device *netdev, int max_sds_rings); |
1394 | int qlcnic_diag_alloc_res(struct net_device *netdev, int test); | |
cdaff185 | 1395 | netdev_tx_t qlcnic_xmit_frame(struct sk_buff *skb, struct net_device *netdev); |
f94bc1e7 SC |
1396 | int qlcnic_validate_max_rss(struct net_device *netdev, u8 max_hw, u8 val); |
1397 | int qlcnic_set_max_rss(struct qlcnic_adapter *adapter, u8 data); | |
18f2f616 | 1398 | void qlcnic_dev_request_reset(struct qlcnic_adapter *); |
e5dcf6dc | 1399 | void qlcnic_alloc_lb_filters_mem(struct qlcnic_adapter *adapter); |
af19b491 | 1400 | |
2e9d722d | 1401 | /* Management functions */ |
2e9d722d | 1402 | int qlcnic_get_mac_address(struct qlcnic_adapter *, u8*); |
346fe763 | 1403 | int qlcnic_get_nic_info(struct qlcnic_adapter *, struct qlcnic_info *, u8); |
2e9d722d | 1404 | int qlcnic_set_nic_info(struct qlcnic_adapter *, struct qlcnic_info *); |
346fe763 | 1405 | int qlcnic_get_pci_info(struct qlcnic_adapter *, struct qlcnic_pci_info*); |
2e9d722d AC |
1406 | |
1407 | /* eSwitch management functions */ | |
4e8acb01 RB |
1408 | int qlcnic_config_switch_port(struct qlcnic_adapter *, |
1409 | struct qlcnic_esw_func_cfg *); | |
1410 | int qlcnic_get_eswitch_port_config(struct qlcnic_adapter *, | |
1411 | struct qlcnic_esw_func_cfg *); | |
2e9d722d | 1412 | int qlcnic_config_port_mirroring(struct qlcnic_adapter *, u8, u8, u8); |
b6021212 AKS |
1413 | int qlcnic_get_port_stats(struct qlcnic_adapter *, const u8, const u8, |
1414 | struct __qlcnic_esw_statistics *); | |
1415 | int qlcnic_get_eswitch_stats(struct qlcnic_adapter *, const u8, u8, | |
1416 | struct __qlcnic_esw_statistics *); | |
1417 | int qlcnic_clear_esw_stats(struct qlcnic_adapter *adapter, u8, u8, u8); | |
54a8997c | 1418 | int qlcnic_get_mac_stats(struct qlcnic_adapter *, struct qlcnic_mac_statistics *); |
2e9d722d AC |
1419 | extern int qlcnic_config_tso; |
1420 | ||
c70001a9 SC |
1421 | int qlcnic_napi_add(struct qlcnic_adapter *, struct net_device *); |
1422 | void qlcnic_napi_del(struct qlcnic_adapter *adapter); | |
1423 | void qlcnic_napi_enable(struct qlcnic_adapter *adapter); | |
1424 | void qlcnic_napi_disable(struct qlcnic_adapter *adapter); | |
1425 | int qlcnic_alloc_sds_rings(struct qlcnic_recv_context *, int); | |
1426 | void qlcnic_free_sds_rings(struct qlcnic_recv_context *); | |
1427 | void qlcnic_free_tx_rings(struct qlcnic_adapter *); | |
1428 | int qlcnic_alloc_tx_rings(struct qlcnic_adapter *, struct net_device *); | |
1429 | ||
ec079a07 SC |
1430 | void qlcnic_create_sysfs_entries(struct qlcnic_adapter *adapter); |
1431 | void qlcnic_remove_sysfs_entries(struct qlcnic_adapter *adapter); | |
1432 | void qlcnic_create_diag_entries(struct qlcnic_adapter *adapter); | |
1433 | void qlcnic_remove_diag_entries(struct qlcnic_adapter *adapter); | |
1434 | int qlcnicvf_config_bridged_mode(struct qlcnic_adapter *, u32); | |
1435 | int qlcnicvf_config_led(struct qlcnic_adapter *, u32, u32); | |
1436 | void qlcnic_set_vlan_config(struct qlcnic_adapter *, | |
1437 | struct qlcnic_esw_func_cfg *); | |
1438 | void qlcnic_set_eswitch_port_features(struct qlcnic_adapter *, | |
1439 | struct qlcnic_esw_func_cfg *); | |
1440 | ||
af19b491 AKS |
1441 | /* |
1442 | * QLOGIC Board information | |
1443 | */ | |
1444 | ||
02420be6 | 1445 | #define QLCNIC_MAX_BOARD_NAME_LEN 100 |
af19b491 AKS |
1446 | struct qlcnic_brdinfo { |
1447 | unsigned short vendor; | |
1448 | unsigned short device; | |
1449 | unsigned short sub_vendor; | |
1450 | unsigned short sub_device; | |
1451 | char short_name[QLCNIC_MAX_BOARD_NAME_LEN]; | |
1452 | }; | |
1453 | ||
1454 | static const struct qlcnic_brdinfo qlcnic_boards[] = { | |
02420be6 | 1455 | {0x1077, 0x8020, 0x1077, 0x203, |
1515faf2 AKS |
1456 | "8200 Series Single Port 10GbE Converged Network Adapter " |
1457 | "(TCP/IP Networking)"}, | |
02420be6 | 1458 | {0x1077, 0x8020, 0x1077, 0x207, |
1515faf2 AKS |
1459 | "8200 Series Dual Port 10GbE Converged Network Adapter " |
1460 | "(TCP/IP Networking)"}, | |
af19b491 AKS |
1461 | {0x1077, 0x8020, 0x1077, 0x20b, |
1462 | "3200 Series Dual Port 10Gb Intelligent Ethernet Adapter"}, | |
1463 | {0x1077, 0x8020, 0x1077, 0x20c, | |
1464 | "3200 Series Quad Port 1Gb Intelligent Ethernet Adapter"}, | |
1465 | {0x1077, 0x8020, 0x1077, 0x20f, | |
1466 | "3200 Series Single Port 10Gb Intelligent Ethernet Adapter"}, | |
e132d8d3 | 1467 | {0x1077, 0x8020, 0x103c, 0x3733, |
6336acd5 | 1468 | "NC523SFP 10Gb 2-port Server Adapter"}, |
2679a135 SV |
1469 | {0x1077, 0x8020, 0x103c, 0x3346, |
1470 | "CN1000Q Dual Port Converged Network Adapter"}, | |
a941fef8 SV |
1471 | {0x1077, 0x8020, 0x1077, 0x210, |
1472 | "QME8242-k 10GbE Dual Port Mezzanine Card"}, | |
af19b491 AKS |
1473 | {0x1077, 0x8020, 0x0, 0x0, "cLOM8214 1/10GbE Controller"}, |
1474 | }; | |
1475 | ||
1476 | #define NUM_SUPPORTED_BOARDS ARRAY_SIZE(qlcnic_boards) | |
1477 | ||
1478 | static inline u32 qlcnic_tx_avail(struct qlcnic_host_tx_ring *tx_ring) | |
1479 | { | |
036d61f0 | 1480 | if (likely(tx_ring->producer < tx_ring->sw_consumer)) |
af19b491 AKS |
1481 | return tx_ring->sw_consumer - tx_ring->producer; |
1482 | else | |
1483 | return tx_ring->sw_consumer + tx_ring->num_desc - | |
1484 | tx_ring->producer; | |
1485 | } | |
1486 | ||
c70001a9 SC |
1487 | static inline void qlcnic_disable_int(struct qlcnic_host_sds_ring *sds_ring) |
1488 | { | |
1489 | writel(0, sds_ring->crb_intr_mask); | |
1490 | } | |
1491 | ||
1492 | static inline void qlcnic_enable_int(struct qlcnic_host_sds_ring *sds_ring) | |
1493 | { | |
1494 | struct qlcnic_adapter *adapter = sds_ring->adapter; | |
1495 | ||
1496 | writel(0x1, sds_ring->crb_intr_mask); | |
1497 | ||
1498 | if (!QLCNIC_IS_MSI_FAMILY(adapter)) | |
1499 | writel(0xfbff, adapter->tgt_mask_reg); | |
1500 | } | |
1501 | ||
af19b491 | 1502 | extern const struct ethtool_ops qlcnic_ethtool_ops; |
b43e5ee7 | 1503 | extern const struct ethtool_ops qlcnic_ethtool_failed_ops; |
af19b491 | 1504 | |
2e9d722d | 1505 | struct qlcnic_nic_template { |
2e9d722d AC |
1506 | int (*config_bridged_mode) (struct qlcnic_adapter *, u32); |
1507 | int (*config_led) (struct qlcnic_adapter *, u32, u32); | |
9f26f547 | 1508 | int (*start_firmware) (struct qlcnic_adapter *); |
2e9d722d AC |
1509 | }; |
1510 | ||
65b5b420 AKS |
1511 | #define QLCDB(adapter, lvl, _fmt, _args...) do { \ |
1512 | if (NETIF_MSG_##lvl & adapter->msg_enable) \ | |
1513 | printk(KERN_INFO "%s: %s: " _fmt, \ | |
1514 | dev_name(&adapter->pdev->dev), \ | |
1515 | __func__, ##_args); \ | |
1516 | } while (0) | |
1517 | ||
af19b491 | 1518 | #endif /* __QLCNIC_H_ */ |