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Commit | Line | Data |
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af19b491 | 1 | /* |
40839129 SV |
2 | * QLogic qlcnic NIC Driver |
3 | * Copyright (c) 2009-2010 QLogic Corporation | |
af19b491 | 4 | * |
40839129 | 5 | * See LICENSE.qlcnic for copyright and licensing details. |
af19b491 AKS |
6 | */ |
7 | ||
8 | #ifndef _QLCNIC_H_ | |
9 | #define _QLCNIC_H_ | |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/kernel.h> | |
13 | #include <linux/types.h> | |
14 | #include <linux/ioport.h> | |
15 | #include <linux/pci.h> | |
16 | #include <linux/netdevice.h> | |
17 | #include <linux/etherdevice.h> | |
18 | #include <linux/ip.h> | |
19 | #include <linux/in.h> | |
20 | #include <linux/tcp.h> | |
21 | #include <linux/skbuff.h> | |
22 | #include <linux/firmware.h> | |
23 | ||
24 | #include <linux/ethtool.h> | |
25 | #include <linux/mii.h> | |
26 | #include <linux/timer.h> | |
27 | ||
28 | #include <linux/vmalloc.h> | |
29 | ||
30 | #include <linux/io.h> | |
31 | #include <asm/byteorder.h> | |
b9796a14 AC |
32 | #include <linux/bitops.h> |
33 | #include <linux/if_vlan.h> | |
af19b491 AKS |
34 | |
35 | #include "qlcnic_hdr.h" | |
7f966452 SC |
36 | #include "qlcnic_hw.h" |
37 | #include "qlcnic_83xx_hw.h" | |
af19b491 AKS |
38 | |
39 | #define _QLCNIC_LINUX_MAJOR 5 | |
40 | #define _QLCNIC_LINUX_MINOR 0 | |
341abdbe SSC |
41 | #define _QLCNIC_LINUX_SUBVERSION 30 |
42 | #define QLCNIC_LINUX_VERSIONID "5.0.30" | |
96f8118c | 43 | #define QLCNIC_DRV_IDC_VER 0x01 |
d4066833 SC |
44 | #define QLCNIC_DRIVER_VERSION ((_QLCNIC_LINUX_MAJOR << 16) |\ |
45 | (_QLCNIC_LINUX_MINOR << 8) | (_QLCNIC_LINUX_SUBVERSION)) | |
af19b491 AKS |
46 | |
47 | #define QLCNIC_VERSION_CODE(a, b, c) (((a) << 24) + ((b) << 16) + (c)) | |
48 | #define _major(v) (((v) >> 24) & 0xff) | |
49 | #define _minor(v) (((v) >> 16) & 0xff) | |
50 | #define _build(v) ((v) & 0xffff) | |
51 | ||
52 | /* version in image has weird encoding: | |
53 | * 7:0 - major | |
54 | * 15:8 - minor | |
55 | * 31:16 - build (little endian) | |
56 | */ | |
57 | #define QLCNIC_DECODE_VERSION(v) \ | |
58 | QLCNIC_VERSION_CODE(((v) & 0xff), (((v) >> 8) & 0xff), ((v) >> 16)) | |
59 | ||
8f891387 | 60 | #define QLCNIC_MIN_FW_VERSION QLCNIC_VERSION_CODE(4, 4, 2) |
af19b491 AKS |
61 | #define QLCNIC_NUM_FLASH_SECTORS (64) |
62 | #define QLCNIC_FLASH_SECTOR_SIZE (64 * 1024) | |
63 | #define QLCNIC_FLASH_TOTAL_SIZE (QLCNIC_NUM_FLASH_SECTORS \ | |
64 | * QLCNIC_FLASH_SECTOR_SIZE) | |
65 | ||
66 | #define RCV_DESC_RINGSIZE(rds_ring) \ | |
67 | (sizeof(struct rcv_desc) * (rds_ring)->num_desc) | |
68 | #define RCV_BUFF_RINGSIZE(rds_ring) \ | |
69 | (sizeof(struct qlcnic_rx_buffer) * rds_ring->num_desc) | |
70 | #define STATUS_DESC_RINGSIZE(sds_ring) \ | |
71 | (sizeof(struct status_desc) * (sds_ring)->num_desc) | |
72 | #define TX_BUFF_RINGSIZE(tx_ring) \ | |
73 | (sizeof(struct qlcnic_cmd_buffer) * tx_ring->num_desc) | |
74 | #define TX_DESC_RINGSIZE(tx_ring) \ | |
75 | (sizeof(struct cmd_desc_type0) * tx_ring->num_desc) | |
76 | ||
77 | #define QLCNIC_P3P_A0 0x50 | |
a2050c7e | 78 | #define QLCNIC_P3P_C0 0x58 |
af19b491 AKS |
79 | |
80 | #define QLCNIC_IS_REVISION_P3P(REVISION) (REVISION >= QLCNIC_P3P_A0) | |
81 | ||
82 | #define FIRST_PAGE_GROUP_START 0 | |
83 | #define FIRST_PAGE_GROUP_END 0x100000 | |
84 | ||
ff1b1bf8 SV |
85 | #define P3P_MAX_MTU (9600) |
86 | #define P3P_MIN_MTU (68) | |
af19b491 AKS |
87 | #define QLCNIC_MAX_ETHERHDR 32 /* This contains some padding */ |
88 | ||
ff1b1bf8 SV |
89 | #define QLCNIC_P3P_RX_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + ETH_DATA_LEN) |
90 | #define QLCNIC_P3P_RX_JUMBO_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + P3P_MAX_MTU) | |
af19b491 AKS |
91 | #define QLCNIC_CT_DEFAULT_RX_BUF_LEN 2048 |
92 | #define QLCNIC_LRO_BUFFER_EXTRA 2048 | |
93 | ||
af19b491 | 94 | /* Tx defines */ |
91a403ca | 95 | #define QLCNIC_MAX_FRAGS_PER_TX 14 |
ef71ff83 RB |
96 | #define MAX_TSO_HEADER_DESC 2 |
97 | #define MGMT_CMD_DESC_RESV 4 | |
98 | #define TX_STOP_THRESH ((MAX_SKB_FRAGS >> 2) + MAX_TSO_HEADER_DESC \ | |
99 | + MGMT_CMD_DESC_RESV) | |
af19b491 | 100 | #define QLCNIC_MAX_TX_TIMEOUTS 2 |
af19b491 AKS |
101 | /* |
102 | * Following are the states of the Phantom. Phantom will set them and | |
103 | * Host will read to check if the fields are correct. | |
104 | */ | |
105 | #define PHAN_INITIALIZE_FAILED 0xffff | |
106 | #define PHAN_INITIALIZE_COMPLETE 0xff01 | |
107 | ||
108 | /* Host writes the following to notify that it has done the init-handshake */ | |
109 | #define PHAN_INITIALIZE_ACK 0xf00f | |
110 | #define PHAN_PEG_RCV_INITIALIZED 0xff01 | |
111 | ||
112 | #define NUM_RCV_DESC_RINGS 3 | |
af19b491 AKS |
113 | |
114 | #define RCV_RING_NORMAL 0 | |
115 | #define RCV_RING_JUMBO 1 | |
af19b491 AKS |
116 | |
117 | #define MIN_CMD_DESCRIPTORS 64 | |
118 | #define MIN_RCV_DESCRIPTORS 64 | |
119 | #define MIN_JUMBO_DESCRIPTORS 32 | |
120 | ||
121 | #define MAX_CMD_DESCRIPTORS 1024 | |
122 | #define MAX_RCV_DESCRIPTORS_1G 4096 | |
123 | #define MAX_RCV_DESCRIPTORS_10G 8192 | |
90d19005 | 124 | #define MAX_RCV_DESCRIPTORS_VF 2048 |
af19b491 AKS |
125 | #define MAX_JUMBO_RCV_DESCRIPTORS_1G 512 |
126 | #define MAX_JUMBO_RCV_DESCRIPTORS_10G 1024 | |
af19b491 AKS |
127 | |
128 | #define DEFAULT_RCV_DESCRIPTORS_1G 2048 | |
129 | #define DEFAULT_RCV_DESCRIPTORS_10G 4096 | |
90d19005 | 130 | #define DEFAULT_RCV_DESCRIPTORS_VF 1024 |
251b036a | 131 | #define MAX_RDS_RINGS 2 |
af19b491 AKS |
132 | |
133 | #define get_next_index(index, length) \ | |
134 | (((index) + 1) & ((length) - 1)) | |
135 | ||
af19b491 AKS |
136 | /* |
137 | * Following data structures describe the descriptors that will be used. | |
138 | * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when | |
139 | * we are doing LSO (above the 1500 size packet) only. | |
140 | */ | |
af19b491 AKS |
141 | struct cmd_desc_type0 { |
142 | u8 tcp_hdr_offset; /* For LSO only */ | |
143 | u8 ip_hdr_offset; /* For LSO only */ | |
144 | __le16 flags_opcode; /* 15:13 unused, 12:7 opcode, 6:0 flags */ | |
145 | __le32 nfrags__length; /* 31:8 total len, 7:0 frag count */ | |
146 | ||
147 | __le64 addr_buffer2; | |
148 | ||
149 | __le16 reference_handle; | |
150 | __le16 mss; | |
151 | u8 port_ctxid; /* 7:4 ctxid 3:0 port */ | |
152 | u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */ | |
153 | __le16 conn_id; /* IPSec offoad only */ | |
154 | ||
155 | __le64 addr_buffer3; | |
156 | __le64 addr_buffer1; | |
157 | ||
158 | __le16 buffer_length[4]; | |
159 | ||
160 | __le64 addr_buffer4; | |
161 | ||
2e9d722d | 162 | u8 eth_addr[ETH_ALEN]; |
af19b491 AKS |
163 | __le16 vlan_TCI; |
164 | ||
165 | } __attribute__ ((aligned(64))); | |
166 | ||
167 | /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */ | |
168 | struct rcv_desc { | |
169 | __le16 reference_handle; | |
170 | __le16 reserved; | |
171 | __le32 buffer_length; /* allocated buffer length (usually 2K) */ | |
172 | __le64 addr_buffer; | |
b1fc6d3c | 173 | } __packed; |
af19b491 | 174 | |
af19b491 AKS |
175 | struct status_desc { |
176 | __le64 status_desc_data[2]; | |
177 | } __attribute__ ((aligned(16))); | |
178 | ||
179 | /* UNIFIED ROMIMAGE */ | |
180 | #define QLCNIC_UNI_FW_MIN_SIZE 0xc8000 | |
181 | #define QLCNIC_UNI_DIR_SECT_PRODUCT_TBL 0x0 | |
182 | #define QLCNIC_UNI_DIR_SECT_BOOTLD 0x6 | |
183 | #define QLCNIC_UNI_DIR_SECT_FW 0x7 | |
184 | ||
185 | /*Offsets */ | |
186 | #define QLCNIC_UNI_CHIP_REV_OFF 10 | |
187 | #define QLCNIC_UNI_FLAGS_OFF 11 | |
188 | #define QLCNIC_UNI_BIOS_VERSION_OFF 12 | |
189 | #define QLCNIC_UNI_BOOTLD_IDX_OFF 27 | |
190 | #define QLCNIC_UNI_FIRMWARE_IDX_OFF 29 | |
191 | ||
192 | struct uni_table_desc{ | |
63507592 SS |
193 | __le32 findex; |
194 | __le32 num_entries; | |
195 | __le32 entry_size; | |
196 | __le32 reserved[5]; | |
af19b491 AKS |
197 | }; |
198 | ||
199 | struct uni_data_desc{ | |
63507592 SS |
200 | __le32 findex; |
201 | __le32 size; | |
202 | __le32 reserved[5]; | |
af19b491 AKS |
203 | }; |
204 | ||
0e5f20b6 | 205 | /* Flash Defines and Structures */ |
206 | #define QLCNIC_FLT_LOCATION 0x3F1000 | |
d865ebb4 | 207 | #define QLCNIC_FDT_LOCATION 0x3F0000 |
a2050c7e SV |
208 | #define QLCNIC_B0_FW_IMAGE_REGION 0x74 |
209 | #define QLCNIC_C0_FW_IMAGE_REGION 0x97 | |
f8d54811 | 210 | #define QLCNIC_BOOTLD_REGION 0X72 |
0e5f20b6 | 211 | struct qlcnic_flt_header { |
212 | u16 version; | |
213 | u16 len; | |
214 | u16 checksum; | |
215 | u16 reserved; | |
216 | }; | |
217 | ||
218 | struct qlcnic_flt_entry { | |
219 | u8 region; | |
220 | u8 reserved0; | |
221 | u8 attrib; | |
222 | u8 reserved1; | |
223 | u32 size; | |
224 | u32 start_addr; | |
f8d54811 | 225 | u32 end_addr; |
0e5f20b6 | 226 | }; |
227 | ||
d865ebb4 SC |
228 | /* Flash Descriptor Table */ |
229 | struct qlcnic_fdt { | |
230 | u32 valid; | |
231 | u16 ver; | |
232 | u16 len; | |
233 | u16 cksum; | |
234 | u16 unused; | |
235 | u8 model[16]; | |
236 | u16 mfg_id; | |
237 | u16 id; | |
238 | u8 flag; | |
239 | u8 erase_cmd; | |
240 | u8 alt_erase_cmd; | |
241 | u8 write_enable_cmd; | |
242 | u8 write_enable_bits; | |
243 | u8 write_statusreg_cmd; | |
244 | u8 unprotected_sec_cmd; | |
245 | u8 read_manuf_cmd; | |
246 | u32 block_size; | |
247 | u32 alt_block_size; | |
248 | u32 flash_size; | |
249 | u32 write_enable_data; | |
250 | u8 readid_addr_len; | |
251 | u8 write_disable_bits; | |
252 | u8 read_dev_id_len; | |
253 | u8 chip_erase_cmd; | |
254 | u16 read_timeo; | |
255 | u8 protected_sec_cmd; | |
256 | u8 resvd[65]; | |
257 | }; | |
af19b491 AKS |
258 | /* Magic number to let user know flash is programmed */ |
259 | #define QLCNIC_BDINFO_MAGIC 0x12345678 | |
260 | ||
ff1b1bf8 SV |
261 | #define QLCNIC_BRDTYPE_P3P_REF_QG 0x0021 |
262 | #define QLCNIC_BRDTYPE_P3P_HMEZ 0x0022 | |
263 | #define QLCNIC_BRDTYPE_P3P_10G_CX4_LP 0x0023 | |
264 | #define QLCNIC_BRDTYPE_P3P_4_GB 0x0024 | |
265 | #define QLCNIC_BRDTYPE_P3P_IMEZ 0x0025 | |
266 | #define QLCNIC_BRDTYPE_P3P_10G_SFP_PLUS 0x0026 | |
267 | #define QLCNIC_BRDTYPE_P3P_10000_BASE_T 0x0027 | |
268 | #define QLCNIC_BRDTYPE_P3P_XG_LOM 0x0028 | |
269 | #define QLCNIC_BRDTYPE_P3P_4_GB_MM 0x0029 | |
270 | #define QLCNIC_BRDTYPE_P3P_10G_SFP_CT 0x002a | |
271 | #define QLCNIC_BRDTYPE_P3P_10G_SFP_QT 0x002b | |
272 | #define QLCNIC_BRDTYPE_P3P_10G_CX4 0x0031 | |
273 | #define QLCNIC_BRDTYPE_P3P_10G_XFP 0x0032 | |
274 | #define QLCNIC_BRDTYPE_P3P_10G_TP 0x0080 | |
af19b491 | 275 | |
2e9d722d AC |
276 | #define QLCNIC_MSIX_TABLE_OFFSET 0x44 |
277 | ||
af19b491 AKS |
278 | /* Flash memory map */ |
279 | #define QLCNIC_BRDCFG_START 0x4000 /* board config */ | |
280 | #define QLCNIC_BOOTLD_START 0x10000 /* bootld */ | |
281 | #define QLCNIC_IMAGE_START 0x43000 /* compressed image */ | |
282 | #define QLCNIC_USER_START 0x3E8000 /* Firmare info */ | |
283 | ||
284 | #define QLCNIC_FW_VERSION_OFFSET (QLCNIC_USER_START+0x408) | |
285 | #define QLCNIC_FW_SIZE_OFFSET (QLCNIC_USER_START+0x40c) | |
286 | #define QLCNIC_FW_SERIAL_NUM_OFFSET (QLCNIC_USER_START+0x81c) | |
287 | #define QLCNIC_BIOS_VERSION_OFFSET (QLCNIC_USER_START+0x83c) | |
288 | ||
289 | #define QLCNIC_BRDTYPE_OFFSET (QLCNIC_BRDCFG_START+0x8) | |
290 | #define QLCNIC_FW_MAGIC_OFFSET (QLCNIC_BRDCFG_START+0x128) | |
291 | ||
292 | #define QLCNIC_FW_MIN_SIZE (0x3fffff) | |
293 | #define QLCNIC_UNIFIED_ROMIMAGE 0 | |
294 | #define QLCNIC_FLASH_ROMIMAGE 1 | |
295 | #define QLCNIC_UNKNOWN_ROMIMAGE 0xff | |
296 | ||
297 | #define QLCNIC_UNIFIED_ROMIMAGE_NAME "phanfw.bin" | |
298 | #define QLCNIC_FLASH_ROMIMAGE_NAME "flash" | |
299 | ||
300 | extern char qlcnic_driver_name[]; | |
301 | ||
302 | /* Number of status descriptors to handle per interrupt */ | |
303 | #define MAX_STATUS_HANDLE (64) | |
304 | ||
305 | /* | |
306 | * qlcnic_skb_frag{} is to contain mapping info for each SG list. This | |
307 | * has to be freed when DMA is complete. This is part of qlcnic_tx_buffer{}. | |
308 | */ | |
309 | struct qlcnic_skb_frag { | |
310 | u64 dma; | |
311 | u64 length; | |
312 | }; | |
313 | ||
af19b491 AKS |
314 | /* Following defines are for the state of the buffers */ |
315 | #define QLCNIC_BUFFER_FREE 0 | |
316 | #define QLCNIC_BUFFER_BUSY 1 | |
317 | ||
318 | /* | |
319 | * There will be one qlcnic_buffer per skb packet. These will be | |
320 | * used to save the dma info for pci_unmap_page() | |
321 | */ | |
322 | struct qlcnic_cmd_buffer { | |
323 | struct sk_buff *skb; | |
ef71ff83 | 324 | struct qlcnic_skb_frag frag_array[MAX_SKB_FRAGS + 1]; |
af19b491 AKS |
325 | u32 frag_count; |
326 | }; | |
327 | ||
328 | /* In rx_buffer, we do not need multiple fragments as is a single buffer */ | |
329 | struct qlcnic_rx_buffer { | |
b1fc6d3c | 330 | u16 ref_handle; |
af19b491 | 331 | struct sk_buff *skb; |
b1fc6d3c | 332 | struct list_head list; |
af19b491 | 333 | u64 dma; |
af19b491 AKS |
334 | }; |
335 | ||
336 | /* Board types */ | |
337 | #define QLCNIC_GBE 0x01 | |
338 | #define QLCNIC_XGBE 0x02 | |
339 | ||
8816d009 AC |
340 | /* |
341 | * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is | |
342 | * adjusted based on configured MTU. | |
343 | */ | |
344 | #define QLCNIC_DEFAULT_INTR_COALESCE_RX_TIME_US 3 | |
345 | #define QLCNIC_DEFAULT_INTR_COALESCE_RX_PACKETS 256 | |
346 | ||
347 | #define QLCNIC_INTR_DEFAULT 0x04 | |
348 | #define QLCNIC_CONFIG_INTR_COALESCE 3 | |
349 | ||
350 | struct qlcnic_nic_intr_coalesce { | |
351 | u8 type; | |
352 | u8 sts_ring_mask; | |
353 | u16 rx_packets; | |
354 | u16 rx_time_us; | |
355 | u16 flag; | |
356 | u32 timer_out; | |
357 | }; | |
358 | ||
18f2f616 | 359 | struct qlcnic_dump_template_hdr { |
63507592 SS |
360 | u32 type; |
361 | u32 offset; | |
362 | u32 size; | |
363 | u32 cap_mask; | |
364 | u32 num_entries; | |
365 | u32 version; | |
366 | u32 timestamp; | |
367 | u32 checksum; | |
368 | u32 drv_cap_mask; | |
369 | u32 sys_info[3]; | |
370 | u32 saved_state[16]; | |
371 | u32 cap_sizes[8]; | |
372 | u32 rsvd[0]; | |
18f2f616 AC |
373 | }; |
374 | ||
375 | struct qlcnic_fw_dump { | |
376 | u8 clr; /* flag to indicate if dump is cleared */ | |
9d6a6440 | 377 | u8 enable; /* enable/disable dump */ |
18f2f616 AC |
378 | u32 size; /* total size of the dump */ |
379 | void *data; /* dump data area */ | |
380 | struct qlcnic_dump_template_hdr *tmpl_hdr; | |
381 | }; | |
382 | ||
af19b491 AKS |
383 | /* |
384 | * One hardware_context{} per adapter | |
385 | * contains interrupt info as well shared hardware info. | |
386 | */ | |
387 | struct qlcnic_hardware_context { | |
388 | void __iomem *pci_base0; | |
389 | void __iomem *ocm_win_crb; | |
390 | ||
391 | unsigned long pci_len0; | |
392 | ||
af19b491 AKS |
393 | rwlock_t crb_lock; |
394 | struct mutex mem_lock; | |
395 | ||
af19b491 AKS |
396 | u8 revision_id; |
397 | u8 pci_func; | |
398 | u8 linkup; | |
22c8c934 | 399 | u8 loopback_state; |
79788450 SC |
400 | u8 beacon_state; |
401 | u8 has_link_events; | |
402 | u8 fw_type; | |
403 | u8 physical_port; | |
404 | u8 reset_context; | |
405 | u8 msix_supported; | |
406 | u8 max_mac_filters; | |
407 | u8 mc_enabled; | |
408 | u8 max_mc_count; | |
409 | u8 diag_test; | |
410 | u8 num_msix; | |
411 | u8 nic_mode; | |
412 | char diag_cnt; | |
413 | ||
af19b491 AKS |
414 | u16 port_type; |
415 | u16 board_type; | |
8816d009 | 416 | |
79788450 SC |
417 | u16 link_speed; |
418 | u16 link_duplex; | |
419 | u16 link_autoneg; | |
420 | u16 module_type; | |
421 | ||
422 | u16 op_mode; | |
423 | u16 switch_mode; | |
424 | u16 max_tx_ques; | |
425 | u16 max_rx_ques; | |
426 | u16 max_mtu; | |
427 | u32 msg_enable; | |
428 | u16 act_pci_func; | |
728a98b8 | 429 | |
79788450 SC |
430 | u32 capabilities; |
431 | u32 temp; | |
432 | u32 int_vec_bit; | |
433 | u32 fw_hal_version; | |
7f966452 | 434 | u32 port_config; |
79788450 | 435 | struct qlcnic_hardware_ops *hw_ops; |
8816d009 | 436 | struct qlcnic_nic_intr_coalesce coal; |
18f2f616 | 437 | struct qlcnic_fw_dump fw_dump; |
d865ebb4 | 438 | struct qlcnic_fdt fdt; |
7f966452 | 439 | struct qlcnic_intrpt_config *intr_tbl; |
7e2cf4fe | 440 | u32 *reg_tbl; |
7f966452 SC |
441 | u32 *ext_reg_tbl; |
442 | u32 mbox_aen[QLC_83XX_MBX_AEN_CNT]; | |
443 | u32 mbox_reg[4]; | |
444 | spinlock_t mbx_lock; | |
af19b491 AKS |
445 | }; |
446 | ||
447 | struct qlcnic_adapter_stats { | |
448 | u64 xmitcalled; | |
449 | u64 xmitfinished; | |
450 | u64 rxdropped; | |
451 | u64 txdropped; | |
452 | u64 csummed; | |
453 | u64 rx_pkts; | |
454 | u64 lro_pkts; | |
455 | u64 rxbytes; | |
456 | u64 txbytes; | |
8bfe8b91 SC |
457 | u64 lrobytes; |
458 | u64 lso_frames; | |
459 | u64 xmit_on; | |
460 | u64 xmit_off; | |
461 | u64 skb_alloc_failure; | |
8ae6df97 AKS |
462 | u64 null_rxbuf; |
463 | u64 rx_dma_map_error; | |
464 | u64 tx_dma_map_error; | |
7f966452 | 465 | u64 spurious_intr; |
4be41e92 | 466 | u64 mac_filter_limit_overrun; |
af19b491 AKS |
467 | }; |
468 | ||
469 | /* | |
470 | * Rcv Descriptor Context. One such per Rcv Descriptor. There may | |
471 | * be one Rcv Descriptor for normal packets, one for jumbo and may be others. | |
472 | */ | |
473 | struct qlcnic_host_rds_ring { | |
036d61f0 AC |
474 | void __iomem *crb_rcv_producer; |
475 | struct rcv_desc *desc_head; | |
476 | struct qlcnic_rx_buffer *rx_buf_arr; | |
af19b491 | 477 | u32 num_desc; |
036d61f0 | 478 | u32 producer; |
af19b491 AKS |
479 | u32 dma_size; |
480 | u32 skb_size; | |
481 | u32 flags; | |
af19b491 AKS |
482 | struct list_head free_list; |
483 | spinlock_t lock; | |
484 | dma_addr_t phys_addr; | |
036d61f0 | 485 | } ____cacheline_internodealigned_in_smp; |
af19b491 AKS |
486 | |
487 | struct qlcnic_host_sds_ring { | |
488 | u32 consumer; | |
489 | u32 num_desc; | |
490 | void __iomem *crb_sts_consumer; | |
af19b491 AKS |
491 | |
492 | struct status_desc *desc_head; | |
493 | struct qlcnic_adapter *adapter; | |
494 | struct napi_struct napi; | |
495 | struct list_head free_list[NUM_RCV_DESC_RINGS]; | |
496 | ||
036d61f0 | 497 | void __iomem *crb_intr_mask; |
af19b491 AKS |
498 | int irq; |
499 | ||
500 | dma_addr_t phys_addr; | |
501 | char name[IFNAMSIZ+4]; | |
036d61f0 | 502 | } ____cacheline_internodealigned_in_smp; |
af19b491 AKS |
503 | |
504 | struct qlcnic_host_tx_ring { | |
4be41e92 | 505 | int irq; |
7f966452 SC |
506 | void __iomem *crb_intr_mask; |
507 | char name[IFNAMSIZ+4]; | |
79788450 | 508 | u16 ctx_id; |
af19b491 | 509 | u32 producer; |
af19b491 | 510 | u32 sw_consumer; |
af19b491 | 511 | u32 num_desc; |
036d61f0 | 512 | void __iomem *crb_cmd_producer; |
af19b491 | 513 | struct cmd_desc_type0 *desc_head; |
4be41e92 SC |
514 | struct qlcnic_adapter *adapter; |
515 | struct napi_struct napi; | |
036d61f0 AC |
516 | struct qlcnic_cmd_buffer *cmd_buf_arr; |
517 | __le32 *hw_consumer; | |
518 | ||
af19b491 AKS |
519 | dma_addr_t phys_addr; |
520 | dma_addr_t hw_cons_phys_addr; | |
036d61f0 AC |
521 | struct netdev_queue *txq; |
522 | } ____cacheline_internodealigned_in_smp; | |
af19b491 AKS |
523 | |
524 | /* | |
525 | * Receive context. There is one such structure per instance of the | |
526 | * receive processing. Any state information that is relevant to | |
527 | * the receive, and is must be in this structure. The global data may be | |
528 | * present elsewhere. | |
529 | */ | |
530 | struct qlcnic_recv_context { | |
b1fc6d3c AC |
531 | struct qlcnic_host_rds_ring *rds_rings; |
532 | struct qlcnic_host_sds_ring *sds_rings; | |
af19b491 AKS |
533 | u32 state; |
534 | u16 context_id; | |
535 | u16 virt_port; | |
536 | ||
af19b491 AKS |
537 | }; |
538 | ||
539 | /* HW context creation */ | |
540 | ||
541 | #define QLCNIC_OS_CRB_RETRY_COUNT 4000 | |
af19b491 AKS |
542 | |
543 | #define QLCNIC_CDRP_CMD_BIT 0x80000000 | |
544 | ||
545 | /* | |
546 | * All responses must have the QLCNIC_CDRP_CMD_BIT cleared | |
547 | * in the crb QLCNIC_CDRP_CRB_OFFSET. | |
548 | */ | |
549 | #define QLCNIC_CDRP_FORM_RSP(rsp) (rsp) | |
550 | #define QLCNIC_CDRP_IS_RSP(rsp) (((rsp) & QLCNIC_CDRP_CMD_BIT) == 0) | |
551 | ||
552 | #define QLCNIC_CDRP_RSP_OK 0x00000001 | |
553 | #define QLCNIC_CDRP_RSP_FAIL 0x00000002 | |
554 | #define QLCNIC_CDRP_RSP_TIMEOUT 0x00000003 | |
555 | ||
556 | /* | |
557 | * All commands must have the QLCNIC_CDRP_CMD_BIT set in | |
558 | * the crb QLCNIC_CDRP_CRB_OFFSET. | |
559 | */ | |
560 | #define QLCNIC_CDRP_FORM_CMD(cmd) (QLCNIC_CDRP_CMD_BIT | (cmd)) | |
561 | #define QLCNIC_CDRP_IS_CMD(cmd) (((cmd) & QLCNIC_CDRP_CMD_BIT) != 0) | |
562 | ||
563 | #define QLCNIC_CDRP_CMD_SUBMIT_CAPABILITIES 0x00000001 | |
564 | #define QLCNIC_CDRP_CMD_READ_MAX_RDS_PER_CTX 0x00000002 | |
565 | #define QLCNIC_CDRP_CMD_READ_MAX_SDS_PER_CTX 0x00000003 | |
566 | #define QLCNIC_CDRP_CMD_READ_MAX_RULES_PER_CTX 0x00000004 | |
567 | #define QLCNIC_CDRP_CMD_READ_MAX_RX_CTX 0x00000005 | |
568 | #define QLCNIC_CDRP_CMD_READ_MAX_TX_CTX 0x00000006 | |
569 | #define QLCNIC_CDRP_CMD_CREATE_RX_CTX 0x00000007 | |
570 | #define QLCNIC_CDRP_CMD_DESTROY_RX_CTX 0x00000008 | |
571 | #define QLCNIC_CDRP_CMD_CREATE_TX_CTX 0x00000009 | |
572 | #define QLCNIC_CDRP_CMD_DESTROY_TX_CTX 0x0000000a | |
7777de9a | 573 | #define QLCNIC_CDRP_CMD_INTRPT_TEST 0x00000011 |
af19b491 AKS |
574 | #define QLCNIC_CDRP_CMD_SET_MTU 0x00000012 |
575 | #define QLCNIC_CDRP_CMD_READ_PHY 0x00000013 | |
576 | #define QLCNIC_CDRP_CMD_WRITE_PHY 0x00000014 | |
577 | #define QLCNIC_CDRP_CMD_READ_HW_REG 0x00000015 | |
578 | #define QLCNIC_CDRP_CMD_GET_FLOW_CTL 0x00000016 | |
579 | #define QLCNIC_CDRP_CMD_SET_FLOW_CTL 0x00000017 | |
580 | #define QLCNIC_CDRP_CMD_READ_MAX_MTU 0x00000018 | |
581 | #define QLCNIC_CDRP_CMD_READ_MAX_LRO 0x00000019 | |
2e9d722d AC |
582 | #define QLCNIC_CDRP_CMD_MAC_ADDRESS 0x0000001f |
583 | ||
584 | #define QLCNIC_CDRP_CMD_GET_PCI_INFO 0x00000020 | |
585 | #define QLCNIC_CDRP_CMD_GET_NIC_INFO 0x00000021 | |
586 | #define QLCNIC_CDRP_CMD_SET_NIC_INFO 0x00000022 | |
2e9d722d AC |
587 | #define QLCNIC_CDRP_CMD_GET_ESWITCH_CAPABILITY 0x00000024 |
588 | #define QLCNIC_CDRP_CMD_TOGGLE_ESWITCH 0x00000025 | |
589 | #define QLCNIC_CDRP_CMD_GET_ESWITCH_STATUS 0x00000026 | |
590 | #define QLCNIC_CDRP_CMD_SET_PORTMIRRORING 0x00000027 | |
591 | #define QLCNIC_CDRP_CMD_CONFIGURE_ESWITCH 0x00000028 | |
4e8acb01 | 592 | #define QLCNIC_CDRP_CMD_GET_ESWITCH_PORT_CONFIG 0x00000029 |
b6021212 | 593 | #define QLCNIC_CDRP_CMD_GET_ESWITCH_STATS 0x0000002a |
7e610caa | 594 | #define QLCNIC_CDRP_CMD_CONFIG_PORT 0x0000002E |
18f2f616 AC |
595 | #define QLCNIC_CDRP_CMD_TEMP_SIZE 0x0000002f |
596 | #define QLCNIC_CDRP_CMD_GET_TEMP_HDR 0x00000030 | |
54a8997c | 597 | #define QLCNIC_CDRP_CMD_GET_MAC_STATS 0x00000037 |
af19b491 AKS |
598 | |
599 | #define QLCNIC_RCODE_SUCCESS 0 | |
e42ede22 | 600 | #define QLCNIC_RCODE_INVALID_ARGS 6 |
7e610caa | 601 | #define QLCNIC_RCODE_NOT_SUPPORTED 9 |
e42ede22 JK |
602 | #define QLCNIC_RCODE_NOT_PERMITTED 10 |
603 | #define QLCNIC_RCODE_NOT_IMPL 15 | |
604 | #define QLCNIC_RCODE_INVALID 16 | |
af19b491 AKS |
605 | #define QLCNIC_RCODE_TIMEOUT 17 |
606 | #define QLCNIC_DESTROY_CTX_RESET 0 | |
607 | ||
608 | /* | |
609 | * Capabilities Announced | |
610 | */ | |
611 | #define QLCNIC_CAP0_LEGACY_CONTEXT (1) | |
612 | #define QLCNIC_CAP0_LEGACY_MN (1 << 2) | |
613 | #define QLCNIC_CAP0_LSO (1 << 6) | |
614 | #define QLCNIC_CAP0_JUMBO_CONTIGUOUS (1 << 7) | |
615 | #define QLCNIC_CAP0_LRO_CONTIGUOUS (1 << 8) | |
8f891387 | 616 | #define QLCNIC_CAP0_VALIDOFF (1 << 11) |
cae82d49 | 617 | #define QLCNIC_CAP0_LRO_MSS (1 << 21) |
af19b491 AKS |
618 | |
619 | /* | |
620 | * Context state | |
621 | */ | |
d626ad4d | 622 | #define QLCNIC_HOST_CTX_STATE_FREED 0 |
af19b491 AKS |
623 | #define QLCNIC_HOST_CTX_STATE_ACTIVE 2 |
624 | ||
625 | /* | |
626 | * Rx context | |
627 | */ | |
628 | ||
629 | struct qlcnic_hostrq_sds_ring { | |
630 | __le64 host_phys_addr; /* Ring base addr */ | |
631 | __le32 ring_size; /* Ring entries */ | |
632 | __le16 msi_index; | |
633 | __le16 rsvd; /* Padding */ | |
b1fc6d3c | 634 | } __packed; |
af19b491 AKS |
635 | |
636 | struct qlcnic_hostrq_rds_ring { | |
637 | __le64 host_phys_addr; /* Ring base addr */ | |
638 | __le64 buff_size; /* Packet buffer size */ | |
639 | __le32 ring_size; /* Ring entries */ | |
640 | __le32 ring_kind; /* Class of ring */ | |
b1fc6d3c | 641 | } __packed; |
af19b491 AKS |
642 | |
643 | struct qlcnic_hostrq_rx_ctx { | |
644 | __le64 host_rsp_dma_addr; /* Response dma'd here */ | |
645 | __le32 capabilities[4]; /* Flag bit vector */ | |
646 | __le32 host_int_crb_mode; /* Interrupt crb usage */ | |
647 | __le32 host_rds_crb_mode; /* RDS crb usage */ | |
648 | /* These ring offsets are relative to data[0] below */ | |
649 | __le32 rds_ring_offset; /* Offset to RDS config */ | |
650 | __le32 sds_ring_offset; /* Offset to SDS config */ | |
651 | __le16 num_rds_rings; /* Count of RDS rings */ | |
652 | __le16 num_sds_rings; /* Count of SDS rings */ | |
8f891387 | 653 | __le16 valid_field_offset; |
654 | u8 txrx_sds_binding; | |
655 | u8 msix_handler; | |
656 | u8 reserved[128]; /* reserve space for future expansion*/ | |
af19b491 AKS |
657 | /* MUST BE 64-bit aligned. |
658 | The following is packed: | |
659 | - N hostrq_rds_rings | |
660 | - N hostrq_sds_rings */ | |
661 | char data[0]; | |
b1fc6d3c | 662 | } __packed; |
af19b491 AKS |
663 | |
664 | struct qlcnic_cardrsp_rds_ring{ | |
665 | __le32 host_producer_crb; /* Crb to use */ | |
666 | __le32 rsvd1; /* Padding */ | |
b1fc6d3c | 667 | } __packed; |
af19b491 AKS |
668 | |
669 | struct qlcnic_cardrsp_sds_ring { | |
670 | __le32 host_consumer_crb; /* Crb to use */ | |
671 | __le32 interrupt_crb; /* Crb to use */ | |
b1fc6d3c | 672 | } __packed; |
af19b491 AKS |
673 | |
674 | struct qlcnic_cardrsp_rx_ctx { | |
675 | /* These ring offsets are relative to data[0] below */ | |
676 | __le32 rds_ring_offset; /* Offset to RDS config */ | |
677 | __le32 sds_ring_offset; /* Offset to SDS config */ | |
678 | __le32 host_ctx_state; /* Starting State */ | |
679 | __le32 num_fn_per_port; /* How many PCI fn share the port */ | |
680 | __le16 num_rds_rings; /* Count of RDS rings */ | |
681 | __le16 num_sds_rings; /* Count of SDS rings */ | |
682 | __le16 context_id; /* Handle for context */ | |
683 | u8 phys_port; /* Physical id of port */ | |
684 | u8 virt_port; /* Virtual/Logical id of port */ | |
685 | u8 reserved[128]; /* save space for future expansion */ | |
686 | /* MUST BE 64-bit aligned. | |
687 | The following is packed: | |
688 | - N cardrsp_rds_rings | |
689 | - N cardrs_sds_rings */ | |
690 | char data[0]; | |
b1fc6d3c | 691 | } __packed; |
af19b491 AKS |
692 | |
693 | #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \ | |
694 | (sizeof(HOSTRQ_RX) + \ | |
695 | (rds_rings)*(sizeof(struct qlcnic_hostrq_rds_ring)) + \ | |
696 | (sds_rings)*(sizeof(struct qlcnic_hostrq_sds_ring))) | |
697 | ||
698 | #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \ | |
699 | (sizeof(CARDRSP_RX) + \ | |
700 | (rds_rings)*(sizeof(struct qlcnic_cardrsp_rds_ring)) + \ | |
701 | (sds_rings)*(sizeof(struct qlcnic_cardrsp_sds_ring))) | |
702 | ||
703 | /* | |
704 | * Tx context | |
705 | */ | |
706 | ||
707 | struct qlcnic_hostrq_cds_ring { | |
708 | __le64 host_phys_addr; /* Ring base addr */ | |
709 | __le32 ring_size; /* Ring entries */ | |
710 | __le32 rsvd; /* Padding */ | |
b1fc6d3c | 711 | } __packed; |
af19b491 AKS |
712 | |
713 | struct qlcnic_hostrq_tx_ctx { | |
714 | __le64 host_rsp_dma_addr; /* Response dma'd here */ | |
715 | __le64 cmd_cons_dma_addr; /* */ | |
716 | __le64 dummy_dma_addr; /* */ | |
717 | __le32 capabilities[4]; /* Flag bit vector */ | |
718 | __le32 host_int_crb_mode; /* Interrupt crb usage */ | |
719 | __le32 rsvd1; /* Padding */ | |
720 | __le16 rsvd2; /* Padding */ | |
721 | __le16 interrupt_ctl; | |
722 | __le16 msi_index; | |
723 | __le16 rsvd3; /* Padding */ | |
724 | struct qlcnic_hostrq_cds_ring cds_ring; /* Desc of cds ring */ | |
725 | u8 reserved[128]; /* future expansion */ | |
b1fc6d3c | 726 | } __packed; |
af19b491 AKS |
727 | |
728 | struct qlcnic_cardrsp_cds_ring { | |
729 | __le32 host_producer_crb; /* Crb to use */ | |
730 | __le32 interrupt_crb; /* Crb to use */ | |
b1fc6d3c | 731 | } __packed; |
af19b491 AKS |
732 | |
733 | struct qlcnic_cardrsp_tx_ctx { | |
734 | __le32 host_ctx_state; /* Starting state */ | |
735 | __le16 context_id; /* Handle for context */ | |
736 | u8 phys_port; /* Physical id of port */ | |
737 | u8 virt_port; /* Virtual/Logical id of port */ | |
738 | struct qlcnic_cardrsp_cds_ring cds_ring; /* Card cds settings */ | |
739 | u8 reserved[128]; /* future expansion */ | |
b1fc6d3c | 740 | } __packed; |
af19b491 AKS |
741 | |
742 | #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX)) | |
743 | #define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX)) | |
744 | ||
745 | /* CRB */ | |
746 | ||
747 | #define QLCNIC_HOST_RDS_CRB_MODE_UNIQUE 0 | |
748 | #define QLCNIC_HOST_RDS_CRB_MODE_SHARED 1 | |
749 | #define QLCNIC_HOST_RDS_CRB_MODE_CUSTOM 2 | |
750 | #define QLCNIC_HOST_RDS_CRB_MODE_MAX 3 | |
751 | ||
752 | #define QLCNIC_HOST_INT_CRB_MODE_UNIQUE 0 | |
753 | #define QLCNIC_HOST_INT_CRB_MODE_SHARED 1 | |
754 | #define QLCNIC_HOST_INT_CRB_MODE_NORX 2 | |
755 | #define QLCNIC_HOST_INT_CRB_MODE_NOTX 3 | |
756 | #define QLCNIC_HOST_INT_CRB_MODE_NORXTX 4 | |
757 | ||
758 | ||
759 | /* MAC */ | |
760 | ||
ff1b1bf8 | 761 | #define MC_COUNT_P3P 38 |
af19b491 AKS |
762 | |
763 | #define QLCNIC_MAC_NOOP 0 | |
764 | #define QLCNIC_MAC_ADD 1 | |
765 | #define QLCNIC_MAC_DEL 2 | |
03c5d770 AKS |
766 | #define QLCNIC_MAC_VLAN_ADD 3 |
767 | #define QLCNIC_MAC_VLAN_DEL 4 | |
af19b491 AKS |
768 | |
769 | struct qlcnic_mac_list_s { | |
770 | struct list_head list; | |
771 | uint8_t mac_addr[ETH_ALEN+2]; | |
772 | }; | |
773 | ||
af19b491 AKS |
774 | #define QLCNIC_HOST_REQUEST 0x13 |
775 | #define QLCNIC_REQUEST 0x14 | |
776 | ||
777 | #define QLCNIC_MAC_EVENT 0x1 | |
778 | ||
779 | #define QLCNIC_IP_UP 2 | |
780 | #define QLCNIC_IP_DOWN 3 | |
781 | ||
22c8c934 | 782 | #define QLCNIC_ILB_MODE 0x1 |
e1428d26 | 783 | #define QLCNIC_ELB_MODE 0x2 |
22c8c934 SC |
784 | |
785 | #define QLCNIC_LINKEVENT 0x1 | |
786 | #define QLCNIC_LB_RESPONSE 0x2 | |
787 | #define QLCNIC_IS_LB_CONFIGURED(VAL) \ | |
788 | (VAL == (QLCNIC_LINKEVENT | QLCNIC_LB_RESPONSE)) | |
789 | ||
af19b491 AKS |
790 | /* |
791 | * Driver --> Firmware | |
792 | */ | |
b1fc6d3c AC |
793 | #define QLCNIC_H2C_OPCODE_CONFIG_RSS 0x1 |
794 | #define QLCNIC_H2C_OPCODE_CONFIG_INTR_COALESCE 0x3 | |
795 | #define QLCNIC_H2C_OPCODE_CONFIG_LED 0x4 | |
796 | #define QLCNIC_H2C_OPCODE_LRO_REQUEST 0x7 | |
797 | #define QLCNIC_H2C_OPCODE_SET_MAC_RECEIVE_MODE 0xc | |
798 | #define QLCNIC_H2C_OPCODE_CONFIG_IPADDR 0x12 | |
22c8c934 | 799 | |
b1fc6d3c AC |
800 | #define QLCNIC_H2C_OPCODE_GET_LINKEVENT 0x15 |
801 | #define QLCNIC_H2C_OPCODE_CONFIG_BRIDGING 0x17 | |
802 | #define QLCNIC_H2C_OPCODE_CONFIG_HW_LRO 0x18 | |
22c8c934 SC |
803 | #define QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK 0x13 |
804 | ||
af19b491 AKS |
805 | /* |
806 | * Firmware --> Driver | |
807 | */ | |
808 | ||
22c8c934 | 809 | #define QLCNIC_C2H_OPCODE_CONFIG_LOOPBACK 0x8f |
7f966452 | 810 | #define QLCNIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE 0x8D |
af19b491 AKS |
811 | |
812 | #define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */ | |
813 | #define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */ | |
814 | #define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */ | |
815 | ||
816 | #define QLCNIC_LRO_REQUEST_CLEANUP 4 | |
817 | ||
818 | /* Capabilites received */ | |
ac8d0c4f AC |
819 | #define QLCNIC_FW_CAPABILITY_TSO BIT_1 |
820 | #define QLCNIC_FW_CAPABILITY_BDG BIT_8 | |
821 | #define QLCNIC_FW_CAPABILITY_FVLANTX BIT_9 | |
822 | #define QLCNIC_FW_CAPABILITY_HW_LRO BIT_10 | |
fef0c060 | 823 | #define QLCNIC_FW_CAPABILITY_MULTI_LOOPBACK BIT_27 |
cae82d49 RB |
824 | #define QLCNIC_FW_CAPABILITY_MORE_CAPS BIT_31 |
825 | ||
826 | #define QLCNIC_FW_CAPABILITY_2_LRO_MAX_TCP_SEG BIT_2 | |
af19b491 AKS |
827 | |
828 | /* module types */ | |
829 | #define LINKEVENT_MODULE_NOT_PRESENT 1 | |
830 | #define LINKEVENT_MODULE_OPTICAL_UNKNOWN 2 | |
831 | #define LINKEVENT_MODULE_OPTICAL_SRLR 3 | |
832 | #define LINKEVENT_MODULE_OPTICAL_LRM 4 | |
833 | #define LINKEVENT_MODULE_OPTICAL_SFP_1G 5 | |
834 | #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE 6 | |
835 | #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN 7 | |
836 | #define LINKEVENT_MODULE_TWINAX 8 | |
837 | ||
838 | #define LINKSPEED_10GBPS 10000 | |
839 | #define LINKSPEED_1GBPS 1000 | |
840 | #define LINKSPEED_100MBPS 100 | |
841 | #define LINKSPEED_10MBPS 10 | |
842 | ||
843 | #define LINKSPEED_ENCODED_10MBPS 0 | |
844 | #define LINKSPEED_ENCODED_100MBPS 1 | |
845 | #define LINKSPEED_ENCODED_1GBPS 2 | |
846 | ||
847 | #define LINKEVENT_AUTONEG_DISABLED 0 | |
848 | #define LINKEVENT_AUTONEG_ENABLED 1 | |
849 | ||
850 | #define LINKEVENT_HALF_DUPLEX 0 | |
851 | #define LINKEVENT_FULL_DUPLEX 1 | |
852 | ||
853 | #define LINKEVENT_LINKSPEED_MBPS 0 | |
854 | #define LINKEVENT_LINKSPEED_ENCODED 1 | |
855 | ||
af19b491 AKS |
856 | /* firmware response header: |
857 | * 63:58 - message type | |
858 | * 57:56 - owner | |
859 | * 55:53 - desc count | |
860 | * 52:48 - reserved | |
861 | * 47:40 - completion id | |
862 | * 39:32 - opcode | |
863 | * 31:16 - error code | |
864 | * 15:00 - reserved | |
865 | */ | |
866 | #define qlcnic_get_nic_msg_opcode(msg_hdr) \ | |
867 | ((msg_hdr >> 32) & 0xFF) | |
868 | ||
869 | struct qlcnic_fw_msg { | |
870 | union { | |
871 | struct { | |
872 | u64 hdr; | |
873 | u64 body[7]; | |
874 | }; | |
875 | u64 words[8]; | |
876 | }; | |
877 | }; | |
878 | ||
879 | struct qlcnic_nic_req { | |
880 | __le64 qhdr; | |
881 | __le64 req_hdr; | |
882 | __le64 words[6]; | |
b1fc6d3c | 883 | } __packed; |
af19b491 AKS |
884 | |
885 | struct qlcnic_mac_req { | |
886 | u8 op; | |
887 | u8 tag; | |
888 | u8 mac_addr[6]; | |
889 | }; | |
890 | ||
7e56cac4 SC |
891 | struct qlcnic_vlan_req { |
892 | __le16 vlan_id; | |
893 | __le16 rsvd[3]; | |
b1fc6d3c | 894 | } __packed; |
7e56cac4 | 895 | |
b501595c SC |
896 | struct qlcnic_ipaddr { |
897 | __be32 ipv4; | |
898 | __be32 ipv6[4]; | |
899 | }; | |
900 | ||
af19b491 AKS |
901 | #define QLCNIC_MSI_ENABLED 0x02 |
902 | #define QLCNIC_MSIX_ENABLED 0x04 | |
7f966452 | 903 | #define QLCNIC_LRO_ENABLED 0x01 |
24763d80 | 904 | #define QLCNIC_LRO_DISABLED 0x00 |
af19b491 AKS |
905 | #define QLCNIC_BRIDGE_ENABLED 0X10 |
906 | #define QLCNIC_DIAG_ENABLED 0x20 | |
0e33c664 | 907 | #define QLCNIC_ESWITCH_ENABLED 0x40 |
0866d96d | 908 | #define QLCNIC_ADAPTER_INITIALIZED 0x80 |
8cf61f89 | 909 | #define QLCNIC_TAGGING_ENABLED 0x100 |
fe4d434d | 910 | #define QLCNIC_MACSPOOF 0x200 |
7373373d | 911 | #define QLCNIC_MAC_OVERRIDE_DISABLED 0x400 |
ee07c1a7 | 912 | #define QLCNIC_PROMISC_DISABLED 0x800 |
b0044bcf | 913 | #define QLCNIC_NEED_FLR 0x1000 |
602ca6f0 | 914 | #define QLCNIC_FW_RESET_OWNER 0x2000 |
032a13c7 | 915 | #define QLCNIC_FW_HANG 0x4000 |
cae82d49 | 916 | #define QLCNIC_FW_LRO_MSS_CAP 0x8000 |
af19b491 AKS |
917 | #define QLCNIC_IS_MSI_FAMILY(adapter) \ |
918 | ((adapter)->flags & (QLCNIC_MSI_ENABLED | QLCNIC_MSIX_ENABLED)) | |
919 | ||
f94bc1e7 | 920 | #define QLCNIC_DEF_NUM_STS_DESC_RINGS 4 |
af19b491 AKS |
921 | #define QLCNIC_MSIX_TBL_SPACE 8192 |
922 | #define QLCNIC_PCI_REG_MSIX_TBL 0x44 | |
2e9d722d | 923 | #define QLCNIC_MSIX_TBL_PGSIZE 4096 |
af19b491 AKS |
924 | |
925 | #define QLCNIC_NETDEV_WEIGHT 128 | |
926 | #define QLCNIC_ADAPTER_UP_MAGIC 777 | |
927 | ||
928 | #define __QLCNIC_FW_ATTACHED 0 | |
929 | #define __QLCNIC_DEV_UP 1 | |
930 | #define __QLCNIC_RESETTING 2 | |
931 | #define __QLCNIC_START_FW 4 | |
451724c8 | 932 | #define __QLCNIC_AER 5 |
89b4208e | 933 | #define __QLCNIC_DIAG_RES_ALLOC 6 |
728a98b8 | 934 | #define __QLCNIC_LED_ENABLE 7 |
af19b491 | 935 | |
7eb9855d | 936 | #define QLCNIC_INTERRUPT_TEST 1 |
cdaff185 | 937 | #define QLCNIC_LOOPBACK_TEST 2 |
c75822a3 | 938 | #define QLCNIC_LED_TEST 3 |
7eb9855d | 939 | |
b5e5492c | 940 | #define QLCNIC_FILTER_AGE 80 |
e5edb7b1 | 941 | #define QLCNIC_READD_AGE 20 |
b5e5492c | 942 | #define QLCNIC_LB_MAX_FILTERS 64 |
7f966452 | 943 | #define QLCNIC_LB_BUCKET_SIZE 32 |
b5e5492c | 944 | |
fef0c060 AKS |
945 | /* QLCNIC Driver Error Code */ |
946 | #define QLCNIC_FW_NOT_RESPOND 51 | |
947 | #define QLCNIC_TEST_IN_PROGRESS 52 | |
948 | #define QLCNIC_UNDEFINED_ERROR 53 | |
949 | #define QLCNIC_LB_CABLE_NOT_CONN 54 | |
950 | ||
b5e5492c AKS |
951 | struct qlcnic_filter { |
952 | struct hlist_node fnode; | |
953 | u8 faddr[ETH_ALEN]; | |
7e56cac4 | 954 | __le16 vlan_id; |
b5e5492c AKS |
955 | unsigned long ftime; |
956 | }; | |
957 | ||
958 | struct qlcnic_filter_hash { | |
959 | struct hlist_head *fhead; | |
960 | u8 fnum; | |
7f966452 SC |
961 | u16 fmax; |
962 | u16 fbucket_size; | |
b5e5492c AKS |
963 | }; |
964 | ||
af19b491 | 965 | struct qlcnic_adapter { |
b1fc6d3c AC |
966 | struct qlcnic_hardware_context *ahw; |
967 | struct qlcnic_recv_context *recv_ctx; | |
968 | struct qlcnic_host_tx_ring *tx_ring; | |
af19b491 AKS |
969 | struct net_device *netdev; |
970 | struct pci_dev *pdev; | |
af19b491 | 971 | |
b1fc6d3c AC |
972 | unsigned long state; |
973 | u32 flags; | |
af19b491 | 974 | |
79788450 | 975 | int max_drv_tx_rings; |
af19b491 AKS |
976 | u16 num_txd; |
977 | u16 num_rxd; | |
978 | u16 num_jumbo_rxd; | |
90d19005 SC |
979 | u16 max_rxd; |
980 | u16 max_jumbo_rxd; | |
af19b491 AKS |
981 | |
982 | u8 max_rds_rings; | |
983 | u8 max_sds_rings; | |
7f966452 | 984 | u8 rx_csum; |
af19b491 | 985 | u8 portnum; |
af19b491 | 986 | |
af19b491 AKS |
987 | u8 fw_wait_cnt; |
988 | u8 fw_fail_cnt; | |
989 | u8 tx_timeo_cnt; | |
990 | u8 need_fw_reset; | |
991 | ||
af19b491 | 992 | u16 is_up; |
8cf61f89 | 993 | u16 pvid; |
2e9d722d | 994 | |
af19b491 | 995 | u32 irq; |
4e70812b | 996 | u32 heartbeat; |
af19b491 AKS |
997 | |
998 | u8 dev_state; | |
aa5e18c0 SC |
999 | u8 reset_ack_timeo; |
1000 | u8 dev_init_timeo; | |
af19b491 AKS |
1001 | |
1002 | u8 mac_addr[ETH_ALEN]; | |
1003 | ||
6df900e9 | 1004 | u64 dev_rst_time; |
e5dcf6dc | 1005 | u8 mac_learn; |
b9796a14 | 1006 | unsigned long vlans[BITS_TO_LONGS(VLAN_N_VID)]; |
d865ebb4 | 1007 | u8 flash_mfg_id; |
346fe763 | 1008 | struct qlcnic_npar_info *npars; |
2e9d722d AC |
1009 | struct qlcnic_eswitch *eswitch; |
1010 | struct qlcnic_nic_template *nic_ops; | |
1011 | ||
af19b491 | 1012 | struct qlcnic_adapter_stats stats; |
b1fc6d3c | 1013 | struct list_head mac_list; |
af19b491 AKS |
1014 | |
1015 | void __iomem *tgt_mask_reg; | |
1016 | void __iomem *tgt_status_reg; | |
1017 | void __iomem *crb_int_state_reg; | |
1018 | void __iomem *isr_int_vec; | |
1019 | ||
f94bc1e7 | 1020 | struct msix_entry *msix_entries; |
7f966452 | 1021 | struct workqueue_struct *qlcnic_wq; |
af19b491 | 1022 | struct delayed_work fw_work; |
7f966452 | 1023 | struct delayed_work idc_aen_work; |
af19b491 | 1024 | |
b5e5492c AKS |
1025 | struct qlcnic_filter_hash fhash; |
1026 | ||
b1fc6d3c AC |
1027 | spinlock_t tx_clean_lock; |
1028 | spinlock_t mac_learn_lock; | |
63507592 | 1029 | u32 file_prd_off; /*File fw product offset*/ |
af19b491 AKS |
1030 | u32 fw_version; |
1031 | const struct firmware *fw; | |
1032 | }; | |
1033 | ||
63507592 | 1034 | struct qlcnic_info_le { |
2e9d722d | 1035 | __le16 pci_func; |
63507592 | 1036 | __le16 op_mode; /* 1 = Priv, 2 = NP, 3 = NP passthru */ |
2e9d722d | 1037 | __le16 phys_port; |
63507592 | 1038 | __le16 switch_mode; /* 0 = disabled, 1 = int, 2 = ext */ |
2e9d722d AC |
1039 | |
1040 | __le32 capabilities; | |
1041 | u8 max_mac_filters; | |
1042 | u8 reserved1; | |
1043 | __le16 max_mtu; | |
1044 | ||
1045 | __le16 max_tx_ques; | |
1046 | __le16 max_rx_ques; | |
1047 | __le16 min_tx_bw; | |
1048 | __le16 max_tx_bw; | |
7f966452 SC |
1049 | __le32 op_type; |
1050 | __le16 max_bw_reg_offset; | |
1051 | __le16 max_linkspeed_reg_offset; | |
1052 | __le32 capability1; | |
1053 | __le32 capability2; | |
1054 | __le32 capability3; | |
1055 | __le16 max_tx_mac_filters; | |
1056 | __le16 max_rx_mcast_mac_filters; | |
1057 | __le16 max_rx_ucast_mac_filters; | |
1058 | __le16 max_rx_ip_addr; | |
1059 | __le16 max_rx_lro_flow; | |
1060 | __le16 max_rx_status_rings; | |
1061 | __le16 max_rx_buf_rings; | |
1062 | __le16 max_tx_vlan_keys; | |
1063 | u8 total_pf; | |
1064 | u8 total_rss_engines; | |
1065 | __le16 max_vports; | |
1066 | u8 reserved2[64]; | |
b1fc6d3c | 1067 | } __packed; |
2e9d722d | 1068 | |
63507592 SS |
1069 | struct qlcnic_info { |
1070 | u16 pci_func; | |
1071 | u16 op_mode; | |
1072 | u16 phys_port; | |
1073 | u16 switch_mode; | |
1074 | u32 capabilities; | |
1075 | u8 max_mac_filters; | |
1076 | u8 reserved1; | |
1077 | u16 max_mtu; | |
1078 | u16 max_tx_ques; | |
1079 | u16 max_rx_ques; | |
1080 | u16 min_tx_bw; | |
1081 | u16 max_tx_bw; | |
7f966452 SC |
1082 | u32 op_type; |
1083 | u16 max_bw_reg_offset; | |
1084 | u16 max_linkspeed_reg_offset; | |
1085 | u32 capability1; | |
1086 | u32 capability2; | |
1087 | u32 capability3; | |
1088 | u16 max_tx_mac_filters; | |
1089 | u16 max_rx_mcast_mac_filters; | |
1090 | u16 max_rx_ucast_mac_filters; | |
1091 | u16 max_rx_ip_addr; | |
1092 | u16 max_rx_lro_flow; | |
1093 | u16 max_rx_status_rings; | |
1094 | u16 max_rx_buf_rings; | |
1095 | u16 max_tx_vlan_keys; | |
1096 | u8 total_pf; | |
1097 | u8 total_rss_engines; | |
1098 | u16 max_vports; | |
63507592 | 1099 | }; |
2e9d722d | 1100 | |
63507592 SS |
1101 | struct qlcnic_pci_info_le { |
1102 | __le16 id; /* pci function id */ | |
1103 | __le16 active; /* 1 = Enabled */ | |
1104 | __le16 type; /* 1 = NIC, 2 = FCoE, 3 = iSCSI */ | |
1105 | __le16 default_port; /* default port number */ | |
1106 | ||
1107 | __le16 tx_min_bw; /* Multiple of 100mbpc */ | |
2e9d722d AC |
1108 | __le16 tx_max_bw; |
1109 | __le16 reserved1[2]; | |
1110 | ||
1111 | u8 mac[ETH_ALEN]; | |
7f966452 SC |
1112 | __le16 func_count; |
1113 | u8 reserved2[104]; | |
1114 | ||
b1fc6d3c | 1115 | } __packed; |
2e9d722d | 1116 | |
63507592 SS |
1117 | struct qlcnic_pci_info { |
1118 | u16 id; | |
1119 | u16 active; | |
1120 | u16 type; | |
1121 | u16 default_port; | |
1122 | u16 tx_min_bw; | |
1123 | u16 tx_max_bw; | |
1124 | u8 mac[ETH_ALEN]; | |
7f966452 | 1125 | u16 func_count; |
63507592 SS |
1126 | }; |
1127 | ||
346fe763 | 1128 | struct qlcnic_npar_info { |
4e8acb01 | 1129 | u16 pvid; |
cea8975e AC |
1130 | u16 min_bw; |
1131 | u16 max_bw; | |
346fe763 RB |
1132 | u8 phy_port; |
1133 | u8 type; | |
1134 | u8 active; | |
1135 | u8 enable_pm; | |
1136 | u8 dest_npar; | |
346fe763 | 1137 | u8 discard_tagged; |
7373373d | 1138 | u8 mac_override; |
4e8acb01 RB |
1139 | u8 mac_anti_spoof; |
1140 | u8 promisc_mode; | |
1141 | u8 offload_flags; | |
bff57d8e | 1142 | u8 pci_func; |
346fe763 | 1143 | }; |
4e8acb01 | 1144 | |
2e9d722d AC |
1145 | struct qlcnic_eswitch { |
1146 | u8 port; | |
1147 | u8 active_vports; | |
1148 | u8 active_vlans; | |
1149 | u8 active_ucast_filters; | |
1150 | u8 max_ucast_filters; | |
1151 | u8 max_active_vlans; | |
1152 | ||
1153 | u32 flags; | |
1154 | #define QLCNIC_SWITCH_ENABLE BIT_1 | |
1155 | #define QLCNIC_SWITCH_VLAN_FILTERING BIT_2 | |
1156 | #define QLCNIC_SWITCH_PROMISC_MODE BIT_3 | |
1157 | #define QLCNIC_SWITCH_PORT_MIRRORING BIT_4 | |
1158 | }; | |
1159 | ||
346fe763 RB |
1160 | |
1161 | /* Return codes for Error handling */ | |
1162 | #define QL_STATUS_INVALID_PARAM -1 | |
1163 | ||
2abea2f0 | 1164 | #define MAX_BW 100 /* % of link speed */ |
346fe763 RB |
1165 | #define MAX_VLAN_ID 4095 |
1166 | #define MIN_VLAN_ID 2 | |
346fe763 RB |
1167 | #define DEFAULT_MAC_LEARN 1 |
1168 | ||
0184bbba | 1169 | #define IS_VALID_VLAN(vlan) (vlan >= MIN_VLAN_ID && vlan < MAX_VLAN_ID) |
2abea2f0 | 1170 | #define IS_VALID_BW(bw) (bw <= MAX_BW) |
346fe763 RB |
1171 | |
1172 | struct qlcnic_pci_func_cfg { | |
1173 | u16 func_type; | |
1174 | u16 min_bw; | |
1175 | u16 max_bw; | |
1176 | u16 port_num; | |
1177 | u8 pci_func; | |
1178 | u8 func_state; | |
1179 | u8 def_mac_addr[6]; | |
1180 | }; | |
1181 | ||
1182 | struct qlcnic_npar_func_cfg { | |
1183 | u32 fw_capab; | |
1184 | u16 port_num; | |
1185 | u16 min_bw; | |
1186 | u16 max_bw; | |
1187 | u16 max_tx_queues; | |
1188 | u16 max_rx_queues; | |
1189 | u8 pci_func; | |
1190 | u8 op_mode; | |
1191 | }; | |
1192 | ||
1193 | struct qlcnic_pm_func_cfg { | |
1194 | u8 pci_func; | |
1195 | u8 action; | |
1196 | u8 dest_npar; | |
1197 | u8 reserved[5]; | |
1198 | }; | |
1199 | ||
1200 | struct qlcnic_esw_func_cfg { | |
1201 | u16 vlan_id; | |
4e8acb01 RB |
1202 | u8 op_mode; |
1203 | u8 op_type; | |
346fe763 RB |
1204 | u8 pci_func; |
1205 | u8 host_vlan_tag; | |
1206 | u8 promisc_mode; | |
1207 | u8 discard_tagged; | |
7373373d | 1208 | u8 mac_override; |
4e8acb01 RB |
1209 | u8 mac_anti_spoof; |
1210 | u8 offload_flags; | |
1211 | u8 reserved[5]; | |
346fe763 RB |
1212 | }; |
1213 | ||
b6021212 AKS |
1214 | #define QLCNIC_STATS_VERSION 1 |
1215 | #define QLCNIC_STATS_PORT 1 | |
1216 | #define QLCNIC_STATS_ESWITCH 2 | |
1217 | #define QLCNIC_QUERY_RX_COUNTER 0 | |
1218 | #define QLCNIC_QUERY_TX_COUNTER 1 | |
54a8997c JK |
1219 | #define QLCNIC_STATS_NOT_AVAIL 0xffffffffffffffffULL |
1220 | #define QLCNIC_FILL_STATS(VAL1) \ | |
1221 | (((VAL1) == QLCNIC_STATS_NOT_AVAIL) ? 0 : VAL1) | |
1222 | #define QLCNIC_MAC_STATS 1 | |
1223 | #define QLCNIC_ESW_STATS 2 | |
ef182805 AKS |
1224 | |
1225 | #define QLCNIC_ADD_ESW_STATS(VAL1, VAL2)\ | |
1226 | do { \ | |
54a8997c JK |
1227 | if (((VAL1) == QLCNIC_STATS_NOT_AVAIL) && \ |
1228 | ((VAL2) != QLCNIC_STATS_NOT_AVAIL)) \ | |
ef182805 | 1229 | (VAL1) = (VAL2); \ |
54a8997c JK |
1230 | else if (((VAL1) != QLCNIC_STATS_NOT_AVAIL) && \ |
1231 | ((VAL2) != QLCNIC_STATS_NOT_AVAIL)) \ | |
ef182805 AKS |
1232 | (VAL1) += (VAL2); \ |
1233 | } while (0) | |
1234 | ||
63507592 | 1235 | struct qlcnic_mac_statistics_le { |
54a8997c JK |
1236 | __le64 mac_tx_frames; |
1237 | __le64 mac_tx_bytes; | |
1238 | __le64 mac_tx_mcast_pkts; | |
1239 | __le64 mac_tx_bcast_pkts; | |
1240 | __le64 mac_tx_pause_cnt; | |
1241 | __le64 mac_tx_ctrl_pkt; | |
1242 | __le64 mac_tx_lt_64b_pkts; | |
1243 | __le64 mac_tx_lt_127b_pkts; | |
1244 | __le64 mac_tx_lt_255b_pkts; | |
1245 | __le64 mac_tx_lt_511b_pkts; | |
1246 | __le64 mac_tx_lt_1023b_pkts; | |
1247 | __le64 mac_tx_lt_1518b_pkts; | |
1248 | __le64 mac_tx_gt_1518b_pkts; | |
1249 | __le64 rsvd1[3]; | |
1250 | ||
1251 | __le64 mac_rx_frames; | |
1252 | __le64 mac_rx_bytes; | |
1253 | __le64 mac_rx_mcast_pkts; | |
1254 | __le64 mac_rx_bcast_pkts; | |
1255 | __le64 mac_rx_pause_cnt; | |
1256 | __le64 mac_rx_ctrl_pkt; | |
1257 | __le64 mac_rx_lt_64b_pkts; | |
1258 | __le64 mac_rx_lt_127b_pkts; | |
1259 | __le64 mac_rx_lt_255b_pkts; | |
1260 | __le64 mac_rx_lt_511b_pkts; | |
1261 | __le64 mac_rx_lt_1023b_pkts; | |
1262 | __le64 mac_rx_lt_1518b_pkts; | |
1263 | __le64 mac_rx_gt_1518b_pkts; | |
1264 | __le64 rsvd2[3]; | |
1265 | ||
1266 | __le64 mac_rx_length_error; | |
1267 | __le64 mac_rx_length_small; | |
1268 | __le64 mac_rx_length_large; | |
1269 | __le64 mac_rx_jabber; | |
1270 | __le64 mac_rx_dropped; | |
1271 | __le64 mac_rx_crc_error; | |
1272 | __le64 mac_align_error; | |
1273 | } __packed; | |
1274 | ||
63507592 SS |
1275 | struct qlcnic_mac_statistics { |
1276 | u64 mac_tx_frames; | |
1277 | u64 mac_tx_bytes; | |
1278 | u64 mac_tx_mcast_pkts; | |
1279 | u64 mac_tx_bcast_pkts; | |
1280 | u64 mac_tx_pause_cnt; | |
1281 | u64 mac_tx_ctrl_pkt; | |
1282 | u64 mac_tx_lt_64b_pkts; | |
1283 | u64 mac_tx_lt_127b_pkts; | |
1284 | u64 mac_tx_lt_255b_pkts; | |
1285 | u64 mac_tx_lt_511b_pkts; | |
1286 | u64 mac_tx_lt_1023b_pkts; | |
1287 | u64 mac_tx_lt_1518b_pkts; | |
1288 | u64 mac_tx_gt_1518b_pkts; | |
1289 | u64 rsvd1[3]; | |
1290 | u64 mac_rx_frames; | |
1291 | u64 mac_rx_bytes; | |
1292 | u64 mac_rx_mcast_pkts; | |
1293 | u64 mac_rx_bcast_pkts; | |
1294 | u64 mac_rx_pause_cnt; | |
1295 | u64 mac_rx_ctrl_pkt; | |
1296 | u64 mac_rx_lt_64b_pkts; | |
1297 | u64 mac_rx_lt_127b_pkts; | |
1298 | u64 mac_rx_lt_255b_pkts; | |
1299 | u64 mac_rx_lt_511b_pkts; | |
1300 | u64 mac_rx_lt_1023b_pkts; | |
1301 | u64 mac_rx_lt_1518b_pkts; | |
1302 | u64 mac_rx_gt_1518b_pkts; | |
1303 | u64 rsvd2[3]; | |
1304 | u64 mac_rx_length_error; | |
1305 | u64 mac_rx_length_small; | |
1306 | u64 mac_rx_length_large; | |
1307 | u64 mac_rx_jabber; | |
1308 | u64 mac_rx_dropped; | |
1309 | u64 mac_rx_crc_error; | |
1310 | u64 mac_align_error; | |
1311 | }; | |
1312 | ||
1313 | struct qlcnic_esw_stats_le { | |
b6021212 AKS |
1314 | __le16 context_id; |
1315 | __le16 version; | |
1316 | __le16 size; | |
1317 | __le16 unused; | |
1318 | __le64 unicast_frames; | |
1319 | __le64 multicast_frames; | |
1320 | __le64 broadcast_frames; | |
1321 | __le64 dropped_frames; | |
1322 | __le64 errors; | |
1323 | __le64 local_frames; | |
1324 | __le64 numbytes; | |
1325 | __le64 rsvd[3]; | |
b1fc6d3c | 1326 | } __packed; |
b6021212 | 1327 | |
63507592 SS |
1328 | struct __qlcnic_esw_statistics { |
1329 | u16 context_id; | |
1330 | u16 version; | |
1331 | u16 size; | |
1332 | u16 unused; | |
1333 | u64 unicast_frames; | |
1334 | u64 multicast_frames; | |
1335 | u64 broadcast_frames; | |
1336 | u64 dropped_frames; | |
1337 | u64 errors; | |
1338 | u64 local_frames; | |
1339 | u64 numbytes; | |
1340 | u64 rsvd[3]; | |
1341 | }; | |
1342 | ||
b6021212 AKS |
1343 | struct qlcnic_esw_statistics { |
1344 | struct __qlcnic_esw_statistics rx; | |
1345 | struct __qlcnic_esw_statistics tx; | |
1346 | }; | |
1347 | ||
40522998 | 1348 | #define QLCNIC_DUMP_MASK_DEF 0x1f |
18f2f616 | 1349 | #define QLCNIC_FORCE_FW_DUMP_KEY 0xdeadfeed |
9d6a6440 AC |
1350 | #define QLCNIC_ENABLE_FW_DUMP 0xaddfeed |
1351 | #define QLCNIC_DISABLE_FW_DUMP 0xbadfeed | |
3d46512c | 1352 | #define QLCNIC_FORCE_FW_RESET 0xdeaddead |
b43e5ee7 SC |
1353 | #define QLCNIC_SET_QUIESCENT 0xadd00010 |
1354 | #define QLCNIC_RESET_QUIESCENT 0xadd00020 | |
18f2f616 | 1355 | |
7777de9a | 1356 | struct _cdrp_cmd { |
7e2cf4fe SC |
1357 | u32 num; |
1358 | u32 *arg; | |
7777de9a AC |
1359 | }; |
1360 | ||
1361 | struct qlcnic_cmd_args { | |
1362 | struct _cdrp_cmd req; | |
1363 | struct _cdrp_cmd rsp; | |
1364 | }; | |
1365 | ||
18f2f616 | 1366 | int qlcnic_fw_cmd_get_minidump_temp(struct qlcnic_adapter *adapter); |
7e610caa | 1367 | int qlcnic_fw_cmd_set_port(struct qlcnic_adapter *adapter, u32 config); |
af19b491 AKS |
1368 | int qlcnic_pci_mem_write_2M(struct qlcnic_adapter *, u64 off, u64 data); |
1369 | int qlcnic_pci_mem_read_2M(struct qlcnic_adapter *, u64 off, u64 *data); | |
897e8c7c DP |
1370 | void qlcnic_pci_camqm_read_2M(struct qlcnic_adapter *, u64, u64 *); |
1371 | void qlcnic_pci_camqm_write_2M(struct qlcnic_adapter *, u64, u64); | |
1372 | ||
1373 | #define ADDR_IN_RANGE(addr, low, high) \ | |
1374 | (((addr) < (high)) && ((addr) >= (low))) | |
af19b491 AKS |
1375 | |
1376 | #define QLCRD32(adapter, off) \ | |
7e2cf4fe SC |
1377 | (adapter->ahw->hw_ops->read_reg)(adapter, off) |
1378 | ||
af19b491 | 1379 | #define QLCWR32(adapter, off, val) \ |
7e2cf4fe | 1380 | adapter->ahw->hw_ops->write_reg(adapter, off, val) |
af19b491 AKS |
1381 | |
1382 | int qlcnic_pcie_sem_lock(struct qlcnic_adapter *, int, u32); | |
1383 | void qlcnic_pcie_sem_unlock(struct qlcnic_adapter *, int); | |
1384 | ||
1385 | #define qlcnic_rom_lock(a) \ | |
1386 | qlcnic_pcie_sem_lock((a), 2, QLCNIC_ROM_LOCK_ID) | |
1387 | #define qlcnic_rom_unlock(a) \ | |
1388 | qlcnic_pcie_sem_unlock((a), 2) | |
1389 | #define qlcnic_phy_lock(a) \ | |
1390 | qlcnic_pcie_sem_lock((a), 3, QLCNIC_PHY_LOCK_ID) | |
1391 | #define qlcnic_phy_unlock(a) \ | |
1392 | qlcnic_pcie_sem_unlock((a), 3) | |
af19b491 AKS |
1393 | #define qlcnic_sw_lock(a) \ |
1394 | qlcnic_pcie_sem_lock((a), 6, 0) | |
1395 | #define qlcnic_sw_unlock(a) \ | |
1396 | qlcnic_pcie_sem_unlock((a), 6) | |
1397 | #define crb_win_lock(a) \ | |
1398 | qlcnic_pcie_sem_lock((a), 7, QLCNIC_CRB_WIN_LOCK_ID) | |
1399 | #define crb_win_unlock(a) \ | |
1400 | qlcnic_pcie_sem_unlock((a), 7) | |
1401 | ||
728a98b8 SC |
1402 | #define __QLCNIC_MAX_LED_RATE 0xf |
1403 | #define __QLCNIC_MAX_LED_STATE 0x2 | |
1404 | ||
58634e74 SC |
1405 | #define MAX_CTL_CHECK 1000 |
1406 | ||
af19b491 | 1407 | int qlcnic_wol_supported(struct qlcnic_adapter *adapter); |
b5e5492c AKS |
1408 | void qlcnic_prune_lb_filters(struct qlcnic_adapter *adapter); |
1409 | void qlcnic_delete_lb_filters(struct qlcnic_adapter *adapter); | |
18f2f616 | 1410 | int qlcnic_dump_fw(struct qlcnic_adapter *); |
af19b491 AKS |
1411 | |
1412 | /* Functions from qlcnic_init.c */ | |
13159183 | 1413 | void qlcnic_schedule_work(struct qlcnic_adapter *, work_func_t, int); |
af19b491 AKS |
1414 | int qlcnic_load_firmware(struct qlcnic_adapter *adapter); |
1415 | int qlcnic_need_fw_reset(struct qlcnic_adapter *adapter); | |
1416 | void qlcnic_request_firmware(struct qlcnic_adapter *adapter); | |
1417 | void qlcnic_release_firmware(struct qlcnic_adapter *adapter); | |
1418 | int qlcnic_pinit_from_rom(struct qlcnic_adapter *adapter); | |
b3a24649 | 1419 | int qlcnic_setup_idc_param(struct qlcnic_adapter *adapter); |
8f891387 | 1420 | int qlcnic_check_flash_fw_ver(struct qlcnic_adapter *adapter); |
af19b491 | 1421 | |
18f2f616 | 1422 | int qlcnic_rom_fast_read(struct qlcnic_adapter *adapter, u32 addr, u32 *valp); |
af19b491 AKS |
1423 | int qlcnic_rom_fast_read_words(struct qlcnic_adapter *adapter, int addr, |
1424 | u8 *bytes, size_t size); | |
1425 | int qlcnic_alloc_sw_resources(struct qlcnic_adapter *adapter); | |
1426 | void qlcnic_free_sw_resources(struct qlcnic_adapter *adapter); | |
1427 | ||
15087c2b | 1428 | void __iomem *qlcnic_get_ioaddr(struct qlcnic_hardware_context *, u32); |
af19b491 AKS |
1429 | |
1430 | int qlcnic_alloc_hw_resources(struct qlcnic_adapter *adapter); | |
1431 | void qlcnic_free_hw_resources(struct qlcnic_adapter *adapter); | |
1432 | ||
8a15ad1f AKS |
1433 | int qlcnic_fw_create_ctx(struct qlcnic_adapter *adapter); |
1434 | void qlcnic_fw_destroy_ctx(struct qlcnic_adapter *adapter); | |
1435 | ||
1436 | void qlcnic_reset_rx_buffers_list(struct qlcnic_adapter *adapter); | |
af19b491 AKS |
1437 | void qlcnic_release_rx_buffers(struct qlcnic_adapter *adapter); |
1438 | void qlcnic_release_tx_buffers(struct qlcnic_adapter *adapter); | |
1439 | ||
d4066833 | 1440 | int qlcnic_check_fw_status(struct qlcnic_adapter *adapter); |
af19b491 | 1441 | void qlcnic_watchdog_task(struct work_struct *work); |
b1fc6d3c | 1442 | void qlcnic_post_rx_buffers(struct qlcnic_adapter *adapter, |
4be41e92 | 1443 | struct qlcnic_host_rds_ring *rds_ring, u8 ring_id); |
af19b491 AKS |
1444 | int qlcnic_process_rcv_ring(struct qlcnic_host_sds_ring *sds_ring, int max); |
1445 | void qlcnic_set_multi(struct net_device *netdev); | |
1446 | void qlcnic_free_mac_list(struct qlcnic_adapter *adapter); | |
af19b491 AKS |
1447 | |
1448 | int qlcnic_fw_cmd_set_mtu(struct qlcnic_adapter *adapter, int mtu); | |
1449 | int qlcnic_change_mtu(struct net_device *netdev, int new_mtu); | |
c8f44aff MM |
1450 | netdev_features_t qlcnic_fix_features(struct net_device *netdev, |
1451 | netdev_features_t features); | |
1452 | int qlcnic_set_features(struct net_device *netdev, netdev_features_t features); | |
2e9d722d | 1453 | int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable); |
af19b491 | 1454 | int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter); |
5ad6ff9d | 1455 | void qlcnic_update_cmd_producer(struct qlcnic_host_tx_ring *); |
22c8c934 SC |
1456 | |
1457 | /* Functions from qlcnic_ethtool.c */ | |
1458 | int qlcnic_check_loopback_buff(unsigned char *data, u8 mac[]); | |
af19b491 AKS |
1459 | |
1460 | /* Functions from qlcnic_main.c */ | |
1461 | int qlcnic_reset_context(struct qlcnic_adapter *); | |
7eb9855d AKS |
1462 | void qlcnic_diag_free_res(struct net_device *netdev, int max_sds_rings); |
1463 | int qlcnic_diag_alloc_res(struct net_device *netdev, int test); | |
cdaff185 | 1464 | netdev_tx_t qlcnic_xmit_frame(struct sk_buff *skb, struct net_device *netdev); |
319ecf12 SC |
1465 | int qlcnic_set_max_rss(struct qlcnic_adapter *, u8, size_t); |
1466 | int qlcnic_validate_max_rss(u8, u8); | |
e5dcf6dc | 1467 | void qlcnic_alloc_lb_filters_mem(struct qlcnic_adapter *adapter); |
7f966452 | 1468 | int qlcnic_enable_msix(struct qlcnic_adapter *, u32); |
af19b491 | 1469 | |
2e9d722d | 1470 | /* eSwitch management functions */ |
4e8acb01 RB |
1471 | int qlcnic_config_switch_port(struct qlcnic_adapter *, |
1472 | struct qlcnic_esw_func_cfg *); | |
1473 | int qlcnic_get_eswitch_port_config(struct qlcnic_adapter *, | |
1474 | struct qlcnic_esw_func_cfg *); | |
2e9d722d | 1475 | int qlcnic_config_port_mirroring(struct qlcnic_adapter *, u8, u8, u8); |
b6021212 AKS |
1476 | int qlcnic_get_port_stats(struct qlcnic_adapter *, const u8, const u8, |
1477 | struct __qlcnic_esw_statistics *); | |
1478 | int qlcnic_get_eswitch_stats(struct qlcnic_adapter *, const u8, u8, | |
1479 | struct __qlcnic_esw_statistics *); | |
1480 | int qlcnic_clear_esw_stats(struct qlcnic_adapter *adapter, u8, u8, u8); | |
54a8997c | 1481 | int qlcnic_get_mac_stats(struct qlcnic_adapter *, struct qlcnic_mac_statistics *); |
2e9d722d | 1482 | |
7e2cf4fe | 1483 | void qlcnic_free_mbx_args(struct qlcnic_cmd_args *cmd); |
7e2cf4fe | 1484 | |
c70001a9 SC |
1485 | int qlcnic_alloc_sds_rings(struct qlcnic_recv_context *, int); |
1486 | void qlcnic_free_sds_rings(struct qlcnic_recv_context *); | |
7f966452 | 1487 | void qlcnic_advert_link_change(struct qlcnic_adapter *, int); |
c70001a9 SC |
1488 | void qlcnic_free_tx_rings(struct qlcnic_adapter *); |
1489 | int qlcnic_alloc_tx_rings(struct qlcnic_adapter *, struct net_device *); | |
1490 | ||
ec079a07 SC |
1491 | void qlcnic_create_sysfs_entries(struct qlcnic_adapter *adapter); |
1492 | void qlcnic_remove_sysfs_entries(struct qlcnic_adapter *adapter); | |
1493 | void qlcnic_create_diag_entries(struct qlcnic_adapter *adapter); | |
1494 | void qlcnic_remove_diag_entries(struct qlcnic_adapter *adapter); | |
7e2cf4fe SC |
1495 | void qlcnic_82xx_add_sysfs(struct qlcnic_adapter *adapter); |
1496 | void qlcnic_82xx_remove_sysfs(struct qlcnic_adapter *adapter); | |
1497 | ||
ec079a07 SC |
1498 | int qlcnicvf_config_bridged_mode(struct qlcnic_adapter *, u32); |
1499 | int qlcnicvf_config_led(struct qlcnic_adapter *, u32, u32); | |
1500 | void qlcnic_set_vlan_config(struct qlcnic_adapter *, | |
1501 | struct qlcnic_esw_func_cfg *); | |
1502 | void qlcnic_set_eswitch_port_features(struct qlcnic_adapter *, | |
1503 | struct qlcnic_esw_func_cfg *); | |
319ecf12 SC |
1504 | void __qlcnic_down(struct qlcnic_adapter *, struct net_device *); |
1505 | void qlcnic_detach(struct qlcnic_adapter *); | |
1506 | void qlcnic_teardown_intr(struct qlcnic_adapter *); | |
1507 | int qlcnic_attach(struct qlcnic_adapter *); | |
1508 | int __qlcnic_up(struct qlcnic_adapter *, struct net_device *); | |
1509 | void qlcnic_restore_indev_addr(struct net_device *, unsigned long); | |
1510 | ||
ec079a07 | 1511 | |
af19b491 AKS |
1512 | /* |
1513 | * QLOGIC Board information | |
1514 | */ | |
1515 | ||
02420be6 | 1516 | #define QLCNIC_MAX_BOARD_NAME_LEN 100 |
22999798 | 1517 | struct qlcnic_board_info { |
af19b491 AKS |
1518 | unsigned short vendor; |
1519 | unsigned short device; | |
1520 | unsigned short sub_vendor; | |
1521 | unsigned short sub_device; | |
1522 | char short_name[QLCNIC_MAX_BOARD_NAME_LEN]; | |
1523 | }; | |
1524 | ||
af19b491 AKS |
1525 | static inline u32 qlcnic_tx_avail(struct qlcnic_host_tx_ring *tx_ring) |
1526 | { | |
036d61f0 | 1527 | if (likely(tx_ring->producer < tx_ring->sw_consumer)) |
af19b491 AKS |
1528 | return tx_ring->sw_consumer - tx_ring->producer; |
1529 | else | |
1530 | return tx_ring->sw_consumer + tx_ring->num_desc - | |
1531 | tx_ring->producer; | |
1532 | } | |
1533 | ||
7e2cf4fe SC |
1534 | struct qlcnic_nic_template { |
1535 | int (*config_bridged_mode) (struct qlcnic_adapter *, u32); | |
1536 | int (*config_led) (struct qlcnic_adapter *, u32, u32); | |
1537 | int (*start_firmware) (struct qlcnic_adapter *); | |
1538 | int (*init_driver) (struct qlcnic_adapter *); | |
1539 | void (*request_reset) (struct qlcnic_adapter *, u32); | |
1540 | void (*cancel_idc_work) (struct qlcnic_adapter *); | |
1541 | int (*napi_add)(struct qlcnic_adapter *, struct net_device *); | |
4be41e92 | 1542 | void (*napi_del)(struct qlcnic_adapter *); |
7e2cf4fe SC |
1543 | void (*config_ipaddr)(struct qlcnic_adapter *, __be32, int); |
1544 | irqreturn_t (*clear_legacy_intr)(struct qlcnic_adapter *); | |
1545 | }; | |
1546 | ||
1547 | /* Adapter hardware abstraction */ | |
1548 | struct qlcnic_hardware_ops { | |
1549 | void (*read_crb) (struct qlcnic_adapter *, char *, loff_t, size_t); | |
1550 | void (*write_crb) (struct qlcnic_adapter *, char *, loff_t, size_t); | |
1551 | int (*read_reg) (struct qlcnic_adapter *, ulong); | |
1552 | int (*write_reg) (struct qlcnic_adapter *, ulong, u32); | |
1553 | void (*get_ocm_win) (struct qlcnic_hardware_context *); | |
1554 | int (*get_mac_address) (struct qlcnic_adapter *, u8 *); | |
1555 | int (*setup_intr) (struct qlcnic_adapter *, u8); | |
1556 | int (*alloc_mbx_args)(struct qlcnic_cmd_args *, | |
1557 | struct qlcnic_adapter *, u32); | |
1558 | int (*mbx_cmd) (struct qlcnic_adapter *, struct qlcnic_cmd_args *); | |
1559 | void (*get_func_no) (struct qlcnic_adapter *); | |
1560 | int (*api_lock) (struct qlcnic_adapter *); | |
1561 | void (*api_unlock) (struct qlcnic_adapter *); | |
1562 | void (*add_sysfs) (struct qlcnic_adapter *); | |
1563 | void (*remove_sysfs) (struct qlcnic_adapter *); | |
1564 | void (*process_lb_rcv_ring_diag) (struct qlcnic_host_sds_ring *); | |
1565 | int (*create_rx_ctx) (struct qlcnic_adapter *); | |
1566 | int (*create_tx_ctx) (struct qlcnic_adapter *, | |
1567 | struct qlcnic_host_tx_ring *, int); | |
1568 | int (*setup_link_event) (struct qlcnic_adapter *, int); | |
1569 | int (*get_nic_info) (struct qlcnic_adapter *, struct qlcnic_info *, u8); | |
1570 | int (*get_pci_info) (struct qlcnic_adapter *, struct qlcnic_pci_info *); | |
1571 | int (*set_nic_info) (struct qlcnic_adapter *, struct qlcnic_info *); | |
1572 | int (*change_macvlan) (struct qlcnic_adapter *, u8*, __le16, u8); | |
1573 | void (*napi_enable) (struct qlcnic_adapter *); | |
1574 | void (*napi_disable) (struct qlcnic_adapter *); | |
1575 | void (*config_intr_coal) (struct qlcnic_adapter *); | |
1576 | int (*config_rss) (struct qlcnic_adapter *, int); | |
1577 | int (*config_hw_lro) (struct qlcnic_adapter *, int); | |
1578 | int (*config_loopback) (struct qlcnic_adapter *, u8); | |
1579 | int (*clear_loopback) (struct qlcnic_adapter *, u8); | |
1580 | int (*config_promisc_mode) (struct qlcnic_adapter *, u32); | |
1581 | void (*change_l2_filter) (struct qlcnic_adapter *, u64 *, __le16); | |
1582 | int (*get_board_info) (struct qlcnic_adapter *); | |
1583 | }; | |
1584 | ||
1585 | extern struct qlcnic_nic_template qlcnic_vf_ops; | |
1586 | ||
1587 | static inline int qlcnic_start_firmware(struct qlcnic_adapter *adapter) | |
1588 | { | |
1589 | return adapter->nic_ops->start_firmware(adapter); | |
1590 | } | |
1591 | ||
1592 | static inline void qlcnic_read_crb(struct qlcnic_adapter *adapter, char *buf, | |
1593 | loff_t offset, size_t size) | |
1594 | { | |
1595 | adapter->ahw->hw_ops->read_crb(adapter, buf, offset, size); | |
1596 | } | |
1597 | ||
1598 | static inline void qlcnic_write_crb(struct qlcnic_adapter *adapter, char *buf, | |
1599 | loff_t offset, size_t size) | |
1600 | { | |
1601 | adapter->ahw->hw_ops->write_crb(adapter, buf, offset, size); | |
1602 | } | |
1603 | ||
7f966452 | 1604 | static inline int qlcnic_hw_read_wx_2M(struct qlcnic_adapter *adapter, |
7e2cf4fe SC |
1605 | ulong off) |
1606 | { | |
1607 | return adapter->ahw->hw_ops->read_reg(adapter, off); | |
1608 | } | |
1609 | ||
1610 | static inline int qlcnic_hw_write_wx_2M(struct qlcnic_adapter *adapter, | |
1611 | ulong off, u32 data) | |
1612 | { | |
1613 | return adapter->ahw->hw_ops->write_reg(adapter, off, data); | |
1614 | } | |
1615 | ||
1616 | static inline int qlcnic_get_mac_address(struct qlcnic_adapter *adapter, | |
1617 | u8 *mac) | |
1618 | { | |
1619 | return adapter->ahw->hw_ops->get_mac_address(adapter, mac); | |
1620 | } | |
1621 | ||
1622 | static inline int qlcnic_setup_intr(struct qlcnic_adapter *adapter, u8 num_intr) | |
1623 | { | |
1624 | return adapter->ahw->hw_ops->setup_intr(adapter, num_intr); | |
1625 | } | |
1626 | ||
1627 | static inline int qlcnic_alloc_mbx_args(struct qlcnic_cmd_args *mbx, | |
1628 | struct qlcnic_adapter *adapter, u32 arg) | |
1629 | { | |
1630 | return adapter->ahw->hw_ops->alloc_mbx_args(mbx, adapter, arg); | |
1631 | } | |
1632 | ||
1633 | static inline int qlcnic_issue_cmd(struct qlcnic_adapter *adapter, | |
1634 | struct qlcnic_cmd_args *cmd) | |
1635 | { | |
1636 | return adapter->ahw->hw_ops->mbx_cmd(adapter, cmd); | |
1637 | } | |
1638 | ||
1639 | static inline void qlcnic_get_func_no(struct qlcnic_adapter *adapter) | |
1640 | { | |
1641 | adapter->ahw->hw_ops->get_func_no(adapter); | |
1642 | } | |
1643 | ||
1644 | static inline int qlcnic_api_lock(struct qlcnic_adapter *adapter) | |
1645 | { | |
1646 | return adapter->ahw->hw_ops->api_lock(adapter); | |
1647 | } | |
1648 | ||
1649 | static inline void qlcnic_api_unlock(struct qlcnic_adapter *adapter) | |
1650 | { | |
1651 | adapter->ahw->hw_ops->api_unlock(adapter); | |
1652 | } | |
1653 | ||
1654 | static inline void qlcnic_add_sysfs(struct qlcnic_adapter *adapter) | |
1655 | { | |
1656 | adapter->ahw->hw_ops->add_sysfs(adapter); | |
1657 | } | |
1658 | ||
1659 | static inline void qlcnic_remove_sysfs(struct qlcnic_adapter *adapter) | |
1660 | { | |
1661 | adapter->ahw->hw_ops->remove_sysfs(adapter); | |
1662 | } | |
1663 | ||
1664 | static inline void | |
1665 | qlcnic_process_rcv_ring_diag(struct qlcnic_host_sds_ring *sds_ring) | |
1666 | { | |
1667 | sds_ring->adapter->ahw->hw_ops->process_lb_rcv_ring_diag(sds_ring); | |
1668 | } | |
1669 | ||
1670 | static inline int qlcnic_fw_cmd_create_rx_ctx(struct qlcnic_adapter *adapter) | |
1671 | { | |
1672 | return adapter->ahw->hw_ops->create_rx_ctx(adapter); | |
1673 | } | |
1674 | ||
1675 | static inline int qlcnic_fw_cmd_create_tx_ctx(struct qlcnic_adapter *adapter, | |
1676 | struct qlcnic_host_tx_ring *ptr, | |
1677 | int ring) | |
1678 | { | |
1679 | return adapter->ahw->hw_ops->create_tx_ctx(adapter, ptr, ring); | |
1680 | } | |
1681 | ||
1682 | static inline int qlcnic_linkevent_request(struct qlcnic_adapter *adapter, | |
1683 | int enable) | |
1684 | { | |
1685 | return adapter->ahw->hw_ops->setup_link_event(adapter, enable); | |
1686 | } | |
1687 | ||
1688 | static inline int qlcnic_get_nic_info(struct qlcnic_adapter *adapter, | |
1689 | struct qlcnic_info *info, u8 id) | |
1690 | { | |
1691 | return adapter->ahw->hw_ops->get_nic_info(adapter, info, id); | |
1692 | } | |
1693 | ||
1694 | static inline int qlcnic_get_pci_info(struct qlcnic_adapter *adapter, | |
1695 | struct qlcnic_pci_info *info) | |
1696 | { | |
1697 | return adapter->ahw->hw_ops->get_pci_info(adapter, info); | |
1698 | } | |
1699 | ||
1700 | static inline int qlcnic_set_nic_info(struct qlcnic_adapter *adapter, | |
1701 | struct qlcnic_info *info) | |
1702 | { | |
1703 | return adapter->ahw->hw_ops->set_nic_info(adapter, info); | |
1704 | } | |
1705 | ||
1706 | static inline int qlcnic_sre_macaddr_change(struct qlcnic_adapter *adapter, | |
1707 | u8 *addr, __le16 id, u8 cmd) | |
1708 | { | |
1709 | return adapter->ahw->hw_ops->change_macvlan(adapter, addr, id, cmd); | |
1710 | } | |
1711 | ||
1712 | static inline int qlcnic_napi_add(struct qlcnic_adapter *adapter, | |
1713 | struct net_device *netdev) | |
1714 | { | |
1715 | return adapter->nic_ops->napi_add(adapter, netdev); | |
1716 | } | |
1717 | ||
4be41e92 SC |
1718 | static inline void qlcnic_napi_del(struct qlcnic_adapter *adapter) |
1719 | { | |
1720 | adapter->nic_ops->napi_del(adapter); | |
1721 | } | |
1722 | ||
7e2cf4fe SC |
1723 | static inline void qlcnic_napi_enable(struct qlcnic_adapter *adapter) |
1724 | { | |
1725 | adapter->ahw->hw_ops->napi_enable(adapter); | |
1726 | } | |
1727 | ||
1728 | static inline void qlcnic_napi_disable(struct qlcnic_adapter *adapter) | |
1729 | { | |
1730 | adapter->ahw->hw_ops->napi_disable(adapter); | |
1731 | } | |
1732 | ||
1733 | static inline void qlcnic_config_intr_coalesce(struct qlcnic_adapter *adapter) | |
1734 | { | |
1735 | adapter->ahw->hw_ops->config_intr_coal(adapter); | |
1736 | } | |
1737 | ||
1738 | static inline int qlcnic_config_rss(struct qlcnic_adapter *adapter, int enable) | |
1739 | { | |
1740 | return adapter->ahw->hw_ops->config_rss(adapter, enable); | |
1741 | } | |
1742 | ||
1743 | static inline int qlcnic_config_hw_lro(struct qlcnic_adapter *adapter, | |
1744 | int enable) | |
1745 | { | |
1746 | return adapter->ahw->hw_ops->config_hw_lro(adapter, enable); | |
1747 | } | |
1748 | ||
1749 | static inline int qlcnic_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode) | |
1750 | { | |
1751 | return adapter->ahw->hw_ops->config_loopback(adapter, mode); | |
1752 | } | |
1753 | ||
1754 | static inline int qlcnic_clear_lb_mode(struct qlcnic_adapter *adapter, u8 mode) | |
1755 | { | |
1756 | return adapter->ahw->hw_ops->config_loopback(adapter, mode); | |
1757 | } | |
1758 | ||
1759 | static inline int qlcnic_nic_set_promisc(struct qlcnic_adapter *adapter, | |
1760 | u32 mode) | |
1761 | { | |
1762 | return adapter->ahw->hw_ops->config_promisc_mode(adapter, mode); | |
1763 | } | |
1764 | ||
1765 | static inline void qlcnic_change_filter(struct qlcnic_adapter *adapter, | |
1766 | u64 *addr, __le16 id) | |
1767 | { | |
1768 | adapter->ahw->hw_ops->change_l2_filter(adapter, addr, id); | |
1769 | } | |
1770 | ||
1771 | static inline int qlcnic_get_board_info(struct qlcnic_adapter *adapter) | |
1772 | { | |
1773 | return adapter->ahw->hw_ops->get_board_info(adapter); | |
1774 | } | |
1775 | ||
1776 | static inline void qlcnic_dev_request_reset(struct qlcnic_adapter *adapter, | |
1777 | u32 key) | |
1778 | { | |
1779 | adapter->nic_ops->request_reset(adapter, key); | |
1780 | } | |
1781 | ||
1782 | static inline void qlcnic_cancel_idc_work(struct qlcnic_adapter *adapter) | |
1783 | { | |
1784 | adapter->nic_ops->cancel_idc_work(adapter); | |
1785 | } | |
1786 | ||
1787 | static inline irqreturn_t | |
1788 | qlcnic_clear_legacy_intr(struct qlcnic_adapter *adapter) | |
1789 | { | |
1790 | return adapter->nic_ops->clear_legacy_intr(adapter); | |
1791 | } | |
1792 | ||
1793 | static inline int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state, | |
1794 | u32 rate) | |
1795 | { | |
1796 | return adapter->nic_ops->config_led(adapter, state, rate); | |
1797 | } | |
1798 | ||
1799 | static inline void qlcnic_config_ipaddr(struct qlcnic_adapter *adapter, | |
1800 | __be32 ip, int cmd) | |
1801 | { | |
1802 | adapter->nic_ops->config_ipaddr(adapter, ip, cmd); | |
1803 | } | |
1804 | ||
c70001a9 SC |
1805 | static inline void qlcnic_disable_int(struct qlcnic_host_sds_ring *sds_ring) |
1806 | { | |
1807 | writel(0, sds_ring->crb_intr_mask); | |
1808 | } | |
1809 | ||
1810 | static inline void qlcnic_enable_int(struct qlcnic_host_sds_ring *sds_ring) | |
1811 | { | |
1812 | struct qlcnic_adapter *adapter = sds_ring->adapter; | |
1813 | ||
1814 | writel(0x1, sds_ring->crb_intr_mask); | |
1815 | ||
1816 | if (!QLCNIC_IS_MSI_FAMILY(adapter)) | |
1817 | writel(0xfbff, adapter->tgt_mask_reg); | |
1818 | } | |
1819 | ||
af19b491 | 1820 | extern const struct ethtool_ops qlcnic_ethtool_ops; |
b43e5ee7 | 1821 | extern const struct ethtool_ops qlcnic_ethtool_failed_ops; |
af19b491 | 1822 | |
65b5b420 | 1823 | #define QLCDB(adapter, lvl, _fmt, _args...) do { \ |
79788450 | 1824 | if (NETIF_MSG_##lvl & adapter->ahw->msg_enable) \ |
65b5b420 AKS |
1825 | printk(KERN_INFO "%s: %s: " _fmt, \ |
1826 | dev_name(&adapter->pdev->dev), \ | |
1827 | __func__, ##_args); \ | |
1828 | } while (0) | |
1829 | ||
7f966452 | 1830 | #define PCI_DEVICE_ID_QLOGIC_QLE834X 0x8030 |
97ee45eb SC |
1831 | #define PCI_DEVICE_ID_QLOGIC_QLE824X 0x8020 |
1832 | static inline bool qlcnic_82xx_check(struct qlcnic_adapter *adapter) | |
1833 | { | |
1834 | unsigned short device = adapter->pdev->device; | |
1835 | return (device == PCI_DEVICE_ID_QLOGIC_QLE824X) ? true : false; | |
1836 | } | |
1837 | ||
7f966452 SC |
1838 | static inline bool qlcnic_83xx_check(struct qlcnic_adapter *adapter) |
1839 | { | |
1840 | unsigned short device = adapter->pdev->device; | |
1841 | return (device == PCI_DEVICE_ID_QLOGIC_QLE834X) ? true : false; | |
1842 | } | |
1843 | ||
1844 | ||
af19b491 | 1845 | #endif /* __QLCNIC_H_ */ |