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Commit | Line | Data |
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af19b491 | 1 | /* |
40839129 | 2 | * QLogic qlcnic NIC Driver |
577ae39d | 3 | * Copyright (c) 2009-2013 QLogic Corporation |
af19b491 | 4 | * |
40839129 | 5 | * See LICENSE.qlcnic for copyright and licensing details. |
af19b491 AKS |
6 | */ |
7 | ||
8 | #ifndef _QLCNIC_H_ | |
9 | #define _QLCNIC_H_ | |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/kernel.h> | |
13 | #include <linux/types.h> | |
14 | #include <linux/ioport.h> | |
15 | #include <linux/pci.h> | |
16 | #include <linux/netdevice.h> | |
17 | #include <linux/etherdevice.h> | |
18 | #include <linux/ip.h> | |
19 | #include <linux/in.h> | |
20 | #include <linux/tcp.h> | |
21 | #include <linux/skbuff.h> | |
22 | #include <linux/firmware.h> | |
af19b491 AKS |
23 | #include <linux/ethtool.h> |
24 | #include <linux/mii.h> | |
25 | #include <linux/timer.h> | |
26 | ||
27 | #include <linux/vmalloc.h> | |
28 | ||
29 | #include <linux/io.h> | |
30 | #include <asm/byteorder.h> | |
b9796a14 AC |
31 | #include <linux/bitops.h> |
32 | #include <linux/if_vlan.h> | |
af19b491 AKS |
33 | |
34 | #include "qlcnic_hdr.h" | |
7f966452 SC |
35 | #include "qlcnic_hw.h" |
36 | #include "qlcnic_83xx_hw.h" | |
14d385b9 | 37 | #include "qlcnic_dcb.h" |
af19b491 AKS |
38 | |
39 | #define _QLCNIC_LINUX_MAJOR 5 | |
4cffa13d | 40 | #define _QLCNIC_LINUX_MINOR 3 |
60b4a1f3 HM |
41 | #define _QLCNIC_LINUX_SUBVERSION 51 |
42 | #define QLCNIC_LINUX_VERSIONID "5.3.51" | |
96f8118c | 43 | #define QLCNIC_DRV_IDC_VER 0x01 |
d4066833 SC |
44 | #define QLCNIC_DRIVER_VERSION ((_QLCNIC_LINUX_MAJOR << 16) |\ |
45 | (_QLCNIC_LINUX_MINOR << 8) | (_QLCNIC_LINUX_SUBVERSION)) | |
af19b491 AKS |
46 | |
47 | #define QLCNIC_VERSION_CODE(a, b, c) (((a) << 24) + ((b) << 16) + (c)) | |
48 | #define _major(v) (((v) >> 24) & 0xff) | |
49 | #define _minor(v) (((v) >> 16) & 0xff) | |
50 | #define _build(v) ((v) & 0xffff) | |
51 | ||
52 | /* version in image has weird encoding: | |
53 | * 7:0 - major | |
54 | * 15:8 - minor | |
55 | * 31:16 - build (little endian) | |
56 | */ | |
57 | #define QLCNIC_DECODE_VERSION(v) \ | |
58 | QLCNIC_VERSION_CODE(((v) & 0xff), (((v) >> 8) & 0xff), ((v) >> 16)) | |
59 | ||
8f891387 | 60 | #define QLCNIC_MIN_FW_VERSION QLCNIC_VERSION_CODE(4, 4, 2) |
af19b491 AKS |
61 | #define QLCNIC_NUM_FLASH_SECTORS (64) |
62 | #define QLCNIC_FLASH_SECTOR_SIZE (64 * 1024) | |
63 | #define QLCNIC_FLASH_TOTAL_SIZE (QLCNIC_NUM_FLASH_SECTORS \ | |
64 | * QLCNIC_FLASH_SECTOR_SIZE) | |
65 | ||
66 | #define RCV_DESC_RINGSIZE(rds_ring) \ | |
67 | (sizeof(struct rcv_desc) * (rds_ring)->num_desc) | |
68 | #define RCV_BUFF_RINGSIZE(rds_ring) \ | |
69 | (sizeof(struct qlcnic_rx_buffer) * rds_ring->num_desc) | |
70 | #define STATUS_DESC_RINGSIZE(sds_ring) \ | |
71 | (sizeof(struct status_desc) * (sds_ring)->num_desc) | |
72 | #define TX_BUFF_RINGSIZE(tx_ring) \ | |
73 | (sizeof(struct qlcnic_cmd_buffer) * tx_ring->num_desc) | |
74 | #define TX_DESC_RINGSIZE(tx_ring) \ | |
75 | (sizeof(struct cmd_desc_type0) * tx_ring->num_desc) | |
76 | ||
77 | #define QLCNIC_P3P_A0 0x50 | |
a2050c7e | 78 | #define QLCNIC_P3P_C0 0x58 |
af19b491 AKS |
79 | |
80 | #define QLCNIC_IS_REVISION_P3P(REVISION) (REVISION >= QLCNIC_P3P_A0) | |
81 | ||
82 | #define FIRST_PAGE_GROUP_START 0 | |
83 | #define FIRST_PAGE_GROUP_END 0x100000 | |
84 | ||
ff1b1bf8 SV |
85 | #define P3P_MAX_MTU (9600) |
86 | #define P3P_MIN_MTU (68) | |
af19b491 AKS |
87 | #define QLCNIC_MAX_ETHERHDR 32 /* This contains some padding */ |
88 | ||
ff1b1bf8 SV |
89 | #define QLCNIC_P3P_RX_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + ETH_DATA_LEN) |
90 | #define QLCNIC_P3P_RX_JUMBO_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + P3P_MAX_MTU) | |
af19b491 AKS |
91 | #define QLCNIC_CT_DEFAULT_RX_BUF_LEN 2048 |
92 | #define QLCNIC_LRO_BUFFER_EXTRA 2048 | |
93 | ||
af19b491 | 94 | /* Tx defines */ |
91a403ca | 95 | #define QLCNIC_MAX_FRAGS_PER_TX 14 |
ef71ff83 RB |
96 | #define MAX_TSO_HEADER_DESC 2 |
97 | #define MGMT_CMD_DESC_RESV 4 | |
98 | #define TX_STOP_THRESH ((MAX_SKB_FRAGS >> 2) + MAX_TSO_HEADER_DESC \ | |
99 | + MGMT_CMD_DESC_RESV) | |
af19b491 | 100 | #define QLCNIC_MAX_TX_TIMEOUTS 2 |
012ec812 HM |
101 | #define QLCNIC_MAX_TX_RINGS 8 |
102 | #define QLCNIC_MAX_SDS_RINGS 8 | |
103 | ||
af19b491 AKS |
104 | /* |
105 | * Following are the states of the Phantom. Phantom will set them and | |
106 | * Host will read to check if the fields are correct. | |
107 | */ | |
108 | #define PHAN_INITIALIZE_FAILED 0xffff | |
109 | #define PHAN_INITIALIZE_COMPLETE 0xff01 | |
110 | ||
111 | /* Host writes the following to notify that it has done the init-handshake */ | |
112 | #define PHAN_INITIALIZE_ACK 0xf00f | |
113 | #define PHAN_PEG_RCV_INITIALIZED 0xff01 | |
114 | ||
115 | #define NUM_RCV_DESC_RINGS 3 | |
af19b491 AKS |
116 | |
117 | #define RCV_RING_NORMAL 0 | |
118 | #define RCV_RING_JUMBO 1 | |
af19b491 AKS |
119 | |
120 | #define MIN_CMD_DESCRIPTORS 64 | |
121 | #define MIN_RCV_DESCRIPTORS 64 | |
122 | #define MIN_JUMBO_DESCRIPTORS 32 | |
123 | ||
124 | #define MAX_CMD_DESCRIPTORS 1024 | |
125 | #define MAX_RCV_DESCRIPTORS_1G 4096 | |
126 | #define MAX_RCV_DESCRIPTORS_10G 8192 | |
90d19005 | 127 | #define MAX_RCV_DESCRIPTORS_VF 2048 |
af19b491 AKS |
128 | #define MAX_JUMBO_RCV_DESCRIPTORS_1G 512 |
129 | #define MAX_JUMBO_RCV_DESCRIPTORS_10G 1024 | |
af19b491 AKS |
130 | |
131 | #define DEFAULT_RCV_DESCRIPTORS_1G 2048 | |
132 | #define DEFAULT_RCV_DESCRIPTORS_10G 4096 | |
90d19005 | 133 | #define DEFAULT_RCV_DESCRIPTORS_VF 1024 |
251b036a | 134 | #define MAX_RDS_RINGS 2 |
af19b491 AKS |
135 | |
136 | #define get_next_index(index, length) \ | |
137 | (((index) + 1) & ((length) - 1)) | |
138 | ||
af19b491 AKS |
139 | /* |
140 | * Following data structures describe the descriptors that will be used. | |
141 | * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when | |
142 | * we are doing LSO (above the 1500 size packet) only. | |
143 | */ | |
af19b491 AKS |
144 | struct cmd_desc_type0 { |
145 | u8 tcp_hdr_offset; /* For LSO only */ | |
146 | u8 ip_hdr_offset; /* For LSO only */ | |
147 | __le16 flags_opcode; /* 15:13 unused, 12:7 opcode, 6:0 flags */ | |
148 | __le32 nfrags__length; /* 31:8 total len, 7:0 frag count */ | |
149 | ||
150 | __le64 addr_buffer2; | |
151 | ||
152 | __le16 reference_handle; | |
153 | __le16 mss; | |
154 | u8 port_ctxid; /* 7:4 ctxid 3:0 port */ | |
155 | u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */ | |
156 | __le16 conn_id; /* IPSec offoad only */ | |
157 | ||
158 | __le64 addr_buffer3; | |
159 | __le64 addr_buffer1; | |
160 | ||
161 | __le16 buffer_length[4]; | |
162 | ||
163 | __le64 addr_buffer4; | |
164 | ||
2e9d722d | 165 | u8 eth_addr[ETH_ALEN]; |
af19b491 AKS |
166 | __le16 vlan_TCI; |
167 | ||
168 | } __attribute__ ((aligned(64))); | |
169 | ||
170 | /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */ | |
171 | struct rcv_desc { | |
172 | __le16 reference_handle; | |
173 | __le16 reserved; | |
174 | __le32 buffer_length; /* allocated buffer length (usually 2K) */ | |
175 | __le64 addr_buffer; | |
b1fc6d3c | 176 | } __packed; |
af19b491 | 177 | |
af19b491 AKS |
178 | struct status_desc { |
179 | __le64 status_desc_data[2]; | |
180 | } __attribute__ ((aligned(16))); | |
181 | ||
182 | /* UNIFIED ROMIMAGE */ | |
183 | #define QLCNIC_UNI_FW_MIN_SIZE 0xc8000 | |
184 | #define QLCNIC_UNI_DIR_SECT_PRODUCT_TBL 0x0 | |
185 | #define QLCNIC_UNI_DIR_SECT_BOOTLD 0x6 | |
186 | #define QLCNIC_UNI_DIR_SECT_FW 0x7 | |
187 | ||
188 | /*Offsets */ | |
189 | #define QLCNIC_UNI_CHIP_REV_OFF 10 | |
190 | #define QLCNIC_UNI_FLAGS_OFF 11 | |
191 | #define QLCNIC_UNI_BIOS_VERSION_OFF 12 | |
192 | #define QLCNIC_UNI_BOOTLD_IDX_OFF 27 | |
193 | #define QLCNIC_UNI_FIRMWARE_IDX_OFF 29 | |
194 | ||
195 | struct uni_table_desc{ | |
63507592 SS |
196 | __le32 findex; |
197 | __le32 num_entries; | |
198 | __le32 entry_size; | |
199 | __le32 reserved[5]; | |
af19b491 AKS |
200 | }; |
201 | ||
202 | struct uni_data_desc{ | |
63507592 SS |
203 | __le32 findex; |
204 | __le32 size; | |
205 | __le32 reserved[5]; | |
af19b491 AKS |
206 | }; |
207 | ||
0e5f20b6 | 208 | /* Flash Defines and Structures */ |
209 | #define QLCNIC_FLT_LOCATION 0x3F1000 | |
d865ebb4 | 210 | #define QLCNIC_FDT_LOCATION 0x3F0000 |
a2050c7e SV |
211 | #define QLCNIC_B0_FW_IMAGE_REGION 0x74 |
212 | #define QLCNIC_C0_FW_IMAGE_REGION 0x97 | |
f8d54811 | 213 | #define QLCNIC_BOOTLD_REGION 0X72 |
0e5f20b6 | 214 | struct qlcnic_flt_header { |
215 | u16 version; | |
216 | u16 len; | |
217 | u16 checksum; | |
218 | u16 reserved; | |
219 | }; | |
220 | ||
221 | struct qlcnic_flt_entry { | |
222 | u8 region; | |
223 | u8 reserved0; | |
224 | u8 attrib; | |
225 | u8 reserved1; | |
226 | u32 size; | |
227 | u32 start_addr; | |
f8d54811 | 228 | u32 end_addr; |
0e5f20b6 | 229 | }; |
230 | ||
d865ebb4 SC |
231 | /* Flash Descriptor Table */ |
232 | struct qlcnic_fdt { | |
233 | u32 valid; | |
234 | u16 ver; | |
235 | u16 len; | |
236 | u16 cksum; | |
237 | u16 unused; | |
238 | u8 model[16]; | |
239 | u16 mfg_id; | |
240 | u16 id; | |
241 | u8 flag; | |
242 | u8 erase_cmd; | |
243 | u8 alt_erase_cmd; | |
244 | u8 write_enable_cmd; | |
245 | u8 write_enable_bits; | |
246 | u8 write_statusreg_cmd; | |
247 | u8 unprotected_sec_cmd; | |
248 | u8 read_manuf_cmd; | |
249 | u32 block_size; | |
250 | u32 alt_block_size; | |
251 | u32 flash_size; | |
252 | u32 write_enable_data; | |
253 | u8 readid_addr_len; | |
254 | u8 write_disable_bits; | |
255 | u8 read_dev_id_len; | |
256 | u8 chip_erase_cmd; | |
257 | u16 read_timeo; | |
258 | u8 protected_sec_cmd; | |
259 | u8 resvd[65]; | |
260 | }; | |
af19b491 AKS |
261 | /* Magic number to let user know flash is programmed */ |
262 | #define QLCNIC_BDINFO_MAGIC 0x12345678 | |
263 | ||
ff1b1bf8 SV |
264 | #define QLCNIC_BRDTYPE_P3P_REF_QG 0x0021 |
265 | #define QLCNIC_BRDTYPE_P3P_HMEZ 0x0022 | |
266 | #define QLCNIC_BRDTYPE_P3P_10G_CX4_LP 0x0023 | |
267 | #define QLCNIC_BRDTYPE_P3P_4_GB 0x0024 | |
268 | #define QLCNIC_BRDTYPE_P3P_IMEZ 0x0025 | |
269 | #define QLCNIC_BRDTYPE_P3P_10G_SFP_PLUS 0x0026 | |
270 | #define QLCNIC_BRDTYPE_P3P_10000_BASE_T 0x0027 | |
271 | #define QLCNIC_BRDTYPE_P3P_XG_LOM 0x0028 | |
272 | #define QLCNIC_BRDTYPE_P3P_4_GB_MM 0x0029 | |
273 | #define QLCNIC_BRDTYPE_P3P_10G_SFP_CT 0x002a | |
274 | #define QLCNIC_BRDTYPE_P3P_10G_SFP_QT 0x002b | |
275 | #define QLCNIC_BRDTYPE_P3P_10G_CX4 0x0031 | |
276 | #define QLCNIC_BRDTYPE_P3P_10G_XFP 0x0032 | |
277 | #define QLCNIC_BRDTYPE_P3P_10G_TP 0x0080 | |
af19b491 | 278 | |
2e9d722d AC |
279 | #define QLCNIC_MSIX_TABLE_OFFSET 0x44 |
280 | ||
af19b491 AKS |
281 | /* Flash memory map */ |
282 | #define QLCNIC_BRDCFG_START 0x4000 /* board config */ | |
283 | #define QLCNIC_BOOTLD_START 0x10000 /* bootld */ | |
284 | #define QLCNIC_IMAGE_START 0x43000 /* compressed image */ | |
285 | #define QLCNIC_USER_START 0x3E8000 /* Firmare info */ | |
286 | ||
287 | #define QLCNIC_FW_VERSION_OFFSET (QLCNIC_USER_START+0x408) | |
288 | #define QLCNIC_FW_SIZE_OFFSET (QLCNIC_USER_START+0x40c) | |
289 | #define QLCNIC_FW_SERIAL_NUM_OFFSET (QLCNIC_USER_START+0x81c) | |
290 | #define QLCNIC_BIOS_VERSION_OFFSET (QLCNIC_USER_START+0x83c) | |
291 | ||
292 | #define QLCNIC_BRDTYPE_OFFSET (QLCNIC_BRDCFG_START+0x8) | |
293 | #define QLCNIC_FW_MAGIC_OFFSET (QLCNIC_BRDCFG_START+0x128) | |
294 | ||
295 | #define QLCNIC_FW_MIN_SIZE (0x3fffff) | |
296 | #define QLCNIC_UNIFIED_ROMIMAGE 0 | |
297 | #define QLCNIC_FLASH_ROMIMAGE 1 | |
298 | #define QLCNIC_UNKNOWN_ROMIMAGE 0xff | |
299 | ||
300 | #define QLCNIC_UNIFIED_ROMIMAGE_NAME "phanfw.bin" | |
301 | #define QLCNIC_FLASH_ROMIMAGE_NAME "flash" | |
302 | ||
303 | extern char qlcnic_driver_name[]; | |
304 | ||
629263ac SC |
305 | extern int qlcnic_use_msi; |
306 | extern int qlcnic_use_msi_x; | |
307 | extern int qlcnic_auto_fw_reset; | |
308 | extern int qlcnic_load_fw_file; | |
629263ac | 309 | |
af19b491 AKS |
310 | /* Number of status descriptors to handle per interrupt */ |
311 | #define MAX_STATUS_HANDLE (64) | |
312 | ||
313 | /* | |
314 | * qlcnic_skb_frag{} is to contain mapping info for each SG list. This | |
315 | * has to be freed when DMA is complete. This is part of qlcnic_tx_buffer{}. | |
316 | */ | |
317 | struct qlcnic_skb_frag { | |
318 | u64 dma; | |
319 | u64 length; | |
320 | }; | |
321 | ||
af19b491 AKS |
322 | /* Following defines are for the state of the buffers */ |
323 | #define QLCNIC_BUFFER_FREE 0 | |
324 | #define QLCNIC_BUFFER_BUSY 1 | |
325 | ||
326 | /* | |
327 | * There will be one qlcnic_buffer per skb packet. These will be | |
328 | * used to save the dma info for pci_unmap_page() | |
329 | */ | |
330 | struct qlcnic_cmd_buffer { | |
331 | struct sk_buff *skb; | |
ef71ff83 | 332 | struct qlcnic_skb_frag frag_array[MAX_SKB_FRAGS + 1]; |
af19b491 AKS |
333 | u32 frag_count; |
334 | }; | |
335 | ||
336 | /* In rx_buffer, we do not need multiple fragments as is a single buffer */ | |
337 | struct qlcnic_rx_buffer { | |
b1fc6d3c | 338 | u16 ref_handle; |
af19b491 | 339 | struct sk_buff *skb; |
b1fc6d3c | 340 | struct list_head list; |
af19b491 | 341 | u64 dma; |
af19b491 AKS |
342 | }; |
343 | ||
344 | /* Board types */ | |
345 | #define QLCNIC_GBE 0x01 | |
346 | #define QLCNIC_XGBE 0x02 | |
347 | ||
8816d009 AC |
348 | /* |
349 | * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is | |
350 | * adjusted based on configured MTU. | |
351 | */ | |
be273dc1 HM |
352 | #define QLCNIC_INTR_COAL_TYPE_RX 1 |
353 | #define QLCNIC_INTR_COAL_TYPE_TX 2 | |
354 | ||
355 | #define QLCNIC_DEF_INTR_COALESCE_RX_TIME_US 3 | |
356 | #define QLCNIC_DEF_INTR_COALESCE_RX_PACKETS 256 | |
357 | ||
358 | #define QLCNIC_DEF_INTR_COALESCE_TX_TIME_US 64 | |
359 | #define QLCNIC_DEF_INTR_COALESCE_TX_PACKETS 64 | |
8816d009 AC |
360 | |
361 | #define QLCNIC_INTR_DEFAULT 0x04 | |
362 | #define QLCNIC_CONFIG_INTR_COALESCE 3 | |
7e38d04b | 363 | #define QLCNIC_DEV_INFO_SIZE 1 |
8816d009 AC |
364 | |
365 | struct qlcnic_nic_intr_coalesce { | |
366 | u8 type; | |
367 | u8 sts_ring_mask; | |
368 | u16 rx_packets; | |
369 | u16 rx_time_us; | |
be273dc1 HM |
370 | u16 tx_packets; |
371 | u16 tx_time_us; | |
8816d009 AC |
372 | u16 flag; |
373 | u32 timer_out; | |
374 | }; | |
375 | ||
18f2f616 | 376 | struct qlcnic_dump_template_hdr { |
63507592 SS |
377 | u32 type; |
378 | u32 offset; | |
379 | u32 size; | |
380 | u32 cap_mask; | |
381 | u32 num_entries; | |
382 | u32 version; | |
383 | u32 timestamp; | |
384 | u32 checksum; | |
385 | u32 drv_cap_mask; | |
386 | u32 sys_info[3]; | |
387 | u32 saved_state[16]; | |
388 | u32 cap_sizes[8]; | |
4e60ac46 | 389 | u32 ocm_wnd_reg[16]; |
63507592 | 390 | u32 rsvd[0]; |
18f2f616 AC |
391 | }; |
392 | ||
393 | struct qlcnic_fw_dump { | |
394 | u8 clr; /* flag to indicate if dump is cleared */ | |
890b6e02 | 395 | bool enable; /* enable/disable dump */ |
18f2f616 AC |
396 | u32 size; /* total size of the dump */ |
397 | void *data; /* dump data area */ | |
398 | struct qlcnic_dump_template_hdr *tmpl_hdr; | |
9baf1aa9 SS |
399 | dma_addr_t phys_addr; |
400 | void *dma_buffer; | |
401 | bool use_pex_dma; | |
18f2f616 AC |
402 | }; |
403 | ||
af19b491 AKS |
404 | /* |
405 | * One hardware_context{} per adapter | |
406 | * contains interrupt info as well shared hardware info. | |
407 | */ | |
408 | struct qlcnic_hardware_context { | |
409 | void __iomem *pci_base0; | |
410 | void __iomem *ocm_win_crb; | |
411 | ||
412 | unsigned long pci_len0; | |
413 | ||
af19b491 AKS |
414 | rwlock_t crb_lock; |
415 | struct mutex mem_lock; | |
416 | ||
af19b491 AKS |
417 | u8 revision_id; |
418 | u8 pci_func; | |
419 | u8 linkup; | |
22c8c934 | 420 | u8 loopback_state; |
79788450 SC |
421 | u8 beacon_state; |
422 | u8 has_link_events; | |
423 | u8 fw_type; | |
424 | u8 physical_port; | |
425 | u8 reset_context; | |
426 | u8 msix_supported; | |
427 | u8 max_mac_filters; | |
428 | u8 mc_enabled; | |
429 | u8 max_mc_count; | |
430 | u8 diag_test; | |
431 | u8 num_msix; | |
432 | u8 nic_mode; | |
97f3f6fc | 433 | int diag_cnt; |
79788450 | 434 | |
52e493d0 | 435 | u16 max_uc_count; |
af19b491 AKS |
436 | u16 port_type; |
437 | u16 board_type; | |
b938662d | 438 | u16 supported_type; |
8816d009 | 439 | |
79788450 SC |
440 | u16 link_speed; |
441 | u16 link_duplex; | |
442 | u16 link_autoneg; | |
443 | u16 module_type; | |
444 | ||
445 | u16 op_mode; | |
446 | u16 switch_mode; | |
447 | u16 max_tx_ques; | |
448 | u16 max_rx_ques; | |
449 | u16 max_mtu; | |
450 | u32 msg_enable; | |
451 | u16 act_pci_func; | |
ee9e8b6c | 452 | u16 max_pci_func; |
728a98b8 | 453 | |
79788450 | 454 | u32 capabilities; |
db131786 | 455 | u32 extra_capability[3]; |
79788450 SC |
456 | u32 temp; |
457 | u32 int_vec_bit; | |
458 | u32 fw_hal_version; | |
7f966452 | 459 | u32 port_config; |
79788450 | 460 | struct qlcnic_hardware_ops *hw_ops; |
8816d009 | 461 | struct qlcnic_nic_intr_coalesce coal; |
18f2f616 | 462 | struct qlcnic_fw_dump fw_dump; |
d865ebb4 | 463 | struct qlcnic_fdt fdt; |
81d0aeb0 | 464 | struct qlc_83xx_reset reset; |
629263ac | 465 | struct qlc_83xx_idc idc; |
7000078a | 466 | struct qlc_83xx_fw_info *fw_info; |
7f966452 | 467 | struct qlcnic_intrpt_config *intr_tbl; |
02feda17 | 468 | struct qlcnic_sriov *sriov; |
7e2cf4fe | 469 | u32 *reg_tbl; |
7f966452 SC |
470 | u32 *ext_reg_tbl; |
471 | u32 mbox_aen[QLC_83XX_MBX_AEN_CNT]; | |
472 | u32 mbox_reg[4]; | |
e5c4e6c6 | 473 | struct qlcnic_mailbox *mailbox; |
77bead46 | 474 | u8 extend_lb_time; |
07a251c8 | 475 | u8 phys_port_id[ETH_ALEN]; |
af19b491 AKS |
476 | }; |
477 | ||
478 | struct qlcnic_adapter_stats { | |
479 | u64 xmitcalled; | |
480 | u64 xmitfinished; | |
481 | u64 rxdropped; | |
482 | u64 txdropped; | |
483 | u64 csummed; | |
484 | u64 rx_pkts; | |
485 | u64 lro_pkts; | |
486 | u64 rxbytes; | |
487 | u64 txbytes; | |
8bfe8b91 SC |
488 | u64 lrobytes; |
489 | u64 lso_frames; | |
490 | u64 xmit_on; | |
491 | u64 xmit_off; | |
492 | u64 skb_alloc_failure; | |
8ae6df97 AKS |
493 | u64 null_rxbuf; |
494 | u64 rx_dma_map_error; | |
495 | u64 tx_dma_map_error; | |
7f966452 | 496 | u64 spurious_intr; |
4be41e92 | 497 | u64 mac_filter_limit_overrun; |
af19b491 AKS |
498 | }; |
499 | ||
500 | /* | |
501 | * Rcv Descriptor Context. One such per Rcv Descriptor. There may | |
502 | * be one Rcv Descriptor for normal packets, one for jumbo and may be others. | |
503 | */ | |
504 | struct qlcnic_host_rds_ring { | |
036d61f0 AC |
505 | void __iomem *crb_rcv_producer; |
506 | struct rcv_desc *desc_head; | |
507 | struct qlcnic_rx_buffer *rx_buf_arr; | |
af19b491 | 508 | u32 num_desc; |
036d61f0 | 509 | u32 producer; |
af19b491 AKS |
510 | u32 dma_size; |
511 | u32 skb_size; | |
512 | u32 flags; | |
af19b491 AKS |
513 | struct list_head free_list; |
514 | spinlock_t lock; | |
515 | dma_addr_t phys_addr; | |
036d61f0 | 516 | } ____cacheline_internodealigned_in_smp; |
af19b491 AKS |
517 | |
518 | struct qlcnic_host_sds_ring { | |
519 | u32 consumer; | |
520 | u32 num_desc; | |
521 | void __iomem *crb_sts_consumer; | |
af19b491 | 522 | |
012ec812 | 523 | struct qlcnic_host_tx_ring *tx_ring; |
af19b491 AKS |
524 | struct status_desc *desc_head; |
525 | struct qlcnic_adapter *adapter; | |
526 | struct napi_struct napi; | |
527 | struct list_head free_list[NUM_RCV_DESC_RINGS]; | |
528 | ||
036d61f0 | 529 | void __iomem *crb_intr_mask; |
af19b491 AKS |
530 | int irq; |
531 | ||
532 | dma_addr_t phys_addr; | |
ddb2e174 | 533 | char name[IFNAMSIZ + 12]; |
036d61f0 | 534 | } ____cacheline_internodealigned_in_smp; |
af19b491 | 535 | |
f27c75b3 HM |
536 | struct qlcnic_tx_queue_stats { |
537 | u64 xmit_on; | |
538 | u64 xmit_off; | |
539 | u64 xmit_called; | |
540 | u64 xmit_finished; | |
541 | u64 tx_bytes; | |
542 | }; | |
543 | ||
af19b491 | 544 | struct qlcnic_host_tx_ring { |
4be41e92 | 545 | int irq; |
7f966452 | 546 | void __iomem *crb_intr_mask; |
ddb2e174 | 547 | char name[IFNAMSIZ + 12]; |
79788450 | 548 | u16 ctx_id; |
012ec812 HM |
549 | |
550 | u32 state; | |
af19b491 | 551 | u32 producer; |
af19b491 | 552 | u32 sw_consumer; |
af19b491 | 553 | u32 num_desc; |
012ec812 | 554 | |
f27c75b3 | 555 | struct qlcnic_tx_queue_stats tx_stats; |
012ec812 | 556 | |
036d61f0 | 557 | void __iomem *crb_cmd_producer; |
af19b491 | 558 | struct cmd_desc_type0 *desc_head; |
4be41e92 SC |
559 | struct qlcnic_adapter *adapter; |
560 | struct napi_struct napi; | |
036d61f0 AC |
561 | struct qlcnic_cmd_buffer *cmd_buf_arr; |
562 | __le32 *hw_consumer; | |
563 | ||
af19b491 AKS |
564 | dma_addr_t phys_addr; |
565 | dma_addr_t hw_cons_phys_addr; | |
036d61f0 AC |
566 | struct netdev_queue *txq; |
567 | } ____cacheline_internodealigned_in_smp; | |
af19b491 AKS |
568 | |
569 | /* | |
570 | * Receive context. There is one such structure per instance of the | |
571 | * receive processing. Any state information that is relevant to | |
572 | * the receive, and is must be in this structure. The global data may be | |
573 | * present elsewhere. | |
574 | */ | |
575 | struct qlcnic_recv_context { | |
b1fc6d3c AC |
576 | struct qlcnic_host_rds_ring *rds_rings; |
577 | struct qlcnic_host_sds_ring *sds_rings; | |
af19b491 AKS |
578 | u32 state; |
579 | u16 context_id; | |
580 | u16 virt_port; | |
af19b491 AKS |
581 | }; |
582 | ||
583 | /* HW context creation */ | |
584 | ||
585 | #define QLCNIC_OS_CRB_RETRY_COUNT 4000 | |
af19b491 AKS |
586 | |
587 | #define QLCNIC_CDRP_CMD_BIT 0x80000000 | |
588 | ||
589 | /* | |
590 | * All responses must have the QLCNIC_CDRP_CMD_BIT cleared | |
591 | * in the crb QLCNIC_CDRP_CRB_OFFSET. | |
592 | */ | |
593 | #define QLCNIC_CDRP_FORM_RSP(rsp) (rsp) | |
594 | #define QLCNIC_CDRP_IS_RSP(rsp) (((rsp) & QLCNIC_CDRP_CMD_BIT) == 0) | |
595 | ||
596 | #define QLCNIC_CDRP_RSP_OK 0x00000001 | |
597 | #define QLCNIC_CDRP_RSP_FAIL 0x00000002 | |
598 | #define QLCNIC_CDRP_RSP_TIMEOUT 0x00000003 | |
599 | ||
600 | /* | |
601 | * All commands must have the QLCNIC_CDRP_CMD_BIT set in | |
602 | * the crb QLCNIC_CDRP_CRB_OFFSET. | |
603 | */ | |
604 | #define QLCNIC_CDRP_FORM_CMD(cmd) (QLCNIC_CDRP_CMD_BIT | (cmd)) | |
af19b491 AKS |
605 | |
606 | #define QLCNIC_RCODE_SUCCESS 0 | |
e42ede22 | 607 | #define QLCNIC_RCODE_INVALID_ARGS 6 |
7e610caa | 608 | #define QLCNIC_RCODE_NOT_SUPPORTED 9 |
e42ede22 JK |
609 | #define QLCNIC_RCODE_NOT_PERMITTED 10 |
610 | #define QLCNIC_RCODE_NOT_IMPL 15 | |
611 | #define QLCNIC_RCODE_INVALID 16 | |
af19b491 AKS |
612 | #define QLCNIC_RCODE_TIMEOUT 17 |
613 | #define QLCNIC_DESTROY_CTX_RESET 0 | |
614 | ||
615 | /* | |
616 | * Capabilities Announced | |
617 | */ | |
618 | #define QLCNIC_CAP0_LEGACY_CONTEXT (1) | |
619 | #define QLCNIC_CAP0_LEGACY_MN (1 << 2) | |
620 | #define QLCNIC_CAP0_LSO (1 << 6) | |
621 | #define QLCNIC_CAP0_JUMBO_CONTIGUOUS (1 << 7) | |
622 | #define QLCNIC_CAP0_LRO_CONTIGUOUS (1 << 8) | |
8f891387 | 623 | #define QLCNIC_CAP0_VALIDOFF (1 << 11) |
cae82d49 | 624 | #define QLCNIC_CAP0_LRO_MSS (1 << 21) |
012ec812 | 625 | #define QLCNIC_CAP0_TX_MULTI (1 << 22) |
af19b491 AKS |
626 | |
627 | /* | |
628 | * Context state | |
629 | */ | |
d626ad4d | 630 | #define QLCNIC_HOST_CTX_STATE_FREED 0 |
af19b491 AKS |
631 | #define QLCNIC_HOST_CTX_STATE_ACTIVE 2 |
632 | ||
633 | /* | |
634 | * Rx context | |
635 | */ | |
636 | ||
637 | struct qlcnic_hostrq_sds_ring { | |
638 | __le64 host_phys_addr; /* Ring base addr */ | |
639 | __le32 ring_size; /* Ring entries */ | |
640 | __le16 msi_index; | |
641 | __le16 rsvd; /* Padding */ | |
b1fc6d3c | 642 | } __packed; |
af19b491 AKS |
643 | |
644 | struct qlcnic_hostrq_rds_ring { | |
645 | __le64 host_phys_addr; /* Ring base addr */ | |
646 | __le64 buff_size; /* Packet buffer size */ | |
647 | __le32 ring_size; /* Ring entries */ | |
648 | __le32 ring_kind; /* Class of ring */ | |
b1fc6d3c | 649 | } __packed; |
af19b491 AKS |
650 | |
651 | struct qlcnic_hostrq_rx_ctx { | |
652 | __le64 host_rsp_dma_addr; /* Response dma'd here */ | |
012ec812 | 653 | __le32 capabilities[4]; /* Flag bit vector */ |
af19b491 AKS |
654 | __le32 host_int_crb_mode; /* Interrupt crb usage */ |
655 | __le32 host_rds_crb_mode; /* RDS crb usage */ | |
656 | /* These ring offsets are relative to data[0] below */ | |
657 | __le32 rds_ring_offset; /* Offset to RDS config */ | |
658 | __le32 sds_ring_offset; /* Offset to SDS config */ | |
659 | __le16 num_rds_rings; /* Count of RDS rings */ | |
660 | __le16 num_sds_rings; /* Count of SDS rings */ | |
8f891387 | 661 | __le16 valid_field_offset; |
662 | u8 txrx_sds_binding; | |
663 | u8 msix_handler; | |
664 | u8 reserved[128]; /* reserve space for future expansion*/ | |
af19b491 AKS |
665 | /* MUST BE 64-bit aligned. |
666 | The following is packed: | |
667 | - N hostrq_rds_rings | |
668 | - N hostrq_sds_rings */ | |
669 | char data[0]; | |
b1fc6d3c | 670 | } __packed; |
af19b491 AKS |
671 | |
672 | struct qlcnic_cardrsp_rds_ring{ | |
673 | __le32 host_producer_crb; /* Crb to use */ | |
674 | __le32 rsvd1; /* Padding */ | |
b1fc6d3c | 675 | } __packed; |
af19b491 AKS |
676 | |
677 | struct qlcnic_cardrsp_sds_ring { | |
678 | __le32 host_consumer_crb; /* Crb to use */ | |
679 | __le32 interrupt_crb; /* Crb to use */ | |
b1fc6d3c | 680 | } __packed; |
af19b491 AKS |
681 | |
682 | struct qlcnic_cardrsp_rx_ctx { | |
683 | /* These ring offsets are relative to data[0] below */ | |
684 | __le32 rds_ring_offset; /* Offset to RDS config */ | |
685 | __le32 sds_ring_offset; /* Offset to SDS config */ | |
686 | __le32 host_ctx_state; /* Starting State */ | |
687 | __le32 num_fn_per_port; /* How many PCI fn share the port */ | |
688 | __le16 num_rds_rings; /* Count of RDS rings */ | |
689 | __le16 num_sds_rings; /* Count of SDS rings */ | |
690 | __le16 context_id; /* Handle for context */ | |
691 | u8 phys_port; /* Physical id of port */ | |
692 | u8 virt_port; /* Virtual/Logical id of port */ | |
693 | u8 reserved[128]; /* save space for future expansion */ | |
694 | /* MUST BE 64-bit aligned. | |
695 | The following is packed: | |
696 | - N cardrsp_rds_rings | |
697 | - N cardrs_sds_rings */ | |
698 | char data[0]; | |
b1fc6d3c | 699 | } __packed; |
af19b491 AKS |
700 | |
701 | #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \ | |
702 | (sizeof(HOSTRQ_RX) + \ | |
703 | (rds_rings)*(sizeof(struct qlcnic_hostrq_rds_ring)) + \ | |
704 | (sds_rings)*(sizeof(struct qlcnic_hostrq_sds_ring))) | |
705 | ||
706 | #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \ | |
707 | (sizeof(CARDRSP_RX) + \ | |
708 | (rds_rings)*(sizeof(struct qlcnic_cardrsp_rds_ring)) + \ | |
709 | (sds_rings)*(sizeof(struct qlcnic_cardrsp_sds_ring))) | |
710 | ||
711 | /* | |
712 | * Tx context | |
713 | */ | |
714 | ||
715 | struct qlcnic_hostrq_cds_ring { | |
716 | __le64 host_phys_addr; /* Ring base addr */ | |
717 | __le32 ring_size; /* Ring entries */ | |
718 | __le32 rsvd; /* Padding */ | |
b1fc6d3c | 719 | } __packed; |
af19b491 AKS |
720 | |
721 | struct qlcnic_hostrq_tx_ctx { | |
722 | __le64 host_rsp_dma_addr; /* Response dma'd here */ | |
723 | __le64 cmd_cons_dma_addr; /* */ | |
724 | __le64 dummy_dma_addr; /* */ | |
725 | __le32 capabilities[4]; /* Flag bit vector */ | |
726 | __le32 host_int_crb_mode; /* Interrupt crb usage */ | |
727 | __le32 rsvd1; /* Padding */ | |
728 | __le16 rsvd2; /* Padding */ | |
729 | __le16 interrupt_ctl; | |
730 | __le16 msi_index; | |
731 | __le16 rsvd3; /* Padding */ | |
732 | struct qlcnic_hostrq_cds_ring cds_ring; /* Desc of cds ring */ | |
733 | u8 reserved[128]; /* future expansion */ | |
b1fc6d3c | 734 | } __packed; |
af19b491 AKS |
735 | |
736 | struct qlcnic_cardrsp_cds_ring { | |
737 | __le32 host_producer_crb; /* Crb to use */ | |
738 | __le32 interrupt_crb; /* Crb to use */ | |
b1fc6d3c | 739 | } __packed; |
af19b491 AKS |
740 | |
741 | struct qlcnic_cardrsp_tx_ctx { | |
742 | __le32 host_ctx_state; /* Starting state */ | |
743 | __le16 context_id; /* Handle for context */ | |
744 | u8 phys_port; /* Physical id of port */ | |
745 | u8 virt_port; /* Virtual/Logical id of port */ | |
746 | struct qlcnic_cardrsp_cds_ring cds_ring; /* Card cds settings */ | |
747 | u8 reserved[128]; /* future expansion */ | |
b1fc6d3c | 748 | } __packed; |
af19b491 AKS |
749 | |
750 | #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX)) | |
751 | #define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX)) | |
752 | ||
753 | /* CRB */ | |
754 | ||
755 | #define QLCNIC_HOST_RDS_CRB_MODE_UNIQUE 0 | |
756 | #define QLCNIC_HOST_RDS_CRB_MODE_SHARED 1 | |
757 | #define QLCNIC_HOST_RDS_CRB_MODE_CUSTOM 2 | |
758 | #define QLCNIC_HOST_RDS_CRB_MODE_MAX 3 | |
759 | ||
760 | #define QLCNIC_HOST_INT_CRB_MODE_UNIQUE 0 | |
761 | #define QLCNIC_HOST_INT_CRB_MODE_SHARED 1 | |
762 | #define QLCNIC_HOST_INT_CRB_MODE_NORX 2 | |
763 | #define QLCNIC_HOST_INT_CRB_MODE_NOTX 3 | |
764 | #define QLCNIC_HOST_INT_CRB_MODE_NORXTX 4 | |
765 | ||
766 | ||
767 | /* MAC */ | |
768 | ||
ff1b1bf8 | 769 | #define MC_COUNT_P3P 38 |
af19b491 AKS |
770 | |
771 | #define QLCNIC_MAC_NOOP 0 | |
772 | #define QLCNIC_MAC_ADD 1 | |
773 | #define QLCNIC_MAC_DEL 2 | |
03c5d770 AKS |
774 | #define QLCNIC_MAC_VLAN_ADD 3 |
775 | #define QLCNIC_MAC_VLAN_DEL 4 | |
af19b491 AKS |
776 | |
777 | struct qlcnic_mac_list_s { | |
778 | struct list_head list; | |
779 | uint8_t mac_addr[ETH_ALEN+2]; | |
780 | }; | |
781 | ||
fe1adc6b JK |
782 | /* MAC Learn */ |
783 | #define NO_MAC_LEARN 0 | |
784 | #define DRV_MAC_LEARN 1 | |
785 | #define FDB_MAC_LEARN 2 | |
786 | ||
af19b491 AKS |
787 | #define QLCNIC_HOST_REQUEST 0x13 |
788 | #define QLCNIC_REQUEST 0x14 | |
789 | ||
790 | #define QLCNIC_MAC_EVENT 0x1 | |
791 | ||
792 | #define QLCNIC_IP_UP 2 | |
793 | #define QLCNIC_IP_DOWN 3 | |
794 | ||
22c8c934 | 795 | #define QLCNIC_ILB_MODE 0x1 |
e1428d26 | 796 | #define QLCNIC_ELB_MODE 0x2 |
22c8c934 SC |
797 | |
798 | #define QLCNIC_LINKEVENT 0x1 | |
799 | #define QLCNIC_LB_RESPONSE 0x2 | |
800 | #define QLCNIC_IS_LB_CONFIGURED(VAL) \ | |
801 | (VAL == (QLCNIC_LINKEVENT | QLCNIC_LB_RESPONSE)) | |
802 | ||
af19b491 AKS |
803 | /* |
804 | * Driver --> Firmware | |
805 | */ | |
b1fc6d3c AC |
806 | #define QLCNIC_H2C_OPCODE_CONFIG_RSS 0x1 |
807 | #define QLCNIC_H2C_OPCODE_CONFIG_INTR_COALESCE 0x3 | |
808 | #define QLCNIC_H2C_OPCODE_CONFIG_LED 0x4 | |
809 | #define QLCNIC_H2C_OPCODE_LRO_REQUEST 0x7 | |
810 | #define QLCNIC_H2C_OPCODE_SET_MAC_RECEIVE_MODE 0xc | |
811 | #define QLCNIC_H2C_OPCODE_CONFIG_IPADDR 0x12 | |
22c8c934 | 812 | |
b1fc6d3c AC |
813 | #define QLCNIC_H2C_OPCODE_GET_LINKEVENT 0x15 |
814 | #define QLCNIC_H2C_OPCODE_CONFIG_BRIDGING 0x17 | |
815 | #define QLCNIC_H2C_OPCODE_CONFIG_HW_LRO 0x18 | |
22c8c934 SC |
816 | #define QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK 0x13 |
817 | ||
af19b491 AKS |
818 | /* |
819 | * Firmware --> Driver | |
820 | */ | |
821 | ||
22c8c934 | 822 | #define QLCNIC_C2H_OPCODE_CONFIG_LOOPBACK 0x8f |
7f966452 | 823 | #define QLCNIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE 0x8D |
2d8ebcab | 824 | #define QLCNIC_C2H_OPCODE_GET_DCB_AEN 0x90 |
af19b491 AKS |
825 | |
826 | #define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */ | |
827 | #define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */ | |
828 | #define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */ | |
829 | ||
830 | #define QLCNIC_LRO_REQUEST_CLEANUP 4 | |
831 | ||
832 | /* Capabilites received */ | |
ac8d0c4f AC |
833 | #define QLCNIC_FW_CAPABILITY_TSO BIT_1 |
834 | #define QLCNIC_FW_CAPABILITY_BDG BIT_8 | |
835 | #define QLCNIC_FW_CAPABILITY_FVLANTX BIT_9 | |
836 | #define QLCNIC_FW_CAPABILITY_HW_LRO BIT_10 | |
012ec812 | 837 | #define QLCNIC_FW_CAPABILITY_2_MULTI_TX BIT_4 |
fef0c060 | 838 | #define QLCNIC_FW_CAPABILITY_MULTI_LOOPBACK BIT_27 |
cae82d49 RB |
839 | #define QLCNIC_FW_CAPABILITY_MORE_CAPS BIT_31 |
840 | ||
841 | #define QLCNIC_FW_CAPABILITY_2_LRO_MAX_TCP_SEG BIT_2 | |
776e7bde | 842 | #define QLCNIC_FW_CAP2_HW_LRO_IPV6 BIT_3 |
8af3f33d | 843 | #define QLCNIC_FW_CAPABILITY_SET_DRV_VER BIT_5 |
487042af | 844 | #define QLCNIC_FW_CAPABILITY_2_BEACON BIT_7 |
35dafcb0 | 845 | #define QLCNIC_FW_CAPABILITY_2_PER_PORT_ESWITCH_CFG BIT_8 |
af19b491 AKS |
846 | |
847 | /* module types */ | |
848 | #define LINKEVENT_MODULE_NOT_PRESENT 1 | |
849 | #define LINKEVENT_MODULE_OPTICAL_UNKNOWN 2 | |
850 | #define LINKEVENT_MODULE_OPTICAL_SRLR 3 | |
851 | #define LINKEVENT_MODULE_OPTICAL_LRM 4 | |
852 | #define LINKEVENT_MODULE_OPTICAL_SFP_1G 5 | |
853 | #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE 6 | |
854 | #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN 7 | |
855 | #define LINKEVENT_MODULE_TWINAX 8 | |
856 | ||
857 | #define LINKSPEED_10GBPS 10000 | |
858 | #define LINKSPEED_1GBPS 1000 | |
859 | #define LINKSPEED_100MBPS 100 | |
860 | #define LINKSPEED_10MBPS 10 | |
861 | ||
862 | #define LINKSPEED_ENCODED_10MBPS 0 | |
863 | #define LINKSPEED_ENCODED_100MBPS 1 | |
864 | #define LINKSPEED_ENCODED_1GBPS 2 | |
865 | ||
866 | #define LINKEVENT_AUTONEG_DISABLED 0 | |
867 | #define LINKEVENT_AUTONEG_ENABLED 1 | |
868 | ||
869 | #define LINKEVENT_HALF_DUPLEX 0 | |
870 | #define LINKEVENT_FULL_DUPLEX 1 | |
871 | ||
872 | #define LINKEVENT_LINKSPEED_MBPS 0 | |
873 | #define LINKEVENT_LINKSPEED_ENCODED 1 | |
874 | ||
af19b491 AKS |
875 | /* firmware response header: |
876 | * 63:58 - message type | |
877 | * 57:56 - owner | |
878 | * 55:53 - desc count | |
879 | * 52:48 - reserved | |
880 | * 47:40 - completion id | |
881 | * 39:32 - opcode | |
882 | * 31:16 - error code | |
883 | * 15:00 - reserved | |
884 | */ | |
885 | #define qlcnic_get_nic_msg_opcode(msg_hdr) \ | |
886 | ((msg_hdr >> 32) & 0xFF) | |
887 | ||
888 | struct qlcnic_fw_msg { | |
889 | union { | |
890 | struct { | |
891 | u64 hdr; | |
892 | u64 body[7]; | |
893 | }; | |
894 | u64 words[8]; | |
895 | }; | |
896 | }; | |
897 | ||
898 | struct qlcnic_nic_req { | |
899 | __le64 qhdr; | |
900 | __le64 req_hdr; | |
901 | __le64 words[6]; | |
b1fc6d3c | 902 | } __packed; |
af19b491 AKS |
903 | |
904 | struct qlcnic_mac_req { | |
905 | u8 op; | |
906 | u8 tag; | |
907 | u8 mac_addr[6]; | |
908 | }; | |
909 | ||
7e56cac4 SC |
910 | struct qlcnic_vlan_req { |
911 | __le16 vlan_id; | |
912 | __le16 rsvd[3]; | |
b1fc6d3c | 913 | } __packed; |
7e56cac4 | 914 | |
b501595c SC |
915 | struct qlcnic_ipaddr { |
916 | __be32 ipv4; | |
917 | __be32 ipv6[4]; | |
918 | }; | |
919 | ||
af19b491 AKS |
920 | #define QLCNIC_MSI_ENABLED 0x02 |
921 | #define QLCNIC_MSIX_ENABLED 0x04 | |
7f966452 | 922 | #define QLCNIC_LRO_ENABLED 0x01 |
24763d80 | 923 | #define QLCNIC_LRO_DISABLED 0x00 |
af19b491 AKS |
924 | #define QLCNIC_BRIDGE_ENABLED 0X10 |
925 | #define QLCNIC_DIAG_ENABLED 0x20 | |
0e33c664 | 926 | #define QLCNIC_ESWITCH_ENABLED 0x40 |
0866d96d | 927 | #define QLCNIC_ADAPTER_INITIALIZED 0x80 |
8cf61f89 | 928 | #define QLCNIC_TAGGING_ENABLED 0x100 |
fe4d434d | 929 | #define QLCNIC_MACSPOOF 0x200 |
7373373d | 930 | #define QLCNIC_MAC_OVERRIDE_DISABLED 0x400 |
ee07c1a7 | 931 | #define QLCNIC_PROMISC_DISABLED 0x800 |
b0044bcf | 932 | #define QLCNIC_NEED_FLR 0x1000 |
602ca6f0 | 933 | #define QLCNIC_FW_RESET_OWNER 0x2000 |
032a13c7 | 934 | #define QLCNIC_FW_HANG 0x4000 |
cae82d49 | 935 | #define QLCNIC_FW_LRO_MSS_CAP 0x8000 |
da6c8063 | 936 | #define QLCNIC_TX_INTR_SHARED 0x10000 |
147a9088 | 937 | #define QLCNIC_APP_CHANGED_FLAGS 0x20000 |
07a251c8 SS |
938 | #define QLCNIC_HAS_PHYS_PORT_ID 0x40000 |
939 | ||
af19b491 AKS |
940 | #define QLCNIC_IS_MSI_FAMILY(adapter) \ |
941 | ((adapter)->flags & (QLCNIC_MSI_ENABLED | QLCNIC_MSIX_ENABLED)) | |
147a9088 SS |
942 | #define QLCNIC_IS_TSO_CAPABLE(adapter) \ |
943 | ((adapter)->ahw->capabilities & QLCNIC_FW_CAPABILITY_TSO) | |
af19b491 | 944 | |
487042af HM |
945 | #define QLCNIC_BEACON_EANBLE 0xC |
946 | #define QLCNIC_BEACON_DISABLE 0xD | |
947 | ||
f94bc1e7 | 948 | #define QLCNIC_DEF_NUM_STS_DESC_RINGS 4 |
012ec812 | 949 | #define QLCNIC_DEF_NUM_TX_RINGS 4 |
af19b491 AKS |
950 | #define QLCNIC_MSIX_TBL_SPACE 8192 |
951 | #define QLCNIC_PCI_REG_MSIX_TBL 0x44 | |
2e9d722d | 952 | #define QLCNIC_MSIX_TBL_PGSIZE 4096 |
af19b491 | 953 | |
af19b491 AKS |
954 | #define QLCNIC_ADAPTER_UP_MAGIC 777 |
955 | ||
956 | #define __QLCNIC_FW_ATTACHED 0 | |
957 | #define __QLCNIC_DEV_UP 1 | |
958 | #define __QLCNIC_RESETTING 2 | |
959 | #define __QLCNIC_START_FW 4 | |
451724c8 | 960 | #define __QLCNIC_AER 5 |
89b4208e | 961 | #define __QLCNIC_DIAG_RES_ALLOC 6 |
728a98b8 | 962 | #define __QLCNIC_LED_ENABLE 7 |
02feda17 | 963 | #define __QLCNIC_ELB_INPROGRESS 8 |
012ec812 | 964 | #define __QLCNIC_MULTI_TX_UNIQUE 9 |
02feda17 RB |
965 | #define __QLCNIC_SRIOV_ENABLE 10 |
966 | #define __QLCNIC_SRIOV_CAPABLE 11 | |
7ed3ce48 | 967 | #define __QLCNIC_MBX_POLL_ENABLE 12 |
4690a7e4 | 968 | #define __QLCNIC_DIAG_MODE 13 |
78ea2d97 | 969 | #define __QLCNIC_MAINTENANCE_MODE 16 |
af19b491 | 970 | |
7eb9855d | 971 | #define QLCNIC_INTERRUPT_TEST 1 |
cdaff185 | 972 | #define QLCNIC_LOOPBACK_TEST 2 |
c75822a3 | 973 | #define QLCNIC_LED_TEST 3 |
7eb9855d | 974 | |
b5e5492c | 975 | #define QLCNIC_FILTER_AGE 80 |
e5edb7b1 | 976 | #define QLCNIC_READD_AGE 20 |
b5e5492c | 977 | #define QLCNIC_LB_MAX_FILTERS 64 |
7f966452 | 978 | #define QLCNIC_LB_BUCKET_SIZE 32 |
629263ac | 979 | #define QLCNIC_ILB_MAX_RCV_LOOP 10 |
fef0c060 | 980 | |
b5e5492c AKS |
981 | struct qlcnic_filter { |
982 | struct hlist_node fnode; | |
983 | u8 faddr[ETH_ALEN]; | |
f80bc8fe | 984 | u16 vlan_id; |
b5e5492c AKS |
985 | unsigned long ftime; |
986 | }; | |
987 | ||
988 | struct qlcnic_filter_hash { | |
989 | struct hlist_head *fhead; | |
990 | u8 fnum; | |
7f966452 SC |
991 | u16 fmax; |
992 | u16 fbucket_size; | |
b5e5492c AKS |
993 | }; |
994 | ||
e5c4e6c6 MC |
995 | /* Mailbox specific data structures */ |
996 | struct qlcnic_mailbox { | |
997 | struct workqueue_struct *work_q; | |
998 | struct qlcnic_adapter *adapter; | |
999 | struct qlcnic_mbx_ops *ops; | |
1000 | struct work_struct work; | |
1001 | struct completion completion; | |
1002 | struct list_head cmd_q; | |
1003 | unsigned long status; | |
1004 | spinlock_t queue_lock; /* Mailbox queue lock */ | |
1005 | spinlock_t aen_lock; /* Mailbox response/AEN lock */ | |
1006 | atomic_t rsp_status; | |
1007 | u32 num_cmds; | |
1008 | }; | |
1009 | ||
af19b491 | 1010 | struct qlcnic_adapter { |
b1fc6d3c AC |
1011 | struct qlcnic_hardware_context *ahw; |
1012 | struct qlcnic_recv_context *recv_ctx; | |
1013 | struct qlcnic_host_tx_ring *tx_ring; | |
af19b491 AKS |
1014 | struct net_device *netdev; |
1015 | struct pci_dev *pdev; | |
af19b491 | 1016 | |
b1fc6d3c AC |
1017 | unsigned long state; |
1018 | u32 flags; | |
af19b491 | 1019 | |
79788450 | 1020 | int max_drv_tx_rings; |
af19b491 AKS |
1021 | u16 num_txd; |
1022 | u16 num_rxd; | |
1023 | u16 num_jumbo_rxd; | |
90d19005 SC |
1024 | u16 max_rxd; |
1025 | u16 max_jumbo_rxd; | |
af19b491 AKS |
1026 | |
1027 | u8 max_rds_rings; | |
1028 | u8 max_sds_rings; | |
7f966452 | 1029 | u8 rx_csum; |
af19b491 | 1030 | u8 portnum; |
af19b491 | 1031 | |
af19b491 AKS |
1032 | u8 fw_wait_cnt; |
1033 | u8 fw_fail_cnt; | |
1034 | u8 tx_timeo_cnt; | |
1035 | u8 need_fw_reset; | |
f036e4f4 | 1036 | u8 reset_ctx_cnt; |
af19b491 | 1037 | |
af19b491 | 1038 | u16 is_up; |
91b7282b RB |
1039 | u16 rx_pvid; |
1040 | u16 tx_pvid; | |
2e9d722d | 1041 | |
af19b491 | 1042 | u32 irq; |
4e70812b | 1043 | u32 heartbeat; |
af19b491 AKS |
1044 | |
1045 | u8 dev_state; | |
aa5e18c0 SC |
1046 | u8 reset_ack_timeo; |
1047 | u8 dev_init_timeo; | |
af19b491 AKS |
1048 | |
1049 | u8 mac_addr[ETH_ALEN]; | |
1050 | ||
6df900e9 | 1051 | u64 dev_rst_time; |
fe1adc6b JK |
1052 | bool drv_mac_learn; |
1053 | bool fdb_mac_learn; | |
b9796a14 | 1054 | unsigned long vlans[BITS_TO_LONGS(VLAN_N_VID)]; |
d865ebb4 | 1055 | u8 flash_mfg_id; |
346fe763 | 1056 | struct qlcnic_npar_info *npars; |
2e9d722d AC |
1057 | struct qlcnic_eswitch *eswitch; |
1058 | struct qlcnic_nic_template *nic_ops; | |
1059 | ||
af19b491 | 1060 | struct qlcnic_adapter_stats stats; |
b1fc6d3c | 1061 | struct list_head mac_list; |
af19b491 AKS |
1062 | |
1063 | void __iomem *tgt_mask_reg; | |
1064 | void __iomem *tgt_status_reg; | |
1065 | void __iomem *crb_int_state_reg; | |
1066 | void __iomem *isr_int_vec; | |
1067 | ||
f94bc1e7 | 1068 | struct msix_entry *msix_entries; |
7f966452 | 1069 | struct workqueue_struct *qlcnic_wq; |
af19b491 | 1070 | struct delayed_work fw_work; |
7f966452 | 1071 | struct delayed_work idc_aen_work; |
7ed3ce48 | 1072 | struct delayed_work mbx_poll_work; |
14d385b9 | 1073 | struct qlcnic_dcb *dcb; |
af19b491 | 1074 | |
b5e5492c | 1075 | struct qlcnic_filter_hash fhash; |
53643a75 | 1076 | struct qlcnic_filter_hash rx_fhash; |
e8b508ef | 1077 | struct list_head vf_mc_list; |
b5e5492c | 1078 | |
b1fc6d3c AC |
1079 | spinlock_t tx_clean_lock; |
1080 | spinlock_t mac_learn_lock; | |
53643a75 SS |
1081 | /* spinlock for catching rcv filters for eswitch traffic */ |
1082 | spinlock_t rx_mac_learn_lock; | |
63507592 | 1083 | u32 file_prd_off; /*File fw product offset*/ |
af19b491 | 1084 | u32 fw_version; |
147a9088 | 1085 | u32 offload_flags; |
af19b491 AKS |
1086 | const struct firmware *fw; |
1087 | }; | |
1088 | ||
63507592 | 1089 | struct qlcnic_info_le { |
2e9d722d | 1090 | __le16 pci_func; |
63507592 | 1091 | __le16 op_mode; /* 1 = Priv, 2 = NP, 3 = NP passthru */ |
2e9d722d | 1092 | __le16 phys_port; |
63507592 | 1093 | __le16 switch_mode; /* 0 = disabled, 1 = int, 2 = ext */ |
2e9d722d AC |
1094 | |
1095 | __le32 capabilities; | |
1096 | u8 max_mac_filters; | |
1097 | u8 reserved1; | |
1098 | __le16 max_mtu; | |
1099 | ||
1100 | __le16 max_tx_ques; | |
1101 | __le16 max_rx_ques; | |
1102 | __le16 min_tx_bw; | |
1103 | __le16 max_tx_bw; | |
7f966452 SC |
1104 | __le32 op_type; |
1105 | __le16 max_bw_reg_offset; | |
1106 | __le16 max_linkspeed_reg_offset; | |
1107 | __le32 capability1; | |
1108 | __le32 capability2; | |
1109 | __le32 capability3; | |
1110 | __le16 max_tx_mac_filters; | |
1111 | __le16 max_rx_mcast_mac_filters; | |
1112 | __le16 max_rx_ucast_mac_filters; | |
1113 | __le16 max_rx_ip_addr; | |
1114 | __le16 max_rx_lro_flow; | |
1115 | __le16 max_rx_status_rings; | |
1116 | __le16 max_rx_buf_rings; | |
1117 | __le16 max_tx_vlan_keys; | |
1118 | u8 total_pf; | |
1119 | u8 total_rss_engines; | |
1120 | __le16 max_vports; | |
02feda17 RB |
1121 | __le16 linkstate_reg_offset; |
1122 | __le16 bit_offsets; | |
1123 | __le16 max_local_ipv6_addrs; | |
1124 | __le16 max_remote_ipv6_addrs; | |
1125 | u8 reserved2[56]; | |
b1fc6d3c | 1126 | } __packed; |
2e9d722d | 1127 | |
63507592 SS |
1128 | struct qlcnic_info { |
1129 | u16 pci_func; | |
1130 | u16 op_mode; | |
1131 | u16 phys_port; | |
1132 | u16 switch_mode; | |
1133 | u32 capabilities; | |
1134 | u8 max_mac_filters; | |
63507592 SS |
1135 | u16 max_mtu; |
1136 | u16 max_tx_ques; | |
1137 | u16 max_rx_ques; | |
1138 | u16 min_tx_bw; | |
1139 | u16 max_tx_bw; | |
7f966452 SC |
1140 | u32 op_type; |
1141 | u16 max_bw_reg_offset; | |
1142 | u16 max_linkspeed_reg_offset; | |
1143 | u32 capability1; | |
1144 | u32 capability2; | |
1145 | u32 capability3; | |
1146 | u16 max_tx_mac_filters; | |
1147 | u16 max_rx_mcast_mac_filters; | |
1148 | u16 max_rx_ucast_mac_filters; | |
1149 | u16 max_rx_ip_addr; | |
1150 | u16 max_rx_lro_flow; | |
1151 | u16 max_rx_status_rings; | |
1152 | u16 max_rx_buf_rings; | |
1153 | u16 max_tx_vlan_keys; | |
1154 | u8 total_pf; | |
1155 | u8 total_rss_engines; | |
1156 | u16 max_vports; | |
02feda17 RB |
1157 | u16 linkstate_reg_offset; |
1158 | u16 bit_offsets; | |
1159 | u16 max_local_ipv6_addrs; | |
1160 | u16 max_remote_ipv6_addrs; | |
63507592 | 1161 | }; |
2e9d722d | 1162 | |
63507592 SS |
1163 | struct qlcnic_pci_info_le { |
1164 | __le16 id; /* pci function id */ | |
1165 | __le16 active; /* 1 = Enabled */ | |
1166 | __le16 type; /* 1 = NIC, 2 = FCoE, 3 = iSCSI */ | |
1167 | __le16 default_port; /* default port number */ | |
1168 | ||
1169 | __le16 tx_min_bw; /* Multiple of 100mbpc */ | |
2e9d722d AC |
1170 | __le16 tx_max_bw; |
1171 | __le16 reserved1[2]; | |
1172 | ||
1173 | u8 mac[ETH_ALEN]; | |
7f966452 SC |
1174 | __le16 func_count; |
1175 | u8 reserved2[104]; | |
1176 | ||
b1fc6d3c | 1177 | } __packed; |
2e9d722d | 1178 | |
63507592 SS |
1179 | struct qlcnic_pci_info { |
1180 | u16 id; | |
1181 | u16 active; | |
1182 | u16 type; | |
1183 | u16 default_port; | |
1184 | u16 tx_min_bw; | |
1185 | u16 tx_max_bw; | |
1186 | u8 mac[ETH_ALEN]; | |
7f966452 | 1187 | u16 func_count; |
63507592 SS |
1188 | }; |
1189 | ||
346fe763 | 1190 | struct qlcnic_npar_info { |
35dafcb0 | 1191 | bool eswitch_status; |
4e8acb01 | 1192 | u16 pvid; |
cea8975e AC |
1193 | u16 min_bw; |
1194 | u16 max_bw; | |
346fe763 RB |
1195 | u8 phy_port; |
1196 | u8 type; | |
1197 | u8 active; | |
1198 | u8 enable_pm; | |
1199 | u8 dest_npar; | |
346fe763 | 1200 | u8 discard_tagged; |
7373373d | 1201 | u8 mac_override; |
4e8acb01 RB |
1202 | u8 mac_anti_spoof; |
1203 | u8 promisc_mode; | |
1204 | u8 offload_flags; | |
bff57d8e | 1205 | u8 pci_func; |
9e630955 | 1206 | u8 mac[ETH_ALEN]; |
346fe763 | 1207 | }; |
4e8acb01 | 1208 | |
2e9d722d AC |
1209 | struct qlcnic_eswitch { |
1210 | u8 port; | |
1211 | u8 active_vports; | |
1212 | u8 active_vlans; | |
1213 | u8 active_ucast_filters; | |
1214 | u8 max_ucast_filters; | |
1215 | u8 max_active_vlans; | |
1216 | ||
1217 | u32 flags; | |
1218 | #define QLCNIC_SWITCH_ENABLE BIT_1 | |
1219 | #define QLCNIC_SWITCH_VLAN_FILTERING BIT_2 | |
1220 | #define QLCNIC_SWITCH_PROMISC_MODE BIT_3 | |
1221 | #define QLCNIC_SWITCH_PORT_MIRRORING BIT_4 | |
1222 | }; | |
1223 | ||
346fe763 RB |
1224 | |
1225 | /* Return codes for Error handling */ | |
1226 | #define QL_STATUS_INVALID_PARAM -1 | |
1227 | ||
2abea2f0 | 1228 | #define MAX_BW 100 /* % of link speed */ |
346fe763 RB |
1229 | #define MAX_VLAN_ID 4095 |
1230 | #define MIN_VLAN_ID 2 | |
346fe763 RB |
1231 | #define DEFAULT_MAC_LEARN 1 |
1232 | ||
0184bbba | 1233 | #define IS_VALID_VLAN(vlan) (vlan >= MIN_VLAN_ID && vlan < MAX_VLAN_ID) |
2abea2f0 | 1234 | #define IS_VALID_BW(bw) (bw <= MAX_BW) |
346fe763 RB |
1235 | |
1236 | struct qlcnic_pci_func_cfg { | |
1237 | u16 func_type; | |
1238 | u16 min_bw; | |
1239 | u16 max_bw; | |
1240 | u16 port_num; | |
1241 | u8 pci_func; | |
1242 | u8 func_state; | |
1243 | u8 def_mac_addr[6]; | |
1244 | }; | |
1245 | ||
1246 | struct qlcnic_npar_func_cfg { | |
1247 | u32 fw_capab; | |
1248 | u16 port_num; | |
1249 | u16 min_bw; | |
1250 | u16 max_bw; | |
1251 | u16 max_tx_queues; | |
1252 | u16 max_rx_queues; | |
1253 | u8 pci_func; | |
1254 | u8 op_mode; | |
1255 | }; | |
1256 | ||
1257 | struct qlcnic_pm_func_cfg { | |
1258 | u8 pci_func; | |
1259 | u8 action; | |
1260 | u8 dest_npar; | |
1261 | u8 reserved[5]; | |
1262 | }; | |
1263 | ||
1264 | struct qlcnic_esw_func_cfg { | |
1265 | u16 vlan_id; | |
4e8acb01 RB |
1266 | u8 op_mode; |
1267 | u8 op_type; | |
346fe763 RB |
1268 | u8 pci_func; |
1269 | u8 host_vlan_tag; | |
1270 | u8 promisc_mode; | |
1271 | u8 discard_tagged; | |
7373373d | 1272 | u8 mac_override; |
4e8acb01 RB |
1273 | u8 mac_anti_spoof; |
1274 | u8 offload_flags; | |
1275 | u8 reserved[5]; | |
346fe763 RB |
1276 | }; |
1277 | ||
b6021212 AKS |
1278 | #define QLCNIC_STATS_VERSION 1 |
1279 | #define QLCNIC_STATS_PORT 1 | |
1280 | #define QLCNIC_STATS_ESWITCH 2 | |
1281 | #define QLCNIC_QUERY_RX_COUNTER 0 | |
1282 | #define QLCNIC_QUERY_TX_COUNTER 1 | |
54a8997c JK |
1283 | #define QLCNIC_STATS_NOT_AVAIL 0xffffffffffffffffULL |
1284 | #define QLCNIC_FILL_STATS(VAL1) \ | |
1285 | (((VAL1) == QLCNIC_STATS_NOT_AVAIL) ? 0 : VAL1) | |
1286 | #define QLCNIC_MAC_STATS 1 | |
1287 | #define QLCNIC_ESW_STATS 2 | |
ef182805 AKS |
1288 | |
1289 | #define QLCNIC_ADD_ESW_STATS(VAL1, VAL2)\ | |
1290 | do { \ | |
54a8997c JK |
1291 | if (((VAL1) == QLCNIC_STATS_NOT_AVAIL) && \ |
1292 | ((VAL2) != QLCNIC_STATS_NOT_AVAIL)) \ | |
ef182805 | 1293 | (VAL1) = (VAL2); \ |
54a8997c JK |
1294 | else if (((VAL1) != QLCNIC_STATS_NOT_AVAIL) && \ |
1295 | ((VAL2) != QLCNIC_STATS_NOT_AVAIL)) \ | |
ef182805 AKS |
1296 | (VAL1) += (VAL2); \ |
1297 | } while (0) | |
1298 | ||
63507592 | 1299 | struct qlcnic_mac_statistics_le { |
54a8997c JK |
1300 | __le64 mac_tx_frames; |
1301 | __le64 mac_tx_bytes; | |
1302 | __le64 mac_tx_mcast_pkts; | |
1303 | __le64 mac_tx_bcast_pkts; | |
1304 | __le64 mac_tx_pause_cnt; | |
1305 | __le64 mac_tx_ctrl_pkt; | |
1306 | __le64 mac_tx_lt_64b_pkts; | |
1307 | __le64 mac_tx_lt_127b_pkts; | |
1308 | __le64 mac_tx_lt_255b_pkts; | |
1309 | __le64 mac_tx_lt_511b_pkts; | |
1310 | __le64 mac_tx_lt_1023b_pkts; | |
1311 | __le64 mac_tx_lt_1518b_pkts; | |
1312 | __le64 mac_tx_gt_1518b_pkts; | |
1313 | __le64 rsvd1[3]; | |
1314 | ||
1315 | __le64 mac_rx_frames; | |
1316 | __le64 mac_rx_bytes; | |
1317 | __le64 mac_rx_mcast_pkts; | |
1318 | __le64 mac_rx_bcast_pkts; | |
1319 | __le64 mac_rx_pause_cnt; | |
1320 | __le64 mac_rx_ctrl_pkt; | |
1321 | __le64 mac_rx_lt_64b_pkts; | |
1322 | __le64 mac_rx_lt_127b_pkts; | |
1323 | __le64 mac_rx_lt_255b_pkts; | |
1324 | __le64 mac_rx_lt_511b_pkts; | |
1325 | __le64 mac_rx_lt_1023b_pkts; | |
1326 | __le64 mac_rx_lt_1518b_pkts; | |
1327 | __le64 mac_rx_gt_1518b_pkts; | |
1328 | __le64 rsvd2[3]; | |
1329 | ||
1330 | __le64 mac_rx_length_error; | |
1331 | __le64 mac_rx_length_small; | |
1332 | __le64 mac_rx_length_large; | |
1333 | __le64 mac_rx_jabber; | |
1334 | __le64 mac_rx_dropped; | |
1335 | __le64 mac_rx_crc_error; | |
1336 | __le64 mac_align_error; | |
1337 | } __packed; | |
1338 | ||
63507592 SS |
1339 | struct qlcnic_mac_statistics { |
1340 | u64 mac_tx_frames; | |
1341 | u64 mac_tx_bytes; | |
1342 | u64 mac_tx_mcast_pkts; | |
1343 | u64 mac_tx_bcast_pkts; | |
1344 | u64 mac_tx_pause_cnt; | |
1345 | u64 mac_tx_ctrl_pkt; | |
1346 | u64 mac_tx_lt_64b_pkts; | |
1347 | u64 mac_tx_lt_127b_pkts; | |
1348 | u64 mac_tx_lt_255b_pkts; | |
1349 | u64 mac_tx_lt_511b_pkts; | |
1350 | u64 mac_tx_lt_1023b_pkts; | |
1351 | u64 mac_tx_lt_1518b_pkts; | |
1352 | u64 mac_tx_gt_1518b_pkts; | |
1353 | u64 rsvd1[3]; | |
1354 | u64 mac_rx_frames; | |
1355 | u64 mac_rx_bytes; | |
1356 | u64 mac_rx_mcast_pkts; | |
1357 | u64 mac_rx_bcast_pkts; | |
1358 | u64 mac_rx_pause_cnt; | |
1359 | u64 mac_rx_ctrl_pkt; | |
1360 | u64 mac_rx_lt_64b_pkts; | |
1361 | u64 mac_rx_lt_127b_pkts; | |
1362 | u64 mac_rx_lt_255b_pkts; | |
1363 | u64 mac_rx_lt_511b_pkts; | |
1364 | u64 mac_rx_lt_1023b_pkts; | |
1365 | u64 mac_rx_lt_1518b_pkts; | |
1366 | u64 mac_rx_gt_1518b_pkts; | |
1367 | u64 rsvd2[3]; | |
1368 | u64 mac_rx_length_error; | |
1369 | u64 mac_rx_length_small; | |
1370 | u64 mac_rx_length_large; | |
1371 | u64 mac_rx_jabber; | |
1372 | u64 mac_rx_dropped; | |
1373 | u64 mac_rx_crc_error; | |
1374 | u64 mac_align_error; | |
1375 | }; | |
1376 | ||
1377 | struct qlcnic_esw_stats_le { | |
b6021212 AKS |
1378 | __le16 context_id; |
1379 | __le16 version; | |
1380 | __le16 size; | |
1381 | __le16 unused; | |
1382 | __le64 unicast_frames; | |
1383 | __le64 multicast_frames; | |
1384 | __le64 broadcast_frames; | |
1385 | __le64 dropped_frames; | |
1386 | __le64 errors; | |
1387 | __le64 local_frames; | |
1388 | __le64 numbytes; | |
1389 | __le64 rsvd[3]; | |
b1fc6d3c | 1390 | } __packed; |
b6021212 | 1391 | |
63507592 SS |
1392 | struct __qlcnic_esw_statistics { |
1393 | u16 context_id; | |
1394 | u16 version; | |
1395 | u16 size; | |
1396 | u16 unused; | |
1397 | u64 unicast_frames; | |
1398 | u64 multicast_frames; | |
1399 | u64 broadcast_frames; | |
1400 | u64 dropped_frames; | |
1401 | u64 errors; | |
1402 | u64 local_frames; | |
1403 | u64 numbytes; | |
1404 | u64 rsvd[3]; | |
1405 | }; | |
1406 | ||
b6021212 AKS |
1407 | struct qlcnic_esw_statistics { |
1408 | struct __qlcnic_esw_statistics rx; | |
1409 | struct __qlcnic_esw_statistics tx; | |
1410 | }; | |
1411 | ||
18f2f616 | 1412 | #define QLCNIC_FORCE_FW_DUMP_KEY 0xdeadfeed |
9d6a6440 AC |
1413 | #define QLCNIC_ENABLE_FW_DUMP 0xaddfeed |
1414 | #define QLCNIC_DISABLE_FW_DUMP 0xbadfeed | |
3d46512c | 1415 | #define QLCNIC_FORCE_FW_RESET 0xdeaddead |
b43e5ee7 SC |
1416 | #define QLCNIC_SET_QUIESCENT 0xadd00010 |
1417 | #define QLCNIC_RESET_QUIESCENT 0xadd00020 | |
18f2f616 | 1418 | |
7777de9a | 1419 | struct _cdrp_cmd { |
7e2cf4fe SC |
1420 | u32 num; |
1421 | u32 *arg; | |
7777de9a AC |
1422 | }; |
1423 | ||
1424 | struct qlcnic_cmd_args { | |
e5c4e6c6 MC |
1425 | struct completion completion; |
1426 | struct list_head list; | |
1427 | struct _cdrp_cmd req; | |
1428 | struct _cdrp_cmd rsp; | |
1429 | atomic_t rsp_status; | |
1430 | int pay_size; | |
1431 | u32 rsp_opcode; | |
1432 | u32 total_cmds; | |
1433 | u32 op_type; | |
1434 | u32 type; | |
1435 | u32 cmd_op; | |
1436 | u32 *hdr; /* Back channel message header */ | |
1437 | u32 *pay; /* Back channel message payload */ | |
1438 | u8 func_num; | |
7777de9a AC |
1439 | }; |
1440 | ||
18f2f616 | 1441 | int qlcnic_fw_cmd_get_minidump_temp(struct qlcnic_adapter *adapter); |
7e610caa | 1442 | int qlcnic_fw_cmd_set_port(struct qlcnic_adapter *adapter, u32 config); |
af19b491 AKS |
1443 | int qlcnic_pci_mem_write_2M(struct qlcnic_adapter *, u64 off, u64 data); |
1444 | int qlcnic_pci_mem_read_2M(struct qlcnic_adapter *, u64 off, u64 *data); | |
897e8c7c DP |
1445 | void qlcnic_pci_camqm_read_2M(struct qlcnic_adapter *, u64, u64 *); |
1446 | void qlcnic_pci_camqm_write_2M(struct qlcnic_adapter *, u64, u64); | |
1447 | ||
1448 | #define ADDR_IN_RANGE(addr, low, high) \ | |
1449 | (((addr) < (high)) && ((addr) >= (low))) | |
af19b491 | 1450 | |
4bd8e738 HM |
1451 | #define QLCRD32(adapter, off, err) \ |
1452 | (adapter->ahw->hw_ops->read_reg)(adapter, off, err) | |
7e2cf4fe | 1453 | |
af19b491 | 1454 | #define QLCWR32(adapter, off, val) \ |
7e2cf4fe | 1455 | adapter->ahw->hw_ops->write_reg(adapter, off, val) |
af19b491 AKS |
1456 | |
1457 | int qlcnic_pcie_sem_lock(struct qlcnic_adapter *, int, u32); | |
1458 | void qlcnic_pcie_sem_unlock(struct qlcnic_adapter *, int); | |
1459 | ||
1460 | #define qlcnic_rom_lock(a) \ | |
1461 | qlcnic_pcie_sem_lock((a), 2, QLCNIC_ROM_LOCK_ID) | |
1462 | #define qlcnic_rom_unlock(a) \ | |
1463 | qlcnic_pcie_sem_unlock((a), 2) | |
1464 | #define qlcnic_phy_lock(a) \ | |
1465 | qlcnic_pcie_sem_lock((a), 3, QLCNIC_PHY_LOCK_ID) | |
1466 | #define qlcnic_phy_unlock(a) \ | |
1467 | qlcnic_pcie_sem_unlock((a), 3) | |
af19b491 AKS |
1468 | #define qlcnic_sw_lock(a) \ |
1469 | qlcnic_pcie_sem_lock((a), 6, 0) | |
1470 | #define qlcnic_sw_unlock(a) \ | |
1471 | qlcnic_pcie_sem_unlock((a), 6) | |
1472 | #define crb_win_lock(a) \ | |
1473 | qlcnic_pcie_sem_lock((a), 7, QLCNIC_CRB_WIN_LOCK_ID) | |
1474 | #define crb_win_unlock(a) \ | |
1475 | qlcnic_pcie_sem_unlock((a), 7) | |
1476 | ||
728a98b8 SC |
1477 | #define __QLCNIC_MAX_LED_RATE 0xf |
1478 | #define __QLCNIC_MAX_LED_STATE 0x2 | |
1479 | ||
58634e74 SC |
1480 | #define MAX_CTL_CHECK 1000 |
1481 | ||
af19b491 | 1482 | int qlcnic_wol_supported(struct qlcnic_adapter *adapter); |
b5e5492c AKS |
1483 | void qlcnic_prune_lb_filters(struct qlcnic_adapter *adapter); |
1484 | void qlcnic_delete_lb_filters(struct qlcnic_adapter *adapter); | |
18f2f616 | 1485 | int qlcnic_dump_fw(struct qlcnic_adapter *); |
890b6e02 SS |
1486 | int qlcnic_enable_fw_dump_state(struct qlcnic_adapter *); |
1487 | bool qlcnic_check_fw_dump_state(struct qlcnic_adapter *); | |
4460f2e8 PP |
1488 | pci_ers_result_t qlcnic_82xx_io_error_detected(struct pci_dev *, |
1489 | pci_channel_state_t); | |
1490 | pci_ers_result_t qlcnic_82xx_io_slot_reset(struct pci_dev *); | |
1491 | void qlcnic_82xx_io_resume(struct pci_dev *); | |
af19b491 AKS |
1492 | |
1493 | /* Functions from qlcnic_init.c */ | |
13159183 | 1494 | void qlcnic_schedule_work(struct qlcnic_adapter *, work_func_t, int); |
af19b491 AKS |
1495 | int qlcnic_load_firmware(struct qlcnic_adapter *adapter); |
1496 | int qlcnic_need_fw_reset(struct qlcnic_adapter *adapter); | |
1497 | void qlcnic_request_firmware(struct qlcnic_adapter *adapter); | |
1498 | void qlcnic_release_firmware(struct qlcnic_adapter *adapter); | |
1499 | int qlcnic_pinit_from_rom(struct qlcnic_adapter *adapter); | |
b3a24649 | 1500 | int qlcnic_setup_idc_param(struct qlcnic_adapter *adapter); |
8f891387 | 1501 | int qlcnic_check_flash_fw_ver(struct qlcnic_adapter *adapter); |
af19b491 | 1502 | |
18f2f616 | 1503 | int qlcnic_rom_fast_read(struct qlcnic_adapter *adapter, u32 addr, u32 *valp); |
af19b491 AKS |
1504 | int qlcnic_rom_fast_read_words(struct qlcnic_adapter *adapter, int addr, |
1505 | u8 *bytes, size_t size); | |
1506 | int qlcnic_alloc_sw_resources(struct qlcnic_adapter *adapter); | |
1507 | void qlcnic_free_sw_resources(struct qlcnic_adapter *adapter); | |
1508 | ||
15087c2b | 1509 | void __iomem *qlcnic_get_ioaddr(struct qlcnic_hardware_context *, u32); |
af19b491 AKS |
1510 | |
1511 | int qlcnic_alloc_hw_resources(struct qlcnic_adapter *adapter); | |
1512 | void qlcnic_free_hw_resources(struct qlcnic_adapter *adapter); | |
1513 | ||
8a15ad1f AKS |
1514 | int qlcnic_fw_create_ctx(struct qlcnic_adapter *adapter); |
1515 | void qlcnic_fw_destroy_ctx(struct qlcnic_adapter *adapter); | |
1516 | ||
1517 | void qlcnic_reset_rx_buffers_list(struct qlcnic_adapter *adapter); | |
af19b491 | 1518 | void qlcnic_release_rx_buffers(struct qlcnic_adapter *adapter); |
012ec812 HM |
1519 | void qlcnic_release_tx_buffers(struct qlcnic_adapter *, |
1520 | struct qlcnic_host_tx_ring *); | |
af19b491 | 1521 | |
d4066833 | 1522 | int qlcnic_check_fw_status(struct qlcnic_adapter *adapter); |
af19b491 | 1523 | void qlcnic_watchdog_task(struct work_struct *work); |
b1fc6d3c | 1524 | void qlcnic_post_rx_buffers(struct qlcnic_adapter *adapter, |
4be41e92 | 1525 | struct qlcnic_host_rds_ring *rds_ring, u8 ring_id); |
af19b491 AKS |
1526 | int qlcnic_process_rcv_ring(struct qlcnic_host_sds_ring *sds_ring, int max); |
1527 | void qlcnic_set_multi(struct net_device *netdev); | |
91b7282b RB |
1528 | void __qlcnic_set_multi(struct net_device *, u16); |
1529 | int qlcnic_nic_add_mac(struct qlcnic_adapter *, const u8 *, u16); | |
fe1adc6b | 1530 | int qlcnic_nic_del_mac(struct qlcnic_adapter *, const u8 *); |
91b7282b | 1531 | void qlcnic_82xx_free_mac_list(struct qlcnic_adapter *adapter); |
07a251c8 | 1532 | int qlcnic_82xx_read_phys_port_id(struct qlcnic_adapter *); |
af19b491 AKS |
1533 | |
1534 | int qlcnic_fw_cmd_set_mtu(struct qlcnic_adapter *adapter, int mtu); | |
8af3f33d | 1535 | int qlcnic_fw_cmd_set_drv_version(struct qlcnic_adapter *, u32); |
af19b491 | 1536 | int qlcnic_change_mtu(struct net_device *netdev, int new_mtu); |
c8f44aff MM |
1537 | netdev_features_t qlcnic_fix_features(struct net_device *netdev, |
1538 | netdev_features_t features); | |
1539 | int qlcnic_set_features(struct net_device *netdev, netdev_features_t features); | |
2e9d722d | 1540 | int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable); |
af19b491 | 1541 | int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter); |
5ad6ff9d | 1542 | void qlcnic_update_cmd_producer(struct qlcnic_host_tx_ring *); |
22c8c934 SC |
1543 | |
1544 | /* Functions from qlcnic_ethtool.c */ | |
ba4468db JK |
1545 | int qlcnic_check_loopback_buff(unsigned char *, u8 []); |
1546 | int qlcnic_do_lb_test(struct qlcnic_adapter *, u8); | |
1547 | int qlcnic_loopback_test(struct net_device *, u8); | |
af19b491 AKS |
1548 | |
1549 | /* Functions from qlcnic_main.c */ | |
1550 | int qlcnic_reset_context(struct qlcnic_adapter *); | |
7eb9855d AKS |
1551 | void qlcnic_diag_free_res(struct net_device *netdev, int max_sds_rings); |
1552 | int qlcnic_diag_alloc_res(struct net_device *netdev, int test); | |
cdaff185 | 1553 | netdev_tx_t qlcnic_xmit_frame(struct sk_buff *skb, struct net_device *netdev); |
aa4a1f7d | 1554 | int qlcnic_set_max_rss(struct qlcnic_adapter *, u8, int); |
6389b76d | 1555 | int qlcnic_validate_max_rss(struct qlcnic_adapter *, __u32); |
80b17be7 | 1556 | int qlcnic_validate_max_tx_rings(struct qlcnic_adapter *, u32 txq); |
e5dcf6dc | 1557 | void qlcnic_alloc_lb_filters_mem(struct qlcnic_adapter *adapter); |
52e493d0 | 1558 | void qlcnic_82xx_set_mac_filter_count(struct qlcnic_adapter *); |
7f966452 | 1559 | int qlcnic_enable_msix(struct qlcnic_adapter *, u32); |
8af3f33d | 1560 | void qlcnic_set_drv_version(struct qlcnic_adapter *); |
af19b491 | 1561 | |
2e9d722d | 1562 | /* eSwitch management functions */ |
4e8acb01 RB |
1563 | int qlcnic_config_switch_port(struct qlcnic_adapter *, |
1564 | struct qlcnic_esw_func_cfg *); | |
629263ac | 1565 | |
4e8acb01 RB |
1566 | int qlcnic_get_eswitch_port_config(struct qlcnic_adapter *, |
1567 | struct qlcnic_esw_func_cfg *); | |
2e9d722d | 1568 | int qlcnic_config_port_mirroring(struct qlcnic_adapter *, u8, u8, u8); |
b6021212 AKS |
1569 | int qlcnic_get_port_stats(struct qlcnic_adapter *, const u8, const u8, |
1570 | struct __qlcnic_esw_statistics *); | |
1571 | int qlcnic_get_eswitch_stats(struct qlcnic_adapter *, const u8, u8, | |
1572 | struct __qlcnic_esw_statistics *); | |
1573 | int qlcnic_clear_esw_stats(struct qlcnic_adapter *adapter, u8, u8, u8); | |
54a8997c | 1574 | int qlcnic_get_mac_stats(struct qlcnic_adapter *, struct qlcnic_mac_statistics *); |
2e9d722d | 1575 | |
7e2cf4fe | 1576 | void qlcnic_free_mbx_args(struct qlcnic_cmd_args *cmd); |
7e2cf4fe | 1577 | |
c70001a9 SC |
1578 | int qlcnic_alloc_sds_rings(struct qlcnic_recv_context *, int); |
1579 | void qlcnic_free_sds_rings(struct qlcnic_recv_context *); | |
7f966452 | 1580 | void qlcnic_advert_link_change(struct qlcnic_adapter *, int); |
c70001a9 SC |
1581 | void qlcnic_free_tx_rings(struct qlcnic_adapter *); |
1582 | int qlcnic_alloc_tx_rings(struct qlcnic_adapter *, struct net_device *); | |
012ec812 | 1583 | void qlcnic_dump_mbx(struct qlcnic_adapter *, struct qlcnic_cmd_args *); |
c70001a9 | 1584 | |
ec079a07 SC |
1585 | void qlcnic_create_sysfs_entries(struct qlcnic_adapter *adapter); |
1586 | void qlcnic_remove_sysfs_entries(struct qlcnic_adapter *adapter); | |
1587 | void qlcnic_create_diag_entries(struct qlcnic_adapter *adapter); | |
1588 | void qlcnic_remove_diag_entries(struct qlcnic_adapter *adapter); | |
7e2cf4fe SC |
1589 | void qlcnic_82xx_add_sysfs(struct qlcnic_adapter *adapter); |
1590 | void qlcnic_82xx_remove_sysfs(struct qlcnic_adapter *adapter); | |
b938662d | 1591 | int qlcnic_82xx_get_settings(struct qlcnic_adapter *, struct ethtool_cmd *); |
7e2cf4fe | 1592 | |
ec079a07 SC |
1593 | int qlcnicvf_config_bridged_mode(struct qlcnic_adapter *, u32); |
1594 | int qlcnicvf_config_led(struct qlcnic_adapter *, u32, u32); | |
1595 | void qlcnic_set_vlan_config(struct qlcnic_adapter *, | |
1596 | struct qlcnic_esw_func_cfg *); | |
1597 | void qlcnic_set_eswitch_port_features(struct qlcnic_adapter *, | |
1598 | struct qlcnic_esw_func_cfg *); | |
629263ac SC |
1599 | |
1600 | void qlcnic_down(struct qlcnic_adapter *, struct net_device *); | |
1601 | int qlcnic_up(struct qlcnic_adapter *, struct net_device *); | |
319ecf12 SC |
1602 | void __qlcnic_down(struct qlcnic_adapter *, struct net_device *); |
1603 | void qlcnic_detach(struct qlcnic_adapter *); | |
1604 | void qlcnic_teardown_intr(struct qlcnic_adapter *); | |
1605 | int qlcnic_attach(struct qlcnic_adapter *); | |
1606 | int __qlcnic_up(struct qlcnic_adapter *, struct net_device *); | |
1607 | void qlcnic_restore_indev_addr(struct net_device *, unsigned long); | |
1608 | ||
629263ac | 1609 | int qlcnic_check_temp(struct qlcnic_adapter *); |
d71170fb SC |
1610 | int qlcnic_init_pci_info(struct qlcnic_adapter *); |
1611 | int qlcnic_set_default_offload_settings(struct qlcnic_adapter *); | |
1612 | int qlcnic_reset_npar_config(struct qlcnic_adapter *); | |
1613 | int qlcnic_set_eswitch_port_config(struct qlcnic_adapter *); | |
f80bc8fe | 1614 | void qlcnic_add_lb_filter(struct qlcnic_adapter *, struct sk_buff *, int, u16); |
487042af | 1615 | int qlcnic_get_beacon_state(struct qlcnic_adapter *, u8 *); |
02feda17 | 1616 | int qlcnic_83xx_configure_opmode(struct qlcnic_adapter *adapter); |
f8468331 RB |
1617 | int qlcnic_read_mac_addr(struct qlcnic_adapter *); |
1618 | int qlcnic_setup_netdev(struct qlcnic_adapter *, struct net_device *, int); | |
147a9088 SS |
1619 | void qlcnic_set_netdev_features(struct qlcnic_adapter *, |
1620 | struct qlcnic_esw_func_cfg *); | |
e8b508ef | 1621 | void qlcnic_sriov_vf_schedule_multi(struct net_device *); |
91b7282b | 1622 | void qlcnic_vf_add_mc_list(struct net_device *, u16); |
f8468331 | 1623 | |
af19b491 AKS |
1624 | /* |
1625 | * QLOGIC Board information | |
1626 | */ | |
1627 | ||
02420be6 | 1628 | #define QLCNIC_MAX_BOARD_NAME_LEN 100 |
22999798 | 1629 | struct qlcnic_board_info { |
af19b491 AKS |
1630 | unsigned short vendor; |
1631 | unsigned short device; | |
1632 | unsigned short sub_vendor; | |
1633 | unsigned short sub_device; | |
1634 | char short_name[QLCNIC_MAX_BOARD_NAME_LEN]; | |
1635 | }; | |
1636 | ||
af19b491 AKS |
1637 | static inline u32 qlcnic_tx_avail(struct qlcnic_host_tx_ring *tx_ring) |
1638 | { | |
036d61f0 | 1639 | if (likely(tx_ring->producer < tx_ring->sw_consumer)) |
af19b491 AKS |
1640 | return tx_ring->sw_consumer - tx_ring->producer; |
1641 | else | |
1642 | return tx_ring->sw_consumer + tx_ring->num_desc - | |
1643 | tx_ring->producer; | |
1644 | } | |
1645 | ||
012ec812 HM |
1646 | static inline int qlcnic_set_real_num_queues(struct qlcnic_adapter *adapter, |
1647 | struct net_device *netdev) | |
1648 | { | |
1649 | int err, tx_q; | |
1650 | ||
1651 | tx_q = adapter->max_drv_tx_rings; | |
1652 | ||
1653 | netdev->num_tx_queues = tx_q; | |
1654 | netdev->real_num_tx_queues = tx_q; | |
1655 | ||
1656 | err = netif_set_real_num_tx_queues(netdev, tx_q); | |
1657 | if (err) | |
1658 | dev_err(&adapter->pdev->dev, "failed to set %d Tx queues\n", | |
1659 | tx_q); | |
1660 | else | |
1661 | dev_info(&adapter->pdev->dev, "set %d Tx queues\n", tx_q); | |
1662 | ||
1663 | return err; | |
1664 | } | |
1665 | ||
7e2cf4fe SC |
1666 | struct qlcnic_nic_template { |
1667 | int (*config_bridged_mode) (struct qlcnic_adapter *, u32); | |
1668 | int (*config_led) (struct qlcnic_adapter *, u32, u32); | |
1669 | int (*start_firmware) (struct qlcnic_adapter *); | |
1670 | int (*init_driver) (struct qlcnic_adapter *); | |
1671 | void (*request_reset) (struct qlcnic_adapter *, u32); | |
1672 | void (*cancel_idc_work) (struct qlcnic_adapter *); | |
1673 | int (*napi_add)(struct qlcnic_adapter *, struct net_device *); | |
4be41e92 | 1674 | void (*napi_del)(struct qlcnic_adapter *); |
7e2cf4fe SC |
1675 | void (*config_ipaddr)(struct qlcnic_adapter *, __be32, int); |
1676 | irqreturn_t (*clear_legacy_intr)(struct qlcnic_adapter *); | |
486a5bc7 RB |
1677 | int (*shutdown)(struct pci_dev *); |
1678 | int (*resume)(struct qlcnic_adapter *); | |
7e2cf4fe SC |
1679 | }; |
1680 | ||
e5c4e6c6 MC |
1681 | struct qlcnic_mbx_ops { |
1682 | int (*enqueue_cmd) (struct qlcnic_adapter *, | |
1683 | struct qlcnic_cmd_args *, unsigned long *); | |
1684 | void (*dequeue_cmd) (struct qlcnic_adapter *, struct qlcnic_cmd_args *); | |
1685 | void (*decode_resp) (struct qlcnic_adapter *, struct qlcnic_cmd_args *); | |
1686 | void (*encode_cmd) (struct qlcnic_adapter *, struct qlcnic_cmd_args *); | |
1687 | void (*nofity_fw) (struct qlcnic_adapter *, u8); | |
1688 | }; | |
1689 | ||
1690 | int qlcnic_83xx_init_mailbox_work(struct qlcnic_adapter *); | |
1691 | void qlcnic_83xx_detach_mailbox_work(struct qlcnic_adapter *); | |
1692 | void qlcnic_83xx_reinit_mbx_work(struct qlcnic_mailbox *mbx); | |
1693 | void qlcnic_83xx_free_mailbox(struct qlcnic_mailbox *mbx); | |
1694 | ||
7e2cf4fe SC |
1695 | /* Adapter hardware abstraction */ |
1696 | struct qlcnic_hardware_ops { | |
1697 | void (*read_crb) (struct qlcnic_adapter *, char *, loff_t, size_t); | |
1698 | void (*write_crb) (struct qlcnic_adapter *, char *, loff_t, size_t); | |
4bd8e738 | 1699 | int (*read_reg) (struct qlcnic_adapter *, ulong, int *); |
7e2cf4fe SC |
1700 | int (*write_reg) (struct qlcnic_adapter *, ulong, u32); |
1701 | void (*get_ocm_win) (struct qlcnic_hardware_context *); | |
07a251c8 | 1702 | int (*get_mac_address) (struct qlcnic_adapter *, u8 *, u8); |
aa4a1f7d | 1703 | int (*setup_intr) (struct qlcnic_adapter *, u8, int); |
7e2cf4fe SC |
1704 | int (*alloc_mbx_args)(struct qlcnic_cmd_args *, |
1705 | struct qlcnic_adapter *, u32); | |
1706 | int (*mbx_cmd) (struct qlcnic_adapter *, struct qlcnic_cmd_args *); | |
1707 | void (*get_func_no) (struct qlcnic_adapter *); | |
1708 | int (*api_lock) (struct qlcnic_adapter *); | |
1709 | void (*api_unlock) (struct qlcnic_adapter *); | |
1710 | void (*add_sysfs) (struct qlcnic_adapter *); | |
1711 | void (*remove_sysfs) (struct qlcnic_adapter *); | |
1712 | void (*process_lb_rcv_ring_diag) (struct qlcnic_host_sds_ring *); | |
1713 | int (*create_rx_ctx) (struct qlcnic_adapter *); | |
1714 | int (*create_tx_ctx) (struct qlcnic_adapter *, | |
1715 | struct qlcnic_host_tx_ring *, int); | |
7cb03b23 RB |
1716 | void (*del_rx_ctx) (struct qlcnic_adapter *); |
1717 | void (*del_tx_ctx) (struct qlcnic_adapter *, | |
1718 | struct qlcnic_host_tx_ring *); | |
7e2cf4fe SC |
1719 | int (*setup_link_event) (struct qlcnic_adapter *, int); |
1720 | int (*get_nic_info) (struct qlcnic_adapter *, struct qlcnic_info *, u8); | |
1721 | int (*get_pci_info) (struct qlcnic_adapter *, struct qlcnic_pci_info *); | |
1722 | int (*set_nic_info) (struct qlcnic_adapter *, struct qlcnic_info *); | |
f80bc8fe | 1723 | int (*change_macvlan) (struct qlcnic_adapter *, u8*, u16, u8); |
7e2cf4fe SC |
1724 | void (*napi_enable) (struct qlcnic_adapter *); |
1725 | void (*napi_disable) (struct qlcnic_adapter *); | |
1726 | void (*config_intr_coal) (struct qlcnic_adapter *); | |
1727 | int (*config_rss) (struct qlcnic_adapter *, int); | |
1728 | int (*config_hw_lro) (struct qlcnic_adapter *, int); | |
1729 | int (*config_loopback) (struct qlcnic_adapter *, u8); | |
1730 | int (*clear_loopback) (struct qlcnic_adapter *, u8); | |
1731 | int (*config_promisc_mode) (struct qlcnic_adapter *, u32); | |
f80bc8fe | 1732 | void (*change_l2_filter) (struct qlcnic_adapter *, u64 *, u16); |
7e2cf4fe | 1733 | int (*get_board_info) (struct qlcnic_adapter *); |
52e493d0 | 1734 | void (*set_mac_filter_count) (struct qlcnic_adapter *); |
91b7282b | 1735 | void (*free_mac_list) (struct qlcnic_adapter *); |
07a251c8 | 1736 | int (*read_phys_port_id) (struct qlcnic_adapter *); |
4460f2e8 PP |
1737 | pci_ers_result_t (*io_error_detected) (struct pci_dev *, |
1738 | pci_channel_state_t); | |
1739 | pci_ers_result_t (*io_slot_reset) (struct pci_dev *); | |
1740 | void (*io_resume) (struct pci_dev *); | |
7e2cf4fe SC |
1741 | }; |
1742 | ||
1743 | extern struct qlcnic_nic_template qlcnic_vf_ops; | |
1744 | ||
1745 | static inline int qlcnic_start_firmware(struct qlcnic_adapter *adapter) | |
1746 | { | |
1747 | return adapter->nic_ops->start_firmware(adapter); | |
1748 | } | |
1749 | ||
1750 | static inline void qlcnic_read_crb(struct qlcnic_adapter *adapter, char *buf, | |
1751 | loff_t offset, size_t size) | |
1752 | { | |
1753 | adapter->ahw->hw_ops->read_crb(adapter, buf, offset, size); | |
1754 | } | |
1755 | ||
1756 | static inline void qlcnic_write_crb(struct qlcnic_adapter *adapter, char *buf, | |
1757 | loff_t offset, size_t size) | |
1758 | { | |
1759 | adapter->ahw->hw_ops->write_crb(adapter, buf, offset, size); | |
1760 | } | |
1761 | ||
7e2cf4fe SC |
1762 | static inline int qlcnic_hw_write_wx_2M(struct qlcnic_adapter *adapter, |
1763 | ulong off, u32 data) | |
1764 | { | |
1765 | return adapter->ahw->hw_ops->write_reg(adapter, off, data); | |
1766 | } | |
1767 | ||
1768 | static inline int qlcnic_get_mac_address(struct qlcnic_adapter *adapter, | |
07a251c8 | 1769 | u8 *mac, u8 function) |
7e2cf4fe | 1770 | { |
07a251c8 | 1771 | return adapter->ahw->hw_ops->get_mac_address(adapter, mac, function); |
7e2cf4fe SC |
1772 | } |
1773 | ||
aa4a1f7d HM |
1774 | static inline int qlcnic_setup_intr(struct qlcnic_adapter *adapter, |
1775 | u8 num_intr, int txq) | |
7e2cf4fe | 1776 | { |
aa4a1f7d | 1777 | return adapter->ahw->hw_ops->setup_intr(adapter, num_intr, txq); |
7e2cf4fe SC |
1778 | } |
1779 | ||
1780 | static inline int qlcnic_alloc_mbx_args(struct qlcnic_cmd_args *mbx, | |
1781 | struct qlcnic_adapter *adapter, u32 arg) | |
1782 | { | |
1783 | return adapter->ahw->hw_ops->alloc_mbx_args(mbx, adapter, arg); | |
1784 | } | |
1785 | ||
1786 | static inline int qlcnic_issue_cmd(struct qlcnic_adapter *adapter, | |
1787 | struct qlcnic_cmd_args *cmd) | |
1788 | { | |
f8468331 RB |
1789 | if (adapter->ahw->hw_ops->mbx_cmd) |
1790 | return adapter->ahw->hw_ops->mbx_cmd(adapter, cmd); | |
1791 | ||
1792 | return -EIO; | |
7e2cf4fe SC |
1793 | } |
1794 | ||
1795 | static inline void qlcnic_get_func_no(struct qlcnic_adapter *adapter) | |
1796 | { | |
1797 | adapter->ahw->hw_ops->get_func_no(adapter); | |
1798 | } | |
1799 | ||
1800 | static inline int qlcnic_api_lock(struct qlcnic_adapter *adapter) | |
1801 | { | |
1802 | return adapter->ahw->hw_ops->api_lock(adapter); | |
1803 | } | |
1804 | ||
1805 | static inline void qlcnic_api_unlock(struct qlcnic_adapter *adapter) | |
1806 | { | |
1807 | adapter->ahw->hw_ops->api_unlock(adapter); | |
1808 | } | |
1809 | ||
1810 | static inline void qlcnic_add_sysfs(struct qlcnic_adapter *adapter) | |
1811 | { | |
f8468331 RB |
1812 | if (adapter->ahw->hw_ops->add_sysfs) |
1813 | adapter->ahw->hw_ops->add_sysfs(adapter); | |
7e2cf4fe SC |
1814 | } |
1815 | ||
1816 | static inline void qlcnic_remove_sysfs(struct qlcnic_adapter *adapter) | |
1817 | { | |
f8468331 RB |
1818 | if (adapter->ahw->hw_ops->remove_sysfs) |
1819 | adapter->ahw->hw_ops->remove_sysfs(adapter); | |
7e2cf4fe SC |
1820 | } |
1821 | ||
1822 | static inline void | |
1823 | qlcnic_process_rcv_ring_diag(struct qlcnic_host_sds_ring *sds_ring) | |
1824 | { | |
1825 | sds_ring->adapter->ahw->hw_ops->process_lb_rcv_ring_diag(sds_ring); | |
1826 | } | |
1827 | ||
1828 | static inline int qlcnic_fw_cmd_create_rx_ctx(struct qlcnic_adapter *adapter) | |
1829 | { | |
1830 | return adapter->ahw->hw_ops->create_rx_ctx(adapter); | |
1831 | } | |
1832 | ||
1833 | static inline int qlcnic_fw_cmd_create_tx_ctx(struct qlcnic_adapter *adapter, | |
1834 | struct qlcnic_host_tx_ring *ptr, | |
1835 | int ring) | |
1836 | { | |
1837 | return adapter->ahw->hw_ops->create_tx_ctx(adapter, ptr, ring); | |
1838 | } | |
1839 | ||
7cb03b23 RB |
1840 | static inline void qlcnic_fw_cmd_del_rx_ctx(struct qlcnic_adapter *adapter) |
1841 | { | |
1842 | return adapter->ahw->hw_ops->del_rx_ctx(adapter); | |
1843 | } | |
1844 | ||
1845 | static inline void qlcnic_fw_cmd_del_tx_ctx(struct qlcnic_adapter *adapter, | |
1846 | struct qlcnic_host_tx_ring *ptr) | |
1847 | { | |
1848 | return adapter->ahw->hw_ops->del_tx_ctx(adapter, ptr); | |
1849 | } | |
1850 | ||
7e2cf4fe SC |
1851 | static inline int qlcnic_linkevent_request(struct qlcnic_adapter *adapter, |
1852 | int enable) | |
1853 | { | |
1854 | return adapter->ahw->hw_ops->setup_link_event(adapter, enable); | |
1855 | } | |
1856 | ||
1857 | static inline int qlcnic_get_nic_info(struct qlcnic_adapter *adapter, | |
1858 | struct qlcnic_info *info, u8 id) | |
1859 | { | |
1860 | return adapter->ahw->hw_ops->get_nic_info(adapter, info, id); | |
1861 | } | |
1862 | ||
1863 | static inline int qlcnic_get_pci_info(struct qlcnic_adapter *adapter, | |
1864 | struct qlcnic_pci_info *info) | |
1865 | { | |
1866 | return adapter->ahw->hw_ops->get_pci_info(adapter, info); | |
1867 | } | |
1868 | ||
1869 | static inline int qlcnic_set_nic_info(struct qlcnic_adapter *adapter, | |
1870 | struct qlcnic_info *info) | |
1871 | { | |
1872 | return adapter->ahw->hw_ops->set_nic_info(adapter, info); | |
1873 | } | |
1874 | ||
1875 | static inline int qlcnic_sre_macaddr_change(struct qlcnic_adapter *adapter, | |
f80bc8fe | 1876 | u8 *addr, u16 id, u8 cmd) |
7e2cf4fe SC |
1877 | { |
1878 | return adapter->ahw->hw_ops->change_macvlan(adapter, addr, id, cmd); | |
1879 | } | |
1880 | ||
1881 | static inline int qlcnic_napi_add(struct qlcnic_adapter *adapter, | |
1882 | struct net_device *netdev) | |
1883 | { | |
1884 | return adapter->nic_ops->napi_add(adapter, netdev); | |
1885 | } | |
1886 | ||
4be41e92 SC |
1887 | static inline void qlcnic_napi_del(struct qlcnic_adapter *adapter) |
1888 | { | |
1889 | adapter->nic_ops->napi_del(adapter); | |
1890 | } | |
1891 | ||
7e2cf4fe SC |
1892 | static inline void qlcnic_napi_enable(struct qlcnic_adapter *adapter) |
1893 | { | |
1894 | adapter->ahw->hw_ops->napi_enable(adapter); | |
1895 | } | |
1896 | ||
486a5bc7 RB |
1897 | static inline int __qlcnic_shutdown(struct pci_dev *pdev) |
1898 | { | |
1899 | struct qlcnic_adapter *adapter = pci_get_drvdata(pdev); | |
1900 | ||
1901 | return adapter->nic_ops->shutdown(pdev); | |
1902 | } | |
1903 | ||
1904 | static inline int __qlcnic_resume(struct qlcnic_adapter *adapter) | |
1905 | { | |
1906 | return adapter->nic_ops->resume(adapter); | |
1907 | } | |
1908 | ||
7e2cf4fe SC |
1909 | static inline void qlcnic_napi_disable(struct qlcnic_adapter *adapter) |
1910 | { | |
1911 | adapter->ahw->hw_ops->napi_disable(adapter); | |
1912 | } | |
1913 | ||
1914 | static inline void qlcnic_config_intr_coalesce(struct qlcnic_adapter *adapter) | |
1915 | { | |
1916 | adapter->ahw->hw_ops->config_intr_coal(adapter); | |
1917 | } | |
1918 | ||
1919 | static inline int qlcnic_config_rss(struct qlcnic_adapter *adapter, int enable) | |
1920 | { | |
1921 | return adapter->ahw->hw_ops->config_rss(adapter, enable); | |
1922 | } | |
1923 | ||
1924 | static inline int qlcnic_config_hw_lro(struct qlcnic_adapter *adapter, | |
1925 | int enable) | |
1926 | { | |
1927 | return adapter->ahw->hw_ops->config_hw_lro(adapter, enable); | |
1928 | } | |
1929 | ||
1930 | static inline int qlcnic_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode) | |
1931 | { | |
1932 | return adapter->ahw->hw_ops->config_loopback(adapter, mode); | |
1933 | } | |
1934 | ||
1935 | static inline int qlcnic_clear_lb_mode(struct qlcnic_adapter *adapter, u8 mode) | |
1936 | { | |
d09529e6 | 1937 | return adapter->ahw->hw_ops->clear_loopback(adapter, mode); |
7e2cf4fe SC |
1938 | } |
1939 | ||
1940 | static inline int qlcnic_nic_set_promisc(struct qlcnic_adapter *adapter, | |
1941 | u32 mode) | |
1942 | { | |
1943 | return adapter->ahw->hw_ops->config_promisc_mode(adapter, mode); | |
1944 | } | |
1945 | ||
1946 | static inline void qlcnic_change_filter(struct qlcnic_adapter *adapter, | |
f80bc8fe | 1947 | u64 *addr, u16 id) |
7e2cf4fe SC |
1948 | { |
1949 | adapter->ahw->hw_ops->change_l2_filter(adapter, addr, id); | |
1950 | } | |
1951 | ||
1952 | static inline int qlcnic_get_board_info(struct qlcnic_adapter *adapter) | |
1953 | { | |
1954 | return adapter->ahw->hw_ops->get_board_info(adapter); | |
1955 | } | |
1956 | ||
91b7282b RB |
1957 | static inline void qlcnic_free_mac_list(struct qlcnic_adapter *adapter) |
1958 | { | |
1959 | return adapter->ahw->hw_ops->free_mac_list(adapter); | |
1960 | } | |
1961 | ||
52e493d0 JK |
1962 | static inline void qlcnic_set_mac_filter_count(struct qlcnic_adapter *adapter) |
1963 | { | |
e9a355a9 SC |
1964 | if (adapter->ahw->hw_ops->set_mac_filter_count) |
1965 | adapter->ahw->hw_ops->set_mac_filter_count(adapter); | |
52e493d0 JK |
1966 | } |
1967 | ||
07a251c8 SS |
1968 | static inline void qlcnic_read_phys_port_id(struct qlcnic_adapter *adapter) |
1969 | { | |
1970 | if (adapter->ahw->hw_ops->read_phys_port_id) | |
1971 | adapter->ahw->hw_ops->read_phys_port_id(adapter); | |
1972 | } | |
1973 | ||
7e2cf4fe SC |
1974 | static inline void qlcnic_dev_request_reset(struct qlcnic_adapter *adapter, |
1975 | u32 key) | |
1976 | { | |
f8468331 RB |
1977 | if (adapter->nic_ops->request_reset) |
1978 | adapter->nic_ops->request_reset(adapter, key); | |
7e2cf4fe SC |
1979 | } |
1980 | ||
1981 | static inline void qlcnic_cancel_idc_work(struct qlcnic_adapter *adapter) | |
1982 | { | |
f8468331 RB |
1983 | if (adapter->nic_ops->cancel_idc_work) |
1984 | adapter->nic_ops->cancel_idc_work(adapter); | |
7e2cf4fe SC |
1985 | } |
1986 | ||
1987 | static inline irqreturn_t | |
1988 | qlcnic_clear_legacy_intr(struct qlcnic_adapter *adapter) | |
1989 | { | |
1990 | return adapter->nic_ops->clear_legacy_intr(adapter); | |
1991 | } | |
1992 | ||
1993 | static inline int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state, | |
1994 | u32 rate) | |
1995 | { | |
1996 | return adapter->nic_ops->config_led(adapter, state, rate); | |
1997 | } | |
1998 | ||
1999 | static inline void qlcnic_config_ipaddr(struct qlcnic_adapter *adapter, | |
2000 | __be32 ip, int cmd) | |
2001 | { | |
2002 | adapter->nic_ops->config_ipaddr(adapter, ip, cmd); | |
2003 | } | |
2004 | ||
012ec812 HM |
2005 | static inline bool qlcnic_check_multi_tx(struct qlcnic_adapter *adapter) |
2006 | { | |
2007 | return test_bit(__QLCNIC_MULTI_TX_UNIQUE, &adapter->state); | |
2008 | } | |
2009 | ||
2010 | static inline void qlcnic_disable_multi_tx(struct qlcnic_adapter *adapter) | |
2011 | { | |
2012 | test_and_clear_bit(__QLCNIC_MULTI_TX_UNIQUE, &adapter->state); | |
2013 | adapter->max_drv_tx_rings = 1; | |
2014 | } | |
2015 | ||
2016 | /* When operating in a muti tx mode, driver needs to write 0x1 | |
2017 | * to src register, instead of 0x0 to disable receiving interrupt. | |
2018 | */ | |
c70001a9 SC |
2019 | static inline void qlcnic_disable_int(struct qlcnic_host_sds_ring *sds_ring) |
2020 | { | |
012ec812 HM |
2021 | struct qlcnic_adapter *adapter = sds_ring->adapter; |
2022 | ||
2023 | if (qlcnic_check_multi_tx(adapter) && | |
c2c5e3a0 | 2024 | !adapter->ahw->diag_test && |
012ec812 HM |
2025 | (adapter->flags & QLCNIC_MSIX_ENABLED)) |
2026 | writel(0x1, sds_ring->crb_intr_mask); | |
2027 | else | |
2028 | writel(0, sds_ring->crb_intr_mask); | |
c70001a9 SC |
2029 | } |
2030 | ||
012ec812 HM |
2031 | /* When operating in a muti tx mode, driver needs to write 0x0 |
2032 | * to src register, instead of 0x1 to enable receiving interrupts. | |
2033 | */ | |
c70001a9 SC |
2034 | static inline void qlcnic_enable_int(struct qlcnic_host_sds_ring *sds_ring) |
2035 | { | |
2036 | struct qlcnic_adapter *adapter = sds_ring->adapter; | |
2037 | ||
012ec812 | 2038 | if (qlcnic_check_multi_tx(adapter) && |
c2c5e3a0 | 2039 | !adapter->ahw->diag_test && |
012ec812 HM |
2040 | (adapter->flags & QLCNIC_MSIX_ENABLED)) |
2041 | writel(0, sds_ring->crb_intr_mask); | |
2042 | else | |
2043 | writel(0x1, sds_ring->crb_intr_mask); | |
c70001a9 SC |
2044 | |
2045 | if (!QLCNIC_IS_MSI_FAMILY(adapter)) | |
2046 | writel(0xfbff, adapter->tgt_mask_reg); | |
2047 | } | |
2048 | ||
4690a7e4 SC |
2049 | static inline int qlcnic_get_diag_lock(struct qlcnic_adapter *adapter) |
2050 | { | |
2051 | return test_and_set_bit(__QLCNIC_DIAG_MODE, &adapter->state); | |
2052 | } | |
2053 | ||
2054 | static inline void qlcnic_release_diag_lock(struct qlcnic_adapter *adapter) | |
2055 | { | |
2056 | clear_bit(__QLCNIC_DIAG_MODE, &adapter->state); | |
2057 | } | |
2058 | ||
099907fa SC |
2059 | static inline int qlcnic_check_diag_status(struct qlcnic_adapter *adapter) |
2060 | { | |
2061 | return test_bit(__QLCNIC_DIAG_MODE, &adapter->state); | |
2062 | } | |
2063 | ||
d1a1105e | 2064 | extern const struct ethtool_ops qlcnic_sriov_vf_ethtool_ops; |
af19b491 | 2065 | extern const struct ethtool_ops qlcnic_ethtool_ops; |
b43e5ee7 | 2066 | extern const struct ethtool_ops qlcnic_ethtool_failed_ops; |
af19b491 | 2067 | |
65b5b420 | 2068 | #define QLCDB(adapter, lvl, _fmt, _args...) do { \ |
79788450 | 2069 | if (NETIF_MSG_##lvl & adapter->ahw->msg_enable) \ |
65b5b420 AKS |
2070 | printk(KERN_INFO "%s: %s: " _fmt, \ |
2071 | dev_name(&adapter->pdev->dev), \ | |
2072 | __func__, ##_args); \ | |
2073 | } while (0) | |
2074 | ||
15ca140f MC |
2075 | #define PCI_DEVICE_ID_QLOGIC_QLE824X 0x8020 |
2076 | #define PCI_DEVICE_ID_QLOGIC_QLE834X 0x8030 | |
f8468331 | 2077 | #define PCI_DEVICE_ID_QLOGIC_VF_QLE834X 0x8430 |
15ca140f MC |
2078 | #define PCI_DEVICE_ID_QLOGIC_QLE844X 0x8040 |
2079 | #define PCI_DEVICE_ID_QLOGIC_VF_QLE844X 0x8440 | |
f8468331 | 2080 | |
97ee45eb SC |
2081 | static inline bool qlcnic_82xx_check(struct qlcnic_adapter *adapter) |
2082 | { | |
2083 | unsigned short device = adapter->pdev->device; | |
2084 | return (device == PCI_DEVICE_ID_QLOGIC_QLE824X) ? true : false; | |
2085 | } | |
2086 | ||
991ca269 MC |
2087 | static inline bool qlcnic_84xx_check(struct qlcnic_adapter *adapter) |
2088 | { | |
2089 | unsigned short device = adapter->pdev->device; | |
2090 | ||
2091 | return ((device == PCI_DEVICE_ID_QLOGIC_QLE844X) || | |
2092 | (device == PCI_DEVICE_ID_QLOGIC_VF_QLE844X)) ? true : false; | |
2093 | } | |
2094 | ||
7f966452 SC |
2095 | static inline bool qlcnic_83xx_check(struct qlcnic_adapter *adapter) |
2096 | { | |
2097 | unsigned short device = adapter->pdev->device; | |
f8468331 RB |
2098 | bool status; |
2099 | ||
2100 | status = ((device == PCI_DEVICE_ID_QLOGIC_QLE834X) || | |
15ca140f MC |
2101 | (device == PCI_DEVICE_ID_QLOGIC_QLE844X) || |
2102 | (device == PCI_DEVICE_ID_QLOGIC_VF_QLE844X) || | |
f8468331 RB |
2103 | (device == PCI_DEVICE_ID_QLOGIC_VF_QLE834X)) ? true : false; |
2104 | ||
2105 | return status; | |
7f966452 SC |
2106 | } |
2107 | ||
02feda17 RB |
2108 | static inline bool qlcnic_sriov_pf_check(struct qlcnic_adapter *adapter) |
2109 | { | |
2110 | return (adapter->ahw->op_mode == QLCNIC_SRIOV_PF_FUNC) ? true : false; | |
2111 | } | |
7f966452 | 2112 | |
f8468331 RB |
2113 | static inline bool qlcnic_sriov_vf_check(struct qlcnic_adapter *adapter) |
2114 | { | |
2115 | unsigned short device = adapter->pdev->device; | |
15ca140f MC |
2116 | bool status; |
2117 | ||
2118 | status = ((device == PCI_DEVICE_ID_QLOGIC_VF_QLE834X) || | |
2119 | (device == PCI_DEVICE_ID_QLOGIC_VF_QLE844X)) ? true : false; | |
f8468331 | 2120 | |
15ca140f | 2121 | return status; |
f8468331 | 2122 | } |
af19b491 | 2123 | #endif /* __QLCNIC_H_ */ |