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Commit | Line | Data |
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577ae39d JK |
1 | /* |
2 | * QLogic qlcnic NIC Driver | |
3 | * Copyright (c) 2009-2013 QLogic Corporation | |
4 | * | |
5 | * See LICENSE.qlcnic for copyright and licensing details. | |
6 | */ | |
7 | ||
7f966452 | 8 | #include "qlcnic.h" |
f8468331 | 9 | #include "qlcnic_sriov.h" |
7f966452 SC |
10 | #include <linux/if_vlan.h> |
11 | #include <linux/ipv6.h> | |
12 | #include <linux/ethtool.h> | |
13 | #include <linux/interrupt.h> | |
9ce226fa | 14 | #include <linux/aer.h> |
7f966452 SC |
15 | |
16 | #define QLCNIC_MAX_TX_QUEUES 1 | |
7f966452 | 17 | #define RSS_HASHTYPE_IP_TCP 0x3 |
f197a7aa | 18 | #define QLC_83XX_FW_MBX_CMD 0 |
7f966452 | 19 | |
7f966452 SC |
20 | static const struct qlcnic_mailbox_metadata qlcnic_83xx_mbx_tbl[] = { |
21 | {QLCNIC_CMD_CONFIGURE_IP_ADDR, 6, 1}, | |
22 | {QLCNIC_CMD_CONFIG_INTRPT, 18, 34}, | |
23 | {QLCNIC_CMD_CREATE_RX_CTX, 136, 27}, | |
24 | {QLCNIC_CMD_DESTROY_RX_CTX, 2, 1}, | |
25 | {QLCNIC_CMD_CREATE_TX_CTX, 54, 18}, | |
26 | {QLCNIC_CMD_DESTROY_TX_CTX, 2, 1}, | |
27 | {QLCNIC_CMD_CONFIGURE_MAC_LEARNING, 2, 1}, | |
28 | {QLCNIC_CMD_INTRPT_TEST, 22, 12}, | |
29 | {QLCNIC_CMD_SET_MTU, 3, 1}, | |
30 | {QLCNIC_CMD_READ_PHY, 4, 2}, | |
31 | {QLCNIC_CMD_WRITE_PHY, 5, 1}, | |
32 | {QLCNIC_CMD_READ_HW_REG, 4, 1}, | |
33 | {QLCNIC_CMD_GET_FLOW_CTL, 4, 2}, | |
34 | {QLCNIC_CMD_SET_FLOW_CTL, 4, 1}, | |
35 | {QLCNIC_CMD_READ_MAX_MTU, 4, 2}, | |
36 | {QLCNIC_CMD_READ_MAX_LRO, 4, 2}, | |
37 | {QLCNIC_CMD_MAC_ADDRESS, 4, 3}, | |
38 | {QLCNIC_CMD_GET_PCI_INFO, 1, 66}, | |
39 | {QLCNIC_CMD_GET_NIC_INFO, 2, 19}, | |
40 | {QLCNIC_CMD_SET_NIC_INFO, 32, 1}, | |
41 | {QLCNIC_CMD_GET_ESWITCH_CAPABILITY, 4, 3}, | |
42 | {QLCNIC_CMD_TOGGLE_ESWITCH, 4, 1}, | |
43 | {QLCNIC_CMD_GET_ESWITCH_STATUS, 4, 3}, | |
44 | {QLCNIC_CMD_SET_PORTMIRRORING, 4, 1}, | |
45 | {QLCNIC_CMD_CONFIGURE_ESWITCH, 4, 1}, | |
46 | {QLCNIC_CMD_GET_ESWITCH_PORT_CONFIG, 4, 3}, | |
47 | {QLCNIC_CMD_GET_ESWITCH_STATS, 5, 1}, | |
48 | {QLCNIC_CMD_CONFIG_PORT, 4, 1}, | |
49 | {QLCNIC_CMD_TEMP_SIZE, 1, 4}, | |
50 | {QLCNIC_CMD_GET_TEMP_HDR, 5, 5}, | |
51 | {QLCNIC_CMD_GET_LINK_EVENT, 2, 1}, | |
52 | {QLCNIC_CMD_CONFIG_MAC_VLAN, 4, 3}, | |
53 | {QLCNIC_CMD_CONFIG_INTR_COAL, 6, 1}, | |
54 | {QLCNIC_CMD_CONFIGURE_RSS, 14, 1}, | |
55 | {QLCNIC_CMD_CONFIGURE_LED, 2, 1}, | |
56 | {QLCNIC_CMD_CONFIGURE_MAC_RX_MODE, 2, 1}, | |
57 | {QLCNIC_CMD_CONFIGURE_HW_LRO, 2, 1}, | |
58 | {QLCNIC_CMD_GET_STATISTICS, 2, 80}, | |
59 | {QLCNIC_CMD_SET_PORT_CONFIG, 2, 1}, | |
60 | {QLCNIC_CMD_GET_PORT_CONFIG, 2, 2}, | |
61 | {QLCNIC_CMD_GET_LINK_STATUS, 2, 4}, | |
62 | {QLCNIC_CMD_IDC_ACK, 5, 1}, | |
63 | {QLCNIC_CMD_INIT_NIC_FUNC, 2, 1}, | |
64 | {QLCNIC_CMD_STOP_NIC_FUNC, 2, 1}, | |
65 | {QLCNIC_CMD_SET_LED_CONFIG, 5, 1}, | |
66 | {QLCNIC_CMD_GET_LED_CONFIG, 1, 5}, | |
8af3f33d | 67 | {QLCNIC_CMD_83XX_SET_DRV_VER, 4, 1}, |
7f966452 | 68 | {QLCNIC_CMD_ADD_RCV_RINGS, 130, 26}, |
02feda17 | 69 | {QLCNIC_CMD_CONFIG_VPORT, 4, 4}, |
f197a7aa | 70 | {QLCNIC_CMD_BC_EVENT_SETUP, 2, 1}, |
14d385b9 | 71 | {QLCNIC_CMD_DCB_QUERY_CAP, 1, 2}, |
fb859ed6 | 72 | {QLCNIC_CMD_DCB_QUERY_PARAM, 2, 50}, |
7f966452 SC |
73 | }; |
74 | ||
f8468331 | 75 | const u32 qlcnic_83xx_ext_reg_tbl[] = { |
7f966452 SC |
76 | 0x38CC, /* Global Reset */ |
77 | 0x38F0, /* Wildcard */ | |
78 | 0x38FC, /* Informant */ | |
79 | 0x3038, /* Host MBX ctrl */ | |
80 | 0x303C, /* FW MBX ctrl */ | |
81 | 0x355C, /* BOOT LOADER ADDRESS REG */ | |
82 | 0x3560, /* BOOT LOADER SIZE REG */ | |
83 | 0x3564, /* FW IMAGE ADDR REG */ | |
84 | 0x1000, /* MBX intr enable */ | |
85 | 0x1200, /* Default Intr mask */ | |
86 | 0x1204, /* Default Interrupt ID */ | |
87 | 0x3780, /* QLC_83XX_IDC_MAJ_VERSION */ | |
88 | 0x3784, /* QLC_83XX_IDC_DEV_STATE */ | |
89 | 0x3788, /* QLC_83XX_IDC_DRV_PRESENCE */ | |
90 | 0x378C, /* QLC_83XX_IDC_DRV_ACK */ | |
91 | 0x3790, /* QLC_83XX_IDC_CTRL */ | |
92 | 0x3794, /* QLC_83XX_IDC_DRV_AUDIT */ | |
93 | 0x3798, /* QLC_83XX_IDC_MIN_VERSION */ | |
94 | 0x379C, /* QLC_83XX_RECOVER_DRV_LOCK */ | |
95 | 0x37A0, /* QLC_83XX_IDC_PF_0 */ | |
96 | 0x37A4, /* QLC_83XX_IDC_PF_1 */ | |
97 | 0x37A8, /* QLC_83XX_IDC_PF_2 */ | |
98 | 0x37AC, /* QLC_83XX_IDC_PF_3 */ | |
99 | 0x37B0, /* QLC_83XX_IDC_PF_4 */ | |
100 | 0x37B4, /* QLC_83XX_IDC_PF_5 */ | |
101 | 0x37B8, /* QLC_83XX_IDC_PF_6 */ | |
102 | 0x37BC, /* QLC_83XX_IDC_PF_7 */ | |
103 | 0x37C0, /* QLC_83XX_IDC_PF_8 */ | |
104 | 0x37C4, /* QLC_83XX_IDC_PF_9 */ | |
105 | 0x37C8, /* QLC_83XX_IDC_PF_10 */ | |
106 | 0x37CC, /* QLC_83XX_IDC_PF_11 */ | |
107 | 0x37D0, /* QLC_83XX_IDC_PF_12 */ | |
108 | 0x37D4, /* QLC_83XX_IDC_PF_13 */ | |
109 | 0x37D8, /* QLC_83XX_IDC_PF_14 */ | |
110 | 0x37DC, /* QLC_83XX_IDC_PF_15 */ | |
111 | 0x37E0, /* QLC_83XX_IDC_DEV_PARTITION_INFO_1 */ | |
112 | 0x37E4, /* QLC_83XX_IDC_DEV_PARTITION_INFO_2 */ | |
113 | 0x37F0, /* QLC_83XX_DRV_OP_MODE */ | |
114 | 0x37F4, /* QLC_83XX_VNIC_STATE */ | |
115 | 0x3868, /* QLC_83XX_DRV_LOCK */ | |
116 | 0x386C, /* QLC_83XX_DRV_UNLOCK */ | |
117 | 0x3504, /* QLC_83XX_DRV_LOCK_ID */ | |
118 | 0x34A4, /* QLC_83XX_ASIC_TEMP */ | |
119 | }; | |
120 | ||
f8468331 | 121 | const u32 qlcnic_83xx_reg_tbl[] = { |
7f966452 SC |
122 | 0x34A8, /* PEG_HALT_STAT1 */ |
123 | 0x34AC, /* PEG_HALT_STAT2 */ | |
124 | 0x34B0, /* FW_HEARTBEAT */ | |
125 | 0x3500, /* FLASH LOCK_ID */ | |
126 | 0x3528, /* FW_CAPABILITIES */ | |
127 | 0x3538, /* Driver active, DRV_REG0 */ | |
128 | 0x3540, /* Device state, DRV_REG1 */ | |
129 | 0x3544, /* Driver state, DRV_REG2 */ | |
130 | 0x3548, /* Driver scratch, DRV_REG3 */ | |
131 | 0x354C, /* Device partiton info, DRV_REG4 */ | |
132 | 0x3524, /* Driver IDC ver, DRV_REG5 */ | |
133 | 0x3550, /* FW_VER_MAJOR */ | |
134 | 0x3554, /* FW_VER_MINOR */ | |
135 | 0x3558, /* FW_VER_SUB */ | |
136 | 0x359C, /* NPAR STATE */ | |
137 | 0x35FC, /* FW_IMG_VALID */ | |
138 | 0x3650, /* CMD_PEG_STATE */ | |
139 | 0x373C, /* RCV_PEG_STATE */ | |
140 | 0x37B4, /* ASIC TEMP */ | |
141 | 0x356C, /* FW API */ | |
142 | 0x3570, /* DRV OP MODE */ | |
143 | 0x3850, /* FLASH LOCK */ | |
144 | 0x3854, /* FLASH UNLOCK */ | |
145 | }; | |
146 | ||
147 | static struct qlcnic_hardware_ops qlcnic_83xx_hw_ops = { | |
148 | .read_crb = qlcnic_83xx_read_crb, | |
149 | .write_crb = qlcnic_83xx_write_crb, | |
150 | .read_reg = qlcnic_83xx_rd_reg_indirect, | |
151 | .write_reg = qlcnic_83xx_wrt_reg_indirect, | |
152 | .get_mac_address = qlcnic_83xx_get_mac_address, | |
153 | .setup_intr = qlcnic_83xx_setup_intr, | |
154 | .alloc_mbx_args = qlcnic_83xx_alloc_mbx_args, | |
e5c4e6c6 | 155 | .mbx_cmd = qlcnic_83xx_issue_cmd, |
7f966452 SC |
156 | .get_func_no = qlcnic_83xx_get_func_no, |
157 | .api_lock = qlcnic_83xx_cam_lock, | |
158 | .api_unlock = qlcnic_83xx_cam_unlock, | |
319ecf12 SC |
159 | .add_sysfs = qlcnic_83xx_add_sysfs, |
160 | .remove_sysfs = qlcnic_83xx_remove_sysfs, | |
4be41e92 | 161 | .process_lb_rcv_ring_diag = qlcnic_83xx_process_rcv_ring_diag, |
7f966452 SC |
162 | .create_rx_ctx = qlcnic_83xx_create_rx_ctx, |
163 | .create_tx_ctx = qlcnic_83xx_create_tx_ctx, | |
7cb03b23 RB |
164 | .del_rx_ctx = qlcnic_83xx_del_rx_ctx, |
165 | .del_tx_ctx = qlcnic_83xx_del_tx_ctx, | |
7f966452 SC |
166 | .setup_link_event = qlcnic_83xx_setup_link_event, |
167 | .get_nic_info = qlcnic_83xx_get_nic_info, | |
168 | .get_pci_info = qlcnic_83xx_get_pci_info, | |
169 | .set_nic_info = qlcnic_83xx_set_nic_info, | |
170 | .change_macvlan = qlcnic_83xx_sre_macaddr_change, | |
4be41e92 SC |
171 | .napi_enable = qlcnic_83xx_napi_enable, |
172 | .napi_disable = qlcnic_83xx_napi_disable, | |
7f966452 SC |
173 | .config_intr_coal = qlcnic_83xx_config_intr_coal, |
174 | .config_rss = qlcnic_83xx_config_rss, | |
175 | .config_hw_lro = qlcnic_83xx_config_hw_lro, | |
7f966452 SC |
176 | .config_promisc_mode = qlcnic_83xx_nic_set_promisc, |
177 | .change_l2_filter = qlcnic_83xx_change_l2_filter, | |
178 | .get_board_info = qlcnic_83xx_get_port_info, | |
52e493d0 | 179 | .set_mac_filter_count = qlcnic_83xx_set_mac_filter_count, |
91b7282b | 180 | .free_mac_list = qlcnic_82xx_free_mac_list, |
9ce226fa PP |
181 | .io_error_detected = qlcnic_83xx_io_error_detected, |
182 | .io_slot_reset = qlcnic_83xx_io_slot_reset, | |
183 | .io_resume = qlcnic_83xx_io_resume, | |
184 | ||
7f966452 SC |
185 | }; |
186 | ||
187 | static struct qlcnic_nic_template qlcnic_83xx_ops = { | |
188 | .config_bridged_mode = qlcnic_config_bridged_mode, | |
189 | .config_led = qlcnic_config_led, | |
629263ac SC |
190 | .request_reset = qlcnic_83xx_idc_request_reset, |
191 | .cancel_idc_work = qlcnic_83xx_idc_exit, | |
4be41e92 SC |
192 | .napi_add = qlcnic_83xx_napi_add, |
193 | .napi_del = qlcnic_83xx_napi_del, | |
7f966452 SC |
194 | .config_ipaddr = qlcnic_83xx_config_ipaddr, |
195 | .clear_legacy_intr = qlcnic_83xx_clear_legacy_intr, | |
486a5bc7 RB |
196 | .shutdown = qlcnic_83xx_shutdown, |
197 | .resume = qlcnic_83xx_resume, | |
7f966452 SC |
198 | }; |
199 | ||
200 | void qlcnic_83xx_register_map(struct qlcnic_hardware_context *ahw) | |
201 | { | |
202 | ahw->hw_ops = &qlcnic_83xx_hw_ops; | |
203 | ahw->reg_tbl = (u32 *)qlcnic_83xx_reg_tbl; | |
204 | ahw->ext_reg_tbl = (u32 *)qlcnic_83xx_ext_reg_tbl; | |
205 | } | |
206 | ||
207 | int qlcnic_83xx_get_fw_version(struct qlcnic_adapter *adapter) | |
208 | { | |
209 | u32 fw_major, fw_minor, fw_build; | |
210 | struct pci_dev *pdev = adapter->pdev; | |
211 | ||
212 | fw_major = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MAJOR); | |
213 | fw_minor = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MINOR); | |
214 | fw_build = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_SUB); | |
215 | adapter->fw_version = QLCNIC_VERSION_CODE(fw_major, fw_minor, fw_build); | |
216 | ||
217 | dev_info(&pdev->dev, "Driver v%s, firmware version %d.%d.%d\n", | |
218 | QLCNIC_LINUX_VERSIONID, fw_major, fw_minor, fw_build); | |
219 | ||
220 | return adapter->fw_version; | |
221 | } | |
222 | ||
223 | static int __qlcnic_set_win_base(struct qlcnic_adapter *adapter, u32 addr) | |
224 | { | |
225 | void __iomem *base; | |
226 | u32 val; | |
227 | ||
228 | base = adapter->ahw->pci_base0 + | |
229 | QLC_83XX_CRB_WIN_FUNC(adapter->ahw->pci_func); | |
230 | writel(addr, base); | |
231 | val = readl(base); | |
232 | if (val != addr) | |
233 | return -EIO; | |
234 | ||
235 | return 0; | |
236 | } | |
237 | ||
4bd8e738 HM |
238 | int qlcnic_83xx_rd_reg_indirect(struct qlcnic_adapter *adapter, ulong addr, |
239 | int *err) | |
7f966452 | 240 | { |
7f966452 SC |
241 | struct qlcnic_hardware_context *ahw = adapter->ahw; |
242 | ||
4bd8e738 HM |
243 | *err = __qlcnic_set_win_base(adapter, (u32) addr); |
244 | if (!*err) { | |
7f966452 SC |
245 | return QLCRDX(ahw, QLCNIC_WILDCARD); |
246 | } else { | |
247 | dev_err(&adapter->pdev->dev, | |
4bd8e738 | 248 | "%s failed, addr = 0x%lx\n", __func__, addr); |
7f966452 SC |
249 | return -EIO; |
250 | } | |
251 | } | |
252 | ||
253 | int qlcnic_83xx_wrt_reg_indirect(struct qlcnic_adapter *adapter, ulong addr, | |
254 | u32 data) | |
255 | { | |
256 | int err; | |
257 | struct qlcnic_hardware_context *ahw = adapter->ahw; | |
258 | ||
259 | err = __qlcnic_set_win_base(adapter, (u32) addr); | |
260 | if (!err) { | |
261 | QLCWRX(ahw, QLCNIC_WILDCARD, data); | |
262 | return 0; | |
263 | } else { | |
264 | dev_err(&adapter->pdev->dev, | |
265 | "%s failed, addr = 0x%x data = 0x%x\n", | |
266 | __func__, (int)addr, data); | |
267 | return err; | |
268 | } | |
269 | } | |
270 | ||
aa4a1f7d | 271 | int qlcnic_83xx_setup_intr(struct qlcnic_adapter *adapter, u8 num_intr, int txq) |
7f966452 SC |
272 | { |
273 | int err, i, num_msix; | |
274 | struct qlcnic_hardware_context *ahw = adapter->ahw; | |
275 | ||
276 | if (!num_intr) | |
277 | num_intr = QLCNIC_DEF_NUM_STS_DESC_RINGS; | |
278 | num_msix = rounddown_pow_of_two(min_t(int, num_online_cpus(), | |
279 | num_intr)); | |
280 | /* account for AEN interrupt MSI-X based interrupts */ | |
281 | num_msix += 1; | |
da6c8063 RB |
282 | |
283 | if (!(adapter->flags & QLCNIC_TX_INTR_SHARED)) | |
284 | num_msix += adapter->max_drv_tx_rings; | |
285 | ||
7f966452 SC |
286 | err = qlcnic_enable_msix(adapter, num_msix); |
287 | if (err == -ENOMEM) | |
288 | return err; | |
289 | if (adapter->flags & QLCNIC_MSIX_ENABLED) | |
290 | num_msix = adapter->ahw->num_msix; | |
f8468331 RB |
291 | else { |
292 | if (qlcnic_sriov_vf_check(adapter)) | |
293 | return -EINVAL; | |
7f966452 | 294 | num_msix = 1; |
f8468331 | 295 | } |
7f966452 SC |
296 | /* setup interrupt mapping table for fw */ |
297 | ahw->intr_tbl = vzalloc(num_msix * | |
298 | sizeof(struct qlcnic_intrpt_config)); | |
299 | if (!ahw->intr_tbl) | |
300 | return -ENOMEM; | |
301 | if (!(adapter->flags & QLCNIC_MSIX_ENABLED)) { | |
302 | /* MSI-X enablement failed, use legacy interrupt */ | |
303 | adapter->tgt_status_reg = ahw->pci_base0 + QLC_83XX_INTX_PTR; | |
304 | adapter->tgt_mask_reg = ahw->pci_base0 + QLC_83XX_INTX_MASK; | |
305 | adapter->isr_int_vec = ahw->pci_base0 + QLC_83XX_INTX_TRGR; | |
306 | adapter->msix_entries[0].vector = adapter->pdev->irq; | |
307 | dev_info(&adapter->pdev->dev, "using legacy interrupt\n"); | |
308 | } | |
309 | ||
310 | for (i = 0; i < num_msix; i++) { | |
311 | if (adapter->flags & QLCNIC_MSIX_ENABLED) | |
312 | ahw->intr_tbl[i].type = QLCNIC_INTRPT_MSIX; | |
313 | else | |
314 | ahw->intr_tbl[i].type = QLCNIC_INTRPT_INTX; | |
315 | ahw->intr_tbl[i].id = i; | |
316 | ahw->intr_tbl[i].src = 0; | |
317 | } | |
318 | return 0; | |
319 | } | |
320 | ||
ac166700 HM |
321 | inline void qlcnic_83xx_clear_legacy_intr_mask(struct qlcnic_adapter *adapter) |
322 | { | |
323 | writel(0, adapter->tgt_mask_reg); | |
324 | } | |
325 | ||
45ef92ed HM |
326 | inline void qlcnic_83xx_set_legacy_intr_mask(struct qlcnic_adapter *adapter) |
327 | { | |
328 | writel(1, adapter->tgt_mask_reg); | |
329 | } | |
330 | ||
ac166700 HM |
331 | /* Enable MSI-x and INT-x interrupts */ |
332 | void qlcnic_83xx_enable_intr(struct qlcnic_adapter *adapter, | |
333 | struct qlcnic_host_sds_ring *sds_ring) | |
7f966452 SC |
334 | { |
335 | writel(0, sds_ring->crb_intr_mask); | |
ac166700 HM |
336 | } |
337 | ||
338 | /* Disable MSI-x and INT-x interrupts */ | |
339 | void qlcnic_83xx_disable_intr(struct qlcnic_adapter *adapter, | |
340 | struct qlcnic_host_sds_ring *sds_ring) | |
341 | { | |
342 | writel(1, sds_ring->crb_intr_mask); | |
343 | } | |
344 | ||
345 | inline void qlcnic_83xx_enable_legacy_msix_mbx_intr(struct qlcnic_adapter | |
346 | *adapter) | |
347 | { | |
348 | u32 mask; | |
349 | ||
350 | /* Mailbox in MSI-x mode and Legacy Interrupt share the same | |
351 | * source register. We could be here before contexts are created | |
352 | * and sds_ring->crb_intr_mask has not been initialized, calculate | |
353 | * BAR offset for Interrupt Source Register | |
354 | */ | |
355 | mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK); | |
356 | writel(0, adapter->ahw->pci_base0 + mask); | |
357 | } | |
358 | ||
f036e4f4 | 359 | void qlcnic_83xx_disable_mbx_intr(struct qlcnic_adapter *adapter) |
ac166700 HM |
360 | { |
361 | u32 mask; | |
362 | ||
363 | mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK); | |
364 | writel(1, adapter->ahw->pci_base0 + mask); | |
f036e4f4 | 365 | QLCWRX(adapter->ahw, QLCNIC_MBX_INTR_ENBL, 0); |
7f966452 SC |
366 | } |
367 | ||
368 | static inline void qlcnic_83xx_get_mbx_data(struct qlcnic_adapter *adapter, | |
369 | struct qlcnic_cmd_args *cmd) | |
370 | { | |
371 | int i; | |
068a8d19 MC |
372 | |
373 | if (cmd->op_type == QLC_83XX_MBX_POST_BC_OP) | |
374 | return; | |
375 | ||
7f966452 SC |
376 | for (i = 0; i < cmd->rsp.num; i++) |
377 | cmd->rsp.arg[i] = readl(QLCNIC_MBX_FW(adapter->ahw, i)); | |
378 | } | |
379 | ||
380 | irqreturn_t qlcnic_83xx_clear_legacy_intr(struct qlcnic_adapter *adapter) | |
381 | { | |
382 | u32 intr_val; | |
383 | struct qlcnic_hardware_context *ahw = adapter->ahw; | |
384 | int retries = 0; | |
385 | ||
386 | intr_val = readl(adapter->tgt_status_reg); | |
387 | ||
388 | if (!QLC_83XX_VALID_INTX_BIT31(intr_val)) | |
389 | return IRQ_NONE; | |
390 | ||
391 | if (QLC_83XX_INTX_FUNC(intr_val) != adapter->ahw->pci_func) { | |
392 | adapter->stats.spurious_intr++; | |
393 | return IRQ_NONE; | |
394 | } | |
ac166700 HM |
395 | /* The barrier is required to ensure writes to the registers */ |
396 | wmb(); | |
397 | ||
7f966452 SC |
398 | /* clear the interrupt trigger control register */ |
399 | writel(0, adapter->isr_int_vec); | |
ac166700 | 400 | intr_val = readl(adapter->isr_int_vec); |
7f966452 SC |
401 | do { |
402 | intr_val = readl(adapter->tgt_status_reg); | |
403 | if (QLC_83XX_INTX_FUNC(intr_val) != ahw->pci_func) | |
404 | break; | |
405 | retries++; | |
406 | } while (QLC_83XX_VALID_INTX_BIT30(intr_val) && | |
407 | (retries < QLC_83XX_LEGACY_INTX_MAX_RETRY)); | |
408 | ||
ac166700 HM |
409 | return IRQ_HANDLED; |
410 | } | |
411 | ||
e5c4e6c6 MC |
412 | static inline void qlcnic_83xx_notify_mbx_response(struct qlcnic_mailbox *mbx) |
413 | { | |
414 | atomic_set(&mbx->rsp_status, QLC_83XX_MBX_RESPONSE_ARRIVED); | |
415 | complete(&mbx->completion); | |
416 | } | |
417 | ||
ac166700 HM |
418 | static void qlcnic_83xx_poll_process_aen(struct qlcnic_adapter *adapter) |
419 | { | |
068a8d19 MC |
420 | u32 resp, event, rsp_status = QLC_83XX_MBX_RESPONSE_ARRIVED; |
421 | struct qlcnic_mailbox *mbx = adapter->ahw->mailbox; | |
ac166700 HM |
422 | unsigned long flags; |
423 | ||
068a8d19 | 424 | spin_lock_irqsave(&mbx->aen_lock, flags); |
ac166700 HM |
425 | resp = QLCRDX(adapter->ahw, QLCNIC_FW_MBX_CTRL); |
426 | if (!(resp & QLCNIC_SET_OWNER)) | |
427 | goto out; | |
428 | ||
429 | event = readl(QLCNIC_MBX_FW(adapter->ahw, 0)); | |
068a8d19 | 430 | if (event & QLCNIC_MBX_ASYNC_EVENT) { |
d1a1105e | 431 | __qlcnic_83xx_process_aen(adapter); |
068a8d19 MC |
432 | } else { |
433 | if (atomic_read(&mbx->rsp_status) != rsp_status) | |
434 | qlcnic_83xx_notify_mbx_response(mbx); | |
435 | } | |
ac166700 HM |
436 | out: |
437 | qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter); | |
068a8d19 | 438 | spin_unlock_irqrestore(&mbx->aen_lock, flags); |
ac166700 HM |
439 | } |
440 | ||
441 | irqreturn_t qlcnic_83xx_intr(int irq, void *data) | |
442 | { | |
443 | struct qlcnic_adapter *adapter = data; | |
444 | struct qlcnic_host_sds_ring *sds_ring; | |
445 | struct qlcnic_hardware_context *ahw = adapter->ahw; | |
446 | ||
447 | if (qlcnic_83xx_clear_legacy_intr(adapter) == IRQ_NONE) | |
7f966452 | 448 | return IRQ_NONE; |
ac166700 HM |
449 | |
450 | qlcnic_83xx_poll_process_aen(adapter); | |
451 | ||
452 | if (ahw->diag_test == QLCNIC_INTERRUPT_TEST) { | |
453 | ahw->diag_cnt++; | |
454 | qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter); | |
455 | return IRQ_HANDLED; | |
7f966452 SC |
456 | } |
457 | ||
ac166700 HM |
458 | if (!test_bit(__QLCNIC_DEV_UP, &adapter->state)) { |
459 | qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter); | |
460 | } else { | |
461 | sds_ring = &adapter->recv_ctx->sds_rings[0]; | |
462 | napi_schedule(&sds_ring->napi); | |
463 | } | |
7f966452 SC |
464 | |
465 | return IRQ_HANDLED; | |
466 | } | |
467 | ||
468 | irqreturn_t qlcnic_83xx_tmp_intr(int irq, void *data) | |
469 | { | |
470 | struct qlcnic_host_sds_ring *sds_ring = data; | |
471 | struct qlcnic_adapter *adapter = sds_ring->adapter; | |
472 | ||
473 | if (adapter->flags & QLCNIC_MSIX_ENABLED) | |
474 | goto done; | |
475 | ||
476 | if (adapter->nic_ops->clear_legacy_intr(adapter) == IRQ_NONE) | |
477 | return IRQ_NONE; | |
478 | ||
479 | done: | |
480 | adapter->ahw->diag_cnt++; | |
481 | qlcnic_83xx_enable_intr(adapter, sds_ring); | |
482 | ||
483 | return IRQ_HANDLED; | |
484 | } | |
485 | ||
486 | void qlcnic_83xx_free_mbx_intr(struct qlcnic_adapter *adapter) | |
487 | { | |
f036e4f4 RB |
488 | u32 num_msix; |
489 | ||
45ef92ed HM |
490 | if (!(adapter->flags & QLCNIC_MSIX_ENABLED)) |
491 | qlcnic_83xx_set_legacy_intr_mask(adapter); | |
492 | ||
f036e4f4 | 493 | qlcnic_83xx_disable_mbx_intr(adapter); |
7f966452 | 494 | |
ac166700 HM |
495 | if (adapter->flags & QLCNIC_MSIX_ENABLED) |
496 | num_msix = adapter->ahw->num_msix - 1; | |
497 | else | |
498 | num_msix = 0; | |
7f966452 | 499 | |
ac166700 HM |
500 | msleep(20); |
501 | synchronize_irq(adapter->msix_entries[num_msix].vector); | |
502 | free_irq(adapter->msix_entries[num_msix].vector, adapter); | |
7f966452 SC |
503 | } |
504 | ||
505 | int qlcnic_83xx_setup_mbx_intr(struct qlcnic_adapter *adapter) | |
506 | { | |
507 | irq_handler_t handler; | |
508 | u32 val; | |
7f966452 SC |
509 | int err = 0; |
510 | unsigned long flags = 0; | |
511 | ||
512 | if (!(adapter->flags & QLCNIC_MSI_ENABLED) && | |
513 | !(adapter->flags & QLCNIC_MSIX_ENABLED)) | |
514 | flags |= IRQF_SHARED; | |
515 | ||
516 | if (adapter->flags & QLCNIC_MSIX_ENABLED) { | |
517 | handler = qlcnic_83xx_handle_aen; | |
518 | val = adapter->msix_entries[adapter->ahw->num_msix - 1].vector; | |
aa2a8034 | 519 | err = request_irq(val, handler, flags, "qlcnic-MB", adapter); |
7f966452 SC |
520 | if (err) { |
521 | dev_err(&adapter->pdev->dev, | |
522 | "failed to register MBX interrupt\n"); | |
523 | return err; | |
524 | } | |
ac166700 HM |
525 | } else { |
526 | handler = qlcnic_83xx_intr; | |
527 | val = adapter->msix_entries[0].vector; | |
528 | err = request_irq(val, handler, flags, "qlcnic", adapter); | |
529 | if (err) { | |
530 | dev_err(&adapter->pdev->dev, | |
531 | "failed to register INTx interrupt\n"); | |
532 | return err; | |
533 | } | |
534 | qlcnic_83xx_clear_legacy_intr_mask(adapter); | |
7f966452 SC |
535 | } |
536 | ||
537 | /* Enable mailbox interrupt */ | |
e5c4e6c6 | 538 | qlcnic_83xx_enable_mbx_interrupt(adapter); |
7f966452 SC |
539 | |
540 | return err; | |
541 | } | |
542 | ||
543 | void qlcnic_83xx_get_func_no(struct qlcnic_adapter *adapter) | |
544 | { | |
545 | u32 val = QLCRDX(adapter->ahw, QLCNIC_INFORMANT); | |
f8468331 | 546 | adapter->ahw->pci_func = (val >> 24) & 0xff; |
7f966452 SC |
547 | } |
548 | ||
549 | int qlcnic_83xx_cam_lock(struct qlcnic_adapter *adapter) | |
550 | { | |
551 | void __iomem *addr; | |
552 | u32 val, limit = 0; | |
553 | ||
554 | struct qlcnic_hardware_context *ahw = adapter->ahw; | |
555 | ||
556 | addr = ahw->pci_base0 + QLC_83XX_SEM_LOCK_FUNC(ahw->pci_func); | |
557 | do { | |
558 | val = readl(addr); | |
559 | if (val) { | |
560 | /* write the function number to register */ | |
561 | QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER, | |
562 | ahw->pci_func); | |
563 | return 0; | |
564 | } | |
565 | usleep_range(1000, 2000); | |
566 | } while (++limit <= QLCNIC_PCIE_SEM_TIMEOUT); | |
567 | ||
568 | return -EIO; | |
569 | } | |
570 | ||
571 | void qlcnic_83xx_cam_unlock(struct qlcnic_adapter *adapter) | |
572 | { | |
573 | void __iomem *addr; | |
574 | u32 val; | |
575 | struct qlcnic_hardware_context *ahw = adapter->ahw; | |
576 | ||
577 | addr = ahw->pci_base0 + QLC_83XX_SEM_UNLOCK_FUNC(ahw->pci_func); | |
578 | val = readl(addr); | |
579 | } | |
580 | ||
581 | void qlcnic_83xx_read_crb(struct qlcnic_adapter *adapter, char *buf, | |
582 | loff_t offset, size_t size) | |
583 | { | |
4bd8e738 | 584 | int ret = 0; |
7f966452 SC |
585 | u32 data; |
586 | ||
587 | if (qlcnic_api_lock(adapter)) { | |
588 | dev_err(&adapter->pdev->dev, | |
589 | "%s: failed to acquire lock. addr offset 0x%x\n", | |
590 | __func__, (u32)offset); | |
591 | return; | |
592 | } | |
593 | ||
4bd8e738 | 594 | data = QLCRD32(adapter, (u32) offset, &ret); |
7f966452 SC |
595 | qlcnic_api_unlock(adapter); |
596 | ||
597 | if (ret == -EIO) { | |
598 | dev_err(&adapter->pdev->dev, | |
599 | "%s: failed. addr offset 0x%x\n", | |
600 | __func__, (u32)offset); | |
601 | return; | |
602 | } | |
7f966452 SC |
603 | memcpy(buf, &data, size); |
604 | } | |
605 | ||
606 | void qlcnic_83xx_write_crb(struct qlcnic_adapter *adapter, char *buf, | |
607 | loff_t offset, size_t size) | |
608 | { | |
609 | u32 data; | |
610 | ||
611 | memcpy(&data, buf, size); | |
612 | qlcnic_83xx_wrt_reg_indirect(adapter, (u32) offset, data); | |
613 | } | |
614 | ||
615 | int qlcnic_83xx_get_port_info(struct qlcnic_adapter *adapter) | |
616 | { | |
617 | int status; | |
618 | ||
619 | status = qlcnic_83xx_get_port_config(adapter); | |
620 | if (status) { | |
621 | dev_err(&adapter->pdev->dev, | |
622 | "Get Port Info failed\n"); | |
623 | } else { | |
624 | if (QLC_83XX_SFP_10G_CAPABLE(adapter->ahw->port_config)) | |
625 | adapter->ahw->port_type = QLCNIC_XGBE; | |
626 | else | |
627 | adapter->ahw->port_type = QLCNIC_GBE; | |
629263ac | 628 | |
7f966452 SC |
629 | if (QLC_83XX_AUTONEG(adapter->ahw->port_config)) |
630 | adapter->ahw->link_autoneg = AUTONEG_ENABLE; | |
631 | } | |
632 | return status; | |
633 | } | |
634 | ||
52e493d0 JK |
635 | void qlcnic_83xx_set_mac_filter_count(struct qlcnic_adapter *adapter) |
636 | { | |
637 | struct qlcnic_hardware_context *ahw = adapter->ahw; | |
638 | u16 act_pci_fn = ahw->act_pci_func; | |
639 | u16 count; | |
640 | ||
641 | ahw->max_mc_count = QLC_83XX_MAX_MC_COUNT; | |
642 | if (act_pci_fn <= 2) | |
643 | count = (QLC_83XX_MAX_UC_COUNT - QLC_83XX_MAX_MC_COUNT) / | |
644 | act_pci_fn; | |
645 | else | |
646 | count = (QLC_83XX_LB_MAX_FILTERS - QLC_83XX_MAX_MC_COUNT) / | |
647 | act_pci_fn; | |
648 | ahw->max_uc_count = count; | |
649 | } | |
650 | ||
e5c4e6c6 | 651 | void qlcnic_83xx_enable_mbx_interrupt(struct qlcnic_adapter *adapter) |
7f966452 SC |
652 | { |
653 | u32 val; | |
654 | ||
655 | if (adapter->flags & QLCNIC_MSIX_ENABLED) | |
656 | val = BIT_2 | ((adapter->ahw->num_msix - 1) << 8); | |
657 | else | |
658 | val = BIT_2; | |
629263ac | 659 | |
7f966452 | 660 | QLCWRX(adapter->ahw, QLCNIC_MBX_INTR_ENBL, val); |
ac166700 | 661 | qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter); |
7f966452 SC |
662 | } |
663 | ||
664 | void qlcnic_83xx_check_vf(struct qlcnic_adapter *adapter, | |
665 | const struct pci_device_id *ent) | |
666 | { | |
667 | u32 op_mode, priv_level; | |
668 | struct qlcnic_hardware_context *ahw = adapter->ahw; | |
669 | ||
7f966452 | 670 | ahw->fw_hal_version = 2; |
7f966452 SC |
671 | qlcnic_get_func_no(adapter); |
672 | ||
f8468331 RB |
673 | if (qlcnic_sriov_vf_check(adapter)) { |
674 | qlcnic_sriov_vf_set_ops(adapter); | |
675 | return; | |
676 | } | |
677 | ||
7f966452 SC |
678 | /* Determine function privilege level */ |
679 | op_mode = QLCRDX(adapter->ahw, QLC_83XX_DRV_OP_MODE); | |
680 | if (op_mode == QLC_83XX_DEFAULT_OPMODE) | |
681 | priv_level = QLCNIC_MGMT_FUNC; | |
682 | else | |
683 | priv_level = QLC_83XX_GET_FUNC_PRIVILEGE(op_mode, | |
684 | ahw->pci_func); | |
685 | ||
686 | if (priv_level == QLCNIC_NON_PRIV_FUNC) { | |
687 | ahw->op_mode = QLCNIC_NON_PRIV_FUNC; | |
688 | dev_info(&adapter->pdev->dev, | |
689 | "HAL Version: %d Non Privileged function\n", | |
690 | ahw->fw_hal_version); | |
691 | adapter->nic_ops = &qlcnic_vf_ops; | |
692 | } else { | |
02feda17 RB |
693 | if (pci_find_ext_capability(adapter->pdev, |
694 | PCI_EXT_CAP_ID_SRIOV)) | |
695 | set_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state); | |
7f966452 SC |
696 | adapter->nic_ops = &qlcnic_83xx_ops; |
697 | } | |
698 | } | |
699 | ||
700 | static void qlcnic_83xx_handle_link_aen(struct qlcnic_adapter *adapter, | |
701 | u32 data[]); | |
702 | static void qlcnic_83xx_handle_idc_comp_aen(struct qlcnic_adapter *adapter, | |
703 | u32 data[]); | |
704 | ||
012ec812 HM |
705 | void qlcnic_dump_mbx(struct qlcnic_adapter *adapter, |
706 | struct qlcnic_cmd_args *cmd) | |
7f966452 SC |
707 | { |
708 | int i; | |
709 | ||
068a8d19 MC |
710 | if (cmd->op_type == QLC_83XX_MBX_POST_BC_OP) |
711 | return; | |
712 | ||
7f966452 SC |
713 | dev_info(&adapter->pdev->dev, |
714 | "Host MBX regs(%d)\n", cmd->req.num); | |
715 | for (i = 0; i < cmd->req.num; i++) { | |
716 | if (i && !(i % 8)) | |
717 | pr_info("\n"); | |
718 | pr_info("%08x ", cmd->req.arg[i]); | |
719 | } | |
720 | pr_info("\n"); | |
721 | dev_info(&adapter->pdev->dev, | |
722 | "FW MBX regs(%d)\n", cmd->rsp.num); | |
723 | for (i = 0; i < cmd->rsp.num; i++) { | |
724 | if (i && !(i % 8)) | |
725 | pr_info("\n"); | |
726 | pr_info("%08x ", cmd->rsp.arg[i]); | |
727 | } | |
728 | pr_info("\n"); | |
729 | } | |
730 | ||
60dcbcb0 MC |
731 | static void qlcnic_83xx_poll_for_mbx_completion(struct qlcnic_adapter *adapter, |
732 | struct qlcnic_cmd_args *cmd) | |
65ab999d | 733 | { |
068a8d19 MC |
734 | struct qlcnic_hardware_context *ahw = adapter->ahw; |
735 | int opcode = LSW(cmd->req.arg[0]); | |
736 | unsigned long max_loops; | |
65ab999d | 737 | |
068a8d19 | 738 | max_loops = cmd->total_cmds * QLC_83XX_MBX_CMD_LOOP; |
65ab999d | 739 | |
068a8d19 MC |
740 | for (; max_loops; max_loops--) { |
741 | if (atomic_read(&cmd->rsp_status) == | |
742 | QLC_83XX_MBX_RESPONSE_ARRIVED) | |
743 | return; | |
744 | ||
745 | udelay(1); | |
746 | } | |
747 | ||
748 | dev_err(&adapter->pdev->dev, | |
749 | "%s: Mailbox command timed out, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n", | |
750 | __func__, opcode, cmd->type, ahw->pci_func, ahw->op_mode); | |
751 | flush_workqueue(ahw->mailbox->work_q); | |
752 | return; | |
7f966452 SC |
753 | } |
754 | ||
e5c4e6c6 MC |
755 | int qlcnic_83xx_issue_cmd(struct qlcnic_adapter *adapter, |
756 | struct qlcnic_cmd_args *cmd) | |
7f966452 | 757 | { |
068a8d19 | 758 | struct qlcnic_mailbox *mbx = adapter->ahw->mailbox; |
7f966452 | 759 | struct qlcnic_hardware_context *ahw = adapter->ahw; |
068a8d19 MC |
760 | int cmd_type, err, opcode; |
761 | unsigned long timeout; | |
7f966452 SC |
762 | |
763 | opcode = LSW(cmd->req.arg[0]); | |
068a8d19 MC |
764 | cmd_type = cmd->type; |
765 | err = mbx->ops->enqueue_cmd(adapter, cmd, &timeout); | |
766 | if (err) { | |
767 | dev_err(&adapter->pdev->dev, | |
768 | "%s: Mailbox not available, cmd_op=0x%x, cmd_context=0x%x, pci_func=0x%x, op_mode=0x%x\n", | |
769 | __func__, opcode, cmd->type, ahw->pci_func, | |
770 | ahw->op_mode); | |
771 | return err; | |
7f966452 SC |
772 | } |
773 | ||
068a8d19 MC |
774 | switch (cmd_type) { |
775 | case QLC_83XX_MBX_CMD_WAIT: | |
776 | if (!wait_for_completion_timeout(&cmd->completion, timeout)) { | |
65ab999d | 777 | dev_err(&adapter->pdev->dev, |
068a8d19 MC |
778 | "%s: Mailbox command timed out, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n", |
779 | __func__, opcode, cmd_type, ahw->pci_func, | |
780 | ahw->op_mode); | |
781 | flush_workqueue(mbx->work_q); | |
7f966452 | 782 | } |
068a8d19 MC |
783 | break; |
784 | case QLC_83XX_MBX_CMD_NO_WAIT: | |
785 | return 0; | |
786 | case QLC_83XX_MBX_CMD_BUSY_WAIT: | |
787 | qlcnic_83xx_poll_for_mbx_completion(adapter, cmd); | |
788 | break; | |
789 | default: | |
790 | dev_err(&adapter->pdev->dev, | |
791 | "%s: Invalid mailbox command, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n", | |
792 | __func__, opcode, cmd_type, ahw->pci_func, | |
793 | ahw->op_mode); | |
794 | qlcnic_83xx_detach_mailbox_work(adapter); | |
7f966452 | 795 | } |
65ab999d | 796 | |
068a8d19 | 797 | return cmd->rsp_opcode; |
7f966452 SC |
798 | } |
799 | ||
800 | int qlcnic_83xx_alloc_mbx_args(struct qlcnic_cmd_args *mbx, | |
801 | struct qlcnic_adapter *adapter, u32 type) | |
802 | { | |
803 | int i, size; | |
804 | u32 temp; | |
805 | const struct qlcnic_mailbox_metadata *mbx_tbl; | |
806 | ||
e5c4e6c6 | 807 | memset(mbx, 0, sizeof(struct qlcnic_cmd_args)); |
7f966452 SC |
808 | mbx_tbl = qlcnic_83xx_mbx_tbl; |
809 | size = ARRAY_SIZE(qlcnic_83xx_mbx_tbl); | |
810 | for (i = 0; i < size; i++) { | |
811 | if (type == mbx_tbl[i].cmd) { | |
f197a7aa | 812 | mbx->op_type = QLC_83XX_FW_MBX_CMD; |
7f966452 SC |
813 | mbx->req.num = mbx_tbl[i].in_args; |
814 | mbx->rsp.num = mbx_tbl[i].out_args; | |
815 | mbx->req.arg = kcalloc(mbx->req.num, sizeof(u32), | |
816 | GFP_ATOMIC); | |
817 | if (!mbx->req.arg) | |
818 | return -ENOMEM; | |
819 | mbx->rsp.arg = kcalloc(mbx->rsp.num, sizeof(u32), | |
820 | GFP_ATOMIC); | |
821 | if (!mbx->rsp.arg) { | |
822 | kfree(mbx->req.arg); | |
823 | mbx->req.arg = NULL; | |
824 | return -ENOMEM; | |
825 | } | |
826 | memset(mbx->req.arg, 0, sizeof(u32) * mbx->req.num); | |
827 | memset(mbx->rsp.arg, 0, sizeof(u32) * mbx->rsp.num); | |
828 | temp = adapter->ahw->fw_hal_version << 29; | |
829 | mbx->req.arg[0] = (type | (mbx->req.num << 16) | temp); | |
068a8d19 | 830 | mbx->cmd_op = type; |
f197a7aa | 831 | return 0; |
7f966452 SC |
832 | } |
833 | } | |
f197a7aa | 834 | return -EINVAL; |
7f966452 SC |
835 | } |
836 | ||
837 | void qlcnic_83xx_idc_aen_work(struct work_struct *work) | |
838 | { | |
839 | struct qlcnic_adapter *adapter; | |
840 | struct qlcnic_cmd_args cmd; | |
841 | int i, err = 0; | |
842 | ||
843 | adapter = container_of(work, struct qlcnic_adapter, idc_aen_work.work); | |
b6b4316c SS |
844 | err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_IDC_ACK); |
845 | if (err) | |
846 | return; | |
7f966452 SC |
847 | |
848 | for (i = 1; i < QLC_83XX_MBX_AEN_CNT; i++) | |
849 | cmd.req.arg[i] = adapter->ahw->mbox_aen[i]; | |
850 | ||
851 | err = qlcnic_issue_cmd(adapter, &cmd); | |
852 | if (err) | |
853 | dev_info(&adapter->pdev->dev, | |
854 | "%s: Mailbox IDC ACK failed.\n", __func__); | |
855 | qlcnic_free_mbx_args(&cmd); | |
856 | } | |
857 | ||
858 | static void qlcnic_83xx_handle_idc_comp_aen(struct qlcnic_adapter *adapter, | |
859 | u32 data[]) | |
860 | { | |
861 | dev_dbg(&adapter->pdev->dev, "Completion AEN:0x%x.\n", | |
862 | QLCNIC_MBX_RSP(data[0])); | |
629263ac | 863 | clear_bit(QLC_83XX_IDC_COMP_AEN, &adapter->ahw->idc.status); |
7f966452 SC |
864 | return; |
865 | } | |
866 | ||
d1a1105e | 867 | void __qlcnic_83xx_process_aen(struct qlcnic_adapter *adapter) |
7f966452 | 868 | { |
77bead46 | 869 | struct qlcnic_hardware_context *ahw = adapter->ahw; |
483202d5 | 870 | u32 event[QLC_83XX_MBX_AEN_CNT]; |
7f966452 | 871 | int i; |
7f966452 | 872 | |
7f966452 SC |
873 | for (i = 0; i < QLC_83XX_MBX_AEN_CNT; i++) |
874 | event[i] = readl(QLCNIC_MBX_FW(ahw, i)); | |
875 | ||
876 | switch (QLCNIC_MBX_RSP(event[0])) { | |
877 | ||
878 | case QLCNIC_MBX_LINK_EVENT: | |
879 | qlcnic_83xx_handle_link_aen(adapter, event); | |
880 | break; | |
881 | case QLCNIC_MBX_COMP_EVENT: | |
882 | qlcnic_83xx_handle_idc_comp_aen(adapter, event); | |
883 | break; | |
884 | case QLCNIC_MBX_REQUEST_EVENT: | |
885 | for (i = 0; i < QLC_83XX_MBX_AEN_CNT; i++) | |
886 | adapter->ahw->mbox_aen[i] = QLCNIC_MBX_RSP(event[i]); | |
887 | queue_delayed_work(adapter->qlcnic_wq, | |
888 | &adapter->idc_aen_work, 0); | |
889 | break; | |
890 | case QLCNIC_MBX_TIME_EXTEND_EVENT: | |
77bead46 | 891 | ahw->extend_lb_time = event[1] >> 8 & 0xf; |
7f966452 | 892 | break; |
f197a7aa RB |
893 | case QLCNIC_MBX_BC_EVENT: |
894 | qlcnic_sriov_handle_bc_event(adapter, event[1]); | |
895 | break; | |
7f966452 SC |
896 | case QLCNIC_MBX_SFP_INSERT_EVENT: |
897 | dev_info(&adapter->pdev->dev, "SFP+ Insert AEN:0x%x.\n", | |
898 | QLCNIC_MBX_RSP(event[0])); | |
899 | break; | |
900 | case QLCNIC_MBX_SFP_REMOVE_EVENT: | |
901 | dev_info(&adapter->pdev->dev, "SFP Removed AEN:0x%x.\n", | |
902 | QLCNIC_MBX_RSP(event[0])); | |
903 | break; | |
2d8ebcab SC |
904 | case QLCNIC_MBX_DCBX_CONFIG_CHANGE_EVENT: |
905 | qlcnic_dcb_handle_aen(adapter, (void *)&event[1]); | |
906 | break; | |
7f966452 SC |
907 | default: |
908 | dev_dbg(&adapter->pdev->dev, "Unsupported AEN:0x%x.\n", | |
909 | QLCNIC_MBX_RSP(event[0])); | |
910 | break; | |
911 | } | |
912 | ||
913 | QLCWRX(ahw, QLCNIC_FW_MBX_CTRL, QLCNIC_CLR_OWNER); | |
7f966452 SC |
914 | } |
915 | ||
d1a1105e RB |
916 | static void qlcnic_83xx_process_aen(struct qlcnic_adapter *adapter) |
917 | { | |
068a8d19 | 918 | u32 resp, event, rsp_status = QLC_83XX_MBX_RESPONSE_ARRIVED; |
d1a1105e | 919 | struct qlcnic_hardware_context *ahw = adapter->ahw; |
068a8d19 | 920 | struct qlcnic_mailbox *mbx = ahw->mailbox; |
d1a1105e RB |
921 | unsigned long flags; |
922 | ||
068a8d19 | 923 | spin_lock_irqsave(&mbx->aen_lock, flags); |
d1a1105e RB |
924 | resp = QLCRDX(ahw, QLCNIC_FW_MBX_CTRL); |
925 | if (resp & QLCNIC_SET_OWNER) { | |
926 | event = readl(QLCNIC_MBX_FW(ahw, 0)); | |
068a8d19 | 927 | if (event & QLCNIC_MBX_ASYNC_EVENT) { |
d1a1105e | 928 | __qlcnic_83xx_process_aen(adapter); |
068a8d19 MC |
929 | } else { |
930 | if (atomic_read(&mbx->rsp_status) != rsp_status) | |
931 | qlcnic_83xx_notify_mbx_response(mbx); | |
932 | } | |
d1a1105e | 933 | } |
068a8d19 | 934 | spin_unlock_irqrestore(&mbx->aen_lock, flags); |
d1a1105e RB |
935 | } |
936 | ||
7ed3ce48 RB |
937 | static void qlcnic_83xx_mbx_poll_work(struct work_struct *work) |
938 | { | |
939 | struct qlcnic_adapter *adapter; | |
940 | ||
941 | adapter = container_of(work, struct qlcnic_adapter, mbx_poll_work.work); | |
942 | ||
943 | if (!test_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state)) | |
944 | return; | |
945 | ||
946 | qlcnic_83xx_process_aen(adapter); | |
947 | queue_delayed_work(adapter->qlcnic_wq, &adapter->mbx_poll_work, | |
948 | (HZ / 10)); | |
949 | } | |
950 | ||
951 | void qlcnic_83xx_enable_mbx_poll(struct qlcnic_adapter *adapter) | |
952 | { | |
953 | if (test_and_set_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state)) | |
954 | return; | |
955 | ||
956 | INIT_DELAYED_WORK(&adapter->mbx_poll_work, qlcnic_83xx_mbx_poll_work); | |
79da4d08 | 957 | queue_delayed_work(adapter->qlcnic_wq, &adapter->mbx_poll_work, 0); |
7ed3ce48 RB |
958 | } |
959 | ||
960 | void qlcnic_83xx_disable_mbx_poll(struct qlcnic_adapter *adapter) | |
961 | { | |
962 | if (!test_and_clear_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state)) | |
963 | return; | |
964 | cancel_delayed_work_sync(&adapter->mbx_poll_work); | |
965 | } | |
966 | ||
7f966452 SC |
967 | static int qlcnic_83xx_add_rings(struct qlcnic_adapter *adapter) |
968 | { | |
969 | int index, i, err, sds_mbx_size; | |
970 | u32 *buf, intrpt_id, intr_mask; | |
971 | u16 context_id; | |
972 | u8 num_sds; | |
973 | struct qlcnic_cmd_args cmd; | |
974 | struct qlcnic_host_sds_ring *sds; | |
975 | struct qlcnic_sds_mbx sds_mbx; | |
976 | struct qlcnic_add_rings_mbx_out *mbx_out; | |
977 | struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx; | |
978 | struct qlcnic_hardware_context *ahw = adapter->ahw; | |
979 | ||
980 | sds_mbx_size = sizeof(struct qlcnic_sds_mbx); | |
981 | context_id = recv_ctx->context_id; | |
982 | num_sds = (adapter->max_sds_rings - QLCNIC_MAX_RING_SETS); | |
983 | ahw->hw_ops->alloc_mbx_args(&cmd, adapter, | |
984 | QLCNIC_CMD_ADD_RCV_RINGS); | |
985 | cmd.req.arg[1] = 0 | (num_sds << 8) | (context_id << 16); | |
986 | ||
987 | /* set up status rings, mbx 2-81 */ | |
988 | index = 2; | |
989 | for (i = 8; i < adapter->max_sds_rings; i++) { | |
990 | memset(&sds_mbx, 0, sds_mbx_size); | |
991 | sds = &recv_ctx->sds_rings[i]; | |
992 | sds->consumer = 0; | |
993 | memset(sds->desc_head, 0, STATUS_DESC_RINGSIZE(sds)); | |
a96227e6 SS |
994 | sds_mbx.phy_addr_low = LSD(sds->phys_addr); |
995 | sds_mbx.phy_addr_high = MSD(sds->phys_addr); | |
7f966452 SC |
996 | sds_mbx.sds_ring_size = sds->num_desc; |
997 | ||
998 | if (adapter->flags & QLCNIC_MSIX_ENABLED) | |
999 | intrpt_id = ahw->intr_tbl[i].id; | |
1000 | else | |
1001 | intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID); | |
1002 | ||
1003 | if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST) | |
1004 | sds_mbx.intrpt_id = intrpt_id; | |
1005 | else | |
1006 | sds_mbx.intrpt_id = 0xffff; | |
1007 | sds_mbx.intrpt_val = 0; | |
1008 | buf = &cmd.req.arg[index]; | |
1009 | memcpy(buf, &sds_mbx, sds_mbx_size); | |
1010 | index += sds_mbx_size / sizeof(u32); | |
1011 | } | |
1012 | ||
1013 | /* send the mailbox command */ | |
1014 | err = ahw->hw_ops->mbx_cmd(adapter, &cmd); | |
1015 | if (err) { | |
1016 | dev_err(&adapter->pdev->dev, | |
1017 | "Failed to add rings %d\n", err); | |
1018 | goto out; | |
1019 | } | |
1020 | ||
1021 | mbx_out = (struct qlcnic_add_rings_mbx_out *)&cmd.rsp.arg[1]; | |
1022 | index = 0; | |
1023 | /* status descriptor ring */ | |
1024 | for (i = 8; i < adapter->max_sds_rings; i++) { | |
1025 | sds = &recv_ctx->sds_rings[i]; | |
1026 | sds->crb_sts_consumer = ahw->pci_base0 + | |
1027 | mbx_out->host_csmr[index]; | |
1028 | if (adapter->flags & QLCNIC_MSIX_ENABLED) | |
1029 | intr_mask = ahw->intr_tbl[i].src; | |
1030 | else | |
1031 | intr_mask = QLCRDX(ahw, QLCNIC_DEF_INT_MASK); | |
1032 | ||
1033 | sds->crb_intr_mask = ahw->pci_base0 + intr_mask; | |
1034 | index++; | |
1035 | } | |
1036 | out: | |
1037 | qlcnic_free_mbx_args(&cmd); | |
1038 | return err; | |
1039 | } | |
1040 | ||
7cb03b23 RB |
1041 | void qlcnic_83xx_del_rx_ctx(struct qlcnic_adapter *adapter) |
1042 | { | |
1043 | int err; | |
1044 | u32 temp = 0; | |
1045 | struct qlcnic_cmd_args cmd; | |
1046 | struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx; | |
1047 | ||
1048 | if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_RX_CTX)) | |
1049 | return; | |
1050 | ||
1051 | if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter)) | |
1052 | cmd.req.arg[0] |= (0x3 << 29); | |
1053 | ||
1054 | if (qlcnic_sriov_pf_check(adapter)) | |
1055 | qlcnic_pf_set_interface_id_del_rx_ctx(adapter, &temp); | |
1056 | ||
1057 | cmd.req.arg[1] = recv_ctx->context_id | temp; | |
1058 | err = qlcnic_issue_cmd(adapter, &cmd); | |
1059 | if (err) | |
1060 | dev_err(&adapter->pdev->dev, | |
1061 | "Failed to destroy rx ctx in firmware\n"); | |
1062 | ||
1063 | recv_ctx->state = QLCNIC_HOST_CTX_STATE_FREED; | |
1064 | qlcnic_free_mbx_args(&cmd); | |
1065 | } | |
1066 | ||
7f966452 SC |
1067 | int qlcnic_83xx_create_rx_ctx(struct qlcnic_adapter *adapter) |
1068 | { | |
1069 | int i, err, index, sds_mbx_size, rds_mbx_size; | |
1070 | u8 num_sds, num_rds; | |
1071 | u32 *buf, intrpt_id, intr_mask, cap = 0; | |
1072 | struct qlcnic_host_sds_ring *sds; | |
1073 | struct qlcnic_host_rds_ring *rds; | |
1074 | struct qlcnic_sds_mbx sds_mbx; | |
1075 | struct qlcnic_rds_mbx rds_mbx; | |
1076 | struct qlcnic_cmd_args cmd; | |
1077 | struct qlcnic_rcv_mbx_out *mbx_out; | |
1078 | struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx; | |
1079 | struct qlcnic_hardware_context *ahw = adapter->ahw; | |
1080 | num_rds = adapter->max_rds_rings; | |
1081 | ||
1082 | if (adapter->max_sds_rings <= QLCNIC_MAX_RING_SETS) | |
1083 | num_sds = adapter->max_sds_rings; | |
1084 | else | |
1085 | num_sds = QLCNIC_MAX_RING_SETS; | |
1086 | ||
1087 | sds_mbx_size = sizeof(struct qlcnic_sds_mbx); | |
1088 | rds_mbx_size = sizeof(struct qlcnic_rds_mbx); | |
1089 | cap = QLCNIC_CAP0_LEGACY_CONTEXT; | |
1090 | ||
1091 | if (adapter->flags & QLCNIC_FW_LRO_MSS_CAP) | |
1092 | cap |= QLC_83XX_FW_CAP_LRO_MSS; | |
1093 | ||
1094 | /* set mailbox hdr and capabilities */ | |
b6b4316c SS |
1095 | err = qlcnic_alloc_mbx_args(&cmd, adapter, |
1096 | QLCNIC_CMD_CREATE_RX_CTX); | |
1097 | if (err) | |
1098 | return err; | |
7cb03b23 RB |
1099 | |
1100 | if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter)) | |
1101 | cmd.req.arg[0] |= (0x3 << 29); | |
1102 | ||
7f966452 SC |
1103 | cmd.req.arg[1] = cap; |
1104 | cmd.req.arg[5] = 1 | (num_rds << 5) | (num_sds << 8) | | |
1105 | (QLC_83XX_HOST_RDS_MODE_UNIQUE << 16); | |
7cb03b23 RB |
1106 | |
1107 | if (qlcnic_sriov_pf_check(adapter)) | |
1108 | qlcnic_pf_set_interface_id_create_rx_ctx(adapter, | |
1109 | &cmd.req.arg[6]); | |
7f966452 SC |
1110 | /* set up status rings, mbx 8-57/87 */ |
1111 | index = QLC_83XX_HOST_SDS_MBX_IDX; | |
1112 | for (i = 0; i < num_sds; i++) { | |
1113 | memset(&sds_mbx, 0, sds_mbx_size); | |
1114 | sds = &recv_ctx->sds_rings[i]; | |
1115 | sds->consumer = 0; | |
1116 | memset(sds->desc_head, 0, STATUS_DESC_RINGSIZE(sds)); | |
a96227e6 SS |
1117 | sds_mbx.phy_addr_low = LSD(sds->phys_addr); |
1118 | sds_mbx.phy_addr_high = MSD(sds->phys_addr); | |
7f966452 SC |
1119 | sds_mbx.sds_ring_size = sds->num_desc; |
1120 | if (adapter->flags & QLCNIC_MSIX_ENABLED) | |
1121 | intrpt_id = ahw->intr_tbl[i].id; | |
1122 | else | |
1123 | intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID); | |
1124 | if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST) | |
1125 | sds_mbx.intrpt_id = intrpt_id; | |
1126 | else | |
1127 | sds_mbx.intrpt_id = 0xffff; | |
1128 | sds_mbx.intrpt_val = 0; | |
1129 | buf = &cmd.req.arg[index]; | |
1130 | memcpy(buf, &sds_mbx, sds_mbx_size); | |
1131 | index += sds_mbx_size / sizeof(u32); | |
1132 | } | |
1133 | /* set up receive rings, mbx 88-111/135 */ | |
1134 | index = QLCNIC_HOST_RDS_MBX_IDX; | |
1135 | rds = &recv_ctx->rds_rings[0]; | |
1136 | rds->producer = 0; | |
1137 | memset(&rds_mbx, 0, rds_mbx_size); | |
a96227e6 SS |
1138 | rds_mbx.phy_addr_reg_low = LSD(rds->phys_addr); |
1139 | rds_mbx.phy_addr_reg_high = MSD(rds->phys_addr); | |
7f966452 SC |
1140 | rds_mbx.reg_ring_sz = rds->dma_size; |
1141 | rds_mbx.reg_ring_len = rds->num_desc; | |
1142 | /* Jumbo ring */ | |
1143 | rds = &recv_ctx->rds_rings[1]; | |
1144 | rds->producer = 0; | |
a96227e6 SS |
1145 | rds_mbx.phy_addr_jmb_low = LSD(rds->phys_addr); |
1146 | rds_mbx.phy_addr_jmb_high = MSD(rds->phys_addr); | |
7f966452 SC |
1147 | rds_mbx.jmb_ring_sz = rds->dma_size; |
1148 | rds_mbx.jmb_ring_len = rds->num_desc; | |
1149 | buf = &cmd.req.arg[index]; | |
1150 | memcpy(buf, &rds_mbx, rds_mbx_size); | |
1151 | ||
1152 | /* send the mailbox command */ | |
1153 | err = ahw->hw_ops->mbx_cmd(adapter, &cmd); | |
1154 | if (err) { | |
1155 | dev_err(&adapter->pdev->dev, | |
1156 | "Failed to create Rx ctx in firmware%d\n", err); | |
1157 | goto out; | |
1158 | } | |
1159 | mbx_out = (struct qlcnic_rcv_mbx_out *)&cmd.rsp.arg[1]; | |
1160 | recv_ctx->context_id = mbx_out->ctx_id; | |
1161 | recv_ctx->state = mbx_out->state; | |
1162 | recv_ctx->virt_port = mbx_out->vport_id; | |
1163 | dev_info(&adapter->pdev->dev, "Rx Context[%d] Created, state:0x%x\n", | |
1164 | recv_ctx->context_id, recv_ctx->state); | |
1165 | /* Receive descriptor ring */ | |
1166 | /* Standard ring */ | |
1167 | rds = &recv_ctx->rds_rings[0]; | |
1168 | rds->crb_rcv_producer = ahw->pci_base0 + | |
1169 | mbx_out->host_prod[0].reg_buf; | |
1170 | /* Jumbo ring */ | |
1171 | rds = &recv_ctx->rds_rings[1]; | |
1172 | rds->crb_rcv_producer = ahw->pci_base0 + | |
1173 | mbx_out->host_prod[0].jmb_buf; | |
1174 | /* status descriptor ring */ | |
1175 | for (i = 0; i < num_sds; i++) { | |
1176 | sds = &recv_ctx->sds_rings[i]; | |
1177 | sds->crb_sts_consumer = ahw->pci_base0 + | |
1178 | mbx_out->host_csmr[i]; | |
1179 | if (adapter->flags & QLCNIC_MSIX_ENABLED) | |
1180 | intr_mask = ahw->intr_tbl[i].src; | |
1181 | else | |
1182 | intr_mask = QLCRDX(ahw, QLCNIC_DEF_INT_MASK); | |
1183 | sds->crb_intr_mask = ahw->pci_base0 + intr_mask; | |
1184 | } | |
1185 | ||
1186 | if (adapter->max_sds_rings > QLCNIC_MAX_RING_SETS) | |
1187 | err = qlcnic_83xx_add_rings(adapter); | |
1188 | out: | |
1189 | qlcnic_free_mbx_args(&cmd); | |
1190 | return err; | |
1191 | } | |
1192 | ||
7cb03b23 RB |
1193 | void qlcnic_83xx_del_tx_ctx(struct qlcnic_adapter *adapter, |
1194 | struct qlcnic_host_tx_ring *tx_ring) | |
1195 | { | |
1196 | struct qlcnic_cmd_args cmd; | |
1197 | u32 temp = 0; | |
1198 | ||
1199 | if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_TX_CTX)) | |
1200 | return; | |
1201 | ||
1202 | if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter)) | |
1203 | cmd.req.arg[0] |= (0x3 << 29); | |
1204 | ||
1205 | if (qlcnic_sriov_pf_check(adapter)) | |
1206 | qlcnic_pf_set_interface_id_del_tx_ctx(adapter, &temp); | |
1207 | ||
1208 | cmd.req.arg[1] = tx_ring->ctx_id | temp; | |
1209 | if (qlcnic_issue_cmd(adapter, &cmd)) | |
1210 | dev_err(&adapter->pdev->dev, | |
1211 | "Failed to destroy tx ctx in firmware\n"); | |
1212 | qlcnic_free_mbx_args(&cmd); | |
1213 | } | |
1214 | ||
7f966452 SC |
1215 | int qlcnic_83xx_create_tx_ctx(struct qlcnic_adapter *adapter, |
1216 | struct qlcnic_host_tx_ring *tx, int ring) | |
1217 | { | |
1218 | int err; | |
1219 | u16 msix_id; | |
7cb03b23 | 1220 | u32 *buf, intr_mask, temp = 0; |
7f966452 SC |
1221 | struct qlcnic_cmd_args cmd; |
1222 | struct qlcnic_tx_mbx mbx; | |
1223 | struct qlcnic_tx_mbx_out *mbx_out; | |
1224 | struct qlcnic_hardware_context *ahw = adapter->ahw; | |
da6c8063 | 1225 | u32 msix_vector; |
7f966452 SC |
1226 | |
1227 | /* Reset host resources */ | |
1228 | tx->producer = 0; | |
1229 | tx->sw_consumer = 0; | |
1230 | *(tx->hw_consumer) = 0; | |
1231 | ||
1232 | memset(&mbx, 0, sizeof(struct qlcnic_tx_mbx)); | |
1233 | ||
1234 | /* setup mailbox inbox registerss */ | |
a96227e6 SS |
1235 | mbx.phys_addr_low = LSD(tx->phys_addr); |
1236 | mbx.phys_addr_high = MSD(tx->phys_addr); | |
1237 | mbx.cnsmr_index_low = LSD(tx->hw_cons_phys_addr); | |
1238 | mbx.cnsmr_index_high = MSD(tx->hw_cons_phys_addr); | |
7f966452 | 1239 | mbx.size = tx->num_desc; |
da6c8063 RB |
1240 | if (adapter->flags & QLCNIC_MSIX_ENABLED) { |
1241 | if (!(adapter->flags & QLCNIC_TX_INTR_SHARED)) | |
1242 | msix_vector = adapter->max_sds_rings + ring; | |
1243 | else | |
1244 | msix_vector = adapter->max_sds_rings - 1; | |
1245 | msix_id = ahw->intr_tbl[msix_vector].id; | |
1246 | } else { | |
7f966452 | 1247 | msix_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID); |
da6c8063 RB |
1248 | } |
1249 | ||
7f966452 SC |
1250 | if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST) |
1251 | mbx.intr_id = msix_id; | |
1252 | else | |
1253 | mbx.intr_id = 0xffff; | |
1254 | mbx.src = 0; | |
1255 | ||
b6b4316c SS |
1256 | err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CREATE_TX_CTX); |
1257 | if (err) | |
1258 | return err; | |
7cb03b23 RB |
1259 | |
1260 | if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter)) | |
1261 | cmd.req.arg[0] |= (0x3 << 29); | |
1262 | ||
1263 | if (qlcnic_sriov_pf_check(adapter)) | |
1264 | qlcnic_pf_set_interface_id_create_tx_ctx(adapter, &temp); | |
1265 | ||
7f966452 | 1266 | cmd.req.arg[1] = QLCNIC_CAP0_LEGACY_CONTEXT; |
7cb03b23 | 1267 | cmd.req.arg[5] = QLCNIC_MAX_TX_QUEUES | temp; |
7f966452 SC |
1268 | buf = &cmd.req.arg[6]; |
1269 | memcpy(buf, &mbx, sizeof(struct qlcnic_tx_mbx)); | |
1270 | /* send the mailbox command*/ | |
1271 | err = qlcnic_issue_cmd(adapter, &cmd); | |
1272 | if (err) { | |
1273 | dev_err(&adapter->pdev->dev, | |
1274 | "Failed to create Tx ctx in firmware 0x%x\n", err); | |
1275 | goto out; | |
1276 | } | |
1277 | mbx_out = (struct qlcnic_tx_mbx_out *)&cmd.rsp.arg[2]; | |
1278 | tx->crb_cmd_producer = ahw->pci_base0 + mbx_out->host_prod; | |
1279 | tx->ctx_id = mbx_out->ctx_id; | |
da6c8063 RB |
1280 | if ((adapter->flags & QLCNIC_MSIX_ENABLED) && |
1281 | !(adapter->flags & QLCNIC_TX_INTR_SHARED)) { | |
7f966452 SC |
1282 | intr_mask = ahw->intr_tbl[adapter->max_sds_rings + ring].src; |
1283 | tx->crb_intr_mask = ahw->pci_base0 + intr_mask; | |
1284 | } | |
1285 | dev_info(&adapter->pdev->dev, "Tx Context[0x%x] Created, state:0x%x\n", | |
1286 | tx->ctx_id, mbx_out->state); | |
1287 | out: | |
1288 | qlcnic_free_mbx_args(&cmd); | |
1289 | return err; | |
1290 | } | |
1291 | ||
13a82b44 MC |
1292 | static int qlcnic_83xx_diag_alloc_res(struct net_device *netdev, int test, |
1293 | int num_sds_ring) | |
ba4468db JK |
1294 | { |
1295 | struct qlcnic_adapter *adapter = netdev_priv(netdev); | |
1296 | struct qlcnic_host_sds_ring *sds_ring; | |
1297 | struct qlcnic_host_rds_ring *rds_ring; | |
13a82b44 | 1298 | u16 adapter_state = adapter->is_up; |
ba4468db JK |
1299 | u8 ring; |
1300 | int ret; | |
1301 | ||
1302 | netif_device_detach(netdev); | |
1303 | ||
1304 | if (netif_running(netdev)) | |
1305 | __qlcnic_down(adapter, netdev); | |
1306 | ||
1307 | qlcnic_detach(adapter); | |
1308 | ||
1309 | adapter->max_sds_rings = 1; | |
1310 | adapter->ahw->diag_test = test; | |
1311 | adapter->ahw->linkup = 0; | |
1312 | ||
1313 | ret = qlcnic_attach(adapter); | |
1314 | if (ret) { | |
1315 | netif_device_attach(netdev); | |
1316 | return ret; | |
1317 | } | |
1318 | ||
1319 | ret = qlcnic_fw_create_ctx(adapter); | |
1320 | if (ret) { | |
1321 | qlcnic_detach(adapter); | |
13a82b44 MC |
1322 | if (adapter_state == QLCNIC_ADAPTER_UP_MAGIC) { |
1323 | adapter->max_sds_rings = num_sds_ring; | |
1324 | qlcnic_attach(adapter); | |
1325 | } | |
ba4468db JK |
1326 | netif_device_attach(netdev); |
1327 | return ret; | |
1328 | } | |
1329 | ||
1330 | for (ring = 0; ring < adapter->max_rds_rings; ring++) { | |
1331 | rds_ring = &adapter->recv_ctx->rds_rings[ring]; | |
1332 | qlcnic_post_rx_buffers(adapter, rds_ring, ring); | |
1333 | } | |
1334 | ||
1335 | if (adapter->ahw->diag_test == QLCNIC_INTERRUPT_TEST) { | |
1336 | for (ring = 0; ring < adapter->max_sds_rings; ring++) { | |
1337 | sds_ring = &adapter->recv_ctx->sds_rings[ring]; | |
1338 | qlcnic_83xx_enable_intr(adapter, sds_ring); | |
1339 | } | |
1340 | } | |
1341 | ||
1342 | if (adapter->ahw->diag_test == QLCNIC_LOOPBACK_TEST) { | |
1343 | /* disable and free mailbox interrupt */ | |
79da4d08 MC |
1344 | if (!(adapter->flags & QLCNIC_MSIX_ENABLED)) { |
1345 | qlcnic_83xx_enable_mbx_poll(adapter); | |
d1a1105e | 1346 | qlcnic_83xx_free_mbx_intr(adapter); |
79da4d08 | 1347 | } |
ba4468db JK |
1348 | adapter->ahw->loopback_state = 0; |
1349 | adapter->ahw->hw_ops->setup_link_event(adapter, 1); | |
1350 | } | |
1351 | ||
1352 | set_bit(__QLCNIC_DEV_UP, &adapter->state); | |
1353 | return 0; | |
1354 | } | |
1355 | ||
1356 | static void qlcnic_83xx_diag_free_res(struct net_device *netdev, | |
1357 | int max_sds_rings) | |
1358 | { | |
1359 | struct qlcnic_adapter *adapter = netdev_priv(netdev); | |
1360 | struct qlcnic_host_sds_ring *sds_ring; | |
1361 | int ring, err; | |
1362 | ||
1363 | clear_bit(__QLCNIC_DEV_UP, &adapter->state); | |
1364 | if (adapter->ahw->diag_test == QLCNIC_INTERRUPT_TEST) { | |
1365 | for (ring = 0; ring < adapter->max_sds_rings; ring++) { | |
1366 | sds_ring = &adapter->recv_ctx->sds_rings[ring]; | |
ac166700 | 1367 | qlcnic_83xx_disable_intr(adapter, sds_ring); |
79da4d08 MC |
1368 | if (!(adapter->flags & QLCNIC_MSIX_ENABLED)) |
1369 | qlcnic_83xx_enable_mbx_poll(adapter); | |
ba4468db JK |
1370 | } |
1371 | } | |
1372 | ||
1373 | qlcnic_fw_destroy_ctx(adapter); | |
1374 | qlcnic_detach(adapter); | |
1375 | ||
1376 | if (adapter->ahw->diag_test == QLCNIC_LOOPBACK_TEST) { | |
d1a1105e RB |
1377 | if (!(adapter->flags & QLCNIC_MSIX_ENABLED)) { |
1378 | err = qlcnic_83xx_setup_mbx_intr(adapter); | |
79da4d08 | 1379 | qlcnic_83xx_disable_mbx_poll(adapter); |
d1a1105e RB |
1380 | if (err) { |
1381 | dev_err(&adapter->pdev->dev, | |
1382 | "%s: failed to setup mbx interrupt\n", | |
1383 | __func__); | |
1384 | goto out; | |
1385 | } | |
ba4468db JK |
1386 | } |
1387 | } | |
1388 | adapter->ahw->diag_test = 0; | |
1389 | adapter->max_sds_rings = max_sds_rings; | |
1390 | ||
1391 | if (qlcnic_attach(adapter)) | |
1392 | goto out; | |
1393 | ||
1394 | if (netif_running(netdev)) | |
1395 | __qlcnic_up(adapter, netdev); | |
79da4d08 MC |
1396 | |
1397 | if (adapter->ahw->diag_test == QLCNIC_INTERRUPT_TEST && | |
1398 | !(adapter->flags & QLCNIC_MSIX_ENABLED)) | |
1399 | qlcnic_83xx_disable_mbx_poll(adapter); | |
ba4468db JK |
1400 | out: |
1401 | netif_device_attach(netdev); | |
1402 | } | |
1403 | ||
319ecf12 SC |
1404 | int qlcnic_83xx_config_led(struct qlcnic_adapter *adapter, u32 state, |
1405 | u32 beacon) | |
1406 | { | |
1407 | struct qlcnic_cmd_args cmd; | |
1408 | u32 mbx_in; | |
1409 | int i, status = 0; | |
1410 | ||
1411 | if (state) { | |
1412 | /* Get LED configuration */ | |
b6b4316c SS |
1413 | status = qlcnic_alloc_mbx_args(&cmd, adapter, |
1414 | QLCNIC_CMD_GET_LED_CONFIG); | |
1415 | if (status) | |
1416 | return status; | |
1417 | ||
319ecf12 SC |
1418 | status = qlcnic_issue_cmd(adapter, &cmd); |
1419 | if (status) { | |
1420 | dev_err(&adapter->pdev->dev, | |
1421 | "Get led config failed.\n"); | |
1422 | goto mbx_err; | |
1423 | } else { | |
1424 | for (i = 0; i < 4; i++) | |
1425 | adapter->ahw->mbox_reg[i] = cmd.rsp.arg[i+1]; | |
1426 | } | |
1427 | qlcnic_free_mbx_args(&cmd); | |
1428 | /* Set LED Configuration */ | |
1429 | mbx_in = (LSW(QLC_83XX_LED_CONFIG) << 16) | | |
1430 | LSW(QLC_83XX_LED_CONFIG); | |
b6b4316c SS |
1431 | status = qlcnic_alloc_mbx_args(&cmd, adapter, |
1432 | QLCNIC_CMD_SET_LED_CONFIG); | |
1433 | if (status) | |
1434 | return status; | |
1435 | ||
319ecf12 SC |
1436 | cmd.req.arg[1] = mbx_in; |
1437 | cmd.req.arg[2] = mbx_in; | |
1438 | cmd.req.arg[3] = mbx_in; | |
1439 | if (beacon) | |
1440 | cmd.req.arg[4] = QLC_83XX_ENABLE_BEACON; | |
1441 | status = qlcnic_issue_cmd(adapter, &cmd); | |
1442 | if (status) { | |
1443 | dev_err(&adapter->pdev->dev, | |
1444 | "Set led config failed.\n"); | |
1445 | } | |
1446 | mbx_err: | |
1447 | qlcnic_free_mbx_args(&cmd); | |
1448 | return status; | |
1449 | ||
1450 | } else { | |
1451 | /* Restoring default LED configuration */ | |
b6b4316c SS |
1452 | status = qlcnic_alloc_mbx_args(&cmd, adapter, |
1453 | QLCNIC_CMD_SET_LED_CONFIG); | |
1454 | if (status) | |
1455 | return status; | |
1456 | ||
319ecf12 SC |
1457 | cmd.req.arg[1] = adapter->ahw->mbox_reg[0]; |
1458 | cmd.req.arg[2] = adapter->ahw->mbox_reg[1]; | |
1459 | cmd.req.arg[3] = adapter->ahw->mbox_reg[2]; | |
1460 | if (beacon) | |
1461 | cmd.req.arg[4] = adapter->ahw->mbox_reg[3]; | |
1462 | status = qlcnic_issue_cmd(adapter, &cmd); | |
1463 | if (status) | |
1464 | dev_err(&adapter->pdev->dev, | |
1465 | "Restoring led config failed.\n"); | |
1466 | qlcnic_free_mbx_args(&cmd); | |
1467 | return status; | |
1468 | } | |
1469 | } | |
1470 | ||
d16951d9 HM |
1471 | int qlcnic_83xx_set_led(struct net_device *netdev, |
1472 | enum ethtool_phys_id_state state) | |
1473 | { | |
1474 | struct qlcnic_adapter *adapter = netdev_priv(netdev); | |
1475 | int err = -EIO, active = 1; | |
1476 | ||
1477 | if (adapter->ahw->op_mode == QLCNIC_NON_PRIV_FUNC) { | |
1478 | netdev_warn(netdev, | |
1479 | "LED test is not supported in non-privileged mode\n"); | |
1480 | return -EOPNOTSUPP; | |
1481 | } | |
1482 | ||
1483 | switch (state) { | |
1484 | case ETHTOOL_ID_ACTIVE: | |
1485 | if (test_and_set_bit(__QLCNIC_LED_ENABLE, &adapter->state)) | |
1486 | return -EBUSY; | |
1487 | ||
1488 | if (test_bit(__QLCNIC_RESETTING, &adapter->state)) | |
1489 | break; | |
1490 | ||
1491 | err = qlcnic_83xx_config_led(adapter, active, 0); | |
1492 | if (err) | |
1493 | netdev_err(netdev, "Failed to set LED blink state\n"); | |
1494 | break; | |
1495 | case ETHTOOL_ID_INACTIVE: | |
1496 | active = 0; | |
1497 | ||
1498 | if (test_bit(__QLCNIC_RESETTING, &adapter->state)) | |
1499 | break; | |
1500 | ||
1501 | err = qlcnic_83xx_config_led(adapter, active, 0); | |
1502 | if (err) | |
1503 | netdev_err(netdev, "Failed to reset LED blink state\n"); | |
1504 | break; | |
1505 | ||
1506 | default: | |
1507 | return -EINVAL; | |
1508 | } | |
1509 | ||
1510 | if (!active || err) | |
1511 | clear_bit(__QLCNIC_LED_ENABLE, &adapter->state); | |
1512 | ||
1513 | return err; | |
1514 | } | |
1515 | ||
7f966452 SC |
1516 | void qlcnic_83xx_register_nic_idc_func(struct qlcnic_adapter *adapter, |
1517 | int enable) | |
1518 | { | |
1519 | struct qlcnic_cmd_args cmd; | |
1520 | int status; | |
1521 | ||
f8468331 RB |
1522 | if (qlcnic_sriov_vf_check(adapter)) |
1523 | return; | |
1524 | ||
7f966452 | 1525 | if (enable) { |
b6b4316c SS |
1526 | status = qlcnic_alloc_mbx_args(&cmd, adapter, |
1527 | QLCNIC_CMD_INIT_NIC_FUNC); | |
1528 | if (status) | |
1529 | return; | |
1530 | ||
d5fcff04 | 1531 | cmd.req.arg[1] = BIT_0 | BIT_31; |
7f966452 | 1532 | } else { |
b6b4316c SS |
1533 | status = qlcnic_alloc_mbx_args(&cmd, adapter, |
1534 | QLCNIC_CMD_STOP_NIC_FUNC); | |
1535 | if (status) | |
1536 | return; | |
1537 | ||
d5fcff04 | 1538 | cmd.req.arg[1] = BIT_0 | BIT_31; |
7f966452 SC |
1539 | } |
1540 | status = qlcnic_issue_cmd(adapter, &cmd); | |
1541 | if (status) | |
1542 | dev_err(&adapter->pdev->dev, | |
1543 | "Failed to %s in NIC IDC function event.\n", | |
1544 | (enable ? "register" : "unregister")); | |
1545 | ||
1546 | qlcnic_free_mbx_args(&cmd); | |
1547 | } | |
1548 | ||
1549 | int qlcnic_83xx_set_port_config(struct qlcnic_adapter *adapter) | |
1550 | { | |
1551 | struct qlcnic_cmd_args cmd; | |
1552 | int err; | |
1553 | ||
b6b4316c SS |
1554 | err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_PORT_CONFIG); |
1555 | if (err) | |
1556 | return err; | |
1557 | ||
7f966452 SC |
1558 | cmd.req.arg[1] = adapter->ahw->port_config; |
1559 | err = qlcnic_issue_cmd(adapter, &cmd); | |
1560 | if (err) | |
1561 | dev_info(&adapter->pdev->dev, "Set Port Config failed.\n"); | |
1562 | qlcnic_free_mbx_args(&cmd); | |
1563 | return err; | |
1564 | } | |
1565 | ||
1566 | int qlcnic_83xx_get_port_config(struct qlcnic_adapter *adapter) | |
1567 | { | |
1568 | struct qlcnic_cmd_args cmd; | |
1569 | int err; | |
1570 | ||
b6b4316c SS |
1571 | err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PORT_CONFIG); |
1572 | if (err) | |
1573 | return err; | |
1574 | ||
7f966452 SC |
1575 | err = qlcnic_issue_cmd(adapter, &cmd); |
1576 | if (err) | |
1577 | dev_info(&adapter->pdev->dev, "Get Port config failed\n"); | |
1578 | else | |
1579 | adapter->ahw->port_config = cmd.rsp.arg[1]; | |
1580 | qlcnic_free_mbx_args(&cmd); | |
1581 | return err; | |
1582 | } | |
1583 | ||
1584 | int qlcnic_83xx_setup_link_event(struct qlcnic_adapter *adapter, int enable) | |
1585 | { | |
1586 | int err; | |
1587 | u32 temp; | |
1588 | struct qlcnic_cmd_args cmd; | |
1589 | ||
b6b4316c SS |
1590 | err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LINK_EVENT); |
1591 | if (err) | |
1592 | return err; | |
1593 | ||
7f966452 SC |
1594 | temp = adapter->recv_ctx->context_id << 16; |
1595 | cmd.req.arg[1] = (enable ? 1 : 0) | BIT_8 | temp; | |
1596 | err = qlcnic_issue_cmd(adapter, &cmd); | |
1597 | if (err) | |
1598 | dev_info(&adapter->pdev->dev, | |
1599 | "Setup linkevent mailbox failed\n"); | |
1600 | qlcnic_free_mbx_args(&cmd); | |
1601 | return err; | |
1602 | } | |
1603 | ||
7cb03b23 RB |
1604 | static void qlcnic_83xx_set_interface_id_promisc(struct qlcnic_adapter *adapter, |
1605 | u32 *interface_id) | |
1606 | { | |
1607 | if (qlcnic_sriov_pf_check(adapter)) { | |
1608 | qlcnic_pf_set_interface_id_promisc(adapter, interface_id); | |
1609 | } else { | |
1610 | if (!qlcnic_sriov_vf_check(adapter)) | |
1611 | *interface_id = adapter->recv_ctx->context_id << 16; | |
1612 | } | |
1613 | } | |
1614 | ||
7f966452 SC |
1615 | int qlcnic_83xx_nic_set_promisc(struct qlcnic_adapter *adapter, u32 mode) |
1616 | { | |
068a8d19 | 1617 | struct qlcnic_cmd_args *cmd = NULL; |
7cb03b23 | 1618 | u32 temp = 0; |
068a8d19 | 1619 | int err; |
7f966452 SC |
1620 | |
1621 | if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED) | |
1622 | return -EIO; | |
1623 | ||
068a8d19 MC |
1624 | cmd = kzalloc(sizeof(*cmd), GFP_ATOMIC); |
1625 | if (!cmd) | |
1626 | return -ENOMEM; | |
1627 | ||
1628 | err = qlcnic_alloc_mbx_args(cmd, adapter, | |
b6b4316c SS |
1629 | QLCNIC_CMD_CONFIGURE_MAC_RX_MODE); |
1630 | if (err) | |
068a8d19 | 1631 | goto out; |
b6b4316c | 1632 | |
068a8d19 | 1633 | cmd->type = QLC_83XX_MBX_CMD_NO_WAIT; |
7cb03b23 | 1634 | qlcnic_83xx_set_interface_id_promisc(adapter, &temp); |
068a8d19 MC |
1635 | cmd->req.arg[1] = (mode ? 1 : 0) | temp; |
1636 | err = qlcnic_issue_cmd(adapter, cmd); | |
1637 | if (!err) | |
1638 | return err; | |
7f966452 | 1639 | |
068a8d19 MC |
1640 | qlcnic_free_mbx_args(cmd); |
1641 | ||
1642 | out: | |
1643 | kfree(cmd); | |
7f966452 SC |
1644 | return err; |
1645 | } | |
1646 | ||
ba4468db JK |
1647 | int qlcnic_83xx_loopback_test(struct net_device *netdev, u8 mode) |
1648 | { | |
1649 | struct qlcnic_adapter *adapter = netdev_priv(netdev); | |
1650 | struct qlcnic_hardware_context *ahw = adapter->ahw; | |
1651 | int ret = 0, loop = 0, max_sds_rings = adapter->max_sds_rings; | |
1652 | ||
ba4468db | 1653 | if (ahw->op_mode == QLCNIC_NON_PRIV_FUNC) { |
4690a7e4 SC |
1654 | netdev_warn(netdev, |
1655 | "Loopback test not supported in non privileged mode\n"); | |
b9c11984 | 1656 | return -ENOTSUPP; |
ba4468db JK |
1657 | } |
1658 | ||
4690a7e4 SC |
1659 | if (test_bit(__QLCNIC_RESETTING, &adapter->state)) { |
1660 | netdev_info(netdev, "Device is resetting\n"); | |
ba4468db | 1661 | return -EBUSY; |
4690a7e4 SC |
1662 | } |
1663 | ||
1664 | if (qlcnic_get_diag_lock(adapter)) { | |
1665 | netdev_info(netdev, "Device is in diagnostics mode\n"); | |
1666 | return -EBUSY; | |
1667 | } | |
1668 | ||
1669 | netdev_info(netdev, "%s loopback test in progress\n", | |
1670 | mode == QLCNIC_ILB_MODE ? "internal" : "external"); | |
ba4468db | 1671 | |
13a82b44 MC |
1672 | ret = qlcnic_83xx_diag_alloc_res(netdev, QLCNIC_LOOPBACK_TEST, |
1673 | max_sds_rings); | |
ba4468db JK |
1674 | if (ret) |
1675 | goto fail_diag_alloc; | |
1676 | ||
1677 | ret = qlcnic_83xx_set_lb_mode(adapter, mode); | |
1678 | if (ret) | |
1679 | goto free_diag_res; | |
1680 | ||
1681 | /* Poll for link up event before running traffic */ | |
1682 | do { | |
2c4a7878 | 1683 | msleep(QLC_83XX_LB_MSLEEP_COUNT); |
d1a1105e | 1684 | |
2c4a7878 JK |
1685 | if (test_bit(__QLCNIC_RESETTING, &adapter->state)) { |
1686 | netdev_info(netdev, | |
1687 | "Device is resetting, free LB test resources\n"); | |
b9c11984 | 1688 | ret = -EBUSY; |
2c4a7878 JK |
1689 | goto free_diag_res; |
1690 | } | |
1691 | if (loop++ > QLC_83XX_LB_WAIT_COUNT) { | |
1692 | netdev_info(netdev, | |
1693 | "Firmware didn't sent link up event to loopback request\n"); | |
b9c11984 | 1694 | ret = -ETIMEDOUT; |
ba4468db JK |
1695 | qlcnic_83xx_clear_lb_mode(adapter, mode); |
1696 | goto free_diag_res; | |
1697 | } | |
1698 | } while ((adapter->ahw->linkup && ahw->has_link_events) != 1); | |
1699 | ||
a4325ea2 JK |
1700 | /* Make sure carrier is off and queue is stopped during loopback */ |
1701 | if (netif_running(netdev)) { | |
1702 | netif_carrier_off(netdev); | |
012ec812 | 1703 | netif_tx_stop_all_queues(netdev); |
a4325ea2 JK |
1704 | } |
1705 | ||
ba4468db JK |
1706 | ret = qlcnic_do_lb_test(adapter, mode); |
1707 | ||
1708 | qlcnic_83xx_clear_lb_mode(adapter, mode); | |
1709 | ||
1710 | free_diag_res: | |
1711 | qlcnic_83xx_diag_free_res(netdev, max_sds_rings); | |
1712 | ||
1713 | fail_diag_alloc: | |
1714 | adapter->max_sds_rings = max_sds_rings; | |
4690a7e4 | 1715 | qlcnic_release_diag_lock(adapter); |
ba4468db JK |
1716 | return ret; |
1717 | } | |
1718 | ||
77bead46 MC |
1719 | static void qlcnic_extend_lb_idc_cmpltn_wait(struct qlcnic_adapter *adapter, |
1720 | u32 *max_wait_count) | |
1721 | { | |
1722 | struct qlcnic_hardware_context *ahw = adapter->ahw; | |
1723 | int temp; | |
1724 | ||
1725 | netdev_info(adapter->netdev, "Recieved loopback IDC time extend event for 0x%x seconds\n", | |
1726 | ahw->extend_lb_time); | |
1727 | temp = ahw->extend_lb_time * 1000; | |
1728 | *max_wait_count += temp / QLC_83XX_LB_MSLEEP_COUNT; | |
1729 | ahw->extend_lb_time = 0; | |
1730 | } | |
1731 | ||
7f966452 SC |
1732 | int qlcnic_83xx_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode) |
1733 | { | |
1734 | struct qlcnic_hardware_context *ahw = adapter->ahw; | |
2c4a7878 | 1735 | struct net_device *netdev = adapter->netdev; |
77bead46 | 1736 | u32 config, max_wait_count; |
629263ac | 1737 | int status = 0, loop = 0; |
7f966452 | 1738 | |
77bead46 MC |
1739 | ahw->extend_lb_time = 0; |
1740 | max_wait_count = QLC_83XX_LB_WAIT_COUNT; | |
7f966452 SC |
1741 | status = qlcnic_83xx_get_port_config(adapter); |
1742 | if (status) | |
1743 | return status; | |
1744 | ||
1745 | config = ahw->port_config; | |
b9c11984 JK |
1746 | |
1747 | /* Check if port is already in loopback mode */ | |
1748 | if ((config & QLC_83XX_CFG_LOOPBACK_HSS) || | |
1749 | (config & QLC_83XX_CFG_LOOPBACK_EXT)) { | |
1750 | netdev_err(netdev, | |
1751 | "Port already in Loopback mode.\n"); | |
1752 | return -EINPROGRESS; | |
1753 | } | |
1754 | ||
629263ac | 1755 | set_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status); |
7f966452 SC |
1756 | |
1757 | if (mode == QLCNIC_ILB_MODE) | |
1758 | ahw->port_config |= QLC_83XX_CFG_LOOPBACK_HSS; | |
1759 | if (mode == QLCNIC_ELB_MODE) | |
1760 | ahw->port_config |= QLC_83XX_CFG_LOOPBACK_EXT; | |
1761 | ||
1762 | status = qlcnic_83xx_set_port_config(adapter); | |
1763 | if (status) { | |
2c4a7878 JK |
1764 | netdev_err(netdev, |
1765 | "Failed to Set Loopback Mode = 0x%x.\n", | |
1766 | ahw->port_config); | |
7f966452 | 1767 | ahw->port_config = config; |
629263ac | 1768 | clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status); |
7f966452 SC |
1769 | return status; |
1770 | } | |
1771 | ||
9a05f92b | 1772 | /* Wait for Link and IDC Completion AEN */ |
629263ac | 1773 | do { |
2c4a7878 | 1774 | msleep(QLC_83XX_LB_MSLEEP_COUNT); |
d1a1105e | 1775 | |
2c4a7878 JK |
1776 | if (test_bit(__QLCNIC_RESETTING, &adapter->state)) { |
1777 | netdev_info(netdev, | |
1778 | "Device is resetting, free LB test resources\n"); | |
1779 | clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status); | |
b9c11984 | 1780 | return -EBUSY; |
2c4a7878 | 1781 | } |
77bead46 MC |
1782 | |
1783 | if (ahw->extend_lb_time) | |
1784 | qlcnic_extend_lb_idc_cmpltn_wait(adapter, | |
1785 | &max_wait_count); | |
1786 | ||
1787 | if (loop++ > max_wait_count) { | |
1788 | netdev_err(netdev, "%s: Did not receive loopback IDC completion AEN\n", | |
1789 | __func__); | |
629263ac | 1790 | clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status); |
9a05f92b | 1791 | qlcnic_83xx_clear_lb_mode(adapter, mode); |
b9c11984 | 1792 | return -ETIMEDOUT; |
629263ac SC |
1793 | } |
1794 | } while (test_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status)); | |
1795 | ||
7f966452 SC |
1796 | qlcnic_sre_macaddr_change(adapter, adapter->mac_addr, 0, |
1797 | QLCNIC_MAC_ADD); | |
1798 | return status; | |
1799 | } | |
1800 | ||
1801 | int qlcnic_83xx_clear_lb_mode(struct qlcnic_adapter *adapter, u8 mode) | |
1802 | { | |
1803 | struct qlcnic_hardware_context *ahw = adapter->ahw; | |
77bead46 | 1804 | u32 config = ahw->port_config, max_wait_count; |
2c4a7878 | 1805 | struct net_device *netdev = adapter->netdev; |
629263ac | 1806 | int status = 0, loop = 0; |
7f966452 | 1807 | |
77bead46 MC |
1808 | ahw->extend_lb_time = 0; |
1809 | max_wait_count = QLC_83XX_LB_WAIT_COUNT; | |
629263ac | 1810 | set_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status); |
7f966452 SC |
1811 | if (mode == QLCNIC_ILB_MODE) |
1812 | ahw->port_config &= ~QLC_83XX_CFG_LOOPBACK_HSS; | |
1813 | if (mode == QLCNIC_ELB_MODE) | |
1814 | ahw->port_config &= ~QLC_83XX_CFG_LOOPBACK_EXT; | |
1815 | ||
1816 | status = qlcnic_83xx_set_port_config(adapter); | |
1817 | if (status) { | |
2c4a7878 JK |
1818 | netdev_err(netdev, |
1819 | "Failed to Clear Loopback Mode = 0x%x.\n", | |
1820 | ahw->port_config); | |
7f966452 | 1821 | ahw->port_config = config; |
629263ac | 1822 | clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status); |
7f966452 SC |
1823 | return status; |
1824 | } | |
1825 | ||
9a05f92b | 1826 | /* Wait for Link and IDC Completion AEN */ |
629263ac | 1827 | do { |
2c4a7878 | 1828 | msleep(QLC_83XX_LB_MSLEEP_COUNT); |
d1a1105e | 1829 | |
2c4a7878 JK |
1830 | if (test_bit(__QLCNIC_RESETTING, &adapter->state)) { |
1831 | netdev_info(netdev, | |
1832 | "Device is resetting, free LB test resources\n"); | |
1833 | clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status); | |
b9c11984 | 1834 | return -EBUSY; |
2c4a7878 JK |
1835 | } |
1836 | ||
77bead46 MC |
1837 | if (ahw->extend_lb_time) |
1838 | qlcnic_extend_lb_idc_cmpltn_wait(adapter, | |
1839 | &max_wait_count); | |
1840 | ||
1841 | if (loop++ > max_wait_count) { | |
1842 | netdev_err(netdev, "%s: Did not receive loopback IDC completion AEN\n", | |
1843 | __func__); | |
629263ac | 1844 | clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status); |
b9c11984 | 1845 | return -ETIMEDOUT; |
629263ac SC |
1846 | } |
1847 | } while (test_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status)); | |
1848 | ||
7f966452 SC |
1849 | qlcnic_sre_macaddr_change(adapter, adapter->mac_addr, 0, |
1850 | QLCNIC_MAC_DEL); | |
1851 | return status; | |
1852 | } | |
1853 | ||
7cb03b23 RB |
1854 | static void qlcnic_83xx_set_interface_id_ipaddr(struct qlcnic_adapter *adapter, |
1855 | u32 *interface_id) | |
1856 | { | |
1857 | if (qlcnic_sriov_pf_check(adapter)) { | |
1858 | qlcnic_pf_set_interface_id_ipaddr(adapter, interface_id); | |
1859 | } else { | |
1860 | if (!qlcnic_sriov_vf_check(adapter)) | |
1861 | *interface_id = adapter->recv_ctx->context_id << 16; | |
1862 | } | |
1863 | } | |
1864 | ||
7f966452 SC |
1865 | void qlcnic_83xx_config_ipaddr(struct qlcnic_adapter *adapter, __be32 ip, |
1866 | int mode) | |
1867 | { | |
1868 | int err; | |
7cb03b23 | 1869 | u32 temp = 0, temp_ip; |
7f966452 SC |
1870 | struct qlcnic_cmd_args cmd; |
1871 | ||
b6b4316c SS |
1872 | err = qlcnic_alloc_mbx_args(&cmd, adapter, |
1873 | QLCNIC_CMD_CONFIGURE_IP_ADDR); | |
1874 | if (err) | |
1875 | return; | |
1876 | ||
7cb03b23 RB |
1877 | qlcnic_83xx_set_interface_id_ipaddr(adapter, &temp); |
1878 | ||
1879 | if (mode == QLCNIC_IP_UP) | |
7f966452 | 1880 | cmd.req.arg[1] = 1 | temp; |
7cb03b23 | 1881 | else |
7f966452 | 1882 | cmd.req.arg[1] = 2 | temp; |
7f966452 | 1883 | |
283c1c68 M |
1884 | /* |
1885 | * Adapter needs IP address in network byte order. | |
1886 | * But hardware mailbox registers go through writel(), hence IP address | |
1887 | * gets swapped on big endian architecture. | |
1888 | * To negate swapping of writel() on big endian architecture | |
1889 | * use swab32(value). | |
1890 | */ | |
1891 | ||
1892 | temp_ip = swab32(ntohl(ip)); | |
1893 | memcpy(&cmd.req.arg[2], &temp_ip, sizeof(u32)); | |
7f966452 SC |
1894 | err = qlcnic_issue_cmd(adapter, &cmd); |
1895 | if (err != QLCNIC_RCODE_SUCCESS) | |
1896 | dev_err(&adapter->netdev->dev, | |
1897 | "could not notify %s IP 0x%x request\n", | |
1898 | (mode == QLCNIC_IP_UP) ? "Add" : "Remove", ip); | |
7cb03b23 | 1899 | |
7f966452 SC |
1900 | qlcnic_free_mbx_args(&cmd); |
1901 | } | |
1902 | ||
1903 | int qlcnic_83xx_config_hw_lro(struct qlcnic_adapter *adapter, int mode) | |
1904 | { | |
1905 | int err; | |
1906 | u32 temp, arg1; | |
1907 | struct qlcnic_cmd_args cmd; | |
283c1c68 M |
1908 | int lro_bit_mask; |
1909 | ||
1910 | lro_bit_mask = (mode ? (BIT_0 | BIT_1 | BIT_2 | BIT_3) : 0); | |
7f966452 SC |
1911 | |
1912 | if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED) | |
1913 | return 0; | |
1914 | ||
b6b4316c SS |
1915 | err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIGURE_HW_LRO); |
1916 | if (err) | |
1917 | return err; | |
1918 | ||
7f966452 | 1919 | temp = adapter->recv_ctx->context_id << 16; |
283c1c68 | 1920 | arg1 = lro_bit_mask | temp; |
7f966452 SC |
1921 | cmd.req.arg[1] = arg1; |
1922 | ||
1923 | err = qlcnic_issue_cmd(adapter, &cmd); | |
1924 | if (err) | |
1925 | dev_info(&adapter->pdev->dev, "LRO config failed\n"); | |
1926 | qlcnic_free_mbx_args(&cmd); | |
1927 | ||
1928 | return err; | |
1929 | } | |
1930 | ||
1931 | int qlcnic_83xx_config_rss(struct qlcnic_adapter *adapter, int enable) | |
1932 | { | |
1933 | int err; | |
1934 | u32 word; | |
1935 | struct qlcnic_cmd_args cmd; | |
1936 | const u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL, | |
1937 | 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL, | |
1938 | 0x255b0ec26d5a56daULL }; | |
1939 | ||
b6b4316c SS |
1940 | err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIGURE_RSS); |
1941 | if (err) | |
1942 | return err; | |
7f966452 SC |
1943 | /* |
1944 | * RSS request: | |
1945 | * bits 3-0: Rsvd | |
1946 | * 5-4: hash_type_ipv4 | |
1947 | * 7-6: hash_type_ipv6 | |
1948 | * 8: enable | |
1949 | * 9: use indirection table | |
1950 | * 16-31: indirection table mask | |
1951 | */ | |
1952 | word = ((u32)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) | | |
1953 | ((u32)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) | | |
1954 | ((u32)(enable & 0x1) << 8) | | |
1955 | ((0x7ULL) << 16); | |
1956 | cmd.req.arg[1] = (adapter->recv_ctx->context_id); | |
1957 | cmd.req.arg[2] = word; | |
1958 | memcpy(&cmd.req.arg[4], key, sizeof(key)); | |
1959 | ||
1960 | err = qlcnic_issue_cmd(adapter, &cmd); | |
1961 | ||
1962 | if (err) | |
1963 | dev_info(&adapter->pdev->dev, "RSS config failed\n"); | |
1964 | qlcnic_free_mbx_args(&cmd); | |
1965 | ||
1966 | return err; | |
1967 | ||
1968 | } | |
1969 | ||
7cb03b23 RB |
1970 | static void qlcnic_83xx_set_interface_id_macaddr(struct qlcnic_adapter *adapter, |
1971 | u32 *interface_id) | |
1972 | { | |
1973 | if (qlcnic_sriov_pf_check(adapter)) { | |
1974 | qlcnic_pf_set_interface_id_macaddr(adapter, interface_id); | |
1975 | } else { | |
1976 | if (!qlcnic_sriov_vf_check(adapter)) | |
1977 | *interface_id = adapter->recv_ctx->context_id << 16; | |
1978 | } | |
1979 | } | |
1980 | ||
7f966452 | 1981 | int qlcnic_83xx_sre_macaddr_change(struct qlcnic_adapter *adapter, u8 *addr, |
f80bc8fe | 1982 | u16 vlan_id, u8 op) |
7f966452 | 1983 | { |
068a8d19 | 1984 | struct qlcnic_cmd_args *cmd = NULL; |
7f966452 | 1985 | struct qlcnic_macvlan_mbx mv; |
068a8d19 MC |
1986 | u32 *buf, temp = 0; |
1987 | int err; | |
7f966452 SC |
1988 | |
1989 | if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED) | |
1990 | return -EIO; | |
1991 | ||
068a8d19 MC |
1992 | cmd = kzalloc(sizeof(*cmd), GFP_ATOMIC); |
1993 | if (!cmd) | |
1994 | return -ENOMEM; | |
1995 | ||
1996 | err = qlcnic_alloc_mbx_args(cmd, adapter, QLCNIC_CMD_CONFIG_MAC_VLAN); | |
7f966452 | 1997 | if (err) |
068a8d19 MC |
1998 | goto out; |
1999 | ||
2000 | cmd->type = QLC_83XX_MBX_CMD_NO_WAIT; | |
7f966452 | 2001 | |
91b7282b RB |
2002 | if (vlan_id) |
2003 | op = (op == QLCNIC_MAC_ADD || op == QLCNIC_MAC_VLAN_ADD) ? | |
2004 | QLCNIC_MAC_VLAN_ADD : QLCNIC_MAC_VLAN_DEL; | |
2005 | ||
068a8d19 | 2006 | cmd->req.arg[1] = op | (1 << 8); |
7cb03b23 | 2007 | qlcnic_83xx_set_interface_id_macaddr(adapter, &temp); |
068a8d19 | 2008 | cmd->req.arg[1] |= temp; |
f80bc8fe | 2009 | mv.vlan = vlan_id; |
a96227e6 SS |
2010 | mv.mac_addr0 = addr[0]; |
2011 | mv.mac_addr1 = addr[1]; | |
2012 | mv.mac_addr2 = addr[2]; | |
2013 | mv.mac_addr3 = addr[3]; | |
2014 | mv.mac_addr4 = addr[4]; | |
2015 | mv.mac_addr5 = addr[5]; | |
068a8d19 | 2016 | buf = &cmd->req.arg[2]; |
7f966452 | 2017 | memcpy(buf, &mv, sizeof(struct qlcnic_macvlan_mbx)); |
068a8d19 MC |
2018 | err = qlcnic_issue_cmd(adapter, cmd); |
2019 | if (!err) | |
2020 | return err; | |
2021 | ||
2022 | qlcnic_free_mbx_args(cmd); | |
2023 | out: | |
2024 | kfree(cmd); | |
7f966452 SC |
2025 | return err; |
2026 | } | |
2027 | ||
2028 | void qlcnic_83xx_change_l2_filter(struct qlcnic_adapter *adapter, u64 *addr, | |
f80bc8fe | 2029 | u16 vlan_id) |
7f966452 SC |
2030 | { |
2031 | u8 mac[ETH_ALEN]; | |
2032 | memcpy(&mac, addr, ETH_ALEN); | |
2033 | qlcnic_83xx_sre_macaddr_change(adapter, mac, vlan_id, QLCNIC_MAC_ADD); | |
2034 | } | |
2035 | ||
2036 | void qlcnic_83xx_configure_mac(struct qlcnic_adapter *adapter, u8 *mac, | |
2037 | u8 type, struct qlcnic_cmd_args *cmd) | |
2038 | { | |
2039 | switch (type) { | |
2040 | case QLCNIC_SET_STATION_MAC: | |
2041 | case QLCNIC_SET_FAC_DEF_MAC: | |
2042 | memcpy(&cmd->req.arg[2], mac, sizeof(u32)); | |
2043 | memcpy(&cmd->req.arg[3], &mac[4], sizeof(u16)); | |
2044 | break; | |
2045 | } | |
2046 | cmd->req.arg[1] = type; | |
2047 | } | |
2048 | ||
07a251c8 SS |
2049 | int qlcnic_83xx_get_mac_address(struct qlcnic_adapter *adapter, u8 *mac, |
2050 | u8 function) | |
7f966452 SC |
2051 | { |
2052 | int err, i; | |
2053 | struct qlcnic_cmd_args cmd; | |
2054 | u32 mac_low, mac_high; | |
2055 | ||
07a251c8 | 2056 | function = 0; |
b6b4316c SS |
2057 | err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_MAC_ADDRESS); |
2058 | if (err) | |
2059 | return err; | |
2060 | ||
7f966452 SC |
2061 | qlcnic_83xx_configure_mac(adapter, mac, QLCNIC_GET_CURRENT_MAC, &cmd); |
2062 | err = qlcnic_issue_cmd(adapter, &cmd); | |
2063 | ||
2064 | if (err == QLCNIC_RCODE_SUCCESS) { | |
2065 | mac_low = cmd.rsp.arg[1]; | |
2066 | mac_high = cmd.rsp.arg[2]; | |
2067 | ||
2068 | for (i = 0; i < 2; i++) | |
2069 | mac[i] = (u8) (mac_high >> ((1 - i) * 8)); | |
2070 | for (i = 2; i < 6; i++) | |
2071 | mac[i] = (u8) (mac_low >> ((5 - i) * 8)); | |
2072 | } else { | |
2073 | dev_err(&adapter->pdev->dev, "Failed to get mac address%d\n", | |
2074 | err); | |
2075 | err = -EIO; | |
2076 | } | |
2077 | qlcnic_free_mbx_args(&cmd); | |
2078 | return err; | |
2079 | } | |
2080 | ||
2081 | void qlcnic_83xx_config_intr_coal(struct qlcnic_adapter *adapter) | |
2082 | { | |
2083 | int err; | |
be273dc1 | 2084 | u16 temp; |
7f966452 SC |
2085 | struct qlcnic_cmd_args cmd; |
2086 | struct qlcnic_nic_intr_coalesce *coal = &adapter->ahw->coal; | |
2087 | ||
2088 | if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED) | |
2089 | return; | |
2090 | ||
b6b4316c SS |
2091 | err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_INTR_COAL); |
2092 | if (err) | |
2093 | return; | |
2094 | ||
be273dc1 HM |
2095 | if (coal->type == QLCNIC_INTR_COAL_TYPE_RX) { |
2096 | temp = adapter->recv_ctx->context_id; | |
2097 | cmd.req.arg[1] = QLCNIC_INTR_COAL_TYPE_RX | temp << 16; | |
2098 | temp = coal->rx_time_us; | |
2099 | cmd.req.arg[2] = coal->rx_packets | temp << 16; | |
2100 | } else if (coal->type == QLCNIC_INTR_COAL_TYPE_TX) { | |
2101 | temp = adapter->tx_ring->ctx_id; | |
2102 | cmd.req.arg[1] = QLCNIC_INTR_COAL_TYPE_TX | temp << 16; | |
2103 | temp = coal->tx_time_us; | |
2104 | cmd.req.arg[2] = coal->tx_packets | temp << 16; | |
2105 | } | |
7f966452 | 2106 | cmd.req.arg[3] = coal->flag; |
7f966452 SC |
2107 | err = qlcnic_issue_cmd(adapter, &cmd); |
2108 | if (err != QLCNIC_RCODE_SUCCESS) | |
2109 | dev_info(&adapter->pdev->dev, | |
2110 | "Failed to send interrupt coalescence parameters\n"); | |
2111 | qlcnic_free_mbx_args(&cmd); | |
2112 | } | |
2113 | ||
2114 | static void qlcnic_83xx_handle_link_aen(struct qlcnic_adapter *adapter, | |
2115 | u32 data[]) | |
2116 | { | |
b1f5037f | 2117 | struct qlcnic_hardware_context *ahw = adapter->ahw; |
7f966452 SC |
2118 | u8 link_status, duplex; |
2119 | /* link speed */ | |
2120 | link_status = LSB(data[3]) & 1; | |
b1f5037f RB |
2121 | if (link_status) { |
2122 | ahw->link_speed = MSW(data[2]); | |
2123 | duplex = LSB(MSW(data[3])); | |
2124 | if (duplex) | |
2125 | ahw->link_duplex = DUPLEX_FULL; | |
2126 | else | |
2127 | ahw->link_duplex = DUPLEX_HALF; | |
2128 | } else { | |
2129 | ahw->link_speed = SPEED_UNKNOWN; | |
2130 | ahw->link_duplex = DUPLEX_UNKNOWN; | |
2131 | } | |
2132 | ||
2133 | ahw->link_autoneg = MSB(MSW(data[3])); | |
2134 | ahw->module_type = MSB(LSW(data[3])); | |
2135 | ahw->has_link_events = 1; | |
7f966452 SC |
2136 | qlcnic_advert_link_change(adapter, link_status); |
2137 | } | |
2138 | ||
2139 | irqreturn_t qlcnic_83xx_handle_aen(int irq, void *data) | |
2140 | { | |
2141 | struct qlcnic_adapter *adapter = data; | |
068a8d19 | 2142 | struct qlcnic_mailbox *mbx; |
483202d5 | 2143 | u32 mask, resp, event; |
068a8d19 | 2144 | unsigned long flags; |
483202d5 | 2145 | |
068a8d19 MC |
2146 | mbx = adapter->ahw->mailbox; |
2147 | spin_lock_irqsave(&mbx->aen_lock, flags); | |
483202d5 JK |
2148 | resp = QLCRDX(adapter->ahw, QLCNIC_FW_MBX_CTRL); |
2149 | if (!(resp & QLCNIC_SET_OWNER)) | |
2150 | goto out; | |
ac166700 | 2151 | |
483202d5 JK |
2152 | event = readl(QLCNIC_MBX_FW(adapter->ahw, 0)); |
2153 | if (event & QLCNIC_MBX_ASYNC_EVENT) | |
d1a1105e | 2154 | __qlcnic_83xx_process_aen(adapter); |
068a8d19 MC |
2155 | else |
2156 | qlcnic_83xx_notify_mbx_response(mbx); | |
2157 | ||
483202d5 JK |
2158 | out: |
2159 | mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK); | |
2160 | writel(0, adapter->ahw->pci_base0 + mask); | |
068a8d19 | 2161 | spin_unlock_irqrestore(&mbx->aen_lock, flags); |
7f966452 SC |
2162 | return IRQ_HANDLED; |
2163 | } | |
2164 | ||
2165 | int qlcnic_enable_eswitch(struct qlcnic_adapter *adapter, u8 port, u8 enable) | |
2166 | { | |
2167 | int err = -EIO; | |
2168 | struct qlcnic_cmd_args cmd; | |
2169 | ||
2170 | if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC) { | |
2171 | dev_err(&adapter->pdev->dev, | |
2172 | "%s: Error, invoked by non management func\n", | |
2173 | __func__); | |
2174 | return err; | |
2175 | } | |
2176 | ||
b6b4316c SS |
2177 | err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_TOGGLE_ESWITCH); |
2178 | if (err) | |
2179 | return err; | |
2180 | ||
7f966452 SC |
2181 | cmd.req.arg[1] = (port & 0xf) | BIT_4; |
2182 | err = qlcnic_issue_cmd(adapter, &cmd); | |
2183 | ||
2184 | if (err != QLCNIC_RCODE_SUCCESS) { | |
2185 | dev_err(&adapter->pdev->dev, "Failed to enable eswitch%d\n", | |
2186 | err); | |
2187 | err = -EIO; | |
2188 | } | |
2189 | qlcnic_free_mbx_args(&cmd); | |
2190 | ||
2191 | return err; | |
2192 | ||
2193 | } | |
2194 | ||
2195 | int qlcnic_83xx_set_nic_info(struct qlcnic_adapter *adapter, | |
2196 | struct qlcnic_info *nic) | |
2197 | { | |
2198 | int i, err = -EIO; | |
2199 | struct qlcnic_cmd_args cmd; | |
2200 | ||
2201 | if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC) { | |
2202 | dev_err(&adapter->pdev->dev, | |
2203 | "%s: Error, invoked by non management func\n", | |
2204 | __func__); | |
2205 | return err; | |
2206 | } | |
2207 | ||
b6b4316c SS |
2208 | err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_NIC_INFO); |
2209 | if (err) | |
2210 | return err; | |
2211 | ||
7f966452 SC |
2212 | cmd.req.arg[1] = (nic->pci_func << 16); |
2213 | cmd.req.arg[2] = 0x1 << 16; | |
2214 | cmd.req.arg[3] = nic->phys_port | (nic->switch_mode << 16); | |
2215 | cmd.req.arg[4] = nic->capabilities; | |
2216 | cmd.req.arg[5] = (nic->max_mac_filters & 0xFF) | ((nic->max_mtu) << 16); | |
2217 | cmd.req.arg[6] = (nic->max_tx_ques) | ((nic->max_rx_ques) << 16); | |
2218 | cmd.req.arg[7] = (nic->min_tx_bw) | ((nic->max_tx_bw) << 16); | |
2219 | for (i = 8; i < 32; i++) | |
2220 | cmd.req.arg[i] = 0; | |
2221 | ||
2222 | err = qlcnic_issue_cmd(adapter, &cmd); | |
2223 | ||
2224 | if (err != QLCNIC_RCODE_SUCCESS) { | |
2225 | dev_err(&adapter->pdev->dev, "Failed to set nic info%d\n", | |
2226 | err); | |
2227 | err = -EIO; | |
2228 | } | |
2229 | ||
2230 | qlcnic_free_mbx_args(&cmd); | |
2231 | ||
2232 | return err; | |
2233 | } | |
2234 | ||
2235 | int qlcnic_83xx_get_nic_info(struct qlcnic_adapter *adapter, | |
2236 | struct qlcnic_info *npar_info, u8 func_id) | |
2237 | { | |
2238 | int err; | |
2239 | u32 temp; | |
2240 | u8 op = 0; | |
2241 | struct qlcnic_cmd_args cmd; | |
8af3f33d | 2242 | struct qlcnic_hardware_context *ahw = adapter->ahw; |
7f966452 | 2243 | |
b6b4316c SS |
2244 | err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_NIC_INFO); |
2245 | if (err) | |
2246 | return err; | |
2247 | ||
8af3f33d | 2248 | if (func_id != ahw->pci_func) { |
7f966452 SC |
2249 | temp = func_id << 16; |
2250 | cmd.req.arg[1] = op | BIT_31 | temp; | |
2251 | } else { | |
8af3f33d | 2252 | cmd.req.arg[1] = ahw->pci_func << 16; |
7f966452 SC |
2253 | } |
2254 | err = qlcnic_issue_cmd(adapter, &cmd); | |
2255 | if (err) { | |
2256 | dev_info(&adapter->pdev->dev, | |
2257 | "Failed to get nic info %d\n", err); | |
2258 | goto out; | |
2259 | } | |
2260 | ||
2261 | npar_info->op_type = cmd.rsp.arg[1]; | |
2262 | npar_info->pci_func = cmd.rsp.arg[2] & 0xFFFF; | |
2263 | npar_info->op_mode = (cmd.rsp.arg[2] & 0xFFFF0000) >> 16; | |
2264 | npar_info->phys_port = cmd.rsp.arg[3] & 0xFFFF; | |
2265 | npar_info->switch_mode = (cmd.rsp.arg[3] & 0xFFFF0000) >> 16; | |
2266 | npar_info->capabilities = cmd.rsp.arg[4]; | |
2267 | npar_info->max_mac_filters = cmd.rsp.arg[5] & 0xFF; | |
2268 | npar_info->max_mtu = (cmd.rsp.arg[5] & 0xFFFF0000) >> 16; | |
2269 | npar_info->max_tx_ques = cmd.rsp.arg[6] & 0xFFFF; | |
2270 | npar_info->max_rx_ques = (cmd.rsp.arg[6] & 0xFFFF0000) >> 16; | |
2271 | npar_info->min_tx_bw = cmd.rsp.arg[7] & 0xFFFF; | |
2272 | npar_info->max_tx_bw = (cmd.rsp.arg[7] & 0xFFFF0000) >> 16; | |
2273 | if (cmd.rsp.arg[8] & 0x1) | |
2274 | npar_info->max_bw_reg_offset = (cmd.rsp.arg[8] & 0x7FFE) >> 1; | |
2275 | if (cmd.rsp.arg[8] & 0x10000) { | |
2276 | temp = (cmd.rsp.arg[8] & 0x7FFE0000) >> 17; | |
2277 | npar_info->max_linkspeed_reg_offset = temp; | |
2278 | } | |
8af3f33d PP |
2279 | if (npar_info->capabilities & QLCNIC_FW_CAPABILITY_MORE_CAPS) |
2280 | memcpy(ahw->extra_capability, &cmd.rsp.arg[16], | |
2281 | sizeof(ahw->extra_capability)); | |
7f966452 SC |
2282 | |
2283 | out: | |
2284 | qlcnic_free_mbx_args(&cmd); | |
2285 | return err; | |
2286 | } | |
2287 | ||
2288 | int qlcnic_83xx_get_pci_info(struct qlcnic_adapter *adapter, | |
2289 | struct qlcnic_pci_info *pci_info) | |
2290 | { | |
ee9e8b6c MC |
2291 | struct qlcnic_hardware_context *ahw = adapter->ahw; |
2292 | struct device *dev = &adapter->pdev->dev; | |
2293 | struct qlcnic_cmd_args cmd; | |
7f966452 SC |
2294 | int i, err = 0, j = 0; |
2295 | u32 temp; | |
7f966452 | 2296 | |
b6b4316c SS |
2297 | err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PCI_INFO); |
2298 | if (err) | |
2299 | return err; | |
2300 | ||
7f966452 SC |
2301 | err = qlcnic_issue_cmd(adapter, &cmd); |
2302 | ||
ee9e8b6c | 2303 | ahw->act_pci_func = 0; |
7f966452 | 2304 | if (err == QLCNIC_RCODE_SUCCESS) { |
ee9e8b6c | 2305 | ahw->max_pci_func = cmd.rsp.arg[1] & 0xFF; |
7f966452 SC |
2306 | for (i = 2, j = 0; j < QLCNIC_MAX_PCI_FUNC; j++, pci_info++) { |
2307 | pci_info->id = cmd.rsp.arg[i] & 0xFFFF; | |
2308 | pci_info->active = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16; | |
2309 | i++; | |
2310 | pci_info->type = cmd.rsp.arg[i] & 0xFFFF; | |
2311 | if (pci_info->type == QLCNIC_TYPE_NIC) | |
ee9e8b6c | 2312 | ahw->act_pci_func++; |
7f966452 SC |
2313 | temp = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16; |
2314 | pci_info->default_port = temp; | |
2315 | i++; | |
2316 | pci_info->tx_min_bw = cmd.rsp.arg[i] & 0xFFFF; | |
2317 | temp = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16; | |
2318 | pci_info->tx_max_bw = temp; | |
2319 | i = i + 2; | |
2320 | memcpy(pci_info->mac, &cmd.rsp.arg[i], ETH_ALEN - 2); | |
2321 | i++; | |
2322 | memcpy(pci_info->mac + sizeof(u32), &cmd.rsp.arg[i], 2); | |
2323 | i = i + 3; | |
ee9e8b6c MC |
2324 | if (ahw->op_mode == QLCNIC_MGMT_FUNC) |
2325 | dev_info(dev, "id = %d active = %d type = %d\n" | |
2326 | "\tport = %d min bw = %d max bw = %d\n" | |
2327 | "\tmac_addr = %pM\n", pci_info->id, | |
2328 | pci_info->active, pci_info->type, | |
2329 | pci_info->default_port, | |
2330 | pci_info->tx_min_bw, | |
2331 | pci_info->tx_max_bw, pci_info->mac); | |
7f966452 | 2332 | } |
ee9e8b6c | 2333 | if (ahw->op_mode == QLCNIC_MGMT_FUNC) |
35dafcb0 | 2334 | dev_info(dev, "Max functions = %d, active functions = %d\n", |
ee9e8b6c MC |
2335 | ahw->max_pci_func, ahw->act_pci_func); |
2336 | ||
7f966452 | 2337 | } else { |
ee9e8b6c | 2338 | dev_err(dev, "Failed to get PCI Info, error = %d\n", err); |
7f966452 SC |
2339 | err = -EIO; |
2340 | } | |
2341 | ||
2342 | qlcnic_free_mbx_args(&cmd); | |
2343 | ||
2344 | return err; | |
2345 | } | |
2346 | ||
2347 | int qlcnic_83xx_config_intrpt(struct qlcnic_adapter *adapter, bool op_type) | |
2348 | { | |
2349 | int i, index, err; | |
7f966452 | 2350 | u8 max_ints; |
e2ab1233 | 2351 | u32 val, temp, type; |
7f966452 SC |
2352 | struct qlcnic_cmd_args cmd; |
2353 | ||
7dd90cf1 | 2354 | max_ints = adapter->ahw->num_msix - 1; |
b6b4316c SS |
2355 | err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_INTRPT); |
2356 | if (err) | |
2357 | return err; | |
2358 | ||
7f966452 | 2359 | cmd.req.arg[1] = max_ints; |
7cb03b23 RB |
2360 | |
2361 | if (qlcnic_sriov_vf_check(adapter)) | |
2362 | cmd.req.arg[1] |= (adapter->ahw->pci_func << 8) | BIT_16; | |
2363 | ||
7f966452 SC |
2364 | for (i = 0, index = 2; i < max_ints; i++) { |
2365 | type = op_type ? QLCNIC_INTRPT_ADD : QLCNIC_INTRPT_DEL; | |
2366 | val = type | (adapter->ahw->intr_tbl[i].type << 4); | |
2367 | if (adapter->ahw->intr_tbl[i].type == QLCNIC_INTRPT_MSIX) | |
2368 | val |= (adapter->ahw->intr_tbl[i].id << 16); | |
2369 | cmd.req.arg[index++] = val; | |
2370 | } | |
2371 | err = qlcnic_issue_cmd(adapter, &cmd); | |
2372 | if (err) { | |
2373 | dev_err(&adapter->pdev->dev, | |
2374 | "Failed to configure interrupts 0x%x\n", err); | |
2375 | goto out; | |
2376 | } | |
2377 | ||
2378 | max_ints = cmd.rsp.arg[1]; | |
2379 | for (i = 0, index = 2; i < max_ints; i++, index += 2) { | |
2380 | val = cmd.rsp.arg[index]; | |
2381 | if (LSB(val)) { | |
2382 | dev_info(&adapter->pdev->dev, | |
2383 | "Can't configure interrupt %d\n", | |
2384 | adapter->ahw->intr_tbl[i].id); | |
2385 | continue; | |
2386 | } | |
2387 | if (op_type) { | |
2388 | adapter->ahw->intr_tbl[i].id = MSW(val); | |
2389 | adapter->ahw->intr_tbl[i].enabled = 1; | |
2390 | temp = cmd.rsp.arg[index + 1]; | |
2391 | adapter->ahw->intr_tbl[i].src = temp; | |
2392 | } else { | |
2393 | adapter->ahw->intr_tbl[i].id = i; | |
2394 | adapter->ahw->intr_tbl[i].enabled = 0; | |
2395 | adapter->ahw->intr_tbl[i].src = 0; | |
2396 | } | |
2397 | } | |
2398 | out: | |
2399 | qlcnic_free_mbx_args(&cmd); | |
2400 | return err; | |
2401 | } | |
d865ebb4 SC |
2402 | |
2403 | int qlcnic_83xx_lock_flash(struct qlcnic_adapter *adapter) | |
2404 | { | |
2405 | int id, timeout = 0; | |
2406 | u32 status = 0; | |
2407 | ||
2408 | while (status == 0) { | |
2409 | status = QLC_SHARED_REG_RD32(adapter, QLCNIC_FLASH_LOCK); | |
2410 | if (status) | |
2411 | break; | |
2412 | ||
2413 | if (++timeout >= QLC_83XX_FLASH_LOCK_TIMEOUT) { | |
2414 | id = QLC_SHARED_REG_RD32(adapter, | |
2415 | QLCNIC_FLASH_LOCK_OWNER); | |
2416 | dev_err(&adapter->pdev->dev, | |
2417 | "%s: failed, lock held by %d\n", __func__, id); | |
2418 | return -EIO; | |
2419 | } | |
2420 | usleep_range(1000, 2000); | |
2421 | } | |
2422 | ||
2423 | QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER, adapter->portnum); | |
2424 | return 0; | |
2425 | } | |
2426 | ||
2427 | void qlcnic_83xx_unlock_flash(struct qlcnic_adapter *adapter) | |
2428 | { | |
2429 | QLC_SHARED_REG_RD32(adapter, QLCNIC_FLASH_UNLOCK); | |
2430 | QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER, 0xFF); | |
2431 | } | |
2432 | ||
629263ac SC |
2433 | int qlcnic_83xx_lockless_flash_read32(struct qlcnic_adapter *adapter, |
2434 | u32 flash_addr, u8 *p_data, | |
2435 | int count) | |
d865ebb4 | 2436 | { |
4bd8e738 | 2437 | u32 word, range, flash_offset, addr = flash_addr, ret; |
d865ebb4 | 2438 | ulong indirect_add, direct_window; |
4bd8e738 | 2439 | int i, err = 0; |
d865ebb4 SC |
2440 | |
2441 | flash_offset = addr & (QLCNIC_FLASH_SECTOR_SIZE - 1); | |
2442 | if (addr & 0x3) { | |
2443 | dev_err(&adapter->pdev->dev, "Illegal addr = 0x%x\n", addr); | |
2444 | return -EIO; | |
2445 | } | |
2446 | ||
2447 | qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_DIRECT_WINDOW, | |
2448 | (addr)); | |
2449 | ||
2450 | range = flash_offset + (count * sizeof(u32)); | |
2451 | /* Check if data is spread across multiple sectors */ | |
2452 | if (range > (QLCNIC_FLASH_SECTOR_SIZE - 1)) { | |
2453 | ||
2454 | /* Multi sector read */ | |
2455 | for (i = 0; i < count; i++) { | |
2456 | indirect_add = QLC_83XX_FLASH_DIRECT_DATA(addr); | |
4bd8e738 HM |
2457 | ret = QLCRD32(adapter, indirect_add, &err); |
2458 | if (err == -EIO) | |
2459 | return err; | |
d865ebb4 SC |
2460 | |
2461 | word = ret; | |
2462 | *(u32 *)p_data = word; | |
2463 | p_data = p_data + 4; | |
2464 | addr = addr + 4; | |
2465 | flash_offset = flash_offset + 4; | |
2466 | ||
2467 | if (flash_offset > (QLCNIC_FLASH_SECTOR_SIZE - 1)) { | |
2468 | direct_window = QLC_83XX_FLASH_DIRECT_WINDOW; | |
2469 | /* This write is needed once for each sector */ | |
2470 | qlcnic_83xx_wrt_reg_indirect(adapter, | |
2471 | direct_window, | |
2472 | (addr)); | |
2473 | flash_offset = 0; | |
2474 | } | |
2475 | } | |
2476 | } else { | |
2477 | /* Single sector read */ | |
2478 | for (i = 0; i < count; i++) { | |
2479 | indirect_add = QLC_83XX_FLASH_DIRECT_DATA(addr); | |
4bd8e738 HM |
2480 | ret = QLCRD32(adapter, indirect_add, &err); |
2481 | if (err == -EIO) | |
2482 | return err; | |
d865ebb4 SC |
2483 | |
2484 | word = ret; | |
2485 | *(u32 *)p_data = word; | |
2486 | p_data = p_data + 4; | |
2487 | addr = addr + 4; | |
2488 | } | |
2489 | } | |
2490 | ||
2491 | return 0; | |
2492 | } | |
2493 | ||
2494 | static int qlcnic_83xx_poll_flash_status_reg(struct qlcnic_adapter *adapter) | |
2495 | { | |
2496 | u32 status; | |
2497 | int retries = QLC_83XX_FLASH_READ_RETRY_COUNT; | |
4bd8e738 | 2498 | int err = 0; |
d865ebb4 SC |
2499 | |
2500 | do { | |
4bd8e738 HM |
2501 | status = QLCRD32(adapter, QLC_83XX_FLASH_STATUS, &err); |
2502 | if (err == -EIO) | |
2503 | return err; | |
2504 | ||
d865ebb4 SC |
2505 | if ((status & QLC_83XX_FLASH_STATUS_READY) == |
2506 | QLC_83XX_FLASH_STATUS_READY) | |
2507 | break; | |
2508 | ||
2509 | msleep(QLC_83XX_FLASH_STATUS_REG_POLL_DELAY); | |
2510 | } while (--retries); | |
2511 | ||
2512 | if (!retries) | |
2513 | return -EIO; | |
2514 | ||
2515 | return 0; | |
2516 | } | |
2517 | ||
a520030e | 2518 | int qlcnic_83xx_enable_flash_write(struct qlcnic_adapter *adapter) |
d865ebb4 SC |
2519 | { |
2520 | int ret; | |
2521 | u32 cmd; | |
2522 | cmd = adapter->ahw->fdt.write_statusreg_cmd; | |
2523 | qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, | |
2524 | (QLC_83XX_FLASH_FDT_WRITE_DEF_SIG | cmd)); | |
2525 | qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, | |
2526 | adapter->ahw->fdt.write_enable_bits); | |
2527 | qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL, | |
2528 | QLC_83XX_FLASH_SECOND_ERASE_MS_VAL); | |
2529 | ret = qlcnic_83xx_poll_flash_status_reg(adapter); | |
2530 | if (ret) | |
2531 | return -EIO; | |
2532 | ||
2533 | return 0; | |
2534 | } | |
2535 | ||
a520030e | 2536 | int qlcnic_83xx_disable_flash_write(struct qlcnic_adapter *adapter) |
d865ebb4 SC |
2537 | { |
2538 | int ret; | |
2539 | ||
2540 | qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, | |
2541 | (QLC_83XX_FLASH_FDT_WRITE_DEF_SIG | | |
2542 | adapter->ahw->fdt.write_statusreg_cmd)); | |
2543 | qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, | |
2544 | adapter->ahw->fdt.write_disable_bits); | |
2545 | qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL, | |
2546 | QLC_83XX_FLASH_SECOND_ERASE_MS_VAL); | |
2547 | ret = qlcnic_83xx_poll_flash_status_reg(adapter); | |
2548 | if (ret) | |
2549 | return -EIO; | |
2550 | ||
2551 | return 0; | |
2552 | } | |
2553 | ||
2554 | int qlcnic_83xx_read_flash_mfg_id(struct qlcnic_adapter *adapter) | |
2555 | { | |
4bd8e738 HM |
2556 | int ret, err = 0; |
2557 | u32 mfg_id; | |
d865ebb4 SC |
2558 | |
2559 | if (qlcnic_83xx_lock_flash(adapter)) | |
2560 | return -EIO; | |
2561 | ||
2562 | qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, | |
2563 | QLC_83XX_FLASH_FDT_READ_MFG_ID_VAL); | |
2564 | qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL, | |
2565 | QLC_83XX_FLASH_READ_CTRL); | |
2566 | ret = qlcnic_83xx_poll_flash_status_reg(adapter); | |
2567 | if (ret) { | |
2568 | qlcnic_83xx_unlock_flash(adapter); | |
2569 | return -EIO; | |
2570 | } | |
2571 | ||
4bd8e738 HM |
2572 | mfg_id = QLCRD32(adapter, QLC_83XX_FLASH_RDDATA, &err); |
2573 | if (err == -EIO) { | |
2574 | qlcnic_83xx_unlock_flash(adapter); | |
2575 | return err; | |
2576 | } | |
d865ebb4 SC |
2577 | |
2578 | adapter->flash_mfg_id = (mfg_id & 0xFF); | |
2579 | qlcnic_83xx_unlock_flash(adapter); | |
2580 | ||
2581 | return 0; | |
2582 | } | |
2583 | ||
2584 | int qlcnic_83xx_read_flash_descriptor_table(struct qlcnic_adapter *adapter) | |
2585 | { | |
2586 | int count, fdt_size, ret = 0; | |
2587 | ||
2588 | fdt_size = sizeof(struct qlcnic_fdt); | |
2589 | count = fdt_size / sizeof(u32); | |
2590 | ||
2591 | if (qlcnic_83xx_lock_flash(adapter)) | |
2592 | return -EIO; | |
2593 | ||
2594 | memset(&adapter->ahw->fdt, 0, fdt_size); | |
2595 | ret = qlcnic_83xx_lockless_flash_read32(adapter, QLCNIC_FDT_LOCATION, | |
2596 | (u8 *)&adapter->ahw->fdt, | |
2597 | count); | |
2598 | ||
2599 | qlcnic_83xx_unlock_flash(adapter); | |
2600 | return ret; | |
2601 | } | |
2602 | ||
2603 | int qlcnic_83xx_erase_flash_sector(struct qlcnic_adapter *adapter, | |
2604 | u32 sector_start_addr) | |
2605 | { | |
2606 | u32 reversed_addr, addr1, addr2, cmd; | |
2607 | int ret = -EIO; | |
2608 | ||
2609 | if (qlcnic_83xx_lock_flash(adapter) != 0) | |
2610 | return -EIO; | |
2611 | ||
2612 | if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id) { | |
a520030e | 2613 | ret = qlcnic_83xx_enable_flash_write(adapter); |
d865ebb4 SC |
2614 | if (ret) { |
2615 | qlcnic_83xx_unlock_flash(adapter); | |
2616 | dev_err(&adapter->pdev->dev, | |
2617 | "%s failed at %d\n", | |
2618 | __func__, __LINE__); | |
2619 | return ret; | |
2620 | } | |
2621 | } | |
2622 | ||
2623 | ret = qlcnic_83xx_poll_flash_status_reg(adapter); | |
2624 | if (ret) { | |
2625 | qlcnic_83xx_unlock_flash(adapter); | |
2626 | dev_err(&adapter->pdev->dev, | |
2627 | "%s: failed at %d\n", __func__, __LINE__); | |
2628 | return -EIO; | |
2629 | } | |
2630 | ||
2631 | addr1 = (sector_start_addr & 0xFF) << 16; | |
2632 | addr2 = (sector_start_addr & 0xFF0000) >> 16; | |
2633 | reversed_addr = addr1 | addr2; | |
2634 | ||
2635 | qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, | |
2636 | reversed_addr); | |
2637 | cmd = QLC_83XX_FLASH_FDT_ERASE_DEF_SIG | adapter->ahw->fdt.erase_cmd; | |
2638 | if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id) | |
2639 | qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, cmd); | |
2640 | else | |
2641 | qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, | |
2642 | QLC_83XX_FLASH_OEM_ERASE_SIG); | |
2643 | qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL, | |
2644 | QLC_83XX_FLASH_LAST_ERASE_MS_VAL); | |
2645 | ||
2646 | ret = qlcnic_83xx_poll_flash_status_reg(adapter); | |
2647 | if (ret) { | |
2648 | qlcnic_83xx_unlock_flash(adapter); | |
2649 | dev_err(&adapter->pdev->dev, | |
2650 | "%s: failed at %d\n", __func__, __LINE__); | |
2651 | return -EIO; | |
2652 | } | |
2653 | ||
2654 | if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id) { | |
a520030e | 2655 | ret = qlcnic_83xx_disable_flash_write(adapter); |
d865ebb4 SC |
2656 | if (ret) { |
2657 | qlcnic_83xx_unlock_flash(adapter); | |
2658 | dev_err(&adapter->pdev->dev, | |
2659 | "%s: failed at %d\n", __func__, __LINE__); | |
2660 | return ret; | |
2661 | } | |
2662 | } | |
2663 | ||
2664 | qlcnic_83xx_unlock_flash(adapter); | |
2665 | ||
2666 | return 0; | |
2667 | } | |
2668 | ||
2669 | int qlcnic_83xx_flash_write32(struct qlcnic_adapter *adapter, u32 addr, | |
2670 | u32 *p_data) | |
2671 | { | |
2672 | int ret = -EIO; | |
2673 | u32 addr1 = 0x00800000 | (addr >> 2); | |
2674 | ||
2675 | qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, addr1); | |
2676 | qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data); | |
2677 | qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL, | |
2678 | QLC_83XX_FLASH_LAST_ERASE_MS_VAL); | |
2679 | ret = qlcnic_83xx_poll_flash_status_reg(adapter); | |
2680 | if (ret) { | |
2681 | dev_err(&adapter->pdev->dev, | |
2682 | "%s: failed at %d\n", __func__, __LINE__); | |
2683 | return -EIO; | |
2684 | } | |
2685 | ||
2686 | return 0; | |
2687 | } | |
2688 | ||
2689 | int qlcnic_83xx_flash_bulk_write(struct qlcnic_adapter *adapter, u32 addr, | |
2690 | u32 *p_data, int count) | |
2691 | { | |
2692 | u32 temp; | |
4bd8e738 | 2693 | int ret = -EIO, err = 0; |
d865ebb4 | 2694 | |
a520030e HM |
2695 | if ((count < QLC_83XX_FLASH_WRITE_MIN) || |
2696 | (count > QLC_83XX_FLASH_WRITE_MAX)) { | |
d865ebb4 SC |
2697 | dev_err(&adapter->pdev->dev, |
2698 | "%s: Invalid word count\n", __func__); | |
2699 | return -EIO; | |
2700 | } | |
2701 | ||
4bd8e738 HM |
2702 | temp = QLCRD32(adapter, QLC_83XX_FLASH_SPI_CONTROL, &err); |
2703 | if (err == -EIO) | |
2704 | return err; | |
2705 | ||
d865ebb4 SC |
2706 | qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_SPI_CONTROL, |
2707 | (temp | QLC_83XX_FLASH_SPI_CTRL)); | |
2708 | qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, | |
2709 | QLC_83XX_FLASH_ADDR_TEMP_VAL); | |
2710 | ||
2711 | /* First DWORD write */ | |
2712 | qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data++); | |
2713 | qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL, | |
2714 | QLC_83XX_FLASH_FIRST_MS_PATTERN); | |
2715 | ret = qlcnic_83xx_poll_flash_status_reg(adapter); | |
2716 | if (ret) { | |
2717 | dev_err(&adapter->pdev->dev, | |
2718 | "%s: failed at %d\n", __func__, __LINE__); | |
2719 | return -EIO; | |
2720 | } | |
2721 | ||
2722 | count--; | |
2723 | qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, | |
2724 | QLC_83XX_FLASH_ADDR_SECOND_TEMP_VAL); | |
2725 | /* Second to N-1 DWORD writes */ | |
2726 | while (count != 1) { | |
2727 | qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, | |
2728 | *p_data++); | |
2729 | qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL, | |
2730 | QLC_83XX_FLASH_SECOND_MS_PATTERN); | |
2731 | ret = qlcnic_83xx_poll_flash_status_reg(adapter); | |
2732 | if (ret) { | |
2733 | dev_err(&adapter->pdev->dev, | |
2734 | "%s: failed at %d\n", __func__, __LINE__); | |
2735 | return -EIO; | |
2736 | } | |
2737 | count--; | |
2738 | } | |
2739 | ||
2740 | qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, | |
2741 | QLC_83XX_FLASH_ADDR_TEMP_VAL | | |
2742 | (addr >> 2)); | |
2743 | /* Last DWORD write */ | |
2744 | qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data++); | |
2745 | qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL, | |
2746 | QLC_83XX_FLASH_LAST_MS_PATTERN); | |
2747 | ret = qlcnic_83xx_poll_flash_status_reg(adapter); | |
2748 | if (ret) { | |
2749 | dev_err(&adapter->pdev->dev, | |
2750 | "%s: failed at %d\n", __func__, __LINE__); | |
2751 | return -EIO; | |
2752 | } | |
2753 | ||
4bd8e738 HM |
2754 | ret = QLCRD32(adapter, QLC_83XX_FLASH_SPI_STATUS, &err); |
2755 | if (err == -EIO) | |
2756 | return err; | |
2757 | ||
d865ebb4 SC |
2758 | if ((ret & QLC_83XX_FLASH_SPI_CTRL) == QLC_83XX_FLASH_SPI_CTRL) { |
2759 | dev_err(&adapter->pdev->dev, "%s: failed at %d\n", | |
2760 | __func__, __LINE__); | |
2761 | /* Operation failed, clear error bit */ | |
4bd8e738 HM |
2762 | temp = QLCRD32(adapter, QLC_83XX_FLASH_SPI_CONTROL, &err); |
2763 | if (err == -EIO) | |
2764 | return err; | |
2765 | ||
d865ebb4 SC |
2766 | qlcnic_83xx_wrt_reg_indirect(adapter, |
2767 | QLC_83XX_FLASH_SPI_CONTROL, | |
2768 | (temp | QLC_83XX_FLASH_SPI_CTRL)); | |
2769 | } | |
2770 | ||
2771 | return 0; | |
2772 | } | |
629263ac SC |
2773 | |
2774 | static void qlcnic_83xx_recover_driver_lock(struct qlcnic_adapter *adapter) | |
2775 | { | |
2776 | u32 val, id; | |
2777 | ||
2778 | val = QLCRDX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK); | |
2779 | ||
2780 | /* Check if recovery need to be performed by the calling function */ | |
2781 | if ((val & QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK) == 0) { | |
2782 | val = val & ~0x3F; | |
2783 | val = val | ((adapter->portnum << 2) | | |
2784 | QLC_83XX_NEED_DRV_LOCK_RECOVERY); | |
2785 | QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val); | |
2786 | dev_info(&adapter->pdev->dev, | |
2787 | "%s: lock recovery initiated\n", __func__); | |
2788 | msleep(QLC_83XX_DRV_LOCK_RECOVERY_DELAY); | |
2789 | val = QLCRDX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK); | |
2790 | id = ((val >> 2) & 0xF); | |
2791 | if (id == adapter->portnum) { | |
2792 | val = val & ~QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK; | |
2793 | val = val | QLC_83XX_DRV_LOCK_RECOVERY_IN_PROGRESS; | |
2794 | QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val); | |
2795 | /* Force release the lock */ | |
2796 | QLCRDX(adapter->ahw, QLC_83XX_DRV_UNLOCK); | |
2797 | /* Clear recovery bits */ | |
2798 | val = val & ~0x3F; | |
2799 | QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val); | |
2800 | dev_info(&adapter->pdev->dev, | |
2801 | "%s: lock recovery completed\n", __func__); | |
2802 | } else { | |
2803 | dev_info(&adapter->pdev->dev, | |
2804 | "%s: func %d to resume lock recovery process\n", | |
2805 | __func__, id); | |
2806 | } | |
2807 | } else { | |
2808 | dev_info(&adapter->pdev->dev, | |
2809 | "%s: lock recovery initiated by other functions\n", | |
2810 | __func__); | |
2811 | } | |
2812 | } | |
2813 | ||
2814 | int qlcnic_83xx_lock_driver(struct qlcnic_adapter *adapter) | |
2815 | { | |
2816 | u32 lock_alive_counter, val, id, i = 0, status = 0, temp = 0; | |
2817 | int max_attempt = 0; | |
2818 | ||
2819 | while (status == 0) { | |
2820 | status = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK); | |
2821 | if (status) | |
2822 | break; | |
2823 | ||
2824 | msleep(QLC_83XX_DRV_LOCK_WAIT_DELAY); | |
2825 | i++; | |
2826 | ||
2827 | if (i == 1) | |
2828 | temp = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID); | |
2829 | ||
2830 | if (i == QLC_83XX_DRV_LOCK_WAIT_COUNTER) { | |
2831 | val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID); | |
2832 | if (val == temp) { | |
2833 | id = val & 0xFF; | |
2834 | dev_info(&adapter->pdev->dev, | |
2835 | "%s: lock to be recovered from %d\n", | |
2836 | __func__, id); | |
2837 | qlcnic_83xx_recover_driver_lock(adapter); | |
2838 | i = 0; | |
2839 | max_attempt++; | |
2840 | } else { | |
2841 | dev_err(&adapter->pdev->dev, | |
2842 | "%s: failed to get lock\n", __func__); | |
2843 | return -EIO; | |
2844 | } | |
2845 | } | |
2846 | ||
2847 | /* Force exit from while loop after few attempts */ | |
2848 | if (max_attempt == QLC_83XX_MAX_DRV_LOCK_RECOVERY_ATTEMPT) { | |
2849 | dev_err(&adapter->pdev->dev, | |
2850 | "%s: failed to get lock\n", __func__); | |
2851 | return -EIO; | |
2852 | } | |
2853 | } | |
2854 | ||
2855 | val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID); | |
2856 | lock_alive_counter = val >> 8; | |
2857 | lock_alive_counter++; | |
2858 | val = lock_alive_counter << 8 | adapter->portnum; | |
2859 | QLCWRX(adapter->ahw, QLC_83XX_DRV_LOCK_ID, val); | |
2860 | ||
2861 | return 0; | |
2862 | } | |
2863 | ||
2864 | void qlcnic_83xx_unlock_driver(struct qlcnic_adapter *adapter) | |
2865 | { | |
2866 | u32 val, lock_alive_counter, id; | |
2867 | ||
2868 | val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID); | |
2869 | id = val & 0xFF; | |
2870 | lock_alive_counter = val >> 8; | |
2871 | ||
2872 | if (id != adapter->portnum) | |
2873 | dev_err(&adapter->pdev->dev, | |
2874 | "%s:Warning func %d is unlocking lock owned by %d\n", | |
2875 | __func__, adapter->portnum, id); | |
2876 | ||
2877 | val = (lock_alive_counter << 8) | 0xFF; | |
2878 | QLCWRX(adapter->ahw, QLC_83XX_DRV_LOCK_ID, val); | |
2879 | QLCRDX(adapter->ahw, QLC_83XX_DRV_UNLOCK); | |
2880 | } | |
2881 | ||
2882 | int qlcnic_83xx_ms_mem_write128(struct qlcnic_adapter *adapter, u64 addr, | |
2883 | u32 *data, u32 count) | |
2884 | { | |
2885 | int i, j, ret = 0; | |
2886 | u32 temp; | |
4bd8e738 | 2887 | int err = 0; |
629263ac SC |
2888 | |
2889 | /* Check alignment */ | |
2890 | if (addr & 0xF) | |
2891 | return -EIO; | |
2892 | ||
2893 | mutex_lock(&adapter->ahw->mem_lock); | |
2894 | qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_ADDR_HI, 0); | |
2895 | ||
2896 | for (i = 0; i < count; i++, addr += 16) { | |
2897 | if (!((ADDR_IN_RANGE(addr, QLCNIC_ADDR_QDR_NET, | |
2898 | QLCNIC_ADDR_QDR_NET_MAX)) || | |
2899 | (ADDR_IN_RANGE(addr, QLCNIC_ADDR_DDR_NET, | |
2900 | QLCNIC_ADDR_DDR_NET_MAX)))) { | |
2901 | mutex_unlock(&adapter->ahw->mem_lock); | |
2902 | return -EIO; | |
2903 | } | |
2904 | ||
2905 | qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_ADDR_LO, addr); | |
2906 | qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_LO, | |
2907 | *data++); | |
2908 | qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_HI, | |
2909 | *data++); | |
2910 | qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_ULO, | |
2911 | *data++); | |
2912 | qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_UHI, | |
2913 | *data++); | |
2914 | qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_CTRL, | |
2915 | QLCNIC_TA_WRITE_ENABLE); | |
2916 | qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_CTRL, | |
2917 | QLCNIC_TA_WRITE_START); | |
2918 | ||
2919 | for (j = 0; j < MAX_CTL_CHECK; j++) { | |
4bd8e738 HM |
2920 | temp = QLCRD32(adapter, QLCNIC_MS_CTRL, &err); |
2921 | if (err == -EIO) { | |
2922 | mutex_unlock(&adapter->ahw->mem_lock); | |
2923 | return err; | |
2924 | } | |
2925 | ||
629263ac SC |
2926 | if ((temp & TA_CTL_BUSY) == 0) |
2927 | break; | |
2928 | } | |
2929 | ||
2930 | /* Status check failure */ | |
2931 | if (j >= MAX_CTL_CHECK) { | |
2932 | printk_ratelimited(KERN_WARNING | |
2933 | "MS memory write failed\n"); | |
2934 | mutex_unlock(&adapter->ahw->mem_lock); | |
2935 | return -EIO; | |
2936 | } | |
2937 | } | |
2938 | ||
2939 | mutex_unlock(&adapter->ahw->mem_lock); | |
2940 | ||
2941 | return ret; | |
2942 | } | |
81d0aeb0 SC |
2943 | |
2944 | int qlcnic_83xx_flash_read32(struct qlcnic_adapter *adapter, u32 flash_addr, | |
2945 | u8 *p_data, int count) | |
2946 | { | |
4bd8e738 | 2947 | u32 word, addr = flash_addr, ret; |
81d0aeb0 | 2948 | ulong indirect_addr; |
4bd8e738 | 2949 | int i, err = 0; |
81d0aeb0 SC |
2950 | |
2951 | if (qlcnic_83xx_lock_flash(adapter) != 0) | |
2952 | return -EIO; | |
2953 | ||
2954 | if (addr & 0x3) { | |
2955 | dev_err(&adapter->pdev->dev, "Illegal addr = 0x%x\n", addr); | |
2956 | qlcnic_83xx_unlock_flash(adapter); | |
2957 | return -EIO; | |
2958 | } | |
2959 | ||
2960 | for (i = 0; i < count; i++) { | |
2961 | if (qlcnic_83xx_wrt_reg_indirect(adapter, | |
2962 | QLC_83XX_FLASH_DIRECT_WINDOW, | |
2963 | (addr))) { | |
2964 | qlcnic_83xx_unlock_flash(adapter); | |
2965 | return -EIO; | |
2966 | } | |
2967 | ||
2968 | indirect_addr = QLC_83XX_FLASH_DIRECT_DATA(addr); | |
4bd8e738 HM |
2969 | ret = QLCRD32(adapter, indirect_addr, &err); |
2970 | if (err == -EIO) | |
2971 | return err; | |
2972 | ||
81d0aeb0 | 2973 | word = ret; |
1403f43a | 2974 | *(u32 *)p_data = word; |
81d0aeb0 SC |
2975 | p_data = p_data + 4; |
2976 | addr = addr + 4; | |
2977 | } | |
2978 | ||
2979 | qlcnic_83xx_unlock_flash(adapter); | |
2980 | ||
2981 | return 0; | |
2982 | } | |
7e38d04b SC |
2983 | |
2984 | int qlcnic_83xx_test_link(struct qlcnic_adapter *adapter) | |
2985 | { | |
7cb03b23 | 2986 | u8 pci_func; |
7e38d04b SC |
2987 | int err; |
2988 | u32 config = 0, state; | |
2989 | struct qlcnic_cmd_args cmd; | |
2990 | struct qlcnic_hardware_context *ahw = adapter->ahw; | |
2991 | ||
7cb03b23 RB |
2992 | if (qlcnic_sriov_vf_check(adapter)) |
2993 | pci_func = adapter->portnum; | |
2994 | else | |
2995 | pci_func = ahw->pci_func; | |
2996 | ||
2997 | state = readl(ahw->pci_base0 + QLC_83XX_LINK_STATE(pci_func)); | |
2998 | if (!QLC_83xx_FUNC_VAL(state, pci_func)) { | |
7e38d04b SC |
2999 | dev_info(&adapter->pdev->dev, "link state down\n"); |
3000 | return config; | |
3001 | } | |
b6b4316c SS |
3002 | |
3003 | err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LINK_STATUS); | |
3004 | if (err) | |
3005 | return err; | |
3006 | ||
7e38d04b SC |
3007 | err = qlcnic_issue_cmd(adapter, &cmd); |
3008 | if (err) { | |
3009 | dev_info(&adapter->pdev->dev, | |
3010 | "Get Link Status Command failed: 0x%x\n", err); | |
3011 | goto out; | |
3012 | } else { | |
3013 | config = cmd.rsp.arg[1]; | |
3014 | switch (QLC_83XX_CURRENT_LINK_SPEED(config)) { | |
3015 | case QLC_83XX_10M_LINK: | |
3016 | ahw->link_speed = SPEED_10; | |
3017 | break; | |
3018 | case QLC_83XX_100M_LINK: | |
3019 | ahw->link_speed = SPEED_100; | |
3020 | break; | |
3021 | case QLC_83XX_1G_LINK: | |
3022 | ahw->link_speed = SPEED_1000; | |
3023 | break; | |
3024 | case QLC_83XX_10G_LINK: | |
3025 | ahw->link_speed = SPEED_10000; | |
3026 | break; | |
3027 | default: | |
3028 | ahw->link_speed = 0; | |
3029 | break; | |
3030 | } | |
3031 | config = cmd.rsp.arg[3]; | |
b938662d HM |
3032 | if (QLC_83XX_SFP_PRESENT(config)) { |
3033 | switch (ahw->module_type) { | |
3034 | case LINKEVENT_MODULE_OPTICAL_UNKNOWN: | |
3035 | case LINKEVENT_MODULE_OPTICAL_SRLR: | |
3036 | case LINKEVENT_MODULE_OPTICAL_LRM: | |
3037 | case LINKEVENT_MODULE_OPTICAL_SFP_1G: | |
3038 | ahw->supported_type = PORT_FIBRE; | |
3039 | break; | |
3040 | case LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE: | |
3041 | case LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN: | |
3042 | case LINKEVENT_MODULE_TWINAX: | |
3043 | ahw->supported_type = PORT_TP; | |
3044 | break; | |
3045 | default: | |
3046 | ahw->supported_type = PORT_OTHER; | |
3047 | } | |
3048 | } | |
7e38d04b SC |
3049 | if (config & 1) |
3050 | err = 1; | |
3051 | } | |
3052 | out: | |
3053 | qlcnic_free_mbx_args(&cmd); | |
3054 | return config; | |
3055 | } | |
3056 | ||
b938662d HM |
3057 | int qlcnic_83xx_get_settings(struct qlcnic_adapter *adapter, |
3058 | struct ethtool_cmd *ecmd) | |
7e38d04b SC |
3059 | { |
3060 | u32 config = 0; | |
3061 | int status = 0; | |
3062 | struct qlcnic_hardware_context *ahw = adapter->ahw; | |
3063 | ||
3064 | /* Get port configuration info */ | |
3065 | status = qlcnic_83xx_get_port_info(adapter); | |
3066 | /* Get Link Status related info */ | |
3067 | config = qlcnic_83xx_test_link(adapter); | |
3068 | ahw->module_type = QLC_83XX_SFP_MODULE_TYPE(config); | |
3069 | /* hard code until there is a way to get it from flash */ | |
3070 | ahw->board_type = QLCNIC_BRDTYPE_83XX_10G; | |
b938662d HM |
3071 | |
3072 | if (netif_running(adapter->netdev) && ahw->has_link_events) { | |
3073 | ethtool_cmd_speed_set(ecmd, ahw->link_speed); | |
3074 | ecmd->duplex = ahw->link_duplex; | |
3075 | ecmd->autoneg = ahw->link_autoneg; | |
3076 | } else { | |
3077 | ethtool_cmd_speed_set(ecmd, SPEED_UNKNOWN); | |
3078 | ecmd->duplex = DUPLEX_UNKNOWN; | |
3079 | ecmd->autoneg = AUTONEG_DISABLE; | |
3080 | } | |
3081 | ||
3082 | if (ahw->port_type == QLCNIC_XGBE) { | |
15d79747 HM |
3083 | ecmd->supported = SUPPORTED_10000baseT_Full; |
3084 | ecmd->advertising = ADVERTISED_10000baseT_Full; | |
b938662d HM |
3085 | } else { |
3086 | ecmd->supported = (SUPPORTED_10baseT_Half | | |
3087 | SUPPORTED_10baseT_Full | | |
3088 | SUPPORTED_100baseT_Half | | |
3089 | SUPPORTED_100baseT_Full | | |
3090 | SUPPORTED_1000baseT_Half | | |
3091 | SUPPORTED_1000baseT_Full); | |
3092 | ecmd->advertising = (ADVERTISED_100baseT_Half | | |
3093 | ADVERTISED_100baseT_Full | | |
3094 | ADVERTISED_1000baseT_Half | | |
3095 | ADVERTISED_1000baseT_Full); | |
3096 | } | |
3097 | ||
3098 | switch (ahw->supported_type) { | |
3099 | case PORT_FIBRE: | |
3100 | ecmd->supported |= SUPPORTED_FIBRE; | |
3101 | ecmd->advertising |= ADVERTISED_FIBRE; | |
3102 | ecmd->port = PORT_FIBRE; | |
3103 | ecmd->transceiver = XCVR_EXTERNAL; | |
3104 | break; | |
3105 | case PORT_TP: | |
3106 | ecmd->supported |= SUPPORTED_TP; | |
3107 | ecmd->advertising |= ADVERTISED_TP; | |
3108 | ecmd->port = PORT_TP; | |
3109 | ecmd->transceiver = XCVR_INTERNAL; | |
3110 | break; | |
3111 | default: | |
3112 | ecmd->supported |= SUPPORTED_FIBRE; | |
3113 | ecmd->advertising |= ADVERTISED_FIBRE; | |
3114 | ecmd->port = PORT_OTHER; | |
3115 | ecmd->transceiver = XCVR_EXTERNAL; | |
3116 | break; | |
3117 | } | |
3118 | ecmd->phy_address = ahw->physical_port; | |
7e38d04b SC |
3119 | return status; |
3120 | } | |
3121 | ||
3122 | int qlcnic_83xx_set_settings(struct qlcnic_adapter *adapter, | |
3123 | struct ethtool_cmd *ecmd) | |
3124 | { | |
3125 | int status = 0; | |
3126 | u32 config = adapter->ahw->port_config; | |
3127 | ||
3128 | if (ecmd->autoneg) | |
3129 | adapter->ahw->port_config |= BIT_15; | |
3130 | ||
3131 | switch (ethtool_cmd_speed(ecmd)) { | |
3132 | case SPEED_10: | |
3133 | adapter->ahw->port_config |= BIT_8; | |
3134 | break; | |
3135 | case SPEED_100: | |
3136 | adapter->ahw->port_config |= BIT_9; | |
3137 | break; | |
3138 | case SPEED_1000: | |
3139 | adapter->ahw->port_config |= BIT_10; | |
3140 | break; | |
3141 | case SPEED_10000: | |
3142 | adapter->ahw->port_config |= BIT_11; | |
3143 | break; | |
3144 | default: | |
3145 | return -EINVAL; | |
3146 | } | |
3147 | ||
3148 | status = qlcnic_83xx_set_port_config(adapter); | |
3149 | if (status) { | |
3150 | dev_info(&adapter->pdev->dev, | |
0b1587b1 | 3151 | "Failed to Set Link Speed and autoneg.\n"); |
7e38d04b SC |
3152 | adapter->ahw->port_config = config; |
3153 | } | |
3154 | return status; | |
3155 | } | |
3156 | ||
3157 | static inline u64 *qlcnic_83xx_copy_stats(struct qlcnic_cmd_args *cmd, | |
3158 | u64 *data, int index) | |
3159 | { | |
3160 | u32 low, hi; | |
3161 | u64 val; | |
3162 | ||
3163 | low = cmd->rsp.arg[index]; | |
3164 | hi = cmd->rsp.arg[index + 1]; | |
3165 | val = (((u64) low) | (((u64) hi) << 32)); | |
3166 | *data++ = val; | |
3167 | return data; | |
3168 | } | |
3169 | ||
3170 | static u64 *qlcnic_83xx_fill_stats(struct qlcnic_adapter *adapter, | |
3171 | struct qlcnic_cmd_args *cmd, u64 *data, | |
3172 | int type, int *ret) | |
3173 | { | |
3174 | int err, k, total_regs; | |
3175 | ||
3176 | *ret = 0; | |
3177 | err = qlcnic_issue_cmd(adapter, cmd); | |
3178 | if (err != QLCNIC_RCODE_SUCCESS) { | |
3179 | dev_info(&adapter->pdev->dev, | |
3180 | "Error in get statistics mailbox command\n"); | |
3181 | *ret = -EIO; | |
3182 | return data; | |
3183 | } | |
3184 | total_regs = cmd->rsp.num; | |
3185 | switch (type) { | |
3186 | case QLC_83XX_STAT_MAC: | |
3187 | /* fill in MAC tx counters */ | |
3188 | for (k = 2; k < 28; k += 2) | |
3189 | data = qlcnic_83xx_copy_stats(cmd, data, k); | |
3190 | /* skip 24 bytes of reserved area */ | |
3191 | /* fill in MAC rx counters */ | |
3192 | for (k += 6; k < 60; k += 2) | |
3193 | data = qlcnic_83xx_copy_stats(cmd, data, k); | |
3194 | /* skip 24 bytes of reserved area */ | |
3195 | /* fill in MAC rx frame stats */ | |
3196 | for (k += 6; k < 80; k += 2) | |
3197 | data = qlcnic_83xx_copy_stats(cmd, data, k); | |
52290740 SS |
3198 | /* fill in eSwitch stats */ |
3199 | for (; k < total_regs; k += 2) | |
3200 | data = qlcnic_83xx_copy_stats(cmd, data, k); | |
7e38d04b SC |
3201 | break; |
3202 | case QLC_83XX_STAT_RX: | |
3203 | for (k = 2; k < 8; k += 2) | |
3204 | data = qlcnic_83xx_copy_stats(cmd, data, k); | |
3205 | /* skip 8 bytes of reserved data */ | |
3206 | for (k += 2; k < 24; k += 2) | |
3207 | data = qlcnic_83xx_copy_stats(cmd, data, k); | |
3208 | /* skip 8 bytes containing RE1FBQ error data */ | |
3209 | for (k += 2; k < total_regs; k += 2) | |
3210 | data = qlcnic_83xx_copy_stats(cmd, data, k); | |
3211 | break; | |
3212 | case QLC_83XX_STAT_TX: | |
3213 | for (k = 2; k < 10; k += 2) | |
3214 | data = qlcnic_83xx_copy_stats(cmd, data, k); | |
3215 | /* skip 8 bytes of reserved data */ | |
3216 | for (k += 2; k < total_regs; k += 2) | |
3217 | data = qlcnic_83xx_copy_stats(cmd, data, k); | |
3218 | break; | |
3219 | default: | |
3220 | dev_warn(&adapter->pdev->dev, "Unknown get statistics mode\n"); | |
3221 | *ret = -EIO; | |
3222 | } | |
3223 | return data; | |
3224 | } | |
3225 | ||
3226 | void qlcnic_83xx_get_stats(struct qlcnic_adapter *adapter, u64 *data) | |
3227 | { | |
3228 | struct qlcnic_cmd_args cmd; | |
7bc27a8c | 3229 | struct net_device *netdev = adapter->netdev; |
7e38d04b SC |
3230 | int ret = 0; |
3231 | ||
b6b4316c SS |
3232 | ret = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_STATISTICS); |
3233 | if (ret) | |
3234 | return; | |
7e38d04b SC |
3235 | /* Get Tx stats */ |
3236 | cmd.req.arg[1] = BIT_1 | (adapter->tx_ring->ctx_id << 16); | |
3237 | cmd.rsp.num = QLC_83XX_TX_STAT_REGS; | |
3238 | data = qlcnic_83xx_fill_stats(adapter, &cmd, data, | |
3239 | QLC_83XX_STAT_TX, &ret); | |
3240 | if (ret) { | |
7bc27a8c | 3241 | netdev_err(netdev, "Error getting Tx stats\n"); |
7e38d04b SC |
3242 | goto out; |
3243 | } | |
3244 | /* Get MAC stats */ | |
3245 | cmd.req.arg[1] = BIT_2 | (adapter->portnum << 16); | |
3246 | cmd.rsp.num = QLC_83XX_MAC_STAT_REGS; | |
3247 | memset(cmd.rsp.arg, 0, sizeof(u32) * cmd.rsp.num); | |
3248 | data = qlcnic_83xx_fill_stats(adapter, &cmd, data, | |
3249 | QLC_83XX_STAT_MAC, &ret); | |
3250 | if (ret) { | |
7bc27a8c | 3251 | netdev_err(netdev, "Error getting MAC stats\n"); |
7e38d04b SC |
3252 | goto out; |
3253 | } | |
3254 | /* Get Rx stats */ | |
3255 | cmd.req.arg[1] = adapter->recv_ctx->context_id << 16; | |
3256 | cmd.rsp.num = QLC_83XX_RX_STAT_REGS; | |
3257 | memset(cmd.rsp.arg, 0, sizeof(u32) * cmd.rsp.num); | |
3258 | data = qlcnic_83xx_fill_stats(adapter, &cmd, data, | |
3259 | QLC_83XX_STAT_RX, &ret); | |
3260 | if (ret) | |
7bc27a8c | 3261 | netdev_err(netdev, "Error getting Rx stats\n"); |
7e38d04b SC |
3262 | out: |
3263 | qlcnic_free_mbx_args(&cmd); | |
3264 | } | |
3265 | ||
3266 | int qlcnic_83xx_reg_test(struct qlcnic_adapter *adapter) | |
3267 | { | |
3268 | u32 major, minor, sub; | |
3269 | ||
3270 | major = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MAJOR); | |
3271 | minor = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MINOR); | |
3272 | sub = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_SUB); | |
3273 | ||
3274 | if (adapter->fw_version != QLCNIC_VERSION_CODE(major, minor, sub)) { | |
3275 | dev_info(&adapter->pdev->dev, "%s: Reg test failed\n", | |
3276 | __func__); | |
3277 | return 1; | |
3278 | } | |
3279 | return 0; | |
3280 | } | |
3281 | ||
3282 | int qlcnic_83xx_get_regs_len(struct qlcnic_adapter *adapter) | |
3283 | { | |
3284 | return (ARRAY_SIZE(qlcnic_83xx_ext_reg_tbl) * | |
3285 | sizeof(adapter->ahw->ext_reg_tbl)) + | |
3286 | (ARRAY_SIZE(qlcnic_83xx_reg_tbl) + | |
3287 | sizeof(adapter->ahw->reg_tbl)); | |
3288 | } | |
3289 | ||
3290 | int qlcnic_83xx_get_registers(struct qlcnic_adapter *adapter, u32 *regs_buff) | |
3291 | { | |
3292 | int i, j = 0; | |
3293 | ||
3294 | for (i = QLCNIC_DEV_INFO_SIZE + 1; | |
3295 | j < ARRAY_SIZE(qlcnic_83xx_reg_tbl); i++, j++) | |
3296 | regs_buff[i] = QLC_SHARED_REG_RD32(adapter, j); | |
3297 | ||
3298 | for (j = 0; j < ARRAY_SIZE(qlcnic_83xx_ext_reg_tbl); j++) | |
3299 | regs_buff[i++] = QLCRDX(adapter->ahw, j); | |
3300 | return i; | |
3301 | } | |
3302 | ||
58ead415 | 3303 | int qlcnic_83xx_interrupt_test(struct net_device *netdev) |
7e38d04b | 3304 | { |
58ead415 JK |
3305 | struct qlcnic_adapter *adapter = netdev_priv(netdev); |
3306 | struct qlcnic_hardware_context *ahw = adapter->ahw; | |
3307 | struct qlcnic_cmd_args cmd; | |
7e38d04b SC |
3308 | u32 data; |
3309 | u16 intrpt_id, id; | |
58ead415 JK |
3310 | u8 val; |
3311 | int ret, max_sds_rings = adapter->max_sds_rings; | |
3312 | ||
d1fcc172 MC |
3313 | if (test_bit(__QLCNIC_RESETTING, &adapter->state)) { |
3314 | netdev_info(netdev, "Device is resetting\n"); | |
3315 | return -EBUSY; | |
3316 | } | |
3317 | ||
4690a7e4 SC |
3318 | if (qlcnic_get_diag_lock(adapter)) { |
3319 | netdev_info(netdev, "Device in diagnostics mode\n"); | |
3320 | return -EBUSY; | |
3321 | } | |
58ead415 | 3322 | |
13a82b44 MC |
3323 | ret = qlcnic_83xx_diag_alloc_res(netdev, QLCNIC_INTERRUPT_TEST, |
3324 | max_sds_rings); | |
58ead415 JK |
3325 | if (ret) |
3326 | goto fail_diag_irq; | |
3327 | ||
3328 | ahw->diag_cnt = 0; | |
b6b4316c SS |
3329 | ret = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_INTRPT_TEST); |
3330 | if (ret) | |
3331 | goto fail_diag_irq; | |
7e38d04b SC |
3332 | |
3333 | if (adapter->flags & QLCNIC_MSIX_ENABLED) | |
58ead415 | 3334 | intrpt_id = ahw->intr_tbl[0].id; |
7e38d04b | 3335 | else |
58ead415 | 3336 | intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID); |
7e38d04b | 3337 | |
58ead415 JK |
3338 | cmd.req.arg[1] = 1; |
3339 | cmd.req.arg[2] = intrpt_id; | |
3340 | cmd.req.arg[3] = BIT_0; | |
7e38d04b | 3341 | |
58ead415 JK |
3342 | ret = qlcnic_issue_cmd(adapter, &cmd); |
3343 | data = cmd.rsp.arg[2]; | |
7e38d04b SC |
3344 | id = LSW(data); |
3345 | val = LSB(MSW(data)); | |
3346 | if (id != intrpt_id) | |
3347 | dev_info(&adapter->pdev->dev, | |
3348 | "Interrupt generated: 0x%x, requested:0x%x\n", | |
3349 | id, intrpt_id); | |
3350 | if (val) | |
58ead415 | 3351 | dev_err(&adapter->pdev->dev, |
7e38d04b | 3352 | "Interrupt test error: 0x%x\n", val); |
58ead415 JK |
3353 | if (ret) |
3354 | goto done; | |
3355 | ||
3356 | msleep(20); | |
3357 | ret = !ahw->diag_cnt; | |
7e38d04b | 3358 | |
58ead415 JK |
3359 | done: |
3360 | qlcnic_free_mbx_args(&cmd); | |
3361 | qlcnic_83xx_diag_free_res(netdev, max_sds_rings); | |
3362 | ||
3363 | fail_diag_irq: | |
3364 | adapter->max_sds_rings = max_sds_rings; | |
4690a7e4 | 3365 | qlcnic_release_diag_lock(adapter); |
7e38d04b SC |
3366 | return ret; |
3367 | } | |
3368 | ||
3369 | void qlcnic_83xx_get_pauseparam(struct qlcnic_adapter *adapter, | |
3370 | struct ethtool_pauseparam *pause) | |
3371 | { | |
3372 | struct qlcnic_hardware_context *ahw = adapter->ahw; | |
3373 | int status = 0; | |
3374 | u32 config; | |
3375 | ||
3376 | status = qlcnic_83xx_get_port_config(adapter); | |
3377 | if (status) { | |
3378 | dev_err(&adapter->pdev->dev, | |
3379 | "%s: Get Pause Config failed\n", __func__); | |
3380 | return; | |
3381 | } | |
3382 | config = ahw->port_config; | |
3383 | if (config & QLC_83XX_CFG_STD_PAUSE) { | |
3384 | if (config & QLC_83XX_CFG_STD_TX_PAUSE) | |
3385 | pause->tx_pause = 1; | |
3386 | if (config & QLC_83XX_CFG_STD_RX_PAUSE) | |
3387 | pause->rx_pause = 1; | |
3388 | } | |
3389 | ||
3390 | if (QLC_83XX_AUTONEG(config)) | |
3391 | pause->autoneg = 1; | |
3392 | } | |
3393 | ||
3394 | int qlcnic_83xx_set_pauseparam(struct qlcnic_adapter *adapter, | |
3395 | struct ethtool_pauseparam *pause) | |
3396 | { | |
3397 | struct qlcnic_hardware_context *ahw = adapter->ahw; | |
3398 | int status = 0; | |
3399 | u32 config; | |
3400 | ||
3401 | status = qlcnic_83xx_get_port_config(adapter); | |
3402 | if (status) { | |
3403 | dev_err(&adapter->pdev->dev, | |
3404 | "%s: Get Pause Config failed.\n", __func__); | |
3405 | return status; | |
3406 | } | |
3407 | config = ahw->port_config; | |
3408 | ||
3409 | if (ahw->port_type == QLCNIC_GBE) { | |
3410 | if (pause->autoneg) | |
3411 | ahw->port_config |= QLC_83XX_ENABLE_AUTONEG; | |
3412 | if (!pause->autoneg) | |
3413 | ahw->port_config &= ~QLC_83XX_ENABLE_AUTONEG; | |
3414 | } else if ((ahw->port_type == QLCNIC_XGBE) && (pause->autoneg)) { | |
3415 | return -EOPNOTSUPP; | |
3416 | } | |
3417 | ||
3418 | if (!(config & QLC_83XX_CFG_STD_PAUSE)) | |
3419 | ahw->port_config |= QLC_83XX_CFG_STD_PAUSE; | |
3420 | ||
3421 | if (pause->rx_pause && pause->tx_pause) { | |
3422 | ahw->port_config |= QLC_83XX_CFG_STD_TX_RX_PAUSE; | |
3423 | } else if (pause->rx_pause && !pause->tx_pause) { | |
3424 | ahw->port_config &= ~QLC_83XX_CFG_STD_TX_PAUSE; | |
3425 | ahw->port_config |= QLC_83XX_CFG_STD_RX_PAUSE; | |
3426 | } else if (pause->tx_pause && !pause->rx_pause) { | |
3427 | ahw->port_config &= ~QLC_83XX_CFG_STD_RX_PAUSE; | |
3428 | ahw->port_config |= QLC_83XX_CFG_STD_TX_PAUSE; | |
3429 | } else if (!pause->rx_pause && !pause->tx_pause) { | |
3430 | ahw->port_config &= ~QLC_83XX_CFG_STD_TX_RX_PAUSE; | |
3431 | } | |
3432 | status = qlcnic_83xx_set_port_config(adapter); | |
3433 | if (status) { | |
3434 | dev_err(&adapter->pdev->dev, | |
3435 | "%s: Set Pause Config failed.\n", __func__); | |
3436 | ahw->port_config = config; | |
3437 | } | |
3438 | return status; | |
3439 | } | |
3440 | ||
3441 | static int qlcnic_83xx_read_flash_status_reg(struct qlcnic_adapter *adapter) | |
3442 | { | |
4bd8e738 HM |
3443 | int ret, err = 0; |
3444 | u32 temp; | |
7e38d04b SC |
3445 | |
3446 | qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, | |
3447 | QLC_83XX_FLASH_OEM_READ_SIG); | |
3448 | qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL, | |
3449 | QLC_83XX_FLASH_READ_CTRL); | |
3450 | ret = qlcnic_83xx_poll_flash_status_reg(adapter); | |
3451 | if (ret) | |
3452 | return -EIO; | |
3453 | ||
4bd8e738 HM |
3454 | temp = QLCRD32(adapter, QLC_83XX_FLASH_RDDATA, &err); |
3455 | if (err == -EIO) | |
3456 | return err; | |
3457 | ||
3458 | return temp & 0xFF; | |
7e38d04b SC |
3459 | } |
3460 | ||
3461 | int qlcnic_83xx_flash_test(struct qlcnic_adapter *adapter) | |
3462 | { | |
3463 | int status; | |
3464 | ||
3465 | status = qlcnic_83xx_read_flash_status_reg(adapter); | |
3466 | if (status == -EIO) { | |
3467 | dev_info(&adapter->pdev->dev, "%s: EEPROM test failed.\n", | |
3468 | __func__); | |
3469 | return 1; | |
3470 | } | |
3471 | return 0; | |
3472 | } | |
486a5bc7 RB |
3473 | |
3474 | int qlcnic_83xx_shutdown(struct pci_dev *pdev) | |
3475 | { | |
3476 | struct qlcnic_adapter *adapter = pci_get_drvdata(pdev); | |
3477 | struct net_device *netdev = adapter->netdev; | |
3478 | int retval; | |
3479 | ||
3480 | netif_device_detach(netdev); | |
3481 | qlcnic_cancel_idc_work(adapter); | |
3482 | ||
3483 | if (netif_running(netdev)) | |
3484 | qlcnic_down(adapter, netdev); | |
3485 | ||
3486 | qlcnic_83xx_disable_mbx_intr(adapter); | |
3487 | cancel_delayed_work_sync(&adapter->idc_aen_work); | |
3488 | ||
3489 | retval = pci_save_state(pdev); | |
3490 | if (retval) | |
3491 | return retval; | |
3492 | ||
3493 | return 0; | |
3494 | } | |
3495 | ||
3496 | int qlcnic_83xx_resume(struct qlcnic_adapter *adapter) | |
3497 | { | |
3498 | struct qlcnic_hardware_context *ahw = adapter->ahw; | |
3499 | struct qlc_83xx_idc *idc = &ahw->idc; | |
3500 | int err = 0; | |
3501 | ||
3502 | err = qlcnic_83xx_idc_init(adapter); | |
3503 | if (err) | |
3504 | return err; | |
3505 | ||
3506 | if (ahw->nic_mode == QLC_83XX_VIRTUAL_NIC_MODE) { | |
3507 | if (ahw->op_mode == QLCNIC_MGMT_FUNC) { | |
3508 | qlcnic_83xx_set_vnic_opmode(adapter); | |
3509 | } else { | |
3510 | err = qlcnic_83xx_check_vnic_state(adapter); | |
3511 | if (err) | |
3512 | return err; | |
3513 | } | |
3514 | } | |
3515 | ||
3516 | err = qlcnic_83xx_idc_reattach_driver(adapter); | |
3517 | if (err) | |
3518 | return err; | |
3519 | ||
3520 | qlcnic_schedule_work(adapter, qlcnic_83xx_idc_poll_dev_state, | |
3521 | idc->delay); | |
3522 | return err; | |
3523 | } | |
e5c4e6c6 MC |
3524 | |
3525 | void qlcnic_83xx_reinit_mbx_work(struct qlcnic_mailbox *mbx) | |
3526 | { | |
3527 | INIT_COMPLETION(mbx->completion); | |
3528 | set_bit(QLC_83XX_MBX_READY, &mbx->status); | |
3529 | } | |
3530 | ||
3531 | void qlcnic_83xx_free_mailbox(struct qlcnic_mailbox *mbx) | |
3532 | { | |
3533 | destroy_workqueue(mbx->work_q); | |
3534 | kfree(mbx); | |
3535 | } | |
3536 | ||
3537 | static inline void | |
3538 | qlcnic_83xx_notify_cmd_completion(struct qlcnic_adapter *adapter, | |
3539 | struct qlcnic_cmd_args *cmd) | |
3540 | { | |
3541 | atomic_set(&cmd->rsp_status, QLC_83XX_MBX_RESPONSE_ARRIVED); | |
3542 | ||
3543 | if (cmd->type == QLC_83XX_MBX_CMD_NO_WAIT) { | |
3544 | qlcnic_free_mbx_args(cmd); | |
3545 | kfree(cmd); | |
3546 | return; | |
3547 | } | |
3548 | complete(&cmd->completion); | |
3549 | } | |
3550 | ||
60dcbcb0 | 3551 | static void qlcnic_83xx_flush_mbx_queue(struct qlcnic_adapter *adapter) |
e5c4e6c6 MC |
3552 | { |
3553 | struct qlcnic_mailbox *mbx = adapter->ahw->mailbox; | |
3554 | struct list_head *head = &mbx->cmd_q; | |
3555 | struct qlcnic_cmd_args *cmd = NULL; | |
3556 | ||
3557 | spin_lock(&mbx->queue_lock); | |
3558 | ||
3559 | while (!list_empty(head)) { | |
3560 | cmd = list_entry(head->next, struct qlcnic_cmd_args, list); | |
35570cfe MC |
3561 | dev_info(&adapter->pdev->dev, "%s: Mailbox command 0x%x\n", |
3562 | __func__, cmd->cmd_op); | |
e5c4e6c6 MC |
3563 | list_del(&cmd->list); |
3564 | mbx->num_cmds--; | |
3565 | qlcnic_83xx_notify_cmd_completion(adapter, cmd); | |
3566 | } | |
3567 | ||
3568 | spin_unlock(&mbx->queue_lock); | |
3569 | } | |
3570 | ||
60dcbcb0 | 3571 | static int qlcnic_83xx_check_mbx_status(struct qlcnic_adapter *adapter) |
e5c4e6c6 MC |
3572 | { |
3573 | struct qlcnic_hardware_context *ahw = adapter->ahw; | |
3574 | struct qlcnic_mailbox *mbx = ahw->mailbox; | |
3575 | u32 host_mbx_ctrl; | |
3576 | ||
3577 | if (!test_bit(QLC_83XX_MBX_READY, &mbx->status)) | |
3578 | return -EBUSY; | |
3579 | ||
3580 | host_mbx_ctrl = QLCRDX(ahw, QLCNIC_HOST_MBX_CTRL); | |
3581 | if (host_mbx_ctrl) { | |
35570cfe | 3582 | clear_bit(QLC_83XX_MBX_READY, &mbx->status); |
e5c4e6c6 MC |
3583 | ahw->idc.collect_dump = 1; |
3584 | return -EIO; | |
3585 | } | |
3586 | ||
3587 | return 0; | |
3588 | } | |
3589 | ||
3590 | static inline void qlcnic_83xx_signal_mbx_cmd(struct qlcnic_adapter *adapter, | |
3591 | u8 issue_cmd) | |
3592 | { | |
3593 | if (issue_cmd) | |
3594 | QLCWRX(adapter->ahw, QLCNIC_HOST_MBX_CTRL, QLCNIC_SET_OWNER); | |
3595 | else | |
3596 | QLCWRX(adapter->ahw, QLCNIC_FW_MBX_CTRL, QLCNIC_CLR_OWNER); | |
3597 | } | |
3598 | ||
60dcbcb0 MC |
3599 | static void qlcnic_83xx_dequeue_mbx_cmd(struct qlcnic_adapter *adapter, |
3600 | struct qlcnic_cmd_args *cmd) | |
e5c4e6c6 MC |
3601 | { |
3602 | struct qlcnic_mailbox *mbx = adapter->ahw->mailbox; | |
3603 | ||
3604 | spin_lock(&mbx->queue_lock); | |
3605 | ||
3606 | list_del(&cmd->list); | |
3607 | mbx->num_cmds--; | |
3608 | ||
3609 | spin_unlock(&mbx->queue_lock); | |
3610 | ||
3611 | qlcnic_83xx_notify_cmd_completion(adapter, cmd); | |
3612 | } | |
3613 | ||
3614 | static void qlcnic_83xx_encode_mbx_cmd(struct qlcnic_adapter *adapter, | |
3615 | struct qlcnic_cmd_args *cmd) | |
3616 | { | |
3617 | u32 mbx_cmd, fw_hal_version, hdr_size, total_size, tmp; | |
3618 | struct qlcnic_hardware_context *ahw = adapter->ahw; | |
3619 | int i, j; | |
3620 | ||
3621 | if (cmd->op_type != QLC_83XX_MBX_POST_BC_OP) { | |
3622 | mbx_cmd = cmd->req.arg[0]; | |
3623 | writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 0)); | |
3624 | for (i = 1; i < cmd->req.num; i++) | |
3625 | writel(cmd->req.arg[i], QLCNIC_MBX_HOST(ahw, i)); | |
3626 | } else { | |
3627 | fw_hal_version = ahw->fw_hal_version; | |
3628 | hdr_size = sizeof(struct qlcnic_bc_hdr) / sizeof(u32); | |
3629 | total_size = cmd->pay_size + hdr_size; | |
3630 | tmp = QLCNIC_CMD_BC_EVENT_SETUP | total_size << 16; | |
3631 | mbx_cmd = tmp | fw_hal_version << 29; | |
3632 | writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 0)); | |
3633 | ||
3634 | /* Back channel specific operations bits */ | |
3635 | mbx_cmd = 0x1 | 1 << 4; | |
3636 | ||
3637 | if (qlcnic_sriov_pf_check(adapter)) | |
3638 | mbx_cmd |= cmd->func_num << 5; | |
3639 | ||
3640 | writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 1)); | |
3641 | ||
3642 | for (i = 2, j = 0; j < hdr_size; i++, j++) | |
3643 | writel(*(cmd->hdr++), QLCNIC_MBX_HOST(ahw, i)); | |
3644 | for (j = 0; j < cmd->pay_size; j++, i++) | |
3645 | writel(*(cmd->pay++), QLCNIC_MBX_HOST(ahw, i)); | |
3646 | } | |
3647 | } | |
3648 | ||
3649 | void qlcnic_83xx_detach_mailbox_work(struct qlcnic_adapter *adapter) | |
3650 | { | |
3651 | struct qlcnic_mailbox *mbx = adapter->ahw->mailbox; | |
3652 | ||
3653 | clear_bit(QLC_83XX_MBX_READY, &mbx->status); | |
3654 | complete(&mbx->completion); | |
3655 | cancel_work_sync(&mbx->work); | |
3656 | flush_workqueue(mbx->work_q); | |
3657 | qlcnic_83xx_flush_mbx_queue(adapter); | |
3658 | } | |
3659 | ||
60dcbcb0 MC |
3660 | static int qlcnic_83xx_enqueue_mbx_cmd(struct qlcnic_adapter *adapter, |
3661 | struct qlcnic_cmd_args *cmd, | |
3662 | unsigned long *timeout) | |
e5c4e6c6 MC |
3663 | { |
3664 | struct qlcnic_mailbox *mbx = adapter->ahw->mailbox; | |
3665 | ||
3666 | if (test_bit(QLC_83XX_MBX_READY, &mbx->status)) { | |
3667 | atomic_set(&cmd->rsp_status, QLC_83XX_MBX_RESPONSE_WAIT); | |
3668 | init_completion(&cmd->completion); | |
3669 | cmd->rsp_opcode = QLC_83XX_MBX_RESPONSE_UNKNOWN; | |
3670 | ||
3671 | spin_lock(&mbx->queue_lock); | |
3672 | ||
3673 | list_add_tail(&cmd->list, &mbx->cmd_q); | |
3674 | mbx->num_cmds++; | |
3675 | cmd->total_cmds = mbx->num_cmds; | |
3676 | *timeout = cmd->total_cmds * QLC_83XX_MBX_TIMEOUT; | |
3677 | queue_work(mbx->work_q, &mbx->work); | |
3678 | ||
3679 | spin_unlock(&mbx->queue_lock); | |
3680 | ||
3681 | return 0; | |
3682 | } | |
3683 | ||
3684 | return -EBUSY; | |
3685 | } | |
3686 | ||
60dcbcb0 MC |
3687 | static int qlcnic_83xx_check_mac_rcode(struct qlcnic_adapter *adapter, |
3688 | struct qlcnic_cmd_args *cmd) | |
e5c4e6c6 MC |
3689 | { |
3690 | u8 mac_cmd_rcode; | |
3691 | u32 fw_data; | |
3692 | ||
3693 | if (cmd->cmd_op == QLCNIC_CMD_CONFIG_MAC_VLAN) { | |
3694 | fw_data = readl(QLCNIC_MBX_FW(adapter->ahw, 2)); | |
3695 | mac_cmd_rcode = (u8)fw_data; | |
3696 | if (mac_cmd_rcode == QLC_83XX_NO_NIC_RESOURCE || | |
3697 | mac_cmd_rcode == QLC_83XX_MAC_PRESENT || | |
3698 | mac_cmd_rcode == QLC_83XX_MAC_ABSENT) { | |
3699 | cmd->rsp_opcode = QLCNIC_RCODE_SUCCESS; | |
3700 | return QLCNIC_RCODE_SUCCESS; | |
3701 | } | |
3702 | } | |
3703 | ||
3704 | return -EINVAL; | |
3705 | } | |
3706 | ||
3707 | static void qlcnic_83xx_decode_mbx_rsp(struct qlcnic_adapter *adapter, | |
3708 | struct qlcnic_cmd_args *cmd) | |
3709 | { | |
3710 | struct qlcnic_hardware_context *ahw = adapter->ahw; | |
3711 | struct device *dev = &adapter->pdev->dev; | |
3712 | u8 mbx_err_code; | |
3713 | u32 fw_data; | |
3714 | ||
3715 | fw_data = readl(QLCNIC_MBX_FW(ahw, 0)); | |
3716 | mbx_err_code = QLCNIC_MBX_STATUS(fw_data); | |
3717 | qlcnic_83xx_get_mbx_data(adapter, cmd); | |
3718 | ||
3719 | switch (mbx_err_code) { | |
3720 | case QLCNIC_MBX_RSP_OK: | |
3721 | case QLCNIC_MBX_PORT_RSP_OK: | |
3722 | cmd->rsp_opcode = QLCNIC_RCODE_SUCCESS; | |
3723 | break; | |
3724 | default: | |
3725 | if (!qlcnic_83xx_check_mac_rcode(adapter, cmd)) | |
3726 | break; | |
3727 | ||
3728 | dev_err(dev, "%s: Mailbox command failed, opcode=0x%x, cmd_type=0x%x, func=0x%x, op_mode=0x%x, error=0x%x\n", | |
3729 | __func__, cmd->cmd_op, cmd->type, ahw->pci_func, | |
3730 | ahw->op_mode, mbx_err_code); | |
3731 | cmd->rsp_opcode = QLC_83XX_MBX_RESPONSE_FAILED; | |
3732 | qlcnic_dump_mbx(adapter, cmd); | |
3733 | } | |
3734 | ||
3735 | return; | |
3736 | } | |
3737 | ||
3738 | static void qlcnic_83xx_mailbox_worker(struct work_struct *work) | |
3739 | { | |
3740 | struct qlcnic_mailbox *mbx = container_of(work, struct qlcnic_mailbox, | |
3741 | work); | |
3742 | struct qlcnic_adapter *adapter = mbx->adapter; | |
3743 | struct qlcnic_mbx_ops *mbx_ops = mbx->ops; | |
3744 | struct device *dev = &adapter->pdev->dev; | |
3745 | atomic_t *rsp_status = &mbx->rsp_status; | |
3746 | struct list_head *head = &mbx->cmd_q; | |
3747 | struct qlcnic_hardware_context *ahw; | |
3748 | struct qlcnic_cmd_args *cmd = NULL; | |
3749 | ||
3750 | ahw = adapter->ahw; | |
3751 | ||
3752 | while (true) { | |
35570cfe MC |
3753 | if (qlcnic_83xx_check_mbx_status(adapter)) { |
3754 | qlcnic_83xx_flush_mbx_queue(adapter); | |
e5c4e6c6 | 3755 | return; |
35570cfe | 3756 | } |
e5c4e6c6 MC |
3757 | |
3758 | atomic_set(rsp_status, QLC_83XX_MBX_RESPONSE_WAIT); | |
3759 | ||
3760 | spin_lock(&mbx->queue_lock); | |
3761 | ||
3762 | if (list_empty(head)) { | |
3763 | spin_unlock(&mbx->queue_lock); | |
3764 | return; | |
3765 | } | |
3766 | cmd = list_entry(head->next, struct qlcnic_cmd_args, list); | |
3767 | ||
3768 | spin_unlock(&mbx->queue_lock); | |
3769 | ||
3770 | mbx_ops->encode_cmd(adapter, cmd); | |
3771 | mbx_ops->nofity_fw(adapter, QLC_83XX_MBX_REQUEST); | |
3772 | ||
3773 | if (wait_for_completion_timeout(&mbx->completion, | |
3774 | QLC_83XX_MBX_TIMEOUT)) { | |
3775 | mbx_ops->decode_resp(adapter, cmd); | |
3776 | mbx_ops->nofity_fw(adapter, QLC_83XX_MBX_COMPLETION); | |
3777 | } else { | |
3778 | dev_err(dev, "%s: Mailbox command timeout, opcode=0x%x, cmd_type=0x%x, func=0x%x, op_mode=0x%x\n", | |
3779 | __func__, cmd->cmd_op, cmd->type, ahw->pci_func, | |
3780 | ahw->op_mode); | |
3781 | clear_bit(QLC_83XX_MBX_READY, &mbx->status); | |
b942f44a | 3782 | qlcnic_dump_mbx(adapter, cmd); |
e5c4e6c6 MC |
3783 | qlcnic_83xx_idc_request_reset(adapter, |
3784 | QLCNIC_FORCE_FW_DUMP_KEY); | |
3785 | cmd->rsp_opcode = QLCNIC_RCODE_TIMEOUT; | |
3786 | } | |
3787 | mbx_ops->dequeue_cmd(adapter, cmd); | |
3788 | } | |
3789 | } | |
3790 | ||
3791 | static struct qlcnic_mbx_ops qlcnic_83xx_mbx_ops = { | |
3792 | .enqueue_cmd = qlcnic_83xx_enqueue_mbx_cmd, | |
3793 | .dequeue_cmd = qlcnic_83xx_dequeue_mbx_cmd, | |
3794 | .decode_resp = qlcnic_83xx_decode_mbx_rsp, | |
3795 | .encode_cmd = qlcnic_83xx_encode_mbx_cmd, | |
3796 | .nofity_fw = qlcnic_83xx_signal_mbx_cmd, | |
3797 | }; | |
3798 | ||
3799 | int qlcnic_83xx_init_mailbox_work(struct qlcnic_adapter *adapter) | |
3800 | { | |
3801 | struct qlcnic_hardware_context *ahw = adapter->ahw; | |
3802 | struct qlcnic_mailbox *mbx; | |
3803 | ||
3804 | ahw->mailbox = kzalloc(sizeof(*mbx), GFP_KERNEL); | |
3805 | if (!ahw->mailbox) | |
3806 | return -ENOMEM; | |
3807 | ||
3808 | mbx = ahw->mailbox; | |
3809 | mbx->ops = &qlcnic_83xx_mbx_ops; | |
3810 | mbx->adapter = adapter; | |
3811 | ||
3812 | spin_lock_init(&mbx->queue_lock); | |
3813 | spin_lock_init(&mbx->aen_lock); | |
3814 | INIT_LIST_HEAD(&mbx->cmd_q); | |
3815 | init_completion(&mbx->completion); | |
3816 | ||
3817 | mbx->work_q = create_singlethread_workqueue("qlcnic_mailbox"); | |
3818 | if (mbx->work_q == NULL) { | |
3819 | kfree(mbx); | |
3820 | return -ENOMEM; | |
3821 | } | |
3822 | ||
3823 | INIT_WORK(&mbx->work, qlcnic_83xx_mailbox_worker); | |
3824 | set_bit(QLC_83XX_MBX_READY, &mbx->status); | |
3825 | return 0; | |
3826 | } | |
9ce226fa PP |
3827 | |
3828 | pci_ers_result_t qlcnic_83xx_io_error_detected(struct pci_dev *pdev, | |
3829 | pci_channel_state_t state) | |
3830 | { | |
3831 | struct qlcnic_adapter *adapter = pci_get_drvdata(pdev); | |
3832 | ||
3833 | if (state == pci_channel_io_perm_failure) | |
3834 | return PCI_ERS_RESULT_DISCONNECT; | |
3835 | ||
3836 | if (state == pci_channel_io_normal) | |
3837 | return PCI_ERS_RESULT_RECOVERED; | |
3838 | ||
3839 | set_bit(__QLCNIC_AER, &adapter->state); | |
3840 | set_bit(__QLCNIC_RESETTING, &adapter->state); | |
3841 | ||
3842 | qlcnic_83xx_aer_stop_poll_work(adapter); | |
3843 | ||
3844 | pci_save_state(pdev); | |
3845 | pci_disable_device(pdev); | |
3846 | ||
3847 | return PCI_ERS_RESULT_NEED_RESET; | |
3848 | } | |
3849 | ||
3850 | pci_ers_result_t qlcnic_83xx_io_slot_reset(struct pci_dev *pdev) | |
3851 | { | |
3852 | struct qlcnic_adapter *adapter = pci_get_drvdata(pdev); | |
3853 | int err = 0; | |
3854 | ||
3855 | pdev->error_state = pci_channel_io_normal; | |
3856 | err = pci_enable_device(pdev); | |
3857 | if (err) | |
3858 | goto disconnect; | |
3859 | ||
3860 | pci_set_power_state(pdev, PCI_D0); | |
3861 | pci_set_master(pdev); | |
3862 | pci_restore_state(pdev); | |
3863 | ||
3864 | err = qlcnic_83xx_aer_reset(adapter); | |
3865 | if (err == 0) | |
3866 | return PCI_ERS_RESULT_RECOVERED; | |
3867 | disconnect: | |
3868 | clear_bit(__QLCNIC_AER, &adapter->state); | |
3869 | clear_bit(__QLCNIC_RESETTING, &adapter->state); | |
3870 | return PCI_ERS_RESULT_DISCONNECT; | |
3871 | } | |
3872 | ||
3873 | void qlcnic_83xx_io_resume(struct pci_dev *pdev) | |
3874 | { | |
3875 | struct qlcnic_adapter *adapter = pci_get_drvdata(pdev); | |
3876 | ||
3877 | pci_cleanup_aer_uncorrect_error_status(pdev); | |
3878 | if (test_and_clear_bit(__QLCNIC_AER, &adapter->state)) | |
3879 | qlcnic_83xx_aer_start_poll_work(adapter); | |
3880 | } |