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qlcnic: Support VLAN id config.
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / qlogic / qlcnic / qlcnic_83xx_hw.c
CommitLineData
577ae39d
JK		 1/*
2 * QLogic qlcnic NIC Driver
3 * Copyright (c) 2009-2013 QLogic Corporation
4 *
5 * See LICENSE.qlcnic for copyright and licensing details.
6 */
7
7f966452 8#include "qlcnic.h"
f8468331 9#include "qlcnic_sriov.h"
7f966452
SC		 10#include <linux/if_vlan.h>
11#include <linux/ipv6.h>
12#include <linux/ethtool.h>
13#include <linux/interrupt.h>
14
15#define QLCNIC_MAX_TX_QUEUES 1
7f966452 16#define RSS_HASHTYPE_IP_TCP 0x3
f197a7aa 17#define QLC_83XX_FW_MBX_CMD 0
7f966452 18
7f966452
SC		 19static const struct qlcnic_mailbox_metadata qlcnic_83xx_mbx_tbl[] = {
20 {QLCNIC_CMD_CONFIGURE_IP_ADDR, 6, 1},
21 {QLCNIC_CMD_CONFIG_INTRPT, 18, 34},
22 {QLCNIC_CMD_CREATE_RX_CTX, 136, 27},
23 {QLCNIC_CMD_DESTROY_RX_CTX, 2, 1},
24 {QLCNIC_CMD_CREATE_TX_CTX, 54, 18},
25 {QLCNIC_CMD_DESTROY_TX_CTX, 2, 1},
26 {QLCNIC_CMD_CONFIGURE_MAC_LEARNING, 2, 1},
27 {QLCNIC_CMD_INTRPT_TEST, 22, 12},
28 {QLCNIC_CMD_SET_MTU, 3, 1},
29 {QLCNIC_CMD_READ_PHY, 4, 2},
30 {QLCNIC_CMD_WRITE_PHY, 5, 1},
31 {QLCNIC_CMD_READ_HW_REG, 4, 1},
32 {QLCNIC_CMD_GET_FLOW_CTL, 4, 2},
33 {QLCNIC_CMD_SET_FLOW_CTL, 4, 1},
34 {QLCNIC_CMD_READ_MAX_MTU, 4, 2},
35 {QLCNIC_CMD_READ_MAX_LRO, 4, 2},
36 {QLCNIC_CMD_MAC_ADDRESS, 4, 3},
37 {QLCNIC_CMD_GET_PCI_INFO, 1, 66},
38 {QLCNIC_CMD_GET_NIC_INFO, 2, 19},
39 {QLCNIC_CMD_SET_NIC_INFO, 32, 1},
40 {QLCNIC_CMD_GET_ESWITCH_CAPABILITY, 4, 3},
41 {QLCNIC_CMD_TOGGLE_ESWITCH, 4, 1},
42 {QLCNIC_CMD_GET_ESWITCH_STATUS, 4, 3},
43 {QLCNIC_CMD_SET_PORTMIRRORING, 4, 1},
44 {QLCNIC_CMD_CONFIGURE_ESWITCH, 4, 1},
45 {QLCNIC_CMD_GET_ESWITCH_PORT_CONFIG, 4, 3},
46 {QLCNIC_CMD_GET_ESWITCH_STATS, 5, 1},
47 {QLCNIC_CMD_CONFIG_PORT, 4, 1},
48 {QLCNIC_CMD_TEMP_SIZE, 1, 4},
49 {QLCNIC_CMD_GET_TEMP_HDR, 5, 5},
50 {QLCNIC_CMD_GET_LINK_EVENT, 2, 1},
51 {QLCNIC_CMD_CONFIG_MAC_VLAN, 4, 3},
52 {QLCNIC_CMD_CONFIG_INTR_COAL, 6, 1},
53 {QLCNIC_CMD_CONFIGURE_RSS, 14, 1},
54 {QLCNIC_CMD_CONFIGURE_LED, 2, 1},
55 {QLCNIC_CMD_CONFIGURE_MAC_RX_MODE, 2, 1},
56 {QLCNIC_CMD_CONFIGURE_HW_LRO, 2, 1},
57 {QLCNIC_CMD_GET_STATISTICS, 2, 80},
58 {QLCNIC_CMD_SET_PORT_CONFIG, 2, 1},
59 {QLCNIC_CMD_GET_PORT_CONFIG, 2, 2},
60 {QLCNIC_CMD_GET_LINK_STATUS, 2, 4},
61 {QLCNIC_CMD_IDC_ACK, 5, 1},
62 {QLCNIC_CMD_INIT_NIC_FUNC, 2, 1},
63 {QLCNIC_CMD_STOP_NIC_FUNC, 2, 1},
64 {QLCNIC_CMD_SET_LED_CONFIG, 5, 1},
65 {QLCNIC_CMD_GET_LED_CONFIG, 1, 5},
66 {QLCNIC_CMD_ADD_RCV_RINGS, 130, 26},
02feda17 67 {QLCNIC_CMD_CONFIG_VPORT, 4, 4},
f197a7aa 68 {QLCNIC_CMD_BC_EVENT_SETUP, 2, 1},
7f966452
SC		 69};
70
f8468331 71const u32 qlcnic_83xx_ext_reg_tbl[] = {
7f966452
SC		 72 0x38CC, /* Global Reset */
73 0x38F0, /* Wildcard */
74 0x38FC, /* Informant */
75 0x3038, /* Host MBX ctrl */
76 0x303C, /* FW MBX ctrl */
77 0x355C, /* BOOT LOADER ADDRESS REG */
78 0x3560, /* BOOT LOADER SIZE REG */
79 0x3564, /* FW IMAGE ADDR REG */
80 0x1000, /* MBX intr enable */
81 0x1200, /* Default Intr mask */
82 0x1204, /* Default Interrupt ID */
83 0x3780, /* QLC_83XX_IDC_MAJ_VERSION */
84 0x3784, /* QLC_83XX_IDC_DEV_STATE */
85 0x3788, /* QLC_83XX_IDC_DRV_PRESENCE */
86 0x378C, /* QLC_83XX_IDC_DRV_ACK */
87 0x3790, /* QLC_83XX_IDC_CTRL */
88 0x3794, /* QLC_83XX_IDC_DRV_AUDIT */
89 0x3798, /* QLC_83XX_IDC_MIN_VERSION */
90 0x379C, /* QLC_83XX_RECOVER_DRV_LOCK */
91 0x37A0, /* QLC_83XX_IDC_PF_0 */
92 0x37A4, /* QLC_83XX_IDC_PF_1 */
93 0x37A8, /* QLC_83XX_IDC_PF_2 */
94 0x37AC, /* QLC_83XX_IDC_PF_3 */
95 0x37B0, /* QLC_83XX_IDC_PF_4 */
96 0x37B4, /* QLC_83XX_IDC_PF_5 */
97 0x37B8, /* QLC_83XX_IDC_PF_6 */
98 0x37BC, /* QLC_83XX_IDC_PF_7 */
99 0x37C0, /* QLC_83XX_IDC_PF_8 */
100 0x37C4, /* QLC_83XX_IDC_PF_9 */
101 0x37C8, /* QLC_83XX_IDC_PF_10 */
102 0x37CC, /* QLC_83XX_IDC_PF_11 */
103 0x37D0, /* QLC_83XX_IDC_PF_12 */
104 0x37D4, /* QLC_83XX_IDC_PF_13 */
105 0x37D8, /* QLC_83XX_IDC_PF_14 */
106 0x37DC, /* QLC_83XX_IDC_PF_15 */
107 0x37E0, /* QLC_83XX_IDC_DEV_PARTITION_INFO_1 */
108 0x37E4, /* QLC_83XX_IDC_DEV_PARTITION_INFO_2 */
109 0x37F0, /* QLC_83XX_DRV_OP_MODE */
110 0x37F4, /* QLC_83XX_VNIC_STATE */
111 0x3868, /* QLC_83XX_DRV_LOCK */
112 0x386C, /* QLC_83XX_DRV_UNLOCK */
113 0x3504, /* QLC_83XX_DRV_LOCK_ID */
114 0x34A4, /* QLC_83XX_ASIC_TEMP */
115};
116
f8468331 117const u32 qlcnic_83xx_reg_tbl[] = {
7f966452
SC		 118 0x34A8, /* PEG_HALT_STAT1 */
119 0x34AC, /* PEG_HALT_STAT2 */
120 0x34B0, /* FW_HEARTBEAT */
121 0x3500, /* FLASH LOCK_ID */
122 0x3528, /* FW_CAPABILITIES */
123 0x3538, /* Driver active, DRV_REG0 */
124 0x3540, /* Device state, DRV_REG1 */
125 0x3544, /* Driver state, DRV_REG2 */
126 0x3548, /* Driver scratch, DRV_REG3 */
127 0x354C, /* Device partiton info, DRV_REG4 */
128 0x3524, /* Driver IDC ver, DRV_REG5 */
129 0x3550, /* FW_VER_MAJOR */
130 0x3554, /* FW_VER_MINOR */
131 0x3558, /* FW_VER_SUB */
132 0x359C, /* NPAR STATE */
133 0x35FC, /* FW_IMG_VALID */
134 0x3650, /* CMD_PEG_STATE */
135 0x373C, /* RCV_PEG_STATE */
136 0x37B4, /* ASIC TEMP */
137 0x356C, /* FW API */
138 0x3570, /* DRV OP MODE */
139 0x3850, /* FLASH LOCK */
140 0x3854, /* FLASH UNLOCK */
141};
142
143static struct qlcnic_hardware_ops qlcnic_83xx_hw_ops = {
144 .read_crb = qlcnic_83xx_read_crb,
145 .write_crb = qlcnic_83xx_write_crb,
146 .read_reg = qlcnic_83xx_rd_reg_indirect,
147 .write_reg = qlcnic_83xx_wrt_reg_indirect,
148 .get_mac_address = qlcnic_83xx_get_mac_address,
149 .setup_intr = qlcnic_83xx_setup_intr,
150 .alloc_mbx_args = qlcnic_83xx_alloc_mbx_args,
151 .mbx_cmd = qlcnic_83xx_mbx_op,
152 .get_func_no = qlcnic_83xx_get_func_no,
153 .api_lock = qlcnic_83xx_cam_lock,
154 .api_unlock = qlcnic_83xx_cam_unlock,
319ecf12
SC		 155 .add_sysfs = qlcnic_83xx_add_sysfs,
156 .remove_sysfs = qlcnic_83xx_remove_sysfs,
4be41e92 157 .process_lb_rcv_ring_diag = qlcnic_83xx_process_rcv_ring_diag,
7f966452
SC		 158 .create_rx_ctx = qlcnic_83xx_create_rx_ctx,
159 .create_tx_ctx = qlcnic_83xx_create_tx_ctx,
7cb03b23
RB		 160 .del_rx_ctx = qlcnic_83xx_del_rx_ctx,
161 .del_tx_ctx = qlcnic_83xx_del_tx_ctx,
7f966452
SC		 162 .setup_link_event = qlcnic_83xx_setup_link_event,
163 .get_nic_info = qlcnic_83xx_get_nic_info,
164 .get_pci_info = qlcnic_83xx_get_pci_info,
165 .set_nic_info = qlcnic_83xx_set_nic_info,
166 .change_macvlan = qlcnic_83xx_sre_macaddr_change,
4be41e92
SC		 167 .napi_enable = qlcnic_83xx_napi_enable,
168 .napi_disable = qlcnic_83xx_napi_disable,
7f966452
SC		 169 .config_intr_coal = qlcnic_83xx_config_intr_coal,
170 .config_rss = qlcnic_83xx_config_rss,
171 .config_hw_lro = qlcnic_83xx_config_hw_lro,
7f966452
SC		 172 .config_promisc_mode = qlcnic_83xx_nic_set_promisc,
173 .change_l2_filter = qlcnic_83xx_change_l2_filter,
174 .get_board_info = qlcnic_83xx_get_port_info,
91b7282b 175 .free_mac_list = qlcnic_82xx_free_mac_list,
7f966452
SC		 176};
177
178static struct qlcnic_nic_template qlcnic_83xx_ops = {
179 .config_bridged_mode = qlcnic_config_bridged_mode,
180 .config_led = qlcnic_config_led,
629263ac
SC		 181 .request_reset = qlcnic_83xx_idc_request_reset,
182 .cancel_idc_work = qlcnic_83xx_idc_exit,
4be41e92
SC		 183 .napi_add = qlcnic_83xx_napi_add,
184 .napi_del = qlcnic_83xx_napi_del,
7f966452
SC		 185 .config_ipaddr = qlcnic_83xx_config_ipaddr,
186 .clear_legacy_intr = qlcnic_83xx_clear_legacy_intr,
187};
188
189void qlcnic_83xx_register_map(struct qlcnic_hardware_context *ahw)
190{
191 ahw->hw_ops = &qlcnic_83xx_hw_ops;
192 ahw->reg_tbl = (u32 *)qlcnic_83xx_reg_tbl;
193 ahw->ext_reg_tbl = (u32 *)qlcnic_83xx_ext_reg_tbl;
194}
195
196int qlcnic_83xx_get_fw_version(struct qlcnic_adapter *adapter)
197{
198 u32 fw_major, fw_minor, fw_build;
199 struct pci_dev *pdev = adapter->pdev;
200
201 fw_major = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MAJOR);
202 fw_minor = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MINOR);
203 fw_build = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_SUB);
204 adapter->fw_version = QLCNIC_VERSION_CODE(fw_major, fw_minor, fw_build);
205
206 dev_info(&pdev->dev, "Driver v%s, firmware version %d.%d.%d\n",
207 QLCNIC_LINUX_VERSIONID, fw_major, fw_minor, fw_build);
208
209 return adapter->fw_version;
210}
211
212static int __qlcnic_set_win_base(struct qlcnic_adapter *adapter, u32 addr)
213{
214 void __iomem *base;
215 u32 val;
216
217 base = adapter->ahw->pci_base0 +
218 QLC_83XX_CRB_WIN_FUNC(adapter->ahw->pci_func);
219 writel(addr, base);
220 val = readl(base);
221 if (val != addr)
222 return -EIO;
223
224 return 0;
225}
226
227int qlcnic_83xx_rd_reg_indirect(struct qlcnic_adapter *adapter, ulong addr)
228{
229 int ret;
230 struct qlcnic_hardware_context *ahw = adapter->ahw;
231
232 ret = __qlcnic_set_win_base(adapter, (u32) addr);
233 if (!ret) {
234 return QLCRDX(ahw, QLCNIC_WILDCARD);
235 } else {
236 dev_err(&adapter->pdev->dev,
237 "%s failed, addr = 0x%x\n", __func__, (int)addr);
238 return -EIO;
239 }
240}
241
242int qlcnic_83xx_wrt_reg_indirect(struct qlcnic_adapter *adapter, ulong addr,
243 u32 data)
244{
245 int err;
246 struct qlcnic_hardware_context *ahw = adapter->ahw;
247
248 err = __qlcnic_set_win_base(adapter, (u32) addr);
249 if (!err) {
250 QLCWRX(ahw, QLCNIC_WILDCARD, data);
251 return 0;
252 } else {
253 dev_err(&adapter->pdev->dev,
254 "%s failed, addr = 0x%x data = 0x%x\n",
255 __func__, (int)addr, data);
256 return err;
257 }
258}
259
260int qlcnic_83xx_setup_intr(struct qlcnic_adapter *adapter, u8 num_intr)
261{
262 int err, i, num_msix;
263 struct qlcnic_hardware_context *ahw = adapter->ahw;
264
265 if (!num_intr)
266 num_intr = QLCNIC_DEF_NUM_STS_DESC_RINGS;
267 num_msix = rounddown_pow_of_two(min_t(int, num_online_cpus(),
268 num_intr));
269 /* account for AEN interrupt MSI-X based interrupts */
270 num_msix += 1;
da6c8063
RB		 271
272 if (!(adapter->flags & QLCNIC_TX_INTR_SHARED))
273 num_msix += adapter->max_drv_tx_rings;
274
7f966452
SC		 275 err = qlcnic_enable_msix(adapter, num_msix);
276 if (err == -ENOMEM)
277 return err;
278 if (adapter->flags & QLCNIC_MSIX_ENABLED)
279 num_msix = adapter->ahw->num_msix;
f8468331
RB		 280 else {
281 if (qlcnic_sriov_vf_check(adapter))
282 return -EINVAL;
7f966452 283 num_msix = 1;
f8468331 284 }
7f966452
SC		 285 /* setup interrupt mapping table for fw */
286 ahw->intr_tbl = vzalloc(num_msix *
287 sizeof(struct qlcnic_intrpt_config));
288 if (!ahw->intr_tbl)
289 return -ENOMEM;
290 if (!(adapter->flags & QLCNIC_MSIX_ENABLED)) {
291 /* MSI-X enablement failed, use legacy interrupt */
292 adapter->tgt_status_reg = ahw->pci_base0 + QLC_83XX_INTX_PTR;
293 adapter->tgt_mask_reg = ahw->pci_base0 + QLC_83XX_INTX_MASK;
294 adapter->isr_int_vec = ahw->pci_base0 + QLC_83XX_INTX_TRGR;
295 adapter->msix_entries[0].vector = adapter->pdev->irq;
296 dev_info(&adapter->pdev->dev, "using legacy interrupt\n");
297 }
298
299 for (i = 0; i < num_msix; i++) {
300 if (adapter->flags & QLCNIC_MSIX_ENABLED)
301 ahw->intr_tbl[i].type = QLCNIC_INTRPT_MSIX;
302 else
303 ahw->intr_tbl[i].type = QLCNIC_INTRPT_INTX;
304 ahw->intr_tbl[i].id = i;
305 ahw->intr_tbl[i].src = 0;
306 }
307 return 0;
308}
309
ac166700
HM		 310inline void qlcnic_83xx_clear_legacy_intr_mask(struct qlcnic_adapter *adapter)
311{
312 writel(0, adapter->tgt_mask_reg);
313}
314
315/* Enable MSI-x and INT-x interrupts */
316void qlcnic_83xx_enable_intr(struct qlcnic_adapter *adapter,
317 struct qlcnic_host_sds_ring *sds_ring)
7f966452
SC		 318{
319 writel(0, sds_ring->crb_intr_mask);
ac166700
HM		 320}
321
322/* Disable MSI-x and INT-x interrupts */
323void qlcnic_83xx_disable_intr(struct qlcnic_adapter *adapter,
324 struct qlcnic_host_sds_ring *sds_ring)
325{
326 writel(1, sds_ring->crb_intr_mask);
327}
328
329inline void qlcnic_83xx_enable_legacy_msix_mbx_intr(struct qlcnic_adapter
330 *adapter)
331{
332 u32 mask;
333
334 /* Mailbox in MSI-x mode and Legacy Interrupt share the same
335 * source register. We could be here before contexts are created
336 * and sds_ring->crb_intr_mask has not been initialized, calculate
337 * BAR offset for Interrupt Source Register
338 */
339 mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
340 writel(0, adapter->ahw->pci_base0 + mask);
341}
342
f036e4f4 343void qlcnic_83xx_disable_mbx_intr(struct qlcnic_adapter *adapter)
ac166700
HM		 344{
345 u32 mask;
346
347 mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
348 writel(1, adapter->ahw->pci_base0 + mask);
f036e4f4 349 QLCWRX(adapter->ahw, QLCNIC_MBX_INTR_ENBL, 0);
7f966452
SC		 350}
351
352static inline void qlcnic_83xx_get_mbx_data(struct qlcnic_adapter *adapter,
353 struct qlcnic_cmd_args *cmd)
354{
355 int i;
356 for (i = 0; i < cmd->rsp.num; i++)
357 cmd->rsp.arg[i] = readl(QLCNIC_MBX_FW(adapter->ahw, i));
358}
359
360irqreturn_t qlcnic_83xx_clear_legacy_intr(struct qlcnic_adapter *adapter)
361{
362 u32 intr_val;
363 struct qlcnic_hardware_context *ahw = adapter->ahw;
364 int retries = 0;
365
366 intr_val = readl(adapter->tgt_status_reg);
367
368 if (!QLC_83XX_VALID_INTX_BIT31(intr_val))
369 return IRQ_NONE;
370
371 if (QLC_83XX_INTX_FUNC(intr_val) != adapter->ahw->pci_func) {
372 adapter->stats.spurious_intr++;
373 return IRQ_NONE;
374 }
ac166700
HM		 375 /* The barrier is required to ensure writes to the registers */
376 wmb();
377
7f966452
SC		 378 /* clear the interrupt trigger control register */
379 writel(0, adapter->isr_int_vec);
ac166700 380 intr_val = readl(adapter->isr_int_vec);
7f966452
SC		 381 do {
382 intr_val = readl(adapter->tgt_status_reg);
383 if (QLC_83XX_INTX_FUNC(intr_val) != ahw->pci_func)
384 break;
385 retries++;
386 } while (QLC_83XX_VALID_INTX_BIT30(intr_val) &&
387 (retries < QLC_83XX_LEGACY_INTX_MAX_RETRY));
388
ac166700
HM		 389 return IRQ_HANDLED;
390}
391
392static void qlcnic_83xx_poll_process_aen(struct qlcnic_adapter *adapter)
393{
394 u32 resp, event;
395 unsigned long flags;
396
397 spin_lock_irqsave(&adapter->ahw->mbx_lock, flags);
398
399 resp = QLCRDX(adapter->ahw, QLCNIC_FW_MBX_CTRL);
400 if (!(resp & QLCNIC_SET_OWNER))
401 goto out;
402
403 event = readl(QLCNIC_MBX_FW(adapter->ahw, 0));
404 if (event & QLCNIC_MBX_ASYNC_EVENT)
405 qlcnic_83xx_process_aen(adapter);
406out:
407 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
408 spin_unlock_irqrestore(&adapter->ahw->mbx_lock, flags);
409}
410
411irqreturn_t qlcnic_83xx_intr(int irq, void *data)
412{
413 struct qlcnic_adapter *adapter = data;
414 struct qlcnic_host_sds_ring *sds_ring;
415 struct qlcnic_hardware_context *ahw = adapter->ahw;
416
417 if (qlcnic_83xx_clear_legacy_intr(adapter) == IRQ_NONE)
7f966452 418 return IRQ_NONE;
ac166700
HM		 419
420 qlcnic_83xx_poll_process_aen(adapter);
421
422 if (ahw->diag_test == QLCNIC_INTERRUPT_TEST) {
423 ahw->diag_cnt++;
424 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
425 return IRQ_HANDLED;
7f966452
SC		 426 }
427
ac166700
HM		 428 if (!test_bit(__QLCNIC_DEV_UP, &adapter->state)) {
429 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
430 } else {
431 sds_ring = &adapter->recv_ctx->sds_rings[0];
432 napi_schedule(&sds_ring->napi);
433 }
7f966452
SC		 434
435 return IRQ_HANDLED;
436}
437
438irqreturn_t qlcnic_83xx_tmp_intr(int irq, void *data)
439{
440 struct qlcnic_host_sds_ring *sds_ring = data;
441 struct qlcnic_adapter *adapter = sds_ring->adapter;
442
443 if (adapter->flags & QLCNIC_MSIX_ENABLED)
444 goto done;
445
446 if (adapter->nic_ops->clear_legacy_intr(adapter) == IRQ_NONE)
447 return IRQ_NONE;
448
449done:
450 adapter->ahw->diag_cnt++;
451 qlcnic_83xx_enable_intr(adapter, sds_ring);
452
453 return IRQ_HANDLED;
454}
455
456void qlcnic_83xx_free_mbx_intr(struct qlcnic_adapter *adapter)
457{
f036e4f4
RB		 458 u32 num_msix;
459
460 qlcnic_83xx_disable_mbx_intr(adapter);
7f966452 461
ac166700
HM		 462 if (adapter->flags & QLCNIC_MSIX_ENABLED)
463 num_msix = adapter->ahw->num_msix - 1;
464 else
465 num_msix = 0;
7f966452 466
ac166700
HM		 467 msleep(20);
468 synchronize_irq(adapter->msix_entries[num_msix].vector);
469 free_irq(adapter->msix_entries[num_msix].vector, adapter);
7f966452
SC		 470}
471
472int qlcnic_83xx_setup_mbx_intr(struct qlcnic_adapter *adapter)
473{
474 irq_handler_t handler;
475 u32 val;
476 char name[32];
477 int err = 0;
478 unsigned long flags = 0;
479
480 if (!(adapter->flags & QLCNIC_MSI_ENABLED) &&
481 !(adapter->flags & QLCNIC_MSIX_ENABLED))
482 flags |= IRQF_SHARED;
483
484 if (adapter->flags & QLCNIC_MSIX_ENABLED) {
485 handler = qlcnic_83xx_handle_aen;
486 val = adapter->msix_entries[adapter->ahw->num_msix - 1].vector;
487 snprintf(name, (IFNAMSIZ + 4),
ac166700 488 "%s[%s]", "qlcnic", "aen");
7f966452
SC		 489 err = request_irq(val, handler, flags, name, adapter);
490 if (err) {
491 dev_err(&adapter->pdev->dev,
492 "failed to register MBX interrupt\n");
493 return err;
494 }
ac166700
HM		 495 } else {
496 handler = qlcnic_83xx_intr;
497 val = adapter->msix_entries[0].vector;
498 err = request_irq(val, handler, flags, "qlcnic", adapter);
499 if (err) {
500 dev_err(&adapter->pdev->dev,
501 "failed to register INTx interrupt\n");
502 return err;
503 }
504 qlcnic_83xx_clear_legacy_intr_mask(adapter);
7f966452
SC		 505 }
506
507 /* Enable mailbox interrupt */
508 qlcnic_83xx_enable_mbx_intrpt(adapter);
7f966452
SC		 509
510 return err;
511}
512
513void qlcnic_83xx_get_func_no(struct qlcnic_adapter *adapter)
514{
515 u32 val = QLCRDX(adapter->ahw, QLCNIC_INFORMANT);
f8468331 516 adapter->ahw->pci_func = (val >> 24) & 0xff;
7f966452
SC		 517}
518
519int qlcnic_83xx_cam_lock(struct qlcnic_adapter *adapter)
520{
521 void __iomem *addr;
522 u32 val, limit = 0;
523
524 struct qlcnic_hardware_context *ahw = adapter->ahw;
525
526 addr = ahw->pci_base0 + QLC_83XX_SEM_LOCK_FUNC(ahw->pci_func);
527 do {
528 val = readl(addr);
529 if (val) {
530 /* write the function number to register */
531 QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER,
532 ahw->pci_func);
533 return 0;
534 }
535 usleep_range(1000, 2000);
536 } while (++limit <= QLCNIC_PCIE_SEM_TIMEOUT);
537
538 return -EIO;
539}
540
541void qlcnic_83xx_cam_unlock(struct qlcnic_adapter *adapter)
542{
543 void __iomem *addr;
544 u32 val;
545 struct qlcnic_hardware_context *ahw = adapter->ahw;
546
547 addr = ahw->pci_base0 + QLC_83XX_SEM_UNLOCK_FUNC(ahw->pci_func);
548 val = readl(addr);
549}
550
551void qlcnic_83xx_read_crb(struct qlcnic_adapter *adapter, char *buf,
552 loff_t offset, size_t size)
553{
554 int ret;
555 u32 data;
556
557 if (qlcnic_api_lock(adapter)) {
558 dev_err(&adapter->pdev->dev,
559 "%s: failed to acquire lock. addr offset 0x%x\n",
560 __func__, (u32)offset);
561 return;
562 }
563
564 ret = qlcnic_83xx_rd_reg_indirect(adapter, (u32) offset);
565 qlcnic_api_unlock(adapter);
566
567 if (ret == -EIO) {
568 dev_err(&adapter->pdev->dev,
569 "%s: failed. addr offset 0x%x\n",
570 __func__, (u32)offset);
571 return;
572 }
573 data = ret;
574 memcpy(buf, &data, size);
575}
576
577void qlcnic_83xx_write_crb(struct qlcnic_adapter *adapter, char *buf,
578 loff_t offset, size_t size)
579{
580 u32 data;
581
582 memcpy(&data, buf, size);
583 qlcnic_83xx_wrt_reg_indirect(adapter, (u32) offset, data);
584}
585
586int qlcnic_83xx_get_port_info(struct qlcnic_adapter *adapter)
587{
588 int status;
589
590 status = qlcnic_83xx_get_port_config(adapter);
591 if (status) {
592 dev_err(&adapter->pdev->dev,
593 "Get Port Info failed\n");
594 } else {
595 if (QLC_83XX_SFP_10G_CAPABLE(adapter->ahw->port_config))
596 adapter->ahw->port_type = QLCNIC_XGBE;
597 else
598 adapter->ahw->port_type = QLCNIC_GBE;
629263ac 599
7f966452
SC		 600 if (QLC_83XX_AUTONEG(adapter->ahw->port_config))
601 adapter->ahw->link_autoneg = AUTONEG_ENABLE;
602 }
603 return status;
604}
605
606void qlcnic_83xx_enable_mbx_intrpt(struct qlcnic_adapter *adapter)
607{
608 u32 val;
609
610 if (adapter->flags & QLCNIC_MSIX_ENABLED)
611 val = BIT_2 | ((adapter->ahw->num_msix - 1) << 8);
612 else
613 val = BIT_2;
629263ac 614
7f966452 615 QLCWRX(adapter->ahw, QLCNIC_MBX_INTR_ENBL, val);
ac166700 616 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
7f966452
SC		 617}
618
619void qlcnic_83xx_check_vf(struct qlcnic_adapter *adapter,
620 const struct pci_device_id *ent)
621{
622 u32 op_mode, priv_level;
623 struct qlcnic_hardware_context *ahw = adapter->ahw;
624
7f966452 625 ahw->fw_hal_version = 2;
7f966452
SC		 626 qlcnic_get_func_no(adapter);
627
f8468331
RB		 628 if (qlcnic_sriov_vf_check(adapter)) {
629 qlcnic_sriov_vf_set_ops(adapter);
630 return;
631 }
632
7f966452
SC		 633 /* Determine function privilege level */
634 op_mode = QLCRDX(adapter->ahw, QLC_83XX_DRV_OP_MODE);
635 if (op_mode == QLC_83XX_DEFAULT_OPMODE)
636 priv_level = QLCNIC_MGMT_FUNC;
637 else
638 priv_level = QLC_83XX_GET_FUNC_PRIVILEGE(op_mode,
639 ahw->pci_func);
640
641 if (priv_level == QLCNIC_NON_PRIV_FUNC) {
642 ahw->op_mode = QLCNIC_NON_PRIV_FUNC;
643 dev_info(&adapter->pdev->dev,
644 "HAL Version: %d Non Privileged function\n",
645 ahw->fw_hal_version);
646 adapter->nic_ops = &qlcnic_vf_ops;
647 } else {
02feda17
RB		 648 if (pci_find_ext_capability(adapter->pdev,
649 PCI_EXT_CAP_ID_SRIOV))
650 set_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state);
7f966452
SC		 651 adapter->nic_ops = &qlcnic_83xx_ops;
652 }
653}
654
655static void qlcnic_83xx_handle_link_aen(struct qlcnic_adapter *adapter,
656 u32 data[]);
657static void qlcnic_83xx_handle_idc_comp_aen(struct qlcnic_adapter *adapter,
658 u32 data[]);
659
660static void qlcnic_dump_mbx(struct qlcnic_adapter *adapter,
661 struct qlcnic_cmd_args *cmd)
662{
663 int i;
664
665 dev_info(&adapter->pdev->dev,
666 "Host MBX regs(%d)\n", cmd->req.num);
667 for (i = 0; i < cmd->req.num; i++) {
668 if (i && !(i % 8))
669 pr_info("\n");
670 pr_info("%08x ", cmd->req.arg[i]);
671 }
672 pr_info("\n");
673 dev_info(&adapter->pdev->dev,
674 "FW MBX regs(%d)\n", cmd->rsp.num);
675 for (i = 0; i < cmd->rsp.num; i++) {
676 if (i && !(i % 8))
677 pr_info("\n");
678 pr_info("%08x ", cmd->rsp.arg[i]);
679 }
680 pr_info("\n");
681}
682
65ab999d 683/* Mailbox response for mac rcode */
f197a7aa 684u32 qlcnic_83xx_mac_rcode(struct qlcnic_adapter *adapter)
65ab999d
JK		 685{
686 u32 fw_data;
687 u8 mac_cmd_rcode;
688
689 fw_data = readl(QLCNIC_MBX_FW(adapter->ahw, 2));
690 mac_cmd_rcode = (u8)fw_data;
691 if (mac_cmd_rcode == QLC_83XX_NO_NIC_RESOURCE ||
692 mac_cmd_rcode == QLC_83XX_MAC_PRESENT ||
693 mac_cmd_rcode == QLC_83XX_MAC_ABSENT)
694 return QLCNIC_RCODE_SUCCESS;
695 return 1;
696}
697
f197a7aa 698u32 qlcnic_83xx_mbx_poll(struct qlcnic_adapter *adapter)
7f966452
SC		 699{
700 u32 data;
701 unsigned long wait_time = 0;
702 struct qlcnic_hardware_context *ahw = adapter->ahw;
703 /* wait for mailbox completion */
704 do {
705 data = QLCRDX(ahw, QLCNIC_FW_MBX_CTRL);
706 if (++wait_time > QLCNIC_MBX_TIMEOUT) {
707 data = QLCNIC_RCODE_TIMEOUT;
708 break;
709 }
710 mdelay(1);
711 } while (!data);
712 return data;
713}
714
715int qlcnic_83xx_mbx_op(struct qlcnic_adapter *adapter,
716 struct qlcnic_cmd_args *cmd)
717{
718 int i;
719 u16 opcode;
65ab999d 720 u8 mbx_err_code;
ac166700 721 unsigned long flags;
483202d5 722 u32 rsp, mbx_val, fw_data, rsp_num, mbx_cmd;
7f966452
SC		 723 struct qlcnic_hardware_context *ahw = adapter->ahw;
724
725 opcode = LSW(cmd->req.arg[0]);
629263ac
SC		 726 if (!test_bit(QLC_83XX_MBX_READY, &adapter->ahw->idc.status)) {
727 dev_info(&adapter->pdev->dev,
728 "Mailbox cmd attempted, 0x%x\n", opcode);
729 dev_info(&adapter->pdev->dev, "Mailbox detached\n");
730 return 0;
731 }
732
ac166700 733 spin_lock_irqsave(&adapter->ahw->mbx_lock, flags);
7f966452
SC		 734 mbx_val = QLCRDX(ahw, QLCNIC_HOST_MBX_CTRL);
735
736 if (mbx_val) {
737 QLCDB(adapter, DRV,
738 "Mailbox cmd attempted, 0x%x\n", opcode);
739 QLCDB(adapter, DRV,
740 "Mailbox not available, 0x%x, collect FW dump\n",
741 mbx_val);
742 cmd->rsp.arg[0] = QLCNIC_RCODE_TIMEOUT;
ac166700 743 spin_unlock_irqrestore(&adapter->ahw->mbx_lock, flags);
7f966452
SC		 744 return cmd->rsp.arg[0];
745 }
746
747 /* Fill in mailbox registers */
748 mbx_cmd = cmd->req.arg[0];
749 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 0));
750 for (i = 1; i < cmd->req.num; i++)
751 writel(cmd->req.arg[i], QLCNIC_MBX_HOST(ahw, i));
752
753 /* Signal FW about the impending command */
754 QLCWRX(ahw, QLCNIC_HOST_MBX_CTRL, QLCNIC_SET_OWNER);
755poll:
756 rsp = qlcnic_83xx_mbx_poll(adapter);
7f966452 757 if (rsp != QLCNIC_RCODE_TIMEOUT) {
65ab999d
JK		 758 /* Get the FW response data */
759 fw_data = readl(QLCNIC_MBX_FW(ahw, 0));
483202d5
JK		 760 if (fw_data & QLCNIC_MBX_ASYNC_EVENT) {
761 qlcnic_83xx_process_aen(adapter);
7f966452
SC		 762 mbx_val = QLCRDX(ahw, QLCNIC_HOST_MBX_CTRL);
763 if (mbx_val)
764 goto poll;
65ab999d
JK		 765 }
766 mbx_err_code = QLCNIC_MBX_STATUS(fw_data);
767 rsp_num = QLCNIC_MBX_NUM_REGS(fw_data);
768 opcode = QLCNIC_MBX_RSP(fw_data);
769 qlcnic_83xx_get_mbx_data(adapter, cmd);
770
771 switch (mbx_err_code) {
772 case QLCNIC_MBX_RSP_OK:
773 case QLCNIC_MBX_PORT_RSP_OK:
7f966452 774 rsp = QLCNIC_RCODE_SUCCESS;
65ab999d
JK		 775 break;
776 default:
7f966452 777 if (opcode == QLCNIC_CMD_CONFIG_MAC_VLAN) {
65ab999d
JK		 778 rsp = qlcnic_83xx_mac_rcode(adapter);
779 if (!rsp)
7f966452 780 goto out;
7f966452 781 }
65ab999d
JK		 782 dev_err(&adapter->pdev->dev,
783 "MBX command 0x%x failed with err:0x%x\n",
784 opcode, mbx_err_code);
7f966452
SC		 785 rsp = mbx_err_code;
786 qlcnic_dump_mbx(adapter, cmd);
65ab999d 787 break;
7f966452 788 }
65ab999d 789 goto out;
7f966452 790 }
65ab999d
JK		 791
792 dev_err(&adapter->pdev->dev, "MBX command 0x%x timed out\n",
793 QLCNIC_MBX_RSP(mbx_cmd));
794 rsp = QLCNIC_RCODE_TIMEOUT;
7f966452
SC		 795out:
796 /* clear fw mbx control register */
797 QLCWRX(ahw, QLCNIC_FW_MBX_CTRL, QLCNIC_CLR_OWNER);
ac166700 798 spin_unlock_irqrestore(&adapter->ahw->mbx_lock, flags);
7f966452
SC		 799 return rsp;
800}
801
802int qlcnic_83xx_alloc_mbx_args(struct qlcnic_cmd_args *mbx,
803 struct qlcnic_adapter *adapter, u32 type)
804{
805 int i, size;
806 u32 temp;
807 const struct qlcnic_mailbox_metadata *mbx_tbl;
808
809 mbx_tbl = qlcnic_83xx_mbx_tbl;
810 size = ARRAY_SIZE(qlcnic_83xx_mbx_tbl);
811 for (i = 0; i < size; i++) {
812 if (type == mbx_tbl[i].cmd) {
f197a7aa 813 mbx->op_type = QLC_83XX_FW_MBX_CMD;
7f966452
SC		 814 mbx->req.num = mbx_tbl[i].in_args;
815 mbx->rsp.num = mbx_tbl[i].out_args;
816 mbx->req.arg = kcalloc(mbx->req.num, sizeof(u32),
817 GFP_ATOMIC);
818 if (!mbx->req.arg)
819 return -ENOMEM;
820 mbx->rsp.arg = kcalloc(mbx->rsp.num, sizeof(u32),
821 GFP_ATOMIC);
822 if (!mbx->rsp.arg) {
823 kfree(mbx->req.arg);
824 mbx->req.arg = NULL;
825 return -ENOMEM;
826 }
827 memset(mbx->req.arg, 0, sizeof(u32) * mbx->req.num);
828 memset(mbx->rsp.arg, 0, sizeof(u32) * mbx->rsp.num);
829 temp = adapter->ahw->fw_hal_version << 29;
830 mbx->req.arg[0] = (type | (mbx->req.num << 16) | temp);
f197a7aa 831 return 0;
7f966452
SC		 832 }
833 }
f197a7aa 834 return -EINVAL;
7f966452
SC		 835}
836
837void qlcnic_83xx_idc_aen_work(struct work_struct *work)
838{
839 struct qlcnic_adapter *adapter;
840 struct qlcnic_cmd_args cmd;
841 int i, err = 0;
842
843 adapter = container_of(work, struct qlcnic_adapter, idc_aen_work.work);
844 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_IDC_ACK);
845
846 for (i = 1; i < QLC_83XX_MBX_AEN_CNT; i++)
847 cmd.req.arg[i] = adapter->ahw->mbox_aen[i];
848
849 err = qlcnic_issue_cmd(adapter, &cmd);
850 if (err)
851 dev_info(&adapter->pdev->dev,
852 "%s: Mailbox IDC ACK failed.\n", __func__);
853 qlcnic_free_mbx_args(&cmd);
854}
855
856static void qlcnic_83xx_handle_idc_comp_aen(struct qlcnic_adapter *adapter,
857 u32 data[])
858{
859 dev_dbg(&adapter->pdev->dev, "Completion AEN:0x%x.\n",
860 QLCNIC_MBX_RSP(data[0]));
629263ac 861 clear_bit(QLC_83XX_IDC_COMP_AEN, &adapter->ahw->idc.status);
7f966452
SC		 862 return;
863}
864
865void qlcnic_83xx_process_aen(struct qlcnic_adapter *adapter)
866{
483202d5 867 u32 event[QLC_83XX_MBX_AEN_CNT];
7f966452
SC		 868 int i;
869 struct qlcnic_hardware_context *ahw = adapter->ahw;
870
7f966452
SC		 871 for (i = 0; i < QLC_83XX_MBX_AEN_CNT; i++)
872 event[i] = readl(QLCNIC_MBX_FW(ahw, i));
873
874 switch (QLCNIC_MBX_RSP(event[0])) {
875
876 case QLCNIC_MBX_LINK_EVENT:
877 qlcnic_83xx_handle_link_aen(adapter, event);
878 break;
879 case QLCNIC_MBX_COMP_EVENT:
880 qlcnic_83xx_handle_idc_comp_aen(adapter, event);
881 break;
882 case QLCNIC_MBX_REQUEST_EVENT:
883 for (i = 0; i < QLC_83XX_MBX_AEN_CNT; i++)
884 adapter->ahw->mbox_aen[i] = QLCNIC_MBX_RSP(event[i]);
885 queue_delayed_work(adapter->qlcnic_wq,
886 &adapter->idc_aen_work, 0);
887 break;
888 case QLCNIC_MBX_TIME_EXTEND_EVENT:
889 break;
f197a7aa
RB		 890 case QLCNIC_MBX_BC_EVENT:
891 qlcnic_sriov_handle_bc_event(adapter, event[1]);
892 break;
7f966452
SC		 893 case QLCNIC_MBX_SFP_INSERT_EVENT:
894 dev_info(&adapter->pdev->dev, "SFP+ Insert AEN:0x%x.\n",
895 QLCNIC_MBX_RSP(event[0]));
896 break;
897 case QLCNIC_MBX_SFP_REMOVE_EVENT:
898 dev_info(&adapter->pdev->dev, "SFP Removed AEN:0x%x.\n",
899 QLCNIC_MBX_RSP(event[0]));
900 break;
901 default:
902 dev_dbg(&adapter->pdev->dev, "Unsupported AEN:0x%x.\n",
903 QLCNIC_MBX_RSP(event[0]));
904 break;
905 }
906
907 QLCWRX(ahw, QLCNIC_FW_MBX_CTRL, QLCNIC_CLR_OWNER);
7f966452
SC		 908}
909
910static int qlcnic_83xx_add_rings(struct qlcnic_adapter *adapter)
911{
912 int index, i, err, sds_mbx_size;
913 u32 *buf, intrpt_id, intr_mask;
914 u16 context_id;
915 u8 num_sds;
916 struct qlcnic_cmd_args cmd;
917 struct qlcnic_host_sds_ring *sds;
918 struct qlcnic_sds_mbx sds_mbx;
919 struct qlcnic_add_rings_mbx_out *mbx_out;
920 struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
921 struct qlcnic_hardware_context *ahw = adapter->ahw;
922
923 sds_mbx_size = sizeof(struct qlcnic_sds_mbx);
924 context_id = recv_ctx->context_id;
925 num_sds = (adapter->max_sds_rings - QLCNIC_MAX_RING_SETS);
926 ahw->hw_ops->alloc_mbx_args(&cmd, adapter,
927 QLCNIC_CMD_ADD_RCV_RINGS);
928 cmd.req.arg[1] = 0 | (num_sds << 8) | (context_id << 16);
929
930 /* set up status rings, mbx 2-81 */
931 index = 2;
932 for (i = 8; i < adapter->max_sds_rings; i++) {
933 memset(&sds_mbx, 0, sds_mbx_size);
934 sds = &recv_ctx->sds_rings[i];
935 sds->consumer = 0;
936 memset(sds->desc_head, 0, STATUS_DESC_RINGSIZE(sds));
a96227e6
SS		 937 sds_mbx.phy_addr_low = LSD(sds->phys_addr);
938 sds_mbx.phy_addr_high = MSD(sds->phys_addr);
7f966452
SC		 939 sds_mbx.sds_ring_size = sds->num_desc;
940
941 if (adapter->flags & QLCNIC_MSIX_ENABLED)
942 intrpt_id = ahw->intr_tbl[i].id;
943 else
944 intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
945
946 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
947 sds_mbx.intrpt_id = intrpt_id;
948 else
949 sds_mbx.intrpt_id = 0xffff;
950 sds_mbx.intrpt_val = 0;
951 buf = &cmd.req.arg[index];
952 memcpy(buf, &sds_mbx, sds_mbx_size);
953 index += sds_mbx_size / sizeof(u32);
954 }
955
956 /* send the mailbox command */
957 err = ahw->hw_ops->mbx_cmd(adapter, &cmd);
958 if (err) {
959 dev_err(&adapter->pdev->dev,
960 "Failed to add rings %d\n", err);
961 goto out;
962 }
963
964 mbx_out = (struct qlcnic_add_rings_mbx_out *)&cmd.rsp.arg[1];
965 index = 0;
966 /* status descriptor ring */
967 for (i = 8; i < adapter->max_sds_rings; i++) {
968 sds = &recv_ctx->sds_rings[i];
969 sds->crb_sts_consumer = ahw->pci_base0 +
970 mbx_out->host_csmr[index];
971 if (adapter->flags & QLCNIC_MSIX_ENABLED)
972 intr_mask = ahw->intr_tbl[i].src;
973 else
974 intr_mask = QLCRDX(ahw, QLCNIC_DEF_INT_MASK);
975
976 sds->crb_intr_mask = ahw->pci_base0 + intr_mask;
977 index++;
978 }
979out:
980 qlcnic_free_mbx_args(&cmd);
981 return err;
982}
983
7cb03b23
RB		 984void qlcnic_83xx_del_rx_ctx(struct qlcnic_adapter *adapter)
985{
986 int err;
987 u32 temp = 0;
988 struct qlcnic_cmd_args cmd;
989 struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
990
991 if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_RX_CTX))
992 return;
993
994 if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
995 cmd.req.arg[0] |= (0x3 << 29);
996
997 if (qlcnic_sriov_pf_check(adapter))
998 qlcnic_pf_set_interface_id_del_rx_ctx(adapter, &temp);
999
1000 cmd.req.arg[1] = recv_ctx->context_id | temp;
1001 err = qlcnic_issue_cmd(adapter, &cmd);
1002 if (err)
1003 dev_err(&adapter->pdev->dev,
1004 "Failed to destroy rx ctx in firmware\n");
1005
1006 recv_ctx->state = QLCNIC_HOST_CTX_STATE_FREED;
1007 qlcnic_free_mbx_args(&cmd);
1008}
1009
7f966452
SC		 1010int qlcnic_83xx_create_rx_ctx(struct qlcnic_adapter *adapter)
1011{
1012 int i, err, index, sds_mbx_size, rds_mbx_size;
1013 u8 num_sds, num_rds;
1014 u32 *buf, intrpt_id, intr_mask, cap = 0;
1015 struct qlcnic_host_sds_ring *sds;
1016 struct qlcnic_host_rds_ring *rds;
1017 struct qlcnic_sds_mbx sds_mbx;
1018 struct qlcnic_rds_mbx rds_mbx;
1019 struct qlcnic_cmd_args cmd;
1020 struct qlcnic_rcv_mbx_out *mbx_out;
1021 struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
1022 struct qlcnic_hardware_context *ahw = adapter->ahw;
1023 num_rds = adapter->max_rds_rings;
1024
1025 if (adapter->max_sds_rings <= QLCNIC_MAX_RING_SETS)
1026 num_sds = adapter->max_sds_rings;
1027 else
1028 num_sds = QLCNIC_MAX_RING_SETS;
1029
1030 sds_mbx_size = sizeof(struct qlcnic_sds_mbx);
1031 rds_mbx_size = sizeof(struct qlcnic_rds_mbx);
1032 cap = QLCNIC_CAP0_LEGACY_CONTEXT;
1033
1034 if (adapter->flags & QLCNIC_FW_LRO_MSS_CAP)
1035 cap |= QLC_83XX_FW_CAP_LRO_MSS;
1036
1037 /* set mailbox hdr and capabilities */
1038 qlcnic_alloc_mbx_args(&cmd, adapter,
1039 QLCNIC_CMD_CREATE_RX_CTX);
7cb03b23
RB		 1040
1041 if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1042 cmd.req.arg[0] |= (0x3 << 29);
1043
7f966452
SC		 1044 cmd.req.arg[1] = cap;
1045 cmd.req.arg[5] = 1 | (num_rds << 5) | (num_sds << 8) |
1046 (QLC_83XX_HOST_RDS_MODE_UNIQUE << 16);
7cb03b23
RB		 1047
1048 if (qlcnic_sriov_pf_check(adapter))
1049 qlcnic_pf_set_interface_id_create_rx_ctx(adapter,
1050 &cmd.req.arg[6]);
7f966452
SC		 1051 /* set up status rings, mbx 8-57/87 */
1052 index = QLC_83XX_HOST_SDS_MBX_IDX;
1053 for (i = 0; i < num_sds; i++) {
1054 memset(&sds_mbx, 0, sds_mbx_size);
1055 sds = &recv_ctx->sds_rings[i];
1056 sds->consumer = 0;
1057 memset(sds->desc_head, 0, STATUS_DESC_RINGSIZE(sds));
a96227e6
SS		 1058 sds_mbx.phy_addr_low = LSD(sds->phys_addr);
1059 sds_mbx.phy_addr_high = MSD(sds->phys_addr);
7f966452
SC		 1060 sds_mbx.sds_ring_size = sds->num_desc;
1061 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1062 intrpt_id = ahw->intr_tbl[i].id;
1063 else
1064 intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
1065 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1066 sds_mbx.intrpt_id = intrpt_id;
1067 else
1068 sds_mbx.intrpt_id = 0xffff;
1069 sds_mbx.intrpt_val = 0;
1070 buf = &cmd.req.arg[index];
1071 memcpy(buf, &sds_mbx, sds_mbx_size);
1072 index += sds_mbx_size / sizeof(u32);
1073 }
1074 /* set up receive rings, mbx 88-111/135 */
1075 index = QLCNIC_HOST_RDS_MBX_IDX;
1076 rds = &recv_ctx->rds_rings[0];
1077 rds->producer = 0;
1078 memset(&rds_mbx, 0, rds_mbx_size);
a96227e6
SS		 1079 rds_mbx.phy_addr_reg_low = LSD(rds->phys_addr);
1080 rds_mbx.phy_addr_reg_high = MSD(rds->phys_addr);
7f966452
SC		 1081 rds_mbx.reg_ring_sz = rds->dma_size;
1082 rds_mbx.reg_ring_len = rds->num_desc;
1083 /* Jumbo ring */
1084 rds = &recv_ctx->rds_rings[1];
1085 rds->producer = 0;
a96227e6
SS		 1086 rds_mbx.phy_addr_jmb_low = LSD(rds->phys_addr);
1087 rds_mbx.phy_addr_jmb_high = MSD(rds->phys_addr);
7f966452
SC		 1088 rds_mbx.jmb_ring_sz = rds->dma_size;
1089 rds_mbx.jmb_ring_len = rds->num_desc;
1090 buf = &cmd.req.arg[index];
1091 memcpy(buf, &rds_mbx, rds_mbx_size);
1092
1093 /* send the mailbox command */
1094 err = ahw->hw_ops->mbx_cmd(adapter, &cmd);
1095 if (err) {
1096 dev_err(&adapter->pdev->dev,
1097 "Failed to create Rx ctx in firmware%d\n", err);
1098 goto out;
1099 }
1100 mbx_out = (struct qlcnic_rcv_mbx_out *)&cmd.rsp.arg[1];
1101 recv_ctx->context_id = mbx_out->ctx_id;
1102 recv_ctx->state = mbx_out->state;
1103 recv_ctx->virt_port = mbx_out->vport_id;
1104 dev_info(&adapter->pdev->dev, "Rx Context[%d] Created, state:0x%x\n",
1105 recv_ctx->context_id, recv_ctx->state);
1106 /* Receive descriptor ring */
1107 /* Standard ring */
1108 rds = &recv_ctx->rds_rings[0];
1109 rds->crb_rcv_producer = ahw->pci_base0 +
1110 mbx_out->host_prod[0].reg_buf;
1111 /* Jumbo ring */
1112 rds = &recv_ctx->rds_rings[1];
1113 rds->crb_rcv_producer = ahw->pci_base0 +
1114 mbx_out->host_prod[0].jmb_buf;
1115 /* status descriptor ring */
1116 for (i = 0; i < num_sds; i++) {
1117 sds = &recv_ctx->sds_rings[i];
1118 sds->crb_sts_consumer = ahw->pci_base0 +
1119 mbx_out->host_csmr[i];
1120 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1121 intr_mask = ahw->intr_tbl[i].src;
1122 else
1123 intr_mask = QLCRDX(ahw, QLCNIC_DEF_INT_MASK);
1124 sds->crb_intr_mask = ahw->pci_base0 + intr_mask;
1125 }
1126
1127 if (adapter->max_sds_rings > QLCNIC_MAX_RING_SETS)
1128 err = qlcnic_83xx_add_rings(adapter);
1129out:
1130 qlcnic_free_mbx_args(&cmd);
1131 return err;
1132}
1133
7cb03b23
RB		 1134void qlcnic_83xx_del_tx_ctx(struct qlcnic_adapter *adapter,
1135 struct qlcnic_host_tx_ring *tx_ring)
1136{
1137 struct qlcnic_cmd_args cmd;
1138 u32 temp = 0;
1139
1140 if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_TX_CTX))
1141 return;
1142
1143 if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1144 cmd.req.arg[0] |= (0x3 << 29);
1145
1146 if (qlcnic_sriov_pf_check(adapter))
1147 qlcnic_pf_set_interface_id_del_tx_ctx(adapter, &temp);
1148
1149 cmd.req.arg[1] = tx_ring->ctx_id | temp;
1150 if (qlcnic_issue_cmd(adapter, &cmd))
1151 dev_err(&adapter->pdev->dev,
1152 "Failed to destroy tx ctx in firmware\n");
1153 qlcnic_free_mbx_args(&cmd);
1154}
1155
7f966452
SC		 1156int qlcnic_83xx_create_tx_ctx(struct qlcnic_adapter *adapter,
1157 struct qlcnic_host_tx_ring *tx, int ring)
1158{
1159 int err;
1160 u16 msix_id;
7cb03b23 1161 u32 *buf, intr_mask, temp = 0;
7f966452
SC		 1162 struct qlcnic_cmd_args cmd;
1163 struct qlcnic_tx_mbx mbx;
1164 struct qlcnic_tx_mbx_out *mbx_out;
1165 struct qlcnic_hardware_context *ahw = adapter->ahw;
da6c8063 1166 u32 msix_vector;
7f966452
SC		 1167
1168 /* Reset host resources */
1169 tx->producer = 0;
1170 tx->sw_consumer = 0;
1171 *(tx->hw_consumer) = 0;
1172
1173 memset(&mbx, 0, sizeof(struct qlcnic_tx_mbx));
1174
1175 /* setup mailbox inbox registerss */
a96227e6
SS		 1176 mbx.phys_addr_low = LSD(tx->phys_addr);
1177 mbx.phys_addr_high = MSD(tx->phys_addr);
1178 mbx.cnsmr_index_low = LSD(tx->hw_cons_phys_addr);
1179 mbx.cnsmr_index_high = MSD(tx->hw_cons_phys_addr);
7f966452 1180 mbx.size = tx->num_desc;
da6c8063
RB		 1181 if (adapter->flags & QLCNIC_MSIX_ENABLED) {
1182 if (!(adapter->flags & QLCNIC_TX_INTR_SHARED))
1183 msix_vector = adapter->max_sds_rings + ring;
1184 else
1185 msix_vector = adapter->max_sds_rings - 1;
1186 msix_id = ahw->intr_tbl[msix_vector].id;
1187 } else {
7f966452 1188 msix_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
da6c8063
RB		 1189 }
1190
7f966452
SC		 1191 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1192 mbx.intr_id = msix_id;
1193 else
1194 mbx.intr_id = 0xffff;
1195 mbx.src = 0;
1196
1197 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CREATE_TX_CTX);
7cb03b23
RB		 1198
1199 if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1200 cmd.req.arg[0] |= (0x3 << 29);
1201
1202 if (qlcnic_sriov_pf_check(adapter))
1203 qlcnic_pf_set_interface_id_create_tx_ctx(adapter, &temp);
1204
7f966452 1205 cmd.req.arg[1] = QLCNIC_CAP0_LEGACY_CONTEXT;
7cb03b23 1206 cmd.req.arg[5] = QLCNIC_MAX_TX_QUEUES | temp;
7f966452
SC		 1207 buf = &cmd.req.arg[6];
1208 memcpy(buf, &mbx, sizeof(struct qlcnic_tx_mbx));
1209 /* send the mailbox command*/
1210 err = qlcnic_issue_cmd(adapter, &cmd);
1211 if (err) {
1212 dev_err(&adapter->pdev->dev,
1213 "Failed to create Tx ctx in firmware 0x%x\n", err);
1214 goto out;
1215 }
1216 mbx_out = (struct qlcnic_tx_mbx_out *)&cmd.rsp.arg[2];
1217 tx->crb_cmd_producer = ahw->pci_base0 + mbx_out->host_prod;
1218 tx->ctx_id = mbx_out->ctx_id;
da6c8063
RB		 1219 if ((adapter->flags & QLCNIC_MSIX_ENABLED) &&
1220 !(adapter->flags & QLCNIC_TX_INTR_SHARED)) {
7f966452
SC		 1221 intr_mask = ahw->intr_tbl[adapter->max_sds_rings + ring].src;
1222 tx->crb_intr_mask = ahw->pci_base0 + intr_mask;
1223 }
1224 dev_info(&adapter->pdev->dev, "Tx Context[0x%x] Created, state:0x%x\n",
1225 tx->ctx_id, mbx_out->state);
1226out:
1227 qlcnic_free_mbx_args(&cmd);
1228 return err;
1229}
1230
ba4468db
JK		 1231static int qlcnic_83xx_diag_alloc_res(struct net_device *netdev, int test)
1232{
1233 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1234 struct qlcnic_host_sds_ring *sds_ring;
1235 struct qlcnic_host_rds_ring *rds_ring;
1236 u8 ring;
1237 int ret;
1238
1239 netif_device_detach(netdev);
1240
1241 if (netif_running(netdev))
1242 __qlcnic_down(adapter, netdev);
1243
1244 qlcnic_detach(adapter);
1245
1246 adapter->max_sds_rings = 1;
1247 adapter->ahw->diag_test = test;
1248 adapter->ahw->linkup = 0;
1249
1250 ret = qlcnic_attach(adapter);
1251 if (ret) {
1252 netif_device_attach(netdev);
1253 return ret;
1254 }
1255
1256 ret = qlcnic_fw_create_ctx(adapter);
1257 if (ret) {
1258 qlcnic_detach(adapter);
1259 netif_device_attach(netdev);
1260 return ret;
1261 }
1262
1263 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
1264 rds_ring = &adapter->recv_ctx->rds_rings[ring];
1265 qlcnic_post_rx_buffers(adapter, rds_ring, ring);
1266 }
1267
1268 if (adapter->ahw->diag_test == QLCNIC_INTERRUPT_TEST) {
1269 for (ring = 0; ring < adapter->max_sds_rings; ring++) {
1270 sds_ring = &adapter->recv_ctx->sds_rings[ring];
1271 qlcnic_83xx_enable_intr(adapter, sds_ring);
1272 }
1273 }
1274
1275 if (adapter->ahw->diag_test == QLCNIC_LOOPBACK_TEST) {
1276 /* disable and free mailbox interrupt */
1277 qlcnic_83xx_free_mbx_intr(adapter);
1278 adapter->ahw->loopback_state = 0;
1279 adapter->ahw->hw_ops->setup_link_event(adapter, 1);
1280 }
1281
1282 set_bit(__QLCNIC_DEV_UP, &adapter->state);
1283 return 0;
1284}
1285
1286static void qlcnic_83xx_diag_free_res(struct net_device *netdev,
1287 int max_sds_rings)
1288{
1289 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1290 struct qlcnic_host_sds_ring *sds_ring;
1291 int ring, err;
1292
1293 clear_bit(__QLCNIC_DEV_UP, &adapter->state);
1294 if (adapter->ahw->diag_test == QLCNIC_INTERRUPT_TEST) {
1295 for (ring = 0; ring < adapter->max_sds_rings; ring++) {
1296 sds_ring = &adapter->recv_ctx->sds_rings[ring];
ac166700 1297 qlcnic_83xx_disable_intr(adapter, sds_ring);
ba4468db
JK		 1298 }
1299 }
1300
1301 qlcnic_fw_destroy_ctx(adapter);
1302 qlcnic_detach(adapter);
1303
1304 if (adapter->ahw->diag_test == QLCNIC_LOOPBACK_TEST) {
1305 err = qlcnic_83xx_setup_mbx_intr(adapter);
1306 if (err) {
1307 dev_err(&adapter->pdev->dev,
1308 "%s: failed to setup mbx interrupt\n",
1309 __func__);
1310 goto out;
1311 }
1312 }
1313 adapter->ahw->diag_test = 0;
1314 adapter->max_sds_rings = max_sds_rings;
1315
1316 if (qlcnic_attach(adapter))
1317 goto out;
1318
1319 if (netif_running(netdev))
1320 __qlcnic_up(adapter, netdev);
1321out:
1322 netif_device_attach(netdev);
1323}
1324
319ecf12
SC		 1325int qlcnic_83xx_config_led(struct qlcnic_adapter *adapter, u32 state,
1326 u32 beacon)
1327{
1328 struct qlcnic_cmd_args cmd;
1329 u32 mbx_in;
1330 int i, status = 0;
1331
1332 if (state) {
1333 /* Get LED configuration */
1334 qlcnic_alloc_mbx_args(&cmd, adapter,
1335 QLCNIC_CMD_GET_LED_CONFIG);
1336 status = qlcnic_issue_cmd(adapter, &cmd);
1337 if (status) {
1338 dev_err(&adapter->pdev->dev,
1339 "Get led config failed.\n");
1340 goto mbx_err;
1341 } else {
1342 for (i = 0; i < 4; i++)
1343 adapter->ahw->mbox_reg[i] = cmd.rsp.arg[i+1];
1344 }
1345 qlcnic_free_mbx_args(&cmd);
1346 /* Set LED Configuration */
1347 mbx_in = (LSW(QLC_83XX_LED_CONFIG) << 16) |
1348 LSW(QLC_83XX_LED_CONFIG);
1349 qlcnic_alloc_mbx_args(&cmd, adapter,
1350 QLCNIC_CMD_SET_LED_CONFIG);
1351 cmd.req.arg[1] = mbx_in;
1352 cmd.req.arg[2] = mbx_in;
1353 cmd.req.arg[3] = mbx_in;
1354 if (beacon)
1355 cmd.req.arg[4] = QLC_83XX_ENABLE_BEACON;
1356 status = qlcnic_issue_cmd(adapter, &cmd);
1357 if (status) {
1358 dev_err(&adapter->pdev->dev,
1359 "Set led config failed.\n");
1360 }
1361mbx_err:
1362 qlcnic_free_mbx_args(&cmd);
1363 return status;
1364
1365 } else {
1366 /* Restoring default LED configuration */
1367 qlcnic_alloc_mbx_args(&cmd, adapter,
1368 QLCNIC_CMD_SET_LED_CONFIG);
1369 cmd.req.arg[1] = adapter->ahw->mbox_reg[0];
1370 cmd.req.arg[2] = adapter->ahw->mbox_reg[1];
1371 cmd.req.arg[3] = adapter->ahw->mbox_reg[2];
1372 if (beacon)
1373 cmd.req.arg[4] = adapter->ahw->mbox_reg[3];
1374 status = qlcnic_issue_cmd(adapter, &cmd);
1375 if (status)
1376 dev_err(&adapter->pdev->dev,
1377 "Restoring led config failed.\n");
1378 qlcnic_free_mbx_args(&cmd);
1379 return status;
1380 }
1381}
1382
d16951d9
HM		 1383int qlcnic_83xx_set_led(struct net_device *netdev,
1384 enum ethtool_phys_id_state state)
1385{
1386 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1387 int err = -EIO, active = 1;
1388
1389 if (adapter->ahw->op_mode == QLCNIC_NON_PRIV_FUNC) {
1390 netdev_warn(netdev,
1391 "LED test is not supported in non-privileged mode\n");
1392 return -EOPNOTSUPP;
1393 }
1394
1395 switch (state) {
1396 case ETHTOOL_ID_ACTIVE:
1397 if (test_and_set_bit(__QLCNIC_LED_ENABLE, &adapter->state))
1398 return -EBUSY;
1399
1400 if (test_bit(__QLCNIC_RESETTING, &adapter->state))
1401 break;
1402
1403 err = qlcnic_83xx_config_led(adapter, active, 0);
1404 if (err)
1405 netdev_err(netdev, "Failed to set LED blink state\n");
1406 break;
1407 case ETHTOOL_ID_INACTIVE:
1408 active = 0;
1409
1410 if (test_bit(__QLCNIC_RESETTING, &adapter->state))
1411 break;
1412
1413 err = qlcnic_83xx_config_led(adapter, active, 0);
1414 if (err)
1415 netdev_err(netdev, "Failed to reset LED blink state\n");
1416 break;
1417
1418 default:
1419 return -EINVAL;
1420 }
1421
1422 if (!active || err)
1423 clear_bit(__QLCNIC_LED_ENABLE, &adapter->state);
1424
1425 return err;
1426}
1427
7f966452
SC		 1428void qlcnic_83xx_register_nic_idc_func(struct qlcnic_adapter *adapter,
1429 int enable)
1430{
1431 struct qlcnic_cmd_args cmd;
1432 int status;
1433
f8468331
RB		 1434 if (qlcnic_sriov_vf_check(adapter))
1435 return;
1436
7f966452
SC		 1437 if (enable) {
1438 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_INIT_NIC_FUNC);
d5fcff04 1439 cmd.req.arg[1] = BIT_0 | BIT_31;
7f966452
SC		 1440 } else {
1441 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_STOP_NIC_FUNC);
d5fcff04 1442 cmd.req.arg[1] = BIT_0 | BIT_31;
7f966452
SC		 1443 }
1444 status = qlcnic_issue_cmd(adapter, &cmd);
1445 if (status)
1446 dev_err(&adapter->pdev->dev,
1447 "Failed to %s in NIC IDC function event.\n",
1448 (enable ? "register" : "unregister"));
1449
1450 qlcnic_free_mbx_args(&cmd);
1451}
1452
1453int qlcnic_83xx_set_port_config(struct qlcnic_adapter *adapter)
1454{
1455 struct qlcnic_cmd_args cmd;
1456 int err;
1457
1458 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_PORT_CONFIG);
1459 cmd.req.arg[1] = adapter->ahw->port_config;
1460 err = qlcnic_issue_cmd(adapter, &cmd);
1461 if (err)
1462 dev_info(&adapter->pdev->dev, "Set Port Config failed.\n");
1463 qlcnic_free_mbx_args(&cmd);
1464 return err;
1465}
1466
1467int qlcnic_83xx_get_port_config(struct qlcnic_adapter *adapter)
1468{
1469 struct qlcnic_cmd_args cmd;
1470 int err;
1471
1472 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PORT_CONFIG);
1473 err = qlcnic_issue_cmd(adapter, &cmd);
1474 if (err)
1475 dev_info(&adapter->pdev->dev, "Get Port config failed\n");
1476 else
1477 adapter->ahw->port_config = cmd.rsp.arg[1];
1478 qlcnic_free_mbx_args(&cmd);
1479 return err;
1480}
1481
1482int qlcnic_83xx_setup_link_event(struct qlcnic_adapter *adapter, int enable)
1483{
1484 int err;
1485 u32 temp;
1486 struct qlcnic_cmd_args cmd;
1487
1488 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LINK_EVENT);
1489 temp = adapter->recv_ctx->context_id << 16;
1490 cmd.req.arg[1] = (enable ? 1 : 0) | BIT_8 | temp;
1491 err = qlcnic_issue_cmd(adapter, &cmd);
1492 if (err)
1493 dev_info(&adapter->pdev->dev,
1494 "Setup linkevent mailbox failed\n");
1495 qlcnic_free_mbx_args(&cmd);
1496 return err;
1497}
1498
7cb03b23
RB		 1499static void qlcnic_83xx_set_interface_id_promisc(struct qlcnic_adapter *adapter,
1500 u32 *interface_id)
1501{
1502 if (qlcnic_sriov_pf_check(adapter)) {
1503 qlcnic_pf_set_interface_id_promisc(adapter, interface_id);
1504 } else {
1505 if (!qlcnic_sriov_vf_check(adapter))
1506 *interface_id = adapter->recv_ctx->context_id << 16;
1507 }
1508}
1509
7f966452
SC		 1510int qlcnic_83xx_nic_set_promisc(struct qlcnic_adapter *adapter, u32 mode)
1511{
1512 int err;
7cb03b23 1513 u32 temp = 0;
7f966452
SC		 1514 struct qlcnic_cmd_args cmd;
1515
1516 if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
1517 return -EIO;
1518
1519 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIGURE_MAC_RX_MODE);
7cb03b23 1520 qlcnic_83xx_set_interface_id_promisc(adapter, &temp);
7f966452
SC		 1521 cmd.req.arg[1] = (mode ? 1 : 0) | temp;
1522 err = qlcnic_issue_cmd(adapter, &cmd);
1523 if (err)
1524 dev_info(&adapter->pdev->dev,
1525 "Promiscous mode config failed\n");
7f966452 1526
7cb03b23 1527 qlcnic_free_mbx_args(&cmd);
7f966452
SC		 1528 return err;
1529}
1530
ba4468db
JK		 1531int qlcnic_83xx_loopback_test(struct net_device *netdev, u8 mode)
1532{
1533 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1534 struct qlcnic_hardware_context *ahw = adapter->ahw;
1535 int ret = 0, loop = 0, max_sds_rings = adapter->max_sds_rings;
1536
1537 QLCDB(adapter, DRV, "%s loopback test in progress\n",
1538 mode == QLCNIC_ILB_MODE ? "internal" : "external");
1539 if (ahw->op_mode == QLCNIC_NON_PRIV_FUNC) {
1540 dev_warn(&adapter->pdev->dev,
1541 "Loopback test not supported for non privilege function\n");
1542 return ret;
1543 }
1544
1545 if (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))
1546 return -EBUSY;
1547
1548 ret = qlcnic_83xx_diag_alloc_res(netdev, QLCNIC_LOOPBACK_TEST);
1549 if (ret)
1550 goto fail_diag_alloc;
1551
1552 ret = qlcnic_83xx_set_lb_mode(adapter, mode);
1553 if (ret)
1554 goto free_diag_res;
1555
1556 /* Poll for link up event before running traffic */
1557 do {
1558 msleep(500);
1559 qlcnic_83xx_process_aen(adapter);
1560 if (loop++ > QLCNIC_ILB_MAX_RCV_LOOP) {
1561 dev_info(&adapter->pdev->dev,
1562 "Firmware didn't sent link up event to loopback request\n");
1563 ret = -QLCNIC_FW_NOT_RESPOND;
1564 qlcnic_83xx_clear_lb_mode(adapter, mode);
1565 goto free_diag_res;
1566 }
1567 } while ((adapter->ahw->linkup && ahw->has_link_events) != 1);
1568
1569 ret = qlcnic_do_lb_test(adapter, mode);
1570
1571 qlcnic_83xx_clear_lb_mode(adapter, mode);
1572
1573free_diag_res:
1574 qlcnic_83xx_diag_free_res(netdev, max_sds_rings);
1575
1576fail_diag_alloc:
1577 adapter->max_sds_rings = max_sds_rings;
1578 clear_bit(__QLCNIC_RESETTING, &adapter->state);
1579 return ret;
1580}
1581
7f966452
SC		 1582int qlcnic_83xx_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
1583{
1584 struct qlcnic_hardware_context *ahw = adapter->ahw;
629263ac 1585 int status = 0, loop = 0;
7f966452
SC		 1586 u32 config;
1587
1588 status = qlcnic_83xx_get_port_config(adapter);
1589 if (status)
1590 return status;
1591
1592 config = ahw->port_config;
629263ac 1593 set_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
7f966452
SC		 1594
1595 if (mode == QLCNIC_ILB_MODE)
1596 ahw->port_config |= QLC_83XX_CFG_LOOPBACK_HSS;
1597 if (mode == QLCNIC_ELB_MODE)
1598 ahw->port_config |= QLC_83XX_CFG_LOOPBACK_EXT;
1599
1600 status = qlcnic_83xx_set_port_config(adapter);
1601 if (status) {
1602 dev_err(&adapter->pdev->dev,
1603 "Failed to Set Loopback Mode = 0x%x.\n",
1604 ahw->port_config);
1605 ahw->port_config = config;
629263ac 1606 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
7f966452
SC		 1607 return status;
1608 }
1609
9a05f92b 1610 /* Wait for Link and IDC Completion AEN */
629263ac
SC		 1611 do {
1612 msleep(300);
9a05f92b 1613 qlcnic_83xx_process_aen(adapter);
629263ac
SC		 1614 if (loop++ > QLCNIC_ILB_MAX_RCV_LOOP) {
1615 dev_err(&adapter->pdev->dev,
1616 "FW did not generate IDC completion AEN\n");
1617 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
9a05f92b 1618 qlcnic_83xx_clear_lb_mode(adapter, mode);
629263ac
SC		 1619 return -EIO;
1620 }
1621 } while (test_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status));
1622
7f966452
SC		 1623 qlcnic_sre_macaddr_change(adapter, adapter->mac_addr, 0,
1624 QLCNIC_MAC_ADD);
1625 return status;
1626}
1627
1628int qlcnic_83xx_clear_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
1629{
1630 struct qlcnic_hardware_context *ahw = adapter->ahw;
629263ac 1631 int status = 0, loop = 0;
7f966452
SC		 1632 u32 config = ahw->port_config;
1633
629263ac 1634 set_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
7f966452
SC		 1635 if (mode == QLCNIC_ILB_MODE)
1636 ahw->port_config &= ~QLC_83XX_CFG_LOOPBACK_HSS;
1637 if (mode == QLCNIC_ELB_MODE)
1638 ahw->port_config &= ~QLC_83XX_CFG_LOOPBACK_EXT;
1639
1640 status = qlcnic_83xx_set_port_config(adapter);
1641 if (status) {
1642 dev_err(&adapter->pdev->dev,
1643 "Failed to Clear Loopback Mode = 0x%x.\n",
1644 ahw->port_config);
1645 ahw->port_config = config;
629263ac 1646 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
7f966452
SC		 1647 return status;
1648 }
1649
9a05f92b 1650 /* Wait for Link and IDC Completion AEN */
629263ac
SC		 1651 do {
1652 msleep(300);
9a05f92b 1653 qlcnic_83xx_process_aen(adapter);
629263ac
SC		 1654 if (loop++ > QLCNIC_ILB_MAX_RCV_LOOP) {
1655 dev_err(&adapter->pdev->dev,
1656 "Firmware didn't sent IDC completion AEN\n");
1657 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1658 return -EIO;
1659 }
1660 } while (test_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status));
1661
7f966452
SC		 1662 qlcnic_sre_macaddr_change(adapter, adapter->mac_addr, 0,
1663 QLCNIC_MAC_DEL);
1664 return status;
1665}
1666
7cb03b23
RB		 1667static void qlcnic_83xx_set_interface_id_ipaddr(struct qlcnic_adapter *adapter,
1668 u32 *interface_id)
1669{
1670 if (qlcnic_sriov_pf_check(adapter)) {
1671 qlcnic_pf_set_interface_id_ipaddr(adapter, interface_id);
1672 } else {
1673 if (!qlcnic_sriov_vf_check(adapter))
1674 *interface_id = adapter->recv_ctx->context_id << 16;
1675 }
1676}
1677
7f966452
SC		 1678void qlcnic_83xx_config_ipaddr(struct qlcnic_adapter *adapter, __be32 ip,
1679 int mode)
1680{
1681 int err;
7cb03b23 1682 u32 temp = 0, temp_ip;
7f966452
SC		 1683 struct qlcnic_cmd_args cmd;
1684
1685 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIGURE_IP_ADDR);
7cb03b23
RB		 1686 qlcnic_83xx_set_interface_id_ipaddr(adapter, &temp);
1687
1688 if (mode == QLCNIC_IP_UP)
7f966452 1689 cmd.req.arg[1] = 1 | temp;
7cb03b23 1690 else
7f966452 1691 cmd.req.arg[1] = 2 | temp;
7f966452 1692
283c1c68
M		 1693 /*
1694 * Adapter needs IP address in network byte order.
1695 * But hardware mailbox registers go through writel(), hence IP address
1696 * gets swapped on big endian architecture.
1697 * To negate swapping of writel() on big endian architecture
1698 * use swab32(value).
1699 */
1700
1701 temp_ip = swab32(ntohl(ip));
1702 memcpy(&cmd.req.arg[2], &temp_ip, sizeof(u32));
7f966452
SC		 1703 err = qlcnic_issue_cmd(adapter, &cmd);
1704 if (err != QLCNIC_RCODE_SUCCESS)
1705 dev_err(&adapter->netdev->dev,
1706 "could not notify %s IP 0x%x request\n",
1707 (mode == QLCNIC_IP_UP) ? "Add" : "Remove", ip);
7cb03b23 1708
7f966452
SC		 1709 qlcnic_free_mbx_args(&cmd);
1710}
1711
1712int qlcnic_83xx_config_hw_lro(struct qlcnic_adapter *adapter, int mode)
1713{
1714 int err;
1715 u32 temp, arg1;
1716 struct qlcnic_cmd_args cmd;
283c1c68
M		 1717 int lro_bit_mask;
1718
1719 lro_bit_mask = (mode ? (BIT_0 | BIT_1 | BIT_2 | BIT_3) : 0);
7f966452
SC		 1720
1721 if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
1722 return 0;
1723
1724 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIGURE_HW_LRO);
1725 temp = adapter->recv_ctx->context_id << 16;
283c1c68 1726 arg1 = lro_bit_mask | temp;
7f966452
SC		 1727 cmd.req.arg[1] = arg1;
1728
1729 err = qlcnic_issue_cmd(adapter, &cmd);
1730 if (err)
1731 dev_info(&adapter->pdev->dev, "LRO config failed\n");
1732 qlcnic_free_mbx_args(&cmd);
1733
1734 return err;
1735}
1736
1737int qlcnic_83xx_config_rss(struct qlcnic_adapter *adapter, int enable)
1738{
1739 int err;
1740 u32 word;
1741 struct qlcnic_cmd_args cmd;
1742 const u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
1743 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
1744 0x255b0ec26d5a56daULL };
1745
1746 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIGURE_RSS);
1747
1748 /*
1749 * RSS request:
1750 * bits 3-0: Rsvd
1751 * 5-4: hash_type_ipv4
1752 * 7-6: hash_type_ipv6
1753 * 8: enable
1754 * 9: use indirection table
1755 * 16-31: indirection table mask
1756 */
1757 word = ((u32)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
1758 ((u32)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
1759 ((u32)(enable & 0x1) << 8) |
1760 ((0x7ULL) << 16);
1761 cmd.req.arg[1] = (adapter->recv_ctx->context_id);
1762 cmd.req.arg[2] = word;
1763 memcpy(&cmd.req.arg[4], key, sizeof(key));
1764
1765 err = qlcnic_issue_cmd(adapter, &cmd);
1766
1767 if (err)
1768 dev_info(&adapter->pdev->dev, "RSS config failed\n");
1769 qlcnic_free_mbx_args(&cmd);
1770
1771 return err;
1772
1773}
1774
7cb03b23
RB		 1775static void qlcnic_83xx_set_interface_id_macaddr(struct qlcnic_adapter *adapter,
1776 u32 *interface_id)
1777{
1778 if (qlcnic_sriov_pf_check(adapter)) {
1779 qlcnic_pf_set_interface_id_macaddr(adapter, interface_id);
1780 } else {
1781 if (!qlcnic_sriov_vf_check(adapter))
1782 *interface_id = adapter->recv_ctx->context_id << 16;
1783 }
1784}
1785
7f966452 1786int qlcnic_83xx_sre_macaddr_change(struct qlcnic_adapter *adapter, u8 *addr,
f80bc8fe 1787 u16 vlan_id, u8 op)
7f966452
SC		 1788{
1789 int err;
7cb03b23 1790 u32 *buf, temp = 0;
7f966452
SC		 1791 struct qlcnic_cmd_args cmd;
1792 struct qlcnic_macvlan_mbx mv;
1793
1794 if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
1795 return -EIO;
1796
1797 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_MAC_VLAN);
1798 if (err)
1799 return err;
7f966452 1800
91b7282b
RB		 1801 if (vlan_id)
1802 op = (op == QLCNIC_MAC_ADD || op == QLCNIC_MAC_VLAN_ADD) ?
1803 QLCNIC_MAC_VLAN_ADD : QLCNIC_MAC_VLAN_DEL;
1804
7cb03b23
RB		 1805 cmd.req.arg[1] = op | (1 << 8);
1806 qlcnic_83xx_set_interface_id_macaddr(adapter, &temp);
1807 cmd.req.arg[1] |= temp;
f80bc8fe 1808 mv.vlan = vlan_id;
a96227e6
SS		 1809 mv.mac_addr0 = addr[0];
1810 mv.mac_addr1 = addr[1];
1811 mv.mac_addr2 = addr[2];
1812 mv.mac_addr3 = addr[3];
1813 mv.mac_addr4 = addr[4];
1814 mv.mac_addr5 = addr[5];
7f966452
SC		 1815 buf = &cmd.req.arg[2];
1816 memcpy(buf, &mv, sizeof(struct qlcnic_macvlan_mbx));
1817 err = qlcnic_issue_cmd(adapter, &cmd);
1818 if (err)
1819 dev_err(&adapter->pdev->dev,
1820 "MAC-VLAN %s to CAM failed, err=%d.\n",
1821 ((op == 1) ? "add " : "delete "), err);
1822 qlcnic_free_mbx_args(&cmd);
1823 return err;
1824}
1825
1826void qlcnic_83xx_change_l2_filter(struct qlcnic_adapter *adapter, u64 *addr,
f80bc8fe 1827 u16 vlan_id)
7f966452
SC		 1828{
1829 u8 mac[ETH_ALEN];
1830 memcpy(&mac, addr, ETH_ALEN);
1831 qlcnic_83xx_sre_macaddr_change(adapter, mac, vlan_id, QLCNIC_MAC_ADD);
1832}
1833
1834void qlcnic_83xx_configure_mac(struct qlcnic_adapter *adapter, u8 *mac,
1835 u8 type, struct qlcnic_cmd_args *cmd)
1836{
1837 switch (type) {
1838 case QLCNIC_SET_STATION_MAC:
1839 case QLCNIC_SET_FAC_DEF_MAC:
1840 memcpy(&cmd->req.arg[2], mac, sizeof(u32));
1841 memcpy(&cmd->req.arg[3], &mac[4], sizeof(u16));
1842 break;
1843 }
1844 cmd->req.arg[1] = type;
1845}
1846
1847int qlcnic_83xx_get_mac_address(struct qlcnic_adapter *adapter, u8 *mac)
1848{
1849 int err, i;
1850 struct qlcnic_cmd_args cmd;
1851 u32 mac_low, mac_high;
1852
1853 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_MAC_ADDRESS);
1854 qlcnic_83xx_configure_mac(adapter, mac, QLCNIC_GET_CURRENT_MAC, &cmd);
1855 err = qlcnic_issue_cmd(adapter, &cmd);
1856
1857 if (err == QLCNIC_RCODE_SUCCESS) {
1858 mac_low = cmd.rsp.arg[1];
1859 mac_high = cmd.rsp.arg[2];
1860
1861 for (i = 0; i < 2; i++)
1862 mac[i] = (u8) (mac_high >> ((1 - i) * 8));
1863 for (i = 2; i < 6; i++)
1864 mac[i] = (u8) (mac_low >> ((5 - i) * 8));
1865 } else {
1866 dev_err(&adapter->pdev->dev, "Failed to get mac address%d\n",
1867 err);
1868 err = -EIO;
1869 }
1870 qlcnic_free_mbx_args(&cmd);
1871 return err;
1872}
1873
1874void qlcnic_83xx_config_intr_coal(struct qlcnic_adapter *adapter)
1875{
1876 int err;
1877 u32 temp;
1878 struct qlcnic_cmd_args cmd;
1879 struct qlcnic_nic_intr_coalesce *coal = &adapter->ahw->coal;
1880
1881 if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
1882 return;
1883
1884 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_INTR_COAL);
1885 cmd.req.arg[1] = 1 | (adapter->recv_ctx->context_id << 16);
1886 cmd.req.arg[3] = coal->flag;
1887 temp = coal->rx_time_us << 16;
1888 cmd.req.arg[2] = coal->rx_packets | temp;
1889 err = qlcnic_issue_cmd(adapter, &cmd);
1890 if (err != QLCNIC_RCODE_SUCCESS)
1891 dev_info(&adapter->pdev->dev,
1892 "Failed to send interrupt coalescence parameters\n");
1893 qlcnic_free_mbx_args(&cmd);
1894}
1895
1896static void qlcnic_83xx_handle_link_aen(struct qlcnic_adapter *adapter,
1897 u32 data[])
1898{
1899 u8 link_status, duplex;
1900 /* link speed */
1901 link_status = LSB(data[3]) & 1;
1902 adapter->ahw->link_speed = MSW(data[2]);
1903 adapter->ahw->link_autoneg = MSB(MSW(data[3]));
1904 adapter->ahw->module_type = MSB(LSW(data[3]));
1905 duplex = LSB(MSW(data[3]));
1906 if (duplex)
1907 adapter->ahw->link_duplex = DUPLEX_FULL;
1908 else
1909 adapter->ahw->link_duplex = DUPLEX_HALF;
1910 adapter->ahw->has_link_events = 1;
1911 qlcnic_advert_link_change(adapter, link_status);
1912}
1913
1914irqreturn_t qlcnic_83xx_handle_aen(int irq, void *data)
1915{
1916 struct qlcnic_adapter *adapter = data;
483202d5
JK		 1917 unsigned long flags;
1918 u32 mask, resp, event;
1919
1920 spin_lock_irqsave(&adapter->ahw->mbx_lock, flags);
1921 resp = QLCRDX(adapter->ahw, QLCNIC_FW_MBX_CTRL);
1922 if (!(resp & QLCNIC_SET_OWNER))
1923 goto out;
ac166700 1924
483202d5
JK		 1925 event = readl(QLCNIC_MBX_FW(adapter->ahw, 0));
1926 if (event & QLCNIC_MBX_ASYNC_EVENT)
1927 qlcnic_83xx_process_aen(adapter);
1928out:
1929 mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
1930 writel(0, adapter->ahw->pci_base0 + mask);
1931 spin_unlock_irqrestore(&adapter->ahw->mbx_lock, flags);
1932
7f966452
SC		 1933 return IRQ_HANDLED;
1934}
1935
1936int qlcnic_enable_eswitch(struct qlcnic_adapter *adapter, u8 port, u8 enable)
1937{
1938 int err = -EIO;
1939 struct qlcnic_cmd_args cmd;
1940
1941 if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC) {
1942 dev_err(&adapter->pdev->dev,
1943 "%s: Error, invoked by non management func\n",
1944 __func__);
1945 return err;
1946 }
1947
1948 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_TOGGLE_ESWITCH);
1949 cmd.req.arg[1] = (port & 0xf) | BIT_4;
1950 err = qlcnic_issue_cmd(adapter, &cmd);
1951
1952 if (err != QLCNIC_RCODE_SUCCESS) {
1953 dev_err(&adapter->pdev->dev, "Failed to enable eswitch%d\n",
1954 err);
1955 err = -EIO;
1956 }
1957 qlcnic_free_mbx_args(&cmd);
1958
1959 return err;
1960
1961}
1962
1963int qlcnic_83xx_set_nic_info(struct qlcnic_adapter *adapter,
1964 struct qlcnic_info *nic)
1965{
1966 int i, err = -EIO;
1967 struct qlcnic_cmd_args cmd;
1968
1969 if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC) {
1970 dev_err(&adapter->pdev->dev,
1971 "%s: Error, invoked by non management func\n",
1972 __func__);
1973 return err;
1974 }
1975
1976 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_NIC_INFO);
1977 cmd.req.arg[1] = (nic->pci_func << 16);
1978 cmd.req.arg[2] = 0x1 << 16;
1979 cmd.req.arg[3] = nic->phys_port | (nic->switch_mode << 16);
1980 cmd.req.arg[4] = nic->capabilities;
1981 cmd.req.arg[5] = (nic->max_mac_filters & 0xFF) | ((nic->max_mtu) << 16);
1982 cmd.req.arg[6] = (nic->max_tx_ques) | ((nic->max_rx_ques) << 16);
1983 cmd.req.arg[7] = (nic->min_tx_bw) | ((nic->max_tx_bw) << 16);
1984 for (i = 8; i < 32; i++)
1985 cmd.req.arg[i] = 0;
1986
1987 err = qlcnic_issue_cmd(adapter, &cmd);
1988
1989 if (err != QLCNIC_RCODE_SUCCESS) {
1990 dev_err(&adapter->pdev->dev, "Failed to set nic info%d\n",
1991 err);
1992 err = -EIO;
1993 }
1994
1995 qlcnic_free_mbx_args(&cmd);
1996
1997 return err;
1998}
1999
2000int qlcnic_83xx_get_nic_info(struct qlcnic_adapter *adapter,
2001 struct qlcnic_info *npar_info, u8 func_id)
2002{
2003 int err;
2004 u32 temp;
2005 u8 op = 0;
2006 struct qlcnic_cmd_args cmd;
2007
2008 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_NIC_INFO);
2009 if (func_id != adapter->ahw->pci_func) {
2010 temp = func_id << 16;
2011 cmd.req.arg[1] = op | BIT_31 | temp;
2012 } else {
2013 cmd.req.arg[1] = adapter->ahw->pci_func << 16;
2014 }
2015 err = qlcnic_issue_cmd(adapter, &cmd);
2016 if (err) {
2017 dev_info(&adapter->pdev->dev,
2018 "Failed to get nic info %d\n", err);
2019 goto out;
2020 }
2021
2022 npar_info->op_type = cmd.rsp.arg[1];
2023 npar_info->pci_func = cmd.rsp.arg[2] & 0xFFFF;
2024 npar_info->op_mode = (cmd.rsp.arg[2] & 0xFFFF0000) >> 16;
2025 npar_info->phys_port = cmd.rsp.arg[3] & 0xFFFF;
2026 npar_info->switch_mode = (cmd.rsp.arg[3] & 0xFFFF0000) >> 16;
2027 npar_info->capabilities = cmd.rsp.arg[4];
2028 npar_info->max_mac_filters = cmd.rsp.arg[5] & 0xFF;
2029 npar_info->max_mtu = (cmd.rsp.arg[5] & 0xFFFF0000) >> 16;
2030 npar_info->max_tx_ques = cmd.rsp.arg[6] & 0xFFFF;
2031 npar_info->max_rx_ques = (cmd.rsp.arg[6] & 0xFFFF0000) >> 16;
2032 npar_info->min_tx_bw = cmd.rsp.arg[7] & 0xFFFF;
2033 npar_info->max_tx_bw = (cmd.rsp.arg[7] & 0xFFFF0000) >> 16;
2034 if (cmd.rsp.arg[8] & 0x1)
2035 npar_info->max_bw_reg_offset = (cmd.rsp.arg[8] & 0x7FFE) >> 1;
2036 if (cmd.rsp.arg[8] & 0x10000) {
2037 temp = (cmd.rsp.arg[8] & 0x7FFE0000) >> 17;
2038 npar_info->max_linkspeed_reg_offset = temp;
2039 }
2040
2041out:
2042 qlcnic_free_mbx_args(&cmd);
2043 return err;
2044}
2045
2046int qlcnic_83xx_get_pci_info(struct qlcnic_adapter *adapter,
2047 struct qlcnic_pci_info *pci_info)
2048{
2049 int i, err = 0, j = 0;
2050 u32 temp;
2051 struct qlcnic_cmd_args cmd;
2052
2053 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PCI_INFO);
2054 err = qlcnic_issue_cmd(adapter, &cmd);
2055
2056 adapter->ahw->act_pci_func = 0;
2057 if (err == QLCNIC_RCODE_SUCCESS) {
2058 pci_info->func_count = cmd.rsp.arg[1] & 0xFF;
2059 dev_info(&adapter->pdev->dev,
2060 "%s: total functions = %d\n",
2061 __func__, pci_info->func_count);
2062 for (i = 2, j = 0; j < QLCNIC_MAX_PCI_FUNC; j++, pci_info++) {
2063 pci_info->id = cmd.rsp.arg[i] & 0xFFFF;
2064 pci_info->active = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2065 i++;
2066 pci_info->type = cmd.rsp.arg[i] & 0xFFFF;
2067 if (pci_info->type == QLCNIC_TYPE_NIC)
2068 adapter->ahw->act_pci_func++;
2069 temp = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2070 pci_info->default_port = temp;
2071 i++;
2072 pci_info->tx_min_bw = cmd.rsp.arg[i] & 0xFFFF;
2073 temp = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2074 pci_info->tx_max_bw = temp;
2075 i = i + 2;
2076 memcpy(pci_info->mac, &cmd.rsp.arg[i], ETH_ALEN - 2);
2077 i++;
2078 memcpy(pci_info->mac + sizeof(u32), &cmd.rsp.arg[i], 2);
2079 i = i + 3;
2080
2081 dev_info(&adapter->pdev->dev, "%s:\n"
2082 "\tid = %d active = %d type = %d\n"
2083 "\tport = %d min bw = %d max bw = %d\n"
2084 "\tmac_addr = %pM\n", __func__,
2085 pci_info->id, pci_info->active, pci_info->type,
2086 pci_info->default_port, pci_info->tx_min_bw,
2087 pci_info->tx_max_bw, pci_info->mac);
2088 }
2089 } else {
2090 dev_err(&adapter->pdev->dev, "Failed to get PCI Info%d\n",
2091 err);
2092 err = -EIO;
2093 }
2094
2095 qlcnic_free_mbx_args(&cmd);
2096
2097 return err;
2098}
2099
2100int qlcnic_83xx_config_intrpt(struct qlcnic_adapter *adapter, bool op_type)
2101{
2102 int i, index, err;
7f966452 2103 u8 max_ints;
e2ab1233 2104 u32 val, temp, type;
7f966452
SC		 2105 struct qlcnic_cmd_args cmd;
2106
7dd90cf1 2107 max_ints = adapter->ahw->num_msix - 1;
7f966452
SC		 2108 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_INTRPT);
2109 cmd.req.arg[1] = max_ints;
7cb03b23
RB		 2110
2111 if (qlcnic_sriov_vf_check(adapter))
2112 cmd.req.arg[1] |= (adapter->ahw->pci_func << 8) | BIT_16;
2113
7f966452
SC		 2114 for (i = 0, index = 2; i < max_ints; i++) {
2115 type = op_type ? QLCNIC_INTRPT_ADD : QLCNIC_INTRPT_DEL;
2116 val = type | (adapter->ahw->intr_tbl[i].type << 4);
2117 if (adapter->ahw->intr_tbl[i].type == QLCNIC_INTRPT_MSIX)
2118 val |= (adapter->ahw->intr_tbl[i].id << 16);
2119 cmd.req.arg[index++] = val;
2120 }
2121 err = qlcnic_issue_cmd(adapter, &cmd);
2122 if (err) {
2123 dev_err(&adapter->pdev->dev,
2124 "Failed to configure interrupts 0x%x\n", err);
2125 goto out;
2126 }
2127
2128 max_ints = cmd.rsp.arg[1];
2129 for (i = 0, index = 2; i < max_ints; i++, index += 2) {
2130 val = cmd.rsp.arg[index];
2131 if (LSB(val)) {
2132 dev_info(&adapter->pdev->dev,
2133 "Can't configure interrupt %d\n",
2134 adapter->ahw->intr_tbl[i].id);
2135 continue;
2136 }
2137 if (op_type) {
2138 adapter->ahw->intr_tbl[i].id = MSW(val);
2139 adapter->ahw->intr_tbl[i].enabled = 1;
2140 temp = cmd.rsp.arg[index + 1];
2141 adapter->ahw->intr_tbl[i].src = temp;
2142 } else {
2143 adapter->ahw->intr_tbl[i].id = i;
2144 adapter->ahw->intr_tbl[i].enabled = 0;
2145 adapter->ahw->intr_tbl[i].src = 0;
2146 }
2147 }
2148out:
2149 qlcnic_free_mbx_args(&cmd);
2150 return err;
2151}
d865ebb4
SC		 2152
2153int qlcnic_83xx_lock_flash(struct qlcnic_adapter *adapter)
2154{
2155 int id, timeout = 0;
2156 u32 status = 0;
2157
2158 while (status == 0) {
2159 status = QLC_SHARED_REG_RD32(adapter, QLCNIC_FLASH_LOCK);
2160 if (status)
2161 break;
2162
2163 if (++timeout >= QLC_83XX_FLASH_LOCK_TIMEOUT) {
2164 id = QLC_SHARED_REG_RD32(adapter,
2165 QLCNIC_FLASH_LOCK_OWNER);
2166 dev_err(&adapter->pdev->dev,
2167 "%s: failed, lock held by %d\n", __func__, id);
2168 return -EIO;
2169 }
2170 usleep_range(1000, 2000);
2171 }
2172
2173 QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER, adapter->portnum);
2174 return 0;
2175}
2176
2177void qlcnic_83xx_unlock_flash(struct qlcnic_adapter *adapter)
2178{
2179 QLC_SHARED_REG_RD32(adapter, QLCNIC_FLASH_UNLOCK);
2180 QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER, 0xFF);
2181}
2182
629263ac
SC		 2183int qlcnic_83xx_lockless_flash_read32(struct qlcnic_adapter *adapter,
2184 u32 flash_addr, u8 *p_data,
2185 int count)
d865ebb4
SC		 2186{
2187 int i, ret;
2188 u32 word, range, flash_offset, addr = flash_addr;
2189 ulong indirect_add, direct_window;
2190
2191 flash_offset = addr & (QLCNIC_FLASH_SECTOR_SIZE - 1);
2192 if (addr & 0x3) {
2193 dev_err(&adapter->pdev->dev, "Illegal addr = 0x%x\n", addr);
2194 return -EIO;
2195 }
2196
2197 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_DIRECT_WINDOW,
2198 (addr));
2199
2200 range = flash_offset + (count * sizeof(u32));
2201 /* Check if data is spread across multiple sectors */
2202 if (range > (QLCNIC_FLASH_SECTOR_SIZE - 1)) {
2203
2204 /* Multi sector read */
2205 for (i = 0; i < count; i++) {
2206 indirect_add = QLC_83XX_FLASH_DIRECT_DATA(addr);
2207 ret = qlcnic_83xx_rd_reg_indirect(adapter,
2208 indirect_add);
2209 if (ret == -EIO)
2210 return -EIO;
2211
2212 word = ret;
2213 *(u32 *)p_data = word;
2214 p_data = p_data + 4;
2215 addr = addr + 4;
2216 flash_offset = flash_offset + 4;
2217
2218 if (flash_offset > (QLCNIC_FLASH_SECTOR_SIZE - 1)) {
2219 direct_window = QLC_83XX_FLASH_DIRECT_WINDOW;
2220 /* This write is needed once for each sector */
2221 qlcnic_83xx_wrt_reg_indirect(adapter,
2222 direct_window,
2223 (addr));
2224 flash_offset = 0;
2225 }
2226 }
2227 } else {
2228 /* Single sector read */
2229 for (i = 0; i < count; i++) {
2230 indirect_add = QLC_83XX_FLASH_DIRECT_DATA(addr);
2231 ret = qlcnic_83xx_rd_reg_indirect(adapter,
2232 indirect_add);
2233 if (ret == -EIO)
2234 return -EIO;
2235
2236 word = ret;
2237 *(u32 *)p_data = word;
2238 p_data = p_data + 4;
2239 addr = addr + 4;
2240 }
2241 }
2242
2243 return 0;
2244}
2245
2246static int qlcnic_83xx_poll_flash_status_reg(struct qlcnic_adapter *adapter)
2247{
2248 u32 status;
2249 int retries = QLC_83XX_FLASH_READ_RETRY_COUNT;
2250
2251 do {
2252 status = qlcnic_83xx_rd_reg_indirect(adapter,
2253 QLC_83XX_FLASH_STATUS);
2254 if ((status & QLC_83XX_FLASH_STATUS_READY) ==
2255 QLC_83XX_FLASH_STATUS_READY)
2256 break;
2257
2258 msleep(QLC_83XX_FLASH_STATUS_REG_POLL_DELAY);
2259 } while (--retries);
2260
2261 if (!retries)
2262 return -EIO;
2263
2264 return 0;
2265}
2266
a520030e 2267int qlcnic_83xx_enable_flash_write(struct qlcnic_adapter *adapter)
d865ebb4
SC		 2268{
2269 int ret;
2270 u32 cmd;
2271 cmd = adapter->ahw->fdt.write_statusreg_cmd;
2272 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2273 (QLC_83XX_FLASH_FDT_WRITE_DEF_SIG | cmd));
2274 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2275 adapter->ahw->fdt.write_enable_bits);
2276 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2277 QLC_83XX_FLASH_SECOND_ERASE_MS_VAL);
2278 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2279 if (ret)
2280 return -EIO;
2281
2282 return 0;
2283}
2284
a520030e 2285int qlcnic_83xx_disable_flash_write(struct qlcnic_adapter *adapter)
d865ebb4
SC		 2286{
2287 int ret;
2288
2289 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2290 (QLC_83XX_FLASH_FDT_WRITE_DEF_SIG |
2291 adapter->ahw->fdt.write_statusreg_cmd));
2292 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2293 adapter->ahw->fdt.write_disable_bits);
2294 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2295 QLC_83XX_FLASH_SECOND_ERASE_MS_VAL);
2296 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2297 if (ret)
2298 return -EIO;
2299
2300 return 0;
2301}
2302
2303int qlcnic_83xx_read_flash_mfg_id(struct qlcnic_adapter *adapter)
2304{
2305 int ret, mfg_id;
2306
2307 if (qlcnic_83xx_lock_flash(adapter))
2308 return -EIO;
2309
2310 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2311 QLC_83XX_FLASH_FDT_READ_MFG_ID_VAL);
2312 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2313 QLC_83XX_FLASH_READ_CTRL);
2314 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2315 if (ret) {
2316 qlcnic_83xx_unlock_flash(adapter);
2317 return -EIO;
2318 }
2319
2320 mfg_id = qlcnic_83xx_rd_reg_indirect(adapter, QLC_83XX_FLASH_RDDATA);
2321 if (mfg_id == -EIO)
2322 return -EIO;
2323
2324 adapter->flash_mfg_id = (mfg_id & 0xFF);
2325 qlcnic_83xx_unlock_flash(adapter);
2326
2327 return 0;
2328}
2329
2330int qlcnic_83xx_read_flash_descriptor_table(struct qlcnic_adapter *adapter)
2331{
2332 int count, fdt_size, ret = 0;
2333
2334 fdt_size = sizeof(struct qlcnic_fdt);
2335 count = fdt_size / sizeof(u32);
2336
2337 if (qlcnic_83xx_lock_flash(adapter))
2338 return -EIO;
2339
2340 memset(&adapter->ahw->fdt, 0, fdt_size);
2341 ret = qlcnic_83xx_lockless_flash_read32(adapter, QLCNIC_FDT_LOCATION,
2342 (u8 *)&adapter->ahw->fdt,
2343 count);
2344
2345 qlcnic_83xx_unlock_flash(adapter);
2346 return ret;
2347}
2348
2349int qlcnic_83xx_erase_flash_sector(struct qlcnic_adapter *adapter,
2350 u32 sector_start_addr)
2351{
2352 u32 reversed_addr, addr1, addr2, cmd;
2353 int ret = -EIO;
2354
2355 if (qlcnic_83xx_lock_flash(adapter) != 0)
2356 return -EIO;
2357
2358 if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id) {
a520030e 2359 ret = qlcnic_83xx_enable_flash_write(adapter);
d865ebb4
SC		 2360 if (ret) {
2361 qlcnic_83xx_unlock_flash(adapter);
2362 dev_err(&adapter->pdev->dev,
2363 "%s failed at %d\n",
2364 __func__, __LINE__);
2365 return ret;
2366 }
2367 }
2368
2369 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2370 if (ret) {
2371 qlcnic_83xx_unlock_flash(adapter);
2372 dev_err(&adapter->pdev->dev,
2373 "%s: failed at %d\n", __func__, __LINE__);
2374 return -EIO;
2375 }
2376
2377 addr1 = (sector_start_addr & 0xFF) << 16;
2378 addr2 = (sector_start_addr & 0xFF0000) >> 16;
2379 reversed_addr = addr1 | addr2;
2380
2381 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2382 reversed_addr);
2383 cmd = QLC_83XX_FLASH_FDT_ERASE_DEF_SIG | adapter->ahw->fdt.erase_cmd;
2384 if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id)
2385 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, cmd);
2386 else
2387 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2388 QLC_83XX_FLASH_OEM_ERASE_SIG);
2389 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2390 QLC_83XX_FLASH_LAST_ERASE_MS_VAL);
2391
2392 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2393 if (ret) {
2394 qlcnic_83xx_unlock_flash(adapter);
2395 dev_err(&adapter->pdev->dev,
2396 "%s: failed at %d\n", __func__, __LINE__);
2397 return -EIO;
2398 }
2399
2400 if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id) {
a520030e 2401 ret = qlcnic_83xx_disable_flash_write(adapter);
d865ebb4
SC		 2402 if (ret) {
2403 qlcnic_83xx_unlock_flash(adapter);
2404 dev_err(&adapter->pdev->dev,
2405 "%s: failed at %d\n", __func__, __LINE__);
2406 return ret;
2407 }
2408 }
2409
2410 qlcnic_83xx_unlock_flash(adapter);
2411
2412 return 0;
2413}
2414
2415int qlcnic_83xx_flash_write32(struct qlcnic_adapter *adapter, u32 addr,
2416 u32 *p_data)
2417{
2418 int ret = -EIO;
2419 u32 addr1 = 0x00800000 | (addr >> 2);
2420
2421 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, addr1);
2422 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data);
2423 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2424 QLC_83XX_FLASH_LAST_ERASE_MS_VAL);
2425 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2426 if (ret) {
2427 dev_err(&adapter->pdev->dev,
2428 "%s: failed at %d\n", __func__, __LINE__);
2429 return -EIO;
2430 }
2431
2432 return 0;
2433}
2434
2435int qlcnic_83xx_flash_bulk_write(struct qlcnic_adapter *adapter, u32 addr,
2436 u32 *p_data, int count)
2437{
2438 u32 temp;
2439 int ret = -EIO;
2440
a520030e
HM		 2441 if ((count < QLC_83XX_FLASH_WRITE_MIN) ||
2442 (count > QLC_83XX_FLASH_WRITE_MAX)) {
d865ebb4
SC		 2443 dev_err(&adapter->pdev->dev,
2444 "%s: Invalid word count\n", __func__);
2445 return -EIO;
2446 }
2447
2448 temp = qlcnic_83xx_rd_reg_indirect(adapter,
2449 QLC_83XX_FLASH_SPI_CONTROL);
2450 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_SPI_CONTROL,
2451 (temp | QLC_83XX_FLASH_SPI_CTRL));
2452 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2453 QLC_83XX_FLASH_ADDR_TEMP_VAL);
2454
2455 /* First DWORD write */
2456 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data++);
2457 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2458 QLC_83XX_FLASH_FIRST_MS_PATTERN);
2459 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2460 if (ret) {
2461 dev_err(&adapter->pdev->dev,
2462 "%s: failed at %d\n", __func__, __LINE__);
2463 return -EIO;
2464 }
2465
2466 count--;
2467 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2468 QLC_83XX_FLASH_ADDR_SECOND_TEMP_VAL);
2469 /* Second to N-1 DWORD writes */
2470 while (count != 1) {
2471 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2472 *p_data++);
2473 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2474 QLC_83XX_FLASH_SECOND_MS_PATTERN);
2475 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2476 if (ret) {
2477 dev_err(&adapter->pdev->dev,
2478 "%s: failed at %d\n", __func__, __LINE__);
2479 return -EIO;
2480 }
2481 count--;
2482 }
2483
2484 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2485 QLC_83XX_FLASH_ADDR_TEMP_VAL |
2486 (addr >> 2));
2487 /* Last DWORD write */
2488 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data++);
2489 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2490 QLC_83XX_FLASH_LAST_MS_PATTERN);
2491 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2492 if (ret) {
2493 dev_err(&adapter->pdev->dev,
2494 "%s: failed at %d\n", __func__, __LINE__);
2495 return -EIO;
2496 }
2497
2498 ret = qlcnic_83xx_rd_reg_indirect(adapter, QLC_83XX_FLASH_SPI_STATUS);
2499 if ((ret & QLC_83XX_FLASH_SPI_CTRL) == QLC_83XX_FLASH_SPI_CTRL) {
2500 dev_err(&adapter->pdev->dev, "%s: failed at %d\n",
2501 __func__, __LINE__);
2502 /* Operation failed, clear error bit */
2503 temp = qlcnic_83xx_rd_reg_indirect(adapter,
2504 QLC_83XX_FLASH_SPI_CONTROL);
2505 qlcnic_83xx_wrt_reg_indirect(adapter,
2506 QLC_83XX_FLASH_SPI_CONTROL,
2507 (temp | QLC_83XX_FLASH_SPI_CTRL));
2508 }
2509
2510 return 0;
2511}
629263ac
SC		 2512
2513static void qlcnic_83xx_recover_driver_lock(struct qlcnic_adapter *adapter)
2514{
2515 u32 val, id;
2516
2517 val = QLCRDX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK);
2518
2519 /* Check if recovery need to be performed by the calling function */
2520 if ((val & QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK) == 0) {
2521 val = val & ~0x3F;
2522 val = val | ((adapter->portnum << 2) |
2523 QLC_83XX_NEED_DRV_LOCK_RECOVERY);
2524 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2525 dev_info(&adapter->pdev->dev,
2526 "%s: lock recovery initiated\n", __func__);
2527 msleep(QLC_83XX_DRV_LOCK_RECOVERY_DELAY);
2528 val = QLCRDX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK);
2529 id = ((val >> 2) & 0xF);
2530 if (id == adapter->portnum) {
2531 val = val & ~QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK;
2532 val = val | QLC_83XX_DRV_LOCK_RECOVERY_IN_PROGRESS;
2533 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2534 /* Force release the lock */
2535 QLCRDX(adapter->ahw, QLC_83XX_DRV_UNLOCK);
2536 /* Clear recovery bits */
2537 val = val & ~0x3F;
2538 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2539 dev_info(&adapter->pdev->dev,
2540 "%s: lock recovery completed\n", __func__);
2541 } else {
2542 dev_info(&adapter->pdev->dev,
2543 "%s: func %d to resume lock recovery process\n",
2544 __func__, id);
2545 }
2546 } else {
2547 dev_info(&adapter->pdev->dev,
2548 "%s: lock recovery initiated by other functions\n",
2549 __func__);
2550 }
2551}
2552
2553int qlcnic_83xx_lock_driver(struct qlcnic_adapter *adapter)
2554{
2555 u32 lock_alive_counter, val, id, i = 0, status = 0, temp = 0;
2556 int max_attempt = 0;
2557
2558 while (status == 0) {
2559 status = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK);
2560 if (status)
2561 break;
2562
2563 msleep(QLC_83XX_DRV_LOCK_WAIT_DELAY);
2564 i++;
2565
2566 if (i == 1)
2567 temp = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2568
2569 if (i == QLC_83XX_DRV_LOCK_WAIT_COUNTER) {
2570 val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2571 if (val == temp) {
2572 id = val & 0xFF;
2573 dev_info(&adapter->pdev->dev,
2574 "%s: lock to be recovered from %d\n",
2575 __func__, id);
2576 qlcnic_83xx_recover_driver_lock(adapter);
2577 i = 0;
2578 max_attempt++;
2579 } else {
2580 dev_err(&adapter->pdev->dev,
2581 "%s: failed to get lock\n", __func__);
2582 return -EIO;
2583 }
2584 }
2585
2586 /* Force exit from while loop after few attempts */
2587 if (max_attempt == QLC_83XX_MAX_DRV_LOCK_RECOVERY_ATTEMPT) {
2588 dev_err(&adapter->pdev->dev,
2589 "%s: failed to get lock\n", __func__);
2590 return -EIO;
2591 }
2592 }
2593
2594 val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2595 lock_alive_counter = val >> 8;
2596 lock_alive_counter++;
2597 val = lock_alive_counter << 8 | adapter->portnum;
2598 QLCWRX(adapter->ahw, QLC_83XX_DRV_LOCK_ID, val);
2599
2600 return 0;
2601}
2602
2603void qlcnic_83xx_unlock_driver(struct qlcnic_adapter *adapter)
2604{
2605 u32 val, lock_alive_counter, id;
2606
2607 val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2608 id = val & 0xFF;
2609 lock_alive_counter = val >> 8;
2610
2611 if (id != adapter->portnum)
2612 dev_err(&adapter->pdev->dev,
2613 "%s:Warning func %d is unlocking lock owned by %d\n",
2614 __func__, adapter->portnum, id);
2615
2616 val = (lock_alive_counter << 8) | 0xFF;
2617 QLCWRX(adapter->ahw, QLC_83XX_DRV_LOCK_ID, val);
2618 QLCRDX(adapter->ahw, QLC_83XX_DRV_UNLOCK);
2619}
2620
2621int qlcnic_83xx_ms_mem_write128(struct qlcnic_adapter *adapter, u64 addr,
2622 u32 *data, u32 count)
2623{
2624 int i, j, ret = 0;
2625 u32 temp;
2626
2627 /* Check alignment */
2628 if (addr & 0xF)
2629 return -EIO;
2630
2631 mutex_lock(&adapter->ahw->mem_lock);
2632 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_ADDR_HI, 0);
2633
2634 for (i = 0; i < count; i++, addr += 16) {
2635 if (!((ADDR_IN_RANGE(addr, QLCNIC_ADDR_QDR_NET,
2636 QLCNIC_ADDR_QDR_NET_MAX)) ||
2637 (ADDR_IN_RANGE(addr, QLCNIC_ADDR_DDR_NET,
2638 QLCNIC_ADDR_DDR_NET_MAX)))) {
2639 mutex_unlock(&adapter->ahw->mem_lock);
2640 return -EIO;
2641 }
2642
2643 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_ADDR_LO, addr);
2644 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_LO,
2645 *data++);
2646 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_HI,
2647 *data++);
2648 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_ULO,
2649 *data++);
2650 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_UHI,
2651 *data++);
2652 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_CTRL,
2653 QLCNIC_TA_WRITE_ENABLE);
2654 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_CTRL,
2655 QLCNIC_TA_WRITE_START);
2656
2657 for (j = 0; j < MAX_CTL_CHECK; j++) {
2658 temp = qlcnic_83xx_rd_reg_indirect(adapter,
2659 QLCNIC_MS_CTRL);
2660 if ((temp & TA_CTL_BUSY) == 0)
2661 break;
2662 }
2663
2664 /* Status check failure */
2665 if (j >= MAX_CTL_CHECK) {
2666 printk_ratelimited(KERN_WARNING
2667 "MS memory write failed\n");
2668 mutex_unlock(&adapter->ahw->mem_lock);
2669 return -EIO;
2670 }
2671 }
2672
2673 mutex_unlock(&adapter->ahw->mem_lock);
2674
2675 return ret;
2676}
81d0aeb0
SC		 2677
2678int qlcnic_83xx_flash_read32(struct qlcnic_adapter *adapter, u32 flash_addr,
2679 u8 *p_data, int count)
2680{
2681 int i, ret;
2682 u32 word, addr = flash_addr;
2683 ulong indirect_addr;
2684
2685 if (qlcnic_83xx_lock_flash(adapter) != 0)
2686 return -EIO;
2687
2688 if (addr & 0x3) {
2689 dev_err(&adapter->pdev->dev, "Illegal addr = 0x%x\n", addr);
2690 qlcnic_83xx_unlock_flash(adapter);
2691 return -EIO;
2692 }
2693
2694 for (i = 0; i < count; i++) {
2695 if (qlcnic_83xx_wrt_reg_indirect(adapter,
2696 QLC_83XX_FLASH_DIRECT_WINDOW,
2697 (addr))) {
2698 qlcnic_83xx_unlock_flash(adapter);
2699 return -EIO;
2700 }
2701
2702 indirect_addr = QLC_83XX_FLASH_DIRECT_DATA(addr);
2703 ret = qlcnic_83xx_rd_reg_indirect(adapter,
2704 indirect_addr);
2705 if (ret == -EIO)
2706 return -EIO;
2707 word = ret;
1403f43a 2708 *(u32 *)p_data = word;
81d0aeb0
SC		 2709 p_data = p_data + 4;
2710 addr = addr + 4;
2711 }
2712
2713 qlcnic_83xx_unlock_flash(adapter);
2714
2715 return 0;
2716}
7e38d04b
SC		 2717
2718int qlcnic_83xx_test_link(struct qlcnic_adapter *adapter)
2719{
7cb03b23 2720 u8 pci_func;
7e38d04b
SC		 2721 int err;
2722 u32 config = 0, state;
2723 struct qlcnic_cmd_args cmd;
2724 struct qlcnic_hardware_context *ahw = adapter->ahw;
2725
7cb03b23
RB		 2726 if (qlcnic_sriov_vf_check(adapter))
2727 pci_func = adapter->portnum;
2728 else
2729 pci_func = ahw->pci_func;
2730
2731 state = readl(ahw->pci_base0 + QLC_83XX_LINK_STATE(pci_func));
2732 if (!QLC_83xx_FUNC_VAL(state, pci_func)) {
7e38d04b
SC		 2733 dev_info(&adapter->pdev->dev, "link state down\n");
2734 return config;
2735 }
2736 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LINK_STATUS);
2737 err = qlcnic_issue_cmd(adapter, &cmd);
2738 if (err) {
2739 dev_info(&adapter->pdev->dev,
2740 "Get Link Status Command failed: 0x%x\n", err);
2741 goto out;
2742 } else {
2743 config = cmd.rsp.arg[1];
2744 switch (QLC_83XX_CURRENT_LINK_SPEED(config)) {
2745 case QLC_83XX_10M_LINK:
2746 ahw->link_speed = SPEED_10;
2747 break;
2748 case QLC_83XX_100M_LINK:
2749 ahw->link_speed = SPEED_100;
2750 break;
2751 case QLC_83XX_1G_LINK:
2752 ahw->link_speed = SPEED_1000;
2753 break;
2754 case QLC_83XX_10G_LINK:
2755 ahw->link_speed = SPEED_10000;
2756 break;
2757 default:
2758 ahw->link_speed = 0;
2759 break;
2760 }
2761 config = cmd.rsp.arg[3];
2762 if (config & 1)
2763 err = 1;
2764 }
2765out:
2766 qlcnic_free_mbx_args(&cmd);
2767 return config;
2768}
2769
2770int qlcnic_83xx_get_settings(struct qlcnic_adapter *adapter)
2771{
2772 u32 config = 0;
2773 int status = 0;
2774 struct qlcnic_hardware_context *ahw = adapter->ahw;
2775
2776 /* Get port configuration info */
2777 status = qlcnic_83xx_get_port_info(adapter);
2778 /* Get Link Status related info */
2779 config = qlcnic_83xx_test_link(adapter);
2780 ahw->module_type = QLC_83XX_SFP_MODULE_TYPE(config);
2781 /* hard code until there is a way to get it from flash */
2782 ahw->board_type = QLCNIC_BRDTYPE_83XX_10G;
2783 return status;
2784}
2785
2786int qlcnic_83xx_set_settings(struct qlcnic_adapter *adapter,
2787 struct ethtool_cmd *ecmd)
2788{
2789 int status = 0;
2790 u32 config = adapter->ahw->port_config;
2791
2792 if (ecmd->autoneg)
2793 adapter->ahw->port_config |= BIT_15;
2794
2795 switch (ethtool_cmd_speed(ecmd)) {
2796 case SPEED_10:
2797 adapter->ahw->port_config |= BIT_8;
2798 break;
2799 case SPEED_100:
2800 adapter->ahw->port_config |= BIT_9;
2801 break;
2802 case SPEED_1000:
2803 adapter->ahw->port_config |= BIT_10;
2804 break;
2805 case SPEED_10000:
2806 adapter->ahw->port_config |= BIT_11;
2807 break;
2808 default:
2809 return -EINVAL;
2810 }
2811
2812 status = qlcnic_83xx_set_port_config(adapter);
2813 if (status) {
2814 dev_info(&adapter->pdev->dev,
2815 "Faild to Set Link Speed and autoneg.\n");
2816 adapter->ahw->port_config = config;
2817 }
2818 return status;
2819}
2820
2821static inline u64 *qlcnic_83xx_copy_stats(struct qlcnic_cmd_args *cmd,
2822 u64 *data, int index)
2823{
2824 u32 low, hi;
2825 u64 val;
2826
2827 low = cmd->rsp.arg[index];
2828 hi = cmd->rsp.arg[index + 1];
2829 val = (((u64) low) | (((u64) hi) << 32));
2830 *data++ = val;
2831 return data;
2832}
2833
2834static u64 *qlcnic_83xx_fill_stats(struct qlcnic_adapter *adapter,
2835 struct qlcnic_cmd_args *cmd, u64 *data,
2836 int type, int *ret)
2837{
2838 int err, k, total_regs;
2839
2840 *ret = 0;
2841 err = qlcnic_issue_cmd(adapter, cmd);
2842 if (err != QLCNIC_RCODE_SUCCESS) {
2843 dev_info(&adapter->pdev->dev,
2844 "Error in get statistics mailbox command\n");
2845 *ret = -EIO;
2846 return data;
2847 }
2848 total_regs = cmd->rsp.num;
2849 switch (type) {
2850 case QLC_83XX_STAT_MAC:
2851 /* fill in MAC tx counters */
2852 for (k = 2; k < 28; k += 2)
2853 data = qlcnic_83xx_copy_stats(cmd, data, k);
2854 /* skip 24 bytes of reserved area */
2855 /* fill in MAC rx counters */
2856 for (k += 6; k < 60; k += 2)
2857 data = qlcnic_83xx_copy_stats(cmd, data, k);
2858 /* skip 24 bytes of reserved area */
2859 /* fill in MAC rx frame stats */
2860 for (k += 6; k < 80; k += 2)
2861 data = qlcnic_83xx_copy_stats(cmd, data, k);
2862 break;
2863 case QLC_83XX_STAT_RX:
2864 for (k = 2; k < 8; k += 2)
2865 data = qlcnic_83xx_copy_stats(cmd, data, k);
2866 /* skip 8 bytes of reserved data */
2867 for (k += 2; k < 24; k += 2)
2868 data = qlcnic_83xx_copy_stats(cmd, data, k);
2869 /* skip 8 bytes containing RE1FBQ error data */
2870 for (k += 2; k < total_regs; k += 2)
2871 data = qlcnic_83xx_copy_stats(cmd, data, k);
2872 break;
2873 case QLC_83XX_STAT_TX:
2874 for (k = 2; k < 10; k += 2)
2875 data = qlcnic_83xx_copy_stats(cmd, data, k);
2876 /* skip 8 bytes of reserved data */
2877 for (k += 2; k < total_regs; k += 2)
2878 data = qlcnic_83xx_copy_stats(cmd, data, k);
2879 break;
2880 default:
2881 dev_warn(&adapter->pdev->dev, "Unknown get statistics mode\n");
2882 *ret = -EIO;
2883 }
2884 return data;
2885}
2886
2887void qlcnic_83xx_get_stats(struct qlcnic_adapter *adapter, u64 *data)
2888{
2889 struct qlcnic_cmd_args cmd;
2890 int ret = 0;
2891
2892 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_STATISTICS);
2893 /* Get Tx stats */
2894 cmd.req.arg[1] = BIT_1 | (adapter->tx_ring->ctx_id << 16);
2895 cmd.rsp.num = QLC_83XX_TX_STAT_REGS;
2896 data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
2897 QLC_83XX_STAT_TX, &ret);
2898 if (ret) {
2899 dev_info(&adapter->pdev->dev, "Error getting MAC stats\n");
2900 goto out;
2901 }
2902 /* Get MAC stats */
2903 cmd.req.arg[1] = BIT_2 | (adapter->portnum << 16);
2904 cmd.rsp.num = QLC_83XX_MAC_STAT_REGS;
2905 memset(cmd.rsp.arg, 0, sizeof(u32) * cmd.rsp.num);
2906 data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
2907 QLC_83XX_STAT_MAC, &ret);
2908 if (ret) {
2909 dev_info(&adapter->pdev->dev,
2910 "Error getting Rx stats\n");
2911 goto out;
2912 }
2913 /* Get Rx stats */
2914 cmd.req.arg[1] = adapter->recv_ctx->context_id << 16;
2915 cmd.rsp.num = QLC_83XX_RX_STAT_REGS;
2916 memset(cmd.rsp.arg, 0, sizeof(u32) * cmd.rsp.num);
2917 data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
2918 QLC_83XX_STAT_RX, &ret);
2919 if (ret)
2920 dev_info(&adapter->pdev->dev,
2921 "Error getting Tx stats\n");
2922out:
2923 qlcnic_free_mbx_args(&cmd);
2924}
2925
2926int qlcnic_83xx_reg_test(struct qlcnic_adapter *adapter)
2927{
2928 u32 major, minor, sub;
2929
2930 major = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MAJOR);
2931 minor = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MINOR);
2932 sub = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_SUB);
2933
2934 if (adapter->fw_version != QLCNIC_VERSION_CODE(major, minor, sub)) {
2935 dev_info(&adapter->pdev->dev, "%s: Reg test failed\n",
2936 __func__);
2937 return 1;
2938 }
2939 return 0;
2940}
2941
2942int qlcnic_83xx_get_regs_len(struct qlcnic_adapter *adapter)
2943{
2944 return (ARRAY_SIZE(qlcnic_83xx_ext_reg_tbl) *
2945 sizeof(adapter->ahw->ext_reg_tbl)) +
2946 (ARRAY_SIZE(qlcnic_83xx_reg_tbl) +
2947 sizeof(adapter->ahw->reg_tbl));
2948}
2949
2950int qlcnic_83xx_get_registers(struct qlcnic_adapter *adapter, u32 *regs_buff)
2951{
2952 int i, j = 0;
2953
2954 for (i = QLCNIC_DEV_INFO_SIZE + 1;
2955 j < ARRAY_SIZE(qlcnic_83xx_reg_tbl); i++, j++)
2956 regs_buff[i] = QLC_SHARED_REG_RD32(adapter, j);
2957
2958 for (j = 0; j < ARRAY_SIZE(qlcnic_83xx_ext_reg_tbl); j++)
2959 regs_buff[i++] = QLCRDX(adapter->ahw, j);
2960 return i;
2961}
2962
58ead415 2963int qlcnic_83xx_interrupt_test(struct net_device *netdev)
7e38d04b 2964{
58ead415
JK		 2965 struct qlcnic_adapter *adapter = netdev_priv(netdev);
2966 struct qlcnic_hardware_context *ahw = adapter->ahw;
2967 struct qlcnic_cmd_args cmd;
7e38d04b
SC		 2968 u32 data;
2969 u16 intrpt_id, id;
58ead415
JK		 2970 u8 val;
2971 int ret, max_sds_rings = adapter->max_sds_rings;
2972
2973 if (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))
2974 return -EIO;
2975
2976 ret = qlcnic_83xx_diag_alloc_res(netdev, QLCNIC_INTERRUPT_TEST);
2977 if (ret)
2978 goto fail_diag_irq;
2979
2980 ahw->diag_cnt = 0;
2981 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_INTRPT_TEST);
7e38d04b
SC		 2982
2983 if (adapter->flags & QLCNIC_MSIX_ENABLED)
58ead415 2984 intrpt_id = ahw->intr_tbl[0].id;
7e38d04b 2985 else
58ead415 2986 intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
7e38d04b 2987
58ead415
JK		 2988 cmd.req.arg[1] = 1;
2989 cmd.req.arg[2] = intrpt_id;
2990 cmd.req.arg[3] = BIT_0;
7e38d04b 2991
58ead415
JK		 2992 ret = qlcnic_issue_cmd(adapter, &cmd);
2993 data = cmd.rsp.arg[2];
7e38d04b
SC		 2994 id = LSW(data);
2995 val = LSB(MSW(data));
2996 if (id != intrpt_id)
2997 dev_info(&adapter->pdev->dev,
2998 "Interrupt generated: 0x%x, requested:0x%x\n",
2999 id, intrpt_id);
3000 if (val)
58ead415 3001 dev_err(&adapter->pdev->dev,
7e38d04b 3002 "Interrupt test error: 0x%x\n", val);
58ead415
JK		 3003 if (ret)
3004 goto done;
3005
3006 msleep(20);
3007 ret = !ahw->diag_cnt;
7e38d04b 3008
58ead415
JK		 3009done:
3010 qlcnic_free_mbx_args(&cmd);
3011 qlcnic_83xx_diag_free_res(netdev, max_sds_rings);
3012
3013fail_diag_irq:
3014 adapter->max_sds_rings = max_sds_rings;
3015 clear_bit(__QLCNIC_RESETTING, &adapter->state);
7e38d04b
SC		 3016 return ret;
3017}
3018
3019void qlcnic_83xx_get_pauseparam(struct qlcnic_adapter *adapter,
3020 struct ethtool_pauseparam *pause)
3021{
3022 struct qlcnic_hardware_context *ahw = adapter->ahw;
3023 int status = 0;
3024 u32 config;
3025
3026 status = qlcnic_83xx_get_port_config(adapter);
3027 if (status) {
3028 dev_err(&adapter->pdev->dev,
3029 "%s: Get Pause Config failed\n", __func__);
3030 return;
3031 }
3032 config = ahw->port_config;
3033 if (config & QLC_83XX_CFG_STD_PAUSE) {
3034 if (config & QLC_83XX_CFG_STD_TX_PAUSE)
3035 pause->tx_pause = 1;
3036 if (config & QLC_83XX_CFG_STD_RX_PAUSE)
3037 pause->rx_pause = 1;
3038 }
3039
3040 if (QLC_83XX_AUTONEG(config))
3041 pause->autoneg = 1;
3042}
3043
3044int qlcnic_83xx_set_pauseparam(struct qlcnic_adapter *adapter,
3045 struct ethtool_pauseparam *pause)
3046{
3047 struct qlcnic_hardware_context *ahw = adapter->ahw;
3048 int status = 0;
3049 u32 config;
3050
3051 status = qlcnic_83xx_get_port_config(adapter);
3052 if (status) {
3053 dev_err(&adapter->pdev->dev,
3054 "%s: Get Pause Config failed.\n", __func__);
3055 return status;
3056 }
3057 config = ahw->port_config;
3058
3059 if (ahw->port_type == QLCNIC_GBE) {
3060 if (pause->autoneg)
3061 ahw->port_config |= QLC_83XX_ENABLE_AUTONEG;
3062 if (!pause->autoneg)
3063 ahw->port_config &= ~QLC_83XX_ENABLE_AUTONEG;
3064 } else if ((ahw->port_type == QLCNIC_XGBE) && (pause->autoneg)) {
3065 return -EOPNOTSUPP;
3066 }
3067
3068 if (!(config & QLC_83XX_CFG_STD_PAUSE))
3069 ahw->port_config |= QLC_83XX_CFG_STD_PAUSE;
3070
3071 if (pause->rx_pause && pause->tx_pause) {
3072 ahw->port_config |= QLC_83XX_CFG_STD_TX_RX_PAUSE;
3073 } else if (pause->rx_pause && !pause->tx_pause) {
3074 ahw->port_config &= ~QLC_83XX_CFG_STD_TX_PAUSE;
3075 ahw->port_config |= QLC_83XX_CFG_STD_RX_PAUSE;
3076 } else if (pause->tx_pause && !pause->rx_pause) {
3077 ahw->port_config &= ~QLC_83XX_CFG_STD_RX_PAUSE;
3078 ahw->port_config |= QLC_83XX_CFG_STD_TX_PAUSE;
3079 } else if (!pause->rx_pause && !pause->tx_pause) {
3080 ahw->port_config &= ~QLC_83XX_CFG_STD_TX_RX_PAUSE;
3081 }
3082 status = qlcnic_83xx_set_port_config(adapter);
3083 if (status) {
3084 dev_err(&adapter->pdev->dev,
3085 "%s: Set Pause Config failed.\n", __func__);
3086 ahw->port_config = config;
3087 }
3088 return status;
3089}
3090
3091static int qlcnic_83xx_read_flash_status_reg(struct qlcnic_adapter *adapter)
3092{
3093 int ret;
3094
3095 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
3096 QLC_83XX_FLASH_OEM_READ_SIG);
3097 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
3098 QLC_83XX_FLASH_READ_CTRL);
3099 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
3100 if (ret)
3101 return -EIO;
3102
3103 ret = qlcnic_83xx_rd_reg_indirect(adapter, QLC_83XX_FLASH_RDDATA);
3104 return ret & 0xFF;
3105}
3106
3107int qlcnic_83xx_flash_test(struct qlcnic_adapter *adapter)
3108{
3109 int status;
3110
3111 status = qlcnic_83xx_read_flash_status_reg(adapter);
3112 if (status == -EIO) {
3113 dev_info(&adapter->pdev->dev, "%s: EEPROM test failed.\n",
3114 __func__);
3115 return 1;
3116 }
3117 return 0;
3118}
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