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qlcnic: Enhance PVID handling for 84xx adapters
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / qlogic / qlcnic / qlcnic_83xx_hw.c
CommitLineData
577ae39d
JK		 1/*
2 * QLogic qlcnic NIC Driver
3 * Copyright (c) 2009-2013 QLogic Corporation
4 *
5 * See LICENSE.qlcnic for copyright and licensing details.
6 */
7
7f966452 8#include "qlcnic.h"
f8468331 9#include "qlcnic_sriov.h"
7f966452
SC		 10#include <linux/if_vlan.h>
11#include <linux/ipv6.h>
12#include <linux/ethtool.h>
13#include <linux/interrupt.h>
14
15#define QLCNIC_MAX_TX_QUEUES 1
7f966452 16#define RSS_HASHTYPE_IP_TCP 0x3
f197a7aa 17#define QLC_83XX_FW_MBX_CMD 0
7f966452 18
7f966452
SC		 19static const struct qlcnic_mailbox_metadata qlcnic_83xx_mbx_tbl[] = {
20 {QLCNIC_CMD_CONFIGURE_IP_ADDR, 6, 1},
21 {QLCNIC_CMD_CONFIG_INTRPT, 18, 34},
22 {QLCNIC_CMD_CREATE_RX_CTX, 136, 27},
23 {QLCNIC_CMD_DESTROY_RX_CTX, 2, 1},
24 {QLCNIC_CMD_CREATE_TX_CTX, 54, 18},
25 {QLCNIC_CMD_DESTROY_TX_CTX, 2, 1},
26 {QLCNIC_CMD_CONFIGURE_MAC_LEARNING, 2, 1},
27 {QLCNIC_CMD_INTRPT_TEST, 22, 12},
28 {QLCNIC_CMD_SET_MTU, 3, 1},
29 {QLCNIC_CMD_READ_PHY, 4, 2},
30 {QLCNIC_CMD_WRITE_PHY, 5, 1},
31 {QLCNIC_CMD_READ_HW_REG, 4, 1},
32 {QLCNIC_CMD_GET_FLOW_CTL, 4, 2},
33 {QLCNIC_CMD_SET_FLOW_CTL, 4, 1},
34 {QLCNIC_CMD_READ_MAX_MTU, 4, 2},
35 {QLCNIC_CMD_READ_MAX_LRO, 4, 2},
36 {QLCNIC_CMD_MAC_ADDRESS, 4, 3},
37 {QLCNIC_CMD_GET_PCI_INFO, 1, 66},
38 {QLCNIC_CMD_GET_NIC_INFO, 2, 19},
39 {QLCNIC_CMD_SET_NIC_INFO, 32, 1},
40 {QLCNIC_CMD_GET_ESWITCH_CAPABILITY, 4, 3},
41 {QLCNIC_CMD_TOGGLE_ESWITCH, 4, 1},
42 {QLCNIC_CMD_GET_ESWITCH_STATUS, 4, 3},
43 {QLCNIC_CMD_SET_PORTMIRRORING, 4, 1},
44 {QLCNIC_CMD_CONFIGURE_ESWITCH, 4, 1},
45 {QLCNIC_CMD_GET_ESWITCH_PORT_CONFIG, 4, 3},
46 {QLCNIC_CMD_GET_ESWITCH_STATS, 5, 1},
47 {QLCNIC_CMD_CONFIG_PORT, 4, 1},
48 {QLCNIC_CMD_TEMP_SIZE, 1, 4},
49 {QLCNIC_CMD_GET_TEMP_HDR, 5, 5},
50 {QLCNIC_CMD_GET_LINK_EVENT, 2, 1},
51 {QLCNIC_CMD_CONFIG_MAC_VLAN, 4, 3},
52 {QLCNIC_CMD_CONFIG_INTR_COAL, 6, 1},
53 {QLCNIC_CMD_CONFIGURE_RSS, 14, 1},
54 {QLCNIC_CMD_CONFIGURE_LED, 2, 1},
55 {QLCNIC_CMD_CONFIGURE_MAC_RX_MODE, 2, 1},
56 {QLCNIC_CMD_CONFIGURE_HW_LRO, 2, 1},
57 {QLCNIC_CMD_GET_STATISTICS, 2, 80},
58 {QLCNIC_CMD_SET_PORT_CONFIG, 2, 1},
59 {QLCNIC_CMD_GET_PORT_CONFIG, 2, 2},
60 {QLCNIC_CMD_GET_LINK_STATUS, 2, 4},
61 {QLCNIC_CMD_IDC_ACK, 5, 1},
62 {QLCNIC_CMD_INIT_NIC_FUNC, 2, 1},
63 {QLCNIC_CMD_STOP_NIC_FUNC, 2, 1},
64 {QLCNIC_CMD_SET_LED_CONFIG, 5, 1},
65 {QLCNIC_CMD_GET_LED_CONFIG, 1, 5},
8af3f33d 66 {QLCNIC_CMD_83XX_SET_DRV_VER, 4, 1},
7f966452 67 {QLCNIC_CMD_ADD_RCV_RINGS, 130, 26},
02feda17 68 {QLCNIC_CMD_CONFIG_VPORT, 4, 4},
f197a7aa 69 {QLCNIC_CMD_BC_EVENT_SETUP, 2, 1},
14d385b9 70 {QLCNIC_CMD_DCB_QUERY_CAP, 1, 2},
fb859ed6 71 {QLCNIC_CMD_DCB_QUERY_PARAM, 2, 50},
7f966452
SC		 72};
73
f8468331 74const u32 qlcnic_83xx_ext_reg_tbl[] = {
7f966452
SC		 75 0x38CC, /* Global Reset */
76 0x38F0, /* Wildcard */
77 0x38FC, /* Informant */
78 0x3038, /* Host MBX ctrl */
79 0x303C, /* FW MBX ctrl */
80 0x355C, /* BOOT LOADER ADDRESS REG */
81 0x3560, /* BOOT LOADER SIZE REG */
82 0x3564, /* FW IMAGE ADDR REG */
83 0x1000, /* MBX intr enable */
84 0x1200, /* Default Intr mask */
85 0x1204, /* Default Interrupt ID */
86 0x3780, /* QLC_83XX_IDC_MAJ_VERSION */
87 0x3784, /* QLC_83XX_IDC_DEV_STATE */
88 0x3788, /* QLC_83XX_IDC_DRV_PRESENCE */
89 0x378C, /* QLC_83XX_IDC_DRV_ACK */
90 0x3790, /* QLC_83XX_IDC_CTRL */
91 0x3794, /* QLC_83XX_IDC_DRV_AUDIT */
92 0x3798, /* QLC_83XX_IDC_MIN_VERSION */
93 0x379C, /* QLC_83XX_RECOVER_DRV_LOCK */
94 0x37A0, /* QLC_83XX_IDC_PF_0 */
95 0x37A4, /* QLC_83XX_IDC_PF_1 */
96 0x37A8, /* QLC_83XX_IDC_PF_2 */
97 0x37AC, /* QLC_83XX_IDC_PF_3 */
98 0x37B0, /* QLC_83XX_IDC_PF_4 */
99 0x37B4, /* QLC_83XX_IDC_PF_5 */
100 0x37B8, /* QLC_83XX_IDC_PF_6 */
101 0x37BC, /* QLC_83XX_IDC_PF_7 */
102 0x37C0, /* QLC_83XX_IDC_PF_8 */
103 0x37C4, /* QLC_83XX_IDC_PF_9 */
104 0x37C8, /* QLC_83XX_IDC_PF_10 */
105 0x37CC, /* QLC_83XX_IDC_PF_11 */
106 0x37D0, /* QLC_83XX_IDC_PF_12 */
107 0x37D4, /* QLC_83XX_IDC_PF_13 */
108 0x37D8, /* QLC_83XX_IDC_PF_14 */
109 0x37DC, /* QLC_83XX_IDC_PF_15 */
110 0x37E0, /* QLC_83XX_IDC_DEV_PARTITION_INFO_1 */
111 0x37E4, /* QLC_83XX_IDC_DEV_PARTITION_INFO_2 */
112 0x37F0, /* QLC_83XX_DRV_OP_MODE */
113 0x37F4, /* QLC_83XX_VNIC_STATE */
114 0x3868, /* QLC_83XX_DRV_LOCK */
115 0x386C, /* QLC_83XX_DRV_UNLOCK */
116 0x3504, /* QLC_83XX_DRV_LOCK_ID */
117 0x34A4, /* QLC_83XX_ASIC_TEMP */
118};
119
f8468331 120const u32 qlcnic_83xx_reg_tbl[] = {
7f966452
SC		 121 0x34A8, /* PEG_HALT_STAT1 */
122 0x34AC, /* PEG_HALT_STAT2 */
123 0x34B0, /* FW_HEARTBEAT */
124 0x3500, /* FLASH LOCK_ID */
125 0x3528, /* FW_CAPABILITIES */
126 0x3538, /* Driver active, DRV_REG0 */
127 0x3540, /* Device state, DRV_REG1 */
128 0x3544, /* Driver state, DRV_REG2 */
129 0x3548, /* Driver scratch, DRV_REG3 */
130 0x354C, /* Device partiton info, DRV_REG4 */
131 0x3524, /* Driver IDC ver, DRV_REG5 */
132 0x3550, /* FW_VER_MAJOR */
133 0x3554, /* FW_VER_MINOR */
134 0x3558, /* FW_VER_SUB */
135 0x359C, /* NPAR STATE */
136 0x35FC, /* FW_IMG_VALID */
137 0x3650, /* CMD_PEG_STATE */
138 0x373C, /* RCV_PEG_STATE */
139 0x37B4, /* ASIC TEMP */
140 0x356C, /* FW API */
141 0x3570, /* DRV OP MODE */
142 0x3850, /* FLASH LOCK */
143 0x3854, /* FLASH UNLOCK */
144};
145
146static struct qlcnic_hardware_ops qlcnic_83xx_hw_ops = {
147 .read_crb = qlcnic_83xx_read_crb,
148 .write_crb = qlcnic_83xx_write_crb,
149 .read_reg = qlcnic_83xx_rd_reg_indirect,
150 .write_reg = qlcnic_83xx_wrt_reg_indirect,
151 .get_mac_address = qlcnic_83xx_get_mac_address,
152 .setup_intr = qlcnic_83xx_setup_intr,
153 .alloc_mbx_args = qlcnic_83xx_alloc_mbx_args,
e5c4e6c6 154 .mbx_cmd = qlcnic_83xx_issue_cmd,
7f966452
SC		 155 .get_func_no = qlcnic_83xx_get_func_no,
156 .api_lock = qlcnic_83xx_cam_lock,
157 .api_unlock = qlcnic_83xx_cam_unlock,
319ecf12
SC		 158 .add_sysfs = qlcnic_83xx_add_sysfs,
159 .remove_sysfs = qlcnic_83xx_remove_sysfs,
4be41e92 160 .process_lb_rcv_ring_diag = qlcnic_83xx_process_rcv_ring_diag,
7f966452
SC		 161 .create_rx_ctx = qlcnic_83xx_create_rx_ctx,
162 .create_tx_ctx = qlcnic_83xx_create_tx_ctx,
7cb03b23
RB		 163 .del_rx_ctx = qlcnic_83xx_del_rx_ctx,
164 .del_tx_ctx = qlcnic_83xx_del_tx_ctx,
7f966452
SC		 165 .setup_link_event = qlcnic_83xx_setup_link_event,
166 .get_nic_info = qlcnic_83xx_get_nic_info,
167 .get_pci_info = qlcnic_83xx_get_pci_info,
168 .set_nic_info = qlcnic_83xx_set_nic_info,
169 .change_macvlan = qlcnic_83xx_sre_macaddr_change,
4be41e92
SC		 170 .napi_enable = qlcnic_83xx_napi_enable,
171 .napi_disable = qlcnic_83xx_napi_disable,
7f966452
SC		 172 .config_intr_coal = qlcnic_83xx_config_intr_coal,
173 .config_rss = qlcnic_83xx_config_rss,
174 .config_hw_lro = qlcnic_83xx_config_hw_lro,
7f966452
SC		 175 .config_promisc_mode = qlcnic_83xx_nic_set_promisc,
176 .change_l2_filter = qlcnic_83xx_change_l2_filter,
177 .get_board_info = qlcnic_83xx_get_port_info,
52e493d0 178 .set_mac_filter_count = qlcnic_83xx_set_mac_filter_count,
91b7282b 179 .free_mac_list = qlcnic_82xx_free_mac_list,
7f966452
SC		 180};
181
182static struct qlcnic_nic_template qlcnic_83xx_ops = {
183 .config_bridged_mode = qlcnic_config_bridged_mode,
184 .config_led = qlcnic_config_led,
629263ac
SC		 185 .request_reset = qlcnic_83xx_idc_request_reset,
186 .cancel_idc_work = qlcnic_83xx_idc_exit,
4be41e92
SC		 187 .napi_add = qlcnic_83xx_napi_add,
188 .napi_del = qlcnic_83xx_napi_del,
7f966452
SC		 189 .config_ipaddr = qlcnic_83xx_config_ipaddr,
190 .clear_legacy_intr = qlcnic_83xx_clear_legacy_intr,
486a5bc7
RB		 191 .shutdown = qlcnic_83xx_shutdown,
192 .resume = qlcnic_83xx_resume,
7f966452
SC		 193};
194
195void qlcnic_83xx_register_map(struct qlcnic_hardware_context *ahw)
196{
197 ahw->hw_ops = &qlcnic_83xx_hw_ops;
198 ahw->reg_tbl = (u32 *)qlcnic_83xx_reg_tbl;
199 ahw->ext_reg_tbl = (u32 *)qlcnic_83xx_ext_reg_tbl;
200}
201
202int qlcnic_83xx_get_fw_version(struct qlcnic_adapter *adapter)
203{
204 u32 fw_major, fw_minor, fw_build;
205 struct pci_dev *pdev = adapter->pdev;
206
207 fw_major = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MAJOR);
208 fw_minor = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MINOR);
209 fw_build = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_SUB);
210 adapter->fw_version = QLCNIC_VERSION_CODE(fw_major, fw_minor, fw_build);
211
212 dev_info(&pdev->dev, "Driver v%s, firmware version %d.%d.%d\n",
213 QLCNIC_LINUX_VERSIONID, fw_major, fw_minor, fw_build);
214
215 return adapter->fw_version;
216}
217
218static int __qlcnic_set_win_base(struct qlcnic_adapter *adapter, u32 addr)
219{
220 void __iomem *base;
221 u32 val;
222
223 base = adapter->ahw->pci_base0 +
224 QLC_83XX_CRB_WIN_FUNC(adapter->ahw->pci_func);
225 writel(addr, base);
226 val = readl(base);
227 if (val != addr)
228 return -EIO;
229
230 return 0;
231}
232
4bd8e738
HM		 233int qlcnic_83xx_rd_reg_indirect(struct qlcnic_adapter *adapter, ulong addr,
234 int *err)
7f966452 235{
7f966452
SC		 236 struct qlcnic_hardware_context *ahw = adapter->ahw;
237
4bd8e738
HM		 238 *err = __qlcnic_set_win_base(adapter, (u32) addr);
239 if (!*err) {
7f966452
SC		 240 return QLCRDX(ahw, QLCNIC_WILDCARD);
241 } else {
242 dev_err(&adapter->pdev->dev,
4bd8e738 243 "%s failed, addr = 0x%lx\n", __func__, addr);
7f966452
SC		 244 return -EIO;
245 }
246}
247
248int qlcnic_83xx_wrt_reg_indirect(struct qlcnic_adapter *adapter, ulong addr,
249 u32 data)
250{
251 int err;
252 struct qlcnic_hardware_context *ahw = adapter->ahw;
253
254 err = __qlcnic_set_win_base(adapter, (u32) addr);
255 if (!err) {
256 QLCWRX(ahw, QLCNIC_WILDCARD, data);
257 return 0;
258 } else {
259 dev_err(&adapter->pdev->dev,
260 "%s failed, addr = 0x%x data = 0x%x\n",
261 __func__, (int)addr, data);
262 return err;
263 }
264}
265
aa4a1f7d 266int qlcnic_83xx_setup_intr(struct qlcnic_adapter *adapter, u8 num_intr, int txq)
7f966452
SC		 267{
268 int err, i, num_msix;
269 struct qlcnic_hardware_context *ahw = adapter->ahw;
270
271 if (!num_intr)
272 num_intr = QLCNIC_DEF_NUM_STS_DESC_RINGS;
273 num_msix = rounddown_pow_of_two(min_t(int, num_online_cpus(),
274 num_intr));
275 /* account for AEN interrupt MSI-X based interrupts */
276 num_msix += 1;
da6c8063
RB		 277
278 if (!(adapter->flags & QLCNIC_TX_INTR_SHARED))
279 num_msix += adapter->max_drv_tx_rings;
280
7f966452
SC		 281 err = qlcnic_enable_msix(adapter, num_msix);
282 if (err == -ENOMEM)
283 return err;
284 if (adapter->flags & QLCNIC_MSIX_ENABLED)
285 num_msix = adapter->ahw->num_msix;
f8468331
RB		 286 else {
287 if (qlcnic_sriov_vf_check(adapter))
288 return -EINVAL;
7f966452 289 num_msix = 1;
f8468331 290 }
7f966452
SC		 291 /* setup interrupt mapping table for fw */
292 ahw->intr_tbl = vzalloc(num_msix *
293 sizeof(struct qlcnic_intrpt_config));
294 if (!ahw->intr_tbl)
295 return -ENOMEM;
296 if (!(adapter->flags & QLCNIC_MSIX_ENABLED)) {
297 /* MSI-X enablement failed, use legacy interrupt */
298 adapter->tgt_status_reg = ahw->pci_base0 + QLC_83XX_INTX_PTR;
299 adapter->tgt_mask_reg = ahw->pci_base0 + QLC_83XX_INTX_MASK;
300 adapter->isr_int_vec = ahw->pci_base0 + QLC_83XX_INTX_TRGR;
301 adapter->msix_entries[0].vector = adapter->pdev->irq;
302 dev_info(&adapter->pdev->dev, "using legacy interrupt\n");
303 }
304
305 for (i = 0; i < num_msix; i++) {
306 if (adapter->flags & QLCNIC_MSIX_ENABLED)
307 ahw->intr_tbl[i].type = QLCNIC_INTRPT_MSIX;
308 else
309 ahw->intr_tbl[i].type = QLCNIC_INTRPT_INTX;
310 ahw->intr_tbl[i].id = i;
311 ahw->intr_tbl[i].src = 0;
312 }
313 return 0;
314}
315
ac166700
HM		 316inline void qlcnic_83xx_clear_legacy_intr_mask(struct qlcnic_adapter *adapter)
317{
318 writel(0, adapter->tgt_mask_reg);
319}
320
45ef92ed
HM		 321inline void qlcnic_83xx_set_legacy_intr_mask(struct qlcnic_adapter *adapter)
322{
323 writel(1, adapter->tgt_mask_reg);
324}
325
ac166700
HM		 326/* Enable MSI-x and INT-x interrupts */
327void qlcnic_83xx_enable_intr(struct qlcnic_adapter *adapter,
328 struct qlcnic_host_sds_ring *sds_ring)
7f966452
SC		 329{
330 writel(0, sds_ring->crb_intr_mask);
ac166700
HM		 331}
332
333/* Disable MSI-x and INT-x interrupts */
334void qlcnic_83xx_disable_intr(struct qlcnic_adapter *adapter,
335 struct qlcnic_host_sds_ring *sds_ring)
336{
337 writel(1, sds_ring->crb_intr_mask);
338}
339
340inline void qlcnic_83xx_enable_legacy_msix_mbx_intr(struct qlcnic_adapter
341 *adapter)
342{
343 u32 mask;
344
345 /* Mailbox in MSI-x mode and Legacy Interrupt share the same
346 * source register. We could be here before contexts are created
347 * and sds_ring->crb_intr_mask has not been initialized, calculate
348 * BAR offset for Interrupt Source Register
349 */
350 mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
351 writel(0, adapter->ahw->pci_base0 + mask);
352}
353
f036e4f4 354void qlcnic_83xx_disable_mbx_intr(struct qlcnic_adapter *adapter)
ac166700
HM		 355{
356 u32 mask;
357
358 mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
359 writel(1, adapter->ahw->pci_base0 + mask);
f036e4f4 360 QLCWRX(adapter->ahw, QLCNIC_MBX_INTR_ENBL, 0);
7f966452
SC		 361}
362
363static inline void qlcnic_83xx_get_mbx_data(struct qlcnic_adapter *adapter,
364 struct qlcnic_cmd_args *cmd)
365{
366 int i;
068a8d19
MC		 367
368 if (cmd->op_type == QLC_83XX_MBX_POST_BC_OP)
369 return;
370
7f966452
SC		 371 for (i = 0; i < cmd->rsp.num; i++)
372 cmd->rsp.arg[i] = readl(QLCNIC_MBX_FW(adapter->ahw, i));
373}
374
375irqreturn_t qlcnic_83xx_clear_legacy_intr(struct qlcnic_adapter *adapter)
376{
377 u32 intr_val;
378 struct qlcnic_hardware_context *ahw = adapter->ahw;
379 int retries = 0;
380
381 intr_val = readl(adapter->tgt_status_reg);
382
383 if (!QLC_83XX_VALID_INTX_BIT31(intr_val))
384 return IRQ_NONE;
385
386 if (QLC_83XX_INTX_FUNC(intr_val) != adapter->ahw->pci_func) {
387 adapter->stats.spurious_intr++;
388 return IRQ_NONE;
389 }
ac166700
HM		 390 /* The barrier is required to ensure writes to the registers */
391 wmb();
392
7f966452
SC		 393 /* clear the interrupt trigger control register */
394 writel(0, adapter->isr_int_vec);
ac166700 395 intr_val = readl(adapter->isr_int_vec);
7f966452
SC		 396 do {
397 intr_val = readl(adapter->tgt_status_reg);
398 if (QLC_83XX_INTX_FUNC(intr_val) != ahw->pci_func)
399 break;
400 retries++;
401 } while (QLC_83XX_VALID_INTX_BIT30(intr_val) &&
402 (retries < QLC_83XX_LEGACY_INTX_MAX_RETRY));
403
ac166700
HM		 404 return IRQ_HANDLED;
405}
406
e5c4e6c6
MC		 407static inline void qlcnic_83xx_notify_mbx_response(struct qlcnic_mailbox *mbx)
408{
409 atomic_set(&mbx->rsp_status, QLC_83XX_MBX_RESPONSE_ARRIVED);
410 complete(&mbx->completion);
411}
412
ac166700
HM		 413static void qlcnic_83xx_poll_process_aen(struct qlcnic_adapter *adapter)
414{
068a8d19
MC		 415 u32 resp, event, rsp_status = QLC_83XX_MBX_RESPONSE_ARRIVED;
416 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
ac166700
HM		 417 unsigned long flags;
418
068a8d19 419 spin_lock_irqsave(&mbx->aen_lock, flags);
ac166700
HM		 420 resp = QLCRDX(adapter->ahw, QLCNIC_FW_MBX_CTRL);
421 if (!(resp & QLCNIC_SET_OWNER))
422 goto out;
423
424 event = readl(QLCNIC_MBX_FW(adapter->ahw, 0));
068a8d19 425 if (event & QLCNIC_MBX_ASYNC_EVENT) {
d1a1105e 426 __qlcnic_83xx_process_aen(adapter);
068a8d19
MC		 427 } else {
428 if (atomic_read(&mbx->rsp_status) != rsp_status)
429 qlcnic_83xx_notify_mbx_response(mbx);
430 }
ac166700
HM		 431out:
432 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
068a8d19 433 spin_unlock_irqrestore(&mbx->aen_lock, flags);
ac166700
HM		 434}
435
436irqreturn_t qlcnic_83xx_intr(int irq, void *data)
437{
438 struct qlcnic_adapter *adapter = data;
439 struct qlcnic_host_sds_ring *sds_ring;
440 struct qlcnic_hardware_context *ahw = adapter->ahw;
441
442 if (qlcnic_83xx_clear_legacy_intr(adapter) == IRQ_NONE)
7f966452 443 return IRQ_NONE;
ac166700
HM		 444
445 qlcnic_83xx_poll_process_aen(adapter);
446
447 if (ahw->diag_test == QLCNIC_INTERRUPT_TEST) {
448 ahw->diag_cnt++;
449 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
450 return IRQ_HANDLED;
7f966452
SC		 451 }
452
ac166700
HM		 453 if (!test_bit(__QLCNIC_DEV_UP, &adapter->state)) {
454 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
455 } else {
456 sds_ring = &adapter->recv_ctx->sds_rings[0];
457 napi_schedule(&sds_ring->napi);
458 }
7f966452
SC		 459
460 return IRQ_HANDLED;
461}
462
463irqreturn_t qlcnic_83xx_tmp_intr(int irq, void *data)
464{
465 struct qlcnic_host_sds_ring *sds_ring = data;
466 struct qlcnic_adapter *adapter = sds_ring->adapter;
467
468 if (adapter->flags & QLCNIC_MSIX_ENABLED)
469 goto done;
470
471 if (adapter->nic_ops->clear_legacy_intr(adapter) == IRQ_NONE)
472 return IRQ_NONE;
473
474done:
475 adapter->ahw->diag_cnt++;
476 qlcnic_83xx_enable_intr(adapter, sds_ring);
477
478 return IRQ_HANDLED;
479}
480
481void qlcnic_83xx_free_mbx_intr(struct qlcnic_adapter *adapter)
482{
f036e4f4
RB		 483 u32 num_msix;
484
45ef92ed
HM		 485 if (!(adapter->flags & QLCNIC_MSIX_ENABLED))
486 qlcnic_83xx_set_legacy_intr_mask(adapter);
487
f036e4f4 488 qlcnic_83xx_disable_mbx_intr(adapter);
7f966452 489
ac166700
HM		 490 if (adapter->flags & QLCNIC_MSIX_ENABLED)
491 num_msix = adapter->ahw->num_msix - 1;
492 else
493 num_msix = 0;
7f966452 494
ac166700
HM		 495 msleep(20);
496 synchronize_irq(adapter->msix_entries[num_msix].vector);
497 free_irq(adapter->msix_entries[num_msix].vector, adapter);
7f966452
SC		 498}
499
500int qlcnic_83xx_setup_mbx_intr(struct qlcnic_adapter *adapter)
501{
502 irq_handler_t handler;
503 u32 val;
7f966452
SC		 504 int err = 0;
505 unsigned long flags = 0;
506
507 if (!(adapter->flags & QLCNIC_MSI_ENABLED) &&
508 !(adapter->flags & QLCNIC_MSIX_ENABLED))
509 flags |= IRQF_SHARED;
510
511 if (adapter->flags & QLCNIC_MSIX_ENABLED) {
512 handler = qlcnic_83xx_handle_aen;
513 val = adapter->msix_entries[adapter->ahw->num_msix - 1].vector;
aa2a8034 514 err = request_irq(val, handler, flags, "qlcnic-MB", adapter);
7f966452
SC		 515 if (err) {
516 dev_err(&adapter->pdev->dev,
517 "failed to register MBX interrupt\n");
518 return err;
519 }
ac166700
HM		 520 } else {
521 handler = qlcnic_83xx_intr;
522 val = adapter->msix_entries[0].vector;
523 err = request_irq(val, handler, flags, "qlcnic", adapter);
524 if (err) {
525 dev_err(&adapter->pdev->dev,
526 "failed to register INTx interrupt\n");
527 return err;
528 }
529 qlcnic_83xx_clear_legacy_intr_mask(adapter);
7f966452
SC		 530 }
531
532 /* Enable mailbox interrupt */
e5c4e6c6 533 qlcnic_83xx_enable_mbx_interrupt(adapter);
7f966452
SC		 534
535 return err;
536}
537
538void qlcnic_83xx_get_func_no(struct qlcnic_adapter *adapter)
539{
540 u32 val = QLCRDX(adapter->ahw, QLCNIC_INFORMANT);
f8468331 541 adapter->ahw->pci_func = (val >> 24) & 0xff;
7f966452
SC		 542}
543
544int qlcnic_83xx_cam_lock(struct qlcnic_adapter *adapter)
545{
546 void __iomem *addr;
547 u32 val, limit = 0;
548
549 struct qlcnic_hardware_context *ahw = adapter->ahw;
550
551 addr = ahw->pci_base0 + QLC_83XX_SEM_LOCK_FUNC(ahw->pci_func);
552 do {
553 val = readl(addr);
554 if (val) {
555 /* write the function number to register */
556 QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER,
557 ahw->pci_func);
558 return 0;
559 }
560 usleep_range(1000, 2000);
561 } while (++limit <= QLCNIC_PCIE_SEM_TIMEOUT);
562
563 return -EIO;
564}
565
566void qlcnic_83xx_cam_unlock(struct qlcnic_adapter *adapter)
567{
568 void __iomem *addr;
569 u32 val;
570 struct qlcnic_hardware_context *ahw = adapter->ahw;
571
572 addr = ahw->pci_base0 + QLC_83XX_SEM_UNLOCK_FUNC(ahw->pci_func);
573 val = readl(addr);
574}
575
576void qlcnic_83xx_read_crb(struct qlcnic_adapter *adapter, char *buf,
577 loff_t offset, size_t size)
578{
4bd8e738 579 int ret = 0;
7f966452
SC		 580 u32 data;
581
582 if (qlcnic_api_lock(adapter)) {
583 dev_err(&adapter->pdev->dev,
584 "%s: failed to acquire lock. addr offset 0x%x\n",
585 __func__, (u32)offset);
586 return;
587 }
588
4bd8e738 589 data = QLCRD32(adapter, (u32) offset, &ret);
7f966452
SC		 590 qlcnic_api_unlock(adapter);
591
592 if (ret == -EIO) {
593 dev_err(&adapter->pdev->dev,
594 "%s: failed. addr offset 0x%x\n",
595 __func__, (u32)offset);
596 return;
597 }
7f966452
SC		 598 memcpy(buf, &data, size);
599}
600
601void qlcnic_83xx_write_crb(struct qlcnic_adapter *adapter, char *buf,
602 loff_t offset, size_t size)
603{
604 u32 data;
605
606 memcpy(&data, buf, size);
607 qlcnic_83xx_wrt_reg_indirect(adapter, (u32) offset, data);
608}
609
610int qlcnic_83xx_get_port_info(struct qlcnic_adapter *adapter)
611{
612 int status;
613
614 status = qlcnic_83xx_get_port_config(adapter);
615 if (status) {
616 dev_err(&adapter->pdev->dev,
617 "Get Port Info failed\n");
618 } else {
619 if (QLC_83XX_SFP_10G_CAPABLE(adapter->ahw->port_config))
620 adapter->ahw->port_type = QLCNIC_XGBE;
621 else
622 adapter->ahw->port_type = QLCNIC_GBE;
629263ac 623
7f966452
SC		 624 if (QLC_83XX_AUTONEG(adapter->ahw->port_config))
625 adapter->ahw->link_autoneg = AUTONEG_ENABLE;
626 }
627 return status;
628}
629
52e493d0
JK		 630void qlcnic_83xx_set_mac_filter_count(struct qlcnic_adapter *adapter)
631{
632 struct qlcnic_hardware_context *ahw = adapter->ahw;
633 u16 act_pci_fn = ahw->act_pci_func;
634 u16 count;
635
636 ahw->max_mc_count = QLC_83XX_MAX_MC_COUNT;
637 if (act_pci_fn <= 2)
638 count = (QLC_83XX_MAX_UC_COUNT - QLC_83XX_MAX_MC_COUNT) /
639 act_pci_fn;
640 else
641 count = (QLC_83XX_LB_MAX_FILTERS - QLC_83XX_MAX_MC_COUNT) /
642 act_pci_fn;
643 ahw->max_uc_count = count;
644}
645
e5c4e6c6 646void qlcnic_83xx_enable_mbx_interrupt(struct qlcnic_adapter *adapter)
7f966452
SC		 647{
648 u32 val;
649
650 if (adapter->flags & QLCNIC_MSIX_ENABLED)
651 val = BIT_2 | ((adapter->ahw->num_msix - 1) << 8);
652 else
653 val = BIT_2;
629263ac 654
7f966452 655 QLCWRX(adapter->ahw, QLCNIC_MBX_INTR_ENBL, val);
ac166700 656 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
7f966452
SC		 657}
658
659void qlcnic_83xx_check_vf(struct qlcnic_adapter *adapter,
660 const struct pci_device_id *ent)
661{
662 u32 op_mode, priv_level;
663 struct qlcnic_hardware_context *ahw = adapter->ahw;
664
7f966452 665 ahw->fw_hal_version = 2;
7f966452
SC		 666 qlcnic_get_func_no(adapter);
667
f8468331
RB		 668 if (qlcnic_sriov_vf_check(adapter)) {
669 qlcnic_sriov_vf_set_ops(adapter);
670 return;
671 }
672
7f966452
SC		 673 /* Determine function privilege level */
674 op_mode = QLCRDX(adapter->ahw, QLC_83XX_DRV_OP_MODE);
675 if (op_mode == QLC_83XX_DEFAULT_OPMODE)
676 priv_level = QLCNIC_MGMT_FUNC;
677 else
678 priv_level = QLC_83XX_GET_FUNC_PRIVILEGE(op_mode,
679 ahw->pci_func);
680
681 if (priv_level == QLCNIC_NON_PRIV_FUNC) {
682 ahw->op_mode = QLCNIC_NON_PRIV_FUNC;
683 dev_info(&adapter->pdev->dev,
684 "HAL Version: %d Non Privileged function\n",
685 ahw->fw_hal_version);
686 adapter->nic_ops = &qlcnic_vf_ops;
687 } else {
02feda17
RB		 688 if (pci_find_ext_capability(adapter->pdev,
689 PCI_EXT_CAP_ID_SRIOV))
690 set_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state);
7f966452
SC		 691 adapter->nic_ops = &qlcnic_83xx_ops;
692 }
693}
694
695static void qlcnic_83xx_handle_link_aen(struct qlcnic_adapter *adapter,
696 u32 data[]);
697static void qlcnic_83xx_handle_idc_comp_aen(struct qlcnic_adapter *adapter,
698 u32 data[]);
699
012ec812
HM		 700void qlcnic_dump_mbx(struct qlcnic_adapter *adapter,
701 struct qlcnic_cmd_args *cmd)
7f966452
SC		 702{
703 int i;
704
068a8d19
MC		 705 if (cmd->op_type == QLC_83XX_MBX_POST_BC_OP)
706 return;
707
7f966452
SC		 708 dev_info(&adapter->pdev->dev,
709 "Host MBX regs(%d)\n", cmd->req.num);
710 for (i = 0; i < cmd->req.num; i++) {
711 if (i && !(i % 8))
712 pr_info("\n");
713 pr_info("%08x ", cmd->req.arg[i]);
714 }
715 pr_info("\n");
716 dev_info(&adapter->pdev->dev,
717 "FW MBX regs(%d)\n", cmd->rsp.num);
718 for (i = 0; i < cmd->rsp.num; i++) {
719 if (i && !(i % 8))
720 pr_info("\n");
721 pr_info("%08x ", cmd->rsp.arg[i]);
722 }
723 pr_info("\n");
724}
725
068a8d19
MC		 726static inline void
727qlcnic_83xx_poll_for_mbx_completion(struct qlcnic_adapter *adapter,
728 struct qlcnic_cmd_args *cmd)
65ab999d 729{
068a8d19
MC		 730 struct qlcnic_hardware_context *ahw = adapter->ahw;
731 int opcode = LSW(cmd->req.arg[0]);
732 unsigned long max_loops;
65ab999d 733
068a8d19 734 max_loops = cmd->total_cmds * QLC_83XX_MBX_CMD_LOOP;
65ab999d 735
068a8d19
MC		 736 for (; max_loops; max_loops--) {
737 if (atomic_read(&cmd->rsp_status) ==
738 QLC_83XX_MBX_RESPONSE_ARRIVED)
739 return;
740
741 udelay(1);
742 }
743
744 dev_err(&adapter->pdev->dev,
745 "%s: Mailbox command timed out, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
746 __func__, opcode, cmd->type, ahw->pci_func, ahw->op_mode);
747 flush_workqueue(ahw->mailbox->work_q);
748 return;
7f966452
SC		 749}
750
e5c4e6c6
MC		 751int qlcnic_83xx_issue_cmd(struct qlcnic_adapter *adapter,
752 struct qlcnic_cmd_args *cmd)
7f966452 753{
068a8d19 754 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
7f966452 755 struct qlcnic_hardware_context *ahw = adapter->ahw;
068a8d19
MC		 756 int cmd_type, err, opcode;
757 unsigned long timeout;
7f966452
SC		 758
759 opcode = LSW(cmd->req.arg[0]);
068a8d19
MC		 760 cmd_type = cmd->type;
761 err = mbx->ops->enqueue_cmd(adapter, cmd, &timeout);
762 if (err) {
763 dev_err(&adapter->pdev->dev,
764 "%s: Mailbox not available, cmd_op=0x%x, cmd_context=0x%x, pci_func=0x%x, op_mode=0x%x\n",
765 __func__, opcode, cmd->type, ahw->pci_func,
766 ahw->op_mode);
767 return err;
7f966452
SC		 768 }
769
068a8d19
MC		 770 switch (cmd_type) {
771 case QLC_83XX_MBX_CMD_WAIT:
772 if (!wait_for_completion_timeout(&cmd->completion, timeout)) {
65ab999d 773 dev_err(&adapter->pdev->dev,
068a8d19
MC		 774 "%s: Mailbox command timed out, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
775 __func__, opcode, cmd_type, ahw->pci_func,
776 ahw->op_mode);
777 flush_workqueue(mbx->work_q);
7f966452 778 }
068a8d19
MC		 779 break;
780 case QLC_83XX_MBX_CMD_NO_WAIT:
781 return 0;
782 case QLC_83XX_MBX_CMD_BUSY_WAIT:
783 qlcnic_83xx_poll_for_mbx_completion(adapter, cmd);
784 break;
785 default:
786 dev_err(&adapter->pdev->dev,
787 "%s: Invalid mailbox command, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
788 __func__, opcode, cmd_type, ahw->pci_func,
789 ahw->op_mode);
790 qlcnic_83xx_detach_mailbox_work(adapter);
7f966452 791 }
65ab999d 792
068a8d19 793 return cmd->rsp_opcode;
7f966452
SC		 794}
795
796int qlcnic_83xx_alloc_mbx_args(struct qlcnic_cmd_args *mbx,
797 struct qlcnic_adapter *adapter, u32 type)
798{
799 int i, size;
800 u32 temp;
801 const struct qlcnic_mailbox_metadata *mbx_tbl;
802
e5c4e6c6 803 memset(mbx, 0, sizeof(struct qlcnic_cmd_args));
7f966452
SC		 804 mbx_tbl = qlcnic_83xx_mbx_tbl;
805 size = ARRAY_SIZE(qlcnic_83xx_mbx_tbl);
806 for (i = 0; i < size; i++) {
807 if (type == mbx_tbl[i].cmd) {
f197a7aa 808 mbx->op_type = QLC_83XX_FW_MBX_CMD;
7f966452
SC		 809 mbx->req.num = mbx_tbl[i].in_args;
810 mbx->rsp.num = mbx_tbl[i].out_args;
811 mbx->req.arg = kcalloc(mbx->req.num, sizeof(u32),
812 GFP_ATOMIC);
813 if (!mbx->req.arg)
814 return -ENOMEM;
815 mbx->rsp.arg = kcalloc(mbx->rsp.num, sizeof(u32),
816 GFP_ATOMIC);
817 if (!mbx->rsp.arg) {
818 kfree(mbx->req.arg);
819 mbx->req.arg = NULL;
820 return -ENOMEM;
821 }
822 memset(mbx->req.arg, 0, sizeof(u32) * mbx->req.num);
823 memset(mbx->rsp.arg, 0, sizeof(u32) * mbx->rsp.num);
824 temp = adapter->ahw->fw_hal_version << 29;
825 mbx->req.arg[0] = (type | (mbx->req.num << 16) | temp);
068a8d19 826 mbx->cmd_op = type;
f197a7aa 827 return 0;
7f966452
SC		 828 }
829 }
f197a7aa 830 return -EINVAL;
7f966452
SC		 831}
832
833void qlcnic_83xx_idc_aen_work(struct work_struct *work)
834{
835 struct qlcnic_adapter *adapter;
836 struct qlcnic_cmd_args cmd;
837 int i, err = 0;
838
839 adapter = container_of(work, struct qlcnic_adapter, idc_aen_work.work);
b6b4316c
SS		 840 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_IDC_ACK);
841 if (err)
842 return;
7f966452
SC		 843
844 for (i = 1; i < QLC_83XX_MBX_AEN_CNT; i++)
845 cmd.req.arg[i] = adapter->ahw->mbox_aen[i];
846
847 err = qlcnic_issue_cmd(adapter, &cmd);
848 if (err)
849 dev_info(&adapter->pdev->dev,
850 "%s: Mailbox IDC ACK failed.\n", __func__);
851 qlcnic_free_mbx_args(&cmd);
852}
853
854static void qlcnic_83xx_handle_idc_comp_aen(struct qlcnic_adapter *adapter,
855 u32 data[])
856{
857 dev_dbg(&adapter->pdev->dev, "Completion AEN:0x%x.\n",
858 QLCNIC_MBX_RSP(data[0]));
629263ac 859 clear_bit(QLC_83XX_IDC_COMP_AEN, &adapter->ahw->idc.status);
7f966452
SC		 860 return;
861}
862
d1a1105e 863void __qlcnic_83xx_process_aen(struct qlcnic_adapter *adapter)
7f966452 864{
77bead46 865 struct qlcnic_hardware_context *ahw = adapter->ahw;
483202d5 866 u32 event[QLC_83XX_MBX_AEN_CNT];
7f966452 867 int i;
7f966452 868
7f966452
SC		 869 for (i = 0; i < QLC_83XX_MBX_AEN_CNT; i++)
870 event[i] = readl(QLCNIC_MBX_FW(ahw, i));
871
872 switch (QLCNIC_MBX_RSP(event[0])) {
873
874 case QLCNIC_MBX_LINK_EVENT:
875 qlcnic_83xx_handle_link_aen(adapter, event);
876 break;
877 case QLCNIC_MBX_COMP_EVENT:
878 qlcnic_83xx_handle_idc_comp_aen(adapter, event);
879 break;
880 case QLCNIC_MBX_REQUEST_EVENT:
881 for (i = 0; i < QLC_83XX_MBX_AEN_CNT; i++)
882 adapter->ahw->mbox_aen[i] = QLCNIC_MBX_RSP(event[i]);
883 queue_delayed_work(adapter->qlcnic_wq,
884 &adapter->idc_aen_work, 0);
885 break;
886 case QLCNIC_MBX_TIME_EXTEND_EVENT:
77bead46 887 ahw->extend_lb_time = event[1] >> 8 & 0xf;
7f966452 888 break;
f197a7aa
RB		 889 case QLCNIC_MBX_BC_EVENT:
890 qlcnic_sriov_handle_bc_event(adapter, event[1]);
891 break;
7f966452
SC		 892 case QLCNIC_MBX_SFP_INSERT_EVENT:
893 dev_info(&adapter->pdev->dev, "SFP+ Insert AEN:0x%x.\n",
894 QLCNIC_MBX_RSP(event[0]));
895 break;
896 case QLCNIC_MBX_SFP_REMOVE_EVENT:
897 dev_info(&adapter->pdev->dev, "SFP Removed AEN:0x%x.\n",
898 QLCNIC_MBX_RSP(event[0]));
899 break;
2d8ebcab
SC		 900 case QLCNIC_MBX_DCBX_CONFIG_CHANGE_EVENT:
901 qlcnic_dcb_handle_aen(adapter, (void *)&event[1]);
902 break;
7f966452
SC		 903 default:
904 dev_dbg(&adapter->pdev->dev, "Unsupported AEN:0x%x.\n",
905 QLCNIC_MBX_RSP(event[0]));
906 break;
907 }
908
909 QLCWRX(ahw, QLCNIC_FW_MBX_CTRL, QLCNIC_CLR_OWNER);
7f966452
SC		 910}
911
d1a1105e
RB		 912static void qlcnic_83xx_process_aen(struct qlcnic_adapter *adapter)
913{
068a8d19 914 u32 resp, event, rsp_status = QLC_83XX_MBX_RESPONSE_ARRIVED;
d1a1105e 915 struct qlcnic_hardware_context *ahw = adapter->ahw;
068a8d19 916 struct qlcnic_mailbox *mbx = ahw->mailbox;
d1a1105e
RB		 917 unsigned long flags;
918
068a8d19 919 spin_lock_irqsave(&mbx->aen_lock, flags);
d1a1105e
RB		 920 resp = QLCRDX(ahw, QLCNIC_FW_MBX_CTRL);
921 if (resp & QLCNIC_SET_OWNER) {
922 event = readl(QLCNIC_MBX_FW(ahw, 0));
068a8d19 923 if (event & QLCNIC_MBX_ASYNC_EVENT) {
d1a1105e 924 __qlcnic_83xx_process_aen(adapter);
068a8d19
MC		 925 } else {
926 if (atomic_read(&mbx->rsp_status) != rsp_status)
927 qlcnic_83xx_notify_mbx_response(mbx);
928 }
d1a1105e 929 }
068a8d19 930 spin_unlock_irqrestore(&mbx->aen_lock, flags);
d1a1105e
RB		 931}
932
7ed3ce48
RB		 933static void qlcnic_83xx_mbx_poll_work(struct work_struct *work)
934{
935 struct qlcnic_adapter *adapter;
936
937 adapter = container_of(work, struct qlcnic_adapter, mbx_poll_work.work);
938
939 if (!test_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state))
940 return;
941
942 qlcnic_83xx_process_aen(adapter);
943 queue_delayed_work(adapter->qlcnic_wq, &adapter->mbx_poll_work,
944 (HZ / 10));
945}
946
947void qlcnic_83xx_enable_mbx_poll(struct qlcnic_adapter *adapter)
948{
949 if (test_and_set_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state))
950 return;
951
952 INIT_DELAYED_WORK(&adapter->mbx_poll_work, qlcnic_83xx_mbx_poll_work);
79da4d08 953 queue_delayed_work(adapter->qlcnic_wq, &adapter->mbx_poll_work, 0);
7ed3ce48
RB		 954}
955
956void qlcnic_83xx_disable_mbx_poll(struct qlcnic_adapter *adapter)
957{
958 if (!test_and_clear_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state))
959 return;
960 cancel_delayed_work_sync(&adapter->mbx_poll_work);
961}
962
7f966452
SC		 963static int qlcnic_83xx_add_rings(struct qlcnic_adapter *adapter)
964{
965 int index, i, err, sds_mbx_size;
966 u32 *buf, intrpt_id, intr_mask;
967 u16 context_id;
968 u8 num_sds;
969 struct qlcnic_cmd_args cmd;
970 struct qlcnic_host_sds_ring *sds;
971 struct qlcnic_sds_mbx sds_mbx;
972 struct qlcnic_add_rings_mbx_out *mbx_out;
973 struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
974 struct qlcnic_hardware_context *ahw = adapter->ahw;
975
976 sds_mbx_size = sizeof(struct qlcnic_sds_mbx);
977 context_id = recv_ctx->context_id;
978 num_sds = (adapter->max_sds_rings - QLCNIC_MAX_RING_SETS);
979 ahw->hw_ops->alloc_mbx_args(&cmd, adapter,
980 QLCNIC_CMD_ADD_RCV_RINGS);
981 cmd.req.arg[1] = 0 | (num_sds << 8) | (context_id << 16);
982
983 /* set up status rings, mbx 2-81 */
984 index = 2;
985 for (i = 8; i < adapter->max_sds_rings; i++) {
986 memset(&sds_mbx, 0, sds_mbx_size);
987 sds = &recv_ctx->sds_rings[i];
988 sds->consumer = 0;
989 memset(sds->desc_head, 0, STATUS_DESC_RINGSIZE(sds));
a96227e6
SS		 990 sds_mbx.phy_addr_low = LSD(sds->phys_addr);
991 sds_mbx.phy_addr_high = MSD(sds->phys_addr);
7f966452
SC		 992 sds_mbx.sds_ring_size = sds->num_desc;
993
994 if (adapter->flags & QLCNIC_MSIX_ENABLED)
995 intrpt_id = ahw->intr_tbl[i].id;
996 else
997 intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
998
999 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1000 sds_mbx.intrpt_id = intrpt_id;
1001 else
1002 sds_mbx.intrpt_id = 0xffff;
1003 sds_mbx.intrpt_val = 0;
1004 buf = &cmd.req.arg[index];
1005 memcpy(buf, &sds_mbx, sds_mbx_size);
1006 index += sds_mbx_size / sizeof(u32);
1007 }
1008
1009 /* send the mailbox command */
1010 err = ahw->hw_ops->mbx_cmd(adapter, &cmd);
1011 if (err) {
1012 dev_err(&adapter->pdev->dev,
1013 "Failed to add rings %d\n", err);
1014 goto out;
1015 }
1016
1017 mbx_out = (struct qlcnic_add_rings_mbx_out *)&cmd.rsp.arg[1];
1018 index = 0;
1019 /* status descriptor ring */
1020 for (i = 8; i < adapter->max_sds_rings; i++) {
1021 sds = &recv_ctx->sds_rings[i];
1022 sds->crb_sts_consumer = ahw->pci_base0 +
1023 mbx_out->host_csmr[index];
1024 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1025 intr_mask = ahw->intr_tbl[i].src;
1026 else
1027 intr_mask = QLCRDX(ahw, QLCNIC_DEF_INT_MASK);
1028
1029 sds->crb_intr_mask = ahw->pci_base0 + intr_mask;
1030 index++;
1031 }
1032out:
1033 qlcnic_free_mbx_args(&cmd);
1034 return err;
1035}
1036
7cb03b23
RB		 1037void qlcnic_83xx_del_rx_ctx(struct qlcnic_adapter *adapter)
1038{
1039 int err;
1040 u32 temp = 0;
1041 struct qlcnic_cmd_args cmd;
1042 struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
1043
1044 if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_RX_CTX))
1045 return;
1046
1047 if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1048 cmd.req.arg[0] |= (0x3 << 29);
1049
1050 if (qlcnic_sriov_pf_check(adapter))
1051 qlcnic_pf_set_interface_id_del_rx_ctx(adapter, &temp);
1052
1053 cmd.req.arg[1] = recv_ctx->context_id | temp;
1054 err = qlcnic_issue_cmd(adapter, &cmd);
1055 if (err)
1056 dev_err(&adapter->pdev->dev,
1057 "Failed to destroy rx ctx in firmware\n");
1058
1059 recv_ctx->state = QLCNIC_HOST_CTX_STATE_FREED;
1060 qlcnic_free_mbx_args(&cmd);
1061}
1062
7f966452
SC		 1063int qlcnic_83xx_create_rx_ctx(struct qlcnic_adapter *adapter)
1064{
1065 int i, err, index, sds_mbx_size, rds_mbx_size;
1066 u8 num_sds, num_rds;
1067 u32 *buf, intrpt_id, intr_mask, cap = 0;
1068 struct qlcnic_host_sds_ring *sds;
1069 struct qlcnic_host_rds_ring *rds;
1070 struct qlcnic_sds_mbx sds_mbx;
1071 struct qlcnic_rds_mbx rds_mbx;
1072 struct qlcnic_cmd_args cmd;
1073 struct qlcnic_rcv_mbx_out *mbx_out;
1074 struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
1075 struct qlcnic_hardware_context *ahw = adapter->ahw;
1076 num_rds = adapter->max_rds_rings;
1077
1078 if (adapter->max_sds_rings <= QLCNIC_MAX_RING_SETS)
1079 num_sds = adapter->max_sds_rings;
1080 else
1081 num_sds = QLCNIC_MAX_RING_SETS;
1082
1083 sds_mbx_size = sizeof(struct qlcnic_sds_mbx);
1084 rds_mbx_size = sizeof(struct qlcnic_rds_mbx);
1085 cap = QLCNIC_CAP0_LEGACY_CONTEXT;
1086
1087 if (adapter->flags & QLCNIC_FW_LRO_MSS_CAP)
1088 cap |= QLC_83XX_FW_CAP_LRO_MSS;
1089
1090 /* set mailbox hdr and capabilities */
b6b4316c
SS		 1091 err = qlcnic_alloc_mbx_args(&cmd, adapter,
1092 QLCNIC_CMD_CREATE_RX_CTX);
1093 if (err)
1094 return err;
7cb03b23
RB		 1095
1096 if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1097 cmd.req.arg[0] |= (0x3 << 29);
1098
7f966452
SC		 1099 cmd.req.arg[1] = cap;
1100 cmd.req.arg[5] = 1 | (num_rds << 5) | (num_sds << 8) |
1101 (QLC_83XX_HOST_RDS_MODE_UNIQUE << 16);
7cb03b23
RB		 1102
1103 if (qlcnic_sriov_pf_check(adapter))
1104 qlcnic_pf_set_interface_id_create_rx_ctx(adapter,
1105 &cmd.req.arg[6]);
7f966452
SC		 1106 /* set up status rings, mbx 8-57/87 */
1107 index = QLC_83XX_HOST_SDS_MBX_IDX;
1108 for (i = 0; i < num_sds; i++) {
1109 memset(&sds_mbx, 0, sds_mbx_size);
1110 sds = &recv_ctx->sds_rings[i];
1111 sds->consumer = 0;
1112 memset(sds->desc_head, 0, STATUS_DESC_RINGSIZE(sds));
a96227e6
SS		 1113 sds_mbx.phy_addr_low = LSD(sds->phys_addr);
1114 sds_mbx.phy_addr_high = MSD(sds->phys_addr);
7f966452
SC		 1115 sds_mbx.sds_ring_size = sds->num_desc;
1116 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1117 intrpt_id = ahw->intr_tbl[i].id;
1118 else
1119 intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
1120 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1121 sds_mbx.intrpt_id = intrpt_id;
1122 else
1123 sds_mbx.intrpt_id = 0xffff;
1124 sds_mbx.intrpt_val = 0;
1125 buf = &cmd.req.arg[index];
1126 memcpy(buf, &sds_mbx, sds_mbx_size);
1127 index += sds_mbx_size / sizeof(u32);
1128 }
1129 /* set up receive rings, mbx 88-111/135 */
1130 index = QLCNIC_HOST_RDS_MBX_IDX;
1131 rds = &recv_ctx->rds_rings[0];
1132 rds->producer = 0;
1133 memset(&rds_mbx, 0, rds_mbx_size);
a96227e6
SS		 1134 rds_mbx.phy_addr_reg_low = LSD(rds->phys_addr);
1135 rds_mbx.phy_addr_reg_high = MSD(rds->phys_addr);
7f966452
SC		 1136 rds_mbx.reg_ring_sz = rds->dma_size;
1137 rds_mbx.reg_ring_len = rds->num_desc;
1138 /* Jumbo ring */
1139 rds = &recv_ctx->rds_rings[1];
1140 rds->producer = 0;
a96227e6
SS		 1141 rds_mbx.phy_addr_jmb_low = LSD(rds->phys_addr);
1142 rds_mbx.phy_addr_jmb_high = MSD(rds->phys_addr);
7f966452
SC		 1143 rds_mbx.jmb_ring_sz = rds->dma_size;
1144 rds_mbx.jmb_ring_len = rds->num_desc;
1145 buf = &cmd.req.arg[index];
1146 memcpy(buf, &rds_mbx, rds_mbx_size);
1147
1148 /* send the mailbox command */
1149 err = ahw->hw_ops->mbx_cmd(adapter, &cmd);
1150 if (err) {
1151 dev_err(&adapter->pdev->dev,
1152 "Failed to create Rx ctx in firmware%d\n", err);
1153 goto out;
1154 }
1155 mbx_out = (struct qlcnic_rcv_mbx_out *)&cmd.rsp.arg[1];
1156 recv_ctx->context_id = mbx_out->ctx_id;
1157 recv_ctx->state = mbx_out->state;
1158 recv_ctx->virt_port = mbx_out->vport_id;
1159 dev_info(&adapter->pdev->dev, "Rx Context[%d] Created, state:0x%x\n",
1160 recv_ctx->context_id, recv_ctx->state);
1161 /* Receive descriptor ring */
1162 /* Standard ring */
1163 rds = &recv_ctx->rds_rings[0];
1164 rds->crb_rcv_producer = ahw->pci_base0 +
1165 mbx_out->host_prod[0].reg_buf;
1166 /* Jumbo ring */
1167 rds = &recv_ctx->rds_rings[1];
1168 rds->crb_rcv_producer = ahw->pci_base0 +
1169 mbx_out->host_prod[0].jmb_buf;
1170 /* status descriptor ring */
1171 for (i = 0; i < num_sds; i++) {
1172 sds = &recv_ctx->sds_rings[i];
1173 sds->crb_sts_consumer = ahw->pci_base0 +
1174 mbx_out->host_csmr[i];
1175 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1176 intr_mask = ahw->intr_tbl[i].src;
1177 else
1178 intr_mask = QLCRDX(ahw, QLCNIC_DEF_INT_MASK);
1179 sds->crb_intr_mask = ahw->pci_base0 + intr_mask;
1180 }
1181
1182 if (adapter->max_sds_rings > QLCNIC_MAX_RING_SETS)
1183 err = qlcnic_83xx_add_rings(adapter);
1184out:
1185 qlcnic_free_mbx_args(&cmd);
1186 return err;
1187}
1188
7cb03b23
RB		 1189void qlcnic_83xx_del_tx_ctx(struct qlcnic_adapter *adapter,
1190 struct qlcnic_host_tx_ring *tx_ring)
1191{
1192 struct qlcnic_cmd_args cmd;
1193 u32 temp = 0;
1194
1195 if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_TX_CTX))
1196 return;
1197
1198 if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1199 cmd.req.arg[0] |= (0x3 << 29);
1200
1201 if (qlcnic_sriov_pf_check(adapter))
1202 qlcnic_pf_set_interface_id_del_tx_ctx(adapter, &temp);
1203
1204 cmd.req.arg[1] = tx_ring->ctx_id | temp;
1205 if (qlcnic_issue_cmd(adapter, &cmd))
1206 dev_err(&adapter->pdev->dev,
1207 "Failed to destroy tx ctx in firmware\n");
1208 qlcnic_free_mbx_args(&cmd);
1209}
1210
7f966452
SC		 1211int qlcnic_83xx_create_tx_ctx(struct qlcnic_adapter *adapter,
1212 struct qlcnic_host_tx_ring *tx, int ring)
1213{
1214 int err;
1215 u16 msix_id;
7cb03b23 1216 u32 *buf, intr_mask, temp = 0;
7f966452
SC		 1217 struct qlcnic_cmd_args cmd;
1218 struct qlcnic_tx_mbx mbx;
1219 struct qlcnic_tx_mbx_out *mbx_out;
1220 struct qlcnic_hardware_context *ahw = adapter->ahw;
da6c8063 1221 u32 msix_vector;
7f966452
SC		 1222
1223 /* Reset host resources */
1224 tx->producer = 0;
1225 tx->sw_consumer = 0;
1226 *(tx->hw_consumer) = 0;
1227
1228 memset(&mbx, 0, sizeof(struct qlcnic_tx_mbx));
1229
1230 /* setup mailbox inbox registerss */
a96227e6
SS		 1231 mbx.phys_addr_low = LSD(tx->phys_addr);
1232 mbx.phys_addr_high = MSD(tx->phys_addr);
1233 mbx.cnsmr_index_low = LSD(tx->hw_cons_phys_addr);
1234 mbx.cnsmr_index_high = MSD(tx->hw_cons_phys_addr);
7f966452 1235 mbx.size = tx->num_desc;
da6c8063
RB		 1236 if (adapter->flags & QLCNIC_MSIX_ENABLED) {
1237 if (!(adapter->flags & QLCNIC_TX_INTR_SHARED))
1238 msix_vector = adapter->max_sds_rings + ring;
1239 else
1240 msix_vector = adapter->max_sds_rings - 1;
1241 msix_id = ahw->intr_tbl[msix_vector].id;
1242 } else {
7f966452 1243 msix_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
da6c8063
RB		 1244 }
1245
7f966452
SC		 1246 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1247 mbx.intr_id = msix_id;
1248 else
1249 mbx.intr_id = 0xffff;
1250 mbx.src = 0;
1251
b6b4316c
SS		 1252 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CREATE_TX_CTX);
1253 if (err)
1254 return err;
7cb03b23
RB		 1255
1256 if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1257 cmd.req.arg[0] |= (0x3 << 29);
1258
1259 if (qlcnic_sriov_pf_check(adapter))
1260 qlcnic_pf_set_interface_id_create_tx_ctx(adapter, &temp);
1261
7f966452 1262 cmd.req.arg[1] = QLCNIC_CAP0_LEGACY_CONTEXT;
7cb03b23 1263 cmd.req.arg[5] = QLCNIC_MAX_TX_QUEUES | temp;
7f966452
SC		 1264 buf = &cmd.req.arg[6];
1265 memcpy(buf, &mbx, sizeof(struct qlcnic_tx_mbx));
1266 /* send the mailbox command*/
1267 err = qlcnic_issue_cmd(adapter, &cmd);
1268 if (err) {
1269 dev_err(&adapter->pdev->dev,
1270 "Failed to create Tx ctx in firmware 0x%x\n", err);
1271 goto out;
1272 }
1273 mbx_out = (struct qlcnic_tx_mbx_out *)&cmd.rsp.arg[2];
1274 tx->crb_cmd_producer = ahw->pci_base0 + mbx_out->host_prod;
1275 tx->ctx_id = mbx_out->ctx_id;
da6c8063
RB		 1276 if ((adapter->flags & QLCNIC_MSIX_ENABLED) &&
1277 !(adapter->flags & QLCNIC_TX_INTR_SHARED)) {
7f966452
SC		 1278 intr_mask = ahw->intr_tbl[adapter->max_sds_rings + ring].src;
1279 tx->crb_intr_mask = ahw->pci_base0 + intr_mask;
1280 }
1281 dev_info(&adapter->pdev->dev, "Tx Context[0x%x] Created, state:0x%x\n",
1282 tx->ctx_id, mbx_out->state);
1283out:
1284 qlcnic_free_mbx_args(&cmd);
1285 return err;
1286}
1287
13a82b44
MC		 1288static int qlcnic_83xx_diag_alloc_res(struct net_device *netdev, int test,
1289 int num_sds_ring)
ba4468db
JK		 1290{
1291 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1292 struct qlcnic_host_sds_ring *sds_ring;
1293 struct qlcnic_host_rds_ring *rds_ring;
13a82b44 1294 u16 adapter_state = adapter->is_up;
ba4468db
JK		 1295 u8 ring;
1296 int ret;
1297
1298 netif_device_detach(netdev);
1299
1300 if (netif_running(netdev))
1301 __qlcnic_down(adapter, netdev);
1302
1303 qlcnic_detach(adapter);
1304
1305 adapter->max_sds_rings = 1;
1306 adapter->ahw->diag_test = test;
1307 adapter->ahw->linkup = 0;
1308
1309 ret = qlcnic_attach(adapter);
1310 if (ret) {
1311 netif_device_attach(netdev);
1312 return ret;
1313 }
1314
1315 ret = qlcnic_fw_create_ctx(adapter);
1316 if (ret) {
1317 qlcnic_detach(adapter);
13a82b44
MC		 1318 if (adapter_state == QLCNIC_ADAPTER_UP_MAGIC) {
1319 adapter->max_sds_rings = num_sds_ring;
1320 qlcnic_attach(adapter);
1321 }
ba4468db
JK		 1322 netif_device_attach(netdev);
1323 return ret;
1324 }
1325
1326 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
1327 rds_ring = &adapter->recv_ctx->rds_rings[ring];
1328 qlcnic_post_rx_buffers(adapter, rds_ring, ring);
1329 }
1330
1331 if (adapter->ahw->diag_test == QLCNIC_INTERRUPT_TEST) {
1332 for (ring = 0; ring < adapter->max_sds_rings; ring++) {
1333 sds_ring = &adapter->recv_ctx->sds_rings[ring];
1334 qlcnic_83xx_enable_intr(adapter, sds_ring);
1335 }
1336 }
1337
1338 if (adapter->ahw->diag_test == QLCNIC_LOOPBACK_TEST) {
1339 /* disable and free mailbox interrupt */
79da4d08
MC		 1340 if (!(adapter->flags & QLCNIC_MSIX_ENABLED)) {
1341 qlcnic_83xx_enable_mbx_poll(adapter);
d1a1105e 1342 qlcnic_83xx_free_mbx_intr(adapter);
79da4d08 1343 }
ba4468db
JK		 1344 adapter->ahw->loopback_state = 0;
1345 adapter->ahw->hw_ops->setup_link_event(adapter, 1);
1346 }
1347
1348 set_bit(__QLCNIC_DEV_UP, &adapter->state);
1349 return 0;
1350}
1351
1352static void qlcnic_83xx_diag_free_res(struct net_device *netdev,
1353 int max_sds_rings)
1354{
1355 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1356 struct qlcnic_host_sds_ring *sds_ring;
1357 int ring, err;
1358
1359 clear_bit(__QLCNIC_DEV_UP, &adapter->state);
1360 if (adapter->ahw->diag_test == QLCNIC_INTERRUPT_TEST) {
1361 for (ring = 0; ring < adapter->max_sds_rings; ring++) {
1362 sds_ring = &adapter->recv_ctx->sds_rings[ring];
ac166700 1363 qlcnic_83xx_disable_intr(adapter, sds_ring);
79da4d08
MC		 1364 if (!(adapter->flags & QLCNIC_MSIX_ENABLED))
1365 qlcnic_83xx_enable_mbx_poll(adapter);
ba4468db
JK		 1366 }
1367 }
1368
1369 qlcnic_fw_destroy_ctx(adapter);
1370 qlcnic_detach(adapter);
1371
1372 if (adapter->ahw->diag_test == QLCNIC_LOOPBACK_TEST) {
d1a1105e
RB		 1373 if (!(adapter->flags & QLCNIC_MSIX_ENABLED)) {
1374 err = qlcnic_83xx_setup_mbx_intr(adapter);
79da4d08 1375 qlcnic_83xx_disable_mbx_poll(adapter);
d1a1105e
RB		 1376 if (err) {
1377 dev_err(&adapter->pdev->dev,
1378 "%s: failed to setup mbx interrupt\n",
1379 __func__);
1380 goto out;
1381 }
ba4468db
JK		 1382 }
1383 }
1384 adapter->ahw->diag_test = 0;
1385 adapter->max_sds_rings = max_sds_rings;
1386
1387 if (qlcnic_attach(adapter))
1388 goto out;
1389
1390 if (netif_running(netdev))
1391 __qlcnic_up(adapter, netdev);
79da4d08
MC		 1392
1393 if (adapter->ahw->diag_test == QLCNIC_INTERRUPT_TEST &&
1394 !(adapter->flags & QLCNIC_MSIX_ENABLED))
1395 qlcnic_83xx_disable_mbx_poll(adapter);
ba4468db
JK		 1396out:
1397 netif_device_attach(netdev);
1398}
1399
319ecf12
SC		 1400int qlcnic_83xx_config_led(struct qlcnic_adapter *adapter, u32 state,
1401 u32 beacon)
1402{
1403 struct qlcnic_cmd_args cmd;
1404 u32 mbx_in;
1405 int i, status = 0;
1406
1407 if (state) {
1408 /* Get LED configuration */
b6b4316c
SS		 1409 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1410 QLCNIC_CMD_GET_LED_CONFIG);
1411 if (status)
1412 return status;
1413
319ecf12
SC		 1414 status = qlcnic_issue_cmd(adapter, &cmd);
1415 if (status) {
1416 dev_err(&adapter->pdev->dev,
1417 "Get led config failed.\n");
1418 goto mbx_err;
1419 } else {
1420 for (i = 0; i < 4; i++)
1421 adapter->ahw->mbox_reg[i] = cmd.rsp.arg[i+1];
1422 }
1423 qlcnic_free_mbx_args(&cmd);
1424 /* Set LED Configuration */
1425 mbx_in = (LSW(QLC_83XX_LED_CONFIG) << 16) |
1426 LSW(QLC_83XX_LED_CONFIG);
b6b4316c
SS		 1427 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1428 QLCNIC_CMD_SET_LED_CONFIG);
1429 if (status)
1430 return status;
1431
319ecf12
SC		 1432 cmd.req.arg[1] = mbx_in;
1433 cmd.req.arg[2] = mbx_in;
1434 cmd.req.arg[3] = mbx_in;
1435 if (beacon)
1436 cmd.req.arg[4] = QLC_83XX_ENABLE_BEACON;
1437 status = qlcnic_issue_cmd(adapter, &cmd);
1438 if (status) {
1439 dev_err(&adapter->pdev->dev,
1440 "Set led config failed.\n");
1441 }
1442mbx_err:
1443 qlcnic_free_mbx_args(&cmd);
1444 return status;
1445
1446 } else {
1447 /* Restoring default LED configuration */
b6b4316c
SS		 1448 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1449 QLCNIC_CMD_SET_LED_CONFIG);
1450 if (status)
1451 return status;
1452
319ecf12
SC		 1453 cmd.req.arg[1] = adapter->ahw->mbox_reg[0];
1454 cmd.req.arg[2] = adapter->ahw->mbox_reg[1];
1455 cmd.req.arg[3] = adapter->ahw->mbox_reg[2];
1456 if (beacon)
1457 cmd.req.arg[4] = adapter->ahw->mbox_reg[3];
1458 status = qlcnic_issue_cmd(adapter, &cmd);
1459 if (status)
1460 dev_err(&adapter->pdev->dev,
1461 "Restoring led config failed.\n");
1462 qlcnic_free_mbx_args(&cmd);
1463 return status;
1464 }
1465}
1466
d16951d9
HM		 1467int qlcnic_83xx_set_led(struct net_device *netdev,
1468 enum ethtool_phys_id_state state)
1469{
1470 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1471 int err = -EIO, active = 1;
1472
1473 if (adapter->ahw->op_mode == QLCNIC_NON_PRIV_FUNC) {
1474 netdev_warn(netdev,
1475 "LED test is not supported in non-privileged mode\n");
1476 return -EOPNOTSUPP;
1477 }
1478
1479 switch (state) {
1480 case ETHTOOL_ID_ACTIVE:
1481 if (test_and_set_bit(__QLCNIC_LED_ENABLE, &adapter->state))
1482 return -EBUSY;
1483
1484 if (test_bit(__QLCNIC_RESETTING, &adapter->state))
1485 break;
1486
1487 err = qlcnic_83xx_config_led(adapter, active, 0);
1488 if (err)
1489 netdev_err(netdev, "Failed to set LED blink state\n");
1490 break;
1491 case ETHTOOL_ID_INACTIVE:
1492 active = 0;
1493
1494 if (test_bit(__QLCNIC_RESETTING, &adapter->state))
1495 break;
1496
1497 err = qlcnic_83xx_config_led(adapter, active, 0);
1498 if (err)
1499 netdev_err(netdev, "Failed to reset LED blink state\n");
1500 break;
1501
1502 default:
1503 return -EINVAL;
1504 }
1505
1506 if (!active || err)
1507 clear_bit(__QLCNIC_LED_ENABLE, &adapter->state);
1508
1509 return err;
1510}
1511
7f966452
SC		 1512void qlcnic_83xx_register_nic_idc_func(struct qlcnic_adapter *adapter,
1513 int enable)
1514{
1515 struct qlcnic_cmd_args cmd;
1516 int status;
1517
f8468331
RB		 1518 if (qlcnic_sriov_vf_check(adapter))
1519 return;
1520
7f966452 1521 if (enable) {
b6b4316c
SS		 1522 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1523 QLCNIC_CMD_INIT_NIC_FUNC);
1524 if (status)
1525 return;
1526
d5fcff04 1527 cmd.req.arg[1] = BIT_0 | BIT_31;
7f966452 1528 } else {
b6b4316c
SS		 1529 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1530 QLCNIC_CMD_STOP_NIC_FUNC);
1531 if (status)
1532 return;
1533
d5fcff04 1534 cmd.req.arg[1] = BIT_0 | BIT_31;
7f966452
SC		 1535 }
1536 status = qlcnic_issue_cmd(adapter, &cmd);
1537 if (status)
1538 dev_err(&adapter->pdev->dev,
1539 "Failed to %s in NIC IDC function event.\n",
1540 (enable ? "register" : "unregister"));
1541
1542 qlcnic_free_mbx_args(&cmd);
1543}
1544
1545int qlcnic_83xx_set_port_config(struct qlcnic_adapter *adapter)
1546{
1547 struct qlcnic_cmd_args cmd;
1548 int err;
1549
b6b4316c
SS		 1550 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_PORT_CONFIG);
1551 if (err)
1552 return err;
1553
7f966452
SC		 1554 cmd.req.arg[1] = adapter->ahw->port_config;
1555 err = qlcnic_issue_cmd(adapter, &cmd);
1556 if (err)
1557 dev_info(&adapter->pdev->dev, "Set Port Config failed.\n");
1558 qlcnic_free_mbx_args(&cmd);
1559 return err;
1560}
1561
1562int qlcnic_83xx_get_port_config(struct qlcnic_adapter *adapter)
1563{
1564 struct qlcnic_cmd_args cmd;
1565 int err;
1566
b6b4316c
SS		 1567 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PORT_CONFIG);
1568 if (err)
1569 return err;
1570
7f966452
SC		 1571 err = qlcnic_issue_cmd(adapter, &cmd);
1572 if (err)
1573 dev_info(&adapter->pdev->dev, "Get Port config failed\n");
1574 else
1575 adapter->ahw->port_config = cmd.rsp.arg[1];
1576 qlcnic_free_mbx_args(&cmd);
1577 return err;
1578}
1579
1580int qlcnic_83xx_setup_link_event(struct qlcnic_adapter *adapter, int enable)
1581{
1582 int err;
1583 u32 temp;
1584 struct qlcnic_cmd_args cmd;
1585
b6b4316c
SS		 1586 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LINK_EVENT);
1587 if (err)
1588 return err;
1589
7f966452
SC		 1590 temp = adapter->recv_ctx->context_id << 16;
1591 cmd.req.arg[1] = (enable ? 1 : 0) | BIT_8 | temp;
1592 err = qlcnic_issue_cmd(adapter, &cmd);
1593 if (err)
1594 dev_info(&adapter->pdev->dev,
1595 "Setup linkevent mailbox failed\n");
1596 qlcnic_free_mbx_args(&cmd);
1597 return err;
1598}
1599
7cb03b23
RB		 1600static void qlcnic_83xx_set_interface_id_promisc(struct qlcnic_adapter *adapter,
1601 u32 *interface_id)
1602{
1603 if (qlcnic_sriov_pf_check(adapter)) {
1604 qlcnic_pf_set_interface_id_promisc(adapter, interface_id);
1605 } else {
1606 if (!qlcnic_sriov_vf_check(adapter))
1607 *interface_id = adapter->recv_ctx->context_id << 16;
1608 }
1609}
1610
7f966452
SC		 1611int qlcnic_83xx_nic_set_promisc(struct qlcnic_adapter *adapter, u32 mode)
1612{
068a8d19 1613 struct qlcnic_cmd_args *cmd = NULL;
7cb03b23 1614 u32 temp = 0;
068a8d19 1615 int err;
7f966452
SC		 1616
1617 if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
1618 return -EIO;
1619
068a8d19
MC		 1620 cmd = kzalloc(sizeof(*cmd), GFP_ATOMIC);
1621 if (!cmd)
1622 return -ENOMEM;
1623
1624 err = qlcnic_alloc_mbx_args(cmd, adapter,
b6b4316c
SS		 1625 QLCNIC_CMD_CONFIGURE_MAC_RX_MODE);
1626 if (err)
068a8d19 1627 goto out;
b6b4316c 1628
068a8d19 1629 cmd->type = QLC_83XX_MBX_CMD_NO_WAIT;
7cb03b23 1630 qlcnic_83xx_set_interface_id_promisc(adapter, &temp);
068a8d19
MC		 1631 cmd->req.arg[1] = (mode ? 1 : 0) | temp;
1632 err = qlcnic_issue_cmd(adapter, cmd);
1633 if (!err)
1634 return err;
7f966452 1635
068a8d19
MC		 1636 qlcnic_free_mbx_args(cmd);
1637
1638out:
1639 kfree(cmd);
7f966452
SC		 1640 return err;
1641}
1642
ba4468db
JK		 1643int qlcnic_83xx_loopback_test(struct net_device *netdev, u8 mode)
1644{
1645 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1646 struct qlcnic_hardware_context *ahw = adapter->ahw;
1647 int ret = 0, loop = 0, max_sds_rings = adapter->max_sds_rings;
1648
ba4468db 1649 if (ahw->op_mode == QLCNIC_NON_PRIV_FUNC) {
4690a7e4
SC		 1650 netdev_warn(netdev,
1651 "Loopback test not supported in non privileged mode\n");
b9c11984 1652 return -ENOTSUPP;
ba4468db
JK		 1653 }
1654
4690a7e4
SC		 1655 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1656 netdev_info(netdev, "Device is resetting\n");
ba4468db 1657 return -EBUSY;
4690a7e4
SC		 1658 }
1659
1660 if (qlcnic_get_diag_lock(adapter)) {
1661 netdev_info(netdev, "Device is in diagnostics mode\n");
1662 return -EBUSY;
1663 }
1664
1665 netdev_info(netdev, "%s loopback test in progress\n",
1666 mode == QLCNIC_ILB_MODE ? "internal" : "external");
ba4468db 1667
13a82b44
MC		 1668 ret = qlcnic_83xx_diag_alloc_res(netdev, QLCNIC_LOOPBACK_TEST,
1669 max_sds_rings);
ba4468db
JK		 1670 if (ret)
1671 goto fail_diag_alloc;
1672
1673 ret = qlcnic_83xx_set_lb_mode(adapter, mode);
1674 if (ret)
1675 goto free_diag_res;
1676
1677 /* Poll for link up event before running traffic */
1678 do {
2c4a7878 1679 msleep(QLC_83XX_LB_MSLEEP_COUNT);
d1a1105e 1680
2c4a7878
JK		 1681 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1682 netdev_info(netdev,
1683 "Device is resetting, free LB test resources\n");
b9c11984 1684 ret = -EBUSY;
2c4a7878
JK		 1685 goto free_diag_res;
1686 }
1687 if (loop++ > QLC_83XX_LB_WAIT_COUNT) {
1688 netdev_info(netdev,
1689 "Firmware didn't sent link up event to loopback request\n");
b9c11984 1690 ret = -ETIMEDOUT;
ba4468db
JK		 1691 qlcnic_83xx_clear_lb_mode(adapter, mode);
1692 goto free_diag_res;
1693 }
1694 } while ((adapter->ahw->linkup && ahw->has_link_events) != 1);
1695
a4325ea2
JK		 1696 /* Make sure carrier is off and queue is stopped during loopback */
1697 if (netif_running(netdev)) {
1698 netif_carrier_off(netdev);
012ec812 1699 netif_tx_stop_all_queues(netdev);
a4325ea2
JK		 1700 }
1701
ba4468db
JK		 1702 ret = qlcnic_do_lb_test(adapter, mode);
1703
1704 qlcnic_83xx_clear_lb_mode(adapter, mode);
1705
1706free_diag_res:
1707 qlcnic_83xx_diag_free_res(netdev, max_sds_rings);
1708
1709fail_diag_alloc:
1710 adapter->max_sds_rings = max_sds_rings;
4690a7e4 1711 qlcnic_release_diag_lock(adapter);
ba4468db
JK		 1712 return ret;
1713}
1714
77bead46
MC		 1715static void qlcnic_extend_lb_idc_cmpltn_wait(struct qlcnic_adapter *adapter,
1716 u32 *max_wait_count)
1717{
1718 struct qlcnic_hardware_context *ahw = adapter->ahw;
1719 int temp;
1720
1721 netdev_info(adapter->netdev, "Recieved loopback IDC time extend event for 0x%x seconds\n",
1722 ahw->extend_lb_time);
1723 temp = ahw->extend_lb_time * 1000;
1724 *max_wait_count += temp / QLC_83XX_LB_MSLEEP_COUNT;
1725 ahw->extend_lb_time = 0;
1726}
1727
7f966452
SC		 1728int qlcnic_83xx_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
1729{
1730 struct qlcnic_hardware_context *ahw = adapter->ahw;
2c4a7878 1731 struct net_device *netdev = adapter->netdev;
77bead46 1732 u32 config, max_wait_count;
629263ac 1733 int status = 0, loop = 0;
7f966452 1734
77bead46
MC		 1735 ahw->extend_lb_time = 0;
1736 max_wait_count = QLC_83XX_LB_WAIT_COUNT;
7f966452
SC		 1737 status = qlcnic_83xx_get_port_config(adapter);
1738 if (status)
1739 return status;
1740
1741 config = ahw->port_config;
b9c11984
JK		 1742
1743 /* Check if port is already in loopback mode */
1744 if ((config & QLC_83XX_CFG_LOOPBACK_HSS) ||
1745 (config & QLC_83XX_CFG_LOOPBACK_EXT)) {
1746 netdev_err(netdev,
1747 "Port already in Loopback mode.\n");
1748 return -EINPROGRESS;
1749 }
1750
629263ac 1751 set_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
7f966452
SC		 1752
1753 if (mode == QLCNIC_ILB_MODE)
1754 ahw->port_config |= QLC_83XX_CFG_LOOPBACK_HSS;
1755 if (mode == QLCNIC_ELB_MODE)
1756 ahw->port_config |= QLC_83XX_CFG_LOOPBACK_EXT;
1757
1758 status = qlcnic_83xx_set_port_config(adapter);
1759 if (status) {
2c4a7878
JK		 1760 netdev_err(netdev,
1761 "Failed to Set Loopback Mode = 0x%x.\n",
1762 ahw->port_config);
7f966452 1763 ahw->port_config = config;
629263ac 1764 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
7f966452
SC		 1765 return status;
1766 }
1767
9a05f92b 1768 /* Wait for Link and IDC Completion AEN */
629263ac 1769 do {
2c4a7878 1770 msleep(QLC_83XX_LB_MSLEEP_COUNT);
d1a1105e 1771
2c4a7878
JK		 1772 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1773 netdev_info(netdev,
1774 "Device is resetting, free LB test resources\n");
1775 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
b9c11984 1776 return -EBUSY;
2c4a7878 1777 }
77bead46
MC		 1778
1779 if (ahw->extend_lb_time)
1780 qlcnic_extend_lb_idc_cmpltn_wait(adapter,
1781 &max_wait_count);
1782
1783 if (loop++ > max_wait_count) {
1784 netdev_err(netdev, "%s: Did not receive loopback IDC completion AEN\n",
1785 __func__);
629263ac 1786 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
9a05f92b 1787 qlcnic_83xx_clear_lb_mode(adapter, mode);
b9c11984 1788 return -ETIMEDOUT;
629263ac
SC		 1789 }
1790 } while (test_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status));
1791
7f966452
SC		 1792 qlcnic_sre_macaddr_change(adapter, adapter->mac_addr, 0,
1793 QLCNIC_MAC_ADD);
1794 return status;
1795}
1796
1797int qlcnic_83xx_clear_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
1798{
1799 struct qlcnic_hardware_context *ahw = adapter->ahw;
77bead46 1800 u32 config = ahw->port_config, max_wait_count;
2c4a7878 1801 struct net_device *netdev = adapter->netdev;
629263ac 1802 int status = 0, loop = 0;
7f966452 1803
77bead46
MC		 1804 ahw->extend_lb_time = 0;
1805 max_wait_count = QLC_83XX_LB_WAIT_COUNT;
629263ac 1806 set_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
7f966452
SC		 1807 if (mode == QLCNIC_ILB_MODE)
1808 ahw->port_config &= ~QLC_83XX_CFG_LOOPBACK_HSS;
1809 if (mode == QLCNIC_ELB_MODE)
1810 ahw->port_config &= ~QLC_83XX_CFG_LOOPBACK_EXT;
1811
1812 status = qlcnic_83xx_set_port_config(adapter);
1813 if (status) {
2c4a7878
JK		 1814 netdev_err(netdev,
1815 "Failed to Clear Loopback Mode = 0x%x.\n",
1816 ahw->port_config);
7f966452 1817 ahw->port_config = config;
629263ac 1818 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
7f966452
SC		 1819 return status;
1820 }
1821
9a05f92b 1822 /* Wait for Link and IDC Completion AEN */
629263ac 1823 do {
2c4a7878 1824 msleep(QLC_83XX_LB_MSLEEP_COUNT);
d1a1105e 1825
2c4a7878
JK		 1826 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1827 netdev_info(netdev,
1828 "Device is resetting, free LB test resources\n");
1829 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
b9c11984 1830 return -EBUSY;
2c4a7878
JK		 1831 }
1832
77bead46
MC		 1833 if (ahw->extend_lb_time)
1834 qlcnic_extend_lb_idc_cmpltn_wait(adapter,
1835 &max_wait_count);
1836
1837 if (loop++ > max_wait_count) {
1838 netdev_err(netdev, "%s: Did not receive loopback IDC completion AEN\n",
1839 __func__);
629263ac 1840 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
b9c11984 1841 return -ETIMEDOUT;
629263ac
SC		 1842 }
1843 } while (test_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status));
1844
7f966452
SC		 1845 qlcnic_sre_macaddr_change(adapter, adapter->mac_addr, 0,
1846 QLCNIC_MAC_DEL);
1847 return status;
1848}
1849
7cb03b23
RB		 1850static void qlcnic_83xx_set_interface_id_ipaddr(struct qlcnic_adapter *adapter,
1851 u32 *interface_id)
1852{
1853 if (qlcnic_sriov_pf_check(adapter)) {
1854 qlcnic_pf_set_interface_id_ipaddr(adapter, interface_id);
1855 } else {
1856 if (!qlcnic_sriov_vf_check(adapter))
1857 *interface_id = adapter->recv_ctx->context_id << 16;
1858 }
1859}
1860
7f966452
SC		 1861void qlcnic_83xx_config_ipaddr(struct qlcnic_adapter *adapter, __be32 ip,
1862 int mode)
1863{
1864 int err;
7cb03b23 1865 u32 temp = 0, temp_ip;
7f966452
SC		 1866 struct qlcnic_cmd_args cmd;
1867
b6b4316c
SS		 1868 err = qlcnic_alloc_mbx_args(&cmd, adapter,
1869 QLCNIC_CMD_CONFIGURE_IP_ADDR);
1870 if (err)
1871 return;
1872
7cb03b23
RB		 1873 qlcnic_83xx_set_interface_id_ipaddr(adapter, &temp);
1874
1875 if (mode == QLCNIC_IP_UP)
7f966452 1876 cmd.req.arg[1] = 1 | temp;
7cb03b23 1877 else
7f966452 1878 cmd.req.arg[1] = 2 | temp;
7f966452 1879
283c1c68
M		 1880 /*
1881 * Adapter needs IP address in network byte order.
1882 * But hardware mailbox registers go through writel(), hence IP address
1883 * gets swapped on big endian architecture.
1884 * To negate swapping of writel() on big endian architecture
1885 * use swab32(value).
1886 */
1887
1888 temp_ip = swab32(ntohl(ip));
1889 memcpy(&cmd.req.arg[2], &temp_ip, sizeof(u32));
7f966452
SC		 1890 err = qlcnic_issue_cmd(adapter, &cmd);
1891 if (err != QLCNIC_RCODE_SUCCESS)
1892 dev_err(&adapter->netdev->dev,
1893 "could not notify %s IP 0x%x request\n",
1894 (mode == QLCNIC_IP_UP) ? "Add" : "Remove", ip);
7cb03b23 1895
7f966452
SC		 1896 qlcnic_free_mbx_args(&cmd);
1897}
1898
1899int qlcnic_83xx_config_hw_lro(struct qlcnic_adapter *adapter, int mode)
1900{
1901 int err;
1902 u32 temp, arg1;
1903 struct qlcnic_cmd_args cmd;
283c1c68
M		 1904 int lro_bit_mask;
1905
1906 lro_bit_mask = (mode ? (BIT_0 | BIT_1 | BIT_2 | BIT_3) : 0);
7f966452
SC		 1907
1908 if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
1909 return 0;
1910
b6b4316c
SS		 1911 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIGURE_HW_LRO);
1912 if (err)
1913 return err;
1914
7f966452 1915 temp = adapter->recv_ctx->context_id << 16;
283c1c68 1916 arg1 = lro_bit_mask | temp;
7f966452
SC		 1917 cmd.req.arg[1] = arg1;
1918
1919 err = qlcnic_issue_cmd(adapter, &cmd);
1920 if (err)
1921 dev_info(&adapter->pdev->dev, "LRO config failed\n");
1922 qlcnic_free_mbx_args(&cmd);
1923
1924 return err;
1925}
1926
1927int qlcnic_83xx_config_rss(struct qlcnic_adapter *adapter, int enable)
1928{
1929 int err;
1930 u32 word;
1931 struct qlcnic_cmd_args cmd;
1932 const u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
1933 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
1934 0x255b0ec26d5a56daULL };
1935
b6b4316c
SS		 1936 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIGURE_RSS);
1937 if (err)
1938 return err;
7f966452
SC		 1939 /*
1940 * RSS request:
1941 * bits 3-0: Rsvd
1942 * 5-4: hash_type_ipv4
1943 * 7-6: hash_type_ipv6
1944 * 8: enable
1945 * 9: use indirection table
1946 * 16-31: indirection table mask
1947 */
1948 word = ((u32)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
1949 ((u32)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
1950 ((u32)(enable & 0x1) << 8) |
1951 ((0x7ULL) << 16);
1952 cmd.req.arg[1] = (adapter->recv_ctx->context_id);
1953 cmd.req.arg[2] = word;
1954 memcpy(&cmd.req.arg[4], key, sizeof(key));
1955
1956 err = qlcnic_issue_cmd(adapter, &cmd);
1957
1958 if (err)
1959 dev_info(&adapter->pdev->dev, "RSS config failed\n");
1960 qlcnic_free_mbx_args(&cmd);
1961
1962 return err;
1963
1964}
1965
7cb03b23
RB		 1966static void qlcnic_83xx_set_interface_id_macaddr(struct qlcnic_adapter *adapter,
1967 u32 *interface_id)
1968{
1969 if (qlcnic_sriov_pf_check(adapter)) {
1970 qlcnic_pf_set_interface_id_macaddr(adapter, interface_id);
1971 } else {
1972 if (!qlcnic_sriov_vf_check(adapter))
1973 *interface_id = adapter->recv_ctx->context_id << 16;
1974 }
1975}
1976
7f966452 1977int qlcnic_83xx_sre_macaddr_change(struct qlcnic_adapter *adapter, u8 *addr,
f80bc8fe 1978 u16 vlan_id, u8 op)
7f966452 1979{
068a8d19 1980 struct qlcnic_cmd_args *cmd = NULL;
7f966452 1981 struct qlcnic_macvlan_mbx mv;
068a8d19
MC		 1982 u32 *buf, temp = 0;
1983 int err;
7f966452
SC		 1984
1985 if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
1986 return -EIO;
1987
068a8d19
MC		 1988 cmd = kzalloc(sizeof(*cmd), GFP_ATOMIC);
1989 if (!cmd)
1990 return -ENOMEM;
1991
1992 err = qlcnic_alloc_mbx_args(cmd, adapter, QLCNIC_CMD_CONFIG_MAC_VLAN);
7f966452 1993 if (err)
068a8d19
MC		 1994 goto out;
1995
1996 cmd->type = QLC_83XX_MBX_CMD_NO_WAIT;
7f966452 1997
91b7282b
RB		 1998 if (vlan_id)
1999 op = (op == QLCNIC_MAC_ADD || op == QLCNIC_MAC_VLAN_ADD) ?
2000 QLCNIC_MAC_VLAN_ADD : QLCNIC_MAC_VLAN_DEL;
2001
068a8d19 2002 cmd->req.arg[1] = op | (1 << 8);
7cb03b23 2003 qlcnic_83xx_set_interface_id_macaddr(adapter, &temp);
068a8d19 2004 cmd->req.arg[1] |= temp;
f80bc8fe 2005 mv.vlan = vlan_id;
a96227e6
SS		 2006 mv.mac_addr0 = addr[0];
2007 mv.mac_addr1 = addr[1];
2008 mv.mac_addr2 = addr[2];
2009 mv.mac_addr3 = addr[3];
2010 mv.mac_addr4 = addr[4];
2011 mv.mac_addr5 = addr[5];
068a8d19 2012 buf = &cmd->req.arg[2];
7f966452 2013 memcpy(buf, &mv, sizeof(struct qlcnic_macvlan_mbx));
068a8d19
MC		 2014 err = qlcnic_issue_cmd(adapter, cmd);
2015 if (!err)
2016 return err;
2017
2018 qlcnic_free_mbx_args(cmd);
2019out:
2020 kfree(cmd);
7f966452
SC		 2021 return err;
2022}
2023
2024void qlcnic_83xx_change_l2_filter(struct qlcnic_adapter *adapter, u64 *addr,
f80bc8fe 2025 u16 vlan_id)
7f966452
SC		 2026{
2027 u8 mac[ETH_ALEN];
2028 memcpy(&mac, addr, ETH_ALEN);
2029 qlcnic_83xx_sre_macaddr_change(adapter, mac, vlan_id, QLCNIC_MAC_ADD);
2030}
2031
2032void qlcnic_83xx_configure_mac(struct qlcnic_adapter *adapter, u8 *mac,
2033 u8 type, struct qlcnic_cmd_args *cmd)
2034{
2035 switch (type) {
2036 case QLCNIC_SET_STATION_MAC:
2037 case QLCNIC_SET_FAC_DEF_MAC:
2038 memcpy(&cmd->req.arg[2], mac, sizeof(u32));
2039 memcpy(&cmd->req.arg[3], &mac[4], sizeof(u16));
2040 break;
2041 }
2042 cmd->req.arg[1] = type;
2043}
2044
07a251c8
SS		 2045int qlcnic_83xx_get_mac_address(struct qlcnic_adapter *adapter, u8 *mac,
2046 u8 function)
7f966452
SC		 2047{
2048 int err, i;
2049 struct qlcnic_cmd_args cmd;
2050 u32 mac_low, mac_high;
2051
07a251c8 2052 function = 0;
b6b4316c
SS		 2053 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_MAC_ADDRESS);
2054 if (err)
2055 return err;
2056
7f966452
SC		 2057 qlcnic_83xx_configure_mac(adapter, mac, QLCNIC_GET_CURRENT_MAC, &cmd);
2058 err = qlcnic_issue_cmd(adapter, &cmd);
2059
2060 if (err == QLCNIC_RCODE_SUCCESS) {
2061 mac_low = cmd.rsp.arg[1];
2062 mac_high = cmd.rsp.arg[2];
2063
2064 for (i = 0; i < 2; i++)
2065 mac[i] = (u8) (mac_high >> ((1 - i) * 8));
2066 for (i = 2; i < 6; i++)
2067 mac[i] = (u8) (mac_low >> ((5 - i) * 8));
2068 } else {
2069 dev_err(&adapter->pdev->dev, "Failed to get mac address%d\n",
2070 err);
2071 err = -EIO;
2072 }
2073 qlcnic_free_mbx_args(&cmd);
2074 return err;
2075}
2076
2077void qlcnic_83xx_config_intr_coal(struct qlcnic_adapter *adapter)
2078{
2079 int err;
be273dc1 2080 u16 temp;
7f966452
SC		 2081 struct qlcnic_cmd_args cmd;
2082 struct qlcnic_nic_intr_coalesce *coal = &adapter->ahw->coal;
2083
2084 if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
2085 return;
2086
b6b4316c
SS		 2087 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_INTR_COAL);
2088 if (err)
2089 return;
2090
be273dc1
HM		 2091 if (coal->type == QLCNIC_INTR_COAL_TYPE_RX) {
2092 temp = adapter->recv_ctx->context_id;
2093 cmd.req.arg[1] = QLCNIC_INTR_COAL_TYPE_RX | temp << 16;
2094 temp = coal->rx_time_us;
2095 cmd.req.arg[2] = coal->rx_packets | temp << 16;
2096 } else if (coal->type == QLCNIC_INTR_COAL_TYPE_TX) {
2097 temp = adapter->tx_ring->ctx_id;
2098 cmd.req.arg[1] = QLCNIC_INTR_COAL_TYPE_TX | temp << 16;
2099 temp = coal->tx_time_us;
2100 cmd.req.arg[2] = coal->tx_packets | temp << 16;
2101 }
7f966452 2102 cmd.req.arg[3] = coal->flag;
7f966452
SC		 2103 err = qlcnic_issue_cmd(adapter, &cmd);
2104 if (err != QLCNIC_RCODE_SUCCESS)
2105 dev_info(&adapter->pdev->dev,
2106 "Failed to send interrupt coalescence parameters\n");
2107 qlcnic_free_mbx_args(&cmd);
2108}
2109
2110static void qlcnic_83xx_handle_link_aen(struct qlcnic_adapter *adapter,
2111 u32 data[])
2112{
b1f5037f 2113 struct qlcnic_hardware_context *ahw = adapter->ahw;
7f966452
SC		 2114 u8 link_status, duplex;
2115 /* link speed */
2116 link_status = LSB(data[3]) & 1;
b1f5037f
RB		 2117 if (link_status) {
2118 ahw->link_speed = MSW(data[2]);
2119 duplex = LSB(MSW(data[3]));
2120 if (duplex)
2121 ahw->link_duplex = DUPLEX_FULL;
2122 else
2123 ahw->link_duplex = DUPLEX_HALF;
2124 } else {
2125 ahw->link_speed = SPEED_UNKNOWN;
2126 ahw->link_duplex = DUPLEX_UNKNOWN;
2127 }
2128
2129 ahw->link_autoneg = MSB(MSW(data[3]));
2130 ahw->module_type = MSB(LSW(data[3]));
2131 ahw->has_link_events = 1;
7f966452
SC		 2132 qlcnic_advert_link_change(adapter, link_status);
2133}
2134
2135irqreturn_t qlcnic_83xx_handle_aen(int irq, void *data)
2136{
2137 struct qlcnic_adapter *adapter = data;
068a8d19 2138 struct qlcnic_mailbox *mbx;
483202d5 2139 u32 mask, resp, event;
068a8d19 2140 unsigned long flags;
483202d5 2141
068a8d19
MC		 2142 mbx = adapter->ahw->mailbox;
2143 spin_lock_irqsave(&mbx->aen_lock, flags);
483202d5
JK		 2144 resp = QLCRDX(adapter->ahw, QLCNIC_FW_MBX_CTRL);
2145 if (!(resp & QLCNIC_SET_OWNER))
2146 goto out;
ac166700 2147
483202d5
JK		 2148 event = readl(QLCNIC_MBX_FW(adapter->ahw, 0));
2149 if (event & QLCNIC_MBX_ASYNC_EVENT)
d1a1105e 2150 __qlcnic_83xx_process_aen(adapter);
068a8d19
MC		 2151 else
2152 qlcnic_83xx_notify_mbx_response(mbx);
2153
483202d5
JK		 2154out:
2155 mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
2156 writel(0, adapter->ahw->pci_base0 + mask);
068a8d19 2157 spin_unlock_irqrestore(&mbx->aen_lock, flags);
7f966452
SC		 2158 return IRQ_HANDLED;
2159}
2160
2161int qlcnic_enable_eswitch(struct qlcnic_adapter *adapter, u8 port, u8 enable)
2162{
2163 int err = -EIO;
2164 struct qlcnic_cmd_args cmd;
2165
2166 if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC) {
2167 dev_err(&adapter->pdev->dev,
2168 "%s: Error, invoked by non management func\n",
2169 __func__);
2170 return err;
2171 }
2172
b6b4316c
SS		 2173 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_TOGGLE_ESWITCH);
2174 if (err)
2175 return err;
2176
7f966452
SC		 2177 cmd.req.arg[1] = (port & 0xf) | BIT_4;
2178 err = qlcnic_issue_cmd(adapter, &cmd);
2179
2180 if (err != QLCNIC_RCODE_SUCCESS) {
2181 dev_err(&adapter->pdev->dev, "Failed to enable eswitch%d\n",
2182 err);
2183 err = -EIO;
2184 }
2185 qlcnic_free_mbx_args(&cmd);
2186
2187 return err;
2188
2189}
2190
2191int qlcnic_83xx_set_nic_info(struct qlcnic_adapter *adapter,
2192 struct qlcnic_info *nic)
2193{
2194 int i, err = -EIO;
2195 struct qlcnic_cmd_args cmd;
2196
2197 if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC) {
2198 dev_err(&adapter->pdev->dev,
2199 "%s: Error, invoked by non management func\n",
2200 __func__);
2201 return err;
2202 }
2203
b6b4316c
SS		 2204 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_NIC_INFO);
2205 if (err)
2206 return err;
2207
7f966452
SC		 2208 cmd.req.arg[1] = (nic->pci_func << 16);
2209 cmd.req.arg[2] = 0x1 << 16;
2210 cmd.req.arg[3] = nic->phys_port | (nic->switch_mode << 16);
2211 cmd.req.arg[4] = nic->capabilities;
2212 cmd.req.arg[5] = (nic->max_mac_filters & 0xFF) | ((nic->max_mtu) << 16);
2213 cmd.req.arg[6] = (nic->max_tx_ques) | ((nic->max_rx_ques) << 16);
2214 cmd.req.arg[7] = (nic->min_tx_bw) | ((nic->max_tx_bw) << 16);
2215 for (i = 8; i < 32; i++)
2216 cmd.req.arg[i] = 0;
2217
2218 err = qlcnic_issue_cmd(adapter, &cmd);
2219
2220 if (err != QLCNIC_RCODE_SUCCESS) {
2221 dev_err(&adapter->pdev->dev, "Failed to set nic info%d\n",
2222 err);
2223 err = -EIO;
2224 }
2225
2226 qlcnic_free_mbx_args(&cmd);
2227
2228 return err;
2229}
2230
2231int qlcnic_83xx_get_nic_info(struct qlcnic_adapter *adapter,
2232 struct qlcnic_info *npar_info, u8 func_id)
2233{
2234 int err;
2235 u32 temp;
2236 u8 op = 0;
2237 struct qlcnic_cmd_args cmd;
8af3f33d 2238 struct qlcnic_hardware_context *ahw = adapter->ahw;
7f966452 2239
b6b4316c
SS		 2240 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_NIC_INFO);
2241 if (err)
2242 return err;
2243
8af3f33d 2244 if (func_id != ahw->pci_func) {
7f966452
SC		 2245 temp = func_id << 16;
2246 cmd.req.arg[1] = op | BIT_31 | temp;
2247 } else {
8af3f33d 2248 cmd.req.arg[1] = ahw->pci_func << 16;
7f966452
SC		 2249 }
2250 err = qlcnic_issue_cmd(adapter, &cmd);
2251 if (err) {
2252 dev_info(&adapter->pdev->dev,
2253 "Failed to get nic info %d\n", err);
2254 goto out;
2255 }
2256
2257 npar_info->op_type = cmd.rsp.arg[1];
2258 npar_info->pci_func = cmd.rsp.arg[2] & 0xFFFF;
2259 npar_info->op_mode = (cmd.rsp.arg[2] & 0xFFFF0000) >> 16;
2260 npar_info->phys_port = cmd.rsp.arg[3] & 0xFFFF;
2261 npar_info->switch_mode = (cmd.rsp.arg[3] & 0xFFFF0000) >> 16;
2262 npar_info->capabilities = cmd.rsp.arg[4];
2263 npar_info->max_mac_filters = cmd.rsp.arg[5] & 0xFF;
2264 npar_info->max_mtu = (cmd.rsp.arg[5] & 0xFFFF0000) >> 16;
2265 npar_info->max_tx_ques = cmd.rsp.arg[6] & 0xFFFF;
2266 npar_info->max_rx_ques = (cmd.rsp.arg[6] & 0xFFFF0000) >> 16;
2267 npar_info->min_tx_bw = cmd.rsp.arg[7] & 0xFFFF;
2268 npar_info->max_tx_bw = (cmd.rsp.arg[7] & 0xFFFF0000) >> 16;
2269 if (cmd.rsp.arg[8] & 0x1)
2270 npar_info->max_bw_reg_offset = (cmd.rsp.arg[8] & 0x7FFE) >> 1;
2271 if (cmd.rsp.arg[8] & 0x10000) {
2272 temp = (cmd.rsp.arg[8] & 0x7FFE0000) >> 17;
2273 npar_info->max_linkspeed_reg_offset = temp;
2274 }
8af3f33d
PP		 2275 if (npar_info->capabilities & QLCNIC_FW_CAPABILITY_MORE_CAPS)
2276 memcpy(ahw->extra_capability, &cmd.rsp.arg[16],
2277 sizeof(ahw->extra_capability));
7f966452
SC		 2278
2279out:
2280 qlcnic_free_mbx_args(&cmd);
2281 return err;
2282}
2283
2284int qlcnic_83xx_get_pci_info(struct qlcnic_adapter *adapter,
2285 struct qlcnic_pci_info *pci_info)
2286{
ee9e8b6c
MC		 2287 struct qlcnic_hardware_context *ahw = adapter->ahw;
2288 struct device *dev = &adapter->pdev->dev;
2289 struct qlcnic_cmd_args cmd;
7f966452
SC		 2290 int i, err = 0, j = 0;
2291 u32 temp;
7f966452 2292
b6b4316c
SS		 2293 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PCI_INFO);
2294 if (err)
2295 return err;
2296
7f966452
SC		 2297 err = qlcnic_issue_cmd(adapter, &cmd);
2298
ee9e8b6c 2299 ahw->act_pci_func = 0;
7f966452 2300 if (err == QLCNIC_RCODE_SUCCESS) {
ee9e8b6c 2301 ahw->max_pci_func = cmd.rsp.arg[1] & 0xFF;
7f966452
SC		 2302 for (i = 2, j = 0; j < QLCNIC_MAX_PCI_FUNC; j++, pci_info++) {
2303 pci_info->id = cmd.rsp.arg[i] & 0xFFFF;
2304 pci_info->active = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2305 i++;
2306 pci_info->type = cmd.rsp.arg[i] & 0xFFFF;
2307 if (pci_info->type == QLCNIC_TYPE_NIC)
ee9e8b6c 2308 ahw->act_pci_func++;
7f966452
SC		 2309 temp = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2310 pci_info->default_port = temp;
2311 i++;
2312 pci_info->tx_min_bw = cmd.rsp.arg[i] & 0xFFFF;
2313 temp = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2314 pci_info->tx_max_bw = temp;
2315 i = i + 2;
2316 memcpy(pci_info->mac, &cmd.rsp.arg[i], ETH_ALEN - 2);
2317 i++;
2318 memcpy(pci_info->mac + sizeof(u32), &cmd.rsp.arg[i], 2);
2319 i = i + 3;
ee9e8b6c
MC		 2320 if (ahw->op_mode == QLCNIC_MGMT_FUNC)
2321 dev_info(dev, "id = %d active = %d type = %d\n"
2322 "\tport = %d min bw = %d max bw = %d\n"
2323 "\tmac_addr = %pM\n", pci_info->id,
2324 pci_info->active, pci_info->type,
2325 pci_info->default_port,
2326 pci_info->tx_min_bw,
2327 pci_info->tx_max_bw, pci_info->mac);
7f966452 2328 }
ee9e8b6c
MC		 2329 if (ahw->op_mode == QLCNIC_MGMT_FUNC)
2330 dev_info(dev, "Max vNIC functions = %d, active vNIC functions = %d\n",
2331 ahw->max_pci_func, ahw->act_pci_func);
2332
7f966452 2333 } else {
ee9e8b6c 2334 dev_err(dev, "Failed to get PCI Info, error = %d\n", err);
7f966452
SC		 2335 err = -EIO;
2336 }
2337
2338 qlcnic_free_mbx_args(&cmd);
2339
2340 return err;
2341}
2342
2343int qlcnic_83xx_config_intrpt(struct qlcnic_adapter *adapter, bool op_type)
2344{
2345 int i, index, err;
7f966452 2346 u8 max_ints;
e2ab1233 2347 u32 val, temp, type;
7f966452
SC		 2348 struct qlcnic_cmd_args cmd;
2349
7dd90cf1 2350 max_ints = adapter->ahw->num_msix - 1;
b6b4316c
SS		 2351 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_INTRPT);
2352 if (err)
2353 return err;
2354
7f966452 2355 cmd.req.arg[1] = max_ints;
7cb03b23
RB		 2356
2357 if (qlcnic_sriov_vf_check(adapter))
2358 cmd.req.arg[1] |= (adapter->ahw->pci_func << 8) | BIT_16;
2359
7f966452
SC		 2360 for (i = 0, index = 2; i < max_ints; i++) {
2361 type = op_type ? QLCNIC_INTRPT_ADD : QLCNIC_INTRPT_DEL;
2362 val = type | (adapter->ahw->intr_tbl[i].type << 4);
2363 if (adapter->ahw->intr_tbl[i].type == QLCNIC_INTRPT_MSIX)
2364 val |= (adapter->ahw->intr_tbl[i].id << 16);
2365 cmd.req.arg[index++] = val;
2366 }
2367 err = qlcnic_issue_cmd(adapter, &cmd);
2368 if (err) {
2369 dev_err(&adapter->pdev->dev,
2370 "Failed to configure interrupts 0x%x\n", err);
2371 goto out;
2372 }
2373
2374 max_ints = cmd.rsp.arg[1];
2375 for (i = 0, index = 2; i < max_ints; i++, index += 2) {
2376 val = cmd.rsp.arg[index];
2377 if (LSB(val)) {
2378 dev_info(&adapter->pdev->dev,
2379 "Can't configure interrupt %d\n",
2380 adapter->ahw->intr_tbl[i].id);
2381 continue;
2382 }
2383 if (op_type) {
2384 adapter->ahw->intr_tbl[i].id = MSW(val);
2385 adapter->ahw->intr_tbl[i].enabled = 1;
2386 temp = cmd.rsp.arg[index + 1];
2387 adapter->ahw->intr_tbl[i].src = temp;
2388 } else {
2389 adapter->ahw->intr_tbl[i].id = i;
2390 adapter->ahw->intr_tbl[i].enabled = 0;
2391 adapter->ahw->intr_tbl[i].src = 0;
2392 }
2393 }
2394out:
2395 qlcnic_free_mbx_args(&cmd);
2396 return err;
2397}
d865ebb4
SC		 2398
2399int qlcnic_83xx_lock_flash(struct qlcnic_adapter *adapter)
2400{
2401 int id, timeout = 0;
2402 u32 status = 0;
2403
2404 while (status == 0) {
2405 status = QLC_SHARED_REG_RD32(adapter, QLCNIC_FLASH_LOCK);
2406 if (status)
2407 break;
2408
2409 if (++timeout >= QLC_83XX_FLASH_LOCK_TIMEOUT) {
2410 id = QLC_SHARED_REG_RD32(adapter,
2411 QLCNIC_FLASH_LOCK_OWNER);
2412 dev_err(&adapter->pdev->dev,
2413 "%s: failed, lock held by %d\n", __func__, id);
2414 return -EIO;
2415 }
2416 usleep_range(1000, 2000);
2417 }
2418
2419 QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER, adapter->portnum);
2420 return 0;
2421}
2422
2423void qlcnic_83xx_unlock_flash(struct qlcnic_adapter *adapter)
2424{
2425 QLC_SHARED_REG_RD32(adapter, QLCNIC_FLASH_UNLOCK);
2426 QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER, 0xFF);
2427}
2428
629263ac
SC		 2429int qlcnic_83xx_lockless_flash_read32(struct qlcnic_adapter *adapter,
2430 u32 flash_addr, u8 *p_data,
2431 int count)
d865ebb4 2432{
4bd8e738 2433 u32 word, range, flash_offset, addr = flash_addr, ret;
d865ebb4 2434 ulong indirect_add, direct_window;
4bd8e738 2435 int i, err = 0;
d865ebb4
SC		 2436
2437 flash_offset = addr & (QLCNIC_FLASH_SECTOR_SIZE - 1);
2438 if (addr & 0x3) {
2439 dev_err(&adapter->pdev->dev, "Illegal addr = 0x%x\n", addr);
2440 return -EIO;
2441 }
2442
2443 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_DIRECT_WINDOW,
2444 (addr));
2445
2446 range = flash_offset + (count * sizeof(u32));
2447 /* Check if data is spread across multiple sectors */
2448 if (range > (QLCNIC_FLASH_SECTOR_SIZE - 1)) {
2449
2450 /* Multi sector read */
2451 for (i = 0; i < count; i++) {
2452 indirect_add = QLC_83XX_FLASH_DIRECT_DATA(addr);
4bd8e738
HM		 2453 ret = QLCRD32(adapter, indirect_add, &err);
2454 if (err == -EIO)
2455 return err;
d865ebb4
SC		 2456
2457 word = ret;
2458 *(u32 *)p_data = word;
2459 p_data = p_data + 4;
2460 addr = addr + 4;
2461 flash_offset = flash_offset + 4;
2462
2463 if (flash_offset > (QLCNIC_FLASH_SECTOR_SIZE - 1)) {
2464 direct_window = QLC_83XX_FLASH_DIRECT_WINDOW;
2465 /* This write is needed once for each sector */
2466 qlcnic_83xx_wrt_reg_indirect(adapter,
2467 direct_window,
2468 (addr));
2469 flash_offset = 0;
2470 }
2471 }
2472 } else {
2473 /* Single sector read */
2474 for (i = 0; i < count; i++) {
2475 indirect_add = QLC_83XX_FLASH_DIRECT_DATA(addr);
4bd8e738
HM		 2476 ret = QLCRD32(adapter, indirect_add, &err);
2477 if (err == -EIO)
2478 return err;
d865ebb4
SC		 2479
2480 word = ret;
2481 *(u32 *)p_data = word;
2482 p_data = p_data + 4;
2483 addr = addr + 4;
2484 }
2485 }
2486
2487 return 0;
2488}
2489
2490static int qlcnic_83xx_poll_flash_status_reg(struct qlcnic_adapter *adapter)
2491{
2492 u32 status;
2493 int retries = QLC_83XX_FLASH_READ_RETRY_COUNT;
4bd8e738 2494 int err = 0;
d865ebb4
SC		 2495
2496 do {
4bd8e738
HM		 2497 status = QLCRD32(adapter, QLC_83XX_FLASH_STATUS, &err);
2498 if (err == -EIO)
2499 return err;
2500
d865ebb4
SC		 2501 if ((status & QLC_83XX_FLASH_STATUS_READY) ==
2502 QLC_83XX_FLASH_STATUS_READY)
2503 break;
2504
2505 msleep(QLC_83XX_FLASH_STATUS_REG_POLL_DELAY);
2506 } while (--retries);
2507
2508 if (!retries)
2509 return -EIO;
2510
2511 return 0;
2512}
2513
a520030e 2514int qlcnic_83xx_enable_flash_write(struct qlcnic_adapter *adapter)
d865ebb4
SC		 2515{
2516 int ret;
2517 u32 cmd;
2518 cmd = adapter->ahw->fdt.write_statusreg_cmd;
2519 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2520 (QLC_83XX_FLASH_FDT_WRITE_DEF_SIG | cmd));
2521 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2522 adapter->ahw->fdt.write_enable_bits);
2523 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2524 QLC_83XX_FLASH_SECOND_ERASE_MS_VAL);
2525 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2526 if (ret)
2527 return -EIO;
2528
2529 return 0;
2530}
2531
a520030e 2532int qlcnic_83xx_disable_flash_write(struct qlcnic_adapter *adapter)
d865ebb4
SC		 2533{
2534 int ret;
2535
2536 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2537 (QLC_83XX_FLASH_FDT_WRITE_DEF_SIG |
2538 adapter->ahw->fdt.write_statusreg_cmd));
2539 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2540 adapter->ahw->fdt.write_disable_bits);
2541 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2542 QLC_83XX_FLASH_SECOND_ERASE_MS_VAL);
2543 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2544 if (ret)
2545 return -EIO;
2546
2547 return 0;
2548}
2549
2550int qlcnic_83xx_read_flash_mfg_id(struct qlcnic_adapter *adapter)
2551{
4bd8e738
HM		 2552 int ret, err = 0;
2553 u32 mfg_id;
d865ebb4
SC		 2554
2555 if (qlcnic_83xx_lock_flash(adapter))
2556 return -EIO;
2557
2558 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2559 QLC_83XX_FLASH_FDT_READ_MFG_ID_VAL);
2560 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2561 QLC_83XX_FLASH_READ_CTRL);
2562 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2563 if (ret) {
2564 qlcnic_83xx_unlock_flash(adapter);
2565 return -EIO;
2566 }
2567
4bd8e738
HM		 2568 mfg_id = QLCRD32(adapter, QLC_83XX_FLASH_RDDATA, &err);
2569 if (err == -EIO) {
2570 qlcnic_83xx_unlock_flash(adapter);
2571 return err;
2572 }
d865ebb4
SC		 2573
2574 adapter->flash_mfg_id = (mfg_id & 0xFF);
2575 qlcnic_83xx_unlock_flash(adapter);
2576
2577 return 0;
2578}
2579
2580int qlcnic_83xx_read_flash_descriptor_table(struct qlcnic_adapter *adapter)
2581{
2582 int count, fdt_size, ret = 0;
2583
2584 fdt_size = sizeof(struct qlcnic_fdt);
2585 count = fdt_size / sizeof(u32);
2586
2587 if (qlcnic_83xx_lock_flash(adapter))
2588 return -EIO;
2589
2590 memset(&adapter->ahw->fdt, 0, fdt_size);
2591 ret = qlcnic_83xx_lockless_flash_read32(adapter, QLCNIC_FDT_LOCATION,
2592 (u8 *)&adapter->ahw->fdt,
2593 count);
2594
2595 qlcnic_83xx_unlock_flash(adapter);
2596 return ret;
2597}
2598
2599int qlcnic_83xx_erase_flash_sector(struct qlcnic_adapter *adapter,
2600 u32 sector_start_addr)
2601{
2602 u32 reversed_addr, addr1, addr2, cmd;
2603 int ret = -EIO;
2604
2605 if (qlcnic_83xx_lock_flash(adapter) != 0)
2606 return -EIO;
2607
2608 if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id) {
a520030e 2609 ret = qlcnic_83xx_enable_flash_write(adapter);
d865ebb4
SC		 2610 if (ret) {
2611 qlcnic_83xx_unlock_flash(adapter);
2612 dev_err(&adapter->pdev->dev,
2613 "%s failed at %d\n",
2614 __func__, __LINE__);
2615 return ret;
2616 }
2617 }
2618
2619 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2620 if (ret) {
2621 qlcnic_83xx_unlock_flash(adapter);
2622 dev_err(&adapter->pdev->dev,
2623 "%s: failed at %d\n", __func__, __LINE__);
2624 return -EIO;
2625 }
2626
2627 addr1 = (sector_start_addr & 0xFF) << 16;
2628 addr2 = (sector_start_addr & 0xFF0000) >> 16;
2629 reversed_addr = addr1 | addr2;
2630
2631 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2632 reversed_addr);
2633 cmd = QLC_83XX_FLASH_FDT_ERASE_DEF_SIG | adapter->ahw->fdt.erase_cmd;
2634 if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id)
2635 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, cmd);
2636 else
2637 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2638 QLC_83XX_FLASH_OEM_ERASE_SIG);
2639 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2640 QLC_83XX_FLASH_LAST_ERASE_MS_VAL);
2641
2642 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2643 if (ret) {
2644 qlcnic_83xx_unlock_flash(adapter);
2645 dev_err(&adapter->pdev->dev,
2646 "%s: failed at %d\n", __func__, __LINE__);
2647 return -EIO;
2648 }
2649
2650 if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id) {
a520030e 2651 ret = qlcnic_83xx_disable_flash_write(adapter);
d865ebb4
SC		 2652 if (ret) {
2653 qlcnic_83xx_unlock_flash(adapter);
2654 dev_err(&adapter->pdev->dev,
2655 "%s: failed at %d\n", __func__, __LINE__);
2656 return ret;
2657 }
2658 }
2659
2660 qlcnic_83xx_unlock_flash(adapter);
2661
2662 return 0;
2663}
2664
2665int qlcnic_83xx_flash_write32(struct qlcnic_adapter *adapter, u32 addr,
2666 u32 *p_data)
2667{
2668 int ret = -EIO;
2669 u32 addr1 = 0x00800000 | (addr >> 2);
2670
2671 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, addr1);
2672 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data);
2673 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2674 QLC_83XX_FLASH_LAST_ERASE_MS_VAL);
2675 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2676 if (ret) {
2677 dev_err(&adapter->pdev->dev,
2678 "%s: failed at %d\n", __func__, __LINE__);
2679 return -EIO;
2680 }
2681
2682 return 0;
2683}
2684
2685int qlcnic_83xx_flash_bulk_write(struct qlcnic_adapter *adapter, u32 addr,
2686 u32 *p_data, int count)
2687{
2688 u32 temp;
4bd8e738 2689 int ret = -EIO, err = 0;
d865ebb4 2690
a520030e
HM		 2691 if ((count < QLC_83XX_FLASH_WRITE_MIN) ||
2692 (count > QLC_83XX_FLASH_WRITE_MAX)) {
d865ebb4
SC		 2693 dev_err(&adapter->pdev->dev,
2694 "%s: Invalid word count\n", __func__);
2695 return -EIO;
2696 }
2697
4bd8e738
HM		 2698 temp = QLCRD32(adapter, QLC_83XX_FLASH_SPI_CONTROL, &err);
2699 if (err == -EIO)
2700 return err;
2701
d865ebb4
SC		 2702 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_SPI_CONTROL,
2703 (temp | QLC_83XX_FLASH_SPI_CTRL));
2704 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2705 QLC_83XX_FLASH_ADDR_TEMP_VAL);
2706
2707 /* First DWORD write */
2708 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data++);
2709 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2710 QLC_83XX_FLASH_FIRST_MS_PATTERN);
2711 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2712 if (ret) {
2713 dev_err(&adapter->pdev->dev,
2714 "%s: failed at %d\n", __func__, __LINE__);
2715 return -EIO;
2716 }
2717
2718 count--;
2719 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2720 QLC_83XX_FLASH_ADDR_SECOND_TEMP_VAL);
2721 /* Second to N-1 DWORD writes */
2722 while (count != 1) {
2723 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2724 *p_data++);
2725 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2726 QLC_83XX_FLASH_SECOND_MS_PATTERN);
2727 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2728 if (ret) {
2729 dev_err(&adapter->pdev->dev,
2730 "%s: failed at %d\n", __func__, __LINE__);
2731 return -EIO;
2732 }
2733 count--;
2734 }
2735
2736 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2737 QLC_83XX_FLASH_ADDR_TEMP_VAL |
2738 (addr >> 2));
2739 /* Last DWORD write */
2740 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data++);
2741 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2742 QLC_83XX_FLASH_LAST_MS_PATTERN);
2743 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2744 if (ret) {
2745 dev_err(&adapter->pdev->dev,
2746 "%s: failed at %d\n", __func__, __LINE__);
2747 return -EIO;
2748 }
2749
4bd8e738
HM		 2750 ret = QLCRD32(adapter, QLC_83XX_FLASH_SPI_STATUS, &err);
2751 if (err == -EIO)
2752 return err;
2753
d865ebb4
SC		 2754 if ((ret & QLC_83XX_FLASH_SPI_CTRL) == QLC_83XX_FLASH_SPI_CTRL) {
2755 dev_err(&adapter->pdev->dev, "%s: failed at %d\n",
2756 __func__, __LINE__);
2757 /* Operation failed, clear error bit */
4bd8e738
HM		 2758 temp = QLCRD32(adapter, QLC_83XX_FLASH_SPI_CONTROL, &err);
2759 if (err == -EIO)
2760 return err;
2761
d865ebb4
SC		 2762 qlcnic_83xx_wrt_reg_indirect(adapter,
2763 QLC_83XX_FLASH_SPI_CONTROL,
2764 (temp | QLC_83XX_FLASH_SPI_CTRL));
2765 }
2766
2767 return 0;
2768}
629263ac
SC		 2769
2770static void qlcnic_83xx_recover_driver_lock(struct qlcnic_adapter *adapter)
2771{
2772 u32 val, id;
2773
2774 val = QLCRDX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK);
2775
2776 /* Check if recovery need to be performed by the calling function */
2777 if ((val & QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK) == 0) {
2778 val = val & ~0x3F;
2779 val = val | ((adapter->portnum << 2) |
2780 QLC_83XX_NEED_DRV_LOCK_RECOVERY);
2781 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2782 dev_info(&adapter->pdev->dev,
2783 "%s: lock recovery initiated\n", __func__);
2784 msleep(QLC_83XX_DRV_LOCK_RECOVERY_DELAY);
2785 val = QLCRDX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK);
2786 id = ((val >> 2) & 0xF);
2787 if (id == adapter->portnum) {
2788 val = val & ~QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK;
2789 val = val | QLC_83XX_DRV_LOCK_RECOVERY_IN_PROGRESS;
2790 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2791 /* Force release the lock */
2792 QLCRDX(adapter->ahw, QLC_83XX_DRV_UNLOCK);
2793 /* Clear recovery bits */
2794 val = val & ~0x3F;
2795 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2796 dev_info(&adapter->pdev->dev,
2797 "%s: lock recovery completed\n", __func__);
2798 } else {
2799 dev_info(&adapter->pdev->dev,
2800 "%s: func %d to resume lock recovery process\n",
2801 __func__, id);
2802 }
2803 } else {
2804 dev_info(&adapter->pdev->dev,
2805 "%s: lock recovery initiated by other functions\n",
2806 __func__);
2807 }
2808}
2809
2810int qlcnic_83xx_lock_driver(struct qlcnic_adapter *adapter)
2811{
2812 u32 lock_alive_counter, val, id, i = 0, status = 0, temp = 0;
2813 int max_attempt = 0;
2814
2815 while (status == 0) {
2816 status = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK);
2817 if (status)
2818 break;
2819
2820 msleep(QLC_83XX_DRV_LOCK_WAIT_DELAY);
2821 i++;
2822
2823 if (i == 1)
2824 temp = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2825
2826 if (i == QLC_83XX_DRV_LOCK_WAIT_COUNTER) {
2827 val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2828 if (val == temp) {
2829 id = val & 0xFF;
2830 dev_info(&adapter->pdev->dev,
2831 "%s: lock to be recovered from %d\n",
2832 __func__, id);
2833 qlcnic_83xx_recover_driver_lock(adapter);
2834 i = 0;
2835 max_attempt++;
2836 } else {
2837 dev_err(&adapter->pdev->dev,
2838 "%s: failed to get lock\n", __func__);
2839 return -EIO;
2840 }
2841 }
2842
2843 /* Force exit from while loop after few attempts */
2844 if (max_attempt == QLC_83XX_MAX_DRV_LOCK_RECOVERY_ATTEMPT) {
2845 dev_err(&adapter->pdev->dev,
2846 "%s: failed to get lock\n", __func__);
2847 return -EIO;
2848 }
2849 }
2850
2851 val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2852 lock_alive_counter = val >> 8;
2853 lock_alive_counter++;
2854 val = lock_alive_counter << 8 | adapter->portnum;
2855 QLCWRX(adapter->ahw, QLC_83XX_DRV_LOCK_ID, val);
2856
2857 return 0;
2858}
2859
2860void qlcnic_83xx_unlock_driver(struct qlcnic_adapter *adapter)
2861{
2862 u32 val, lock_alive_counter, id;
2863
2864 val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2865 id = val & 0xFF;
2866 lock_alive_counter = val >> 8;
2867
2868 if (id != adapter->portnum)
2869 dev_err(&adapter->pdev->dev,
2870 "%s:Warning func %d is unlocking lock owned by %d\n",
2871 __func__, adapter->portnum, id);
2872
2873 val = (lock_alive_counter << 8) | 0xFF;
2874 QLCWRX(adapter->ahw, QLC_83XX_DRV_LOCK_ID, val);
2875 QLCRDX(adapter->ahw, QLC_83XX_DRV_UNLOCK);
2876}
2877
2878int qlcnic_83xx_ms_mem_write128(struct qlcnic_adapter *adapter, u64 addr,
2879 u32 *data, u32 count)
2880{
2881 int i, j, ret = 0;
2882 u32 temp;
4bd8e738 2883 int err = 0;
629263ac
SC		 2884
2885 /* Check alignment */
2886 if (addr & 0xF)
2887 return -EIO;
2888
2889 mutex_lock(&adapter->ahw->mem_lock);
2890 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_ADDR_HI, 0);
2891
2892 for (i = 0; i < count; i++, addr += 16) {
2893 if (!((ADDR_IN_RANGE(addr, QLCNIC_ADDR_QDR_NET,
2894 QLCNIC_ADDR_QDR_NET_MAX)) ||
2895 (ADDR_IN_RANGE(addr, QLCNIC_ADDR_DDR_NET,
2896 QLCNIC_ADDR_DDR_NET_MAX)))) {
2897 mutex_unlock(&adapter->ahw->mem_lock);
2898 return -EIO;
2899 }
2900
2901 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_ADDR_LO, addr);
2902 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_LO,
2903 *data++);
2904 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_HI,
2905 *data++);
2906 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_ULO,
2907 *data++);
2908 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_UHI,
2909 *data++);
2910 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_CTRL,
2911 QLCNIC_TA_WRITE_ENABLE);
2912 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_CTRL,
2913 QLCNIC_TA_WRITE_START);
2914
2915 for (j = 0; j < MAX_CTL_CHECK; j++) {
4bd8e738
HM		 2916 temp = QLCRD32(adapter, QLCNIC_MS_CTRL, &err);
2917 if (err == -EIO) {
2918 mutex_unlock(&adapter->ahw->mem_lock);
2919 return err;
2920 }
2921
629263ac
SC		 2922 if ((temp & TA_CTL_BUSY) == 0)
2923 break;
2924 }
2925
2926 /* Status check failure */
2927 if (j >= MAX_CTL_CHECK) {
2928 printk_ratelimited(KERN_WARNING
2929 "MS memory write failed\n");
2930 mutex_unlock(&adapter->ahw->mem_lock);
2931 return -EIO;
2932 }
2933 }
2934
2935 mutex_unlock(&adapter->ahw->mem_lock);
2936
2937 return ret;
2938}
81d0aeb0
SC		 2939
2940int qlcnic_83xx_flash_read32(struct qlcnic_adapter *adapter, u32 flash_addr,
2941 u8 *p_data, int count)
2942{
4bd8e738 2943 u32 word, addr = flash_addr, ret;
81d0aeb0 2944 ulong indirect_addr;
4bd8e738 2945 int i, err = 0;
81d0aeb0
SC		 2946
2947 if (qlcnic_83xx_lock_flash(adapter) != 0)
2948 return -EIO;
2949
2950 if (addr & 0x3) {
2951 dev_err(&adapter->pdev->dev, "Illegal addr = 0x%x\n", addr);
2952 qlcnic_83xx_unlock_flash(adapter);
2953 return -EIO;
2954 }
2955
2956 for (i = 0; i < count; i++) {
2957 if (qlcnic_83xx_wrt_reg_indirect(adapter,
2958 QLC_83XX_FLASH_DIRECT_WINDOW,
2959 (addr))) {
2960 qlcnic_83xx_unlock_flash(adapter);
2961 return -EIO;
2962 }
2963
2964 indirect_addr = QLC_83XX_FLASH_DIRECT_DATA(addr);
4bd8e738
HM		 2965 ret = QLCRD32(adapter, indirect_addr, &err);
2966 if (err == -EIO)
2967 return err;
2968
81d0aeb0 2969 word = ret;
1403f43a 2970 *(u32 *)p_data = word;
81d0aeb0
SC		 2971 p_data = p_data + 4;
2972 addr = addr + 4;
2973 }
2974
2975 qlcnic_83xx_unlock_flash(adapter);
2976
2977 return 0;
2978}
7e38d04b
SC		 2979
2980int qlcnic_83xx_test_link(struct qlcnic_adapter *adapter)
2981{
7cb03b23 2982 u8 pci_func;
7e38d04b
SC		 2983 int err;
2984 u32 config = 0, state;
2985 struct qlcnic_cmd_args cmd;
2986 struct qlcnic_hardware_context *ahw = adapter->ahw;
2987
7cb03b23
RB		 2988 if (qlcnic_sriov_vf_check(adapter))
2989 pci_func = adapter->portnum;
2990 else
2991 pci_func = ahw->pci_func;
2992
2993 state = readl(ahw->pci_base0 + QLC_83XX_LINK_STATE(pci_func));
2994 if (!QLC_83xx_FUNC_VAL(state, pci_func)) {
7e38d04b
SC		 2995 dev_info(&adapter->pdev->dev, "link state down\n");
2996 return config;
2997 }
b6b4316c
SS		 2998
2999 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LINK_STATUS);
3000 if (err)
3001 return err;
3002
7e38d04b
SC		 3003 err = qlcnic_issue_cmd(adapter, &cmd);
3004 if (err) {
3005 dev_info(&adapter->pdev->dev,
3006 "Get Link Status Command failed: 0x%x\n", err);
3007 goto out;
3008 } else {
3009 config = cmd.rsp.arg[1];
3010 switch (QLC_83XX_CURRENT_LINK_SPEED(config)) {
3011 case QLC_83XX_10M_LINK:
3012 ahw->link_speed = SPEED_10;
3013 break;
3014 case QLC_83XX_100M_LINK:
3015 ahw->link_speed = SPEED_100;
3016 break;
3017 case QLC_83XX_1G_LINK:
3018 ahw->link_speed = SPEED_1000;
3019 break;
3020 case QLC_83XX_10G_LINK:
3021 ahw->link_speed = SPEED_10000;
3022 break;
3023 default:
3024 ahw->link_speed = 0;
3025 break;
3026 }
3027 config = cmd.rsp.arg[3];
b938662d
HM		 3028 if (QLC_83XX_SFP_PRESENT(config)) {
3029 switch (ahw->module_type) {
3030 case LINKEVENT_MODULE_OPTICAL_UNKNOWN:
3031 case LINKEVENT_MODULE_OPTICAL_SRLR:
3032 case LINKEVENT_MODULE_OPTICAL_LRM:
3033 case LINKEVENT_MODULE_OPTICAL_SFP_1G:
3034 ahw->supported_type = PORT_FIBRE;
3035 break;
3036 case LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE:
3037 case LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN:
3038 case LINKEVENT_MODULE_TWINAX:
3039 ahw->supported_type = PORT_TP;
3040 break;
3041 default:
3042 ahw->supported_type = PORT_OTHER;
3043 }
3044 }
7e38d04b
SC		 3045 if (config & 1)
3046 err = 1;
3047 }
3048out:
3049 qlcnic_free_mbx_args(&cmd);
3050 return config;
3051}
3052
b938662d
HM		 3053int qlcnic_83xx_get_settings(struct qlcnic_adapter *adapter,
3054 struct ethtool_cmd *ecmd)
7e38d04b
SC		 3055{
3056 u32 config = 0;
3057 int status = 0;
3058 struct qlcnic_hardware_context *ahw = adapter->ahw;
3059
3060 /* Get port configuration info */
3061 status = qlcnic_83xx_get_port_info(adapter);
3062 /* Get Link Status related info */
3063 config = qlcnic_83xx_test_link(adapter);
3064 ahw->module_type = QLC_83XX_SFP_MODULE_TYPE(config);
3065 /* hard code until there is a way to get it from flash */
3066 ahw->board_type = QLCNIC_BRDTYPE_83XX_10G;
b938662d
HM		 3067
3068 if (netif_running(adapter->netdev) && ahw->has_link_events) {
3069 ethtool_cmd_speed_set(ecmd, ahw->link_speed);
3070 ecmd->duplex = ahw->link_duplex;
3071 ecmd->autoneg = ahw->link_autoneg;
3072 } else {
3073 ethtool_cmd_speed_set(ecmd, SPEED_UNKNOWN);
3074 ecmd->duplex = DUPLEX_UNKNOWN;
3075 ecmd->autoneg = AUTONEG_DISABLE;
3076 }
3077
3078 if (ahw->port_type == QLCNIC_XGBE) {
15d79747
HM		 3079 ecmd->supported = SUPPORTED_10000baseT_Full;
3080 ecmd->advertising = ADVERTISED_10000baseT_Full;
b938662d
HM		 3081 } else {
3082 ecmd->supported = (SUPPORTED_10baseT_Half |
3083 SUPPORTED_10baseT_Full |
3084 SUPPORTED_100baseT_Half |
3085 SUPPORTED_100baseT_Full |
3086 SUPPORTED_1000baseT_Half |
3087 SUPPORTED_1000baseT_Full);
3088 ecmd->advertising = (ADVERTISED_100baseT_Half |
3089 ADVERTISED_100baseT_Full |
3090 ADVERTISED_1000baseT_Half |
3091 ADVERTISED_1000baseT_Full);
3092 }
3093
3094 switch (ahw->supported_type) {
3095 case PORT_FIBRE:
3096 ecmd->supported |= SUPPORTED_FIBRE;
3097 ecmd->advertising |= ADVERTISED_FIBRE;
3098 ecmd->port = PORT_FIBRE;
3099 ecmd->transceiver = XCVR_EXTERNAL;
3100 break;
3101 case PORT_TP:
3102 ecmd->supported |= SUPPORTED_TP;
3103 ecmd->advertising |= ADVERTISED_TP;
3104 ecmd->port = PORT_TP;
3105 ecmd->transceiver = XCVR_INTERNAL;
3106 break;
3107 default:
3108 ecmd->supported |= SUPPORTED_FIBRE;
3109 ecmd->advertising |= ADVERTISED_FIBRE;
3110 ecmd->port = PORT_OTHER;
3111 ecmd->transceiver = XCVR_EXTERNAL;
3112 break;
3113 }
3114 ecmd->phy_address = ahw->physical_port;
7e38d04b
SC		 3115 return status;
3116}
3117
3118int qlcnic_83xx_set_settings(struct qlcnic_adapter *adapter,
3119 struct ethtool_cmd *ecmd)
3120{
3121 int status = 0;
3122 u32 config = adapter->ahw->port_config;
3123
3124 if (ecmd->autoneg)
3125 adapter->ahw->port_config |= BIT_15;
3126
3127 switch (ethtool_cmd_speed(ecmd)) {
3128 case SPEED_10:
3129 adapter->ahw->port_config |= BIT_8;
3130 break;
3131 case SPEED_100:
3132 adapter->ahw->port_config |= BIT_9;
3133 break;
3134 case SPEED_1000:
3135 adapter->ahw->port_config |= BIT_10;
3136 break;
3137 case SPEED_10000:
3138 adapter->ahw->port_config |= BIT_11;
3139 break;
3140 default:
3141 return -EINVAL;
3142 }
3143
3144 status = qlcnic_83xx_set_port_config(adapter);
3145 if (status) {
3146 dev_info(&adapter->pdev->dev,
3147 "Faild to Set Link Speed and autoneg.\n");
3148 adapter->ahw->port_config = config;
3149 }
3150 return status;
3151}
3152
3153static inline u64 *qlcnic_83xx_copy_stats(struct qlcnic_cmd_args *cmd,
3154 u64 *data, int index)
3155{
3156 u32 low, hi;
3157 u64 val;
3158
3159 low = cmd->rsp.arg[index];
3160 hi = cmd->rsp.arg[index + 1];
3161 val = (((u64) low) | (((u64) hi) << 32));
3162 *data++ = val;
3163 return data;
3164}
3165
3166static u64 *qlcnic_83xx_fill_stats(struct qlcnic_adapter *adapter,
3167 struct qlcnic_cmd_args *cmd, u64 *data,
3168 int type, int *ret)
3169{
3170 int err, k, total_regs;
3171
3172 *ret = 0;
3173 err = qlcnic_issue_cmd(adapter, cmd);
3174 if (err != QLCNIC_RCODE_SUCCESS) {
3175 dev_info(&adapter->pdev->dev,
3176 "Error in get statistics mailbox command\n");
3177 *ret = -EIO;
3178 return data;
3179 }
3180 total_regs = cmd->rsp.num;
3181 switch (type) {
3182 case QLC_83XX_STAT_MAC:
3183 /* fill in MAC tx counters */
3184 for (k = 2; k < 28; k += 2)
3185 data = qlcnic_83xx_copy_stats(cmd, data, k);
3186 /* skip 24 bytes of reserved area */
3187 /* fill in MAC rx counters */
3188 for (k += 6; k < 60; k += 2)
3189 data = qlcnic_83xx_copy_stats(cmd, data, k);
3190 /* skip 24 bytes of reserved area */
3191 /* fill in MAC rx frame stats */
3192 for (k += 6; k < 80; k += 2)
3193 data = qlcnic_83xx_copy_stats(cmd, data, k);
52290740
SS		 3194 /* fill in eSwitch stats */
3195 for (; k < total_regs; k += 2)
3196 data = qlcnic_83xx_copy_stats(cmd, data, k);
7e38d04b
SC		 3197 break;
3198 case QLC_83XX_STAT_RX:
3199 for (k = 2; k < 8; k += 2)
3200 data = qlcnic_83xx_copy_stats(cmd, data, k);
3201 /* skip 8 bytes of reserved data */
3202 for (k += 2; k < 24; k += 2)
3203 data = qlcnic_83xx_copy_stats(cmd, data, k);
3204 /* skip 8 bytes containing RE1FBQ error data */
3205 for (k += 2; k < total_regs; k += 2)
3206 data = qlcnic_83xx_copy_stats(cmd, data, k);
3207 break;
3208 case QLC_83XX_STAT_TX:
3209 for (k = 2; k < 10; k += 2)
3210 data = qlcnic_83xx_copy_stats(cmd, data, k);
3211 /* skip 8 bytes of reserved data */
3212 for (k += 2; k < total_regs; k += 2)
3213 data = qlcnic_83xx_copy_stats(cmd, data, k);
3214 break;
3215 default:
3216 dev_warn(&adapter->pdev->dev, "Unknown get statistics mode\n");
3217 *ret = -EIO;
3218 }
3219 return data;
3220}
3221
3222void qlcnic_83xx_get_stats(struct qlcnic_adapter *adapter, u64 *data)
3223{
3224 struct qlcnic_cmd_args cmd;
7bc27a8c 3225 struct net_device *netdev = adapter->netdev;
7e38d04b
SC		 3226 int ret = 0;
3227
b6b4316c
SS		 3228 ret = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_STATISTICS);
3229 if (ret)
3230 return;
7e38d04b
SC		 3231 /* Get Tx stats */
3232 cmd.req.arg[1] = BIT_1 | (adapter->tx_ring->ctx_id << 16);
3233 cmd.rsp.num = QLC_83XX_TX_STAT_REGS;
3234 data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
3235 QLC_83XX_STAT_TX, &ret);
3236 if (ret) {
7bc27a8c 3237 netdev_err(netdev, "Error getting Tx stats\n");
7e38d04b
SC		 3238 goto out;
3239 }
3240 /* Get MAC stats */
3241 cmd.req.arg[1] = BIT_2 | (adapter->portnum << 16);
3242 cmd.rsp.num = QLC_83XX_MAC_STAT_REGS;
3243 memset(cmd.rsp.arg, 0, sizeof(u32) * cmd.rsp.num);
3244 data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
3245 QLC_83XX_STAT_MAC, &ret);
3246 if (ret) {
7bc27a8c 3247 netdev_err(netdev, "Error getting MAC stats\n");
7e38d04b
SC		 3248 goto out;
3249 }
3250 /* Get Rx stats */
3251 cmd.req.arg[1] = adapter->recv_ctx->context_id << 16;
3252 cmd.rsp.num = QLC_83XX_RX_STAT_REGS;
3253 memset(cmd.rsp.arg, 0, sizeof(u32) * cmd.rsp.num);
3254 data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
3255 QLC_83XX_STAT_RX, &ret);
3256 if (ret)
7bc27a8c 3257 netdev_err(netdev, "Error getting Rx stats\n");
7e38d04b
SC		 3258out:
3259 qlcnic_free_mbx_args(&cmd);
3260}
3261
3262int qlcnic_83xx_reg_test(struct qlcnic_adapter *adapter)
3263{
3264 u32 major, minor, sub;
3265
3266 major = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MAJOR);
3267 minor = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MINOR);
3268 sub = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_SUB);
3269
3270 if (adapter->fw_version != QLCNIC_VERSION_CODE(major, minor, sub)) {
3271 dev_info(&adapter->pdev->dev, "%s: Reg test failed\n",
3272 __func__);
3273 return 1;
3274 }
3275 return 0;
3276}
3277
3278int qlcnic_83xx_get_regs_len(struct qlcnic_adapter *adapter)
3279{
3280 return (ARRAY_SIZE(qlcnic_83xx_ext_reg_tbl) *
3281 sizeof(adapter->ahw->ext_reg_tbl)) +
3282 (ARRAY_SIZE(qlcnic_83xx_reg_tbl) +
3283 sizeof(adapter->ahw->reg_tbl));
3284}
3285
3286int qlcnic_83xx_get_registers(struct qlcnic_adapter *adapter, u32 *regs_buff)
3287{
3288 int i, j = 0;
3289
3290 for (i = QLCNIC_DEV_INFO_SIZE + 1;
3291 j < ARRAY_SIZE(qlcnic_83xx_reg_tbl); i++, j++)
3292 regs_buff[i] = QLC_SHARED_REG_RD32(adapter, j);
3293
3294 for (j = 0; j < ARRAY_SIZE(qlcnic_83xx_ext_reg_tbl); j++)
3295 regs_buff[i++] = QLCRDX(adapter->ahw, j);
3296 return i;
3297}
3298
58ead415 3299int qlcnic_83xx_interrupt_test(struct net_device *netdev)
7e38d04b 3300{
58ead415
JK		 3301 struct qlcnic_adapter *adapter = netdev_priv(netdev);
3302 struct qlcnic_hardware_context *ahw = adapter->ahw;
3303 struct qlcnic_cmd_args cmd;
7e38d04b
SC		 3304 u32 data;
3305 u16 intrpt_id, id;
58ead415
JK		 3306 u8 val;
3307 int ret, max_sds_rings = adapter->max_sds_rings;
3308
d1fcc172
MC		 3309 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
3310 netdev_info(netdev, "Device is resetting\n");
3311 return -EBUSY;
3312 }
3313
4690a7e4
SC		 3314 if (qlcnic_get_diag_lock(adapter)) {
3315 netdev_info(netdev, "Device in diagnostics mode\n");
3316 return -EBUSY;
3317 }
58ead415 3318
13a82b44
MC		 3319 ret = qlcnic_83xx_diag_alloc_res(netdev, QLCNIC_INTERRUPT_TEST,
3320 max_sds_rings);
58ead415
JK		 3321 if (ret)
3322 goto fail_diag_irq;
3323
3324 ahw->diag_cnt = 0;
b6b4316c
SS		 3325 ret = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_INTRPT_TEST);
3326 if (ret)
3327 goto fail_diag_irq;
7e38d04b
SC		 3328
3329 if (adapter->flags & QLCNIC_MSIX_ENABLED)
58ead415 3330 intrpt_id = ahw->intr_tbl[0].id;
7e38d04b 3331 else
58ead415 3332 intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
7e38d04b 3333
58ead415
JK		 3334 cmd.req.arg[1] = 1;
3335 cmd.req.arg[2] = intrpt_id;
3336 cmd.req.arg[3] = BIT_0;
7e38d04b 3337
58ead415
JK		 3338 ret = qlcnic_issue_cmd(adapter, &cmd);
3339 data = cmd.rsp.arg[2];
7e38d04b
SC		 3340 id = LSW(data);
3341 val = LSB(MSW(data));
3342 if (id != intrpt_id)
3343 dev_info(&adapter->pdev->dev,
3344 "Interrupt generated: 0x%x, requested:0x%x\n",
3345 id, intrpt_id);
3346 if (val)
58ead415 3347 dev_err(&adapter->pdev->dev,
7e38d04b 3348 "Interrupt test error: 0x%x\n", val);
58ead415
JK		 3349 if (ret)
3350 goto done;
3351
3352 msleep(20);
3353 ret = !ahw->diag_cnt;
7e38d04b 3354
58ead415
JK		 3355done:
3356 qlcnic_free_mbx_args(&cmd);
3357 qlcnic_83xx_diag_free_res(netdev, max_sds_rings);
3358
3359fail_diag_irq:
3360 adapter->max_sds_rings = max_sds_rings;
4690a7e4 3361 qlcnic_release_diag_lock(adapter);
7e38d04b
SC		 3362 return ret;
3363}
3364
3365void qlcnic_83xx_get_pauseparam(struct qlcnic_adapter *adapter,
3366 struct ethtool_pauseparam *pause)
3367{
3368 struct qlcnic_hardware_context *ahw = adapter->ahw;
3369 int status = 0;
3370 u32 config;
3371
3372 status = qlcnic_83xx_get_port_config(adapter);
3373 if (status) {
3374 dev_err(&adapter->pdev->dev,
3375 "%s: Get Pause Config failed\n", __func__);
3376 return;
3377 }
3378 config = ahw->port_config;
3379 if (config & QLC_83XX_CFG_STD_PAUSE) {
3380 if (config & QLC_83XX_CFG_STD_TX_PAUSE)
3381 pause->tx_pause = 1;
3382 if (config & QLC_83XX_CFG_STD_RX_PAUSE)
3383 pause->rx_pause = 1;
3384 }
3385
3386 if (QLC_83XX_AUTONEG(config))
3387 pause->autoneg = 1;
3388}
3389
3390int qlcnic_83xx_set_pauseparam(struct qlcnic_adapter *adapter,
3391 struct ethtool_pauseparam *pause)
3392{
3393 struct qlcnic_hardware_context *ahw = adapter->ahw;
3394 int status = 0;
3395 u32 config;
3396
3397 status = qlcnic_83xx_get_port_config(adapter);
3398 if (status) {
3399 dev_err(&adapter->pdev->dev,
3400 "%s: Get Pause Config failed.\n", __func__);
3401 return status;
3402 }
3403 config = ahw->port_config;
3404
3405 if (ahw->port_type == QLCNIC_GBE) {
3406 if (pause->autoneg)
3407 ahw->port_config |= QLC_83XX_ENABLE_AUTONEG;
3408 if (!pause->autoneg)
3409 ahw->port_config &= ~QLC_83XX_ENABLE_AUTONEG;
3410 } else if ((ahw->port_type == QLCNIC_XGBE) && (pause->autoneg)) {
3411 return -EOPNOTSUPP;
3412 }
3413
3414 if (!(config & QLC_83XX_CFG_STD_PAUSE))
3415 ahw->port_config |= QLC_83XX_CFG_STD_PAUSE;
3416
3417 if (pause->rx_pause && pause->tx_pause) {
3418 ahw->port_config |= QLC_83XX_CFG_STD_TX_RX_PAUSE;
3419 } else if (pause->rx_pause && !pause->tx_pause) {
3420 ahw->port_config &= ~QLC_83XX_CFG_STD_TX_PAUSE;
3421 ahw->port_config |= QLC_83XX_CFG_STD_RX_PAUSE;
3422 } else if (pause->tx_pause && !pause->rx_pause) {
3423 ahw->port_config &= ~QLC_83XX_CFG_STD_RX_PAUSE;
3424 ahw->port_config |= QLC_83XX_CFG_STD_TX_PAUSE;
3425 } else if (!pause->rx_pause && !pause->tx_pause) {
3426 ahw->port_config &= ~QLC_83XX_CFG_STD_TX_RX_PAUSE;
3427 }
3428 status = qlcnic_83xx_set_port_config(adapter);
3429 if (status) {
3430 dev_err(&adapter->pdev->dev,
3431 "%s: Set Pause Config failed.\n", __func__);
3432 ahw->port_config = config;
3433 }
3434 return status;
3435}
3436
3437static int qlcnic_83xx_read_flash_status_reg(struct qlcnic_adapter *adapter)
3438{
4bd8e738
HM		 3439 int ret, err = 0;
3440 u32 temp;
7e38d04b
SC		 3441
3442 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
3443 QLC_83XX_FLASH_OEM_READ_SIG);
3444 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
3445 QLC_83XX_FLASH_READ_CTRL);
3446 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
3447 if (ret)
3448 return -EIO;
3449
4bd8e738
HM		 3450 temp = QLCRD32(adapter, QLC_83XX_FLASH_RDDATA, &err);
3451 if (err == -EIO)
3452 return err;
3453
3454 return temp & 0xFF;
7e38d04b
SC		 3455}
3456
3457int qlcnic_83xx_flash_test(struct qlcnic_adapter *adapter)
3458{
3459 int status;
3460
3461 status = qlcnic_83xx_read_flash_status_reg(adapter);
3462 if (status == -EIO) {
3463 dev_info(&adapter->pdev->dev, "%s: EEPROM test failed.\n",
3464 __func__);
3465 return 1;
3466 }
3467 return 0;
3468}
486a5bc7
RB		 3469
3470int qlcnic_83xx_shutdown(struct pci_dev *pdev)
3471{
3472 struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
3473 struct net_device *netdev = adapter->netdev;
3474 int retval;
3475
3476 netif_device_detach(netdev);
3477 qlcnic_cancel_idc_work(adapter);
3478
3479 if (netif_running(netdev))
3480 qlcnic_down(adapter, netdev);
3481
3482 qlcnic_83xx_disable_mbx_intr(adapter);
3483 cancel_delayed_work_sync(&adapter->idc_aen_work);
3484
3485 retval = pci_save_state(pdev);
3486 if (retval)
3487 return retval;
3488
3489 return 0;
3490}
3491
3492int qlcnic_83xx_resume(struct qlcnic_adapter *adapter)
3493{
3494 struct qlcnic_hardware_context *ahw = adapter->ahw;
3495 struct qlc_83xx_idc *idc = &ahw->idc;
3496 int err = 0;
3497
3498 err = qlcnic_83xx_idc_init(adapter);
3499 if (err)
3500 return err;
3501
3502 if (ahw->nic_mode == QLC_83XX_VIRTUAL_NIC_MODE) {
3503 if (ahw->op_mode == QLCNIC_MGMT_FUNC) {
3504 qlcnic_83xx_set_vnic_opmode(adapter);
3505 } else {
3506 err = qlcnic_83xx_check_vnic_state(adapter);
3507 if (err)
3508 return err;
3509 }
3510 }
3511
3512 err = qlcnic_83xx_idc_reattach_driver(adapter);
3513 if (err)
3514 return err;
3515
3516 qlcnic_schedule_work(adapter, qlcnic_83xx_idc_poll_dev_state,
3517 idc->delay);
3518 return err;
3519}
e5c4e6c6
MC		 3520
3521void qlcnic_83xx_reinit_mbx_work(struct qlcnic_mailbox *mbx)
3522{
3523 INIT_COMPLETION(mbx->completion);
3524 set_bit(QLC_83XX_MBX_READY, &mbx->status);
3525}
3526
3527void qlcnic_83xx_free_mailbox(struct qlcnic_mailbox *mbx)
3528{
3529 destroy_workqueue(mbx->work_q);
3530 kfree(mbx);
3531}
3532
3533static inline void
3534qlcnic_83xx_notify_cmd_completion(struct qlcnic_adapter *adapter,
3535 struct qlcnic_cmd_args *cmd)
3536{
3537 atomic_set(&cmd->rsp_status, QLC_83XX_MBX_RESPONSE_ARRIVED);
3538
3539 if (cmd->type == QLC_83XX_MBX_CMD_NO_WAIT) {
3540 qlcnic_free_mbx_args(cmd);
3541 kfree(cmd);
3542 return;
3543 }
3544 complete(&cmd->completion);
3545}
3546
3547static inline void qlcnic_83xx_flush_mbx_queue(struct qlcnic_adapter *adapter)
3548{
3549 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3550 struct list_head *head = &mbx->cmd_q;
3551 struct qlcnic_cmd_args *cmd = NULL;
3552
3553 spin_lock(&mbx->queue_lock);
3554
3555 while (!list_empty(head)) {
3556 cmd = list_entry(head->next, struct qlcnic_cmd_args, list);
35570cfe
MC		 3557 dev_info(&adapter->pdev->dev, "%s: Mailbox command 0x%x\n",
3558 __func__, cmd->cmd_op);
e5c4e6c6
MC		 3559 list_del(&cmd->list);
3560 mbx->num_cmds--;
3561 qlcnic_83xx_notify_cmd_completion(adapter, cmd);
3562 }
3563
3564 spin_unlock(&mbx->queue_lock);
3565}
3566
3567static inline int qlcnic_83xx_check_mbx_status(struct qlcnic_adapter *adapter)
3568{
3569 struct qlcnic_hardware_context *ahw = adapter->ahw;
3570 struct qlcnic_mailbox *mbx = ahw->mailbox;
3571 u32 host_mbx_ctrl;
3572
3573 if (!test_bit(QLC_83XX_MBX_READY, &mbx->status))
3574 return -EBUSY;
3575
3576 host_mbx_ctrl = QLCRDX(ahw, QLCNIC_HOST_MBX_CTRL);
3577 if (host_mbx_ctrl) {
35570cfe 3578 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
e5c4e6c6
MC		 3579 ahw->idc.collect_dump = 1;
3580 return -EIO;
3581 }
3582
3583 return 0;
3584}
3585
3586static inline void qlcnic_83xx_signal_mbx_cmd(struct qlcnic_adapter *adapter,
3587 u8 issue_cmd)
3588{
3589 if (issue_cmd)
3590 QLCWRX(adapter->ahw, QLCNIC_HOST_MBX_CTRL, QLCNIC_SET_OWNER);
3591 else
3592 QLCWRX(adapter->ahw, QLCNIC_FW_MBX_CTRL, QLCNIC_CLR_OWNER);
3593}
3594
3595static inline void qlcnic_83xx_dequeue_mbx_cmd(struct qlcnic_adapter *adapter,
3596 struct qlcnic_cmd_args *cmd)
3597{
3598 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3599
3600 spin_lock(&mbx->queue_lock);
3601
3602 list_del(&cmd->list);
3603 mbx->num_cmds--;
3604
3605 spin_unlock(&mbx->queue_lock);
3606
3607 qlcnic_83xx_notify_cmd_completion(adapter, cmd);
3608}
3609
3610static void qlcnic_83xx_encode_mbx_cmd(struct qlcnic_adapter *adapter,
3611 struct qlcnic_cmd_args *cmd)
3612{
3613 u32 mbx_cmd, fw_hal_version, hdr_size, total_size, tmp;
3614 struct qlcnic_hardware_context *ahw = adapter->ahw;
3615 int i, j;
3616
3617 if (cmd->op_type != QLC_83XX_MBX_POST_BC_OP) {
3618 mbx_cmd = cmd->req.arg[0];
3619 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 0));
3620 for (i = 1; i < cmd->req.num; i++)
3621 writel(cmd->req.arg[i], QLCNIC_MBX_HOST(ahw, i));
3622 } else {
3623 fw_hal_version = ahw->fw_hal_version;
3624 hdr_size = sizeof(struct qlcnic_bc_hdr) / sizeof(u32);
3625 total_size = cmd->pay_size + hdr_size;
3626 tmp = QLCNIC_CMD_BC_EVENT_SETUP | total_size << 16;
3627 mbx_cmd = tmp | fw_hal_version << 29;
3628 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 0));
3629
3630 /* Back channel specific operations bits */
3631 mbx_cmd = 0x1 | 1 << 4;
3632
3633 if (qlcnic_sriov_pf_check(adapter))
3634 mbx_cmd |= cmd->func_num << 5;
3635
3636 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 1));
3637
3638 for (i = 2, j = 0; j < hdr_size; i++, j++)
3639 writel(*(cmd->hdr++), QLCNIC_MBX_HOST(ahw, i));
3640 for (j = 0; j < cmd->pay_size; j++, i++)
3641 writel(*(cmd->pay++), QLCNIC_MBX_HOST(ahw, i));
3642 }
3643}
3644
3645void qlcnic_83xx_detach_mailbox_work(struct qlcnic_adapter *adapter)
3646{
3647 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3648
3649 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
3650 complete(&mbx->completion);
3651 cancel_work_sync(&mbx->work);
3652 flush_workqueue(mbx->work_q);
3653 qlcnic_83xx_flush_mbx_queue(adapter);
3654}
3655
3656static inline int qlcnic_83xx_enqueue_mbx_cmd(struct qlcnic_adapter *adapter,
3657 struct qlcnic_cmd_args *cmd,
3658 unsigned long *timeout)
3659{
3660 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3661
3662 if (test_bit(QLC_83XX_MBX_READY, &mbx->status)) {
3663 atomic_set(&cmd->rsp_status, QLC_83XX_MBX_RESPONSE_WAIT);
3664 init_completion(&cmd->completion);
3665 cmd->rsp_opcode = QLC_83XX_MBX_RESPONSE_UNKNOWN;
3666
3667 spin_lock(&mbx->queue_lock);
3668
3669 list_add_tail(&cmd->list, &mbx->cmd_q);
3670 mbx->num_cmds++;
3671 cmd->total_cmds = mbx->num_cmds;
3672 *timeout = cmd->total_cmds * QLC_83XX_MBX_TIMEOUT;
3673 queue_work(mbx->work_q, &mbx->work);
3674
3675 spin_unlock(&mbx->queue_lock);
3676
3677 return 0;
3678 }
3679
3680 return -EBUSY;
3681}
3682
3683static inline int qlcnic_83xx_check_mac_rcode(struct qlcnic_adapter *adapter,
3684 struct qlcnic_cmd_args *cmd)
3685{
3686 u8 mac_cmd_rcode;
3687 u32 fw_data;
3688
3689 if (cmd->cmd_op == QLCNIC_CMD_CONFIG_MAC_VLAN) {
3690 fw_data = readl(QLCNIC_MBX_FW(adapter->ahw, 2));
3691 mac_cmd_rcode = (u8)fw_data;
3692 if (mac_cmd_rcode == QLC_83XX_NO_NIC_RESOURCE ||
3693 mac_cmd_rcode == QLC_83XX_MAC_PRESENT ||
3694 mac_cmd_rcode == QLC_83XX_MAC_ABSENT) {
3695 cmd->rsp_opcode = QLCNIC_RCODE_SUCCESS;
3696 return QLCNIC_RCODE_SUCCESS;
3697 }
3698 }
3699
3700 return -EINVAL;
3701}
3702
3703static void qlcnic_83xx_decode_mbx_rsp(struct qlcnic_adapter *adapter,
3704 struct qlcnic_cmd_args *cmd)
3705{
3706 struct qlcnic_hardware_context *ahw = adapter->ahw;
3707 struct device *dev = &adapter->pdev->dev;
3708 u8 mbx_err_code;
3709 u32 fw_data;
3710
3711 fw_data = readl(QLCNIC_MBX_FW(ahw, 0));
3712 mbx_err_code = QLCNIC_MBX_STATUS(fw_data);
3713 qlcnic_83xx_get_mbx_data(adapter, cmd);
3714
3715 switch (mbx_err_code) {
3716 case QLCNIC_MBX_RSP_OK:
3717 case QLCNIC_MBX_PORT_RSP_OK:
3718 cmd->rsp_opcode = QLCNIC_RCODE_SUCCESS;
3719 break;
3720 default:
3721 if (!qlcnic_83xx_check_mac_rcode(adapter, cmd))
3722 break;
3723
3724 dev_err(dev, "%s: Mailbox command failed, opcode=0x%x, cmd_type=0x%x, func=0x%x, op_mode=0x%x, error=0x%x\n",
3725 __func__, cmd->cmd_op, cmd->type, ahw->pci_func,
3726 ahw->op_mode, mbx_err_code);
3727 cmd->rsp_opcode = QLC_83XX_MBX_RESPONSE_FAILED;
3728 qlcnic_dump_mbx(adapter, cmd);
3729 }
3730
3731 return;
3732}
3733
3734static void qlcnic_83xx_mailbox_worker(struct work_struct *work)
3735{
3736 struct qlcnic_mailbox *mbx = container_of(work, struct qlcnic_mailbox,
3737 work);
3738 struct qlcnic_adapter *adapter = mbx->adapter;
3739 struct qlcnic_mbx_ops *mbx_ops = mbx->ops;
3740 struct device *dev = &adapter->pdev->dev;
3741 atomic_t *rsp_status = &mbx->rsp_status;
3742 struct list_head *head = &mbx->cmd_q;
3743 struct qlcnic_hardware_context *ahw;
3744 struct qlcnic_cmd_args *cmd = NULL;
3745
3746 ahw = adapter->ahw;
3747
3748 while (true) {
35570cfe
MC		 3749 if (qlcnic_83xx_check_mbx_status(adapter)) {
3750 qlcnic_83xx_flush_mbx_queue(adapter);
e5c4e6c6 3751 return;
35570cfe 3752 }
e5c4e6c6
MC		 3753
3754 atomic_set(rsp_status, QLC_83XX_MBX_RESPONSE_WAIT);
3755
3756 spin_lock(&mbx->queue_lock);
3757
3758 if (list_empty(head)) {
3759 spin_unlock(&mbx->queue_lock);
3760 return;
3761 }
3762 cmd = list_entry(head->next, struct qlcnic_cmd_args, list);
3763
3764 spin_unlock(&mbx->queue_lock);
3765
3766 mbx_ops->encode_cmd(adapter, cmd);
3767 mbx_ops->nofity_fw(adapter, QLC_83XX_MBX_REQUEST);
3768
3769 if (wait_for_completion_timeout(&mbx->completion,
3770 QLC_83XX_MBX_TIMEOUT)) {
3771 mbx_ops->decode_resp(adapter, cmd);
3772 mbx_ops->nofity_fw(adapter, QLC_83XX_MBX_COMPLETION);
3773 } else {
3774 dev_err(dev, "%s: Mailbox command timeout, opcode=0x%x, cmd_type=0x%x, func=0x%x, op_mode=0x%x\n",
3775 __func__, cmd->cmd_op, cmd->type, ahw->pci_func,
3776 ahw->op_mode);
3777 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
b942f44a 3778 qlcnic_dump_mbx(adapter, cmd);
e5c4e6c6
MC		 3779 qlcnic_83xx_idc_request_reset(adapter,
3780 QLCNIC_FORCE_FW_DUMP_KEY);
3781 cmd->rsp_opcode = QLCNIC_RCODE_TIMEOUT;
3782 }
3783 mbx_ops->dequeue_cmd(adapter, cmd);
3784 }
3785}
3786
3787static struct qlcnic_mbx_ops qlcnic_83xx_mbx_ops = {
3788 .enqueue_cmd = qlcnic_83xx_enqueue_mbx_cmd,
3789 .dequeue_cmd = qlcnic_83xx_dequeue_mbx_cmd,
3790 .decode_resp = qlcnic_83xx_decode_mbx_rsp,
3791 .encode_cmd = qlcnic_83xx_encode_mbx_cmd,
3792 .nofity_fw = qlcnic_83xx_signal_mbx_cmd,
3793};
3794
3795int qlcnic_83xx_init_mailbox_work(struct qlcnic_adapter *adapter)
3796{
3797 struct qlcnic_hardware_context *ahw = adapter->ahw;
3798 struct qlcnic_mailbox *mbx;
3799
3800 ahw->mailbox = kzalloc(sizeof(*mbx), GFP_KERNEL);
3801 if (!ahw->mailbox)
3802 return -ENOMEM;
3803
3804 mbx = ahw->mailbox;
3805 mbx->ops = &qlcnic_83xx_mbx_ops;
3806 mbx->adapter = adapter;
3807
3808 spin_lock_init(&mbx->queue_lock);
3809 spin_lock_init(&mbx->aen_lock);
3810 INIT_LIST_HEAD(&mbx->cmd_q);
3811 init_completion(&mbx->completion);
3812
3813 mbx->work_q = create_singlethread_workqueue("qlcnic_mailbox");
3814 if (mbx->work_q == NULL) {
3815 kfree(mbx);
3816 return -ENOMEM;
3817 }
3818
3819 INIT_WORK(&mbx->work, qlcnic_83xx_mailbox_worker);
3820 set_bit(QLC_83XX_MBX_READY, &mbx->status);
3821 return 0;
3822}
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