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qlcnic: Fix link speed and duplex display for 83xx adapter
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / qlogic / qlcnic / qlcnic_83xx_hw.h
CommitLineData
577ae39d
JK		 1/*
2 * QLogic qlcnic NIC Driver
3 * Copyright (c) 2009-2013 QLogic Corporation
4 *
5 * See LICENSE.qlcnic for copyright and licensing details.
6 */
7
7f966452
SC		 8#ifndef __QLCNIC_83XX_HW_H
9#define __QLCNIC_83XX_HW_H
10
11#include <linux/types.h>
12#include <linux/etherdevice.h>
13#include "qlcnic_hw.h"
14
a520030e
HM		 15#define QLCNIC_83XX_BAR0_LENGTH 0x4000
16
7f966452
SC		 17/* Directly mapped registers */
18#define QLC_83XX_CRB_WIN_BASE 0x3800
19#define QLC_83XX_CRB_WIN_FUNC(f) (QLC_83XX_CRB_WIN_BASE+((f)*4))
20#define QLC_83XX_SEM_LOCK_BASE 0x3840
21#define QLC_83XX_SEM_UNLOCK_BASE 0x3844
22#define QLC_83XX_SEM_LOCK_FUNC(f) (QLC_83XX_SEM_LOCK_BASE+((f)*8))
23#define QLC_83XX_SEM_UNLOCK_FUNC(f) (QLC_83XX_SEM_UNLOCK_BASE+((f)*8))
24#define QLC_83XX_LINK_STATE(f) (0x3698+((f) > 7 ? 4 : 0))
25#define QLC_83XX_LINK_SPEED(f) (0x36E0+(((f) >> 2) * 4))
26#define QLC_83XX_LINK_SPEED_FACTOR 10
27#define QLC_83xx_FUNC_VAL(v, f) ((v) & (1 << (f * 4)))
28#define QLC_83XX_INTX_PTR 0x38C0
29#define QLC_83XX_INTX_TRGR 0x38C4
30#define QLC_83XX_INTX_MASK 0x38C8
31
32#define QLC_83XX_DRV_LOCK_WAIT_COUNTER 100
33#define QLC_83XX_DRV_LOCK_WAIT_DELAY 20
34#define QLC_83XX_NEED_DRV_LOCK_RECOVERY 1
35#define QLC_83XX_DRV_LOCK_RECOVERY_IN_PROGRESS 2
36#define QLC_83XX_MAX_DRV_LOCK_RECOVERY_ATTEMPT 3
37#define QLC_83XX_DRV_LOCK_RECOVERY_DELAY 200
38#define QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK 0x3
2c4a7878
JK		 39#define QLC_83XX_LB_WAIT_COUNT 250
40#define QLC_83XX_LB_MSLEEP_COUNT 20
7f966452
SC		 41#define QLC_83XX_NO_NIC_RESOURCE 0x5
42#define QLC_83XX_MAC_PRESENT 0xC
43#define QLC_83XX_MAC_ABSENT 0xD
44
45
46#define QLC_83XX_FLASH_SECTOR_SIZE (64 * 1024)
47
48/* PEG status definitions */
49#define QLC_83XX_CMDPEG_COMPLETE 0xff01
50#define QLC_83XX_VALID_INTX_BIT30(val) ((val) & BIT_30)
51#define QLC_83XX_VALID_INTX_BIT31(val) ((val) & BIT_31)
52#define QLC_83XX_INTX_FUNC(val) ((val) & 0xFF)
53#define QLC_83XX_LEGACY_INTX_MAX_RETRY 100
54#define QLC_83XX_LEGACY_INTX_DELAY 4
55#define QLC_83XX_REG_DESC 1
56#define QLC_83XX_LRO_DESC 2
57#define QLC_83XX_CTRL_DESC 3
58#define QLC_83XX_FW_CAPABILITY_TSO BIT_6
59#define QLC_83XX_FW_CAP_LRO_MSS BIT_17
60#define QLC_83XX_HOST_RDS_MODE_UNIQUE 0
61#define QLC_83XX_HOST_SDS_MBX_IDX 8
62
63#define QLCNIC_HOST_RDS_MBX_IDX 88
64#define QLCNIC_MAX_RING_SETS 8
65
629263ac
SC		 66/* Pause control registers */
67#define QLC_83XX_SRE_SHIM_REG 0x0D200284
68#define QLC_83XX_PORT0_THRESHOLD 0x0B2003A4
69#define QLC_83XX_PORT1_THRESHOLD 0x0B2013A4
70#define QLC_83XX_PORT0_TC_MC_REG 0x0B200388
71#define QLC_83XX_PORT1_TC_MC_REG 0x0B201388
72#define QLC_83XX_PORT0_TC_STATS 0x0B20039C
73#define QLC_83XX_PORT1_TC_STATS 0x0B20139C
74#define QLC_83XX_PORT2_IFB_THRESHOLD 0x0B200704
75#define QLC_83XX_PORT3_IFB_THRESHOLD 0x0B201704
76
77/* Peg PC status registers */
78#define QLC_83XX_CRB_PEG_NET_0 0x3400003c
79#define QLC_83XX_CRB_PEG_NET_1 0x3410003c
80#define QLC_83XX_CRB_PEG_NET_2 0x3420003c
81#define QLC_83XX_CRB_PEG_NET_3 0x3430003c
82#define QLC_83XX_CRB_PEG_NET_4 0x34b0003c
83
84/* Firmware image definitions */
85#define QLC_83XX_BOOTLOADER_FLASH_ADDR 0x10000
86#define QLC_83XX_FW_FILE_NAME "83xx_fw.bin"
87#define QLC_83XX_BOOT_FROM_FLASH 0
88#define QLC_83XX_BOOT_FROM_FILE 0x12345678
89
81d0aeb0
SC		 90#define QLC_83XX_MAX_RESET_SEQ_ENTRIES 16
91
7cb03b23
RB		 92/* status descriptor mailbox data
93 * @phy_addr_{low|high}: physical address of buffer
94 * @sds_ring_size: buffer size
95 * @intrpt_id: interrupt id
96 * @intrpt_val: source of interrupt
97 */
98struct qlcnic_sds_mbx {
99 u32 phy_addr_low;
100 u32 phy_addr_high;
101 u32 rsvd1[4];
102#if defined(__LITTLE_ENDIAN)
103 u16 sds_ring_size;
104 u16 rsvd2;
105 u16 rsvd3[2];
106 u16 intrpt_id;
107 u8 intrpt_val;
108 u8 rsvd4;
109#elif defined(__BIG_ENDIAN)
110 u16 rsvd2;
111 u16 sds_ring_size;
112 u16 rsvd3[2];
113 u8 rsvd4;
114 u8 intrpt_val;
115 u16 intrpt_id;
116#endif
117 u32 rsvd5;
118} __packed;
119
120/* receive descriptor buffer data
121 * phy_addr_reg_{low|high}: physical address of regular buffer
122 * phy_addr_jmb_{low|high}: physical address of jumbo buffer
123 * reg_ring_sz: size of regular buffer
124 * reg_ring_len: no. of entries in regular buffer
125 * jmb_ring_len: no. of entries in jumbo buffer
126 * jmb_ring_sz: size of jumbo buffer
127 */
128struct qlcnic_rds_mbx {
129 u32 phy_addr_reg_low;
130 u32 phy_addr_reg_high;
131 u32 phy_addr_jmb_low;
132 u32 phy_addr_jmb_high;
133#if defined(__LITTLE_ENDIAN)
134 u16 reg_ring_sz;
135 u16 reg_ring_len;
136 u16 jmb_ring_sz;
137 u16 jmb_ring_len;
138#elif defined(__BIG_ENDIAN)
139 u16 reg_ring_len;
140 u16 reg_ring_sz;
141 u16 jmb_ring_len;
142 u16 jmb_ring_sz;
143#endif
144} __packed;
145
146/* host producers for regular and jumbo rings */
147struct __host_producer_mbx {
148 u32 reg_buf;
149 u32 jmb_buf;
150} __packed;
151
152/* Receive context mailbox data outbox registers
153 * @state: state of the context
154 * @vport_id: virtual port id
155 * @context_id: receive context id
156 * @num_pci_func: number of pci functions of the port
157 * @phy_port: physical port id
158 */
159struct qlcnic_rcv_mbx_out {
160#if defined(__LITTLE_ENDIAN)
161 u8 rcv_num;
162 u8 sts_num;
163 u16 ctx_id;
164 u8 state;
165 u8 num_pci_func;
166 u8 phy_port;
167 u8 vport_id;
168#elif defined(__BIG_ENDIAN)
169 u16 ctx_id;
170 u8 sts_num;
171 u8 rcv_num;
172 u8 vport_id;
173 u8 phy_port;
174 u8 num_pci_func;
175 u8 state;
176#endif
177 u32 host_csmr[QLCNIC_MAX_RING_SETS];
178 struct __host_producer_mbx host_prod[QLCNIC_MAX_RING_SETS];
179} __packed;
180
181struct qlcnic_add_rings_mbx_out {
182#if defined(__LITTLE_ENDIAN)
183 u8 rcv_num;
184 u8 sts_num;
185 u16 ctx_id;
186#elif defined(__BIG_ENDIAN)
187 u16 ctx_id;
188 u8 sts_num;
189 u8 rcv_num;
190#endif
191 u32 host_csmr[QLCNIC_MAX_RING_SETS];
192 struct __host_producer_mbx host_prod[QLCNIC_MAX_RING_SETS];
193} __packed;
194
195/* Transmit context mailbox inbox registers
196 * @phys_addr_{low|high}: DMA address of the transmit buffer
197 * @cnsmr_index_{low|high}: host consumer index
198 * @size: legth of transmit buffer ring
199 * @intr_id: interrput id
200 * @src: src of interrupt
201 */
202struct qlcnic_tx_mbx {
203 u32 phys_addr_low;
204 u32 phys_addr_high;
205 u32 cnsmr_index_low;
206 u32 cnsmr_index_high;
207#if defined(__LITTLE_ENDIAN)
208 u16 size;
209 u16 intr_id;
210 u8 src;
211 u8 rsvd[3];
212#elif defined(__BIG_ENDIAN)
213 u16 intr_id;
214 u16 size;
215 u8 rsvd[3];
216 u8 src;
217#endif
218} __packed;
219
220/* Transmit context mailbox outbox registers
221 * @host_prod: host producer index
222 * @ctx_id: transmit context id
223 * @state: state of the transmit context
224 */
225
226struct qlcnic_tx_mbx_out {
227 u32 host_prod;
228#if defined(__LITTLE_ENDIAN)
229 u16 ctx_id;
230 u8 state;
231 u8 rsvd;
232#elif defined(__BIG_ENDIAN)
233 u8 rsvd;
234 u8 state;
235 u16 ctx_id;
236#endif
237} __packed;
238
7f966452
SC		 239struct qlcnic_intrpt_config {
240 u8 type;
241 u8 enabled;
242 u16 id;
243 u32 src;
244};
245
246struct qlcnic_macvlan_mbx {
a96227e6
SS		 247#if defined(__LITTLE_ENDIAN)
248 u8 mac_addr0;
249 u8 mac_addr1;
250 u8 mac_addr2;
251 u8 mac_addr3;
252 u8 mac_addr4;
253 u8 mac_addr5;
7f966452 254 u16 vlan;
a96227e6
SS		 255#elif defined(__BIG_ENDIAN)
256 u8 mac_addr3;
257 u8 mac_addr2;
258 u8 mac_addr1;
259 u8 mac_addr0;
260 u16 vlan;
261 u8 mac_addr5;
262 u8 mac_addr4;
263#endif
7f966452
SC		 264};
265
629263ac
SC		 266struct qlc_83xx_fw_info {
267 const struct firmware *fw;
268 u16 major_fw_version;
269 u8 minor_fw_version;
270 u8 sub_fw_version;
271 u8 fw_build_num;
272 u8 load_from_file;
273};
274
81d0aeb0
SC		 275struct qlc_83xx_reset {
276 struct qlc_83xx_reset_hdr *hdr;
277 int seq_index;
278 int seq_error;
279 int array_index;
280 u32 array[QLC_83XX_MAX_RESET_SEQ_ENTRIES];
281 u8 *buff;
282 u8 *stop_offset;
283 u8 *start_offset;
284 u8 *init_offset;
285 u8 seq_end;
286 u8 template_end;
287};
288
629263ac
SC		 289#define QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY 0x1
290#define QLC_83XX_IDC_GRACEFULL_RESET 0x2
291#define QLC_83XX_IDC_TIMESTAMP 0
292#define QLC_83XX_IDC_DURATION 1
293#define QLC_83XX_IDC_INIT_TIMEOUT_SECS 30
294#define QLC_83XX_IDC_RESET_ACK_TIMEOUT_SECS 10
295#define QLC_83XX_IDC_RESET_TIMEOUT_SECS 10
296#define QLC_83XX_IDC_QUIESCE_ACK_TIMEOUT_SECS 20
297#define QLC_83XX_IDC_FW_POLL_DELAY (1 * HZ)
298#define QLC_83XX_IDC_FW_FAIL_THRESH 2
299#define QLC_83XX_IDC_MAX_FUNC_PER_PARTITION_INFO 8
300#define QLC_83XX_IDC_MAX_CNA_FUNCTIONS 16
301#define QLC_83XX_IDC_MAJOR_VERSION 1
302#define QLC_83XX_IDC_MINOR_VERSION 0
303#define QLC_83XX_IDC_FLASH_PARAM_ADDR 0x3e8020
304
629263ac
SC		 305struct qlcnic_adapter;
306struct qlc_83xx_idc {
307 int (*state_entry) (struct qlcnic_adapter *);
308 u64 sec_counter;
309 u64 delay;
310 unsigned long status;
311 int err_code;
312 int collect_dump;
313 u8 curr_state;
314 u8 prev_state;
315 u8 vnic_state;
316 u8 vnic_wait_limit;
317 u8 quiesce_req;
099907fa 318 u8 delay_reset;
629263ac
SC		 319 char **name;
320};
7f966452 321
f036e4f4
RB		 322/* Device States */
323enum qlcnic_83xx_states {
324 QLC_83XX_IDC_DEV_UNKNOWN,
325 QLC_83XX_IDC_DEV_COLD,
326 QLC_83XX_IDC_DEV_INIT,
327 QLC_83XX_IDC_DEV_READY,
328 QLC_83XX_IDC_DEV_NEED_RESET,
329 QLC_83XX_IDC_DEV_NEED_QUISCENT,
330 QLC_83XX_IDC_DEV_FAILED,
331 QLC_83XX_IDC_DEV_QUISCENT
332};
333
483202d5
JK		 334#define QLCNIC_MBX_RSP(reg) LSW(reg)
335#define QLCNIC_MBX_NUM_REGS(reg) (MSW(reg) & 0x1FF)
336#define QLCNIC_MBX_STATUS(reg) (((reg) >> 25) & 0x7F)
337#define QLCNIC_MBX_HOST(ahw, i) ((ahw)->pci_base0 + ((i) * 4))
338#define QLCNIC_MBX_FW(ahw, i) ((ahw)->pci_base0 + 0x800 + ((i) * 4))
339
7f966452
SC		 340/* Mailbox process AEN count */
341#define QLC_83XX_IDC_COMP_AEN 3
342#define QLC_83XX_MBX_AEN_CNT 5
343#define QLC_83XX_MODULE_LOADED 1
344#define QLC_83XX_MBX_READY 2
345#define QLC_83XX_MBX_AEN_ACK 3
346#define QLC_83XX_SFP_PRESENT(data) ((data) & 3)
347#define QLC_83XX_SFP_ERR(data) (((data) >> 2) & 3)
348#define QLC_83XX_SFP_MODULE_TYPE(data) (((data) >> 4) & 0x1F)
349#define QLC_83XX_SFP_CU_LENGTH(data) (LSB((data) >> 16))
350#define QLC_83XX_SFP_TX_FAULT(data) ((data) & BIT_10)
351#define QLC_83XX_SFP_10G_CAPABLE(data) ((data) & BIT_11)
352#define QLC_83XX_LINK_STATS(data) ((data) & BIT_0)
353#define QLC_83XX_CURRENT_LINK_SPEED(data) (((data) >> 3) & 7)
354#define QLC_83XX_LINK_PAUSE(data) (((data) >> 6) & 3)
355#define QLC_83XX_LINK_LB(data) (((data) >> 8) & 7)
356#define QLC_83XX_LINK_FEC(data) ((data) & BIT_12)
357#define QLC_83XX_LINK_EEE(data) ((data) & BIT_13)
358#define QLC_83XX_DCBX(data) (((data) >> 28) & 7)
359#define QLC_83XX_AUTONEG(data) ((data) & BIT_15)
360#define QLC_83XX_CFG_STD_PAUSE (1 << 5)
361#define QLC_83XX_CFG_STD_TX_PAUSE (1 << 20)
362#define QLC_83XX_CFG_STD_RX_PAUSE (2 << 20)
363#define QLC_83XX_CFG_STD_TX_RX_PAUSE (3 << 20)
364#define QLC_83XX_ENABLE_AUTONEG (1 << 15)
365#define QLC_83XX_CFG_LOOPBACK_HSS (2 << 1)
366#define QLC_83XX_CFG_LOOPBACK_PHY (3 << 1)
367#define QLC_83XX_CFG_LOOPBACK_EXT (4 << 1)
368
369/* LED configuration settings */
370#define QLC_83XX_ENABLE_BEACON 0xe
371#define QLC_83XX_LED_RATE 0xff
372#define QLC_83XX_LED_ACT (1 << 10)
373#define QLC_83XX_LED_MOD (0 << 13)
374#define QLC_83XX_LED_CONFIG (QLC_83XX_LED_RATE | QLC_83XX_LED_ACT | \
375 QLC_83XX_LED_MOD)
376
377#define QLC_83XX_10M_LINK 1
378#define QLC_83XX_100M_LINK 2
379#define QLC_83XX_1G_LINK 3
380#define QLC_83XX_10G_LINK 4
381#define QLC_83XX_STAT_TX 3
382#define QLC_83XX_STAT_RX 2
383#define QLC_83XX_STAT_MAC 1
384#define QLC_83XX_TX_STAT_REGS 14
385#define QLC_83XX_RX_STAT_REGS 40
52290740 386#define QLC_83XX_MAC_STAT_REGS 94
7f966452
SC		 387
388#define QLC_83XX_GET_FUNC_PRIVILEGE(VAL, FN) (0x3 & ((VAL) >> (FN * 2)))
389#define QLC_83XX_SET_FUNC_OPMODE(VAL, FN) ((VAL) << (FN * 2))
390#define QLC_83XX_DEFAULT_OPMODE 0x55555555
391#define QLC_83XX_PRIVLEGED_FUNC 0x1
392#define QLC_83XX_VIRTUAL_FUNC 0x2
393
394#define QLC_83XX_LB_MAX_FILTERS 2048
395#define QLC_83XX_LB_BUCKET_SIZE 256
396#define QLC_83XX_MINIMUM_VECTOR 3
52e493d0
JK		 397#define QLC_83XX_MAX_MC_COUNT 38
398#define QLC_83XX_MAX_UC_COUNT 4096
7f966452
SC		 399
400#define QLC_83XX_GET_FUNC_MODE_FROM_NPAR_INFO(val) (val & 0x80000000)
401#define QLC_83XX_GET_LRO_CAPABILITY(val) (val & 0x20)
402#define QLC_83XX_GET_LSO_CAPABILITY(val) (val & 0x40)
403#define QLC_83XX_GET_LSO_CAPABILITY(val) (val & 0x40)
404#define QLC_83XX_GET_HW_LRO_CAPABILITY(val) (val & 0x400)
405#define QLC_83XX_GET_VLAN_ALIGN_CAPABILITY(val) (val & 0x4000)
99e85879 406#define QLC_83XX_GET_FW_LRO_MSS_CAPABILITY(val) (val & 0x20000)
7f966452
SC		 407#define QLC_83XX_VIRTUAL_NIC_MODE 0xFF
408#define QLC_83XX_DEFAULT_MODE 0x0
02feda17 409#define QLC_83XX_SRIOV_MODE 0x1
7f966452
SC		 410#define QLCNIC_BRDTYPE_83XX_10G 0x0083
411
d865ebb4
SC		 412#define QLC_83XX_FLASH_SPI_STATUS 0x2808E010
413#define QLC_83XX_FLASH_SPI_CONTROL 0x2808E014
414#define QLC_83XX_FLASH_STATUS 0x42100004
415#define QLC_83XX_FLASH_CONTROL 0x42110004
416#define QLC_83XX_FLASH_ADDR 0x42110008
417#define QLC_83XX_FLASH_WRDATA 0x4211000C
418#define QLC_83XX_FLASH_RDDATA 0x42110018
419#define QLC_83XX_FLASH_DIRECT_WINDOW 0x42110030
420#define QLC_83XX_FLASH_DIRECT_DATA(DATA) (0x42150000 | (0x0000FFFF&DATA))
421#define QLC_83XX_FLASH_SECTOR_ERASE_CMD 0xdeadbeef
422#define QLC_83XX_FLASH_WRITE_CMD 0xdacdacda
423#define QLC_83XX_FLASH_BULK_WRITE_CMD 0xcadcadca
424#define QLC_83XX_FLASH_READ_RETRY_COUNT 5000
425#define QLC_83XX_FLASH_STATUS_READY 0x6
a520030e
HM		 426#define QLC_83XX_FLASH_WRITE_MIN 2
427#define QLC_83XX_FLASH_WRITE_MAX 64
d865ebb4
SC		 428#define QLC_83XX_FLASH_STATUS_REG_POLL_DELAY 1
429#define QLC_83XX_ERASE_MODE 1
430#define QLC_83XX_WRITE_MODE 2
431#define QLC_83XX_BULK_WRITE_MODE 3
432#define QLC_83XX_FLASH_FDT_WRITE_DEF_SIG 0xFD0100
433#define QLC_83XX_FLASH_FDT_ERASE_DEF_SIG 0xFD0300
434#define QLC_83XX_FLASH_FDT_READ_MFG_ID_VAL 0xFD009F
435#define QLC_83XX_FLASH_OEM_ERASE_SIG 0xFD03D8
436#define QLC_83XX_FLASH_OEM_WRITE_SIG 0xFD0101
437#define QLC_83XX_FLASH_OEM_READ_SIG 0xFD0005
438#define QLC_83XX_FLASH_ADDR_TEMP_VAL 0x00800000
439#define QLC_83XX_FLASH_ADDR_SECOND_TEMP_VAL 0x00800001
440#define QLC_83XX_FLASH_WRDATA_DEF 0x0
441#define QLC_83XX_FLASH_READ_CTRL 0x3F
442#define QLC_83XX_FLASH_SPI_CTRL 0x4
443#define QLC_83XX_FLASH_FIRST_ERASE_MS_VAL 0x2
444#define QLC_83XX_FLASH_SECOND_ERASE_MS_VAL 0x5
445#define QLC_83XX_FLASH_LAST_ERASE_MS_VAL 0x3D
446#define QLC_83XX_FLASH_FIRST_MS_PATTERN 0x43
447#define QLC_83XX_FLASH_SECOND_MS_PATTERN 0x7F
448#define QLC_83XX_FLASH_LAST_MS_PATTERN 0x7D
449#define QLC_83xx_FLASH_MAX_WAIT_USEC 100
450#define QLC_83XX_FLASH_LOCK_TIMEOUT 10000
451
7f966452
SC		 452/* Additional registers in 83xx */
453enum qlc_83xx_ext_regs {
454 QLCNIC_GLOBAL_RESET = 0,
455 QLCNIC_WILDCARD,
456 QLCNIC_INFORMANT,
457 QLCNIC_HOST_MBX_CTRL,
458 QLCNIC_FW_MBX_CTRL,
459 QLCNIC_BOOTLOADER_ADDR,
460 QLCNIC_BOOTLOADER_SIZE,
461 QLCNIC_FW_IMAGE_ADDR,
462 QLCNIC_MBX_INTR_ENBL,
463 QLCNIC_DEF_INT_MASK,
464 QLCNIC_DEF_INT_ID,
465 QLC_83XX_IDC_MAJ_VERSION,
466 QLC_83XX_IDC_DEV_STATE,
467 QLC_83XX_IDC_DRV_PRESENCE,
468 QLC_83XX_IDC_DRV_ACK,
469 QLC_83XX_IDC_CTRL,
470 QLC_83XX_IDC_DRV_AUDIT,
471 QLC_83XX_IDC_MIN_VERSION,
472 QLC_83XX_RECOVER_DRV_LOCK,
473 QLC_83XX_IDC_PF_0,
474 QLC_83XX_IDC_PF_1,
475 QLC_83XX_IDC_PF_2,
476 QLC_83XX_IDC_PF_3,
477 QLC_83XX_IDC_PF_4,
478 QLC_83XX_IDC_PF_5,
479 QLC_83XX_IDC_PF_6,
480 QLC_83XX_IDC_PF_7,
481 QLC_83XX_IDC_PF_8,
482 QLC_83XX_IDC_PF_9,
483 QLC_83XX_IDC_PF_10,
484 QLC_83XX_IDC_PF_11,
485 QLC_83XX_IDC_PF_12,
486 QLC_83XX_IDC_PF_13,
487 QLC_83XX_IDC_PF_14,
488 QLC_83XX_IDC_PF_15,
489 QLC_83XX_IDC_DEV_PARTITION_INFO_1,
490 QLC_83XX_IDC_DEV_PARTITION_INFO_2,
491 QLC_83XX_DRV_OP_MODE,
492 QLC_83XX_VNIC_STATE,
493 QLC_83XX_DRV_LOCK,
494 QLC_83XX_DRV_UNLOCK,
495 QLC_83XX_DRV_LOCK_ID,
496 QLC_83XX_ASIC_TEMP,
497};
498
499/* 83xx funcitons */
500int qlcnic_83xx_get_fw_version(struct qlcnic_adapter *);
501int qlcnic_83xx_mbx_op(struct qlcnic_adapter *, struct qlcnic_cmd_args *);
502int qlcnic_83xx_setup_intr(struct qlcnic_adapter *, u8);
503void qlcnic_83xx_get_func_no(struct qlcnic_adapter *);
504int qlcnic_83xx_cam_lock(struct qlcnic_adapter *);
505void qlcnic_83xx_cam_unlock(struct qlcnic_adapter *);
506int qlcnic_send_ctrl_op(struct qlcnic_adapter *, struct qlcnic_cmd_args *, u32);
319ecf12
SC		 507void qlcnic_83xx_add_sysfs(struct qlcnic_adapter *);
508void qlcnic_83xx_remove_sysfs(struct qlcnic_adapter *);
7f966452
SC		 509void qlcnic_83xx_write_crb(struct qlcnic_adapter *, char *, loff_t, size_t);
510void qlcnic_83xx_read_crb(struct qlcnic_adapter *, char *, loff_t, size_t);
511int qlcnic_83xx_rd_reg_indirect(struct qlcnic_adapter *, ulong);
512int qlcnic_83xx_wrt_reg_indirect(struct qlcnic_adapter *, ulong, u32);
4be41e92 513void qlcnic_83xx_process_rcv_diag(struct qlcnic_adapter *, int, u64 []);
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SC		 514int qlcnic_83xx_nic_set_promisc(struct qlcnic_adapter *, u32);
515int qlcnic_83xx_set_lb_mode(struct qlcnic_adapter *, u8);
516int qlcnic_83xx_clear_lb_mode(struct qlcnic_adapter *, u8);
517int qlcnic_83xx_config_hw_lro(struct qlcnic_adapter *, int);
518int qlcnic_83xx_config_rss(struct qlcnic_adapter *, int);
519int qlcnic_83xx_config_intr_coalesce(struct qlcnic_adapter *);
f80bc8fe 520void qlcnic_83xx_change_l2_filter(struct qlcnic_adapter *, u64 *, u16);
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SC		 521int qlcnic_83xx_get_pci_info(struct qlcnic_adapter *, struct qlcnic_pci_info *);
522int qlcnic_83xx_set_nic_info(struct qlcnic_adapter *, struct qlcnic_info *);
523void qlcnic_83xx_register_nic_idc_func(struct qlcnic_adapter *, int);
524
4be41e92
SC		 525int qlcnic_83xx_napi_add(struct qlcnic_adapter *, struct net_device *);
526void qlcnic_83xx_napi_del(struct qlcnic_adapter *);
527void qlcnic_83xx_napi_enable(struct qlcnic_adapter *);
528void qlcnic_83xx_napi_disable(struct qlcnic_adapter *);
319ecf12 529int qlcnic_83xx_config_led(struct qlcnic_adapter *, u32, u32);
7f966452
SC		 530void qlcnic_ind_wr(struct qlcnic_adapter *, u32, u32);
531int qlcnic_ind_rd(struct qlcnic_adapter *, u32);
7f966452
SC		 532int qlcnic_83xx_create_rx_ctx(struct qlcnic_adapter *);
533int qlcnic_83xx_create_tx_ctx(struct qlcnic_adapter *,
534 struct qlcnic_host_tx_ring *, int);
7cb03b23
RB		 535void qlcnic_83xx_del_rx_ctx(struct qlcnic_adapter *);
536void qlcnic_83xx_del_tx_ctx(struct qlcnic_adapter *,
537 struct qlcnic_host_tx_ring *);
7f966452
SC		 538int qlcnic_83xx_get_nic_info(struct qlcnic_adapter *, struct qlcnic_info *, u8);
539int qlcnic_83xx_setup_link_event(struct qlcnic_adapter *, int);
540void qlcnic_83xx_process_rcv_ring_diag(struct qlcnic_host_sds_ring *);
541int qlcnic_83xx_config_intrpt(struct qlcnic_adapter *, bool);
f80bc8fe 542int qlcnic_83xx_sre_macaddr_change(struct qlcnic_adapter *, u8 *, u16, u8);
7f966452
SC		 543int qlcnic_83xx_get_mac_address(struct qlcnic_adapter *, u8 *);
544void qlcnic_83xx_configure_mac(struct qlcnic_adapter *, u8 *, u8,
545 struct qlcnic_cmd_args *);
546int qlcnic_83xx_alloc_mbx_args(struct qlcnic_cmd_args *,
547 struct qlcnic_adapter *, u32);
548void qlcnic_free_mbx_args(struct qlcnic_cmd_args *);
549void qlcnic_set_npar_data(struct qlcnic_adapter *, const struct qlcnic_info *,
550 struct qlcnic_info *);
551void qlcnic_83xx_config_intr_coal(struct qlcnic_adapter *);
552irqreturn_t qlcnic_83xx_handle_aen(int, void *);
553int qlcnic_83xx_get_port_info(struct qlcnic_adapter *);
554void qlcnic_83xx_enable_mbx_intrpt(struct qlcnic_adapter *);
f036e4f4 555void qlcnic_83xx_disable_mbx_intr(struct qlcnic_adapter *);
7f966452 556irqreturn_t qlcnic_83xx_clear_legacy_intr(struct qlcnic_adapter *);
ac166700 557irqreturn_t qlcnic_83xx_intr(int, void *);
7f966452
SC		 558irqreturn_t qlcnic_83xx_tmp_intr(int, void *);
559void qlcnic_83xx_enable_intr(struct qlcnic_adapter *,
560 struct qlcnic_host_sds_ring *);
ac166700
HM		 561void qlcnic_83xx_disable_intr(struct qlcnic_adapter *,
562 struct qlcnic_host_sds_ring *);
7f966452
SC		 563void qlcnic_83xx_check_vf(struct qlcnic_adapter *,
564 const struct pci_device_id *);
d1a1105e 565void __qlcnic_83xx_process_aen(struct qlcnic_adapter *);
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SC		 566int qlcnic_83xx_get_port_config(struct qlcnic_adapter *);
567int qlcnic_83xx_set_port_config(struct qlcnic_adapter *);
568int qlcnic_enable_eswitch(struct qlcnic_adapter *, u8, u8);
569int qlcnic_83xx_get_nic_configuration(struct qlcnic_adapter *);
570int qlcnic_83xx_config_default_opmode(struct qlcnic_adapter *);
571int qlcnic_83xx_setup_mbx_intr(struct qlcnic_adapter *);
572void qlcnic_83xx_free_mbx_intr(struct qlcnic_adapter *);
573void qlcnic_83xx_register_map(struct qlcnic_hardware_context *);
574void qlcnic_83xx_idc_aen_work(struct work_struct *);
575void qlcnic_83xx_config_ipaddr(struct qlcnic_adapter *, __be32, int);
d865ebb4
SC		 576
577int qlcnic_83xx_erase_flash_sector(struct qlcnic_adapter *, u32);
578int qlcnic_83xx_flash_bulk_write(struct qlcnic_adapter *, u32, u32 *, int);
579int qlcnic_83xx_flash_write32(struct qlcnic_adapter *, u32, u32 *);
580int qlcnic_83xx_lock_flash(struct qlcnic_adapter *);
581void qlcnic_83xx_unlock_flash(struct qlcnic_adapter *);
582int qlcnic_83xx_save_flash_status(struct qlcnic_adapter *);
583int qlcnic_83xx_restore_flash_status(struct qlcnic_adapter *, int);
584int qlcnic_83xx_read_flash_mfg_id(struct qlcnic_adapter *);
585int qlcnic_83xx_read_flash_descriptor_table(struct qlcnic_adapter *);
629263ac
SC		 586int qlcnic_83xx_flash_read32(struct qlcnic_adapter *, u32, u8 *, int);
587int qlcnic_83xx_lockless_flash_read32(struct qlcnic_adapter *,
588 u32, u8 *, int);
f8468331 589int qlcnic_83xx_init(struct qlcnic_adapter *, int);
629263ac
SC		 590int qlcnic_83xx_idc_ready_state_entry(struct qlcnic_adapter *);
591int qlcnic_83xx_check_hw_status(struct qlcnic_adapter *p_dev);
592void qlcnic_83xx_idc_poll_dev_state(struct work_struct *);
81d0aeb0 593int qlcnic_83xx_get_reset_instruction_template(struct qlcnic_adapter *);
629263ac
SC		 594void qlcnic_83xx_idc_exit(struct qlcnic_adapter *);
595void qlcnic_83xx_idc_request_reset(struct qlcnic_adapter *, u32);
596int qlcnic_83xx_lock_driver(struct qlcnic_adapter *);
597void qlcnic_83xx_unlock_driver(struct qlcnic_adapter *);
598int qlcnic_83xx_set_default_offload_settings(struct qlcnic_adapter *);
599int qlcnic_83xx_ms_mem_write128(struct qlcnic_adapter *, u64, u32 *, u32);
d71170fb
SC		 600int qlcnic_83xx_idc_vnic_pf_entry(struct qlcnic_adapter *);
601int qlcnic_83xx_enable_vnic_mode(struct qlcnic_adapter *, int);
602int qlcnic_83xx_disable_vnic_mode(struct qlcnic_adapter *, int);
603int qlcnic_83xx_config_vnic_opmode(struct qlcnic_adapter *);
604int qlcnic_83xx_get_vnic_vport_info(struct qlcnic_adapter *,
605 struct qlcnic_info *, u8);
606int qlcnic_83xx_get_vnic_pf_info(struct qlcnic_adapter *, struct qlcnic_info *);
4e60ac46
SC		 607
608void qlcnic_83xx_get_minidump_template(struct qlcnic_adapter *);
7e38d04b 609void qlcnic_83xx_get_stats(struct qlcnic_adapter *adapter, u64 *data);
b938662d 610int qlcnic_83xx_get_settings(struct qlcnic_adapter *, struct ethtool_cmd *);
7e38d04b
SC		 611int qlcnic_83xx_set_settings(struct qlcnic_adapter *, struct ethtool_cmd *);
612void qlcnic_83xx_get_pauseparam(struct qlcnic_adapter *,
613 struct ethtool_pauseparam *);
614int qlcnic_83xx_set_pauseparam(struct qlcnic_adapter *,
615 struct ethtool_pauseparam *);
616int qlcnic_83xx_test_link(struct qlcnic_adapter *);
617int qlcnic_83xx_reg_test(struct qlcnic_adapter *);
618int qlcnic_83xx_get_regs_len(struct qlcnic_adapter *);
619int qlcnic_83xx_get_registers(struct qlcnic_adapter *, u32 *);
ba4468db 620int qlcnic_83xx_loopback_test(struct net_device *, u8);
58ead415 621int qlcnic_83xx_interrupt_test(struct net_device *);
d16951d9 622int qlcnic_83xx_set_led(struct net_device *, enum ethtool_phys_id_state);
7e38d04b 623int qlcnic_83xx_flash_test(struct qlcnic_adapter *);
a520030e
HM		 624int qlcnic_83xx_enable_flash_write(struct qlcnic_adapter *);
625int qlcnic_83xx_disable_flash_write(struct qlcnic_adapter *);
f197a7aa 626u32 qlcnic_83xx_mac_rcode(struct qlcnic_adapter *);
9106e5db 627u32 qlcnic_83xx_mbx_poll(struct qlcnic_adapter *, u32 *);
7ed3ce48
RB		 628void qlcnic_83xx_enable_mbx_poll(struct qlcnic_adapter *);
629void qlcnic_83xx_disable_mbx_poll(struct qlcnic_adapter *);
52e493d0 630void qlcnic_83xx_set_mac_filter_count(struct qlcnic_adapter *);
486a5bc7
RB		 631int qlcnic_83xx_shutdown(struct pci_dev *);
632int qlcnic_83xx_resume(struct qlcnic_adapter *);
633int qlcnic_83xx_idc_init(struct qlcnic_adapter *);
634int qlcnic_83xx_idc_reattach_driver(struct qlcnic_adapter *);
635int qlcnic_83xx_set_vnic_opmode(struct qlcnic_adapter *);
636int qlcnic_83xx_check_vnic_state(struct qlcnic_adapter *);
7f966452 637#endif
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