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Merge tag 'actions-drivers-for-4.13' of git://git.kernel.org/pub/scm/linux/kernel...
[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / qlogic / qlcnic / qlcnic_83xx_hw.h
CommitLineData
577ae39d
JK		 1/*
2 * QLogic qlcnic NIC Driver
3 * Copyright (c) 2009-2013 QLogic Corporation
4 *
5 * See LICENSE.qlcnic for copyright and licensing details.
6 */
7
7f966452
SC		 8#ifndef __QLCNIC_83XX_HW_H
9#define __QLCNIC_83XX_HW_H
10
11#include <linux/types.h>
12#include <linux/etherdevice.h>
a930a463 13
7f966452
SC		 14#include "qlcnic_hw.h"
15
a520030e
HM		 16#define QLCNIC_83XX_BAR0_LENGTH 0x4000
17
7f966452
SC		 18/* Directly mapped registers */
19#define QLC_83XX_CRB_WIN_BASE 0x3800
20#define QLC_83XX_CRB_WIN_FUNC(f) (QLC_83XX_CRB_WIN_BASE+((f)*4))
21#define QLC_83XX_SEM_LOCK_BASE 0x3840
22#define QLC_83XX_SEM_UNLOCK_BASE 0x3844
23#define QLC_83XX_SEM_LOCK_FUNC(f) (QLC_83XX_SEM_LOCK_BASE+((f)*8))
24#define QLC_83XX_SEM_UNLOCK_FUNC(f) (QLC_83XX_SEM_UNLOCK_BASE+((f)*8))
25#define QLC_83XX_LINK_STATE(f) (0x3698+((f) > 7 ? 4 : 0))
26#define QLC_83XX_LINK_SPEED(f) (0x36E0+(((f) >> 2) * 4))
27#define QLC_83XX_LINK_SPEED_FACTOR 10
28#define QLC_83xx_FUNC_VAL(v, f) ((v) & (1 << (f * 4)))
29#define QLC_83XX_INTX_PTR 0x38C0
30#define QLC_83XX_INTX_TRGR 0x38C4
31#define QLC_83XX_INTX_MASK 0x38C8
32
33#define QLC_83XX_DRV_LOCK_WAIT_COUNTER 100
34#define QLC_83XX_DRV_LOCK_WAIT_DELAY 20
35#define QLC_83XX_NEED_DRV_LOCK_RECOVERY 1
36#define QLC_83XX_DRV_LOCK_RECOVERY_IN_PROGRESS 2
37#define QLC_83XX_MAX_DRV_LOCK_RECOVERY_ATTEMPT 3
38#define QLC_83XX_DRV_LOCK_RECOVERY_DELAY 200
39#define QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK 0x3
2c4a7878
JK		 40#define QLC_83XX_LB_WAIT_COUNT 250
41#define QLC_83XX_LB_MSLEEP_COUNT 20
7f966452
SC		 42#define QLC_83XX_NO_NIC_RESOURCE 0x5
43#define QLC_83XX_MAC_PRESENT 0xC
44#define QLC_83XX_MAC_ABSENT 0xD
45
46
47#define QLC_83XX_FLASH_SECTOR_SIZE (64 * 1024)
48
49/* PEG status definitions */
50#define QLC_83XX_CMDPEG_COMPLETE 0xff01
51#define QLC_83XX_VALID_INTX_BIT30(val) ((val) & BIT_30)
52#define QLC_83XX_VALID_INTX_BIT31(val) ((val) & BIT_31)
53#define QLC_83XX_INTX_FUNC(val) ((val) & 0xFF)
54#define QLC_83XX_LEGACY_INTX_MAX_RETRY 100
55#define QLC_83XX_LEGACY_INTX_DELAY 4
56#define QLC_83XX_REG_DESC 1
57#define QLC_83XX_LRO_DESC 2
58#define QLC_83XX_CTRL_DESC 3
59#define QLC_83XX_FW_CAPABILITY_TSO BIT_6
60#define QLC_83XX_FW_CAP_LRO_MSS BIT_17
61#define QLC_83XX_HOST_RDS_MODE_UNIQUE 0
62#define QLC_83XX_HOST_SDS_MBX_IDX 8
63
64#define QLCNIC_HOST_RDS_MBX_IDX 88
7f966452 65
629263ac
SC		 66/* Pause control registers */
67#define QLC_83XX_SRE_SHIM_REG 0x0D200284
68#define QLC_83XX_PORT0_THRESHOLD 0x0B2003A4
69#define QLC_83XX_PORT1_THRESHOLD 0x0B2013A4
70#define QLC_83XX_PORT0_TC_MC_REG 0x0B200388
71#define QLC_83XX_PORT1_TC_MC_REG 0x0B201388
72#define QLC_83XX_PORT0_TC_STATS 0x0B20039C
73#define QLC_83XX_PORT1_TC_STATS 0x0B20139C
74#define QLC_83XX_PORT2_IFB_THRESHOLD 0x0B200704
75#define QLC_83XX_PORT3_IFB_THRESHOLD 0x0B201704
76
77/* Peg PC status registers */
78#define QLC_83XX_CRB_PEG_NET_0 0x3400003c
79#define QLC_83XX_CRB_PEG_NET_1 0x3410003c
80#define QLC_83XX_CRB_PEG_NET_2 0x3420003c
81#define QLC_83XX_CRB_PEG_NET_3 0x3430003c
82#define QLC_83XX_CRB_PEG_NET_4 0x34b0003c
83
84/* Firmware image definitions */
85#define QLC_83XX_BOOTLOADER_FLASH_ADDR 0x10000
86#define QLC_83XX_FW_FILE_NAME "83xx_fw.bin"
3ced0a88 87#define QLC_83XX_POST_FW_FILE_NAME "83xx_post_fw.bin"
fef349ce 88#define QLC_84XX_FW_FILE_NAME "84xx_fw.bin"
629263ac
SC		 89#define QLC_83XX_BOOT_FROM_FLASH 0
90#define QLC_83XX_BOOT_FROM_FILE 0x12345678
91
fef349ce 92#define QLC_FW_FILE_NAME_LEN 20
81d0aeb0
SC		 93#define QLC_83XX_MAX_RESET_SEQ_ENTRIES 16
94
e5c4e6c6
MC		 95#define QLC_83XX_MBX_POST_BC_OP 0x1
96#define QLC_83XX_MBX_COMPLETION 0x0
97#define QLC_83XX_MBX_REQUEST 0x1
98
99#define QLC_83XX_MBX_TIMEOUT (5 * HZ)
100#define QLC_83XX_MBX_CMD_LOOP 5000000
101
7cb03b23
RB		 102/* status descriptor mailbox data
103 * @phy_addr_{low|high}: physical address of buffer
104 * @sds_ring_size: buffer size
105 * @intrpt_id: interrupt id
106 * @intrpt_val: source of interrupt
107 */
108struct qlcnic_sds_mbx {
109 u32 phy_addr_low;
110 u32 phy_addr_high;
111 u32 rsvd1[4];
112#if defined(__LITTLE_ENDIAN)
113 u16 sds_ring_size;
114 u16 rsvd2;
115 u16 rsvd3[2];
116 u16 intrpt_id;
117 u8 intrpt_val;
118 u8 rsvd4;
119#elif defined(__BIG_ENDIAN)
120 u16 rsvd2;
121 u16 sds_ring_size;
122 u16 rsvd3[2];
123 u8 rsvd4;
124 u8 intrpt_val;
125 u16 intrpt_id;
126#endif
127 u32 rsvd5;
128} __packed;
129
130/* receive descriptor buffer data
131 * phy_addr_reg_{low|high}: physical address of regular buffer
132 * phy_addr_jmb_{low|high}: physical address of jumbo buffer
133 * reg_ring_sz: size of regular buffer
134 * reg_ring_len: no. of entries in regular buffer
135 * jmb_ring_len: no. of entries in jumbo buffer
136 * jmb_ring_sz: size of jumbo buffer
137 */
138struct qlcnic_rds_mbx {
139 u32 phy_addr_reg_low;
140 u32 phy_addr_reg_high;
141 u32 phy_addr_jmb_low;
142 u32 phy_addr_jmb_high;
143#if defined(__LITTLE_ENDIAN)
144 u16 reg_ring_sz;
145 u16 reg_ring_len;
146 u16 jmb_ring_sz;
147 u16 jmb_ring_len;
148#elif defined(__BIG_ENDIAN)
149 u16 reg_ring_len;
150 u16 reg_ring_sz;
151 u16 jmb_ring_len;
152 u16 jmb_ring_sz;
153#endif
154} __packed;
155
156/* host producers for regular and jumbo rings */
157struct __host_producer_mbx {
158 u32 reg_buf;
159 u32 jmb_buf;
160} __packed;
161
162/* Receive context mailbox data outbox registers
163 * @state: state of the context
164 * @vport_id: virtual port id
165 * @context_id: receive context id
166 * @num_pci_func: number of pci functions of the port
167 * @phy_port: physical port id
168 */
169struct qlcnic_rcv_mbx_out {
170#if defined(__LITTLE_ENDIAN)
171 u8 rcv_num;
172 u8 sts_num;
173 u16 ctx_id;
174 u8 state;
175 u8 num_pci_func;
176 u8 phy_port;
177 u8 vport_id;
178#elif defined(__BIG_ENDIAN)
179 u16 ctx_id;
180 u8 sts_num;
181 u8 rcv_num;
182 u8 vport_id;
183 u8 phy_port;
184 u8 num_pci_func;
185 u8 state;
186#endif
34e8c406
HM		 187 u32 host_csmr[QLCNIC_MAX_SDS_RINGS];
188 struct __host_producer_mbx host_prod[QLCNIC_MAX_SDS_RINGS];
7cb03b23
RB		 189} __packed;
190
191struct qlcnic_add_rings_mbx_out {
192#if defined(__LITTLE_ENDIAN)
193 u8 rcv_num;
194 u8 sts_num;
195 u16 ctx_id;
196#elif defined(__BIG_ENDIAN)
197 u16 ctx_id;
198 u8 sts_num;
199 u8 rcv_num;
200#endif
34e8c406
HM		 201 u32 host_csmr[QLCNIC_MAX_SDS_RINGS];
202 struct __host_producer_mbx host_prod[QLCNIC_MAX_SDS_RINGS];
7cb03b23
RB		 203} __packed;
204
205/* Transmit context mailbox inbox registers
206 * @phys_addr_{low|high}: DMA address of the transmit buffer
207 * @cnsmr_index_{low|high}: host consumer index
208 * @size: legth of transmit buffer ring
dbedd44e 209 * @intr_id: interrupt id
7cb03b23
RB		 210 * @src: src of interrupt
211 */
212struct qlcnic_tx_mbx {
213 u32 phys_addr_low;
214 u32 phys_addr_high;
215 u32 cnsmr_index_low;
216 u32 cnsmr_index_high;
217#if defined(__LITTLE_ENDIAN)
218 u16 size;
219 u16 intr_id;
220 u8 src;
221 u8 rsvd[3];
222#elif defined(__BIG_ENDIAN)
223 u16 intr_id;
224 u16 size;
225 u8 rsvd[3];
226 u8 src;
227#endif
228} __packed;
229
230/* Transmit context mailbox outbox registers
231 * @host_prod: host producer index
232 * @ctx_id: transmit context id
233 * @state: state of the transmit context
234 */
235
236struct qlcnic_tx_mbx_out {
237 u32 host_prod;
238#if defined(__LITTLE_ENDIAN)
239 u16 ctx_id;
240 u8 state;
241 u8 rsvd;
242#elif defined(__BIG_ENDIAN)
243 u8 rsvd;
244 u8 state;
245 u16 ctx_id;
246#endif
247} __packed;
248
7f966452
SC		 249struct qlcnic_intrpt_config {
250 u8 type;
251 u8 enabled;
252 u16 id;
253 u32 src;
254};
255
256struct qlcnic_macvlan_mbx {
a96227e6
SS		 257#if defined(__LITTLE_ENDIAN)
258 u8 mac_addr0;
259 u8 mac_addr1;
260 u8 mac_addr2;
261 u8 mac_addr3;
262 u8 mac_addr4;
263 u8 mac_addr5;
7f966452 264 u16 vlan;
a96227e6
SS		 265#elif defined(__BIG_ENDIAN)
266 u8 mac_addr3;
267 u8 mac_addr2;
268 u8 mac_addr1;
269 u8 mac_addr0;
270 u16 vlan;
271 u8 mac_addr5;
272 u8 mac_addr4;
273#endif
7f966452
SC		 274};
275
629263ac
SC		 276struct qlc_83xx_fw_info {
277 const struct firmware *fw;
7000078a 278 char fw_file_name[QLC_FW_FILE_NAME_LEN];
629263ac
SC		 279};
280
81d0aeb0
SC		 281struct qlc_83xx_reset {
282 struct qlc_83xx_reset_hdr *hdr;
283 int seq_index;
284 int seq_error;
285 int array_index;
286 u32 array[QLC_83XX_MAX_RESET_SEQ_ENTRIES];
287 u8 *buff;
288 u8 *stop_offset;
289 u8 *start_offset;
290 u8 *init_offset;
291 u8 seq_end;
292 u8 template_end;
293};
294
629263ac
SC		 295#define QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY 0x1
296#define QLC_83XX_IDC_GRACEFULL_RESET 0x2
890b6e02 297#define QLC_83XX_IDC_DISABLE_FW_DUMP 0x4
629263ac
SC		 298#define QLC_83XX_IDC_TIMESTAMP 0
299#define QLC_83XX_IDC_DURATION 1
300#define QLC_83XX_IDC_INIT_TIMEOUT_SECS 30
301#define QLC_83XX_IDC_RESET_ACK_TIMEOUT_SECS 10
302#define QLC_83XX_IDC_RESET_TIMEOUT_SECS 10
303#define QLC_83XX_IDC_QUIESCE_ACK_TIMEOUT_SECS 20
304#define QLC_83XX_IDC_FW_POLL_DELAY (1 * HZ)
305#define QLC_83XX_IDC_FW_FAIL_THRESH 2
306#define QLC_83XX_IDC_MAX_FUNC_PER_PARTITION_INFO 8
307#define QLC_83XX_IDC_MAX_CNA_FUNCTIONS 16
308#define QLC_83XX_IDC_MAJOR_VERSION 1
309#define QLC_83XX_IDC_MINOR_VERSION 0
310#define QLC_83XX_IDC_FLASH_PARAM_ADDR 0x3e8020
311
629263ac 312struct qlcnic_adapter;
225837a0
SS		 313struct qlcnic_fw_dump;
314
629263ac
SC		 315struct qlc_83xx_idc {
316 int (*state_entry) (struct qlcnic_adapter *);
317 u64 sec_counter;
318 u64 delay;
319 unsigned long status;
320 int err_code;
321 int collect_dump;
322 u8 curr_state;
323 u8 prev_state;
324 u8 vnic_state;
325 u8 vnic_wait_limit;
326 u8 quiesce_req;
099907fa 327 u8 delay_reset;
629263ac
SC		 328 char **name;
329};
7f966452 330
154d0c81
MC		 331enum qlcnic_vlan_operations {
332 QLC_VLAN_ADD = 0,
333 QLC_VLAN_DELETE
334};
335
f036e4f4
RB		 336/* Device States */
337enum qlcnic_83xx_states {
338 QLC_83XX_IDC_DEV_UNKNOWN,
339 QLC_83XX_IDC_DEV_COLD,
340 QLC_83XX_IDC_DEV_INIT,
341 QLC_83XX_IDC_DEV_READY,
342 QLC_83XX_IDC_DEV_NEED_RESET,
343 QLC_83XX_IDC_DEV_NEED_QUISCENT,
344 QLC_83XX_IDC_DEV_FAILED,
345 QLC_83XX_IDC_DEV_QUISCENT
346};
347
483202d5
JK		 348#define QLCNIC_MBX_RSP(reg) LSW(reg)
349#define QLCNIC_MBX_NUM_REGS(reg) (MSW(reg) & 0x1FF)
350#define QLCNIC_MBX_STATUS(reg) (((reg) >> 25) & 0x7F)
351#define QLCNIC_MBX_HOST(ahw, i) ((ahw)->pci_base0 + ((i) * 4))
352#define QLCNIC_MBX_FW(ahw, i) ((ahw)->pci_base0 + 0x800 + ((i) * 4))
353
7f966452
SC		 354/* Mailbox process AEN count */
355#define QLC_83XX_IDC_COMP_AEN 3
356#define QLC_83XX_MBX_AEN_CNT 5
357#define QLC_83XX_MODULE_LOADED 1
358#define QLC_83XX_MBX_READY 2
359#define QLC_83XX_MBX_AEN_ACK 3
360#define QLC_83XX_SFP_PRESENT(data) ((data) & 3)
361#define QLC_83XX_SFP_ERR(data) (((data) >> 2) & 3)
362#define QLC_83XX_SFP_MODULE_TYPE(data) (((data) >> 4) & 0x1F)
363#define QLC_83XX_SFP_CU_LENGTH(data) (LSB((data) >> 16))
364#define QLC_83XX_SFP_TX_FAULT(data) ((data) & BIT_10)
7f966452
SC		 365#define QLC_83XX_LINK_STATS(data) ((data) & BIT_0)
366#define QLC_83XX_CURRENT_LINK_SPEED(data) (((data) >> 3) & 7)
367#define QLC_83XX_LINK_PAUSE(data) (((data) >> 6) & 3)
368#define QLC_83XX_LINK_LB(data) (((data) >> 8) & 7)
369#define QLC_83XX_LINK_FEC(data) ((data) & BIT_12)
370#define QLC_83XX_LINK_EEE(data) ((data) & BIT_13)
371#define QLC_83XX_DCBX(data) (((data) >> 28) & 7)
372#define QLC_83XX_AUTONEG(data) ((data) & BIT_15)
6177a95a
JK		 373#define QLC_83XX_TX_PAUSE 0x10
374#define QLC_83XX_RX_PAUSE 0x20
375#define QLC_83XX_TX_RX_PAUSE 0x30
7f966452
SC		 376#define QLC_83XX_CFG_STD_PAUSE (1 << 5)
377#define QLC_83XX_CFG_STD_TX_PAUSE (1 << 20)
378#define QLC_83XX_CFG_STD_RX_PAUSE (2 << 20)
379#define QLC_83XX_CFG_STD_TX_RX_PAUSE (3 << 20)
380#define QLC_83XX_ENABLE_AUTONEG (1 << 15)
381#define QLC_83XX_CFG_LOOPBACK_HSS (2 << 1)
382#define QLC_83XX_CFG_LOOPBACK_PHY (3 << 1)
383#define QLC_83XX_CFG_LOOPBACK_EXT (4 << 1)
384
385/* LED configuration settings */
386#define QLC_83XX_ENABLE_BEACON 0xe
a0431589
HM		 387#define QLC_83XX_BEACON_ON 1
388#define QLC_83XX_BEACON_OFF 0
7f966452
SC		 389#define QLC_83XX_LED_RATE 0xff
390#define QLC_83XX_LED_ACT (1 << 10)
391#define QLC_83XX_LED_MOD (0 << 13)
392#define QLC_83XX_LED_CONFIG (QLC_83XX_LED_RATE | QLC_83XX_LED_ACT | \
393 QLC_83XX_LED_MOD)
394
395#define QLC_83XX_10M_LINK 1
396#define QLC_83XX_100M_LINK 2
397#define QLC_83XX_1G_LINK 3
398#define QLC_83XX_10G_LINK 4
399#define QLC_83XX_STAT_TX 3
400#define QLC_83XX_STAT_RX 2
401#define QLC_83XX_STAT_MAC 1
402#define QLC_83XX_TX_STAT_REGS 14
403#define QLC_83XX_RX_STAT_REGS 40
52290740 404#define QLC_83XX_MAC_STAT_REGS 94
7f966452
SC		 405
406#define QLC_83XX_GET_FUNC_PRIVILEGE(VAL, FN) (0x3 & ((VAL) >> (FN * 2)))
407#define QLC_83XX_SET_FUNC_OPMODE(VAL, FN) ((VAL) << (FN * 2))
408#define QLC_83XX_DEFAULT_OPMODE 0x55555555
409#define QLC_83XX_PRIVLEGED_FUNC 0x1
410#define QLC_83XX_VIRTUAL_FUNC 0x2
411
412#define QLC_83XX_LB_MAX_FILTERS 2048
413#define QLC_83XX_LB_BUCKET_SIZE 256
414#define QLC_83XX_MINIMUM_VECTOR 3
52e493d0
JK		 415#define QLC_83XX_MAX_MC_COUNT 38
416#define QLC_83XX_MAX_UC_COUNT 4096
7f966452 417
58945e1b 418#define QLC_83XX_PVID_STRIP_CAPABILITY BIT_22
7f966452
SC		 419#define QLC_83XX_GET_FUNC_MODE_FROM_NPAR_INFO(val) (val & 0x80000000)
420#define QLC_83XX_GET_LRO_CAPABILITY(val) (val & 0x20)
421#define QLC_83XX_GET_LSO_CAPABILITY(val) (val & 0x40)
7f966452
SC		 422#define QLC_83XX_GET_HW_LRO_CAPABILITY(val) (val & 0x400)
423#define QLC_83XX_GET_VLAN_ALIGN_CAPABILITY(val) (val & 0x4000)
99e85879 424#define QLC_83XX_GET_FW_LRO_MSS_CAPABILITY(val) (val & 0x20000)
35dafcb0 425#define QLC_83XX_ESWITCH_CAPABILITY BIT_23
02feda17 426#define QLC_83XX_SRIOV_MODE 0x1
7f966452
SC		 427#define QLCNIC_BRDTYPE_83XX_10G 0x0083
428
d865ebb4
SC		 429#define QLC_83XX_FLASH_SPI_STATUS 0x2808E010
430#define QLC_83XX_FLASH_SPI_CONTROL 0x2808E014
431#define QLC_83XX_FLASH_STATUS 0x42100004
432#define QLC_83XX_FLASH_CONTROL 0x42110004
433#define QLC_83XX_FLASH_ADDR 0x42110008
434#define QLC_83XX_FLASH_WRDATA 0x4211000C
435#define QLC_83XX_FLASH_RDDATA 0x42110018
436#define QLC_83XX_FLASH_DIRECT_WINDOW 0x42110030
437#define QLC_83XX_FLASH_DIRECT_DATA(DATA) (0x42150000 | (0x0000FFFF&DATA))
438#define QLC_83XX_FLASH_SECTOR_ERASE_CMD 0xdeadbeef
439#define QLC_83XX_FLASH_WRITE_CMD 0xdacdacda
440#define QLC_83XX_FLASH_BULK_WRITE_CMD 0xcadcadca
441#define QLC_83XX_FLASH_READ_RETRY_COUNT 5000
442#define QLC_83XX_FLASH_STATUS_READY 0x6
a520030e
HM		 443#define QLC_83XX_FLASH_WRITE_MIN 2
444#define QLC_83XX_FLASH_WRITE_MAX 64
d865ebb4
SC		 445#define QLC_83XX_FLASH_STATUS_REG_POLL_DELAY 1
446#define QLC_83XX_ERASE_MODE 1
447#define QLC_83XX_WRITE_MODE 2
448#define QLC_83XX_BULK_WRITE_MODE 3
449#define QLC_83XX_FLASH_FDT_WRITE_DEF_SIG 0xFD0100
450#define QLC_83XX_FLASH_FDT_ERASE_DEF_SIG 0xFD0300
451#define QLC_83XX_FLASH_FDT_READ_MFG_ID_VAL 0xFD009F
452#define QLC_83XX_FLASH_OEM_ERASE_SIG 0xFD03D8
453#define QLC_83XX_FLASH_OEM_WRITE_SIG 0xFD0101
454#define QLC_83XX_FLASH_OEM_READ_SIG 0xFD0005
455#define QLC_83XX_FLASH_ADDR_TEMP_VAL 0x00800000
456#define QLC_83XX_FLASH_ADDR_SECOND_TEMP_VAL 0x00800001
457#define QLC_83XX_FLASH_WRDATA_DEF 0x0
458#define QLC_83XX_FLASH_READ_CTRL 0x3F
459#define QLC_83XX_FLASH_SPI_CTRL 0x4
460#define QLC_83XX_FLASH_FIRST_ERASE_MS_VAL 0x2
461#define QLC_83XX_FLASH_SECOND_ERASE_MS_VAL 0x5
462#define QLC_83XX_FLASH_LAST_ERASE_MS_VAL 0x3D
463#define QLC_83XX_FLASH_FIRST_MS_PATTERN 0x43
464#define QLC_83XX_FLASH_SECOND_MS_PATTERN 0x7F
465#define QLC_83XX_FLASH_LAST_MS_PATTERN 0x7D
466#define QLC_83xx_FLASH_MAX_WAIT_USEC 100
467#define QLC_83XX_FLASH_LOCK_TIMEOUT 10000
468
e5c4e6c6
MC		 469enum qlc_83xx_mbx_cmd_type {
470 QLC_83XX_MBX_CMD_WAIT = 0,
471 QLC_83XX_MBX_CMD_NO_WAIT,
472 QLC_83XX_MBX_CMD_BUSY_WAIT,
473};
474
475enum qlc_83xx_mbx_response_states {
476 QLC_83XX_MBX_RESPONSE_WAIT = 0,
477 QLC_83XX_MBX_RESPONSE_ARRIVED,
478};
479
480#define QLC_83XX_MBX_RESPONSE_FAILED 0x2
481#define QLC_83XX_MBX_RESPONSE_UNKNOWN 0x3
482
7f966452
SC		 483/* Additional registers in 83xx */
484enum qlc_83xx_ext_regs {
485 QLCNIC_GLOBAL_RESET = 0,
486 QLCNIC_WILDCARD,
487 QLCNIC_INFORMANT,
488 QLCNIC_HOST_MBX_CTRL,
489 QLCNIC_FW_MBX_CTRL,
490 QLCNIC_BOOTLOADER_ADDR,
491 QLCNIC_BOOTLOADER_SIZE,
492 QLCNIC_FW_IMAGE_ADDR,
493 QLCNIC_MBX_INTR_ENBL,
494 QLCNIC_DEF_INT_MASK,
495 QLCNIC_DEF_INT_ID,
496 QLC_83XX_IDC_MAJ_VERSION,
497 QLC_83XX_IDC_DEV_STATE,
498 QLC_83XX_IDC_DRV_PRESENCE,
499 QLC_83XX_IDC_DRV_ACK,
500 QLC_83XX_IDC_CTRL,
501 QLC_83XX_IDC_DRV_AUDIT,
502 QLC_83XX_IDC_MIN_VERSION,
503 QLC_83XX_RECOVER_DRV_LOCK,
504 QLC_83XX_IDC_PF_0,
505 QLC_83XX_IDC_PF_1,
506 QLC_83XX_IDC_PF_2,
507 QLC_83XX_IDC_PF_3,
508 QLC_83XX_IDC_PF_4,
509 QLC_83XX_IDC_PF_5,
510 QLC_83XX_IDC_PF_6,
511 QLC_83XX_IDC_PF_7,
512 QLC_83XX_IDC_PF_8,
513 QLC_83XX_IDC_PF_9,
514 QLC_83XX_IDC_PF_10,
515 QLC_83XX_IDC_PF_11,
516 QLC_83XX_IDC_PF_12,
517 QLC_83XX_IDC_PF_13,
518 QLC_83XX_IDC_PF_14,
519 QLC_83XX_IDC_PF_15,
520 QLC_83XX_IDC_DEV_PARTITION_INFO_1,
521 QLC_83XX_IDC_DEV_PARTITION_INFO_2,
522 QLC_83XX_DRV_OP_MODE,
523 QLC_83XX_VNIC_STATE,
524 QLC_83XX_DRV_LOCK,
525 QLC_83XX_DRV_UNLOCK,
526 QLC_83XX_DRV_LOCK_ID,
527 QLC_83XX_ASIC_TEMP,
528};
529
3720bf79 530/* Initialize/Stop NIC command bit definitions */
9b0fff2a 531#define QLC_REGISTER_LB_IDC BIT_0
2b3d7b75
SS		 532#define QLC_REGISTER_DCB_AEN BIT_1
533#define QLC_83XX_MULTI_TENANCY_INFO BIT_29
9b0fff2a 534#define QLC_INIT_FW_RESOURCES BIT_31
3720bf79 535
7f966452
SC		 536/* 83xx funcitons */
537int qlcnic_83xx_get_fw_version(struct qlcnic_adapter *);
e5c4e6c6 538int qlcnic_83xx_issue_cmd(struct qlcnic_adapter *, struct qlcnic_cmd_args *);
34e8c406 539int qlcnic_83xx_setup_intr(struct qlcnic_adapter *);
7f966452
SC		 540void qlcnic_83xx_get_func_no(struct qlcnic_adapter *);
541int qlcnic_83xx_cam_lock(struct qlcnic_adapter *);
542void qlcnic_83xx_cam_unlock(struct qlcnic_adapter *);
543int qlcnic_send_ctrl_op(struct qlcnic_adapter *, struct qlcnic_cmd_args *, u32);
319ecf12
SC		 544void qlcnic_83xx_add_sysfs(struct qlcnic_adapter *);
545void qlcnic_83xx_remove_sysfs(struct qlcnic_adapter *);
7f966452
SC		 546void qlcnic_83xx_write_crb(struct qlcnic_adapter *, char *, loff_t, size_t);
547void qlcnic_83xx_read_crb(struct qlcnic_adapter *, char *, loff_t, size_t);
4bd8e738 548int qlcnic_83xx_rd_reg_indirect(struct qlcnic_adapter *, ulong, int *);
7f966452 549int qlcnic_83xx_wrt_reg_indirect(struct qlcnic_adapter *, ulong, u32);
7f966452 550int qlcnic_83xx_nic_set_promisc(struct qlcnic_adapter *, u32);
7f966452
SC		 551int qlcnic_83xx_config_hw_lro(struct qlcnic_adapter *, int);
552int qlcnic_83xx_config_rss(struct qlcnic_adapter *, int);
f80bc8fe 553void qlcnic_83xx_change_l2_filter(struct qlcnic_adapter *, u64 *, u16);
7f966452
SC		 554int qlcnic_83xx_get_pci_info(struct qlcnic_adapter *, struct qlcnic_pci_info *);
555int qlcnic_83xx_set_nic_info(struct qlcnic_adapter *, struct qlcnic_info *);
9b0fff2a 556void qlcnic_83xx_initialize_nic(struct qlcnic_adapter *, int);
7f966452 557
4be41e92
SC		 558int qlcnic_83xx_napi_add(struct qlcnic_adapter *, struct net_device *);
559void qlcnic_83xx_napi_del(struct qlcnic_adapter *);
560void qlcnic_83xx_napi_enable(struct qlcnic_adapter *);
561void qlcnic_83xx_napi_disable(struct qlcnic_adapter *);
319ecf12 562int qlcnic_83xx_config_led(struct qlcnic_adapter *, u32, u32);
8d37ba02 563int qlcnic_ind_wr(struct qlcnic_adapter *, u32, u32);
7f966452 564int qlcnic_ind_rd(struct qlcnic_adapter *, u32);
7f966452
SC		 565int qlcnic_83xx_create_rx_ctx(struct qlcnic_adapter *);
566int qlcnic_83xx_create_tx_ctx(struct qlcnic_adapter *,
567 struct qlcnic_host_tx_ring *, int);
7cb03b23
RB		 568void qlcnic_83xx_del_rx_ctx(struct qlcnic_adapter *);
569void qlcnic_83xx_del_tx_ctx(struct qlcnic_adapter *,
570 struct qlcnic_host_tx_ring *);
7f966452
SC		 571int qlcnic_83xx_get_nic_info(struct qlcnic_adapter *, struct qlcnic_info *, u8);
572int qlcnic_83xx_setup_link_event(struct qlcnic_adapter *, int);
573void qlcnic_83xx_process_rcv_ring_diag(struct qlcnic_host_sds_ring *);
574int qlcnic_83xx_config_intrpt(struct qlcnic_adapter *, bool);
f80bc8fe 575int qlcnic_83xx_sre_macaddr_change(struct qlcnic_adapter *, u8 *, u16, u8);
07a251c8 576int qlcnic_83xx_get_mac_address(struct qlcnic_adapter *, u8 *, u8);
7f966452
SC		 577int qlcnic_83xx_alloc_mbx_args(struct qlcnic_cmd_args *,
578 struct qlcnic_adapter *, u32);
579void qlcnic_free_mbx_args(struct qlcnic_cmd_args *);
580void qlcnic_set_npar_data(struct qlcnic_adapter *, const struct qlcnic_info *,
581 struct qlcnic_info *);
a514722a
HM		 582int qlcnic_83xx_config_intr_coal(struct qlcnic_adapter *,
583 struct ethtool_coalesce *);
584int qlcnic_83xx_set_rx_tx_intr_coal(struct qlcnic_adapter *);
7f966452 585int qlcnic_83xx_get_port_info(struct qlcnic_adapter *);
e5c4e6c6 586void qlcnic_83xx_enable_mbx_interrupt(struct qlcnic_adapter *);
f036e4f4 587void qlcnic_83xx_disable_mbx_intr(struct qlcnic_adapter *);
7f966452 588irqreturn_t qlcnic_83xx_clear_legacy_intr(struct qlcnic_adapter *);
ac166700 589irqreturn_t qlcnic_83xx_intr(int, void *);
7f966452 590irqreturn_t qlcnic_83xx_tmp_intr(int, void *);
7f966452
SC		 591void qlcnic_83xx_check_vf(struct qlcnic_adapter *,
592 const struct pci_device_id *);
7f966452
SC		 593int qlcnic_83xx_config_default_opmode(struct qlcnic_adapter *);
594int qlcnic_83xx_setup_mbx_intr(struct qlcnic_adapter *);
595void qlcnic_83xx_free_mbx_intr(struct qlcnic_adapter *);
596void qlcnic_83xx_register_map(struct qlcnic_hardware_context *);
597void qlcnic_83xx_idc_aen_work(struct work_struct *);
598void qlcnic_83xx_config_ipaddr(struct qlcnic_adapter *, __be32, int);
d865ebb4
SC		 599
600int qlcnic_83xx_erase_flash_sector(struct qlcnic_adapter *, u32);
601int qlcnic_83xx_flash_bulk_write(struct qlcnic_adapter *, u32, u32 *, int);
602int qlcnic_83xx_flash_write32(struct qlcnic_adapter *, u32, u32 *);
603int qlcnic_83xx_lock_flash(struct qlcnic_adapter *);
604void qlcnic_83xx_unlock_flash(struct qlcnic_adapter *);
605int qlcnic_83xx_save_flash_status(struct qlcnic_adapter *);
606int qlcnic_83xx_restore_flash_status(struct qlcnic_adapter *, int);
607int qlcnic_83xx_read_flash_mfg_id(struct qlcnic_adapter *);
608int qlcnic_83xx_read_flash_descriptor_table(struct qlcnic_adapter *);
629263ac
SC		 609int qlcnic_83xx_flash_read32(struct qlcnic_adapter *, u32, u8 *, int);
610int qlcnic_83xx_lockless_flash_read32(struct qlcnic_adapter *,
611 u32, u8 *, int);
f8468331 612int qlcnic_83xx_init(struct qlcnic_adapter *, int);
629263ac 613int qlcnic_83xx_idc_ready_state_entry(struct qlcnic_adapter *);
629263ac
SC		 614void qlcnic_83xx_idc_poll_dev_state(struct work_struct *);
615void qlcnic_83xx_idc_exit(struct qlcnic_adapter *);
616void qlcnic_83xx_idc_request_reset(struct qlcnic_adapter *, u32);
617int qlcnic_83xx_lock_driver(struct qlcnic_adapter *);
618void qlcnic_83xx_unlock_driver(struct qlcnic_adapter *);
619int qlcnic_83xx_set_default_offload_settings(struct qlcnic_adapter *);
d71170fb 620int qlcnic_83xx_idc_vnic_pf_entry(struct qlcnic_adapter *);
d71170fb
SC		 621int qlcnic_83xx_disable_vnic_mode(struct qlcnic_adapter *, int);
622int qlcnic_83xx_config_vnic_opmode(struct qlcnic_adapter *);
623int qlcnic_83xx_get_vnic_vport_info(struct qlcnic_adapter *,
624 struct qlcnic_info *, u8);
625int qlcnic_83xx_get_vnic_pf_info(struct qlcnic_adapter *, struct qlcnic_info *);
4c776aad 626int qlcnic_83xx_set_port_eswitch_status(struct qlcnic_adapter *, int, int *);
4e60ac46
SC		 627
628void qlcnic_83xx_get_minidump_template(struct qlcnic_adapter *);
7e38d04b 629void qlcnic_83xx_get_stats(struct qlcnic_adapter *adapter, u64 *data);
d01a6d3c 630int qlcnic_83xx_extend_md_capab(struct qlcnic_adapter *);
49cef10f
PR		 631int qlcnic_83xx_get_link_ksettings(struct qlcnic_adapter *adapter,
632 struct ethtool_link_ksettings *ecmd);
633int qlcnic_83xx_set_link_ksettings(struct qlcnic_adapter *adapter,
634 const struct ethtool_link_ksettings *ecmd);
7e38d04b
SC		 635void qlcnic_83xx_get_pauseparam(struct qlcnic_adapter *,
636 struct ethtool_pauseparam *);
637int qlcnic_83xx_set_pauseparam(struct qlcnic_adapter *,
638 struct ethtool_pauseparam *);
639int qlcnic_83xx_test_link(struct qlcnic_adapter *);
f9c3fe2f 640void qlcnic_83xx_get_port_type(struct qlcnic_adapter *adapter);
7e38d04b
SC		 641int qlcnic_83xx_reg_test(struct qlcnic_adapter *);
642int qlcnic_83xx_get_regs_len(struct qlcnic_adapter *);
643int qlcnic_83xx_get_registers(struct qlcnic_adapter *, u32 *);
ba4468db 644int qlcnic_83xx_loopback_test(struct net_device *, u8);
58ead415 645int qlcnic_83xx_interrupt_test(struct net_device *);
d16951d9 646int qlcnic_83xx_set_led(struct net_device *, enum ethtool_phys_id_state);
7e38d04b 647int qlcnic_83xx_flash_test(struct qlcnic_adapter *);
a520030e
HM		 648int qlcnic_83xx_enable_flash_write(struct qlcnic_adapter *);
649int qlcnic_83xx_disable_flash_write(struct qlcnic_adapter *);
7ed3ce48
RB		 650void qlcnic_83xx_enable_mbx_poll(struct qlcnic_adapter *);
651void qlcnic_83xx_disable_mbx_poll(struct qlcnic_adapter *);
486a5bc7
RB		 652int qlcnic_83xx_idc_init(struct qlcnic_adapter *);
653int qlcnic_83xx_idc_reattach_driver(struct qlcnic_adapter *);
654int qlcnic_83xx_set_vnic_opmode(struct qlcnic_adapter *);
655int qlcnic_83xx_check_vnic_state(struct qlcnic_adapter *);
9ce226fa
PP		 656void qlcnic_83xx_aer_stop_poll_work(struct qlcnic_adapter *);
657int qlcnic_83xx_aer_reset(struct qlcnic_adapter *);
658void qlcnic_83xx_aer_start_poll_work(struct qlcnic_adapter *);
225837a0
SS		 659u32 qlcnic_83xx_get_saved_state(void *, u32);
660void qlcnic_83xx_set_saved_state(void *, u32, u32);
661void qlcnic_83xx_cache_tmpl_hdr_values(struct qlcnic_fw_dump *);
662u32 qlcnic_83xx_get_cap_size(void *, int);
663void qlcnic_83xx_set_sys_info(void *, int, u32);
664void qlcnic_83xx_store_cap_mask(void *, u32);
8d37ba02 665int qlcnic_ms_mem_write128(struct qlcnic_adapter *, u64, u32 *, u32);
7f966452 666#endif
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