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Merge branch 'for-davem' of git://git.kernel.org/pub/scm/linux/kernel/git/bwh/sfc...
[mirror_ubuntu-zesty-kernel.git] / drivers / net / ethernet / qlogic / qlcnic / qlcnic_83xx_init.c
CommitLineData
577ae39d
JK		 1/*
2 * QLogic qlcnic NIC Driver
3 * Copyright (c) 2009-2013 QLogic Corporation
4 *
5 * See LICENSE.qlcnic for copyright and licensing details.
6 */
7
f8468331 8#include "qlcnic_sriov.h"
629263ac
SC		 9#include "qlcnic.h"
10#include "qlcnic_hw.h"
11
81d0aeb0
SC		 12/* Reset template definitions */
13#define QLC_83XX_RESTART_TEMPLATE_SIZE 0x2000
14#define QLC_83XX_RESET_TEMPLATE_ADDR 0x4F0000
15#define QLC_83XX_RESET_SEQ_VERSION 0x0101
16
17#define QLC_83XX_OPCODE_NOP 0x0000
18#define QLC_83XX_OPCODE_WRITE_LIST 0x0001
19#define QLC_83XX_OPCODE_READ_WRITE_LIST 0x0002
20#define QLC_83XX_OPCODE_POLL_LIST 0x0004
21#define QLC_83XX_OPCODE_POLL_WRITE_LIST 0x0008
22#define QLC_83XX_OPCODE_READ_MODIFY_WRITE 0x0010
23#define QLC_83XX_OPCODE_SEQ_PAUSE 0x0020
24#define QLC_83XX_OPCODE_SEQ_END 0x0040
25#define QLC_83XX_OPCODE_TMPL_END 0x0080
26#define QLC_83XX_OPCODE_POLL_READ_LIST 0x0100
27
c0d79cd0
MC		 28/* EPORT control registers */
29#define QLC_83XX_RESET_CONTROL 0x28084E50
30#define QLC_83XX_RESET_REG 0x28084E60
31#define QLC_83XX_RESET_PORT0 0x28084E70
32#define QLC_83XX_RESET_PORT1 0x28084E80
33#define QLC_83XX_RESET_PORT2 0x28084E90
34#define QLC_83XX_RESET_PORT3 0x28084EA0
35#define QLC_83XX_RESET_SRESHIM 0x28084EB0
36#define QLC_83XX_RESET_EPGSHIM 0x28084EC0
37#define QLC_83XX_RESET_ETHERPCS 0x28084ED0
38
629263ac 39static int qlcnic_83xx_init_default_driver(struct qlcnic_adapter *adapter);
629263ac
SC		 40static int qlcnic_83xx_check_heartbeat(struct qlcnic_adapter *p_dev);
41static int qlcnic_83xx_restart_hw(struct qlcnic_adapter *adapter);
42
81d0aeb0
SC		 43/* Template header */
44struct qlc_83xx_reset_hdr {
a96227e6 45#if defined(__LITTLE_ENDIAN)
81d0aeb0
SC		 46 u16 version;
47 u16 signature;
48 u16 size;
49 u16 entries;
50 u16 hdr_size;
51 u16 checksum;
52 u16 init_offset;
53 u16 start_offset;
a96227e6
SS		 54#elif defined(__BIG_ENDIAN)
55 u16 signature;
56 u16 version;
57 u16 entries;
58 u16 size;
59 u16 checksum;
60 u16 hdr_size;
61 u16 start_offset;
62 u16 init_offset;
63#endif
81d0aeb0
SC		 64} __packed;
65
66/* Command entry header. */
67struct qlc_83xx_entry_hdr {
a96227e6
SS		 68#if defined(__LITTLE_ENDIAN)
69 u16 cmd;
70 u16 size;
71 u16 count;
72 u16 delay;
73#elif defined(__BIG_ENDIAN)
74 u16 size;
75 u16 cmd;
76 u16 delay;
77 u16 count;
78#endif
81d0aeb0
SC		 79} __packed;
80
81/* Generic poll command */
82struct qlc_83xx_poll {
83 u32 mask;
84 u32 status;
85} __packed;
86
87/* Read modify write command */
88struct qlc_83xx_rmw {
89 u32 mask;
90 u32 xor_value;
91 u32 or_value;
a96227e6 92#if defined(__LITTLE_ENDIAN)
81d0aeb0
SC		 93 u8 shl;
94 u8 shr;
95 u8 index_a;
96 u8 rsvd;
a96227e6
SS		 97#elif defined(__BIG_ENDIAN)
98 u8 rsvd;
99 u8 index_a;
100 u8 shr;
101 u8 shl;
102#endif
81d0aeb0
SC		 103} __packed;
104
105/* Generic command with 2 DWORD */
106struct qlc_83xx_entry {
107 u32 arg1;
108 u32 arg2;
109} __packed;
110
111/* Generic command with 4 DWORD */
112struct qlc_83xx_quad_entry {
113 u32 dr_addr;
114 u32 dr_value;
115 u32 ar_addr;
116 u32 ar_value;
117} __packed;
629263ac
SC		 118static const char *const qlc_83xx_idc_states[] = {
119 "Unknown",
120 "Cold",
121 "Init",
122 "Ready",
123 "Need Reset",
124 "Need Quiesce",
125 "Failed",
126 "Quiesce"
127};
128
629263ac
SC		 129static int
130qlcnic_83xx_idc_check_driver_presence_reg(struct qlcnic_adapter *adapter)
131{
132 u32 val;
133
134 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
135 if ((val & 0xFFFF))
136 return 1;
137 else
138 return 0;
139}
140
141static void qlcnic_83xx_idc_log_state_history(struct qlcnic_adapter *adapter)
142{
143 u32 cur, prev;
144 cur = adapter->ahw->idc.curr_state;
145 prev = adapter->ahw->idc.prev_state;
146
147 dev_info(&adapter->pdev->dev,
148 "current state = %s, prev state = %s\n",
149 adapter->ahw->idc.name[cur],
150 adapter->ahw->idc.name[prev]);
151}
152
153static int qlcnic_83xx_idc_update_audit_reg(struct qlcnic_adapter *adapter,
154 u8 mode, int lock)
155{
156 u32 val;
157 int seconds;
158
159 if (lock) {
160 if (qlcnic_83xx_lock_driver(adapter))
161 return -EBUSY;
162 }
163
f036e4f4
RB		 164 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT);
165 val |= (adapter->portnum & 0xf);
629263ac
SC		 166 val |= mode << 7;
167 if (mode)
168 seconds = jiffies / HZ - adapter->ahw->idc.sec_counter;
169 else
170 seconds = jiffies / HZ;
171
172 val |= seconds << 8;
173 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT, val);
174 adapter->ahw->idc.sec_counter = jiffies / HZ;
175
176 if (lock)
177 qlcnic_83xx_unlock_driver(adapter);
178
179 return 0;
180}
181
182static void qlcnic_83xx_idc_update_minor_version(struct qlcnic_adapter *adapter)
183{
184 u32 val;
185
186 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MIN_VERSION);
187 val = val & ~(0x3 << (adapter->portnum * 2));
188 val = val | (QLC_83XX_IDC_MINOR_VERSION << (adapter->portnum * 2));
189 QLCWRX(adapter->ahw, QLC_83XX_IDC_MIN_VERSION, val);
190}
191
192static int qlcnic_83xx_idc_update_major_version(struct qlcnic_adapter *adapter,
193 int lock)
194{
195 u32 val;
196
197 if (lock) {
198 if (qlcnic_83xx_lock_driver(adapter))
199 return -EBUSY;
200 }
201
202 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION);
203 val = val & ~0xFF;
204 val = val | QLC_83XX_IDC_MAJOR_VERSION;
205 QLCWRX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION, val);
206
207 if (lock)
208 qlcnic_83xx_unlock_driver(adapter);
209
210 return 0;
211}
212
213static int
214qlcnic_83xx_idc_update_drv_presence_reg(struct qlcnic_adapter *adapter,
215 int status, int lock)
216{
217 u32 val;
218
219 if (lock) {
220 if (qlcnic_83xx_lock_driver(adapter))
221 return -EBUSY;
222 }
223
224 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
225
226 if (status)
227 val = val | (1 << adapter->portnum);
228 else
229 val = val & ~(1 << adapter->portnum);
230
231 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val);
232 qlcnic_83xx_idc_update_minor_version(adapter);
233
234 if (lock)
235 qlcnic_83xx_unlock_driver(adapter);
236
237 return 0;
238}
239
240static int qlcnic_83xx_idc_check_major_version(struct qlcnic_adapter *adapter)
241{
242 u32 val;
243 u8 version;
244
245 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION);
246 version = val & 0xFF;
247
248 if (version != QLC_83XX_IDC_MAJOR_VERSION) {
249 dev_info(&adapter->pdev->dev,
250 "%s:mismatch. version 0x%x, expected version 0x%x\n",
251 __func__, version, QLC_83XX_IDC_MAJOR_VERSION);
252 return -EIO;
253 }
254
255 return 0;
256}
257
258static int qlcnic_83xx_idc_clear_registers(struct qlcnic_adapter *adapter,
259 int lock)
260{
261 u32 val;
262
263 if (lock) {
264 if (qlcnic_83xx_lock_driver(adapter))
265 return -EBUSY;
266 }
267
268 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_ACK, 0);
269 /* Clear gracefull reset bit */
270 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
271 val &= ~QLC_83XX_IDC_GRACEFULL_RESET;
272 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
273
274 if (lock)
275 qlcnic_83xx_unlock_driver(adapter);
276
277 return 0;
278}
279
280static int qlcnic_83xx_idc_update_drv_ack_reg(struct qlcnic_adapter *adapter,
281 int flag, int lock)
282{
283 u32 val;
284
285 if (lock) {
286 if (qlcnic_83xx_lock_driver(adapter))
287 return -EBUSY;
288 }
289
290 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_ACK);
291 if (flag)
292 val = val | (1 << adapter->portnum);
293 else
294 val = val & ~(1 << adapter->portnum);
295 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_ACK, val);
296
297 if (lock)
298 qlcnic_83xx_unlock_driver(adapter);
299
300 return 0;
301}
302
303static int qlcnic_83xx_idc_check_timeout(struct qlcnic_adapter *adapter,
304 int time_limit)
305{
306 u64 seconds;
307
308 seconds = jiffies / HZ - adapter->ahw->idc.sec_counter;
309 if (seconds <= time_limit)
310 return 0;
311 else
312 return -EBUSY;
313}
314
315/**
316 * qlcnic_83xx_idc_check_reset_ack_reg
317 *
318 * @adapter: adapter structure
319 *
320 * Check ACK wait limit and clear the functions which failed to ACK
321 *
322 * Return 0 if all functions have acknowledged the reset request.
323 **/
324static int qlcnic_83xx_idc_check_reset_ack_reg(struct qlcnic_adapter *adapter)
325{
326 int timeout;
327 u32 ack, presence, val;
328
329 timeout = QLC_83XX_IDC_RESET_TIMEOUT_SECS;
330 ack = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_ACK);
331 presence = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
332 dev_info(&adapter->pdev->dev,
333 "%s: ack = 0x%x, presence = 0x%x\n", __func__, ack, presence);
334 if (!((ack & presence) == presence)) {
335 if (qlcnic_83xx_idc_check_timeout(adapter, timeout)) {
336 /* Clear functions which failed to ACK */
337 dev_info(&adapter->pdev->dev,
338 "%s: ACK wait exceeds time limit\n", __func__);
339 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
340 val = val & ~(ack ^ presence);
341 if (qlcnic_83xx_lock_driver(adapter))
342 return -EBUSY;
343 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val);
344 dev_info(&adapter->pdev->dev,
345 "%s: updated drv presence reg = 0x%x\n",
346 __func__, val);
347 qlcnic_83xx_unlock_driver(adapter);
348 return 0;
349
350 } else {
351 return 1;
352 }
353 } else {
354 dev_info(&adapter->pdev->dev,
355 "%s: Reset ACK received from all functions\n",
356 __func__);
357 return 0;
358 }
359}
360
361/**
362 * qlcnic_83xx_idc_tx_soft_reset
363 *
364 * @adapter: adapter structure
365 *
366 * Handle context deletion and recreation request from transmit routine
367 *
368 * Returns -EBUSY or Success (0)
369 *
370 **/
371static int qlcnic_83xx_idc_tx_soft_reset(struct qlcnic_adapter *adapter)
372{
373 struct net_device *netdev = adapter->netdev;
374
375 if (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))
376 return -EBUSY;
377
378 netif_device_detach(netdev);
379 qlcnic_down(adapter, netdev);
380 qlcnic_up(adapter, netdev);
381 netif_device_attach(netdev);
382 clear_bit(__QLCNIC_RESETTING, &adapter->state);
383 dev_err(&adapter->pdev->dev, "%s:\n", __func__);
384
629263ac
SC		 385 return 0;
386}
387
388/**
389 * qlcnic_83xx_idc_detach_driver
390 *
391 * @adapter: adapter structure
392 * Detach net interface, stop TX and cleanup resources before the HW reset.
393 * Returns: None
394 *
395 **/
396static void qlcnic_83xx_idc_detach_driver(struct qlcnic_adapter *adapter)
397{
398 int i;
399 struct net_device *netdev = adapter->netdev;
400
401 netif_device_detach(netdev);
068a8d19 402 qlcnic_83xx_detach_mailbox_work(adapter);
f036e4f4 403
629263ac 404 /* Disable mailbox interrupt */
f036e4f4 405 qlcnic_83xx_disable_mbx_intr(adapter);
629263ac
SC		 406 qlcnic_down(adapter, netdev);
407 for (i = 0; i < adapter->ahw->num_msix; i++) {
408 adapter->ahw->intr_tbl[i].id = i;
409 adapter->ahw->intr_tbl[i].enabled = 0;
410 adapter->ahw->intr_tbl[i].src = 0;
411 }
f036e4f4
RB		 412
413 if (qlcnic_sriov_pf_check(adapter))
414 qlcnic_sriov_pf_reset(adapter);
629263ac
SC		 415}
416
417/**
418 * qlcnic_83xx_idc_attach_driver
419 *
420 * @adapter: adapter structure
421 *
422 * Re-attach and re-enable net interface
423 * Returns: None
424 *
425 **/
426static void qlcnic_83xx_idc_attach_driver(struct qlcnic_adapter *adapter)
427{
428 struct net_device *netdev = adapter->netdev;
429
430 if (netif_running(netdev)) {
431 if (qlcnic_up(adapter, netdev))
432 goto done;
433 qlcnic_restore_indev_addr(netdev, NETDEV_UP);
434 }
435done:
436 netif_device_attach(netdev);
629263ac
SC		 437}
438
439static int qlcnic_83xx_idc_enter_failed_state(struct qlcnic_adapter *adapter,
440 int lock)
441{
442 if (lock) {
443 if (qlcnic_83xx_lock_driver(adapter))
444 return -EBUSY;
445 }
446
447 qlcnic_83xx_idc_clear_registers(adapter, 0);
448 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_FAILED);
449 if (lock)
450 qlcnic_83xx_unlock_driver(adapter);
451
452 qlcnic_83xx_idc_log_state_history(adapter);
453 dev_info(&adapter->pdev->dev, "Device will enter failed state\n");
454
455 return 0;
456}
457
458static int qlcnic_83xx_idc_enter_init_state(struct qlcnic_adapter *adapter,
459 int lock)
460{
461 if (lock) {
462 if (qlcnic_83xx_lock_driver(adapter))
463 return -EBUSY;
464 }
465
466 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_INIT);
467
468 if (lock)
469 qlcnic_83xx_unlock_driver(adapter);
470
471 return 0;
472}
473
474static int qlcnic_83xx_idc_enter_need_quiesce(struct qlcnic_adapter *adapter,
475 int lock)
476{
477 if (lock) {
478 if (qlcnic_83xx_lock_driver(adapter))
479 return -EBUSY;
480 }
481
482 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE,
483 QLC_83XX_IDC_DEV_NEED_QUISCENT);
484
485 if (lock)
486 qlcnic_83xx_unlock_driver(adapter);
487
488 return 0;
489}
490
491static int
492qlcnic_83xx_idc_enter_need_reset_state(struct qlcnic_adapter *adapter, int lock)
493{
494 if (lock) {
495 if (qlcnic_83xx_lock_driver(adapter))
496 return -EBUSY;
497 }
498
499 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE,
500 QLC_83XX_IDC_DEV_NEED_RESET);
501
502 if (lock)
503 qlcnic_83xx_unlock_driver(adapter);
504
505 return 0;
506}
507
508static int qlcnic_83xx_idc_enter_ready_state(struct qlcnic_adapter *adapter,
509 int lock)
510{
511 if (lock) {
512 if (qlcnic_83xx_lock_driver(adapter))
513 return -EBUSY;
514 }
515
516 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_READY);
517 if (lock)
518 qlcnic_83xx_unlock_driver(adapter);
519
520 return 0;
521}
522
523/**
524 * qlcnic_83xx_idc_find_reset_owner_id
525 *
526 * @adapter: adapter structure
527 *
528 * NIC gets precedence over ISCSI and ISCSI has precedence over FCOE.
529 * Within the same class, function with lowest PCI ID assumes ownership
530 *
531 * Returns: reset owner id or failure indication (-EIO)
532 *
533 **/
534static int qlcnic_83xx_idc_find_reset_owner_id(struct qlcnic_adapter *adapter)
535{
536 u32 reg, reg1, reg2, i, j, owner, class;
537
538 reg1 = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_PARTITION_INFO_1);
539 reg2 = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_PARTITION_INFO_2);
540 owner = QLCNIC_TYPE_NIC;
541 i = 0;
542 j = 0;
543 reg = reg1;
544
545 do {
546 class = (((reg & (0xF << j * 4)) >> j * 4) & 0x3);
547 if (class == owner)
548 break;
549 if (i == (QLC_83XX_IDC_MAX_FUNC_PER_PARTITION_INFO - 1)) {
550 reg = reg2;
551 j = 0;
552 } else {
553 j++;
554 }
555
556 if (i == (QLC_83XX_IDC_MAX_CNA_FUNCTIONS - 1)) {
557 if (owner == QLCNIC_TYPE_NIC)
558 owner = QLCNIC_TYPE_ISCSI;
559 else if (owner == QLCNIC_TYPE_ISCSI)
560 owner = QLCNIC_TYPE_FCOE;
561 else if (owner == QLCNIC_TYPE_FCOE)
562 return -EIO;
563 reg = reg1;
564 j = 0;
565 i = 0;
566 }
567 } while (i++ < QLC_83XX_IDC_MAX_CNA_FUNCTIONS);
568
569 return i;
570}
571
572static int qlcnic_83xx_idc_restart_hw(struct qlcnic_adapter *adapter, int lock)
573{
574 int ret = 0;
575
576 ret = qlcnic_83xx_restart_hw(adapter);
577
578 if (ret) {
579 qlcnic_83xx_idc_enter_failed_state(adapter, lock);
580 } else {
581 qlcnic_83xx_idc_clear_registers(adapter, lock);
582 ret = qlcnic_83xx_idc_enter_ready_state(adapter, lock);
583 }
584
585 return ret;
586}
587
588static int qlcnic_83xx_idc_check_fan_failure(struct qlcnic_adapter *adapter)
589{
590 u32 status;
591
592 status = QLC_SHARED_REG_RD32(adapter, QLCNIC_PEG_HALT_STATUS1);
593
594 if (status & QLCNIC_RCODE_FATAL_ERROR) {
595 dev_err(&adapter->pdev->dev,
596 "peg halt status1=0x%x\n", status);
597 if (QLCNIC_FWERROR_CODE(status) == QLCNIC_FWERROR_FAN_FAILURE) {
598 dev_err(&adapter->pdev->dev,
599 "On board active cooling fan failed. "
600 "Device has been halted.\n");
601 dev_err(&adapter->pdev->dev,
602 "Replace the adapter.\n");
603 return -EIO;
604 }
605 }
606
607 return 0;
608}
609
486a5bc7 610int qlcnic_83xx_idc_reattach_driver(struct qlcnic_adapter *adapter)
629263ac 611{
f036e4f4
RB		 612 int err;
613
068a8d19
MC		 614 qlcnic_83xx_reinit_mbx_work(adapter->ahw->mailbox);
615 qlcnic_83xx_enable_mbx_interrupt(adapter);
616
d5fcff04
HM		 617 /* register for NIC IDC AEN Events */
618 qlcnic_83xx_register_nic_idc_func(adapter, 1);
619
f036e4f4
RB		 620 err = qlcnic_sriov_pf_reinit(adapter);
621 if (err)
622 return err;
623
e5c4e6c6 624 qlcnic_83xx_enable_mbx_interrupt(adapter);
629263ac
SC		 625
626 if (qlcnic_83xx_configure_opmode(adapter)) {
627 qlcnic_83xx_idc_enter_failed_state(adapter, 1);
628 return -EIO;
629 }
630
631 if (adapter->nic_ops->init_driver(adapter)) {
632 qlcnic_83xx_idc_enter_failed_state(adapter, 1);
633 return -EIO;
634 }
635
24866d15
HM		 636 if (adapter->portnum == 0)
637 qlcnic_set_drv_version(adapter);
629263ac
SC		 638 qlcnic_83xx_idc_attach_driver(adapter);
639
640 return 0;
641}
642
643static void qlcnic_83xx_idc_update_idc_params(struct qlcnic_adapter *adapter)
644{
536faa61
SC		 645 struct qlcnic_hardware_context *ahw = adapter->ahw;
646
629263ac 647 qlcnic_83xx_idc_update_drv_presence_reg(adapter, 1, 1);
629263ac
SC		 648 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
649 set_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
536faa61
SC		 650
651 ahw->idc.quiesce_req = 0;
652 ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY;
653 ahw->idc.err_code = 0;
654 ahw->idc.collect_dump = 0;
655 ahw->reset_context = 0;
656 adapter->tx_timeo_cnt = 0;
099907fa 657 ahw->idc.delay_reset = 0;
536faa61
SC		 658
659 clear_bit(__QLCNIC_RESETTING, &adapter->state);
629263ac
SC		 660}
661
662/**
663 * qlcnic_83xx_idc_ready_state_entry
664 *
665 * @adapter: adapter structure
666 *
667 * Perform ready state initialization, this routine will get invoked only
668 * once from READY state.
669 *
670 * Returns: Error code or Success(0)
671 *
672 **/
673int qlcnic_83xx_idc_ready_state_entry(struct qlcnic_adapter *adapter)
674{
675 struct qlcnic_hardware_context *ahw = adapter->ahw;
676
677 if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_READY) {
678 qlcnic_83xx_idc_update_idc_params(adapter);
679 /* Re-attach the device if required */
680 if ((ahw->idc.prev_state == QLC_83XX_IDC_DEV_NEED_RESET) ||
681 (ahw->idc.prev_state == QLC_83XX_IDC_DEV_INIT)) {
682 if (qlcnic_83xx_idc_reattach_driver(adapter))
683 return -EIO;
684 }
685 }
686
687 return 0;
688}
689
d71170fb
SC		 690/**
691 * qlcnic_83xx_idc_vnic_pf_entry
692 *
693 * @adapter: adapter structure
694 *
695 * Ensure vNIC mode privileged function starts only after vNIC mode is
696 * enabled by management function.
697 * If vNIC mode is ready, start initialization.
698 *
699 * Returns: -EIO or 0
700 *
701 **/
702int qlcnic_83xx_idc_vnic_pf_entry(struct qlcnic_adapter *adapter)
703{
704 u32 state;
705 struct qlcnic_hardware_context *ahw = adapter->ahw;
706
707 /* Privileged function waits till mgmt function enables VNIC mode */
708 state = QLCRDX(adapter->ahw, QLC_83XX_VNIC_STATE);
709 if (state != QLCNIC_DEV_NPAR_OPER) {
710 if (!ahw->idc.vnic_wait_limit--) {
711 qlcnic_83xx_idc_enter_failed_state(adapter, 1);
712 return -EIO;
713 }
714 dev_info(&adapter->pdev->dev, "vNIC mode disabled\n");
715 return -EIO;
716
717 } else {
718 /* Perform one time initialization from ready state */
719 if (ahw->idc.vnic_state != QLCNIC_DEV_NPAR_OPER) {
720 qlcnic_83xx_idc_update_idc_params(adapter);
721
722 /* If the previous state is UNKNOWN, device will be
723 already attached properly by Init routine*/
724 if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_UNKNOWN) {
725 if (qlcnic_83xx_idc_reattach_driver(adapter))
726 return -EIO;
727 }
728 adapter->ahw->idc.vnic_state = QLCNIC_DEV_NPAR_OPER;
729 dev_info(&adapter->pdev->dev, "vNIC mode enabled\n");
730 }
731 }
732
733 return 0;
734}
735
629263ac
SC		 736static int qlcnic_83xx_idc_unknown_state(struct qlcnic_adapter *adapter)
737{
738 adapter->ahw->idc.err_code = -EIO;
739 dev_err(&adapter->pdev->dev,
740 "%s: Device in unknown state\n", __func__);
741 return 0;
742}
743
744/**
745 * qlcnic_83xx_idc_cold_state
746 *
747 * @adapter: adapter structure
748 *
749 * If HW is up and running device will enter READY state.
750 * If firmware image from host needs to be loaded, device is
751 * forced to start with the file firmware image.
752 *
753 * Returns: Error code or Success(0)
754 *
755 **/
756static int qlcnic_83xx_idc_cold_state_handler(struct qlcnic_adapter *adapter)
757{
758 qlcnic_83xx_idc_update_drv_presence_reg(adapter, 1, 0);
759 qlcnic_83xx_idc_update_audit_reg(adapter, 1, 0);
760
761 if (qlcnic_load_fw_file) {
762 qlcnic_83xx_idc_restart_hw(adapter, 0);
763 } else {
764 if (qlcnic_83xx_check_hw_status(adapter)) {
765 qlcnic_83xx_idc_enter_failed_state(adapter, 0);
766 return -EIO;
767 } else {
768 qlcnic_83xx_idc_enter_ready_state(adapter, 0);
769 }
770 }
771 return 0;
772}
773
774/**
775 * qlcnic_83xx_idc_init_state
776 *
777 * @adapter: adapter structure
778 *
779 * Reset owner will restart the device from this state.
780 * Device will enter failed state if it remains
781 * in this state for more than DEV_INIT time limit.
782 *
783 * Returns: Error code or Success(0)
784 *
785 **/
786static int qlcnic_83xx_idc_init_state(struct qlcnic_adapter *adapter)
787{
788 int timeout, ret = 0;
789 u32 owner;
790
791 timeout = QLC_83XX_IDC_INIT_TIMEOUT_SECS;
792 if (adapter->ahw->idc.prev_state == QLC_83XX_IDC_DEV_NEED_RESET) {
793 owner = qlcnic_83xx_idc_find_reset_owner_id(adapter);
794 if (adapter->ahw->pci_func == owner)
795 ret = qlcnic_83xx_idc_restart_hw(adapter, 1);
796 } else {
797 ret = qlcnic_83xx_idc_check_timeout(adapter, timeout);
798 return ret;
799 }
800
801 return ret;
802}
803
804/**
805 * qlcnic_83xx_idc_ready_state
806 *
807 * @adapter: adapter structure
808 *
809 * Perform IDC protocol specicifed actions after monitoring device state and
810 * events.
811 *
812 * Returns: Error code or Success(0)
813 *
814 **/
815static int qlcnic_83xx_idc_ready_state(struct qlcnic_adapter *adapter)
816{
629263ac 817 struct qlcnic_hardware_context *ahw = adapter->ahw;
068a8d19 818 struct qlcnic_mailbox *mbx = ahw->mailbox;
629263ac 819 int ret = 0;
068a8d19 820 u32 val;
629263ac
SC		 821
822 /* Perform NIC configuration based ready state entry actions */
823 if (ahw->idc.state_entry(adapter))
824 return -EIO;
825
826 if (qlcnic_check_temp(adapter)) {
827 if (ahw->temp == QLCNIC_TEMP_PANIC) {
828 qlcnic_83xx_idc_check_fan_failure(adapter);
829 dev_err(&adapter->pdev->dev,
830 "Error: device temperature %d above limits\n",
831 adapter->ahw->temp);
068a8d19 832 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
629263ac
SC		 833 set_bit(__QLCNIC_RESETTING, &adapter->state);
834 qlcnic_83xx_idc_detach_driver(adapter);
835 qlcnic_83xx_idc_enter_failed_state(adapter, 1);
836 return -EIO;
837 }
838 }
839
840 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
841 ret = qlcnic_83xx_check_heartbeat(adapter);
842 if (ret) {
843 adapter->flags |= QLCNIC_FW_HANG;
844 if (!(val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY)) {
068a8d19 845 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
629263ac
SC		 846 set_bit(__QLCNIC_RESETTING, &adapter->state);
847 qlcnic_83xx_idc_enter_need_reset_state(adapter, 1);
848 }
849 return -EIO;
850 }
851
852 if ((val & QLC_83XX_IDC_GRACEFULL_RESET) || ahw->idc.collect_dump) {
068a8d19
MC		 853 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
854
629263ac
SC		 855 /* Move to need reset state and prepare for reset */
856 qlcnic_83xx_idc_enter_need_reset_state(adapter, 1);
857 return ret;
858 }
859
860 /* Check for soft reset request */
861 if (ahw->reset_context &&
862 !(val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY)) {
536faa61 863 adapter->ahw->reset_context = 0;
629263ac
SC		 864 qlcnic_83xx_idc_tx_soft_reset(adapter);
865 return ret;
866 }
867
868 /* Move to need quiesce state if requested */
869 if (adapter->ahw->idc.quiesce_req) {
870 qlcnic_83xx_idc_enter_need_quiesce(adapter, 1);
871 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
872 return ret;
873 }
874
875 return ret;
876}
877
878/**
879 * qlcnic_83xx_idc_need_reset_state
880 *
881 * @adapter: adapter structure
882 *
883 * Device will remain in this state until:
884 * Reset request ACK's are recieved from all the functions
885 * Wait time exceeds max time limit
886 *
887 * Returns: Error code or Success(0)
888 *
889 **/
890static int qlcnic_83xx_idc_need_reset_state(struct qlcnic_adapter *adapter)
891{
068a8d19 892 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
629263ac
SC		 893 int ret = 0;
894
895 if (adapter->ahw->idc.prev_state != QLC_83XX_IDC_DEV_NEED_RESET) {
629263ac
SC		 896 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
897 set_bit(__QLCNIC_RESETTING, &adapter->state);
068a8d19 898 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
d71170fb
SC		 899 if (adapter->ahw->nic_mode == QLC_83XX_VIRTUAL_NIC_MODE)
900 qlcnic_83xx_disable_vnic_mode(adapter, 1);
099907fa
SC		 901
902 if (qlcnic_check_diag_status(adapter)) {
903 dev_info(&adapter->pdev->dev,
904 "%s: Wait for diag completion\n", __func__);
905 adapter->ahw->idc.delay_reset = 1;
906 return 0;
907 } else {
908 qlcnic_83xx_idc_update_drv_ack_reg(adapter, 1, 1);
909 qlcnic_83xx_idc_detach_driver(adapter);
910 }
629263ac
SC		 911 }
912
099907fa 913 if (qlcnic_check_diag_status(adapter)) {
629263ac 914 dev_info(&adapter->pdev->dev,
099907fa
SC		 915 "%s: Wait for diag completion\n", __func__);
916 return -1;
917 } else {
918 if (adapter->ahw->idc.delay_reset) {
919 qlcnic_83xx_idc_update_drv_ack_reg(adapter, 1, 1);
920 qlcnic_83xx_idc_detach_driver(adapter);
921 adapter->ahw->idc.delay_reset = 0;
922 }
923
924 /* Check for ACK from other functions */
925 ret = qlcnic_83xx_idc_check_reset_ack_reg(adapter);
926 if (ret) {
927 dev_info(&adapter->pdev->dev,
928 "%s: Waiting for reset ACK\n", __func__);
929 return -1;
930 }
629263ac
SC		 931 }
932
933 /* Transit to INIT state and restart the HW */
934 qlcnic_83xx_idc_enter_init_state(adapter, 1);
935
936 return ret;
937}
938
939static int qlcnic_83xx_idc_need_quiesce_state(struct qlcnic_adapter *adapter)
940{
941 dev_err(&adapter->pdev->dev, "%s: TBD\n", __func__);
942 return 0;
943}
944
945static int qlcnic_83xx_idc_failed_state(struct qlcnic_adapter *adapter)
946{
947 dev_err(&adapter->pdev->dev, "%s: please restart!!\n", __func__);
536faa61 948 clear_bit(__QLCNIC_RESETTING, &adapter->state);
629263ac
SC		 949 adapter->ahw->idc.err_code = -EIO;
950
951 return 0;
952}
953
954static int qlcnic_83xx_idc_quiesce_state(struct qlcnic_adapter *adapter)
955{
956 dev_info(&adapter->pdev->dev, "%s: TBD\n", __func__);
957 return 0;
958}
959
960static int qlcnic_83xx_idc_check_state_validity(struct qlcnic_adapter *adapter,
961 u32 state)
962{
963 u32 cur, prev, next;
964
965 cur = adapter->ahw->idc.curr_state;
966 prev = adapter->ahw->idc.prev_state;
967 next = state;
968
969 if ((next < QLC_83XX_IDC_DEV_COLD) ||
970 (next > QLC_83XX_IDC_DEV_QUISCENT)) {
971 dev_err(&adapter->pdev->dev,
972 "%s: curr %d, prev %d, next state %d is invalid\n",
973 __func__, cur, prev, state);
974 return 1;
975 }
976
977 if ((cur == QLC_83XX_IDC_DEV_UNKNOWN) &&
978 (prev == QLC_83XX_IDC_DEV_UNKNOWN)) {
979 if ((next != QLC_83XX_IDC_DEV_COLD) &&
980 (next != QLC_83XX_IDC_DEV_READY)) {
981 dev_err(&adapter->pdev->dev,
982 "%s: failed, cur %d prev %d next %d\n",
983 __func__, cur, prev, next);
984 return 1;
985 }
986 }
987
988 if (next == QLC_83XX_IDC_DEV_INIT) {
989 if ((prev != QLC_83XX_IDC_DEV_INIT) &&
990 (prev != QLC_83XX_IDC_DEV_COLD) &&
991 (prev != QLC_83XX_IDC_DEV_NEED_RESET)) {
992 dev_err(&adapter->pdev->dev,
993 "%s: failed, cur %d prev %d next %d\n",
994 __func__, cur, prev, next);
995 return 1;
996 }
997 }
998
999 return 0;
1000}
1001
1002static void qlcnic_83xx_periodic_tasks(struct qlcnic_adapter *adapter)
1003{
1004 if (adapter->fhash.fnum)
1005 qlcnic_prune_lb_filters(adapter);
1006}
1007
1008/**
1009 * qlcnic_83xx_idc_poll_dev_state
1010 *
1011 * @work: kernel work queue structure used to schedule the function
1012 *
1013 * Poll device state periodically and perform state specific
1014 * actions defined by Inter Driver Communication (IDC) protocol.
1015 *
1016 * Returns: None
1017 *
1018 **/
1019void qlcnic_83xx_idc_poll_dev_state(struct work_struct *work)
1020{
1021 struct qlcnic_adapter *adapter;
1022 u32 state;
1023
1024 adapter = container_of(work, struct qlcnic_adapter, fw_work.work);
1025 state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE);
1026
1027 if (qlcnic_83xx_idc_check_state_validity(adapter, state)) {
1028 qlcnic_83xx_idc_log_state_history(adapter);
1029 adapter->ahw->idc.curr_state = QLC_83XX_IDC_DEV_UNKNOWN;
1030 } else {
1031 adapter->ahw->idc.curr_state = state;
1032 }
1033
1034 switch (adapter->ahw->idc.curr_state) {
1035 case QLC_83XX_IDC_DEV_READY:
1036 qlcnic_83xx_idc_ready_state(adapter);
1037 break;
1038 case QLC_83XX_IDC_DEV_NEED_RESET:
1039 qlcnic_83xx_idc_need_reset_state(adapter);
1040 break;
1041 case QLC_83XX_IDC_DEV_NEED_QUISCENT:
1042 qlcnic_83xx_idc_need_quiesce_state(adapter);
1043 break;
1044 case QLC_83XX_IDC_DEV_FAILED:
1045 qlcnic_83xx_idc_failed_state(adapter);
1046 return;
1047 case QLC_83XX_IDC_DEV_INIT:
1048 qlcnic_83xx_idc_init_state(adapter);
1049 break;
1050 case QLC_83XX_IDC_DEV_QUISCENT:
1051 qlcnic_83xx_idc_quiesce_state(adapter);
1052 break;
1053 default:
1054 qlcnic_83xx_idc_unknown_state(adapter);
1055 return;
1056 }
1057 adapter->ahw->idc.prev_state = adapter->ahw->idc.curr_state;
1058 qlcnic_83xx_periodic_tasks(adapter);
1059
1060 /* Re-schedule the function */
1061 if (test_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status))
1062 qlcnic_schedule_work(adapter, qlcnic_83xx_idc_poll_dev_state,
1063 adapter->ahw->idc.delay);
1064}
1065
1066static void qlcnic_83xx_setup_idc_parameters(struct qlcnic_adapter *adapter)
1067{
1068 u32 idc_params, val;
1069
1070 if (qlcnic_83xx_lockless_flash_read32(adapter,
1071 QLC_83XX_IDC_FLASH_PARAM_ADDR,
1072 (u8 *)&idc_params, 1)) {
1073 dev_info(&adapter->pdev->dev,
1074 "%s:failed to get IDC params from flash\n", __func__);
1075 adapter->dev_init_timeo = QLC_83XX_IDC_INIT_TIMEOUT_SECS;
1076 adapter->reset_ack_timeo = QLC_83XX_IDC_RESET_TIMEOUT_SECS;
1077 } else {
1078 adapter->dev_init_timeo = idc_params & 0xFFFF;
1079 adapter->reset_ack_timeo = ((idc_params >> 16) & 0xFFFF);
1080 }
1081
1082 adapter->ahw->idc.curr_state = QLC_83XX_IDC_DEV_UNKNOWN;
1083 adapter->ahw->idc.prev_state = QLC_83XX_IDC_DEV_UNKNOWN;
1084 adapter->ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY;
1085 adapter->ahw->idc.err_code = 0;
1086 adapter->ahw->idc.collect_dump = 0;
1087 adapter->ahw->idc.name = (char **)qlc_83xx_idc_states;
1088
1089 clear_bit(__QLCNIC_RESETTING, &adapter->state);
629263ac
SC		 1090 set_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
1091
1092 /* Check if reset recovery is disabled */
1093 if (!qlcnic_auto_fw_reset) {
1094 /* Propagate do not reset request to other functions */
1095 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1096 val = val | QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY;
1097 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
1098 }
1099}
1100
1101static int
1102qlcnic_83xx_idc_first_to_load_function_handler(struct qlcnic_adapter *adapter)
1103{
1104 u32 state, val;
1105
1106 if (qlcnic_83xx_lock_driver(adapter))
1107 return -EIO;
1108
1109 /* Clear driver lock register */
1110 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, 0);
1111 if (qlcnic_83xx_idc_update_major_version(adapter, 0)) {
1112 qlcnic_83xx_unlock_driver(adapter);
1113 return -EIO;
1114 }
1115
1116 state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE);
1117 if (qlcnic_83xx_idc_check_state_validity(adapter, state)) {
1118 qlcnic_83xx_unlock_driver(adapter);
1119 return -EIO;
1120 }
1121
1122 if (state != QLC_83XX_IDC_DEV_COLD && qlcnic_load_fw_file) {
1123 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE,
1124 QLC_83XX_IDC_DEV_COLD);
1125 state = QLC_83XX_IDC_DEV_COLD;
1126 }
1127
1128 adapter->ahw->idc.curr_state = state;
1129 /* First to load function should cold boot the device */
1130 if (state == QLC_83XX_IDC_DEV_COLD)
1131 qlcnic_83xx_idc_cold_state_handler(adapter);
1132
1133 /* Check if reset recovery is enabled */
1134 if (qlcnic_auto_fw_reset) {
1135 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1136 val = val & ~QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY;
1137 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
1138 }
1139
1140 qlcnic_83xx_unlock_driver(adapter);
1141
1142 return 0;
1143}
1144
486a5bc7 1145int qlcnic_83xx_idc_init(struct qlcnic_adapter *adapter)
629263ac 1146{
81d0aeb0
SC		 1147 int ret = -EIO;
1148
629263ac
SC		 1149 qlcnic_83xx_setup_idc_parameters(adapter);
1150
81d0aeb0
SC		 1151 if (qlcnic_83xx_get_reset_instruction_template(adapter))
1152 return ret;
1153
629263ac
SC		 1154 if (!qlcnic_83xx_idc_check_driver_presence_reg(adapter)) {
1155 if (qlcnic_83xx_idc_first_to_load_function_handler(adapter))
1156 return -EIO;
1157 } else {
1158 if (qlcnic_83xx_idc_check_major_version(adapter))
1159 return -EIO;
1160 }
1161
1162 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
1163
1164 return 0;
1165}
1166
1167void qlcnic_83xx_idc_exit(struct qlcnic_adapter *adapter)
1168{
1169 int id;
1170 u32 val;
1171
1172 while (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))
1173 usleep_range(10000, 11000);
1174
1175 id = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
1176 id = id & 0xFF;
1177
1178 if (id == adapter->portnum) {
1179 dev_err(&adapter->pdev->dev,
1180 "%s: wait for lock recovery.. %d\n", __func__, id);
1181 msleep(20);
1182 id = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
1183 id = id & 0xFF;
1184 }
1185
1186 /* Clear driver presence bit */
1187 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
1188 val = val & ~(1 << adapter->portnum);
1189 QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val);
1190 clear_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
1191 clear_bit(__QLCNIC_RESETTING, &adapter->state);
1192
1193 cancel_delayed_work_sync(&adapter->fw_work);
1194}
1195
1196void qlcnic_83xx_idc_request_reset(struct qlcnic_adapter *adapter, u32 key)
1197{
1198 u32 val;
1199
068a8d19
MC		 1200 if (qlcnic_sriov_vf_check(adapter))
1201 return;
1202
629263ac
SC		 1203 if (qlcnic_83xx_lock_driver(adapter)) {
1204 dev_err(&adapter->pdev->dev,
1205 "%s:failed, please retry\n", __func__);
1206 return;
1207 }
1208
1209 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1210 if ((val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY) ||
1211 !qlcnic_auto_fw_reset) {
1212 dev_err(&adapter->pdev->dev,
1213 "%s:failed, device in non reset mode\n", __func__);
1214 qlcnic_83xx_unlock_driver(adapter);
1215 return;
1216 }
1217
1218 if (key == QLCNIC_FORCE_FW_RESET) {
1219 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1220 val = val | QLC_83XX_IDC_GRACEFULL_RESET;
1221 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
1222 } else if (key == QLCNIC_FORCE_FW_DUMP_KEY) {
1223 adapter->ahw->idc.collect_dump = 1;
1224 }
1225
1226 qlcnic_83xx_unlock_driver(adapter);
1227 return;
1228}
1229
1230static int qlcnic_83xx_copy_bootloader(struct qlcnic_adapter *adapter)
1231{
1232 u8 *p_cache;
1233 u32 src, size;
1234 u64 dest;
1235 int ret = -EIO;
1236
1237 src = QLC_83XX_BOOTLOADER_FLASH_ADDR;
1238 dest = QLCRDX(adapter->ahw, QLCNIC_BOOTLOADER_ADDR);
1239 size = QLCRDX(adapter->ahw, QLCNIC_BOOTLOADER_SIZE);
1240
1241 /* alignment check */
1242 if (size & 0xF)
1243 size = (size + 16) & ~0xF;
1244
1245 p_cache = kzalloc(size, GFP_KERNEL);
b2adaca9 1246 if (p_cache == NULL)
629263ac 1247 return -ENOMEM;
b2adaca9 1248
629263ac
SC		 1249 ret = qlcnic_83xx_lockless_flash_read32(adapter, src, p_cache,
1250 size / sizeof(u32));
1251 if (ret) {
1252 kfree(p_cache);
1253 return ret;
1254 }
1255 /* 16 byte write to MS memory */
1256 ret = qlcnic_83xx_ms_mem_write128(adapter, dest, (u32 *)p_cache,
1257 size / 16);
1258 if (ret) {
1259 kfree(p_cache);
1260 return ret;
1261 }
1262 kfree(p_cache);
1263
1264 return ret;
1265}
1266
1267static int qlcnic_83xx_copy_fw_file(struct qlcnic_adapter *adapter)
1268{
1269 u32 dest, *p_cache;
1270 u64 addr;
1271 u8 data[16];
1272 size_t size;
1273 int i, ret = -EIO;
1274
1275 dest = QLCRDX(adapter->ahw, QLCNIC_FW_IMAGE_ADDR);
1276 size = (adapter->ahw->fw_info.fw->size & ~0xF);
1277 p_cache = (u32 *)adapter->ahw->fw_info.fw->data;
1278 addr = (u64)dest;
1279
1280 ret = qlcnic_83xx_ms_mem_write128(adapter, addr,
1281 (u32 *)p_cache, size / 16);
1282 if (ret) {
1283 dev_err(&adapter->pdev->dev, "MS memory write failed\n");
1284 release_firmware(adapter->ahw->fw_info.fw);
1285 adapter->ahw->fw_info.fw = NULL;
1286 return -EIO;
1287 }
1288
1289 /* alignment check */
1290 if (adapter->ahw->fw_info.fw->size & 0xF) {
1291 addr = dest + size;
1292 for (i = 0; i < (adapter->ahw->fw_info.fw->size & 0xF); i++)
1293 data[i] = adapter->ahw->fw_info.fw->data[size + i];
1294 for (; i < 16; i++)
1295 data[i] = 0;
1296 ret = qlcnic_83xx_ms_mem_write128(adapter, addr,
1297 (u32 *)data, 1);
1298 if (ret) {
1299 dev_err(&adapter->pdev->dev,
1300 "MS memory write failed\n");
1301 release_firmware(adapter->ahw->fw_info.fw);
1302 adapter->ahw->fw_info.fw = NULL;
1303 return -EIO;
1304 }
1305 }
1306 release_firmware(adapter->ahw->fw_info.fw);
1307 adapter->ahw->fw_info.fw = NULL;
1308
1309 return 0;
1310}
1311
1312static void qlcnic_83xx_dump_pause_control_regs(struct qlcnic_adapter *adapter)
1313{
1314 int i, j;
1315 u32 val = 0, val1 = 0, reg = 0;
4bd8e738 1316 int err = 0;
629263ac 1317
4bd8e738
HM		 1318 val = QLCRD32(adapter, QLC_83XX_SRE_SHIM_REG, &err);
1319 if (err == -EIO)
1320 return;
629263ac
SC		 1321 dev_info(&adapter->pdev->dev, "SRE-Shim Ctrl:0x%x\n", val);
1322
1323 for (j = 0; j < 2; j++) {
1324 if (j == 0) {
1325 dev_info(&adapter->pdev->dev,
1326 "Port 0 RxB Pause Threshold Regs[TC7..TC0]:");
1327 reg = QLC_83XX_PORT0_THRESHOLD;
1328 } else if (j == 1) {
1329 dev_info(&adapter->pdev->dev,
1330 "Port 1 RxB Pause Threshold Regs[TC7..TC0]:");
1331 reg = QLC_83XX_PORT1_THRESHOLD;
1332 }
1333 for (i = 0; i < 8; i++) {
4bd8e738
HM		 1334 val = QLCRD32(adapter, reg + (i * 0x4), &err);
1335 if (err == -EIO)
1336 return;
629263ac
SC		 1337 dev_info(&adapter->pdev->dev, "0x%x ", val);
1338 }
1339 dev_info(&adapter->pdev->dev, "\n");
1340 }
1341
1342 for (j = 0; j < 2; j++) {
1343 if (j == 0) {
1344 dev_info(&adapter->pdev->dev,
1345 "Port 0 RxB TC Max Cell Registers[4..1]:");
1346 reg = QLC_83XX_PORT0_TC_MC_REG;
1347 } else if (j == 1) {
1348 dev_info(&adapter->pdev->dev,
1349 "Port 1 RxB TC Max Cell Registers[4..1]:");
1350 reg = QLC_83XX_PORT1_TC_MC_REG;
1351 }
1352 for (i = 0; i < 4; i++) {
4bd8e738
HM		 1353 val = QLCRD32(adapter, reg + (i * 0x4), &err);
1354 if (err == -EIO)
1355 return;
1356 dev_info(&adapter->pdev->dev, "0x%x ", val);
629263ac
SC		 1357 }
1358 dev_info(&adapter->pdev->dev, "\n");
1359 }
1360
1361 for (j = 0; j < 2; j++) {
1362 if (j == 0) {
1363 dev_info(&adapter->pdev->dev,
1364 "Port 0 RxB Rx TC Stats[TC7..TC0]:");
1365 reg = QLC_83XX_PORT0_TC_STATS;
1366 } else if (j == 1) {
1367 dev_info(&adapter->pdev->dev,
1368 "Port 1 RxB Rx TC Stats[TC7..TC0]:");
1369 reg = QLC_83XX_PORT1_TC_STATS;
1370 }
1371 for (i = 7; i >= 0; i--) {
4bd8e738
HM		 1372 val = QLCRD32(adapter, reg, &err);
1373 if (err == -EIO)
1374 return;
629263ac
SC		 1375 val &= ~(0x7 << 29); /* Reset bits 29 to 31 */
1376 QLCWR32(adapter, reg, (val | (i << 29)));
4bd8e738
HM		 1377 val = QLCRD32(adapter, reg, &err);
1378 if (err == -EIO)
1379 return;
629263ac
SC		 1380 dev_info(&adapter->pdev->dev, "0x%x ", val);
1381 }
1382 dev_info(&adapter->pdev->dev, "\n");
1383 }
1384
4bd8e738
HM		 1385 val = QLCRD32(adapter, QLC_83XX_PORT2_IFB_THRESHOLD, &err);
1386 if (err == -EIO)
1387 return;
1388 val1 = QLCRD32(adapter, QLC_83XX_PORT3_IFB_THRESHOLD, &err);
1389 if (err == -EIO)
1390 return;
629263ac
SC		 1391 dev_info(&adapter->pdev->dev,
1392 "IFB-Pause Thresholds: Port 2:0x%x, Port 3:0x%x\n",
1393 val, val1);
1394}
1395
81d0aeb0 1396
629263ac
SC		 1397static void qlcnic_83xx_disable_pause_frames(struct qlcnic_adapter *adapter)
1398{
1399 u32 reg = 0, i, j;
1400
1401 if (qlcnic_83xx_lock_driver(adapter)) {
1402 dev_err(&adapter->pdev->dev,
1403 "%s:failed to acquire driver lock\n", __func__);
1404 return;
1405 }
1406
1407 qlcnic_83xx_dump_pause_control_regs(adapter);
1408 QLCWR32(adapter, QLC_83XX_SRE_SHIM_REG, 0x0);
1409
1410 for (j = 0; j < 2; j++) {
1411 if (j == 0)
1412 reg = QLC_83XX_PORT0_THRESHOLD;
1413 else if (j == 1)
1414 reg = QLC_83XX_PORT1_THRESHOLD;
1415
1416 for (i = 0; i < 8; i++)
1417 QLCWR32(adapter, reg + (i * 0x4), 0x0);
1418 }
1419
1420 for (j = 0; j < 2; j++) {
1421 if (j == 0)
1422 reg = QLC_83XX_PORT0_TC_MC_REG;
1423 else if (j == 1)
1424 reg = QLC_83XX_PORT1_TC_MC_REG;
1425
1426 for (i = 0; i < 4; i++)
1427 QLCWR32(adapter, reg + (i * 0x4), 0x03FF03FF);
1428 }
1429
1430 QLCWR32(adapter, QLC_83XX_PORT2_IFB_THRESHOLD, 0);
1431 QLCWR32(adapter, QLC_83XX_PORT3_IFB_THRESHOLD, 0);
1432 dev_info(&adapter->pdev->dev,
1433 "Disabled pause frames successfully on all ports\n");
1434 qlcnic_83xx_unlock_driver(adapter);
1435}
1436
c0d79cd0
MC		 1437static void qlcnic_83xx_take_eport_out_of_reset(struct qlcnic_adapter *adapter)
1438{
1439 QLCWR32(adapter, QLC_83XX_RESET_REG, 0);
1440 QLCWR32(adapter, QLC_83XX_RESET_PORT0, 0);
1441 QLCWR32(adapter, QLC_83XX_RESET_PORT1, 0);
1442 QLCWR32(adapter, QLC_83XX_RESET_PORT2, 0);
1443 QLCWR32(adapter, QLC_83XX_RESET_PORT3, 0);
1444 QLCWR32(adapter, QLC_83XX_RESET_SRESHIM, 0);
1445 QLCWR32(adapter, QLC_83XX_RESET_EPGSHIM, 0);
1446 QLCWR32(adapter, QLC_83XX_RESET_ETHERPCS, 0);
1447 QLCWR32(adapter, QLC_83XX_RESET_CONTROL, 1);
1448}
1449
629263ac
SC		 1450static int qlcnic_83xx_check_heartbeat(struct qlcnic_adapter *p_dev)
1451{
1452 u32 heartbeat, peg_status;
4bd8e738 1453 int retries, ret = -EIO, err = 0;
629263ac
SC		 1454
1455 retries = QLCNIC_HEARTBEAT_CHECK_RETRY_COUNT;
1456 p_dev->heartbeat = QLC_SHARED_REG_RD32(p_dev,
1457 QLCNIC_PEG_ALIVE_COUNTER);
1458
1459 do {
1460 msleep(QLCNIC_HEARTBEAT_PERIOD_MSECS);
1461 heartbeat = QLC_SHARED_REG_RD32(p_dev,
1462 QLCNIC_PEG_ALIVE_COUNTER);
1463 if (heartbeat != p_dev->heartbeat) {
1464 ret = QLCNIC_RCODE_SUCCESS;
1465 break;
1466 }
1467 } while (--retries);
1468
1469 if (ret) {
1470 dev_err(&p_dev->pdev->dev, "firmware hang detected\n");
c0d79cd0 1471 qlcnic_83xx_take_eport_out_of_reset(p_dev);
629263ac
SC		 1472 qlcnic_83xx_disable_pause_frames(p_dev);
1473 peg_status = QLC_SHARED_REG_RD32(p_dev,
1474 QLCNIC_PEG_HALT_STATUS1);
1475 dev_info(&p_dev->pdev->dev, "Dumping HW/FW registers\n"
1476 "PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,\n"
1477 "PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,\n"
1478 "PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,\n"
1479 "PEG_NET_4_PC: 0x%x\n", peg_status,
1480 QLC_SHARED_REG_RD32(p_dev, QLCNIC_PEG_HALT_STATUS2),
4bd8e738
HM		 1481 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_0, &err),
1482 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_1, &err),
1483 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_2, &err),
1484 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_3, &err),
1485 QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_4, &err));
629263ac
SC		 1486
1487 if (QLCNIC_FWERROR_CODE(peg_status) == 0x67)
1488 dev_err(&p_dev->pdev->dev,
1489 "Device is being reset err code 0x00006700.\n");
1490 }
1491
1492 return ret;
1493}
1494
1495static int qlcnic_83xx_check_cmd_peg_status(struct qlcnic_adapter *p_dev)
1496{
1497 int retries = QLCNIC_CMDPEG_CHECK_RETRY_COUNT;
1498 u32 val;
1499
1500 do {
1501 val = QLC_SHARED_REG_RD32(p_dev, QLCNIC_CMDPEG_STATE);
1502 if (val == QLC_83XX_CMDPEG_COMPLETE)
1503 return 0;
1504 msleep(QLCNIC_CMDPEG_CHECK_DELAY);
1505 } while (--retries);
1506
1507 dev_err(&p_dev->pdev->dev, "%s: failed, state = 0x%x\n", __func__, val);
1508 return -EIO;
1509}
1510
1511int qlcnic_83xx_check_hw_status(struct qlcnic_adapter *p_dev)
1512{
1513 int err;
1514
1515 err = qlcnic_83xx_check_cmd_peg_status(p_dev);
1516 if (err)
1517 return err;
1518
1519 err = qlcnic_83xx_check_heartbeat(p_dev);
1520 if (err)
1521 return err;
1522
1523 return err;
1524}
1525
81d0aeb0
SC		 1526static int qlcnic_83xx_poll_reg(struct qlcnic_adapter *p_dev, u32 addr,
1527 int duration, u32 mask, u32 status)
1528{
4bd8e738 1529 int timeout_error, err = 0;
81d0aeb0 1530 u32 value;
81d0aeb0
SC		 1531 u8 retries;
1532
4bd8e738
HM		 1533 value = QLCRD32(p_dev, addr, &err);
1534 if (err == -EIO)
1535 return err;
81d0aeb0
SC		 1536 retries = duration / 10;
1537
1538 do {
1539 if ((value & mask) != status) {
1540 timeout_error = 1;
1541 msleep(duration / 10);
4bd8e738
HM		 1542 value = QLCRD32(p_dev, addr, &err);
1543 if (err == -EIO)
1544 return err;
81d0aeb0
SC		 1545 } else {
1546 timeout_error = 0;
1547 break;
1548 }
1549 } while (retries--);
1550
1551 if (timeout_error) {
1552 p_dev->ahw->reset.seq_error++;
1553 dev_err(&p_dev->pdev->dev,
1554 "%s: Timeout Err, entry_num = %d\n",
1555 __func__, p_dev->ahw->reset.seq_index);
1556 dev_err(&p_dev->pdev->dev,
1557 "0x%08x 0x%08x 0x%08x\n",
1558 value, mask, status);
1559 }
1560
1561 return timeout_error;
1562}
1563
1564static int qlcnic_83xx_reset_template_checksum(struct qlcnic_adapter *p_dev)
1565{
1566 u32 sum = 0;
1567 u16 *buff = (u16 *)p_dev->ahw->reset.buff;
1568 int count = p_dev->ahw->reset.hdr->size / sizeof(u16);
1569
1570 while (count-- > 0)
1571 sum += *buff++;
1572
1573 while (sum >> 16)
1574 sum = (sum & 0xFFFF) + (sum >> 16);
1575
1576 if (~sum) {
1577 return 0;
1578 } else {
1579 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1580 return -1;
1581 }
1582}
1583
1584int qlcnic_83xx_get_reset_instruction_template(struct qlcnic_adapter *p_dev)
1585{
81d0aeb0 1586 struct qlcnic_hardware_context *ahw = p_dev->ahw;
486a5bc7
RB		 1587 u32 addr, count, prev_ver, curr_ver;
1588 u8 *p_buff;
1589
1590 if (ahw->reset.buff != NULL) {
1591 prev_ver = p_dev->fw_version;
1592 curr_ver = qlcnic_83xx_get_fw_version(p_dev);
1593 if (curr_ver > prev_ver)
1594 kfree(ahw->reset.buff);
1595 else
1596 return 0;
1597 }
81d0aeb0
SC		 1598
1599 ahw->reset.seq_error = 0;
1600 ahw->reset.buff = kzalloc(QLC_83XX_RESTART_TEMPLATE_SIZE, GFP_KERNEL);
b2adaca9 1601 if (p_dev->ahw->reset.buff == NULL)
81d0aeb0 1602 return -ENOMEM;
b2adaca9 1603
81d0aeb0
SC		 1604 p_buff = p_dev->ahw->reset.buff;
1605 addr = QLC_83XX_RESET_TEMPLATE_ADDR;
1606 count = sizeof(struct qlc_83xx_reset_hdr) / sizeof(u32);
1607
1608 /* Copy template header from flash */
1609 if (qlcnic_83xx_flash_read32(p_dev, addr, p_buff, count)) {
1610 dev_err(&p_dev->pdev->dev, "%s: flash read failed\n", __func__);
1611 return -EIO;
1612 }
1613 ahw->reset.hdr = (struct qlc_83xx_reset_hdr *)ahw->reset.buff;
1614 addr = QLC_83XX_RESET_TEMPLATE_ADDR + ahw->reset.hdr->hdr_size;
1615 p_buff = ahw->reset.buff + ahw->reset.hdr->hdr_size;
1616 count = (ahw->reset.hdr->size - ahw->reset.hdr->hdr_size) / sizeof(u32);
1617
1618 /* Copy rest of the template */
1619 if (qlcnic_83xx_flash_read32(p_dev, addr, p_buff, count)) {
1620 dev_err(&p_dev->pdev->dev, "%s: flash read failed\n", __func__);
1621 return -EIO;
1622 }
1623
1624 if (qlcnic_83xx_reset_template_checksum(p_dev))
1625 return -EIO;
1626 /* Get Stop, Start and Init command offsets */
1627 ahw->reset.init_offset = ahw->reset.buff + ahw->reset.hdr->init_offset;
1628 ahw->reset.start_offset = ahw->reset.buff +
1629 ahw->reset.hdr->start_offset;
1630 ahw->reset.stop_offset = ahw->reset.buff + ahw->reset.hdr->hdr_size;
1631 return 0;
1632}
1633
1634/* Read Write HW register command */
1635static void qlcnic_83xx_read_write_crb_reg(struct qlcnic_adapter *p_dev,
1636 u32 raddr, u32 waddr)
1637{
4bd8e738
HM		 1638 int err = 0;
1639 u32 value;
81d0aeb0 1640
4bd8e738
HM		 1641 value = QLCRD32(p_dev, raddr, &err);
1642 if (err == -EIO)
1643 return;
81d0aeb0
SC		 1644 qlcnic_83xx_wrt_reg_indirect(p_dev, waddr, value);
1645}
1646
1647/* Read Modify Write HW register command */
1648static void qlcnic_83xx_rmw_crb_reg(struct qlcnic_adapter *p_dev,
1649 u32 raddr, u32 waddr,
1650 struct qlc_83xx_rmw *p_rmw_hdr)
1651{
4bd8e738
HM		 1652 int err = 0;
1653 u32 value;
81d0aeb0 1654
4bd8e738 1655 if (p_rmw_hdr->index_a) {
81d0aeb0 1656 value = p_dev->ahw->reset.array[p_rmw_hdr->index_a];
4bd8e738
HM		 1657 } else {
1658 value = QLCRD32(p_dev, raddr, &err);
1659 if (err == -EIO)
1660 return;
1661 }
81d0aeb0
SC		 1662
1663 value &= p_rmw_hdr->mask;
1664 value <<= p_rmw_hdr->shl;
1665 value >>= p_rmw_hdr->shr;
1666 value |= p_rmw_hdr->or_value;
1667 value ^= p_rmw_hdr->xor_value;
1668 qlcnic_83xx_wrt_reg_indirect(p_dev, waddr, value);
1669}
1670
1671/* Write HW register command */
1672static void qlcnic_83xx_write_list(struct qlcnic_adapter *p_dev,
1673 struct qlc_83xx_entry_hdr *p_hdr)
1674{
1675 int i;
1676 struct qlc_83xx_entry *entry;
1677
1678 entry = (struct qlc_83xx_entry *)((char *)p_hdr +
1679 sizeof(struct qlc_83xx_entry_hdr));
1680
1681 for (i = 0; i < p_hdr->count; i++, entry++) {
1682 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->arg1,
1683 entry->arg2);
1684 if (p_hdr->delay)
1685 udelay((u32)(p_hdr->delay));
1686 }
1687}
1688
1689/* Read and Write instruction */
1690static void qlcnic_83xx_read_write_list(struct qlcnic_adapter *p_dev,
1691 struct qlc_83xx_entry_hdr *p_hdr)
1692{
1693 int i;
1694 struct qlc_83xx_entry *entry;
1695
1696 entry = (struct qlc_83xx_entry *)((char *)p_hdr +
1697 sizeof(struct qlc_83xx_entry_hdr));
1698
1699 for (i = 0; i < p_hdr->count; i++, entry++) {
1700 qlcnic_83xx_read_write_crb_reg(p_dev, entry->arg1,
1701 entry->arg2);
1702 if (p_hdr->delay)
1703 udelay((u32)(p_hdr->delay));
1704 }
1705}
1706
1707/* Poll HW register command */
1708static void qlcnic_83xx_poll_list(struct qlcnic_adapter *p_dev,
1709 struct qlc_83xx_entry_hdr *p_hdr)
1710{
1711 long delay;
1712 struct qlc_83xx_entry *entry;
1713 struct qlc_83xx_poll *poll;
4bd8e738 1714 int i, err = 0;
81d0aeb0
SC		 1715 unsigned long arg1, arg2;
1716
1717 poll = (struct qlc_83xx_poll *)((char *)p_hdr +
1718 sizeof(struct qlc_83xx_entry_hdr));
1719
1720 entry = (struct qlc_83xx_entry *)((char *)poll +
1721 sizeof(struct qlc_83xx_poll));
1722 delay = (long)p_hdr->delay;
1723
1724 if (!delay) {
1725 for (i = 0; i < p_hdr->count; i++, entry++)
1726 qlcnic_83xx_poll_reg(p_dev, entry->arg1,
1727 delay, poll->mask,
1728 poll->status);
1729 } else {
1730 for (i = 0; i < p_hdr->count; i++, entry++) {
1731 arg1 = entry->arg1;
1732 arg2 = entry->arg2;
1733 if (delay) {
1734 if (qlcnic_83xx_poll_reg(p_dev,
1735 arg1, delay,
1736 poll->mask,
1737 poll->status)){
4bd8e738
HM		 1738 QLCRD32(p_dev, arg1, &err);
1739 if (err == -EIO)
1740 return;
1741 QLCRD32(p_dev, arg2, &err);
1742 if (err == -EIO)
1743 return;
81d0aeb0
SC		 1744 }
1745 }
1746 }
1747 }
1748}
1749
1750/* Poll and write HW register command */
1751static void qlcnic_83xx_poll_write_list(struct qlcnic_adapter *p_dev,
1752 struct qlc_83xx_entry_hdr *p_hdr)
1753{
1754 int i;
1755 long delay;
1756 struct qlc_83xx_quad_entry *entry;
1757 struct qlc_83xx_poll *poll;
1758
1759 poll = (struct qlc_83xx_poll *)((char *)p_hdr +
1760 sizeof(struct qlc_83xx_entry_hdr));
1761 entry = (struct qlc_83xx_quad_entry *)((char *)poll +
1762 sizeof(struct qlc_83xx_poll));
1763 delay = (long)p_hdr->delay;
1764
1765 for (i = 0; i < p_hdr->count; i++, entry++) {
1766 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->dr_addr,
1767 entry->dr_value);
1768 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->ar_addr,
1769 entry->ar_value);
1770 if (delay)
1771 qlcnic_83xx_poll_reg(p_dev, entry->ar_addr, delay,
1772 poll->mask, poll->status);
1773 }
1774}
1775
1776/* Read Modify Write register command */
1777static void qlcnic_83xx_read_modify_write(struct qlcnic_adapter *p_dev,
1778 struct qlc_83xx_entry_hdr *p_hdr)
1779{
1780 int i;
1781 struct qlc_83xx_entry *entry;
1782 struct qlc_83xx_rmw *rmw_hdr;
1783
1784 rmw_hdr = (struct qlc_83xx_rmw *)((char *)p_hdr +
1785 sizeof(struct qlc_83xx_entry_hdr));
1786
1787 entry = (struct qlc_83xx_entry *)((char *)rmw_hdr +
1788 sizeof(struct qlc_83xx_rmw));
1789
1790 for (i = 0; i < p_hdr->count; i++, entry++) {
1791 qlcnic_83xx_rmw_crb_reg(p_dev, entry->arg1,
1792 entry->arg2, rmw_hdr);
1793 if (p_hdr->delay)
1794 udelay((u32)(p_hdr->delay));
1795 }
1796}
1797
1798static void qlcnic_83xx_pause(struct qlc_83xx_entry_hdr *p_hdr)
1799{
1800 if (p_hdr->delay)
1801 mdelay((u32)((long)p_hdr->delay));
1802}
1803
1804/* Read and poll register command */
1805static void qlcnic_83xx_poll_read_list(struct qlcnic_adapter *p_dev,
1806 struct qlc_83xx_entry_hdr *p_hdr)
1807{
1808 long delay;
4bd8e738 1809 int index, i, j, err;
81d0aeb0
SC		 1810 struct qlc_83xx_quad_entry *entry;
1811 struct qlc_83xx_poll *poll;
1812 unsigned long addr;
1813
1814 poll = (struct qlc_83xx_poll *)((char *)p_hdr +
1815 sizeof(struct qlc_83xx_entry_hdr));
1816
1817 entry = (struct qlc_83xx_quad_entry *)((char *)poll +
1818 sizeof(struct qlc_83xx_poll));
1819 delay = (long)p_hdr->delay;
1820
1821 for (i = 0; i < p_hdr->count; i++, entry++) {
1822 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->ar_addr,
1823 entry->ar_value);
1824 if (delay) {
1825 if (!qlcnic_83xx_poll_reg(p_dev, entry->ar_addr, delay,
1826 poll->mask, poll->status)){
1827 index = p_dev->ahw->reset.array_index;
1828 addr = entry->dr_addr;
4bd8e738
HM		 1829 j = QLCRD32(p_dev, addr, &err);
1830 if (err == -EIO)
1831 return;
1832
81d0aeb0
SC		 1833 p_dev->ahw->reset.array[index++] = j;
1834
1835 if (index == QLC_83XX_MAX_RESET_SEQ_ENTRIES)
1836 p_dev->ahw->reset.array_index = 1;
1837 }
1838 }
1839 }
1840}
1841
1842static inline void qlcnic_83xx_seq_end(struct qlcnic_adapter *p_dev)
1843{
1844 p_dev->ahw->reset.seq_end = 1;
1845}
1846
1847static void qlcnic_83xx_template_end(struct qlcnic_adapter *p_dev)
1848{
1849 p_dev->ahw->reset.template_end = 1;
1850 if (p_dev->ahw->reset.seq_error == 0)
1851 dev_err(&p_dev->pdev->dev,
1852 "HW restart process completed successfully.\n");
1853 else
1854 dev_err(&p_dev->pdev->dev,
1855 "HW restart completed with timeout errors.\n");
1856}
1857
1858/**
1859* qlcnic_83xx_exec_template_cmd
1860*
1861* @p_dev: adapter structure
1862* @p_buff: Poiter to instruction template
1863*
1864* Template provides instructions to stop, restart and initalize firmware.
1865* These instructions are abstracted as a series of read, write and
1866* poll operations on hardware registers. Register information and operation
1867* specifics are not exposed to the driver. Driver reads the template from
1868* flash and executes the instructions located at pre-defined offsets.
1869*
1870* Returns: None
1871* */
1872static void qlcnic_83xx_exec_template_cmd(struct qlcnic_adapter *p_dev,
1873 char *p_buff)
1874{
1875 int index, entries;
1876 struct qlc_83xx_entry_hdr *p_hdr;
1877 char *entry = p_buff;
1878
1879 p_dev->ahw->reset.seq_end = 0;
1880 p_dev->ahw->reset.template_end = 0;
1881 entries = p_dev->ahw->reset.hdr->entries;
1882 index = p_dev->ahw->reset.seq_index;
1883
1884 for (; (!p_dev->ahw->reset.seq_end) && (index < entries); index++) {
1885 p_hdr = (struct qlc_83xx_entry_hdr *)entry;
1886
1887 switch (p_hdr->cmd) {
1888 case QLC_83XX_OPCODE_NOP:
1889 break;
1890 case QLC_83XX_OPCODE_WRITE_LIST:
1891 qlcnic_83xx_write_list(p_dev, p_hdr);
1892 break;
1893 case QLC_83XX_OPCODE_READ_WRITE_LIST:
1894 qlcnic_83xx_read_write_list(p_dev, p_hdr);
1895 break;
1896 case QLC_83XX_OPCODE_POLL_LIST:
1897 qlcnic_83xx_poll_list(p_dev, p_hdr);
1898 break;
1899 case QLC_83XX_OPCODE_POLL_WRITE_LIST:
1900 qlcnic_83xx_poll_write_list(p_dev, p_hdr);
1901 break;
1902 case QLC_83XX_OPCODE_READ_MODIFY_WRITE:
1903 qlcnic_83xx_read_modify_write(p_dev, p_hdr);
1904 break;
1905 case QLC_83XX_OPCODE_SEQ_PAUSE:
1906 qlcnic_83xx_pause(p_hdr);
1907 break;
1908 case QLC_83XX_OPCODE_SEQ_END:
1909 qlcnic_83xx_seq_end(p_dev);
1910 break;
1911 case QLC_83XX_OPCODE_TMPL_END:
1912 qlcnic_83xx_template_end(p_dev);
1913 break;
1914 case QLC_83XX_OPCODE_POLL_READ_LIST:
1915 qlcnic_83xx_poll_read_list(p_dev, p_hdr);
1916 break;
1917 default:
1918 dev_err(&p_dev->pdev->dev,
1919 "%s: Unknown opcode 0x%04x in template %d\n",
1920 __func__, p_hdr->cmd, index);
1921 break;
1922 }
1923 entry += p_hdr->size;
1924 }
1925 p_dev->ahw->reset.seq_index = index;
1926}
1927
1928static void qlcnic_83xx_stop_hw(struct qlcnic_adapter *p_dev)
1929{
1930 p_dev->ahw->reset.seq_index = 0;
1931
1932 qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.stop_offset);
1933 if (p_dev->ahw->reset.seq_end != 1)
1934 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1935}
1936
1937static void qlcnic_83xx_start_hw(struct qlcnic_adapter *p_dev)
1938{
1939 qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.start_offset);
1940 if (p_dev->ahw->reset.template_end != 1)
1941 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1942}
1943
1944static void qlcnic_83xx_init_hw(struct qlcnic_adapter *p_dev)
1945{
1946 qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.init_offset);
1947 if (p_dev->ahw->reset.seq_end != 1)
1948 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1949}
1950
fef349ce
PP		 1951static inline void qlcnic_83xx_get_fw_file_name(struct qlcnic_adapter *adapter,
1952 char *file_name)
1953{
1954 struct pci_dev *pdev = adapter->pdev;
1955
1956 memset(file_name, 0, QLC_FW_FILE_NAME_LEN);
1957
1958 switch (pdev->device) {
1959 case PCI_DEVICE_ID_QLOGIC_QLE834X:
1960 strncpy(file_name, QLC_83XX_FW_FILE_NAME,
1961 QLC_FW_FILE_NAME_LEN);
1962 break;
1963 case PCI_DEVICE_ID_QLOGIC_QLE844X:
1964 strncpy(file_name, QLC_84XX_FW_FILE_NAME,
1965 QLC_FW_FILE_NAME_LEN);
1966 break;
1967 default:
1968 dev_err(&pdev->dev, "%s: Invalid device id\n",
1969 __func__);
1970 }
1971}
1972
629263ac
SC		 1973static int qlcnic_83xx_load_fw_image_from_host(struct qlcnic_adapter *adapter)
1974{
fef349ce 1975 char fw_file_name[QLC_FW_FILE_NAME_LEN];
629263ac
SC		 1976 int err = -EIO;
1977
fef349ce
PP		 1978 qlcnic_83xx_get_fw_file_name(adapter, fw_file_name);
1979 if (request_firmware(&adapter->ahw->fw_info.fw, fw_file_name,
1980 &(adapter->pdev->dev))) {
629263ac
SC		 1981 dev_err(&adapter->pdev->dev,
1982 "No file FW image, loading flash FW image.\n");
1983 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID,
1984 QLC_83XX_BOOT_FROM_FLASH);
1985 } else {
1986 if (qlcnic_83xx_copy_fw_file(adapter))
1987 return err;
1988 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID,
1989 QLC_83XX_BOOT_FROM_FILE);
1990 }
1991
1992 return 0;
1993}
1994
1995static int qlcnic_83xx_restart_hw(struct qlcnic_adapter *adapter)
1996{
4e60ac46 1997 u32 val;
629263ac
SC		 1998 int err = -EIO;
1999
81d0aeb0 2000 qlcnic_83xx_stop_hw(adapter);
4e60ac46
SC		 2001
2002 /* Collect FW register dump if required */
2003 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
2004 if (!(val & QLC_83XX_IDC_GRACEFULL_RESET))
2005 qlcnic_dump_fw(adapter);
81d0aeb0
SC		 2006 qlcnic_83xx_init_hw(adapter);
2007
629263ac
SC		 2008 if (qlcnic_83xx_copy_bootloader(adapter))
2009 return err;
2010 /* Boot either flash image or firmware image from host file system */
2011 if (qlcnic_load_fw_file) {
2012 if (qlcnic_83xx_load_fw_image_from_host(adapter))
2013 return err;
2014 } else {
2015 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID,
2016 QLC_83XX_BOOT_FROM_FLASH);
2017 }
2018
81d0aeb0 2019 qlcnic_83xx_start_hw(adapter);
629263ac
SC		 2020 if (qlcnic_83xx_check_hw_status(adapter))
2021 return -EIO;
2022
2023 return 0;
2024}
2025
2026/**
2027* qlcnic_83xx_config_default_opmode
2028*
2029* @adapter: adapter structure
2030*
2031* Configure default driver operating mode
2032*
2033* Returns: Error code or Success(0)
2034* */
2035int qlcnic_83xx_config_default_opmode(struct qlcnic_adapter *adapter)
2036{
2037 u32 op_mode;
2038 struct qlcnic_hardware_context *ahw = adapter->ahw;
2039
2040 qlcnic_get_func_no(adapter);
2041 op_mode = QLCRDX(ahw, QLC_83XX_DRV_OP_MODE);
2042
02feda17
RB		 2043 if (test_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state))
2044 op_mode = QLC_83XX_DEFAULT_OPMODE;
2045
629263ac
SC		 2046 if (op_mode == QLC_83XX_DEFAULT_OPMODE) {
2047 adapter->nic_ops->init_driver = qlcnic_83xx_init_default_driver;
2048 ahw->idc.state_entry = qlcnic_83xx_idc_ready_state_entry;
2049 } else {
2050 return -EIO;
2051 }
2052
2053 return 0;
2054}
2055
2056int qlcnic_83xx_get_nic_configuration(struct qlcnic_adapter *adapter)
2057{
2058 int err;
2059 struct qlcnic_info nic_info;
2060 struct qlcnic_hardware_context *ahw = adapter->ahw;
2061
2062 memset(&nic_info, 0, sizeof(struct qlcnic_info));
2063 err = qlcnic_get_nic_info(adapter, &nic_info, ahw->pci_func);
2064 if (err)
2065 return -EIO;
2066
2067 ahw->physical_port = (u8) nic_info.phys_port;
2068 ahw->switch_mode = nic_info.switch_mode;
2069 ahw->max_tx_ques = nic_info.max_tx_ques;
2070 ahw->max_rx_ques = nic_info.max_rx_ques;
2071 ahw->capabilities = nic_info.capabilities;
2072 ahw->max_mac_filters = nic_info.max_mac_filters;
2073 ahw->max_mtu = nic_info.max_mtu;
2074
02feda17
RB		 2075 /* VNIC mode is detected by BIT_23 in capabilities. This bit is also
2076 * set in case device is SRIOV capable. VNIC and SRIOV are mutually
2077 * exclusive. So in case of sriov capable device load driver in
2078 * default mode
2079 */
2080 if (test_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state)) {
2081 ahw->nic_mode = QLC_83XX_DEFAULT_MODE;
2082 return ahw->nic_mode;
2083 }
2084
629263ac
SC		 2085 if (ahw->capabilities & BIT_23)
2086 ahw->nic_mode = QLC_83XX_VIRTUAL_NIC_MODE;
2087 else
2088 ahw->nic_mode = QLC_83XX_DEFAULT_MODE;
2089
2090 return ahw->nic_mode;
2091}
2092
02feda17 2093int qlcnic_83xx_configure_opmode(struct qlcnic_adapter *adapter)
629263ac
SC		 2094{
2095 int ret;
2096
2097 ret = qlcnic_83xx_get_nic_configuration(adapter);
2098 if (ret == -EIO)
2099 return -EIO;
2100
d71170fb
SC		 2101 if (ret == QLC_83XX_VIRTUAL_NIC_MODE) {
2102 if (qlcnic_83xx_config_vnic_opmode(adapter))
2103 return -EIO;
2104 } else if (ret == QLC_83XX_DEFAULT_MODE) {
629263ac
SC		 2105 if (qlcnic_83xx_config_default_opmode(adapter))
2106 return -EIO;
2107 }
2108
2109 return 0;
2110}
2111
2112static void qlcnic_83xx_config_buff_descriptors(struct qlcnic_adapter *adapter)
2113{
2114 struct qlcnic_hardware_context *ahw = adapter->ahw;
2115
2116 if (ahw->port_type == QLCNIC_XGBE) {
2117 adapter->num_rxd = DEFAULT_RCV_DESCRIPTORS_10G;
2118 adapter->max_rxd = MAX_RCV_DESCRIPTORS_10G;
2119 adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G;
2120 adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G;
2121
2122 } else if (ahw->port_type == QLCNIC_GBE) {
2123 adapter->num_rxd = DEFAULT_RCV_DESCRIPTORS_1G;
2124 adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_1G;
2125 adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_1G;
2126 adapter->max_rxd = MAX_RCV_DESCRIPTORS_1G;
2127 }
2128 adapter->num_txd = MAX_CMD_DESCRIPTORS;
2129 adapter->max_rds_rings = MAX_RDS_RINGS;
2130}
2131
2132static int qlcnic_83xx_init_default_driver(struct qlcnic_adapter *adapter)
2133{
2134 int err = -EIO;
2135
4e60ac46 2136 qlcnic_83xx_get_minidump_template(adapter);
629263ac
SC		 2137 if (qlcnic_83xx_get_port_info(adapter))
2138 return err;
2139
2140 qlcnic_83xx_config_buff_descriptors(adapter);
2141 adapter->ahw->msix_supported = !!qlcnic_use_msi_x;
2142 adapter->flags |= QLCNIC_ADAPTER_INITIALIZED;
2143
2144 dev_info(&adapter->pdev->dev, "HAL Version: %d\n",
2145 adapter->ahw->fw_hal_version);
2146
2147 return 0;
2148}
2149
2150#define IS_QLC_83XX_USED(a, b, c) (((1 << a->portnum) & b) || ((c >> 6) & 0x1))
2151static void qlcnic_83xx_clear_function_resources(struct qlcnic_adapter *adapter)
2152{
2153 struct qlcnic_cmd_args cmd;
2154 u32 presence_mask, audit_mask;
2155 int status;
2156
2157 presence_mask = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
2158 audit_mask = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT);
2159
2160 if (IS_QLC_83XX_USED(adapter, presence_mask, audit_mask)) {
b6b4316c
SS		 2161 status = qlcnic_alloc_mbx_args(&cmd, adapter,
2162 QLCNIC_CMD_STOP_NIC_FUNC);
2163 if (status)
2164 return;
2165
629263ac
SC		 2166 cmd.req.arg[1] = BIT_31;
2167 status = qlcnic_issue_cmd(adapter, &cmd);
2168 if (status)
2169 dev_err(&adapter->pdev->dev,
2170 "Failed to clean up the function resources\n");
2171 qlcnic_free_mbx_args(&cmd);
2172 }
2173}
2174
f8468331 2175int qlcnic_83xx_init(struct qlcnic_adapter *adapter, int pci_using_dac)
629263ac
SC		 2176{
2177 struct qlcnic_hardware_context *ahw = adapter->ahw;
068a8d19 2178 int err = 0;
629263ac 2179
068a8d19
MC		 2180 ahw->msix_supported = !!qlcnic_use_msi_x;
2181 err = qlcnic_83xx_init_mailbox_work(adapter);
2182 if (err)
2183 goto exit;
f8468331 2184
068a8d19
MC		 2185 if (qlcnic_sriov_vf_check(adapter)) {
2186 err = qlcnic_sriov_vf_init(adapter, pci_using_dac);
2187 if (err)
2188 goto detach_mbx;
2189 else
2190 return err;
2191 }
629263ac 2192
068a8d19
MC		 2193 err = qlcnic_83xx_check_hw_status(adapter);
2194 if (err)
2195 goto detach_mbx;
2196
b5acb255
MC		 2197 if (!qlcnic_83xx_read_flash_descriptor_table(adapter))
2198 qlcnic_83xx_read_flash_mfg_id(adapter);
2199
2200 err = qlcnic_83xx_idc_init(adapter);
2201 if (err)
2202 goto detach_mbx;
2203
aa4a1f7d 2204 err = qlcnic_setup_intr(adapter, 0, 0);
068a8d19
MC		 2205 if (err) {
2206 dev_err(&adapter->pdev->dev, "Failed to setup interrupt\n");
2207 goto disable_intr;
2208 }
2209
2210 err = qlcnic_83xx_setup_mbx_intr(adapter);
2211 if (err)
2212 goto disable_mbx_intr;
629263ac 2213
629263ac
SC		 2214 qlcnic_83xx_clear_function_resources(adapter);
2215
c70a3175
JK		 2216 INIT_DELAYED_WORK(&adapter->idc_aen_work, qlcnic_83xx_idc_aen_work);
2217
d5fcff04
HM		 2218 /* register for NIC IDC AEN Events */
2219 qlcnic_83xx_register_nic_idc_func(adapter, 1);
2220
629263ac 2221 /* Configure default, SR-IOV or Virtual NIC mode of operation */
068a8d19
MC		 2222 err = qlcnic_83xx_configure_opmode(adapter);
2223 if (err)
2224 goto disable_mbx_intr;
629263ac
SC		 2225
2226 /* Perform operating mode specific initialization */
068a8d19
MC		 2227 err = adapter->nic_ops->init_driver(adapter);
2228 if (err)
2229 goto disable_mbx_intr;
629263ac 2230
629263ac
SC		 2231 /* Periodically monitor device status */
2232 qlcnic_83xx_idc_poll_dev_state(&adapter->fw_work.work);
068a8d19 2233 return 0;
629263ac 2234
068a8d19
MC		 2235disable_mbx_intr:
2236 qlcnic_83xx_free_mbx_intr(adapter);
2237
2238disable_intr:
2239 qlcnic_teardown_intr(adapter);
2240
2241detach_mbx:
2242 qlcnic_83xx_detach_mailbox_work(adapter);
2243 qlcnic_83xx_free_mailbox(ahw->mailbox);
2244exit:
2245 return err;
629263ac 2246}
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