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c4e84bde RM |
1 | /* |
2 | * QLogic qlge NIC HBA Driver | |
3 | * Copyright (c) 2003-2008 QLogic Corporation | |
4 | * See LICENSE.qlge for copyright and licensing details. | |
5 | * Author: Linux qlge network device driver by | |
6 | * Ron Mercer <ron.mercer@qlogic.com> | |
7 | */ | |
8 | #include <linux/kernel.h> | |
18c49b91 | 9 | #include <linux/bitops.h> |
c4e84bde RM |
10 | #include <linux/types.h> |
11 | #include <linux/module.h> | |
12 | #include <linux/list.h> | |
13 | #include <linux/pci.h> | |
14 | #include <linux/dma-mapping.h> | |
15 | #include <linux/pagemap.h> | |
16 | #include <linux/sched.h> | |
17 | #include <linux/slab.h> | |
18 | #include <linux/dmapool.h> | |
19 | #include <linux/mempool.h> | |
20 | #include <linux/spinlock.h> | |
21 | #include <linux/kthread.h> | |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/errno.h> | |
24 | #include <linux/ioport.h> | |
25 | #include <linux/in.h> | |
26 | #include <linux/ip.h> | |
27 | #include <linux/ipv6.h> | |
28 | #include <net/ipv6.h> | |
29 | #include <linux/tcp.h> | |
30 | #include <linux/udp.h> | |
31 | #include <linux/if_arp.h> | |
32 | #include <linux/if_ether.h> | |
33 | #include <linux/netdevice.h> | |
34 | #include <linux/etherdevice.h> | |
35 | #include <linux/ethtool.h> | |
18c49b91 | 36 | #include <linux/if_vlan.h> |
c4e84bde | 37 | #include <linux/skbuff.h> |
c4e84bde RM |
38 | #include <linux/delay.h> |
39 | #include <linux/mm.h> | |
40 | #include <linux/vmalloc.h> | |
70c71606 | 41 | #include <linux/prefetch.h> |
b7c6bfb7 | 42 | #include <net/ip6_checksum.h> |
c4e84bde RM |
43 | |
44 | #include "qlge.h" | |
45 | ||
46 | char qlge_driver_name[] = DRV_NAME; | |
47 | const char qlge_driver_version[] = DRV_VERSION; | |
48 | ||
49 | MODULE_AUTHOR("Ron Mercer <ron.mercer@qlogic.com>"); | |
50 | MODULE_DESCRIPTION(DRV_STRING " "); | |
51 | MODULE_LICENSE("GPL"); | |
52 | MODULE_VERSION(DRV_VERSION); | |
53 | ||
54 | static const u32 default_msg = | |
55 | NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | | |
56 | /* NETIF_MSG_TIMER | */ | |
57 | NETIF_MSG_IFDOWN | | |
58 | NETIF_MSG_IFUP | | |
59 | NETIF_MSG_RX_ERR | | |
60 | NETIF_MSG_TX_ERR | | |
4974097a RM |
61 | /* NETIF_MSG_TX_QUEUED | */ |
62 | /* NETIF_MSG_INTR | NETIF_MSG_TX_DONE | NETIF_MSG_RX_STATUS | */ | |
c4e84bde RM |
63 | /* NETIF_MSG_PKTDATA | */ |
64 | NETIF_MSG_HW | NETIF_MSG_WOL | 0; | |
65 | ||
84cf7029 SR |
66 | static int debug = -1; /* defaults above */ |
67 | module_param(debug, int, 0664); | |
c4e84bde RM |
68 | MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); |
69 | ||
70 | #define MSIX_IRQ 0 | |
71 | #define MSI_IRQ 1 | |
72 | #define LEG_IRQ 2 | |
a5a62a1c | 73 | static int qlge_irq_type = MSIX_IRQ; |
84cf7029 | 74 | module_param(qlge_irq_type, int, 0664); |
a5a62a1c | 75 | MODULE_PARM_DESC(qlge_irq_type, "0 = MSI-X, 1 = MSI, 2 = Legacy."); |
c4e84bde | 76 | |
8aae2600 RM |
77 | static int qlge_mpi_coredump; |
78 | module_param(qlge_mpi_coredump, int, 0); | |
79 | MODULE_PARM_DESC(qlge_mpi_coredump, | |
80 | "Option to enable MPI firmware dump. " | |
d5c1da56 RM |
81 | "Default is OFF - Do Not allocate memory. "); |
82 | ||
83 | static int qlge_force_coredump; | |
84 | module_param(qlge_force_coredump, int, 0); | |
85 | MODULE_PARM_DESC(qlge_force_coredump, | |
86 | "Option to allow force of firmware core dump. " | |
87 | "Default is OFF - Do not allow."); | |
8aae2600 | 88 | |
9baa3c34 | 89 | static const struct pci_device_id qlge_pci_tbl[] = { |
b0c2aadf | 90 | {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QLGE_DEVICE_ID_8012)}, |
cdca8d02 | 91 | {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QLGE_DEVICE_ID_8000)}, |
c4e84bde RM |
92 | /* required last entry */ |
93 | {0,} | |
94 | }; | |
95 | ||
96 | MODULE_DEVICE_TABLE(pci, qlge_pci_tbl); | |
97 | ||
a45adbe8 JK |
98 | static int ql_wol(struct ql_adapter *); |
99 | static void qlge_set_multicast_list(struct net_device *); | |
100 | static int ql_adapter_down(struct ql_adapter *); | |
101 | static int ql_adapter_up(struct ql_adapter *); | |
ac409215 | 102 | |
c4e84bde RM |
103 | /* This hardware semaphore causes exclusive access to |
104 | * resources shared between the NIC driver, MPI firmware, | |
105 | * FCOE firmware and the FC driver. | |
106 | */ | |
107 | static int ql_sem_trylock(struct ql_adapter *qdev, u32 sem_mask) | |
108 | { | |
109 | u32 sem_bits = 0; | |
110 | ||
111 | switch (sem_mask) { | |
112 | case SEM_XGMAC0_MASK: | |
113 | sem_bits = SEM_SET << SEM_XGMAC0_SHIFT; | |
114 | break; | |
115 | case SEM_XGMAC1_MASK: | |
116 | sem_bits = SEM_SET << SEM_XGMAC1_SHIFT; | |
117 | break; | |
118 | case SEM_ICB_MASK: | |
119 | sem_bits = SEM_SET << SEM_ICB_SHIFT; | |
120 | break; | |
121 | case SEM_MAC_ADDR_MASK: | |
122 | sem_bits = SEM_SET << SEM_MAC_ADDR_SHIFT; | |
123 | break; | |
124 | case SEM_FLASH_MASK: | |
125 | sem_bits = SEM_SET << SEM_FLASH_SHIFT; | |
126 | break; | |
127 | case SEM_PROBE_MASK: | |
128 | sem_bits = SEM_SET << SEM_PROBE_SHIFT; | |
129 | break; | |
130 | case SEM_RT_IDX_MASK: | |
131 | sem_bits = SEM_SET << SEM_RT_IDX_SHIFT; | |
132 | break; | |
133 | case SEM_PROC_REG_MASK: | |
134 | sem_bits = SEM_SET << SEM_PROC_REG_SHIFT; | |
135 | break; | |
136 | default: | |
ae9540f7 | 137 | netif_alert(qdev, probe, qdev->ndev, "bad Semaphore mask!.\n"); |
c4e84bde RM |
138 | return -EINVAL; |
139 | } | |
140 | ||
141 | ql_write32(qdev, SEM, sem_bits | sem_mask); | |
142 | return !(ql_read32(qdev, SEM) & sem_bits); | |
143 | } | |
144 | ||
145 | int ql_sem_spinlock(struct ql_adapter *qdev, u32 sem_mask) | |
146 | { | |
0857e9d7 | 147 | unsigned int wait_count = 30; |
c4e84bde RM |
148 | do { |
149 | if (!ql_sem_trylock(qdev, sem_mask)) | |
150 | return 0; | |
0857e9d7 RM |
151 | udelay(100); |
152 | } while (--wait_count); | |
c4e84bde RM |
153 | return -ETIMEDOUT; |
154 | } | |
155 | ||
156 | void ql_sem_unlock(struct ql_adapter *qdev, u32 sem_mask) | |
157 | { | |
158 | ql_write32(qdev, SEM, sem_mask); | |
159 | ql_read32(qdev, SEM); /* flush */ | |
160 | } | |
161 | ||
162 | /* This function waits for a specific bit to come ready | |
163 | * in a given register. It is used mostly by the initialize | |
164 | * process, but is also used in kernel thread API such as | |
165 | * netdev->set_multi, netdev->set_mac_address, netdev->vlan_rx_add_vid. | |
166 | */ | |
167 | int ql_wait_reg_rdy(struct ql_adapter *qdev, u32 reg, u32 bit, u32 err_bit) | |
168 | { | |
169 | u32 temp; | |
170 | int count = UDELAY_COUNT; | |
171 | ||
172 | while (count) { | |
173 | temp = ql_read32(qdev, reg); | |
174 | ||
175 | /* check for errors */ | |
176 | if (temp & err_bit) { | |
ae9540f7 JP |
177 | netif_alert(qdev, probe, qdev->ndev, |
178 | "register 0x%.08x access error, value = 0x%.08x!.\n", | |
179 | reg, temp); | |
c4e84bde RM |
180 | return -EIO; |
181 | } else if (temp & bit) | |
182 | return 0; | |
183 | udelay(UDELAY_DELAY); | |
184 | count--; | |
185 | } | |
ae9540f7 JP |
186 | netif_alert(qdev, probe, qdev->ndev, |
187 | "Timed out waiting for reg %x to come ready.\n", reg); | |
c4e84bde RM |
188 | return -ETIMEDOUT; |
189 | } | |
190 | ||
191 | /* The CFG register is used to download TX and RX control blocks | |
192 | * to the chip. This function waits for an operation to complete. | |
193 | */ | |
194 | static int ql_wait_cfg(struct ql_adapter *qdev, u32 bit) | |
195 | { | |
196 | int count = UDELAY_COUNT; | |
197 | u32 temp; | |
198 | ||
199 | while (count) { | |
200 | temp = ql_read32(qdev, CFG); | |
201 | if (temp & CFG_LE) | |
202 | return -EIO; | |
203 | if (!(temp & bit)) | |
204 | return 0; | |
205 | udelay(UDELAY_DELAY); | |
206 | count--; | |
207 | } | |
208 | return -ETIMEDOUT; | |
209 | } | |
210 | ||
211 | ||
212 | /* Used to issue init control blocks to hw. Maps control block, | |
213 | * sets address, triggers download, waits for completion. | |
214 | */ | |
215 | int ql_write_cfg(struct ql_adapter *qdev, void *ptr, int size, u32 bit, | |
216 | u16 q_id) | |
217 | { | |
218 | u64 map; | |
219 | int status = 0; | |
220 | int direction; | |
221 | u32 mask; | |
222 | u32 value; | |
223 | ||
224 | direction = | |
225 | (bit & (CFG_LRQ | CFG_LR | CFG_LCQ)) ? PCI_DMA_TODEVICE : | |
226 | PCI_DMA_FROMDEVICE; | |
227 | ||
228 | map = pci_map_single(qdev->pdev, ptr, size, direction); | |
229 | if (pci_dma_mapping_error(qdev->pdev, map)) { | |
ae9540f7 | 230 | netif_err(qdev, ifup, qdev->ndev, "Couldn't map DMA area.\n"); |
c4e84bde RM |
231 | return -ENOMEM; |
232 | } | |
233 | ||
4322c5be RM |
234 | status = ql_sem_spinlock(qdev, SEM_ICB_MASK); |
235 | if (status) | |
236 | return status; | |
237 | ||
c4e84bde RM |
238 | status = ql_wait_cfg(qdev, bit); |
239 | if (status) { | |
ae9540f7 JP |
240 | netif_err(qdev, ifup, qdev->ndev, |
241 | "Timed out waiting for CFG to come ready.\n"); | |
c4e84bde RM |
242 | goto exit; |
243 | } | |
244 | ||
c4e84bde RM |
245 | ql_write32(qdev, ICB_L, (u32) map); |
246 | ql_write32(qdev, ICB_H, (u32) (map >> 32)); | |
c4e84bde RM |
247 | |
248 | mask = CFG_Q_MASK | (bit << 16); | |
249 | value = bit | (q_id << CFG_Q_SHIFT); | |
250 | ql_write32(qdev, CFG, (mask | value)); | |
251 | ||
252 | /* | |
253 | * Wait for the bit to clear after signaling hw. | |
254 | */ | |
255 | status = ql_wait_cfg(qdev, bit); | |
256 | exit: | |
4322c5be | 257 | ql_sem_unlock(qdev, SEM_ICB_MASK); /* does flush too */ |
c4e84bde RM |
258 | pci_unmap_single(qdev->pdev, map, size, direction); |
259 | return status; | |
260 | } | |
261 | ||
262 | /* Get a specific MAC address from the CAM. Used for debug and reg dump. */ | |
263 | int ql_get_mac_addr_reg(struct ql_adapter *qdev, u32 type, u16 index, | |
264 | u32 *value) | |
265 | { | |
266 | u32 offset = 0; | |
267 | int status; | |
268 | ||
c4e84bde RM |
269 | switch (type) { |
270 | case MAC_ADDR_TYPE_MULTI_MAC: | |
271 | case MAC_ADDR_TYPE_CAM_MAC: | |
272 | { | |
273 | status = | |
274 | ql_wait_reg_rdy(qdev, | |
939678f8 | 275 | MAC_ADDR_IDX, MAC_ADDR_MW, 0); |
c4e84bde RM |
276 | if (status) |
277 | goto exit; | |
278 | ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */ | |
279 | (index << MAC_ADDR_IDX_SHIFT) | /* index */ | |
280 | MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */ | |
281 | status = | |
282 | ql_wait_reg_rdy(qdev, | |
939678f8 | 283 | MAC_ADDR_IDX, MAC_ADDR_MR, 0); |
c4e84bde RM |
284 | if (status) |
285 | goto exit; | |
286 | *value++ = ql_read32(qdev, MAC_ADDR_DATA); | |
287 | status = | |
288 | ql_wait_reg_rdy(qdev, | |
939678f8 | 289 | MAC_ADDR_IDX, MAC_ADDR_MW, 0); |
c4e84bde RM |
290 | if (status) |
291 | goto exit; | |
292 | ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */ | |
293 | (index << MAC_ADDR_IDX_SHIFT) | /* index */ | |
294 | MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */ | |
295 | status = | |
296 | ql_wait_reg_rdy(qdev, | |
939678f8 | 297 | MAC_ADDR_IDX, MAC_ADDR_MR, 0); |
c4e84bde RM |
298 | if (status) |
299 | goto exit; | |
300 | *value++ = ql_read32(qdev, MAC_ADDR_DATA); | |
301 | if (type == MAC_ADDR_TYPE_CAM_MAC) { | |
302 | status = | |
303 | ql_wait_reg_rdy(qdev, | |
939678f8 | 304 | MAC_ADDR_IDX, MAC_ADDR_MW, 0); |
c4e84bde RM |
305 | if (status) |
306 | goto exit; | |
307 | ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */ | |
308 | (index << MAC_ADDR_IDX_SHIFT) | /* index */ | |
309 | MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */ | |
310 | status = | |
311 | ql_wait_reg_rdy(qdev, MAC_ADDR_IDX, | |
939678f8 | 312 | MAC_ADDR_MR, 0); |
c4e84bde RM |
313 | if (status) |
314 | goto exit; | |
315 | *value++ = ql_read32(qdev, MAC_ADDR_DATA); | |
316 | } | |
317 | break; | |
318 | } | |
319 | case MAC_ADDR_TYPE_VLAN: | |
320 | case MAC_ADDR_TYPE_MULTI_FLTR: | |
321 | default: | |
ae9540f7 JP |
322 | netif_crit(qdev, ifup, qdev->ndev, |
323 | "Address type %d not yet supported.\n", type); | |
c4e84bde RM |
324 | status = -EPERM; |
325 | } | |
326 | exit: | |
c4e84bde RM |
327 | return status; |
328 | } | |
329 | ||
330 | /* Set up a MAC, multicast or VLAN address for the | |
331 | * inbound frame matching. | |
332 | */ | |
333 | static int ql_set_mac_addr_reg(struct ql_adapter *qdev, u8 *addr, u32 type, | |
334 | u16 index) | |
335 | { | |
336 | u32 offset = 0; | |
337 | int status = 0; | |
338 | ||
c4e84bde RM |
339 | switch (type) { |
340 | case MAC_ADDR_TYPE_MULTI_MAC: | |
76b26694 RM |
341 | { |
342 | u32 upper = (addr[0] << 8) | addr[1]; | |
343 | u32 lower = (addr[2] << 24) | (addr[3] << 16) | | |
344 | (addr[4] << 8) | (addr[5]); | |
345 | ||
346 | status = | |
347 | ql_wait_reg_rdy(qdev, | |
348 | MAC_ADDR_IDX, MAC_ADDR_MW, 0); | |
349 | if (status) | |
350 | goto exit; | |
351 | ql_write32(qdev, MAC_ADDR_IDX, (offset++) | | |
352 | (index << MAC_ADDR_IDX_SHIFT) | | |
353 | type | MAC_ADDR_E); | |
354 | ql_write32(qdev, MAC_ADDR_DATA, lower); | |
355 | status = | |
356 | ql_wait_reg_rdy(qdev, | |
357 | MAC_ADDR_IDX, MAC_ADDR_MW, 0); | |
358 | if (status) | |
359 | goto exit; | |
360 | ql_write32(qdev, MAC_ADDR_IDX, (offset++) | | |
361 | (index << MAC_ADDR_IDX_SHIFT) | | |
362 | type | MAC_ADDR_E); | |
363 | ||
364 | ql_write32(qdev, MAC_ADDR_DATA, upper); | |
365 | status = | |
366 | ql_wait_reg_rdy(qdev, | |
367 | MAC_ADDR_IDX, MAC_ADDR_MW, 0); | |
368 | if (status) | |
369 | goto exit; | |
370 | break; | |
371 | } | |
c4e84bde RM |
372 | case MAC_ADDR_TYPE_CAM_MAC: |
373 | { | |
374 | u32 cam_output; | |
375 | u32 upper = (addr[0] << 8) | addr[1]; | |
376 | u32 lower = | |
377 | (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) | | |
378 | (addr[5]); | |
c4e84bde RM |
379 | status = |
380 | ql_wait_reg_rdy(qdev, | |
939678f8 | 381 | MAC_ADDR_IDX, MAC_ADDR_MW, 0); |
c4e84bde RM |
382 | if (status) |
383 | goto exit; | |
384 | ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */ | |
385 | (index << MAC_ADDR_IDX_SHIFT) | /* index */ | |
386 | type); /* type */ | |
387 | ql_write32(qdev, MAC_ADDR_DATA, lower); | |
388 | status = | |
389 | ql_wait_reg_rdy(qdev, | |
939678f8 | 390 | MAC_ADDR_IDX, MAC_ADDR_MW, 0); |
c4e84bde RM |
391 | if (status) |
392 | goto exit; | |
393 | ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */ | |
394 | (index << MAC_ADDR_IDX_SHIFT) | /* index */ | |
395 | type); /* type */ | |
396 | ql_write32(qdev, MAC_ADDR_DATA, upper); | |
397 | status = | |
398 | ql_wait_reg_rdy(qdev, | |
939678f8 | 399 | MAC_ADDR_IDX, MAC_ADDR_MW, 0); |
c4e84bde RM |
400 | if (status) |
401 | goto exit; | |
402 | ql_write32(qdev, MAC_ADDR_IDX, (offset) | /* offset */ | |
403 | (index << MAC_ADDR_IDX_SHIFT) | /* index */ | |
404 | type); /* type */ | |
405 | /* This field should also include the queue id | |
406 | and possibly the function id. Right now we hardcode | |
407 | the route field to NIC core. | |
408 | */ | |
76b26694 RM |
409 | cam_output = (CAM_OUT_ROUTE_NIC | |
410 | (qdev-> | |
411 | func << CAM_OUT_FUNC_SHIFT) | | |
412 | (0 << CAM_OUT_CQ_ID_SHIFT)); | |
f646968f | 413 | if (qdev->ndev->features & NETIF_F_HW_VLAN_CTAG_RX) |
76b26694 RM |
414 | cam_output |= CAM_OUT_RV; |
415 | /* route to NIC core */ | |
416 | ql_write32(qdev, MAC_ADDR_DATA, cam_output); | |
c4e84bde RM |
417 | break; |
418 | } | |
419 | case MAC_ADDR_TYPE_VLAN: | |
420 | { | |
421 | u32 enable_bit = *((u32 *) &addr[0]); | |
422 | /* For VLAN, the addr actually holds a bit that | |
423 | * either enables or disables the vlan id we are | |
424 | * addressing. It's either MAC_ADDR_E on or off. | |
425 | * That's bit-27 we're talking about. | |
426 | */ | |
c4e84bde RM |
427 | status = |
428 | ql_wait_reg_rdy(qdev, | |
939678f8 | 429 | MAC_ADDR_IDX, MAC_ADDR_MW, 0); |
c4e84bde RM |
430 | if (status) |
431 | goto exit; | |
432 | ql_write32(qdev, MAC_ADDR_IDX, offset | /* offset */ | |
433 | (index << MAC_ADDR_IDX_SHIFT) | /* index */ | |
434 | type | /* type */ | |
435 | enable_bit); /* enable/disable */ | |
436 | break; | |
437 | } | |
438 | case MAC_ADDR_TYPE_MULTI_FLTR: | |
439 | default: | |
ae9540f7 JP |
440 | netif_crit(qdev, ifup, qdev->ndev, |
441 | "Address type %d not yet supported.\n", type); | |
c4e84bde RM |
442 | status = -EPERM; |
443 | } | |
444 | exit: | |
c4e84bde RM |
445 | return status; |
446 | } | |
447 | ||
7fab3bfe RM |
448 | /* Set or clear MAC address in hardware. We sometimes |
449 | * have to clear it to prevent wrong frame routing | |
450 | * especially in a bonding environment. | |
451 | */ | |
452 | static int ql_set_mac_addr(struct ql_adapter *qdev, int set) | |
453 | { | |
454 | int status; | |
455 | char zero_mac_addr[ETH_ALEN]; | |
456 | char *addr; | |
457 | ||
458 | if (set) { | |
801e9096 | 459 | addr = &qdev->current_mac_addr[0]; |
ae9540f7 JP |
460 | netif_printk(qdev, ifup, KERN_DEBUG, qdev->ndev, |
461 | "Set Mac addr %pM\n", addr); | |
7fab3bfe | 462 | } else { |
c7bf7169 | 463 | eth_zero_addr(zero_mac_addr); |
7fab3bfe | 464 | addr = &zero_mac_addr[0]; |
ae9540f7 JP |
465 | netif_printk(qdev, ifup, KERN_DEBUG, qdev->ndev, |
466 | "Clearing MAC address\n"); | |
7fab3bfe RM |
467 | } |
468 | status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK); | |
469 | if (status) | |
470 | return status; | |
471 | status = ql_set_mac_addr_reg(qdev, (u8 *) addr, | |
472 | MAC_ADDR_TYPE_CAM_MAC, qdev->func * MAX_CQ); | |
473 | ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK); | |
474 | if (status) | |
ae9540f7 JP |
475 | netif_err(qdev, ifup, qdev->ndev, |
476 | "Failed to init mac address.\n"); | |
7fab3bfe RM |
477 | return status; |
478 | } | |
479 | ||
6a473308 RM |
480 | void ql_link_on(struct ql_adapter *qdev) |
481 | { | |
ae9540f7 | 482 | netif_err(qdev, link, qdev->ndev, "Link is up.\n"); |
6a473308 RM |
483 | netif_carrier_on(qdev->ndev); |
484 | ql_set_mac_addr(qdev, 1); | |
485 | } | |
486 | ||
487 | void ql_link_off(struct ql_adapter *qdev) | |
488 | { | |
ae9540f7 | 489 | netif_err(qdev, link, qdev->ndev, "Link is down.\n"); |
6a473308 RM |
490 | netif_carrier_off(qdev->ndev); |
491 | ql_set_mac_addr(qdev, 0); | |
492 | } | |
493 | ||
c4e84bde RM |
494 | /* Get a specific frame routing value from the CAM. |
495 | * Used for debug and reg dump. | |
496 | */ | |
497 | int ql_get_routing_reg(struct ql_adapter *qdev, u32 index, u32 *value) | |
498 | { | |
499 | int status = 0; | |
500 | ||
939678f8 | 501 | status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, 0); |
c4e84bde RM |
502 | if (status) |
503 | goto exit; | |
504 | ||
505 | ql_write32(qdev, RT_IDX, | |
506 | RT_IDX_TYPE_NICQ | RT_IDX_RS | (index << RT_IDX_IDX_SHIFT)); | |
939678f8 | 507 | status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MR, 0); |
c4e84bde RM |
508 | if (status) |
509 | goto exit; | |
510 | *value = ql_read32(qdev, RT_DATA); | |
511 | exit: | |
c4e84bde RM |
512 | return status; |
513 | } | |
514 | ||
515 | /* The NIC function for this chip has 16 routing indexes. Each one can be used | |
516 | * to route different frame types to various inbound queues. We send broadcast/ | |
517 | * multicast/error frames to the default queue for slow handling, | |
518 | * and CAM hit/RSS frames to the fast handling queues. | |
519 | */ | |
520 | static int ql_set_routing_reg(struct ql_adapter *qdev, u32 index, u32 mask, | |
521 | int enable) | |
522 | { | |
8587ea35 | 523 | int status = -EINVAL; /* Return error if no mask match. */ |
c4e84bde RM |
524 | u32 value = 0; |
525 | ||
c4e84bde RM |
526 | switch (mask) { |
527 | case RT_IDX_CAM_HIT: | |
528 | { | |
529 | value = RT_IDX_DST_CAM_Q | /* dest */ | |
530 | RT_IDX_TYPE_NICQ | /* type */ | |
531 | (RT_IDX_CAM_HIT_SLOT << RT_IDX_IDX_SHIFT);/* index */ | |
532 | break; | |
533 | } | |
534 | case RT_IDX_VALID: /* Promiscuous Mode frames. */ | |
535 | { | |
536 | value = RT_IDX_DST_DFLT_Q | /* dest */ | |
537 | RT_IDX_TYPE_NICQ | /* type */ | |
538 | (RT_IDX_PROMISCUOUS_SLOT << RT_IDX_IDX_SHIFT);/* index */ | |
539 | break; | |
540 | } | |
541 | case RT_IDX_ERR: /* Pass up MAC,IP,TCP/UDP error frames. */ | |
542 | { | |
543 | value = RT_IDX_DST_DFLT_Q | /* dest */ | |
544 | RT_IDX_TYPE_NICQ | /* type */ | |
545 | (RT_IDX_ALL_ERR_SLOT << RT_IDX_IDX_SHIFT);/* index */ | |
546 | break; | |
547 | } | |
fbc2ac33 RM |
548 | case RT_IDX_IP_CSUM_ERR: /* Pass up IP CSUM error frames. */ |
549 | { | |
550 | value = RT_IDX_DST_DFLT_Q | /* dest */ | |
551 | RT_IDX_TYPE_NICQ | /* type */ | |
552 | (RT_IDX_IP_CSUM_ERR_SLOT << | |
553 | RT_IDX_IDX_SHIFT); /* index */ | |
554 | break; | |
555 | } | |
556 | case RT_IDX_TU_CSUM_ERR: /* Pass up TCP/UDP CSUM error frames. */ | |
557 | { | |
558 | value = RT_IDX_DST_DFLT_Q | /* dest */ | |
559 | RT_IDX_TYPE_NICQ | /* type */ | |
560 | (RT_IDX_TCP_UDP_CSUM_ERR_SLOT << | |
561 | RT_IDX_IDX_SHIFT); /* index */ | |
562 | break; | |
563 | } | |
c4e84bde RM |
564 | case RT_IDX_BCAST: /* Pass up Broadcast frames to default Q. */ |
565 | { | |
566 | value = RT_IDX_DST_DFLT_Q | /* dest */ | |
567 | RT_IDX_TYPE_NICQ | /* type */ | |
568 | (RT_IDX_BCAST_SLOT << RT_IDX_IDX_SHIFT);/* index */ | |
569 | break; | |
570 | } | |
571 | case RT_IDX_MCAST: /* Pass up All Multicast frames. */ | |
572 | { | |
e163d7f2 | 573 | value = RT_IDX_DST_DFLT_Q | /* dest */ |
c4e84bde RM |
574 | RT_IDX_TYPE_NICQ | /* type */ |
575 | (RT_IDX_ALLMULTI_SLOT << RT_IDX_IDX_SHIFT);/* index */ | |
576 | break; | |
577 | } | |
578 | case RT_IDX_MCAST_MATCH: /* Pass up matched Multicast frames. */ | |
579 | { | |
e163d7f2 | 580 | value = RT_IDX_DST_DFLT_Q | /* dest */ |
c4e84bde RM |
581 | RT_IDX_TYPE_NICQ | /* type */ |
582 | (RT_IDX_MCAST_MATCH_SLOT << RT_IDX_IDX_SHIFT);/* index */ | |
583 | break; | |
584 | } | |
585 | case RT_IDX_RSS_MATCH: /* Pass up matched RSS frames. */ | |
586 | { | |
587 | value = RT_IDX_DST_RSS | /* dest */ | |
588 | RT_IDX_TYPE_NICQ | /* type */ | |
589 | (RT_IDX_RSS_MATCH_SLOT << RT_IDX_IDX_SHIFT);/* index */ | |
590 | break; | |
591 | } | |
592 | case 0: /* Clear the E-bit on an entry. */ | |
593 | { | |
594 | value = RT_IDX_DST_DFLT_Q | /* dest */ | |
595 | RT_IDX_TYPE_NICQ | /* type */ | |
596 | (index << RT_IDX_IDX_SHIFT);/* index */ | |
597 | break; | |
598 | } | |
599 | default: | |
ae9540f7 JP |
600 | netif_err(qdev, ifup, qdev->ndev, |
601 | "Mask type %d not yet supported.\n", mask); | |
c4e84bde RM |
602 | status = -EPERM; |
603 | goto exit; | |
604 | } | |
605 | ||
606 | if (value) { | |
607 | status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, 0); | |
608 | if (status) | |
609 | goto exit; | |
610 | value |= (enable ? RT_IDX_E : 0); | |
611 | ql_write32(qdev, RT_IDX, value); | |
612 | ql_write32(qdev, RT_DATA, enable ? mask : 0); | |
613 | } | |
614 | exit: | |
c4e84bde RM |
615 | return status; |
616 | } | |
617 | ||
618 | static void ql_enable_interrupts(struct ql_adapter *qdev) | |
619 | { | |
620 | ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16) | INTR_EN_EI); | |
621 | } | |
622 | ||
623 | static void ql_disable_interrupts(struct ql_adapter *qdev) | |
624 | { | |
625 | ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16)); | |
626 | } | |
627 | ||
628 | /* If we're running with multiple MSI-X vectors then we enable on the fly. | |
629 | * Otherwise, we may have multiple outstanding workers and don't want to | |
630 | * enable until the last one finishes. In this case, the irq_cnt gets | |
25985edc | 631 | * incremented every time we queue a worker and decremented every time |
c4e84bde RM |
632 | * a worker finishes. Once it hits zero we enable the interrupt. |
633 | */ | |
bb0d215c | 634 | u32 ql_enable_completion_interrupt(struct ql_adapter *qdev, u32 intr) |
c4e84bde | 635 | { |
bb0d215c RM |
636 | u32 var = 0; |
637 | unsigned long hw_flags = 0; | |
638 | struct intr_context *ctx = qdev->intr_context + intr; | |
639 | ||
640 | if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags) && intr)) { | |
641 | /* Always enable if we're MSIX multi interrupts and | |
642 | * it's not the default (zeroeth) interrupt. | |
643 | */ | |
c4e84bde | 644 | ql_write32(qdev, INTR_EN, |
bb0d215c RM |
645 | ctx->intr_en_mask); |
646 | var = ql_read32(qdev, STS); | |
647 | return var; | |
c4e84bde | 648 | } |
bb0d215c RM |
649 | |
650 | spin_lock_irqsave(&qdev->hw_lock, hw_flags); | |
651 | if (atomic_dec_and_test(&ctx->irq_cnt)) { | |
652 | ql_write32(qdev, INTR_EN, | |
653 | ctx->intr_en_mask); | |
654 | var = ql_read32(qdev, STS); | |
655 | } | |
656 | spin_unlock_irqrestore(&qdev->hw_lock, hw_flags); | |
657 | return var; | |
c4e84bde RM |
658 | } |
659 | ||
660 | static u32 ql_disable_completion_interrupt(struct ql_adapter *qdev, u32 intr) | |
661 | { | |
662 | u32 var = 0; | |
bb0d215c | 663 | struct intr_context *ctx; |
c4e84bde | 664 | |
bb0d215c RM |
665 | /* HW disables for us if we're MSIX multi interrupts and |
666 | * it's not the default (zeroeth) interrupt. | |
667 | */ | |
668 | if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags) && intr)) | |
669 | return 0; | |
670 | ||
671 | ctx = qdev->intr_context + intr; | |
08b1bc8f | 672 | spin_lock(&qdev->hw_lock); |
bb0d215c | 673 | if (!atomic_read(&ctx->irq_cnt)) { |
c4e84bde | 674 | ql_write32(qdev, INTR_EN, |
bb0d215c | 675 | ctx->intr_dis_mask); |
c4e84bde RM |
676 | var = ql_read32(qdev, STS); |
677 | } | |
bb0d215c | 678 | atomic_inc(&ctx->irq_cnt); |
08b1bc8f | 679 | spin_unlock(&qdev->hw_lock); |
c4e84bde RM |
680 | return var; |
681 | } | |
682 | ||
683 | static void ql_enable_all_completion_interrupts(struct ql_adapter *qdev) | |
684 | { | |
685 | int i; | |
686 | for (i = 0; i < qdev->intr_count; i++) { | |
687 | /* The enable call does a atomic_dec_and_test | |
688 | * and enables only if the result is zero. | |
689 | * So we precharge it here. | |
690 | */ | |
bb0d215c RM |
691 | if (unlikely(!test_bit(QL_MSIX_ENABLED, &qdev->flags) || |
692 | i == 0)) | |
693 | atomic_set(&qdev->intr_context[i].irq_cnt, 1); | |
c4e84bde RM |
694 | ql_enable_completion_interrupt(qdev, i); |
695 | } | |
696 | ||
697 | } | |
698 | ||
b0c2aadf RM |
699 | static int ql_validate_flash(struct ql_adapter *qdev, u32 size, const char *str) |
700 | { | |
701 | int status, i; | |
702 | u16 csum = 0; | |
703 | __le16 *flash = (__le16 *)&qdev->flash; | |
704 | ||
705 | status = strncmp((char *)&qdev->flash, str, 4); | |
706 | if (status) { | |
ae9540f7 | 707 | netif_err(qdev, ifup, qdev->ndev, "Invalid flash signature.\n"); |
b0c2aadf RM |
708 | return status; |
709 | } | |
710 | ||
711 | for (i = 0; i < size; i++) | |
712 | csum += le16_to_cpu(*flash++); | |
713 | ||
714 | if (csum) | |
ae9540f7 JP |
715 | netif_err(qdev, ifup, qdev->ndev, |
716 | "Invalid flash checksum, csum = 0x%.04x.\n", csum); | |
b0c2aadf RM |
717 | |
718 | return csum; | |
719 | } | |
720 | ||
26351479 | 721 | static int ql_read_flash_word(struct ql_adapter *qdev, int offset, __le32 *data) |
c4e84bde RM |
722 | { |
723 | int status = 0; | |
724 | /* wait for reg to come ready */ | |
725 | status = ql_wait_reg_rdy(qdev, | |
726 | FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR); | |
727 | if (status) | |
728 | goto exit; | |
729 | /* set up for reg read */ | |
730 | ql_write32(qdev, FLASH_ADDR, FLASH_ADDR_R | offset); | |
731 | /* wait for reg to come ready */ | |
732 | status = ql_wait_reg_rdy(qdev, | |
733 | FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR); | |
734 | if (status) | |
735 | goto exit; | |
26351479 RM |
736 | /* This data is stored on flash as an array of |
737 | * __le32. Since ql_read32() returns cpu endian | |
738 | * we need to swap it back. | |
739 | */ | |
740 | *data = cpu_to_le32(ql_read32(qdev, FLASH_DATA)); | |
c4e84bde RM |
741 | exit: |
742 | return status; | |
743 | } | |
744 | ||
cdca8d02 RM |
745 | static int ql_get_8000_flash_params(struct ql_adapter *qdev) |
746 | { | |
747 | u32 i, size; | |
748 | int status; | |
749 | __le32 *p = (__le32 *)&qdev->flash; | |
750 | u32 offset; | |
542512e4 | 751 | u8 mac_addr[6]; |
cdca8d02 RM |
752 | |
753 | /* Get flash offset for function and adjust | |
754 | * for dword access. | |
755 | */ | |
e4552f51 | 756 | if (!qdev->port) |
cdca8d02 RM |
757 | offset = FUNC0_FLASH_OFFSET / sizeof(u32); |
758 | else | |
759 | offset = FUNC1_FLASH_OFFSET / sizeof(u32); | |
760 | ||
761 | if (ql_sem_spinlock(qdev, SEM_FLASH_MASK)) | |
762 | return -ETIMEDOUT; | |
763 | ||
764 | size = sizeof(struct flash_params_8000) / sizeof(u32); | |
765 | for (i = 0; i < size; i++, p++) { | |
766 | status = ql_read_flash_word(qdev, i+offset, p); | |
767 | if (status) { | |
ae9540f7 JP |
768 | netif_err(qdev, ifup, qdev->ndev, |
769 | "Error reading flash.\n"); | |
cdca8d02 RM |
770 | goto exit; |
771 | } | |
772 | } | |
773 | ||
774 | status = ql_validate_flash(qdev, | |
775 | sizeof(struct flash_params_8000) / sizeof(u16), | |
776 | "8000"); | |
777 | if (status) { | |
ae9540f7 | 778 | netif_err(qdev, ifup, qdev->ndev, "Invalid flash.\n"); |
cdca8d02 RM |
779 | status = -EINVAL; |
780 | goto exit; | |
781 | } | |
782 | ||
542512e4 RM |
783 | /* Extract either manufacturer or BOFM modified |
784 | * MAC address. | |
785 | */ | |
786 | if (qdev->flash.flash_params_8000.data_type1 == 2) | |
787 | memcpy(mac_addr, | |
788 | qdev->flash.flash_params_8000.mac_addr1, | |
789 | qdev->ndev->addr_len); | |
790 | else | |
791 | memcpy(mac_addr, | |
792 | qdev->flash.flash_params_8000.mac_addr, | |
793 | qdev->ndev->addr_len); | |
794 | ||
795 | if (!is_valid_ether_addr(mac_addr)) { | |
ae9540f7 | 796 | netif_err(qdev, ifup, qdev->ndev, "Invalid MAC address.\n"); |
cdca8d02 RM |
797 | status = -EINVAL; |
798 | goto exit; | |
799 | } | |
800 | ||
801 | memcpy(qdev->ndev->dev_addr, | |
542512e4 | 802 | mac_addr, |
cdca8d02 RM |
803 | qdev->ndev->addr_len); |
804 | ||
805 | exit: | |
806 | ql_sem_unlock(qdev, SEM_FLASH_MASK); | |
807 | return status; | |
808 | } | |
809 | ||
b0c2aadf | 810 | static int ql_get_8012_flash_params(struct ql_adapter *qdev) |
c4e84bde RM |
811 | { |
812 | int i; | |
813 | int status; | |
26351479 | 814 | __le32 *p = (__le32 *)&qdev->flash; |
e78f5fa7 | 815 | u32 offset = 0; |
b0c2aadf | 816 | u32 size = sizeof(struct flash_params_8012) / sizeof(u32); |
e78f5fa7 RM |
817 | |
818 | /* Second function's parameters follow the first | |
819 | * function's. | |
820 | */ | |
e4552f51 | 821 | if (qdev->port) |
b0c2aadf | 822 | offset = size; |
c4e84bde RM |
823 | |
824 | if (ql_sem_spinlock(qdev, SEM_FLASH_MASK)) | |
825 | return -ETIMEDOUT; | |
826 | ||
b0c2aadf | 827 | for (i = 0; i < size; i++, p++) { |
e78f5fa7 | 828 | status = ql_read_flash_word(qdev, i+offset, p); |
c4e84bde | 829 | if (status) { |
ae9540f7 JP |
830 | netif_err(qdev, ifup, qdev->ndev, |
831 | "Error reading flash.\n"); | |
c4e84bde RM |
832 | goto exit; |
833 | } | |
834 | ||
835 | } | |
b0c2aadf RM |
836 | |
837 | status = ql_validate_flash(qdev, | |
838 | sizeof(struct flash_params_8012) / sizeof(u16), | |
839 | "8012"); | |
840 | if (status) { | |
ae9540f7 | 841 | netif_err(qdev, ifup, qdev->ndev, "Invalid flash.\n"); |
b0c2aadf RM |
842 | status = -EINVAL; |
843 | goto exit; | |
844 | } | |
845 | ||
846 | if (!is_valid_ether_addr(qdev->flash.flash_params_8012.mac_addr)) { | |
847 | status = -EINVAL; | |
848 | goto exit; | |
849 | } | |
850 | ||
851 | memcpy(qdev->ndev->dev_addr, | |
852 | qdev->flash.flash_params_8012.mac_addr, | |
853 | qdev->ndev->addr_len); | |
854 | ||
c4e84bde RM |
855 | exit: |
856 | ql_sem_unlock(qdev, SEM_FLASH_MASK); | |
857 | return status; | |
858 | } | |
859 | ||
860 | /* xgmac register are located behind the xgmac_addr and xgmac_data | |
861 | * register pair. Each read/write requires us to wait for the ready | |
862 | * bit before reading/writing the data. | |
863 | */ | |
864 | static int ql_write_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 data) | |
865 | { | |
866 | int status; | |
867 | /* wait for reg to come ready */ | |
868 | status = ql_wait_reg_rdy(qdev, | |
869 | XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME); | |
870 | if (status) | |
871 | return status; | |
872 | /* write the data to the data reg */ | |
873 | ql_write32(qdev, XGMAC_DATA, data); | |
874 | /* trigger the write */ | |
875 | ql_write32(qdev, XGMAC_ADDR, reg); | |
876 | return status; | |
877 | } | |
878 | ||
879 | /* xgmac register are located behind the xgmac_addr and xgmac_data | |
880 | * register pair. Each read/write requires us to wait for the ready | |
881 | * bit before reading/writing the data. | |
882 | */ | |
883 | int ql_read_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 *data) | |
884 | { | |
885 | int status = 0; | |
886 | /* wait for reg to come ready */ | |
887 | status = ql_wait_reg_rdy(qdev, | |
888 | XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME); | |
889 | if (status) | |
890 | goto exit; | |
891 | /* set up for reg read */ | |
892 | ql_write32(qdev, XGMAC_ADDR, reg | XGMAC_ADDR_R); | |
893 | /* wait for reg to come ready */ | |
894 | status = ql_wait_reg_rdy(qdev, | |
895 | XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME); | |
896 | if (status) | |
897 | goto exit; | |
898 | /* get the data */ | |
899 | *data = ql_read32(qdev, XGMAC_DATA); | |
900 | exit: | |
901 | return status; | |
902 | } | |
903 | ||
904 | /* This is used for reading the 64-bit statistics regs. */ | |
905 | int ql_read_xgmac_reg64(struct ql_adapter *qdev, u32 reg, u64 *data) | |
906 | { | |
907 | int status = 0; | |
908 | u32 hi = 0; | |
909 | u32 lo = 0; | |
910 | ||
911 | status = ql_read_xgmac_reg(qdev, reg, &lo); | |
912 | if (status) | |
913 | goto exit; | |
914 | ||
915 | status = ql_read_xgmac_reg(qdev, reg + 4, &hi); | |
916 | if (status) | |
917 | goto exit; | |
918 | ||
919 | *data = (u64) lo | ((u64) hi << 32); | |
920 | ||
921 | exit: | |
922 | return status; | |
923 | } | |
924 | ||
cdca8d02 RM |
925 | static int ql_8000_port_initialize(struct ql_adapter *qdev) |
926 | { | |
bcc2cb3b | 927 | int status; |
cfec0cbc RM |
928 | /* |
929 | * Get MPI firmware version for driver banner | |
930 | * and ethool info. | |
931 | */ | |
932 | status = ql_mb_about_fw(qdev); | |
933 | if (status) | |
934 | goto exit; | |
bcc2cb3b RM |
935 | status = ql_mb_get_fw_state(qdev); |
936 | if (status) | |
937 | goto exit; | |
938 | /* Wake up a worker to get/set the TX/RX frame sizes. */ | |
939 | queue_delayed_work(qdev->workqueue, &qdev->mpi_port_cfg_work, 0); | |
940 | exit: | |
941 | return status; | |
cdca8d02 RM |
942 | } |
943 | ||
c4e84bde RM |
944 | /* Take the MAC Core out of reset. |
945 | * Enable statistics counting. | |
946 | * Take the transmitter/receiver out of reset. | |
947 | * This functionality may be done in the MPI firmware at a | |
948 | * later date. | |
949 | */ | |
b0c2aadf | 950 | static int ql_8012_port_initialize(struct ql_adapter *qdev) |
c4e84bde RM |
951 | { |
952 | int status = 0; | |
953 | u32 data; | |
954 | ||
955 | if (ql_sem_trylock(qdev, qdev->xg_sem_mask)) { | |
956 | /* Another function has the semaphore, so | |
957 | * wait for the port init bit to come ready. | |
958 | */ | |
ae9540f7 JP |
959 | netif_info(qdev, link, qdev->ndev, |
960 | "Another function has the semaphore, so wait for the port init bit to come ready.\n"); | |
c4e84bde RM |
961 | status = ql_wait_reg_rdy(qdev, STS, qdev->port_init, 0); |
962 | if (status) { | |
ae9540f7 JP |
963 | netif_crit(qdev, link, qdev->ndev, |
964 | "Port initialize timed out.\n"); | |
c4e84bde RM |
965 | } |
966 | return status; | |
967 | } | |
968 | ||
ae9540f7 | 969 | netif_info(qdev, link, qdev->ndev, "Got xgmac semaphore!.\n"); |
c4e84bde RM |
970 | /* Set the core reset. */ |
971 | status = ql_read_xgmac_reg(qdev, GLOBAL_CFG, &data); | |
972 | if (status) | |
973 | goto end; | |
974 | data |= GLOBAL_CFG_RESET; | |
975 | status = ql_write_xgmac_reg(qdev, GLOBAL_CFG, data); | |
976 | if (status) | |
977 | goto end; | |
978 | ||
979 | /* Clear the core reset and turn on jumbo for receiver. */ | |
980 | data &= ~GLOBAL_CFG_RESET; /* Clear core reset. */ | |
981 | data |= GLOBAL_CFG_JUMBO; /* Turn on jumbo. */ | |
982 | data |= GLOBAL_CFG_TX_STAT_EN; | |
983 | data |= GLOBAL_CFG_RX_STAT_EN; | |
984 | status = ql_write_xgmac_reg(qdev, GLOBAL_CFG, data); | |
985 | if (status) | |
986 | goto end; | |
987 | ||
988 | /* Enable transmitter, and clear it's reset. */ | |
989 | status = ql_read_xgmac_reg(qdev, TX_CFG, &data); | |
990 | if (status) | |
991 | goto end; | |
992 | data &= ~TX_CFG_RESET; /* Clear the TX MAC reset. */ | |
993 | data |= TX_CFG_EN; /* Enable the transmitter. */ | |
994 | status = ql_write_xgmac_reg(qdev, TX_CFG, data); | |
995 | if (status) | |
996 | goto end; | |
997 | ||
998 | /* Enable receiver and clear it's reset. */ | |
999 | status = ql_read_xgmac_reg(qdev, RX_CFG, &data); | |
1000 | if (status) | |
1001 | goto end; | |
1002 | data &= ~RX_CFG_RESET; /* Clear the RX MAC reset. */ | |
1003 | data |= RX_CFG_EN; /* Enable the receiver. */ | |
1004 | status = ql_write_xgmac_reg(qdev, RX_CFG, data); | |
1005 | if (status) | |
1006 | goto end; | |
1007 | ||
1008 | /* Turn on jumbo. */ | |
1009 | status = | |
1010 | ql_write_xgmac_reg(qdev, MAC_TX_PARAMS, MAC_TX_PARAMS_JUMBO | (0x2580 << 16)); | |
1011 | if (status) | |
1012 | goto end; | |
1013 | status = | |
1014 | ql_write_xgmac_reg(qdev, MAC_RX_PARAMS, 0x2580); | |
1015 | if (status) | |
1016 | goto end; | |
1017 | ||
1018 | /* Signal to the world that the port is enabled. */ | |
1019 | ql_write32(qdev, STS, ((qdev->port_init << 16) | qdev->port_init)); | |
1020 | end: | |
1021 | ql_sem_unlock(qdev, qdev->xg_sem_mask); | |
1022 | return status; | |
1023 | } | |
1024 | ||
7c734359 RM |
1025 | static inline unsigned int ql_lbq_block_size(struct ql_adapter *qdev) |
1026 | { | |
1027 | return PAGE_SIZE << qdev->lbq_buf_order; | |
1028 | } | |
1029 | ||
c4e84bde | 1030 | /* Get the next large buffer. */ |
8668ae92 | 1031 | static struct bq_desc *ql_get_curr_lbuf(struct rx_ring *rx_ring) |
c4e84bde RM |
1032 | { |
1033 | struct bq_desc *lbq_desc = &rx_ring->lbq[rx_ring->lbq_curr_idx]; | |
1034 | rx_ring->lbq_curr_idx++; | |
1035 | if (rx_ring->lbq_curr_idx == rx_ring->lbq_len) | |
1036 | rx_ring->lbq_curr_idx = 0; | |
1037 | rx_ring->lbq_free_cnt++; | |
1038 | return lbq_desc; | |
1039 | } | |
1040 | ||
7c734359 RM |
1041 | static struct bq_desc *ql_get_curr_lchunk(struct ql_adapter *qdev, |
1042 | struct rx_ring *rx_ring) | |
1043 | { | |
1044 | struct bq_desc *lbq_desc = ql_get_curr_lbuf(rx_ring); | |
1045 | ||
1046 | pci_dma_sync_single_for_cpu(qdev->pdev, | |
64b9b41d | 1047 | dma_unmap_addr(lbq_desc, mapaddr), |
7c734359 RM |
1048 | rx_ring->lbq_buf_size, |
1049 | PCI_DMA_FROMDEVICE); | |
1050 | ||
1051 | /* If it's the last chunk of our master page then | |
1052 | * we unmap it. | |
1053 | */ | |
1054 | if ((lbq_desc->p.pg_chunk.offset + rx_ring->lbq_buf_size) | |
1055 | == ql_lbq_block_size(qdev)) | |
1056 | pci_unmap_page(qdev->pdev, | |
1057 | lbq_desc->p.pg_chunk.map, | |
1058 | ql_lbq_block_size(qdev), | |
1059 | PCI_DMA_FROMDEVICE); | |
1060 | return lbq_desc; | |
1061 | } | |
1062 | ||
c4e84bde | 1063 | /* Get the next small buffer. */ |
8668ae92 | 1064 | static struct bq_desc *ql_get_curr_sbuf(struct rx_ring *rx_ring) |
c4e84bde RM |
1065 | { |
1066 | struct bq_desc *sbq_desc = &rx_ring->sbq[rx_ring->sbq_curr_idx]; | |
1067 | rx_ring->sbq_curr_idx++; | |
1068 | if (rx_ring->sbq_curr_idx == rx_ring->sbq_len) | |
1069 | rx_ring->sbq_curr_idx = 0; | |
1070 | rx_ring->sbq_free_cnt++; | |
1071 | return sbq_desc; | |
1072 | } | |
1073 | ||
1074 | /* Update an rx ring index. */ | |
1075 | static void ql_update_cq(struct rx_ring *rx_ring) | |
1076 | { | |
1077 | rx_ring->cnsmr_idx++; | |
1078 | rx_ring->curr_entry++; | |
1079 | if (unlikely(rx_ring->cnsmr_idx == rx_ring->cq_len)) { | |
1080 | rx_ring->cnsmr_idx = 0; | |
1081 | rx_ring->curr_entry = rx_ring->cq_base; | |
1082 | } | |
1083 | } | |
1084 | ||
1085 | static void ql_write_cq_idx(struct rx_ring *rx_ring) | |
1086 | { | |
1087 | ql_write_db_reg(rx_ring->cnsmr_idx, rx_ring->cnsmr_idx_db_reg); | |
1088 | } | |
1089 | ||
7c734359 RM |
1090 | static int ql_get_next_chunk(struct ql_adapter *qdev, struct rx_ring *rx_ring, |
1091 | struct bq_desc *lbq_desc) | |
1092 | { | |
1093 | if (!rx_ring->pg_chunk.page) { | |
1094 | u64 map; | |
453f85d4 | 1095 | rx_ring->pg_chunk.page = alloc_pages(__GFP_COMP | GFP_ATOMIC, |
7c734359 RM |
1096 | qdev->lbq_buf_order); |
1097 | if (unlikely(!rx_ring->pg_chunk.page)) { | |
ae9540f7 JP |
1098 | netif_err(qdev, drv, qdev->ndev, |
1099 | "page allocation failed.\n"); | |
7c734359 RM |
1100 | return -ENOMEM; |
1101 | } | |
1102 | rx_ring->pg_chunk.offset = 0; | |
1103 | map = pci_map_page(qdev->pdev, rx_ring->pg_chunk.page, | |
1104 | 0, ql_lbq_block_size(qdev), | |
1105 | PCI_DMA_FROMDEVICE); | |
1106 | if (pci_dma_mapping_error(qdev->pdev, map)) { | |
1107 | __free_pages(rx_ring->pg_chunk.page, | |
1108 | qdev->lbq_buf_order); | |
ef380794 | 1109 | rx_ring->pg_chunk.page = NULL; |
ae9540f7 JP |
1110 | netif_err(qdev, drv, qdev->ndev, |
1111 | "PCI mapping failed.\n"); | |
7c734359 RM |
1112 | return -ENOMEM; |
1113 | } | |
1114 | rx_ring->pg_chunk.map = map; | |
1115 | rx_ring->pg_chunk.va = page_address(rx_ring->pg_chunk.page); | |
1116 | } | |
1117 | ||
1118 | /* Copy the current master pg_chunk info | |
1119 | * to the current descriptor. | |
1120 | */ | |
1121 | lbq_desc->p.pg_chunk = rx_ring->pg_chunk; | |
1122 | ||
1123 | /* Adjust the master page chunk for next | |
1124 | * buffer get. | |
1125 | */ | |
1126 | rx_ring->pg_chunk.offset += rx_ring->lbq_buf_size; | |
1127 | if (rx_ring->pg_chunk.offset == ql_lbq_block_size(qdev)) { | |
1128 | rx_ring->pg_chunk.page = NULL; | |
1129 | lbq_desc->p.pg_chunk.last_flag = 1; | |
1130 | } else { | |
1131 | rx_ring->pg_chunk.va += rx_ring->lbq_buf_size; | |
1132 | get_page(rx_ring->pg_chunk.page); | |
1133 | lbq_desc->p.pg_chunk.last_flag = 0; | |
1134 | } | |
1135 | return 0; | |
1136 | } | |
c4e84bde RM |
1137 | /* Process (refill) a large buffer queue. */ |
1138 | static void ql_update_lbq(struct ql_adapter *qdev, struct rx_ring *rx_ring) | |
1139 | { | |
49f2186d RM |
1140 | u32 clean_idx = rx_ring->lbq_clean_idx; |
1141 | u32 start_idx = clean_idx; | |
c4e84bde | 1142 | struct bq_desc *lbq_desc; |
c4e84bde RM |
1143 | u64 map; |
1144 | int i; | |
1145 | ||
7c734359 | 1146 | while (rx_ring->lbq_free_cnt > 32) { |
81f25d96 | 1147 | for (i = (rx_ring->lbq_clean_idx % 16); i < 16; i++) { |
ae9540f7 JP |
1148 | netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev, |
1149 | "lbq: try cleaning clean_idx = %d.\n", | |
1150 | clean_idx); | |
c4e84bde | 1151 | lbq_desc = &rx_ring->lbq[clean_idx]; |
7c734359 | 1152 | if (ql_get_next_chunk(qdev, rx_ring, lbq_desc)) { |
81f25d96 | 1153 | rx_ring->lbq_clean_idx = clean_idx; |
ae9540f7 | 1154 | netif_err(qdev, ifup, qdev->ndev, |
81f25d96 JK |
1155 | "Could not get a page chunk, i=%d, clean_idx =%d .\n", |
1156 | i, clean_idx); | |
ae9540f7 JP |
1157 | return; |
1158 | } | |
7c734359 RM |
1159 | |
1160 | map = lbq_desc->p.pg_chunk.map + | |
1161 | lbq_desc->p.pg_chunk.offset; | |
64b9b41d FT |
1162 | dma_unmap_addr_set(lbq_desc, mapaddr, map); |
1163 | dma_unmap_len_set(lbq_desc, maplen, | |
7c734359 | 1164 | rx_ring->lbq_buf_size); |
2c9a0d41 | 1165 | *lbq_desc->addr = cpu_to_le64(map); |
7c734359 RM |
1166 | |
1167 | pci_dma_sync_single_for_device(qdev->pdev, map, | |
1168 | rx_ring->lbq_buf_size, | |
1169 | PCI_DMA_FROMDEVICE); | |
c4e84bde RM |
1170 | clean_idx++; |
1171 | if (clean_idx == rx_ring->lbq_len) | |
1172 | clean_idx = 0; | |
1173 | } | |
1174 | ||
1175 | rx_ring->lbq_clean_idx = clean_idx; | |
1176 | rx_ring->lbq_prod_idx += 16; | |
1177 | if (rx_ring->lbq_prod_idx == rx_ring->lbq_len) | |
1178 | rx_ring->lbq_prod_idx = 0; | |
49f2186d RM |
1179 | rx_ring->lbq_free_cnt -= 16; |
1180 | } | |
1181 | ||
1182 | if (start_idx != clean_idx) { | |
ae9540f7 JP |
1183 | netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev, |
1184 | "lbq: updating prod idx = %d.\n", | |
1185 | rx_ring->lbq_prod_idx); | |
c4e84bde RM |
1186 | ql_write_db_reg(rx_ring->lbq_prod_idx, |
1187 | rx_ring->lbq_prod_idx_db_reg); | |
c4e84bde RM |
1188 | } |
1189 | } | |
1190 | ||
1191 | /* Process (refill) a small buffer queue. */ | |
1192 | static void ql_update_sbq(struct ql_adapter *qdev, struct rx_ring *rx_ring) | |
1193 | { | |
49f2186d RM |
1194 | u32 clean_idx = rx_ring->sbq_clean_idx; |
1195 | u32 start_idx = clean_idx; | |
c4e84bde | 1196 | struct bq_desc *sbq_desc; |
c4e84bde RM |
1197 | u64 map; |
1198 | int i; | |
1199 | ||
1200 | while (rx_ring->sbq_free_cnt > 16) { | |
81f25d96 | 1201 | for (i = (rx_ring->sbq_clean_idx % 16); i < 16; i++) { |
c4e84bde | 1202 | sbq_desc = &rx_ring->sbq[clean_idx]; |
ae9540f7 JP |
1203 | netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev, |
1204 | "sbq: try cleaning clean_idx = %d.\n", | |
1205 | clean_idx); | |
c4e84bde | 1206 | if (sbq_desc->p.skb == NULL) { |
ae9540f7 JP |
1207 | netif_printk(qdev, rx_status, KERN_DEBUG, |
1208 | qdev->ndev, | |
1209 | "sbq: getting new skb for index %d.\n", | |
1210 | sbq_desc->index); | |
c4e84bde RM |
1211 | sbq_desc->p.skb = |
1212 | netdev_alloc_skb(qdev->ndev, | |
52e55f3c | 1213 | SMALL_BUFFER_SIZE); |
c4e84bde | 1214 | if (sbq_desc->p.skb == NULL) { |
c4e84bde RM |
1215 | rx_ring->sbq_clean_idx = clean_idx; |
1216 | return; | |
1217 | } | |
1218 | skb_reserve(sbq_desc->p.skb, QLGE_SB_PAD); | |
1219 | map = pci_map_single(qdev->pdev, | |
1220 | sbq_desc->p.skb->data, | |
52e55f3c RM |
1221 | rx_ring->sbq_buf_size, |
1222 | PCI_DMA_FROMDEVICE); | |
c907a35a | 1223 | if (pci_dma_mapping_error(qdev->pdev, map)) { |
ae9540f7 JP |
1224 | netif_err(qdev, ifup, qdev->ndev, |
1225 | "PCI mapping failed.\n"); | |
c907a35a | 1226 | rx_ring->sbq_clean_idx = clean_idx; |
06a3d510 RM |
1227 | dev_kfree_skb_any(sbq_desc->p.skb); |
1228 | sbq_desc->p.skb = NULL; | |
c907a35a RM |
1229 | return; |
1230 | } | |
64b9b41d FT |
1231 | dma_unmap_addr_set(sbq_desc, mapaddr, map); |
1232 | dma_unmap_len_set(sbq_desc, maplen, | |
52e55f3c | 1233 | rx_ring->sbq_buf_size); |
2c9a0d41 | 1234 | *sbq_desc->addr = cpu_to_le64(map); |
c4e84bde RM |
1235 | } |
1236 | ||
1237 | clean_idx++; | |
1238 | if (clean_idx == rx_ring->sbq_len) | |
1239 | clean_idx = 0; | |
1240 | } | |
1241 | rx_ring->sbq_clean_idx = clean_idx; | |
1242 | rx_ring->sbq_prod_idx += 16; | |
1243 | if (rx_ring->sbq_prod_idx == rx_ring->sbq_len) | |
1244 | rx_ring->sbq_prod_idx = 0; | |
49f2186d RM |
1245 | rx_ring->sbq_free_cnt -= 16; |
1246 | } | |
1247 | ||
1248 | if (start_idx != clean_idx) { | |
ae9540f7 JP |
1249 | netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev, |
1250 | "sbq: updating prod idx = %d.\n", | |
1251 | rx_ring->sbq_prod_idx); | |
c4e84bde RM |
1252 | ql_write_db_reg(rx_ring->sbq_prod_idx, |
1253 | rx_ring->sbq_prod_idx_db_reg); | |
c4e84bde RM |
1254 | } |
1255 | } | |
1256 | ||
1257 | static void ql_update_buffer_queues(struct ql_adapter *qdev, | |
1258 | struct rx_ring *rx_ring) | |
1259 | { | |
1260 | ql_update_sbq(qdev, rx_ring); | |
1261 | ql_update_lbq(qdev, rx_ring); | |
1262 | } | |
1263 | ||
1264 | /* Unmaps tx buffers. Can be called from send() if a pci mapping | |
1265 | * fails at some stage, or from the interrupt when a tx completes. | |
1266 | */ | |
1267 | static void ql_unmap_send(struct ql_adapter *qdev, | |
1268 | struct tx_ring_desc *tx_ring_desc, int mapped) | |
1269 | { | |
1270 | int i; | |
1271 | for (i = 0; i < mapped; i++) { | |
1272 | if (i == 0 || (i == 7 && mapped > 7)) { | |
1273 | /* | |
1274 | * Unmap the skb->data area, or the | |
1275 | * external sglist (AKA the Outbound | |
1276 | * Address List (OAL)). | |
1277 | * If its the zeroeth element, then it's | |
1278 | * the skb->data area. If it's the 7th | |
1279 | * element and there is more than 6 frags, | |
1280 | * then its an OAL. | |
1281 | */ | |
1282 | if (i == 7) { | |
ae9540f7 JP |
1283 | netif_printk(qdev, tx_done, KERN_DEBUG, |
1284 | qdev->ndev, | |
1285 | "unmapping OAL area.\n"); | |
c4e84bde RM |
1286 | } |
1287 | pci_unmap_single(qdev->pdev, | |
64b9b41d | 1288 | dma_unmap_addr(&tx_ring_desc->map[i], |
c4e84bde | 1289 | mapaddr), |
64b9b41d | 1290 | dma_unmap_len(&tx_ring_desc->map[i], |
c4e84bde RM |
1291 | maplen), |
1292 | PCI_DMA_TODEVICE); | |
1293 | } else { | |
ae9540f7 JP |
1294 | netif_printk(qdev, tx_done, KERN_DEBUG, qdev->ndev, |
1295 | "unmapping frag %d.\n", i); | |
c4e84bde | 1296 | pci_unmap_page(qdev->pdev, |
64b9b41d | 1297 | dma_unmap_addr(&tx_ring_desc->map[i], |
c4e84bde | 1298 | mapaddr), |
64b9b41d | 1299 | dma_unmap_len(&tx_ring_desc->map[i], |
c4e84bde RM |
1300 | maplen), PCI_DMA_TODEVICE); |
1301 | } | |
1302 | } | |
1303 | ||
1304 | } | |
1305 | ||
1306 | /* Map the buffers for this transmit. This will return | |
1307 | * NETDEV_TX_BUSY or NETDEV_TX_OK based on success. | |
1308 | */ | |
1309 | static int ql_map_send(struct ql_adapter *qdev, | |
1310 | struct ob_mac_iocb_req *mac_iocb_ptr, | |
1311 | struct sk_buff *skb, struct tx_ring_desc *tx_ring_desc) | |
1312 | { | |
1313 | int len = skb_headlen(skb); | |
1314 | dma_addr_t map; | |
1315 | int frag_idx, err, map_idx = 0; | |
1316 | struct tx_buf_desc *tbd = mac_iocb_ptr->tbd; | |
1317 | int frag_cnt = skb_shinfo(skb)->nr_frags; | |
1318 | ||
1319 | if (frag_cnt) { | |
ae9540f7 JP |
1320 | netif_printk(qdev, tx_queued, KERN_DEBUG, qdev->ndev, |
1321 | "frag_cnt = %d.\n", frag_cnt); | |
c4e84bde RM |
1322 | } |
1323 | /* | |
1324 | * Map the skb buffer first. | |
1325 | */ | |
1326 | map = pci_map_single(qdev->pdev, skb->data, len, PCI_DMA_TODEVICE); | |
1327 | ||
1328 | err = pci_dma_mapping_error(qdev->pdev, map); | |
1329 | if (err) { | |
ae9540f7 JP |
1330 | netif_err(qdev, tx_queued, qdev->ndev, |
1331 | "PCI mapping failed with error: %d\n", err); | |
c4e84bde RM |
1332 | |
1333 | return NETDEV_TX_BUSY; | |
1334 | } | |
1335 | ||
1336 | tbd->len = cpu_to_le32(len); | |
1337 | tbd->addr = cpu_to_le64(map); | |
64b9b41d FT |
1338 | dma_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr, map); |
1339 | dma_unmap_len_set(&tx_ring_desc->map[map_idx], maplen, len); | |
c4e84bde RM |
1340 | map_idx++; |
1341 | ||
1342 | /* | |
1343 | * This loop fills the remainder of the 8 address descriptors | |
1344 | * in the IOCB. If there are more than 7 fragments, then the | |
1345 | * eighth address desc will point to an external list (OAL). | |
1346 | * When this happens, the remainder of the frags will be stored | |
1347 | * in this list. | |
1348 | */ | |
1349 | for (frag_idx = 0; frag_idx < frag_cnt; frag_idx++, map_idx++) { | |
1350 | skb_frag_t *frag = &skb_shinfo(skb)->frags[frag_idx]; | |
1351 | tbd++; | |
1352 | if (frag_idx == 6 && frag_cnt > 7) { | |
1353 | /* Let's tack on an sglist. | |
1354 | * Our control block will now | |
1355 | * look like this: | |
1356 | * iocb->seg[0] = skb->data | |
1357 | * iocb->seg[1] = frag[0] | |
1358 | * iocb->seg[2] = frag[1] | |
1359 | * iocb->seg[3] = frag[2] | |
1360 | * iocb->seg[4] = frag[3] | |
1361 | * iocb->seg[5] = frag[4] | |
1362 | * iocb->seg[6] = frag[5] | |
1363 | * iocb->seg[7] = ptr to OAL (external sglist) | |
1364 | * oal->seg[0] = frag[6] | |
1365 | * oal->seg[1] = frag[7] | |
1366 | * oal->seg[2] = frag[8] | |
1367 | * oal->seg[3] = frag[9] | |
1368 | * oal->seg[4] = frag[10] | |
1369 | * etc... | |
1370 | */ | |
1371 | /* Tack on the OAL in the eighth segment of IOCB. */ | |
1372 | map = pci_map_single(qdev->pdev, &tx_ring_desc->oal, | |
1373 | sizeof(struct oal), | |
1374 | PCI_DMA_TODEVICE); | |
1375 | err = pci_dma_mapping_error(qdev->pdev, map); | |
1376 | if (err) { | |
ae9540f7 JP |
1377 | netif_err(qdev, tx_queued, qdev->ndev, |
1378 | "PCI mapping outbound address list with error: %d\n", | |
1379 | err); | |
c4e84bde RM |
1380 | goto map_error; |
1381 | } | |
1382 | ||
1383 | tbd->addr = cpu_to_le64(map); | |
1384 | /* | |
1385 | * The length is the number of fragments | |
1386 | * that remain to be mapped times the length | |
1387 | * of our sglist (OAL). | |
1388 | */ | |
1389 | tbd->len = | |
1390 | cpu_to_le32((sizeof(struct tx_buf_desc) * | |
1391 | (frag_cnt - frag_idx)) | TX_DESC_C); | |
64b9b41d | 1392 | dma_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr, |
c4e84bde | 1393 | map); |
64b9b41d | 1394 | dma_unmap_len_set(&tx_ring_desc->map[map_idx], maplen, |
c4e84bde RM |
1395 | sizeof(struct oal)); |
1396 | tbd = (struct tx_buf_desc *)&tx_ring_desc->oal; | |
1397 | map_idx++; | |
1398 | } | |
1399 | ||
9e903e08 | 1400 | map = skb_frag_dma_map(&qdev->pdev->dev, frag, 0, skb_frag_size(frag), |
5d6bcdfe | 1401 | DMA_TO_DEVICE); |
c4e84bde | 1402 | |
5d6bcdfe | 1403 | err = dma_mapping_error(&qdev->pdev->dev, map); |
c4e84bde | 1404 | if (err) { |
ae9540f7 JP |
1405 | netif_err(qdev, tx_queued, qdev->ndev, |
1406 | "PCI mapping frags failed with error: %d.\n", | |
1407 | err); | |
c4e84bde RM |
1408 | goto map_error; |
1409 | } | |
1410 | ||
1411 | tbd->addr = cpu_to_le64(map); | |
9e903e08 | 1412 | tbd->len = cpu_to_le32(skb_frag_size(frag)); |
64b9b41d FT |
1413 | dma_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr, map); |
1414 | dma_unmap_len_set(&tx_ring_desc->map[map_idx], maplen, | |
9e903e08 | 1415 | skb_frag_size(frag)); |
c4e84bde RM |
1416 | |
1417 | } | |
1418 | /* Save the number of segments we've mapped. */ | |
1419 | tx_ring_desc->map_cnt = map_idx; | |
1420 | /* Terminate the last segment. */ | |
1421 | tbd->len = cpu_to_le32(le32_to_cpu(tbd->len) | TX_DESC_E); | |
1422 | return NETDEV_TX_OK; | |
1423 | ||
1424 | map_error: | |
1425 | /* | |
1426 | * If the first frag mapping failed, then i will be zero. | |
1427 | * This causes the unmap of the skb->data area. Otherwise | |
1428 | * we pass in the number of frags that mapped successfully | |
1429 | * so they can be umapped. | |
1430 | */ | |
1431 | ql_unmap_send(qdev, tx_ring_desc, map_idx); | |
1432 | return NETDEV_TX_BUSY; | |
1433 | } | |
1434 | ||
433c88e8 | 1435 | /* Categorizing receive firmware frame errors */ |
ae721f3a SV |
1436 | static void ql_categorize_rx_err(struct ql_adapter *qdev, u8 rx_err, |
1437 | struct rx_ring *rx_ring) | |
433c88e8 JK |
1438 | { |
1439 | struct nic_stats *stats = &qdev->nic_stats; | |
1440 | ||
1441 | stats->rx_err_count++; | |
ae721f3a | 1442 | rx_ring->rx_errors++; |
433c88e8 JK |
1443 | |
1444 | switch (rx_err & IB_MAC_IOCB_RSP_ERR_MASK) { | |
1445 | case IB_MAC_IOCB_RSP_ERR_CODE_ERR: | |
1446 | stats->rx_code_err++; | |
1447 | break; | |
1448 | case IB_MAC_IOCB_RSP_ERR_OVERSIZE: | |
1449 | stats->rx_oversize_err++; | |
1450 | break; | |
1451 | case IB_MAC_IOCB_RSP_ERR_UNDERSIZE: | |
1452 | stats->rx_undersize_err++; | |
1453 | break; | |
1454 | case IB_MAC_IOCB_RSP_ERR_PREAMBLE: | |
1455 | stats->rx_preamble_err++; | |
1456 | break; | |
1457 | case IB_MAC_IOCB_RSP_ERR_FRAME_LEN: | |
1458 | stats->rx_frame_len_err++; | |
1459 | break; | |
1460 | case IB_MAC_IOCB_RSP_ERR_CRC: | |
1461 | stats->rx_crc_err++; | |
1462 | default: | |
1463 | break; | |
1464 | } | |
1465 | } | |
1466 | ||
a45adbe8 JK |
1467 | /** |
1468 | * ql_update_mac_hdr_len - helper routine to update the mac header length | |
1469 | * based on vlan tags if present | |
1470 | */ | |
1471 | static void ql_update_mac_hdr_len(struct ql_adapter *qdev, | |
1472 | struct ib_mac_iocb_rsp *ib_mac_rsp, | |
1473 | void *page, size_t *len) | |
1474 | { | |
1475 | u16 *tags; | |
1476 | ||
1477 | if (qdev->ndev->features & NETIF_F_HW_VLAN_CTAG_RX) | |
1478 | return; | |
1479 | if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) { | |
1480 | tags = (u16 *)page; | |
1481 | /* Look for stacked vlan tags in ethertype field */ | |
1482 | if (tags[6] == ETH_P_8021Q && | |
1483 | tags[8] == ETH_P_8021Q) | |
1484 | *len += 2 * VLAN_HLEN; | |
1485 | else | |
1486 | *len += VLAN_HLEN; | |
1487 | } | |
1488 | } | |
1489 | ||
63526713 RM |
1490 | /* Process an inbound completion from an rx ring. */ |
1491 | static void ql_process_mac_rx_gro_page(struct ql_adapter *qdev, | |
1492 | struct rx_ring *rx_ring, | |
1493 | struct ib_mac_iocb_rsp *ib_mac_rsp, | |
1494 | u32 length, | |
1495 | u16 vlan_id) | |
1496 | { | |
1497 | struct sk_buff *skb; | |
1498 | struct bq_desc *lbq_desc = ql_get_curr_lchunk(qdev, rx_ring); | |
63526713 RM |
1499 | struct napi_struct *napi = &rx_ring->napi; |
1500 | ||
ae721f3a SV |
1501 | /* Frame error, so drop the packet. */ |
1502 | if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_ERR_MASK) { | |
1503 | ql_categorize_rx_err(qdev, ib_mac_rsp->flags2, rx_ring); | |
1504 | put_page(lbq_desc->p.pg_chunk.page); | |
1505 | return; | |
1506 | } | |
63526713 RM |
1507 | napi->dev = qdev->ndev; |
1508 | ||
1509 | skb = napi_get_frags(napi); | |
1510 | if (!skb) { | |
ae9540f7 JP |
1511 | netif_err(qdev, drv, qdev->ndev, |
1512 | "Couldn't get an skb, exiting.\n"); | |
63526713 RM |
1513 | rx_ring->rx_dropped++; |
1514 | put_page(lbq_desc->p.pg_chunk.page); | |
1515 | return; | |
1516 | } | |
1517 | prefetch(lbq_desc->p.pg_chunk.va); | |
da7ebfd7 IC |
1518 | __skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags, |
1519 | lbq_desc->p.pg_chunk.page, | |
1520 | lbq_desc->p.pg_chunk.offset, | |
1521 | length); | |
63526713 RM |
1522 | |
1523 | skb->len += length; | |
1524 | skb->data_len += length; | |
1525 | skb->truesize += length; | |
1526 | skb_shinfo(skb)->nr_frags++; | |
1527 | ||
1528 | rx_ring->rx_packets++; | |
1529 | rx_ring->rx_bytes += length; | |
1530 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
1531 | skb_record_rx_queue(skb, rx_ring->cq_id); | |
18c49b91 | 1532 | if (vlan_id != 0xffff) |
86a9bad3 | 1533 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_id); |
18c49b91 | 1534 | napi_gro_frags(napi); |
63526713 RM |
1535 | } |
1536 | ||
4f848c0a RM |
1537 | /* Process an inbound completion from an rx ring. */ |
1538 | static void ql_process_mac_rx_page(struct ql_adapter *qdev, | |
1539 | struct rx_ring *rx_ring, | |
1540 | struct ib_mac_iocb_rsp *ib_mac_rsp, | |
1541 | u32 length, | |
1542 | u16 vlan_id) | |
1543 | { | |
1544 | struct net_device *ndev = qdev->ndev; | |
1545 | struct sk_buff *skb = NULL; | |
1546 | void *addr; | |
1547 | struct bq_desc *lbq_desc = ql_get_curr_lchunk(qdev, rx_ring); | |
1548 | struct napi_struct *napi = &rx_ring->napi; | |
a45adbe8 | 1549 | size_t hlen = ETH_HLEN; |
4f848c0a RM |
1550 | |
1551 | skb = netdev_alloc_skb(ndev, length); | |
1552 | if (!skb) { | |
4f848c0a RM |
1553 | rx_ring->rx_dropped++; |
1554 | put_page(lbq_desc->p.pg_chunk.page); | |
1555 | return; | |
1556 | } | |
1557 | ||
1558 | addr = lbq_desc->p.pg_chunk.va; | |
1559 | prefetch(addr); | |
1560 | ||
ae721f3a SV |
1561 | /* Frame error, so drop the packet. */ |
1562 | if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_ERR_MASK) { | |
1563 | ql_categorize_rx_err(qdev, ib_mac_rsp->flags2, rx_ring); | |
1564 | goto err_out; | |
1565 | } | |
1566 | ||
a45adbe8 JK |
1567 | /* Update the MAC header length*/ |
1568 | ql_update_mac_hdr_len(qdev, ib_mac_rsp, addr, &hlen); | |
1569 | ||
4f848c0a RM |
1570 | /* The max framesize filter on this chip is set higher than |
1571 | * MTU since FCoE uses 2k frames. | |
1572 | */ | |
a45adbe8 | 1573 | if (skb->len > ndev->mtu + hlen) { |
ae9540f7 JP |
1574 | netif_err(qdev, drv, qdev->ndev, |
1575 | "Segment too small, dropping.\n"); | |
4f848c0a RM |
1576 | rx_ring->rx_dropped++; |
1577 | goto err_out; | |
1578 | } | |
59ae1d12 | 1579 | skb_put_data(skb, addr, hlen); |
ae9540f7 JP |
1580 | netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev, |
1581 | "%d bytes of headers and data in large. Chain page to new skb and pull tail.\n", | |
1582 | length); | |
4f848c0a | 1583 | skb_fill_page_desc(skb, 0, lbq_desc->p.pg_chunk.page, |
a45adbe8 JK |
1584 | lbq_desc->p.pg_chunk.offset + hlen, |
1585 | length - hlen); | |
1586 | skb->len += length - hlen; | |
1587 | skb->data_len += length - hlen; | |
1588 | skb->truesize += length - hlen; | |
4f848c0a RM |
1589 | |
1590 | rx_ring->rx_packets++; | |
1591 | rx_ring->rx_bytes += skb->len; | |
1592 | skb->protocol = eth_type_trans(skb, ndev); | |
bc8acf2c | 1593 | skb_checksum_none_assert(skb); |
4f848c0a | 1594 | |
88230fd5 | 1595 | if ((ndev->features & NETIF_F_RXCSUM) && |
4f848c0a RM |
1596 | !(ib_mac_rsp->flags1 & IB_MAC_CSUM_ERR_MASK)) { |
1597 | /* TCP frame. */ | |
1598 | if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_T) { | |
ae9540f7 JP |
1599 | netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev, |
1600 | "TCP checksum done!\n"); | |
4f848c0a RM |
1601 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
1602 | } else if ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_U) && | |
1603 | (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_V4)) { | |
1604 | /* Unfragmented ipv4 UDP frame. */ | |
e02ef331 | 1605 | struct iphdr *iph = |
a45adbe8 | 1606 | (struct iphdr *)((u8 *)addr + hlen); |
4f848c0a | 1607 | if (!(iph->frag_off & |
0d653ed8 | 1608 | htons(IP_MF|IP_OFFSET))) { |
4f848c0a | 1609 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
ae9540f7 JP |
1610 | netif_printk(qdev, rx_status, KERN_DEBUG, |
1611 | qdev->ndev, | |
e02ef331 | 1612 | "UDP checksum done!\n"); |
4f848c0a RM |
1613 | } |
1614 | } | |
1615 | } | |
1616 | ||
1617 | skb_record_rx_queue(skb, rx_ring->cq_id); | |
18c49b91 | 1618 | if (vlan_id != 0xffff) |
86a9bad3 | 1619 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_id); |
18c49b91 JP |
1620 | if (skb->ip_summed == CHECKSUM_UNNECESSARY) |
1621 | napi_gro_receive(napi, skb); | |
1622 | else | |
1623 | netif_receive_skb(skb); | |
4f848c0a RM |
1624 | return; |
1625 | err_out: | |
1626 | dev_kfree_skb_any(skb); | |
1627 | put_page(lbq_desc->p.pg_chunk.page); | |
1628 | } | |
1629 | ||
1630 | /* Process an inbound completion from an rx ring. */ | |
1631 | static void ql_process_mac_rx_skb(struct ql_adapter *qdev, | |
1632 | struct rx_ring *rx_ring, | |
1633 | struct ib_mac_iocb_rsp *ib_mac_rsp, | |
1634 | u32 length, | |
1635 | u16 vlan_id) | |
1636 | { | |
1637 | struct net_device *ndev = qdev->ndev; | |
1638 | struct sk_buff *skb = NULL; | |
1639 | struct sk_buff *new_skb = NULL; | |
1640 | struct bq_desc *sbq_desc = ql_get_curr_sbuf(rx_ring); | |
1641 | ||
1642 | skb = sbq_desc->p.skb; | |
1643 | /* Allocate new_skb and copy */ | |
1644 | new_skb = netdev_alloc_skb(qdev->ndev, length + NET_IP_ALIGN); | |
1645 | if (new_skb == NULL) { | |
4f848c0a RM |
1646 | rx_ring->rx_dropped++; |
1647 | return; | |
1648 | } | |
1649 | skb_reserve(new_skb, NET_IP_ALIGN); | |
2c9a266a MC |
1650 | |
1651 | pci_dma_sync_single_for_cpu(qdev->pdev, | |
1652 | dma_unmap_addr(sbq_desc, mapaddr), | |
1653 | dma_unmap_len(sbq_desc, maplen), | |
1654 | PCI_DMA_FROMDEVICE); | |
1655 | ||
59ae1d12 | 1656 | skb_put_data(new_skb, skb->data, length); |
2c9a266a MC |
1657 | |
1658 | pci_dma_sync_single_for_device(qdev->pdev, | |
1659 | dma_unmap_addr(sbq_desc, mapaddr), | |
1660 | dma_unmap_len(sbq_desc, maplen), | |
1661 | PCI_DMA_FROMDEVICE); | |
4f848c0a RM |
1662 | skb = new_skb; |
1663 | ||
ae721f3a SV |
1664 | /* Frame error, so drop the packet. */ |
1665 | if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_ERR_MASK) { | |
1666 | ql_categorize_rx_err(qdev, ib_mac_rsp->flags2, rx_ring); | |
1667 | dev_kfree_skb_any(skb); | |
1668 | return; | |
1669 | } | |
1670 | ||
4f848c0a RM |
1671 | /* loopback self test for ethtool */ |
1672 | if (test_bit(QL_SELFTEST, &qdev->flags)) { | |
1673 | ql_check_lb_frame(qdev, skb); | |
1674 | dev_kfree_skb_any(skb); | |
1675 | return; | |
1676 | } | |
1677 | ||
1678 | /* The max framesize filter on this chip is set higher than | |
1679 | * MTU since FCoE uses 2k frames. | |
1680 | */ | |
1681 | if (skb->len > ndev->mtu + ETH_HLEN) { | |
1682 | dev_kfree_skb_any(skb); | |
1683 | rx_ring->rx_dropped++; | |
1684 | return; | |
1685 | } | |
1686 | ||
1687 | prefetch(skb->data); | |
4f848c0a | 1688 | if (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) { |
ae9540f7 JP |
1689 | netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev, |
1690 | "%s Multicast.\n", | |
1691 | (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) == | |
1692 | IB_MAC_IOCB_RSP_M_HASH ? "Hash" : | |
1693 | (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) == | |
1694 | IB_MAC_IOCB_RSP_M_REG ? "Registered" : | |
1695 | (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) == | |
1696 | IB_MAC_IOCB_RSP_M_PROM ? "Promiscuous" : ""); | |
4f848c0a RM |
1697 | } |
1698 | if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_P) | |
ae9540f7 JP |
1699 | netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev, |
1700 | "Promiscuous Packet.\n"); | |
4f848c0a RM |
1701 | |
1702 | rx_ring->rx_packets++; | |
1703 | rx_ring->rx_bytes += skb->len; | |
1704 | skb->protocol = eth_type_trans(skb, ndev); | |
bc8acf2c | 1705 | skb_checksum_none_assert(skb); |
4f848c0a RM |
1706 | |
1707 | /* If rx checksum is on, and there are no | |
1708 | * csum or frame errors. | |
1709 | */ | |
88230fd5 | 1710 | if ((ndev->features & NETIF_F_RXCSUM) && |
4f848c0a RM |
1711 | !(ib_mac_rsp->flags1 & IB_MAC_CSUM_ERR_MASK)) { |
1712 | /* TCP frame. */ | |
1713 | if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_T) { | |
ae9540f7 JP |
1714 | netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev, |
1715 | "TCP checksum done!\n"); | |
4f848c0a RM |
1716 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
1717 | } else if ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_U) && | |
1718 | (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_V4)) { | |
1719 | /* Unfragmented ipv4 UDP frame. */ | |
1720 | struct iphdr *iph = (struct iphdr *) skb->data; | |
1721 | if (!(iph->frag_off & | |
0d653ed8 | 1722 | htons(IP_MF|IP_OFFSET))) { |
4f848c0a | 1723 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
ae9540f7 JP |
1724 | netif_printk(qdev, rx_status, KERN_DEBUG, |
1725 | qdev->ndev, | |
e02ef331 | 1726 | "UDP checksum done!\n"); |
4f848c0a RM |
1727 | } |
1728 | } | |
1729 | } | |
1730 | ||
1731 | skb_record_rx_queue(skb, rx_ring->cq_id); | |
18c49b91 | 1732 | if (vlan_id != 0xffff) |
86a9bad3 | 1733 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_id); |
18c49b91 JP |
1734 | if (skb->ip_summed == CHECKSUM_UNNECESSARY) |
1735 | napi_gro_receive(&rx_ring->napi, skb); | |
1736 | else | |
1737 | netif_receive_skb(skb); | |
4f848c0a RM |
1738 | } |
1739 | ||
8668ae92 | 1740 | static void ql_realign_skb(struct sk_buff *skb, int len) |
c4e84bde RM |
1741 | { |
1742 | void *temp_addr = skb->data; | |
1743 | ||
1744 | /* Undo the skb_reserve(skb,32) we did before | |
1745 | * giving to hardware, and realign data on | |
1746 | * a 2-byte boundary. | |
1747 | */ | |
1748 | skb->data -= QLGE_SB_PAD - NET_IP_ALIGN; | |
1749 | skb->tail -= QLGE_SB_PAD - NET_IP_ALIGN; | |
1750 | skb_copy_to_linear_data(skb, temp_addr, | |
1751 | (unsigned int)len); | |
1752 | } | |
1753 | ||
1754 | /* | |
1755 | * This function builds an skb for the given inbound | |
1756 | * completion. It will be rewritten for readability in the near | |
1757 | * future, but for not it works well. | |
1758 | */ | |
1759 | static struct sk_buff *ql_build_rx_skb(struct ql_adapter *qdev, | |
1760 | struct rx_ring *rx_ring, | |
1761 | struct ib_mac_iocb_rsp *ib_mac_rsp) | |
1762 | { | |
1763 | struct bq_desc *lbq_desc; | |
1764 | struct bq_desc *sbq_desc; | |
1765 | struct sk_buff *skb = NULL; | |
1766 | u32 length = le32_to_cpu(ib_mac_rsp->data_len); | |
a45adbe8 JK |
1767 | u32 hdr_len = le32_to_cpu(ib_mac_rsp->hdr_len); |
1768 | size_t hlen = ETH_HLEN; | |
c4e84bde RM |
1769 | |
1770 | /* | |
1771 | * Handle the header buffer if present. | |
1772 | */ | |
1773 | if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HV && | |
1774 | ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) { | |
ae9540f7 JP |
1775 | netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev, |
1776 | "Header of %d bytes in small buffer.\n", hdr_len); | |
c4e84bde RM |
1777 | /* |
1778 | * Headers fit nicely into a small buffer. | |
1779 | */ | |
1780 | sbq_desc = ql_get_curr_sbuf(rx_ring); | |
1781 | pci_unmap_single(qdev->pdev, | |
64b9b41d FT |
1782 | dma_unmap_addr(sbq_desc, mapaddr), |
1783 | dma_unmap_len(sbq_desc, maplen), | |
c4e84bde RM |
1784 | PCI_DMA_FROMDEVICE); |
1785 | skb = sbq_desc->p.skb; | |
1786 | ql_realign_skb(skb, hdr_len); | |
1787 | skb_put(skb, hdr_len); | |
1788 | sbq_desc->p.skb = NULL; | |
1789 | } | |
1790 | ||
1791 | /* | |
1792 | * Handle the data buffer(s). | |
1793 | */ | |
1794 | if (unlikely(!length)) { /* Is there data too? */ | |
ae9540f7 JP |
1795 | netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev, |
1796 | "No Data buffer in this packet.\n"); | |
c4e84bde RM |
1797 | return skb; |
1798 | } | |
1799 | ||
1800 | if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DS) { | |
1801 | if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) { | |
ae9540f7 JP |
1802 | netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev, |
1803 | "Headers in small, data of %d bytes in small, combine them.\n", | |
1804 | length); | |
c4e84bde RM |
1805 | /* |
1806 | * Data is less than small buffer size so it's | |
1807 | * stuffed in a small buffer. | |
1808 | * For this case we append the data | |
1809 | * from the "data" small buffer to the "header" small | |
1810 | * buffer. | |
1811 | */ | |
1812 | sbq_desc = ql_get_curr_sbuf(rx_ring); | |
1813 | pci_dma_sync_single_for_cpu(qdev->pdev, | |
64b9b41d | 1814 | dma_unmap_addr |
c4e84bde | 1815 | (sbq_desc, mapaddr), |
64b9b41d | 1816 | dma_unmap_len |
c4e84bde RM |
1817 | (sbq_desc, maplen), |
1818 | PCI_DMA_FROMDEVICE); | |
59ae1d12 | 1819 | skb_put_data(skb, sbq_desc->p.skb->data, length); |
c4e84bde | 1820 | pci_dma_sync_single_for_device(qdev->pdev, |
64b9b41d | 1821 | dma_unmap_addr |
c4e84bde RM |
1822 | (sbq_desc, |
1823 | mapaddr), | |
64b9b41d | 1824 | dma_unmap_len |
c4e84bde RM |
1825 | (sbq_desc, |
1826 | maplen), | |
1827 | PCI_DMA_FROMDEVICE); | |
1828 | } else { | |
ae9540f7 JP |
1829 | netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev, |
1830 | "%d bytes in a single small buffer.\n", | |
1831 | length); | |
c4e84bde RM |
1832 | sbq_desc = ql_get_curr_sbuf(rx_ring); |
1833 | skb = sbq_desc->p.skb; | |
1834 | ql_realign_skb(skb, length); | |
1835 | skb_put(skb, length); | |
1836 | pci_unmap_single(qdev->pdev, | |
64b9b41d | 1837 | dma_unmap_addr(sbq_desc, |
c4e84bde | 1838 | mapaddr), |
64b9b41d | 1839 | dma_unmap_len(sbq_desc, |
c4e84bde RM |
1840 | maplen), |
1841 | PCI_DMA_FROMDEVICE); | |
1842 | sbq_desc->p.skb = NULL; | |
1843 | } | |
1844 | } else if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DL) { | |
1845 | if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) { | |
ae9540f7 JP |
1846 | netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev, |
1847 | "Header in small, %d bytes in large. Chain large to small!\n", | |
1848 | length); | |
c4e84bde RM |
1849 | /* |
1850 | * The data is in a single large buffer. We | |
1851 | * chain it to the header buffer's skb and let | |
1852 | * it rip. | |
1853 | */ | |
7c734359 | 1854 | lbq_desc = ql_get_curr_lchunk(qdev, rx_ring); |
ae9540f7 JP |
1855 | netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev, |
1856 | "Chaining page at offset = %d, for %d bytes to skb.\n", | |
1857 | lbq_desc->p.pg_chunk.offset, length); | |
7c734359 RM |
1858 | skb_fill_page_desc(skb, 0, lbq_desc->p.pg_chunk.page, |
1859 | lbq_desc->p.pg_chunk.offset, | |
1860 | length); | |
c4e84bde RM |
1861 | skb->len += length; |
1862 | skb->data_len += length; | |
1863 | skb->truesize += length; | |
c4e84bde RM |
1864 | } else { |
1865 | /* | |
1866 | * The headers and data are in a single large buffer. We | |
1867 | * copy it to a new skb and let it go. This can happen with | |
1868 | * jumbo mtu on a non-TCP/UDP frame. | |
1869 | */ | |
7c734359 | 1870 | lbq_desc = ql_get_curr_lchunk(qdev, rx_ring); |
c4e84bde RM |
1871 | skb = netdev_alloc_skb(qdev->ndev, length); |
1872 | if (skb == NULL) { | |
ae9540f7 JP |
1873 | netif_printk(qdev, probe, KERN_DEBUG, qdev->ndev, |
1874 | "No skb available, drop the packet.\n"); | |
c4e84bde RM |
1875 | return NULL; |
1876 | } | |
4055c7d4 | 1877 | pci_unmap_page(qdev->pdev, |
64b9b41d | 1878 | dma_unmap_addr(lbq_desc, |
4055c7d4 | 1879 | mapaddr), |
64b9b41d | 1880 | dma_unmap_len(lbq_desc, maplen), |
4055c7d4 | 1881 | PCI_DMA_FROMDEVICE); |
c4e84bde | 1882 | skb_reserve(skb, NET_IP_ALIGN); |
ae9540f7 JP |
1883 | netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev, |
1884 | "%d bytes of headers and data in large. Chain page to new skb and pull tail.\n", | |
1885 | length); | |
7c734359 RM |
1886 | skb_fill_page_desc(skb, 0, |
1887 | lbq_desc->p.pg_chunk.page, | |
1888 | lbq_desc->p.pg_chunk.offset, | |
1889 | length); | |
c4e84bde RM |
1890 | skb->len += length; |
1891 | skb->data_len += length; | |
1892 | skb->truesize += length; | |
a45adbe8 JK |
1893 | ql_update_mac_hdr_len(qdev, ib_mac_rsp, |
1894 | lbq_desc->p.pg_chunk.va, | |
1895 | &hlen); | |
1896 | __pskb_pull_tail(skb, hlen); | |
c4e84bde RM |
1897 | } |
1898 | } else { | |
1899 | /* | |
1900 | * The data is in a chain of large buffers | |
1901 | * pointed to by a small buffer. We loop | |
1902 | * thru and chain them to the our small header | |
1903 | * buffer's skb. | |
1904 | * frags: There are 18 max frags and our small | |
1905 | * buffer will hold 32 of them. The thing is, | |
1906 | * we'll use 3 max for our 9000 byte jumbo | |
1907 | * frames. If the MTU goes up we could | |
1908 | * eventually be in trouble. | |
1909 | */ | |
7c734359 | 1910 | int size, i = 0; |
c4e84bde RM |
1911 | sbq_desc = ql_get_curr_sbuf(rx_ring); |
1912 | pci_unmap_single(qdev->pdev, | |
64b9b41d FT |
1913 | dma_unmap_addr(sbq_desc, mapaddr), |
1914 | dma_unmap_len(sbq_desc, maplen), | |
c4e84bde RM |
1915 | PCI_DMA_FROMDEVICE); |
1916 | if (!(ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS)) { | |
1917 | /* | |
1918 | * This is an non TCP/UDP IP frame, so | |
1919 | * the headers aren't split into a small | |
1920 | * buffer. We have to use the small buffer | |
1921 | * that contains our sg list as our skb to | |
1922 | * send upstairs. Copy the sg list here to | |
1923 | * a local buffer and use it to find the | |
1924 | * pages to chain. | |
1925 | */ | |
ae9540f7 JP |
1926 | netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev, |
1927 | "%d bytes of headers & data in chain of large.\n", | |
1928 | length); | |
c4e84bde | 1929 | skb = sbq_desc->p.skb; |
c4e84bde RM |
1930 | sbq_desc->p.skb = NULL; |
1931 | skb_reserve(skb, NET_IP_ALIGN); | |
c4e84bde | 1932 | } |
afe6e00c | 1933 | do { |
7c734359 RM |
1934 | lbq_desc = ql_get_curr_lchunk(qdev, rx_ring); |
1935 | size = (length < rx_ring->lbq_buf_size) ? length : | |
1936 | rx_ring->lbq_buf_size; | |
c4e84bde | 1937 | |
ae9540f7 JP |
1938 | netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev, |
1939 | "Adding page %d to skb for %d bytes.\n", | |
1940 | i, size); | |
7c734359 RM |
1941 | skb_fill_page_desc(skb, i, |
1942 | lbq_desc->p.pg_chunk.page, | |
1943 | lbq_desc->p.pg_chunk.offset, | |
1944 | size); | |
c4e84bde RM |
1945 | skb->len += size; |
1946 | skb->data_len += size; | |
1947 | skb->truesize += size; | |
1948 | length -= size; | |
c4e84bde | 1949 | i++; |
afe6e00c | 1950 | } while (length > 0); |
a45adbe8 JK |
1951 | ql_update_mac_hdr_len(qdev, ib_mac_rsp, lbq_desc->p.pg_chunk.va, |
1952 | &hlen); | |
1953 | __pskb_pull_tail(skb, hlen); | |
c4e84bde RM |
1954 | } |
1955 | return skb; | |
1956 | } | |
1957 | ||
1958 | /* Process an inbound completion from an rx ring. */ | |
4f848c0a | 1959 | static void ql_process_mac_split_rx_intr(struct ql_adapter *qdev, |
c4e84bde | 1960 | struct rx_ring *rx_ring, |
4f848c0a RM |
1961 | struct ib_mac_iocb_rsp *ib_mac_rsp, |
1962 | u16 vlan_id) | |
c4e84bde RM |
1963 | { |
1964 | struct net_device *ndev = qdev->ndev; | |
1965 | struct sk_buff *skb = NULL; | |
1966 | ||
1967 | QL_DUMP_IB_MAC_RSP(ib_mac_rsp); | |
1968 | ||
1969 | skb = ql_build_rx_skb(qdev, rx_ring, ib_mac_rsp); | |
1970 | if (unlikely(!skb)) { | |
ae9540f7 JP |
1971 | netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev, |
1972 | "No skb available, drop packet.\n"); | |
885ee398 | 1973 | rx_ring->rx_dropped++; |
c4e84bde RM |
1974 | return; |
1975 | } | |
1976 | ||
ae721f3a SV |
1977 | /* Frame error, so drop the packet. */ |
1978 | if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_ERR_MASK) { | |
1979 | ql_categorize_rx_err(qdev, ib_mac_rsp->flags2, rx_ring); | |
1980 | dev_kfree_skb_any(skb); | |
1981 | return; | |
1982 | } | |
1983 | ||
ec33a491 RM |
1984 | /* The max framesize filter on this chip is set higher than |
1985 | * MTU since FCoE uses 2k frames. | |
1986 | */ | |
1987 | if (skb->len > ndev->mtu + ETH_HLEN) { | |
1988 | dev_kfree_skb_any(skb); | |
885ee398 | 1989 | rx_ring->rx_dropped++; |
ec33a491 RM |
1990 | return; |
1991 | } | |
1992 | ||
9dfbbaa6 RM |
1993 | /* loopback self test for ethtool */ |
1994 | if (test_bit(QL_SELFTEST, &qdev->flags)) { | |
1995 | ql_check_lb_frame(qdev, skb); | |
1996 | dev_kfree_skb_any(skb); | |
1997 | return; | |
1998 | } | |
1999 | ||
c4e84bde | 2000 | prefetch(skb->data); |
c4e84bde | 2001 | if (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) { |
ae9540f7 JP |
2002 | netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev, "%s Multicast.\n", |
2003 | (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) == | |
2004 | IB_MAC_IOCB_RSP_M_HASH ? "Hash" : | |
2005 | (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) == | |
2006 | IB_MAC_IOCB_RSP_M_REG ? "Registered" : | |
2007 | (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) == | |
2008 | IB_MAC_IOCB_RSP_M_PROM ? "Promiscuous" : ""); | |
885ee398 | 2009 | rx_ring->rx_multicast++; |
c4e84bde RM |
2010 | } |
2011 | if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_P) { | |
ae9540f7 JP |
2012 | netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev, |
2013 | "Promiscuous Packet.\n"); | |
c4e84bde | 2014 | } |
d555f592 | 2015 | |
d555f592 | 2016 | skb->protocol = eth_type_trans(skb, ndev); |
bc8acf2c | 2017 | skb_checksum_none_assert(skb); |
d555f592 RM |
2018 | |
2019 | /* If rx checksum is on, and there are no | |
2020 | * csum or frame errors. | |
2021 | */ | |
88230fd5 | 2022 | if ((ndev->features & NETIF_F_RXCSUM) && |
d555f592 RM |
2023 | !(ib_mac_rsp->flags1 & IB_MAC_CSUM_ERR_MASK)) { |
2024 | /* TCP frame. */ | |
2025 | if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_T) { | |
ae9540f7 JP |
2026 | netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev, |
2027 | "TCP checksum done!\n"); | |
d555f592 RM |
2028 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
2029 | } else if ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_U) && | |
2030 | (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_V4)) { | |
2031 | /* Unfragmented ipv4 UDP frame. */ | |
2032 | struct iphdr *iph = (struct iphdr *) skb->data; | |
2033 | if (!(iph->frag_off & | |
0d653ed8 | 2034 | htons(IP_MF|IP_OFFSET))) { |
d555f592 | 2035 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
ae9540f7 JP |
2036 | netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev, |
2037 | "TCP checksum done!\n"); | |
d555f592 RM |
2038 | } |
2039 | } | |
c4e84bde | 2040 | } |
d555f592 | 2041 | |
885ee398 RM |
2042 | rx_ring->rx_packets++; |
2043 | rx_ring->rx_bytes += skb->len; | |
b2014ff8 | 2044 | skb_record_rx_queue(skb, rx_ring->cq_id); |
a45adbe8 | 2045 | if (vlan_id != 0xffff) |
86a9bad3 | 2046 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_id); |
18c49b91 JP |
2047 | if (skb->ip_summed == CHECKSUM_UNNECESSARY) |
2048 | napi_gro_receive(&rx_ring->napi, skb); | |
2049 | else | |
2050 | netif_receive_skb(skb); | |
c4e84bde RM |
2051 | } |
2052 | ||
4f848c0a RM |
2053 | /* Process an inbound completion from an rx ring. */ |
2054 | static unsigned long ql_process_mac_rx_intr(struct ql_adapter *qdev, | |
2055 | struct rx_ring *rx_ring, | |
2056 | struct ib_mac_iocb_rsp *ib_mac_rsp) | |
2057 | { | |
2058 | u32 length = le32_to_cpu(ib_mac_rsp->data_len); | |
a45adbe8 JK |
2059 | u16 vlan_id = ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) && |
2060 | (qdev->ndev->features & NETIF_F_HW_VLAN_CTAG_RX)) ? | |
4f848c0a RM |
2061 | ((le16_to_cpu(ib_mac_rsp->vlan_id) & |
2062 | IB_MAC_IOCB_RSP_VLAN_MASK)) : 0xffff; | |
2063 | ||
2064 | QL_DUMP_IB_MAC_RSP(ib_mac_rsp); | |
2065 | ||
2066 | if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HV) { | |
2067 | /* The data and headers are split into | |
2068 | * separate buffers. | |
2069 | */ | |
2070 | ql_process_mac_split_rx_intr(qdev, rx_ring, ib_mac_rsp, | |
2071 | vlan_id); | |
2072 | } else if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DS) { | |
2073 | /* The data fit in a single small buffer. | |
2074 | * Allocate a new skb, copy the data and | |
2075 | * return the buffer to the free pool. | |
2076 | */ | |
2077 | ql_process_mac_rx_skb(qdev, rx_ring, ib_mac_rsp, | |
2078 | length, vlan_id); | |
63526713 RM |
2079 | } else if ((ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DL) && |
2080 | !(ib_mac_rsp->flags1 & IB_MAC_CSUM_ERR_MASK) && | |
2081 | (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_T)) { | |
2082 | /* TCP packet in a page chunk that's been checksummed. | |
2083 | * Tack it on to our GRO skb and let it go. | |
2084 | */ | |
2085 | ql_process_mac_rx_gro_page(qdev, rx_ring, ib_mac_rsp, | |
2086 | length, vlan_id); | |
4f848c0a RM |
2087 | } else if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DL) { |
2088 | /* Non-TCP packet in a page chunk. Allocate an | |
2089 | * skb, tack it on frags, and send it up. | |
2090 | */ | |
2091 | ql_process_mac_rx_page(qdev, rx_ring, ib_mac_rsp, | |
2092 | length, vlan_id); | |
2093 | } else { | |
c0c56955 RM |
2094 | /* Non-TCP/UDP large frames that span multiple buffers |
2095 | * can be processed corrrectly by the split frame logic. | |
2096 | */ | |
2097 | ql_process_mac_split_rx_intr(qdev, rx_ring, ib_mac_rsp, | |
2098 | vlan_id); | |
4f848c0a RM |
2099 | } |
2100 | ||
2101 | return (unsigned long)length; | |
2102 | } | |
2103 | ||
c4e84bde RM |
2104 | /* Process an outbound completion from an rx ring. */ |
2105 | static void ql_process_mac_tx_intr(struct ql_adapter *qdev, | |
2106 | struct ob_mac_iocb_rsp *mac_rsp) | |
2107 | { | |
2108 | struct tx_ring *tx_ring; | |
2109 | struct tx_ring_desc *tx_ring_desc; | |
2110 | ||
2111 | QL_DUMP_OB_MAC_RSP(mac_rsp); | |
2112 | tx_ring = &qdev->tx_ring[mac_rsp->txq_idx]; | |
2113 | tx_ring_desc = &tx_ring->q[mac_rsp->tid]; | |
2114 | ql_unmap_send(qdev, tx_ring_desc, tx_ring_desc->map_cnt); | |
885ee398 RM |
2115 | tx_ring->tx_bytes += (tx_ring_desc->skb)->len; |
2116 | tx_ring->tx_packets++; | |
c4e84bde RM |
2117 | dev_kfree_skb(tx_ring_desc->skb); |
2118 | tx_ring_desc->skb = NULL; | |
2119 | ||
2120 | if (unlikely(mac_rsp->flags1 & (OB_MAC_IOCB_RSP_E | | |
2121 | OB_MAC_IOCB_RSP_S | | |
2122 | OB_MAC_IOCB_RSP_L | | |
2123 | OB_MAC_IOCB_RSP_P | OB_MAC_IOCB_RSP_B))) { | |
2124 | if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_E) { | |
ae9540f7 JP |
2125 | netif_warn(qdev, tx_done, qdev->ndev, |
2126 | "Total descriptor length did not match transfer length.\n"); | |
c4e84bde RM |
2127 | } |
2128 | if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_S) { | |
ae9540f7 JP |
2129 | netif_warn(qdev, tx_done, qdev->ndev, |
2130 | "Frame too short to be valid, not sent.\n"); | |
c4e84bde RM |
2131 | } |
2132 | if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_L) { | |
ae9540f7 JP |
2133 | netif_warn(qdev, tx_done, qdev->ndev, |
2134 | "Frame too long, but sent anyway.\n"); | |
c4e84bde RM |
2135 | } |
2136 | if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_B) { | |
ae9540f7 JP |
2137 | netif_warn(qdev, tx_done, qdev->ndev, |
2138 | "PCI backplane error. Frame not sent.\n"); | |
c4e84bde RM |
2139 | } |
2140 | } | |
2141 | atomic_inc(&tx_ring->tx_count); | |
2142 | } | |
2143 | ||
2144 | /* Fire up a handler to reset the MPI processor. */ | |
2145 | void ql_queue_fw_error(struct ql_adapter *qdev) | |
2146 | { | |
6a473308 | 2147 | ql_link_off(qdev); |
c4e84bde RM |
2148 | queue_delayed_work(qdev->workqueue, &qdev->mpi_reset_work, 0); |
2149 | } | |
2150 | ||
2151 | void ql_queue_asic_error(struct ql_adapter *qdev) | |
2152 | { | |
6a473308 | 2153 | ql_link_off(qdev); |
c4e84bde | 2154 | ql_disable_interrupts(qdev); |
6497b607 RM |
2155 | /* Clear adapter up bit to signal the recovery |
2156 | * process that it shouldn't kill the reset worker | |
2157 | * thread | |
2158 | */ | |
2159 | clear_bit(QL_ADAPTER_UP, &qdev->flags); | |
da92b393 JK |
2160 | /* Set asic recovery bit to indicate reset process that we are |
2161 | * in fatal error recovery process rather than normal close | |
2162 | */ | |
2163 | set_bit(QL_ASIC_RECOVERY, &qdev->flags); | |
c4e84bde RM |
2164 | queue_delayed_work(qdev->workqueue, &qdev->asic_reset_work, 0); |
2165 | } | |
2166 | ||
2167 | static void ql_process_chip_ae_intr(struct ql_adapter *qdev, | |
2168 | struct ib_ae_iocb_rsp *ib_ae_rsp) | |
2169 | { | |
2170 | switch (ib_ae_rsp->event) { | |
2171 | case MGMT_ERR_EVENT: | |
ae9540f7 JP |
2172 | netif_err(qdev, rx_err, qdev->ndev, |
2173 | "Management Processor Fatal Error.\n"); | |
c4e84bde RM |
2174 | ql_queue_fw_error(qdev); |
2175 | return; | |
2176 | ||
2177 | case CAM_LOOKUP_ERR_EVENT: | |
5069ee55 JK |
2178 | netdev_err(qdev->ndev, "Multiple CAM hits lookup occurred.\n"); |
2179 | netdev_err(qdev->ndev, "This event shouldn't occur.\n"); | |
c4e84bde RM |
2180 | ql_queue_asic_error(qdev); |
2181 | return; | |
2182 | ||
2183 | case SOFT_ECC_ERROR_EVENT: | |
5069ee55 | 2184 | netdev_err(qdev->ndev, "Soft ECC error detected.\n"); |
c4e84bde RM |
2185 | ql_queue_asic_error(qdev); |
2186 | break; | |
2187 | ||
2188 | case PCI_ERR_ANON_BUF_RD: | |
5069ee55 JK |
2189 | netdev_err(qdev->ndev, "PCI error occurred when reading " |
2190 | "anonymous buffers from rx_ring %d.\n", | |
2191 | ib_ae_rsp->q_id); | |
c4e84bde RM |
2192 | ql_queue_asic_error(qdev); |
2193 | break; | |
2194 | ||
2195 | default: | |
ae9540f7 JP |
2196 | netif_err(qdev, drv, qdev->ndev, "Unexpected event %d.\n", |
2197 | ib_ae_rsp->event); | |
c4e84bde RM |
2198 | ql_queue_asic_error(qdev); |
2199 | break; | |
2200 | } | |
2201 | } | |
2202 | ||
2203 | static int ql_clean_outbound_rx_ring(struct rx_ring *rx_ring) | |
2204 | { | |
2205 | struct ql_adapter *qdev = rx_ring->qdev; | |
ba7cd3ba | 2206 | u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg); |
c4e84bde RM |
2207 | struct ob_mac_iocb_rsp *net_rsp = NULL; |
2208 | int count = 0; | |
2209 | ||
1e213303 | 2210 | struct tx_ring *tx_ring; |
c4e84bde RM |
2211 | /* While there are entries in the completion queue. */ |
2212 | while (prod != rx_ring->cnsmr_idx) { | |
2213 | ||
ae9540f7 JP |
2214 | netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev, |
2215 | "cq_id = %d, prod = %d, cnsmr = %d.\n.", | |
2216 | rx_ring->cq_id, prod, rx_ring->cnsmr_idx); | |
c4e84bde RM |
2217 | |
2218 | net_rsp = (struct ob_mac_iocb_rsp *)rx_ring->curr_entry; | |
2219 | rmb(); | |
2220 | switch (net_rsp->opcode) { | |
2221 | ||
2222 | case OPCODE_OB_MAC_TSO_IOCB: | |
2223 | case OPCODE_OB_MAC_IOCB: | |
2224 | ql_process_mac_tx_intr(qdev, net_rsp); | |
2225 | break; | |
2226 | default: | |
ae9540f7 JP |
2227 | netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev, |
2228 | "Hit default case, not handled! dropping the packet, opcode = %x.\n", | |
2229 | net_rsp->opcode); | |
c4e84bde RM |
2230 | } |
2231 | count++; | |
2232 | ql_update_cq(rx_ring); | |
ba7cd3ba | 2233 | prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg); |
c4e84bde | 2234 | } |
4da79504 DC |
2235 | if (!net_rsp) |
2236 | return 0; | |
c4e84bde | 2237 | ql_write_cq_idx(rx_ring); |
1e213303 | 2238 | tx_ring = &qdev->tx_ring[net_rsp->txq_idx]; |
4da79504 | 2239 | if (__netif_subqueue_stopped(qdev->ndev, tx_ring->wq_id)) { |
d0de7309 | 2240 | if ((atomic_read(&tx_ring->tx_count) > (tx_ring->wq_len / 4))) |
c4e84bde RM |
2241 | /* |
2242 | * The queue got stopped because the tx_ring was full. | |
2243 | * Wake it up, because it's now at least 25% empty. | |
2244 | */ | |
1e213303 | 2245 | netif_wake_subqueue(qdev->ndev, tx_ring->wq_id); |
c4e84bde RM |
2246 | } |
2247 | ||
2248 | return count; | |
2249 | } | |
2250 | ||
2251 | static int ql_clean_inbound_rx_ring(struct rx_ring *rx_ring, int budget) | |
2252 | { | |
2253 | struct ql_adapter *qdev = rx_ring->qdev; | |
ba7cd3ba | 2254 | u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg); |
c4e84bde RM |
2255 | struct ql_net_rsp_iocb *net_rsp; |
2256 | int count = 0; | |
2257 | ||
2258 | /* While there are entries in the completion queue. */ | |
2259 | while (prod != rx_ring->cnsmr_idx) { | |
2260 | ||
ae9540f7 JP |
2261 | netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev, |
2262 | "cq_id = %d, prod = %d, cnsmr = %d.\n.", | |
2263 | rx_ring->cq_id, prod, rx_ring->cnsmr_idx); | |
c4e84bde RM |
2264 | |
2265 | net_rsp = rx_ring->curr_entry; | |
2266 | rmb(); | |
2267 | switch (net_rsp->opcode) { | |
2268 | case OPCODE_IB_MAC_IOCB: | |
2269 | ql_process_mac_rx_intr(qdev, rx_ring, | |
2270 | (struct ib_mac_iocb_rsp *) | |
2271 | net_rsp); | |
2272 | break; | |
2273 | ||
2274 | case OPCODE_IB_AE_IOCB: | |
2275 | ql_process_chip_ae_intr(qdev, (struct ib_ae_iocb_rsp *) | |
2276 | net_rsp); | |
2277 | break; | |
2278 | default: | |
ae9540f7 JP |
2279 | netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev, |
2280 | "Hit default case, not handled! dropping the packet, opcode = %x.\n", | |
2281 | net_rsp->opcode); | |
2282 | break; | |
c4e84bde RM |
2283 | } |
2284 | count++; | |
2285 | ql_update_cq(rx_ring); | |
ba7cd3ba | 2286 | prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg); |
c4e84bde RM |
2287 | if (count == budget) |
2288 | break; | |
2289 | } | |
2290 | ql_update_buffer_queues(qdev, rx_ring); | |
2291 | ql_write_cq_idx(rx_ring); | |
2292 | return count; | |
2293 | } | |
2294 | ||
2295 | static int ql_napi_poll_msix(struct napi_struct *napi, int budget) | |
2296 | { | |
2297 | struct rx_ring *rx_ring = container_of(napi, struct rx_ring, napi); | |
2298 | struct ql_adapter *qdev = rx_ring->qdev; | |
39aa8165 RM |
2299 | struct rx_ring *trx_ring; |
2300 | int i, work_done = 0; | |
2301 | struct intr_context *ctx = &qdev->intr_context[rx_ring->cq_id]; | |
c4e84bde | 2302 | |
ae9540f7 JP |
2303 | netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev, |
2304 | "Enter, NAPI POLL cq_id = %d.\n", rx_ring->cq_id); | |
c4e84bde | 2305 | |
39aa8165 RM |
2306 | /* Service the TX rings first. They start |
2307 | * right after the RSS rings. */ | |
2308 | for (i = qdev->rss_ring_count; i < qdev->rx_ring_count; i++) { | |
2309 | trx_ring = &qdev->rx_ring[i]; | |
2310 | /* If this TX completion ring belongs to this vector and | |
2311 | * it's not empty then service it. | |
2312 | */ | |
2313 | if ((ctx->irq_mask & (1 << trx_ring->cq_id)) && | |
2314 | (ql_read_sh_reg(trx_ring->prod_idx_sh_reg) != | |
2315 | trx_ring->cnsmr_idx)) { | |
ae9540f7 JP |
2316 | netif_printk(qdev, intr, KERN_DEBUG, qdev->ndev, |
2317 | "%s: Servicing TX completion ring %d.\n", | |
2318 | __func__, trx_ring->cq_id); | |
39aa8165 RM |
2319 | ql_clean_outbound_rx_ring(trx_ring); |
2320 | } | |
2321 | } | |
2322 | ||
2323 | /* | |
2324 | * Now service the RSS ring if it's active. | |
2325 | */ | |
2326 | if (ql_read_sh_reg(rx_ring->prod_idx_sh_reg) != | |
2327 | rx_ring->cnsmr_idx) { | |
ae9540f7 JP |
2328 | netif_printk(qdev, intr, KERN_DEBUG, qdev->ndev, |
2329 | "%s: Servicing RX completion ring %d.\n", | |
2330 | __func__, rx_ring->cq_id); | |
39aa8165 RM |
2331 | work_done = ql_clean_inbound_rx_ring(rx_ring, budget); |
2332 | } | |
2333 | ||
c4e84bde | 2334 | if (work_done < budget) { |
6ad20165 | 2335 | napi_complete_done(napi, work_done); |
c4e84bde RM |
2336 | ql_enable_completion_interrupt(qdev, rx_ring->irq); |
2337 | } | |
2338 | return work_done; | |
2339 | } | |
2340 | ||
c8f44aff | 2341 | static void qlge_vlan_mode(struct net_device *ndev, netdev_features_t features) |
c4e84bde RM |
2342 | { |
2343 | struct ql_adapter *qdev = netdev_priv(ndev); | |
2344 | ||
f646968f | 2345 | if (features & NETIF_F_HW_VLAN_CTAG_RX) { |
c4e84bde | 2346 | ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK | |
18c49b91 | 2347 | NIC_RCV_CFG_VLAN_MATCH_AND_NON); |
c4e84bde | 2348 | } else { |
c4e84bde RM |
2349 | ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK); |
2350 | } | |
2351 | } | |
2352 | ||
a45adbe8 JK |
2353 | /** |
2354 | * qlge_update_hw_vlan_features - helper routine to reinitialize the adapter | |
2355 | * based on the features to enable/disable hardware vlan accel | |
2356 | */ | |
2357 | static int qlge_update_hw_vlan_features(struct net_device *ndev, | |
2358 | netdev_features_t features) | |
2359 | { | |
2360 | struct ql_adapter *qdev = netdev_priv(ndev); | |
2361 | int status = 0; | |
61132bf7 | 2362 | bool need_restart = netif_running(ndev); |
a45adbe8 | 2363 | |
61132bf7 ML |
2364 | if (need_restart) { |
2365 | status = ql_adapter_down(qdev); | |
2366 | if (status) { | |
2367 | netif_err(qdev, link, qdev->ndev, | |
2368 | "Failed to bring down the adapter\n"); | |
2369 | return status; | |
2370 | } | |
a45adbe8 JK |
2371 | } |
2372 | ||
2373 | /* update the features with resent change */ | |
2374 | ndev->features = features; | |
2375 | ||
61132bf7 ML |
2376 | if (need_restart) { |
2377 | status = ql_adapter_up(qdev); | |
2378 | if (status) { | |
2379 | netif_err(qdev, link, qdev->ndev, | |
2380 | "Failed to bring up the adapter\n"); | |
2381 | return status; | |
2382 | } | |
a45adbe8 | 2383 | } |
61132bf7 | 2384 | |
a45adbe8 JK |
2385 | return status; |
2386 | } | |
2387 | ||
c8f44aff MM |
2388 | static netdev_features_t qlge_fix_features(struct net_device *ndev, |
2389 | netdev_features_t features) | |
18c49b91 | 2390 | { |
a45adbe8 | 2391 | int err; |
18c49b91 | 2392 | |
a45adbe8 JK |
2393 | /* Update the behavior of vlan accel in the adapter */ |
2394 | err = qlge_update_hw_vlan_features(ndev, features); | |
2395 | if (err) | |
2396 | return err; | |
2397 | ||
18c49b91 JP |
2398 | return features; |
2399 | } | |
2400 | ||
c8f44aff MM |
2401 | static int qlge_set_features(struct net_device *ndev, |
2402 | netdev_features_t features) | |
18c49b91 | 2403 | { |
c8f44aff | 2404 | netdev_features_t changed = ndev->features ^ features; |
18c49b91 | 2405 | |
f646968f | 2406 | if (changed & NETIF_F_HW_VLAN_CTAG_RX) |
18c49b91 JP |
2407 | qlge_vlan_mode(ndev, features); |
2408 | ||
2409 | return 0; | |
2410 | } | |
2411 | ||
8e586137 | 2412 | static int __qlge_vlan_rx_add_vid(struct ql_adapter *qdev, u16 vid) |
c4e84bde | 2413 | { |
c4e84bde | 2414 | u32 enable_bit = MAC_ADDR_E; |
8e586137 | 2415 | int err; |
c4e84bde | 2416 | |
8e586137 JP |
2417 | err = ql_set_mac_addr_reg(qdev, (u8 *) &enable_bit, |
2418 | MAC_ADDR_TYPE_VLAN, vid); | |
2419 | if (err) | |
ae9540f7 JP |
2420 | netif_err(qdev, ifup, qdev->ndev, |
2421 | "Failed to init vlan address.\n"); | |
8e586137 | 2422 | return err; |
c4e84bde RM |
2423 | } |
2424 | ||
80d5c368 | 2425 | static int qlge_vlan_rx_add_vid(struct net_device *ndev, __be16 proto, u16 vid) |
c4e84bde RM |
2426 | { |
2427 | struct ql_adapter *qdev = netdev_priv(ndev); | |
cc288f54 | 2428 | int status; |
8e586137 | 2429 | int err; |
cc288f54 RM |
2430 | |
2431 | status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK); | |
2432 | if (status) | |
8e586137 | 2433 | return status; |
c4e84bde | 2434 | |
8e586137 | 2435 | err = __qlge_vlan_rx_add_vid(qdev, vid); |
18c49b91 JP |
2436 | set_bit(vid, qdev->active_vlans); |
2437 | ||
2438 | ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK); | |
8e586137 JP |
2439 | |
2440 | return err; | |
18c49b91 JP |
2441 | } |
2442 | ||
8e586137 | 2443 | static int __qlge_vlan_rx_kill_vid(struct ql_adapter *qdev, u16 vid) |
18c49b91 JP |
2444 | { |
2445 | u32 enable_bit = 0; | |
8e586137 | 2446 | int err; |
18c49b91 | 2447 | |
8e586137 JP |
2448 | err = ql_set_mac_addr_reg(qdev, (u8 *) &enable_bit, |
2449 | MAC_ADDR_TYPE_VLAN, vid); | |
2450 | if (err) | |
ae9540f7 JP |
2451 | netif_err(qdev, ifup, qdev->ndev, |
2452 | "Failed to clear vlan address.\n"); | |
8e586137 | 2453 | return err; |
18c49b91 JP |
2454 | } |
2455 | ||
80d5c368 | 2456 | static int qlge_vlan_rx_kill_vid(struct net_device *ndev, __be16 proto, u16 vid) |
18c49b91 JP |
2457 | { |
2458 | struct ql_adapter *qdev = netdev_priv(ndev); | |
2459 | int status; | |
8e586137 | 2460 | int err; |
c4e84bde | 2461 | |
18c49b91 JP |
2462 | status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK); |
2463 | if (status) | |
8e586137 | 2464 | return status; |
18c49b91 | 2465 | |
8e586137 | 2466 | err = __qlge_vlan_rx_kill_vid(qdev, vid); |
18c49b91 JP |
2467 | clear_bit(vid, qdev->active_vlans); |
2468 | ||
2469 | ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK); | |
8e586137 JP |
2470 | |
2471 | return err; | |
c4e84bde RM |
2472 | } |
2473 | ||
c1b60092 RM |
2474 | static void qlge_restore_vlan(struct ql_adapter *qdev) |
2475 | { | |
18c49b91 JP |
2476 | int status; |
2477 | u16 vid; | |
2478 | ||
2479 | status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK); | |
2480 | if (status) | |
2481 | return; | |
2482 | ||
2483 | for_each_set_bit(vid, qdev->active_vlans, VLAN_N_VID) | |
2484 | __qlge_vlan_rx_add_vid(qdev, vid); | |
2485 | ||
2486 | ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK); | |
c1b60092 RM |
2487 | } |
2488 | ||
c4e84bde RM |
2489 | /* MSI-X Multiple Vector Interrupt Handler for inbound completions. */ |
2490 | static irqreturn_t qlge_msix_rx_isr(int irq, void *dev_id) | |
2491 | { | |
2492 | struct rx_ring *rx_ring = dev_id; | |
288379f0 | 2493 | napi_schedule(&rx_ring->napi); |
c4e84bde RM |
2494 | return IRQ_HANDLED; |
2495 | } | |
2496 | ||
c4e84bde RM |
2497 | /* This handles a fatal error, MPI activity, and the default |
2498 | * rx_ring in an MSI-X multiple vector environment. | |
2499 | * In MSI/Legacy environment it also process the rest of | |
2500 | * the rx_rings. | |
2501 | */ | |
2502 | static irqreturn_t qlge_isr(int irq, void *dev_id) | |
2503 | { | |
2504 | struct rx_ring *rx_ring = dev_id; | |
2505 | struct ql_adapter *qdev = rx_ring->qdev; | |
2506 | struct intr_context *intr_context = &qdev->intr_context[0]; | |
2507 | u32 var; | |
c4e84bde RM |
2508 | int work_done = 0; |
2509 | ||
bb0d215c RM |
2510 | spin_lock(&qdev->hw_lock); |
2511 | if (atomic_read(&qdev->intr_context[0].irq_cnt)) { | |
ae9540f7 JP |
2512 | netif_printk(qdev, intr, KERN_DEBUG, qdev->ndev, |
2513 | "Shared Interrupt, Not ours!\n"); | |
bb0d215c RM |
2514 | spin_unlock(&qdev->hw_lock); |
2515 | return IRQ_NONE; | |
c4e84bde | 2516 | } |
bb0d215c | 2517 | spin_unlock(&qdev->hw_lock); |
c4e84bde | 2518 | |
bb0d215c | 2519 | var = ql_disable_completion_interrupt(qdev, intr_context->intr); |
c4e84bde RM |
2520 | |
2521 | /* | |
2522 | * Check for fatal error. | |
2523 | */ | |
2524 | if (var & STS_FE) { | |
2525 | ql_queue_asic_error(qdev); | |
5069ee55 | 2526 | netdev_err(qdev->ndev, "Got fatal error, STS = %x.\n", var); |
c4e84bde | 2527 | var = ql_read32(qdev, ERR_STS); |
5069ee55 JK |
2528 | netdev_err(qdev->ndev, "Resetting chip. " |
2529 | "Error Status Register = 0x%x\n", var); | |
c4e84bde RM |
2530 | return IRQ_HANDLED; |
2531 | } | |
2532 | ||
2533 | /* | |
2534 | * Check MPI processor activity. | |
2535 | */ | |
5ee22a5a RM |
2536 | if ((var & STS_PI) && |
2537 | (ql_read32(qdev, INTR_MASK) & INTR_MASK_PI)) { | |
c4e84bde RM |
2538 | /* |
2539 | * We've got an async event or mailbox completion. | |
2540 | * Handle it and clear the source of the interrupt. | |
2541 | */ | |
ae9540f7 JP |
2542 | netif_err(qdev, intr, qdev->ndev, |
2543 | "Got MPI processor interrupt.\n"); | |
c4e84bde | 2544 | ql_disable_completion_interrupt(qdev, intr_context->intr); |
5ee22a5a RM |
2545 | ql_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16)); |
2546 | queue_delayed_work_on(smp_processor_id(), | |
2547 | qdev->workqueue, &qdev->mpi_work, 0); | |
c4e84bde RM |
2548 | work_done++; |
2549 | } | |
2550 | ||
2551 | /* | |
39aa8165 RM |
2552 | * Get the bit-mask that shows the active queues for this |
2553 | * pass. Compare it to the queues that this irq services | |
2554 | * and call napi if there's a match. | |
c4e84bde | 2555 | */ |
39aa8165 RM |
2556 | var = ql_read32(qdev, ISR1); |
2557 | if (var & intr_context->irq_mask) { | |
ae9540f7 JP |
2558 | netif_info(qdev, intr, qdev->ndev, |
2559 | "Waking handler for rx_ring[0].\n"); | |
39aa8165 | 2560 | ql_disable_completion_interrupt(qdev, intr_context->intr); |
32a5b2a0 RM |
2561 | napi_schedule(&rx_ring->napi); |
2562 | work_done++; | |
2563 | } | |
bb0d215c | 2564 | ql_enable_completion_interrupt(qdev, intr_context->intr); |
c4e84bde RM |
2565 | return work_done ? IRQ_HANDLED : IRQ_NONE; |
2566 | } | |
2567 | ||
2568 | static int ql_tso(struct sk_buff *skb, struct ob_mac_tso_iocb_req *mac_iocb_ptr) | |
2569 | { | |
2570 | ||
2571 | if (skb_is_gso(skb)) { | |
2572 | int err; | |
1ee1cfe7 | 2573 | __be16 l3_proto = vlan_get_protocol(skb); |
bb9689e6 | 2574 | |
2575 | err = skb_cow_head(skb, 0); | |
2576 | if (err < 0) | |
2577 | return err; | |
c4e84bde RM |
2578 | |
2579 | mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB; | |
2580 | mac_iocb_ptr->flags3 |= OB_MAC_TSO_IOCB_IC; | |
2581 | mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len); | |
2582 | mac_iocb_ptr->total_hdrs_len = | |
2583 | cpu_to_le16(skb_transport_offset(skb) + tcp_hdrlen(skb)); | |
2584 | mac_iocb_ptr->net_trans_offset = | |
2585 | cpu_to_le16(skb_network_offset(skb) | | |
2586 | skb_transport_offset(skb) | |
2587 | << OB_MAC_TRANSPORT_HDR_SHIFT); | |
2588 | mac_iocb_ptr->mss = cpu_to_le16(skb_shinfo(skb)->gso_size); | |
2589 | mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_LSO; | |
1ee1cfe7 | 2590 | if (likely(l3_proto == htons(ETH_P_IP))) { |
c4e84bde RM |
2591 | struct iphdr *iph = ip_hdr(skb); |
2592 | iph->check = 0; | |
2593 | mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP4; | |
2594 | tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, | |
2595 | iph->daddr, 0, | |
2596 | IPPROTO_TCP, | |
2597 | 0); | |
1ee1cfe7 | 2598 | } else if (l3_proto == htons(ETH_P_IPV6)) { |
c4e84bde RM |
2599 | mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP6; |
2600 | tcp_hdr(skb)->check = | |
2601 | ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, | |
2602 | &ipv6_hdr(skb)->daddr, | |
2603 | 0, IPPROTO_TCP, 0); | |
2604 | } | |
2605 | return 1; | |
2606 | } | |
2607 | return 0; | |
2608 | } | |
2609 | ||
2610 | static void ql_hw_csum_setup(struct sk_buff *skb, | |
2611 | struct ob_mac_tso_iocb_req *mac_iocb_ptr) | |
2612 | { | |
2613 | int len; | |
2614 | struct iphdr *iph = ip_hdr(skb); | |
fd2df4f7 | 2615 | __sum16 *check; |
c4e84bde RM |
2616 | mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB; |
2617 | mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len); | |
2618 | mac_iocb_ptr->net_trans_offset = | |
2619 | cpu_to_le16(skb_network_offset(skb) | | |
2620 | skb_transport_offset(skb) << OB_MAC_TRANSPORT_HDR_SHIFT); | |
2621 | ||
2622 | mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP4; | |
2623 | len = (ntohs(iph->tot_len) - (iph->ihl << 2)); | |
2624 | if (likely(iph->protocol == IPPROTO_TCP)) { | |
2625 | check = &(tcp_hdr(skb)->check); | |
2626 | mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_TC; | |
2627 | mac_iocb_ptr->total_hdrs_len = | |
2628 | cpu_to_le16(skb_transport_offset(skb) + | |
2629 | (tcp_hdr(skb)->doff << 2)); | |
2630 | } else { | |
2631 | check = &(udp_hdr(skb)->check); | |
2632 | mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_UC; | |
2633 | mac_iocb_ptr->total_hdrs_len = | |
2634 | cpu_to_le16(skb_transport_offset(skb) + | |
2635 | sizeof(struct udphdr)); | |
2636 | } | |
2637 | *check = ~csum_tcpudp_magic(iph->saddr, | |
2638 | iph->daddr, len, iph->protocol, 0); | |
2639 | } | |
2640 | ||
61357325 | 2641 | static netdev_tx_t qlge_send(struct sk_buff *skb, struct net_device *ndev) |
c4e84bde RM |
2642 | { |
2643 | struct tx_ring_desc *tx_ring_desc; | |
2644 | struct ob_mac_iocb_req *mac_iocb_ptr; | |
2645 | struct ql_adapter *qdev = netdev_priv(ndev); | |
2646 | int tso; | |
2647 | struct tx_ring *tx_ring; | |
1e213303 | 2648 | u32 tx_ring_idx = (u32) skb->queue_mapping; |
c4e84bde RM |
2649 | |
2650 | tx_ring = &qdev->tx_ring[tx_ring_idx]; | |
2651 | ||
74c50b4b RM |
2652 | if (skb_padto(skb, ETH_ZLEN)) |
2653 | return NETDEV_TX_OK; | |
2654 | ||
c4e84bde | 2655 | if (unlikely(atomic_read(&tx_ring->tx_count) < 2)) { |
ae9540f7 | 2656 | netif_info(qdev, tx_queued, qdev->ndev, |
41812db8 | 2657 | "%s: BUG! shutting down tx queue %d due to lack of resources.\n", |
ae9540f7 | 2658 | __func__, tx_ring_idx); |
1e213303 | 2659 | netif_stop_subqueue(ndev, tx_ring->wq_id); |
885ee398 | 2660 | tx_ring->tx_errors++; |
c4e84bde RM |
2661 | return NETDEV_TX_BUSY; |
2662 | } | |
2663 | tx_ring_desc = &tx_ring->q[tx_ring->prod_idx]; | |
2664 | mac_iocb_ptr = tx_ring_desc->queue_entry; | |
e332471c | 2665 | memset((void *)mac_iocb_ptr, 0, sizeof(*mac_iocb_ptr)); |
c4e84bde RM |
2666 | |
2667 | mac_iocb_ptr->opcode = OPCODE_OB_MAC_IOCB; | |
2668 | mac_iocb_ptr->tid = tx_ring_desc->index; | |
2669 | /* We use the upper 32-bits to store the tx queue for this IO. | |
2670 | * When we get the completion we can use it to establish the context. | |
2671 | */ | |
2672 | mac_iocb_ptr->txq_idx = tx_ring_idx; | |
2673 | tx_ring_desc->skb = skb; | |
2674 | ||
2675 | mac_iocb_ptr->frame_len = cpu_to_le16((u16) skb->len); | |
2676 | ||
df8a39de | 2677 | if (skb_vlan_tag_present(skb)) { |
ae9540f7 | 2678 | netif_printk(qdev, tx_queued, KERN_DEBUG, qdev->ndev, |
df8a39de | 2679 | "Adding a vlan tag %d.\n", skb_vlan_tag_get(skb)); |
c4e84bde | 2680 | mac_iocb_ptr->flags3 |= OB_MAC_IOCB_V; |
df8a39de | 2681 | mac_iocb_ptr->vlan_tci = cpu_to_le16(skb_vlan_tag_get(skb)); |
c4e84bde RM |
2682 | } |
2683 | tso = ql_tso(skb, (struct ob_mac_tso_iocb_req *)mac_iocb_ptr); | |
2684 | if (tso < 0) { | |
2685 | dev_kfree_skb_any(skb); | |
2686 | return NETDEV_TX_OK; | |
2687 | } else if (unlikely(!tso) && (skb->ip_summed == CHECKSUM_PARTIAL)) { | |
2688 | ql_hw_csum_setup(skb, | |
2689 | (struct ob_mac_tso_iocb_req *)mac_iocb_ptr); | |
2690 | } | |
0d979f74 RM |
2691 | if (ql_map_send(qdev, mac_iocb_ptr, skb, tx_ring_desc) != |
2692 | NETDEV_TX_OK) { | |
ae9540f7 JP |
2693 | netif_err(qdev, tx_queued, qdev->ndev, |
2694 | "Could not map the segments.\n"); | |
885ee398 | 2695 | tx_ring->tx_errors++; |
0d979f74 RM |
2696 | return NETDEV_TX_BUSY; |
2697 | } | |
c4e84bde RM |
2698 | QL_DUMP_OB_MAC_IOCB(mac_iocb_ptr); |
2699 | tx_ring->prod_idx++; | |
2700 | if (tx_ring->prod_idx == tx_ring->wq_len) | |
2701 | tx_ring->prod_idx = 0; | |
2702 | wmb(); | |
2703 | ||
2704 | ql_write_db_reg(tx_ring->prod_idx, tx_ring->prod_idx_db_reg); | |
ae9540f7 JP |
2705 | netif_printk(qdev, tx_queued, KERN_DEBUG, qdev->ndev, |
2706 | "tx queued, slot %d, len %d\n", | |
2707 | tx_ring->prod_idx, skb->len); | |
c4e84bde RM |
2708 | |
2709 | atomic_dec(&tx_ring->tx_count); | |
41812db8 JK |
2710 | |
2711 | if (unlikely(atomic_read(&tx_ring->tx_count) < 2)) { | |
2712 | netif_stop_subqueue(ndev, tx_ring->wq_id); | |
2713 | if ((atomic_read(&tx_ring->tx_count) > (tx_ring->wq_len / 4))) | |
2714 | /* | |
2715 | * The queue got stopped because the tx_ring was full. | |
2716 | * Wake it up, because it's now at least 25% empty. | |
2717 | */ | |
2718 | netif_wake_subqueue(qdev->ndev, tx_ring->wq_id); | |
2719 | } | |
c4e84bde RM |
2720 | return NETDEV_TX_OK; |
2721 | } | |
2722 | ||
9dfbbaa6 | 2723 | |
c4e84bde RM |
2724 | static void ql_free_shadow_space(struct ql_adapter *qdev) |
2725 | { | |
2726 | if (qdev->rx_ring_shadow_reg_area) { | |
2727 | pci_free_consistent(qdev->pdev, | |
2728 | PAGE_SIZE, | |
2729 | qdev->rx_ring_shadow_reg_area, | |
2730 | qdev->rx_ring_shadow_reg_dma); | |
2731 | qdev->rx_ring_shadow_reg_area = NULL; | |
2732 | } | |
2733 | if (qdev->tx_ring_shadow_reg_area) { | |
2734 | pci_free_consistent(qdev->pdev, | |
2735 | PAGE_SIZE, | |
2736 | qdev->tx_ring_shadow_reg_area, | |
2737 | qdev->tx_ring_shadow_reg_dma); | |
2738 | qdev->tx_ring_shadow_reg_area = NULL; | |
2739 | } | |
2740 | } | |
2741 | ||
2742 | static int ql_alloc_shadow_space(struct ql_adapter *qdev) | |
2743 | { | |
2744 | qdev->rx_ring_shadow_reg_area = | |
440c734f JP |
2745 | pci_zalloc_consistent(qdev->pdev, PAGE_SIZE, |
2746 | &qdev->rx_ring_shadow_reg_dma); | |
c4e84bde | 2747 | if (qdev->rx_ring_shadow_reg_area == NULL) { |
ae9540f7 JP |
2748 | netif_err(qdev, ifup, qdev->ndev, |
2749 | "Allocation of RX shadow space failed.\n"); | |
c4e84bde RM |
2750 | return -ENOMEM; |
2751 | } | |
440c734f | 2752 | |
c4e84bde | 2753 | qdev->tx_ring_shadow_reg_area = |
440c734f JP |
2754 | pci_zalloc_consistent(qdev->pdev, PAGE_SIZE, |
2755 | &qdev->tx_ring_shadow_reg_dma); | |
c4e84bde | 2756 | if (qdev->tx_ring_shadow_reg_area == NULL) { |
ae9540f7 JP |
2757 | netif_err(qdev, ifup, qdev->ndev, |
2758 | "Allocation of TX shadow space failed.\n"); | |
c4e84bde RM |
2759 | goto err_wqp_sh_area; |
2760 | } | |
2761 | return 0; | |
2762 | ||
2763 | err_wqp_sh_area: | |
2764 | pci_free_consistent(qdev->pdev, | |
2765 | PAGE_SIZE, | |
2766 | qdev->rx_ring_shadow_reg_area, | |
2767 | qdev->rx_ring_shadow_reg_dma); | |
2768 | return -ENOMEM; | |
2769 | } | |
2770 | ||
2771 | static void ql_init_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring) | |
2772 | { | |
2773 | struct tx_ring_desc *tx_ring_desc; | |
2774 | int i; | |
2775 | struct ob_mac_iocb_req *mac_iocb_ptr; | |
2776 | ||
2777 | mac_iocb_ptr = tx_ring->wq_base; | |
2778 | tx_ring_desc = tx_ring->q; | |
2779 | for (i = 0; i < tx_ring->wq_len; i++) { | |
2780 | tx_ring_desc->index = i; | |
2781 | tx_ring_desc->skb = NULL; | |
2782 | tx_ring_desc->queue_entry = mac_iocb_ptr; | |
2783 | mac_iocb_ptr++; | |
2784 | tx_ring_desc++; | |
2785 | } | |
2786 | atomic_set(&tx_ring->tx_count, tx_ring->wq_len); | |
c4e84bde RM |
2787 | } |
2788 | ||
2789 | static void ql_free_tx_resources(struct ql_adapter *qdev, | |
2790 | struct tx_ring *tx_ring) | |
2791 | { | |
2792 | if (tx_ring->wq_base) { | |
2793 | pci_free_consistent(qdev->pdev, tx_ring->wq_size, | |
2794 | tx_ring->wq_base, tx_ring->wq_base_dma); | |
2795 | tx_ring->wq_base = NULL; | |
2796 | } | |
2797 | kfree(tx_ring->q); | |
2798 | tx_ring->q = NULL; | |
2799 | } | |
2800 | ||
2801 | static int ql_alloc_tx_resources(struct ql_adapter *qdev, | |
2802 | struct tx_ring *tx_ring) | |
2803 | { | |
2804 | tx_ring->wq_base = | |
2805 | pci_alloc_consistent(qdev->pdev, tx_ring->wq_size, | |
2806 | &tx_ring->wq_base_dma); | |
2807 | ||
8e95a202 | 2808 | if ((tx_ring->wq_base == NULL) || |
f5c4441c JK |
2809 | tx_ring->wq_base_dma & WQ_ADDR_ALIGN) |
2810 | goto pci_alloc_err; | |
2811 | ||
c4e84bde RM |
2812 | tx_ring->q = |
2813 | kmalloc(tx_ring->wq_len * sizeof(struct tx_ring_desc), GFP_KERNEL); | |
2814 | if (tx_ring->q == NULL) | |
2815 | goto err; | |
2816 | ||
2817 | return 0; | |
2818 | err: | |
2819 | pci_free_consistent(qdev->pdev, tx_ring->wq_size, | |
2820 | tx_ring->wq_base, tx_ring->wq_base_dma); | |
f5c4441c JK |
2821 | tx_ring->wq_base = NULL; |
2822 | pci_alloc_err: | |
2823 | netif_err(qdev, ifup, qdev->ndev, "tx_ring alloc failed.\n"); | |
c4e84bde RM |
2824 | return -ENOMEM; |
2825 | } | |
2826 | ||
8668ae92 | 2827 | static void ql_free_lbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring) |
c4e84bde | 2828 | { |
c4e84bde RM |
2829 | struct bq_desc *lbq_desc; |
2830 | ||
7c734359 RM |
2831 | uint32_t curr_idx, clean_idx; |
2832 | ||
2833 | curr_idx = rx_ring->lbq_curr_idx; | |
2834 | clean_idx = rx_ring->lbq_clean_idx; | |
2835 | while (curr_idx != clean_idx) { | |
2836 | lbq_desc = &rx_ring->lbq[curr_idx]; | |
2837 | ||
2838 | if (lbq_desc->p.pg_chunk.last_flag) { | |
c4e84bde | 2839 | pci_unmap_page(qdev->pdev, |
7c734359 RM |
2840 | lbq_desc->p.pg_chunk.map, |
2841 | ql_lbq_block_size(qdev), | |
c4e84bde | 2842 | PCI_DMA_FROMDEVICE); |
7c734359 | 2843 | lbq_desc->p.pg_chunk.last_flag = 0; |
c4e84bde | 2844 | } |
7c734359 RM |
2845 | |
2846 | put_page(lbq_desc->p.pg_chunk.page); | |
2847 | lbq_desc->p.pg_chunk.page = NULL; | |
2848 | ||
2849 | if (++curr_idx == rx_ring->lbq_len) | |
2850 | curr_idx = 0; | |
2851 | ||
c4e84bde | 2852 | } |
ef380794 TLSC |
2853 | if (rx_ring->pg_chunk.page) { |
2854 | pci_unmap_page(qdev->pdev, rx_ring->pg_chunk.map, | |
2855 | ql_lbq_block_size(qdev), PCI_DMA_FROMDEVICE); | |
2856 | put_page(rx_ring->pg_chunk.page); | |
2857 | rx_ring->pg_chunk.page = NULL; | |
2858 | } | |
c4e84bde RM |
2859 | } |
2860 | ||
8668ae92 | 2861 | static void ql_free_sbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring) |
c4e84bde RM |
2862 | { |
2863 | int i; | |
2864 | struct bq_desc *sbq_desc; | |
2865 | ||
2866 | for (i = 0; i < rx_ring->sbq_len; i++) { | |
2867 | sbq_desc = &rx_ring->sbq[i]; | |
2868 | if (sbq_desc == NULL) { | |
ae9540f7 JP |
2869 | netif_err(qdev, ifup, qdev->ndev, |
2870 | "sbq_desc %d is NULL.\n", i); | |
c4e84bde RM |
2871 | return; |
2872 | } | |
2873 | if (sbq_desc->p.skb) { | |
2874 | pci_unmap_single(qdev->pdev, | |
64b9b41d FT |
2875 | dma_unmap_addr(sbq_desc, mapaddr), |
2876 | dma_unmap_len(sbq_desc, maplen), | |
c4e84bde RM |
2877 | PCI_DMA_FROMDEVICE); |
2878 | dev_kfree_skb(sbq_desc->p.skb); | |
2879 | sbq_desc->p.skb = NULL; | |
2880 | } | |
c4e84bde RM |
2881 | } |
2882 | } | |
2883 | ||
4545a3f2 RM |
2884 | /* Free all large and small rx buffers associated |
2885 | * with the completion queues for this device. | |
2886 | */ | |
2887 | static void ql_free_rx_buffers(struct ql_adapter *qdev) | |
2888 | { | |
2889 | int i; | |
2890 | struct rx_ring *rx_ring; | |
2891 | ||
2892 | for (i = 0; i < qdev->rx_ring_count; i++) { | |
2893 | rx_ring = &qdev->rx_ring[i]; | |
2894 | if (rx_ring->lbq) | |
2895 | ql_free_lbq_buffers(qdev, rx_ring); | |
2896 | if (rx_ring->sbq) | |
2897 | ql_free_sbq_buffers(qdev, rx_ring); | |
2898 | } | |
2899 | } | |
2900 | ||
2901 | static void ql_alloc_rx_buffers(struct ql_adapter *qdev) | |
2902 | { | |
2903 | struct rx_ring *rx_ring; | |
2904 | int i; | |
2905 | ||
2906 | for (i = 0; i < qdev->rx_ring_count; i++) { | |
2907 | rx_ring = &qdev->rx_ring[i]; | |
2908 | if (rx_ring->type != TX_Q) | |
2909 | ql_update_buffer_queues(qdev, rx_ring); | |
2910 | } | |
2911 | } | |
2912 | ||
2913 | static void ql_init_lbq_ring(struct ql_adapter *qdev, | |
2914 | struct rx_ring *rx_ring) | |
2915 | { | |
2916 | int i; | |
2917 | struct bq_desc *lbq_desc; | |
2918 | __le64 *bq = rx_ring->lbq_base; | |
2919 | ||
2920 | memset(rx_ring->lbq, 0, rx_ring->lbq_len * sizeof(struct bq_desc)); | |
2921 | for (i = 0; i < rx_ring->lbq_len; i++) { | |
2922 | lbq_desc = &rx_ring->lbq[i]; | |
2923 | memset(lbq_desc, 0, sizeof(*lbq_desc)); | |
2924 | lbq_desc->index = i; | |
2925 | lbq_desc->addr = bq; | |
2926 | bq++; | |
2927 | } | |
2928 | } | |
2929 | ||
2930 | static void ql_init_sbq_ring(struct ql_adapter *qdev, | |
c4e84bde RM |
2931 | struct rx_ring *rx_ring) |
2932 | { | |
2933 | int i; | |
2934 | struct bq_desc *sbq_desc; | |
2c9a0d41 | 2935 | __le64 *bq = rx_ring->sbq_base; |
c4e84bde | 2936 | |
4545a3f2 | 2937 | memset(rx_ring->sbq, 0, rx_ring->sbq_len * sizeof(struct bq_desc)); |
c4e84bde RM |
2938 | for (i = 0; i < rx_ring->sbq_len; i++) { |
2939 | sbq_desc = &rx_ring->sbq[i]; | |
4545a3f2 | 2940 | memset(sbq_desc, 0, sizeof(*sbq_desc)); |
c4e84bde | 2941 | sbq_desc->index = i; |
2c9a0d41 | 2942 | sbq_desc->addr = bq; |
c4e84bde RM |
2943 | bq++; |
2944 | } | |
c4e84bde RM |
2945 | } |
2946 | ||
2947 | static void ql_free_rx_resources(struct ql_adapter *qdev, | |
2948 | struct rx_ring *rx_ring) | |
2949 | { | |
c4e84bde RM |
2950 | /* Free the small buffer queue. */ |
2951 | if (rx_ring->sbq_base) { | |
2952 | pci_free_consistent(qdev->pdev, | |
2953 | rx_ring->sbq_size, | |
2954 | rx_ring->sbq_base, rx_ring->sbq_base_dma); | |
2955 | rx_ring->sbq_base = NULL; | |
2956 | } | |
2957 | ||
2958 | /* Free the small buffer queue control blocks. */ | |
2959 | kfree(rx_ring->sbq); | |
2960 | rx_ring->sbq = NULL; | |
2961 | ||
2962 | /* Free the large buffer queue. */ | |
2963 | if (rx_ring->lbq_base) { | |
2964 | pci_free_consistent(qdev->pdev, | |
2965 | rx_ring->lbq_size, | |
2966 | rx_ring->lbq_base, rx_ring->lbq_base_dma); | |
2967 | rx_ring->lbq_base = NULL; | |
2968 | } | |
2969 | ||
2970 | /* Free the large buffer queue control blocks. */ | |
2971 | kfree(rx_ring->lbq); | |
2972 | rx_ring->lbq = NULL; | |
2973 | ||
2974 | /* Free the rx queue. */ | |
2975 | if (rx_ring->cq_base) { | |
2976 | pci_free_consistent(qdev->pdev, | |
2977 | rx_ring->cq_size, | |
2978 | rx_ring->cq_base, rx_ring->cq_base_dma); | |
2979 | rx_ring->cq_base = NULL; | |
2980 | } | |
2981 | } | |
2982 | ||
2983 | /* Allocate queues and buffers for this completions queue based | |
2984 | * on the values in the parameter structure. */ | |
2985 | static int ql_alloc_rx_resources(struct ql_adapter *qdev, | |
2986 | struct rx_ring *rx_ring) | |
2987 | { | |
2988 | ||
2989 | /* | |
2990 | * Allocate the completion queue for this rx_ring. | |
2991 | */ | |
2992 | rx_ring->cq_base = | |
2993 | pci_alloc_consistent(qdev->pdev, rx_ring->cq_size, | |
2994 | &rx_ring->cq_base_dma); | |
2995 | ||
2996 | if (rx_ring->cq_base == NULL) { | |
ae9540f7 | 2997 | netif_err(qdev, ifup, qdev->ndev, "rx_ring alloc failed.\n"); |
c4e84bde RM |
2998 | return -ENOMEM; |
2999 | } | |
3000 | ||
3001 | if (rx_ring->sbq_len) { | |
3002 | /* | |
3003 | * Allocate small buffer queue. | |
3004 | */ | |
3005 | rx_ring->sbq_base = | |
3006 | pci_alloc_consistent(qdev->pdev, rx_ring->sbq_size, | |
3007 | &rx_ring->sbq_base_dma); | |
3008 | ||
3009 | if (rx_ring->sbq_base == NULL) { | |
ae9540f7 JP |
3010 | netif_err(qdev, ifup, qdev->ndev, |
3011 | "Small buffer queue allocation failed.\n"); | |
c4e84bde RM |
3012 | goto err_mem; |
3013 | } | |
3014 | ||
3015 | /* | |
3016 | * Allocate small buffer queue control blocks. | |
3017 | */ | |
14f8dc49 JP |
3018 | rx_ring->sbq = kmalloc_array(rx_ring->sbq_len, |
3019 | sizeof(struct bq_desc), | |
3020 | GFP_KERNEL); | |
3021 | if (rx_ring->sbq == NULL) | |
c4e84bde | 3022 | goto err_mem; |
c4e84bde | 3023 | |
4545a3f2 | 3024 | ql_init_sbq_ring(qdev, rx_ring); |
c4e84bde RM |
3025 | } |
3026 | ||
3027 | if (rx_ring->lbq_len) { | |
3028 | /* | |
3029 | * Allocate large buffer queue. | |
3030 | */ | |
3031 | rx_ring->lbq_base = | |
3032 | pci_alloc_consistent(qdev->pdev, rx_ring->lbq_size, | |
3033 | &rx_ring->lbq_base_dma); | |
3034 | ||
3035 | if (rx_ring->lbq_base == NULL) { | |
ae9540f7 JP |
3036 | netif_err(qdev, ifup, qdev->ndev, |
3037 | "Large buffer queue allocation failed.\n"); | |
c4e84bde RM |
3038 | goto err_mem; |
3039 | } | |
3040 | /* | |
3041 | * Allocate large buffer queue control blocks. | |
3042 | */ | |
14f8dc49 JP |
3043 | rx_ring->lbq = kmalloc_array(rx_ring->lbq_len, |
3044 | sizeof(struct bq_desc), | |
3045 | GFP_KERNEL); | |
3046 | if (rx_ring->lbq == NULL) | |
c4e84bde | 3047 | goto err_mem; |
c4e84bde | 3048 | |
4545a3f2 | 3049 | ql_init_lbq_ring(qdev, rx_ring); |
c4e84bde RM |
3050 | } |
3051 | ||
3052 | return 0; | |
3053 | ||
3054 | err_mem: | |
3055 | ql_free_rx_resources(qdev, rx_ring); | |
3056 | return -ENOMEM; | |
3057 | } | |
3058 | ||
3059 | static void ql_tx_ring_clean(struct ql_adapter *qdev) | |
3060 | { | |
3061 | struct tx_ring *tx_ring; | |
3062 | struct tx_ring_desc *tx_ring_desc; | |
3063 | int i, j; | |
3064 | ||
3065 | /* | |
3066 | * Loop through all queues and free | |
3067 | * any resources. | |
3068 | */ | |
3069 | for (j = 0; j < qdev->tx_ring_count; j++) { | |
3070 | tx_ring = &qdev->tx_ring[j]; | |
3071 | for (i = 0; i < tx_ring->wq_len; i++) { | |
3072 | tx_ring_desc = &tx_ring->q[i]; | |
3073 | if (tx_ring_desc && tx_ring_desc->skb) { | |
ae9540f7 JP |
3074 | netif_err(qdev, ifdown, qdev->ndev, |
3075 | "Freeing lost SKB %p, from queue %d, index %d.\n", | |
3076 | tx_ring_desc->skb, j, | |
3077 | tx_ring_desc->index); | |
c4e84bde RM |
3078 | ql_unmap_send(qdev, tx_ring_desc, |
3079 | tx_ring_desc->map_cnt); | |
3080 | dev_kfree_skb(tx_ring_desc->skb); | |
3081 | tx_ring_desc->skb = NULL; | |
3082 | } | |
3083 | } | |
3084 | } | |
3085 | } | |
3086 | ||
c4e84bde RM |
3087 | static void ql_free_mem_resources(struct ql_adapter *qdev) |
3088 | { | |
3089 | int i; | |
3090 | ||
3091 | for (i = 0; i < qdev->tx_ring_count; i++) | |
3092 | ql_free_tx_resources(qdev, &qdev->tx_ring[i]); | |
3093 | for (i = 0; i < qdev->rx_ring_count; i++) | |
3094 | ql_free_rx_resources(qdev, &qdev->rx_ring[i]); | |
3095 | ql_free_shadow_space(qdev); | |
3096 | } | |
3097 | ||
3098 | static int ql_alloc_mem_resources(struct ql_adapter *qdev) | |
3099 | { | |
3100 | int i; | |
3101 | ||
3102 | /* Allocate space for our shadow registers and such. */ | |
3103 | if (ql_alloc_shadow_space(qdev)) | |
3104 | return -ENOMEM; | |
3105 | ||
3106 | for (i = 0; i < qdev->rx_ring_count; i++) { | |
3107 | if (ql_alloc_rx_resources(qdev, &qdev->rx_ring[i]) != 0) { | |
ae9540f7 JP |
3108 | netif_err(qdev, ifup, qdev->ndev, |
3109 | "RX resource allocation failed.\n"); | |
c4e84bde RM |
3110 | goto err_mem; |
3111 | } | |
3112 | } | |
3113 | /* Allocate tx queue resources */ | |
3114 | for (i = 0; i < qdev->tx_ring_count; i++) { | |
3115 | if (ql_alloc_tx_resources(qdev, &qdev->tx_ring[i]) != 0) { | |
ae9540f7 JP |
3116 | netif_err(qdev, ifup, qdev->ndev, |
3117 | "TX resource allocation failed.\n"); | |
c4e84bde RM |
3118 | goto err_mem; |
3119 | } | |
3120 | } | |
3121 | return 0; | |
3122 | ||
3123 | err_mem: | |
3124 | ql_free_mem_resources(qdev); | |
3125 | return -ENOMEM; | |
3126 | } | |
3127 | ||
3128 | /* Set up the rx ring control block and pass it to the chip. | |
3129 | * The control block is defined as | |
3130 | * "Completion Queue Initialization Control Block", or cqicb. | |
3131 | */ | |
3132 | static int ql_start_rx_ring(struct ql_adapter *qdev, struct rx_ring *rx_ring) | |
3133 | { | |
3134 | struct cqicb *cqicb = &rx_ring->cqicb; | |
3135 | void *shadow_reg = qdev->rx_ring_shadow_reg_area + | |
b8facca0 | 3136 | (rx_ring->cq_id * RX_RING_SHADOW_SPACE); |
c4e84bde | 3137 | u64 shadow_reg_dma = qdev->rx_ring_shadow_reg_dma + |
b8facca0 | 3138 | (rx_ring->cq_id * RX_RING_SHADOW_SPACE); |
c4e84bde RM |
3139 | void __iomem *doorbell_area = |
3140 | qdev->doorbell_area + (DB_PAGE_SIZE * (128 + rx_ring->cq_id)); | |
3141 | int err = 0; | |
3142 | u16 bq_len; | |
d4a4aba6 | 3143 | u64 tmp; |
b8facca0 RM |
3144 | __le64 *base_indirect_ptr; |
3145 | int page_entries; | |
c4e84bde RM |
3146 | |
3147 | /* Set up the shadow registers for this ring. */ | |
3148 | rx_ring->prod_idx_sh_reg = shadow_reg; | |
3149 | rx_ring->prod_idx_sh_reg_dma = shadow_reg_dma; | |
7c734359 | 3150 | *rx_ring->prod_idx_sh_reg = 0; |
c4e84bde RM |
3151 | shadow_reg += sizeof(u64); |
3152 | shadow_reg_dma += sizeof(u64); | |
3153 | rx_ring->lbq_base_indirect = shadow_reg; | |
3154 | rx_ring->lbq_base_indirect_dma = shadow_reg_dma; | |
b8facca0 RM |
3155 | shadow_reg += (sizeof(u64) * MAX_DB_PAGES_PER_BQ(rx_ring->lbq_len)); |
3156 | shadow_reg_dma += (sizeof(u64) * MAX_DB_PAGES_PER_BQ(rx_ring->lbq_len)); | |
c4e84bde RM |
3157 | rx_ring->sbq_base_indirect = shadow_reg; |
3158 | rx_ring->sbq_base_indirect_dma = shadow_reg_dma; | |
3159 | ||
3160 | /* PCI doorbell mem area + 0x00 for consumer index register */ | |
8668ae92 | 3161 | rx_ring->cnsmr_idx_db_reg = (u32 __iomem *) doorbell_area; |
c4e84bde RM |
3162 | rx_ring->cnsmr_idx = 0; |
3163 | rx_ring->curr_entry = rx_ring->cq_base; | |
3164 | ||
3165 | /* PCI doorbell mem area + 0x04 for valid register */ | |
3166 | rx_ring->valid_db_reg = doorbell_area + 0x04; | |
3167 | ||
3168 | /* PCI doorbell mem area + 0x18 for large buffer consumer */ | |
8668ae92 | 3169 | rx_ring->lbq_prod_idx_db_reg = (u32 __iomem *) (doorbell_area + 0x18); |
c4e84bde RM |
3170 | |
3171 | /* PCI doorbell mem area + 0x1c */ | |
8668ae92 | 3172 | rx_ring->sbq_prod_idx_db_reg = (u32 __iomem *) (doorbell_area + 0x1c); |
c4e84bde RM |
3173 | |
3174 | memset((void *)cqicb, 0, sizeof(struct cqicb)); | |
3175 | cqicb->msix_vect = rx_ring->irq; | |
3176 | ||
459caf5a RM |
3177 | bq_len = (rx_ring->cq_len == 65536) ? 0 : (u16) rx_ring->cq_len; |
3178 | cqicb->len = cpu_to_le16(bq_len | LEN_V | LEN_CPP_CONT); | |
c4e84bde | 3179 | |
97345524 | 3180 | cqicb->addr = cpu_to_le64(rx_ring->cq_base_dma); |
c4e84bde | 3181 | |
97345524 | 3182 | cqicb->prod_idx_addr = cpu_to_le64(rx_ring->prod_idx_sh_reg_dma); |
c4e84bde RM |
3183 | |
3184 | /* | |
3185 | * Set up the control block load flags. | |
3186 | */ | |
3187 | cqicb->flags = FLAGS_LC | /* Load queue base address */ | |
3188 | FLAGS_LV | /* Load MSI-X vector */ | |
3189 | FLAGS_LI; /* Load irq delay values */ | |
3190 | if (rx_ring->lbq_len) { | |
3191 | cqicb->flags |= FLAGS_LL; /* Load lbq values */ | |
a419aef8 | 3192 | tmp = (u64)rx_ring->lbq_base_dma; |
43d620c8 | 3193 | base_indirect_ptr = rx_ring->lbq_base_indirect; |
b8facca0 RM |
3194 | page_entries = 0; |
3195 | do { | |
3196 | *base_indirect_ptr = cpu_to_le64(tmp); | |
3197 | tmp += DB_PAGE_SIZE; | |
3198 | base_indirect_ptr++; | |
3199 | page_entries++; | |
3200 | } while (page_entries < MAX_DB_PAGES_PER_BQ(rx_ring->lbq_len)); | |
97345524 RM |
3201 | cqicb->lbq_addr = |
3202 | cpu_to_le64(rx_ring->lbq_base_indirect_dma); | |
459caf5a RM |
3203 | bq_len = (rx_ring->lbq_buf_size == 65536) ? 0 : |
3204 | (u16) rx_ring->lbq_buf_size; | |
3205 | cqicb->lbq_buf_size = cpu_to_le16(bq_len); | |
3206 | bq_len = (rx_ring->lbq_len == 65536) ? 0 : | |
3207 | (u16) rx_ring->lbq_len; | |
c4e84bde | 3208 | cqicb->lbq_len = cpu_to_le16(bq_len); |
4545a3f2 | 3209 | rx_ring->lbq_prod_idx = 0; |
c4e84bde | 3210 | rx_ring->lbq_curr_idx = 0; |
4545a3f2 RM |
3211 | rx_ring->lbq_clean_idx = 0; |
3212 | rx_ring->lbq_free_cnt = rx_ring->lbq_len; | |
c4e84bde RM |
3213 | } |
3214 | if (rx_ring->sbq_len) { | |
3215 | cqicb->flags |= FLAGS_LS; /* Load sbq values */ | |
a419aef8 | 3216 | tmp = (u64)rx_ring->sbq_base_dma; |
43d620c8 | 3217 | base_indirect_ptr = rx_ring->sbq_base_indirect; |
b8facca0 RM |
3218 | page_entries = 0; |
3219 | do { | |
3220 | *base_indirect_ptr = cpu_to_le64(tmp); | |
3221 | tmp += DB_PAGE_SIZE; | |
3222 | base_indirect_ptr++; | |
3223 | page_entries++; | |
3224 | } while (page_entries < MAX_DB_PAGES_PER_BQ(rx_ring->sbq_len)); | |
97345524 RM |
3225 | cqicb->sbq_addr = |
3226 | cpu_to_le64(rx_ring->sbq_base_indirect_dma); | |
c4e84bde | 3227 | cqicb->sbq_buf_size = |
52e55f3c | 3228 | cpu_to_le16((u16)(rx_ring->sbq_buf_size)); |
459caf5a RM |
3229 | bq_len = (rx_ring->sbq_len == 65536) ? 0 : |
3230 | (u16) rx_ring->sbq_len; | |
c4e84bde | 3231 | cqicb->sbq_len = cpu_to_le16(bq_len); |
4545a3f2 | 3232 | rx_ring->sbq_prod_idx = 0; |
c4e84bde | 3233 | rx_ring->sbq_curr_idx = 0; |
4545a3f2 RM |
3234 | rx_ring->sbq_clean_idx = 0; |
3235 | rx_ring->sbq_free_cnt = rx_ring->sbq_len; | |
c4e84bde RM |
3236 | } |
3237 | switch (rx_ring->type) { | |
3238 | case TX_Q: | |
c4e84bde RM |
3239 | cqicb->irq_delay = cpu_to_le16(qdev->tx_coalesce_usecs); |
3240 | cqicb->pkt_delay = cpu_to_le16(qdev->tx_max_coalesced_frames); | |
3241 | break; | |
c4e84bde RM |
3242 | case RX_Q: |
3243 | /* Inbound completion handling rx_rings run in | |
3244 | * separate NAPI contexts. | |
3245 | */ | |
3246 | netif_napi_add(qdev->ndev, &rx_ring->napi, ql_napi_poll_msix, | |
3247 | 64); | |
3248 | cqicb->irq_delay = cpu_to_le16(qdev->rx_coalesce_usecs); | |
3249 | cqicb->pkt_delay = cpu_to_le16(qdev->rx_max_coalesced_frames); | |
3250 | break; | |
3251 | default: | |
ae9540f7 JP |
3252 | netif_printk(qdev, ifup, KERN_DEBUG, qdev->ndev, |
3253 | "Invalid rx_ring->type = %d.\n", rx_ring->type); | |
c4e84bde | 3254 | } |
c4e84bde RM |
3255 | err = ql_write_cfg(qdev, cqicb, sizeof(struct cqicb), |
3256 | CFG_LCQ, rx_ring->cq_id); | |
3257 | if (err) { | |
ae9540f7 | 3258 | netif_err(qdev, ifup, qdev->ndev, "Failed to load CQICB.\n"); |
c4e84bde RM |
3259 | return err; |
3260 | } | |
c4e84bde RM |
3261 | return err; |
3262 | } | |
3263 | ||
3264 | static int ql_start_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring) | |
3265 | { | |
3266 | struct wqicb *wqicb = (struct wqicb *)tx_ring; | |
3267 | void __iomem *doorbell_area = | |
3268 | qdev->doorbell_area + (DB_PAGE_SIZE * tx_ring->wq_id); | |
3269 | void *shadow_reg = qdev->tx_ring_shadow_reg_area + | |
3270 | (tx_ring->wq_id * sizeof(u64)); | |
3271 | u64 shadow_reg_dma = qdev->tx_ring_shadow_reg_dma + | |
3272 | (tx_ring->wq_id * sizeof(u64)); | |
3273 | int err = 0; | |
3274 | ||
3275 | /* | |
3276 | * Assign doorbell registers for this tx_ring. | |
3277 | */ | |
3278 | /* TX PCI doorbell mem area for tx producer index */ | |
8668ae92 | 3279 | tx_ring->prod_idx_db_reg = (u32 __iomem *) doorbell_area; |
c4e84bde RM |
3280 | tx_ring->prod_idx = 0; |
3281 | /* TX PCI doorbell mem area + 0x04 */ | |
3282 | tx_ring->valid_db_reg = doorbell_area + 0x04; | |
3283 | ||
3284 | /* | |
3285 | * Assign shadow registers for this tx_ring. | |
3286 | */ | |
3287 | tx_ring->cnsmr_idx_sh_reg = shadow_reg; | |
3288 | tx_ring->cnsmr_idx_sh_reg_dma = shadow_reg_dma; | |
3289 | ||
3290 | wqicb->len = cpu_to_le16(tx_ring->wq_len | Q_LEN_V | Q_LEN_CPP_CONT); | |
3291 | wqicb->flags = cpu_to_le16(Q_FLAGS_LC | | |
3292 | Q_FLAGS_LB | Q_FLAGS_LI | Q_FLAGS_LO); | |
3293 | wqicb->cq_id_rss = cpu_to_le16(tx_ring->cq_id); | |
3294 | wqicb->rid = 0; | |
97345524 | 3295 | wqicb->addr = cpu_to_le64(tx_ring->wq_base_dma); |
c4e84bde | 3296 | |
97345524 | 3297 | wqicb->cnsmr_idx_addr = cpu_to_le64(tx_ring->cnsmr_idx_sh_reg_dma); |
c4e84bde RM |
3298 | |
3299 | ql_init_tx_ring(qdev, tx_ring); | |
3300 | ||
e332471c | 3301 | err = ql_write_cfg(qdev, wqicb, sizeof(*wqicb), CFG_LRQ, |
c4e84bde RM |
3302 | (u16) tx_ring->wq_id); |
3303 | if (err) { | |
ae9540f7 | 3304 | netif_err(qdev, ifup, qdev->ndev, "Failed to load tx_ring.\n"); |
c4e84bde RM |
3305 | return err; |
3306 | } | |
c4e84bde RM |
3307 | return err; |
3308 | } | |
3309 | ||
3310 | static void ql_disable_msix(struct ql_adapter *qdev) | |
3311 | { | |
3312 | if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) { | |
3313 | pci_disable_msix(qdev->pdev); | |
3314 | clear_bit(QL_MSIX_ENABLED, &qdev->flags); | |
3315 | kfree(qdev->msi_x_entry); | |
3316 | qdev->msi_x_entry = NULL; | |
3317 | } else if (test_bit(QL_MSI_ENABLED, &qdev->flags)) { | |
3318 | pci_disable_msi(qdev->pdev); | |
3319 | clear_bit(QL_MSI_ENABLED, &qdev->flags); | |
3320 | } | |
3321 | } | |
3322 | ||
a4ab6137 RM |
3323 | /* We start by trying to get the number of vectors |
3324 | * stored in qdev->intr_count. If we don't get that | |
3325 | * many then we reduce the count and try again. | |
3326 | */ | |
c4e84bde RM |
3327 | static void ql_enable_msix(struct ql_adapter *qdev) |
3328 | { | |
a4ab6137 | 3329 | int i, err; |
c4e84bde | 3330 | |
c4e84bde | 3331 | /* Get the MSIX vectors. */ |
a5a62a1c | 3332 | if (qlge_irq_type == MSIX_IRQ) { |
c4e84bde RM |
3333 | /* Try to alloc space for the msix struct, |
3334 | * if it fails then go to MSI/legacy. | |
3335 | */ | |
a4ab6137 | 3336 | qdev->msi_x_entry = kcalloc(qdev->intr_count, |
c4e84bde RM |
3337 | sizeof(struct msix_entry), |
3338 | GFP_KERNEL); | |
3339 | if (!qdev->msi_x_entry) { | |
a5a62a1c | 3340 | qlge_irq_type = MSI_IRQ; |
c4e84bde RM |
3341 | goto msi; |
3342 | } | |
3343 | ||
a4ab6137 | 3344 | for (i = 0; i < qdev->intr_count; i++) |
c4e84bde RM |
3345 | qdev->msi_x_entry[i].entry = i; |
3346 | ||
50b483a1 AG |
3347 | err = pci_enable_msix_range(qdev->pdev, qdev->msi_x_entry, |
3348 | 1, qdev->intr_count); | |
a4ab6137 | 3349 | if (err < 0) { |
c4e84bde RM |
3350 | kfree(qdev->msi_x_entry); |
3351 | qdev->msi_x_entry = NULL; | |
ae9540f7 JP |
3352 | netif_warn(qdev, ifup, qdev->ndev, |
3353 | "MSI-X Enable failed, trying MSI.\n"); | |
a5a62a1c | 3354 | qlge_irq_type = MSI_IRQ; |
50b483a1 AG |
3355 | } else { |
3356 | qdev->intr_count = err; | |
a4ab6137 | 3357 | set_bit(QL_MSIX_ENABLED, &qdev->flags); |
ae9540f7 JP |
3358 | netif_info(qdev, ifup, qdev->ndev, |
3359 | "MSI-X Enabled, got %d vectors.\n", | |
3360 | qdev->intr_count); | |
a4ab6137 | 3361 | return; |
c4e84bde RM |
3362 | } |
3363 | } | |
3364 | msi: | |
a4ab6137 | 3365 | qdev->intr_count = 1; |
a5a62a1c | 3366 | if (qlge_irq_type == MSI_IRQ) { |
c4e84bde RM |
3367 | if (!pci_enable_msi(qdev->pdev)) { |
3368 | set_bit(QL_MSI_ENABLED, &qdev->flags); | |
ae9540f7 JP |
3369 | netif_info(qdev, ifup, qdev->ndev, |
3370 | "Running with MSI interrupts.\n"); | |
c4e84bde RM |
3371 | return; |
3372 | } | |
3373 | } | |
a5a62a1c | 3374 | qlge_irq_type = LEG_IRQ; |
ae9540f7 JP |
3375 | netif_printk(qdev, ifup, KERN_DEBUG, qdev->ndev, |
3376 | "Running with legacy interrupts.\n"); | |
c4e84bde RM |
3377 | } |
3378 | ||
39aa8165 RM |
3379 | /* Each vector services 1 RSS ring and and 1 or more |
3380 | * TX completion rings. This function loops through | |
3381 | * the TX completion rings and assigns the vector that | |
3382 | * will service it. An example would be if there are | |
3383 | * 2 vectors (so 2 RSS rings) and 8 TX completion rings. | |
3384 | * This would mean that vector 0 would service RSS ring 0 | |
25985edc | 3385 | * and TX completion rings 0,1,2 and 3. Vector 1 would |
39aa8165 RM |
3386 | * service RSS ring 1 and TX completion rings 4,5,6 and 7. |
3387 | */ | |
3388 | static void ql_set_tx_vect(struct ql_adapter *qdev) | |
3389 | { | |
3390 | int i, j, vect; | |
3391 | u32 tx_rings_per_vector = qdev->tx_ring_count / qdev->intr_count; | |
3392 | ||
3393 | if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags))) { | |
3394 | /* Assign irq vectors to TX rx_rings.*/ | |
3395 | for (vect = 0, j = 0, i = qdev->rss_ring_count; | |
3396 | i < qdev->rx_ring_count; i++) { | |
3397 | if (j == tx_rings_per_vector) { | |
3398 | vect++; | |
3399 | j = 0; | |
3400 | } | |
3401 | qdev->rx_ring[i].irq = vect; | |
3402 | j++; | |
3403 | } | |
3404 | } else { | |
3405 | /* For single vector all rings have an irq | |
3406 | * of zero. | |
3407 | */ | |
3408 | for (i = 0; i < qdev->rx_ring_count; i++) | |
3409 | qdev->rx_ring[i].irq = 0; | |
3410 | } | |
3411 | } | |
3412 | ||
3413 | /* Set the interrupt mask for this vector. Each vector | |
3414 | * will service 1 RSS ring and 1 or more TX completion | |
3415 | * rings. This function sets up a bit mask per vector | |
3416 | * that indicates which rings it services. | |
3417 | */ | |
3418 | static void ql_set_irq_mask(struct ql_adapter *qdev, struct intr_context *ctx) | |
3419 | { | |
3420 | int j, vect = ctx->intr; | |
3421 | u32 tx_rings_per_vector = qdev->tx_ring_count / qdev->intr_count; | |
3422 | ||
3423 | if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags))) { | |
3424 | /* Add the RSS ring serviced by this vector | |
3425 | * to the mask. | |
3426 | */ | |
3427 | ctx->irq_mask = (1 << qdev->rx_ring[vect].cq_id); | |
3428 | /* Add the TX ring(s) serviced by this vector | |
3429 | * to the mask. */ | |
3430 | for (j = 0; j < tx_rings_per_vector; j++) { | |
3431 | ctx->irq_mask |= | |
3432 | (1 << qdev->rx_ring[qdev->rss_ring_count + | |
3433 | (vect * tx_rings_per_vector) + j].cq_id); | |
3434 | } | |
3435 | } else { | |
3436 | /* For single vector we just shift each queue's | |
3437 | * ID into the mask. | |
3438 | */ | |
3439 | for (j = 0; j < qdev->rx_ring_count; j++) | |
3440 | ctx->irq_mask |= (1 << qdev->rx_ring[j].cq_id); | |
3441 | } | |
3442 | } | |
3443 | ||
c4e84bde RM |
3444 | /* |
3445 | * Here we build the intr_context structures based on | |
3446 | * our rx_ring count and intr vector count. | |
3447 | * The intr_context structure is used to hook each vector | |
3448 | * to possibly different handlers. | |
3449 | */ | |
3450 | static void ql_resolve_queues_to_irqs(struct ql_adapter *qdev) | |
3451 | { | |
3452 | int i = 0; | |
3453 | struct intr_context *intr_context = &qdev->intr_context[0]; | |
3454 | ||
c4e84bde RM |
3455 | if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags))) { |
3456 | /* Each rx_ring has it's | |
3457 | * own intr_context since we have separate | |
3458 | * vectors for each queue. | |
c4e84bde RM |
3459 | */ |
3460 | for (i = 0; i < qdev->intr_count; i++, intr_context++) { | |
3461 | qdev->rx_ring[i].irq = i; | |
3462 | intr_context->intr = i; | |
3463 | intr_context->qdev = qdev; | |
39aa8165 RM |
3464 | /* Set up this vector's bit-mask that indicates |
3465 | * which queues it services. | |
3466 | */ | |
3467 | ql_set_irq_mask(qdev, intr_context); | |
c4e84bde RM |
3468 | /* |
3469 | * We set up each vectors enable/disable/read bits so | |
3470 | * there's no bit/mask calculations in the critical path. | |
3471 | */ | |
3472 | intr_context->intr_en_mask = | |
3473 | INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | | |
3474 | INTR_EN_TYPE_ENABLE | INTR_EN_IHD_MASK | INTR_EN_IHD | |
3475 | | i; | |
3476 | intr_context->intr_dis_mask = | |
3477 | INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | | |
3478 | INTR_EN_TYPE_DISABLE | INTR_EN_IHD_MASK | | |
3479 | INTR_EN_IHD | i; | |
3480 | intr_context->intr_read_mask = | |
3481 | INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | | |
3482 | INTR_EN_TYPE_READ | INTR_EN_IHD_MASK | INTR_EN_IHD | | |
3483 | i; | |
39aa8165 RM |
3484 | if (i == 0) { |
3485 | /* The first vector/queue handles | |
3486 | * broadcast/multicast, fatal errors, | |
3487 | * and firmware events. This in addition | |
3488 | * to normal inbound NAPI processing. | |
c4e84bde | 3489 | */ |
39aa8165 | 3490 | intr_context->handler = qlge_isr; |
b2014ff8 RM |
3491 | sprintf(intr_context->name, "%s-rx-%d", |
3492 | qdev->ndev->name, i); | |
3493 | } else { | |
c4e84bde | 3494 | /* |
39aa8165 | 3495 | * Inbound queues handle unicast frames only. |
c4e84bde | 3496 | */ |
39aa8165 RM |
3497 | intr_context->handler = qlge_msix_rx_isr; |
3498 | sprintf(intr_context->name, "%s-rx-%d", | |
c4e84bde | 3499 | qdev->ndev->name, i); |
c4e84bde RM |
3500 | } |
3501 | } | |
3502 | } else { | |
3503 | /* | |
3504 | * All rx_rings use the same intr_context since | |
3505 | * there is only one vector. | |
3506 | */ | |
3507 | intr_context->intr = 0; | |
3508 | intr_context->qdev = qdev; | |
3509 | /* | |
3510 | * We set up each vectors enable/disable/read bits so | |
3511 | * there's no bit/mask calculations in the critical path. | |
3512 | */ | |
3513 | intr_context->intr_en_mask = | |
3514 | INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_ENABLE; | |
3515 | intr_context->intr_dis_mask = | |
3516 | INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | | |
3517 | INTR_EN_TYPE_DISABLE; | |
3518 | intr_context->intr_read_mask = | |
3519 | INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_READ; | |
3520 | /* | |
3521 | * Single interrupt means one handler for all rings. | |
3522 | */ | |
3523 | intr_context->handler = qlge_isr; | |
3524 | sprintf(intr_context->name, "%s-single_irq", qdev->ndev->name); | |
39aa8165 RM |
3525 | /* Set up this vector's bit-mask that indicates |
3526 | * which queues it services. In this case there is | |
3527 | * a single vector so it will service all RSS and | |
3528 | * TX completion rings. | |
3529 | */ | |
3530 | ql_set_irq_mask(qdev, intr_context); | |
c4e84bde | 3531 | } |
39aa8165 RM |
3532 | /* Tell the TX completion rings which MSIx vector |
3533 | * they will be using. | |
3534 | */ | |
3535 | ql_set_tx_vect(qdev); | |
c4e84bde RM |
3536 | } |
3537 | ||
3538 | static void ql_free_irq(struct ql_adapter *qdev) | |
3539 | { | |
3540 | int i; | |
3541 | struct intr_context *intr_context = &qdev->intr_context[0]; | |
3542 | ||
3543 | for (i = 0; i < qdev->intr_count; i++, intr_context++) { | |
3544 | if (intr_context->hooked) { | |
3545 | if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) { | |
3546 | free_irq(qdev->msi_x_entry[i].vector, | |
3547 | &qdev->rx_ring[i]); | |
c4e84bde RM |
3548 | } else { |
3549 | free_irq(qdev->pdev->irq, &qdev->rx_ring[0]); | |
c4e84bde RM |
3550 | } |
3551 | } | |
3552 | } | |
3553 | ql_disable_msix(qdev); | |
3554 | } | |
3555 | ||
3556 | static int ql_request_irq(struct ql_adapter *qdev) | |
3557 | { | |
3558 | int i; | |
3559 | int status = 0; | |
3560 | struct pci_dev *pdev = qdev->pdev; | |
3561 | struct intr_context *intr_context = &qdev->intr_context[0]; | |
3562 | ||
3563 | ql_resolve_queues_to_irqs(qdev); | |
3564 | ||
3565 | for (i = 0; i < qdev->intr_count; i++, intr_context++) { | |
3566 | atomic_set(&intr_context->irq_cnt, 0); | |
3567 | if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) { | |
3568 | status = request_irq(qdev->msi_x_entry[i].vector, | |
3569 | intr_context->handler, | |
3570 | 0, | |
3571 | intr_context->name, | |
3572 | &qdev->rx_ring[i]); | |
3573 | if (status) { | |
ae9540f7 JP |
3574 | netif_err(qdev, ifup, qdev->ndev, |
3575 | "Failed request for MSIX interrupt %d.\n", | |
3576 | i); | |
c4e84bde | 3577 | goto err_irq; |
c4e84bde RM |
3578 | } |
3579 | } else { | |
ae9540f7 JP |
3580 | netif_printk(qdev, ifup, KERN_DEBUG, qdev->ndev, |
3581 | "trying msi or legacy interrupts.\n"); | |
3582 | netif_printk(qdev, ifup, KERN_DEBUG, qdev->ndev, | |
3583 | "%s: irq = %d.\n", __func__, pdev->irq); | |
3584 | netif_printk(qdev, ifup, KERN_DEBUG, qdev->ndev, | |
3585 | "%s: context->name = %s.\n", __func__, | |
3586 | intr_context->name); | |
3587 | netif_printk(qdev, ifup, KERN_DEBUG, qdev->ndev, | |
3588 | "%s: dev_id = 0x%p.\n", __func__, | |
3589 | &qdev->rx_ring[0]); | |
c4e84bde RM |
3590 | status = |
3591 | request_irq(pdev->irq, qlge_isr, | |
3592 | test_bit(QL_MSI_ENABLED, | |
3593 | &qdev-> | |
3594 | flags) ? 0 : IRQF_SHARED, | |
3595 | intr_context->name, &qdev->rx_ring[0]); | |
3596 | if (status) | |
3597 | goto err_irq; | |
3598 | ||
ae9540f7 JP |
3599 | netif_err(qdev, ifup, qdev->ndev, |
3600 | "Hooked intr %d, queue type %s, with name %s.\n", | |
3601 | i, | |
3602 | qdev->rx_ring[0].type == DEFAULT_Q ? | |
3603 | "DEFAULT_Q" : | |
3604 | qdev->rx_ring[0].type == TX_Q ? "TX_Q" : | |
3605 | qdev->rx_ring[0].type == RX_Q ? "RX_Q" : "", | |
3606 | intr_context->name); | |
c4e84bde RM |
3607 | } |
3608 | intr_context->hooked = 1; | |
3609 | } | |
3610 | return status; | |
3611 | err_irq: | |
a42c3a28 | 3612 | netif_err(qdev, ifup, qdev->ndev, "Failed to get the interrupts!!!\n"); |
c4e84bde RM |
3613 | ql_free_irq(qdev); |
3614 | return status; | |
3615 | } | |
3616 | ||
3617 | static int ql_start_rss(struct ql_adapter *qdev) | |
3618 | { | |
215faf9c JP |
3619 | static const u8 init_hash_seed[] = { |
3620 | 0x6d, 0x5a, 0x56, 0xda, 0x25, 0x5b, 0x0e, 0xc2, | |
3621 | 0x41, 0x67, 0x25, 0x3d, 0x43, 0xa3, 0x8f, 0xb0, | |
3622 | 0xd0, 0xca, 0x2b, 0xcb, 0xae, 0x7b, 0x30, 0xb4, | |
3623 | 0x77, 0xcb, 0x2d, 0xa3, 0x80, 0x30, 0xf2, 0x0c, | |
3624 | 0x6a, 0x42, 0xb7, 0x3b, 0xbe, 0xac, 0x01, 0xfa | |
3625 | }; | |
c4e84bde RM |
3626 | struct ricb *ricb = &qdev->ricb; |
3627 | int status = 0; | |
3628 | int i; | |
3629 | u8 *hash_id = (u8 *) ricb->hash_cq_id; | |
3630 | ||
e332471c | 3631 | memset((void *)ricb, 0, sizeof(*ricb)); |
c4e84bde | 3632 | |
b2014ff8 | 3633 | ricb->base_cq = RSS_L4K; |
c4e84bde | 3634 | ricb->flags = |
541ae28c RM |
3635 | (RSS_L6K | RSS_LI | RSS_LB | RSS_LM | RSS_RT4 | RSS_RT6); |
3636 | ricb->mask = cpu_to_le16((u16)(0x3ff)); | |
c4e84bde RM |
3637 | |
3638 | /* | |
3639 | * Fill out the Indirection Table. | |
3640 | */ | |
541ae28c RM |
3641 | for (i = 0; i < 1024; i++) |
3642 | hash_id[i] = (i & (qdev->rss_ring_count - 1)); | |
c4e84bde | 3643 | |
541ae28c RM |
3644 | memcpy((void *)&ricb->ipv6_hash_key[0], init_hash_seed, 40); |
3645 | memcpy((void *)&ricb->ipv4_hash_key[0], init_hash_seed, 16); | |
c4e84bde | 3646 | |
e332471c | 3647 | status = ql_write_cfg(qdev, ricb, sizeof(*ricb), CFG_LR, 0); |
c4e84bde | 3648 | if (status) { |
ae9540f7 | 3649 | netif_err(qdev, ifup, qdev->ndev, "Failed to load RICB.\n"); |
c4e84bde RM |
3650 | return status; |
3651 | } | |
c4e84bde RM |
3652 | return status; |
3653 | } | |
3654 | ||
a5f59dc9 | 3655 | static int ql_clear_routing_entries(struct ql_adapter *qdev) |
c4e84bde | 3656 | { |
a5f59dc9 | 3657 | int i, status = 0; |
c4e84bde | 3658 | |
8587ea35 RM |
3659 | status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK); |
3660 | if (status) | |
3661 | return status; | |
c4e84bde RM |
3662 | /* Clear all the entries in the routing table. */ |
3663 | for (i = 0; i < 16; i++) { | |
3664 | status = ql_set_routing_reg(qdev, i, 0, 0); | |
3665 | if (status) { | |
ae9540f7 JP |
3666 | netif_err(qdev, ifup, qdev->ndev, |
3667 | "Failed to init routing register for CAM packets.\n"); | |
a5f59dc9 | 3668 | break; |
c4e84bde RM |
3669 | } |
3670 | } | |
a5f59dc9 RM |
3671 | ql_sem_unlock(qdev, SEM_RT_IDX_MASK); |
3672 | return status; | |
3673 | } | |
3674 | ||
3675 | /* Initialize the frame-to-queue routing. */ | |
3676 | static int ql_route_initialize(struct ql_adapter *qdev) | |
3677 | { | |
3678 | int status = 0; | |
3679 | ||
fd21cf52 RM |
3680 | /* Clear all the entries in the routing table. */ |
3681 | status = ql_clear_routing_entries(qdev); | |
a5f59dc9 RM |
3682 | if (status) |
3683 | return status; | |
3684 | ||
fd21cf52 | 3685 | status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK); |
a5f59dc9 | 3686 | if (status) |
fd21cf52 | 3687 | return status; |
c4e84bde | 3688 | |
fbc2ac33 RM |
3689 | status = ql_set_routing_reg(qdev, RT_IDX_IP_CSUM_ERR_SLOT, |
3690 | RT_IDX_IP_CSUM_ERR, 1); | |
3691 | if (status) { | |
3692 | netif_err(qdev, ifup, qdev->ndev, | |
3693 | "Failed to init routing register " | |
3694 | "for IP CSUM error packets.\n"); | |
3695 | goto exit; | |
3696 | } | |
3697 | status = ql_set_routing_reg(qdev, RT_IDX_TCP_UDP_CSUM_ERR_SLOT, | |
3698 | RT_IDX_TU_CSUM_ERR, 1); | |
c4e84bde | 3699 | if (status) { |
ae9540f7 | 3700 | netif_err(qdev, ifup, qdev->ndev, |
fbc2ac33 RM |
3701 | "Failed to init routing register " |
3702 | "for TCP/UDP CSUM error packets.\n"); | |
8587ea35 | 3703 | goto exit; |
c4e84bde RM |
3704 | } |
3705 | status = ql_set_routing_reg(qdev, RT_IDX_BCAST_SLOT, RT_IDX_BCAST, 1); | |
3706 | if (status) { | |
ae9540f7 JP |
3707 | netif_err(qdev, ifup, qdev->ndev, |
3708 | "Failed to init routing register for broadcast packets.\n"); | |
8587ea35 | 3709 | goto exit; |
c4e84bde RM |
3710 | } |
3711 | /* If we have more than one inbound queue, then turn on RSS in the | |
3712 | * routing block. | |
3713 | */ | |
3714 | if (qdev->rss_ring_count > 1) { | |
3715 | status = ql_set_routing_reg(qdev, RT_IDX_RSS_MATCH_SLOT, | |
3716 | RT_IDX_RSS_MATCH, 1); | |
3717 | if (status) { | |
ae9540f7 JP |
3718 | netif_err(qdev, ifup, qdev->ndev, |
3719 | "Failed to init routing register for MATCH RSS packets.\n"); | |
8587ea35 | 3720 | goto exit; |
c4e84bde RM |
3721 | } |
3722 | } | |
3723 | ||
3724 | status = ql_set_routing_reg(qdev, RT_IDX_CAM_HIT_SLOT, | |
3725 | RT_IDX_CAM_HIT, 1); | |
8587ea35 | 3726 | if (status) |
ae9540f7 JP |
3727 | netif_err(qdev, ifup, qdev->ndev, |
3728 | "Failed to init routing register for CAM packets.\n"); | |
8587ea35 RM |
3729 | exit: |
3730 | ql_sem_unlock(qdev, SEM_RT_IDX_MASK); | |
c4e84bde RM |
3731 | return status; |
3732 | } | |
3733 | ||
2ee1e272 | 3734 | int ql_cam_route_initialize(struct ql_adapter *qdev) |
bb58b5b6 | 3735 | { |
7fab3bfe | 3736 | int status, set; |
bb58b5b6 | 3737 | |
7fab3bfe RM |
3738 | /* If check if the link is up and use to |
3739 | * determine if we are setting or clearing | |
3740 | * the MAC address in the CAM. | |
3741 | */ | |
3742 | set = ql_read32(qdev, STS); | |
3743 | set &= qdev->port_link_up; | |
3744 | status = ql_set_mac_addr(qdev, set); | |
bb58b5b6 | 3745 | if (status) { |
ae9540f7 | 3746 | netif_err(qdev, ifup, qdev->ndev, "Failed to init mac address.\n"); |
bb58b5b6 RM |
3747 | return status; |
3748 | } | |
3749 | ||
3750 | status = ql_route_initialize(qdev); | |
3751 | if (status) | |
ae9540f7 | 3752 | netif_err(qdev, ifup, qdev->ndev, "Failed to init routing table.\n"); |
bb58b5b6 RM |
3753 | |
3754 | return status; | |
3755 | } | |
3756 | ||
c4e84bde RM |
3757 | static int ql_adapter_initialize(struct ql_adapter *qdev) |
3758 | { | |
3759 | u32 value, mask; | |
3760 | int i; | |
3761 | int status = 0; | |
3762 | ||
3763 | /* | |
3764 | * Set up the System register to halt on errors. | |
3765 | */ | |
3766 | value = SYS_EFE | SYS_FAE; | |
3767 | mask = value << 16; | |
3768 | ql_write32(qdev, SYS, mask | value); | |
3769 | ||
c9cf0a04 | 3770 | /* Set the default queue, and VLAN behavior. */ |
a45adbe8 JK |
3771 | value = NIC_RCV_CFG_DFQ; |
3772 | mask = NIC_RCV_CFG_DFQ_MASK; | |
3773 | if (qdev->ndev->features & NETIF_F_HW_VLAN_CTAG_RX) { | |
3774 | value |= NIC_RCV_CFG_RV; | |
3775 | mask |= (NIC_RCV_CFG_RV << 16); | |
3776 | } | |
c4e84bde RM |
3777 | ql_write32(qdev, NIC_RCV_CFG, (mask | value)); |
3778 | ||
3779 | /* Set the MPI interrupt to enabled. */ | |
3780 | ql_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16) | INTR_MASK_PI); | |
3781 | ||
3782 | /* Enable the function, set pagesize, enable error checking. */ | |
3783 | value = FSC_FE | FSC_EPC_INBOUND | FSC_EPC_OUTBOUND | | |
572c526f RM |
3784 | FSC_EC | FSC_VM_PAGE_4K; |
3785 | value |= SPLT_SETTING; | |
c4e84bde RM |
3786 | |
3787 | /* Set/clear header splitting. */ | |
3788 | mask = FSC_VM_PAGESIZE_MASK | | |
3789 | FSC_DBL_MASK | FSC_DBRST_MASK | (value << 16); | |
3790 | ql_write32(qdev, FSC, mask | value); | |
3791 | ||
572c526f | 3792 | ql_write32(qdev, SPLT_HDR, SPLT_LEN); |
c4e84bde | 3793 | |
a3b71939 RM |
3794 | /* Set RX packet routing to use port/pci function on which the |
3795 | * packet arrived on in addition to usual frame routing. | |
3796 | * This is helpful on bonding where both interfaces can have | |
3797 | * the same MAC address. | |
3798 | */ | |
3799 | ql_write32(qdev, RST_FO, RST_FO_RR_MASK | RST_FO_RR_RCV_FUNC_CQ); | |
bc083ce9 RM |
3800 | /* Reroute all packets to our Interface. |
3801 | * They may have been routed to MPI firmware | |
3802 | * due to WOL. | |
3803 | */ | |
3804 | value = ql_read32(qdev, MGMT_RCV_CFG); | |
3805 | value &= ~MGMT_RCV_CFG_RM; | |
3806 | mask = 0xffff0000; | |
3807 | ||
3808 | /* Sticky reg needs clearing due to WOL. */ | |
3809 | ql_write32(qdev, MGMT_RCV_CFG, mask); | |
3810 | ql_write32(qdev, MGMT_RCV_CFG, mask | value); | |
3811 | ||
3812 | /* Default WOL is enable on Mezz cards */ | |
3813 | if (qdev->pdev->subsystem_device == 0x0068 || | |
3814 | qdev->pdev->subsystem_device == 0x0180) | |
3815 | qdev->wol = WAKE_MAGIC; | |
a3b71939 | 3816 | |
c4e84bde RM |
3817 | /* Start up the rx queues. */ |
3818 | for (i = 0; i < qdev->rx_ring_count; i++) { | |
3819 | status = ql_start_rx_ring(qdev, &qdev->rx_ring[i]); | |
3820 | if (status) { | |
ae9540f7 JP |
3821 | netif_err(qdev, ifup, qdev->ndev, |
3822 | "Failed to start rx ring[%d].\n", i); | |
c4e84bde RM |
3823 | return status; |
3824 | } | |
3825 | } | |
3826 | ||
3827 | /* If there is more than one inbound completion queue | |
3828 | * then download a RICB to configure RSS. | |
3829 | */ | |
3830 | if (qdev->rss_ring_count > 1) { | |
3831 | status = ql_start_rss(qdev); | |
3832 | if (status) { | |
ae9540f7 | 3833 | netif_err(qdev, ifup, qdev->ndev, "Failed to start RSS.\n"); |
c4e84bde RM |
3834 | return status; |
3835 | } | |
3836 | } | |
3837 | ||
3838 | /* Start up the tx queues. */ | |
3839 | for (i = 0; i < qdev->tx_ring_count; i++) { | |
3840 | status = ql_start_tx_ring(qdev, &qdev->tx_ring[i]); | |
3841 | if (status) { | |
ae9540f7 JP |
3842 | netif_err(qdev, ifup, qdev->ndev, |
3843 | "Failed to start tx ring[%d].\n", i); | |
c4e84bde RM |
3844 | return status; |
3845 | } | |
3846 | } | |
3847 | ||
b0c2aadf RM |
3848 | /* Initialize the port and set the max framesize. */ |
3849 | status = qdev->nic_ops->port_initialize(qdev); | |
80928860 | 3850 | if (status) |
ae9540f7 | 3851 | netif_err(qdev, ifup, qdev->ndev, "Failed to start port.\n"); |
c4e84bde | 3852 | |
bb58b5b6 RM |
3853 | /* Set up the MAC address and frame routing filter. */ |
3854 | status = ql_cam_route_initialize(qdev); | |
c4e84bde | 3855 | if (status) { |
ae9540f7 JP |
3856 | netif_err(qdev, ifup, qdev->ndev, |
3857 | "Failed to init CAM/Routing tables.\n"); | |
c4e84bde RM |
3858 | return status; |
3859 | } | |
3860 | ||
3861 | /* Start NAPI for the RSS queues. */ | |
19257f5a | 3862 | for (i = 0; i < qdev->rss_ring_count; i++) |
c4e84bde | 3863 | napi_enable(&qdev->rx_ring[i].napi); |
c4e84bde RM |
3864 | |
3865 | return status; | |
3866 | } | |
3867 | ||
3868 | /* Issue soft reset to chip. */ | |
3869 | static int ql_adapter_reset(struct ql_adapter *qdev) | |
3870 | { | |
3871 | u32 value; | |
c4e84bde | 3872 | int status = 0; |
a5f59dc9 | 3873 | unsigned long end_jiffies; |
c4e84bde | 3874 | |
a5f59dc9 RM |
3875 | /* Clear all the entries in the routing table. */ |
3876 | status = ql_clear_routing_entries(qdev); | |
3877 | if (status) { | |
ae9540f7 | 3878 | netif_err(qdev, ifup, qdev->ndev, "Failed to clear routing bits.\n"); |
a5f59dc9 RM |
3879 | return status; |
3880 | } | |
3881 | ||
da92b393 JK |
3882 | /* Check if bit is set then skip the mailbox command and |
3883 | * clear the bit, else we are in normal reset process. | |
3884 | */ | |
3885 | if (!test_bit(QL_ASIC_RECOVERY, &qdev->flags)) { | |
3886 | /* Stop management traffic. */ | |
3887 | ql_mb_set_mgmnt_traffic_ctl(qdev, MB_SET_MPI_TFK_STOP); | |
3888 | ||
3889 | /* Wait for the NIC and MGMNT FIFOs to empty. */ | |
3890 | ql_wait_fifo_empty(qdev); | |
3891 | } else | |
3892 | clear_bit(QL_ASIC_RECOVERY, &qdev->flags); | |
84087f4d | 3893 | |
c4e84bde | 3894 | ql_write32(qdev, RST_FO, (RST_FO_FR << 16) | RST_FO_FR); |
a75ee7f1 | 3895 | |
3f6e785f | 3896 | end_jiffies = jiffies + usecs_to_jiffies(30); |
c4e84bde RM |
3897 | do { |
3898 | value = ql_read32(qdev, RST_FO); | |
3899 | if ((value & RST_FO_FR) == 0) | |
3900 | break; | |
a75ee7f1 RM |
3901 | cpu_relax(); |
3902 | } while (time_before(jiffies, end_jiffies)); | |
c4e84bde | 3903 | |
c4e84bde | 3904 | if (value & RST_FO_FR) { |
ae9540f7 JP |
3905 | netif_err(qdev, ifdown, qdev->ndev, |
3906 | "ETIMEDOUT!!! errored out of resetting the chip!\n"); | |
a75ee7f1 | 3907 | status = -ETIMEDOUT; |
c4e84bde RM |
3908 | } |
3909 | ||
84087f4d RM |
3910 | /* Resume management traffic. */ |
3911 | ql_mb_set_mgmnt_traffic_ctl(qdev, MB_SET_MPI_TFK_RESUME); | |
c4e84bde RM |
3912 | return status; |
3913 | } | |
3914 | ||
3915 | static void ql_display_dev_info(struct net_device *ndev) | |
3916 | { | |
b16fed0a | 3917 | struct ql_adapter *qdev = netdev_priv(ndev); |
c4e84bde | 3918 | |
ae9540f7 JP |
3919 | netif_info(qdev, probe, qdev->ndev, |
3920 | "Function #%d, Port %d, NIC Roll %d, NIC Rev = %d, " | |
3921 | "XG Roll = %d, XG Rev = %d.\n", | |
3922 | qdev->func, | |
3923 | qdev->port, | |
3924 | qdev->chip_rev_id & 0x0000000f, | |
3925 | qdev->chip_rev_id >> 4 & 0x0000000f, | |
3926 | qdev->chip_rev_id >> 8 & 0x0000000f, | |
3927 | qdev->chip_rev_id >> 12 & 0x0000000f); | |
3928 | netif_info(qdev, probe, qdev->ndev, | |
3929 | "MAC address %pM\n", ndev->dev_addr); | |
c4e84bde RM |
3930 | } |
3931 | ||
ac409215 | 3932 | static int ql_wol(struct ql_adapter *qdev) |
bc083ce9 RM |
3933 | { |
3934 | int status = 0; | |
3935 | u32 wol = MB_WOL_DISABLE; | |
3936 | ||
3937 | /* The CAM is still intact after a reset, but if we | |
3938 | * are doing WOL, then we may need to program the | |
3939 | * routing regs. We would also need to issue the mailbox | |
3940 | * commands to instruct the MPI what to do per the ethtool | |
3941 | * settings. | |
3942 | */ | |
3943 | ||
3944 | if (qdev->wol & (WAKE_ARP | WAKE_MAGICSECURE | WAKE_PHY | WAKE_UCAST | | |
3945 | WAKE_MCAST | WAKE_BCAST)) { | |
ae9540f7 | 3946 | netif_err(qdev, ifdown, qdev->ndev, |
fd9071ec | 3947 | "Unsupported WOL parameter. qdev->wol = 0x%x.\n", |
ae9540f7 | 3948 | qdev->wol); |
bc083ce9 RM |
3949 | return -EINVAL; |
3950 | } | |
3951 | ||
3952 | if (qdev->wol & WAKE_MAGIC) { | |
3953 | status = ql_mb_wol_set_magic(qdev, 1); | |
3954 | if (status) { | |
ae9540f7 JP |
3955 | netif_err(qdev, ifdown, qdev->ndev, |
3956 | "Failed to set magic packet on %s.\n", | |
3957 | qdev->ndev->name); | |
bc083ce9 RM |
3958 | return status; |
3959 | } else | |
ae9540f7 JP |
3960 | netif_info(qdev, drv, qdev->ndev, |
3961 | "Enabled magic packet successfully on %s.\n", | |
3962 | qdev->ndev->name); | |
bc083ce9 RM |
3963 | |
3964 | wol |= MB_WOL_MAGIC_PKT; | |
3965 | } | |
3966 | ||
3967 | if (qdev->wol) { | |
bc083ce9 RM |
3968 | wol |= MB_WOL_MODE_ON; |
3969 | status = ql_mb_wol_mode(qdev, wol); | |
ae9540f7 JP |
3970 | netif_err(qdev, drv, qdev->ndev, |
3971 | "WOL %s (wol code 0x%x) on %s\n", | |
318ae2ed | 3972 | (status == 0) ? "Successfully set" : "Failed", |
ae9540f7 | 3973 | wol, qdev->ndev->name); |
bc083ce9 RM |
3974 | } |
3975 | ||
3976 | return status; | |
3977 | } | |
3978 | ||
c5dadddb | 3979 | static void ql_cancel_all_work_sync(struct ql_adapter *qdev) |
c4e84bde | 3980 | { |
c4e84bde | 3981 | |
6497b607 RM |
3982 | /* Don't kill the reset worker thread if we |
3983 | * are in the process of recovery. | |
3984 | */ | |
3985 | if (test_bit(QL_ADAPTER_UP, &qdev->flags)) | |
3986 | cancel_delayed_work_sync(&qdev->asic_reset_work); | |
c4e84bde RM |
3987 | cancel_delayed_work_sync(&qdev->mpi_reset_work); |
3988 | cancel_delayed_work_sync(&qdev->mpi_work); | |
2ee1e272 | 3989 | cancel_delayed_work_sync(&qdev->mpi_idc_work); |
8aae2600 | 3990 | cancel_delayed_work_sync(&qdev->mpi_core_to_log); |
bcc2cb3b | 3991 | cancel_delayed_work_sync(&qdev->mpi_port_cfg_work); |
c5dadddb BL |
3992 | } |
3993 | ||
3994 | static int ql_adapter_down(struct ql_adapter *qdev) | |
3995 | { | |
3996 | int i, status = 0; | |
3997 | ||
3998 | ql_link_off(qdev); | |
3999 | ||
4000 | ql_cancel_all_work_sync(qdev); | |
c4e84bde | 4001 | |
39aa8165 RM |
4002 | for (i = 0; i < qdev->rss_ring_count; i++) |
4003 | napi_disable(&qdev->rx_ring[i].napi); | |
c4e84bde RM |
4004 | |
4005 | clear_bit(QL_ADAPTER_UP, &qdev->flags); | |
4006 | ||
4007 | ql_disable_interrupts(qdev); | |
4008 | ||
4009 | ql_tx_ring_clean(qdev); | |
4010 | ||
6b318cb3 RM |
4011 | /* Call netif_napi_del() from common point. |
4012 | */ | |
b2014ff8 | 4013 | for (i = 0; i < qdev->rss_ring_count; i++) |
6b318cb3 RM |
4014 | netif_napi_del(&qdev->rx_ring[i].napi); |
4015 | ||
c4e84bde RM |
4016 | status = ql_adapter_reset(qdev); |
4017 | if (status) | |
ae9540f7 JP |
4018 | netif_err(qdev, ifdown, qdev->ndev, "reset(func #%d) FAILED!\n", |
4019 | qdev->func); | |
fe5f0980 BL |
4020 | ql_free_rx_buffers(qdev); |
4021 | ||
c4e84bde RM |
4022 | return status; |
4023 | } | |
4024 | ||
4025 | static int ql_adapter_up(struct ql_adapter *qdev) | |
4026 | { | |
4027 | int err = 0; | |
4028 | ||
c4e84bde RM |
4029 | err = ql_adapter_initialize(qdev); |
4030 | if (err) { | |
ae9540f7 | 4031 | netif_info(qdev, ifup, qdev->ndev, "Unable to initialize adapter.\n"); |
c4e84bde RM |
4032 | goto err_init; |
4033 | } | |
c4e84bde | 4034 | set_bit(QL_ADAPTER_UP, &qdev->flags); |
4545a3f2 | 4035 | ql_alloc_rx_buffers(qdev); |
8b007de1 RM |
4036 | /* If the port is initialized and the |
4037 | * link is up the turn on the carrier. | |
4038 | */ | |
4039 | if ((ql_read32(qdev, STS) & qdev->port_init) && | |
4040 | (ql_read32(qdev, STS) & qdev->port_link_up)) | |
6a473308 | 4041 | ql_link_on(qdev); |
f2c05004 RM |
4042 | /* Restore rx mode. */ |
4043 | clear_bit(QL_ALLMULTI, &qdev->flags); | |
4044 | clear_bit(QL_PROMISCUOUS, &qdev->flags); | |
4045 | qlge_set_multicast_list(qdev->ndev); | |
4046 | ||
c1b60092 RM |
4047 | /* Restore vlan setting. */ |
4048 | qlge_restore_vlan(qdev); | |
4049 | ||
c4e84bde RM |
4050 | ql_enable_interrupts(qdev); |
4051 | ql_enable_all_completion_interrupts(qdev); | |
1e213303 | 4052 | netif_tx_start_all_queues(qdev->ndev); |
c4e84bde RM |
4053 | |
4054 | return 0; | |
4055 | err_init: | |
4056 | ql_adapter_reset(qdev); | |
4057 | return err; | |
4058 | } | |
4059 | ||
c4e84bde RM |
4060 | static void ql_release_adapter_resources(struct ql_adapter *qdev) |
4061 | { | |
4062 | ql_free_mem_resources(qdev); | |
4063 | ql_free_irq(qdev); | |
4064 | } | |
4065 | ||
4066 | static int ql_get_adapter_resources(struct ql_adapter *qdev) | |
4067 | { | |
4068 | int status = 0; | |
4069 | ||
4070 | if (ql_alloc_mem_resources(qdev)) { | |
ae9540f7 | 4071 | netif_err(qdev, ifup, qdev->ndev, "Unable to allocate memory.\n"); |
c4e84bde RM |
4072 | return -ENOMEM; |
4073 | } | |
4074 | status = ql_request_irq(qdev); | |
c4e84bde RM |
4075 | return status; |
4076 | } | |
4077 | ||
4078 | static int qlge_close(struct net_device *ndev) | |
4079 | { | |
4080 | struct ql_adapter *qdev = netdev_priv(ndev); | |
4081 | ||
4bbd1a19 RM |
4082 | /* If we hit pci_channel_io_perm_failure |
4083 | * failure condition, then we already | |
4084 | * brought the adapter down. | |
4085 | */ | |
4086 | if (test_bit(QL_EEH_FATAL, &qdev->flags)) { | |
ae9540f7 | 4087 | netif_err(qdev, drv, qdev->ndev, "EEH fatal did unload.\n"); |
4bbd1a19 RM |
4088 | clear_bit(QL_EEH_FATAL, &qdev->flags); |
4089 | return 0; | |
4090 | } | |
4091 | ||
c4e84bde RM |
4092 | /* |
4093 | * Wait for device to recover from a reset. | |
4094 | * (Rarely happens, but possible.) | |
4095 | */ | |
4096 | while (!test_bit(QL_ADAPTER_UP, &qdev->flags)) | |
4097 | msleep(1); | |
4098 | ql_adapter_down(qdev); | |
4099 | ql_release_adapter_resources(qdev); | |
c4e84bde RM |
4100 | return 0; |
4101 | } | |
4102 | ||
4103 | static int ql_configure_rings(struct ql_adapter *qdev) | |
4104 | { | |
4105 | int i; | |
4106 | struct rx_ring *rx_ring; | |
4107 | struct tx_ring *tx_ring; | |
a4ab6137 | 4108 | int cpu_cnt = min(MAX_CPUS, (int)num_online_cpus()); |
7c734359 RM |
4109 | unsigned int lbq_buf_len = (qdev->ndev->mtu > 1500) ? |
4110 | LARGE_BUFFER_MAX_SIZE : LARGE_BUFFER_MIN_SIZE; | |
4111 | ||
4112 | qdev->lbq_buf_order = get_order(lbq_buf_len); | |
a4ab6137 RM |
4113 | |
4114 | /* In a perfect world we have one RSS ring for each CPU | |
4115 | * and each has it's own vector. To do that we ask for | |
4116 | * cpu_cnt vectors. ql_enable_msix() will adjust the | |
4117 | * vector count to what we actually get. We then | |
4118 | * allocate an RSS ring for each. | |
4119 | * Essentially, we are doing min(cpu_count, msix_vector_count). | |
c4e84bde | 4120 | */ |
a4ab6137 RM |
4121 | qdev->intr_count = cpu_cnt; |
4122 | ql_enable_msix(qdev); | |
4123 | /* Adjust the RSS ring count to the actual vector count. */ | |
4124 | qdev->rss_ring_count = qdev->intr_count; | |
c4e84bde | 4125 | qdev->tx_ring_count = cpu_cnt; |
b2014ff8 | 4126 | qdev->rx_ring_count = qdev->tx_ring_count + qdev->rss_ring_count; |
c4e84bde | 4127 | |
c4e84bde RM |
4128 | for (i = 0; i < qdev->tx_ring_count; i++) { |
4129 | tx_ring = &qdev->tx_ring[i]; | |
e332471c | 4130 | memset((void *)tx_ring, 0, sizeof(*tx_ring)); |
c4e84bde RM |
4131 | tx_ring->qdev = qdev; |
4132 | tx_ring->wq_id = i; | |
4133 | tx_ring->wq_len = qdev->tx_ring_size; | |
4134 | tx_ring->wq_size = | |
4135 | tx_ring->wq_len * sizeof(struct ob_mac_iocb_req); | |
4136 | ||
4137 | /* | |
4138 | * The completion queue ID for the tx rings start | |
39aa8165 | 4139 | * immediately after the rss rings. |
c4e84bde | 4140 | */ |
39aa8165 | 4141 | tx_ring->cq_id = qdev->rss_ring_count + i; |
c4e84bde RM |
4142 | } |
4143 | ||
4144 | for (i = 0; i < qdev->rx_ring_count; i++) { | |
4145 | rx_ring = &qdev->rx_ring[i]; | |
e332471c | 4146 | memset((void *)rx_ring, 0, sizeof(*rx_ring)); |
c4e84bde RM |
4147 | rx_ring->qdev = qdev; |
4148 | rx_ring->cq_id = i; | |
4149 | rx_ring->cpu = i % cpu_cnt; /* CPU to run handler on. */ | |
b2014ff8 | 4150 | if (i < qdev->rss_ring_count) { |
39aa8165 RM |
4151 | /* |
4152 | * Inbound (RSS) queues. | |
4153 | */ | |
c4e84bde RM |
4154 | rx_ring->cq_len = qdev->rx_ring_size; |
4155 | rx_ring->cq_size = | |
4156 | rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb); | |
4157 | rx_ring->lbq_len = NUM_LARGE_BUFFERS; | |
4158 | rx_ring->lbq_size = | |
2c9a0d41 | 4159 | rx_ring->lbq_len * sizeof(__le64); |
7c734359 | 4160 | rx_ring->lbq_buf_size = (u16)lbq_buf_len; |
c4e84bde RM |
4161 | rx_ring->sbq_len = NUM_SMALL_BUFFERS; |
4162 | rx_ring->sbq_size = | |
2c9a0d41 | 4163 | rx_ring->sbq_len * sizeof(__le64); |
52e55f3c | 4164 | rx_ring->sbq_buf_size = SMALL_BUF_MAP_SIZE; |
b2014ff8 RM |
4165 | rx_ring->type = RX_Q; |
4166 | } else { | |
c4e84bde RM |
4167 | /* |
4168 | * Outbound queue handles outbound completions only. | |
4169 | */ | |
4170 | /* outbound cq is same size as tx_ring it services. */ | |
4171 | rx_ring->cq_len = qdev->tx_ring_size; | |
4172 | rx_ring->cq_size = | |
4173 | rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb); | |
4174 | rx_ring->lbq_len = 0; | |
4175 | rx_ring->lbq_size = 0; | |
4176 | rx_ring->lbq_buf_size = 0; | |
4177 | rx_ring->sbq_len = 0; | |
4178 | rx_ring->sbq_size = 0; | |
4179 | rx_ring->sbq_buf_size = 0; | |
4180 | rx_ring->type = TX_Q; | |
c4e84bde RM |
4181 | } |
4182 | } | |
4183 | return 0; | |
4184 | } | |
4185 | ||
4186 | static int qlge_open(struct net_device *ndev) | |
4187 | { | |
4188 | int err = 0; | |
4189 | struct ql_adapter *qdev = netdev_priv(ndev); | |
4190 | ||
74e12435 RM |
4191 | err = ql_adapter_reset(qdev); |
4192 | if (err) | |
4193 | return err; | |
4194 | ||
c4e84bde RM |
4195 | err = ql_configure_rings(qdev); |
4196 | if (err) | |
4197 | return err; | |
4198 | ||
4199 | err = ql_get_adapter_resources(qdev); | |
4200 | if (err) | |
4201 | goto error_up; | |
4202 | ||
4203 | err = ql_adapter_up(qdev); | |
4204 | if (err) | |
4205 | goto error_up; | |
4206 | ||
4207 | return err; | |
4208 | ||
4209 | error_up: | |
4210 | ql_release_adapter_resources(qdev); | |
c4e84bde RM |
4211 | return err; |
4212 | } | |
4213 | ||
7c734359 RM |
4214 | static int ql_change_rx_buffers(struct ql_adapter *qdev) |
4215 | { | |
4216 | struct rx_ring *rx_ring; | |
4217 | int i, status; | |
4218 | u32 lbq_buf_len; | |
4219 | ||
25985edc | 4220 | /* Wait for an outstanding reset to complete. */ |
7c734359 | 4221 | if (!test_bit(QL_ADAPTER_UP, &qdev->flags)) { |
351434c6 DC |
4222 | int i = 4; |
4223 | ||
4224 | while (--i && !test_bit(QL_ADAPTER_UP, &qdev->flags)) { | |
ae9540f7 JP |
4225 | netif_err(qdev, ifup, qdev->ndev, |
4226 | "Waiting for adapter UP...\n"); | |
7c734359 RM |
4227 | ssleep(1); |
4228 | } | |
4229 | ||
4230 | if (!i) { | |
ae9540f7 JP |
4231 | netif_err(qdev, ifup, qdev->ndev, |
4232 | "Timed out waiting for adapter UP\n"); | |
7c734359 RM |
4233 | return -ETIMEDOUT; |
4234 | } | |
4235 | } | |
4236 | ||
4237 | status = ql_adapter_down(qdev); | |
4238 | if (status) | |
4239 | goto error; | |
4240 | ||
4241 | /* Get the new rx buffer size. */ | |
4242 | lbq_buf_len = (qdev->ndev->mtu > 1500) ? | |
4243 | LARGE_BUFFER_MAX_SIZE : LARGE_BUFFER_MIN_SIZE; | |
4244 | qdev->lbq_buf_order = get_order(lbq_buf_len); | |
4245 | ||
4246 | for (i = 0; i < qdev->rss_ring_count; i++) { | |
4247 | rx_ring = &qdev->rx_ring[i]; | |
4248 | /* Set the new size. */ | |
4249 | rx_ring->lbq_buf_size = lbq_buf_len; | |
4250 | } | |
4251 | ||
4252 | status = ql_adapter_up(qdev); | |
4253 | if (status) | |
4254 | goto error; | |
4255 | ||
4256 | return status; | |
4257 | error: | |
ae9540f7 JP |
4258 | netif_alert(qdev, ifup, qdev->ndev, |
4259 | "Driver up/down cycle failed, closing device.\n"); | |
7c734359 RM |
4260 | set_bit(QL_ADAPTER_UP, &qdev->flags); |
4261 | dev_close(qdev->ndev); | |
4262 | return status; | |
4263 | } | |
4264 | ||
c4e84bde RM |
4265 | static int qlge_change_mtu(struct net_device *ndev, int new_mtu) |
4266 | { | |
4267 | struct ql_adapter *qdev = netdev_priv(ndev); | |
7c734359 | 4268 | int status; |
c4e84bde RM |
4269 | |
4270 | if (ndev->mtu == 1500 && new_mtu == 9000) { | |
ae9540f7 | 4271 | netif_err(qdev, ifup, qdev->ndev, "Changing to jumbo MTU.\n"); |
c4e84bde | 4272 | } else if (ndev->mtu == 9000 && new_mtu == 1500) { |
ae9540f7 | 4273 | netif_err(qdev, ifup, qdev->ndev, "Changing to normal MTU.\n"); |
c4e84bde RM |
4274 | } else |
4275 | return -EINVAL; | |
7c734359 RM |
4276 | |
4277 | queue_delayed_work(qdev->workqueue, | |
4278 | &qdev->mpi_port_cfg_work, 3*HZ); | |
4279 | ||
746079da BL |
4280 | ndev->mtu = new_mtu; |
4281 | ||
7c734359 | 4282 | if (!netif_running(qdev->ndev)) { |
7c734359 RM |
4283 | return 0; |
4284 | } | |
4285 | ||
7c734359 RM |
4286 | status = ql_change_rx_buffers(qdev); |
4287 | if (status) { | |
ae9540f7 JP |
4288 | netif_err(qdev, ifup, qdev->ndev, |
4289 | "Changing MTU failed.\n"); | |
7c734359 RM |
4290 | } |
4291 | ||
4292 | return status; | |
c4e84bde RM |
4293 | } |
4294 | ||
4295 | static struct net_device_stats *qlge_get_stats(struct net_device | |
4296 | *ndev) | |
4297 | { | |
885ee398 RM |
4298 | struct ql_adapter *qdev = netdev_priv(ndev); |
4299 | struct rx_ring *rx_ring = &qdev->rx_ring[0]; | |
4300 | struct tx_ring *tx_ring = &qdev->tx_ring[0]; | |
4301 | unsigned long pkts, mcast, dropped, errors, bytes; | |
4302 | int i; | |
4303 | ||
4304 | /* Get RX stats. */ | |
4305 | pkts = mcast = dropped = errors = bytes = 0; | |
4306 | for (i = 0; i < qdev->rss_ring_count; i++, rx_ring++) { | |
4307 | pkts += rx_ring->rx_packets; | |
4308 | bytes += rx_ring->rx_bytes; | |
4309 | dropped += rx_ring->rx_dropped; | |
4310 | errors += rx_ring->rx_errors; | |
4311 | mcast += rx_ring->rx_multicast; | |
4312 | } | |
4313 | ndev->stats.rx_packets = pkts; | |
4314 | ndev->stats.rx_bytes = bytes; | |
4315 | ndev->stats.rx_dropped = dropped; | |
4316 | ndev->stats.rx_errors = errors; | |
4317 | ndev->stats.multicast = mcast; | |
4318 | ||
4319 | /* Get TX stats. */ | |
4320 | pkts = errors = bytes = 0; | |
4321 | for (i = 0; i < qdev->tx_ring_count; i++, tx_ring++) { | |
4322 | pkts += tx_ring->tx_packets; | |
4323 | bytes += tx_ring->tx_bytes; | |
4324 | errors += tx_ring->tx_errors; | |
4325 | } | |
4326 | ndev->stats.tx_packets = pkts; | |
4327 | ndev->stats.tx_bytes = bytes; | |
4328 | ndev->stats.tx_errors = errors; | |
bcc90f55 | 4329 | return &ndev->stats; |
c4e84bde RM |
4330 | } |
4331 | ||
ac409215 | 4332 | static void qlge_set_multicast_list(struct net_device *ndev) |
c4e84bde | 4333 | { |
b16fed0a | 4334 | struct ql_adapter *qdev = netdev_priv(ndev); |
22bedad3 | 4335 | struct netdev_hw_addr *ha; |
cc288f54 | 4336 | int i, status; |
c4e84bde | 4337 | |
cc288f54 RM |
4338 | status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK); |
4339 | if (status) | |
4340 | return; | |
c4e84bde RM |
4341 | /* |
4342 | * Set or clear promiscuous mode if a | |
4343 | * transition is taking place. | |
4344 | */ | |
4345 | if (ndev->flags & IFF_PROMISC) { | |
4346 | if (!test_bit(QL_PROMISCUOUS, &qdev->flags)) { | |
4347 | if (ql_set_routing_reg | |
4348 | (qdev, RT_IDX_PROMISCUOUS_SLOT, RT_IDX_VALID, 1)) { | |
ae9540f7 | 4349 | netif_err(qdev, hw, qdev->ndev, |
25985edc | 4350 | "Failed to set promiscuous mode.\n"); |
c4e84bde RM |
4351 | } else { |
4352 | set_bit(QL_PROMISCUOUS, &qdev->flags); | |
4353 | } | |
4354 | } | |
4355 | } else { | |
4356 | if (test_bit(QL_PROMISCUOUS, &qdev->flags)) { | |
4357 | if (ql_set_routing_reg | |
4358 | (qdev, RT_IDX_PROMISCUOUS_SLOT, RT_IDX_VALID, 0)) { | |
ae9540f7 | 4359 | netif_err(qdev, hw, qdev->ndev, |
25985edc | 4360 | "Failed to clear promiscuous mode.\n"); |
c4e84bde RM |
4361 | } else { |
4362 | clear_bit(QL_PROMISCUOUS, &qdev->flags); | |
4363 | } | |
4364 | } | |
4365 | } | |
4366 | ||
4367 | /* | |
4368 | * Set or clear all multicast mode if a | |
4369 | * transition is taking place. | |
4370 | */ | |
4371 | if ((ndev->flags & IFF_ALLMULTI) || | |
4cd24eaf | 4372 | (netdev_mc_count(ndev) > MAX_MULTICAST_ENTRIES)) { |
c4e84bde RM |
4373 | if (!test_bit(QL_ALLMULTI, &qdev->flags)) { |
4374 | if (ql_set_routing_reg | |
4375 | (qdev, RT_IDX_ALLMULTI_SLOT, RT_IDX_MCAST, 1)) { | |
ae9540f7 JP |
4376 | netif_err(qdev, hw, qdev->ndev, |
4377 | "Failed to set all-multi mode.\n"); | |
c4e84bde RM |
4378 | } else { |
4379 | set_bit(QL_ALLMULTI, &qdev->flags); | |
4380 | } | |
4381 | } | |
4382 | } else { | |
4383 | if (test_bit(QL_ALLMULTI, &qdev->flags)) { | |
4384 | if (ql_set_routing_reg | |
4385 | (qdev, RT_IDX_ALLMULTI_SLOT, RT_IDX_MCAST, 0)) { | |
ae9540f7 JP |
4386 | netif_err(qdev, hw, qdev->ndev, |
4387 | "Failed to clear all-multi mode.\n"); | |
c4e84bde RM |
4388 | } else { |
4389 | clear_bit(QL_ALLMULTI, &qdev->flags); | |
4390 | } | |
4391 | } | |
4392 | } | |
4393 | ||
4cd24eaf | 4394 | if (!netdev_mc_empty(ndev)) { |
cc288f54 RM |
4395 | status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK); |
4396 | if (status) | |
4397 | goto exit; | |
f9dcbcc9 | 4398 | i = 0; |
22bedad3 JP |
4399 | netdev_for_each_mc_addr(ha, ndev) { |
4400 | if (ql_set_mac_addr_reg(qdev, (u8 *) ha->addr, | |
c4e84bde | 4401 | MAC_ADDR_TYPE_MULTI_MAC, i)) { |
ae9540f7 JP |
4402 | netif_err(qdev, hw, qdev->ndev, |
4403 | "Failed to loadmulticast address.\n"); | |
cc288f54 | 4404 | ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK); |
c4e84bde RM |
4405 | goto exit; |
4406 | } | |
f9dcbcc9 JP |
4407 | i++; |
4408 | } | |
cc288f54 | 4409 | ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK); |
c4e84bde RM |
4410 | if (ql_set_routing_reg |
4411 | (qdev, RT_IDX_MCAST_MATCH_SLOT, RT_IDX_MCAST_MATCH, 1)) { | |
ae9540f7 JP |
4412 | netif_err(qdev, hw, qdev->ndev, |
4413 | "Failed to set multicast match mode.\n"); | |
c4e84bde RM |
4414 | } else { |
4415 | set_bit(QL_ALLMULTI, &qdev->flags); | |
4416 | } | |
4417 | } | |
4418 | exit: | |
8587ea35 | 4419 | ql_sem_unlock(qdev, SEM_RT_IDX_MASK); |
c4e84bde RM |
4420 | } |
4421 | ||
4422 | static int qlge_set_mac_address(struct net_device *ndev, void *p) | |
4423 | { | |
b16fed0a | 4424 | struct ql_adapter *qdev = netdev_priv(ndev); |
c4e84bde | 4425 | struct sockaddr *addr = p; |
cc288f54 | 4426 | int status; |
c4e84bde | 4427 | |
c4e84bde RM |
4428 | if (!is_valid_ether_addr(addr->sa_data)) |
4429 | return -EADDRNOTAVAIL; | |
4430 | memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len); | |
801e9096 RM |
4431 | /* Update local copy of current mac address. */ |
4432 | memcpy(qdev->current_mac_addr, ndev->dev_addr, ndev->addr_len); | |
c4e84bde | 4433 | |
cc288f54 RM |
4434 | status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK); |
4435 | if (status) | |
4436 | return status; | |
cc288f54 RM |
4437 | status = ql_set_mac_addr_reg(qdev, (u8 *) ndev->dev_addr, |
4438 | MAC_ADDR_TYPE_CAM_MAC, qdev->func * MAX_CQ); | |
cc288f54 | 4439 | if (status) |
ae9540f7 | 4440 | netif_err(qdev, hw, qdev->ndev, "Failed to load MAC address.\n"); |
cc288f54 RM |
4441 | ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK); |
4442 | return status; | |
c4e84bde RM |
4443 | } |
4444 | ||
4445 | static void qlge_tx_timeout(struct net_device *ndev) | |
4446 | { | |
b16fed0a | 4447 | struct ql_adapter *qdev = netdev_priv(ndev); |
6497b607 | 4448 | ql_queue_asic_error(qdev); |
c4e84bde RM |
4449 | } |
4450 | ||
4451 | static void ql_asic_reset_work(struct work_struct *work) | |
4452 | { | |
4453 | struct ql_adapter *qdev = | |
4454 | container_of(work, struct ql_adapter, asic_reset_work.work); | |
db98812f | 4455 | int status; |
f2c0d8df | 4456 | rtnl_lock(); |
db98812f RM |
4457 | status = ql_adapter_down(qdev); |
4458 | if (status) | |
4459 | goto error; | |
4460 | ||
4461 | status = ql_adapter_up(qdev); | |
4462 | if (status) | |
4463 | goto error; | |
2cd6dbaa RM |
4464 | |
4465 | /* Restore rx mode. */ | |
4466 | clear_bit(QL_ALLMULTI, &qdev->flags); | |
4467 | clear_bit(QL_PROMISCUOUS, &qdev->flags); | |
4468 | qlge_set_multicast_list(qdev->ndev); | |
4469 | ||
f2c0d8df | 4470 | rtnl_unlock(); |
db98812f RM |
4471 | return; |
4472 | error: | |
ae9540f7 JP |
4473 | netif_alert(qdev, ifup, qdev->ndev, |
4474 | "Driver up/down cycle failed, closing device\n"); | |
f2c0d8df | 4475 | |
db98812f RM |
4476 | set_bit(QL_ADAPTER_UP, &qdev->flags); |
4477 | dev_close(qdev->ndev); | |
4478 | rtnl_unlock(); | |
c4e84bde RM |
4479 | } |
4480 | ||
ef9c7ab4 | 4481 | static const struct nic_operations qla8012_nic_ops = { |
b0c2aadf RM |
4482 | .get_flash = ql_get_8012_flash_params, |
4483 | .port_initialize = ql_8012_port_initialize, | |
4484 | }; | |
4485 | ||
ef9c7ab4 | 4486 | static const struct nic_operations qla8000_nic_ops = { |
cdca8d02 RM |
4487 | .get_flash = ql_get_8000_flash_params, |
4488 | .port_initialize = ql_8000_port_initialize, | |
4489 | }; | |
4490 | ||
e4552f51 RM |
4491 | /* Find the pcie function number for the other NIC |
4492 | * on this chip. Since both NIC functions share a | |
4493 | * common firmware we have the lowest enabled function | |
4494 | * do any common work. Examples would be resetting | |
4495 | * after a fatal firmware error, or doing a firmware | |
4496 | * coredump. | |
4497 | */ | |
4498 | static int ql_get_alt_pcie_func(struct ql_adapter *qdev) | |
4499 | { | |
4500 | int status = 0; | |
4501 | u32 temp; | |
4502 | u32 nic_func1, nic_func2; | |
4503 | ||
4504 | status = ql_read_mpi_reg(qdev, MPI_TEST_FUNC_PORT_CFG, | |
4505 | &temp); | |
4506 | if (status) | |
4507 | return status; | |
4508 | ||
4509 | nic_func1 = ((temp >> MPI_TEST_NIC1_FUNC_SHIFT) & | |
4510 | MPI_TEST_NIC_FUNC_MASK); | |
4511 | nic_func2 = ((temp >> MPI_TEST_NIC2_FUNC_SHIFT) & | |
4512 | MPI_TEST_NIC_FUNC_MASK); | |
4513 | ||
4514 | if (qdev->func == nic_func1) | |
4515 | qdev->alt_func = nic_func2; | |
4516 | else if (qdev->func == nic_func2) | |
4517 | qdev->alt_func = nic_func1; | |
4518 | else | |
4519 | status = -EIO; | |
4520 | ||
4521 | return status; | |
4522 | } | |
b0c2aadf | 4523 | |
e4552f51 | 4524 | static int ql_get_board_info(struct ql_adapter *qdev) |
c4e84bde | 4525 | { |
e4552f51 | 4526 | int status; |
c4e84bde RM |
4527 | qdev->func = |
4528 | (ql_read32(qdev, STS) & STS_FUNC_ID_MASK) >> STS_FUNC_ID_SHIFT; | |
e4552f51 RM |
4529 | if (qdev->func > 3) |
4530 | return -EIO; | |
4531 | ||
4532 | status = ql_get_alt_pcie_func(qdev); | |
4533 | if (status) | |
4534 | return status; | |
4535 | ||
4536 | qdev->port = (qdev->func < qdev->alt_func) ? 0 : 1; | |
4537 | if (qdev->port) { | |
c4e84bde RM |
4538 | qdev->xg_sem_mask = SEM_XGMAC1_MASK; |
4539 | qdev->port_link_up = STS_PL1; | |
4540 | qdev->port_init = STS_PI1; | |
4541 | qdev->mailbox_in = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC2_MBI; | |
4542 | qdev->mailbox_out = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC2_MBO; | |
4543 | } else { | |
4544 | qdev->xg_sem_mask = SEM_XGMAC0_MASK; | |
4545 | qdev->port_link_up = STS_PL0; | |
4546 | qdev->port_init = STS_PI0; | |
4547 | qdev->mailbox_in = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBI; | |
4548 | qdev->mailbox_out = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBO; | |
4549 | } | |
4550 | qdev->chip_rev_id = ql_read32(qdev, REV_ID); | |
b0c2aadf RM |
4551 | qdev->device_id = qdev->pdev->device; |
4552 | if (qdev->device_id == QLGE_DEVICE_ID_8012) | |
4553 | qdev->nic_ops = &qla8012_nic_ops; | |
cdca8d02 RM |
4554 | else if (qdev->device_id == QLGE_DEVICE_ID_8000) |
4555 | qdev->nic_ops = &qla8000_nic_ops; | |
e4552f51 | 4556 | return status; |
c4e84bde RM |
4557 | } |
4558 | ||
4559 | static void ql_release_all(struct pci_dev *pdev) | |
4560 | { | |
4561 | struct net_device *ndev = pci_get_drvdata(pdev); | |
4562 | struct ql_adapter *qdev = netdev_priv(ndev); | |
4563 | ||
4564 | if (qdev->workqueue) { | |
4565 | destroy_workqueue(qdev->workqueue); | |
4566 | qdev->workqueue = NULL; | |
4567 | } | |
39aa8165 | 4568 | |
c4e84bde | 4569 | if (qdev->reg_base) |
8668ae92 | 4570 | iounmap(qdev->reg_base); |
c4e84bde RM |
4571 | if (qdev->doorbell_area) |
4572 | iounmap(qdev->doorbell_area); | |
8aae2600 | 4573 | vfree(qdev->mpi_coredump); |
c4e84bde | 4574 | pci_release_regions(pdev); |
c4e84bde RM |
4575 | } |
4576 | ||
1dd06ae8 GKH |
4577 | static int ql_init_device(struct pci_dev *pdev, struct net_device *ndev, |
4578 | int cards_found) | |
c4e84bde RM |
4579 | { |
4580 | struct ql_adapter *qdev = netdev_priv(ndev); | |
1d1023d0 | 4581 | int err = 0; |
c4e84bde | 4582 | |
e332471c | 4583 | memset((void *)qdev, 0, sizeof(*qdev)); |
c4e84bde RM |
4584 | err = pci_enable_device(pdev); |
4585 | if (err) { | |
4586 | dev_err(&pdev->dev, "PCI device enable failed.\n"); | |
4587 | return err; | |
4588 | } | |
4589 | ||
ebd6e774 RM |
4590 | qdev->ndev = ndev; |
4591 | qdev->pdev = pdev; | |
4592 | pci_set_drvdata(pdev, ndev); | |
c4e84bde | 4593 | |
bc9167f3 RM |
4594 | /* Set PCIe read request size */ |
4595 | err = pcie_set_readrq(pdev, 4096); | |
4596 | if (err) { | |
4597 | dev_err(&pdev->dev, "Set readrq failed.\n"); | |
4f9a91c8 | 4598 | goto err_out1; |
bc9167f3 RM |
4599 | } |
4600 | ||
c4e84bde RM |
4601 | err = pci_request_regions(pdev, DRV_NAME); |
4602 | if (err) { | |
4603 | dev_err(&pdev->dev, "PCI region request failed.\n"); | |
ebd6e774 | 4604 | return err; |
c4e84bde RM |
4605 | } |
4606 | ||
4607 | pci_set_master(pdev); | |
6a35528a | 4608 | if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) { |
c4e84bde | 4609 | set_bit(QL_DMA64, &qdev->flags); |
6a35528a | 4610 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); |
c4e84bde | 4611 | } else { |
284901a9 | 4612 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
c4e84bde | 4613 | if (!err) |
284901a9 | 4614 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
c4e84bde RM |
4615 | } |
4616 | ||
4617 | if (err) { | |
4618 | dev_err(&pdev->dev, "No usable DMA configuration.\n"); | |
4f9a91c8 | 4619 | goto err_out2; |
c4e84bde RM |
4620 | } |
4621 | ||
73475339 RM |
4622 | /* Set PCIe reset type for EEH to fundamental. */ |
4623 | pdev->needs_freset = 1; | |
6d190c6e | 4624 | pci_save_state(pdev); |
c4e84bde RM |
4625 | qdev->reg_base = |
4626 | ioremap_nocache(pci_resource_start(pdev, 1), | |
4627 | pci_resource_len(pdev, 1)); | |
4628 | if (!qdev->reg_base) { | |
4629 | dev_err(&pdev->dev, "Register mapping failed.\n"); | |
4630 | err = -ENOMEM; | |
4f9a91c8 | 4631 | goto err_out2; |
c4e84bde RM |
4632 | } |
4633 | ||
4634 | qdev->doorbell_area_size = pci_resource_len(pdev, 3); | |
4635 | qdev->doorbell_area = | |
4636 | ioremap_nocache(pci_resource_start(pdev, 3), | |
4637 | pci_resource_len(pdev, 3)); | |
4638 | if (!qdev->doorbell_area) { | |
4639 | dev_err(&pdev->dev, "Doorbell register mapping failed.\n"); | |
4640 | err = -ENOMEM; | |
4f9a91c8 | 4641 | goto err_out2; |
c4e84bde RM |
4642 | } |
4643 | ||
e4552f51 RM |
4644 | err = ql_get_board_info(qdev); |
4645 | if (err) { | |
4646 | dev_err(&pdev->dev, "Register access failed.\n"); | |
4647 | err = -EIO; | |
4f9a91c8 | 4648 | goto err_out2; |
e4552f51 | 4649 | } |
c4e84bde RM |
4650 | qdev->msg_enable = netif_msg_init(debug, default_msg); |
4651 | spin_lock_init(&qdev->hw_lock); | |
4652 | spin_lock_init(&qdev->stats_lock); | |
4653 | ||
8aae2600 RM |
4654 | if (qlge_mpi_coredump) { |
4655 | qdev->mpi_coredump = | |
4656 | vmalloc(sizeof(struct ql_mpi_coredump)); | |
4657 | if (qdev->mpi_coredump == NULL) { | |
8aae2600 | 4658 | err = -ENOMEM; |
ce96bc86 | 4659 | goto err_out2; |
8aae2600 | 4660 | } |
d5c1da56 RM |
4661 | if (qlge_force_coredump) |
4662 | set_bit(QL_FRC_COREDUMP, &qdev->flags); | |
8aae2600 | 4663 | } |
c4e84bde | 4664 | /* make sure the EEPROM is good */ |
b0c2aadf | 4665 | err = qdev->nic_ops->get_flash(qdev); |
c4e84bde RM |
4666 | if (err) { |
4667 | dev_err(&pdev->dev, "Invalid FLASH.\n"); | |
4f9a91c8 | 4668 | goto err_out2; |
c4e84bde RM |
4669 | } |
4670 | ||
801e9096 RM |
4671 | /* Keep local copy of current mac address. */ |
4672 | memcpy(qdev->current_mac_addr, ndev->dev_addr, ndev->addr_len); | |
c4e84bde RM |
4673 | |
4674 | /* Set up the default ring sizes. */ | |
4675 | qdev->tx_ring_size = NUM_TX_RING_ENTRIES; | |
4676 | qdev->rx_ring_size = NUM_RX_RING_ENTRIES; | |
4677 | ||
4678 | /* Set up the coalescing parameters. */ | |
4679 | qdev->rx_coalesce_usecs = DFLT_COALESCE_WAIT; | |
4680 | qdev->tx_coalesce_usecs = DFLT_COALESCE_WAIT; | |
4681 | qdev->rx_max_coalesced_frames = DFLT_INTER_FRAME_WAIT; | |
4682 | qdev->tx_max_coalesced_frames = DFLT_INTER_FRAME_WAIT; | |
4683 | ||
4684 | /* | |
4685 | * Set up the operating parameters. | |
4686 | */ | |
df656bf6 KC |
4687 | qdev->workqueue = alloc_ordered_workqueue("%s", WQ_MEM_RECLAIM, |
4688 | ndev->name); | |
c4e84bde RM |
4689 | INIT_DELAYED_WORK(&qdev->asic_reset_work, ql_asic_reset_work); |
4690 | INIT_DELAYED_WORK(&qdev->mpi_reset_work, ql_mpi_reset_work); | |
4691 | INIT_DELAYED_WORK(&qdev->mpi_work, ql_mpi_work); | |
bcc2cb3b | 4692 | INIT_DELAYED_WORK(&qdev->mpi_port_cfg_work, ql_mpi_port_cfg_work); |
2ee1e272 | 4693 | INIT_DELAYED_WORK(&qdev->mpi_idc_work, ql_mpi_idc_work); |
8aae2600 | 4694 | INIT_DELAYED_WORK(&qdev->mpi_core_to_log, ql_mpi_core_to_log); |
bcc2cb3b | 4695 | init_completion(&qdev->ide_completion); |
4d7b6b5d | 4696 | mutex_init(&qdev->mpi_mutex); |
c4e84bde RM |
4697 | |
4698 | if (!cards_found) { | |
4699 | dev_info(&pdev->dev, "%s\n", DRV_STRING); | |
4700 | dev_info(&pdev->dev, "Driver name: %s, Version: %s.\n", | |
4701 | DRV_NAME, DRV_VERSION); | |
4702 | } | |
4703 | return 0; | |
4f9a91c8 | 4704 | err_out2: |
c4e84bde | 4705 | ql_release_all(pdev); |
4f9a91c8 | 4706 | err_out1: |
c4e84bde RM |
4707 | pci_disable_device(pdev); |
4708 | return err; | |
4709 | } | |
4710 | ||
25ed7849 SH |
4711 | static const struct net_device_ops qlge_netdev_ops = { |
4712 | .ndo_open = qlge_open, | |
4713 | .ndo_stop = qlge_close, | |
4714 | .ndo_start_xmit = qlge_send, | |
4715 | .ndo_change_mtu = qlge_change_mtu, | |
4716 | .ndo_get_stats = qlge_get_stats, | |
afc4b13d | 4717 | .ndo_set_rx_mode = qlge_set_multicast_list, |
25ed7849 SH |
4718 | .ndo_set_mac_address = qlge_set_mac_address, |
4719 | .ndo_validate_addr = eth_validate_addr, | |
4720 | .ndo_tx_timeout = qlge_tx_timeout, | |
18c49b91 JP |
4721 | .ndo_fix_features = qlge_fix_features, |
4722 | .ndo_set_features = qlge_set_features, | |
01e6b953 RM |
4723 | .ndo_vlan_rx_add_vid = qlge_vlan_rx_add_vid, |
4724 | .ndo_vlan_rx_kill_vid = qlge_vlan_rx_kill_vid, | |
25ed7849 SH |
4725 | }; |
4726 | ||
df7e828c | 4727 | static void ql_timer(struct timer_list *t) |
15c052fc | 4728 | { |
df7e828c | 4729 | struct ql_adapter *qdev = from_timer(qdev, t, timer); |
15c052fc RM |
4730 | u32 var = 0; |
4731 | ||
4732 | var = ql_read32(qdev, STS); | |
4733 | if (pci_channel_offline(qdev->pdev)) { | |
ae9540f7 | 4734 | netif_err(qdev, ifup, qdev->ndev, "EEH STS = 0x%.08x.\n", var); |
15c052fc RM |
4735 | return; |
4736 | } | |
4737 | ||
72046d84 | 4738 | mod_timer(&qdev->timer, jiffies + (5*HZ)); |
15c052fc RM |
4739 | } |
4740 | ||
5d8e8726 | 4741 | static int qlge_probe(struct pci_dev *pdev, |
1dd06ae8 | 4742 | const struct pci_device_id *pci_entry) |
c4e84bde RM |
4743 | { |
4744 | struct net_device *ndev = NULL; | |
4745 | struct ql_adapter *qdev = NULL; | |
4746 | static int cards_found = 0; | |
4747 | int err = 0; | |
4748 | ||
1e213303 | 4749 | ndev = alloc_etherdev_mq(sizeof(struct ql_adapter), |
9eb8738d | 4750 | min(MAX_CPUS, netif_get_num_default_rss_queues())); |
c4e84bde RM |
4751 | if (!ndev) |
4752 | return -ENOMEM; | |
4753 | ||
4754 | err = ql_init_device(pdev, ndev, cards_found); | |
4755 | if (err < 0) { | |
4756 | free_netdev(ndev); | |
4757 | return err; | |
4758 | } | |
4759 | ||
4760 | qdev = netdev_priv(ndev); | |
4761 | SET_NETDEV_DEV(ndev, &pdev->dev); | |
a45adbe8 JK |
4762 | ndev->hw_features = NETIF_F_SG | |
4763 | NETIF_F_IP_CSUM | | |
4764 | NETIF_F_TSO | | |
4765 | NETIF_F_TSO_ECN | | |
4766 | NETIF_F_HW_VLAN_CTAG_TX | | |
4767 | NETIF_F_HW_VLAN_CTAG_RX | | |
4768 | NETIF_F_HW_VLAN_CTAG_FILTER | | |
4769 | NETIF_F_RXCSUM; | |
4770 | ndev->features = ndev->hw_features; | |
1a0150a9 | 4771 | ndev->vlan_features = ndev->hw_features; |
51bb352f | 4772 | /* vlan gets same features (except vlan filter) */ |
f6d1ac4b VY |
4773 | ndev->vlan_features &= ~(NETIF_F_HW_VLAN_CTAG_FILTER | |
4774 | NETIF_F_HW_VLAN_CTAG_TX | | |
4775 | NETIF_F_HW_VLAN_CTAG_RX); | |
c4e84bde RM |
4776 | |
4777 | if (test_bit(QL_DMA64, &qdev->flags)) | |
4778 | ndev->features |= NETIF_F_HIGHDMA; | |
4779 | ||
4780 | /* | |
4781 | * Set up net_device structure. | |
4782 | */ | |
4783 | ndev->tx_queue_len = qdev->tx_ring_size; | |
4784 | ndev->irq = pdev->irq; | |
25ed7849 SH |
4785 | |
4786 | ndev->netdev_ops = &qlge_netdev_ops; | |
7ad24ea4 | 4787 | ndev->ethtool_ops = &qlge_ethtool_ops; |
c4e84bde | 4788 | ndev->watchdog_timeo = 10 * HZ; |
25ed7849 | 4789 | |
d894be57 JW |
4790 | /* MTU range: this driver only supports 1500 or 9000, so this only |
4791 | * filters out values above or below, and we'll rely on | |
4792 | * qlge_change_mtu to make sure only 1500 or 9000 are allowed | |
4793 | */ | |
4794 | ndev->min_mtu = ETH_DATA_LEN; | |
4795 | ndev->max_mtu = 9000; | |
4796 | ||
c4e84bde RM |
4797 | err = register_netdev(ndev); |
4798 | if (err) { | |
4799 | dev_err(&pdev->dev, "net device registration failed.\n"); | |
4800 | ql_release_all(pdev); | |
4801 | pci_disable_device(pdev); | |
4d2593cc | 4802 | free_netdev(ndev); |
c4e84bde RM |
4803 | return err; |
4804 | } | |
15c052fc RM |
4805 | /* Start up the timer to trigger EEH if |
4806 | * the bus goes dead | |
4807 | */ | |
df7e828c KC |
4808 | timer_setup(&qdev->timer, ql_timer, TIMER_DEFERRABLE); |
4809 | mod_timer(&qdev->timer, jiffies + (5*HZ)); | |
6a473308 | 4810 | ql_link_off(qdev); |
c4e84bde | 4811 | ql_display_dev_info(ndev); |
9dfbbaa6 | 4812 | atomic_set(&qdev->lb_count, 0); |
c4e84bde RM |
4813 | cards_found++; |
4814 | return 0; | |
4815 | } | |
4816 | ||
9dfbbaa6 RM |
4817 | netdev_tx_t ql_lb_send(struct sk_buff *skb, struct net_device *ndev) |
4818 | { | |
4819 | return qlge_send(skb, ndev); | |
4820 | } | |
4821 | ||
4822 | int ql_clean_lb_rx_ring(struct rx_ring *rx_ring, int budget) | |
4823 | { | |
4824 | return ql_clean_inbound_rx_ring(rx_ring, budget); | |
4825 | } | |
4826 | ||
5d8e8726 | 4827 | static void qlge_remove(struct pci_dev *pdev) |
c4e84bde RM |
4828 | { |
4829 | struct net_device *ndev = pci_get_drvdata(pdev); | |
15c052fc RM |
4830 | struct ql_adapter *qdev = netdev_priv(ndev); |
4831 | del_timer_sync(&qdev->timer); | |
c5dadddb | 4832 | ql_cancel_all_work_sync(qdev); |
c4e84bde RM |
4833 | unregister_netdev(ndev); |
4834 | ql_release_all(pdev); | |
4835 | pci_disable_device(pdev); | |
4836 | free_netdev(ndev); | |
4837 | } | |
4838 | ||
6d190c6e RM |
4839 | /* Clean up resources without touching hardware. */ |
4840 | static void ql_eeh_close(struct net_device *ndev) | |
4841 | { | |
4842 | int i; | |
4843 | struct ql_adapter *qdev = netdev_priv(ndev); | |
4844 | ||
4845 | if (netif_carrier_ok(ndev)) { | |
4846 | netif_carrier_off(ndev); | |
4847 | netif_stop_queue(ndev); | |
4848 | } | |
4849 | ||
7ae80abd | 4850 | /* Disabling the timer */ |
c5dadddb | 4851 | ql_cancel_all_work_sync(qdev); |
6d190c6e RM |
4852 | |
4853 | for (i = 0; i < qdev->rss_ring_count; i++) | |
4854 | netif_napi_del(&qdev->rx_ring[i].napi); | |
4855 | ||
4856 | clear_bit(QL_ADAPTER_UP, &qdev->flags); | |
4857 | ql_tx_ring_clean(qdev); | |
4858 | ql_free_rx_buffers(qdev); | |
4859 | ql_release_adapter_resources(qdev); | |
4860 | } | |
4861 | ||
c4e84bde RM |
4862 | /* |
4863 | * This callback is called by the PCI subsystem whenever | |
4864 | * a PCI bus error is detected. | |
4865 | */ | |
4866 | static pci_ers_result_t qlge_io_error_detected(struct pci_dev *pdev, | |
4867 | enum pci_channel_state state) | |
4868 | { | |
4869 | struct net_device *ndev = pci_get_drvdata(pdev); | |
4bbd1a19 | 4870 | struct ql_adapter *qdev = netdev_priv(ndev); |
fbc663ce | 4871 | |
6d190c6e RM |
4872 | switch (state) { |
4873 | case pci_channel_io_normal: | |
4874 | return PCI_ERS_RESULT_CAN_RECOVER; | |
4875 | case pci_channel_io_frozen: | |
4876 | netif_device_detach(ndev); | |
3275c0c6 | 4877 | del_timer_sync(&qdev->timer); |
6d190c6e RM |
4878 | if (netif_running(ndev)) |
4879 | ql_eeh_close(ndev); | |
4880 | pci_disable_device(pdev); | |
4881 | return PCI_ERS_RESULT_NEED_RESET; | |
4882 | case pci_channel_io_perm_failure: | |
4883 | dev_err(&pdev->dev, | |
4884 | "%s: pci_channel_io_perm_failure.\n", __func__); | |
3275c0c6 | 4885 | del_timer_sync(&qdev->timer); |
4bbd1a19 RM |
4886 | ql_eeh_close(ndev); |
4887 | set_bit(QL_EEH_FATAL, &qdev->flags); | |
fbc663ce | 4888 | return PCI_ERS_RESULT_DISCONNECT; |
6d190c6e | 4889 | } |
c4e84bde RM |
4890 | |
4891 | /* Request a slot reset. */ | |
4892 | return PCI_ERS_RESULT_NEED_RESET; | |
4893 | } | |
4894 | ||
4895 | /* | |
4896 | * This callback is called after the PCI buss has been reset. | |
4897 | * Basically, this tries to restart the card from scratch. | |
4898 | * This is a shortened version of the device probe/discovery code, | |
4899 | * it resembles the first-half of the () routine. | |
4900 | */ | |
4901 | static pci_ers_result_t qlge_io_slot_reset(struct pci_dev *pdev) | |
4902 | { | |
4903 | struct net_device *ndev = pci_get_drvdata(pdev); | |
4904 | struct ql_adapter *qdev = netdev_priv(ndev); | |
4905 | ||
6d190c6e RM |
4906 | pdev->error_state = pci_channel_io_normal; |
4907 | ||
4908 | pci_restore_state(pdev); | |
c4e84bde | 4909 | if (pci_enable_device(pdev)) { |
ae9540f7 JP |
4910 | netif_err(qdev, ifup, qdev->ndev, |
4911 | "Cannot re-enable PCI device after reset.\n"); | |
c4e84bde RM |
4912 | return PCI_ERS_RESULT_DISCONNECT; |
4913 | } | |
c4e84bde | 4914 | pci_set_master(pdev); |
a112fd4c RM |
4915 | |
4916 | if (ql_adapter_reset(qdev)) { | |
ae9540f7 | 4917 | netif_err(qdev, drv, qdev->ndev, "reset FAILED!\n"); |
4bbd1a19 | 4918 | set_bit(QL_EEH_FATAL, &qdev->flags); |
a112fd4c RM |
4919 | return PCI_ERS_RESULT_DISCONNECT; |
4920 | } | |
4921 | ||
c4e84bde RM |
4922 | return PCI_ERS_RESULT_RECOVERED; |
4923 | } | |
4924 | ||
4925 | static void qlge_io_resume(struct pci_dev *pdev) | |
4926 | { | |
4927 | struct net_device *ndev = pci_get_drvdata(pdev); | |
4928 | struct ql_adapter *qdev = netdev_priv(ndev); | |
6d190c6e | 4929 | int err = 0; |
c4e84bde | 4930 | |
c4e84bde | 4931 | if (netif_running(ndev)) { |
6d190c6e RM |
4932 | err = qlge_open(ndev); |
4933 | if (err) { | |
ae9540f7 JP |
4934 | netif_err(qdev, ifup, qdev->ndev, |
4935 | "Device initialization failed after reset.\n"); | |
c4e84bde RM |
4936 | return; |
4937 | } | |
6d190c6e | 4938 | } else { |
ae9540f7 JP |
4939 | netif_err(qdev, ifup, qdev->ndev, |
4940 | "Device was not running prior to EEH.\n"); | |
c4e84bde | 4941 | } |
72046d84 | 4942 | mod_timer(&qdev->timer, jiffies + (5*HZ)); |
c4e84bde RM |
4943 | netif_device_attach(ndev); |
4944 | } | |
4945 | ||
3646f0e5 | 4946 | static const struct pci_error_handlers qlge_err_handler = { |
c4e84bde RM |
4947 | .error_detected = qlge_io_error_detected, |
4948 | .slot_reset = qlge_io_slot_reset, | |
4949 | .resume = qlge_io_resume, | |
4950 | }; | |
4951 | ||
4952 | static int qlge_suspend(struct pci_dev *pdev, pm_message_t state) | |
4953 | { | |
4954 | struct net_device *ndev = pci_get_drvdata(pdev); | |
4955 | struct ql_adapter *qdev = netdev_priv(ndev); | |
6b318cb3 | 4956 | int err; |
c4e84bde RM |
4957 | |
4958 | netif_device_detach(ndev); | |
15c052fc | 4959 | del_timer_sync(&qdev->timer); |
c4e84bde RM |
4960 | |
4961 | if (netif_running(ndev)) { | |
4962 | err = ql_adapter_down(qdev); | |
4963 | if (!err) | |
4964 | return err; | |
4965 | } | |
4966 | ||
bc083ce9 | 4967 | ql_wol(qdev); |
c4e84bde RM |
4968 | err = pci_save_state(pdev); |
4969 | if (err) | |
4970 | return err; | |
4971 | ||
4972 | pci_disable_device(pdev); | |
4973 | ||
4974 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); | |
4975 | ||
4976 | return 0; | |
4977 | } | |
4978 | ||
04da2cf9 | 4979 | #ifdef CONFIG_PM |
c4e84bde RM |
4980 | static int qlge_resume(struct pci_dev *pdev) |
4981 | { | |
4982 | struct net_device *ndev = pci_get_drvdata(pdev); | |
4983 | struct ql_adapter *qdev = netdev_priv(ndev); | |
4984 | int err; | |
4985 | ||
4986 | pci_set_power_state(pdev, PCI_D0); | |
4987 | pci_restore_state(pdev); | |
4988 | err = pci_enable_device(pdev); | |
4989 | if (err) { | |
ae9540f7 | 4990 | netif_err(qdev, ifup, qdev->ndev, "Cannot enable PCI device from suspend\n"); |
c4e84bde RM |
4991 | return err; |
4992 | } | |
4993 | pci_set_master(pdev); | |
4994 | ||
4995 | pci_enable_wake(pdev, PCI_D3hot, 0); | |
4996 | pci_enable_wake(pdev, PCI_D3cold, 0); | |
4997 | ||
4998 | if (netif_running(ndev)) { | |
4999 | err = ql_adapter_up(qdev); | |
5000 | if (err) | |
5001 | return err; | |
5002 | } | |
5003 | ||
72046d84 | 5004 | mod_timer(&qdev->timer, jiffies + (5*HZ)); |
c4e84bde RM |
5005 | netif_device_attach(ndev); |
5006 | ||
5007 | return 0; | |
5008 | } | |
04da2cf9 | 5009 | #endif /* CONFIG_PM */ |
c4e84bde RM |
5010 | |
5011 | static void qlge_shutdown(struct pci_dev *pdev) | |
5012 | { | |
5013 | qlge_suspend(pdev, PMSG_SUSPEND); | |
5014 | } | |
5015 | ||
5016 | static struct pci_driver qlge_driver = { | |
5017 | .name = DRV_NAME, | |
5018 | .id_table = qlge_pci_tbl, | |
5019 | .probe = qlge_probe, | |
5d8e8726 | 5020 | .remove = qlge_remove, |
c4e84bde RM |
5021 | #ifdef CONFIG_PM |
5022 | .suspend = qlge_suspend, | |
5023 | .resume = qlge_resume, | |
5024 | #endif | |
5025 | .shutdown = qlge_shutdown, | |
5026 | .err_handler = &qlge_err_handler | |
5027 | }; | |
5028 | ||
70a611de | 5029 | module_pci_driver(qlge_driver); |