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b9b17deb
TT		 1/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13/* Qualcomm Technologies, Inc. EMAC Ethernet Controller MAC layer support
14 */
15
16#include <linux/tcp.h>
17#include <linux/ip.h>
18#include <linux/ipv6.h>
19#include <linux/crc32.h>
20#include <linux/if_vlan.h>
21#include <linux/jiffies.h>
22#include <linux/phy.h>
23#include <linux/of.h>
24#include <net/ip6_checksum.h>
25#include "emac.h"
26#include "emac-sgmii.h"
27
28/* EMAC base register offsets */
29#define EMAC_MAC_CTRL 0x001480
30#define EMAC_WOL_CTRL0 0x0014a0
31#define EMAC_RSS_KEY0 0x0014b0
32#define EMAC_H1TPD_BASE_ADDR_LO 0x0014e0
33#define EMAC_H2TPD_BASE_ADDR_LO 0x0014e4
34#define EMAC_H3TPD_BASE_ADDR_LO 0x0014e8
35#define EMAC_INTER_SRAM_PART9 0x001534
36#define EMAC_DESC_CTRL_0 0x001540
37#define EMAC_DESC_CTRL_1 0x001544
38#define EMAC_DESC_CTRL_2 0x001550
39#define EMAC_DESC_CTRL_10 0x001554
40#define EMAC_DESC_CTRL_12 0x001558
41#define EMAC_DESC_CTRL_13 0x00155c
42#define EMAC_DESC_CTRL_3 0x001560
43#define EMAC_DESC_CTRL_4 0x001564
44#define EMAC_DESC_CTRL_5 0x001568
45#define EMAC_DESC_CTRL_14 0x00156c
46#define EMAC_DESC_CTRL_15 0x001570
47#define EMAC_DESC_CTRL_16 0x001574
48#define EMAC_DESC_CTRL_6 0x001578
49#define EMAC_DESC_CTRL_8 0x001580
50#define EMAC_DESC_CTRL_9 0x001584
51#define EMAC_DESC_CTRL_11 0x001588
52#define EMAC_TXQ_CTRL_0 0x001590
53#define EMAC_TXQ_CTRL_1 0x001594
54#define EMAC_TXQ_CTRL_2 0x001598
55#define EMAC_RXQ_CTRL_0 0x0015a0
56#define EMAC_RXQ_CTRL_1 0x0015a4
57#define EMAC_RXQ_CTRL_2 0x0015a8
58#define EMAC_RXQ_CTRL_3 0x0015ac
59#define EMAC_BASE_CPU_NUMBER 0x0015b8
60#define EMAC_DMA_CTRL 0x0015c0
61#define EMAC_MAILBOX_0 0x0015e0
62#define EMAC_MAILBOX_5 0x0015e4
63#define EMAC_MAILBOX_6 0x0015e8
64#define EMAC_MAILBOX_13 0x0015ec
65#define EMAC_MAILBOX_2 0x0015f4
66#define EMAC_MAILBOX_3 0x0015f8
67#define EMAC_MAILBOX_11 0x00160c
68#define EMAC_AXI_MAST_CTRL 0x001610
69#define EMAC_MAILBOX_12 0x001614
70#define EMAC_MAILBOX_9 0x001618
71#define EMAC_MAILBOX_10 0x00161c
72#define EMAC_ATHR_HEADER_CTRL 0x001620
73#define EMAC_CLK_GATE_CTRL 0x001814
74#define EMAC_MISC_CTRL 0x001990
75#define EMAC_MAILBOX_7 0x0019e0
76#define EMAC_MAILBOX_8 0x0019e4
77#define EMAC_MAILBOX_15 0x001bd4
78#define EMAC_MAILBOX_16 0x001bd8
79
80/* EMAC_MAC_CTRL */
81#define SINGLE_PAUSE_MODE 0x10000000
82#define DEBUG_MODE 0x08000000
83#define BROAD_EN 0x04000000
84#define MULTI_ALL 0x02000000
85#define RX_CHKSUM_EN 0x01000000
86#define HUGE 0x00800000
87#define SPEED(x) (((x) & 0x3) << 20)
88#define SPEED_MASK SPEED(0x3)
89#define SIMR 0x00080000
90#define TPAUSE 0x00010000
91#define PROM_MODE 0x00008000
92#define VLAN_STRIP 0x00004000
93#define PRLEN_BMSK 0x00003c00
94#define PRLEN_SHFT 10
95#define HUGEN 0x00000200
96#define FLCHK 0x00000100
97#define PCRCE 0x00000080
98#define CRCE 0x00000040
99#define FULLD 0x00000020
100#define MAC_LP_EN 0x00000010
101#define RXFC 0x00000008
102#define TXFC 0x00000004
103#define RXEN 0x00000002
104#define TXEN 0x00000001
105
b9b17deb
TT		 106/* EMAC_DESC_CTRL_3 */
107#define RFD_RING_SIZE_BMSK 0xfff
108
109/* EMAC_DESC_CTRL_4 */
110#define RX_BUFFER_SIZE_BMSK 0xffff
111
112/* EMAC_DESC_CTRL_6 */
113#define RRD_RING_SIZE_BMSK 0xfff
114
115/* EMAC_DESC_CTRL_9 */
116#define TPD_RING_SIZE_BMSK 0xffff
117
118/* EMAC_TXQ_CTRL_0 */
119#define NUM_TXF_BURST_PREF_BMSK 0xffff0000
120#define NUM_TXF_BURST_PREF_SHFT 16
121#define LS_8023_SP 0x80
122#define TXQ_MODE 0x40
123#define TXQ_EN 0x20
124#define IP_OP_SP 0x10
125#define NUM_TPD_BURST_PREF_BMSK 0xf
126#define NUM_TPD_BURST_PREF_SHFT 0
127
128/* EMAC_TXQ_CTRL_1 */
129#define JUMBO_TASK_OFFLOAD_THRESHOLD_BMSK 0x7ff
130
131/* EMAC_TXQ_CTRL_2 */
132#define TXF_HWM_BMSK 0xfff0000
133#define TXF_LWM_BMSK 0xfff
134
135/* EMAC_RXQ_CTRL_0 */
136#define RXQ_EN BIT(31)
137#define CUT_THRU_EN BIT(30)
138#define RSS_HASH_EN BIT(29)
139#define NUM_RFD_BURST_PREF_BMSK 0x3f00000
140#define NUM_RFD_BURST_PREF_SHFT 20
141#define IDT_TABLE_SIZE_BMSK 0x1ff00
142#define IDT_TABLE_SIZE_SHFT 8
143#define SP_IPV6 0x80
144
145/* EMAC_RXQ_CTRL_1 */
146#define JUMBO_1KAH_BMSK 0xf000
147#define JUMBO_1KAH_SHFT 12
148#define RFD_PREF_LOW_TH 0x10
149#define RFD_PREF_LOW_THRESHOLD_BMSK 0xfc0
150#define RFD_PREF_LOW_THRESHOLD_SHFT 6
151#define RFD_PREF_UP_TH 0x10
152#define RFD_PREF_UP_THRESHOLD_BMSK 0x3f
153#define RFD_PREF_UP_THRESHOLD_SHFT 0
154
155/* EMAC_RXQ_CTRL_2 */
156#define RXF_DOF_THRESFHOLD 0x1a0
157#define RXF_DOF_THRESHOLD_BMSK 0xfff0000
158#define RXF_DOF_THRESHOLD_SHFT 16
159#define RXF_UOF_THRESFHOLD 0xbe
160#define RXF_UOF_THRESHOLD_BMSK 0xfff
161#define RXF_UOF_THRESHOLD_SHFT 0
162
163/* EMAC_RXQ_CTRL_3 */
164#define RXD_TIMER_BMSK 0xffff0000
165#define RXD_THRESHOLD_BMSK 0xfff
166#define RXD_THRESHOLD_SHFT 0
167
168/* EMAC_DMA_CTRL */
169#define DMAW_DLY_CNT_BMSK 0xf0000
170#define DMAW_DLY_CNT_SHFT 16
171#define DMAR_DLY_CNT_BMSK 0xf800
172#define DMAR_DLY_CNT_SHFT 11
173#define DMAR_REQ_PRI 0x400
174#define REGWRBLEN_BMSK 0x380
175#define REGWRBLEN_SHFT 7
176#define REGRDBLEN_BMSK 0x70
177#define REGRDBLEN_SHFT 4
178#define OUT_ORDER_MODE 0x4
179#define ENH_ORDER_MODE 0x2
180#define IN_ORDER_MODE 0x1
181
182/* EMAC_MAILBOX_13 */
183#define RFD3_PROC_IDX_BMSK 0xfff0000
184#define RFD3_PROC_IDX_SHFT 16
185#define RFD3_PROD_IDX_BMSK 0xfff
186#define RFD3_PROD_IDX_SHFT 0
187
188/* EMAC_MAILBOX_2 */
189#define NTPD_CONS_IDX_BMSK 0xffff0000
190#define NTPD_CONS_IDX_SHFT 16
191
192/* EMAC_MAILBOX_3 */
193#define RFD0_CONS_IDX_BMSK 0xfff
194#define RFD0_CONS_IDX_SHFT 0
195
196/* EMAC_MAILBOX_11 */
197#define H3TPD_PROD_IDX_BMSK 0xffff0000
198#define H3TPD_PROD_IDX_SHFT 16
199
200/* EMAC_AXI_MAST_CTRL */
201#define DATA_BYTE_SWAP 0x8
202#define MAX_BOUND 0x2
203#define MAX_BTYPE 0x1
204
205/* EMAC_MAILBOX_12 */
206#define H3TPD_CONS_IDX_BMSK 0xffff0000
207#define H3TPD_CONS_IDX_SHFT 16
208
209/* EMAC_MAILBOX_9 */
210#define H2TPD_PROD_IDX_BMSK 0xffff
211#define H2TPD_PROD_IDX_SHFT 0
212
213/* EMAC_MAILBOX_10 */
214#define H1TPD_CONS_IDX_BMSK 0xffff0000
215#define H1TPD_CONS_IDX_SHFT 16
216#define H2TPD_CONS_IDX_BMSK 0xffff
217#define H2TPD_CONS_IDX_SHFT 0
218
219/* EMAC_ATHR_HEADER_CTRL */
220#define HEADER_CNT_EN 0x2
221#define HEADER_ENABLE 0x1
222
223/* EMAC_MAILBOX_0 */
224#define RFD0_PROC_IDX_BMSK 0xfff0000
225#define RFD0_PROC_IDX_SHFT 16
226#define RFD0_PROD_IDX_BMSK 0xfff
227#define RFD0_PROD_IDX_SHFT 0
228
229/* EMAC_MAILBOX_5 */
230#define RFD1_PROC_IDX_BMSK 0xfff0000
231#define RFD1_PROC_IDX_SHFT 16
232#define RFD1_PROD_IDX_BMSK 0xfff
233#define RFD1_PROD_IDX_SHFT 0
234
235/* EMAC_MISC_CTRL */
236#define RX_UNCPL_INT_EN 0x1
237
238/* EMAC_MAILBOX_7 */
239#define RFD2_CONS_IDX_BMSK 0xfff0000
240#define RFD2_CONS_IDX_SHFT 16
241#define RFD1_CONS_IDX_BMSK 0xfff
242#define RFD1_CONS_IDX_SHFT 0
243
244/* EMAC_MAILBOX_8 */
245#define RFD3_CONS_IDX_BMSK 0xfff
246#define RFD3_CONS_IDX_SHFT 0
247
248/* EMAC_MAILBOX_15 */
249#define NTPD_PROD_IDX_BMSK 0xffff
250#define NTPD_PROD_IDX_SHFT 0
251
252/* EMAC_MAILBOX_16 */
253#define H1TPD_PROD_IDX_BMSK 0xffff
254#define H1TPD_PROD_IDX_SHFT 0
255
256#define RXQ0_RSS_HSTYP_IPV6_TCP_EN 0x20
257#define RXQ0_RSS_HSTYP_IPV6_EN 0x10
258#define RXQ0_RSS_HSTYP_IPV4_TCP_EN 0x8
259#define RXQ0_RSS_HSTYP_IPV4_EN 0x4
260
261/* EMAC_EMAC_WRAPPER_TX_TS_INX */
262#define EMAC_WRAPPER_TX_TS_EMPTY BIT(31)
263#define EMAC_WRAPPER_TX_TS_INX_BMSK 0xffff
264
265struct emac_skb_cb {
266 u32 tpd_idx;
267 unsigned long jiffies;
268};
269
270#define EMAC_SKB_CB(skb) ((struct emac_skb_cb *)(skb)->cb)
271#define EMAC_RSS_IDT_SIZE 256
272#define JUMBO_1KAH 0x4
273#define RXD_TH 0x100
274#define EMAC_TPD_LAST_FRAGMENT 0x80000000
275#define EMAC_TPD_TSTAMP_SAVE 0x80000000
276
277/* EMAC Errors in emac_rrd.word[3] */
278#define EMAC_RRD_L4F BIT(14)
279#define EMAC_RRD_IPF BIT(15)
280#define EMAC_RRD_CRC BIT(21)
281#define EMAC_RRD_FAE BIT(22)
282#define EMAC_RRD_TRN BIT(23)
283#define EMAC_RRD_RNT BIT(24)
284#define EMAC_RRD_INC BIT(25)
285#define EMAC_RRD_FOV BIT(29)
286#define EMAC_RRD_LEN BIT(30)
287
288/* Error bits that will result in a received frame being discarded */
289#define EMAC_RRD_ERROR (EMAC_RRD_IPF | EMAC_RRD_CRC | EMAC_RRD_FAE | \
290 EMAC_RRD_TRN | EMAC_RRD_RNT | EMAC_RRD_INC | \
291 EMAC_RRD_FOV | EMAC_RRD_LEN)
292#define EMAC_RRD_STATS_DW_IDX 3
293
294#define EMAC_RRD(RXQ, SIZE, IDX) ((RXQ)->rrd.v_addr + (SIZE * (IDX)))
295#define EMAC_RFD(RXQ, SIZE, IDX) ((RXQ)->rfd.v_addr + (SIZE * (IDX)))
296#define EMAC_TPD(TXQ, SIZE, IDX) ((TXQ)->tpd.v_addr + (SIZE * (IDX)))
297
298#define GET_RFD_BUFFER(RXQ, IDX) (&((RXQ)->rfd.rfbuff[(IDX)]))
299#define GET_TPD_BUFFER(RTQ, IDX) (&((RTQ)->tpd.tpbuff[(IDX)]))
300
301#define EMAC_TX_POLL_HWTXTSTAMP_THRESHOLD 8
302
303#define ISR_RX_PKT (\
304 RX_PKT_INT0 |\
305 RX_PKT_INT1 |\
306 RX_PKT_INT2 |\
307 RX_PKT_INT3)
308
b9b17deb
TT		 309void emac_mac_multicast_addr_set(struct emac_adapter *adpt, u8 *addr)
310{
311 u32 crc32, bit, reg, mta;
312
313 /* Calculate the CRC of the MAC address */
314 crc32 = ether_crc(ETH_ALEN, addr);
315
316 /* The HASH Table is an array of 2 32-bit registers. It is
317 * treated like an array of 64 bits (BitArray[hash_value]).
318 * Use the upper 6 bits of the above CRC as the hash value.
319 */
320 reg = (crc32 >> 31) & 0x1;
321 bit = (crc32 >> 26) & 0x1F;
322
323 mta = readl(adpt->base + EMAC_HASH_TAB_REG0 + (reg << 2));
324 mta |= BIT(bit);
325 writel(mta, adpt->base + EMAC_HASH_TAB_REG0 + (reg << 2));
326}
327
328void emac_mac_multicast_addr_clear(struct emac_adapter *adpt)
329{
330 writel(0, adpt->base + EMAC_HASH_TAB_REG0);
331 writel(0, adpt->base + EMAC_HASH_TAB_REG1);
332}
333
334/* definitions for RSS */
335#define EMAC_RSS_KEY(_i, _type) \
336 (EMAC_RSS_KEY0 + ((_i) * sizeof(_type)))
337#define EMAC_RSS_TBL(_i, _type) \
338 (EMAC_IDT_TABLE0 + ((_i) * sizeof(_type)))
339
340/* Config MAC modes */
341void emac_mac_mode_config(struct emac_adapter *adpt)
342{
343 struct net_device *netdev = adpt->netdev;
344 u32 mac;
345
346 mac = readl(adpt->base + EMAC_MAC_CTRL);
347 mac &= ~(VLAN_STRIP | PROM_MODE | MULTI_ALL | MAC_LP_EN);
348
349 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
350 mac |= VLAN_STRIP;
351
352 if (netdev->flags & IFF_PROMISC)
353 mac |= PROM_MODE;
354
355 if (netdev->flags & IFF_ALLMULTI)
356 mac |= MULTI_ALL;
357
358 writel(mac, adpt->base + EMAC_MAC_CTRL);
359}
360
361/* Config descriptor rings */
362static void emac_mac_dma_rings_config(struct emac_adapter *adpt)
363{
364 static const unsigned short tpd_q_offset[] = {
365 EMAC_DESC_CTRL_8, EMAC_H1TPD_BASE_ADDR_LO,
366 EMAC_H2TPD_BASE_ADDR_LO, EMAC_H3TPD_BASE_ADDR_LO};
367 static const unsigned short rfd_q_offset[] = {
368 EMAC_DESC_CTRL_2, EMAC_DESC_CTRL_10,
369 EMAC_DESC_CTRL_12, EMAC_DESC_CTRL_13};
370 static const unsigned short rrd_q_offset[] = {
371 EMAC_DESC_CTRL_5, EMAC_DESC_CTRL_14,
372 EMAC_DESC_CTRL_15, EMAC_DESC_CTRL_16};
373
374 /* TPD (Transmit Packet Descriptor) */
375 writel(upper_32_bits(adpt->tx_q.tpd.dma_addr),
376 adpt->base + EMAC_DESC_CTRL_1);
377
378 writel(lower_32_bits(adpt->tx_q.tpd.dma_addr),
379 adpt->base + tpd_q_offset[0]);
380
381 writel(adpt->tx_q.tpd.count & TPD_RING_SIZE_BMSK,
382 adpt->base + EMAC_DESC_CTRL_9);
383
384 /* RFD (Receive Free Descriptor) & RRD (Receive Return Descriptor) */
385 writel(upper_32_bits(adpt->rx_q.rfd.dma_addr),
386 adpt->base + EMAC_DESC_CTRL_0);
387
388 writel(lower_32_bits(adpt->rx_q.rfd.dma_addr),
389 adpt->base + rfd_q_offset[0]);
390 writel(lower_32_bits(adpt->rx_q.rrd.dma_addr),
391 adpt->base + rrd_q_offset[0]);
392
393 writel(adpt->rx_q.rfd.count & RFD_RING_SIZE_BMSK,
394 adpt->base + EMAC_DESC_CTRL_3);
395 writel(adpt->rx_q.rrd.count & RRD_RING_SIZE_BMSK,
396 adpt->base + EMAC_DESC_CTRL_6);
397
398 writel(adpt->rxbuf_size & RX_BUFFER_SIZE_BMSK,
399 adpt->base + EMAC_DESC_CTRL_4);
400
401 writel(0, adpt->base + EMAC_DESC_CTRL_11);
402
403 /* Load all of the base addresses above and ensure that triggering HW to
404 * read ring pointers is flushed
405 */
406 writel(1, adpt->base + EMAC_INTER_SRAM_PART9);
407}
408
409/* Config transmit parameters */
410static void emac_mac_tx_config(struct emac_adapter *adpt)
411{
412 u32 val;
413
414 writel((EMAC_MAX_TX_OFFLOAD_THRESH >> 3) &
415 JUMBO_TASK_OFFLOAD_THRESHOLD_BMSK, adpt->base + EMAC_TXQ_CTRL_1);
416
417 val = (adpt->tpd_burst << NUM_TPD_BURST_PREF_SHFT) &
418 NUM_TPD_BURST_PREF_BMSK;
419
420 val |= TXQ_MODE | LS_8023_SP;
421 val |= (0x0100 << NUM_TXF_BURST_PREF_SHFT) &
422 NUM_TXF_BURST_PREF_BMSK;
423
424 writel(val, adpt->base + EMAC_TXQ_CTRL_0);
425 emac_reg_update32(adpt->base + EMAC_TXQ_CTRL_2,
426 (TXF_HWM_BMSK | TXF_LWM_BMSK), 0);
427}
428
429/* Config receive parameters */
430static void emac_mac_rx_config(struct emac_adapter *adpt)
431{
432 u32 val;
433
434 val = (adpt->rfd_burst << NUM_RFD_BURST_PREF_SHFT) &
435 NUM_RFD_BURST_PREF_BMSK;
436 val |= (SP_IPV6 | CUT_THRU_EN);
437
438 writel(val, adpt->base + EMAC_RXQ_CTRL_0);
439
440 val = readl(adpt->base + EMAC_RXQ_CTRL_1);
441 val &= ~(JUMBO_1KAH_BMSK | RFD_PREF_LOW_THRESHOLD_BMSK |
442 RFD_PREF_UP_THRESHOLD_BMSK);
443 val |= (JUMBO_1KAH << JUMBO_1KAH_SHFT) |
444 (RFD_PREF_LOW_TH << RFD_PREF_LOW_THRESHOLD_SHFT) |
445 (RFD_PREF_UP_TH << RFD_PREF_UP_THRESHOLD_SHFT);
446 writel(val, adpt->base + EMAC_RXQ_CTRL_1);
447
448 val = readl(adpt->base + EMAC_RXQ_CTRL_2);
449 val &= ~(RXF_DOF_THRESHOLD_BMSK | RXF_UOF_THRESHOLD_BMSK);
450 val |= (RXF_DOF_THRESFHOLD << RXF_DOF_THRESHOLD_SHFT) |
451 (RXF_UOF_THRESFHOLD << RXF_UOF_THRESHOLD_SHFT);
452 writel(val, adpt->base + EMAC_RXQ_CTRL_2);
453
454 val = readl(adpt->base + EMAC_RXQ_CTRL_3);
455 val &= ~(RXD_TIMER_BMSK | RXD_THRESHOLD_BMSK);
456 val |= RXD_TH << RXD_THRESHOLD_SHFT;
457 writel(val, adpt->base + EMAC_RXQ_CTRL_3);
458}
459
460/* Config dma */
461static void emac_mac_dma_config(struct emac_adapter *adpt)
462{
463 u32 dma_ctrl = DMAR_REQ_PRI;
464
465 switch (adpt->dma_order) {
466 case emac_dma_ord_in:
467 dma_ctrl |= IN_ORDER_MODE;
468 break;
469 case emac_dma_ord_enh:
470 dma_ctrl |= ENH_ORDER_MODE;
471 break;
472 case emac_dma_ord_out:
473 dma_ctrl |= OUT_ORDER_MODE;
474 break;
475 default:
476 break;
477 }
478
479 dma_ctrl |= (((u32)adpt->dmar_block) << REGRDBLEN_SHFT) &
480 REGRDBLEN_BMSK;
481 dma_ctrl |= (((u32)adpt->dmaw_block) << REGWRBLEN_SHFT) &
482 REGWRBLEN_BMSK;
483 dma_ctrl |= (((u32)adpt->dmar_dly_cnt) << DMAR_DLY_CNT_SHFT) &
484 DMAR_DLY_CNT_BMSK;
485 dma_ctrl |= (((u32)adpt->dmaw_dly_cnt) << DMAW_DLY_CNT_SHFT) &
486 DMAW_DLY_CNT_BMSK;
487
488 /* config DMA and ensure that configuration is flushed to HW */
489 writel(dma_ctrl, adpt->base + EMAC_DMA_CTRL);
490}
491
492/* set MAC address */
493static void emac_set_mac_address(struct emac_adapter *adpt, u8 *addr)
494{
495 u32 sta;
496
497 /* for example: 00-A0-C6-11-22-33
498 * 0<-->C6112233, 1<-->00A0.
499 */
500
501 /* low 32bit word */
502 sta = (((u32)addr[2]) << 24) | (((u32)addr[3]) << 16) |
503 (((u32)addr[4]) << 8) | (((u32)addr[5]));
504 writel(sta, adpt->base + EMAC_MAC_STA_ADDR0);
505
506 /* hight 32bit word */
507 sta = (((u32)addr[0]) << 8) | (u32)addr[1];
508 writel(sta, adpt->base + EMAC_MAC_STA_ADDR1);
509}
510
511static void emac_mac_config(struct emac_adapter *adpt)
512{
513 struct net_device *netdev = adpt->netdev;
514 unsigned int max_frame;
515 u32 val;
516
517 emac_set_mac_address(adpt, netdev->dev_addr);
518
519 max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
520 adpt->rxbuf_size = netdev->mtu > EMAC_DEF_RX_BUF_SIZE ?
521 ALIGN(max_frame, 8) : EMAC_DEF_RX_BUF_SIZE;
522
523 emac_mac_dma_rings_config(adpt);
524
525 writel(netdev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
526 adpt->base + EMAC_MAX_FRAM_LEN_CTRL);
527
528 emac_mac_tx_config(adpt);
529 emac_mac_rx_config(adpt);
530 emac_mac_dma_config(adpt);
531
532 val = readl(adpt->base + EMAC_AXI_MAST_CTRL);
533 val &= ~(DATA_BYTE_SWAP | MAX_BOUND);
534 val |= MAX_BTYPE;
535 writel(val, adpt->base + EMAC_AXI_MAST_CTRL);
536 writel(0, adpt->base + EMAC_CLK_GATE_CTRL);
537 writel(RX_UNCPL_INT_EN, adpt->base + EMAC_MISC_CTRL);
538}
539
540void emac_mac_reset(struct emac_adapter *adpt)
541{
542 emac_mac_stop(adpt);
543
544 emac_reg_update32(adpt->base + EMAC_DMA_MAS_CTRL, 0, SOFT_RST);
545 usleep_range(100, 150); /* reset may take up to 100usec */
546
547 /* interrupt clear-on-read */
548 emac_reg_update32(adpt->base + EMAC_DMA_MAS_CTRL, 0, INT_RD_CLR_EN);
549}
550
0f20276d 551static void emac_mac_start(struct emac_adapter *adpt)
b9b17deb
TT		 552{
553 struct phy_device *phydev = adpt->phydev;
554 u32 mac, csr1;
555
556 /* enable tx queue */
557 emac_reg_update32(adpt->base + EMAC_TXQ_CTRL_0, 0, TXQ_EN);
558
559 /* enable rx queue */
560 emac_reg_update32(adpt->base + EMAC_RXQ_CTRL_0, 0, RXQ_EN);
561
562 /* enable mac control */
563 mac = readl(adpt->base + EMAC_MAC_CTRL);
564 csr1 = readl(adpt->csr + EMAC_EMAC_WRAPPER_CSR1);
565
566 mac |= TXEN | RXEN; /* enable RX/TX */
567
df63022e
TT		 568 /* Configure MAC flow control to match the PHY's settings. */
569 if (phydev->pause)
570 mac |= RXFC;
571 if (phydev->pause != phydev->asym_pause)
572 mac |= TXFC;
b9b17deb
TT		 573
574 /* setup link speed */
575 mac &= ~SPEED_MASK;
576 if (phydev->speed == SPEED_1000) {
577 mac |= SPEED(2);
578 csr1 |= FREQ_MODE;
579 } else {
580 mac |= SPEED(1);
581 csr1 &= ~FREQ_MODE;
582 }
583
584 if (phydev->duplex == DUPLEX_FULL)
585 mac |= FULLD;
586 else
587 mac &= ~FULLD;
588
589 /* other parameters */
590 mac |= (CRCE | PCRCE);
591 mac |= ((adpt->preamble << PRLEN_SHFT) & PRLEN_BMSK);
592 mac |= BROAD_EN;
593 mac |= FLCHK;
594 mac &= ~RX_CHKSUM_EN;
595 mac &= ~(HUGEN | VLAN_STRIP | TPAUSE | SIMR | HUGE | MULTI_ALL |
596 DEBUG_MODE | SINGLE_PAUSE_MODE);
597
598 writel_relaxed(csr1, adpt->csr + EMAC_EMAC_WRAPPER_CSR1);
599
600 writel_relaxed(mac, adpt->base + EMAC_MAC_CTRL);
601
602 /* enable interrupt read clear, low power sleep mode and
603 * the irq moderators
604 */
605
606 writel_relaxed(adpt->irq_mod, adpt->base + EMAC_IRQ_MOD_TIM_INIT);
607 writel_relaxed(INT_RD_CLR_EN | LPW_MODE | IRQ_MODERATOR_EN |
608 IRQ_MODERATOR2_EN, adpt->base + EMAC_DMA_MAS_CTRL);
609
610 emac_mac_mode_config(adpt);
611
612 emac_reg_update32(adpt->base + EMAC_ATHR_HEADER_CTRL,
613 (HEADER_ENABLE | HEADER_CNT_EN), 0);
b9b17deb
TT		 614}
615
616void emac_mac_stop(struct emac_adapter *adpt)
617{
618 emac_reg_update32(adpt->base + EMAC_RXQ_CTRL_0, RXQ_EN, 0);
619 emac_reg_update32(adpt->base + EMAC_TXQ_CTRL_0, TXQ_EN, 0);
620 emac_reg_update32(adpt->base + EMAC_MAC_CTRL, TXEN | RXEN, 0);
621 usleep_range(1000, 1050); /* stopping mac may take upto 1msec */
622}
623
624/* Free all descriptors of given transmit queue */
625static void emac_tx_q_descs_free(struct emac_adapter *adpt)
626{
627 struct emac_tx_queue *tx_q = &adpt->tx_q;
628 unsigned int i;
629 size_t size;
630
631 /* ring already cleared, nothing to do */
632 if (!tx_q->tpd.tpbuff)
633 return;
634
635 for (i = 0; i < tx_q->tpd.count; i++) {
636 struct emac_buffer *tpbuf = GET_TPD_BUFFER(tx_q, i);
637
638 if (tpbuf->dma_addr) {
639 dma_unmap_single(adpt->netdev->dev.parent,
640 tpbuf->dma_addr, tpbuf->length,
641 DMA_TO_DEVICE);
642 tpbuf->dma_addr = 0;
643 }
644 if (tpbuf->skb) {
645 dev_kfree_skb_any(tpbuf->skb);
646 tpbuf->skb = NULL;
647 }
648 }
649
650 size = sizeof(struct emac_buffer) * tx_q->tpd.count;
651 memset(tx_q->tpd.tpbuff, 0, size);
652
653 /* clear the descriptor ring */
654 memset(tx_q->tpd.v_addr, 0, tx_q->tpd.size);
655
656 tx_q->tpd.consume_idx = 0;
657 tx_q->tpd.produce_idx = 0;
658}
659
660/* Free all descriptors of given receive queue */
661static void emac_rx_q_free_descs(struct emac_adapter *adpt)
662{
663 struct device *dev = adpt->netdev->dev.parent;
664 struct emac_rx_queue *rx_q = &adpt->rx_q;
665 unsigned int i;
666 size_t size;
667
668 /* ring already cleared, nothing to do */
669 if (!rx_q->rfd.rfbuff)
670 return;
671
672 for (i = 0; i < rx_q->rfd.count; i++) {
673 struct emac_buffer *rfbuf = GET_RFD_BUFFER(rx_q, i);
674
675 if (rfbuf->dma_addr) {
676 dma_unmap_single(dev, rfbuf->dma_addr, rfbuf->length,
677 DMA_FROM_DEVICE);
678 rfbuf->dma_addr = 0;
679 }
680 if (rfbuf->skb) {
681 dev_kfree_skb(rfbuf->skb);
682 rfbuf->skb = NULL;
683 }
684 }
685
686 size = sizeof(struct emac_buffer) * rx_q->rfd.count;
687 memset(rx_q->rfd.rfbuff, 0, size);
688
689 /* clear the descriptor rings */
690 memset(rx_q->rrd.v_addr, 0, rx_q->rrd.size);
691 rx_q->rrd.produce_idx = 0;
692 rx_q->rrd.consume_idx = 0;
693
694 memset(rx_q->rfd.v_addr, 0, rx_q->rfd.size);
695 rx_q->rfd.produce_idx = 0;
696 rx_q->rfd.consume_idx = 0;
697}
698
699/* Free all buffers associated with given transmit queue */
700static void emac_tx_q_bufs_free(struct emac_adapter *adpt)
701{
702 struct emac_tx_queue *tx_q = &adpt->tx_q;
703
704 emac_tx_q_descs_free(adpt);
705
706 kfree(tx_q->tpd.tpbuff);
707 tx_q->tpd.tpbuff = NULL;
708 tx_q->tpd.v_addr = NULL;
709 tx_q->tpd.dma_addr = 0;
710 tx_q->tpd.size = 0;
711}
712
713/* Allocate TX descriptor ring for the given transmit queue */
714static int emac_tx_q_desc_alloc(struct emac_adapter *adpt,
715 struct emac_tx_queue *tx_q)
716{
717 struct emac_ring_header *ring_header = &adpt->ring_header;
718 size_t size;
719
720 size = sizeof(struct emac_buffer) * tx_q->tpd.count;
721 tx_q->tpd.tpbuff = kzalloc(size, GFP_KERNEL);
722 if (!tx_q->tpd.tpbuff)
723 return -ENOMEM;
724
725 tx_q->tpd.size = tx_q->tpd.count * (adpt->tpd_size * 4);
726 tx_q->tpd.dma_addr = ring_header->dma_addr + ring_header->used;
727 tx_q->tpd.v_addr = ring_header->v_addr + ring_header->used;
728 ring_header->used += ALIGN(tx_q->tpd.size, 8);
729 tx_q->tpd.produce_idx = 0;
730 tx_q->tpd.consume_idx = 0;
731
732 return 0;
733}
734
735/* Free all buffers associated with given transmit queue */
736static void emac_rx_q_bufs_free(struct emac_adapter *adpt)
737{
738 struct emac_rx_queue *rx_q = &adpt->rx_q;
739
740 emac_rx_q_free_descs(adpt);
741
742 kfree(rx_q->rfd.rfbuff);
743 rx_q->rfd.rfbuff = NULL;
744
745 rx_q->rfd.v_addr = NULL;
746 rx_q->rfd.dma_addr = 0;
747 rx_q->rfd.size = 0;
748
749 rx_q->rrd.v_addr = NULL;
750 rx_q->rrd.dma_addr = 0;
751 rx_q->rrd.size = 0;
752}
753
754/* Allocate RX descriptor rings for the given receive queue */
755static int emac_rx_descs_alloc(struct emac_adapter *adpt)
756{
757 struct emac_ring_header *ring_header = &adpt->ring_header;
758 struct emac_rx_queue *rx_q = &adpt->rx_q;
759 size_t size;
760
761 size = sizeof(struct emac_buffer) * rx_q->rfd.count;
762 rx_q->rfd.rfbuff = kzalloc(size, GFP_KERNEL);
763 if (!rx_q->rfd.rfbuff)
764 return -ENOMEM;
765
766 rx_q->rrd.size = rx_q->rrd.count * (adpt->rrd_size * 4);
767 rx_q->rfd.size = rx_q->rfd.count * (adpt->rfd_size * 4);
768
769 rx_q->rrd.dma_addr = ring_header->dma_addr + ring_header->used;
770 rx_q->rrd.v_addr = ring_header->v_addr + ring_header->used;
771 ring_header->used += ALIGN(rx_q->rrd.size, 8);
772
773 rx_q->rfd.dma_addr = ring_header->dma_addr + ring_header->used;
774 rx_q->rfd.v_addr = ring_header->v_addr + ring_header->used;
775 ring_header->used += ALIGN(rx_q->rfd.size, 8);
776
777 rx_q->rrd.produce_idx = 0;
778 rx_q->rrd.consume_idx = 0;
779
780 rx_q->rfd.produce_idx = 0;
781 rx_q->rfd.consume_idx = 0;
782
783 return 0;
784}
785
786/* Allocate all TX and RX descriptor rings */
787int emac_mac_rx_tx_rings_alloc_all(struct emac_adapter *adpt)
788{
789 struct emac_ring_header *ring_header = &adpt->ring_header;
790 struct device *dev = adpt->netdev->dev.parent;
791 unsigned int num_tx_descs = adpt->tx_desc_cnt;
792 unsigned int num_rx_descs = adpt->rx_desc_cnt;
793 int ret;
794
795 adpt->tx_q.tpd.count = adpt->tx_desc_cnt;
796
797 adpt->rx_q.rrd.count = adpt->rx_desc_cnt;
798 adpt->rx_q.rfd.count = adpt->rx_desc_cnt;
799
800 /* Ring DMA buffer. Each ring may need up to 8 bytes for alignment,
801 * hence the additional padding bytes are allocated.
802 */
803 ring_header->size = num_tx_descs * (adpt->tpd_size * 4) +
804 num_rx_descs * (adpt->rfd_size * 4) +
805 num_rx_descs * (adpt->rrd_size * 4) +
806 8 + 2 * 8; /* 8 byte per one Tx and two Rx rings */
807
808 ring_header->used = 0;
809 ring_header->v_addr = dma_zalloc_coherent(dev, ring_header->size,
810 &ring_header->dma_addr,
811 GFP_KERNEL);
812 if (!ring_header->v_addr)
813 return -ENOMEM;
814
815 ring_header->used = ALIGN(ring_header->dma_addr, 8) -
816 ring_header->dma_addr;
817
818 ret = emac_tx_q_desc_alloc(adpt, &adpt->tx_q);
819 if (ret) {
820 netdev_err(adpt->netdev, "error: Tx Queue alloc failed\n");
821 goto err_alloc_tx;
822 }
823
824 ret = emac_rx_descs_alloc(adpt);
825 if (ret) {
826 netdev_err(adpt->netdev, "error: Rx Queue alloc failed\n");
827 goto err_alloc_rx;
828 }
829
830 return 0;
831
832err_alloc_rx:
833 emac_tx_q_bufs_free(adpt);
834err_alloc_tx:
835 dma_free_coherent(dev, ring_header->size,
836 ring_header->v_addr, ring_header->dma_addr);
837
838 ring_header->v_addr = NULL;
839 ring_header->dma_addr = 0;
840 ring_header->size = 0;
841 ring_header->used = 0;
842
843 return ret;
844}
845
846/* Free all TX and RX descriptor rings */
847void emac_mac_rx_tx_rings_free_all(struct emac_adapter *adpt)
848{
849 struct emac_ring_header *ring_header = &adpt->ring_header;
850 struct device *dev = adpt->netdev->dev.parent;
851
852 emac_tx_q_bufs_free(adpt);
853 emac_rx_q_bufs_free(adpt);
854
855 dma_free_coherent(dev, ring_header->size,
856 ring_header->v_addr, ring_header->dma_addr);
857
858 ring_header->v_addr = NULL;
859 ring_header->dma_addr = 0;
860 ring_header->size = 0;
861 ring_header->used = 0;
862}
863
864/* Initialize descriptor rings */
865static void emac_mac_rx_tx_ring_reset_all(struct emac_adapter *adpt)
866{
867 unsigned int i;
868
869 adpt->tx_q.tpd.produce_idx = 0;
870 adpt->tx_q.tpd.consume_idx = 0;
871 for (i = 0; i < adpt->tx_q.tpd.count; i++)
872 adpt->tx_q.tpd.tpbuff[i].dma_addr = 0;
873
874 adpt->rx_q.rrd.produce_idx = 0;
875 adpt->rx_q.rrd.consume_idx = 0;
876 adpt->rx_q.rfd.produce_idx = 0;
877 adpt->rx_q.rfd.consume_idx = 0;
878 for (i = 0; i < adpt->rx_q.rfd.count; i++)
879 adpt->rx_q.rfd.rfbuff[i].dma_addr = 0;
880}
881
882/* Produce new receive free descriptor */
883static void emac_mac_rx_rfd_create(struct emac_adapter *adpt,
884 struct emac_rx_queue *rx_q,
885 dma_addr_t addr)
886{
887 u32 *hw_rfd = EMAC_RFD(rx_q, adpt->rfd_size, rx_q->rfd.produce_idx);
888
889 *(hw_rfd++) = lower_32_bits(addr);
890 *hw_rfd = upper_32_bits(addr);
891
892 if (++rx_q->rfd.produce_idx == rx_q->rfd.count)
893 rx_q->rfd.produce_idx = 0;
894}
895
896/* Fill up receive queue's RFD with preallocated receive buffers */
897static void emac_mac_rx_descs_refill(struct emac_adapter *adpt,
898 struct emac_rx_queue *rx_q)
899{
900 struct emac_buffer *curr_rxbuf;
901 struct emac_buffer *next_rxbuf;
902 unsigned int count = 0;
903 u32 next_produce_idx;
904
905 next_produce_idx = rx_q->rfd.produce_idx + 1;
906 if (next_produce_idx == rx_q->rfd.count)
907 next_produce_idx = 0;
908
909 curr_rxbuf = GET_RFD_BUFFER(rx_q, rx_q->rfd.produce_idx);
910 next_rxbuf = GET_RFD_BUFFER(rx_q, next_produce_idx);
911
912 /* this always has a blank rx_buffer*/
913 while (!next_rxbuf->dma_addr) {
914 struct sk_buff *skb;
915 int ret;
916
917 skb = netdev_alloc_skb_ip_align(adpt->netdev, adpt->rxbuf_size);
918 if (!skb)
919 break;
920
921 curr_rxbuf->dma_addr =
922 dma_map_single(adpt->netdev->dev.parent, skb->data,
923 curr_rxbuf->length, DMA_FROM_DEVICE);
924 ret = dma_mapping_error(adpt->netdev->dev.parent,
925 curr_rxbuf->dma_addr);
926 if (ret) {
927 dev_kfree_skb(skb);
928 break;
929 }
930 curr_rxbuf->skb = skb;
931 curr_rxbuf->length = adpt->rxbuf_size;
932
933 emac_mac_rx_rfd_create(adpt, rx_q, curr_rxbuf->dma_addr);
934 next_produce_idx = rx_q->rfd.produce_idx + 1;
935 if (next_produce_idx == rx_q->rfd.count)
936 next_produce_idx = 0;
937
938 curr_rxbuf = GET_RFD_BUFFER(rx_q, rx_q->rfd.produce_idx);
939 next_rxbuf = GET_RFD_BUFFER(rx_q, next_produce_idx);
940 count++;
941 }
942
943 if (count) {
944 u32 prod_idx = (rx_q->rfd.produce_idx << rx_q->produce_shift) &
945 rx_q->produce_mask;
946 emac_reg_update32(adpt->base + rx_q->produce_reg,
947 rx_q->produce_mask, prod_idx);
948 }
949}
950
951static void emac_adjust_link(struct net_device *netdev)
952{
953 struct emac_adapter *adpt = netdev_priv(netdev);
fd0e97b8 954 struct emac_sgmii *sgmii = &adpt->phy;
b9b17deb
TT		 955 struct phy_device *phydev = netdev->phydev;
956
fd0e97b8 957 if (phydev->link) {
b9b17deb 958 emac_mac_start(adpt);
fd0e97b8
TT		 959 sgmii->link_up(adpt);
960 } else {
961 sgmii->link_down(adpt);
b9b17deb 962 emac_mac_stop(adpt);
fd0e97b8 963 }
b9b17deb
TT		 964
965 phy_print_status(phydev);
966}
967
968/* Bringup the interface/HW */
969int emac_mac_up(struct emac_adapter *adpt)
970{
971 struct net_device *netdev = adpt->netdev;
b9b17deb
TT		 972 int ret;
973
974 emac_mac_rx_tx_ring_reset_all(adpt);
975 emac_mac_config(adpt);
b9b17deb
TT		 976 emac_mac_rx_descs_refill(adpt, &adpt->rx_q);
977
9da34f27 978 adpt->phydev->irq = PHY_IGNORE_INTERRUPT;
b9b17deb
TT		 979 ret = phy_connect_direct(netdev, adpt->phydev, emac_adjust_link,
980 PHY_INTERFACE_MODE_SGMII);
981 if (ret) {
982 netdev_err(adpt->netdev, "could not connect phy\n");
b9b17deb
TT		 983 return ret;
984 }
985
9da34f27
TT		 986 phy_attached_print(adpt->phydev, NULL);
987
b9b17deb
TT		 988 /* enable mac irq */
989 writel((u32)~DIS_INT, adpt->base + EMAC_INT_STATUS);
990 writel(adpt->irq.mask, adpt->base + EMAC_INT_MASK);
991
b9b17deb
TT		 992 phy_start(adpt->phydev);
993
994 napi_enable(&adpt->rx_q.napi);
995 netif_start_queue(netdev);
996
997 return 0;
998}
999
1000/* Bring down the interface/HW */
1001void emac_mac_down(struct emac_adapter *adpt)
1002{
1003 struct net_device *netdev = adpt->netdev;
1004
1005 netif_stop_queue(netdev);
1006 napi_disable(&adpt->rx_q.napi);
1007
1008 phy_stop(adpt->phydev);
b9b17deb 1009
93966b71
TT		 1010 /* Interrupts must be disabled before the PHY is disconnected, to
1011 * avoid a race condition where adjust_link is null when we get
1012 * an interrupt.
1013 */
b9b17deb
TT		 1014 writel(DIS_INT, adpt->base + EMAC_INT_STATUS);
1015 writel(0, adpt->base + EMAC_INT_MASK);
1016 synchronize_irq(adpt->irq.irq);
b9b17deb 1017
93966b71
TT		 1018 phy_disconnect(adpt->phydev);
1019
b9b17deb
TT		 1020 emac_mac_reset(adpt);
1021
1022 emac_tx_q_descs_free(adpt);
1023 netdev_reset_queue(adpt->netdev);
1024 emac_rx_q_free_descs(adpt);
1025}
1026
1027/* Consume next received packet descriptor */
1028static bool emac_rx_process_rrd(struct emac_adapter *adpt,
1029 struct emac_rx_queue *rx_q,
1030 struct emac_rrd *rrd)
1031{
1032 u32 *hw_rrd = EMAC_RRD(rx_q, adpt->rrd_size, rx_q->rrd.consume_idx);
1033
1034 rrd->word[3] = *(hw_rrd + 3);
1035
1036 if (!RRD_UPDT(rrd))
1037 return false;
1038
1039 rrd->word[4] = 0;
1040 rrd->word[5] = 0;
1041
1042 rrd->word[0] = *(hw_rrd++);
1043 rrd->word[1] = *(hw_rrd++);
1044 rrd->word[2] = *(hw_rrd++);
1045
1046 if (unlikely(RRD_NOR(rrd) != 1)) {
1047 netdev_err(adpt->netdev,
1048 "error: multi-RFD not support yet! nor:%lu\n",
1049 RRD_NOR(rrd));
1050 }
1051
1052 /* mark rrd as processed */
1053 RRD_UPDT_SET(rrd, 0);
1054 *hw_rrd = rrd->word[3];
1055
1056 if (++rx_q->rrd.consume_idx == rx_q->rrd.count)
1057 rx_q->rrd.consume_idx = 0;
1058
1059 return true;
1060}
1061
1062/* Produce new transmit descriptor */
1063static void emac_tx_tpd_create(struct emac_adapter *adpt,
1064 struct emac_tx_queue *tx_q, struct emac_tpd *tpd)
1065{
1066 u32 *hw_tpd;
1067
1068 tx_q->tpd.last_produce_idx = tx_q->tpd.produce_idx;
1069 hw_tpd = EMAC_TPD(tx_q, adpt->tpd_size, tx_q->tpd.produce_idx);
1070
1071 if (++tx_q->tpd.produce_idx == tx_q->tpd.count)
1072 tx_q->tpd.produce_idx = 0;
1073
1074 *(hw_tpd++) = tpd->word[0];
1075 *(hw_tpd++) = tpd->word[1];
1076 *(hw_tpd++) = tpd->word[2];
1077 *hw_tpd = tpd->word[3];
1078}
1079
1080/* Mark the last transmit descriptor as such (for the transmit packet) */
1081static void emac_tx_tpd_mark_last(struct emac_adapter *adpt,
1082 struct emac_tx_queue *tx_q)
1083{
1084 u32 *hw_tpd =
1085 EMAC_TPD(tx_q, adpt->tpd_size, tx_q->tpd.last_produce_idx);
1086 u32 tmp_tpd;
1087
1088 tmp_tpd = *(hw_tpd + 1);
1089 tmp_tpd |= EMAC_TPD_LAST_FRAGMENT;
1090 *(hw_tpd + 1) = tmp_tpd;
1091}
1092
1093static void emac_rx_rfd_clean(struct emac_rx_queue *rx_q, struct emac_rrd *rrd)
1094{
1095 struct emac_buffer *rfbuf = rx_q->rfd.rfbuff;
1096 u32 consume_idx = RRD_SI(rrd);
1097 unsigned int i;
1098
1099 for (i = 0; i < RRD_NOR(rrd); i++) {
1100 rfbuf[consume_idx].skb = NULL;
1101 if (++consume_idx == rx_q->rfd.count)
1102 consume_idx = 0;
1103 }
1104
1105 rx_q->rfd.consume_idx = consume_idx;
1106 rx_q->rfd.process_idx = consume_idx;
1107}
1108
1109/* Push the received skb to upper layers */
1110static void emac_receive_skb(struct emac_rx_queue *rx_q,
1111 struct sk_buff *skb,
1112 u16 vlan_tag, bool vlan_flag)
1113{
1114 if (vlan_flag) {
1115 u16 vlan;
1116
1117 EMAC_TAG_TO_VLAN(vlan_tag, vlan);
1118 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan);
1119 }
1120
1121 napi_gro_receive(&rx_q->napi, skb);
1122}
1123
1124/* Process receive event */
1125void emac_mac_rx_process(struct emac_adapter *adpt, struct emac_rx_queue *rx_q,
1126 int *num_pkts, int max_pkts)
1127{
1128 u32 proc_idx, hw_consume_idx, num_consume_pkts;
1129 struct net_device *netdev = adpt->netdev;
1130 struct emac_buffer *rfbuf;
1131 unsigned int count = 0;
1132 struct emac_rrd rrd;
1133 struct sk_buff *skb;
1134 u32 reg;
1135
1136 reg = readl_relaxed(adpt->base + rx_q->consume_reg);
1137
1138 hw_consume_idx = (reg & rx_q->consume_mask) >> rx_q->consume_shift;
1139 num_consume_pkts = (hw_consume_idx >= rx_q->rrd.consume_idx) ?
1140 (hw_consume_idx - rx_q->rrd.consume_idx) :
1141 (hw_consume_idx + rx_q->rrd.count - rx_q->rrd.consume_idx);
1142
1143 do {
1144 if (!num_consume_pkts)
1145 break;
1146
1147 if (!emac_rx_process_rrd(adpt, rx_q, &rrd))
1148 break;
1149
1150 if (likely(RRD_NOR(&rrd) == 1)) {
1151 /* good receive */
1152 rfbuf = GET_RFD_BUFFER(rx_q, RRD_SI(&rrd));
1153 dma_unmap_single(adpt->netdev->dev.parent,
1154 rfbuf->dma_addr, rfbuf->length,
1155 DMA_FROM_DEVICE);
1156 rfbuf->dma_addr = 0;
1157 skb = rfbuf->skb;
1158 } else {
1159 netdev_err(adpt->netdev,
1160 "error: multi-RFD not support yet!\n");
1161 break;
1162 }
1163 emac_rx_rfd_clean(rx_q, &rrd);
1164 num_consume_pkts--;
1165 count++;
1166
1167 /* Due to a HW issue in L4 check sum detection (UDP/TCP frags
1168 * with DF set are marked as error), drop packets based on the
1169 * error mask rather than the summary bit (ignoring L4F errors)
1170 */
1171 if (rrd.word[EMAC_RRD_STATS_DW_IDX] & EMAC_RRD_ERROR) {
1172 netif_dbg(adpt, rx_status, adpt->netdev,
1173 "Drop error packet[RRD: 0x%x:0x%x:0x%x:0x%x]\n",
1174 rrd.word[0], rrd.word[1],
1175 rrd.word[2], rrd.word[3]);
1176
1177 dev_kfree_skb(skb);
1178 continue;
1179 }
1180
1181 skb_put(skb, RRD_PKT_SIZE(&rrd) - ETH_FCS_LEN);
1182 skb->dev = netdev;
1183 skb->protocol = eth_type_trans(skb, skb->dev);
1184 if (netdev->features & NETIF_F_RXCSUM)
1185 skb->ip_summed = RRD_L4F(&rrd) ?
1186 CHECKSUM_NONE : CHECKSUM_UNNECESSARY;
1187 else
1188 skb_checksum_none_assert(skb);
1189
1190 emac_receive_skb(rx_q, skb, (u16)RRD_CVALN_TAG(&rrd),
1191 (bool)RRD_CVTAG(&rrd));
1192
b9b17deb
TT		 1193 (*num_pkts)++;
1194 } while (*num_pkts < max_pkts);
1195
1196 if (count) {
1197 proc_idx = (rx_q->rfd.process_idx << rx_q->process_shft) &
1198 rx_q->process_mask;
1199 emac_reg_update32(adpt->base + rx_q->process_reg,
1200 rx_q->process_mask, proc_idx);
1201 emac_mac_rx_descs_refill(adpt, rx_q);
1202 }
1203}
1204
1205/* get the number of free transmit descriptors */
1206static unsigned int emac_tpd_num_free_descs(struct emac_tx_queue *tx_q)
1207{
1208 u32 produce_idx = tx_q->tpd.produce_idx;
1209 u32 consume_idx = tx_q->tpd.consume_idx;
1210
1211 return (consume_idx > produce_idx) ?
1212 (consume_idx - produce_idx - 1) :
1213 (tx_q->tpd.count + consume_idx - produce_idx - 1);
1214}
1215
1216/* Process transmit event */
1217void emac_mac_tx_process(struct emac_adapter *adpt, struct emac_tx_queue *tx_q)
1218{
1219 u32 reg = readl_relaxed(adpt->base + tx_q->consume_reg);
1220 u32 hw_consume_idx, pkts_compl = 0, bytes_compl = 0;
1221 struct emac_buffer *tpbuf;
1222
1223 hw_consume_idx = (reg & tx_q->consume_mask) >> tx_q->consume_shift;
1224
1225 while (tx_q->tpd.consume_idx != hw_consume_idx) {
1226 tpbuf = GET_TPD_BUFFER(tx_q, tx_q->tpd.consume_idx);
1227 if (tpbuf->dma_addr) {
1228 dma_unmap_single(adpt->netdev->dev.parent,
1229 tpbuf->dma_addr, tpbuf->length,
1230 DMA_TO_DEVICE);
1231 tpbuf->dma_addr = 0;
1232 }
1233
1234 if (tpbuf->skb) {
1235 pkts_compl++;
1236 bytes_compl += tpbuf->skb->len;
1237 dev_kfree_skb_irq(tpbuf->skb);
1238 tpbuf->skb = NULL;
1239 }
1240
1241 if (++tx_q->tpd.consume_idx == tx_q->tpd.count)
1242 tx_q->tpd.consume_idx = 0;
1243 }
1244
1245 netdev_completed_queue(adpt->netdev, pkts_compl, bytes_compl);
1246
1247 if (netif_queue_stopped(adpt->netdev))
1248 if (emac_tpd_num_free_descs(tx_q) > (MAX_SKB_FRAGS + 1))
1249 netif_wake_queue(adpt->netdev);
1250}
1251
1252/* Initialize all queue data structures */
1253void emac_mac_rx_tx_ring_init_all(struct platform_device *pdev,
1254 struct emac_adapter *adpt)
1255{
1256 adpt->rx_q.netdev = adpt->netdev;
1257
1258 adpt->rx_q.produce_reg = EMAC_MAILBOX_0;
1259 adpt->rx_q.produce_mask = RFD0_PROD_IDX_BMSK;
1260 adpt->rx_q.produce_shift = RFD0_PROD_IDX_SHFT;
1261
1262 adpt->rx_q.process_reg = EMAC_MAILBOX_0;
1263 adpt->rx_q.process_mask = RFD0_PROC_IDX_BMSK;
1264 adpt->rx_q.process_shft = RFD0_PROC_IDX_SHFT;
1265
1266 adpt->rx_q.consume_reg = EMAC_MAILBOX_3;
1267 adpt->rx_q.consume_mask = RFD0_CONS_IDX_BMSK;
1268 adpt->rx_q.consume_shift = RFD0_CONS_IDX_SHFT;
1269
1270 adpt->rx_q.irq = &adpt->irq;
1271 adpt->rx_q.intr = adpt->irq.mask & ISR_RX_PKT;
1272
1273 adpt->tx_q.produce_reg = EMAC_MAILBOX_15;
1274 adpt->tx_q.produce_mask = NTPD_PROD_IDX_BMSK;
1275 adpt->tx_q.produce_shift = NTPD_PROD_IDX_SHFT;
1276
1277 adpt->tx_q.consume_reg = EMAC_MAILBOX_2;
1278 adpt->tx_q.consume_mask = NTPD_CONS_IDX_BMSK;
1279 adpt->tx_q.consume_shift = NTPD_CONS_IDX_SHFT;
1280}
1281
1282/* Fill up transmit descriptors with TSO and Checksum offload information */
1283static int emac_tso_csum(struct emac_adapter *adpt,
1284 struct emac_tx_queue *tx_q,
1285 struct sk_buff *skb,
1286 struct emac_tpd *tpd)
1287{
1288 unsigned int hdr_len;
1289 int ret;
1290
1291 if (skb_is_gso(skb)) {
1292 if (skb_header_cloned(skb)) {
1293 ret = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
1294 if (unlikely(ret))
1295 return ret;
1296 }
1297
1298 if (skb->protocol == htons(ETH_P_IP)) {
1299 u32 pkt_len = ((unsigned char *)ip_hdr(skb) - skb->data)
1300 + ntohs(ip_hdr(skb)->tot_len);
1301 if (skb->len > pkt_len)
1302 pskb_trim(skb, pkt_len);
1303 }
1304
1305 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
1306 if (unlikely(skb->len == hdr_len)) {
1307 /* we only need to do csum */
1308 netif_warn(adpt, tx_err, adpt->netdev,
1309 "tso not needed for packet with 0 data\n");
1310 goto do_csum;
1311 }
1312
1313 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4) {
1314 ip_hdr(skb)->check = 0;
1315 tcp_hdr(skb)->check =
1316 ~csum_tcpudp_magic(ip_hdr(skb)->saddr,
1317 ip_hdr(skb)->daddr,
1318 0, IPPROTO_TCP, 0);
1319 TPD_IPV4_SET(tpd, 1);
1320 }
1321
1322 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
1323 /* ipv6 tso need an extra tpd */
1324 struct emac_tpd extra_tpd;
1325
1326 memset(tpd, 0, sizeof(*tpd));
1327 memset(&extra_tpd, 0, sizeof(extra_tpd));
1328
1329 ipv6_hdr(skb)->payload_len = 0;
1330 tcp_hdr(skb)->check =
1331 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
1332 &ipv6_hdr(skb)->daddr,
1333 0, IPPROTO_TCP, 0);
1334 TPD_PKT_LEN_SET(&extra_tpd, skb->len);
1335 TPD_LSO_SET(&extra_tpd, 1);
1336 TPD_LSOV_SET(&extra_tpd, 1);
1337 emac_tx_tpd_create(adpt, tx_q, &extra_tpd);
1338 TPD_LSOV_SET(tpd, 1);
1339 }
1340
1341 TPD_LSO_SET(tpd, 1);
1342 TPD_TCPHDR_OFFSET_SET(tpd, skb_transport_offset(skb));
1343 TPD_MSS_SET(tpd, skb_shinfo(skb)->gso_size);
1344 return 0;
1345 }
1346
1347do_csum:
1348 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
1349 unsigned int css, cso;
1350
1351 cso = skb_transport_offset(skb);
1352 if (unlikely(cso & 0x1)) {
1353 netdev_err(adpt->netdev,
1354 "error: payload offset should be even\n");
1355 return -EINVAL;
1356 }
1357 css = cso + skb->csum_offset;
1358
1359 TPD_PAYLOAD_OFFSET_SET(tpd, cso >> 1);
1360 TPD_CXSUM_OFFSET_SET(tpd, css >> 1);
1361 TPD_CSX_SET(tpd, 1);
1362 }
1363
1364 return 0;
1365}
1366
1367/* Fill up transmit descriptors */
1368static void emac_tx_fill_tpd(struct emac_adapter *adpt,
1369 struct emac_tx_queue *tx_q, struct sk_buff *skb,
1370 struct emac_tpd *tpd)
1371{
1372 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
1373 unsigned int first = tx_q->tpd.produce_idx;
1374 unsigned int len = skb_headlen(skb);
1375 struct emac_buffer *tpbuf = NULL;
1376 unsigned int mapped_len = 0;
1377 unsigned int i;
1378 int count = 0;
1379 int ret;
1380
1381 /* if Large Segment Offload is (in TCP Segmentation Offload struct) */
1382 if (TPD_LSO(tpd)) {
1383 mapped_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
1384
1385 tpbuf = GET_TPD_BUFFER(tx_q, tx_q->tpd.produce_idx);
1386 tpbuf->length = mapped_len;
1387 tpbuf->dma_addr = dma_map_single(adpt->netdev->dev.parent,
1388 skb->data, tpbuf->length,
1389 DMA_TO_DEVICE);
1390 ret = dma_mapping_error(adpt->netdev->dev.parent,
1391 tpbuf->dma_addr);
1392 if (ret)
1393 goto error;
1394
1395 TPD_BUFFER_ADDR_L_SET(tpd, lower_32_bits(tpbuf->dma_addr));
1396 TPD_BUFFER_ADDR_H_SET(tpd, upper_32_bits(tpbuf->dma_addr));
1397 TPD_BUF_LEN_SET(tpd, tpbuf->length);
1398 emac_tx_tpd_create(adpt, tx_q, tpd);
1399 count++;
1400 }
1401
1402 if (mapped_len < len) {
1403 tpbuf = GET_TPD_BUFFER(tx_q, tx_q->tpd.produce_idx);
1404 tpbuf->length = len - mapped_len;
1405 tpbuf->dma_addr = dma_map_single(adpt->netdev->dev.parent,
1406 skb->data + mapped_len,
1407 tpbuf->length, DMA_TO_DEVICE);
1408 ret = dma_mapping_error(adpt->netdev->dev.parent,
1409 tpbuf->dma_addr);
1410 if (ret)
1411 goto error;
1412
1413 TPD_BUFFER_ADDR_L_SET(tpd, lower_32_bits(tpbuf->dma_addr));
1414 TPD_BUFFER_ADDR_H_SET(tpd, upper_32_bits(tpbuf->dma_addr));
1415 TPD_BUF_LEN_SET(tpd, tpbuf->length);
1416 emac_tx_tpd_create(adpt, tx_q, tpd);
1417 count++;
1418 }
1419
1420 for (i = 0; i < nr_frags; i++) {
1421 struct skb_frag_struct *frag;
1422
1423 frag = &skb_shinfo(skb)->frags[i];
1424
1425 tpbuf = GET_TPD_BUFFER(tx_q, tx_q->tpd.produce_idx);
1426 tpbuf->length = frag->size;
1427 tpbuf->dma_addr = dma_map_page(adpt->netdev->dev.parent,
1428 frag->page.p, frag->page_offset,
1429 tpbuf->length, DMA_TO_DEVICE);
1430 ret = dma_mapping_error(adpt->netdev->dev.parent,
1431 tpbuf->dma_addr);
1432 if (ret)
1433 goto error;
1434
1435 TPD_BUFFER_ADDR_L_SET(tpd, lower_32_bits(tpbuf->dma_addr));
1436 TPD_BUFFER_ADDR_H_SET(tpd, upper_32_bits(tpbuf->dma_addr));
1437 TPD_BUF_LEN_SET(tpd, tpbuf->length);
1438 emac_tx_tpd_create(adpt, tx_q, tpd);
1439 count++;
1440 }
1441
1442 /* The last tpd */
1443 wmb();
1444 emac_tx_tpd_mark_last(adpt, tx_q);
1445
1446 /* The last buffer info contain the skb address,
1447 * so it will be freed after unmap
1448 */
1449 tpbuf->skb = skb;
1450
1451 return;
1452
1453error:
1454 /* One of the memory mappings failed, so undo everything */
1455 tx_q->tpd.produce_idx = first;
1456
1457 while (count--) {
1458 tpbuf = GET_TPD_BUFFER(tx_q, first);
1459 dma_unmap_page(adpt->netdev->dev.parent, tpbuf->dma_addr,
1460 tpbuf->length, DMA_TO_DEVICE);
1461 tpbuf->dma_addr = 0;
1462 tpbuf->length = 0;
1463
1464 if (++first == tx_q->tpd.count)
1465 first = 0;
1466 }
1467
1468 dev_kfree_skb(skb);
1469}
1470
1471/* Transmit the packet using specified transmit queue */
1472int emac_mac_tx_buf_send(struct emac_adapter *adpt, struct emac_tx_queue *tx_q,
1473 struct sk_buff *skb)
1474{
1475 struct emac_tpd tpd;
1476 u32 prod_idx;
1477
1478 memset(&tpd, 0, sizeof(tpd));
1479
1480 if (emac_tso_csum(adpt, tx_q, skb, &tpd) != 0) {
1481 dev_kfree_skb_any(skb);
1482 return NETDEV_TX_OK;
1483 }
1484
1485 if (skb_vlan_tag_present(skb)) {
1486 u16 tag;
1487
1488 EMAC_VLAN_TO_TAG(skb_vlan_tag_get(skb), tag);
1489 TPD_CVLAN_TAG_SET(&tpd, tag);
1490 TPD_INSTC_SET(&tpd, 1);
1491 }
1492
1493 if (skb_network_offset(skb) != ETH_HLEN)
1494 TPD_TYP_SET(&tpd, 1);
1495
1496 emac_tx_fill_tpd(adpt, tx_q, skb, &tpd);
1497
1498 netdev_sent_queue(adpt->netdev, skb->len);
1499
1500 /* Make sure the are enough free descriptors to hold one
1501 * maximum-sized SKB. We need one desc for each fragment,
1502 * one for the checksum (emac_tso_csum), one for TSO, and
1503 * and one for the SKB header.
1504 */
1505 if (emac_tpd_num_free_descs(tx_q) < (MAX_SKB_FRAGS + 3))
1506 netif_stop_queue(adpt->netdev);
1507
1508 /* update produce idx */
1509 prod_idx = (tx_q->tpd.produce_idx << tx_q->produce_shift) &
1510 tx_q->produce_mask;
1511 emac_reg_update32(adpt->base + tx_q->produce_reg,
1512 tx_q->produce_mask, prod_idx);
1513
1514 return NETDEV_TX_OK;
1515}
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