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b9b17deb TT |
1 | /* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. |
2 | * | |
3 | * This program is free software; you can redistribute it and/or modify | |
4 | * it under the terms of the GNU General Public License version 2 and | |
5 | * only version 2 as published by the Free Software Foundation. | |
6 | * | |
7 | * This program is distributed in the hope that it will be useful, | |
8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
10 | * GNU General Public License for more details. | |
11 | */ | |
12 | ||
13 | /* Qualcomm Technologies, Inc. EMAC Gigabit Ethernet Driver */ | |
14 | ||
15 | #include <linux/if_ether.h> | |
16 | #include <linux/if_vlan.h> | |
17 | #include <linux/interrupt.h> | |
18 | #include <linux/io.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/of.h> | |
21 | #include <linux/of_net.h> | |
22 | #include <linux/of_device.h> | |
23 | #include <linux/phy.h> | |
24 | #include <linux/platform_device.h> | |
5f3d3807 | 25 | #include <linux/acpi.h> |
b9b17deb TT |
26 | #include "emac.h" |
27 | #include "emac-mac.h" | |
28 | #include "emac-phy.h" | |
29 | #include "emac-sgmii.h" | |
30 | ||
31 | #define EMAC_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \ | |
32 | NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP) | |
33 | ||
34 | #define EMAC_RRD_SIZE 4 | |
35 | /* The RRD size if timestamping is enabled: */ | |
36 | #define EMAC_TS_RRD_SIZE 6 | |
37 | #define EMAC_TPD_SIZE 4 | |
38 | #define EMAC_RFD_SIZE 2 | |
39 | ||
40 | #define REG_MAC_RX_STATUS_BIN EMAC_RXMAC_STATC_REG0 | |
41 | #define REG_MAC_RX_STATUS_END EMAC_RXMAC_STATC_REG22 | |
42 | #define REG_MAC_TX_STATUS_BIN EMAC_TXMAC_STATC_REG0 | |
43 | #define REG_MAC_TX_STATUS_END EMAC_TXMAC_STATC_REG24 | |
44 | ||
45 | #define RXQ0_NUM_RFD_PREF_DEF 8 | |
46 | #define TXQ0_NUM_TPD_PREF_DEF 5 | |
47 | ||
48 | #define EMAC_PREAMBLE_DEF 7 | |
49 | ||
50 | #define DMAR_DLY_CNT_DEF 15 | |
51 | #define DMAW_DLY_CNT_DEF 4 | |
52 | ||
53 | #define IMR_NORMAL_MASK (\ | |
54 | ISR_ERROR |\ | |
55 | ISR_GPHY_LINK |\ | |
56 | ISR_TX_PKT |\ | |
57 | GPHY_WAKEUP_INT) | |
58 | ||
59 | #define IMR_EXTENDED_MASK (\ | |
60 | SW_MAN_INT |\ | |
61 | ISR_OVER |\ | |
62 | ISR_ERROR |\ | |
63 | ISR_GPHY_LINK |\ | |
64 | ISR_TX_PKT |\ | |
65 | GPHY_WAKEUP_INT) | |
66 | ||
67 | #define ISR_TX_PKT (\ | |
68 | TX_PKT_INT |\ | |
69 | TX_PKT_INT1 |\ | |
70 | TX_PKT_INT2 |\ | |
71 | TX_PKT_INT3) | |
72 | ||
73 | #define ISR_GPHY_LINK (\ | |
74 | GPHY_LINK_UP_INT |\ | |
75 | GPHY_LINK_DOWN_INT) | |
76 | ||
77 | #define ISR_OVER (\ | |
78 | RFD0_UR_INT |\ | |
79 | RFD1_UR_INT |\ | |
80 | RFD2_UR_INT |\ | |
81 | RFD3_UR_INT |\ | |
82 | RFD4_UR_INT |\ | |
83 | RXF_OF_INT |\ | |
84 | TXF_UR_INT) | |
85 | ||
86 | #define ISR_ERROR (\ | |
87 | DMAR_TO_INT |\ | |
88 | DMAW_TO_INT |\ | |
89 | TXQ_TO_INT) | |
90 | ||
91 | /* in sync with enum emac_clk_id */ | |
92 | static const char * const emac_clk_name[] = { | |
93 | "axi_clk", "cfg_ahb_clk", "high_speed_clk", "mdio_clk", "tx_clk", | |
94 | "rx_clk", "sys_clk" | |
95 | }; | |
96 | ||
97 | void emac_reg_update32(void __iomem *addr, u32 mask, u32 val) | |
98 | { | |
99 | u32 data = readl(addr); | |
100 | ||
101 | writel(((data & ~mask) | val), addr); | |
102 | } | |
103 | ||
104 | /* reinitialize */ | |
105 | int emac_reinit_locked(struct emac_adapter *adpt) | |
106 | { | |
107 | int ret; | |
108 | ||
109 | mutex_lock(&adpt->reset_lock); | |
110 | ||
111 | emac_mac_down(adpt); | |
112 | emac_sgmii_reset(adpt); | |
113 | ret = emac_mac_up(adpt); | |
114 | ||
115 | mutex_unlock(&adpt->reset_lock); | |
116 | ||
117 | return ret; | |
118 | } | |
119 | ||
120 | /* NAPI */ | |
121 | static int emac_napi_rtx(struct napi_struct *napi, int budget) | |
122 | { | |
123 | struct emac_rx_queue *rx_q = | |
124 | container_of(napi, struct emac_rx_queue, napi); | |
125 | struct emac_adapter *adpt = netdev_priv(rx_q->netdev); | |
126 | struct emac_irq *irq = rx_q->irq; | |
127 | int work_done = 0; | |
128 | ||
129 | emac_mac_rx_process(adpt, rx_q, &work_done, budget); | |
130 | ||
131 | if (work_done < budget) { | |
132 | napi_complete(napi); | |
133 | ||
134 | irq->mask |= rx_q->intr; | |
135 | writel(irq->mask, adpt->base + EMAC_INT_MASK); | |
136 | } | |
137 | ||
138 | return work_done; | |
139 | } | |
140 | ||
141 | /* Transmit the packet */ | |
142 | static int emac_start_xmit(struct sk_buff *skb, struct net_device *netdev) | |
143 | { | |
144 | struct emac_adapter *adpt = netdev_priv(netdev); | |
145 | ||
146 | return emac_mac_tx_buf_send(adpt, &adpt->tx_q, skb); | |
147 | } | |
148 | ||
149 | irqreturn_t emac_isr(int _irq, void *data) | |
150 | { | |
151 | struct emac_irq *irq = data; | |
152 | struct emac_adapter *adpt = | |
153 | container_of(irq, struct emac_adapter, irq); | |
154 | struct emac_rx_queue *rx_q = &adpt->rx_q; | |
155 | u32 isr, status; | |
156 | ||
157 | /* disable the interrupt */ | |
158 | writel(0, adpt->base + EMAC_INT_MASK); | |
159 | ||
160 | isr = readl_relaxed(adpt->base + EMAC_INT_STATUS); | |
161 | ||
162 | status = isr & irq->mask; | |
163 | if (status == 0) | |
164 | goto exit; | |
165 | ||
166 | if (status & ISR_ERROR) { | |
167 | netif_warn(adpt, intr, adpt->netdev, | |
168 | "warning: error irq status 0x%lx\n", | |
169 | status & ISR_ERROR); | |
170 | /* reset MAC */ | |
171 | schedule_work(&adpt->work_thread); | |
172 | } | |
173 | ||
174 | /* Schedule the napi for receive queue with interrupt | |
175 | * status bit set | |
176 | */ | |
177 | if (status & rx_q->intr) { | |
178 | if (napi_schedule_prep(&rx_q->napi)) { | |
179 | irq->mask &= ~rx_q->intr; | |
180 | __napi_schedule(&rx_q->napi); | |
181 | } | |
182 | } | |
183 | ||
184 | if (status & TX_PKT_INT) | |
185 | emac_mac_tx_process(adpt, &adpt->tx_q); | |
186 | ||
187 | if (status & ISR_OVER) | |
188 | net_warn_ratelimited("warning: TX/RX overflow\n"); | |
189 | ||
190 | /* link event */ | |
191 | if (status & ISR_GPHY_LINK) | |
192 | phy_mac_interrupt(adpt->phydev, !!(status & GPHY_LINK_UP_INT)); | |
193 | ||
194 | exit: | |
195 | /* enable the interrupt */ | |
196 | writel(irq->mask, adpt->base + EMAC_INT_MASK); | |
197 | ||
198 | return IRQ_HANDLED; | |
199 | } | |
200 | ||
201 | /* Configure VLAN tag strip/insert feature */ | |
202 | static int emac_set_features(struct net_device *netdev, | |
203 | netdev_features_t features) | |
204 | { | |
205 | netdev_features_t changed = features ^ netdev->features; | |
206 | struct emac_adapter *adpt = netdev_priv(netdev); | |
207 | ||
208 | /* We only need to reprogram the hardware if the VLAN tag features | |
209 | * have changed, and if it's already running. | |
210 | */ | |
211 | if (!(changed & (NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX))) | |
212 | return 0; | |
213 | ||
214 | if (!netif_running(netdev)) | |
215 | return 0; | |
216 | ||
217 | /* emac_mac_mode_config() uses netdev->features to configure the EMAC, | |
218 | * so make sure it's set first. | |
219 | */ | |
220 | netdev->features = features; | |
221 | ||
222 | return emac_reinit_locked(adpt); | |
223 | } | |
224 | ||
225 | /* Configure Multicast and Promiscuous modes */ | |
226 | static void emac_rx_mode_set(struct net_device *netdev) | |
227 | { | |
228 | struct emac_adapter *adpt = netdev_priv(netdev); | |
229 | struct netdev_hw_addr *ha; | |
230 | ||
231 | emac_mac_mode_config(adpt); | |
232 | ||
233 | /* update multicast address filtering */ | |
234 | emac_mac_multicast_addr_clear(adpt); | |
235 | netdev_for_each_mc_addr(ha, netdev) | |
236 | emac_mac_multicast_addr_set(adpt, ha->addr); | |
237 | } | |
238 | ||
239 | /* Change the Maximum Transfer Unit (MTU) */ | |
240 | static int emac_change_mtu(struct net_device *netdev, int new_mtu) | |
241 | { | |
b9b17deb TT |
242 | struct emac_adapter *adpt = netdev_priv(netdev); |
243 | ||
b9b17deb TT |
244 | netif_info(adpt, hw, adpt->netdev, |
245 | "changing MTU from %d to %d\n", netdev->mtu, | |
246 | new_mtu); | |
247 | netdev->mtu = new_mtu; | |
248 | ||
249 | if (netif_running(netdev)) | |
250 | return emac_reinit_locked(adpt); | |
251 | ||
252 | return 0; | |
253 | } | |
254 | ||
255 | /* Called when the network interface is made active */ | |
256 | static int emac_open(struct net_device *netdev) | |
257 | { | |
258 | struct emac_adapter *adpt = netdev_priv(netdev); | |
259 | int ret; | |
260 | ||
261 | /* allocate rx/tx dma buffer & descriptors */ | |
262 | ret = emac_mac_rx_tx_rings_alloc_all(adpt); | |
263 | if (ret) { | |
264 | netdev_err(adpt->netdev, "error allocating rx/tx rings\n"); | |
265 | return ret; | |
266 | } | |
267 | ||
268 | ret = emac_mac_up(adpt); | |
269 | if (ret) { | |
270 | emac_mac_rx_tx_rings_free_all(adpt); | |
271 | return ret; | |
272 | } | |
273 | ||
274 | emac_mac_start(adpt); | |
275 | ||
276 | return 0; | |
277 | } | |
278 | ||
279 | /* Called when the network interface is disabled */ | |
280 | static int emac_close(struct net_device *netdev) | |
281 | { | |
282 | struct emac_adapter *adpt = netdev_priv(netdev); | |
283 | ||
284 | mutex_lock(&adpt->reset_lock); | |
285 | ||
286 | emac_mac_down(adpt); | |
287 | emac_mac_rx_tx_rings_free_all(adpt); | |
288 | ||
289 | mutex_unlock(&adpt->reset_lock); | |
290 | ||
291 | return 0; | |
292 | } | |
293 | ||
294 | /* Respond to a TX hang */ | |
295 | static void emac_tx_timeout(struct net_device *netdev) | |
296 | { | |
297 | struct emac_adapter *adpt = netdev_priv(netdev); | |
298 | ||
299 | schedule_work(&adpt->work_thread); | |
300 | } | |
301 | ||
302 | /* IOCTL support for the interface */ | |
303 | static int emac_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) | |
304 | { | |
305 | if (!netif_running(netdev)) | |
306 | return -EINVAL; | |
307 | ||
308 | if (!netdev->phydev) | |
309 | return -ENODEV; | |
310 | ||
311 | return phy_mii_ioctl(netdev->phydev, ifr, cmd); | |
312 | } | |
313 | ||
314 | /* Provide network statistics info for the interface */ | |
315 | static struct rtnl_link_stats64 *emac_get_stats64(struct net_device *netdev, | |
316 | struct rtnl_link_stats64 *net_stats) | |
317 | { | |
318 | struct emac_adapter *adpt = netdev_priv(netdev); | |
319 | unsigned int addr = REG_MAC_RX_STATUS_BIN; | |
320 | struct emac_stats *stats = &adpt->stats; | |
321 | u64 *stats_itr = &adpt->stats.rx_ok; | |
322 | u32 val; | |
323 | ||
324 | spin_lock(&stats->lock); | |
325 | ||
326 | while (addr <= REG_MAC_RX_STATUS_END) { | |
327 | val = readl_relaxed(adpt->base + addr); | |
328 | *stats_itr += val; | |
329 | stats_itr++; | |
330 | addr += sizeof(u32); | |
331 | } | |
332 | ||
333 | /* additional rx status */ | |
334 | val = readl_relaxed(adpt->base + EMAC_RXMAC_STATC_REG23); | |
335 | adpt->stats.rx_crc_align += val; | |
336 | val = readl_relaxed(adpt->base + EMAC_RXMAC_STATC_REG24); | |
337 | adpt->stats.rx_jabbers += val; | |
338 | ||
339 | /* update tx status */ | |
340 | addr = REG_MAC_TX_STATUS_BIN; | |
341 | stats_itr = &adpt->stats.tx_ok; | |
342 | ||
343 | while (addr <= REG_MAC_TX_STATUS_END) { | |
344 | val = readl_relaxed(adpt->base + addr); | |
345 | *stats_itr += val; | |
346 | ++stats_itr; | |
347 | addr += sizeof(u32); | |
348 | } | |
349 | ||
350 | /* additional tx status */ | |
351 | val = readl_relaxed(adpt->base + EMAC_TXMAC_STATC_REG25); | |
352 | adpt->stats.tx_col += val; | |
353 | ||
354 | /* return parsed statistics */ | |
355 | net_stats->rx_packets = stats->rx_ok; | |
356 | net_stats->tx_packets = stats->tx_ok; | |
357 | net_stats->rx_bytes = stats->rx_byte_cnt; | |
358 | net_stats->tx_bytes = stats->tx_byte_cnt; | |
359 | net_stats->multicast = stats->rx_mcast; | |
360 | net_stats->collisions = stats->tx_1_col + stats->tx_2_col * 2 + | |
361 | stats->tx_late_col + stats->tx_abort_col; | |
362 | ||
363 | net_stats->rx_errors = stats->rx_frag + stats->rx_fcs_err + | |
364 | stats->rx_len_err + stats->rx_sz_ov + | |
365 | stats->rx_align_err; | |
366 | net_stats->rx_fifo_errors = stats->rx_rxf_ov; | |
367 | net_stats->rx_length_errors = stats->rx_len_err; | |
368 | net_stats->rx_crc_errors = stats->rx_fcs_err; | |
369 | net_stats->rx_frame_errors = stats->rx_align_err; | |
370 | net_stats->rx_over_errors = stats->rx_rxf_ov; | |
371 | net_stats->rx_missed_errors = stats->rx_rxf_ov; | |
372 | ||
373 | net_stats->tx_errors = stats->tx_late_col + stats->tx_abort_col + | |
374 | stats->tx_underrun + stats->tx_trunc; | |
375 | net_stats->tx_fifo_errors = stats->tx_underrun; | |
376 | net_stats->tx_aborted_errors = stats->tx_abort_col; | |
377 | net_stats->tx_window_errors = stats->tx_late_col; | |
378 | ||
379 | spin_unlock(&stats->lock); | |
380 | ||
381 | return net_stats; | |
382 | } | |
383 | ||
384 | static const struct net_device_ops emac_netdev_ops = { | |
385 | .ndo_open = emac_open, | |
386 | .ndo_stop = emac_close, | |
387 | .ndo_validate_addr = eth_validate_addr, | |
388 | .ndo_start_xmit = emac_start_xmit, | |
389 | .ndo_set_mac_address = eth_mac_addr, | |
390 | .ndo_change_mtu = emac_change_mtu, | |
391 | .ndo_do_ioctl = emac_ioctl, | |
392 | .ndo_tx_timeout = emac_tx_timeout, | |
393 | .ndo_get_stats64 = emac_get_stats64, | |
394 | .ndo_set_features = emac_set_features, | |
395 | .ndo_set_rx_mode = emac_rx_mode_set, | |
396 | }; | |
397 | ||
398 | /* Watchdog task routine, called to reinitialize the EMAC */ | |
399 | static void emac_work_thread(struct work_struct *work) | |
400 | { | |
401 | struct emac_adapter *adpt = | |
402 | container_of(work, struct emac_adapter, work_thread); | |
403 | ||
404 | emac_reinit_locked(adpt); | |
405 | } | |
406 | ||
407 | /* Initialize various data structures */ | |
408 | static void emac_init_adapter(struct emac_adapter *adpt) | |
409 | { | |
410 | u32 reg; | |
411 | ||
412 | /* descriptors */ | |
413 | adpt->tx_desc_cnt = EMAC_DEF_TX_DESCS; | |
414 | adpt->rx_desc_cnt = EMAC_DEF_RX_DESCS; | |
415 | ||
416 | /* dma */ | |
417 | adpt->dma_order = emac_dma_ord_out; | |
418 | adpt->dmar_block = emac_dma_req_4096; | |
419 | adpt->dmaw_block = emac_dma_req_128; | |
420 | adpt->dmar_dly_cnt = DMAR_DLY_CNT_DEF; | |
421 | adpt->dmaw_dly_cnt = DMAW_DLY_CNT_DEF; | |
422 | adpt->tpd_burst = TXQ0_NUM_TPD_PREF_DEF; | |
423 | adpt->rfd_burst = RXQ0_NUM_RFD_PREF_DEF; | |
424 | ||
425 | /* irq moderator */ | |
426 | reg = ((EMAC_DEF_RX_IRQ_MOD >> 1) << IRQ_MODERATOR2_INIT_SHFT) | | |
427 | ((EMAC_DEF_TX_IRQ_MOD >> 1) << IRQ_MODERATOR_INIT_SHFT); | |
428 | adpt->irq_mod = reg; | |
429 | ||
430 | /* others */ | |
431 | adpt->preamble = EMAC_PREAMBLE_DEF; | |
432 | } | |
433 | ||
434 | /* Get the clock */ | |
435 | static int emac_clks_get(struct platform_device *pdev, | |
436 | struct emac_adapter *adpt) | |
437 | { | |
438 | unsigned int i; | |
439 | ||
440 | for (i = 0; i < EMAC_CLK_CNT; i++) { | |
441 | struct clk *clk = devm_clk_get(&pdev->dev, emac_clk_name[i]); | |
442 | ||
443 | if (IS_ERR(clk)) { | |
444 | dev_err(&pdev->dev, | |
445 | "could not claim clock %s (error=%li)\n", | |
446 | emac_clk_name[i], PTR_ERR(clk)); | |
447 | ||
448 | return PTR_ERR(clk); | |
449 | } | |
450 | ||
451 | adpt->clk[i] = clk; | |
452 | } | |
453 | ||
454 | return 0; | |
455 | } | |
456 | ||
457 | /* Initialize clocks */ | |
458 | static int emac_clks_phase1_init(struct platform_device *pdev, | |
459 | struct emac_adapter *adpt) | |
460 | { | |
461 | int ret; | |
462 | ||
026acd5f TT |
463 | /* On ACPI platforms, clocks are controlled by firmware and/or |
464 | * ACPI, not by drivers. | |
465 | */ | |
466 | if (has_acpi_companion(&pdev->dev)) | |
467 | return 0; | |
468 | ||
b9b17deb TT |
469 | ret = emac_clks_get(pdev, adpt); |
470 | if (ret) | |
471 | return ret; | |
472 | ||
473 | ret = clk_prepare_enable(adpt->clk[EMAC_CLK_AXI]); | |
474 | if (ret) | |
475 | return ret; | |
476 | ||
477 | ret = clk_prepare_enable(adpt->clk[EMAC_CLK_CFG_AHB]); | |
478 | if (ret) | |
479 | return ret; | |
480 | ||
481 | ret = clk_set_rate(adpt->clk[EMAC_CLK_HIGH_SPEED], 19200000); | |
482 | if (ret) | |
483 | return ret; | |
484 | ||
485 | return clk_prepare_enable(adpt->clk[EMAC_CLK_HIGH_SPEED]); | |
486 | } | |
487 | ||
488 | /* Enable clocks; needs emac_clks_phase1_init to be called before */ | |
489 | static int emac_clks_phase2_init(struct platform_device *pdev, | |
490 | struct emac_adapter *adpt) | |
491 | { | |
492 | int ret; | |
493 | ||
026acd5f TT |
494 | if (has_acpi_companion(&pdev->dev)) |
495 | return 0; | |
496 | ||
b9b17deb TT |
497 | ret = clk_set_rate(adpt->clk[EMAC_CLK_TX], 125000000); |
498 | if (ret) | |
499 | return ret; | |
500 | ||
501 | ret = clk_prepare_enable(adpt->clk[EMAC_CLK_TX]); | |
502 | if (ret) | |
503 | return ret; | |
504 | ||
505 | ret = clk_set_rate(adpt->clk[EMAC_CLK_HIGH_SPEED], 125000000); | |
506 | if (ret) | |
507 | return ret; | |
508 | ||
509 | ret = clk_set_rate(adpt->clk[EMAC_CLK_MDIO], 25000000); | |
510 | if (ret) | |
511 | return ret; | |
512 | ||
513 | ret = clk_prepare_enable(adpt->clk[EMAC_CLK_MDIO]); | |
514 | if (ret) | |
515 | return ret; | |
516 | ||
517 | ret = clk_prepare_enable(adpt->clk[EMAC_CLK_RX]); | |
518 | if (ret) | |
519 | return ret; | |
520 | ||
521 | return clk_prepare_enable(adpt->clk[EMAC_CLK_SYS]); | |
522 | } | |
523 | ||
524 | static void emac_clks_teardown(struct emac_adapter *adpt) | |
525 | { | |
526 | ||
527 | unsigned int i; | |
528 | ||
529 | for (i = 0; i < EMAC_CLK_CNT; i++) | |
530 | clk_disable_unprepare(adpt->clk[i]); | |
531 | } | |
532 | ||
533 | /* Get the resources */ | |
534 | static int emac_probe_resources(struct platform_device *pdev, | |
535 | struct emac_adapter *adpt) | |
536 | { | |
b9b17deb TT |
537 | struct net_device *netdev = adpt->netdev; |
538 | struct resource *res; | |
0de709ac | 539 | char maddr[ETH_ALEN]; |
b9b17deb TT |
540 | int ret = 0; |
541 | ||
542 | /* get mac address */ | |
0de709ac | 543 | if (device_get_mac_address(&pdev->dev, maddr, ETH_ALEN)) |
b9b17deb | 544 | ether_addr_copy(netdev->dev_addr, maddr); |
0de709ac TT |
545 | else |
546 | eth_hw_addr_random(netdev); | |
b9b17deb TT |
547 | |
548 | /* Core 0 interrupt */ | |
549 | ret = platform_get_irq(pdev, 0); | |
550 | if (ret < 0) { | |
551 | dev_err(&pdev->dev, | |
552 | "error: missing core0 irq resource (error=%i)\n", ret); | |
553 | return ret; | |
554 | } | |
555 | adpt->irq.irq = ret; | |
556 | ||
557 | /* base register address */ | |
558 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
559 | adpt->base = devm_ioremap_resource(&pdev->dev, res); | |
560 | if (IS_ERR(adpt->base)) | |
561 | return PTR_ERR(adpt->base); | |
562 | ||
563 | /* CSR register address */ | |
564 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
565 | adpt->csr = devm_ioremap_resource(&pdev->dev, res); | |
566 | if (IS_ERR(adpt->csr)) | |
567 | return PTR_ERR(adpt->csr); | |
568 | ||
569 | netdev->base_addr = (unsigned long)adpt->base; | |
570 | ||
571 | return 0; | |
572 | } | |
573 | ||
574 | static const struct of_device_id emac_dt_match[] = { | |
575 | { | |
576 | .compatible = "qcom,fsm9900-emac", | |
577 | }, | |
578 | {} | |
579 | }; | |
70972685 | 580 | MODULE_DEVICE_TABLE(of, emac_dt_match); |
b9b17deb | 581 | |
5f3d3807 TT |
582 | #if IS_ENABLED(CONFIG_ACPI) |
583 | static const struct acpi_device_id emac_acpi_match[] = { | |
584 | { | |
585 | .id = "QCOM8070", | |
586 | }, | |
587 | {} | |
588 | }; | |
589 | MODULE_DEVICE_TABLE(acpi, emac_acpi_match); | |
590 | #endif | |
591 | ||
b9b17deb TT |
592 | static int emac_probe(struct platform_device *pdev) |
593 | { | |
594 | struct net_device *netdev; | |
595 | struct emac_adapter *adpt; | |
596 | struct emac_phy *phy; | |
597 | u16 devid, revid; | |
598 | u32 reg; | |
599 | int ret; | |
600 | ||
601 | /* The EMAC itself is capable of 64-bit DMA, so try that first. */ | |
602 | ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); | |
603 | if (ret) { | |
604 | /* Some platforms may restrict the EMAC's address bus to less | |
605 | * then the size of DDR. In this case, we need to try a | |
606 | * smaller mask. We could try every possible smaller mask, | |
607 | * but that's overkill. Instead, just fall to 32-bit, which | |
608 | * should always work. | |
609 | */ | |
610 | ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); | |
611 | if (ret) { | |
612 | dev_err(&pdev->dev, "could not set DMA mask\n"); | |
613 | return ret; | |
614 | } | |
615 | } | |
616 | ||
617 | netdev = alloc_etherdev(sizeof(struct emac_adapter)); | |
618 | if (!netdev) | |
619 | return -ENOMEM; | |
620 | ||
621 | dev_set_drvdata(&pdev->dev, netdev); | |
622 | SET_NETDEV_DEV(netdev, &pdev->dev); | |
623 | ||
624 | adpt = netdev_priv(netdev); | |
625 | adpt->netdev = netdev; | |
626 | adpt->msg_enable = EMAC_MSG_DEFAULT; | |
627 | ||
628 | phy = &adpt->phy; | |
629 | ||
630 | mutex_init(&adpt->reset_lock); | |
631 | spin_lock_init(&adpt->stats.lock); | |
632 | ||
633 | adpt->irq.mask = RX_PKT_INT0 | IMR_NORMAL_MASK; | |
634 | ||
635 | ret = emac_probe_resources(pdev, adpt); | |
636 | if (ret) | |
637 | goto err_undo_netdev; | |
638 | ||
639 | /* initialize clocks */ | |
640 | ret = emac_clks_phase1_init(pdev, adpt); | |
641 | if (ret) { | |
642 | dev_err(&pdev->dev, "could not initialize clocks\n"); | |
643 | goto err_undo_netdev; | |
644 | } | |
645 | ||
646 | netdev->watchdog_timeo = EMAC_WATCHDOG_TIME; | |
647 | netdev->irq = adpt->irq.irq; | |
648 | ||
649 | adpt->rrd_size = EMAC_RRD_SIZE; | |
650 | adpt->tpd_size = EMAC_TPD_SIZE; | |
651 | adpt->rfd_size = EMAC_RFD_SIZE; | |
652 | ||
653 | netdev->netdev_ops = &emac_netdev_ops; | |
654 | ||
655 | emac_init_adapter(adpt); | |
656 | ||
657 | /* init external phy */ | |
658 | ret = emac_phy_config(pdev, adpt); | |
659 | if (ret) | |
660 | goto err_undo_clocks; | |
661 | ||
662 | /* init internal sgmii phy */ | |
663 | ret = emac_sgmii_config(pdev, adpt); | |
664 | if (ret) | |
665 | goto err_undo_mdiobus; | |
666 | ||
667 | /* enable clocks */ | |
668 | ret = emac_clks_phase2_init(pdev, adpt); | |
669 | if (ret) { | |
670 | dev_err(&pdev->dev, "could not initialize clocks\n"); | |
671 | goto err_undo_mdiobus; | |
672 | } | |
673 | ||
674 | emac_mac_reset(adpt); | |
675 | ||
676 | /* set hw features */ | |
677 | netdev->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_RXCSUM | | |
678 | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX | | |
679 | NETIF_F_HW_VLAN_CTAG_TX; | |
680 | netdev->hw_features = netdev->features; | |
681 | ||
682 | netdev->vlan_features |= NETIF_F_SG | NETIF_F_HW_CSUM | | |
683 | NETIF_F_TSO | NETIF_F_TSO6; | |
684 | ||
d894be57 JW |
685 | /* MTU range: 46 - 9194 */ |
686 | netdev->min_mtu = EMAC_MIN_ETH_FRAME_SIZE - | |
687 | (ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN); | |
688 | netdev->max_mtu = EMAC_MAX_ETH_FRAME_SIZE - | |
689 | (ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN); | |
690 | ||
b9b17deb TT |
691 | INIT_WORK(&adpt->work_thread, emac_work_thread); |
692 | ||
693 | /* Initialize queues */ | |
694 | emac_mac_rx_tx_ring_init_all(pdev, adpt); | |
695 | ||
696 | netif_napi_add(netdev, &adpt->rx_q.napi, emac_napi_rtx, | |
697 | NAPI_POLL_WEIGHT); | |
698 | ||
699 | ret = register_netdev(netdev); | |
700 | if (ret) { | |
701 | dev_err(&pdev->dev, "could not register net device\n"); | |
702 | goto err_undo_napi; | |
703 | } | |
704 | ||
705 | reg = readl_relaxed(adpt->base + EMAC_DMA_MAS_CTRL); | |
706 | devid = (reg & DEV_ID_NUM_BMSK) >> DEV_ID_NUM_SHFT; | |
707 | revid = (reg & DEV_REV_NUM_BMSK) >> DEV_REV_NUM_SHFT; | |
708 | reg = readl_relaxed(adpt->base + EMAC_CORE_HW_VERSION); | |
709 | ||
710 | netif_info(adpt, probe, netdev, | |
711 | "hardware id %d.%d, hardware version %d.%d.%d\n", | |
712 | devid, revid, | |
713 | (reg & MAJOR_BMSK) >> MAJOR_SHFT, | |
714 | (reg & MINOR_BMSK) >> MINOR_SHFT, | |
715 | (reg & STEP_BMSK) >> STEP_SHFT); | |
716 | ||
717 | return 0; | |
718 | ||
719 | err_undo_napi: | |
720 | netif_napi_del(&adpt->rx_q.napi); | |
721 | err_undo_mdiobus: | |
994c5483 | 722 | put_device(&adpt->phydev->mdio.dev); |
b9b17deb TT |
723 | mdiobus_unregister(adpt->mii_bus); |
724 | err_undo_clocks: | |
725 | emac_clks_teardown(adpt); | |
726 | err_undo_netdev: | |
727 | free_netdev(netdev); | |
728 | ||
729 | return ret; | |
730 | } | |
731 | ||
732 | static int emac_remove(struct platform_device *pdev) | |
733 | { | |
734 | struct net_device *netdev = dev_get_drvdata(&pdev->dev); | |
735 | struct emac_adapter *adpt = netdev_priv(netdev); | |
736 | ||
737 | unregister_netdev(netdev); | |
738 | netif_napi_del(&adpt->rx_q.napi); | |
739 | ||
740 | emac_clks_teardown(adpt); | |
741 | ||
994c5483 | 742 | put_device(&adpt->phydev->mdio.dev); |
b9b17deb TT |
743 | mdiobus_unregister(adpt->mii_bus); |
744 | free_netdev(netdev); | |
b9b17deb | 745 | |
54e19bc7 TT |
746 | if (adpt->phy.digital) |
747 | iounmap(adpt->phy.digital); | |
748 | iounmap(adpt->phy.base); | |
749 | ||
b9b17deb TT |
750 | return 0; |
751 | } | |
752 | ||
753 | static struct platform_driver emac_platform_driver = { | |
754 | .probe = emac_probe, | |
755 | .remove = emac_remove, | |
756 | .driver = { | |
b9b17deb TT |
757 | .name = "qcom-emac", |
758 | .of_match_table = emac_dt_match, | |
5f3d3807 | 759 | .acpi_match_table = ACPI_PTR(emac_acpi_match), |
b9b17deb TT |
760 | }, |
761 | }; | |
762 | ||
763 | module_platform_driver(emac_platform_driver); | |
764 | ||
765 | MODULE_LICENSE("GPL v2"); | |
766 | MODULE_ALIAS("platform:qcom-emac"); |