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291ab06e SW |
1 | /* |
2 | * Copyright (c) 2011, 2012, Qualcomm Atheros Communications Inc. | |
3 | * Copyright (c) 2014, I2SE GmbH | |
4 | * | |
5 | * Permission to use, copy, modify, and/or distribute this software | |
6 | * for any purpose with or without fee is hereby granted, provided | |
7 | * that the above copyright notice and this permission notice appear | |
8 | * in all copies. | |
9 | * | |
10 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL | |
11 | * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED | |
12 | * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL | |
13 | * THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR | |
14 | * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM | |
15 | * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, | |
16 | * NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN | |
17 | * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
18 | */ | |
19 | ||
20 | /* This module implements the Qualcomm Atheros SPI protocol for | |
21 | * kernel-based SPI device; it is essentially an Ethernet-to-SPI | |
22 | * serial converter; | |
23 | */ | |
24 | ||
25 | #include <linux/errno.h> | |
26 | #include <linux/etherdevice.h> | |
27 | #include <linux/if_arp.h> | |
28 | #include <linux/if_ether.h> | |
29 | #include <linux/init.h> | |
30 | #include <linux/interrupt.h> | |
31 | #include <linux/jiffies.h> | |
32 | #include <linux/kernel.h> | |
33 | #include <linux/kthread.h> | |
34 | #include <linux/module.h> | |
35 | #include <linux/moduleparam.h> | |
36 | #include <linux/netdevice.h> | |
37 | #include <linux/of.h> | |
38 | #include <linux/of_device.h> | |
39 | #include <linux/of_net.h> | |
40 | #include <linux/sched.h> | |
41 | #include <linux/skbuff.h> | |
42 | #include <linux/spi/spi.h> | |
43 | #include <linux/types.h> | |
291ab06e SW |
44 | |
45 | #include "qca_7k.h" | |
46 | #include "qca_debug.h" | |
47 | #include "qca_framing.h" | |
48 | #include "qca_spi.h" | |
49 | ||
50 | #define MAX_DMA_BURST_LEN 5000 | |
51 | ||
52 | /* Modules parameters */ | |
53 | #define QCASPI_CLK_SPEED_MIN 1000000 | |
54 | #define QCASPI_CLK_SPEED_MAX 16000000 | |
55 | #define QCASPI_CLK_SPEED 8000000 | |
56 | static int qcaspi_clkspeed; | |
57 | module_param(qcaspi_clkspeed, int, 0); | |
58 | MODULE_PARM_DESC(qcaspi_clkspeed, "SPI bus clock speed (Hz). Use 1000000-16000000."); | |
59 | ||
60 | #define QCASPI_BURST_LEN_MIN 1 | |
61 | #define QCASPI_BURST_LEN_MAX MAX_DMA_BURST_LEN | |
62 | static int qcaspi_burst_len = MAX_DMA_BURST_LEN; | |
63 | module_param(qcaspi_burst_len, int, 0); | |
64 | MODULE_PARM_DESC(qcaspi_burst_len, "Number of data bytes per burst. Use 1-5000."); | |
65 | ||
66 | #define QCASPI_PLUGGABLE_MIN 0 | |
67 | #define QCASPI_PLUGGABLE_MAX 1 | |
68 | static int qcaspi_pluggable = QCASPI_PLUGGABLE_MIN; | |
69 | module_param(qcaspi_pluggable, int, 0); | |
70 | MODULE_PARM_DESC(qcaspi_pluggable, "Pluggable SPI connection (yes/no)."); | |
71 | ||
72 | #define QCASPI_MTU QCAFRM_ETHMAXMTU | |
73 | #define QCASPI_TX_TIMEOUT (1 * HZ) | |
74 | #define QCASPI_QCA7K_REBOOT_TIME_MS 1000 | |
75 | ||
76 | static void | |
77 | start_spi_intr_handling(struct qcaspi *qca, u16 *intr_cause) | |
78 | { | |
79 | *intr_cause = 0; | |
80 | ||
81 | qcaspi_write_register(qca, SPI_REG_INTR_ENABLE, 0); | |
82 | qcaspi_read_register(qca, SPI_REG_INTR_CAUSE, intr_cause); | |
83 | netdev_dbg(qca->net_dev, "interrupts: 0x%04x\n", *intr_cause); | |
84 | } | |
85 | ||
86 | static void | |
87 | end_spi_intr_handling(struct qcaspi *qca, u16 intr_cause) | |
88 | { | |
89 | u16 intr_enable = (SPI_INT_CPU_ON | | |
90 | SPI_INT_PKT_AVLBL | | |
91 | SPI_INT_RDBUF_ERR | | |
92 | SPI_INT_WRBUF_ERR); | |
93 | ||
94 | qcaspi_write_register(qca, SPI_REG_INTR_CAUSE, intr_cause); | |
95 | qcaspi_write_register(qca, SPI_REG_INTR_ENABLE, intr_enable); | |
96 | netdev_dbg(qca->net_dev, "acking int: 0x%04x\n", intr_cause); | |
97 | } | |
98 | ||
99 | static u32 | |
100 | qcaspi_write_burst(struct qcaspi *qca, u8 *src, u32 len) | |
101 | { | |
102 | __be16 cmd; | |
103 | struct spi_message *msg = &qca->spi_msg2; | |
104 | struct spi_transfer *transfer = &qca->spi_xfer2[0]; | |
105 | int ret; | |
106 | ||
107 | cmd = cpu_to_be16(QCA7K_SPI_WRITE | QCA7K_SPI_EXTERNAL); | |
108 | transfer->tx_buf = &cmd; | |
109 | transfer->rx_buf = NULL; | |
110 | transfer->len = QCASPI_CMD_LEN; | |
111 | transfer = &qca->spi_xfer2[1]; | |
112 | transfer->tx_buf = src; | |
113 | transfer->rx_buf = NULL; | |
114 | transfer->len = len; | |
115 | ||
116 | ret = spi_sync(qca->spi_dev, msg); | |
117 | ||
118 | if (ret || (msg->actual_length != QCASPI_CMD_LEN + len)) { | |
119 | qcaspi_spi_error(qca); | |
120 | return 0; | |
121 | } | |
122 | ||
123 | return len; | |
124 | } | |
125 | ||
126 | static u32 | |
127 | qcaspi_write_legacy(struct qcaspi *qca, u8 *src, u32 len) | |
128 | { | |
129 | struct spi_message *msg = &qca->spi_msg1; | |
130 | struct spi_transfer *transfer = &qca->spi_xfer1; | |
131 | int ret; | |
132 | ||
133 | transfer->tx_buf = src; | |
134 | transfer->rx_buf = NULL; | |
135 | transfer->len = len; | |
136 | ||
137 | ret = spi_sync(qca->spi_dev, msg); | |
138 | ||
139 | if (ret || (msg->actual_length != len)) { | |
140 | qcaspi_spi_error(qca); | |
141 | return 0; | |
142 | } | |
143 | ||
144 | return len; | |
145 | } | |
146 | ||
147 | static u32 | |
148 | qcaspi_read_burst(struct qcaspi *qca, u8 *dst, u32 len) | |
149 | { | |
150 | struct spi_message *msg = &qca->spi_msg2; | |
151 | __be16 cmd; | |
152 | struct spi_transfer *transfer = &qca->spi_xfer2[0]; | |
153 | int ret; | |
154 | ||
155 | cmd = cpu_to_be16(QCA7K_SPI_READ | QCA7K_SPI_EXTERNAL); | |
156 | transfer->tx_buf = &cmd; | |
157 | transfer->rx_buf = NULL; | |
158 | transfer->len = QCASPI_CMD_LEN; | |
159 | transfer = &qca->spi_xfer2[1]; | |
160 | transfer->tx_buf = NULL; | |
161 | transfer->rx_buf = dst; | |
162 | transfer->len = len; | |
163 | ||
164 | ret = spi_sync(qca->spi_dev, msg); | |
165 | ||
166 | if (ret || (msg->actual_length != QCASPI_CMD_LEN + len)) { | |
167 | qcaspi_spi_error(qca); | |
168 | return 0; | |
169 | } | |
170 | ||
171 | return len; | |
172 | } | |
173 | ||
174 | static u32 | |
175 | qcaspi_read_legacy(struct qcaspi *qca, u8 *dst, u32 len) | |
176 | { | |
177 | struct spi_message *msg = &qca->spi_msg1; | |
178 | struct spi_transfer *transfer = &qca->spi_xfer1; | |
179 | int ret; | |
180 | ||
181 | transfer->tx_buf = NULL; | |
182 | transfer->rx_buf = dst; | |
183 | transfer->len = len; | |
184 | ||
185 | ret = spi_sync(qca->spi_dev, msg); | |
186 | ||
187 | if (ret || (msg->actual_length != len)) { | |
188 | qcaspi_spi_error(qca); | |
189 | return 0; | |
190 | } | |
191 | ||
192 | return len; | |
193 | } | |
194 | ||
195 | static int | |
196 | qcaspi_tx_frame(struct qcaspi *qca, struct sk_buff *skb) | |
197 | { | |
198 | u32 count; | |
199 | u32 written; | |
200 | u32 offset; | |
201 | u32 len; | |
202 | ||
203 | len = skb->len; | |
204 | ||
205 | qcaspi_write_register(qca, SPI_REG_BFR_SIZE, len); | |
206 | if (qca->legacy_mode) | |
207 | qcaspi_tx_cmd(qca, QCA7K_SPI_WRITE | QCA7K_SPI_EXTERNAL); | |
208 | ||
209 | offset = 0; | |
210 | while (len) { | |
211 | count = len; | |
212 | if (count > qca->burst_len) | |
213 | count = qca->burst_len; | |
214 | ||
215 | if (qca->legacy_mode) { | |
216 | written = qcaspi_write_legacy(qca, | |
217 | skb->data + offset, | |
218 | count); | |
219 | } else { | |
220 | written = qcaspi_write_burst(qca, | |
221 | skb->data + offset, | |
222 | count); | |
223 | } | |
224 | ||
225 | if (written != count) | |
226 | return -1; | |
227 | ||
228 | offset += count; | |
229 | len -= count; | |
230 | } | |
231 | ||
232 | return 0; | |
233 | } | |
234 | ||
235 | static int | |
236 | qcaspi_transmit(struct qcaspi *qca) | |
237 | { | |
238 | struct net_device_stats *n_stats = &qca->net_dev->stats; | |
239 | u16 available = 0; | |
240 | u32 pkt_len; | |
241 | u16 new_head; | |
242 | u16 packets = 0; | |
243 | ||
244 | if (qca->txr.skb[qca->txr.head] == NULL) | |
245 | return 0; | |
246 | ||
247 | qcaspi_read_register(qca, SPI_REG_WRBUF_SPC_AVA, &available); | |
248 | ||
249 | while (qca->txr.skb[qca->txr.head]) { | |
250 | pkt_len = qca->txr.skb[qca->txr.head]->len + QCASPI_HW_PKT_LEN; | |
251 | ||
252 | if (available < pkt_len) { | |
253 | if (packets == 0) | |
254 | qca->stats.write_buf_miss++; | |
255 | break; | |
256 | } | |
257 | ||
258 | if (qcaspi_tx_frame(qca, qca->txr.skb[qca->txr.head]) == -1) { | |
259 | qca->stats.write_err++; | |
260 | return -1; | |
261 | } | |
262 | ||
263 | packets++; | |
264 | n_stats->tx_packets++; | |
265 | n_stats->tx_bytes += qca->txr.skb[qca->txr.head]->len; | |
266 | available -= pkt_len; | |
267 | ||
268 | /* remove the skb from the queue */ | |
269 | /* XXX After inconsistent lock states netif_tx_lock() | |
270 | * has been replaced by netif_tx_lock_bh() and so on. | |
271 | */ | |
272 | netif_tx_lock_bh(qca->net_dev); | |
273 | dev_kfree_skb(qca->txr.skb[qca->txr.head]); | |
274 | qca->txr.skb[qca->txr.head] = NULL; | |
275 | qca->txr.size -= pkt_len; | |
276 | new_head = qca->txr.head + 1; | |
277 | if (new_head >= qca->txr.count) | |
278 | new_head = 0; | |
279 | qca->txr.head = new_head; | |
280 | if (netif_queue_stopped(qca->net_dev)) | |
281 | netif_wake_queue(qca->net_dev); | |
282 | netif_tx_unlock_bh(qca->net_dev); | |
283 | } | |
284 | ||
285 | return 0; | |
286 | } | |
287 | ||
288 | static int | |
289 | qcaspi_receive(struct qcaspi *qca) | |
290 | { | |
291 | struct net_device *net_dev = qca->net_dev; | |
292 | struct net_device_stats *n_stats = &net_dev->stats; | |
293 | u16 available = 0; | |
294 | u32 bytes_read; | |
295 | u8 *cp; | |
296 | ||
297 | /* Allocate rx SKB if we don't have one available. */ | |
298 | if (!qca->rx_skb) { | |
8d66c30b SW |
299 | qca->rx_skb = netdev_alloc_skb_ip_align(net_dev, |
300 | net_dev->mtu + | |
301 | VLAN_ETH_HLEN); | |
291ab06e SW |
302 | if (!qca->rx_skb) { |
303 | netdev_dbg(net_dev, "out of RX resources\n"); | |
304 | qca->stats.out_of_mem++; | |
305 | return -1; | |
306 | } | |
307 | } | |
308 | ||
309 | /* Read the packet size. */ | |
310 | qcaspi_read_register(qca, SPI_REG_RDBUF_BYTE_AVA, &available); | |
311 | netdev_dbg(net_dev, "qcaspi_receive: SPI_REG_RDBUF_BYTE_AVA: Value: %08x\n", | |
312 | available); | |
313 | ||
314 | if (available == 0) { | |
315 | netdev_dbg(net_dev, "qcaspi_receive called without any data being available!\n"); | |
316 | return -1; | |
317 | } | |
318 | ||
319 | qcaspi_write_register(qca, SPI_REG_BFR_SIZE, available); | |
320 | ||
321 | if (qca->legacy_mode) | |
322 | qcaspi_tx_cmd(qca, QCA7K_SPI_READ | QCA7K_SPI_EXTERNAL); | |
323 | ||
324 | while (available) { | |
325 | u32 count = available; | |
326 | ||
327 | if (count > qca->burst_len) | |
328 | count = qca->burst_len; | |
329 | ||
330 | if (qca->legacy_mode) { | |
331 | bytes_read = qcaspi_read_legacy(qca, qca->rx_buffer, | |
332 | count); | |
333 | } else { | |
334 | bytes_read = qcaspi_read_burst(qca, qca->rx_buffer, | |
335 | count); | |
336 | } | |
337 | ||
338 | netdev_dbg(net_dev, "available: %d, byte read: %d\n", | |
339 | available, bytes_read); | |
340 | ||
341 | if (bytes_read) { | |
342 | available -= bytes_read; | |
343 | } else { | |
344 | qca->stats.read_err++; | |
345 | return -1; | |
346 | } | |
347 | ||
348 | cp = qca->rx_buffer; | |
349 | ||
350 | while ((bytes_read--) && (qca->rx_skb)) { | |
351 | s32 retcode; | |
352 | ||
353 | retcode = qcafrm_fsm_decode(&qca->frm_handle, | |
354 | qca->rx_skb->data, | |
355 | skb_tailroom(qca->rx_skb), | |
356 | *cp); | |
357 | cp++; | |
358 | switch (retcode) { | |
359 | case QCAFRM_GATHER: | |
360 | case QCAFRM_NOHEAD: | |
361 | break; | |
362 | case QCAFRM_NOTAIL: | |
363 | netdev_dbg(net_dev, "no RX tail\n"); | |
364 | n_stats->rx_errors++; | |
365 | n_stats->rx_dropped++; | |
366 | break; | |
367 | case QCAFRM_INVLEN: | |
368 | netdev_dbg(net_dev, "invalid RX length\n"); | |
369 | n_stats->rx_errors++; | |
370 | n_stats->rx_dropped++; | |
371 | break; | |
372 | default: | |
373 | qca->rx_skb->dev = qca->net_dev; | |
374 | n_stats->rx_packets++; | |
375 | n_stats->rx_bytes += retcode; | |
376 | skb_put(qca->rx_skb, retcode); | |
377 | qca->rx_skb->protocol = eth_type_trans( | |
378 | qca->rx_skb, qca->rx_skb->dev); | |
379 | qca->rx_skb->ip_summed = CHECKSUM_UNNECESSARY; | |
380 | netif_rx_ni(qca->rx_skb); | |
8d66c30b | 381 | qca->rx_skb = netdev_alloc_skb_ip_align(net_dev, |
291ab06e SW |
382 | net_dev->mtu + VLAN_ETH_HLEN); |
383 | if (!qca->rx_skb) { | |
384 | netdev_dbg(net_dev, "out of RX resources\n"); | |
385 | n_stats->rx_errors++; | |
386 | qca->stats.out_of_mem++; | |
387 | break; | |
388 | } | |
389 | } | |
390 | } | |
391 | } | |
392 | ||
393 | return 0; | |
394 | } | |
395 | ||
396 | /* Check that tx ring stores only so much bytes | |
397 | * that fit into the internal QCA buffer. | |
398 | */ | |
399 | ||
400 | static int | |
401 | qcaspi_tx_ring_has_space(struct tx_ring *txr) | |
402 | { | |
403 | if (txr->skb[txr->tail]) | |
404 | return 0; | |
405 | ||
406 | return (txr->size + QCAFRM_ETHMAXLEN < QCASPI_HW_BUF_LEN) ? 1 : 0; | |
407 | } | |
408 | ||
409 | /* Flush the tx ring. This function is only safe to | |
410 | * call from the qcaspi_spi_thread. | |
411 | */ | |
412 | ||
413 | static void | |
414 | qcaspi_flush_tx_ring(struct qcaspi *qca) | |
415 | { | |
416 | int i; | |
417 | ||
418 | /* XXX After inconsistent lock states netif_tx_lock() | |
419 | * has been replaced by netif_tx_lock_bh() and so on. | |
420 | */ | |
421 | netif_tx_lock_bh(qca->net_dev); | |
422 | for (i = 0; i < TX_RING_MAX_LEN; i++) { | |
423 | if (qca->txr.skb[i]) { | |
424 | dev_kfree_skb(qca->txr.skb[i]); | |
425 | qca->txr.skb[i] = NULL; | |
426 | qca->net_dev->stats.tx_dropped++; | |
427 | } | |
428 | } | |
429 | qca->txr.tail = 0; | |
430 | qca->txr.head = 0; | |
431 | qca->txr.size = 0; | |
432 | netif_tx_unlock_bh(qca->net_dev); | |
433 | } | |
434 | ||
435 | static void | |
436 | qcaspi_qca7k_sync(struct qcaspi *qca, int event) | |
437 | { | |
438 | u16 signature = 0; | |
439 | u16 spi_config; | |
440 | u16 wrbuf_space = 0; | |
441 | static u16 reset_count; | |
442 | ||
443 | if (event == QCASPI_EVENT_CPUON) { | |
444 | /* Read signature twice, if not valid | |
445 | * go back to unknown state. | |
446 | */ | |
447 | qcaspi_read_register(qca, SPI_REG_SIGNATURE, &signature); | |
448 | qcaspi_read_register(qca, SPI_REG_SIGNATURE, &signature); | |
449 | if (signature != QCASPI_GOOD_SIGNATURE) { | |
450 | qca->sync = QCASPI_SYNC_UNKNOWN; | |
451 | netdev_dbg(qca->net_dev, "sync: got CPU on, but signature was invalid, restart\n"); | |
452 | } else { | |
453 | /* ensure that the WRBUF is empty */ | |
454 | qcaspi_read_register(qca, SPI_REG_WRBUF_SPC_AVA, | |
455 | &wrbuf_space); | |
456 | if (wrbuf_space != QCASPI_HW_BUF_LEN) { | |
457 | netdev_dbg(qca->net_dev, "sync: got CPU on, but wrbuf not empty. reset!\n"); | |
458 | qca->sync = QCASPI_SYNC_UNKNOWN; | |
459 | } else { | |
460 | netdev_dbg(qca->net_dev, "sync: got CPU on, now in sync\n"); | |
461 | qca->sync = QCASPI_SYNC_READY; | |
462 | return; | |
463 | } | |
464 | } | |
465 | } | |
466 | ||
467 | switch (qca->sync) { | |
468 | case QCASPI_SYNC_READY: | |
469 | /* Read signature, if not valid go to unknown state. */ | |
470 | qcaspi_read_register(qca, SPI_REG_SIGNATURE, &signature); | |
471 | if (signature != QCASPI_GOOD_SIGNATURE) { | |
472 | qca->sync = QCASPI_SYNC_UNKNOWN; | |
473 | netdev_dbg(qca->net_dev, "sync: bad signature, restart\n"); | |
474 | /* don't reset right away */ | |
475 | return; | |
476 | } | |
477 | break; | |
478 | case QCASPI_SYNC_UNKNOWN: | |
479 | /* Read signature, if not valid stay in unknown state */ | |
480 | qcaspi_read_register(qca, SPI_REG_SIGNATURE, &signature); | |
481 | if (signature != QCASPI_GOOD_SIGNATURE) { | |
482 | netdev_dbg(qca->net_dev, "sync: could not read signature to reset device, retry.\n"); | |
483 | return; | |
484 | } | |
485 | ||
486 | /* TODO: use GPIO to reset QCA7000 in legacy mode*/ | |
487 | netdev_dbg(qca->net_dev, "sync: resetting device.\n"); | |
488 | qcaspi_read_register(qca, SPI_REG_SPI_CONFIG, &spi_config); | |
489 | spi_config |= QCASPI_SLAVE_RESET_BIT; | |
490 | qcaspi_write_register(qca, SPI_REG_SPI_CONFIG, spi_config); | |
491 | ||
492 | qca->sync = QCASPI_SYNC_RESET; | |
493 | qca->stats.trig_reset++; | |
494 | reset_count = 0; | |
495 | break; | |
496 | case QCASPI_SYNC_RESET: | |
497 | reset_count++; | |
498 | netdev_dbg(qca->net_dev, "sync: waiting for CPU on, count %u.\n", | |
499 | reset_count); | |
500 | if (reset_count >= QCASPI_RESET_TIMEOUT) { | |
501 | /* reset did not seem to take place, try again */ | |
502 | qca->sync = QCASPI_SYNC_UNKNOWN; | |
503 | qca->stats.reset_timeout++; | |
504 | netdev_dbg(qca->net_dev, "sync: reset timeout, restarting process.\n"); | |
505 | } | |
506 | break; | |
507 | } | |
508 | } | |
509 | ||
510 | static int | |
511 | qcaspi_spi_thread(void *data) | |
512 | { | |
513 | struct qcaspi *qca = data; | |
514 | u16 intr_cause = 0; | |
515 | ||
516 | netdev_info(qca->net_dev, "SPI thread created\n"); | |
517 | while (!kthread_should_stop()) { | |
518 | set_current_state(TASK_INTERRUPTIBLE); | |
519 | if ((qca->intr_req == qca->intr_svc) && | |
520 | (qca->txr.skb[qca->txr.head] == NULL) && | |
521 | (qca->sync == QCASPI_SYNC_READY)) | |
522 | schedule(); | |
523 | ||
524 | set_current_state(TASK_RUNNING); | |
525 | ||
526 | netdev_dbg(qca->net_dev, "have work to do. int: %d, tx_skb: %p\n", | |
527 | qca->intr_req - qca->intr_svc, | |
528 | qca->txr.skb[qca->txr.head]); | |
529 | ||
530 | qcaspi_qca7k_sync(qca, QCASPI_EVENT_UPDATE); | |
531 | ||
532 | if (qca->sync != QCASPI_SYNC_READY) { | |
533 | netdev_dbg(qca->net_dev, "sync: not ready %u, turn off carrier and flush\n", | |
534 | (unsigned int)qca->sync); | |
535 | netif_stop_queue(qca->net_dev); | |
536 | netif_carrier_off(qca->net_dev); | |
537 | qcaspi_flush_tx_ring(qca); | |
538 | msleep(QCASPI_QCA7K_REBOOT_TIME_MS); | |
539 | } | |
540 | ||
541 | if (qca->intr_svc != qca->intr_req) { | |
542 | qca->intr_svc = qca->intr_req; | |
543 | start_spi_intr_handling(qca, &intr_cause); | |
544 | ||
545 | if (intr_cause & SPI_INT_CPU_ON) { | |
546 | qcaspi_qca7k_sync(qca, QCASPI_EVENT_CPUON); | |
547 | ||
548 | /* not synced. */ | |
549 | if (qca->sync != QCASPI_SYNC_READY) | |
550 | continue; | |
551 | ||
552 | qca->stats.device_reset++; | |
553 | netif_wake_queue(qca->net_dev); | |
554 | netif_carrier_on(qca->net_dev); | |
555 | } | |
556 | ||
557 | if (intr_cause & SPI_INT_RDBUF_ERR) { | |
558 | /* restart sync */ | |
559 | netdev_dbg(qca->net_dev, "===> rdbuf error!\n"); | |
560 | qca->stats.read_buf_err++; | |
561 | qca->sync = QCASPI_SYNC_UNKNOWN; | |
562 | continue; | |
563 | } | |
564 | ||
565 | if (intr_cause & SPI_INT_WRBUF_ERR) { | |
566 | /* restart sync */ | |
567 | netdev_dbg(qca->net_dev, "===> wrbuf error!\n"); | |
568 | qca->stats.write_buf_err++; | |
569 | qca->sync = QCASPI_SYNC_UNKNOWN; | |
570 | continue; | |
571 | } | |
572 | ||
573 | /* can only handle other interrupts | |
dbedd44e | 574 | * if sync has occurred |
291ab06e SW |
575 | */ |
576 | if (qca->sync == QCASPI_SYNC_READY) { | |
577 | if (intr_cause & SPI_INT_PKT_AVLBL) | |
578 | qcaspi_receive(qca); | |
579 | } | |
580 | ||
581 | end_spi_intr_handling(qca, intr_cause); | |
582 | } | |
583 | ||
584 | if (qca->sync == QCASPI_SYNC_READY) | |
585 | qcaspi_transmit(qca); | |
586 | } | |
587 | set_current_state(TASK_RUNNING); | |
588 | netdev_info(qca->net_dev, "SPI thread exit\n"); | |
589 | ||
590 | return 0; | |
591 | } | |
592 | ||
593 | static irqreturn_t | |
594 | qcaspi_intr_handler(int irq, void *data) | |
595 | { | |
596 | struct qcaspi *qca = data; | |
597 | ||
598 | qca->intr_req++; | |
599 | if (qca->spi_thread && | |
600 | qca->spi_thread->state != TASK_RUNNING) | |
601 | wake_up_process(qca->spi_thread); | |
602 | ||
603 | return IRQ_HANDLED; | |
604 | } | |
605 | ||
606 | int | |
607 | qcaspi_netdev_open(struct net_device *dev) | |
608 | { | |
609 | struct qcaspi *qca = netdev_priv(dev); | |
610 | int ret = 0; | |
611 | ||
612 | if (!qca) | |
613 | return -EINVAL; | |
614 | ||
615 | qca->intr_req = 1; | |
616 | qca->intr_svc = 0; | |
617 | qca->sync = QCASPI_SYNC_UNKNOWN; | |
618 | qcafrm_fsm_init(&qca->frm_handle); | |
619 | ||
620 | qca->spi_thread = kthread_run((void *)qcaspi_spi_thread, | |
621 | qca, "%s", dev->name); | |
622 | ||
623 | if (IS_ERR(qca->spi_thread)) { | |
624 | netdev_err(dev, "%s: unable to start kernel thread.\n", | |
625 | QCASPI_DRV_NAME); | |
626 | return PTR_ERR(qca->spi_thread); | |
627 | } | |
628 | ||
629 | ret = request_irq(qca->spi_dev->irq, qcaspi_intr_handler, 0, | |
630 | dev->name, qca); | |
631 | if (ret) { | |
632 | netdev_err(dev, "%s: unable to get IRQ %d (irqval=%d).\n", | |
633 | QCASPI_DRV_NAME, qca->spi_dev->irq, ret); | |
634 | kthread_stop(qca->spi_thread); | |
635 | return ret; | |
636 | } | |
637 | ||
638 | netif_start_queue(qca->net_dev); | |
639 | ||
640 | return 0; | |
641 | } | |
642 | ||
643 | int | |
644 | qcaspi_netdev_close(struct net_device *dev) | |
645 | { | |
646 | struct qcaspi *qca = netdev_priv(dev); | |
647 | ||
648 | netif_stop_queue(dev); | |
649 | ||
650 | qcaspi_write_register(qca, SPI_REG_INTR_ENABLE, 0); | |
651 | free_irq(qca->spi_dev->irq, qca); | |
652 | ||
653 | kthread_stop(qca->spi_thread); | |
654 | qca->spi_thread = NULL; | |
655 | qcaspi_flush_tx_ring(qca); | |
656 | ||
657 | return 0; | |
658 | } | |
659 | ||
660 | static netdev_tx_t | |
661 | qcaspi_netdev_xmit(struct sk_buff *skb, struct net_device *dev) | |
662 | { | |
663 | u32 frame_len; | |
664 | u8 *ptmp; | |
665 | struct qcaspi *qca = netdev_priv(dev); | |
666 | u16 new_tail; | |
667 | struct sk_buff *tskb; | |
668 | u8 pad_len = 0; | |
669 | ||
670 | if (skb->len < QCAFRM_ETHMINLEN) | |
671 | pad_len = QCAFRM_ETHMINLEN - skb->len; | |
672 | ||
673 | if (qca->txr.skb[qca->txr.tail]) { | |
674 | netdev_warn(qca->net_dev, "queue was unexpectedly full!\n"); | |
675 | netif_stop_queue(qca->net_dev); | |
676 | qca->stats.ring_full++; | |
677 | return NETDEV_TX_BUSY; | |
678 | } | |
679 | ||
680 | if ((skb_headroom(skb) < QCAFRM_HEADER_LEN) || | |
681 | (skb_tailroom(skb) < QCAFRM_FOOTER_LEN + pad_len)) { | |
682 | tskb = skb_copy_expand(skb, QCAFRM_HEADER_LEN, | |
683 | QCAFRM_FOOTER_LEN + pad_len, GFP_ATOMIC); | |
684 | if (!tskb) { | |
685 | netdev_dbg(qca->net_dev, "could not allocate tx_buff\n"); | |
686 | qca->stats.out_of_mem++; | |
687 | return NETDEV_TX_BUSY; | |
688 | } | |
689 | dev_kfree_skb(skb); | |
690 | skb = tskb; | |
691 | } | |
692 | ||
693 | frame_len = skb->len + pad_len; | |
694 | ||
695 | ptmp = skb_push(skb, QCAFRM_HEADER_LEN); | |
696 | qcafrm_create_header(ptmp, frame_len); | |
697 | ||
698 | if (pad_len) { | |
699 | ptmp = skb_put(skb, pad_len); | |
700 | memset(ptmp, 0, pad_len); | |
701 | } | |
702 | ||
703 | ptmp = skb_put(skb, QCAFRM_FOOTER_LEN); | |
704 | qcafrm_create_footer(ptmp); | |
705 | ||
706 | netdev_dbg(qca->net_dev, "Tx-ing packet: Size: 0x%08x\n", | |
707 | skb->len); | |
708 | ||
709 | qca->txr.size += skb->len + QCASPI_HW_PKT_LEN; | |
710 | ||
711 | new_tail = qca->txr.tail + 1; | |
712 | if (new_tail >= qca->txr.count) | |
713 | new_tail = 0; | |
714 | ||
715 | qca->txr.skb[qca->txr.tail] = skb; | |
716 | qca->txr.tail = new_tail; | |
717 | ||
718 | if (!qcaspi_tx_ring_has_space(&qca->txr)) { | |
719 | netif_stop_queue(qca->net_dev); | |
720 | qca->stats.ring_full++; | |
721 | } | |
722 | ||
860e9538 | 723 | netif_trans_update(dev); |
291ab06e SW |
724 | |
725 | if (qca->spi_thread && | |
726 | qca->spi_thread->state != TASK_RUNNING) | |
727 | wake_up_process(qca->spi_thread); | |
728 | ||
729 | return NETDEV_TX_OK; | |
730 | } | |
731 | ||
732 | static void | |
733 | qcaspi_netdev_tx_timeout(struct net_device *dev) | |
734 | { | |
735 | struct qcaspi *qca = netdev_priv(dev); | |
736 | ||
737 | netdev_info(qca->net_dev, "Transmit timeout at %ld, latency %ld\n", | |
4d0e9657 | 738 | jiffies, jiffies - dev_trans_start(dev)); |
291ab06e | 739 | qca->net_dev->stats.tx_errors++; |
ed7d42e2 SW |
740 | /* Trigger tx queue flush and QCA7000 reset */ |
741 | qca->sync = QCASPI_SYNC_UNKNOWN; | |
291ab06e SW |
742 | } |
743 | ||
744 | static int | |
745 | qcaspi_netdev_init(struct net_device *dev) | |
746 | { | |
747 | struct qcaspi *qca = netdev_priv(dev); | |
748 | ||
749 | dev->mtu = QCASPI_MTU; | |
750 | dev->type = ARPHRD_ETHER; | |
751 | qca->clkspeed = qcaspi_clkspeed; | |
752 | qca->burst_len = qcaspi_burst_len; | |
753 | qca->spi_thread = NULL; | |
754 | qca->buffer_size = (dev->mtu + VLAN_ETH_HLEN + QCAFRM_HEADER_LEN + | |
755 | QCAFRM_FOOTER_LEN + 4) * 4; | |
756 | ||
757 | memset(&qca->stats, 0, sizeof(struct qcaspi_stats)); | |
758 | ||
759 | qca->rx_buffer = kmalloc(qca->buffer_size, GFP_KERNEL); | |
760 | if (!qca->rx_buffer) | |
761 | return -ENOBUFS; | |
762 | ||
8d66c30b SW |
763 | qca->rx_skb = netdev_alloc_skb_ip_align(dev, qca->net_dev->mtu + |
764 | VLAN_ETH_HLEN); | |
291ab06e SW |
765 | if (!qca->rx_skb) { |
766 | kfree(qca->rx_buffer); | |
767 | netdev_info(qca->net_dev, "Failed to allocate RX sk_buff.\n"); | |
768 | return -ENOBUFS; | |
769 | } | |
770 | ||
771 | return 0; | |
772 | } | |
773 | ||
774 | static void | |
775 | qcaspi_netdev_uninit(struct net_device *dev) | |
776 | { | |
777 | struct qcaspi *qca = netdev_priv(dev); | |
778 | ||
779 | kfree(qca->rx_buffer); | |
780 | qca->buffer_size = 0; | |
781 | if (qca->rx_skb) | |
782 | dev_kfree_skb(qca->rx_skb); | |
783 | } | |
784 | ||
291ab06e SW |
785 | static const struct net_device_ops qcaspi_netdev_ops = { |
786 | .ndo_init = qcaspi_netdev_init, | |
787 | .ndo_uninit = qcaspi_netdev_uninit, | |
788 | .ndo_open = qcaspi_netdev_open, | |
789 | .ndo_stop = qcaspi_netdev_close, | |
790 | .ndo_start_xmit = qcaspi_netdev_xmit, | |
291ab06e SW |
791 | .ndo_set_mac_address = eth_mac_addr, |
792 | .ndo_tx_timeout = qcaspi_netdev_tx_timeout, | |
793 | .ndo_validate_addr = eth_validate_addr, | |
794 | }; | |
795 | ||
796 | static void | |
797 | qcaspi_netdev_setup(struct net_device *dev) | |
798 | { | |
799 | struct qcaspi *qca = NULL; | |
800 | ||
291ab06e SW |
801 | dev->netdev_ops = &qcaspi_netdev_ops; |
802 | qcaspi_set_ethtool_ops(dev); | |
803 | dev->watchdog_timeo = QCASPI_TX_TIMEOUT; | |
a4690afe | 804 | dev->priv_flags &= ~IFF_TX_SKB_SHARING; |
291ab06e SW |
805 | dev->tx_queue_len = 100; |
806 | ||
44770e11 JW |
807 | /* MTU range: 46 - 1500 */ |
808 | dev->min_mtu = QCAFRM_ETHMINMTU; | |
809 | dev->max_mtu = QCAFRM_ETHMAXMTU; | |
810 | ||
291ab06e SW |
811 | qca = netdev_priv(dev); |
812 | memset(qca, 0, sizeof(struct qcaspi)); | |
813 | ||
814 | memset(&qca->spi_xfer1, 0, sizeof(struct spi_transfer)); | |
815 | memset(&qca->spi_xfer2, 0, sizeof(struct spi_transfer) * 2); | |
816 | ||
817 | spi_message_init(&qca->spi_msg1); | |
818 | spi_message_add_tail(&qca->spi_xfer1, &qca->spi_msg1); | |
819 | ||
820 | spi_message_init(&qca->spi_msg2); | |
821 | spi_message_add_tail(&qca->spi_xfer2[0], &qca->spi_msg2); | |
822 | spi_message_add_tail(&qca->spi_xfer2[1], &qca->spi_msg2); | |
823 | ||
824 | memset(&qca->txr, 0, sizeof(qca->txr)); | |
825 | qca->txr.count = TX_RING_MAX_LEN; | |
826 | } | |
827 | ||
828 | static const struct of_device_id qca_spi_of_match[] = { | |
829 | { .compatible = "qca,qca7000" }, | |
830 | { /* sentinel */ } | |
831 | }; | |
832 | MODULE_DEVICE_TABLE(of, qca_spi_of_match); | |
833 | ||
834 | static int | |
cf9d0dcc | 835 | qca_spi_probe(struct spi_device *spi) |
291ab06e SW |
836 | { |
837 | struct qcaspi *qca = NULL; | |
838 | struct net_device *qcaspi_devs = NULL; | |
839 | u8 legacy_mode = 0; | |
840 | u16 signature; | |
841 | const char *mac; | |
842 | ||
cf9d0dcc VB |
843 | if (!spi->dev.of_node) { |
844 | dev_err(&spi->dev, "Missing device tree\n"); | |
291ab06e SW |
845 | return -EINVAL; |
846 | } | |
847 | ||
cf9d0dcc | 848 | legacy_mode = of_property_read_bool(spi->dev.of_node, |
291ab06e SW |
849 | "qca,legacy-mode"); |
850 | ||
851 | if (qcaspi_clkspeed == 0) { | |
cf9d0dcc VB |
852 | if (spi->max_speed_hz) |
853 | qcaspi_clkspeed = spi->max_speed_hz; | |
291ab06e SW |
854 | else |
855 | qcaspi_clkspeed = QCASPI_CLK_SPEED; | |
856 | } | |
857 | ||
858 | if ((qcaspi_clkspeed < QCASPI_CLK_SPEED_MIN) || | |
859 | (qcaspi_clkspeed > QCASPI_CLK_SPEED_MAX)) { | |
cf9d0dcc | 860 | dev_info(&spi->dev, "Invalid clkspeed: %d\n", |
291ab06e SW |
861 | qcaspi_clkspeed); |
862 | return -EINVAL; | |
863 | } | |
864 | ||
865 | if ((qcaspi_burst_len < QCASPI_BURST_LEN_MIN) || | |
866 | (qcaspi_burst_len > QCASPI_BURST_LEN_MAX)) { | |
cf9d0dcc | 867 | dev_info(&spi->dev, "Invalid burst len: %d\n", |
291ab06e SW |
868 | qcaspi_burst_len); |
869 | return -EINVAL; | |
870 | } | |
871 | ||
872 | if ((qcaspi_pluggable < QCASPI_PLUGGABLE_MIN) || | |
873 | (qcaspi_pluggable > QCASPI_PLUGGABLE_MAX)) { | |
cf9d0dcc | 874 | dev_info(&spi->dev, "Invalid pluggable: %d\n", |
291ab06e SW |
875 | qcaspi_pluggable); |
876 | return -EINVAL; | |
877 | } | |
878 | ||
cf9d0dcc | 879 | dev_info(&spi->dev, "ver=%s, clkspeed=%d, burst_len=%d, pluggable=%d\n", |
291ab06e SW |
880 | QCASPI_DRV_VERSION, |
881 | qcaspi_clkspeed, | |
882 | qcaspi_burst_len, | |
883 | qcaspi_pluggable); | |
884 | ||
cf9d0dcc VB |
885 | spi->mode = SPI_MODE_3; |
886 | spi->max_speed_hz = qcaspi_clkspeed; | |
887 | if (spi_setup(spi) < 0) { | |
888 | dev_err(&spi->dev, "Unable to setup SPI device\n"); | |
291ab06e SW |
889 | return -EFAULT; |
890 | } | |
891 | ||
892 | qcaspi_devs = alloc_etherdev(sizeof(struct qcaspi)); | |
893 | if (!qcaspi_devs) | |
894 | return -ENOMEM; | |
895 | ||
896 | qcaspi_netdev_setup(qcaspi_devs); | |
897 | ||
898 | qca = netdev_priv(qcaspi_devs); | |
899 | if (!qca) { | |
900 | free_netdev(qcaspi_devs); | |
cf9d0dcc | 901 | dev_err(&spi->dev, "Fail to retrieve private structure\n"); |
291ab06e SW |
902 | return -ENOMEM; |
903 | } | |
904 | qca->net_dev = qcaspi_devs; | |
cf9d0dcc | 905 | qca->spi_dev = spi; |
291ab06e SW |
906 | qca->legacy_mode = legacy_mode; |
907 | ||
b04096ff | 908 | spi_set_drvdata(spi, qcaspi_devs); |
268be0f7 | 909 | |
cf9d0dcc | 910 | mac = of_get_mac_address(spi->dev.of_node); |
291ab06e SW |
911 | |
912 | if (mac) | |
913 | ether_addr_copy(qca->net_dev->dev_addr, mac); | |
914 | ||
915 | if (!is_valid_ether_addr(qca->net_dev->dev_addr)) { | |
916 | eth_hw_addr_random(qca->net_dev); | |
cf9d0dcc | 917 | dev_info(&spi->dev, "Using random MAC address: %pM\n", |
291ab06e SW |
918 | qca->net_dev->dev_addr); |
919 | } | |
920 | ||
921 | netif_carrier_off(qca->net_dev); | |
922 | ||
923 | if (!qcaspi_pluggable) { | |
924 | qcaspi_read_register(qca, SPI_REG_SIGNATURE, &signature); | |
925 | qcaspi_read_register(qca, SPI_REG_SIGNATURE, &signature); | |
926 | ||
927 | if (signature != QCASPI_GOOD_SIGNATURE) { | |
cf9d0dcc | 928 | dev_err(&spi->dev, "Invalid signature (0x%04X)\n", |
291ab06e SW |
929 | signature); |
930 | free_netdev(qcaspi_devs); | |
931 | return -EFAULT; | |
932 | } | |
933 | } | |
934 | ||
935 | if (register_netdev(qcaspi_devs)) { | |
cf9d0dcc | 936 | dev_info(&spi->dev, "Unable to register net device %s\n", |
291ab06e SW |
937 | qcaspi_devs->name); |
938 | free_netdev(qcaspi_devs); | |
939 | return -EFAULT; | |
940 | } | |
941 | ||
291ab06e SW |
942 | qcaspi_init_device_debugfs(qca); |
943 | ||
944 | return 0; | |
945 | } | |
946 | ||
947 | static int | |
cf9d0dcc | 948 | qca_spi_remove(struct spi_device *spi) |
291ab06e | 949 | { |
cf9d0dcc | 950 | struct net_device *qcaspi_devs = spi_get_drvdata(spi); |
291ab06e SW |
951 | struct qcaspi *qca = netdev_priv(qcaspi_devs); |
952 | ||
953 | qcaspi_remove_device_debugfs(qca); | |
954 | ||
955 | unregister_netdev(qcaspi_devs); | |
956 | free_netdev(qcaspi_devs); | |
957 | ||
958 | return 0; | |
959 | } | |
960 | ||
961 | static const struct spi_device_id qca_spi_id[] = { | |
962 | { "qca7000", 0 }, | |
963 | { /* sentinel */ } | |
964 | }; | |
965 | MODULE_DEVICE_TABLE(spi, qca_spi_id); | |
966 | ||
967 | static struct spi_driver qca_spi_driver = { | |
968 | .driver = { | |
969 | .name = QCASPI_DRV_NAME, | |
291ab06e SW |
970 | .of_match_table = qca_spi_of_match, |
971 | }, | |
972 | .id_table = qca_spi_id, | |
973 | .probe = qca_spi_probe, | |
974 | .remove = qca_spi_remove, | |
975 | }; | |
976 | module_spi_driver(qca_spi_driver); | |
977 | ||
978 | MODULE_DESCRIPTION("Qualcomm Atheros SPI Driver"); | |
979 | MODULE_AUTHOR("Qualcomm Atheros Communications"); | |
980 | MODULE_AUTHOR("Stefan Wahren <stefan.wahren@i2se.com>"); | |
981 | MODULE_LICENSE("Dual BSD/GPL"); | |
982 | MODULE_VERSION(QCASPI_DRV_VERSION); |