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[mirror_ubuntu-zesty-kernel.git] / drivers / net / ethernet / realtek / 8139cp.c
CommitLineData
1da177e4
LT		 1/* 8139cp.c: A Linux PCI Ethernet driver for the RealTek 8139C+ chips. */
2/*
3 Copyright 2001-2004 Jeff Garzik <jgarzik@pobox.com>
4
5 Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com) [tg3.c]
6 Copyright (C) 2000, 2001 David S. Miller (davem@redhat.com) [sungem.c]
7 Copyright 2001 Manfred Spraul [natsemi.c]
8 Copyright 1999-2001 by Donald Becker. [natsemi.c]
9 Written 1997-2001 by Donald Becker. [8139too.c]
10 Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. [acenic.c]
11
12 This software may be used and distributed according to the terms of
13 the GNU General Public License (GPL), incorporated herein by reference.
14 Drivers based on or derived from this code fall under the GPL and must
15 retain the authorship, copyright and license notice. This file is not
16 a complete program and may only be used when the entire operating
17 system is licensed under the GPL.
18
19 See the file COPYING in this distribution for more information.
20
21 Contributors:
f3b197ac 22
1da177e4
LT		 23 Wake-on-LAN support - Felipe Damasio <felipewd@terra.com.br>
24 PCI suspend/resume - Felipe Damasio <felipewd@terra.com.br>
25 LinkChg interrupt - Felipe Damasio <felipewd@terra.com.br>
f3b197ac 26
1da177e4
LT		 27 TODO:
28 * Test Tx checksumming thoroughly
1da177e4
LT		 29
30 Low priority TODO:
31 * Complete reset on PciErr
32 * Consider Rx interrupt mitigation using TimerIntr
33 * Investigate using skb->priority with h/w VLAN priority
34 * Investigate using High Priority Tx Queue with skb->priority
35 * Adjust Rx FIFO threshold and Max Rx DMA burst on Rx FIFO error
36 * Adjust Tx FIFO threshold and Max Tx DMA burst on Tx FIFO error
37 * Implement Tx software interrupt mitigation via
38 Tx descriptor bit
39 * The real minimum of CP_MIN_MTU is 4 bytes. However,
40 for this to be supported, one must(?) turn on packet padding.
41 * Support external MII transceivers (patch available)
42
43 NOTES:
44 * TX checksumming is considered experimental. It is off by
45 default, use ethtool to turn it on.
46
47 */
48
b4f18b3f
JP		 49#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
50
1da177e4 51#define DRV_NAME "8139cp"
d5b20697 52#define DRV_VERSION "1.3"
1da177e4
LT		 53#define DRV_RELDATE "Mar 22, 2004"
54
55
1da177e4 56#include <linux/module.h>
e21ba282 57#include <linux/moduleparam.h>
1da177e4
LT		 58#include <linux/kernel.h>
59#include <linux/compiler.h>
60#include <linux/netdevice.h>
61#include <linux/etherdevice.h>
62#include <linux/init.h>
a6b7a407 63#include <linux/interrupt.h>
1da177e4 64#include <linux/pci.h>
8662d061 65#include <linux/dma-mapping.h>
1da177e4
LT		 66#include <linux/delay.h>
67#include <linux/ethtool.h>
5a0e3ad6 68#include <linux/gfp.h>
1da177e4
LT		 69#include <linux/mii.h>
70#include <linux/if_vlan.h>
71#include <linux/crc32.h>
72#include <linux/in.h>
73#include <linux/ip.h>
74#include <linux/tcp.h>
75#include <linux/udp.h>
76#include <linux/cache.h>
77#include <asm/io.h>
78#include <asm/irq.h>
7c0f6ba6 79#include <linux/uaccess.h>
1da177e4 80
1da177e4
LT		 81/* These identify the driver base version and may not be removed. */
82static char version[] =
9cc40855 83DRV_NAME ": 10/100 PCI Ethernet driver v" DRV_VERSION " (" DRV_RELDATE ")\n";
1da177e4
LT		 84
85MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>");
86MODULE_DESCRIPTION("RealTek RTL-8139C+ series 10/100 PCI Ethernet driver");
a78d8927 87MODULE_VERSION(DRV_VERSION);
1da177e4
LT		 88MODULE_LICENSE("GPL");
89
90static int debug = -1;
e21ba282 91module_param(debug, int, 0);
1da177e4
LT		 92MODULE_PARM_DESC (debug, "8139cp: bitmapped message enable number");
93
94/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
95 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
96static int multicast_filter_limit = 32;
e21ba282 97module_param(multicast_filter_limit, int, 0);
1da177e4
LT		 98MODULE_PARM_DESC (multicast_filter_limit, "8139cp: maximum number of filtered multicast addresses");
99
1da177e4
LT		 100#define CP_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
101 NETIF_MSG_PROBE | \
102 NETIF_MSG_LINK)
103#define CP_NUM_STATS 14 /* struct cp_dma_stats, plus one */
104#define CP_STATS_SIZE 64 /* size in bytes of DMA stats block */
105#define CP_REGS_SIZE (0xff + 1)
106#define CP_REGS_VER 1 /* version 1 */
107#define CP_RX_RING_SIZE 64
108#define CP_TX_RING_SIZE 64
109#define CP_RING_BYTES \
110 ((sizeof(struct cp_desc) * CP_RX_RING_SIZE) + \
111 (sizeof(struct cp_desc) * CP_TX_RING_SIZE) + \
112 CP_STATS_SIZE)
113#define NEXT_TX(N) (((N) + 1) & (CP_TX_RING_SIZE - 1))
114#define NEXT_RX(N) (((N) + 1) & (CP_RX_RING_SIZE - 1))
115#define TX_BUFFS_AVAIL(CP) \
116 (((CP)->tx_tail <= (CP)->tx_head) ? \
117 (CP)->tx_tail + (CP_TX_RING_SIZE - 1) - (CP)->tx_head : \
118 (CP)->tx_tail - (CP)->tx_head - 1)
119
120#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
1da177e4
LT		 121#define CP_INTERNAL_PHY 32
122
123/* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
124#define RX_FIFO_THRESH 5 /* Rx buffer level before first PCI xfer. */
125#define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 */
126#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
127#define TX_EARLY_THRESH 256 /* Early Tx threshold, in bytes */
128
129/* Time in jiffies before concluding the transmitter is hung. */
130#define TX_TIMEOUT (6*HZ)
131
132/* hardware minimum and maximum for a single frame's data payload */
133#define CP_MIN_MTU 60 /* TODO: allow lower, but pad */
134#define CP_MAX_MTU 4096
135
136enum {
137 /* NIC register offsets */
138 MAC0 = 0x00, /* Ethernet hardware address. */
139 MAR0 = 0x08, /* Multicast filter. */
140 StatsAddr = 0x10, /* 64-bit start addr of 64-byte DMA stats blk */
141 TxRingAddr = 0x20, /* 64-bit start addr of Tx ring */
142 HiTxRingAddr = 0x28, /* 64-bit start addr of high priority Tx ring */
143 Cmd = 0x37, /* Command register */
144 IntrMask = 0x3C, /* Interrupt mask */
145 IntrStatus = 0x3E, /* Interrupt status */
146 TxConfig = 0x40, /* Tx configuration */
147 ChipVersion = 0x43, /* 8-bit chip version, inside TxConfig */
148 RxConfig = 0x44, /* Rx configuration */
149 RxMissed = 0x4C, /* 24 bits valid, write clears */
150 Cfg9346 = 0x50, /* EEPROM select/control; Cfg reg [un]lock */
151 Config1 = 0x52, /* Config1 */
152 Config3 = 0x59, /* Config3 */
153 Config4 = 0x5A, /* Config4 */
154 MultiIntr = 0x5C, /* Multiple interrupt select */
155 BasicModeCtrl = 0x62, /* MII BMCR */
156 BasicModeStatus = 0x64, /* MII BMSR */
157 NWayAdvert = 0x66, /* MII ADVERTISE */
158 NWayLPAR = 0x68, /* MII LPA */
159 NWayExpansion = 0x6A, /* MII Expansion */
41b97641 160 TxDmaOkLowDesc = 0x82, /* Low 16 bit address of a Tx descriptor. */
1da177e4
LT		 161 Config5 = 0xD8, /* Config5 */
162 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
163 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
164 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
165 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
166 RxRingAddr = 0xE4, /* 64-bit start addr of Rx ring */
167 TxThresh = 0xEC, /* Early Tx threshold */
168 OldRxBufAddr = 0x30, /* DMA address of Rx ring buffer (C mode) */
169 OldTSD0 = 0x10, /* DMA address of first Tx desc (C mode) */
170
171 /* Tx and Rx status descriptors */
172 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
173 RingEnd = (1 << 30), /* End of descriptor ring */
174 FirstFrag = (1 << 29), /* First segment of a packet */
175 LastFrag = (1 << 28), /* Final segment of a packet */
fcec3456
JG		 176 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
177 MSSShift = 16, /* MSS value position */
8b7a7048 178 MSSMask = 0x7ff, /* MSS value: 11 bits */
1da177e4
LT		 179 TxError = (1 << 23), /* Tx error summary */
180 RxError = (1 << 20), /* Rx error summary */
181 IPCS = (1 << 18), /* Calculate IP checksum */
182 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
183 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
184 TxVlanTag = (1 << 17), /* Add VLAN tag */
185 RxVlanTagged = (1 << 16), /* Rx VLAN tag available */
186 IPFail = (1 << 15), /* IP checksum failed */
187 UDPFail = (1 << 14), /* UDP/IP checksum failed */
188 TCPFail = (1 << 13), /* TCP/IP checksum failed */
189 NormalTxPoll = (1 << 6), /* One or more normal Tx packets to send */
190 PID1 = (1 << 17), /* 2 protocol id bits: 0==non-IP, */
191 PID0 = (1 << 16), /* 1==UDP/IP, 2==TCP/IP, 3==IP */
192 RxProtoTCP = 1,
193 RxProtoUDP = 2,
194 RxProtoIP = 3,
195 TxFIFOUnder = (1 << 25), /* Tx FIFO underrun */
196 TxOWC = (1 << 22), /* Tx Out-of-window collision */
197 TxLinkFail = (1 << 21), /* Link failed during Tx of packet */
198 TxMaxCol = (1 << 20), /* Tx aborted due to excessive collisions */
199 TxColCntShift = 16, /* Shift, to get 4-bit Tx collision cnt */
200 TxColCntMask = 0x01 | 0x02 | 0x04 | 0x08, /* 4-bit collision count */
201 RxErrFrame = (1 << 27), /* Rx frame alignment error */
202 RxMcast = (1 << 26), /* Rx multicast packet rcv'd */
203 RxErrCRC = (1 << 18), /* Rx CRC error */
204 RxErrRunt = (1 << 19), /* Rx error, packet < 64 bytes */
205 RxErrLong = (1 << 21), /* Rx error, packet > 4096 bytes */
206 RxErrFIFO = (1 << 22), /* Rx error, FIFO overflowed, pkt bad */
207
208 /* StatsAddr register */
209 DumpStats = (1 << 3), /* Begin stats dump */
210
211 /* RxConfig register */
212 RxCfgFIFOShift = 13, /* Shift, to get Rx FIFO thresh value */
213 RxCfgDMAShift = 8, /* Shift, to get Rx Max DMA value */
214 AcceptErr = 0x20, /* Accept packets with CRC errors */
215 AcceptRunt = 0x10, /* Accept runt (<64 bytes) packets */
216 AcceptBroadcast = 0x08, /* Accept broadcast packets */
217 AcceptMulticast = 0x04, /* Accept multicast packets */
218 AcceptMyPhys = 0x02, /* Accept pkts with our MAC as dest */
219 AcceptAllPhys = 0x01, /* Accept all pkts w/ physical dest */
220
221 /* IntrMask / IntrStatus registers */
222 PciErr = (1 << 15), /* System error on the PCI bus */
223 TimerIntr = (1 << 14), /* Asserted when TCTR reaches TimerInt value */
224 LenChg = (1 << 13), /* Cable length change */
225 SWInt = (1 << 8), /* Software-requested interrupt */
226 TxEmpty = (1 << 7), /* No Tx descriptors available */
227 RxFIFOOvr = (1 << 6), /* Rx FIFO Overflow */
228 LinkChg = (1 << 5), /* Packet underrun, or link change */
229 RxEmpty = (1 << 4), /* No Rx descriptors available */
230 TxErr = (1 << 3), /* Tx error */
231 TxOK = (1 << 2), /* Tx packet sent */
232 RxErr = (1 << 1), /* Rx error */
233 RxOK = (1 << 0), /* Rx packet received */
234 IntrResvd = (1 << 10), /* reserved, according to RealTek engineers,
235 but hardware likes to raise it */
236
237 IntrAll = PciErr | TimerIntr | LenChg | SWInt | TxEmpty |
238 RxFIFOOvr | LinkChg | RxEmpty | TxErr | TxOK |
239 RxErr | RxOK | IntrResvd,
240
241 /* C mode command register */
242 CmdReset = (1 << 4), /* Enable to reset; self-clearing */
243 RxOn = (1 << 3), /* Rx mode enable */
244 TxOn = (1 << 2), /* Tx mode enable */
245
246 /* C+ mode command register */
247 RxVlanOn = (1 << 6), /* Rx VLAN de-tagging enable */
248 RxChkSum = (1 << 5), /* Rx checksum offload enable */
249 PCIDAC = (1 << 4), /* PCI Dual Address Cycle (64-bit PCI) */
250 PCIMulRW = (1 << 3), /* Enable PCI read/write multiple */
251 CpRxOn = (1 << 1), /* Rx mode enable */
252 CpTxOn = (1 << 0), /* Tx mode enable */
253
254 /* Cfg9436 EEPROM control register */
255 Cfg9346_Lock = 0x00, /* Lock ConfigX/MII register access */
256 Cfg9346_Unlock = 0xC0, /* Unlock ConfigX/MII register access */
257
258 /* TxConfig register */
259 IFG = (1 << 25) | (1 << 24), /* standard IEEE interframe gap */
260 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
261
262 /* Early Tx Threshold register */
263 TxThreshMask = 0x3f, /* Mask bits 5-0 */
264 TxThreshMax = 2048, /* Max early Tx threshold */
265
266 /* Config1 register */
267 DriverLoaded = (1 << 5), /* Software marker, driver is loaded */
268 LWACT = (1 << 4), /* LWAKE active mode */
269 PMEnable = (1 << 0), /* Enable various PM features of chip */
270
271 /* Config3 register */
272 PARMEnable = (1 << 6), /* Enable auto-loading of PHY parms */
273 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
274 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
275
276 /* Config4 register */
277 LWPTN = (1 << 1), /* LWAKE Pattern */
278 LWPME = (1 << 4), /* LANWAKE vs PMEB */
279
280 /* Config5 register */
281 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
282 MWF = (1 << 5), /* Accept Multicast wakeup frame */
283 UWF = (1 << 4), /* Accept Unicast wakeup frame */
284 LANWake = (1 << 1), /* Enable LANWake signal */
285 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
286
287 cp_norx_intr_mask = PciErr | LinkChg | TxOK | TxErr | TxEmpty,
288 cp_rx_intr_mask = RxOK | RxErr | RxEmpty | RxFIFOOvr,
289 cp_intr_mask = cp_rx_intr_mask | cp_norx_intr_mask,
290};
291
292static const unsigned int cp_rx_config =
293 (RX_FIFO_THRESH << RxCfgFIFOShift) |
294 (RX_DMA_BURST << RxCfgDMAShift);
295
296struct cp_desc {
03233b90 297 __le32 opts1;
cf983019 298 __le32 opts2;
03233b90 299 __le64 addr;
1da177e4
LT		 300};
301
1da177e4 302struct cp_dma_stats {
03233b90
AV		 303 __le64 tx_ok;
304 __le64 rx_ok;
305 __le64 tx_err;
306 __le32 rx_err;
307 __le16 rx_fifo;
308 __le16 frame_align;
309 __le32 tx_ok_1col;
310 __le32 tx_ok_mcol;
311 __le64 rx_ok_phys;
312 __le64 rx_ok_bcast;
313 __le32 rx_ok_mcast;
314 __le16 tx_abort;
315 __le16 tx_underrun;
ba2d3587 316} __packed;
1da177e4
LT		 317
318struct cp_extra_stats {
319 unsigned long rx_frags;
320};
321
322struct cp_private {
323 void __iomem *regs;
324 struct net_device *dev;
325 spinlock_t lock;
326 u32 msg_enable;
327
bea3348e
SH		 328 struct napi_struct napi;
329
1da177e4
LT		 330 struct pci_dev *pdev;
331 u32 rx_config;
332 u16 cpcmd;
333
1da177e4 334 struct cp_extra_stats cp_stats;
1da177e4 335
d03d376d
FR		 336 unsigned rx_head ____cacheline_aligned;
337 unsigned rx_tail;
1da177e4 338 struct cp_desc *rx_ring;
0ba894d4 339 struct sk_buff *rx_skb[CP_RX_RING_SIZE];
1da177e4
LT		 340
341 unsigned tx_head ____cacheline_aligned;
342 unsigned tx_tail;
1da177e4 343 struct cp_desc *tx_ring;
48907e39 344 struct sk_buff *tx_skb[CP_TX_RING_SIZE];
7f4c6856 345 u32 tx_opts[CP_TX_RING_SIZE];
d03d376d
FR		 346
347 unsigned rx_buf_sz;
348 unsigned wol_enabled : 1; /* Is Wake-on-LAN enabled? */
1da177e4 349
d03d376d 350 dma_addr_t ring_dma;
1da177e4
LT		 351
352 struct mii_if_info mii_if;
353};
354
355#define cpr8(reg) readb(cp->regs + (reg))
356#define cpr16(reg) readw(cp->regs + (reg))
357#define cpr32(reg) readl(cp->regs + (reg))
358#define cpw8(reg,val) writeb((val), cp->regs + (reg))
359#define cpw16(reg,val) writew((val), cp->regs + (reg))
360#define cpw32(reg,val) writel((val), cp->regs + (reg))
361#define cpw8_f(reg,val) do { \
362 writeb((val), cp->regs + (reg)); \
363 readb(cp->regs + (reg)); \
364 } while (0)
365#define cpw16_f(reg,val) do { \
366 writew((val), cp->regs + (reg)); \
367 readw(cp->regs + (reg)); \
368 } while (0)
369#define cpw32_f(reg,val) do { \
370 writel((val), cp->regs + (reg)); \
371 readl(cp->regs + (reg)); \
372 } while (0)
373
374
375static void __cp_set_rx_mode (struct net_device *dev);
376static void cp_tx (struct cp_private *cp);
377static void cp_clean_rings (struct cp_private *cp);
7502cd10
SK		 378#ifdef CONFIG_NET_POLL_CONTROLLER
379static void cp_poll_controller(struct net_device *dev);
380#endif
722fdb33
PC		 381static int cp_get_eeprom_len(struct net_device *dev);
382static int cp_get_eeprom(struct net_device *dev,
383 struct ethtool_eeprom *eeprom, u8 *data);
384static int cp_set_eeprom(struct net_device *dev,
385 struct ethtool_eeprom *eeprom, u8 *data);
1da177e4 386
1da177e4
LT		 387static struct {
388 const char str[ETH_GSTRING_LEN];
389} ethtool_stats_keys[] = {
390 { "tx_ok" },
391 { "rx_ok" },
392 { "tx_err" },
393 { "rx_err" },
394 { "rx_fifo" },
395 { "frame_align" },
396 { "tx_ok_1col" },
397 { "tx_ok_mcol" },
398 { "rx_ok_phys" },
399 { "rx_ok_bcast" },
400 { "rx_ok_mcast" },
401 { "tx_abort" },
402 { "tx_underrun" },
403 { "rx_frags" },
404};
405
406
1da177e4
LT		 407static inline void cp_set_rxbufsize (struct cp_private *cp)
408{
409 unsigned int mtu = cp->dev->mtu;
f3b197ac 410
1da177e4
LT		 411 if (mtu > ETH_DATA_LEN)
412 /* MTU + ethernet header + FCS + optional VLAN tag */
413 cp->rx_buf_sz = mtu + ETH_HLEN + 8;
414 else
415 cp->rx_buf_sz = PKT_BUF_SZ;
416}
417
418static inline void cp_rx_skb (struct cp_private *cp, struct sk_buff *skb,
419 struct cp_desc *desc)
420{
6864ddb2 421 u32 opts2 = le32_to_cpu(desc->opts2);
422
1da177e4
LT		 423 skb->protocol = eth_type_trans (skb, cp->dev);
424
237225f7
PZ		 425 cp->dev->stats.rx_packets++;
426 cp->dev->stats.rx_bytes += skb->len;
1da177e4 427
6864ddb2 428 if (opts2 & RxVlanTagged)
86a9bad3 429 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
6864ddb2 430
431 napi_gro_receive(&cp->napi, skb);
1da177e4
LT		 432}
433
434static void cp_rx_err_acct (struct cp_private *cp, unsigned rx_tail,
435 u32 status, u32 len)
436{
b4f18b3f
JP		 437 netif_dbg(cp, rx_err, cp->dev, "rx err, slot %d status 0x%x len %d\n",
438 rx_tail, status, len);
237225f7 439 cp->dev->stats.rx_errors++;
1da177e4 440 if (status & RxErrFrame)
237225f7 441 cp->dev->stats.rx_frame_errors++;
1da177e4 442 if (status & RxErrCRC)
237225f7 443 cp->dev->stats.rx_crc_errors++;
1da177e4 444 if ((status & RxErrRunt) || (status & RxErrLong))
237225f7 445 cp->dev->stats.rx_length_errors++;
1da177e4 446 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag))
237225f7 447 cp->dev->stats.rx_length_errors++;
1da177e4 448 if (status & RxErrFIFO)
237225f7 449 cp->dev->stats.rx_fifo_errors++;
1da177e4
LT		 450}
451
452static inline unsigned int cp_rx_csum_ok (u32 status)
453{
454 unsigned int protocol = (status >> 16) & 0x3;
f3b197ac 455
24b7ea9f
SW		 456 if (((protocol == RxProtoTCP) && !(status & TCPFail)) ||
457 ((protocol == RxProtoUDP) && !(status & UDPFail)))
1da177e4 458 return 1;
24b7ea9f
SW		 459 else
460 return 0;
1da177e4
LT		 461}
462
bea3348e 463static int cp_rx_poll(struct napi_struct *napi, int budget)
1da177e4 464{
bea3348e
SH		 465 struct cp_private *cp = container_of(napi, struct cp_private, napi);
466 struct net_device *dev = cp->dev;
467 unsigned int rx_tail = cp->rx_tail;
468 int rx;
1da177e4 469
1da177e4 470 rx = 0;
b628d611 471rx_status_loop:
1da177e4
LT		 472 cpw16(IntrStatus, cp_rx_intr_mask);
473
50ff44be 474 while (rx < budget) {
1da177e4 475 u32 status, len;
cf3c4c03 476 dma_addr_t mapping, new_mapping;
1da177e4
LT		 477 struct sk_buff *skb, *new_skb;
478 struct cp_desc *desc;
839d1624 479 const unsigned buflen = cp->rx_buf_sz;
1da177e4 480
0ba894d4 481 skb = cp->rx_skb[rx_tail];
5d9428de 482 BUG_ON(!skb);
1da177e4
LT		 483
484 desc = &cp->rx_ring[rx_tail];
485 status = le32_to_cpu(desc->opts1);
486 if (status & DescOwn)
487 break;
488
489 len = (status & 0x1fff) - 4;
3598b57b 490 mapping = le64_to_cpu(desc->addr);
1da177e4
LT		 491
492 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag)) {
493 /* we don't support incoming fragmented frames.
494 * instead, we attempt to ensure that the
495 * pre-allocated RX skbs are properly sized such
496 * that RX fragments are never encountered
497 */
498 cp_rx_err_acct(cp, rx_tail, status, len);
237225f7 499 dev->stats.rx_dropped++;
1da177e4
LT		 500 cp->cp_stats.rx_frags++;
501 goto rx_next;
502 }
503
504 if (status & (RxError | RxErrFIFO)) {
505 cp_rx_err_acct(cp, rx_tail, status, len);
506 goto rx_next;
507 }
508
b4f18b3f
JP		 509 netif_dbg(cp, rx_status, dev, "rx slot %d status 0x%x len %d\n",
510 rx_tail, status, len);
1da177e4 511
e2338f86 512 new_skb = napi_alloc_skb(napi, buflen);
1da177e4 513 if (!new_skb) {
237225f7 514 dev->stats.rx_dropped++;
1da177e4
LT		 515 goto rx_next;
516 }
517
cf3c4c03
NH		 518 new_mapping = dma_map_single(&cp->pdev->dev, new_skb->data, buflen,
519 PCI_DMA_FROMDEVICE);
520 if (dma_mapping_error(&cp->pdev->dev, new_mapping)) {
521 dev->stats.rx_dropped++;
d06f5187 522 kfree_skb(new_skb);
cf3c4c03
NH		 523 goto rx_next;
524 }
525
6cc92cdd 526 dma_unmap_single(&cp->pdev->dev, mapping,
1da177e4
LT		 527 buflen, PCI_DMA_FROMDEVICE);
528
529 /* Handle checksum offloading for incoming packets. */
530 if (cp_rx_csum_ok(status))
531 skb->ip_summed = CHECKSUM_UNNECESSARY;
532 else
bc8acf2c 533 skb_checksum_none_assert(skb);
1da177e4
LT		 534
535 skb_put(skb, len);
536
0ba894d4 537 cp->rx_skb[rx_tail] = new_skb;
1da177e4
LT		 538
539 cp_rx_skb(cp, skb, desc);
540 rx++;
cf3c4c03 541 mapping = new_mapping;
1da177e4
LT		 542
543rx_next:
544 cp->rx_ring[rx_tail].opts2 = 0;
545 cp->rx_ring[rx_tail].addr = cpu_to_le64(mapping);
546 if (rx_tail == (CP_RX_RING_SIZE - 1))
547 desc->opts1 = cpu_to_le32(DescOwn | RingEnd |
548 cp->rx_buf_sz);
549 else
550 desc->opts1 = cpu_to_le32(DescOwn | cp->rx_buf_sz);
551 rx_tail = NEXT_RX(rx_tail);
1da177e4
LT		 552 }
553
554 cp->rx_tail = rx_tail;
555
1da177e4
LT		 556 /* if we did not reach work limit, then we're done with
557 * this round of polling
558 */
bea3348e 559 if (rx < budget) {
d15e9c4d
FR		 560 unsigned long flags;
561
1da177e4
LT		 562 if (cpr16(IntrStatus) & cp_rx_intr_mask)
563 goto rx_status_loop;
564
2e71a6f8 565 napi_gro_flush(napi, false);
bea3348e 566 spin_lock_irqsave(&cp->lock, flags);
288379f0 567 __napi_complete(napi);
349124a0 568 cpw16_f(IntrMask, cp_intr_mask);
bea3348e 569 spin_unlock_irqrestore(&cp->lock, flags);
1da177e4
LT		 570 }
571
bea3348e 572 return rx;
1da177e4
LT		 573}
574
7d12e780 575static irqreturn_t cp_interrupt (int irq, void *dev_instance)
1da177e4
LT		 576{
577 struct net_device *dev = dev_instance;
578 struct cp_private *cp;
83c34fd0 579 int handled = 0;
1da177e4
LT		 580 u16 status;
581
582 if (unlikely(dev == NULL))
583 return IRQ_NONE;
584 cp = netdev_priv(dev);
585
83c34fd0
JG		 586 spin_lock(&cp->lock);
587
1da177e4
LT		 588 status = cpr16(IntrStatus);
589 if (!status || (status == 0xFFFF))
83c34fd0
JG		 590 goto out_unlock;
591
592 handled = 1;
1da177e4 593
b4f18b3f
JP		 594 netif_dbg(cp, intr, dev, "intr, status %04x cmd %02x cpcmd %04x\n",
595 status, cpr8(Cmd), cpr16(CpCmd));
1da177e4
LT		 596
597 cpw16(IntrStatus, status & ~cp_rx_intr_mask);
598
1da177e4
LT		 599 /* close possible race's with dev_close */
600 if (unlikely(!netif_running(dev))) {
601 cpw16(IntrMask, 0);
83c34fd0 602 goto out_unlock;
1da177e4
LT		 603 }
604
605 if (status & (RxOK | RxErr | RxEmpty | RxFIFOOvr))
288379f0 606 if (napi_schedule_prep(&cp->napi)) {
1da177e4 607 cpw16_f(IntrMask, cp_norx_intr_mask);
288379f0 608 __napi_schedule(&cp->napi);
1da177e4
LT		 609 }
610
611 if (status & (TxOK | TxErr | TxEmpty | SWInt))
612 cp_tx(cp);
613 if (status & LinkChg)
2501f843 614 mii_check_media(&cp->mii_if, netif_msg_link(cp), false);
1da177e4 615
1da177e4
LT		 616
617 if (status & PciErr) {
618 u16 pci_status;
619
620 pci_read_config_word(cp->pdev, PCI_STATUS, &pci_status);
621 pci_write_config_word(cp->pdev, PCI_STATUS, pci_status);
b4f18b3f
JP		 622 netdev_err(dev, "PCI bus error, status=%04x, PCI status=%04x\n",
623 status, pci_status);
1da177e4
LT		 624
625 /* TODO: reset hardware */
626 }
627
83c34fd0
JG		 628out_unlock:
629 spin_unlock(&cp->lock);
630
631 return IRQ_RETVAL(handled);
1da177e4
LT		 632}
633
7502cd10
SK		 634#ifdef CONFIG_NET_POLL_CONTROLLER
635/*
636 * Polling receive - used by netconsole and other diagnostic tools
637 * to allow network i/o with interrupts disabled.
638 */
639static void cp_poll_controller(struct net_device *dev)
640{
a69afe32
FR		 641 struct cp_private *cp = netdev_priv(dev);
642 const int irq = cp->pdev->irq;
643
644 disable_irq(irq);
645 cp_interrupt(irq, dev);
646 enable_irq(irq);
7502cd10
SK		 647}
648#endif
649
1da177e4
LT		 650static void cp_tx (struct cp_private *cp)
651{
652 unsigned tx_head = cp->tx_head;
653 unsigned tx_tail = cp->tx_tail;
871f0d4c 654 unsigned bytes_compl = 0, pkts_compl = 0;
1da177e4
LT		 655
656 while (tx_tail != tx_head) {
3598b57b 657 struct cp_desc *txd = cp->tx_ring + tx_tail;
1da177e4
LT		 658 struct sk_buff *skb;
659 u32 status;
660
661 rmb();
3598b57b 662 status = le32_to_cpu(txd->opts1);
1da177e4
LT		 663 if (status & DescOwn)
664 break;
665
48907e39 666 skb = cp->tx_skb[tx_tail];
5d9428de 667 BUG_ON(!skb);
1da177e4 668
6cc92cdd 669 dma_unmap_single(&cp->pdev->dev, le64_to_cpu(txd->addr),
7f4c6856 670 cp->tx_opts[tx_tail] & 0xffff,
48907e39 671 PCI_DMA_TODEVICE);
1da177e4
LT		 672
673 if (status & LastFrag) {
674 if (status & (TxError | TxFIFOUnder)) {
b4f18b3f
JP		 675 netif_dbg(cp, tx_err, cp->dev,
676 "tx err, status 0x%x\n", status);
237225f7 677 cp->dev->stats.tx_errors++;
1da177e4 678 if (status & TxOWC)
237225f7 679 cp->dev->stats.tx_window_errors++;
1da177e4 680 if (status & TxMaxCol)
237225f7 681 cp->dev->stats.tx_aborted_errors++;
1da177e4 682 if (status & TxLinkFail)
237225f7 683 cp->dev->stats.tx_carrier_errors++;
1da177e4 684 if (status & TxFIFOUnder)
237225f7 685 cp->dev->stats.tx_fifo_errors++;
1da177e4 686 } else {
237225f7 687 cp->dev->stats.collisions +=
1da177e4 688 ((status >> TxColCntShift) & TxColCntMask);
237225f7
PZ		 689 cp->dev->stats.tx_packets++;
690 cp->dev->stats.tx_bytes += skb->len;
b4f18b3f
JP		 691 netif_dbg(cp, tx_done, cp->dev,
692 "tx done, slot %d\n", tx_tail);
1da177e4 693 }
7fe0ee09
YY		 694 bytes_compl += skb->len;
695 pkts_compl++;
1da177e4
LT		 696 dev_kfree_skb_irq(skb);
697 }
698
48907e39 699 cp->tx_skb[tx_tail] = NULL;
1da177e4
LT		 700
701 tx_tail = NEXT_TX(tx_tail);
702 }
703
704 cp->tx_tail = tx_tail;
705
871f0d4c 706 netdev_completed_queue(cp->dev, pkts_compl, bytes_compl);
1da177e4
LT		 707 if (TX_BUFFS_AVAIL(cp) > (MAX_SKB_FRAGS + 1))
708 netif_wake_queue(cp->dev);
709}
710
6864ddb2 711static inline u32 cp_tx_vlan_tag(struct sk_buff *skb)
712{
df8a39de
JP		 713 return skb_vlan_tag_present(skb) ?
714 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
6864ddb2 715}
716
cf3c4c03
NH		 717static void unwind_tx_frag_mapping(struct cp_private *cp, struct sk_buff *skb,
718 int first, int entry_last)
719{
720 int frag, index;
721 struct cp_desc *txd;
722 skb_frag_t *this_frag;
723 for (frag = 0; frag+first < entry_last; frag++) {
724 index = first+frag;
725 cp->tx_skb[index] = NULL;
726 txd = &cp->tx_ring[index];
727 this_frag = &skb_shinfo(skb)->frags[frag];
728 dma_unmap_single(&cp->pdev->dev, le64_to_cpu(txd->addr),
729 skb_frag_size(this_frag), PCI_DMA_TODEVICE);
730 }
731}
732
61357325
SH		 733static netdev_tx_t cp_start_xmit (struct sk_buff *skb,
734 struct net_device *dev)
1da177e4
LT		 735{
736 struct cp_private *cp = netdev_priv(dev);
737 unsigned entry;
0a5aeee0 738 u32 eor, opts1;
553af567 739 unsigned long intr_flags;
6864ddb2 740 __le32 opts2;
fcec3456 741 int mss = 0;
1da177e4 742
553af567 743 spin_lock_irqsave(&cp->lock, intr_flags);
1da177e4
LT		 744
745 /* This is a hard error, log it. */
746 if (TX_BUFFS_AVAIL(cp) <= (skb_shinfo(skb)->nr_frags + 1)) {
747 netif_stop_queue(dev);
553af567 748 spin_unlock_irqrestore(&cp->lock, intr_flags);
b4f18b3f 749 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
5b548140 750 return NETDEV_TX_BUSY;
1da177e4
LT		 751 }
752
1da177e4
LT		 753 entry = cp->tx_head;
754 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
044a890c 755 mss = skb_shinfo(skb)->gso_size;
fcec3456 756
8b7a7048
DW		 757 if (mss > MSSMask) {
758 WARN_ONCE(1, "Net bug: GSO size %d too large for 8139CP\n",
759 mss);
760 goto out_dma_error;
761 }
762
6864ddb2 763 opts2 = cpu_to_le32(cp_tx_vlan_tag(skb));
0a5aeee0
DW		 764 opts1 = DescOwn;
765 if (mss)
8b7a7048 766 opts1 |= LargeSend | (mss << MSSShift);
0a5aeee0
DW		 767 else if (skb->ip_summed == CHECKSUM_PARTIAL) {
768 const struct iphdr *ip = ip_hdr(skb);
769 if (ip->protocol == IPPROTO_TCP)
770 opts1 |= IPCS | TCPCS;
771 else if (ip->protocol == IPPROTO_UDP)
772 opts1 |= IPCS | UDPCS;
773 else {
774 WARN_ONCE(1,
775 "Net bug: asked to checksum invalid Legacy IP packet\n");
776 goto out_dma_error;
777 }
778 }
6864ddb2 779
1da177e4
LT		 780 if (skb_shinfo(skb)->nr_frags == 0) {
781 struct cp_desc *txd = &cp->tx_ring[entry];
782 u32 len;
783 dma_addr_t mapping;
784
785 len = skb->len;
6cc92cdd 786 mapping = dma_map_single(&cp->pdev->dev, skb->data, len, PCI_DMA_TODEVICE);
cf3c4c03
NH		 787 if (dma_mapping_error(&cp->pdev->dev, mapping))
788 goto out_dma_error;
789
6864ddb2 790 txd->opts2 = opts2;
1da177e4
LT		 791 txd->addr = cpu_to_le64(mapping);
792 wmb();
793
0a5aeee0 794 opts1 |= eor | len | FirstFrag | LastFrag;
fcec3456 795
0a5aeee0 796 txd->opts1 = cpu_to_le32(opts1);
1da177e4
LT		 797 wmb();
798
48907e39 799 cp->tx_skb[entry] = skb;
7f4c6856 800 cp->tx_opts[entry] = opts1;
26b0bad6
DW		 801 netif_dbg(cp, tx_queued, cp->dev, "tx queued, slot %d, skblen %d\n",
802 entry, skb->len);
1da177e4
LT		 803 } else {
804 struct cp_desc *txd;
a3b80404 805 u32 first_len, first_eor, ctrl;
1da177e4
LT		 806 dma_addr_t first_mapping;
807 int frag, first_entry = entry;
1da177e4
LT		 808
809 /* We must give this initial chunk to the device last.
810 * Otherwise we could race with the device.
811 */
812 first_eor = eor;
813 first_len = skb_headlen(skb);
6cc92cdd 814 first_mapping = dma_map_single(&cp->pdev->dev, skb->data,
1da177e4 815 first_len, PCI_DMA_TODEVICE);
cf3c4c03
NH		 816 if (dma_mapping_error(&cp->pdev->dev, first_mapping))
817 goto out_dma_error;
818
48907e39 819 cp->tx_skb[entry] = skb;
1da177e4
LT		 820
821 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
9e903e08 822 const skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
1da177e4 823 u32 len;
1da177e4
LT		 824 dma_addr_t mapping;
825
26b0bad6
DW		 826 entry = NEXT_TX(entry);
827
9e903e08 828 len = skb_frag_size(this_frag);
6cc92cdd 829 mapping = dma_map_single(&cp->pdev->dev,
deb8a069 830 skb_frag_address(this_frag),
1da177e4 831 len, PCI_DMA_TODEVICE);
cf3c4c03
NH		 832 if (dma_mapping_error(&cp->pdev->dev, mapping)) {
833 unwind_tx_frag_mapping(cp, skb, first_entry, entry);
834 goto out_dma_error;
835 }
836
1da177e4
LT		 837 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
838
0a5aeee0 839 ctrl = opts1 | eor | len;
1da177e4
LT		 840
841 if (frag == skb_shinfo(skb)->nr_frags - 1)
842 ctrl |= LastFrag;
843
844 txd = &cp->tx_ring[entry];
6864ddb2 845 txd->opts2 = opts2;
1da177e4
LT		 846 txd->addr = cpu_to_le64(mapping);
847 wmb();
848
849 txd->opts1 = cpu_to_le32(ctrl);
850 wmb();
7f4c6856
DW		 851
852 cp->tx_opts[entry] = ctrl;
48907e39 853 cp->tx_skb[entry] = skb;
1da177e4
LT		 854 }
855
856 txd = &cp->tx_ring[first_entry];
6864ddb2 857 txd->opts2 = opts2;
1da177e4
LT		 858 txd->addr = cpu_to_le64(first_mapping);
859 wmb();
860
0a5aeee0 861 ctrl = opts1 | first_eor | first_len | FirstFrag;
a3b80404 862 txd->opts1 = cpu_to_le32(ctrl);
1da177e4 863 wmb();
26b0bad6 864
7f4c6856 865 cp->tx_opts[first_entry] = ctrl;
26b0bad6
DW		 866 netif_dbg(cp, tx_queued, cp->dev, "tx queued, slots %d-%d, skblen %d\n",
867 first_entry, entry, skb->len);
1da177e4 868 }
26b0bad6 869 cp->tx_head = NEXT_TX(entry);
871f0d4c
DW		 870
871 netdev_sent_queue(dev, skb->len);
1da177e4
LT		 872 if (TX_BUFFS_AVAIL(cp) <= (MAX_SKB_FRAGS + 1))
873 netif_stop_queue(dev);
874
cf3c4c03 875out_unlock:
553af567 876 spin_unlock_irqrestore(&cp->lock, intr_flags);
1da177e4
LT		 877
878 cpw8(TxPoll, NormalTxPoll);
1da177e4 879
6ed10654 880 return NETDEV_TX_OK;
cf3c4c03 881out_dma_error:
508f81d5 882 dev_kfree_skb_any(skb);
cf3c4c03
NH		 883 cp->dev->stats.tx_dropped++;
884 goto out_unlock;
1da177e4
LT		 885}
886
887/* Set or clear the multicast filter for this adaptor.
888 This routine is not state sensitive and need not be SMP locked. */
889
890static void __cp_set_rx_mode (struct net_device *dev)
891{
892 struct cp_private *cp = netdev_priv(dev);
893 u32 mc_filter[2]; /* Multicast hash filter */
a56ed41d 894 int rx_mode;
1da177e4
LT		 895
896 /* Note: do not reorder, GCC is clever about common statements. */
897 if (dev->flags & IFF_PROMISC) {
898 /* Unconditionally log net taps. */
1da177e4
LT		 899 rx_mode =
900 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
901 AcceptAllPhys;
902 mc_filter[1] = mc_filter[0] = 0xffffffff;
a56ed41d 903 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
8e95a202 904 (dev->flags & IFF_ALLMULTI)) {
1da177e4
LT		 905 /* Too many to filter perfectly -- accept all multicasts. */
906 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
907 mc_filter[1] = mc_filter[0] = 0xffffffff;
908 } else {
22bedad3 909 struct netdev_hw_addr *ha;
1da177e4
LT		 910 rx_mode = AcceptBroadcast | AcceptMyPhys;
911 mc_filter[1] = mc_filter[0] = 0;
22bedad3
JP		 912 netdev_for_each_mc_addr(ha, dev) {
913 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
1da177e4
LT		 914
915 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
916 rx_mode |= AcceptMulticast;
917 }
918 }
919
920 /* We can safely update without stopping the chip. */
f872b237
JW		 921 cp->rx_config = cp_rx_config | rx_mode;
922 cpw32_f(RxConfig, cp->rx_config);
923
1da177e4
LT		 924 cpw32_f (MAR0 + 0, mc_filter[0]);
925 cpw32_f (MAR0 + 4, mc_filter[1]);
926}
927
928static void cp_set_rx_mode (struct net_device *dev)
929{
930 unsigned long flags;
931 struct cp_private *cp = netdev_priv(dev);
932
933 spin_lock_irqsave (&cp->lock, flags);
934 __cp_set_rx_mode(dev);
935 spin_unlock_irqrestore (&cp->lock, flags);
936}
937
938static void __cp_get_stats(struct cp_private *cp)
939{
940 /* only lower 24 bits valid; write any value to clear */
237225f7 941 cp->dev->stats.rx_missed_errors += (cpr32 (RxMissed) & 0xffffff);
1da177e4
LT		 942 cpw32 (RxMissed, 0);
943}
944
945static struct net_device_stats *cp_get_stats(struct net_device *dev)
946{
947 struct cp_private *cp = netdev_priv(dev);
948 unsigned long flags;
949
950 /* The chip only need report frame silently dropped. */
951 spin_lock_irqsave(&cp->lock, flags);
952 if (netif_running(dev) && netif_device_present(dev))
953 __cp_get_stats(cp);
954 spin_unlock_irqrestore(&cp->lock, flags);
955
237225f7 956 return &dev->stats;
1da177e4
LT		 957}
958
959static void cp_stop_hw (struct cp_private *cp)
960{
961 cpw16(IntrStatus, ~(cpr16(IntrStatus)));
962 cpw16_f(IntrMask, 0);
963 cpw8(Cmd, 0);
964 cpw16_f(CpCmd, 0);
965 cpw16_f(IntrStatus, ~(cpr16(IntrStatus)));
966
967 cp->rx_tail = 0;
968 cp->tx_head = cp->tx_tail = 0;
871f0d4c
DW		 969
970 netdev_reset_queue(cp->dev);
1da177e4
LT		 971}
972
973static void cp_reset_hw (struct cp_private *cp)
974{
975 unsigned work = 1000;
976
977 cpw8(Cmd, CmdReset);
978
979 while (work--) {
980 if (!(cpr8(Cmd) & CmdReset))
981 return;
982
3173c890 983 schedule_timeout_uninterruptible(10);
1da177e4
LT		 984 }
985
b4f18b3f 986 netdev_err(cp->dev, "hardware reset timeout\n");
1da177e4
LT		 987}
988
989static inline void cp_start_hw (struct cp_private *cp)
990{
a9dbe40f
DW		 991 dma_addr_t ring_dma;
992
1da177e4 993 cpw16(CpCmd, cp->cpcmd);
a9dbe40f
DW		 994
995 /*
996 * These (at least TxRingAddr) need to be configured after the
997 * corresponding bits in CpCmd are enabled. Datasheet v1.6 §6.33
998 * (C+ Command Register) recommends that these and more be configured
999 * *after* the [RT]xEnable bits in CpCmd are set. And on some hardware
1000 * it's been observed that the TxRingAddr is actually reset to garbage
1001 * when C+ mode Tx is enabled in CpCmd.
1002 */
1003 cpw32_f(HiTxRingAddr, 0);
1004 cpw32_f(HiTxRingAddr + 4, 0);
1005
1006 ring_dma = cp->ring_dma;
1007 cpw32_f(RxRingAddr, ring_dma & 0xffffffff);
1008 cpw32_f(RxRingAddr + 4, (ring_dma >> 16) >> 16);
1009
1010 ring_dma += sizeof(struct cp_desc) * CP_RX_RING_SIZE;
1011 cpw32_f(TxRingAddr, ring_dma & 0xffffffff);
1012 cpw32_f(TxRingAddr + 4, (ring_dma >> 16) >> 16);
1013
1014 /*
1015 * Strictly speaking, the datasheet says this should be enabled
1016 * *before* setting the descriptor addresses. But what, then, would
1017 * prevent it from doing DMA to random unconfigured addresses?
1018 * This variant appears to work fine.
1019 */
1da177e4 1020 cpw8(Cmd, RxOn | TxOn);
871f0d4c
DW		 1021
1022 netdev_reset_queue(cp->dev);
1da177e4
LT		 1023}
1024
a8c9cb10
JW		 1025static void cp_enable_irq(struct cp_private *cp)
1026{
1027 cpw16_f(IntrMask, cp_intr_mask);
1028}
1029
1da177e4
LT		 1030static void cp_init_hw (struct cp_private *cp)
1031{
1032 struct net_device *dev = cp->dev;
1da177e4
LT		 1033
1034 cp_reset_hw(cp);
1035
1036 cpw8_f (Cfg9346, Cfg9346_Unlock);
1037
1038 /* Restore our idea of the MAC address. */
03233b90
AV		 1039 cpw32_f (MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0)));
1040 cpw32_f (MAC0 + 4, le32_to_cpu (*(__le32 *) (dev->dev_addr + 4)));
1da177e4
LT		 1041
1042 cp_start_hw(cp);
1043 cpw8(TxThresh, 0x06); /* XXX convert magic num to a constant */
1044
1045 __cp_set_rx_mode(dev);
1046 cpw32_f (TxConfig, IFG | (TX_DMA_BURST << TxDMAShift));
1047
1048 cpw8(Config1, cpr8(Config1) | DriverLoaded | PMEnable);
1049 /* Disable Wake-on-LAN. Can be turned on with ETHTOOL_SWOL */
1050 cpw8(Config3, PARMEnable);
1051 cp->wol_enabled = 0;
1052
f3b197ac 1053 cpw8(Config5, cpr8(Config5) & PMEStatus);
1da177e4 1054
1da177e4
LT		 1055 cpw16(MultiIntr, 0);
1056
1da177e4
LT		 1057 cpw8_f(Cfg9346, Cfg9346_Lock);
1058}
1059
a52be1cb 1060static int cp_refill_rx(struct cp_private *cp)
1da177e4 1061{
a52be1cb 1062 struct net_device *dev = cp->dev;
1da177e4
LT		 1063 unsigned i;
1064
1065 for (i = 0; i < CP_RX_RING_SIZE; i++) {
1066 struct sk_buff *skb;
3598b57b 1067 dma_addr_t mapping;
1da177e4 1068
89d71a66 1069 skb = netdev_alloc_skb_ip_align(dev, cp->rx_buf_sz);
1da177e4
LT		 1070 if (!skb)
1071 goto err_out;
1072
6cc92cdd
JG		 1073 mapping = dma_map_single(&cp->pdev->dev, skb->data,
1074 cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
cf3c4c03
NH		 1075 if (dma_mapping_error(&cp->pdev->dev, mapping)) {
1076 kfree_skb(skb);
1077 goto err_out;
1078 }
0ba894d4 1079 cp->rx_skb[i] = skb;
1da177e4
LT		 1080
1081 cp->rx_ring[i].opts2 = 0;
3598b57b 1082 cp->rx_ring[i].addr = cpu_to_le64(mapping);
1da177e4
LT		 1083 if (i == (CP_RX_RING_SIZE - 1))
1084 cp->rx_ring[i].opts1 =
1085 cpu_to_le32(DescOwn | RingEnd | cp->rx_buf_sz);
1086 else
1087 cp->rx_ring[i].opts1 =
1088 cpu_to_le32(DescOwn | cp->rx_buf_sz);
1089 }
1090
1091 return 0;
1092
1093err_out:
1094 cp_clean_rings(cp);
1095 return -ENOMEM;
1096}
1097
576cfa93
FR		 1098static void cp_init_rings_index (struct cp_private *cp)
1099{
1100 cp->rx_tail = 0;
1101 cp->tx_head = cp->tx_tail = 0;
1102}
1103
1da177e4
LT		 1104static int cp_init_rings (struct cp_private *cp)
1105{
1106 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1107 cp->tx_ring[CP_TX_RING_SIZE - 1].opts1 = cpu_to_le32(RingEnd);
7f4c6856 1108 memset(cp->tx_opts, 0, sizeof(cp->tx_opts));
1da177e4 1109
576cfa93 1110 cp_init_rings_index(cp);
1da177e4
LT		 1111
1112 return cp_refill_rx (cp);
1113}
1114
1115static int cp_alloc_rings (struct cp_private *cp)
1116{
892a925e 1117 struct device *d = &cp->pdev->dev;
1da177e4 1118 void *mem;
892a925e 1119 int rc;
1da177e4 1120
892a925e 1121 mem = dma_alloc_coherent(d, CP_RING_BYTES, &cp->ring_dma, GFP_KERNEL);
1da177e4
LT		 1122 if (!mem)
1123 return -ENOMEM;
1124
1125 cp->rx_ring = mem;
1126 cp->tx_ring = &cp->rx_ring[CP_RX_RING_SIZE];
1127
892a925e 1128 rc = cp_init_rings(cp);
1129 if (rc < 0)
1130 dma_free_coherent(d, CP_RING_BYTES, cp->rx_ring, cp->ring_dma);
1131
1132 return rc;
1da177e4
LT		 1133}
1134
1135static void cp_clean_rings (struct cp_private *cp)
1136{
3598b57b 1137 struct cp_desc *desc;
1da177e4
LT		 1138 unsigned i;
1139
1da177e4 1140 for (i = 0; i < CP_RX_RING_SIZE; i++) {
0ba894d4 1141 if (cp->rx_skb[i]) {
3598b57b 1142 desc = cp->rx_ring + i;
6cc92cdd 1143 dma_unmap_single(&cp->pdev->dev,le64_to_cpu(desc->addr),
1da177e4 1144 cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
fc27bd11 1145 dev_kfree_skb_any(cp->rx_skb[i]);
1da177e4
LT		 1146 }
1147 }
1148
1149 for (i = 0; i < CP_TX_RING_SIZE; i++) {
48907e39
FR		 1150 if (cp->tx_skb[i]) {
1151 struct sk_buff *skb = cp->tx_skb[i];
5734418d 1152
3598b57b 1153 desc = cp->tx_ring + i;
6cc92cdd 1154 dma_unmap_single(&cp->pdev->dev,le64_to_cpu(desc->addr),
48907e39
FR		 1155 le32_to_cpu(desc->opts1) & 0xffff,
1156 PCI_DMA_TODEVICE);
3598b57b 1157 if (le32_to_cpu(desc->opts1) & LastFrag)
fc27bd11 1158 dev_kfree_skb_any(skb);
237225f7 1159 cp->dev->stats.tx_dropped++;
1da177e4
LT		 1160 }
1161 }
98962baa 1162 netdev_reset_queue(cp->dev);
1da177e4 1163
5734418d
FR		 1164 memset(cp->rx_ring, 0, sizeof(struct cp_desc) * CP_RX_RING_SIZE);
1165 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
7f4c6856 1166 memset(cp->tx_opts, 0, sizeof(cp->tx_opts));
5734418d 1167
0ba894d4 1168 memset(cp->rx_skb, 0, sizeof(struct sk_buff *) * CP_RX_RING_SIZE);
48907e39 1169 memset(cp->tx_skb, 0, sizeof(struct sk_buff *) * CP_TX_RING_SIZE);
1da177e4
LT		 1170}
1171
1172static void cp_free_rings (struct cp_private *cp)
1173{
1174 cp_clean_rings(cp);
6cc92cdd
JG		 1175 dma_free_coherent(&cp->pdev->dev, CP_RING_BYTES, cp->rx_ring,
1176 cp->ring_dma);
1da177e4
LT		 1177 cp->rx_ring = NULL;
1178 cp->tx_ring = NULL;
1da177e4
LT		 1179}
1180
1181static int cp_open (struct net_device *dev)
1182{
1183 struct cp_private *cp = netdev_priv(dev);
a69afe32 1184 const int irq = cp->pdev->irq;
1da177e4
LT		 1185 int rc;
1186
b4f18b3f 1187 netif_dbg(cp, ifup, dev, "enabling interface\n");
1da177e4
LT		 1188
1189 rc = cp_alloc_rings(cp);
1190 if (rc)
1191 return rc;
1192
bea3348e
SH		 1193 napi_enable(&cp->napi);
1194
1da177e4
LT		 1195 cp_init_hw(cp);
1196
a69afe32 1197 rc = request_irq(irq, cp_interrupt, IRQF_SHARED, dev->name, dev);
1da177e4
LT		 1198 if (rc)
1199 goto err_out_hw;
1200
a8c9cb10
JW		 1201 cp_enable_irq(cp);
1202
1da177e4 1203 netif_carrier_off(dev);
2501f843 1204 mii_check_media(&cp->mii_if, netif_msg_link(cp), true);
1da177e4
LT		 1205 netif_start_queue(dev);
1206
1207 return 0;
1208
1209err_out_hw:
bea3348e 1210 napi_disable(&cp->napi);
1da177e4
LT		 1211 cp_stop_hw(cp);
1212 cp_free_rings(cp);
1213 return rc;
1214}
1215
1216static int cp_close (struct net_device *dev)
1217{
1218 struct cp_private *cp = netdev_priv(dev);
1219 unsigned long flags;
1220
bea3348e
SH		 1221 napi_disable(&cp->napi);
1222
b4f18b3f 1223 netif_dbg(cp, ifdown, dev, "disabling interface\n");
1da177e4
LT		 1224
1225 spin_lock_irqsave(&cp->lock, flags);
1226
1227 netif_stop_queue(dev);
1228 netif_carrier_off(dev);
1229
1230 cp_stop_hw(cp);
1231
1232 spin_unlock_irqrestore(&cp->lock, flags);
1233
a69afe32 1234 free_irq(cp->pdev->irq, dev);
1da177e4
LT		 1235
1236 cp_free_rings(cp);
1237 return 0;
1238}
1239
9030c0d2
FR		 1240static void cp_tx_timeout(struct net_device *dev)
1241{
1242 struct cp_private *cp = netdev_priv(dev);
1243 unsigned long flags;
41b97641 1244 int rc, i;
9030c0d2 1245
b4f18b3f
JP		 1246 netdev_warn(dev, "Transmit timeout, status %2x %4x %4x %4x\n",
1247 cpr8(Cmd), cpr16(CpCmd),
1248 cpr16(IntrStatus), cpr16(IntrMask));
9030c0d2
FR		 1249
1250 spin_lock_irqsave(&cp->lock, flags);
1251
41b97641
DW		 1252 netif_dbg(cp, tx_err, cp->dev, "TX ring head %d tail %d desc %x\n",
1253 cp->tx_head, cp->tx_tail, cpr16(TxDmaOkLowDesc));
1254 for (i = 0; i < CP_TX_RING_SIZE; i++) {
1255 netif_dbg(cp, tx_err, cp->dev,
1256 "TX slot %d @%p: %08x (%08x) %08x %llx %p\n",
1257 i, &cp->tx_ring[i], le32_to_cpu(cp->tx_ring[i].opts1),
1258 cp->tx_opts[i], le32_to_cpu(cp->tx_ring[i].opts2),
1259 le64_to_cpu(cp->tx_ring[i].addr),
1260 cp->tx_skb[i]);
1261 }
1262
9030c0d2
FR		 1263 cp_stop_hw(cp);
1264 cp_clean_rings(cp);
1265 rc = cp_init_rings(cp);
1266 cp_start_hw(cp);
7a8a8e75 1267 __cp_set_rx_mode(dev);
aaa0062e 1268 cpw16_f(IntrMask, cp_norx_intr_mask);
9030c0d2
FR		 1269
1270 netif_wake_queue(dev);
aaa0062e 1271 napi_schedule_irqoff(&cp->napi);
9030c0d2
FR		 1272
1273 spin_unlock_irqrestore(&cp->lock, flags);
9030c0d2
FR		 1274}
1275
1da177e4
LT		 1276static int cp_change_mtu(struct net_device *dev, int new_mtu)
1277{
1278 struct cp_private *cp = netdev_priv(dev);
1da177e4 1279
1da177e4
LT		 1280 /* if network interface not up, no need for complexity */
1281 if (!netif_running(dev)) {
1282 dev->mtu = new_mtu;
1283 cp_set_rxbufsize(cp); /* set new rx buf size */
1284 return 0;
1285 }
1286
cb64edb6
JG		 1287 /* network IS up, close it, reset MTU, and come up again. */
1288 cp_close(dev);
1da177e4 1289 dev->mtu = new_mtu;
cb64edb6
JG		 1290 cp_set_rxbufsize(cp);
1291 return cp_open(dev);
1da177e4 1292}
1da177e4 1293
f71e1309 1294static const char mii_2_8139_map[8] = {
1da177e4
LT		 1295 BasicModeCtrl,
1296 BasicModeStatus,
1297 0,
1298 0,
1299 NWayAdvert,
1300 NWayLPAR,
1301 NWayExpansion,
1302 0
1303};
1304
1305static int mdio_read(struct net_device *dev, int phy_id, int location)
1306{
1307 struct cp_private *cp = netdev_priv(dev);
1308
1309 return location < 8 && mii_2_8139_map[location] ?
1310 readw(cp->regs + mii_2_8139_map[location]) : 0;
1311}
1312
1313
1314static void mdio_write(struct net_device *dev, int phy_id, int location,
1315 int value)
1316{
1317 struct cp_private *cp = netdev_priv(dev);
1318
1319 if (location == 0) {
1320 cpw8(Cfg9346, Cfg9346_Unlock);
1321 cpw16(BasicModeCtrl, value);
1322 cpw8(Cfg9346, Cfg9346_Lock);
1323 } else if (location < 8 && mii_2_8139_map[location])
1324 cpw16(mii_2_8139_map[location], value);
1325}
1326
1327/* Set the ethtool Wake-on-LAN settings */
1328static int netdev_set_wol (struct cp_private *cp,
1329 const struct ethtool_wolinfo *wol)
1330{
1331 u8 options;
1332
1333 options = cpr8 (Config3) & ~(LinkUp | MagicPacket);
1334 /* If WOL is being disabled, no need for complexity */
1335 if (wol->wolopts) {
1336 if (wol->wolopts & WAKE_PHY) options |= LinkUp;
1337 if (wol->wolopts & WAKE_MAGIC) options |= MagicPacket;
1338 }
1339
1340 cpw8 (Cfg9346, Cfg9346_Unlock);
1341 cpw8 (Config3, options);
1342 cpw8 (Cfg9346, Cfg9346_Lock);
1343
1344 options = 0; /* Paranoia setting */
1345 options = cpr8 (Config5) & ~(UWF | MWF | BWF);
1346 /* If WOL is being disabled, no need for complexity */
1347 if (wol->wolopts) {
1348 if (wol->wolopts & WAKE_UCAST) options |= UWF;
1349 if (wol->wolopts & WAKE_BCAST) options |= BWF;
1350 if (wol->wolopts & WAKE_MCAST) options |= MWF;
1351 }
1352
1353 cpw8 (Config5, options);
1354
1355 cp->wol_enabled = (wol->wolopts) ? 1 : 0;
1356
1357 return 0;
1358}
1359
1360/* Get the ethtool Wake-on-LAN settings */
1361static void netdev_get_wol (struct cp_private *cp,
1362 struct ethtool_wolinfo *wol)
1363{
1364 u8 options;
1365
1366 wol->wolopts = 0; /* Start from scratch */
1367 wol->supported = WAKE_PHY | WAKE_BCAST | WAKE_MAGIC |
1368 WAKE_MCAST | WAKE_UCAST;
1369 /* We don't need to go on if WOL is disabled */
1370 if (!cp->wol_enabled) return;
f3b197ac 1371
1da177e4
LT		 1372 options = cpr8 (Config3);
1373 if (options & LinkUp) wol->wolopts |= WAKE_PHY;
1374 if (options & MagicPacket) wol->wolopts |= WAKE_MAGIC;
1375
1376 options = 0; /* Paranoia setting */
1377 options = cpr8 (Config5);
1378 if (options & UWF) wol->wolopts |= WAKE_UCAST;
1379 if (options & BWF) wol->wolopts |= WAKE_BCAST;
1380 if (options & MWF) wol->wolopts |= WAKE_MCAST;
1381}
1382
1383static void cp_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1384{
1385 struct cp_private *cp = netdev_priv(dev);
1386
68aad78c
RJ		 1387 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
1388 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
1389 strlcpy(info->bus_info, pci_name(cp->pdev), sizeof(info->bus_info));
1da177e4
LT		 1390}
1391
1d0861ac
RJ		 1392static void cp_get_ringparam(struct net_device *dev,
1393 struct ethtool_ringparam *ring)
1394{
1395 ring->rx_max_pending = CP_RX_RING_SIZE;
1396 ring->tx_max_pending = CP_TX_RING_SIZE;
1397 ring->rx_pending = CP_RX_RING_SIZE;
1398 ring->tx_pending = CP_TX_RING_SIZE;
1399}
1400
1da177e4
LT		 1401static int cp_get_regs_len(struct net_device *dev)
1402{
1403 return CP_REGS_SIZE;
1404}
1405
b9f2c044 1406static int cp_get_sset_count (struct net_device *dev, int sset)
1da177e4 1407{
b9f2c044
JG		 1408 switch (sset) {
1409 case ETH_SS_STATS:
1410 return CP_NUM_STATS;
1411 default:
1412 return -EOPNOTSUPP;
1413 }
1da177e4
LT		 1414}
1415
1416static int cp_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1417{
1418 struct cp_private *cp = netdev_priv(dev);
1419 int rc;
1420 unsigned long flags;
1421
1422 spin_lock_irqsave(&cp->lock, flags);
1423 rc = mii_ethtool_gset(&cp->mii_if, cmd);
1424 spin_unlock_irqrestore(&cp->lock, flags);
1425
1426 return rc;
1427}
1428
1429static int cp_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1430{
1431 struct cp_private *cp = netdev_priv(dev);
1432 int rc;
1433 unsigned long flags;
1434
1435 spin_lock_irqsave(&cp->lock, flags);
1436 rc = mii_ethtool_sset(&cp->mii_if, cmd);
1437 spin_unlock_irqrestore(&cp->lock, flags);
1438
1439 return rc;
1440}
1441
1442static int cp_nway_reset(struct net_device *dev)
1443{
1444 struct cp_private *cp = netdev_priv(dev);
1445 return mii_nway_restart(&cp->mii_if);
1446}
1447
1448static u32 cp_get_msglevel(struct net_device *dev)
1449{
1450 struct cp_private *cp = netdev_priv(dev);
1451 return cp->msg_enable;
1452}
1453
1454static void cp_set_msglevel(struct net_device *dev, u32 value)
1455{
1456 struct cp_private *cp = netdev_priv(dev);
1457 cp->msg_enable = value;
1458}
1459
c8f44aff 1460static int cp_set_features(struct net_device *dev, netdev_features_t features)
1da177e4
LT		 1461{
1462 struct cp_private *cp = netdev_priv(dev);
044a890c 1463 unsigned long flags;
1da177e4 1464
044a890c
MM		 1465 if (!((dev->features ^ features) & NETIF_F_RXCSUM))
1466 return 0;
1da177e4 1467
044a890c 1468 spin_lock_irqsave(&cp->lock, flags);
1da177e4 1469
044a890c
MM		 1470 if (features & NETIF_F_RXCSUM)
1471 cp->cpcmd |= RxChkSum;
1da177e4 1472 else
044a890c 1473 cp->cpcmd &= ~RxChkSum;
1da177e4 1474
f646968f 1475 if (features & NETIF_F_HW_VLAN_CTAG_RX)
6864ddb2 1476 cp->cpcmd |= RxVlanOn;
1477 else
1478 cp->cpcmd &= ~RxVlanOn;
1479
044a890c
MM		 1480 cpw16_f(CpCmd, cp->cpcmd);
1481 spin_unlock_irqrestore(&cp->lock, flags);
1da177e4
LT		 1482
1483 return 0;
1484}
1485
1486static void cp_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1487 void *p)
1488{
1489 struct cp_private *cp = netdev_priv(dev);
1490 unsigned long flags;
1491
1492 if (regs->len < CP_REGS_SIZE)
1493 return /* -EINVAL */;
1494
1495 regs->version = CP_REGS_VER;
1496
1497 spin_lock_irqsave(&cp->lock, flags);
1498 memcpy_fromio(p, cp->regs, CP_REGS_SIZE);
1499 spin_unlock_irqrestore(&cp->lock, flags);
1500}
1501
1502static void cp_get_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1503{
1504 struct cp_private *cp = netdev_priv(dev);
1505 unsigned long flags;
1506
1507 spin_lock_irqsave (&cp->lock, flags);
1508 netdev_get_wol (cp, wol);
1509 spin_unlock_irqrestore (&cp->lock, flags);
1510}
1511
1512static int cp_set_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1513{
1514 struct cp_private *cp = netdev_priv(dev);
1515 unsigned long flags;
1516 int rc;
1517
1518 spin_lock_irqsave (&cp->lock, flags);
1519 rc = netdev_set_wol (cp, wol);
1520 spin_unlock_irqrestore (&cp->lock, flags);
1521
1522 return rc;
1523}
1524
1525static void cp_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
1526{
1527 switch (stringset) {
1528 case ETH_SS_STATS:
1529 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
1530 break;
1531 default:
1532 BUG();
1533 break;
1534 }
1535}
1536
1537static void cp_get_ethtool_stats (struct net_device *dev,
1538 struct ethtool_stats *estats, u64 *tmp_stats)
1539{
1540 struct cp_private *cp = netdev_priv(dev);
8b512927
SH		 1541 struct cp_dma_stats *nic_stats;
1542 dma_addr_t dma;
1da177e4
LT		 1543 int i;
1544
6cc92cdd
JG		 1545 nic_stats = dma_alloc_coherent(&cp->pdev->dev, sizeof(*nic_stats),
1546 &dma, GFP_KERNEL);
8b512927
SH		 1547 if (!nic_stats)
1548 return;
97f568d8 1549
1da177e4 1550 /* begin NIC statistics dump */
8b512927 1551 cpw32(StatsAddr + 4, (u64)dma >> 32);
284901a9 1552 cpw32(StatsAddr, ((u64)dma & DMA_BIT_MASK(32)) | DumpStats);
1da177e4
LT		 1553 cpr32(StatsAddr);
1554
97f568d8 1555 for (i = 0; i < 1000; i++) {
1da177e4
LT		 1556 if ((cpr32(StatsAddr) & DumpStats) == 0)
1557 break;
97f568d8 1558 udelay(10);
1da177e4 1559 }
97f568d8
SH		 1560 cpw32(StatsAddr, 0);
1561 cpw32(StatsAddr + 4, 0);
8b512927 1562 cpr32(StatsAddr);
1da177e4
LT		 1563
1564 i = 0;
8b512927
SH		 1565 tmp_stats[i++] = le64_to_cpu(nic_stats->tx_ok);
1566 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok);
1567 tmp_stats[i++] = le64_to_cpu(nic_stats->tx_err);
1568 tmp_stats[i++] = le32_to_cpu(nic_stats->rx_err);
1569 tmp_stats[i++] = le16_to_cpu(nic_stats->rx_fifo);
1570 tmp_stats[i++] = le16_to_cpu(nic_stats->frame_align);
1571 tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_1col);
1572 tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_mcol);
1573 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_phys);
1574 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_bcast);
1575 tmp_stats[i++] = le32_to_cpu(nic_stats->rx_ok_mcast);
1576 tmp_stats[i++] = le16_to_cpu(nic_stats->tx_abort);
1577 tmp_stats[i++] = le16_to_cpu(nic_stats->tx_underrun);
1da177e4 1578 tmp_stats[i++] = cp->cp_stats.rx_frags;
5d9428de 1579 BUG_ON(i != CP_NUM_STATS);
8b512927 1580
6cc92cdd 1581 dma_free_coherent(&cp->pdev->dev, sizeof(*nic_stats), nic_stats, dma);
1da177e4
LT		 1582}
1583
7282d491 1584static const struct ethtool_ops cp_ethtool_ops = {
1da177e4
LT		 1585 .get_drvinfo = cp_get_drvinfo,
1586 .get_regs_len = cp_get_regs_len,
b9f2c044 1587 .get_sset_count = cp_get_sset_count,
1da177e4
LT		 1588 .get_settings = cp_get_settings,
1589 .set_settings = cp_set_settings,
1590 .nway_reset = cp_nway_reset,
1591 .get_link = ethtool_op_get_link,
1592 .get_msglevel = cp_get_msglevel,
1593 .set_msglevel = cp_set_msglevel,
1da177e4
LT		 1594 .get_regs = cp_get_regs,
1595 .get_wol = cp_get_wol,
1596 .set_wol = cp_set_wol,
1597 .get_strings = cp_get_strings,
1598 .get_ethtool_stats = cp_get_ethtool_stats,
722fdb33
PC		 1599 .get_eeprom_len = cp_get_eeprom_len,
1600 .get_eeprom = cp_get_eeprom,
1601 .set_eeprom = cp_set_eeprom,
1d0861ac 1602 .get_ringparam = cp_get_ringparam,
1da177e4
LT		 1603};
1604
1605static int cp_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1606{
1607 struct cp_private *cp = netdev_priv(dev);
1608 int rc;
1609 unsigned long flags;
1610
1611 if (!netif_running(dev))
1612 return -EINVAL;
1613
1614 spin_lock_irqsave(&cp->lock, flags);
1615 rc = generic_mii_ioctl(&cp->mii_if, if_mii(rq), cmd, NULL);
1616 spin_unlock_irqrestore(&cp->lock, flags);
1617 return rc;
1618}
1619
c048aaf4
JP		 1620static int cp_set_mac_address(struct net_device *dev, void *p)
1621{
1622 struct cp_private *cp = netdev_priv(dev);
1623 struct sockaddr *addr = p;
1624
1625 if (!is_valid_ether_addr(addr->sa_data))
1626 return -EADDRNOTAVAIL;
1627
1628 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1629
1630 spin_lock_irq(&cp->lock);
1631
1632 cpw8_f(Cfg9346, Cfg9346_Unlock);
1633 cpw32_f(MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0)));
1634 cpw32_f(MAC0 + 4, le32_to_cpu (*(__le32 *) (dev->dev_addr + 4)));
1635 cpw8_f(Cfg9346, Cfg9346_Lock);
1636
1637 spin_unlock_irq(&cp->lock);
1638
1639 return 0;
1640}
1641
1da177e4
LT		 1642/* Serial EEPROM section. */
1643
1644/* EEPROM_Ctrl bits. */
1645#define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1646#define EE_CS 0x08 /* EEPROM chip select. */
1647#define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1648#define EE_WRITE_0 0x00
1649#define EE_WRITE_1 0x02
1650#define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1651#define EE_ENB (0x80 | EE_CS)
1652
1653/* Delay between EEPROM clock transitions.
1654 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1655 */
1656
7d03f5a4 1657#define eeprom_delay() readb(ee_addr)
1da177e4
LT		 1658
1659/* The EEPROM commands include the alway-set leading bit. */
722fdb33 1660#define EE_EXTEND_CMD (4)
1da177e4
LT		 1661#define EE_WRITE_CMD (5)
1662#define EE_READ_CMD (6)
1663#define EE_ERASE_CMD (7)
1664
722fdb33
PC		 1665#define EE_EWDS_ADDR (0)
1666#define EE_WRAL_ADDR (1)
1667#define EE_ERAL_ADDR (2)
1668#define EE_EWEN_ADDR (3)
1669
1670#define CP_EEPROM_MAGIC PCI_DEVICE_ID_REALTEK_8139
1da177e4 1671
722fdb33
PC		 1672static void eeprom_cmd_start(void __iomem *ee_addr)
1673{
1da177e4
LT		 1674 writeb (EE_ENB & ~EE_CS, ee_addr);
1675 writeb (EE_ENB, ee_addr);
1676 eeprom_delay ();
722fdb33 1677}
1da177e4 1678
722fdb33
PC		 1679static void eeprom_cmd(void __iomem *ee_addr, int cmd, int cmd_len)
1680{
1681 int i;
1682
1683 /* Shift the command bits out. */
1684 for (i = cmd_len - 1; i >= 0; i--) {
1685 int dataval = (cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1da177e4
LT		 1686 writeb (EE_ENB | dataval, ee_addr);
1687 eeprom_delay ();
1688 writeb (EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
1689 eeprom_delay ();
1690 }
1691 writeb (EE_ENB, ee_addr);
1692 eeprom_delay ();
722fdb33
PC		 1693}
1694
1695static void eeprom_cmd_end(void __iomem *ee_addr)
1696{
0bc777bc 1697 writeb(0, ee_addr);
722fdb33
PC		 1698 eeprom_delay ();
1699}
1700
1701static void eeprom_extend_cmd(void __iomem *ee_addr, int extend_cmd,
1702 int addr_len)
1703{
1704 int cmd = (EE_EXTEND_CMD << addr_len) | (extend_cmd << (addr_len - 2));
1705
1706 eeprom_cmd_start(ee_addr);
1707 eeprom_cmd(ee_addr, cmd, 3 + addr_len);
1708 eeprom_cmd_end(ee_addr);
1709}
1710
1711static u16 read_eeprom (void __iomem *ioaddr, int location, int addr_len)
1712{
1713 int i;
1714 u16 retval = 0;
1715 void __iomem *ee_addr = ioaddr + Cfg9346;
1716 int read_cmd = location | (EE_READ_CMD << addr_len);
1717
1718 eeprom_cmd_start(ee_addr);
1719 eeprom_cmd(ee_addr, read_cmd, 3 + addr_len);
1da177e4
LT		 1720
1721 for (i = 16; i > 0; i--) {
1722 writeb (EE_ENB | EE_SHIFT_CLK, ee_addr);
1723 eeprom_delay ();
1724 retval =
1725 (retval << 1) | ((readb (ee_addr) & EE_DATA_READ) ? 1 :
1726 0);
1727 writeb (EE_ENB, ee_addr);
1728 eeprom_delay ();
1729 }
1730
722fdb33 1731 eeprom_cmd_end(ee_addr);
1da177e4
LT		 1732
1733 return retval;
1734}
1735
722fdb33
PC		 1736static void write_eeprom(void __iomem *ioaddr, int location, u16 val,
1737 int addr_len)
1738{
1739 int i;
1740 void __iomem *ee_addr = ioaddr + Cfg9346;
1741 int write_cmd = location | (EE_WRITE_CMD << addr_len);
1742
1743 eeprom_extend_cmd(ee_addr, EE_EWEN_ADDR, addr_len);
1744
1745 eeprom_cmd_start(ee_addr);
1746 eeprom_cmd(ee_addr, write_cmd, 3 + addr_len);
1747 eeprom_cmd(ee_addr, val, 16);
1748 eeprom_cmd_end(ee_addr);
1749
1750 eeprom_cmd_start(ee_addr);
1751 for (i = 0; i < 20000; i++)
1752 if (readb(ee_addr) & EE_DATA_READ)
1753 break;
1754 eeprom_cmd_end(ee_addr);
1755
1756 eeprom_extend_cmd(ee_addr, EE_EWDS_ADDR, addr_len);
1757}
1758
1759static int cp_get_eeprom_len(struct net_device *dev)
1760{
1761 struct cp_private *cp = netdev_priv(dev);
1762 int size;
1763
1764 spin_lock_irq(&cp->lock);
1765 size = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 256 : 128;
1766 spin_unlock_irq(&cp->lock);
1767
1768 return size;
1769}
1770
1771static int cp_get_eeprom(struct net_device *dev,
1772 struct ethtool_eeprom *eeprom, u8 *data)
1773{
1774 struct cp_private *cp = netdev_priv(dev);
1775 unsigned int addr_len;
1776 u16 val;
1777 u32 offset = eeprom->offset >> 1;
1778 u32 len = eeprom->len;
1779 u32 i = 0;
1780
1781 eeprom->magic = CP_EEPROM_MAGIC;
1782
1783 spin_lock_irq(&cp->lock);
1784
1785 addr_len = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 8 : 6;
1786
1787 if (eeprom->offset & 1) {
1788 val = read_eeprom(cp->regs, offset, addr_len);
1789 data[i++] = (u8)(val >> 8);
1790 offset++;
1791 }
1792
1793 while (i < len - 1) {
1794 val = read_eeprom(cp->regs, offset, addr_len);
1795 data[i++] = (u8)val;
1796 data[i++] = (u8)(val >> 8);
1797 offset++;
1798 }
1799
1800 if (i < len) {
1801 val = read_eeprom(cp->regs, offset, addr_len);
1802 data[i] = (u8)val;
1803 }
1804
1805 spin_unlock_irq(&cp->lock);
1806 return 0;
1807}
1808
1809static int cp_set_eeprom(struct net_device *dev,
1810 struct ethtool_eeprom *eeprom, u8 *data)
1811{
1812 struct cp_private *cp = netdev_priv(dev);
1813 unsigned int addr_len;
1814 u16 val;
1815 u32 offset = eeprom->offset >> 1;
1816 u32 len = eeprom->len;
1817 u32 i = 0;
1818
1819 if (eeprom->magic != CP_EEPROM_MAGIC)
1820 return -EINVAL;
1821
1822 spin_lock_irq(&cp->lock);
1823
1824 addr_len = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 8 : 6;
1825
1826 if (eeprom->offset & 1) {
1827 val = read_eeprom(cp->regs, offset, addr_len) & 0xff;
1828 val |= (u16)data[i++] << 8;
1829 write_eeprom(cp->regs, offset, val, addr_len);
1830 offset++;
1831 }
1832
1833 while (i < len - 1) {
1834 val = (u16)data[i++];
1835 val |= (u16)data[i++] << 8;
1836 write_eeprom(cp->regs, offset, val, addr_len);
1837 offset++;
1838 }
1839
1840 if (i < len) {
1841 val = read_eeprom(cp->regs, offset, addr_len) & 0xff00;
1842 val |= (u16)data[i];
1843 write_eeprom(cp->regs, offset, val, addr_len);
1844 }
1845
1846 spin_unlock_irq(&cp->lock);
1847 return 0;
1848}
1849
1da177e4
LT		 1850/* Put the board into D3cold state and wait for WakeUp signal */
1851static void cp_set_d3_state (struct cp_private *cp)
1852{
1ca01512 1853 pci_enable_wake(cp->pdev, PCI_D0, 1); /* Enable PME# generation */
1da177e4
LT		 1854 pci_set_power_state (cp->pdev, PCI_D3hot);
1855}
1856
8b7a7048
DW		 1857static netdev_features_t cp_features_check(struct sk_buff *skb,
1858 struct net_device *dev,
1859 netdev_features_t features)
1860{
1861 if (skb_shinfo(skb)->gso_size > MSSMask)
1862 features &= ~NETIF_F_TSO;
1863
1864 return vlan_features_check(skb, features);
1865}
48dfcde4
SH		 1866static const struct net_device_ops cp_netdev_ops = {
1867 .ndo_open = cp_open,
1868 .ndo_stop = cp_close,
1869 .ndo_validate_addr = eth_validate_addr,
c048aaf4 1870 .ndo_set_mac_address = cp_set_mac_address,
afc4b13d 1871 .ndo_set_rx_mode = cp_set_rx_mode,
48dfcde4
SH		 1872 .ndo_get_stats = cp_get_stats,
1873 .ndo_do_ioctl = cp_ioctl,
00829823 1874 .ndo_start_xmit = cp_start_xmit,
48dfcde4 1875 .ndo_tx_timeout = cp_tx_timeout,
044a890c 1876 .ndo_set_features = cp_set_features,
48dfcde4 1877 .ndo_change_mtu = cp_change_mtu,
8b7a7048 1878 .ndo_features_check = cp_features_check,
fe96aaa1 1879
48dfcde4
SH		 1880#ifdef CONFIG_NET_POLL_CONTROLLER
1881 .ndo_poll_controller = cp_poll_controller,
1882#endif
1883};
1884
1da177e4
LT		 1885static int cp_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1886{
1887 struct net_device *dev;
1888 struct cp_private *cp;
1889 int rc;
1890 void __iomem *regs;
2427ddd8 1891 resource_size_t pciaddr;
1da177e4 1892 unsigned int addr_len, i, pci_using_dac;
1da177e4 1893
5490c272 1894 pr_info_once("%s", version);
1da177e4 1895
1da177e4 1896 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
44c10138 1897 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision < 0x20) {
de4549ca 1898 dev_info(&pdev->dev,
b4f18b3f
JP		 1899 "This (id %04x:%04x rev %02x) is not an 8139C+ compatible chip, use 8139too\n",
1900 pdev->vendor, pdev->device, pdev->revision);
1da177e4
LT		 1901 return -ENODEV;
1902 }
1903
1904 dev = alloc_etherdev(sizeof(struct cp_private));
1905 if (!dev)
1906 return -ENOMEM;
1da177e4
LT		 1907 SET_NETDEV_DEV(dev, &pdev->dev);
1908
1909 cp = netdev_priv(dev);
1910 cp->pdev = pdev;
1911 cp->dev = dev;
1912 cp->msg_enable = (debug < 0 ? CP_DEF_MSG_ENABLE : debug);
1913 spin_lock_init (&cp->lock);
1914 cp->mii_if.dev = dev;
1915 cp->mii_if.mdio_read = mdio_read;
1916 cp->mii_if.mdio_write = mdio_write;
1917 cp->mii_if.phy_id = CP_INTERNAL_PHY;
1918 cp->mii_if.phy_id_mask = 0x1f;
1919 cp->mii_if.reg_num_mask = 0x1f;
1920 cp_set_rxbufsize(cp);
1921
1922 rc = pci_enable_device(pdev);
1923 if (rc)
1924 goto err_out_free;
1925
1926 rc = pci_set_mwi(pdev);
1927 if (rc)
1928 goto err_out_disable;
1929
1930 rc = pci_request_regions(pdev, DRV_NAME);
1931 if (rc)
1932 goto err_out_mwi;
1933
1934 pciaddr = pci_resource_start(pdev, 1);
1935 if (!pciaddr) {
1936 rc = -EIO;
9b91cf9d 1937 dev_err(&pdev->dev, "no MMIO resource\n");
1da177e4
LT		 1938 goto err_out_res;
1939 }
1940 if (pci_resource_len(pdev, 1) < CP_REGS_SIZE) {
1941 rc = -EIO;
9b91cf9d 1942 dev_err(&pdev->dev, "MMIO resource (%llx) too small\n",
2e8a538d 1943 (unsigned long long)pci_resource_len(pdev, 1));
1da177e4
LT		 1944 goto err_out_res;
1945 }
1946
1947 /* Configure DMA attributes. */
1948 if ((sizeof(dma_addr_t) > 4) &&
6a35528a
YH		 1949 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) &&
1950 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
1da177e4
LT		 1951 pci_using_dac = 1;
1952 } else {
1953 pci_using_dac = 0;
1954
284901a9 1955 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 1956 if (rc) {
9b91cf9d 1957 dev_err(&pdev->dev,
b4f18b3f 1958 "No usable DMA configuration, aborting\n");
1da177e4
LT		 1959 goto err_out_res;
1960 }
284901a9 1961 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 1962 if (rc) {
9b91cf9d 1963 dev_err(&pdev->dev,
b4f18b3f 1964 "No usable consistent DMA configuration, aborting\n");
1da177e4
LT		 1965 goto err_out_res;
1966 }
1967 }
1968
1969 cp->cpcmd = (pci_using_dac ? PCIDAC : 0) |
1970 PCIMulRW | RxChkSum | CpRxOn | CpTxOn;
1971
044a890c
MM		 1972 dev->features |= NETIF_F_RXCSUM;
1973 dev->hw_features |= NETIF_F_RXCSUM;
1974
1da177e4
LT		 1975 regs = ioremap(pciaddr, CP_REGS_SIZE);
1976 if (!regs) {
1977 rc = -EIO;
4626dd46 1978 dev_err(&pdev->dev, "Cannot map PCI MMIO (%Lx@%Lx)\n",
b4f18b3f 1979 (unsigned long long)pci_resource_len(pdev, 1),
2e8a538d 1980 (unsigned long long)pciaddr);
1da177e4
LT		 1981 goto err_out_res;
1982 }
1da177e4
LT		 1983 cp->regs = regs;
1984
1985 cp_stop_hw(cp);
1986
1987 /* read MAC address from EEPROM */
1988 addr_len = read_eeprom (regs, 0, 8) == 0x8129 ? 8 : 6;
1989 for (i = 0; i < 3; i++)
03233b90
AV		 1990 ((__le16 *) (dev->dev_addr))[i] =
1991 cpu_to_le16(read_eeprom (regs, i + 7, addr_len));
1da177e4 1992
48dfcde4 1993 dev->netdev_ops = &cp_netdev_ops;
bea3348e 1994 netif_napi_add(dev, &cp->napi, cp_rx_poll, 16);
1da177e4 1995 dev->ethtool_ops = &cp_ethtool_ops;
1da177e4 1996 dev->watchdog_timeo = TX_TIMEOUT;
1da177e4 1997
5a58f227
DW		 1998 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
1999 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
1da177e4
LT		 2000
2001 if (pci_using_dac)
2002 dev->features |= NETIF_F_HIGHDMA;
2003
6864ddb2 2004 dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
f646968f 2005 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
6864ddb2 2006 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
2007 NETIF_F_HIGHDMA;
fcec3456 2008
c7315a95
JW		 2009 /* MTU range: 60 - 4096 */
2010 dev->min_mtu = CP_MIN_MTU;
2011 dev->max_mtu = CP_MAX_MTU;
2012
1da177e4
LT		 2013 rc = register_netdev(dev);
2014 if (rc)
2015 goto err_out_iomap;
2016
a69afe32
FR		 2017 netdev_info(dev, "RTL-8139C+ at 0x%p, %pM, IRQ %d\n",
2018 regs, dev->dev_addr, pdev->irq);
1da177e4
LT		 2019
2020 pci_set_drvdata(pdev, dev);
2021
2022 /* enable busmastering and memory-write-invalidate */
2023 pci_set_master(pdev);
2024
2e8a538d
JG		 2025 if (cp->wol_enabled)
2026 cp_set_d3_state (cp);
1da177e4
LT		 2027
2028 return 0;
2029
2030err_out_iomap:
2031 iounmap(regs);
2032err_out_res:
2033 pci_release_regions(pdev);
2034err_out_mwi:
2035 pci_clear_mwi(pdev);
2036err_out_disable:
2037 pci_disable_device(pdev);
2038err_out_free:
2039 free_netdev(dev);
2040 return rc;
2041}
2042
2043static void cp_remove_one (struct pci_dev *pdev)
2044{
2045 struct net_device *dev = pci_get_drvdata(pdev);
2046 struct cp_private *cp = netdev_priv(dev);
2047
1da177e4
LT		 2048 unregister_netdev(dev);
2049 iounmap(cp->regs);
2e8a538d
JG		 2050 if (cp->wol_enabled)
2051 pci_set_power_state (pdev, PCI_D0);
1da177e4
LT		 2052 pci_release_regions(pdev);
2053 pci_clear_mwi(pdev);
2054 pci_disable_device(pdev);
1da177e4
LT		 2055 free_netdev(dev);
2056}
2057
2058#ifdef CONFIG_PM
05adc3b7 2059static int cp_suspend (struct pci_dev *pdev, pm_message_t state)
1da177e4 2060{
7668a494
FR		 2061 struct net_device *dev = pci_get_drvdata(pdev);
2062 struct cp_private *cp = netdev_priv(dev);
1da177e4
LT		 2063 unsigned long flags;
2064
7668a494
FR		 2065 if (!netif_running(dev))
2066 return 0;
1da177e4
LT		 2067
2068 netif_device_detach (dev);
2069 netif_stop_queue (dev);
2070
2071 spin_lock_irqsave (&cp->lock, flags);
2072
2073 /* Disable Rx and Tx */
2074 cpw16 (IntrMask, 0);
2075 cpw8 (Cmd, cpr8 (Cmd) & (~RxOn | ~TxOn));
2076
2077 spin_unlock_irqrestore (&cp->lock, flags);
2078
576cfa93
FR		 2079 pci_save_state(pdev);
2080 pci_enable_wake(pdev, pci_choose_state(pdev, state), cp->wol_enabled);
2081 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1da177e4
LT		 2082
2083 return 0;
2084}
2085
2086static int cp_resume (struct pci_dev *pdev)
2087{
576cfa93
FR		 2088 struct net_device *dev = pci_get_drvdata (pdev);
2089 struct cp_private *cp = netdev_priv(dev);
a4cf0761 2090 unsigned long flags;
1da177e4 2091
576cfa93
FR		 2092 if (!netif_running(dev))
2093 return 0;
1da177e4
LT		 2094
2095 netif_device_attach (dev);
576cfa93
FR		 2096
2097 pci_set_power_state(pdev, PCI_D0);
2098 pci_restore_state(pdev);
2099 pci_enable_wake(pdev, PCI_D0, 0);
2100
2101 /* FIXME: sh*t may happen if the Rx ring buffer is depleted */
2102 cp_init_rings_index (cp);
1da177e4 2103 cp_init_hw (cp);
a8c9cb10 2104 cp_enable_irq(cp);
1da177e4 2105 netif_start_queue (dev);
a4cf0761
PO		 2106
2107 spin_lock_irqsave (&cp->lock, flags);
2108
2501f843 2109 mii_check_media(&cp->mii_if, netif_msg_link(cp), false);
a4cf0761
PO		 2110
2111 spin_unlock_irqrestore (&cp->lock, flags);
f3b197ac 2112
1da177e4
LT		 2113 return 0;
2114}
2115#endif /* CONFIG_PM */
2116
96b3bff4
VB		 2117static const struct pci_device_id cp_pci_tbl[] = {
2118 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139), },
2119 { PCI_DEVICE(PCI_VENDOR_ID_TTTECH, PCI_DEVICE_ID_TTTECH_MC322), },
2120 { },
2121};
2122MODULE_DEVICE_TABLE(pci, cp_pci_tbl);
2123
1da177e4
LT		 2124static struct pci_driver cp_driver = {
2125 .name = DRV_NAME,
2126 .id_table = cp_pci_tbl,
2127 .probe = cp_init_one,
2128 .remove = cp_remove_one,
2129#ifdef CONFIG_PM
2130 .resume = cp_resume,
2131 .suspend = cp_suspend,
2132#endif
2133};
2134
5490c272 2135module_pci_driver(cp_driver);
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