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UBUNTU: Ubuntu-4.15.0-96.97
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / realtek / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
a6b7a407 24#include <linux/interrupt.h>
1da177e4 25#include <linux/dma-mapping.h>
e1759441 26#include <linux/pm_runtime.h>
bca03d5f 27#include <linux/firmware.h>
ba04c7c9 28#include <linux/pci-aspm.h>
70c71606 29#include <linux/prefetch.h>
e974604b 30#include <linux/ipv6.h>
31#include <net/ip6_checksum.h>
1da177e4
LT		 32
33#include <asm/io.h>
34#include <asm/irq.h>
35
865c652d 36#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 37#define MODULENAME "r8169"
38#define PFX MODULENAME ": "
39
bca03d5f 40#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
41#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
01dc7fec 42#define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
43#define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
70090424 44#define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
c2218925
HW		 45#define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
46#define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
5a5e4443 47#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
7e18dca1 48#define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
b3d7b2f2 49#define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
45dd95c4 50#define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
5598bfe5 51#define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
58152cd4 52#define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
beb330a4 53#define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
57538c4a 54#define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
6e1d0b89
CHL		 55#define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw"
56#define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
57#define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw"
58#define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
bca03d5f 59
1da177e4
LT		 60#ifdef RTL8169_DEBUG
61#define assert(expr) \
5b0384f4
FR		 62 if (!(expr)) { \
63 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
b39d66a8 64 #expr,__FILE__,__func__,__LINE__); \
5b0384f4 65 }
06fa7358
JP		 66#define dprintk(fmt, args...) \
67 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 68#else
69#define assert(expr) do {} while (0)
70#define dprintk(fmt, args...) do {} while (0)
71#endif /* RTL8169_DEBUG */
72
b57b7e5a 73#define R8169_MSG_DEFAULT \
f0e837d9 74 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 75
477206a0
JD		 76#define TX_SLOTS_AVAIL(tp) \
77 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
78
79/* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
80#define TX_FRAGS_READY_FOR(tp,nr_frags) \
81 (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
1da177e4 82
1da177e4
LT		 83/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
84 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 85static const int multicast_filter_limit = 32;
1da177e4 86
9c14ceaf 87#define MAX_READ_REQUEST_SHIFT 12
aee77e4a 88#define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
1da177e4
LT		 89#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
90
91#define R8169_REGS_SIZE 256
92#define R8169_NAPI_WEIGHT 64
93#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
9fba0812 94#define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
1da177e4
LT		 95#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
96#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
97
98#define RTL8169_TX_TIMEOUT (6*HZ)
99#define RTL8169_PHY_TIMEOUT (10*HZ)
100
101/* write/read MMIO register */
102#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
103#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
104#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
105#define RTL_R8(reg) readb (ioaddr + (reg))
106#define RTL_R16(reg) readw (ioaddr + (reg))
06f555f3 107#define RTL_R32(reg) readl (ioaddr + (reg))
1da177e4
LT		 108
109enum mac_version {
85bffe6c
FR		 110 RTL_GIGA_MAC_VER_01 = 0,
111 RTL_GIGA_MAC_VER_02,
112 RTL_GIGA_MAC_VER_03,
113 RTL_GIGA_MAC_VER_04,
114 RTL_GIGA_MAC_VER_05,
115 RTL_GIGA_MAC_VER_06,
116 RTL_GIGA_MAC_VER_07,
117 RTL_GIGA_MAC_VER_08,
118 RTL_GIGA_MAC_VER_09,
119 RTL_GIGA_MAC_VER_10,
120 RTL_GIGA_MAC_VER_11,
121 RTL_GIGA_MAC_VER_12,
122 RTL_GIGA_MAC_VER_13,
123 RTL_GIGA_MAC_VER_14,
124 RTL_GIGA_MAC_VER_15,
125 RTL_GIGA_MAC_VER_16,
126 RTL_GIGA_MAC_VER_17,
127 RTL_GIGA_MAC_VER_18,
128 RTL_GIGA_MAC_VER_19,
129 RTL_GIGA_MAC_VER_20,
130 RTL_GIGA_MAC_VER_21,
131 RTL_GIGA_MAC_VER_22,
132 RTL_GIGA_MAC_VER_23,
133 RTL_GIGA_MAC_VER_24,
134 RTL_GIGA_MAC_VER_25,
135 RTL_GIGA_MAC_VER_26,
136 RTL_GIGA_MAC_VER_27,
137 RTL_GIGA_MAC_VER_28,
138 RTL_GIGA_MAC_VER_29,
139 RTL_GIGA_MAC_VER_30,
140 RTL_GIGA_MAC_VER_31,
141 RTL_GIGA_MAC_VER_32,
142 RTL_GIGA_MAC_VER_33,
70090424 143 RTL_GIGA_MAC_VER_34,
c2218925
HW		 144 RTL_GIGA_MAC_VER_35,
145 RTL_GIGA_MAC_VER_36,
7e18dca1 146 RTL_GIGA_MAC_VER_37,
b3d7b2f2 147 RTL_GIGA_MAC_VER_38,
5598bfe5 148 RTL_GIGA_MAC_VER_39,
c558386b
HW		 149 RTL_GIGA_MAC_VER_40,
150 RTL_GIGA_MAC_VER_41,
57538c4a 151 RTL_GIGA_MAC_VER_42,
58152cd4 152 RTL_GIGA_MAC_VER_43,
45dd95c4 153 RTL_GIGA_MAC_VER_44,
6e1d0b89
CHL		 154 RTL_GIGA_MAC_VER_45,
155 RTL_GIGA_MAC_VER_46,
156 RTL_GIGA_MAC_VER_47,
157 RTL_GIGA_MAC_VER_48,
935e2218
CHL		 158 RTL_GIGA_MAC_VER_49,
159 RTL_GIGA_MAC_VER_50,
160 RTL_GIGA_MAC_VER_51,
85bffe6c 161 RTL_GIGA_MAC_NONE = 0xff,
1da177e4
LT		 162};
163
2b7b4318
FR		 164enum rtl_tx_desc_version {
165 RTL_TD_0 = 0,
166 RTL_TD_1 = 1,
167};
168
d58d46b5
FR		 169#define JUMBO_1K ETH_DATA_LEN
170#define JUMBO_4K (4*1024 - ETH_HLEN - 2)
171#define JUMBO_6K (6*1024 - ETH_HLEN - 2)
172#define JUMBO_7K (7*1024 - ETH_HLEN - 2)
173#define JUMBO_9K (9*1024 - ETH_HLEN - 2)
174
175#define _R(NAME,TD,FW,SZ,B) { \
176 .name = NAME, \
177 .txd_version = TD, \
178 .fw_name = FW, \
179 .jumbo_max = SZ, \
180 .jumbo_tx_csum = B \
181}
1da177e4 182
3c6bee1d 183static const struct {
1da177e4 184 const char *name;
2b7b4318 185 enum rtl_tx_desc_version txd_version;
953a12cc 186 const char *fw_name;
d58d46b5
FR		 187 u16 jumbo_max;
188 bool jumbo_tx_csum;
85bffe6c
FR		 189} rtl_chip_infos[] = {
190 /* PCI devices. */
191 [RTL_GIGA_MAC_VER_01] =
d58d46b5 192 _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 193 [RTL_GIGA_MAC_VER_02] =
d58d46b5 194 _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 195 [RTL_GIGA_MAC_VER_03] =
d58d46b5 196 _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 197 [RTL_GIGA_MAC_VER_04] =
d58d46b5 198 _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 199 [RTL_GIGA_MAC_VER_05] =
d58d46b5 200 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 201 [RTL_GIGA_MAC_VER_06] =
d58d46b5 202 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c
FR		 203 /* PCI-E devices. */
204 [RTL_GIGA_MAC_VER_07] =
d58d46b5 205 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 206 [RTL_GIGA_MAC_VER_08] =
d58d46b5 207 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 208 [RTL_GIGA_MAC_VER_09] =
d58d46b5 209 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 210 [RTL_GIGA_MAC_VER_10] =
d58d46b5 211 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 212 [RTL_GIGA_MAC_VER_11] =
d58d46b5 213 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
85bffe6c 214 [RTL_GIGA_MAC_VER_12] =
d58d46b5 215 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
85bffe6c 216 [RTL_GIGA_MAC_VER_13] =
d58d46b5 217 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 218 [RTL_GIGA_MAC_VER_14] =
d58d46b5 219 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 220 [RTL_GIGA_MAC_VER_15] =
d58d46b5 221 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 222 [RTL_GIGA_MAC_VER_16] =
d58d46b5 223 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 224 [RTL_GIGA_MAC_VER_17] =
f75761b6 225 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
85bffe6c 226 [RTL_GIGA_MAC_VER_18] =
d58d46b5 227 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 228 [RTL_GIGA_MAC_VER_19] =
d58d46b5 229 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 230 [RTL_GIGA_MAC_VER_20] =
d58d46b5 231 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 232 [RTL_GIGA_MAC_VER_21] =
d58d46b5 233 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 234 [RTL_GIGA_MAC_VER_22] =
d58d46b5 235 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 236 [RTL_GIGA_MAC_VER_23] =
d58d46b5 237 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 238 [RTL_GIGA_MAC_VER_24] =
d58d46b5 239 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 240 [RTL_GIGA_MAC_VER_25] =
d58d46b5
FR		 241 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1,
242 JUMBO_9K, false),
85bffe6c 243 [RTL_GIGA_MAC_VER_26] =
d58d46b5
FR		 244 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2,
245 JUMBO_9K, false),
85bffe6c 246 [RTL_GIGA_MAC_VER_27] =
d58d46b5 247 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 248 [RTL_GIGA_MAC_VER_28] =
d58d46b5 249 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 250 [RTL_GIGA_MAC_VER_29] =
d58d46b5
FR		 251 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
252 JUMBO_1K, true),
85bffe6c 253 [RTL_GIGA_MAC_VER_30] =
d58d46b5
FR		 254 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
255 JUMBO_1K, true),
85bffe6c 256 [RTL_GIGA_MAC_VER_31] =
d58d46b5 257 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 258 [RTL_GIGA_MAC_VER_32] =
d58d46b5
FR		 259 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1,
260 JUMBO_9K, false),
85bffe6c 261 [RTL_GIGA_MAC_VER_33] =
d58d46b5
FR		 262 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2,
263 JUMBO_9K, false),
70090424 264 [RTL_GIGA_MAC_VER_34] =
d58d46b5
FR		 265 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
266 JUMBO_9K, false),
c2218925 267 [RTL_GIGA_MAC_VER_35] =
d58d46b5
FR		 268 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1,
269 JUMBO_9K, false),
c2218925 270 [RTL_GIGA_MAC_VER_36] =
d58d46b5
FR		 271 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2,
272 JUMBO_9K, false),
7e18dca1
HW		 273 [RTL_GIGA_MAC_VER_37] =
274 _R("RTL8402", RTL_TD_1, FIRMWARE_8402_1,
275 JUMBO_1K, true),
b3d7b2f2
HW		 276 [RTL_GIGA_MAC_VER_38] =
277 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_1,
278 JUMBO_9K, false),
5598bfe5
HW		 279 [RTL_GIGA_MAC_VER_39] =
280 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_1,
281 JUMBO_1K, true),
c558386b 282 [RTL_GIGA_MAC_VER_40] =
beb330a4 283 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_2,
c558386b
HW		 284 JUMBO_9K, false),
285 [RTL_GIGA_MAC_VER_41] =
286 _R("RTL8168g/8111g", RTL_TD_1, NULL, JUMBO_9K, false),
57538c4a 287 [RTL_GIGA_MAC_VER_42] =
288 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_3,
289 JUMBO_9K, false),
58152cd4 290 [RTL_GIGA_MAC_VER_43] =
291 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_2,
292 JUMBO_1K, true),
45dd95c4 293 [RTL_GIGA_MAC_VER_44] =
294 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_2,
295 JUMBO_9K, false),
6e1d0b89
CHL		 296 [RTL_GIGA_MAC_VER_45] =
297 _R("RTL8168h/8111h", RTL_TD_1, FIRMWARE_8168H_1,
298 JUMBO_9K, false),
299 [RTL_GIGA_MAC_VER_46] =
300 _R("RTL8168h/8111h", RTL_TD_1, FIRMWARE_8168H_2,
301 JUMBO_9K, false),
302 [RTL_GIGA_MAC_VER_47] =
303 _R("RTL8107e", RTL_TD_1, FIRMWARE_8107E_1,
304 JUMBO_1K, false),
305 [RTL_GIGA_MAC_VER_48] =
306 _R("RTL8107e", RTL_TD_1, FIRMWARE_8107E_2,
307 JUMBO_1K, false),
935e2218
CHL		 308 [RTL_GIGA_MAC_VER_49] =
309 _R("RTL8168ep/8111ep", RTL_TD_1, NULL,
310 JUMBO_9K, false),
311 [RTL_GIGA_MAC_VER_50] =
312 _R("RTL8168ep/8111ep", RTL_TD_1, NULL,
313 JUMBO_9K, false),
314 [RTL_GIGA_MAC_VER_51] =
315 _R("RTL8168ep/8111ep", RTL_TD_1, NULL,
316 JUMBO_9K, false),
953a12cc 317};
85bffe6c 318#undef _R
953a12cc 319
bcf0bf90
FR		 320enum cfg_version {
321 RTL_CFG_0 = 0x00,
322 RTL_CFG_1,
323 RTL_CFG_2
324};
325
9baa3c34 326static const struct pci_device_id rtl8169_pci_tbl[] = {
a0561bad
KHF		 327 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x2502), 0, 0, RTL_CFG_1 },
328 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x2600), 0, 0, RTL_CFG_1 },
bcf0bf90 329 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 330 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
610c9087 331 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8161), 0, 0, RTL_CFG_1 },
d81bf551 332 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 333 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
688173b2 334 { PCI_DEVICE(PCI_VENDOR_ID_NCUBE, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90 335 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
2a35cfa5
FR		 336 { PCI_VENDOR_ID_DLINK, 0x4300,
337 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
bcf0bf90 338 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
93a3aa25 339 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
bc1660b5 340 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 341 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
342 { PCI_VENDOR_ID_LINKSYS, 0x1032,
343 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 344 { 0x0001, 0x8168,
345 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 346 {0,},
347};
348
349MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
350
6f0333b8 351static int rx_buf_sz = 16383;
27896c83 352static int use_dac = -1;
b57b7e5a
SH		 353static struct {
354 u32 msg_enable;
355} debug = { -1 };
1da177e4 356
07d3f51f
FR		 357enum rtl_registers {
358 MAC0 = 0, /* Ethernet hardware address. */
773d2021 359 MAC4 = 4,
07d3f51f
FR		 360 MAR0 = 8, /* Multicast filter. */
361 CounterAddrLow = 0x10,
362 CounterAddrHigh = 0x14,
363 TxDescStartAddrLow = 0x20,
364 TxDescStartAddrHigh = 0x24,
365 TxHDescStartAddrLow = 0x28,
366 TxHDescStartAddrHigh = 0x2c,
367 FLASH = 0x30,
368 ERSR = 0x36,
369 ChipCmd = 0x37,
370 TxPoll = 0x38,
371 IntrMask = 0x3c,
372 IntrStatus = 0x3e,
4f6b00e5 373
07d3f51f 374 TxConfig = 0x40,
4f6b00e5
HW		 375#define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
376#define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
2b7b4318 377
4f6b00e5
HW		 378 RxConfig = 0x44,
379#define RX128_INT_EN (1 << 15) /* 8111c and later */
380#define RX_MULTI_EN (1 << 14) /* 8111c only */
381#define RXCFG_FIFO_SHIFT 13
382 /* No threshold before first PCI xfer */
383#define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
beb330a4 384#define RX_EARLY_OFF (1 << 11)
4f6b00e5
HW		 385#define RXCFG_DMA_SHIFT 8
386 /* Unlimited maximum PCI burst. */
387#define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
2b7b4318 388
07d3f51f
FR		 389 RxMissed = 0x4c,
390 Cfg9346 = 0x50,
391 Config0 = 0x51,
392 Config1 = 0x52,
393 Config2 = 0x53,
d387b427
FR		 394#define PME_SIGNAL (1 << 5) /* 8168c and later */
395
07d3f51f
FR		 396 Config3 = 0x54,
397 Config4 = 0x55,
398 Config5 = 0x56,
399 MultiIntr = 0x5c,
400 PHYAR = 0x60,
07d3f51f
FR		 401 PHYstatus = 0x6c,
402 RxMaxSize = 0xda,
403 CPlusCmd = 0xe0,
404 IntrMitigate = 0xe2,
50970831
FR		 405
406#define RTL_COALESCE_MASK 0x0f
407#define RTL_COALESCE_SHIFT 4
408#define RTL_COALESCE_T_MAX (RTL_COALESCE_MASK)
409#define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_MASK << 2)
410
07d3f51f
FR		 411 RxDescAddrLow = 0xe4,
412 RxDescAddrHigh = 0xe8,
f0298f81 413 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
414
415#define NoEarlyTx 0x3f /* Max value : no early transmit. */
416
417 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
418
419#define TxPacketMax (8064 >> 7)
3090bd9a 420#define EarlySize 0x27
f0298f81 421
07d3f51f
FR		 422 FuncEvent = 0xf0,
423 FuncEventMask = 0xf4,
424 FuncPresetState = 0xf8,
935e2218
CHL		 425 IBCR0 = 0xf8,
426 IBCR2 = 0xf9,
427 IBIMR0 = 0xfa,
428 IBISR0 = 0xfb,
07d3f51f 429 FuncForceEvent = 0xfc,
1da177e4
LT		 430};
431
f162a5d1
FR		 432enum rtl8110_registers {
433 TBICSR = 0x64,
434 TBI_ANAR = 0x68,
435 TBI_LPAR = 0x6a,
436};
437
438enum rtl8168_8101_registers {
439 CSIDR = 0x64,
440 CSIAR = 0x68,
441#define CSIAR_FLAG 0x80000000
442#define CSIAR_WRITE_CMD 0x80000000
443#define CSIAR_BYTE_ENABLE 0x0f
444#define CSIAR_BYTE_ENABLE_SHIFT 12
445#define CSIAR_ADDR_MASK 0x0fff
7e18dca1
HW		 446#define CSIAR_FUNC_CARD 0x00000000
447#define CSIAR_FUNC_SDIO 0x00010000
448#define CSIAR_FUNC_NIC 0x00020000
45dd95c4 449#define CSIAR_FUNC_NIC2 0x00010000
065c27c1 450 PMCH = 0x6f,
f162a5d1
FR		 451 EPHYAR = 0x80,
452#define EPHYAR_FLAG 0x80000000
453#define EPHYAR_WRITE_CMD 0x80000000
454#define EPHYAR_REG_MASK 0x1f
455#define EPHYAR_REG_SHIFT 16
456#define EPHYAR_DATA_MASK 0xffff
5a5e4443 457 DLLPR = 0xd0,
4f6b00e5 458#define PFM_EN (1 << 6)
6e1d0b89 459#define TX_10M_PS_EN (1 << 7)
f162a5d1
FR		 460 DBG_REG = 0xd1,
461#define FIX_NAK_1 (1 << 4)
462#define FIX_NAK_2 (1 << 3)
5a5e4443
HW		 463 TWSI = 0xd2,
464 MCU = 0xd3,
4f6b00e5 465#define NOW_IS_OOB (1 << 7)
c558386b
HW		 466#define TX_EMPTY (1 << 5)
467#define RX_EMPTY (1 << 4)
468#define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
5a5e4443
HW		 469#define EN_NDP (1 << 3)
470#define EN_OOB_RESET (1 << 2)
c558386b 471#define LINK_LIST_RDY (1 << 1)
daf9df6d 472 EFUSEAR = 0xdc,
473#define EFUSEAR_FLAG 0x80000000
474#define EFUSEAR_WRITE_CMD 0x80000000
475#define EFUSEAR_READ_CMD 0x00000000
476#define EFUSEAR_REG_MASK 0x03ff
477#define EFUSEAR_REG_SHIFT 8
478#define EFUSEAR_DATA_MASK 0xff
6e1d0b89
CHL		 479 MISC_1 = 0xf2,
480#define PFM_D3COLD_EN (1 << 6)
f162a5d1
FR		 481};
482
c0e45c1c 483enum rtl8168_registers {
4f6b00e5
HW		 484 LED_FREQ = 0x1a,
485 EEE_LED = 0x1b,
b646d900 486 ERIDR = 0x70,
487 ERIAR = 0x74,
488#define ERIAR_FLAG 0x80000000
489#define ERIAR_WRITE_CMD 0x80000000
490#define ERIAR_READ_CMD 0x00000000
491#define ERIAR_ADDR_BYTE_ALIGN 4
b646d900 492#define ERIAR_TYPE_SHIFT 16
4f6b00e5
HW		 493#define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
494#define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
495#define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
935e2218 496#define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
4f6b00e5
HW		 497#define ERIAR_MASK_SHIFT 12
498#define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
499#define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
6e1d0b89 500#define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
c558386b 501#define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
4f6b00e5 502#define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
c0e45c1c 503 EPHY_RXER_NUM = 0x7c,
504 OCPDR = 0xb0, /* OCP GPHY access */
505#define OCPDR_WRITE_CMD 0x80000000
506#define OCPDR_READ_CMD 0x00000000
507#define OCPDR_REG_MASK 0x7f
508#define OCPDR_GPHY_REG_SHIFT 16
509#define OCPDR_DATA_MASK 0xffff
510 OCPAR = 0xb4,
511#define OCPAR_FLAG 0x80000000
512#define OCPAR_GPHY_WRITE_CMD 0x8000f060
513#define OCPAR_GPHY_READ_CMD 0x0000f060
c558386b 514 GPHY_OCP = 0xb8,
01dc7fec 515 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
516 MISC = 0xf0, /* 8168e only. */
cecb5fd7 517#define TXPLA_RST (1 << 29)
5598bfe5 518#define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
4f6b00e5 519#define PWM_EN (1 << 22)
c558386b 520#define RXDV_GATED_EN (1 << 19)
5598bfe5 521#define EARLY_TALLY_EN (1 << 16)
c0e45c1c 522};
523
07d3f51f 524enum rtl_register_content {
1da177e4 525 /* InterruptStatusBits */
07d3f51f
FR		 526 SYSErr = 0x8000,
527 PCSTimeout = 0x4000,
528 SWInt = 0x0100,
529 TxDescUnavail = 0x0080,
530 RxFIFOOver = 0x0040,
531 LinkChg = 0x0020,
532 RxOverflow = 0x0010,
533 TxErr = 0x0008,
534 TxOK = 0x0004,
535 RxErr = 0x0002,
536 RxOK = 0x0001,
1da177e4
LT		 537
538 /* RxStatusDesc */
e03f33af 539 RxBOVF = (1 << 24),
9dccf611
FR		 540 RxFOVF = (1 << 23),
541 RxRWT = (1 << 22),
542 RxRES = (1 << 21),
543 RxRUNT = (1 << 20),
544 RxCRC = (1 << 19),
1da177e4
LT		 545
546 /* ChipCmdBits */
4f6b00e5 547 StopReq = 0x80,
07d3f51f
FR		 548 CmdReset = 0x10,
549 CmdRxEnb = 0x08,
550 CmdTxEnb = 0x04,
551 RxBufEmpty = 0x01,
1da177e4 552
275391a4
FR		 553 /* TXPoll register p.5 */
554 HPQ = 0x80, /* Poll cmd on the high prio queue */
555 NPQ = 0x40, /* Poll cmd on the low prio queue */
556 FSWInt = 0x01, /* Forced software interrupt */
557
1da177e4 558 /* Cfg9346Bits */
07d3f51f
FR		 559 Cfg9346_Lock = 0x00,
560 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 561
562 /* rx_mode_bits */
07d3f51f
FR		 563 AcceptErr = 0x20,
564 AcceptRunt = 0x10,
565 AcceptBroadcast = 0x08,
566 AcceptMulticast = 0x04,
567 AcceptMyPhys = 0x02,
568 AcceptAllPhys = 0x01,
1687b566 569#define RX_CONFIG_ACCEPT_MASK 0x3f
1da177e4 570
1da177e4
LT		 571 /* TxConfigBits */
572 TxInterFrameGapShift = 24,
573 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
574
5d06a99f 575 /* Config1 register p.24 */
f162a5d1
FR		 576 LEDS1 = (1 << 7),
577 LEDS0 = (1 << 6),
f162a5d1
FR		 578 Speed_down = (1 << 4),
579 MEMMAP = (1 << 3),
580 IOMAP = (1 << 2),
581 VPD = (1 << 1),
5d06a99f
FR		 582 PMEnable = (1 << 0), /* Power Management Enable */
583
6dccd16b 584 /* Config2 register p. 25 */
57538c4a 585 ClkReqEn = (1 << 7), /* Clock Request Enable */
2ca6cf06 586 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
6dccd16b
FR		 587 PCI_Clock_66MHz = 0x01,
588 PCI_Clock_33MHz = 0x00,
589
61a4dcc2
FR		 590 /* Config3 register p.25 */
591 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
592 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
d58d46b5 593 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
b51ecea8 594 Rdy_to_L23 = (1 << 1), /* L23 Enable */
f162a5d1 595 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 596
d58d46b5
FR		 597 /* Config4 register */
598 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
599
5d06a99f 600 /* Config5 register p.27 */
61a4dcc2
FR		 601 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
602 MWF = (1 << 5), /* Accept Multicast wakeup frame */
603 UWF = (1 << 4), /* Accept Unicast wakeup frame */
cecb5fd7 604 Spi_en = (1 << 3),
61a4dcc2 605 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f 606 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
57538c4a 607 ASPM_en = (1 << 0), /* ASPM enable */
5d06a99f 608
1da177e4
LT		 609 /* TBICSR p.28 */
610 TBIReset = 0x80000000,
611 TBILoopback = 0x40000000,
612 TBINwEnable = 0x20000000,
613 TBINwRestart = 0x10000000,
614 TBILinkOk = 0x02000000,
615 TBINwComplete = 0x01000000,
616
617 /* CPlusCmd p.31 */
f162a5d1
FR		 618 EnableBist = (1 << 15), // 8168 8101
619 Mac_dbgo_oe = (1 << 14), // 8168 8101
620 Normal_mode = (1 << 13), // unused
621 Force_half_dup = (1 << 12), // 8168 8101
622 Force_rxflow_en = (1 << 11), // 8168 8101
623 Force_txflow_en = (1 << 10), // 8168 8101
624 Cxpl_dbg_sel = (1 << 9), // 8168 8101
625 ASF = (1 << 8), // 8168 8101
626 PktCntrDisable = (1 << 7), // 8168 8101
627 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 628 RxVlan = (1 << 6),
629 RxChkSum = (1 << 5),
630 PCIDAC = (1 << 4),
631 PCIMulRW = (1 << 3),
0e485150
FR		 632 INTT_0 = 0x0000, // 8168
633 INTT_1 = 0x0001, // 8168
634 INTT_2 = 0x0002, // 8168
635 INTT_3 = 0x0003, // 8168
1da177e4
LT		 636
637 /* rtl8169_PHYstatus */
07d3f51f
FR		 638 TBI_Enable = 0x80,
639 TxFlowCtrl = 0x40,
640 RxFlowCtrl = 0x20,
641 _1000bpsF = 0x10,
642 _100bps = 0x08,
643 _10bps = 0x04,
644 LinkStatus = 0x02,
645 FullDup = 0x01,
1da177e4 646
1da177e4 647 /* _TBICSRBit */
07d3f51f 648 TBILinkOK = 0x02000000,
d4a3a0fc 649
6e85d5ad
CV		 650 /* ResetCounterCommand */
651 CounterReset = 0x1,
652
d4a3a0fc 653 /* DumpCounterCommand */
07d3f51f 654 CounterDump = 0x8,
6e1d0b89
CHL		 655
656 /* magic enable v2 */
657 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */
1da177e4
LT		 658};
659
2b7b4318
FR		 660enum rtl_desc_bit {
661 /* First doubleword. */
1da177e4
LT		 662 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
663 RingEnd = (1 << 30), /* End of descriptor ring */
664 FirstFrag = (1 << 29), /* First segment of a packet */
665 LastFrag = (1 << 28), /* Final segment of a packet */
2b7b4318
FR		 666};
667
668/* Generic case. */
669enum rtl_tx_desc_bit {
670 /* First doubleword. */
671 TD_LSO = (1 << 27), /* Large Send Offload */
672#define TD_MSS_MAX 0x07ffu /* MSS value */
1da177e4 673
2b7b4318
FR		 674 /* Second doubleword. */
675 TxVlanTag = (1 << 17), /* Add VLAN tag */
676};
677
678/* 8169, 8168b and 810x except 8102e. */
679enum rtl_tx_desc_bit_0 {
680 /* First doubleword. */
681#define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
682 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
683 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
684 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
685};
686
687/* 8102e, 8168c and beyond. */
688enum rtl_tx_desc_bit_1 {
bdfa4ed6 689 /* First doubleword. */
690 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */
e974604b 691 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */
bdfa4ed6 692#define GTTCPHO_SHIFT 18
e974604b 693#define GTTCPHO_MAX 0x7fU
bdfa4ed6 694
2b7b4318 695 /* Second doubleword. */
e974604b 696#define TCPHO_SHIFT 18
697#define TCPHO_MAX 0x3ffU
2b7b4318 698#define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
e974604b 699 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */
700 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */
2b7b4318
FR		 701 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
702 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
703};
1da177e4 704
2b7b4318 705enum rtl_rx_desc_bit {
1da177e4
LT		 706 /* Rx private */
707 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
9b60047a 708 PID0 = (1 << 17), /* Protocol ID bit 0/2 */
1da177e4
LT		 709
710#define RxProtoUDP (PID1)
711#define RxProtoTCP (PID0)
712#define RxProtoIP (PID1 | PID0)
713#define RxProtoMask RxProtoIP
714
715 IPFail = (1 << 16), /* IP checksum failed */
716 UDPFail = (1 << 15), /* UDP/IP checksum failed */
717 TCPFail = (1 << 14), /* TCP/IP checksum failed */
718 RxVlanTag = (1 << 16), /* VLAN tag available */
719};
720
721#define RsvdMask 0x3fffc000
722
723struct TxDesc {
6cccd6e7
REB		 724 __le32 opts1;
725 __le32 opts2;
726 __le64 addr;
1da177e4
LT		 727};
728
729struct RxDesc {
6cccd6e7
REB		 730 __le32 opts1;
731 __le32 opts2;
732 __le64 addr;
1da177e4
LT		 733};
734
735struct ring_info {
736 struct sk_buff *skb;
737 u32 len;
738 u8 __pad[sizeof(void *) - sizeof(u32)];
739};
740
f23e7fda 741enum features {
41450d46 742 RTL_FEATURE_GMII = (1 << 0),
f23e7fda
FR		 743};
744
355423d0
IV		 745struct rtl8169_counters {
746 __le64 tx_packets;
747 __le64 rx_packets;
748 __le64 tx_errors;
749 __le32 rx_errors;
750 __le16 rx_missed;
751 __le16 align_errors;
752 __le32 tx_one_collision;
753 __le32 tx_multi_collision;
754 __le64 rx_unicast;
755 __le64 rx_broadcast;
756 __le32 rx_multicast;
757 __le16 tx_aborted;
758 __le16 tx_underun;
759};
760
6e85d5ad
CV		 761struct rtl8169_tc_offsets {
762 bool inited;
763 __le64 tx_errors;
764 __le32 tx_multi_collision;
6e85d5ad
CV		 765 __le16 tx_aborted;
766};
767
da78dbff 768enum rtl_flag {
4135fe46 769 RTL_FLAG_TASK_ENABLED = 0,
da78dbff
FR		 770 RTL_FLAG_TASK_SLOW_PENDING,
771 RTL_FLAG_TASK_RESET_PENDING,
772 RTL_FLAG_TASK_PHY_PENDING,
773 RTL_FLAG_MAX
774};
775
8027aa24
JW		 776struct rtl8169_stats {
777 u64 packets;
778 u64 bytes;
779 struct u64_stats_sync syncp;
780};
781
1da177e4
LT		 782struct rtl8169_private {
783 void __iomem *mmio_addr; /* memory map physical address */
cecb5fd7 784 struct pci_dev *pci_dev;
c4028958 785 struct net_device *dev;
bea3348e 786 struct napi_struct napi;
b57b7e5a 787 u32 msg_enable;
2b7b4318
FR		 788 u16 txd_version;
789 u16 mac_version;
1da177e4
LT		 790 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
791 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
1da177e4 792 u32 dirty_tx;
8027aa24
JW		 793 struct rtl8169_stats rx_stats;
794 struct rtl8169_stats tx_stats;
1da177e4
LT		 795 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
796 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
797 dma_addr_t TxPhyAddr;
798 dma_addr_t RxPhyAddr;
6f0333b8 799 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
1da177e4 800 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
1da177e4
LT		 801 struct timer_list timer;
802 u16 cp_cmd;
da78dbff
FR		 803
804 u16 event_slow;
50970831 805 const struct rtl_coalesce_info *coalesce_info;
c0e45c1c 806
807 struct mdio_ops {
24192210
FR		 808 void (*write)(struct rtl8169_private *, int, int);
809 int (*read)(struct rtl8169_private *, int);
c0e45c1c 810 } mdio_ops;
811
065c27c1 812 struct pll_power_ops {
813 void (*down)(struct rtl8169_private *);
814 void (*up)(struct rtl8169_private *);
815 } pll_power_ops;
816
d58d46b5
FR		 817 struct jumbo_ops {
818 void (*enable)(struct rtl8169_private *);
819 void (*disable)(struct rtl8169_private *);
820 } jumbo_ops;
821
beb1fe18 822 struct csi_ops {
52989f0e
FR		 823 void (*write)(struct rtl8169_private *, int, int);
824 u32 (*read)(struct rtl8169_private *, int);
beb1fe18
HW		 825 } csi_ops;
826
54405cde 827 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
6fa1ba61
PR		 828 int (*get_link_ksettings)(struct net_device *,
829 struct ethtool_link_ksettings *);
4da19633 830 void (*phy_reset_enable)(struct rtl8169_private *tp);
07ce4064 831 void (*hw_start)(struct net_device *);
4da19633 832 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
1da177e4 833 unsigned int (*link_ok)(void __iomem *);
8b4ab28d 834 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
5888d3fc 835 bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
4422bcd4
FR		 836
837 struct {
da78dbff
FR		 838 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
839 struct mutex mutex;
4422bcd4
FR		 840 struct work_struct work;
841 } wk;
842
f23e7fda 843 unsigned features;
ccdffb9a
FR		 844
845 struct mii_if_info mii;
42020320
CV		 846 dma_addr_t counters_phys_addr;
847 struct rtl8169_counters *counters;
6e85d5ad 848 struct rtl8169_tc_offsets tc_offset;
e1759441 849 u32 saved_wolopts;
e03f33af 850 u32 opts1_mask;
f1e02ed1 851
b6ffd97f
FR		 852 struct rtl_fw {
853 const struct firmware *fw;
1c361efb
FR		 854
855#define RTL_VER_SIZE 32
856
857 char version[RTL_VER_SIZE];
858
859 struct rtl_fw_phy_action {
860 __le32 *code;
861 size_t size;
862 } phy_action;
b6ffd97f 863 } *rtl_fw;
497888cf 864#define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
c558386b
HW		 865
866 u32 ocp_base;
1da177e4
LT		 867};
868
979b6c13 869MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 870MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 871module_param(use_dac, int, 0);
4300e8c7 872MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 873module_param_named(debug, debug.msg_enable, int, 0);
874MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 875MODULE_LICENSE("GPL");
876MODULE_VERSION(RTL8169_VERSION);
bca03d5f 877MODULE_FIRMWARE(FIRMWARE_8168D_1);
878MODULE_FIRMWARE(FIRMWARE_8168D_2);
01dc7fec 879MODULE_FIRMWARE(FIRMWARE_8168E_1);
880MODULE_FIRMWARE(FIRMWARE_8168E_2);
bbb8af75 881MODULE_FIRMWARE(FIRMWARE_8168E_3);
5a5e4443 882MODULE_FIRMWARE(FIRMWARE_8105E_1);
c2218925
HW		 883MODULE_FIRMWARE(FIRMWARE_8168F_1);
884MODULE_FIRMWARE(FIRMWARE_8168F_2);
7e18dca1 885MODULE_FIRMWARE(FIRMWARE_8402_1);
b3d7b2f2 886MODULE_FIRMWARE(FIRMWARE_8411_1);
45dd95c4 887MODULE_FIRMWARE(FIRMWARE_8411_2);
5598bfe5 888MODULE_FIRMWARE(FIRMWARE_8106E_1);
58152cd4 889MODULE_FIRMWARE(FIRMWARE_8106E_2);
beb330a4 890MODULE_FIRMWARE(FIRMWARE_8168G_2);
57538c4a 891MODULE_FIRMWARE(FIRMWARE_8168G_3);
6e1d0b89
CHL		 892MODULE_FIRMWARE(FIRMWARE_8168H_1);
893MODULE_FIRMWARE(FIRMWARE_8168H_2);
a3bf5c42
FR		 894MODULE_FIRMWARE(FIRMWARE_8107E_1);
895MODULE_FIRMWARE(FIRMWARE_8107E_2);
1da177e4 896
da78dbff
FR		 897static void rtl_lock_work(struct rtl8169_private *tp)
898{
899 mutex_lock(&tp->wk.mutex);
900}
901
902static void rtl_unlock_work(struct rtl8169_private *tp)
903{
904 mutex_unlock(&tp->wk.mutex);
905}
906
d58d46b5
FR		 907static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
908{
7d7903b2
JL		 909 pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
910 PCI_EXP_DEVCTL_READRQ, force);
d58d46b5
FR		 911}
912
ffc46952
FR		 913struct rtl_cond {
914 bool (*check)(struct rtl8169_private *);
915 const char *msg;
916};
917
918static void rtl_udelay(unsigned int d)
919{
920 udelay(d);
921}
922
923static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
924 void (*delay)(unsigned int), unsigned int d, int n,
925 bool high)
926{
927 int i;
928
929 for (i = 0; i < n; i++) {
930 delay(d);
931 if (c->check(tp) == high)
932 return true;
933 }
82e316ef
FR		 934 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
935 c->msg, !high, n, d);
ffc46952
FR		 936 return false;
937}
938
939static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
940 const struct rtl_cond *c,
941 unsigned int d, int n)
942{
943 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
944}
945
946static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
947 const struct rtl_cond *c,
948 unsigned int d, int n)
949{
950 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
951}
952
953static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
954 const struct rtl_cond *c,
955 unsigned int d, int n)
956{
957 return rtl_loop_wait(tp, c, msleep, d, n, true);
958}
959
960static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
961 const struct rtl_cond *c,
962 unsigned int d, int n)
963{
964 return rtl_loop_wait(tp, c, msleep, d, n, false);
965}
966
967#define DECLARE_RTL_COND(name) \
968static bool name ## _check(struct rtl8169_private *); \
969 \
970static const struct rtl_cond name = { \
971 .check = name ## _check, \
972 .msg = #name \
973}; \
974 \
975static bool name ## _check(struct rtl8169_private *tp)
976
c558386b
HW		 977static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
978{
979 if (reg & 0xffff0001) {
980 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
981 return true;
982 }
983 return false;
984}
985
986DECLARE_RTL_COND(rtl_ocp_gphy_cond)
987{
988 void __iomem *ioaddr = tp->mmio_addr;
989
990 return RTL_R32(GPHY_OCP) & OCPAR_FLAG;
991}
992
993static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
994{
995 void __iomem *ioaddr = tp->mmio_addr;
996
997 if (rtl_ocp_reg_failure(tp, reg))
998 return;
999
1000 RTL_W32(GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
1001
1002 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
1003}
1004
1005static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
1006{
1007 void __iomem *ioaddr = tp->mmio_addr;
1008
1009 if (rtl_ocp_reg_failure(tp, reg))
1010 return 0;
1011
1012 RTL_W32(GPHY_OCP, reg << 15);
1013
1014 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
1015 (RTL_R32(GPHY_OCP) & 0xffff) : ~0;
1016}
1017
c558386b
HW		 1018static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1019{
1020 void __iomem *ioaddr = tp->mmio_addr;
1021
1022 if (rtl_ocp_reg_failure(tp, reg))
1023 return;
1024
1025 RTL_W32(OCPDR, OCPAR_FLAG | (reg << 15) | data);
c558386b
HW		 1026}
1027
1028static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1029{
1030 void __iomem *ioaddr = tp->mmio_addr;
1031
1032 if (rtl_ocp_reg_failure(tp, reg))
1033 return 0;
1034
1035 RTL_W32(OCPDR, reg << 15);
1036
3a83ad12 1037 return RTL_R32(OCPDR);
c558386b
HW		 1038}
1039
1040#define OCP_STD_PHY_BASE 0xa400
1041
1042static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
1043{
1044 if (reg == 0x1f) {
1045 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
1046 return;
1047 }
1048
1049 if (tp->ocp_base != OCP_STD_PHY_BASE)
1050 reg -= 0x10;
1051
1052 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
1053}
1054
1055static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1056{
1057 if (tp->ocp_base != OCP_STD_PHY_BASE)
1058 reg -= 0x10;
1059
1060 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
1061}
1062
eee3786f 1063static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
1064{
1065 if (reg == 0x1f) {
1066 tp->ocp_base = value << 4;
1067 return;
1068 }
1069
1070 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
1071}
1072
1073static int mac_mcu_read(struct rtl8169_private *tp, int reg)
1074{
1075 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
1076}
1077
ffc46952
FR		 1078DECLARE_RTL_COND(rtl_phyar_cond)
1079{
1080 void __iomem *ioaddr = tp->mmio_addr;
1081
1082 return RTL_R32(PHYAR) & 0x80000000;
1083}
1084
24192210 1085static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1da177e4 1086{
24192210 1087 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 1088
24192210 1089 RTL_W32(PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1da177e4 1090
ffc46952 1091 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
024a07ba 1092 /*
81a95f04
TT		 1093 * According to hardware specs a 20us delay is required after write
1094 * complete indication, but before sending next command.
024a07ba 1095 */
81a95f04 1096 udelay(20);
1da177e4
LT		 1097}
1098
24192210 1099static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1da177e4 1100{
24192210 1101 void __iomem *ioaddr = tp->mmio_addr;
ffc46952 1102 int value;
1da177e4 1103
24192210 1104 RTL_W32(PHYAR, 0x0 | (reg & 0x1f) << 16);
1da177e4 1105
ffc46952
FR		 1106 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1107 RTL_R32(PHYAR) & 0xffff : ~0;
1108
81a95f04
TT		 1109 /*
1110 * According to hardware specs a 20us delay is required after read
1111 * complete indication, but before sending next command.
1112 */
1113 udelay(20);
1114
1da177e4
LT		 1115 return value;
1116}
1117
935e2218
CHL		 1118DECLARE_RTL_COND(rtl_ocpar_cond)
1119{
1120 void __iomem *ioaddr = tp->mmio_addr;
1121
1122 return RTL_R32(OCPAR) & OCPAR_FLAG;
1123}
1124
24192210 1125static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
c0e45c1c 1126{
24192210 1127 void __iomem *ioaddr = tp->mmio_addr;
c0e45c1c 1128
24192210 1129 RTL_W32(OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
c0e45c1c 1130 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
1131 RTL_W32(EPHY_RXER_NUM, 0);
1132
ffc46952 1133 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
c0e45c1c 1134}
1135
24192210 1136static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
c0e45c1c 1137{
24192210
FR		 1138 r8168dp_1_mdio_access(tp, reg,
1139 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
c0e45c1c 1140}
1141
24192210 1142static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
c0e45c1c 1143{
24192210 1144 void __iomem *ioaddr = tp->mmio_addr;
c0e45c1c 1145
24192210 1146 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
c0e45c1c 1147
1148 mdelay(1);
1149 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
1150 RTL_W32(EPHY_RXER_NUM, 0);
1151
ffc46952
FR		 1152 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1153 RTL_R32(OCPDR) & OCPDR_DATA_MASK : ~0;
c0e45c1c 1154}
1155
e6de30d6 1156#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1157
1158static void r8168dp_2_mdio_start(void __iomem *ioaddr)
1159{
1160 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1161}
1162
1163static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
1164{
1165 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1166}
1167
24192210 1168static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
e6de30d6 1169{
24192210
FR		 1170 void __iomem *ioaddr = tp->mmio_addr;
1171
e6de30d6 1172 r8168dp_2_mdio_start(ioaddr);
1173
24192210 1174 r8169_mdio_write(tp, reg, value);
e6de30d6 1175
1176 r8168dp_2_mdio_stop(ioaddr);
1177}
1178
24192210 1179static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
e6de30d6 1180{
24192210 1181 void __iomem *ioaddr = tp->mmio_addr;
e6de30d6 1182 int value;
1183
1184 r8168dp_2_mdio_start(ioaddr);
1185
24192210 1186 value = r8169_mdio_read(tp, reg);
e6de30d6 1187
1188 r8168dp_2_mdio_stop(ioaddr);
1189
1190 return value;
1191}
1192
4da19633 1193static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
dacf8154 1194{
24192210 1195 tp->mdio_ops.write(tp, location, val);
dacf8154
FR		 1196}
1197
4da19633 1198static int rtl_readphy(struct rtl8169_private *tp, int location)
1199{
24192210 1200 return tp->mdio_ops.read(tp, location);
4da19633 1201}
1202
1203static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1204{
1205 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1206}
1207
76564428 1208static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
daf9df6d 1209{
1210 int val;
1211
4da19633 1212 val = rtl_readphy(tp, reg_addr);
76564428 1213 rtl_writephy(tp, reg_addr, (val & ~m) | p);
daf9df6d 1214}
1215
ccdffb9a
FR		 1216static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1217 int val)
1218{
1219 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1220
4da19633 1221 rtl_writephy(tp, location, val);
ccdffb9a
FR		 1222}
1223
1224static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1225{
1226 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1227
4da19633 1228 return rtl_readphy(tp, location);
ccdffb9a
FR		 1229}
1230
ffc46952
FR		 1231DECLARE_RTL_COND(rtl_ephyar_cond)
1232{
1233 void __iomem *ioaddr = tp->mmio_addr;
1234
1235 return RTL_R32(EPHYAR) & EPHYAR_FLAG;
1236}
1237
fdf6fc06 1238static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
dacf8154 1239{
fdf6fc06 1240 void __iomem *ioaddr = tp->mmio_addr;
dacf8154
FR		 1241
1242 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1243 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1244
ffc46952
FR		 1245 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1246
1247 udelay(10);
dacf8154
FR		 1248}
1249
fdf6fc06 1250static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
dacf8154 1251{
fdf6fc06 1252 void __iomem *ioaddr = tp->mmio_addr;
dacf8154
FR		 1253
1254 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1255
ffc46952
FR		 1256 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1257 RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0;
dacf8154
FR		 1258}
1259
935e2218
CHL		 1260DECLARE_RTL_COND(rtl_eriar_cond)
1261{
1262 void __iomem *ioaddr = tp->mmio_addr;
1263
1264 return RTL_R32(ERIAR) & ERIAR_FLAG;
1265}
1266
fdf6fc06
FR		 1267static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1268 u32 val, int type)
133ac40a 1269{
fdf6fc06 1270 void __iomem *ioaddr = tp->mmio_addr;
133ac40a
HW		 1271
1272 BUG_ON((addr & 3) || (mask == 0));
1273 RTL_W32(ERIDR, val);
1274 RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1275
ffc46952 1276 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
133ac40a
HW		 1277}
1278
fdf6fc06 1279static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
133ac40a 1280{
fdf6fc06 1281 void __iomem *ioaddr = tp->mmio_addr;
133ac40a
HW		 1282
1283 RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1284
ffc46952
FR		 1285 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1286 RTL_R32(ERIDR) : ~0;
133ac40a
HW		 1287}
1288
706123d0 1289static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
fdf6fc06 1290 u32 m, int type)
133ac40a
HW		 1291{
1292 u32 val;
1293
fdf6fc06
FR		 1294 val = rtl_eri_read(tp, addr, type);
1295 rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
133ac40a
HW		 1296}
1297
935e2218
CHL		 1298static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1299{
1300 void __iomem *ioaddr = tp->mmio_addr;
1301
1302 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1303 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1304 RTL_R32(OCPDR) : ~0;
1305}
1306
1307static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1308{
1309 return rtl_eri_read(tp, reg, ERIAR_OOB);
1310}
1311
1312static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1313{
1314 switch (tp->mac_version) {
1315 case RTL_GIGA_MAC_VER_27:
1316 case RTL_GIGA_MAC_VER_28:
1317 case RTL_GIGA_MAC_VER_31:
1318 return r8168dp_ocp_read(tp, mask, reg);
1319 case RTL_GIGA_MAC_VER_49:
1320 case RTL_GIGA_MAC_VER_50:
1321 case RTL_GIGA_MAC_VER_51:
1322 return r8168ep_ocp_read(tp, mask, reg);
1323 default:
1324 BUG();
1325 return ~0;
1326 }
1327}
1328
1329static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1330 u32 data)
1331{
1332 void __iomem *ioaddr = tp->mmio_addr;
1333
1334 RTL_W32(OCPDR, data);
1335 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1336 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1337}
1338
1339static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1340 u32 data)
1341{
1342 rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1343 data, ERIAR_OOB);
1344}
1345
1346static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
1347{
1348 switch (tp->mac_version) {
1349 case RTL_GIGA_MAC_VER_27:
1350 case RTL_GIGA_MAC_VER_28:
1351 case RTL_GIGA_MAC_VER_31:
1352 r8168dp_ocp_write(tp, mask, reg, data);
1353 break;
1354 case RTL_GIGA_MAC_VER_49:
1355 case RTL_GIGA_MAC_VER_50:
1356 case RTL_GIGA_MAC_VER_51:
1357 r8168ep_ocp_write(tp, mask, reg, data);
1358 break;
1359 default:
1360 BUG();
1361 break;
1362 }
1363}
1364
2a9b4d96
CHL		 1365static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
1366{
1367 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC);
1368
1369 ocp_write(tp, 0x1, 0x30, 0x00000001);
1370}
1371
1372#define OOB_CMD_RESET 0x00
1373#define OOB_CMD_DRIVER_START 0x05
1374#define OOB_CMD_DRIVER_STOP 0x06
1375
1376static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1377{
1378 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1379}
1380
1381DECLARE_RTL_COND(rtl_ocp_read_cond)
1382{
1383 u16 reg;
1384
1385 reg = rtl8168_get_ocp_reg(tp);
1386
1387 return ocp_read(tp, 0x0f, reg) & 0x00000800;
1388}
1389
935e2218 1390DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
2a9b4d96 1391{
935e2218
CHL		 1392 return ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1393}
1394
1395DECLARE_RTL_COND(rtl_ocp_tx_cond)
1396{
1397 void __iomem *ioaddr = tp->mmio_addr;
1398
810d7eaf 1399 return RTL_R8(IBISR0) & 0x20;
935e2218 1400}
2a9b4d96 1401
003609da
CHL		 1402static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1403{
1404 void __iomem *ioaddr = tp->mmio_addr;
1405
1406 RTL_W8(IBCR2, RTL_R8(IBCR2) & ~0x01);
810d7eaf 1407 rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
003609da
CHL		 1408 RTL_W8(IBISR0, RTL_R8(IBISR0) | 0x20);
1409 RTL_W8(IBCR0, RTL_R8(IBCR0) & ~0x01);
1410}
1411
935e2218
CHL		 1412static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1413{
1414 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
2a9b4d96
CHL		 1415 rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
1416}
1417
935e2218 1418static void rtl8168ep_driver_start(struct rtl8169_private *tp)
2a9b4d96 1419{
935e2218
CHL		 1420 ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1421 ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1422 rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1423}
1424
1425static void rtl8168_driver_start(struct rtl8169_private *tp)
1426{
1427 switch (tp->mac_version) {
1428 case RTL_GIGA_MAC_VER_27:
1429 case RTL_GIGA_MAC_VER_28:
1430 case RTL_GIGA_MAC_VER_31:
1431 rtl8168dp_driver_start(tp);
1432 break;
1433 case RTL_GIGA_MAC_VER_49:
1434 case RTL_GIGA_MAC_VER_50:
1435 case RTL_GIGA_MAC_VER_51:
1436 rtl8168ep_driver_start(tp);
1437 break;
1438 default:
1439 BUG();
1440 break;
1441 }
1442}
2a9b4d96 1443
935e2218
CHL		 1444static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1445{
1446 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
2a9b4d96
CHL		 1447 rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
1448}
1449
935e2218
CHL		 1450static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1451{
003609da 1452 rtl8168ep_stop_cmac(tp);
935e2218
CHL		 1453 ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1454 ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1455 rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1456}
1457
1458static void rtl8168_driver_stop(struct rtl8169_private *tp)
1459{
1460 switch (tp->mac_version) {
1461 case RTL_GIGA_MAC_VER_27:
1462 case RTL_GIGA_MAC_VER_28:
1463 case RTL_GIGA_MAC_VER_31:
1464 rtl8168dp_driver_stop(tp);
1465 break;
1466 case RTL_GIGA_MAC_VER_49:
1467 case RTL_GIGA_MAC_VER_50:
1468 case RTL_GIGA_MAC_VER_51:
1469 rtl8168ep_driver_stop(tp);
1470 break;
1471 default:
1472 BUG();
1473 break;
1474 }
1475}
1476
1477static int r8168dp_check_dash(struct rtl8169_private *tp)
2a9b4d96
CHL		 1478{
1479 u16 reg = rtl8168_get_ocp_reg(tp);
1480
1481 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
1482}
1483
935e2218
CHL		 1484static int r8168ep_check_dash(struct rtl8169_private *tp)
1485{
1486 return (ocp_read(tp, 0x0f, 0x128) & 0x00000001) ? 1 : 0;
1487}
1488
1489static int r8168_check_dash(struct rtl8169_private *tp)
1490{
1491 switch (tp->mac_version) {
1492 case RTL_GIGA_MAC_VER_27:
1493 case RTL_GIGA_MAC_VER_28:
1494 case RTL_GIGA_MAC_VER_31:
1495 return r8168dp_check_dash(tp);
1496 case RTL_GIGA_MAC_VER_49:
1497 case RTL_GIGA_MAC_VER_50:
1498 case RTL_GIGA_MAC_VER_51:
1499 return r8168ep_check_dash(tp);
1500 default:
1501 return 0;
1502 }
1503}
1504
c28aa385 1505struct exgmac_reg {
1506 u16 addr;
1507 u16 mask;
1508 u32 val;
1509};
1510
fdf6fc06 1511static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
c28aa385 1512 const struct exgmac_reg *r, int len)
1513{
1514 while (len-- > 0) {
fdf6fc06 1515 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
c28aa385 1516 r++;
1517 }
1518}
1519
ffc46952
FR		 1520DECLARE_RTL_COND(rtl_efusear_cond)
1521{
1522 void __iomem *ioaddr = tp->mmio_addr;
1523
1524 return RTL_R32(EFUSEAR) & EFUSEAR_FLAG;
1525}
1526
fdf6fc06 1527static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
daf9df6d 1528{
fdf6fc06 1529 void __iomem *ioaddr = tp->mmio_addr;
daf9df6d 1530
1531 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1532
ffc46952
FR		 1533 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1534 RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
daf9df6d 1535}
1536
9085cdfa
FR		 1537static u16 rtl_get_events(struct rtl8169_private *tp)
1538{
1539 void __iomem *ioaddr = tp->mmio_addr;
1540
1541 return RTL_R16(IntrStatus);
1542}
1543
1544static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1545{
1546 void __iomem *ioaddr = tp->mmio_addr;
1547
1548 RTL_W16(IntrStatus, bits);
1549 mmiowb();
1550}
1551
1552static void rtl_irq_disable(struct rtl8169_private *tp)
1553{
1554 void __iomem *ioaddr = tp->mmio_addr;
1555
1556 RTL_W16(IntrMask, 0);
1557 mmiowb();
1558}
1559
3e990ff5
FR		 1560static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1561{
1562 void __iomem *ioaddr = tp->mmio_addr;
1563
1564 RTL_W16(IntrMask, bits);
1565}
1566
da78dbff
FR		 1567#define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1568#define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1569#define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1570
1571static void rtl_irq_enable_all(struct rtl8169_private *tp)
1572{
1573 rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1574}
1575
811fd301 1576static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1da177e4 1577{
811fd301 1578 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 1579
9085cdfa 1580 rtl_irq_disable(tp);
da78dbff 1581 rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
811fd301 1582 RTL_R8(ChipCmd);
1da177e4
LT		 1583}
1584
4da19633 1585static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1da177e4 1586{
4da19633 1587 void __iomem *ioaddr = tp->mmio_addr;
1588
1da177e4
LT		 1589 return RTL_R32(TBICSR) & TBIReset;
1590}
1591
4da19633 1592static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1da177e4 1593{
4da19633 1594 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 1595}
1596
1597static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1598{
1599 return RTL_R32(TBICSR) & TBILinkOk;
1600}
1601
1602static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1603{
1604 return RTL_R8(PHYstatus) & LinkStatus;
1605}
1606
4da19633 1607static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1da177e4 1608{
4da19633 1609 void __iomem *ioaddr = tp->mmio_addr;
1610
1da177e4
LT		 1611 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1612}
1613
4da19633 1614static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1da177e4
LT		 1615{
1616 unsigned int val;
1617
4da19633 1618 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1619 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1da177e4
LT		 1620}
1621
70090424
HW		 1622static void rtl_link_chg_patch(struct rtl8169_private *tp)
1623{
1624 void __iomem *ioaddr = tp->mmio_addr;
1625 struct net_device *dev = tp->dev;
1626
1627 if (!netif_running(dev))
1628 return;
1629
b3d7b2f2
HW		 1630 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1631 tp->mac_version == RTL_GIGA_MAC_VER_38) {
70090424 1632 if (RTL_R8(PHYstatus) & _1000bpsF) {
fdf6fc06
FR		 1633 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1634 ERIAR_EXGMAC);
1635 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1636 ERIAR_EXGMAC);
70090424 1637 } else if (RTL_R8(PHYstatus) & _100bps) {
fdf6fc06
FR		 1638 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1639 ERIAR_EXGMAC);
1640 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1641 ERIAR_EXGMAC);
70090424 1642 } else {
fdf6fc06
FR		 1643 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1644 ERIAR_EXGMAC);
1645 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1646 ERIAR_EXGMAC);
70090424
HW		 1647 }
1648 /* Reset packet filter */
706123d0 1649 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
70090424 1650 ERIAR_EXGMAC);
706123d0 1651 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
70090424 1652 ERIAR_EXGMAC);
c2218925
HW		 1653 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1654 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1655 if (RTL_R8(PHYstatus) & _1000bpsF) {
fdf6fc06
FR		 1656 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1657 ERIAR_EXGMAC);
1658 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1659 ERIAR_EXGMAC);
c2218925 1660 } else {
fdf6fc06
FR		 1661 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1662 ERIAR_EXGMAC);
1663 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1664 ERIAR_EXGMAC);
c2218925 1665 }
7e18dca1
HW		 1666 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1667 if (RTL_R8(PHYstatus) & _10bps) {
fdf6fc06
FR		 1668 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1669 ERIAR_EXGMAC);
1670 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1671 ERIAR_EXGMAC);
7e18dca1 1672 } else {
fdf6fc06
FR		 1673 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1674 ERIAR_EXGMAC);
7e18dca1 1675 }
70090424
HW		 1676 }
1677}
1678
e4fbce74 1679static void __rtl8169_check_link_status(struct net_device *dev,
cecb5fd7
FR		 1680 struct rtl8169_private *tp,
1681 void __iomem *ioaddr, bool pm)
1da177e4 1682{
1da177e4 1683 if (tp->link_ok(ioaddr)) {
70090424 1684 rtl_link_chg_patch(tp);
e1759441 1685 /* This is to cancel a scheduled suspend if there's one. */
e4fbce74
RW		 1686 if (pm)
1687 pm_request_resume(&tp->pci_dev->dev);
1da177e4 1688 netif_carrier_on(dev);
1519e57f
FR		 1689 if (net_ratelimit())
1690 netif_info(tp, ifup, dev, "link up\n");
b57b7e5a 1691 } else {
1da177e4 1692 netif_carrier_off(dev);
bf82c189 1693 netif_info(tp, ifdown, dev, "link down\n");
e4fbce74 1694 if (pm)
10953db8 1695 pm_schedule_suspend(&tp->pci_dev->dev, 5000);
b57b7e5a 1696 }
1da177e4
LT		 1697}
1698
e4fbce74
RW		 1699static void rtl8169_check_link_status(struct net_device *dev,
1700 struct rtl8169_private *tp,
1701 void __iomem *ioaddr)
1702{
1703 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1704}
1705
e1759441
RW		 1706#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1707
1708static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
61a4dcc2 1709{
61a4dcc2
FR		 1710 void __iomem *ioaddr = tp->mmio_addr;
1711 u8 options;
e1759441 1712 u32 wolopts = 0;
61a4dcc2
FR		 1713
1714 options = RTL_R8(Config1);
1715 if (!(options & PMEnable))
e1759441 1716 return 0;
61a4dcc2
FR		 1717
1718 options = RTL_R8(Config3);
1719 if (options & LinkUp)
e1759441 1720 wolopts |= WAKE_PHY;
6e1d0b89 1721 switch (tp->mac_version) {
ac85bcdb
CHL		 1722 case RTL_GIGA_MAC_VER_34:
1723 case RTL_GIGA_MAC_VER_35:
1724 case RTL_GIGA_MAC_VER_36:
1725 case RTL_GIGA_MAC_VER_37:
1726 case RTL_GIGA_MAC_VER_38:
1727 case RTL_GIGA_MAC_VER_40:
1728 case RTL_GIGA_MAC_VER_41:
1729 case RTL_GIGA_MAC_VER_42:
1730 case RTL_GIGA_MAC_VER_43:
1731 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 1732 case RTL_GIGA_MAC_VER_45:
1733 case RTL_GIGA_MAC_VER_46:
ac85bcdb
CHL		 1734 case RTL_GIGA_MAC_VER_47:
1735 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 1736 case RTL_GIGA_MAC_VER_49:
1737 case RTL_GIGA_MAC_VER_50:
1738 case RTL_GIGA_MAC_VER_51:
6e1d0b89
CHL		 1739 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
1740 wolopts |= WAKE_MAGIC;
1741 break;
1742 default:
1743 if (options & MagicPacket)
1744 wolopts |= WAKE_MAGIC;
1745 break;
1746 }
61a4dcc2
FR		 1747
1748 options = RTL_R8(Config5);
1749 if (options & UWF)
e1759441 1750 wolopts |= WAKE_UCAST;
61a4dcc2 1751 if (options & BWF)
e1759441 1752 wolopts |= WAKE_BCAST;
61a4dcc2 1753 if (options & MWF)
e1759441 1754 wolopts |= WAKE_MCAST;
61a4dcc2 1755
e1759441 1756 return wolopts;
61a4dcc2
FR		 1757}
1758
e1759441 1759static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
61a4dcc2
FR		 1760{
1761 struct rtl8169_private *tp = netdev_priv(dev);
5fa80a32
CHL		 1762 struct device *d = &tp->pci_dev->dev;
1763
1764 pm_runtime_get_noresume(d);
e1759441 1765
da78dbff 1766 rtl_lock_work(tp);
e1759441
RW		 1767
1768 wol->supported = WAKE_ANY;
5fa80a32
CHL		 1769 if (pm_runtime_active(d))
1770 wol->wolopts = __rtl8169_get_wol(tp);
1771 else
1772 wol->wolopts = tp->saved_wolopts;
e1759441 1773
da78dbff 1774 rtl_unlock_work(tp);
5fa80a32
CHL		 1775
1776 pm_runtime_put_noidle(d);
e1759441
RW		 1777}
1778
1779static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1780{
61a4dcc2 1781 void __iomem *ioaddr = tp->mmio_addr;
6e1d0b89 1782 unsigned int i, tmp;
350f7596 1783 static const struct {
61a4dcc2
FR		 1784 u32 opt;
1785 u16 reg;
1786 u8 mask;
1787 } cfg[] = {
61a4dcc2 1788 { WAKE_PHY, Config3, LinkUp },
61a4dcc2
FR		 1789 { WAKE_UCAST, Config5, UWF },
1790 { WAKE_BCAST, Config5, BWF },
1791 { WAKE_MCAST, Config5, MWF },
6e1d0b89
CHL		 1792 { WAKE_ANY, Config5, LanWake },
1793 { WAKE_MAGIC, Config3, MagicPacket }
61a4dcc2 1794 };
851e6022 1795 u8 options;
61a4dcc2 1796
61a4dcc2
FR		 1797 RTL_W8(Cfg9346, Cfg9346_Unlock);
1798
6e1d0b89 1799 switch (tp->mac_version) {
ac85bcdb
CHL		 1800 case RTL_GIGA_MAC_VER_34:
1801 case RTL_GIGA_MAC_VER_35:
1802 case RTL_GIGA_MAC_VER_36:
1803 case RTL_GIGA_MAC_VER_37:
1804 case RTL_GIGA_MAC_VER_38:
1805 case RTL_GIGA_MAC_VER_40:
1806 case RTL_GIGA_MAC_VER_41:
1807 case RTL_GIGA_MAC_VER_42:
1808 case RTL_GIGA_MAC_VER_43:
1809 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 1810 case RTL_GIGA_MAC_VER_45:
1811 case RTL_GIGA_MAC_VER_46:
ac85bcdb
CHL		 1812 case RTL_GIGA_MAC_VER_47:
1813 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 1814 case RTL_GIGA_MAC_VER_49:
1815 case RTL_GIGA_MAC_VER_50:
1816 case RTL_GIGA_MAC_VER_51:
6e1d0b89
CHL		 1817 tmp = ARRAY_SIZE(cfg) - 1;
1818 if (wolopts & WAKE_MAGIC)
706123d0 1819 rtl_w0w1_eri(tp,
6e1d0b89
CHL		 1820 0x0dc,
1821 ERIAR_MASK_0100,
1822 MagicPacket_v2,
1823 0x0000,
1824 ERIAR_EXGMAC);
1825 else
706123d0 1826 rtl_w0w1_eri(tp,
6e1d0b89
CHL		 1827 0x0dc,
1828 ERIAR_MASK_0100,
1829 0x0000,
1830 MagicPacket_v2,
1831 ERIAR_EXGMAC);
1832 break;
1833 default:
1834 tmp = ARRAY_SIZE(cfg);
1835 break;
1836 }
1837
1838 for (i = 0; i < tmp; i++) {
851e6022 1839 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
e1759441 1840 if (wolopts & cfg[i].opt)
61a4dcc2
FR		 1841 options |= cfg[i].mask;
1842 RTL_W8(cfg[i].reg, options);
1843 }
1844
851e6022
FR		 1845 switch (tp->mac_version) {
1846 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1847 options = RTL_R8(Config1) & ~PMEnable;
1848 if (wolopts)
1849 options |= PMEnable;
1850 RTL_W8(Config1, options);
1851 break;
1852 default:
d387b427
FR		 1853 options = RTL_R8(Config2) & ~PME_SIGNAL;
1854 if (wolopts)
1855 options |= PME_SIGNAL;
1856 RTL_W8(Config2, options);
851e6022
FR		 1857 break;
1858 }
1859
61a4dcc2 1860 RTL_W8(Cfg9346, Cfg9346_Lock);
e1759441
RW		 1861}
1862
1863static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1864{
1865 struct rtl8169_private *tp = netdev_priv(dev);
5fa80a32
CHL		 1866 struct device *d = &tp->pci_dev->dev;
1867
1868 pm_runtime_get_noresume(d);
e1759441 1869
da78dbff 1870 rtl_lock_work(tp);
61a4dcc2 1871
5fa80a32
CHL		 1872 if (pm_runtime_active(d))
1873 __rtl8169_set_wol(tp, wol->wolopts);
1874 else
1875 tp->saved_wolopts = wol->wolopts;
da78dbff
FR		 1876
1877 rtl_unlock_work(tp);
61a4dcc2 1878
ea80907f 1879 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1880
5fa80a32
CHL		 1881 pm_runtime_put_noidle(d);
1882
61a4dcc2
FR		 1883 return 0;
1884}
1885
31bd204f
FR		 1886static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1887{
85bffe6c 1888 return rtl_chip_infos[tp->mac_version].fw_name;
31bd204f
FR		 1889}
1890
1da177e4
LT		 1891static void rtl8169_get_drvinfo(struct net_device *dev,
1892 struct ethtool_drvinfo *info)
1893{
1894 struct rtl8169_private *tp = netdev_priv(dev);
b6ffd97f 1895 struct rtl_fw *rtl_fw = tp->rtl_fw;
1da177e4 1896
68aad78c
RJ		 1897 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1898 strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1899 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1c361efb 1900 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
8ac72d16
RJ		 1901 if (!IS_ERR_OR_NULL(rtl_fw))
1902 strlcpy(info->fw_version, rtl_fw->version,
1903 sizeof(info->fw_version));
1da177e4
LT		 1904}
1905
1906static int rtl8169_get_regs_len(struct net_device *dev)
1907{
1908 return R8169_REGS_SIZE;
1909}
1910
1911static int rtl8169_set_speed_tbi(struct net_device *dev,
54405cde 1912 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1da177e4
LT		 1913{
1914 struct rtl8169_private *tp = netdev_priv(dev);
1915 void __iomem *ioaddr = tp->mmio_addr;
1916 int ret = 0;
1917 u32 reg;
1918
1919 reg = RTL_R32(TBICSR);
1920 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1921 (duplex == DUPLEX_FULL)) {
1922 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1923 } else if (autoneg == AUTONEG_ENABLE)
1924 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1925 else {
bf82c189
JP		 1926 netif_warn(tp, link, dev,
1927 "incorrect speed setting refused in TBI mode\n");
1da177e4
LT		 1928 ret = -EOPNOTSUPP;
1929 }
1930
1931 return ret;
1932}
1933
1934static int rtl8169_set_speed_xmii(struct net_device *dev,
54405cde 1935 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1da177e4
LT		 1936{
1937 struct rtl8169_private *tp = netdev_priv(dev);
3577aa1b 1938 int giga_ctrl, bmcr;
54405cde 1939 int rc = -EINVAL;
1da177e4 1940
716b50a3 1941 rtl_writephy(tp, 0x1f, 0x0000);
1da177e4
LT		 1942
1943 if (autoneg == AUTONEG_ENABLE) {
3577aa1b 1944 int auto_nego;
1945
4da19633 1946 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
54405cde
ON		 1947 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1948 ADVERTISE_100HALF | ADVERTISE_100FULL);
1949
1950 if (adv & ADVERTISED_10baseT_Half)
1951 auto_nego |= ADVERTISE_10HALF;
1952 if (adv & ADVERTISED_10baseT_Full)
1953 auto_nego |= ADVERTISE_10FULL;
1954 if (adv & ADVERTISED_100baseT_Half)
1955 auto_nego |= ADVERTISE_100HALF;
1956 if (adv & ADVERTISED_100baseT_Full)
1957 auto_nego |= ADVERTISE_100FULL;
1958
3577aa1b 1959 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1da177e4 1960
4da19633 1961 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
3577aa1b 1962 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
bcf0bf90 1963
3577aa1b 1964 /* The 8100e/8101e/8102e do Fast Ethernet only. */
826e6cbd 1965 if (tp->mii.supports_gmii) {
54405cde
ON		 1966 if (adv & ADVERTISED_1000baseT_Half)
1967 giga_ctrl |= ADVERTISE_1000HALF;
1968 if (adv & ADVERTISED_1000baseT_Full)
1969 giga_ctrl |= ADVERTISE_1000FULL;
1970 } else if (adv & (ADVERTISED_1000baseT_Half |
1971 ADVERTISED_1000baseT_Full)) {
bf82c189
JP		 1972 netif_info(tp, link, dev,
1973 "PHY does not support 1000Mbps\n");
54405cde 1974 goto out;
bcf0bf90 1975 }
1da177e4 1976
3577aa1b 1977 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1978
4da19633 1979 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1980 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
3577aa1b 1981 } else {
3577aa1b 1982 if (speed == SPEED_10)
1983 bmcr = 0;
1984 else if (speed == SPEED_100)
1985 bmcr = BMCR_SPEED100;
1986 else
54405cde 1987 goto out;
3577aa1b 1988
1989 if (duplex == DUPLEX_FULL)
1990 bmcr |= BMCR_FULLDPLX;
2584fbc3
RS		 1991 }
1992
4da19633 1993 rtl_writephy(tp, MII_BMCR, bmcr);
3577aa1b 1994
cecb5fd7
FR		 1995 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1996 tp->mac_version == RTL_GIGA_MAC_VER_03) {
3577aa1b 1997 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
4da19633 1998 rtl_writephy(tp, 0x17, 0x2138);
1999 rtl_writephy(tp, 0x0e, 0x0260);
3577aa1b 2000 } else {
4da19633 2001 rtl_writephy(tp, 0x17, 0x2108);
2002 rtl_writephy(tp, 0x0e, 0x0000);
3577aa1b 2003 }
2004 }
2005
54405cde
ON		 2006 rc = 0;
2007out:
2008 return rc;
1da177e4
LT		 2009}
2010
2011static int rtl8169_set_speed(struct net_device *dev,
54405cde 2012 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1da177e4
LT		 2013{
2014 struct rtl8169_private *tp = netdev_priv(dev);
2015 int ret;
2016
54405cde 2017 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
4876cc1e
FR		 2018 if (ret < 0)
2019 goto out;
1da177e4 2020
4876cc1e 2021 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
c4556975
CHL		 2022 (advertising & ADVERTISED_1000baseT_Full) &&
2023 !pci_is_pcie(tp->pci_dev)) {
1da177e4 2024 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
4876cc1e
FR		 2025 }
2026out:
1da177e4
LT		 2027 return ret;
2028}
2029
c8f44aff
MM		 2030static netdev_features_t rtl8169_fix_features(struct net_device *dev,
2031 netdev_features_t features)
1da177e4 2032{
d58d46b5
FR		 2033 struct rtl8169_private *tp = netdev_priv(dev);
2034
2b7b4318 2035 if (dev->mtu > TD_MSS_MAX)
350fb32a 2036 features &= ~NETIF_F_ALL_TSO;
1da177e4 2037
d58d46b5
FR		 2038 if (dev->mtu > JUMBO_1K &&
2039 !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
2040 features &= ~NETIF_F_IP_CSUM;
2041
350fb32a 2042 return features;
1da177e4
LT		 2043}
2044
da78dbff
FR		 2045static void __rtl8169_set_features(struct net_device *dev,
2046 netdev_features_t features)
1da177e4
LT		 2047{
2048 struct rtl8169_private *tp = netdev_priv(dev);
da78dbff 2049 void __iomem *ioaddr = tp->mmio_addr;
929a031d 2050 u32 rx_config;
1da177e4 2051
929a031d 2052 rx_config = RTL_R32(RxConfig);
2053 if (features & NETIF_F_RXALL)
2054 rx_config |= (AcceptErr | AcceptRunt);
2055 else
2056 rx_config &= ~(AcceptErr | AcceptRunt);
1da177e4 2057
929a031d 2058 RTL_W32(RxConfig, rx_config);
350fb32a 2059
929a031d 2060 if (features & NETIF_F_RXCSUM)
2061 tp->cp_cmd |= RxChkSum;
2062 else
2063 tp->cp_cmd &= ~RxChkSum;
6bbe021d 2064
929a031d 2065 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2066 tp->cp_cmd |= RxVlan;
2067 else
2068 tp->cp_cmd &= ~RxVlan;
2069
2070 tp->cp_cmd |= RTL_R16(CPlusCmd) & ~(RxVlan | RxChkSum);
2071
2072 RTL_W16(CPlusCmd, tp->cp_cmd);
2073 RTL_R16(CPlusCmd);
da78dbff 2074}
1da177e4 2075
da78dbff
FR		 2076static int rtl8169_set_features(struct net_device *dev,
2077 netdev_features_t features)
2078{
2079 struct rtl8169_private *tp = netdev_priv(dev);
2080
929a031d 2081 features &= NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX;
2082
da78dbff 2083 rtl_lock_work(tp);
85911d71 2084 if (features ^ dev->features)
929a031d 2085 __rtl8169_set_features(dev, features);
da78dbff 2086 rtl_unlock_work(tp);
1da177e4
LT		 2087
2088 return 0;
2089}
2090
da78dbff 2091
810f4893 2092static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1da177e4 2093{
df8a39de
JP		 2094 return (skb_vlan_tag_present(skb)) ?
2095 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1da177e4
LT		 2096}
2097
7a8fc77b 2098static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1da177e4
LT		 2099{
2100 u32 opts2 = le32_to_cpu(desc->opts2);
1da177e4 2101
7a8fc77b 2102 if (opts2 & RxVlanTag)
86a9bad3 2103 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1da177e4
LT		 2104}
2105
6fa1ba61
PR		 2106static int rtl8169_get_link_ksettings_tbi(struct net_device *dev,
2107 struct ethtool_link_ksettings *cmd)
1da177e4
LT		 2108{
2109 struct rtl8169_private *tp = netdev_priv(dev);
2110 void __iomem *ioaddr = tp->mmio_addr;
2111 u32 status;
6fa1ba61 2112 u32 supported, advertising;
1da177e4 2113
6fa1ba61 2114 supported =
1da177e4 2115 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
6fa1ba61 2116 cmd->base.port = PORT_FIBRE;
1da177e4
LT		 2117
2118 status = RTL_R32(TBICSR);
6fa1ba61
PR		 2119 advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
2120 cmd->base.autoneg = !!(status & TBINwEnable);
1da177e4 2121
6fa1ba61
PR		 2122 cmd->base.speed = SPEED_1000;
2123 cmd->base.duplex = DUPLEX_FULL; /* Always set */
2124
2125 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
2126 supported);
2127 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
2128 advertising);
ccdffb9a
FR		 2129
2130 return 0;
1da177e4
LT		 2131}
2132
6fa1ba61
PR		 2133static int rtl8169_get_link_ksettings_xmii(struct net_device *dev,
2134 struct ethtool_link_ksettings *cmd)
1da177e4
LT		 2135{
2136 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 2137
82c01a84 2138 mii_ethtool_get_link_ksettings(&tp->mii, cmd);
2139
2140 return 0;
1da177e4
LT		 2141}
2142
6fa1ba61
PR		 2143static int rtl8169_get_link_ksettings(struct net_device *dev,
2144 struct ethtool_link_ksettings *cmd)
1da177e4
LT		 2145{
2146 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 2147 int rc;
1da177e4 2148
da78dbff 2149 rtl_lock_work(tp);
6fa1ba61 2150 rc = tp->get_link_ksettings(dev, cmd);
da78dbff 2151 rtl_unlock_work(tp);
1da177e4 2152
ccdffb9a 2153 return rc;
1da177e4
LT		 2154}
2155
9e77d7a5
TJ		 2156static int rtl8169_set_link_ksettings(struct net_device *dev,
2157 const struct ethtool_link_ksettings *cmd)
2158{
2159 struct rtl8169_private *tp = netdev_priv(dev);
2160 int rc;
2161 u32 advertising;
2162
2163 if (!ethtool_convert_link_mode_to_legacy_u32(&advertising,
2164 cmd->link_modes.advertising))
2165 return -EINVAL;
2166
2167 del_timer_sync(&tp->timer);
2168
2169 rtl_lock_work(tp);
2170 rc = rtl8169_set_speed(dev, cmd->base.autoneg, cmd->base.speed,
2171 cmd->base.duplex, advertising);
2172 rtl_unlock_work(tp);
2173
2174 return rc;
2175}
2176
1da177e4
LT		 2177static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2178 void *p)
2179{
5b0384f4 2180 struct rtl8169_private *tp = netdev_priv(dev);
15edae91
PW		 2181 u32 __iomem *data = tp->mmio_addr;
2182 u32 *dw = p;
2183 int i;
1da177e4 2184
da78dbff 2185 rtl_lock_work(tp);
15edae91
PW		 2186 for (i = 0; i < R8169_REGS_SIZE; i += 4)
2187 memcpy_fromio(dw++, data++, 4);
da78dbff 2188 rtl_unlock_work(tp);
1da177e4
LT		 2189}
2190
b57b7e5a
SH		 2191static u32 rtl8169_get_msglevel(struct net_device *dev)
2192{
2193 struct rtl8169_private *tp = netdev_priv(dev);
2194
2195 return tp->msg_enable;
2196}
2197
2198static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
2199{
2200 struct rtl8169_private *tp = netdev_priv(dev);
2201
2202 tp->msg_enable = value;
2203}
2204
d4a3a0fc
SH		 2205static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
2206 "tx_packets",
2207 "rx_packets",
2208 "tx_errors",
2209 "rx_errors",
2210 "rx_missed",
2211 "align_errors",
2212 "tx_single_collisions",
2213 "tx_multi_collisions",
2214 "unicast",
2215 "broadcast",
2216 "multicast",
2217 "tx_aborted",
2218 "tx_underrun",
2219};
2220
b9f2c044 2221static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 2222{
b9f2c044
JG		 2223 switch (sset) {
2224 case ETH_SS_STATS:
2225 return ARRAY_SIZE(rtl8169_gstrings);
2226 default:
2227 return -EOPNOTSUPP;
2228 }
d4a3a0fc
SH		 2229}
2230
42020320 2231DECLARE_RTL_COND(rtl_counters_cond)
6e85d5ad 2232{
6e85d5ad 2233 void __iomem *ioaddr = tp->mmio_addr;
6e85d5ad 2234
42020320 2235 return RTL_R32(CounterAddrLow) & (CounterReset | CounterDump);
6e85d5ad
CV		 2236}
2237
42020320 2238static bool rtl8169_do_counters(struct net_device *dev, u32 counter_cmd)
6e85d5ad
CV		 2239{
2240 struct rtl8169_private *tp = netdev_priv(dev);
2241 void __iomem *ioaddr = tp->mmio_addr;
42020320
CV		 2242 dma_addr_t paddr = tp->counters_phys_addr;
2243 u32 cmd;
6e85d5ad 2244
42020320 2245 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
a78e9366 2246 RTL_R32(CounterAddrHigh);
42020320
CV		 2247 cmd = (u64)paddr & DMA_BIT_MASK(32);
2248 RTL_W32(CounterAddrLow, cmd);
2249 RTL_W32(CounterAddrLow, cmd | counter_cmd);
6e85d5ad 2250
a78e9366 2251 return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
6e85d5ad
CV		 2252}
2253
2254static bool rtl8169_reset_counters(struct net_device *dev)
2255{
2256 struct rtl8169_private *tp = netdev_priv(dev);
6e85d5ad
CV		 2257
2258 /*
2259 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
2260 * tally counters.
2261 */
2262 if (tp->mac_version < RTL_GIGA_MAC_VER_19)
2263 return true;
2264
42020320 2265 return rtl8169_do_counters(dev, CounterReset);
ffc46952
FR		 2266}
2267
6e85d5ad 2268static bool rtl8169_update_counters(struct net_device *dev)
d4a3a0fc
SH		 2269{
2270 struct rtl8169_private *tp = netdev_priv(dev);
2271 void __iomem *ioaddr = tp->mmio_addr;
d4a3a0fc 2272
355423d0
IV		 2273 /*
2274 * Some chips are unable to dump tally counters when the receiver
2275 * is disabled.
2276 */
2277 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
6e85d5ad 2278 return true;
d4a3a0fc 2279
42020320 2280 return rtl8169_do_counters(dev, CounterDump);
6e85d5ad
CV		 2281}
2282
2283static bool rtl8169_init_counter_offsets(struct net_device *dev)
2284{
2285 struct rtl8169_private *tp = netdev_priv(dev);
42020320 2286 struct rtl8169_counters *counters = tp->counters;
6e85d5ad
CV		 2287 bool ret = false;
2288
2289 /*
2290 * rtl8169_init_counter_offsets is called from rtl_open. On chip
2291 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
2292 * reset by a power cycle, while the counter values collected by the
2293 * driver are reset at every driver unload/load cycle.
2294 *
2295 * To make sure the HW values returned by @get_stats64 match the SW
2296 * values, we collect the initial values at first open(*) and use them
2297 * as offsets to normalize the values returned by @get_stats64.
2298 *
2299 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
2300 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
2301 * set at open time by rtl_hw_start.
2302 */
2303
2304 if (tp->tc_offset.inited)
2305 return true;
2306
2307 /* If both, reset and update fail, propagate to caller. */
2308 if (rtl8169_reset_counters(dev))
2309 ret = true;
2310
2311 if (rtl8169_update_counters(dev))
2312 ret = true;
2313
42020320
CV		 2314 tp->tc_offset.tx_errors = counters->tx_errors;
2315 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
2316 tp->tc_offset.tx_aborted = counters->tx_aborted;
6e85d5ad
CV		 2317 tp->tc_offset.inited = true;
2318
2319 return ret;
d4a3a0fc
SH		 2320}
2321
355423d0
IV		 2322static void rtl8169_get_ethtool_stats(struct net_device *dev,
2323 struct ethtool_stats *stats, u64 *data)
2324{
2325 struct rtl8169_private *tp = netdev_priv(dev);
e0636236 2326 struct device *d = &tp->pci_dev->dev;
42020320 2327 struct rtl8169_counters *counters = tp->counters;
355423d0
IV		 2328
2329 ASSERT_RTNL();
2330
e0636236
CHL		 2331 pm_runtime_get_noresume(d);
2332
2333 if (pm_runtime_active(d))
2334 rtl8169_update_counters(dev);
2335
2336 pm_runtime_put_noidle(d);
355423d0 2337
42020320
CV		 2338 data[0] = le64_to_cpu(counters->tx_packets);
2339 data[1] = le64_to_cpu(counters->rx_packets);
2340 data[2] = le64_to_cpu(counters->tx_errors);
2341 data[3] = le32_to_cpu(counters->rx_errors);
2342 data[4] = le16_to_cpu(counters->rx_missed);
2343 data[5] = le16_to_cpu(counters->align_errors);
2344 data[6] = le32_to_cpu(counters->tx_one_collision);
2345 data[7] = le32_to_cpu(counters->tx_multi_collision);
2346 data[8] = le64_to_cpu(counters->rx_unicast);
2347 data[9] = le64_to_cpu(counters->rx_broadcast);
2348 data[10] = le32_to_cpu(counters->rx_multicast);
2349 data[11] = le16_to_cpu(counters->tx_aborted);
2350 data[12] = le16_to_cpu(counters->tx_underun);
355423d0
IV		 2351}
2352
d4a3a0fc
SH		 2353static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2354{
2355 switch(stringset) {
2356 case ETH_SS_STATS:
2357 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
2358 break;
2359 }
2360}
2361
f0903ea3
FF		 2362static int rtl8169_nway_reset(struct net_device *dev)
2363{
2364 struct rtl8169_private *tp = netdev_priv(dev);
2365
2366 return mii_nway_restart(&tp->mii);
2367}
2368
50970831
FR		 2369/*
2370 * Interrupt coalescing
2371 *
2372 * > 1 - the availability of the IntrMitigate (0xe2) register through the
2373 * > 8169, 8168 and 810x line of chipsets
2374 *
2375 * 8169, 8168, and 8136(810x) serial chipsets support it.
2376 *
2377 * > 2 - the Tx timer unit at gigabit speed
2378 *
2379 * The unit of the timer depends on both the speed and the setting of CPlusCmd
2380 * (0xe0) bit 1 and bit 0.
2381 *
2382 * For 8169
2383 * bit[1:0] \ speed 1000M 100M 10M
2384 * 0 0 320ns 2.56us 40.96us
2385 * 0 1 2.56us 20.48us 327.7us
2386 * 1 0 5.12us 40.96us 655.4us
2387 * 1 1 10.24us 81.92us 1.31ms
2388 *
2389 * For the other
2390 * bit[1:0] \ speed 1000M 100M 10M
2391 * 0 0 5us 2.56us 40.96us
2392 * 0 1 40us 20.48us 327.7us
2393 * 1 0 80us 40.96us 655.4us
2394 * 1 1 160us 81.92us 1.31ms
2395 */
2396
2397/* rx/tx scale factors for one particular CPlusCmd[0:1] value */
2398struct rtl_coalesce_scale {
2399 /* Rx / Tx */
2400 u32 nsecs[2];
2401};
2402
2403/* rx/tx scale factors for all CPlusCmd[0:1] cases */
2404struct rtl_coalesce_info {
2405 u32 speed;
2406 struct rtl_coalesce_scale scalev[4]; /* each CPlusCmd[0:1] case */
2407};
2408
2409/* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
2410#define rxtx_x1822(r, t) { \
2411 {{(r), (t)}}, \
2412 {{(r)*8, (t)*8}}, \
2413 {{(r)*8*2, (t)*8*2}}, \
2414 {{(r)*8*2*2, (t)*8*2*2}}, \
2415}
2416static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
2417 /* speed delays: rx00 tx00 */
2418 { SPEED_10, rxtx_x1822(40960, 40960) },
2419 { SPEED_100, rxtx_x1822( 2560, 2560) },
2420 { SPEED_1000, rxtx_x1822( 320, 320) },
2421 { 0 },
2422};
2423
2424static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
2425 /* speed delays: rx00 tx00 */
2426 { SPEED_10, rxtx_x1822(40960, 40960) },
2427 { SPEED_100, rxtx_x1822( 2560, 2560) },
2428 { SPEED_1000, rxtx_x1822( 5000, 5000) },
2429 { 0 },
2430};
2431#undef rxtx_x1822
2432
2433/* get rx/tx scale vector corresponding to current speed */
2434static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
2435{
2436 struct rtl8169_private *tp = netdev_priv(dev);
2437 struct ethtool_link_ksettings ecmd;
2438 const struct rtl_coalesce_info *ci;
2439 int rc;
2440
2441 rc = rtl8169_get_link_ksettings(dev, &ecmd);
2442 if (rc < 0)
2443 return ERR_PTR(rc);
2444
2445 for (ci = tp->coalesce_info; ci->speed != 0; ci++) {
2446 if (ecmd.base.speed == ci->speed) {
2447 return ci;
2448 }
2449 }
2450
2451 return ERR_PTR(-ELNRNG);
2452}
2453
2454static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
2455{
2456 struct rtl8169_private *tp = netdev_priv(dev);
2457 void __iomem *ioaddr = tp->mmio_addr;
2458 const struct rtl_coalesce_info *ci;
2459 const struct rtl_coalesce_scale *scale;
2460 struct {
2461 u32 *max_frames;
2462 u32 *usecs;
2463 } coal_settings [] = {
2464 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
2465 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
2466 }, *p = coal_settings;
2467 int i;
2468 u16 w;
2469
2470 memset(ec, 0, sizeof(*ec));
2471
2472 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
2473 ci = rtl_coalesce_info(dev);
2474 if (IS_ERR(ci))
2475 return PTR_ERR(ci);
2476
2477 scale = &ci->scalev[RTL_R16(CPlusCmd) & 3];
2478
2479 /* read IntrMitigate and adjust according to scale */
2480 for (w = RTL_R16(IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
2481 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
2482 w >>= RTL_COALESCE_SHIFT;
2483 *p->usecs = w & RTL_COALESCE_MASK;
2484 }
2485
2486 for (i = 0; i < 2; i++) {
2487 p = coal_settings + i;
2488 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
2489
2490 /*
2491 * ethtool_coalesce says it is illegal to set both usecs and
2492 * max_frames to 0.
2493 */
2494 if (!*p->usecs && !*p->max_frames)
2495 *p->max_frames = 1;
2496 }
2497
2498 return 0;
2499}
2500
2501/* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
2502static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
2503 struct net_device *dev, u32 nsec, u16 *cp01)
2504{
2505 const struct rtl_coalesce_info *ci;
2506 u16 i;
2507
2508 ci = rtl_coalesce_info(dev);
2509 if (IS_ERR(ci))
2510 return ERR_CAST(ci);
2511
2512 for (i = 0; i < 4; i++) {
2513 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
2514 ci->scalev[i].nsecs[1]);
2515 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
2516 *cp01 = i;
2517 return &ci->scalev[i];
2518 }
2519 }
2520
2521 return ERR_PTR(-EINVAL);
2522}
2523
2524static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
2525{
2526 struct rtl8169_private *tp = netdev_priv(dev);
2527 void __iomem *ioaddr = tp->mmio_addr;
2528 const struct rtl_coalesce_scale *scale;
2529 struct {
2530 u32 frames;
2531 u32 usecs;
2532 } coal_settings [] = {
2533 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
2534 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
2535 }, *p = coal_settings;
2536 u16 w = 0, cp01;
2537 int i;
2538
2539 scale = rtl_coalesce_choose_scale(dev,
2540 max(p[0].usecs, p[1].usecs) * 1000, &cp01);
2541 if (IS_ERR(scale))
2542 return PTR_ERR(scale);
2543
2544 for (i = 0; i < 2; i++, p++) {
2545 u32 units;
2546
2547 /*
2548 * accept max_frames=1 we returned in rtl_get_coalesce.
2549 * accept it not only when usecs=0 because of e.g. the following scenario:
2550 *
2551 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
2552 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
2553 * - then user does `ethtool -C eth0 rx-usecs 100`
2554 *
2555 * since ethtool sends to kernel whole ethtool_coalesce
2556 * settings, if we do not handle rx_usecs=!0, rx_frames=1
2557 * we'll reject it below in `frames % 4 != 0`.
2558 */
2559 if (p->frames == 1) {
2560 p->frames = 0;
2561 }
2562
2563 units = p->usecs * 1000 / scale->nsecs[i];
2564 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
2565 return -EINVAL;
2566
2567 w <<= RTL_COALESCE_SHIFT;
2568 w |= units;
2569 w <<= RTL_COALESCE_SHIFT;
2570 w |= p->frames >> 2;
2571 }
2572
2573 rtl_lock_work(tp);
2574
2575 RTL_W16(IntrMitigate, swab16(w));
2576
2577 tp->cp_cmd = (tp->cp_cmd & ~3) | cp01;
2578 RTL_W16(CPlusCmd, tp->cp_cmd);
2579 RTL_R16(CPlusCmd);
2580
2581 rtl_unlock_work(tp);
2582
2583 return 0;
2584}
2585
7282d491 2586static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 2587 .get_drvinfo = rtl8169_get_drvinfo,
2588 .get_regs_len = rtl8169_get_regs_len,
2589 .get_link = ethtool_op_get_link,
50970831
FR		 2590 .get_coalesce = rtl_get_coalesce,
2591 .set_coalesce = rtl_set_coalesce,
b57b7e5a
SH		 2592 .get_msglevel = rtl8169_get_msglevel,
2593 .set_msglevel = rtl8169_set_msglevel,
1da177e4 2594 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 2595 .get_wol = rtl8169_get_wol,
2596 .set_wol = rtl8169_set_wol,
d4a3a0fc 2597 .get_strings = rtl8169_get_strings,
b9f2c044 2598 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 2599 .get_ethtool_stats = rtl8169_get_ethtool_stats,
e1593bb1 2600 .get_ts_info = ethtool_op_get_ts_info,
f0903ea3 2601 .nway_reset = rtl8169_nway_reset,
6fa1ba61 2602 .get_link_ksettings = rtl8169_get_link_ksettings,
9e77d7a5 2603 .set_link_ksettings = rtl8169_set_link_ksettings,
1da177e4
LT		 2604};
2605
07d3f51f 2606static void rtl8169_get_mac_version(struct rtl8169_private *tp,
5d320a20 2607 struct net_device *dev, u8 default_version)
1da177e4 2608{
5d320a20 2609 void __iomem *ioaddr = tp->mmio_addr;
0e485150
FR		 2610 /*
2611 * The driver currently handles the 8168Bf and the 8168Be identically
2612 * but they can be identified more specifically through the test below
2613 * if needed:
2614 *
2615 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 2616 *
2617 * Same thing for the 8101Eb and the 8101Ec:
2618 *
2619 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 2620 */
3744100e 2621 static const struct rtl_mac_info {
1da177e4 2622 u32 mask;
e3cf0cc0 2623 u32 val;
1da177e4
LT		 2624 int mac_version;
2625 } mac_info[] = {
935e2218
CHL		 2626 /* 8168EP family. */
2627 { 0x7cf00000, 0x50200000, RTL_GIGA_MAC_VER_51 },
2628 { 0x7cf00000, 0x50100000, RTL_GIGA_MAC_VER_50 },
2629 { 0x7cf00000, 0x50000000, RTL_GIGA_MAC_VER_49 },
2630
6e1d0b89
CHL		 2631 /* 8168H family. */
2632 { 0x7cf00000, 0x54100000, RTL_GIGA_MAC_VER_46 },
2633 { 0x7cf00000, 0x54000000, RTL_GIGA_MAC_VER_45 },
2634
c558386b 2635 /* 8168G family. */
45dd95c4 2636 { 0x7cf00000, 0x5c800000, RTL_GIGA_MAC_VER_44 },
57538c4a 2637 { 0x7cf00000, 0x50900000, RTL_GIGA_MAC_VER_42 },
c558386b
HW		 2638 { 0x7cf00000, 0x4c100000, RTL_GIGA_MAC_VER_41 },
2639 { 0x7cf00000, 0x4c000000, RTL_GIGA_MAC_VER_40 },
2640
c2218925 2641 /* 8168F family. */
b3d7b2f2 2642 { 0x7c800000, 0x48800000, RTL_GIGA_MAC_VER_38 },
c2218925
HW		 2643 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
2644 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
2645
01dc7fec 2646 /* 8168E family. */
70090424 2647 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
01dc7fec 2648 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
2649 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
2650 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
2651
5b538df9 2652 /* 8168D family. */
daf9df6d 2653 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
2654 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
daf9df6d 2655 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
5b538df9 2656
e6de30d6 2657 /* 8168DP family. */
2658 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
2659 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
4804b3b3 2660 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
e6de30d6 2661
ef808d50 2662 /* 8168C family. */
17c99297 2663 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
ef3386f0 2664 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 2665 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 2666 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 2667 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
2668 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 2669 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
6fb07058 2670 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
ef808d50 2671 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 2672
2673 /* 8168B family. */
2674 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
2675 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
2676 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
2677 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
2678
2679 /* 8101 family. */
5598bfe5
HW		 2680 { 0x7cf00000, 0x44900000, RTL_GIGA_MAC_VER_39 },
2681 { 0x7c800000, 0x44800000, RTL_GIGA_MAC_VER_39 },
7e18dca1 2682 { 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37 },
36a0e6c2 2683 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
5a5e4443
HW		 2684 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
2685 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
2686 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2857ffb7
FR		 2687 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
2688 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
2689 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
2690 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
2691 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
2692 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 2693 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 2694 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 2695 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 2696 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
2697 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 2698 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
2699 /* FIXME: where did these entries come from ? -- FR */
2700 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
2701 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
2702
2703 /* 8110 family. */
2704 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
2705 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
2706 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
2707 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
2708 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
2709 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
2710
f21b75e9
JD		 2711 /* Catch-all */
2712 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
3744100e
FR		 2713 };
2714 const struct rtl_mac_info *p = mac_info;
1da177e4
LT		 2715 u32 reg;
2716
e3cf0cc0
FR		 2717 reg = RTL_R32(TxConfig);
2718 while ((reg & p->mask) != p->val)
1da177e4
LT		 2719 p++;
2720 tp->mac_version = p->mac_version;
5d320a20
FR		 2721
2722 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2723 netif_notice(tp, probe, dev,
2724 "unknown MAC, using family default\n");
2725 tp->mac_version = default_version;
58152cd4 2726 } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
2727 tp->mac_version = tp->mii.supports_gmii ?
2728 RTL_GIGA_MAC_VER_42 :
2729 RTL_GIGA_MAC_VER_43;
6e1d0b89
CHL		 2730 } else if (tp->mac_version == RTL_GIGA_MAC_VER_45) {
2731 tp->mac_version = tp->mii.supports_gmii ?
2732 RTL_GIGA_MAC_VER_45 :
2733 RTL_GIGA_MAC_VER_47;
2734 } else if (tp->mac_version == RTL_GIGA_MAC_VER_46) {
2735 tp->mac_version = tp->mii.supports_gmii ?
2736 RTL_GIGA_MAC_VER_46 :
2737 RTL_GIGA_MAC_VER_48;
5d320a20 2738 }
1da177e4
LT		 2739}
2740
2741static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2742{
bcf0bf90 2743 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 2744}
2745
867763c1
FR		 2746struct phy_reg {
2747 u16 reg;
2748 u16 val;
2749};
2750
4da19633 2751static void rtl_writephy_batch(struct rtl8169_private *tp,
2752 const struct phy_reg *regs, int len)
867763c1
FR		 2753{
2754 while (len-- > 0) {
4da19633 2755 rtl_writephy(tp, regs->reg, regs->val);
867763c1
FR		 2756 regs++;
2757 }
2758}
2759
bca03d5f 2760#define PHY_READ 0x00000000
2761#define PHY_DATA_OR 0x10000000
2762#define PHY_DATA_AND 0x20000000
2763#define PHY_BJMPN 0x30000000
eee3786f 2764#define PHY_MDIO_CHG 0x40000000
bca03d5f 2765#define PHY_CLEAR_READCOUNT 0x70000000
2766#define PHY_WRITE 0x80000000
2767#define PHY_READCOUNT_EQ_SKIP 0x90000000
2768#define PHY_COMP_EQ_SKIPN 0xa0000000
2769#define PHY_COMP_NEQ_SKIPN 0xb0000000
2770#define PHY_WRITE_PREVIOUS 0xc0000000
2771#define PHY_SKIPN 0xd0000000
2772#define PHY_DELAY_MS 0xe0000000
bca03d5f 2773
960aee6c
HW		 2774struct fw_info {
2775 u32 magic;
2776 char version[RTL_VER_SIZE];
2777 __le32 fw_start;
2778 __le32 fw_len;
2779 u8 chksum;
2780} __packed;
2781
1c361efb
FR		 2782#define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2783
2784static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
bca03d5f 2785{
b6ffd97f 2786 const struct firmware *fw = rtl_fw->fw;
960aee6c 2787 struct fw_info *fw_info = (struct fw_info *)fw->data;
1c361efb
FR		 2788 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2789 char *version = rtl_fw->version;
2790 bool rc = false;
2791
2792 if (fw->size < FW_OPCODE_SIZE)
2793 goto out;
960aee6c
HW		 2794
2795 if (!fw_info->magic) {
2796 size_t i, size, start;
2797 u8 checksum = 0;
2798
2799 if (fw->size < sizeof(*fw_info))
2800 goto out;
2801
2802 for (i = 0; i < fw->size; i++)
2803 checksum += fw->data[i];
2804 if (checksum != 0)
2805 goto out;
2806
2807 start = le32_to_cpu(fw_info->fw_start);
2808 if (start > fw->size)
2809 goto out;
2810
2811 size = le32_to_cpu(fw_info->fw_len);
2812 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2813 goto out;
2814
2815 memcpy(version, fw_info->version, RTL_VER_SIZE);
2816
2817 pa->code = (__le32 *)(fw->data + start);
2818 pa->size = size;
2819 } else {
1c361efb
FR		 2820 if (fw->size % FW_OPCODE_SIZE)
2821 goto out;
2822
2823 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2824
2825 pa->code = (__le32 *)fw->data;
2826 pa->size = fw->size / FW_OPCODE_SIZE;
2827 }
2828 version[RTL_VER_SIZE - 1] = 0;
2829
2830 rc = true;
2831out:
2832 return rc;
2833}
2834
fd112f2e
FR		 2835static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2836 struct rtl_fw_phy_action *pa)
1c361efb 2837{
fd112f2e 2838 bool rc = false;
1c361efb 2839 size_t index;
bca03d5f 2840
1c361efb
FR		 2841 for (index = 0; index < pa->size; index++) {
2842 u32 action = le32_to_cpu(pa->code[index]);
42b82dc1 2843 u32 regno = (action & 0x0fff0000) >> 16;
bca03d5f 2844
42b82dc1 2845 switch(action & 0xf0000000) {
2846 case PHY_READ:
2847 case PHY_DATA_OR:
2848 case PHY_DATA_AND:
eee3786f 2849 case PHY_MDIO_CHG:
42b82dc1 2850 case PHY_CLEAR_READCOUNT:
2851 case PHY_WRITE:
2852 case PHY_WRITE_PREVIOUS:
2853 case PHY_DELAY_MS:
2854 break;
2855
2856 case PHY_BJMPN:
2857 if (regno > index) {
fd112f2e 2858 netif_err(tp, ifup, tp->dev,
cecb5fd7 2859 "Out of range of firmware\n");
fd112f2e 2860 goto out;
42b82dc1 2861 }
2862 break;
2863 case PHY_READCOUNT_EQ_SKIP:
1c361efb 2864 if (index + 2 >= pa->size) {
fd112f2e 2865 netif_err(tp, ifup, tp->dev,
cecb5fd7 2866 "Out of range of firmware\n");
fd112f2e 2867 goto out;
42b82dc1 2868 }
2869 break;
2870 case PHY_COMP_EQ_SKIPN:
2871 case PHY_COMP_NEQ_SKIPN:
2872 case PHY_SKIPN:
1c361efb 2873 if (index + 1 + regno >= pa->size) {
fd112f2e 2874 netif_err(tp, ifup, tp->dev,
cecb5fd7 2875 "Out of range of firmware\n");
fd112f2e 2876 goto out;
42b82dc1 2877 }
bca03d5f 2878 break;
2879
42b82dc1 2880 default:
fd112f2e 2881 netif_err(tp, ifup, tp->dev,
42b82dc1 2882 "Invalid action 0x%08x\n", action);
fd112f2e 2883 goto out;
bca03d5f 2884 }
2885 }
fd112f2e
FR		 2886 rc = true;
2887out:
2888 return rc;
2889}
bca03d5f 2890
fd112f2e
FR		 2891static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2892{
2893 struct net_device *dev = tp->dev;
2894 int rc = -EINVAL;
2895
2896 if (!rtl_fw_format_ok(tp, rtl_fw)) {
5c2d2b14 2897 netif_err(tp, ifup, dev, "invalid firmware\n");
fd112f2e
FR		 2898 goto out;
2899 }
2900
2901 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2902 rc = 0;
2903out:
2904 return rc;
2905}
2906
2907static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2908{
2909 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
eee3786f 2910 struct mdio_ops org, *ops = &tp->mdio_ops;
fd112f2e
FR		 2911 u32 predata, count;
2912 size_t index;
2913
2914 predata = count = 0;
eee3786f 2915 org.write = ops->write;
2916 org.read = ops->read;
42b82dc1 2917
1c361efb
FR		 2918 for (index = 0; index < pa->size; ) {
2919 u32 action = le32_to_cpu(pa->code[index]);
bca03d5f 2920 u32 data = action & 0x0000ffff;
42b82dc1 2921 u32 regno = (action & 0x0fff0000) >> 16;
2922
2923 if (!action)
2924 break;
bca03d5f 2925
2926 switch(action & 0xf0000000) {
42b82dc1 2927 case PHY_READ:
2928 predata = rtl_readphy(tp, regno);
2929 count++;
2930 index++;
2931 break;
2932 case PHY_DATA_OR:
2933 predata |= data;
2934 index++;
2935 break;
2936 case PHY_DATA_AND:
2937 predata &= data;
2938 index++;
2939 break;
2940 case PHY_BJMPN:
2941 index -= regno;
2942 break;
eee3786f 2943 case PHY_MDIO_CHG:
2944 if (data == 0) {
2945 ops->write = org.write;
2946 ops->read = org.read;
2947 } else if (data == 1) {
2948 ops->write = mac_mcu_write;
2949 ops->read = mac_mcu_read;
2950 }
2951
42b82dc1 2952 index++;
2953 break;
2954 case PHY_CLEAR_READCOUNT:
2955 count = 0;
2956 index++;
2957 break;
bca03d5f 2958 case PHY_WRITE:
42b82dc1 2959 rtl_writephy(tp, regno, data);
2960 index++;
2961 break;
2962 case PHY_READCOUNT_EQ_SKIP:
cecb5fd7 2963 index += (count == data) ? 2 : 1;
bca03d5f 2964 break;
42b82dc1 2965 case PHY_COMP_EQ_SKIPN:
2966 if (predata == data)
2967 index += regno;
2968 index++;
2969 break;
2970 case PHY_COMP_NEQ_SKIPN:
2971 if (predata != data)
2972 index += regno;
2973 index++;
2974 break;
2975 case PHY_WRITE_PREVIOUS:
2976 rtl_writephy(tp, regno, predata);
2977 index++;
2978 break;
2979 case PHY_SKIPN:
2980 index += regno + 1;
2981 break;
2982 case PHY_DELAY_MS:
2983 mdelay(data);
2984 index++;
2985 break;
2986
bca03d5f 2987 default:
2988 BUG();
2989 }
2990 }
eee3786f 2991
2992 ops->write = org.write;
2993 ops->read = org.read;
bca03d5f 2994}
2995
f1e02ed1 2996static void rtl_release_firmware(struct rtl8169_private *tp)
2997{
b6ffd97f
FR		 2998 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2999 release_firmware(tp->rtl_fw->fw);
3000 kfree(tp->rtl_fw);
3001 }
3002 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
f1e02ed1 3003}
3004
953a12cc 3005static void rtl_apply_firmware(struct rtl8169_private *tp)
f1e02ed1 3006{
b6ffd97f 3007 struct rtl_fw *rtl_fw = tp->rtl_fw;
f1e02ed1 3008
3009 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
eef63cc1 3010 if (!IS_ERR_OR_NULL(rtl_fw))
b6ffd97f 3011 rtl_phy_write_fw(tp, rtl_fw);
953a12cc
FR		 3012}
3013
3014static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
3015{
3016 if (rtl_readphy(tp, reg) != val)
3017 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
3018 else
3019 rtl_apply_firmware(tp);
f1e02ed1 3020}
3021
4da19633 3022static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1da177e4 3023{
350f7596 3024 static const struct phy_reg phy_reg_init[] = {
0b9b571d 3025 { 0x1f, 0x0001 },
3026 { 0x06, 0x006e },
3027 { 0x08, 0x0708 },
3028 { 0x15, 0x4000 },
3029 { 0x18, 0x65c7 },
1da177e4 3030
0b9b571d 3031 { 0x1f, 0x0001 },
3032 { 0x03, 0x00a1 },
3033 { 0x02, 0x0008 },
3034 { 0x01, 0x0120 },
3035 { 0x00, 0x1000 },
3036 { 0x04, 0x0800 },
3037 { 0x04, 0x0000 },
1da177e4 3038
0b9b571d 3039 { 0x03, 0xff41 },
3040 { 0x02, 0xdf60 },
3041 { 0x01, 0x0140 },
3042 { 0x00, 0x0077 },
3043 { 0x04, 0x7800 },
3044 { 0x04, 0x7000 },
3045
3046 { 0x03, 0x802f },
3047 { 0x02, 0x4f02 },
3048 { 0x01, 0x0409 },
3049 { 0x00, 0xf0f9 },
3050 { 0x04, 0x9800 },
3051 { 0x04, 0x9000 },
3052
3053 { 0x03, 0xdf01 },
3054 { 0x02, 0xdf20 },
3055 { 0x01, 0xff95 },
3056 { 0x00, 0xba00 },
3057 { 0x04, 0xa800 },
3058 { 0x04, 0xa000 },
3059
3060 { 0x03, 0xff41 },
3061 { 0x02, 0xdf20 },
3062 { 0x01, 0x0140 },
3063 { 0x00, 0x00bb },
3064 { 0x04, 0xb800 },
3065 { 0x04, 0xb000 },
3066
3067 { 0x03, 0xdf41 },
3068 { 0x02, 0xdc60 },
3069 { 0x01, 0x6340 },
3070 { 0x00, 0x007d },
3071 { 0x04, 0xd800 },
3072 { 0x04, 0xd000 },
3073
3074 { 0x03, 0xdf01 },
3075 { 0x02, 0xdf20 },
3076 { 0x01, 0x100a },
3077 { 0x00, 0xa0ff },
3078 { 0x04, 0xf800 },
3079 { 0x04, 0xf000 },
3080
3081 { 0x1f, 0x0000 },
3082 { 0x0b, 0x0000 },
3083 { 0x00, 0x9200 }
3084 };
1da177e4 3085
4da19633 3086 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1da177e4
LT		 3087}
3088
4da19633 3089static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
5615d9f1 3090{
350f7596 3091 static const struct phy_reg phy_reg_init[] = {
a441d7b6
FR		 3092 { 0x1f, 0x0002 },
3093 { 0x01, 0x90d0 },
3094 { 0x1f, 0x0000 }
3095 };
3096
4da19633 3097 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 3098}
3099
4da19633 3100static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2e955856 3101{
3102 struct pci_dev *pdev = tp->pci_dev;
2e955856 3103
ccbae55e
SS		 3104 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
3105 (pdev->subsystem_device != 0xe000))
2e955856 3106 return;
3107
4da19633 3108 rtl_writephy(tp, 0x1f, 0x0001);
3109 rtl_writephy(tp, 0x10, 0xf01b);
3110 rtl_writephy(tp, 0x1f, 0x0000);
2e955856 3111}
3112
4da19633 3113static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2e955856 3114{
350f7596 3115 static const struct phy_reg phy_reg_init[] = {
2e955856 3116 { 0x1f, 0x0001 },
3117 { 0x04, 0x0000 },
3118 { 0x03, 0x00a1 },
3119 { 0x02, 0x0008 },
3120 { 0x01, 0x0120 },
3121 { 0x00, 0x1000 },
3122 { 0x04, 0x0800 },
3123 { 0x04, 0x9000 },
3124 { 0x03, 0x802f },
3125 { 0x02, 0x4f02 },
3126 { 0x01, 0x0409 },
3127 { 0x00, 0xf099 },
3128 { 0x04, 0x9800 },
3129 { 0x04, 0xa000 },
3130 { 0x03, 0xdf01 },
3131 { 0x02, 0xdf20 },
3132 { 0x01, 0xff95 },
3133 { 0x00, 0xba00 },
3134 { 0x04, 0xa800 },
3135 { 0x04, 0xf000 },
3136 { 0x03, 0xdf01 },
3137 { 0x02, 0xdf20 },
3138 { 0x01, 0x101a },
3139 { 0x00, 0xa0ff },
3140 { 0x04, 0xf800 },
3141 { 0x04, 0x0000 },
3142 { 0x1f, 0x0000 },
3143
3144 { 0x1f, 0x0001 },
3145 { 0x10, 0xf41b },
3146 { 0x14, 0xfb54 },
3147 { 0x18, 0xf5c7 },
3148 { 0x1f, 0x0000 },
3149
3150 { 0x1f, 0x0001 },
3151 { 0x17, 0x0cc0 },
3152 { 0x1f, 0x0000 }
3153 };
3154
4da19633 3155 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2e955856 3156
4da19633 3157 rtl8169scd_hw_phy_config_quirk(tp);
2e955856 3158}
3159
4da19633 3160static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
8c7006aa 3161{
350f7596 3162 static const struct phy_reg phy_reg_init[] = {
8c7006aa 3163 { 0x1f, 0x0001 },
3164 { 0x04, 0x0000 },
3165 { 0x03, 0x00a1 },
3166 { 0x02, 0x0008 },
3167 { 0x01, 0x0120 },
3168 { 0x00, 0x1000 },
3169 { 0x04, 0x0800 },
3170 { 0x04, 0x9000 },
3171 { 0x03, 0x802f },
3172 { 0x02, 0x4f02 },
3173 { 0x01, 0x0409 },
3174 { 0x00, 0xf099 },
3175 { 0x04, 0x9800 },
3176 { 0x04, 0xa000 },
3177 { 0x03, 0xdf01 },
3178 { 0x02, 0xdf20 },
3179 { 0x01, 0xff95 },
3180 { 0x00, 0xba00 },
3181 { 0x04, 0xa800 },
3182 { 0x04, 0xf000 },
3183 { 0x03, 0xdf01 },
3184 { 0x02, 0xdf20 },
3185 { 0x01, 0x101a },
3186 { 0x00, 0xa0ff },
3187 { 0x04, 0xf800 },
3188 { 0x04, 0x0000 },
3189 { 0x1f, 0x0000 },
3190
3191 { 0x1f, 0x0001 },
3192 { 0x0b, 0x8480 },
3193 { 0x1f, 0x0000 },
3194
3195 { 0x1f, 0x0001 },
3196 { 0x18, 0x67c7 },
3197 { 0x04, 0x2000 },
3198 { 0x03, 0x002f },
3199 { 0x02, 0x4360 },
3200 { 0x01, 0x0109 },
3201 { 0x00, 0x3022 },
3202 { 0x04, 0x2800 },
3203 { 0x1f, 0x0000 },
3204
3205 { 0x1f, 0x0001 },
3206 { 0x17, 0x0cc0 },
3207 { 0x1f, 0x0000 }
3208 };
3209
4da19633 3210 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
8c7006aa 3211}
3212
4da19633 3213static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
236b8082 3214{
350f7596 3215 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 3216 { 0x10, 0xf41b },
3217 { 0x1f, 0x0000 }
3218 };
3219
4da19633 3220 rtl_writephy(tp, 0x1f, 0x0001);
3221 rtl_patchphy(tp, 0x16, 1 << 0);
236b8082 3222
4da19633 3223 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 3224}
3225
4da19633 3226static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
236b8082 3227{
350f7596 3228 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 3229 { 0x1f, 0x0001 },
3230 { 0x10, 0xf41b },
3231 { 0x1f, 0x0000 }
3232 };
3233
4da19633 3234 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 3235}
3236
4da19633 3237static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 3238{
350f7596 3239 static const struct phy_reg phy_reg_init[] = {
867763c1
FR		 3240 { 0x1f, 0x0000 },
3241 { 0x1d, 0x0f00 },
3242 { 0x1f, 0x0002 },
3243 { 0x0c, 0x1ec8 },
3244 { 0x1f, 0x0000 }
3245 };
3246
4da19633 3247 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
867763c1
FR		 3248}
3249
4da19633 3250static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
ef3386f0 3251{
350f7596 3252 static const struct phy_reg phy_reg_init[] = {
ef3386f0
FR		 3253 { 0x1f, 0x0001 },
3254 { 0x1d, 0x3d98 },
3255 { 0x1f, 0x0000 }
3256 };
3257
4da19633 3258 rtl_writephy(tp, 0x1f, 0x0000);
3259 rtl_patchphy(tp, 0x14, 1 << 5);
3260 rtl_patchphy(tp, 0x0d, 1 << 5);
ef3386f0 3261
4da19633 3262 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
ef3386f0
FR		 3263}
3264
4da19633 3265static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 3266{
350f7596 3267 static const struct phy_reg phy_reg_init[] = {
a3f80671
FR		 3268 { 0x1f, 0x0001 },
3269 { 0x12, 0x2300 },
867763c1
FR		 3270 { 0x1f, 0x0002 },
3271 { 0x00, 0x88d4 },
3272 { 0x01, 0x82b1 },
3273 { 0x03, 0x7002 },
3274 { 0x08, 0x9e30 },
3275 { 0x09, 0x01f0 },
3276 { 0x0a, 0x5500 },
3277 { 0x0c, 0x00c8 },
3278 { 0x1f, 0x0003 },
3279 { 0x12, 0xc096 },
3280 { 0x16, 0x000a },
f50d4275
FR		 3281 { 0x1f, 0x0000 },
3282 { 0x1f, 0x0000 },
3283 { 0x09, 0x2000 },
3284 { 0x09, 0x0000 }
867763c1
FR		 3285 };
3286
4da19633 3287 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 3288
4da19633 3289 rtl_patchphy(tp, 0x14, 1 << 5);
3290 rtl_patchphy(tp, 0x0d, 1 << 5);
3291 rtl_writephy(tp, 0x1f, 0x0000);
867763c1
FR		 3292}
3293
4da19633 3294static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
7da97ec9 3295{
350f7596 3296 static const struct phy_reg phy_reg_init[] = {
f50d4275 3297 { 0x1f, 0x0001 },
7da97ec9 3298 { 0x12, 0x2300 },
f50d4275
FR		 3299 { 0x03, 0x802f },
3300 { 0x02, 0x4f02 },
3301 { 0x01, 0x0409 },
3302 { 0x00, 0xf099 },
3303 { 0x04, 0x9800 },
3304 { 0x04, 0x9000 },
3305 { 0x1d, 0x3d98 },
7da97ec9
FR		 3306 { 0x1f, 0x0002 },
3307 { 0x0c, 0x7eb8 },
f50d4275
FR		 3308 { 0x06, 0x0761 },
3309 { 0x1f, 0x0003 },
3310 { 0x16, 0x0f0a },
7da97ec9
FR		 3311 { 0x1f, 0x0000 }
3312 };
3313
4da19633 3314 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 3315
4da19633 3316 rtl_patchphy(tp, 0x16, 1 << 0);
3317 rtl_patchphy(tp, 0x14, 1 << 5);
3318 rtl_patchphy(tp, 0x0d, 1 << 5);
3319 rtl_writephy(tp, 0x1f, 0x0000);
7da97ec9
FR		 3320}
3321
4da19633 3322static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
197ff761 3323{
350f7596 3324 static const struct phy_reg phy_reg_init[] = {
197ff761
FR		 3325 { 0x1f, 0x0001 },
3326 { 0x12, 0x2300 },
3327 { 0x1d, 0x3d98 },
3328 { 0x1f, 0x0002 },
3329 { 0x0c, 0x7eb8 },
3330 { 0x06, 0x5461 },
3331 { 0x1f, 0x0003 },
3332 { 0x16, 0x0f0a },
3333 { 0x1f, 0x0000 }
3334 };
3335
4da19633 3336 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
197ff761 3337
4da19633 3338 rtl_patchphy(tp, 0x16, 1 << 0);
3339 rtl_patchphy(tp, 0x14, 1 << 5);
3340 rtl_patchphy(tp, 0x0d, 1 << 5);
3341 rtl_writephy(tp, 0x1f, 0x0000);
197ff761
FR		 3342}
3343
4da19633 3344static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
6fb07058 3345{
4da19633 3346 rtl8168c_3_hw_phy_config(tp);
6fb07058
FR		 3347}
3348
bca03d5f 3349static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
5b538df9 3350{
350f7596 3351 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 3352 /* Channel Estimation */
5b538df9 3353 { 0x1f, 0x0001 },
daf9df6d 3354 { 0x06, 0x4064 },
3355 { 0x07, 0x2863 },
3356 { 0x08, 0x059c },
3357 { 0x09, 0x26b4 },
3358 { 0x0a, 0x6a19 },
3359 { 0x0b, 0xdcc8 },
3360 { 0x10, 0xf06d },
3361 { 0x14, 0x7f68 },
3362 { 0x18, 0x7fd9 },
3363 { 0x1c, 0xf0ff },
3364 { 0x1d, 0x3d9c },
5b538df9 3365 { 0x1f, 0x0003 },
daf9df6d 3366 { 0x12, 0xf49f },
3367 { 0x13, 0x070b },
3368 { 0x1a, 0x05ad },
bca03d5f 3369 { 0x14, 0x94c0 },
3370
3371 /*
3372 * Tx Error Issue
cecb5fd7 3373 * Enhance line driver power
bca03d5f 3374 */
5b538df9 3375 { 0x1f, 0x0002 },
daf9df6d 3376 { 0x06, 0x5561 },
3377 { 0x1f, 0x0005 },
3378 { 0x05, 0x8332 },
bca03d5f 3379 { 0x06, 0x5561 },
3380
3381 /*
3382 * Can not link to 1Gbps with bad cable
3383 * Decrease SNR threshold form 21.07dB to 19.04dB
3384 */
3385 { 0x1f, 0x0001 },
3386 { 0x17, 0x0cc0 },
daf9df6d 3387
5b538df9 3388 { 0x1f, 0x0000 },
bca03d5f 3389 { 0x0d, 0xf880 }
daf9df6d 3390 };
3391
4da19633 3392 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
daf9df6d 3393
bca03d5f 3394 /*
3395 * Rx Error Issue
3396 * Fine Tune Switching regulator parameter
3397 */
4da19633 3398 rtl_writephy(tp, 0x1f, 0x0002);
76564428
CHL		 3399 rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
3400 rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
daf9df6d 3401
fdf6fc06 3402 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
350f7596 3403 static const struct phy_reg phy_reg_init[] = {
daf9df6d 3404 { 0x1f, 0x0002 },
3405 { 0x05, 0x669a },
3406 { 0x1f, 0x0005 },
3407 { 0x05, 0x8330 },
3408 { 0x06, 0x669a },
3409 { 0x1f, 0x0002 }
3410 };
3411 int val;
3412
4da19633 3413 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 3414
4da19633 3415 val = rtl_readphy(tp, 0x0d);
daf9df6d 3416
3417 if ((val & 0x00ff) != 0x006c) {
350f7596 3418 static const u32 set[] = {
daf9df6d 3419 0x0065, 0x0066, 0x0067, 0x0068,
3420 0x0069, 0x006a, 0x006b, 0x006c
3421 };
3422 int i;
3423
4da19633 3424 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 3425
3426 val &= 0xff00;
3427 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 3428 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 3429 }
3430 } else {
350f7596 3431 static const struct phy_reg phy_reg_init[] = {
daf9df6d 3432 { 0x1f, 0x0002 },
3433 { 0x05, 0x6662 },
3434 { 0x1f, 0x0005 },
3435 { 0x05, 0x8330 },
3436 { 0x06, 0x6662 }
3437 };
3438
4da19633 3439 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 3440 }
3441
bca03d5f 3442 /* RSET couple improve */
4da19633 3443 rtl_writephy(tp, 0x1f, 0x0002);
3444 rtl_patchphy(tp, 0x0d, 0x0300);
3445 rtl_patchphy(tp, 0x0f, 0x0010);
daf9df6d 3446
bca03d5f 3447 /* Fine tune PLL performance */
4da19633 3448 rtl_writephy(tp, 0x1f, 0x0002);
76564428
CHL		 3449 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3450 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 3451
4da19633 3452 rtl_writephy(tp, 0x1f, 0x0005);
3453 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 3454
3455 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
bca03d5f 3456
4da19633 3457 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 3458}
3459
bca03d5f 3460static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 3461{
350f7596 3462 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 3463 /* Channel Estimation */
daf9df6d 3464 { 0x1f, 0x0001 },
3465 { 0x06, 0x4064 },
3466 { 0x07, 0x2863 },
3467 { 0x08, 0x059c },
3468 { 0x09, 0x26b4 },
3469 { 0x0a, 0x6a19 },
3470 { 0x0b, 0xdcc8 },
3471 { 0x10, 0xf06d },
3472 { 0x14, 0x7f68 },
3473 { 0x18, 0x7fd9 },
3474 { 0x1c, 0xf0ff },
3475 { 0x1d, 0x3d9c },
3476 { 0x1f, 0x0003 },
3477 { 0x12, 0xf49f },
3478 { 0x13, 0x070b },
3479 { 0x1a, 0x05ad },
3480 { 0x14, 0x94c0 },
3481
bca03d5f 3482 /*
3483 * Tx Error Issue
cecb5fd7 3484 * Enhance line driver power
bca03d5f 3485 */
daf9df6d 3486 { 0x1f, 0x0002 },
3487 { 0x06, 0x5561 },
3488 { 0x1f, 0x0005 },
3489 { 0x05, 0x8332 },
bca03d5f 3490 { 0x06, 0x5561 },
3491
3492 /*
3493 * Can not link to 1Gbps with bad cable
3494 * Decrease SNR threshold form 21.07dB to 19.04dB
3495 */
3496 { 0x1f, 0x0001 },
3497 { 0x17, 0x0cc0 },
daf9df6d 3498
3499 { 0x1f, 0x0000 },
bca03d5f 3500 { 0x0d, 0xf880 }
5b538df9
FR		 3501 };
3502
4da19633 3503 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
5b538df9 3504
fdf6fc06 3505 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
350f7596 3506 static const struct phy_reg phy_reg_init[] = {
daf9df6d 3507 { 0x1f, 0x0002 },
3508 { 0x05, 0x669a },
5b538df9 3509 { 0x1f, 0x0005 },
daf9df6d 3510 { 0x05, 0x8330 },
3511 { 0x06, 0x669a },
3512
3513 { 0x1f, 0x0002 }
3514 };
3515 int val;
3516
4da19633 3517 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 3518
4da19633 3519 val = rtl_readphy(tp, 0x0d);
daf9df6d 3520 if ((val & 0x00ff) != 0x006c) {
b6bc7650 3521 static const u32 set[] = {
daf9df6d 3522 0x0065, 0x0066, 0x0067, 0x0068,
3523 0x0069, 0x006a, 0x006b, 0x006c
3524 };
3525 int i;
3526
4da19633 3527 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 3528
3529 val &= 0xff00;
3530 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 3531 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 3532 }
3533 } else {
350f7596 3534 static const struct phy_reg phy_reg_init[] = {
daf9df6d 3535 { 0x1f, 0x0002 },
3536 { 0x05, 0x2642 },
5b538df9 3537 { 0x1f, 0x0005 },
daf9df6d 3538 { 0x05, 0x8330 },
3539 { 0x06, 0x2642 }
5b538df9
FR		 3540 };
3541
4da19633 3542 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 3543 }
3544
bca03d5f 3545 /* Fine tune PLL performance */
4da19633 3546 rtl_writephy(tp, 0x1f, 0x0002);
76564428
CHL		 3547 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3548 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 3549
bca03d5f 3550 /* Switching regulator Slew rate */
4da19633 3551 rtl_writephy(tp, 0x1f, 0x0002);
3552 rtl_patchphy(tp, 0x0f, 0x0017);
daf9df6d 3553
4da19633 3554 rtl_writephy(tp, 0x1f, 0x0005);
3555 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 3556
3557 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
bca03d5f 3558
4da19633 3559 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 3560}
3561
4da19633 3562static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 3563{
350f7596 3564 static const struct phy_reg phy_reg_init[] = {
daf9df6d 3565 { 0x1f, 0x0002 },
3566 { 0x10, 0x0008 },
3567 { 0x0d, 0x006c },
3568
3569 { 0x1f, 0x0000 },
3570 { 0x0d, 0xf880 },
3571
3572 { 0x1f, 0x0001 },
3573 { 0x17, 0x0cc0 },
3574
3575 { 0x1f, 0x0001 },
3576 { 0x0b, 0xa4d8 },
3577 { 0x09, 0x281c },
3578 { 0x07, 0x2883 },
3579 { 0x0a, 0x6b35 },
3580 { 0x1d, 0x3da4 },
3581 { 0x1c, 0xeffd },
3582 { 0x14, 0x7f52 },
3583 { 0x18, 0x7fc6 },
3584 { 0x08, 0x0601 },
3585 { 0x06, 0x4063 },
3586 { 0x10, 0xf074 },
3587 { 0x1f, 0x0003 },
3588 { 0x13, 0x0789 },
3589 { 0x12, 0xf4bd },
3590 { 0x1a, 0x04fd },
3591 { 0x14, 0x84b0 },
3592 { 0x1f, 0x0000 },
3593 { 0x00, 0x9200 },
3594
3595 { 0x1f, 0x0005 },
3596 { 0x01, 0x0340 },
3597 { 0x1f, 0x0001 },
3598 { 0x04, 0x4000 },
3599 { 0x03, 0x1d21 },
3600 { 0x02, 0x0c32 },
3601 { 0x01, 0x0200 },
3602 { 0x00, 0x5554 },
3603 { 0x04, 0x4800 },
3604 { 0x04, 0x4000 },
3605 { 0x04, 0xf000 },
3606 { 0x03, 0xdf01 },
3607 { 0x02, 0xdf20 },
3608 { 0x01, 0x101a },
3609 { 0x00, 0xa0ff },
3610 { 0x04, 0xf800 },
3611 { 0x04, 0xf000 },
3612 { 0x1f, 0x0000 },
3613
3614 { 0x1f, 0x0007 },
3615 { 0x1e, 0x0023 },
3616 { 0x16, 0x0000 },
3617 { 0x1f, 0x0000 }
3618 };
3619
4da19633 3620 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 3621}
3622
e6de30d6 3623static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3624{
3625 static const struct phy_reg phy_reg_init[] = {
3626 { 0x1f, 0x0001 },
3627 { 0x17, 0x0cc0 },
3628
3629 { 0x1f, 0x0007 },
3630 { 0x1e, 0x002d },
3631 { 0x18, 0x0040 },
3632 { 0x1f, 0x0000 }
3633 };
3634
3635 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3636 rtl_patchphy(tp, 0x0d, 1 << 5);
3637}
3638
70090424 3639static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
01dc7fec 3640{
3641 static const struct phy_reg phy_reg_init[] = {
3642 /* Enable Delay cap */
3643 { 0x1f, 0x0005 },
3644 { 0x05, 0x8b80 },
3645 { 0x06, 0xc896 },
3646 { 0x1f, 0x0000 },
3647
3648 /* Channel estimation fine tune */
3649 { 0x1f, 0x0001 },
3650 { 0x0b, 0x6c20 },
3651 { 0x07, 0x2872 },
3652 { 0x1c, 0xefff },
3653 { 0x1f, 0x0003 },
3654 { 0x14, 0x6420 },
3655 { 0x1f, 0x0000 },
3656
3657 /* Update PFM & 10M TX idle timer */
3658 { 0x1f, 0x0007 },
3659 { 0x1e, 0x002f },
3660 { 0x15, 0x1919 },
3661 { 0x1f, 0x0000 },
3662
3663 { 0x1f, 0x0007 },
3664 { 0x1e, 0x00ac },
3665 { 0x18, 0x0006 },
3666 { 0x1f, 0x0000 }
3667 };
3668
15ecd039
FR		 3669 rtl_apply_firmware(tp);
3670
01dc7fec 3671 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3672
3673 /* DCO enable for 10M IDLE Power */
3674 rtl_writephy(tp, 0x1f, 0x0007);
3675 rtl_writephy(tp, 0x1e, 0x0023);
76564428 3676 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
01dc7fec 3677 rtl_writephy(tp, 0x1f, 0x0000);
3678
3679 /* For impedance matching */
3680 rtl_writephy(tp, 0x1f, 0x0002);
76564428 3681 rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
cecb5fd7 3682 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3683
3684 /* PHY auto speed down */
3685 rtl_writephy(tp, 0x1f, 0x0007);
3686 rtl_writephy(tp, 0x1e, 0x002d);
76564428 3687 rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
01dc7fec 3688 rtl_writephy(tp, 0x1f, 0x0000);
76564428 3689 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
01dc7fec 3690
3691 rtl_writephy(tp, 0x1f, 0x0005);
3692 rtl_writephy(tp, 0x05, 0x8b86);
76564428 3693 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
01dc7fec 3694 rtl_writephy(tp, 0x1f, 0x0000);
3695
3696 rtl_writephy(tp, 0x1f, 0x0005);
3697 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3698 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
01dc7fec 3699 rtl_writephy(tp, 0x1f, 0x0007);
3700 rtl_writephy(tp, 0x1e, 0x0020);
76564428 3701 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
01dc7fec 3702 rtl_writephy(tp, 0x1f, 0x0006);
3703 rtl_writephy(tp, 0x00, 0x5a00);
3704 rtl_writephy(tp, 0x1f, 0x0000);
3705 rtl_writephy(tp, 0x0d, 0x0007);
3706 rtl_writephy(tp, 0x0e, 0x003c);
3707 rtl_writephy(tp, 0x0d, 0x4007);
3708 rtl_writephy(tp, 0x0e, 0x0000);
3709 rtl_writephy(tp, 0x0d, 0x0000);
3710}
3711
9ecb9aab 3712static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3713{
3714 const u16 w[] = {
3715 addr[0] | (addr[1] << 8),
3716 addr[2] | (addr[3] << 8),
3717 addr[4] | (addr[5] << 8)
3718 };
3719 const struct exgmac_reg e[] = {
3720 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3721 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3722 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3723 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3724 };
3725
3726 rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3727}
3728
70090424
HW		 3729static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3730{
3731 static const struct phy_reg phy_reg_init[] = {
3732 /* Enable Delay cap */
3733 { 0x1f, 0x0004 },
3734 { 0x1f, 0x0007 },
3735 { 0x1e, 0x00ac },
3736 { 0x18, 0x0006 },
3737 { 0x1f, 0x0002 },
3738 { 0x1f, 0x0000 },
3739 { 0x1f, 0x0000 },
3740
3741 /* Channel estimation fine tune */
3742 { 0x1f, 0x0003 },
3743 { 0x09, 0xa20f },
3744 { 0x1f, 0x0000 },
3745 { 0x1f, 0x0000 },
3746
3747 /* Green Setting */
3748 { 0x1f, 0x0005 },
3749 { 0x05, 0x8b5b },
3750 { 0x06, 0x9222 },
3751 { 0x05, 0x8b6d },
3752 { 0x06, 0x8000 },
3753 { 0x05, 0x8b76 },
3754 { 0x06, 0x8000 },
3755 { 0x1f, 0x0000 }
3756 };
3757
3758 rtl_apply_firmware(tp);
3759
3760 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3761
3762 /* For 4-corner performance improve */
3763 rtl_writephy(tp, 0x1f, 0x0005);
3764 rtl_writephy(tp, 0x05, 0x8b80);
76564428 3765 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
70090424
HW		 3766 rtl_writephy(tp, 0x1f, 0x0000);
3767
3768 /* PHY auto speed down */
3769 rtl_writephy(tp, 0x1f, 0x0004);
3770 rtl_writephy(tp, 0x1f, 0x0007);
3771 rtl_writephy(tp, 0x1e, 0x002d);
76564428 3772 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
70090424
HW		 3773 rtl_writephy(tp, 0x1f, 0x0002);
3774 rtl_writephy(tp, 0x1f, 0x0000);
76564428 3775 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
70090424
HW		 3776
3777 /* improve 10M EEE waveform */
3778 rtl_writephy(tp, 0x1f, 0x0005);
3779 rtl_writephy(tp, 0x05, 0x8b86);
76564428 3780 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
70090424
HW		 3781 rtl_writephy(tp, 0x1f, 0x0000);
3782
3783 /* Improve 2-pair detection performance */
3784 rtl_writephy(tp, 0x1f, 0x0005);
3785 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3786 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
70090424
HW		 3787 rtl_writephy(tp, 0x1f, 0x0000);
3788
3789 /* EEE setting */
1814d6a8 3790 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0003, 0x0000, ERIAR_EXGMAC);
70090424
HW		 3791 rtl_writephy(tp, 0x1f, 0x0005);
3792 rtl_writephy(tp, 0x05, 0x8b85);
1814d6a8 3793 rtl_w0w1_phy(tp, 0x06, 0x2000, 0x0000);
70090424
HW		 3794 rtl_writephy(tp, 0x1f, 0x0004);
3795 rtl_writephy(tp, 0x1f, 0x0007);
3796 rtl_writephy(tp, 0x1e, 0x0020);
1814d6a8 3797 rtl_w0w1_phy(tp, 0x15, 0x0100, 0x0000);
70090424
HW		 3798 rtl_writephy(tp, 0x1f, 0x0002);
3799 rtl_writephy(tp, 0x1f, 0x0000);
3800 rtl_writephy(tp, 0x0d, 0x0007);
3801 rtl_writephy(tp, 0x0e, 0x003c);
3802 rtl_writephy(tp, 0x0d, 0x4007);
1814d6a8 3803 rtl_writephy(tp, 0x0e, 0x0006);
70090424
HW		 3804 rtl_writephy(tp, 0x0d, 0x0000);
3805
3806 /* Green feature */
3807 rtl_writephy(tp, 0x1f, 0x0003);
1814d6a8
HK		 3808 rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
3809 rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
70090424 3810 rtl_writephy(tp, 0x1f, 0x0000);
b399a394
HK		 3811 rtl_writephy(tp, 0x1f, 0x0005);
3812 rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000);
3813 rtl_writephy(tp, 0x1f, 0x0000);
3814 /* soft-reset phy */
3815 rtl_writephy(tp, MII_BMCR, BMCR_RESET | BMCR_ANENABLE | BMCR_ANRESTART);
e0c07557 3816
9ecb9aab 3817 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3818 rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
70090424
HW		 3819}
3820
5f886e08
HW		 3821static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3822{
3823 /* For 4-corner performance improve */
3824 rtl_writephy(tp, 0x1f, 0x0005);
3825 rtl_writephy(tp, 0x05, 0x8b80);
76564428 3826 rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
5f886e08
HW		 3827 rtl_writephy(tp, 0x1f, 0x0000);
3828
3829 /* PHY auto speed down */
3830 rtl_writephy(tp, 0x1f, 0x0007);
3831 rtl_writephy(tp, 0x1e, 0x002d);
76564428 3832 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
5f886e08 3833 rtl_writephy(tp, 0x1f, 0x0000);
76564428 3834 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
5f886e08
HW		 3835
3836 /* Improve 10M EEE waveform */
3837 rtl_writephy(tp, 0x1f, 0x0005);
3838 rtl_writephy(tp, 0x05, 0x8b86);
76564428 3839 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
5f886e08
HW		 3840 rtl_writephy(tp, 0x1f, 0x0000);
3841}
3842
c2218925
HW		 3843static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3844{
3845 static const struct phy_reg phy_reg_init[] = {
3846 /* Channel estimation fine tune */
3847 { 0x1f, 0x0003 },
3848 { 0x09, 0xa20f },
3849 { 0x1f, 0x0000 },
3850
3851 /* Modify green table for giga & fnet */
3852 { 0x1f, 0x0005 },
3853 { 0x05, 0x8b55 },
3854 { 0x06, 0x0000 },
3855 { 0x05, 0x8b5e },
3856 { 0x06, 0x0000 },
3857 { 0x05, 0x8b67 },
3858 { 0x06, 0x0000 },
3859 { 0x05, 0x8b70 },
3860 { 0x06, 0x0000 },
3861 { 0x1f, 0x0000 },
3862 { 0x1f, 0x0007 },
3863 { 0x1e, 0x0078 },
3864 { 0x17, 0x0000 },
3865 { 0x19, 0x00fb },
3866 { 0x1f, 0x0000 },
3867
3868 /* Modify green table for 10M */
3869 { 0x1f, 0x0005 },
3870 { 0x05, 0x8b79 },
3871 { 0x06, 0xaa00 },
3872 { 0x1f, 0x0000 },
3873
3874 /* Disable hiimpedance detection (RTCT) */
3875 { 0x1f, 0x0003 },
3876 { 0x01, 0x328a },
3877 { 0x1f, 0x0000 }
3878 };
3879
3880 rtl_apply_firmware(tp);
3881
3882 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3883
5f886e08 3884 rtl8168f_hw_phy_config(tp);
c2218925
HW		 3885
3886 /* Improve 2-pair detection performance */
3887 rtl_writephy(tp, 0x1f, 0x0005);
3888 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3889 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
c2218925
HW		 3890 rtl_writephy(tp, 0x1f, 0x0000);
3891}
3892
3893static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3894{
3895 rtl_apply_firmware(tp);
3896
5f886e08 3897 rtl8168f_hw_phy_config(tp);
c2218925
HW		 3898}
3899
b3d7b2f2
HW		 3900static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3901{
b3d7b2f2
HW		 3902 static const struct phy_reg phy_reg_init[] = {
3903 /* Channel estimation fine tune */
3904 { 0x1f, 0x0003 },
3905 { 0x09, 0xa20f },
3906 { 0x1f, 0x0000 },
3907
3908 /* Modify green table for giga & fnet */
3909 { 0x1f, 0x0005 },
3910 { 0x05, 0x8b55 },
3911 { 0x06, 0x0000 },
3912 { 0x05, 0x8b5e },
3913 { 0x06, 0x0000 },
3914 { 0x05, 0x8b67 },
3915 { 0x06, 0x0000 },
3916 { 0x05, 0x8b70 },
3917 { 0x06, 0x0000 },
3918 { 0x1f, 0x0000 },
3919 { 0x1f, 0x0007 },
3920 { 0x1e, 0x0078 },
3921 { 0x17, 0x0000 },
3922 { 0x19, 0x00aa },
3923 { 0x1f, 0x0000 },
3924
3925 /* Modify green table for 10M */
3926 { 0x1f, 0x0005 },
3927 { 0x05, 0x8b79 },
3928 { 0x06, 0xaa00 },
3929 { 0x1f, 0x0000 },
3930
3931 /* Disable hiimpedance detection (RTCT) */
3932 { 0x1f, 0x0003 },
3933 { 0x01, 0x328a },
3934 { 0x1f, 0x0000 }
3935 };
3936
3937
3938 rtl_apply_firmware(tp);
3939
3940 rtl8168f_hw_phy_config(tp);
3941
3942 /* Improve 2-pair detection performance */
3943 rtl_writephy(tp, 0x1f, 0x0005);
3944 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3945 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
b3d7b2f2
HW		 3946 rtl_writephy(tp, 0x1f, 0x0000);
3947
3948 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3949
3950 /* Modify green table for giga */
3951 rtl_writephy(tp, 0x1f, 0x0005);
3952 rtl_writephy(tp, 0x05, 0x8b54);
76564428 3953 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
b3d7b2f2 3954 rtl_writephy(tp, 0x05, 0x8b5d);
76564428 3955 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
b3d7b2f2 3956 rtl_writephy(tp, 0x05, 0x8a7c);
76564428 3957 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2 3958 rtl_writephy(tp, 0x05, 0x8a7f);
76564428 3959 rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
b3d7b2f2 3960 rtl_writephy(tp, 0x05, 0x8a82);
76564428 3961 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2 3962 rtl_writephy(tp, 0x05, 0x8a85);
76564428 3963 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2 3964 rtl_writephy(tp, 0x05, 0x8a88);
76564428 3965 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2
HW		 3966 rtl_writephy(tp, 0x1f, 0x0000);
3967
3968 /* uc same-seed solution */
3969 rtl_writephy(tp, 0x1f, 0x0005);
3970 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3971 rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
b3d7b2f2
HW		 3972 rtl_writephy(tp, 0x1f, 0x0000);
3973
3974 /* eee setting */
706123d0 3975 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
b3d7b2f2
HW		 3976 rtl_writephy(tp, 0x1f, 0x0005);
3977 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3978 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
b3d7b2f2
HW		 3979 rtl_writephy(tp, 0x1f, 0x0004);
3980 rtl_writephy(tp, 0x1f, 0x0007);
3981 rtl_writephy(tp, 0x1e, 0x0020);
76564428 3982 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
b3d7b2f2
HW		 3983 rtl_writephy(tp, 0x1f, 0x0000);
3984 rtl_writephy(tp, 0x0d, 0x0007);
3985 rtl_writephy(tp, 0x0e, 0x003c);
3986 rtl_writephy(tp, 0x0d, 0x4007);
3987 rtl_writephy(tp, 0x0e, 0x0000);
3988 rtl_writephy(tp, 0x0d, 0x0000);
3989
3990 /* Green feature */
3991 rtl_writephy(tp, 0x1f, 0x0003);
76564428
CHL		 3992 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3993 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
b3d7b2f2
HW		 3994 rtl_writephy(tp, 0x1f, 0x0000);
3995}
3996
c558386b
HW		 3997static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3998{
c558386b
HW		 3999 rtl_apply_firmware(tp);
4000
41f44d13 4001 rtl_writephy(tp, 0x1f, 0x0a46);
4002 if (rtl_readphy(tp, 0x10) & 0x0100) {
4003 rtl_writephy(tp, 0x1f, 0x0bcc);
76564428 4004 rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
41f44d13 4005 } else {
4006 rtl_writephy(tp, 0x1f, 0x0bcc);
76564428 4007 rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
41f44d13 4008 }
c558386b 4009
41f44d13 4010 rtl_writephy(tp, 0x1f, 0x0a46);
4011 if (rtl_readphy(tp, 0x13) & 0x0100) {
4012 rtl_writephy(tp, 0x1f, 0x0c41);
76564428 4013 rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
41f44d13 4014 } else {
fe7524c0 4015 rtl_writephy(tp, 0x1f, 0x0c41);
76564428 4016 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
41f44d13 4017 }
c558386b 4018
41f44d13 4019 /* Enable PHY auto speed down */
4020 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 4021 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
c558386b 4022
fe7524c0 4023 rtl_writephy(tp, 0x1f, 0x0bcc);
76564428 4024 rtl_w0w1_phy(tp, 0x14, 0x0100, 0x0000);
fe7524c0 4025 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 4026 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
fe7524c0 4027 rtl_writephy(tp, 0x1f, 0x0a43);
4028 rtl_writephy(tp, 0x13, 0x8084);
76564428
CHL		 4029 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
4030 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
fe7524c0 4031
41f44d13 4032 /* EEE auto-fallback function */
4033 rtl_writephy(tp, 0x1f, 0x0a4b);
76564428 4034 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
c558386b 4035
41f44d13 4036 /* Enable UC LPF tune function */
4037 rtl_writephy(tp, 0x1f, 0x0a43);
4038 rtl_writephy(tp, 0x13, 0x8012);
76564428 4039 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
41f44d13 4040
4041 rtl_writephy(tp, 0x1f, 0x0c42);
76564428 4042 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
41f44d13 4043
fe7524c0 4044 /* Improve SWR Efficiency */
4045 rtl_writephy(tp, 0x1f, 0x0bcd);
4046 rtl_writephy(tp, 0x14, 0x5065);
4047 rtl_writephy(tp, 0x14, 0xd065);
4048 rtl_writephy(tp, 0x1f, 0x0bc8);
4049 rtl_writephy(tp, 0x11, 0x5655);
4050 rtl_writephy(tp, 0x1f, 0x0bcd);
4051 rtl_writephy(tp, 0x14, 0x1065);
4052 rtl_writephy(tp, 0x14, 0x9065);
4053 rtl_writephy(tp, 0x14, 0x1065);
4054
1bac1072
DC		 4055 /* Check ALDPS bit, disable it if enabled */
4056 rtl_writephy(tp, 0x1f, 0x0a43);
4057 if (rtl_readphy(tp, 0x10) & 0x0004)
76564428 4058 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
1bac1072 4059
41f44d13 4060 rtl_writephy(tp, 0x1f, 0x0000);
c558386b
HW		 4061}
4062
57538c4a 4063static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
4064{
4065 rtl_apply_firmware(tp);
4066}
4067
6e1d0b89
CHL		 4068static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
4069{
4070 u16 dout_tapbin;
4071 u32 data;
4072
4073 rtl_apply_firmware(tp);
4074
4075 /* CHN EST parameters adjust - giga master */
4076 rtl_writephy(tp, 0x1f, 0x0a43);
4077 rtl_writephy(tp, 0x13, 0x809b);
76564428 4078 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
6e1d0b89 4079 rtl_writephy(tp, 0x13, 0x80a2);
76564428 4080 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
6e1d0b89 4081 rtl_writephy(tp, 0x13, 0x80a4);
76564428 4082 rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
6e1d0b89 4083 rtl_writephy(tp, 0x13, 0x809c);
76564428 4084 rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
6e1d0b89
CHL		 4085 rtl_writephy(tp, 0x1f, 0x0000);
4086
4087 /* CHN EST parameters adjust - giga slave */
4088 rtl_writephy(tp, 0x1f, 0x0a43);
4089 rtl_writephy(tp, 0x13, 0x80ad);
76564428 4090 rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
6e1d0b89 4091 rtl_writephy(tp, 0x13, 0x80b4);
76564428 4092 rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
6e1d0b89 4093 rtl_writephy(tp, 0x13, 0x80ac);
76564428 4094 rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
6e1d0b89
CHL		 4095 rtl_writephy(tp, 0x1f, 0x0000);
4096
4097 /* CHN EST parameters adjust - fnet */
4098 rtl_writephy(tp, 0x1f, 0x0a43);
4099 rtl_writephy(tp, 0x13, 0x808e);
76564428 4100 rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
6e1d0b89 4101 rtl_writephy(tp, 0x13, 0x8090);
76564428 4102 rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
6e1d0b89 4103 rtl_writephy(tp, 0x13, 0x8092);
76564428 4104 rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
6e1d0b89
CHL		 4105 rtl_writephy(tp, 0x1f, 0x0000);
4106
4107 /* enable R-tune & PGA-retune function */
4108 dout_tapbin = 0;
4109 rtl_writephy(tp, 0x1f, 0x0a46);
4110 data = rtl_readphy(tp, 0x13);
4111 data &= 3;
4112 data <<= 2;
4113 dout_tapbin |= data;
4114 data = rtl_readphy(tp, 0x12);
4115 data &= 0xc000;
4116 data >>= 14;
4117 dout_tapbin |= data;
4118 dout_tapbin = ~(dout_tapbin^0x08);
4119 dout_tapbin <<= 12;
4120 dout_tapbin &= 0xf000;
4121 rtl_writephy(tp, 0x1f, 0x0a43);
4122 rtl_writephy(tp, 0x13, 0x827a);
76564428 4123 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
6e1d0b89 4124 rtl_writephy(tp, 0x13, 0x827b);
76564428 4125 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
6e1d0b89 4126 rtl_writephy(tp, 0x13, 0x827c);
76564428 4127 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
6e1d0b89 4128 rtl_writephy(tp, 0x13, 0x827d);
76564428 4129 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
6e1d0b89
CHL		 4130
4131 rtl_writephy(tp, 0x1f, 0x0a43);
4132 rtl_writephy(tp, 0x13, 0x0811);
76564428 4133 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
6e1d0b89 4134 rtl_writephy(tp, 0x1f, 0x0a42);
76564428 4135 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
6e1d0b89
CHL		 4136 rtl_writephy(tp, 0x1f, 0x0000);
4137
4138 /* enable GPHY 10M */
4139 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 4140 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
6e1d0b89
CHL		 4141 rtl_writephy(tp, 0x1f, 0x0000);
4142
4143 /* SAR ADC performance */
4144 rtl_writephy(tp, 0x1f, 0x0bca);
76564428 4145 rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
6e1d0b89
CHL		 4146 rtl_writephy(tp, 0x1f, 0x0000);
4147
4148 rtl_writephy(tp, 0x1f, 0x0a43);
4149 rtl_writephy(tp, 0x13, 0x803f);
76564428 4150 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 4151 rtl_writephy(tp, 0x13, 0x8047);
76564428 4152 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 4153 rtl_writephy(tp, 0x13, 0x804f);
76564428 4154 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 4155 rtl_writephy(tp, 0x13, 0x8057);
76564428 4156 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 4157 rtl_writephy(tp, 0x13, 0x805f);
76564428 4158 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 4159 rtl_writephy(tp, 0x13, 0x8067);
76564428 4160 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 4161 rtl_writephy(tp, 0x13, 0x806f);
76564428 4162 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89
CHL		 4163 rtl_writephy(tp, 0x1f, 0x0000);
4164
4165 /* disable phy pfm mode */
4166 rtl_writephy(tp, 0x1f, 0x0a44);
c832c35f 4167 rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
6e1d0b89
CHL		 4168 rtl_writephy(tp, 0x1f, 0x0000);
4169
4170 /* Check ALDPS bit, disable it if enabled */
4171 rtl_writephy(tp, 0x1f, 0x0a43);
4172 if (rtl_readphy(tp, 0x10) & 0x0004)
76564428 4173 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
6e1d0b89
CHL		 4174
4175 rtl_writephy(tp, 0x1f, 0x0000);
4176}
4177
4178static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
4179{
4180 u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
4181 u16 rlen;
4182 u32 data;
4183
4184 rtl_apply_firmware(tp);
4185
4186 /* CHIN EST parameter update */
4187 rtl_writephy(tp, 0x1f, 0x0a43);
4188 rtl_writephy(tp, 0x13, 0x808a);
76564428 4189 rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
6e1d0b89
CHL		 4190 rtl_writephy(tp, 0x1f, 0x0000);
4191
4192 /* enable R-tune & PGA-retune function */
4193 rtl_writephy(tp, 0x1f, 0x0a43);
4194 rtl_writephy(tp, 0x13, 0x0811);
76564428 4195 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
6e1d0b89 4196 rtl_writephy(tp, 0x1f, 0x0a42);
76564428 4197 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
6e1d0b89
CHL		 4198 rtl_writephy(tp, 0x1f, 0x0000);
4199
4200 /* enable GPHY 10M */
4201 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 4202 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
6e1d0b89
CHL		 4203 rtl_writephy(tp, 0x1f, 0x0000);
4204
4205 r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
4206 data = r8168_mac_ocp_read(tp, 0xdd02);
4207 ioffset_p3 = ((data & 0x80)>>7);
4208 ioffset_p3 <<= 3;
4209
4210 data = r8168_mac_ocp_read(tp, 0xdd00);
4211 ioffset_p3 |= ((data & (0xe000))>>13);
4212 ioffset_p2 = ((data & (0x1e00))>>9);
4213 ioffset_p1 = ((data & (0x01e0))>>5);
4214 ioffset_p0 = ((data & 0x0010)>>4);
4215 ioffset_p0 <<= 3;
4216 ioffset_p0 |= (data & (0x07));
4217 data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
4218
05b9687b 4219 if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
e2e2788e 4220 (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
6e1d0b89
CHL		 4221 rtl_writephy(tp, 0x1f, 0x0bcf);
4222 rtl_writephy(tp, 0x16, data);
4223 rtl_writephy(tp, 0x1f, 0x0000);
4224 }
4225
4226 /* Modify rlen (TX LPF corner frequency) level */
4227 rtl_writephy(tp, 0x1f, 0x0bcd);
4228 data = rtl_readphy(tp, 0x16);
4229 data &= 0x000f;
4230 rlen = 0;
4231 if (data > 3)
4232 rlen = data - 3;
4233 data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
4234 rtl_writephy(tp, 0x17, data);
4235 rtl_writephy(tp, 0x1f, 0x0bcd);
4236 rtl_writephy(tp, 0x1f, 0x0000);
4237
4238 /* disable phy pfm mode */
4239 rtl_writephy(tp, 0x1f, 0x0a44);
c832c35f 4240 rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
6e1d0b89
CHL		 4241 rtl_writephy(tp, 0x1f, 0x0000);
4242
4243 /* Check ALDPS bit, disable it if enabled */
4244 rtl_writephy(tp, 0x1f, 0x0a43);
4245 if (rtl_readphy(tp, 0x10) & 0x0004)
76564428 4246 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
6e1d0b89
CHL		 4247
4248 rtl_writephy(tp, 0x1f, 0x0000);
4249}
4250
935e2218
CHL		 4251static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
4252{
4253 /* Enable PHY auto speed down */
4254 rtl_writephy(tp, 0x1f, 0x0a44);
4255 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
4256 rtl_writephy(tp, 0x1f, 0x0000);
4257
4258 /* patch 10M & ALDPS */
4259 rtl_writephy(tp, 0x1f, 0x0bcc);
4260 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
4261 rtl_writephy(tp, 0x1f, 0x0a44);
4262 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
4263 rtl_writephy(tp, 0x1f, 0x0a43);
4264 rtl_writephy(tp, 0x13, 0x8084);
4265 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
4266 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
4267 rtl_writephy(tp, 0x1f, 0x0000);
4268
4269 /* Enable EEE auto-fallback function */
4270 rtl_writephy(tp, 0x1f, 0x0a4b);
4271 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
4272 rtl_writephy(tp, 0x1f, 0x0000);
4273
4274 /* Enable UC LPF tune function */
4275 rtl_writephy(tp, 0x1f, 0x0a43);
4276 rtl_writephy(tp, 0x13, 0x8012);
4277 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
4278 rtl_writephy(tp, 0x1f, 0x0000);
4279
4280 /* set rg_sel_sdm_rate */
4281 rtl_writephy(tp, 0x1f, 0x0c42);
4282 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
4283 rtl_writephy(tp, 0x1f, 0x0000);
4284
4285 /* Check ALDPS bit, disable it if enabled */
4286 rtl_writephy(tp, 0x1f, 0x0a43);
4287 if (rtl_readphy(tp, 0x10) & 0x0004)
4288 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4289
4290 rtl_writephy(tp, 0x1f, 0x0000);
4291}
4292
4293static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
4294{
4295 /* patch 10M & ALDPS */
4296 rtl_writephy(tp, 0x1f, 0x0bcc);
4297 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
4298 rtl_writephy(tp, 0x1f, 0x0a44);
4299 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
4300 rtl_writephy(tp, 0x1f, 0x0a43);
4301 rtl_writephy(tp, 0x13, 0x8084);
4302 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
4303 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
4304 rtl_writephy(tp, 0x1f, 0x0000);
4305
4306 /* Enable UC LPF tune function */
4307 rtl_writephy(tp, 0x1f, 0x0a43);
4308 rtl_writephy(tp, 0x13, 0x8012);
4309 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
4310 rtl_writephy(tp, 0x1f, 0x0000);
4311
4312 /* Set rg_sel_sdm_rate */
4313 rtl_writephy(tp, 0x1f, 0x0c42);
4314 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
4315 rtl_writephy(tp, 0x1f, 0x0000);
4316
4317 /* Channel estimation parameters */
4318 rtl_writephy(tp, 0x1f, 0x0a43);
4319 rtl_writephy(tp, 0x13, 0x80f3);
4320 rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
4321 rtl_writephy(tp, 0x13, 0x80f0);
4322 rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
4323 rtl_writephy(tp, 0x13, 0x80ef);
4324 rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
4325 rtl_writephy(tp, 0x13, 0x80f6);
4326 rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
4327 rtl_writephy(tp, 0x13, 0x80ec);
4328 rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
4329 rtl_writephy(tp, 0x13, 0x80ed);
4330 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
4331 rtl_writephy(tp, 0x13, 0x80f2);
4332 rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
4333 rtl_writephy(tp, 0x13, 0x80f4);
4334 rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
4335 rtl_writephy(tp, 0x1f, 0x0a43);
4336 rtl_writephy(tp, 0x13, 0x8110);
4337 rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
4338 rtl_writephy(tp, 0x13, 0x810f);
4339 rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
4340 rtl_writephy(tp, 0x13, 0x8111);
4341 rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
4342 rtl_writephy(tp, 0x13, 0x8113);
4343 rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
4344 rtl_writephy(tp, 0x13, 0x8115);
4345 rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
4346 rtl_writephy(tp, 0x13, 0x810e);
4347 rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
4348 rtl_writephy(tp, 0x13, 0x810c);
4349 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
4350 rtl_writephy(tp, 0x13, 0x810b);
4351 rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
4352 rtl_writephy(tp, 0x1f, 0x0a43);
4353 rtl_writephy(tp, 0x13, 0x80d1);
4354 rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
4355 rtl_writephy(tp, 0x13, 0x80cd);
4356 rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
4357 rtl_writephy(tp, 0x13, 0x80d3);
4358 rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
4359 rtl_writephy(tp, 0x13, 0x80d5);
4360 rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
4361 rtl_writephy(tp, 0x13, 0x80d7);
4362 rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
4363
4364 /* Force PWM-mode */
4365 rtl_writephy(tp, 0x1f, 0x0bcd);
4366 rtl_writephy(tp, 0x14, 0x5065);
4367 rtl_writephy(tp, 0x14, 0xd065);
4368 rtl_writephy(tp, 0x1f, 0x0bc8);
4369 rtl_writephy(tp, 0x12, 0x00ed);
4370 rtl_writephy(tp, 0x1f, 0x0bcd);
4371 rtl_writephy(tp, 0x14, 0x1065);
4372 rtl_writephy(tp, 0x14, 0x9065);
4373 rtl_writephy(tp, 0x14, 0x1065);
4374 rtl_writephy(tp, 0x1f, 0x0000);
4375
4376 /* Check ALDPS bit, disable it if enabled */
4377 rtl_writephy(tp, 0x1f, 0x0a43);
4378 if (rtl_readphy(tp, 0x10) & 0x0004)
4379 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4380
4381 rtl_writephy(tp, 0x1f, 0x0000);
4382}
4383
4da19633 4384static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2857ffb7 4385{
350f7596 4386 static const struct phy_reg phy_reg_init[] = {
2857ffb7
FR		 4387 { 0x1f, 0x0003 },
4388 { 0x08, 0x441d },
4389 { 0x01, 0x9100 },
4390 { 0x1f, 0x0000 }
4391 };
4392
4da19633 4393 rtl_writephy(tp, 0x1f, 0x0000);
4394 rtl_patchphy(tp, 0x11, 1 << 12);
4395 rtl_patchphy(tp, 0x19, 1 << 13);
4396 rtl_patchphy(tp, 0x10, 1 << 15);
2857ffb7 4397
4da19633 4398 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2857ffb7
FR		 4399}
4400
5a5e4443
HW		 4401static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
4402{
4403 static const struct phy_reg phy_reg_init[] = {
4404 { 0x1f, 0x0005 },
4405 { 0x1a, 0x0000 },
4406 { 0x1f, 0x0000 },
4407
4408 { 0x1f, 0x0004 },
4409 { 0x1c, 0x0000 },
4410 { 0x1f, 0x0000 },
4411
4412 { 0x1f, 0x0001 },
4413 { 0x15, 0x7701 },
4414 { 0x1f, 0x0000 }
4415 };
4416
4417 /* Disable ALDPS before ram code */
eef63cc1
FR		 4418 rtl_writephy(tp, 0x1f, 0x0000);
4419 rtl_writephy(tp, 0x18, 0x0310);
4420 msleep(100);
5a5e4443 4421
953a12cc 4422 rtl_apply_firmware(tp);
5a5e4443
HW		 4423
4424 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4425}
4426
7e18dca1
HW		 4427static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
4428{
7e18dca1 4429 /* Disable ALDPS before setting firmware */
eef63cc1
FR		 4430 rtl_writephy(tp, 0x1f, 0x0000);
4431 rtl_writephy(tp, 0x18, 0x0310);
4432 msleep(20);
7e18dca1
HW		 4433
4434 rtl_apply_firmware(tp);
4435
4436 /* EEE setting */
fdf6fc06 4437 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
7e18dca1
HW		 4438 rtl_writephy(tp, 0x1f, 0x0004);
4439 rtl_writephy(tp, 0x10, 0x401f);
4440 rtl_writephy(tp, 0x19, 0x7030);
4441 rtl_writephy(tp, 0x1f, 0x0000);
4442}
4443
5598bfe5
HW		 4444static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
4445{
5598bfe5
HW		 4446 static const struct phy_reg phy_reg_init[] = {
4447 { 0x1f, 0x0004 },
4448 { 0x10, 0xc07f },
4449 { 0x19, 0x7030 },
4450 { 0x1f, 0x0000 }
4451 };
4452
4453 /* Disable ALDPS before ram code */
eef63cc1
FR		 4454 rtl_writephy(tp, 0x1f, 0x0000);
4455 rtl_writephy(tp, 0x18, 0x0310);
4456 msleep(100);
5598bfe5
HW		 4457
4458 rtl_apply_firmware(tp);
4459
fdf6fc06 4460 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5598bfe5
HW		 4461 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4462
fdf6fc06 4463 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5598bfe5
HW		 4464}
4465
5615d9f1
FR		 4466static void rtl_hw_phy_config(struct net_device *dev)
4467{
4468 struct rtl8169_private *tp = netdev_priv(dev);
5615d9f1
FR		 4469
4470 rtl8169_print_mac_version(tp);
4471
4472 switch (tp->mac_version) {
4473 case RTL_GIGA_MAC_VER_01:
4474 break;
4475 case RTL_GIGA_MAC_VER_02:
4476 case RTL_GIGA_MAC_VER_03:
4da19633 4477 rtl8169s_hw_phy_config(tp);
5615d9f1
FR		 4478 break;
4479 case RTL_GIGA_MAC_VER_04:
4da19633 4480 rtl8169sb_hw_phy_config(tp);
5615d9f1 4481 break;
2e955856 4482 case RTL_GIGA_MAC_VER_05:
4da19633 4483 rtl8169scd_hw_phy_config(tp);
2e955856 4484 break;
8c7006aa 4485 case RTL_GIGA_MAC_VER_06:
4da19633 4486 rtl8169sce_hw_phy_config(tp);
8c7006aa 4487 break;
2857ffb7
FR		 4488 case RTL_GIGA_MAC_VER_07:
4489 case RTL_GIGA_MAC_VER_08:
4490 case RTL_GIGA_MAC_VER_09:
4da19633 4491 rtl8102e_hw_phy_config(tp);
2857ffb7 4492 break;
236b8082 4493 case RTL_GIGA_MAC_VER_11:
4da19633 4494 rtl8168bb_hw_phy_config(tp);
236b8082
FR		 4495 break;
4496 case RTL_GIGA_MAC_VER_12:
4da19633 4497 rtl8168bef_hw_phy_config(tp);
236b8082
FR		 4498 break;
4499 case RTL_GIGA_MAC_VER_17:
4da19633 4500 rtl8168bef_hw_phy_config(tp);
236b8082 4501 break;
867763c1 4502 case RTL_GIGA_MAC_VER_18:
4da19633 4503 rtl8168cp_1_hw_phy_config(tp);
867763c1
FR		 4504 break;
4505 case RTL_GIGA_MAC_VER_19:
4da19633 4506 rtl8168c_1_hw_phy_config(tp);
867763c1 4507 break;
7da97ec9 4508 case RTL_GIGA_MAC_VER_20:
4da19633 4509 rtl8168c_2_hw_phy_config(tp);
7da97ec9 4510 break;
197ff761 4511 case RTL_GIGA_MAC_VER_21:
4da19633 4512 rtl8168c_3_hw_phy_config(tp);
197ff761 4513 break;
6fb07058 4514 case RTL_GIGA_MAC_VER_22:
4da19633 4515 rtl8168c_4_hw_phy_config(tp);
6fb07058 4516 break;
ef3386f0 4517 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 4518 case RTL_GIGA_MAC_VER_24:
4da19633 4519 rtl8168cp_2_hw_phy_config(tp);
ef3386f0 4520 break;
5b538df9 4521 case RTL_GIGA_MAC_VER_25:
bca03d5f 4522 rtl8168d_1_hw_phy_config(tp);
daf9df6d 4523 break;
4524 case RTL_GIGA_MAC_VER_26:
bca03d5f 4525 rtl8168d_2_hw_phy_config(tp);
daf9df6d 4526 break;
4527 case RTL_GIGA_MAC_VER_27:
4da19633 4528 rtl8168d_3_hw_phy_config(tp);
5b538df9 4529 break;
e6de30d6 4530 case RTL_GIGA_MAC_VER_28:
4531 rtl8168d_4_hw_phy_config(tp);
4532 break;
5a5e4443
HW		 4533 case RTL_GIGA_MAC_VER_29:
4534 case RTL_GIGA_MAC_VER_30:
4535 rtl8105e_hw_phy_config(tp);
4536 break;
cecb5fd7
FR		 4537 case RTL_GIGA_MAC_VER_31:
4538 /* None. */
4539 break;
01dc7fec 4540 case RTL_GIGA_MAC_VER_32:
01dc7fec 4541 case RTL_GIGA_MAC_VER_33:
70090424
HW		 4542 rtl8168e_1_hw_phy_config(tp);
4543 break;
4544 case RTL_GIGA_MAC_VER_34:
4545 rtl8168e_2_hw_phy_config(tp);
01dc7fec 4546 break;
c2218925
HW		 4547 case RTL_GIGA_MAC_VER_35:
4548 rtl8168f_1_hw_phy_config(tp);
4549 break;
4550 case RTL_GIGA_MAC_VER_36:
4551 rtl8168f_2_hw_phy_config(tp);
4552 break;
ef3386f0 4553
7e18dca1
HW		 4554 case RTL_GIGA_MAC_VER_37:
4555 rtl8402_hw_phy_config(tp);
4556 break;
4557
b3d7b2f2
HW		 4558 case RTL_GIGA_MAC_VER_38:
4559 rtl8411_hw_phy_config(tp);
4560 break;
4561
5598bfe5
HW		 4562 case RTL_GIGA_MAC_VER_39:
4563 rtl8106e_hw_phy_config(tp);
4564 break;
4565
c558386b
HW		 4566 case RTL_GIGA_MAC_VER_40:
4567 rtl8168g_1_hw_phy_config(tp);
4568 break;
57538c4a 4569 case RTL_GIGA_MAC_VER_42:
58152cd4 4570 case RTL_GIGA_MAC_VER_43:
45dd95c4 4571 case RTL_GIGA_MAC_VER_44:
57538c4a 4572 rtl8168g_2_hw_phy_config(tp);
4573 break;
6e1d0b89
CHL		 4574 case RTL_GIGA_MAC_VER_45:
4575 case RTL_GIGA_MAC_VER_47:
4576 rtl8168h_1_hw_phy_config(tp);
4577 break;
4578 case RTL_GIGA_MAC_VER_46:
4579 case RTL_GIGA_MAC_VER_48:
4580 rtl8168h_2_hw_phy_config(tp);
4581 break;
c558386b 4582
935e2218
CHL		 4583 case RTL_GIGA_MAC_VER_49:
4584 rtl8168ep_1_hw_phy_config(tp);
4585 break;
4586 case RTL_GIGA_MAC_VER_50:
4587 case RTL_GIGA_MAC_VER_51:
4588 rtl8168ep_2_hw_phy_config(tp);
4589 break;
4590
c558386b 4591 case RTL_GIGA_MAC_VER_41:
5615d9f1
FR		 4592 default:
4593 break;
4594 }
4595}
4596
da78dbff 4597static void rtl_phy_work(struct rtl8169_private *tp)
1da177e4 4598{
1da177e4
LT		 4599 struct timer_list *timer = &tp->timer;
4600 void __iomem *ioaddr = tp->mmio_addr;
4601 unsigned long timeout = RTL8169_PHY_TIMEOUT;
4602
bcf0bf90 4603 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 4604
4da19633 4605 if (tp->phy_reset_pending(tp)) {
5b0384f4 4606 /*
1da177e4
LT		 4607 * A busy loop could burn quite a few cycles on nowadays CPU.
4608 * Let's delay the execution of the timer for a few ticks.
4609 */
4610 timeout = HZ/10;
4611 goto out_mod_timer;
4612 }
4613
4614 if (tp->link_ok(ioaddr))
da78dbff 4615 return;
1da177e4 4616
9bb8eeb5 4617 netif_dbg(tp, link, tp->dev, "PHY reset until link up\n");
1da177e4 4618
4da19633 4619 tp->phy_reset_enable(tp);
1da177e4
LT		 4620
4621out_mod_timer:
4622 mod_timer(timer, jiffies + timeout);
da78dbff
FR		 4623}
4624
4625static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
4626{
da78dbff
FR		 4627 if (!test_and_set_bit(flag, tp->wk.flags))
4628 schedule_work(&tp->wk.work);
da78dbff
FR		 4629}
4630
9de36ccf 4631static void rtl8169_phy_timer(struct timer_list *t)
da78dbff 4632{
9de36ccf 4633 struct rtl8169_private *tp = from_timer(tp, t, timer);
da78dbff 4634
98ddf986 4635 rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
1da177e4
LT		 4636}
4637
ffc46952
FR		 4638DECLARE_RTL_COND(rtl_phy_reset_cond)
4639{
4640 return tp->phy_reset_pending(tp);
4641}
4642
bf793295
FR		 4643static void rtl8169_phy_reset(struct net_device *dev,
4644 struct rtl8169_private *tp)
4645{
4da19633 4646 tp->phy_reset_enable(tp);
ffc46952 4647 rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100);
bf793295
FR		 4648}
4649
2544bfc0
FR		 4650static bool rtl_tbi_enabled(struct rtl8169_private *tp)
4651{
4652 void __iomem *ioaddr = tp->mmio_addr;
4653
4654 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
4655 (RTL_R8(PHYstatus) & TBI_Enable);
4656}
4657
4ff96fa6
FR		 4658static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
4659{
4660 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 4661
5615d9f1 4662 rtl_hw_phy_config(dev);
4ff96fa6 4663
77332894
MS		 4664 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
4665 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4666 RTL_W8(0x82, 0x01);
4667 }
4ff96fa6 4668
6dccd16b
FR		 4669 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
4670
4671 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
4672 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 4673
bcf0bf90 4674 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 4675 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4676 RTL_W8(0x82, 0x01);
4677 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4da19633 4678 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4ff96fa6
FR		 4679 }
4680
bf793295
FR		 4681 rtl8169_phy_reset(dev, tp);
4682
54405cde 4683 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
cecb5fd7
FR		 4684 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4685 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4686 (tp->mii.supports_gmii ?
4687 ADVERTISED_1000baseT_Half |
4688 ADVERTISED_1000baseT_Full : 0));
4ff96fa6 4689
2544bfc0 4690 if (rtl_tbi_enabled(tp))
bf82c189 4691 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4ff96fa6
FR		 4692}
4693
773d2021
FR		 4694static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4695{
4696 void __iomem *ioaddr = tp->mmio_addr;
773d2021 4697
da78dbff 4698 rtl_lock_work(tp);
773d2021
FR		 4699
4700 RTL_W8(Cfg9346, Cfg9346_Unlock);
908ba2bf 4701
9ecb9aab 4702 RTL_W32(MAC4, addr[4] | addr[5] << 8);
908ba2bf 4703 RTL_R32(MAC4);
4704
9ecb9aab 4705 RTL_W32(MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
908ba2bf 4706 RTL_R32(MAC0);
4707
9ecb9aab 4708 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4709 rtl_rar_exgmac_set(tp, addr);
c28aa385 4710
773d2021
FR		 4711 RTL_W8(Cfg9346, Cfg9346_Lock);
4712
da78dbff 4713 rtl_unlock_work(tp);
773d2021
FR		 4714}
4715
4716static int rtl_set_mac_address(struct net_device *dev, void *p)
4717{
4718 struct rtl8169_private *tp = netdev_priv(dev);
f51d4a10 4719 struct device *d = &tp->pci_dev->dev;
773d2021
FR		 4720 struct sockaddr *addr = p;
4721
4722 if (!is_valid_ether_addr(addr->sa_data))
4723 return -EADDRNOTAVAIL;
4724
4725 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
4726
f51d4a10
CHL		 4727 pm_runtime_get_noresume(d);
4728
4729 if (pm_runtime_active(d))
4730 rtl_rar_set(tp, dev->dev_addr);
4731
4732 pm_runtime_put_noidle(d);
773d2021
FR		 4733
4734 return 0;
4735}
4736
5f787a1a
FR		 4737static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4738{
4739 struct rtl8169_private *tp = netdev_priv(dev);
4740 struct mii_ioctl_data *data = if_mii(ifr);
4741
8b4ab28d
FR		 4742 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
4743}
5f787a1a 4744
cecb5fd7
FR		 4745static int rtl_xmii_ioctl(struct rtl8169_private *tp,
4746 struct mii_ioctl_data *data, int cmd)
8b4ab28d 4747{
5f787a1a
FR		 4748 switch (cmd) {
4749 case SIOCGMIIPHY:
4750 data->phy_id = 32; /* Internal PHY */
4751 return 0;
4752
4753 case SIOCGMIIREG:
4da19633 4754 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
5f787a1a
FR		 4755 return 0;
4756
4757 case SIOCSMIIREG:
4da19633 4758 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
5f787a1a
FR		 4759 return 0;
4760 }
4761 return -EOPNOTSUPP;
4762}
4763
8b4ab28d
FR		 4764static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
4765{
4766 return -EOPNOTSUPP;
4767}
4768
baf63293 4769static void rtl_init_mdio_ops(struct rtl8169_private *tp)
c0e45c1c 4770{
4771 struct mdio_ops *ops = &tp->mdio_ops;
4772
4773 switch (tp->mac_version) {
4774 case RTL_GIGA_MAC_VER_27:
4775 ops->write = r8168dp_1_mdio_write;
4776 ops->read = r8168dp_1_mdio_read;
4777 break;
e6de30d6 4778 case RTL_GIGA_MAC_VER_28:
4804b3b3 4779 case RTL_GIGA_MAC_VER_31:
e6de30d6 4780 ops->write = r8168dp_2_mdio_write;
4781 ops->read = r8168dp_2_mdio_read;
4782 break;
c558386b
HW		 4783 case RTL_GIGA_MAC_VER_40:
4784 case RTL_GIGA_MAC_VER_41:
57538c4a 4785 case RTL_GIGA_MAC_VER_42:
58152cd4 4786 case RTL_GIGA_MAC_VER_43:
45dd95c4 4787 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4788 case RTL_GIGA_MAC_VER_45:
4789 case RTL_GIGA_MAC_VER_46:
4790 case RTL_GIGA_MAC_VER_47:
4791 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 4792 case RTL_GIGA_MAC_VER_49:
4793 case RTL_GIGA_MAC_VER_50:
4794 case RTL_GIGA_MAC_VER_51:
c558386b
HW		 4795 ops->write = r8168g_mdio_write;
4796 ops->read = r8168g_mdio_read;
4797 break;
c0e45c1c 4798 default:
4799 ops->write = r8169_mdio_write;
4800 ops->read = r8169_mdio_read;
4801 break;
4802 }
4803}
4804
e2409d83 4805static void rtl_speed_down(struct rtl8169_private *tp)
4806{
4807 u32 adv;
4808 int lpa;
4809
4810 rtl_writephy(tp, 0x1f, 0x0000);
4811 lpa = rtl_readphy(tp, MII_LPA);
4812
4813 if (lpa & (LPA_10HALF | LPA_10FULL))
4814 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
4815 else if (lpa & (LPA_100HALF | LPA_100FULL))
4816 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4817 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4818 else
4819 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4820 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4821 (tp->mii.supports_gmii ?
4822 ADVERTISED_1000baseT_Half |
4823 ADVERTISED_1000baseT_Full : 0);
4824
4825 rtl8169_set_speed(tp->dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
4826 adv);
4827}
4828
649b3b8c 4829static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4830{
4831 void __iomem *ioaddr = tp->mmio_addr;
4832
4833 switch (tp->mac_version) {
b00e69de
CB		 4834 case RTL_GIGA_MAC_VER_25:
4835 case RTL_GIGA_MAC_VER_26:
649b3b8c 4836 case RTL_GIGA_MAC_VER_29:
4837 case RTL_GIGA_MAC_VER_30:
4838 case RTL_GIGA_MAC_VER_32:
4839 case RTL_GIGA_MAC_VER_33:
4840 case RTL_GIGA_MAC_VER_34:
7e18dca1 4841 case RTL_GIGA_MAC_VER_37:
b3d7b2f2 4842 case RTL_GIGA_MAC_VER_38:
5598bfe5 4843 case RTL_GIGA_MAC_VER_39:
c558386b
HW		 4844 case RTL_GIGA_MAC_VER_40:
4845 case RTL_GIGA_MAC_VER_41:
57538c4a 4846 case RTL_GIGA_MAC_VER_42:
58152cd4 4847 case RTL_GIGA_MAC_VER_43:
45dd95c4 4848 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4849 case RTL_GIGA_MAC_VER_45:
4850 case RTL_GIGA_MAC_VER_46:
4851 case RTL_GIGA_MAC_VER_47:
4852 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 4853 case RTL_GIGA_MAC_VER_49:
4854 case RTL_GIGA_MAC_VER_50:
4855 case RTL_GIGA_MAC_VER_51:
649b3b8c 4856 RTL_W32(RxConfig, RTL_R32(RxConfig) |
4857 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4858 break;
4859 default:
4860 break;
4861 }
4862}
4863
4864static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
4865{
4866 if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
4867 return false;
4868
e2409d83 4869 rtl_speed_down(tp);
649b3b8c 4870 rtl_wol_suspend_quirk(tp);
4871
4872 return true;
4873}
4874
065c27c1 4875static void r810x_phy_power_down(struct rtl8169_private *tp)
4876{
4877 rtl_writephy(tp, 0x1f, 0x0000);
4878 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4879}
4880
4881static void r810x_phy_power_up(struct rtl8169_private *tp)
4882{
4883 rtl_writephy(tp, 0x1f, 0x0000);
4884 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4885}
4886
4887static void r810x_pll_power_down(struct rtl8169_private *tp)
4888{
0004299a
HW		 4889 void __iomem *ioaddr = tp->mmio_addr;
4890
649b3b8c 4891 if (rtl_wol_pll_power_down(tp))
065c27c1 4892 return;
065c27c1 4893
4894 r810x_phy_power_down(tp);
0004299a
HW		 4895
4896 switch (tp->mac_version) {
4897 case RTL_GIGA_MAC_VER_07:
4898 case RTL_GIGA_MAC_VER_08:
4899 case RTL_GIGA_MAC_VER_09:
4900 case RTL_GIGA_MAC_VER_10:
4901 case RTL_GIGA_MAC_VER_13:
4902 case RTL_GIGA_MAC_VER_16:
4903 break;
4904 default:
4905 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4906 break;
4907 }
065c27c1 4908}
4909
4910static void r810x_pll_power_up(struct rtl8169_private *tp)
4911{
0004299a
HW		 4912 void __iomem *ioaddr = tp->mmio_addr;
4913
065c27c1 4914 r810x_phy_power_up(tp);
0004299a
HW		 4915
4916 switch (tp->mac_version) {
4917 case RTL_GIGA_MAC_VER_07:
4918 case RTL_GIGA_MAC_VER_08:
4919 case RTL_GIGA_MAC_VER_09:
4920 case RTL_GIGA_MAC_VER_10:
4921 case RTL_GIGA_MAC_VER_13:
4922 case RTL_GIGA_MAC_VER_16:
4923 break;
6e1d0b89
CHL		 4924 case RTL_GIGA_MAC_VER_47:
4925 case RTL_GIGA_MAC_VER_48:
05b9687b 4926 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
6e1d0b89 4927 break;
0004299a
HW		 4928 default:
4929 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4930 break;
4931 }
065c27c1 4932}
4933
4934static void r8168_phy_power_up(struct rtl8169_private *tp)
4935{
4936 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 4937 switch (tp->mac_version) {
4938 case RTL_GIGA_MAC_VER_11:
4939 case RTL_GIGA_MAC_VER_12:
4940 case RTL_GIGA_MAC_VER_17:
4941 case RTL_GIGA_MAC_VER_18:
4942 case RTL_GIGA_MAC_VER_19:
4943 case RTL_GIGA_MAC_VER_20:
4944 case RTL_GIGA_MAC_VER_21:
4945 case RTL_GIGA_MAC_VER_22:
4946 case RTL_GIGA_MAC_VER_23:
4947 case RTL_GIGA_MAC_VER_24:
4948 case RTL_GIGA_MAC_VER_25:
4949 case RTL_GIGA_MAC_VER_26:
4950 case RTL_GIGA_MAC_VER_27:
4951 case RTL_GIGA_MAC_VER_28:
4952 case RTL_GIGA_MAC_VER_31:
4953 rtl_writephy(tp, 0x0e, 0x0000);
4954 break;
4955 default:
4956 break;
4957 }
065c27c1 4958 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4959}
4960
4961static void r8168_phy_power_down(struct rtl8169_private *tp)
4962{
4963 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 4964 switch (tp->mac_version) {
4965 case RTL_GIGA_MAC_VER_32:
4966 case RTL_GIGA_MAC_VER_33:
beb330a4 4967 case RTL_GIGA_MAC_VER_40:
4968 case RTL_GIGA_MAC_VER_41:
01dc7fec 4969 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
4970 break;
4971
4972 case RTL_GIGA_MAC_VER_11:
4973 case RTL_GIGA_MAC_VER_12:
4974 case RTL_GIGA_MAC_VER_17:
4975 case RTL_GIGA_MAC_VER_18:
4976 case RTL_GIGA_MAC_VER_19:
4977 case RTL_GIGA_MAC_VER_20:
4978 case RTL_GIGA_MAC_VER_21:
4979 case RTL_GIGA_MAC_VER_22:
4980 case RTL_GIGA_MAC_VER_23:
4981 case RTL_GIGA_MAC_VER_24:
4982 case RTL_GIGA_MAC_VER_25:
4983 case RTL_GIGA_MAC_VER_26:
4984 case RTL_GIGA_MAC_VER_27:
4985 case RTL_GIGA_MAC_VER_28:
4986 case RTL_GIGA_MAC_VER_31:
4987 rtl_writephy(tp, 0x0e, 0x0200);
4988 default:
4989 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4990 break;
4991 }
065c27c1 4992}
4993
4994static void r8168_pll_power_down(struct rtl8169_private *tp)
4995{
4996 void __iomem *ioaddr = tp->mmio_addr;
4997
cecb5fd7
FR		 4998 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4999 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
935e2218
CHL		 5000 tp->mac_version == RTL_GIGA_MAC_VER_31 ||
5001 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
5002 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
5003 tp->mac_version == RTL_GIGA_MAC_VER_51) &&
2f8c040c 5004 r8168_check_dash(tp)) {
065c27c1 5005 return;
5d2e1957 5006 }
065c27c1 5007
cecb5fd7
FR		 5008 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
5009 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
065c27c1 5010 (RTL_R16(CPlusCmd) & ASF)) {
5011 return;
5012 }
5013
01dc7fec 5014 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
5015 tp->mac_version == RTL_GIGA_MAC_VER_33)
fdf6fc06 5016 rtl_ephy_write(tp, 0x19, 0xff64);
01dc7fec 5017
649b3b8c 5018 if (rtl_wol_pll_power_down(tp))
065c27c1 5019 return;
065c27c1 5020
5021 r8168_phy_power_down(tp);
5022
5023 switch (tp->mac_version) {
5024 case RTL_GIGA_MAC_VER_25:
5025 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 5026 case RTL_GIGA_MAC_VER_27:
5027 case RTL_GIGA_MAC_VER_28:
4804b3b3 5028 case RTL_GIGA_MAC_VER_31:
01dc7fec 5029 case RTL_GIGA_MAC_VER_32:
5030 case RTL_GIGA_MAC_VER_33:
42fde737 5031 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 5032 case RTL_GIGA_MAC_VER_45:
5033 case RTL_GIGA_MAC_VER_46:
935e2218
CHL		 5034 case RTL_GIGA_MAC_VER_50:
5035 case RTL_GIGA_MAC_VER_51:
065c27c1 5036 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
5037 break;
beb330a4 5038 case RTL_GIGA_MAC_VER_40:
5039 case RTL_GIGA_MAC_VER_41:
935e2218 5040 case RTL_GIGA_MAC_VER_49:
706123d0 5041 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
beb330a4 5042 0xfc000000, ERIAR_EXGMAC);
b8e5e6ad 5043 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
beb330a4 5044 break;
065c27c1 5045 }
5046}
5047
5048static void r8168_pll_power_up(struct rtl8169_private *tp)
5049{
5050 void __iomem *ioaddr = tp->mmio_addr;
5051
065c27c1 5052 switch (tp->mac_version) {
5053 case RTL_GIGA_MAC_VER_25:
5054 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 5055 case RTL_GIGA_MAC_VER_27:
5056 case RTL_GIGA_MAC_VER_28:
4804b3b3 5057 case RTL_GIGA_MAC_VER_31:
01dc7fec 5058 case RTL_GIGA_MAC_VER_32:
5059 case RTL_GIGA_MAC_VER_33:
065c27c1 5060 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
5061 break;
42fde737 5062 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 5063 case RTL_GIGA_MAC_VER_45:
5064 case RTL_GIGA_MAC_VER_46:
935e2218
CHL		 5065 case RTL_GIGA_MAC_VER_50:
5066 case RTL_GIGA_MAC_VER_51:
05b9687b 5067 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
6e1d0b89 5068 break;
beb330a4 5069 case RTL_GIGA_MAC_VER_40:
5070 case RTL_GIGA_MAC_VER_41:
935e2218 5071 case RTL_GIGA_MAC_VER_49:
b8e5e6ad 5072 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
706123d0 5073 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
beb330a4 5074 0x00000000, ERIAR_EXGMAC);
5075 break;
065c27c1 5076 }
5077
5078 r8168_phy_power_up(tp);
5079}
5080
d58d46b5
FR		 5081static void rtl_generic_op(struct rtl8169_private *tp,
5082 void (*op)(struct rtl8169_private *))
065c27c1 5083{
5084 if (op)
5085 op(tp);
5086}
5087
5088static void rtl_pll_power_down(struct rtl8169_private *tp)
5089{
d58d46b5 5090 rtl_generic_op(tp, tp->pll_power_ops.down);
065c27c1 5091}
5092
5093static void rtl_pll_power_up(struct rtl8169_private *tp)
5094{
d58d46b5 5095 rtl_generic_op(tp, tp->pll_power_ops.up);
36d1c220
HK		 5096
5097 /* give MAC/PHY some time to resume */
5098 msleep(20);
065c27c1 5099}
5100
baf63293 5101static void rtl_init_pll_power_ops(struct rtl8169_private *tp)
065c27c1 5102{
5103 struct pll_power_ops *ops = &tp->pll_power_ops;
5104
5105 switch (tp->mac_version) {
5106 case RTL_GIGA_MAC_VER_07:
5107 case RTL_GIGA_MAC_VER_08:
5108 case RTL_GIGA_MAC_VER_09:
5109 case RTL_GIGA_MAC_VER_10:
5110 case RTL_GIGA_MAC_VER_16:
5a5e4443
HW		 5111 case RTL_GIGA_MAC_VER_29:
5112 case RTL_GIGA_MAC_VER_30:
7e18dca1 5113 case RTL_GIGA_MAC_VER_37:
5598bfe5 5114 case RTL_GIGA_MAC_VER_39:
58152cd4 5115 case RTL_GIGA_MAC_VER_43:
6e1d0b89
CHL		 5116 case RTL_GIGA_MAC_VER_47:
5117 case RTL_GIGA_MAC_VER_48:
065c27c1 5118 ops->down = r810x_pll_power_down;
5119 ops->up = r810x_pll_power_up;
5120 break;
5121
5122 case RTL_GIGA_MAC_VER_11:
5123 case RTL_GIGA_MAC_VER_12:
5124 case RTL_GIGA_MAC_VER_17:
5125 case RTL_GIGA_MAC_VER_18:
5126 case RTL_GIGA_MAC_VER_19:
5127 case RTL_GIGA_MAC_VER_20:
5128 case RTL_GIGA_MAC_VER_21:
5129 case RTL_GIGA_MAC_VER_22:
5130 case RTL_GIGA_MAC_VER_23:
5131 case RTL_GIGA_MAC_VER_24:
5132 case RTL_GIGA_MAC_VER_25:
5133 case RTL_GIGA_MAC_VER_26:
5134 case RTL_GIGA_MAC_VER_27:
e6de30d6 5135 case RTL_GIGA_MAC_VER_28:
4804b3b3 5136 case RTL_GIGA_MAC_VER_31:
01dc7fec 5137 case RTL_GIGA_MAC_VER_32:
5138 case RTL_GIGA_MAC_VER_33:
70090424 5139 case RTL_GIGA_MAC_VER_34:
c2218925
HW		 5140 case RTL_GIGA_MAC_VER_35:
5141 case RTL_GIGA_MAC_VER_36:
b3d7b2f2 5142 case RTL_GIGA_MAC_VER_38:
c558386b
HW		 5143 case RTL_GIGA_MAC_VER_40:
5144 case RTL_GIGA_MAC_VER_41:
57538c4a 5145 case RTL_GIGA_MAC_VER_42:
45dd95c4 5146 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 5147 case RTL_GIGA_MAC_VER_45:
5148 case RTL_GIGA_MAC_VER_46:
935e2218
CHL		 5149 case RTL_GIGA_MAC_VER_49:
5150 case RTL_GIGA_MAC_VER_50:
5151 case RTL_GIGA_MAC_VER_51:
065c27c1 5152 ops->down = r8168_pll_power_down;
5153 ops->up = r8168_pll_power_up;
5154 break;
5155
5156 default:
5157 ops->down = NULL;
5158 ops->up = NULL;
5159 break;
5160 }
5161}
5162
e542a226
HW		 5163static void rtl_init_rxcfg(struct rtl8169_private *tp)
5164{
5165 void __iomem *ioaddr = tp->mmio_addr;
5166
5167 switch (tp->mac_version) {
5168 case RTL_GIGA_MAC_VER_01:
5169 case RTL_GIGA_MAC_VER_02:
5170 case RTL_GIGA_MAC_VER_03:
5171 case RTL_GIGA_MAC_VER_04:
5172 case RTL_GIGA_MAC_VER_05:
5173 case RTL_GIGA_MAC_VER_06:
5174 case RTL_GIGA_MAC_VER_10:
5175 case RTL_GIGA_MAC_VER_11:
5176 case RTL_GIGA_MAC_VER_12:
5177 case RTL_GIGA_MAC_VER_13:
5178 case RTL_GIGA_MAC_VER_14:
5179 case RTL_GIGA_MAC_VER_15:
5180 case RTL_GIGA_MAC_VER_16:
5181 case RTL_GIGA_MAC_VER_17:
5182 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
5183 break;
5184 case RTL_GIGA_MAC_VER_18:
5185 case RTL_GIGA_MAC_VER_19:
5186 case RTL_GIGA_MAC_VER_20:
5187 case RTL_GIGA_MAC_VER_21:
5188 case RTL_GIGA_MAC_VER_22:
5189 case RTL_GIGA_MAC_VER_23:
5190 case RTL_GIGA_MAC_VER_24:
eb2dc35d 5191 case RTL_GIGA_MAC_VER_34:
3ced8c95 5192 case RTL_GIGA_MAC_VER_35:
e542a226
HW		 5193 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
5194 break;
beb330a4 5195 case RTL_GIGA_MAC_VER_40:
5196 case RTL_GIGA_MAC_VER_41:
57538c4a 5197 case RTL_GIGA_MAC_VER_42:
58152cd4 5198 case RTL_GIGA_MAC_VER_43:
45dd95c4 5199 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 5200 case RTL_GIGA_MAC_VER_45:
5201 case RTL_GIGA_MAC_VER_46:
5202 case RTL_GIGA_MAC_VER_47:
5203 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 5204 case RTL_GIGA_MAC_VER_49:
5205 case RTL_GIGA_MAC_VER_50:
5206 case RTL_GIGA_MAC_VER_51:
7ebc4822 5207 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
beb330a4 5208 break;
e542a226
HW		 5209 default:
5210 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
5211 break;
5212 }
5213}
5214
92fc43b4
HW		 5215static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
5216{
9fba0812 5217 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
92fc43b4
HW		 5218}
5219
d58d46b5
FR		 5220static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
5221{
9c5028e9 5222 void __iomem *ioaddr = tp->mmio_addr;
5223
5224 RTL_W8(Cfg9346, Cfg9346_Unlock);
d58d46b5 5225 rtl_generic_op(tp, tp->jumbo_ops.enable);
9c5028e9 5226 RTL_W8(Cfg9346, Cfg9346_Lock);
d58d46b5
FR		 5227}
5228
5229static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
5230{
9c5028e9 5231 void __iomem *ioaddr = tp->mmio_addr;
5232
5233 RTL_W8(Cfg9346, Cfg9346_Unlock);
d58d46b5 5234 rtl_generic_op(tp, tp->jumbo_ops.disable);
9c5028e9 5235 RTL_W8(Cfg9346, Cfg9346_Lock);
d58d46b5
FR		 5236}
5237
5238static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
5239{
5240 void __iomem *ioaddr = tp->mmio_addr;
5241
5242 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
5243 RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
f65d539c 5244 rtl_tx_performance_tweak(tp->pci_dev, PCI_EXP_DEVCTL_READRQ_512B);
d58d46b5
FR		 5245}
5246
5247static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
5248{
5249 void __iomem *ioaddr = tp->mmio_addr;
5250
5251 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
5252 RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
5253 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
5254}
5255
5256static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
5257{
5258 void __iomem *ioaddr = tp->mmio_addr;
5259
5260 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
5261}
5262
5263static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
5264{
5265 void __iomem *ioaddr = tp->mmio_addr;
5266
5267 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
5268}
5269
5270static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
5271{
5272 void __iomem *ioaddr = tp->mmio_addr;
d58d46b5
FR		 5273
5274 RTL_W8(MaxTxPacketSize, 0x3f);
5275 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
5276 RTL_W8(Config4, RTL_R8(Config4) | 0x01);
f65d539c 5277 rtl_tx_performance_tweak(tp->pci_dev, PCI_EXP_DEVCTL_READRQ_512B);
d58d46b5
FR		 5278}
5279
5280static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
5281{
5282 void __iomem *ioaddr = tp->mmio_addr;
d58d46b5
FR		 5283
5284 RTL_W8(MaxTxPacketSize, 0x0c);
5285 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
5286 RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
4512ff9f 5287 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
d58d46b5
FR		 5288}
5289
5290static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
5291{
5292 rtl_tx_performance_tweak(tp->pci_dev,
f65d539c 5293 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
d58d46b5
FR		 5294}
5295
5296static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
5297{
5298 rtl_tx_performance_tweak(tp->pci_dev,
5299 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
5300}
5301
5302static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
5303{
5304 void __iomem *ioaddr = tp->mmio_addr;
5305
5306 r8168b_0_hw_jumbo_enable(tp);
5307
5308 RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
5309}
5310
5311static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
5312{
5313 void __iomem *ioaddr = tp->mmio_addr;
5314
5315 r8168b_0_hw_jumbo_disable(tp);
5316
5317 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
5318}
5319
baf63293 5320static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
d58d46b5
FR		 5321{
5322 struct jumbo_ops *ops = &tp->jumbo_ops;
5323
5324 switch (tp->mac_version) {
5325 case RTL_GIGA_MAC_VER_11:
5326 ops->disable = r8168b_0_hw_jumbo_disable;
5327 ops->enable = r8168b_0_hw_jumbo_enable;
5328 break;
5329 case RTL_GIGA_MAC_VER_12:
5330 case RTL_GIGA_MAC_VER_17:
5331 ops->disable = r8168b_1_hw_jumbo_disable;
5332 ops->enable = r8168b_1_hw_jumbo_enable;
5333 break;
5334 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
5335 case RTL_GIGA_MAC_VER_19:
5336 case RTL_GIGA_MAC_VER_20:
5337 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
5338 case RTL_GIGA_MAC_VER_22:
5339 case RTL_GIGA_MAC_VER_23:
5340 case RTL_GIGA_MAC_VER_24:
5341 case RTL_GIGA_MAC_VER_25:
5342 case RTL_GIGA_MAC_VER_26:
5343 ops->disable = r8168c_hw_jumbo_disable;
5344 ops->enable = r8168c_hw_jumbo_enable;
5345 break;
5346 case RTL_GIGA_MAC_VER_27:
5347 case RTL_GIGA_MAC_VER_28:
5348 ops->disable = r8168dp_hw_jumbo_disable;
5349 ops->enable = r8168dp_hw_jumbo_enable;
5350 break;
5351 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
5352 case RTL_GIGA_MAC_VER_32:
5353 case RTL_GIGA_MAC_VER_33:
5354 case RTL_GIGA_MAC_VER_34:
5355 ops->disable = r8168e_hw_jumbo_disable;
5356 ops->enable = r8168e_hw_jumbo_enable;
5357 break;
5358
5359 /*
5360 * No action needed for jumbo frames with 8169.
5361 * No jumbo for 810x at all.
5362 */
c558386b
HW		 5363 case RTL_GIGA_MAC_VER_40:
5364 case RTL_GIGA_MAC_VER_41:
57538c4a 5365 case RTL_GIGA_MAC_VER_42:
58152cd4 5366 case RTL_GIGA_MAC_VER_43:
45dd95c4 5367 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 5368 case RTL_GIGA_MAC_VER_45:
5369 case RTL_GIGA_MAC_VER_46:
5370 case RTL_GIGA_MAC_VER_47:
5371 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 5372 case RTL_GIGA_MAC_VER_49:
5373 case RTL_GIGA_MAC_VER_50:
5374 case RTL_GIGA_MAC_VER_51:
d58d46b5
FR		 5375 default:
5376 ops->disable = NULL;
5377 ops->enable = NULL;
5378 break;
5379 }
5380}
5381
ffc46952
FR		 5382DECLARE_RTL_COND(rtl_chipcmd_cond)
5383{
5384 void __iomem *ioaddr = tp->mmio_addr;
5385
5386 return RTL_R8(ChipCmd) & CmdReset;
5387}
5388
6f43adc8
FR		 5389static void rtl_hw_reset(struct rtl8169_private *tp)
5390{
5391 void __iomem *ioaddr = tp->mmio_addr;
6f43adc8 5392
6f43adc8
FR		 5393 RTL_W8(ChipCmd, CmdReset);
5394
ffc46952 5395 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
6f43adc8
FR		 5396}
5397
b6ffd97f 5398static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
953a12cc 5399{
b6ffd97f
FR		 5400 struct rtl_fw *rtl_fw;
5401 const char *name;
5402 int rc = -ENOMEM;
953a12cc 5403
b6ffd97f
FR		 5404 name = rtl_lookup_firmware_name(tp);
5405 if (!name)
5406 goto out_no_firmware;
953a12cc 5407
b6ffd97f
FR		 5408 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
5409 if (!rtl_fw)
5410 goto err_warn;
31bd204f 5411
b6ffd97f
FR		 5412 rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
5413 if (rc < 0)
5414 goto err_free;
5415
fd112f2e
FR		 5416 rc = rtl_check_firmware(tp, rtl_fw);
5417 if (rc < 0)
5418 goto err_release_firmware;
5419
b6ffd97f
FR		 5420 tp->rtl_fw = rtl_fw;
5421out:
5422 return;
5423
fd112f2e
FR		 5424err_release_firmware:
5425 release_firmware(rtl_fw->fw);
b6ffd97f
FR		 5426err_free:
5427 kfree(rtl_fw);
5428err_warn:
5429 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
5430 name, rc);
5431out_no_firmware:
5432 tp->rtl_fw = NULL;
5433 goto out;
5434}
5435
5436static void rtl_request_firmware(struct rtl8169_private *tp)
5437{
5438 if (IS_ERR(tp->rtl_fw))
5439 rtl_request_uncached_firmware(tp);
953a12cc
FR		 5440}
5441
92fc43b4
HW		 5442static void rtl_rx_close(struct rtl8169_private *tp)
5443{
5444 void __iomem *ioaddr = tp->mmio_addr;
92fc43b4 5445
1687b566 5446 RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
92fc43b4
HW		 5447}
5448
ffc46952
FR		 5449DECLARE_RTL_COND(rtl_npq_cond)
5450{
5451 void __iomem *ioaddr = tp->mmio_addr;
5452
5453 return RTL_R8(TxPoll) & NPQ;
5454}
5455
5456DECLARE_RTL_COND(rtl_txcfg_empty_cond)
5457{
5458 void __iomem *ioaddr = tp->mmio_addr;
5459
5460 return RTL_R32(TxConfig) & TXCFG_EMPTY;
5461}
5462
e6de30d6 5463static void rtl8169_hw_reset(struct rtl8169_private *tp)
1da177e4 5464{
e6de30d6 5465 void __iomem *ioaddr = tp->mmio_addr;
5466
1da177e4 5467 /* Disable interrupts */
811fd301 5468 rtl8169_irq_mask_and_ack(tp);
1da177e4 5469
92fc43b4
HW		 5470 rtl_rx_close(tp);
5471
5d2e1957 5472 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4804b3b3 5473 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
5474 tp->mac_version == RTL_GIGA_MAC_VER_31) {
ffc46952 5475 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
c2218925 5476 } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
6e1d0b89
CHL		 5477 tp->mac_version == RTL_GIGA_MAC_VER_35 ||
5478 tp->mac_version == RTL_GIGA_MAC_VER_36 ||
5479 tp->mac_version == RTL_GIGA_MAC_VER_37 ||
5480 tp->mac_version == RTL_GIGA_MAC_VER_38 ||
5481 tp->mac_version == RTL_GIGA_MAC_VER_40 ||
5482 tp->mac_version == RTL_GIGA_MAC_VER_41 ||
5483 tp->mac_version == RTL_GIGA_MAC_VER_42 ||
5484 tp->mac_version == RTL_GIGA_MAC_VER_43 ||
5485 tp->mac_version == RTL_GIGA_MAC_VER_44 ||
5486 tp->mac_version == RTL_GIGA_MAC_VER_45 ||
5487 tp->mac_version == RTL_GIGA_MAC_VER_46 ||
5488 tp->mac_version == RTL_GIGA_MAC_VER_47 ||
935e2218
CHL		 5489 tp->mac_version == RTL_GIGA_MAC_VER_48 ||
5490 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
5491 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
5492 tp->mac_version == RTL_GIGA_MAC_VER_51) {
c2b0c1e7 5493 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
ffc46952 5494 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
92fc43b4
HW		 5495 } else {
5496 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
5497 udelay(100);
e6de30d6 5498 }
5499
92fc43b4 5500 rtl_hw_reset(tp);
1da177e4
LT		 5501}
5502
7f796d83 5503static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 5504{
5505 void __iomem *ioaddr = tp->mmio_addr;
9cb427b6
FR		 5506
5507 /* Set DMA burst size and Interframe Gap Time */
5508 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
5509 (InterFrameGap << TxInterFrameGapShift));
5510}
5511
07ce4064 5512static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 5513{
5514 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 5515
07ce4064
FR		 5516 tp->hw_start(dev);
5517
da78dbff 5518 rtl_irq_enable_all(tp);
07ce4064
FR		 5519}
5520
7f796d83
FR		 5521static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
5522 void __iomem *ioaddr)
5523{
5524 /*
5525 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
5526 * register to be written before TxDescAddrLow to work.
5527 * Switching from MMIO to I/O access fixes the issue as well.
5528 */
5529 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
284901a9 5530 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
7f796d83 5531 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
284901a9 5532 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 5533}
5534
5535static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
5536{
5537 u16 cmd;
5538
5539 cmd = RTL_R16(CPlusCmd);
5540 RTL_W16(CPlusCmd, cmd);
5541 return cmd;
5542}
5543
fdd7b4c3 5544static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
7f796d83
FR		 5545{
5546 /* Low hurts. Let's disable the filtering. */
207d6e87 5547 RTL_W16(RxMaxSize, rx_buf_sz + 1);
7f796d83
FR		 5548}
5549
6dccd16b
FR		 5550static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
5551{
3744100e 5552 static const struct rtl_cfg2_info {
6dccd16b
FR		 5553 u32 mac_version;
5554 u32 clk;
5555 u32 val;
5556 } cfg2_info [] = {
5557 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
5558 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
5559 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
5560 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3744100e
FR		 5561 };
5562 const struct rtl_cfg2_info *p = cfg2_info;
6dccd16b
FR		 5563 unsigned int i;
5564 u32 clk;
5565
5566 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 5567 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 5568 if ((p->mac_version == mac_version) && (p->clk == clk)) {
5569 RTL_W32(0x7c, p->val);
5570 break;
5571 }
5572 }
5573}
5574
e6b763ea
FR		 5575static void rtl_set_rx_mode(struct net_device *dev)
5576{
5577 struct rtl8169_private *tp = netdev_priv(dev);
5578 void __iomem *ioaddr = tp->mmio_addr;
5579 u32 mc_filter[2]; /* Multicast hash filter */
5580 int rx_mode;
5581 u32 tmp = 0;
5582
5583 if (dev->flags & IFF_PROMISC) {
5584 /* Unconditionally log net taps. */
5585 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
5586 rx_mode =
5587 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5588 AcceptAllPhys;
5589 mc_filter[1] = mc_filter[0] = 0xffffffff;
5590 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
5591 (dev->flags & IFF_ALLMULTI)) {
5592 /* Too many to filter perfectly -- accept all multicasts. */
5593 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5594 mc_filter[1] = mc_filter[0] = 0xffffffff;
5595 } else {
5596 struct netdev_hw_addr *ha;
5597
5598 rx_mode = AcceptBroadcast | AcceptMyPhys;
5599 mc_filter[1] = mc_filter[0] = 0;
5600 netdev_for_each_mc_addr(ha, dev) {
5601 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
5602 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5603 rx_mode |= AcceptMulticast;
5604 }
5605 }
5606
5607 if (dev->features & NETIF_F_RXALL)
5608 rx_mode |= (AcceptErr | AcceptRunt);
5609
5610 tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
5611
5612 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
5613 u32 data = mc_filter[0];
5614
5615 mc_filter[0] = swab32(mc_filter[1]);
5616 mc_filter[1] = swab32(data);
5617 }
5618
0481776b
NW		 5619 if (tp->mac_version == RTL_GIGA_MAC_VER_35)
5620 mc_filter[1] = mc_filter[0] = 0xffffffff;
5621
e6b763ea
FR		 5622 RTL_W32(MAR0 + 4, mc_filter[1]);
5623 RTL_W32(MAR0 + 0, mc_filter[0]);
5624
5625 RTL_W32(RxConfig, tmp);
5626}
5627
07ce4064
FR		 5628static void rtl_hw_start_8169(struct net_device *dev)
5629{
5630 struct rtl8169_private *tp = netdev_priv(dev);
5631 void __iomem *ioaddr = tp->mmio_addr;
5632 struct pci_dev *pdev = tp->pci_dev;
07ce4064 5633
9cb427b6
FR		 5634 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
5635 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
5636 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
5637 }
5638
1da177e4 5639 RTL_W8(Cfg9346, Cfg9346_Unlock);
cecb5fd7
FR		 5640 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
5641 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5642 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
5643 tp->mac_version == RTL_GIGA_MAC_VER_04)
9cb427b6
FR		 5644 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5645
e542a226
HW		 5646 rtl_init_rxcfg(tp);
5647
f0298f81 5648 RTL_W8(EarlyTxThres, NoEarlyTx);
1da177e4 5649
6f0333b8 5650 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
1da177e4 5651
cecb5fd7
FR		 5652 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
5653 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5654 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
5655 tp->mac_version == RTL_GIGA_MAC_VER_04)
c946b304 5656 rtl_set_rx_tx_config_registers(tp);
1da177e4 5657
7f796d83 5658 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 5659
cecb5fd7
FR		 5660 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5661 tp->mac_version == RTL_GIGA_MAC_VER_03) {
05b9687b 5662 dprintk("Set MAC Reg C+CR Offset 0xe0. "
1da177e4 5663 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 5664 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 5665 }
5666
bcf0bf90
FR		 5667 RTL_W16(CPlusCmd, tp->cp_cmd);
5668
6dccd16b
FR		 5669 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
5670
1da177e4
LT		 5671 /*
5672 * Undocumented corner. Supposedly:
5673 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
5674 */
5675 RTL_W16(IntrMitigate, 0x0000);
5676
7f796d83 5677 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 5678
cecb5fd7
FR		 5679 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
5680 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
5681 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
5682 tp->mac_version != RTL_GIGA_MAC_VER_04) {
c946b304
FR		 5683 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5684 rtl_set_rx_tx_config_registers(tp);
5685 }
5686
1da177e4 5687 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 5688
5689 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
5690 RTL_R8(IntrMask);
1da177e4
LT		 5691
5692 RTL_W32(RxMissed, 0);
5693
07ce4064 5694 rtl_set_rx_mode(dev);
1da177e4
LT		 5695
5696 /* no early-rx interrupts */
05b9687b 5697 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
07ce4064 5698}
1da177e4 5699
beb1fe18
HW		 5700static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
5701{
5702 if (tp->csi_ops.write)
52989f0e 5703 tp->csi_ops.write(tp, addr, value);
beb1fe18
HW		 5704}
5705
5706static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
5707{
52989f0e 5708 return tp->csi_ops.read ? tp->csi_ops.read(tp, addr) : ~0;
beb1fe18
HW		 5709}
5710
5711static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits)
dacf8154
FR		 5712{
5713 u32 csi;
5714
beb1fe18
HW		 5715 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
5716 rtl_csi_write(tp, 0x070c, csi | bits);
5717}
5718
5719static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
5720{
5721 rtl_csi_access_enable(tp, 0x17000000);
650e8d5d 5722}
5723
beb1fe18 5724static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
e6de30d6 5725{
beb1fe18 5726 rtl_csi_access_enable(tp, 0x27000000);
e6de30d6 5727}
5728
ffc46952
FR		 5729DECLARE_RTL_COND(rtl_csiar_cond)
5730{
5731 void __iomem *ioaddr = tp->mmio_addr;
5732
5733 return RTL_R32(CSIAR) & CSIAR_FLAG;
5734}
5735
52989f0e 5736static void r8169_csi_write(struct rtl8169_private *tp, int addr, int value)
650e8d5d 5737{
52989f0e 5738 void __iomem *ioaddr = tp->mmio_addr;
beb1fe18
HW		 5739
5740 RTL_W32(CSIDR, value);
5741 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5742 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5743
ffc46952 5744 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
beb1fe18
HW		 5745}
5746
52989f0e 5747static u32 r8169_csi_read(struct rtl8169_private *tp, int addr)
beb1fe18 5748{
52989f0e 5749 void __iomem *ioaddr = tp->mmio_addr;
beb1fe18
HW		 5750
5751 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
5752 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5753
ffc46952
FR		 5754 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5755 RTL_R32(CSIDR) : ~0;
beb1fe18
HW		 5756}
5757
52989f0e 5758static void r8402_csi_write(struct rtl8169_private *tp, int addr, int value)
7e18dca1 5759{
52989f0e 5760 void __iomem *ioaddr = tp->mmio_addr;
7e18dca1
HW		 5761
5762 RTL_W32(CSIDR, value);
5763 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5764 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
5765 CSIAR_FUNC_NIC);
5766
ffc46952 5767 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
7e18dca1
HW		 5768}
5769
52989f0e 5770static u32 r8402_csi_read(struct rtl8169_private *tp, int addr)
7e18dca1 5771{
52989f0e 5772 void __iomem *ioaddr = tp->mmio_addr;
7e18dca1
HW		 5773
5774 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
5775 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5776
ffc46952
FR		 5777 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5778 RTL_R32(CSIDR) : ~0;
7e18dca1
HW		 5779}
5780
45dd95c4 5781static void r8411_csi_write(struct rtl8169_private *tp, int addr, int value)
5782{
5783 void __iomem *ioaddr = tp->mmio_addr;
5784
5785 RTL_W32(CSIDR, value);
5786 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5787 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
5788 CSIAR_FUNC_NIC2);
5789
5790 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5791}
5792
5793static u32 r8411_csi_read(struct rtl8169_private *tp, int addr)
5794{
5795 void __iomem *ioaddr = tp->mmio_addr;
5796
5797 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC2 |
5798 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5799
5800 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5801 RTL_R32(CSIDR) : ~0;
5802}
5803
baf63293 5804static void rtl_init_csi_ops(struct rtl8169_private *tp)
beb1fe18
HW		 5805{
5806 struct csi_ops *ops = &tp->csi_ops;
5807
5808 switch (tp->mac_version) {
5809 case RTL_GIGA_MAC_VER_01:
5810 case RTL_GIGA_MAC_VER_02:
5811 case RTL_GIGA_MAC_VER_03:
5812 case RTL_GIGA_MAC_VER_04:
5813 case RTL_GIGA_MAC_VER_05:
5814 case RTL_GIGA_MAC_VER_06:
5815 case RTL_GIGA_MAC_VER_10:
5816 case RTL_GIGA_MAC_VER_11:
5817 case RTL_GIGA_MAC_VER_12:
5818 case RTL_GIGA_MAC_VER_13:
5819 case RTL_GIGA_MAC_VER_14:
5820 case RTL_GIGA_MAC_VER_15:
5821 case RTL_GIGA_MAC_VER_16:
5822 case RTL_GIGA_MAC_VER_17:
5823 ops->write = NULL;
5824 ops->read = NULL;
5825 break;
5826
7e18dca1 5827 case RTL_GIGA_MAC_VER_37:
b3d7b2f2 5828 case RTL_GIGA_MAC_VER_38:
7e18dca1
HW		 5829 ops->write = r8402_csi_write;
5830 ops->read = r8402_csi_read;
5831 break;
5832
45dd95c4 5833 case RTL_GIGA_MAC_VER_44:
5834 ops->write = r8411_csi_write;
5835 ops->read = r8411_csi_read;
5836 break;
5837
beb1fe18
HW		 5838 default:
5839 ops->write = r8169_csi_write;
5840 ops->read = r8169_csi_read;
5841 break;
5842 }
dacf8154
FR		 5843}
5844
5845struct ephy_info {
5846 unsigned int offset;
5847 u16 mask;
5848 u16 bits;
5849};
5850
fdf6fc06
FR		 5851static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
5852 int len)
dacf8154
FR		 5853{
5854 u16 w;
5855
5856 while (len-- > 0) {
fdf6fc06
FR		 5857 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
5858 rtl_ephy_write(tp, e->offset, w);
dacf8154
FR		 5859 e++;
5860 }
5861}
5862
b726e493
FR		 5863static void rtl_disable_clock_request(struct pci_dev *pdev)
5864{
7d7903b2
JL		 5865 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
5866 PCI_EXP_LNKCTL_CLKREQ_EN);
b726e493
FR		 5867}
5868
e6de30d6 5869static void rtl_enable_clock_request(struct pci_dev *pdev)
5870{
7d7903b2
JL		 5871 pcie_capability_set_word(pdev, PCI_EXP_LNKCTL,
5872 PCI_EXP_LNKCTL_CLKREQ_EN);
e6de30d6 5873}
5874
b51ecea8 5875static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable)
5876{
5877 void __iomem *ioaddr = tp->mmio_addr;
5878 u8 data;
5879
5880 data = RTL_R8(Config3);
5881
5882 if (enable)
5883 data |= Rdy_to_L23;
5884 else
5885 data &= ~Rdy_to_L23;
5886
5887 RTL_W8(Config3, data);
5888}
5889
b726e493
FR		 5890#define R8168_CPCMD_QUIRK_MASK (\
5891 EnableBist | \
5892 Mac_dbgo_oe | \
5893 Force_half_dup | \
5894 Force_rxflow_en | \
5895 Force_txflow_en | \
5896 Cxpl_dbg_sel | \
5897 ASF | \
5898 PktCntrDisable | \
5899 Mac_dbgo_sel)
5900
beb1fe18 5901static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
219a1e9d 5902{
beb1fe18
HW		 5903 void __iomem *ioaddr = tp->mmio_addr;
5904 struct pci_dev *pdev = tp->pci_dev;
5905
b726e493
FR		 5906 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5907
5908 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5909
faf1e785 5910 if (tp->dev->mtu <= ETH_DATA_LEN) {
5911 rtl_tx_performance_tweak(pdev, (0x5 << MAX_READ_REQUEST_SHIFT) |
5912 PCI_EXP_DEVCTL_NOSNOOP_EN);
5913 }
219a1e9d
FR		 5914}
5915
beb1fe18 5916static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
219a1e9d 5917{
beb1fe18
HW		 5918 void __iomem *ioaddr = tp->mmio_addr;
5919
5920 rtl_hw_start_8168bb(tp);
b726e493 5921
f0298f81 5922 RTL_W8(MaxTxPacketSize, TxPacketMax);
b726e493
FR		 5923
5924 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
219a1e9d
FR		 5925}
5926
beb1fe18 5927static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
219a1e9d 5928{
beb1fe18
HW		 5929 void __iomem *ioaddr = tp->mmio_addr;
5930 struct pci_dev *pdev = tp->pci_dev;
5931
b726e493
FR		 5932 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
5933
5934 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5935
faf1e785 5936 if (tp->dev->mtu <= ETH_DATA_LEN)
5937 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
b726e493
FR		 5938
5939 rtl_disable_clock_request(pdev);
5940
5941 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
219a1e9d
FR		 5942}
5943
beb1fe18 5944static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
219a1e9d 5945{
350f7596 5946 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 5947 { 0x01, 0, 0x0001 },
5948 { 0x02, 0x0800, 0x1000 },
5949 { 0x03, 0, 0x0042 },
5950 { 0x06, 0x0080, 0x0000 },
5951 { 0x07, 0, 0x2000 }
5952 };
5953
beb1fe18 5954 rtl_csi_access_enable_2(tp);
b726e493 5955
fdf6fc06 5956 rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
b726e493 5957
beb1fe18 5958 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 5959}
5960
beb1fe18 5961static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
ef3386f0 5962{
beb1fe18
HW		 5963 void __iomem *ioaddr = tp->mmio_addr;
5964 struct pci_dev *pdev = tp->pci_dev;
5965
5966 rtl_csi_access_enable_2(tp);
ef3386f0
FR		 5967
5968 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5969
faf1e785 5970 if (tp->dev->mtu <= ETH_DATA_LEN)
5971 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
ef3386f0
FR		 5972
5973 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5974}
5975
beb1fe18 5976static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
7f3e3d3a 5977{
beb1fe18
HW		 5978 void __iomem *ioaddr = tp->mmio_addr;
5979 struct pci_dev *pdev = tp->pci_dev;
5980
5981 rtl_csi_access_enable_2(tp);
7f3e3d3a
FR		 5982
5983 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5984
5985 /* Magic. */
5986 RTL_W8(DBG_REG, 0x20);
5987
f0298f81 5988 RTL_W8(MaxTxPacketSize, TxPacketMax);
7f3e3d3a 5989
faf1e785 5990 if (tp->dev->mtu <= ETH_DATA_LEN)
5991 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
7f3e3d3a
FR		 5992
5993 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5994}
5995
beb1fe18 5996static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
219a1e9d 5997{
beb1fe18 5998 void __iomem *ioaddr = tp->mmio_addr;
350f7596 5999 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 6000 { 0x02, 0x0800, 0x1000 },
6001 { 0x03, 0, 0x0002 },
6002 { 0x06, 0x0080, 0x0000 }
6003 };
6004
beb1fe18 6005 rtl_csi_access_enable_2(tp);
b726e493
FR		 6006
6007 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
6008
fdf6fc06 6009 rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
b726e493 6010
beb1fe18 6011 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 6012}
6013
beb1fe18 6014static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
219a1e9d 6015{
350f7596 6016 static const struct ephy_info e_info_8168c_2[] = {
b726e493
FR		 6017 { 0x01, 0, 0x0001 },
6018 { 0x03, 0x0400, 0x0220 }
6019 };
6020
beb1fe18 6021 rtl_csi_access_enable_2(tp);
b726e493 6022
fdf6fc06 6023 rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
b726e493 6024
beb1fe18 6025 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 6026}
6027
beb1fe18 6028static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
197ff761 6029{
beb1fe18 6030 rtl_hw_start_8168c_2(tp);
197ff761
FR		 6031}
6032
beb1fe18 6033static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
6fb07058 6034{
beb1fe18 6035 rtl_csi_access_enable_2(tp);
6fb07058 6036
beb1fe18 6037 __rtl_hw_start_8168cp(tp);
6fb07058
FR		 6038}
6039
beb1fe18 6040static void rtl_hw_start_8168d(struct rtl8169_private *tp)
5b538df9 6041{
beb1fe18
HW		 6042 void __iomem *ioaddr = tp->mmio_addr;
6043 struct pci_dev *pdev = tp->pci_dev;
6044
6045 rtl_csi_access_enable_2(tp);
5b538df9
FR		 6046
6047 rtl_disable_clock_request(pdev);
6048
f0298f81 6049 RTL_W8(MaxTxPacketSize, TxPacketMax);
5b538df9 6050
faf1e785 6051 if (tp->dev->mtu <= ETH_DATA_LEN)
6052 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5b538df9
FR		 6053
6054 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
6055}
6056
beb1fe18 6057static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4804b3b3 6058{
beb1fe18
HW		 6059 void __iomem *ioaddr = tp->mmio_addr;
6060 struct pci_dev *pdev = tp->pci_dev;
6061
6062 rtl_csi_access_enable_1(tp);
4804b3b3 6063
faf1e785 6064 if (tp->dev->mtu <= ETH_DATA_LEN)
6065 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4804b3b3 6066
6067 RTL_W8(MaxTxPacketSize, TxPacketMax);
6068
6069 rtl_disable_clock_request(pdev);
6070}
6071
beb1fe18 6072static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
e6de30d6 6073{
beb1fe18
HW		 6074 void __iomem *ioaddr = tp->mmio_addr;
6075 struct pci_dev *pdev = tp->pci_dev;
e6de30d6 6076 static const struct ephy_info e_info_8168d_4[] = {
1016a4a1
CHL		 6077 { 0x0b, 0x0000, 0x0048 },
6078 { 0x19, 0x0020, 0x0050 },
6079 { 0x0c, 0x0100, 0x0020 }
e6de30d6 6080 };
e6de30d6 6081
beb1fe18 6082 rtl_csi_access_enable_1(tp);
e6de30d6 6083
6084 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6085
6086 RTL_W8(MaxTxPacketSize, TxPacketMax);
6087
1016a4a1 6088 rtl_ephy_init(tp, e_info_8168d_4, ARRAY_SIZE(e_info_8168d_4));
e6de30d6 6089
6090 rtl_enable_clock_request(pdev);
6091}
6092
beb1fe18 6093static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
01dc7fec 6094{
beb1fe18
HW		 6095 void __iomem *ioaddr = tp->mmio_addr;
6096 struct pci_dev *pdev = tp->pci_dev;
70090424 6097 static const struct ephy_info e_info_8168e_1[] = {
01dc7fec 6098 { 0x00, 0x0200, 0x0100 },
6099 { 0x00, 0x0000, 0x0004 },
6100 { 0x06, 0x0002, 0x0001 },
6101 { 0x06, 0x0000, 0x0030 },
6102 { 0x07, 0x0000, 0x2000 },
6103 { 0x00, 0x0000, 0x0020 },
6104 { 0x03, 0x5800, 0x2000 },
6105 { 0x03, 0x0000, 0x0001 },
6106 { 0x01, 0x0800, 0x1000 },
6107 { 0x07, 0x0000, 0x4000 },
6108 { 0x1e, 0x0000, 0x2000 },
6109 { 0x19, 0xffff, 0xfe6c },
6110 { 0x0a, 0x0000, 0x0040 }
6111 };
6112
beb1fe18 6113 rtl_csi_access_enable_2(tp);
01dc7fec 6114
fdf6fc06 6115 rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
01dc7fec 6116
faf1e785 6117 if (tp->dev->mtu <= ETH_DATA_LEN)
6118 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
01dc7fec 6119
6120 RTL_W8(MaxTxPacketSize, TxPacketMax);
6121
6122 rtl_disable_clock_request(pdev);
6123
6124 /* Reset tx FIFO pointer */
cecb5fd7
FR		 6125 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
6126 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
01dc7fec 6127
cecb5fd7 6128 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
01dc7fec 6129}
6130
beb1fe18 6131static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
70090424 6132{
beb1fe18
HW		 6133 void __iomem *ioaddr = tp->mmio_addr;
6134 struct pci_dev *pdev = tp->pci_dev;
70090424
HW		 6135 static const struct ephy_info e_info_8168e_2[] = {
6136 { 0x09, 0x0000, 0x0080 },
6137 { 0x19, 0x0000, 0x0224 }
6138 };
6139
beb1fe18 6140 rtl_csi_access_enable_1(tp);
70090424 6141
fdf6fc06 6142 rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
70090424 6143
faf1e785 6144 if (tp->dev->mtu <= ETH_DATA_LEN)
6145 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
70090424 6146
fdf6fc06
FR		 6147 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6148 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6149 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
6150 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6151 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
6152 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
706123d0
CHL		 6153 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
6154 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
70090424 6155
3090bd9a 6156 RTL_W8(MaxTxPacketSize, EarlySize);
70090424 6157
4521e1a9
FR		 6158 rtl_disable_clock_request(pdev);
6159
70090424
HW		 6160 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6161 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
6162
6163 /* Adjust EEE LED frequency */
6164 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6165
6166 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
6167 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4521e1a9 6168 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
70090424
HW		 6169}
6170
5f886e08 6171static void rtl_hw_start_8168f(struct rtl8169_private *tp)
c2218925 6172{
beb1fe18
HW		 6173 void __iomem *ioaddr = tp->mmio_addr;
6174 struct pci_dev *pdev = tp->pci_dev;
c2218925 6175
5f886e08 6176 rtl_csi_access_enable_2(tp);
c2218925
HW		 6177
6178 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6179
fdf6fc06
FR		 6180 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6181 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6182 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
6183 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
706123d0
CHL		 6184 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6185 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6186 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
6187 rtl_w0w1_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
fdf6fc06
FR		 6188 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
6189 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
c2218925
HW		 6190
6191 RTL_W8(MaxTxPacketSize, EarlySize);
6192
4521e1a9
FR		 6193 rtl_disable_clock_request(pdev);
6194
c2218925
HW		 6195 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6196 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
c2218925 6197 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4521e1a9
FR		 6198 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
6199 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
c2218925
HW		 6200}
6201
5f886e08
HW		 6202static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
6203{
6204 void __iomem *ioaddr = tp->mmio_addr;
6205 static const struct ephy_info e_info_8168f_1[] = {
6206 { 0x06, 0x00c0, 0x0020 },
6207 { 0x08, 0x0001, 0x0002 },
6208 { 0x09, 0x0000, 0x0080 },
6209 { 0x19, 0x0000, 0x0224 }
6210 };
6211
6212 rtl_hw_start_8168f(tp);
6213
fdf6fc06 6214 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5f886e08 6215
706123d0 6216 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5f886e08
HW		 6217
6218 /* Adjust EEE LED frequency */
6219 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6220}
6221
b3d7b2f2
HW		 6222static void rtl_hw_start_8411(struct rtl8169_private *tp)
6223{
b3d7b2f2
HW		 6224 static const struct ephy_info e_info_8168f_1[] = {
6225 { 0x06, 0x00c0, 0x0020 },
6226 { 0x0f, 0xffff, 0x5200 },
6227 { 0x1e, 0x0000, 0x4000 },
6228 { 0x19, 0x0000, 0x0224 }
6229 };
6230
6231 rtl_hw_start_8168f(tp);
b51ecea8 6232 rtl_pcie_state_l2l3_enable(tp, false);
b3d7b2f2 6233
fdf6fc06 6234 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
b3d7b2f2 6235
706123d0 6236 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
b3d7b2f2
HW		 6237}
6238
5fbea337 6239static void rtl_hw_start_8168g(struct rtl8169_private *tp)
c558386b
HW		 6240{
6241 void __iomem *ioaddr = tp->mmio_addr;
6242 struct pci_dev *pdev = tp->pci_dev;
6243
beb330a4 6244 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6245
c558386b
HW		 6246 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
6247 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
6248 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
6249 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6250
6251 rtl_csi_access_enable_1(tp);
6252
6253 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6254
706123d0
CHL		 6255 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6256 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
beb330a4 6257 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
c558386b 6258
4521e1a9 6259 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
c558386b
HW		 6260 RTL_W8(MaxTxPacketSize, EarlySize);
6261
6262 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6263 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6264
6265 /* Adjust EEE LED frequency */
6266 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6267
706123d0
CHL		 6268 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
6269 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
b51ecea8 6270
6271 rtl_pcie_state_l2l3_enable(tp, false);
c558386b
HW		 6272}
6273
5fbea337
CHL		 6274static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
6275{
6276 void __iomem *ioaddr = tp->mmio_addr;
6277 static const struct ephy_info e_info_8168g_1[] = {
6278 { 0x00, 0x0000, 0x0008 },
6279 { 0x0c, 0x37d0, 0x0820 },
6280 { 0x1e, 0x0000, 0x0001 },
6281 { 0x19, 0x8000, 0x0000 }
6282 };
6283
6284 rtl_hw_start_8168g(tp);
6285
6286 /* disable aspm and clock request before access ephy */
6287 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6288 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6289 rtl_ephy_init(tp, e_info_8168g_1, ARRAY_SIZE(e_info_8168g_1));
6290}
6291
57538c4a 6292static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
6293{
6294 void __iomem *ioaddr = tp->mmio_addr;
6295 static const struct ephy_info e_info_8168g_2[] = {
6296 { 0x00, 0x0000, 0x0008 },
6297 { 0x0c, 0x3df0, 0x0200 },
6298 { 0x19, 0xffff, 0xfc00 },
6299 { 0x1e, 0xffff, 0x20eb }
6300 };
6301
5fbea337 6302 rtl_hw_start_8168g(tp);
57538c4a 6303
6304 /* disable aspm and clock request before access ephy */
6305 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6306 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6307 rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
6308}
6309
45dd95c4 6310static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
6311{
6312 void __iomem *ioaddr = tp->mmio_addr;
6313 static const struct ephy_info e_info_8411_2[] = {
6314 { 0x00, 0x0000, 0x0008 },
6315 { 0x0c, 0x3df0, 0x0200 },
6316 { 0x0f, 0xffff, 0x5200 },
6317 { 0x19, 0x0020, 0x0000 },
6318 { 0x1e, 0x0000, 0x2000 }
6319 };
6320
5fbea337 6321 rtl_hw_start_8168g(tp);
45dd95c4 6322
6323 /* disable aspm and clock request before access ephy */
6324 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6325 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6326 rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
6327}
6328
6e1d0b89
CHL		 6329static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
6330{
6331 void __iomem *ioaddr = tp->mmio_addr;
6332 struct pci_dev *pdev = tp->pci_dev;
72521ea0 6333 int rg_saw_cnt;
6e1d0b89
CHL		 6334 u32 data;
6335 static const struct ephy_info e_info_8168h_1[] = {
6336 { 0x1e, 0x0800, 0x0001 },
6337 { 0x1d, 0x0000, 0x0800 },
6338 { 0x05, 0xffff, 0x2089 },
6339 { 0x06, 0xffff, 0x5881 },
6340 { 0x04, 0xffff, 0x154a },
6341 { 0x01, 0xffff, 0x068b }
6342 };
6343
6344 /* disable aspm and clock request before access ephy */
6345 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6346 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6347 rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));
6348
6349 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6350
6351 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
6352 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
6353 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
6354 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6355
6356 rtl_csi_access_enable_1(tp);
6357
6358 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6359
706123d0
CHL		 6360 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6361 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6e1d0b89 6362
706123d0 6363 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);
6e1d0b89 6364
706123d0 6365 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);
6e1d0b89
CHL		 6366
6367 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
6368
6e1d0b89
CHL		 6369 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
6370 RTL_W8(MaxTxPacketSize, EarlySize);
6371
6372 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6373 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6374
6375 /* Adjust EEE LED frequency */
6376 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6377
6378 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
69f3dc37 6379 RTL_W8(MISC_1, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
6e1d0b89
CHL		 6380
6381 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~TX_10M_PS_EN);
6382
706123d0 6383 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
6e1d0b89
CHL		 6384
6385 rtl_pcie_state_l2l3_enable(tp, false);
6386
6387 rtl_writephy(tp, 0x1f, 0x0c42);
58493333 6388 rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
6e1d0b89
CHL		 6389 rtl_writephy(tp, 0x1f, 0x0000);
6390 if (rg_saw_cnt > 0) {
6391 u16 sw_cnt_1ms_ini;
6392
6393 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
6394 sw_cnt_1ms_ini &= 0x0fff;
6395 data = r8168_mac_ocp_read(tp, 0xd412);
a2cb7ec0 6396 data &= ~0x0fff;
6e1d0b89
CHL		 6397 data |= sw_cnt_1ms_ini;
6398 r8168_mac_ocp_write(tp, 0xd412, data);
6399 }
6400
6401 data = r8168_mac_ocp_read(tp, 0xe056);
a2cb7ec0
CHL		 6402 data &= ~0xf0;
6403 data |= 0x70;
6e1d0b89
CHL		 6404 r8168_mac_ocp_write(tp, 0xe056, data);
6405
6406 data = r8168_mac_ocp_read(tp, 0xe052);
a2cb7ec0
CHL		 6407 data &= ~0x6000;
6408 data |= 0x8008;
6e1d0b89
CHL		 6409 r8168_mac_ocp_write(tp, 0xe052, data);
6410
6411 data = r8168_mac_ocp_read(tp, 0xe0d6);
a2cb7ec0 6412 data &= ~0x01ff;
6e1d0b89
CHL		 6413 data |= 0x017f;
6414 r8168_mac_ocp_write(tp, 0xe0d6, data);
6415
6416 data = r8168_mac_ocp_read(tp, 0xd420);
a2cb7ec0 6417 data &= ~0x0fff;
6e1d0b89
CHL		 6418 data |= 0x047f;
6419 r8168_mac_ocp_write(tp, 0xd420, data);
6420
6421 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
6422 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
6423 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
6424 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
6425}
6426
935e2218
CHL		 6427static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
6428{
6429 void __iomem *ioaddr = tp->mmio_addr;
6430 struct pci_dev *pdev = tp->pci_dev;
6431
003609da
CHL		 6432 rtl8168ep_stop_cmac(tp);
6433
935e2218
CHL		 6434 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6435
6436 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
6437 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x2f, ERIAR_EXGMAC);
6438 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x5f, ERIAR_EXGMAC);
6439 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6440
6441 rtl_csi_access_enable_1(tp);
6442
6443 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6444
6445 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6446 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6447
6448 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f80, 0x00, ERIAR_EXGMAC);
6449
6450 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
6451
935e2218
CHL		 6452 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
6453 RTL_W8(MaxTxPacketSize, EarlySize);
6454
6455 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6456 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6457
6458 /* Adjust EEE LED frequency */
6459 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6460
6461 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
6462
6463 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~TX_10M_PS_EN);
6464
6465 rtl_pcie_state_l2l3_enable(tp, false);
6466}
6467
6468static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
6469{
6470 void __iomem *ioaddr = tp->mmio_addr;
6471 static const struct ephy_info e_info_8168ep_1[] = {
6472 { 0x00, 0xffff, 0x10ab },
6473 { 0x06, 0xffff, 0xf030 },
6474 { 0x08, 0xffff, 0x2006 },
6475 { 0x0d, 0xffff, 0x1666 },
6476 { 0x0c, 0x3ff0, 0x0000 }
6477 };
6478
6479 /* disable aspm and clock request before access ephy */
6480 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6481 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6482 rtl_ephy_init(tp, e_info_8168ep_1, ARRAY_SIZE(e_info_8168ep_1));
6483
6484 rtl_hw_start_8168ep(tp);
6485}
6486
6487static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
6488{
6489 void __iomem *ioaddr = tp->mmio_addr;
6490 static const struct ephy_info e_info_8168ep_2[] = {
6491 { 0x00, 0xffff, 0x10a3 },
6492 { 0x19, 0xffff, 0xfc00 },
6493 { 0x1e, 0xffff, 0x20ea }
6494 };
6495
6496 /* disable aspm and clock request before access ephy */
6497 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6498 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6499 rtl_ephy_init(tp, e_info_8168ep_2, ARRAY_SIZE(e_info_8168ep_2));
6500
6501 rtl_hw_start_8168ep(tp);
6502
6503 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
69f3dc37 6504 RTL_W8(MISC_1, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
935e2218
CHL		 6505}
6506
6507static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
6508{
6509 void __iomem *ioaddr = tp->mmio_addr;
6510 u32 data;
6511 static const struct ephy_info e_info_8168ep_3[] = {
6512 { 0x00, 0xffff, 0x10a3 },
6513 { 0x19, 0xffff, 0x7c00 },
6514 { 0x1e, 0xffff, 0x20eb },
6515 { 0x0d, 0xffff, 0x1666 }
6516 };
6517
6518 /* disable aspm and clock request before access ephy */
6519 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6520 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6521 rtl_ephy_init(tp, e_info_8168ep_3, ARRAY_SIZE(e_info_8168ep_3));
6522
6523 rtl_hw_start_8168ep(tp);
6524
6525 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
69f3dc37 6526 RTL_W8(MISC_1, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
935e2218
CHL		 6527
6528 data = r8168_mac_ocp_read(tp, 0xd3e2);
6529 data &= 0xf000;
6530 data |= 0x0271;
6531 r8168_mac_ocp_write(tp, 0xd3e2, data);
6532
6533 data = r8168_mac_ocp_read(tp, 0xd3e4);
6534 data &= 0xff00;
6535 r8168_mac_ocp_write(tp, 0xd3e4, data);
6536
6537 data = r8168_mac_ocp_read(tp, 0xe860);
6538 data |= 0x0080;
6539 r8168_mac_ocp_write(tp, 0xe860, data);
6540}
6541
07ce4064
FR		 6542static void rtl_hw_start_8168(struct net_device *dev)
6543{
2dd99530
FR		 6544 struct rtl8169_private *tp = netdev_priv(dev);
6545 void __iomem *ioaddr = tp->mmio_addr;
6546
6547 RTL_W8(Cfg9346, Cfg9346_Unlock);
6548
f0298f81 6549 RTL_W8(MaxTxPacketSize, TxPacketMax);
2dd99530 6550
6f0333b8 6551 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
2dd99530 6552
0e485150 6553 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 6554
6555 RTL_W16(CPlusCmd, tp->cp_cmd);
6556
09e294f6 6557 RTL_W16(IntrMitigate, 0x5100);
2dd99530 6558
0e485150 6559 /* Work around for RxFIFO overflow. */
811fd301 6560 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
da78dbff
FR		 6561 tp->event_slow |= RxFIFOOver | PCSTimeout;
6562 tp->event_slow &= ~RxOverflow;
0e485150
FR		 6563 }
6564
6565 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530 6566
1a964649 6567 rtl_set_rx_tx_config_registers(tp);
2dd99530
FR		 6568
6569 RTL_R8(IntrMask);
6570
219a1e9d
FR		 6571 switch (tp->mac_version) {
6572 case RTL_GIGA_MAC_VER_11:
beb1fe18 6573 rtl_hw_start_8168bb(tp);
4804b3b3 6574 break;
219a1e9d
FR		 6575
6576 case RTL_GIGA_MAC_VER_12:
6577 case RTL_GIGA_MAC_VER_17:
beb1fe18 6578 rtl_hw_start_8168bef(tp);
4804b3b3 6579 break;
219a1e9d
FR		 6580
6581 case RTL_GIGA_MAC_VER_18:
beb1fe18 6582 rtl_hw_start_8168cp_1(tp);
4804b3b3 6583 break;
219a1e9d
FR		 6584
6585 case RTL_GIGA_MAC_VER_19:
beb1fe18 6586 rtl_hw_start_8168c_1(tp);
4804b3b3 6587 break;
219a1e9d
FR		 6588
6589 case RTL_GIGA_MAC_VER_20:
beb1fe18 6590 rtl_hw_start_8168c_2(tp);
4804b3b3 6591 break;
219a1e9d 6592
197ff761 6593 case RTL_GIGA_MAC_VER_21:
beb1fe18 6594 rtl_hw_start_8168c_3(tp);
4804b3b3 6595 break;
197ff761 6596
6fb07058 6597 case RTL_GIGA_MAC_VER_22:
beb1fe18 6598 rtl_hw_start_8168c_4(tp);
4804b3b3 6599 break;
6fb07058 6600
ef3386f0 6601 case RTL_GIGA_MAC_VER_23:
beb1fe18 6602 rtl_hw_start_8168cp_2(tp);
4804b3b3 6603 break;
ef3386f0 6604
7f3e3d3a 6605 case RTL_GIGA_MAC_VER_24:
beb1fe18 6606 rtl_hw_start_8168cp_3(tp);
4804b3b3 6607 break;
7f3e3d3a 6608
5b538df9 6609 case RTL_GIGA_MAC_VER_25:
daf9df6d 6610 case RTL_GIGA_MAC_VER_26:
6611 case RTL_GIGA_MAC_VER_27:
beb1fe18 6612 rtl_hw_start_8168d(tp);
4804b3b3 6613 break;
5b538df9 6614
e6de30d6 6615 case RTL_GIGA_MAC_VER_28:
beb1fe18 6616 rtl_hw_start_8168d_4(tp);
4804b3b3 6617 break;
cecb5fd7 6618
4804b3b3 6619 case RTL_GIGA_MAC_VER_31:
beb1fe18 6620 rtl_hw_start_8168dp(tp);
4804b3b3 6621 break;
6622
01dc7fec 6623 case RTL_GIGA_MAC_VER_32:
6624 case RTL_GIGA_MAC_VER_33:
beb1fe18 6625 rtl_hw_start_8168e_1(tp);
70090424
HW		 6626 break;
6627 case RTL_GIGA_MAC_VER_34:
beb1fe18 6628 rtl_hw_start_8168e_2(tp);
01dc7fec 6629 break;
e6de30d6 6630
c2218925
HW		 6631 case RTL_GIGA_MAC_VER_35:
6632 case RTL_GIGA_MAC_VER_36:
beb1fe18 6633 rtl_hw_start_8168f_1(tp);
c2218925
HW		 6634 break;
6635
b3d7b2f2
HW		 6636 case RTL_GIGA_MAC_VER_38:
6637 rtl_hw_start_8411(tp);
6638 break;
6639
c558386b
HW		 6640 case RTL_GIGA_MAC_VER_40:
6641 case RTL_GIGA_MAC_VER_41:
6642 rtl_hw_start_8168g_1(tp);
6643 break;
57538c4a 6644 case RTL_GIGA_MAC_VER_42:
6645 rtl_hw_start_8168g_2(tp);
6646 break;
c558386b 6647
45dd95c4 6648 case RTL_GIGA_MAC_VER_44:
6649 rtl_hw_start_8411_2(tp);
6650 break;
6651
6e1d0b89
CHL		 6652 case RTL_GIGA_MAC_VER_45:
6653 case RTL_GIGA_MAC_VER_46:
6654 rtl_hw_start_8168h_1(tp);
6655 break;
6656
935e2218
CHL		 6657 case RTL_GIGA_MAC_VER_49:
6658 rtl_hw_start_8168ep_1(tp);
6659 break;
6660
6661 case RTL_GIGA_MAC_VER_50:
6662 rtl_hw_start_8168ep_2(tp);
6663 break;
6664
6665 case RTL_GIGA_MAC_VER_51:
6666 rtl_hw_start_8168ep_3(tp);
6667 break;
6668
219a1e9d
FR		 6669 default:
6670 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
6671 dev->name, tp->mac_version);
4804b3b3 6672 break;
219a1e9d 6673 }
2dd99530 6674
1a964649 6675 RTL_W8(Cfg9346, Cfg9346_Lock);
6676
0e485150
FR		 6677 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
6678
1a964649 6679 rtl_set_rx_mode(dev);
b8363901 6680
05b9687b 6681 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
07ce4064 6682}
1da177e4 6683
2857ffb7
FR		 6684#define R810X_CPCMD_QUIRK_MASK (\
6685 EnableBist | \
6686 Mac_dbgo_oe | \
6687 Force_half_dup | \
5edcc537 6688 Force_rxflow_en | \
2857ffb7
FR		 6689 Force_txflow_en | \
6690 Cxpl_dbg_sel | \
6691 ASF | \
6692 PktCntrDisable | \
d24e9aaf 6693 Mac_dbgo_sel)
2857ffb7 6694
beb1fe18 6695static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
2857ffb7 6696{
beb1fe18
HW		 6697 void __iomem *ioaddr = tp->mmio_addr;
6698 struct pci_dev *pdev = tp->pci_dev;
350f7596 6699 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 6700 { 0x01, 0, 0x6e65 },
6701 { 0x02, 0, 0x091f },
6702 { 0x03, 0, 0xc2f9 },
6703 { 0x06, 0, 0xafb5 },
6704 { 0x07, 0, 0x0e00 },
6705 { 0x19, 0, 0xec80 },
6706 { 0x01, 0, 0x2e65 },
6707 { 0x01, 0, 0x6e65 }
6708 };
6709 u8 cfg1;
6710
beb1fe18 6711 rtl_csi_access_enable_2(tp);
2857ffb7
FR		 6712
6713 RTL_W8(DBG_REG, FIX_NAK_1);
6714
6715 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6716
6717 RTL_W8(Config1,
6718 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
6719 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
6720
6721 cfg1 = RTL_R8(Config1);
6722 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
6723 RTL_W8(Config1, cfg1 & ~LEDS0);
6724
fdf6fc06 6725 rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
2857ffb7
FR		 6726}
6727
beb1fe18 6728static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
2857ffb7 6729{
beb1fe18
HW		 6730 void __iomem *ioaddr = tp->mmio_addr;
6731 struct pci_dev *pdev = tp->pci_dev;
6732
6733 rtl_csi_access_enable_2(tp);
2857ffb7
FR		 6734
6735 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6736
6737 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
6738 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2857ffb7
FR		 6739}
6740
beb1fe18 6741static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
2857ffb7 6742{
beb1fe18 6743 rtl_hw_start_8102e_2(tp);
2857ffb7 6744
fdf6fc06 6745 rtl_ephy_write(tp, 0x03, 0xc2f9);
2857ffb7
FR		 6746}
6747
beb1fe18 6748static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5a5e4443 6749{
beb1fe18 6750 void __iomem *ioaddr = tp->mmio_addr;
5a5e4443
HW		 6751 static const struct ephy_info e_info_8105e_1[] = {
6752 { 0x07, 0, 0x4000 },
6753 { 0x19, 0, 0x0200 },
6754 { 0x19, 0, 0x0020 },
6755 { 0x1e, 0, 0x2000 },
6756 { 0x03, 0, 0x0001 },
6757 { 0x19, 0, 0x0100 },
6758 { 0x19, 0, 0x0004 },
6759 { 0x0a, 0, 0x0020 }
6760 };
6761
cecb5fd7 6762 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5a5e4443
HW		 6763 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6764
cecb5fd7 6765 /* Disable Early Tally Counter */
5a5e4443
HW		 6766 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
6767
6768 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4f6b00e5 6769 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5a5e4443 6770
fdf6fc06 6771 rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
b51ecea8 6772
6773 rtl_pcie_state_l2l3_enable(tp, false);
5a5e4443
HW		 6774}
6775
beb1fe18 6776static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5a5e4443 6777{
beb1fe18 6778 rtl_hw_start_8105e_1(tp);
fdf6fc06 6779 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5a5e4443
HW		 6780}
6781
7e18dca1
HW		 6782static void rtl_hw_start_8402(struct rtl8169_private *tp)
6783{
6784 void __iomem *ioaddr = tp->mmio_addr;
6785 static const struct ephy_info e_info_8402[] = {
6786 { 0x19, 0xffff, 0xff64 },
6787 { 0x1e, 0, 0x4000 }
6788 };
6789
6790 rtl_csi_access_enable_2(tp);
6791
6792 /* Force LAN exit from ASPM if Rx/Tx are not idle */
6793 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6794
6795 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6796 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
6797
fdf6fc06 6798 rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
7e18dca1
HW		 6799
6800 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
6801
fdf6fc06
FR		 6802 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
6803 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
706123d0
CHL		 6804 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6805 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
fdf6fc06
FR		 6806 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6807 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
706123d0 6808 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
b51ecea8 6809
6810 rtl_pcie_state_l2l3_enable(tp, false);
7e18dca1
HW		 6811}
6812
5598bfe5
HW		 6813static void rtl_hw_start_8106(struct rtl8169_private *tp)
6814{
6815 void __iomem *ioaddr = tp->mmio_addr;
6816
6817 /* Force LAN exit from ASPM if Rx/Tx are not idle */
6818 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6819
4521e1a9 6820 RTL_W32(MISC, (RTL_R32(MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5598bfe5
HW		 6821 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
6822 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
b51ecea8 6823
6824 rtl_pcie_state_l2l3_enable(tp, false);
5598bfe5
HW		 6825}
6826
07ce4064
FR		 6827static void rtl_hw_start_8101(struct net_device *dev)
6828{
cdf1a608
FR		 6829 struct rtl8169_private *tp = netdev_priv(dev);
6830 void __iomem *ioaddr = tp->mmio_addr;
6831 struct pci_dev *pdev = tp->pci_dev;
6832
da78dbff
FR		 6833 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
6834 tp->event_slow &= ~RxFIFOOver;
811fd301 6835
cecb5fd7 6836 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
7d7903b2 6837 tp->mac_version == RTL_GIGA_MAC_VER_16)
8200bc72
BH		 6838 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL,
6839 PCI_EXP_DEVCTL_NOSNOOP_EN);
cdf1a608 6840
d24e9aaf
HW		 6841 RTL_W8(Cfg9346, Cfg9346_Unlock);
6842
1a964649 6843 RTL_W8(MaxTxPacketSize, TxPacketMax);
6844
6845 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
6846
6847 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
6848 RTL_W16(CPlusCmd, tp->cp_cmd);
6849
6850 rtl_set_rx_tx_desc_registers(tp, ioaddr);
6851
6852 rtl_set_rx_tx_config_registers(tp);
6853
2857ffb7
FR		 6854 switch (tp->mac_version) {
6855 case RTL_GIGA_MAC_VER_07:
beb1fe18 6856 rtl_hw_start_8102e_1(tp);
2857ffb7
FR		 6857 break;
6858
6859 case RTL_GIGA_MAC_VER_08:
beb1fe18 6860 rtl_hw_start_8102e_3(tp);
2857ffb7
FR		 6861 break;
6862
6863 case RTL_GIGA_MAC_VER_09:
beb1fe18 6864 rtl_hw_start_8102e_2(tp);
2857ffb7 6865 break;
5a5e4443
HW		 6866
6867 case RTL_GIGA_MAC_VER_29:
beb1fe18 6868 rtl_hw_start_8105e_1(tp);
5a5e4443
HW		 6869 break;
6870 case RTL_GIGA_MAC_VER_30:
beb1fe18 6871 rtl_hw_start_8105e_2(tp);
5a5e4443 6872 break;
7e18dca1
HW		 6873
6874 case RTL_GIGA_MAC_VER_37:
6875 rtl_hw_start_8402(tp);
6876 break;
5598bfe5
HW		 6877
6878 case RTL_GIGA_MAC_VER_39:
6879 rtl_hw_start_8106(tp);
6880 break;
58152cd4 6881 case RTL_GIGA_MAC_VER_43:
6882 rtl_hw_start_8168g_2(tp);
6883 break;
6e1d0b89
CHL		 6884 case RTL_GIGA_MAC_VER_47:
6885 case RTL_GIGA_MAC_VER_48:
6886 rtl_hw_start_8168h_1(tp);
6887 break;
cdf1a608
FR		 6888 }
6889
d24e9aaf 6890 RTL_W8(Cfg9346, Cfg9346_Lock);
cdf1a608 6891
cdf1a608
FR		 6892 RTL_W16(IntrMitigate, 0x0000);
6893
cdf1a608 6894 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
cdf1a608 6895
cdf1a608
FR		 6896 rtl_set_rx_mode(dev);
6897
1a964649 6898 RTL_R8(IntrMask);
6899
cdf1a608 6900 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
1da177e4
LT		 6901}
6902
6903static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
6904{
d58d46b5
FR		 6905 struct rtl8169_private *tp = netdev_priv(dev);
6906
d58d46b5
FR		 6907 if (new_mtu > ETH_DATA_LEN)
6908 rtl_hw_jumbo_enable(tp);
6909 else
6910 rtl_hw_jumbo_disable(tp);
6911
1da177e4 6912 dev->mtu = new_mtu;
350fb32a
MM		 6913 netdev_update_features(dev);
6914
323bb685 6915 return 0;
1da177e4
LT		 6916}
6917
6918static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
6919{
95e0918d 6920 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 6921 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
6922}
6923
6f0333b8
ED		 6924static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
6925 void **data_buff, struct RxDesc *desc)
1da177e4 6926{
48addcc9 6927 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
231aee63 6928 DMA_FROM_DEVICE);
48addcc9 6929
6f0333b8
ED		 6930 kfree(*data_buff);
6931 *data_buff = NULL;
1da177e4
LT		 6932 rtl8169_make_unusable_by_asic(desc);
6933}
6934
6935static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
6936{
6937 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
6938
a0750138
AD		 6939 /* Force memory writes to complete before releasing descriptor */
6940 dma_wmb();
6941
1da177e4
LT		 6942 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
6943}
6944
6945static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
6946 u32 rx_buf_sz)
6947{
6948 desc->addr = cpu_to_le64(mapping);
1da177e4
LT		 6949 rtl8169_mark_to_asic(desc, rx_buf_sz);
6950}
6951
6f0333b8
ED		 6952static inline void *rtl8169_align(void *data)
6953{
6954 return (void *)ALIGN((long)data, 16);
6955}
6956
0ecbe1ca
SG		 6957static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
6958 struct RxDesc *desc)
1da177e4 6959{
6f0333b8 6960 void *data;
1da177e4 6961 dma_addr_t mapping;
48addcc9 6962 struct device *d = &tp->pci_dev->dev;
0ecbe1ca 6963 struct net_device *dev = tp->dev;
6f0333b8 6964 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
1da177e4 6965
6f0333b8
ED		 6966 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
6967 if (!data)
6968 return NULL;
e9f63f30 6969
6f0333b8
ED		 6970 if (rtl8169_align(data) != data) {
6971 kfree(data);
6972 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
6973 if (!data)
6974 return NULL;
6975 }
3eafe507 6976
48addcc9 6977 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
231aee63 6978 DMA_FROM_DEVICE);
d827d86b
SG		 6979 if (unlikely(dma_mapping_error(d, mapping))) {
6980 if (net_ratelimit())
6981 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
3eafe507 6982 goto err_out;
d827d86b 6983 }
1da177e4
LT		 6984
6985 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6f0333b8 6986 return data;
3eafe507
SG		 6987
6988err_out:
6989 kfree(data);
6990 return NULL;
1da177e4
LT		 6991}
6992
6993static void rtl8169_rx_clear(struct rtl8169_private *tp)
6994{
07d3f51f 6995 unsigned int i;
1da177e4
LT		 6996
6997 for (i = 0; i < NUM_RX_DESC; i++) {
6f0333b8
ED		 6998 if (tp->Rx_databuff[i]) {
6999 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
1da177e4
LT		 7000 tp->RxDescArray + i);
7001 }
7002 }
7003}
7004
0ecbe1ca 7005static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1da177e4 7006{
0ecbe1ca
SG		 7007 desc->opts1 |= cpu_to_le32(RingEnd);
7008}
5b0384f4 7009
0ecbe1ca
SG		 7010static int rtl8169_rx_fill(struct rtl8169_private *tp)
7011{
7012 unsigned int i;
1da177e4 7013
0ecbe1ca
SG		 7014 for (i = 0; i < NUM_RX_DESC; i++) {
7015 void *data;
4ae47c2d 7016
6f0333b8 7017 if (tp->Rx_databuff[i])
1da177e4 7018 continue;
bcf0bf90 7019
0ecbe1ca 7020 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6f0333b8
ED		 7021 if (!data) {
7022 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
0ecbe1ca 7023 goto err_out;
6f0333b8
ED		 7024 }
7025 tp->Rx_databuff[i] = data;
1da177e4 7026 }
1da177e4 7027
0ecbe1ca
SG		 7028 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
7029 return 0;
7030
7031err_out:
7032 rtl8169_rx_clear(tp);
7033 return -ENOMEM;
1da177e4
LT		 7034}
7035
1da177e4
LT		 7036static int rtl8169_init_ring(struct net_device *dev)
7037{
7038 struct rtl8169_private *tp = netdev_priv(dev);
7039
7040 rtl8169_init_ring_indexes(tp);
7041
7042 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
6f0333b8 7043 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
1da177e4 7044
0ecbe1ca 7045 return rtl8169_rx_fill(tp);
1da177e4
LT		 7046}
7047
48addcc9 7048static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
1da177e4
LT		 7049 struct TxDesc *desc)
7050{
7051 unsigned int len = tx_skb->len;
7052
48addcc9
SG		 7053 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
7054
1da177e4
LT		 7055 desc->opts1 = 0x00;
7056 desc->opts2 = 0x00;
7057 desc->addr = 0x00;
7058 tx_skb->len = 0;
7059}
7060
3eafe507
SG		 7061static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
7062 unsigned int n)
1da177e4
LT		 7063{
7064 unsigned int i;
7065
3eafe507
SG		 7066 for (i = 0; i < n; i++) {
7067 unsigned int entry = (start + i) % NUM_TX_DESC;
1da177e4
LT		 7068 struct ring_info *tx_skb = tp->tx_skb + entry;
7069 unsigned int len = tx_skb->len;
7070
7071 if (len) {
7072 struct sk_buff *skb = tx_skb->skb;
7073
48addcc9 7074 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
1da177e4
LT		 7075 tp->TxDescArray + entry);
7076 if (skb) {
7a4b813c 7077 dev_consume_skb_any(skb);
1da177e4
LT		 7078 tx_skb->skb = NULL;
7079 }
1da177e4
LT		 7080 }
7081 }
3eafe507
SG		 7082}
7083
7084static void rtl8169_tx_clear(struct rtl8169_private *tp)
7085{
7086 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
1da177e4
LT		 7087 tp->cur_tx = tp->dirty_tx = 0;
7088}
7089
4422bcd4 7090static void rtl_reset_work(struct rtl8169_private *tp)
1da177e4 7091{
c4028958 7092 struct net_device *dev = tp->dev;
56de414c 7093 int i;
1da177e4 7094
da78dbff
FR		 7095 napi_disable(&tp->napi);
7096 netif_stop_queue(dev);
7097 synchronize_sched();
1da177e4 7098
c7c2c39b 7099 rtl8169_hw_reset(tp);
7100
56de414c
FR		 7101 for (i = 0; i < NUM_RX_DESC; i++)
7102 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
7103
1da177e4 7104 rtl8169_tx_clear(tp);
c7c2c39b 7105 rtl8169_init_ring_indexes(tp);
1da177e4 7106
da78dbff 7107 napi_enable(&tp->napi);
56de414c
FR		 7108 rtl_hw_start(dev);
7109 netif_wake_queue(dev);
7110 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1da177e4
LT		 7111}
7112
7113static void rtl8169_tx_timeout(struct net_device *dev)
7114{
da78dbff
FR		 7115 struct rtl8169_private *tp = netdev_priv(dev);
7116
7117 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 7118}
7119
7120static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2b7b4318 7121 u32 *opts)
1da177e4
LT		 7122{
7123 struct skb_shared_info *info = skb_shinfo(skb);
7124 unsigned int cur_frag, entry;
6e1d0b89 7125 struct TxDesc *uninitialized_var(txd);
48addcc9 7126 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 7127
7128 entry = tp->cur_tx;
7129 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
9e903e08 7130 const skb_frag_t *frag = info->frags + cur_frag;
1da177e4
LT		 7131 dma_addr_t mapping;
7132 u32 status, len;
7133 void *addr;
7134
7135 entry = (entry + 1) % NUM_TX_DESC;
7136
7137 txd = tp->TxDescArray + entry;
9e903e08 7138 len = skb_frag_size(frag);
929f6189 7139 addr = skb_frag_address(frag);
48addcc9 7140 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
d827d86b
SG		 7141 if (unlikely(dma_mapping_error(d, mapping))) {
7142 if (net_ratelimit())
7143 netif_err(tp, drv, tp->dev,
7144 "Failed to map TX fragments DMA!\n");
3eafe507 7145 goto err_out;
d827d86b 7146 }
1da177e4 7147
cecb5fd7 7148 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318
FR		 7149 status = opts[0] | len |
7150 (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 7151
7152 txd->opts1 = cpu_to_le32(status);
2b7b4318 7153 txd->opts2 = cpu_to_le32(opts[1]);
1da177e4
LT		 7154 txd->addr = cpu_to_le64(mapping);
7155
7156 tp->tx_skb[entry].len = len;
7157 }
7158
7159 if (cur_frag) {
7160 tp->tx_skb[entry].skb = skb;
7161 txd->opts1 |= cpu_to_le32(LastFrag);
7162 }
7163
7164 return cur_frag;
3eafe507
SG		 7165
7166err_out:
7167 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
7168 return -EIO;
1da177e4
LT		 7169}
7170
b423e9ae 7171static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
7172{
7173 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
7174}
7175
e974604b 7176static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
7177 struct net_device *dev);
7178/* r8169_csum_workaround()
7179 * The hw limites the value the transport offset. When the offset is out of the
7180 * range, calculate the checksum by sw.
7181 */
7182static void r8169_csum_workaround(struct rtl8169_private *tp,
7183 struct sk_buff *skb)
7184{
7185 if (skb_shinfo(skb)->gso_size) {
7186 netdev_features_t features = tp->dev->features;
7187 struct sk_buff *segs, *nskb;
7188
7189 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
7190 segs = skb_gso_segment(skb, features);
7191 if (IS_ERR(segs) || !segs)
7192 goto drop;
7193
7194 do {
7195 nskb = segs;
7196 segs = segs->next;
7197 nskb->next = NULL;
7198 rtl8169_start_xmit(nskb, tp->dev);
7199 } while (segs);
7200
eb781397 7201 dev_consume_skb_any(skb);
e974604b 7202 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
7203 if (skb_checksum_help(skb) < 0)
7204 goto drop;
7205
7206 rtl8169_start_xmit(skb, tp->dev);
7207 } else {
7208 struct net_device_stats *stats;
7209
7210drop:
7211 stats = &tp->dev->stats;
7212 stats->tx_dropped++;
eb781397 7213 dev_kfree_skb_any(skb);
e974604b 7214 }
7215}
7216
7217/* msdn_giant_send_check()
7218 * According to the document of microsoft, the TCP Pseudo Header excludes the
7219 * packet length for IPv6 TCP large packets.
7220 */
7221static int msdn_giant_send_check(struct sk_buff *skb)
7222{
7223 const struct ipv6hdr *ipv6h;
7224 struct tcphdr *th;
7225 int ret;
7226
7227 ret = skb_cow_head(skb, 0);
7228 if (ret)
7229 return ret;
7230
7231 ipv6h = ipv6_hdr(skb);
7232 th = tcp_hdr(skb);
7233
7234 th->check = 0;
7235 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
7236
7237 return ret;
7238}
7239
7240static inline __be16 get_protocol(struct sk_buff *skb)
7241{
7242 __be16 protocol;
7243
7244 if (skb->protocol == htons(ETH_P_8021Q))
7245 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
7246 else
7247 protocol = skb->protocol;
7248
7249 return protocol;
7250}
7251
5888d3fc 7252static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
7253 struct sk_buff *skb, u32 *opts)
1da177e4 7254{
350fb32a
MM		 7255 u32 mss = skb_shinfo(skb)->gso_size;
7256
2b7b4318
FR		 7257 if (mss) {
7258 opts[0] |= TD_LSO;
5888d3fc 7259 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
7260 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
7261 const struct iphdr *ip = ip_hdr(skb);
7262
7263 if (ip->protocol == IPPROTO_TCP)
7264 opts[0] |= TD0_IP_CS | TD0_TCP_CS;
7265 else if (ip->protocol == IPPROTO_UDP)
7266 opts[0] |= TD0_IP_CS | TD0_UDP_CS;
7267 else
7268 WARN_ON_ONCE(1);
7269 }
7270
7271 return true;
7272}
7273
7274static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
7275 struct sk_buff *skb, u32 *opts)
7276{
bdfa4ed6 7277 u32 transport_offset = (u32)skb_transport_offset(skb);
5888d3fc 7278 u32 mss = skb_shinfo(skb)->gso_size;
7279
7280 if (mss) {
e974604b 7281 if (transport_offset > GTTCPHO_MAX) {
7282 netif_warn(tp, tx_err, tp->dev,
7283 "Invalid transport offset 0x%x for TSO\n",
7284 transport_offset);
7285 return false;
7286 }
7287
7288 switch (get_protocol(skb)) {
7289 case htons(ETH_P_IP):
7290 opts[0] |= TD1_GTSENV4;
7291 break;
7292
7293 case htons(ETH_P_IPV6):
7294 if (msdn_giant_send_check(skb))
7295 return false;
7296
7297 opts[0] |= TD1_GTSENV6;
7298 break;
7299
7300 default:
7301 WARN_ON_ONCE(1);
7302 break;
7303 }
7304
bdfa4ed6 7305 opts[0] |= transport_offset << GTTCPHO_SHIFT;
5888d3fc 7306 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
2b7b4318 7307 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
e974604b 7308 u8 ip_protocol;
1da177e4 7309
b423e9ae 7310 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
207c5f44 7311 return !(skb_checksum_help(skb) || eth_skb_pad(skb));
b423e9ae 7312
e974604b 7313 if (transport_offset > TCPHO_MAX) {
7314 netif_warn(tp, tx_err, tp->dev,
7315 "Invalid transport offset 0x%x\n",
7316 transport_offset);
7317 return false;
7318 }
7319
7320 switch (get_protocol(skb)) {
7321 case htons(ETH_P_IP):
7322 opts[1] |= TD1_IPv4_CS;
7323 ip_protocol = ip_hdr(skb)->protocol;
7324 break;
7325
7326 case htons(ETH_P_IPV6):
7327 opts[1] |= TD1_IPv6_CS;
7328 ip_protocol = ipv6_hdr(skb)->nexthdr;
7329 break;
7330
7331 default:
7332 ip_protocol = IPPROTO_RAW;
7333 break;
7334 }
7335
7336 if (ip_protocol == IPPROTO_TCP)
7337 opts[1] |= TD1_TCP_CS;
7338 else if (ip_protocol == IPPROTO_UDP)
7339 opts[1] |= TD1_UDP_CS;
2b7b4318
FR		 7340 else
7341 WARN_ON_ONCE(1);
e974604b 7342
7343 opts[1] |= transport_offset << TCPHO_SHIFT;
b423e9ae 7344 } else {
7345 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
207c5f44 7346 return !eth_skb_pad(skb);
1da177e4 7347 }
5888d3fc 7348
b423e9ae 7349 return true;
1da177e4
LT		 7350}
7351
61357325
SH		 7352static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
7353 struct net_device *dev)
1da177e4
LT		 7354{
7355 struct rtl8169_private *tp = netdev_priv(dev);
3eafe507 7356 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
1da177e4
LT		 7357 struct TxDesc *txd = tp->TxDescArray + entry;
7358 void __iomem *ioaddr = tp->mmio_addr;
48addcc9 7359 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 7360 dma_addr_t mapping;
7361 u32 status, len;
2b7b4318 7362 u32 opts[2];
3eafe507 7363 int frags;
5b0384f4 7364
477206a0 7365 if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
bf82c189 7366 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
3eafe507 7367 goto err_stop_0;
1da177e4
LT		 7368 }
7369
7370 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3eafe507
SG		 7371 goto err_stop_0;
7372
b423e9ae 7373 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
7374 opts[0] = DescOwn;
7375
e974604b 7376 if (!tp->tso_csum(tp, skb, opts)) {
7377 r8169_csum_workaround(tp, skb);
7378 return NETDEV_TX_OK;
7379 }
b423e9ae 7380
3eafe507 7381 len = skb_headlen(skb);
48addcc9 7382 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
d827d86b
SG		 7383 if (unlikely(dma_mapping_error(d, mapping))) {
7384 if (net_ratelimit())
7385 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
3eafe507 7386 goto err_dma_0;
d827d86b 7387 }
3eafe507
SG		 7388
7389 tp->tx_skb[entry].len = len;
7390 txd->addr = cpu_to_le64(mapping);
1da177e4 7391
2b7b4318 7392 frags = rtl8169_xmit_frags(tp, skb, opts);
3eafe507
SG		 7393 if (frags < 0)
7394 goto err_dma_1;
7395 else if (frags)
2b7b4318 7396 opts[0] |= FirstFrag;
3eafe507 7397 else {
2b7b4318 7398 opts[0] |= FirstFrag | LastFrag;
1da177e4
LT		 7399 tp->tx_skb[entry].skb = skb;
7400 }
7401
2b7b4318
FR		 7402 txd->opts2 = cpu_to_le32(opts[1]);
7403
5047fb5d
RC		 7404 skb_tx_timestamp(skb);
7405
a0750138
AD		 7406 /* Force memory writes to complete before releasing descriptor */
7407 dma_wmb();
1da177e4 7408
cecb5fd7 7409 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318 7410 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 7411 txd->opts1 = cpu_to_le32(status);
7412
a0750138 7413 /* Force all memory writes to complete before notifying device */
4c020a96 7414 wmb();
1da177e4 7415
a0750138
AD		 7416 tp->cur_tx += frags + 1;
7417
87cda7cb 7418 RTL_W8(TxPoll, NPQ);
1da177e4 7419
87cda7cb 7420 mmiowb();
da78dbff 7421
87cda7cb 7422 if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
ae1f23fb
FR		 7423 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
7424 * not miss a ring update when it notices a stopped queue.
7425 */
7426 smp_wmb();
1da177e4 7427 netif_stop_queue(dev);
ae1f23fb
FR		 7428 /* Sync with rtl_tx:
7429 * - publish queue status and cur_tx ring index (write barrier)
7430 * - refresh dirty_tx ring index (read barrier).
7431 * May the current thread have a pessimistic view of the ring
7432 * status and forget to wake up queue, a racing rtl_tx thread
7433 * can't.
7434 */
1e874e04 7435 smp_mb();
477206a0 7436 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
1da177e4
LT		 7437 netif_wake_queue(dev);
7438 }
7439
61357325 7440 return NETDEV_TX_OK;
1da177e4 7441
3eafe507 7442err_dma_1:
48addcc9 7443 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
3eafe507 7444err_dma_0:
989c9ba1 7445 dev_kfree_skb_any(skb);
3eafe507
SG		 7446 dev->stats.tx_dropped++;
7447 return NETDEV_TX_OK;
7448
7449err_stop_0:
1da177e4 7450 netif_stop_queue(dev);
cebf8cc7 7451 dev->stats.tx_dropped++;
61357325 7452 return NETDEV_TX_BUSY;
1da177e4
LT		 7453}
7454
7455static void rtl8169_pcierr_interrupt(struct net_device *dev)
7456{
7457 struct rtl8169_private *tp = netdev_priv(dev);
7458 struct pci_dev *pdev = tp->pci_dev;
1da177e4
LT		 7459 u16 pci_status, pci_cmd;
7460
7461 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
7462 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
7463
bf82c189
JP		 7464 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
7465 pci_cmd, pci_status);
1da177e4
LT		 7466
7467 /*
7468 * The recovery sequence below admits a very elaborated explanation:
7469 * - it seems to work;
d03902b8
FR		 7470 * - I did not see what else could be done;
7471 * - it makes iop3xx happy.
1da177e4
LT		 7472 *
7473 * Feel free to adjust to your needs.
7474 */
a27993f3 7475 if (pdev->broken_parity_status)
d03902b8
FR		 7476 pci_cmd &= ~PCI_COMMAND_PARITY;
7477 else
7478 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
7479
7480 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 7481
7482 pci_write_config_word(pdev, PCI_STATUS,
7483 pci_status & (PCI_STATUS_DETECTED_PARITY |
7484 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
7485 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
7486
7487 /* The infamous DAC f*ckup only happens at boot time */
9fba0812 7488 if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
e6de30d6 7489 void __iomem *ioaddr = tp->mmio_addr;
7490
bf82c189 7491 netif_info(tp, intr, dev, "disabling PCI DAC\n");
1da177e4
LT		 7492 tp->cp_cmd &= ~PCIDAC;
7493 RTL_W16(CPlusCmd, tp->cp_cmd);
7494 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 7495 }
7496
e6de30d6 7497 rtl8169_hw_reset(tp);
d03902b8 7498
98ddf986 7499 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 7500}
7501
da78dbff 7502static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
1da177e4
LT		 7503{
7504 unsigned int dirty_tx, tx_left;
7505
1da177e4
LT		 7506 dirty_tx = tp->dirty_tx;
7507 smp_rmb();
7508 tx_left = tp->cur_tx - dirty_tx;
7509
7510 while (tx_left > 0) {
7511 unsigned int entry = dirty_tx % NUM_TX_DESC;
7512 struct ring_info *tx_skb = tp->tx_skb + entry;
1da177e4
LT		 7513 u32 status;
7514
1da177e4
LT		 7515 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
7516 if (status & DescOwn)
7517 break;
7518
a0750138
AD		 7519 /* This barrier is needed to keep us from reading
7520 * any other fields out of the Tx descriptor until
7521 * we know the status of DescOwn
7522 */
7523 dma_rmb();
7524
48addcc9
SG		 7525 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
7526 tp->TxDescArray + entry);
1da177e4 7527 if (status & LastFrag) {
87cda7cb
DM		 7528 u64_stats_update_begin(&tp->tx_stats.syncp);
7529 tp->tx_stats.packets++;
7530 tp->tx_stats.bytes += tx_skb->skb->len;
7531 u64_stats_update_end(&tp->tx_stats.syncp);
7a4b813c 7532 dev_consume_skb_any(tx_skb->skb);
1da177e4
LT		 7533 tx_skb->skb = NULL;
7534 }
7535 dirty_tx++;
7536 tx_left--;
7537 }
7538
7539 if (tp->dirty_tx != dirty_tx) {
7540 tp->dirty_tx = dirty_tx;
ae1f23fb
FR		 7541 /* Sync with rtl8169_start_xmit:
7542 * - publish dirty_tx ring index (write barrier)
7543 * - refresh cur_tx ring index and queue status (read barrier)
7544 * May the current thread miss the stopped queue condition,
7545 * a racing xmit thread can only have a right view of the
7546 * ring status.
7547 */
1e874e04 7548 smp_mb();
1da177e4 7549 if (netif_queue_stopped(dev) &&
477206a0 7550 TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
1da177e4
LT		 7551 netif_wake_queue(dev);
7552 }
d78ae2dc
FR		 7553 /*
7554 * 8168 hack: TxPoll requests are lost when the Tx packets are
7555 * too close. Let's kick an extra TxPoll request when a burst
7556 * of start_xmit activity is detected (if it is not detected,
7557 * it is slow enough). -- FR
7558 */
da78dbff
FR		 7559 if (tp->cur_tx != dirty_tx) {
7560 void __iomem *ioaddr = tp->mmio_addr;
7561
d78ae2dc 7562 RTL_W8(TxPoll, NPQ);
da78dbff 7563 }
1da177e4
LT		 7564 }
7565}
7566
126fa4b9
FR		 7567static inline int rtl8169_fragmented_frame(u32 status)
7568{
7569 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
7570}
7571
adea1ac7 7572static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
1da177e4 7573{
1da177e4
LT		 7574 u32 status = opts1 & RxProtoMask;
7575
7576 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
d5d3ebe3 7577 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
1da177e4
LT		 7578 skb->ip_summed = CHECKSUM_UNNECESSARY;
7579 else
bc8acf2c 7580 skb_checksum_none_assert(skb);
1da177e4
LT		 7581}
7582
6f0333b8
ED		 7583static struct sk_buff *rtl8169_try_rx_copy(void *data,
7584 struct rtl8169_private *tp,
7585 int pkt_size,
7586 dma_addr_t addr)
1da177e4 7587{
b449655f 7588 struct sk_buff *skb;
48addcc9 7589 struct device *d = &tp->pci_dev->dev;
b449655f 7590
6f0333b8 7591 data = rtl8169_align(data);
48addcc9 7592 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6f0333b8 7593 prefetch(data);
e2338f86 7594 skb = napi_alloc_skb(&tp->napi, pkt_size);
6f0333b8
ED		 7595 if (skb)
7596 memcpy(skb->data, data, pkt_size);
48addcc9
SG		 7597 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
7598
6f0333b8 7599 return skb;
1da177e4
LT		 7600}
7601
da78dbff 7602static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
1da177e4
LT		 7603{
7604 unsigned int cur_rx, rx_left;
6f0333b8 7605 unsigned int count;
1da177e4 7606
1da177e4 7607 cur_rx = tp->cur_rx;
1da177e4 7608
9fba0812 7609 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
1da177e4 7610 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 7611 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 7612 u32 status;
7613
e03f33af 7614 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
1da177e4
LT		 7615 if (status & DescOwn)
7616 break;
a0750138
AD		 7617
7618 /* This barrier is needed to keep us from reading
7619 * any other fields out of the Rx descriptor until
7620 * we know the status of DescOwn
7621 */
7622 dma_rmb();
7623
4dcb7d33 7624 if (unlikely(status & RxRES)) {
bf82c189
JP		 7625 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
7626 status);
cebf8cc7 7627 dev->stats.rx_errors++;
1da177e4 7628 if (status & (RxRWT | RxRUNT))
cebf8cc7 7629 dev->stats.rx_length_errors++;
1da177e4 7630 if (status & RxCRC)
cebf8cc7 7631 dev->stats.rx_crc_errors++;
9dccf611 7632 if (status & RxFOVF) {
da78dbff 7633 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
cebf8cc7 7634 dev->stats.rx_fifo_errors++;
9dccf611 7635 }
6bbe021d
BG		 7636 if ((status & (RxRUNT | RxCRC)) &&
7637 !(status & (RxRWT | RxFOVF)) &&
7638 (dev->features & NETIF_F_RXALL))
7639 goto process_pkt;
1da177e4 7640 } else {
6f0333b8 7641 struct sk_buff *skb;
6bbe021d
BG		 7642 dma_addr_t addr;
7643 int pkt_size;
7644
7645process_pkt:
7646 addr = le64_to_cpu(desc->addr);
79d0c1d2
BG		 7647 if (likely(!(dev->features & NETIF_F_RXFCS)))
7648 pkt_size = (status & 0x00003fff) - 4;
7649 else
7650 pkt_size = status & 0x00003fff;
1da177e4 7651
126fa4b9
FR		 7652 /*
7653 * The driver does not support incoming fragmented
7654 * frames. They are seen as a symptom of over-mtu
7655 * sized frames.
7656 */
7657 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 7658 dev->stats.rx_dropped++;
7659 dev->stats.rx_length_errors++;
ce11ff5e 7660 goto release_descriptor;
126fa4b9
FR		 7661 }
7662
6f0333b8
ED		 7663 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
7664 tp, pkt_size, addr);
6f0333b8
ED		 7665 if (!skb) {
7666 dev->stats.rx_dropped++;
ce11ff5e 7667 goto release_descriptor;
1da177e4
LT		 7668 }
7669
adea1ac7 7670 rtl8169_rx_csum(skb, status);
1da177e4
LT		 7671 skb_put(skb, pkt_size);
7672 skb->protocol = eth_type_trans(skb, dev);
7673
7a8fc77b
FR		 7674 rtl8169_rx_vlan_tag(desc, skb);
7675
39174291 7676 if (skb->pkt_type == PACKET_MULTICAST)
7677 dev->stats.multicast++;
7678
56de414c 7679 napi_gro_receive(&tp->napi, skb);
1da177e4 7680
8027aa24
JW		 7681 u64_stats_update_begin(&tp->rx_stats.syncp);
7682 tp->rx_stats.packets++;
7683 tp->rx_stats.bytes += pkt_size;
7684 u64_stats_update_end(&tp->rx_stats.syncp);
1da177e4 7685 }
ce11ff5e 7686release_descriptor:
7687 desc->opts2 = 0;
ce11ff5e 7688 rtl8169_mark_to_asic(desc, rx_buf_sz);
1da177e4
LT		 7689 }
7690
7691 count = cur_rx - tp->cur_rx;
7692 tp->cur_rx = cur_rx;
7693
1da177e4
LT		 7694 return count;
7695}
7696
07d3f51f 7697static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 7698{
07d3f51f 7699 struct net_device *dev = dev_instance;
1da177e4 7700 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 7701 int handled = 0;
9085cdfa 7702 u16 status;
1da177e4 7703
9085cdfa 7704 status = rtl_get_events(tp);
da78dbff
FR		 7705 if (status && status != 0xffff) {
7706 status &= RTL_EVENT_NAPI | tp->event_slow;
7707 if (status) {
7708 handled = 1;
1da177e4 7709
da78dbff
FR		 7710 rtl_irq_disable(tp);
7711 napi_schedule(&tp->napi);
f11a377b 7712 }
da78dbff
FR		 7713 }
7714 return IRQ_RETVAL(handled);
7715}
1da177e4 7716
da78dbff
FR		 7717/*
7718 * Workqueue context.
7719 */
7720static void rtl_slow_event_work(struct rtl8169_private *tp)
7721{
7722 struct net_device *dev = tp->dev;
7723 u16 status;
7724
7725 status = rtl_get_events(tp) & tp->event_slow;
7726 rtl_ack_events(tp, status);
1da177e4 7727
da78dbff
FR		 7728 if (unlikely(status & RxFIFOOver)) {
7729 switch (tp->mac_version) {
7730 /* Work around for rx fifo overflow */
7731 case RTL_GIGA_MAC_VER_11:
7732 netif_stop_queue(dev);
934714d0
FR		 7733 /* XXX - Hack alert. See rtl_task(). */
7734 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
da78dbff 7735 default:
f11a377b
DD		 7736 break;
7737 }
da78dbff 7738 }
1da177e4 7739
da78dbff
FR		 7740 if (unlikely(status & SYSErr))
7741 rtl8169_pcierr_interrupt(dev);
0e485150 7742
da78dbff
FR		 7743 if (status & LinkChg)
7744 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
1da177e4 7745
7dbb4918 7746 rtl_irq_enable_all(tp);
1da177e4
LT		 7747}
7748
4422bcd4
FR		 7749static void rtl_task(struct work_struct *work)
7750{
da78dbff
FR		 7751 static const struct {
7752 int bitnr;
7753 void (*action)(struct rtl8169_private *);
7754 } rtl_work[] = {
934714d0 7755 /* XXX - keep rtl_slow_event_work() as first element. */
da78dbff
FR		 7756 { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work },
7757 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
7758 { RTL_FLAG_TASK_PHY_PENDING, rtl_phy_work }
7759 };
4422bcd4
FR		 7760 struct rtl8169_private *tp =
7761 container_of(work, struct rtl8169_private, wk.work);
da78dbff
FR		 7762 struct net_device *dev = tp->dev;
7763 int i;
7764
7765 rtl_lock_work(tp);
7766
6c4a70c5
FR		 7767 if (!netif_running(dev) ||
7768 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
da78dbff
FR		 7769 goto out_unlock;
7770
7771 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
7772 bool pending;
7773
da78dbff 7774 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
da78dbff
FR		 7775 if (pending)
7776 rtl_work[i].action(tp);
7777 }
4422bcd4 7778
da78dbff
FR		 7779out_unlock:
7780 rtl_unlock_work(tp);
4422bcd4
FR		 7781}
7782
bea3348e 7783static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 7784{
bea3348e
SH		 7785 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
7786 struct net_device *dev = tp->dev;
da78dbff 7787 u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
f6ac4177 7788 int work_done;
da78dbff
FR		 7789 u16 status;
7790
7791 status = rtl_get_events(tp);
7792 rtl_ack_events(tp, status & ~tp->event_slow);
7793
f6ac4177 7794 work_done = rtl_rx(dev, tp, (u32) budget);
da78dbff 7795
f6ac4177 7796 rtl_tx(dev, tp);
1da177e4 7797
da78dbff
FR		 7798 if (status & tp->event_slow) {
7799 enable_mask &= ~tp->event_slow;
7800
7801 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
7802 }
1da177e4 7803
bea3348e 7804 if (work_done < budget) {
6ad20165 7805 napi_complete_done(napi, work_done);
f11a377b 7806
da78dbff
FR		 7807 rtl_irq_enable(tp, enable_mask);
7808 mmiowb();
1da177e4
LT		 7809 }
7810
bea3348e 7811 return work_done;
1da177e4 7812}
1da177e4 7813
523a6094
FR		 7814static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
7815{
7816 struct rtl8169_private *tp = netdev_priv(dev);
7817
7818 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
7819 return;
7820
7821 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
7822 RTL_W32(RxMissed, 0);
7823}
7824
1da177e4
LT		 7825static void rtl8169_down(struct net_device *dev)
7826{
7827 struct rtl8169_private *tp = netdev_priv(dev);
7828 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 7829
4876cc1e 7830 del_timer_sync(&tp->timer);
1da177e4 7831
93dd79e8 7832 napi_disable(&tp->napi);
da78dbff 7833 netif_stop_queue(dev);
1da177e4 7834
92fc43b4 7835 rtl8169_hw_reset(tp);
323bb685
SG		 7836 /*
7837 * At this point device interrupts can not be enabled in any function,
209e5ac8
FR		 7838 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
7839 * and napi is disabled (rtl8169_poll).
323bb685 7840 */
523a6094 7841 rtl8169_rx_missed(dev, ioaddr);
1da177e4 7842
1da177e4 7843 /* Give a racing hard_start_xmit a few cycles to complete. */
da78dbff 7844 synchronize_sched();
1da177e4 7845
1da177e4
LT		 7846 rtl8169_tx_clear(tp);
7847
7848 rtl8169_rx_clear(tp);
065c27c1 7849
7850 rtl_pll_power_down(tp);
1da177e4
LT		 7851}
7852
7853static int rtl8169_close(struct net_device *dev)
7854{
7855 struct rtl8169_private *tp = netdev_priv(dev);
7856 struct pci_dev *pdev = tp->pci_dev;
7857
e1759441
RW		 7858 pm_runtime_get_sync(&pdev->dev);
7859
cecb5fd7 7860 /* Update counters before going down */
355423d0
IV		 7861 rtl8169_update_counters(dev);
7862
da78dbff 7863 rtl_lock_work(tp);
4135fe46
KHF		 7864 /* Clear all task flags */
7865 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
da78dbff 7866
1da177e4 7867 rtl8169_down(dev);
da78dbff 7868 rtl_unlock_work(tp);
1da177e4 7869
4ea72445
L		 7870 cancel_work_sync(&tp->wk.work);
7871
41450d46 7872 pci_free_irq(pdev, 0, dev);
1da177e4 7873
82553bb6
SG		 7874 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7875 tp->RxPhyAddr);
7876 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7877 tp->TxPhyAddr);
1da177e4
LT		 7878 tp->TxDescArray = NULL;
7879 tp->RxDescArray = NULL;
7880
e1759441
RW		 7881 pm_runtime_put_sync(&pdev->dev);
7882
1da177e4
LT		 7883 return 0;
7884}
7885
dc1c00ce
FR		 7886#ifdef CONFIG_NET_POLL_CONTROLLER
7887static void rtl8169_netpoll(struct net_device *dev)
7888{
7889 struct rtl8169_private *tp = netdev_priv(dev);
7890
d18c4419 7891 rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), dev);
dc1c00ce
FR		 7892}
7893#endif
7894
df43ac78
FR		 7895static int rtl_open(struct net_device *dev)
7896{
7897 struct rtl8169_private *tp = netdev_priv(dev);
7898 void __iomem *ioaddr = tp->mmio_addr;
7899 struct pci_dev *pdev = tp->pci_dev;
7900 int retval = -ENOMEM;
7901
7902 pm_runtime_get_sync(&pdev->dev);
7903
7904 /*
e75d6606 7905 * Rx and Tx descriptors needs 256 bytes alignment.
df43ac78
FR		 7906 * dma_alloc_coherent provides more.
7907 */
7908 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
7909 &tp->TxPhyAddr, GFP_KERNEL);
7910 if (!tp->TxDescArray)
7911 goto err_pm_runtime_put;
7912
7913 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
7914 &tp->RxPhyAddr, GFP_KERNEL);
7915 if (!tp->RxDescArray)
7916 goto err_free_tx_0;
7917
7918 retval = rtl8169_init_ring(dev);
7919 if (retval < 0)
7920 goto err_free_rx_1;
7921
7922 INIT_WORK(&tp->wk.work, rtl_task);
7923
7924 smp_mb();
7925
7926 rtl_request_firmware(tp);
7927
41450d46
HK		 7928 retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, dev,
7929 dev->name);
df43ac78
FR		 7930 if (retval < 0)
7931 goto err_release_fw_2;
7932
7933 rtl_lock_work(tp);
7934
7935 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7936
7937 napi_enable(&tp->napi);
7938
7939 rtl8169_init_phy(dev, tp);
7940
7941 __rtl8169_set_features(dev, dev->features);
7942
7943 rtl_pll_power_up(tp);
7944
7945 rtl_hw_start(dev);
7946
6e85d5ad
CV		 7947 if (!rtl8169_init_counter_offsets(dev))
7948 netif_warn(tp, hw, dev, "counter reset/update failed\n");
7949
df43ac78
FR		 7950 netif_start_queue(dev);
7951
7952 rtl_unlock_work(tp);
7953
7954 tp->saved_wolopts = 0;
7955 pm_runtime_put_noidle(&pdev->dev);
7956
7957 rtl8169_check_link_status(dev, tp, ioaddr);
7958out:
7959 return retval;
7960
7961err_release_fw_2:
7962 rtl_release_firmware(tp);
7963 rtl8169_rx_clear(tp);
7964err_free_rx_1:
7965 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7966 tp->RxPhyAddr);
7967 tp->RxDescArray = NULL;
7968err_free_tx_0:
7969 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7970 tp->TxPhyAddr);
7971 tp->TxDescArray = NULL;
7972err_pm_runtime_put:
7973 pm_runtime_put_noidle(&pdev->dev);
7974 goto out;
7975}
7976
bc1f4470 7977static void
8027aa24 7978rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
1da177e4
LT		 7979{
7980 struct rtl8169_private *tp = netdev_priv(dev);
7981 void __iomem *ioaddr = tp->mmio_addr;
f09cf4b7 7982 struct pci_dev *pdev = tp->pci_dev;
42020320 7983 struct rtl8169_counters *counters = tp->counters;
8027aa24 7984 unsigned int start;
1da177e4 7985
f09cf4b7
CHL		 7986 pm_runtime_get_noresume(&pdev->dev);
7987
7988 if (netif_running(dev) && pm_runtime_active(&pdev->dev))
523a6094 7989 rtl8169_rx_missed(dev, ioaddr);
5b0384f4 7990
8027aa24 7991 do {
57a7744e 7992 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
8027aa24
JW		 7993 stats->rx_packets = tp->rx_stats.packets;
7994 stats->rx_bytes = tp->rx_stats.bytes;
57a7744e 7995 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
8027aa24 7996
8027aa24 7997 do {
57a7744e 7998 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
8027aa24
JW		 7999 stats->tx_packets = tp->tx_stats.packets;
8000 stats->tx_bytes = tp->tx_stats.bytes;
57a7744e 8001 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
8027aa24
JW		 8002
8003 stats->rx_dropped = dev->stats.rx_dropped;
8004 stats->tx_dropped = dev->stats.tx_dropped;
8005 stats->rx_length_errors = dev->stats.rx_length_errors;
8006 stats->rx_errors = dev->stats.rx_errors;
8007 stats->rx_crc_errors = dev->stats.rx_crc_errors;
8008 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
8009 stats->rx_missed_errors = dev->stats.rx_missed_errors;
d7d2d89d 8010 stats->multicast = dev->stats.multicast;
8027aa24 8011
6e85d5ad
CV		 8012 /*
8013 * Fetch additonal counter values missing in stats collected by driver
8014 * from tally counters.
8015 */
f09cf4b7
CHL		 8016 if (pm_runtime_active(&pdev->dev))
8017 rtl8169_update_counters(dev);
6e85d5ad
CV		 8018
8019 /*
8020 * Subtract values fetched during initalization.
8021 * See rtl8169_init_counter_offsets for a description why we do that.
8022 */
42020320 8023 stats->tx_errors = le64_to_cpu(counters->tx_errors) -
6e85d5ad 8024 le64_to_cpu(tp->tc_offset.tx_errors);
42020320 8025 stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
6e85d5ad 8026 le32_to_cpu(tp->tc_offset.tx_multi_collision);
42020320 8027 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
6e85d5ad
CV		 8028 le16_to_cpu(tp->tc_offset.tx_aborted);
8029
f09cf4b7 8030 pm_runtime_put_noidle(&pdev->dev);
1da177e4
LT		 8031}
8032
861ab440 8033static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 8034{
065c27c1 8035 struct rtl8169_private *tp = netdev_priv(dev);
8036
5d06a99f 8037 if (!netif_running(dev))
861ab440 8038 return;
5d06a99f
FR		 8039
8040 netif_device_detach(dev);
8041 netif_stop_queue(dev);
da78dbff
FR		 8042
8043 rtl_lock_work(tp);
8044 napi_disable(&tp->napi);
4135fe46
KHF		 8045 /* Clear all task flags */
8046 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
8047
da78dbff
FR		 8048 rtl_unlock_work(tp);
8049
8050 rtl_pll_power_down(tp);
861ab440
RW		 8051}
8052
8053#ifdef CONFIG_PM
8054
8055static int rtl8169_suspend(struct device *device)
8056{
8057 struct pci_dev *pdev = to_pci_dev(device);
8058 struct net_device *dev = pci_get_drvdata(pdev);
5d06a99f 8059
861ab440 8060 rtl8169_net_suspend(dev);
1371fa6d 8061
5d06a99f
FR		 8062 return 0;
8063}
8064
e1759441
RW		 8065static void __rtl8169_resume(struct net_device *dev)
8066{
065c27c1 8067 struct rtl8169_private *tp = netdev_priv(dev);
8068
e1759441 8069 netif_device_attach(dev);
065c27c1 8070
8071 rtl_pll_power_up(tp);
8072
cff4c162
AS		 8073 rtl_lock_work(tp);
8074 napi_enable(&tp->napi);
6c4a70c5 8075 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
cff4c162 8076 rtl_unlock_work(tp);
da78dbff 8077
98ddf986 8078 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
e1759441
RW		 8079}
8080
861ab440 8081static int rtl8169_resume(struct device *device)
5d06a99f 8082{
861ab440 8083 struct pci_dev *pdev = to_pci_dev(device);
5d06a99f 8084 struct net_device *dev = pci_get_drvdata(pdev);
fccec10b
SG		 8085 struct rtl8169_private *tp = netdev_priv(dev);
8086
8087 rtl8169_init_phy(dev, tp);
5d06a99f 8088
e1759441
RW		 8089 if (netif_running(dev))
8090 __rtl8169_resume(dev);
5d06a99f 8091
e1759441
RW		 8092 return 0;
8093}
8094
8095static int rtl8169_runtime_suspend(struct device *device)
8096{
8097 struct pci_dev *pdev = to_pci_dev(device);
8098 struct net_device *dev = pci_get_drvdata(pdev);
8099 struct rtl8169_private *tp = netdev_priv(dev);
8100
8101 if (!tp->TxDescArray)
8102 return 0;
8103
da78dbff 8104 rtl_lock_work(tp);
e1759441
RW		 8105 tp->saved_wolopts = __rtl8169_get_wol(tp);
8106 __rtl8169_set_wol(tp, WAKE_ANY);
da78dbff 8107 rtl_unlock_work(tp);
e1759441
RW		 8108
8109 rtl8169_net_suspend(dev);
8110
f09cf4b7
CHL		 8111 /* Update counters before going runtime suspend */
8112 rtl8169_rx_missed(dev, tp->mmio_addr);
8113 rtl8169_update_counters(dev);
8114
e1759441
RW		 8115 return 0;
8116}
8117
8118static int rtl8169_runtime_resume(struct device *device)
8119{
8120 struct pci_dev *pdev = to_pci_dev(device);
8121 struct net_device *dev = pci_get_drvdata(pdev);
8122 struct rtl8169_private *tp = netdev_priv(dev);
f51d4a10 8123 rtl_rar_set(tp, dev->dev_addr);
e1759441
RW		 8124
8125 if (!tp->TxDescArray)
8126 return 0;
8127
da78dbff 8128 rtl_lock_work(tp);
e1759441
RW		 8129 __rtl8169_set_wol(tp, tp->saved_wolopts);
8130 tp->saved_wolopts = 0;
da78dbff 8131 rtl_unlock_work(tp);
e1759441 8132
fccec10b
SG		 8133 rtl8169_init_phy(dev, tp);
8134
e1759441 8135 __rtl8169_resume(dev);
5d06a99f 8136
5d06a99f
FR		 8137 return 0;
8138}
8139
e1759441
RW		 8140static int rtl8169_runtime_idle(struct device *device)
8141{
8142 struct pci_dev *pdev = to_pci_dev(device);
8143 struct net_device *dev = pci_get_drvdata(pdev);
8144 struct rtl8169_private *tp = netdev_priv(dev);
8145
e4fbce74 8146 return tp->TxDescArray ? -EBUSY : 0;
e1759441
RW		 8147}
8148
47145210 8149static const struct dev_pm_ops rtl8169_pm_ops = {
cecb5fd7
FR		 8150 .suspend = rtl8169_suspend,
8151 .resume = rtl8169_resume,
8152 .freeze = rtl8169_suspend,
8153 .thaw = rtl8169_resume,
8154 .poweroff = rtl8169_suspend,
8155 .restore = rtl8169_resume,
8156 .runtime_suspend = rtl8169_runtime_suspend,
8157 .runtime_resume = rtl8169_runtime_resume,
8158 .runtime_idle = rtl8169_runtime_idle,
861ab440
RW		 8159};
8160
8161#define RTL8169_PM_OPS (&rtl8169_pm_ops)
8162
8163#else /* !CONFIG_PM */
8164
8165#define RTL8169_PM_OPS NULL
8166
8167#endif /* !CONFIG_PM */
8168
649b3b8c 8169static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
8170{
8171 void __iomem *ioaddr = tp->mmio_addr;
8172
8173 /* WoL fails with 8168b when the receiver is disabled. */
8174 switch (tp->mac_version) {
8175 case RTL_GIGA_MAC_VER_11:
8176 case RTL_GIGA_MAC_VER_12:
8177 case RTL_GIGA_MAC_VER_17:
8178 pci_clear_master(tp->pci_dev);
8179
8180 RTL_W8(ChipCmd, CmdRxEnb);
8181 /* PCI commit */
8182 RTL_R8(ChipCmd);
8183 break;
8184 default:
8185 break;
8186 }
8187}
8188
1765f95d
FR		 8189static void rtl_shutdown(struct pci_dev *pdev)
8190{
861ab440 8191 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 8192 struct rtl8169_private *tp = netdev_priv(dev);
2a15cd2f 8193 struct device *d = &pdev->dev;
8194
8195 pm_runtime_get_sync(d);
861ab440
RW		 8196
8197 rtl8169_net_suspend(dev);
1765f95d 8198
cecb5fd7 8199 /* Restore original MAC address */
cc098dc7
IV		 8200 rtl_rar_set(tp, dev->perm_addr);
8201
92fc43b4 8202 rtl8169_hw_reset(tp);
4bb3f522 8203
861ab440 8204 if (system_state == SYSTEM_POWER_OFF) {
649b3b8c 8205 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
8206 rtl_wol_suspend_quirk(tp);
8207 rtl_wol_shutdown_quirk(tp);
ca52efd5 8208 }
8209
861ab440
RW		 8210 pci_wake_from_d3(pdev, true);
8211 pci_set_power_state(pdev, PCI_D3hot);
8212 }
2a15cd2f 8213
8214 pm_runtime_put_noidle(d);
861ab440 8215}
5d06a99f 8216
baf63293 8217static void rtl_remove_one(struct pci_dev *pdev)
e27566ed
FR		 8218{
8219 struct net_device *dev = pci_get_drvdata(pdev);
8220 struct rtl8169_private *tp = netdev_priv(dev);
8221
ee7a1beb
CHL		 8222 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
8223 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
935e2218
CHL		 8224 tp->mac_version == RTL_GIGA_MAC_VER_31 ||
8225 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
8226 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
8227 tp->mac_version == RTL_GIGA_MAC_VER_51) &&
ee7a1beb 8228 r8168_check_dash(tp)) {
e27566ed
FR		 8229 rtl8168_driver_stop(tp);
8230 }
8231
ad1be8d3
DN		 8232 netif_napi_del(&tp->napi);
8233
e27566ed
FR		 8234 unregister_netdev(dev);
8235
8236 rtl_release_firmware(tp);
8237
8238 if (pci_dev_run_wake(pdev))
8239 pm_runtime_get_noresume(&pdev->dev);
8240
8241 /* restore original MAC address */
8242 rtl_rar_set(tp, dev->perm_addr);
e27566ed
FR		 8243}
8244
fa9c385e 8245static const struct net_device_ops rtl_netdev_ops = {
df43ac78 8246 .ndo_open = rtl_open,
fa9c385e
FR		 8247 .ndo_stop = rtl8169_close,
8248 .ndo_get_stats64 = rtl8169_get_stats64,
8249 .ndo_start_xmit = rtl8169_start_xmit,
8250 .ndo_tx_timeout = rtl8169_tx_timeout,
8251 .ndo_validate_addr = eth_validate_addr,
8252 .ndo_change_mtu = rtl8169_change_mtu,
8253 .ndo_fix_features = rtl8169_fix_features,
8254 .ndo_set_features = rtl8169_set_features,
8255 .ndo_set_mac_address = rtl_set_mac_address,
8256 .ndo_do_ioctl = rtl8169_ioctl,
8257 .ndo_set_rx_mode = rtl_set_rx_mode,
8258#ifdef CONFIG_NET_POLL_CONTROLLER
8259 .ndo_poll_controller = rtl8169_netpoll,
8260#endif
8261
8262};
8263
31fa8b18
FR		 8264static const struct rtl_cfg_info {
8265 void (*hw_start)(struct net_device *);
8266 unsigned int region;
8267 unsigned int align;
8268 u16 event_slow;
8269 unsigned features;
50970831 8270 const struct rtl_coalesce_info *coalesce_info;
31fa8b18
FR		 8271 u8 default_ver;
8272} rtl_cfg_infos [] = {
8273 [RTL_CFG_0] = {
8274 .hw_start = rtl_hw_start_8169,
8275 .region = 1,
8276 .align = 0,
8277 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
8278 .features = RTL_FEATURE_GMII,
50970831 8279 .coalesce_info = rtl_coalesce_info_8169,
31fa8b18
FR		 8280 .default_ver = RTL_GIGA_MAC_VER_01,
8281 },
8282 [RTL_CFG_1] = {
8283 .hw_start = rtl_hw_start_8168,
8284 .region = 2,
8285 .align = 8,
8286 .event_slow = SYSErr | LinkChg | RxOverflow,
41450d46 8287 .features = RTL_FEATURE_GMII,
50970831 8288 .coalesce_info = rtl_coalesce_info_8168_8136,
31fa8b18
FR		 8289 .default_ver = RTL_GIGA_MAC_VER_11,
8290 },
8291 [RTL_CFG_2] = {
8292 .hw_start = rtl_hw_start_8101,
8293 .region = 2,
8294 .align = 8,
8295 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
8296 PCSTimeout,
50970831 8297 .coalesce_info = rtl_coalesce_info_8168_8136,
31fa8b18
FR		 8298 .default_ver = RTL_GIGA_MAC_VER_13,
8299 }
8300};
8301
41450d46 8302static int rtl_alloc_irq(struct rtl8169_private *tp)
31fa8b18
FR		 8303{
8304 void __iomem *ioaddr = tp->mmio_addr;
41450d46 8305 unsigned int flags;
31fa8b18 8306
dd8f3f61
HK		 8307 switch (tp->mac_version) {
8308 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
41450d46
HK		 8309 RTL_W8(Cfg9346, Cfg9346_Unlock);
8310 RTL_W8(Config2, RTL_R8(Config2) & ~MSIEnable);
8311 RTL_W8(Cfg9346, Cfg9346_Lock);
dd8f3f61
HK		 8312 /* fall through */
8313 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_24:
41450d46 8314 flags = PCI_IRQ_LEGACY;
dd8f3f61
HK		 8315 break;
8316 default:
41450d46 8317 flags = PCI_IRQ_ALL_TYPES;
dd8f3f61 8318 break;
31fa8b18 8319 }
41450d46
HK		 8320
8321 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
31fa8b18
FR		 8322}
8323
c558386b
HW		 8324DECLARE_RTL_COND(rtl_link_list_ready_cond)
8325{
8326 void __iomem *ioaddr = tp->mmio_addr;
8327
8328 return RTL_R8(MCU) & LINK_LIST_RDY;
8329}
8330
8331DECLARE_RTL_COND(rtl_rxtx_empty_cond)
8332{
8333 void __iomem *ioaddr = tp->mmio_addr;
8334
8335 return (RTL_R8(MCU) & RXTX_EMPTY) == RXTX_EMPTY;
8336}
8337
baf63293 8338static void rtl_hw_init_8168g(struct rtl8169_private *tp)
c558386b
HW		 8339{
8340 void __iomem *ioaddr = tp->mmio_addr;
8341 u32 data;
8342
8343 tp->ocp_base = OCP_STD_PHY_BASE;
8344
8345 RTL_W32(MISC, RTL_R32(MISC) | RXDV_GATED_EN);
8346
8347 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
8348 return;
8349
8350 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
8351 return;
8352
8353 RTL_W8(ChipCmd, RTL_R8(ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
8354 msleep(1);
8355 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
8356
5f8bcce9 8357 data = r8168_mac_ocp_read(tp, 0xe8de);
c558386b
HW		 8358 data &= ~(1 << 14);
8359 r8168_mac_ocp_write(tp, 0xe8de, data);
8360
8361 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
8362 return;
8363
5f8bcce9 8364 data = r8168_mac_ocp_read(tp, 0xe8de);
c558386b
HW		 8365 data |= (1 << 15);
8366 r8168_mac_ocp_write(tp, 0xe8de, data);
8367
8368 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
8369 return;
8370}
8371
003609da
CHL		 8372static void rtl_hw_init_8168ep(struct rtl8169_private *tp)
8373{
8374 rtl8168ep_stop_cmac(tp);
8375 rtl_hw_init_8168g(tp);
8376}
8377
baf63293 8378static void rtl_hw_initialize(struct rtl8169_private *tp)
c558386b
HW		 8379{
8380 switch (tp->mac_version) {
8381 case RTL_GIGA_MAC_VER_40:
8382 case RTL_GIGA_MAC_VER_41:
57538c4a 8383 case RTL_GIGA_MAC_VER_42:
58152cd4 8384 case RTL_GIGA_MAC_VER_43:
45dd95c4 8385 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 8386 case RTL_GIGA_MAC_VER_45:
8387 case RTL_GIGA_MAC_VER_46:
8388 case RTL_GIGA_MAC_VER_47:
8389 case RTL_GIGA_MAC_VER_48:
003609da
CHL		 8390 rtl_hw_init_8168g(tp);
8391 break;
935e2218
CHL		 8392 case RTL_GIGA_MAC_VER_49:
8393 case RTL_GIGA_MAC_VER_50:
8394 case RTL_GIGA_MAC_VER_51:
003609da 8395 rtl_hw_init_8168ep(tp);
c558386b 8396 break;
c558386b
HW		 8397 default:
8398 break;
8399 }
8400}
8401
929a031d 8402static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3b6cf25d
FR		 8403{
8404 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
8405 const unsigned int region = cfg->region;
8406 struct rtl8169_private *tp;
8407 struct mii_if_info *mii;
8408 struct net_device *dev;
8409 void __iomem *ioaddr;
8410 int chipset, i;
8411 int rc;
8412
8413 if (netif_msg_drv(&debug)) {
8414 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
8415 MODULENAME, RTL8169_VERSION);
8416 }
8417
3ef17c89
HK		 8418 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
8419 if (!dev)
8420 return -ENOMEM;
3b6cf25d
FR		 8421
8422 SET_NETDEV_DEV(dev, &pdev->dev);
fa9c385e 8423 dev->netdev_ops = &rtl_netdev_ops;
3b6cf25d
FR		 8424 tp = netdev_priv(dev);
8425 tp->dev = dev;
8426 tp->pci_dev = pdev;
8427 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
8428
8429 mii = &tp->mii;
8430 mii->dev = dev;
8431 mii->mdio_read = rtl_mdio_read;
8432 mii->mdio_write = rtl_mdio_write;
8433 mii->phy_id_mask = 0x1f;
8434 mii->reg_num_mask = 0x1f;
8435 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
8436
8437 /* disable ASPM completely as that cause random device stop working
8438 * problems as well as full system hangs for some PCIe devices users */
8439 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
8440 PCIE_LINK_STATE_CLKPM);
8441
8442 /* enable device (incl. PCI PM wakeup and hotplug setup) */
3ef17c89 8443 rc = pcim_enable_device(pdev);
3b6cf25d
FR		 8444 if (rc < 0) {
8445 netif_err(tp, probe, dev, "enable failure\n");
3ef17c89 8446 return rc;
3b6cf25d
FR		 8447 }
8448
3ef17c89 8449 if (pcim_set_mwi(pdev) < 0)
3b6cf25d
FR		 8450 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
8451
8452 /* make sure PCI base addr 1 is MMIO */
8453 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
8454 netif_err(tp, probe, dev,
8455 "region #%d not an MMIO resource, aborting\n",
8456 region);
3ef17c89 8457 return -ENODEV;
3b6cf25d
FR		 8458 }
8459
8460 /* check for weird/broken PCI region reporting */
8461 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
8462 netif_err(tp, probe, dev,
8463 "Invalid PCI region size(s), aborting\n");
3ef17c89 8464 return -ENODEV;
3b6cf25d
FR		 8465 }
8466
8467 rc = pci_request_regions(pdev, MODULENAME);
8468 if (rc < 0) {
8469 netif_err(tp, probe, dev, "could not request regions\n");
3ef17c89 8470 return rc;
3b6cf25d
FR		 8471 }
8472
3b6cf25d 8473 /* ioremap MMIO region */
3ef17c89
HK		 8474 ioaddr = devm_ioremap(&pdev->dev, pci_resource_start(pdev, region),
8475 R8169_REGS_SIZE);
3b6cf25d
FR		 8476 if (!ioaddr) {
8477 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
3ef17c89 8478 return -EIO;
3b6cf25d
FR		 8479 }
8480 tp->mmio_addr = ioaddr;
8481
8482 if (!pci_is_pcie(pdev))
8483 netif_info(tp, probe, dev, "not PCI Express\n");
8484
8485 /* Identify chip attached to board */
8486 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
8487
27896c83
AB		 8488 tp->cp_cmd = 0;
8489
8490 if ((sizeof(dma_addr_t) > 4) &&
8491 (use_dac == 1 || (use_dac == -1 && pci_is_pcie(pdev) &&
8492 tp->mac_version >= RTL_GIGA_MAC_VER_18)) &&
f0076436
AB		 8493 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
8494 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
27896c83
AB		 8495
8496 /* CPlusCmd Dual Access Cycle is only needed for non-PCIe */
8497 if (!pci_is_pcie(pdev))
8498 tp->cp_cmd |= PCIDAC;
8499 dev->features |= NETIF_F_HIGHDMA;
8500 } else {
8501 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
8502 if (rc < 0) {
8503 netif_err(tp, probe, dev, "DMA configuration failed\n");
3ef17c89 8504 return rc;
27896c83
AB		 8505 }
8506 }
8507
3b6cf25d
FR		 8508 rtl_init_rxcfg(tp);
8509
8510 rtl_irq_disable(tp);
8511
c558386b
HW		 8512 rtl_hw_initialize(tp);
8513
3b6cf25d
FR		 8514 rtl_hw_reset(tp);
8515
8516 rtl_ack_events(tp, 0xffff);
8517
8518 pci_set_master(pdev);
8519
3b6cf25d
FR		 8520 rtl_init_mdio_ops(tp);
8521 rtl_init_pll_power_ops(tp);
8522 rtl_init_jumbo_ops(tp);
beb1fe18 8523 rtl_init_csi_ops(tp);
3b6cf25d
FR		 8524
8525 rtl8169_print_mac_version(tp);
8526
8527 chipset = tp->mac_version;
8528 tp->txd_version = rtl_chip_infos[chipset].txd_version;
8529
41450d46
HK		 8530 rc = rtl_alloc_irq(tp);
8531 if (rc < 0) {
8532 netif_err(tp, probe, dev, "Can't allocate interrupt\n");
8533 return rc;
8534 }
3b6cf25d 8535
e593cea7 8536 tp->saved_wolopts = __rtl8169_get_wol(tp);
0e7bb68b 8537
3b6cf25d
FR		 8538 if (rtl_tbi_enabled(tp)) {
8539 tp->set_speed = rtl8169_set_speed_tbi;
6fa1ba61 8540 tp->get_link_ksettings = rtl8169_get_link_ksettings_tbi;
3b6cf25d
FR		 8541 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
8542 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
8543 tp->link_ok = rtl8169_tbi_link_ok;
8544 tp->do_ioctl = rtl_tbi_ioctl;
8545 } else {
8546 tp->set_speed = rtl8169_set_speed_xmii;
6fa1ba61 8547 tp->get_link_ksettings = rtl8169_get_link_ksettings_xmii;
3b6cf25d
FR		 8548 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
8549 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
8550 tp->link_ok = rtl8169_xmii_link_ok;
8551 tp->do_ioctl = rtl_xmii_ioctl;
8552 }
8553
8554 mutex_init(&tp->wk.mutex);
340fea3d
KM		 8555 u64_stats_init(&tp->rx_stats.syncp);
8556 u64_stats_init(&tp->tx_stats.syncp);
3b6cf25d
FR		 8557
8558 /* Get MAC address */
89cceb27
CHL		 8559 if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
8560 tp->mac_version == RTL_GIGA_MAC_VER_36 ||
8561 tp->mac_version == RTL_GIGA_MAC_VER_37 ||
8562 tp->mac_version == RTL_GIGA_MAC_VER_38 ||
8563 tp->mac_version == RTL_GIGA_MAC_VER_40 ||
8564 tp->mac_version == RTL_GIGA_MAC_VER_41 ||
8565 tp->mac_version == RTL_GIGA_MAC_VER_42 ||
8566 tp->mac_version == RTL_GIGA_MAC_VER_43 ||
8567 tp->mac_version == RTL_GIGA_MAC_VER_44 ||
8568 tp->mac_version == RTL_GIGA_MAC_VER_45 ||
6e1d0b89
CHL		 8569 tp->mac_version == RTL_GIGA_MAC_VER_46 ||
8570 tp->mac_version == RTL_GIGA_MAC_VER_47 ||
935e2218
CHL		 8571 tp->mac_version == RTL_GIGA_MAC_VER_48 ||
8572 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
8573 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
8574 tp->mac_version == RTL_GIGA_MAC_VER_51) {
6e1d0b89
CHL		 8575 u16 mac_addr[3];
8576
05b9687b
CHL		 8577 *(u32 *)&mac_addr[0] = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC);
8578 *(u16 *)&mac_addr[2] = rtl_eri_read(tp, 0xe4, ERIAR_EXGMAC);
6e1d0b89
CHL		 8579
8580 if (is_valid_ether_addr((u8 *)mac_addr))
8581 rtl_rar_set(tp, (u8 *)mac_addr);
8582 }
3b6cf25d
FR		 8583 for (i = 0; i < ETH_ALEN; i++)
8584 dev->dev_addr[i] = RTL_R8(MAC0 + i);
3b6cf25d 8585
7ad24ea4 8586 dev->ethtool_ops = &rtl8169_ethtool_ops;
3b6cf25d 8587 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3b6cf25d
FR		 8588
8589 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
8590
8591 /* don't enable SG, IP_CSUM and TSO by default - it might not work
8592 * properly for all devices */
8593 dev->features |= NETIF_F_RXCSUM |
f646968f 8594 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d
FR		 8595
8596 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
f646968f
PM		 8597 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
8598 NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d
FR		 8599 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
8600 NETIF_F_HIGHDMA;
e624bd8c 8601 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
3b6cf25d 8602
929a031d 8603 tp->cp_cmd |= RxChkSum | RxVlan;
8604
8605 /*
8606 * Pretend we are using VLANs; This bypasses a nasty bug where
8607 * Interrupts stop flowing on high load on 8110SCd controllers.
8608 */
3b6cf25d 8609 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
929a031d 8610 /* Disallow toggling */
f646968f 8611 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d 8612
5888d3fc 8613 if (tp->txd_version == RTL_TD_0)
8614 tp->tso_csum = rtl8169_tso_csum_v1;
e974604b 8615 else if (tp->txd_version == RTL_TD_1) {
5888d3fc 8616 tp->tso_csum = rtl8169_tso_csum_v2;
e974604b 8617 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
8618 } else
5888d3fc 8619 WARN_ON_ONCE(1);
8620
3b6cf25d
FR		 8621 dev->hw_features |= NETIF_F_RXALL;
8622 dev->hw_features |= NETIF_F_RXFCS;
8623
c7315a95
JW		 8624 /* MTU range: 60 - hw-specific max */
8625 dev->min_mtu = ETH_ZLEN;
8626 dev->max_mtu = rtl_chip_infos[chipset].jumbo_max;
8627
3b6cf25d
FR		 8628 tp->hw_start = cfg->hw_start;
8629 tp->event_slow = cfg->event_slow;
50970831 8630 tp->coalesce_info = cfg->coalesce_info;
3b6cf25d
FR		 8631
8632 tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
8633 ~(RxBOVF | RxFOVF) : ~0;
8634
9de36ccf 8635 timer_setup(&tp->timer, rtl8169_phy_timer, 0);
3b6cf25d
FR		 8636
8637 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
8638
3ef17c89
HK		 8639 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
8640 &tp->counters_phys_addr,
8641 GFP_KERNEL);
a4870c71
HK		 8642 if (!tp->counters)
8643 return -ENOMEM;
42020320 8644
b99d3b7b
HK		 8645 pci_set_drvdata(pdev, dev);
8646
3b6cf25d
FR		 8647 rc = register_netdev(dev);
8648 if (rc < 0)
a4870c71 8649 return rc;
3b6cf25d 8650
92a7c4e7
FR		 8651 netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
8652 rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
d18c4419
HK		 8653 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff),
8654 pci_irq_vector(pdev, 0));
3b6cf25d
FR		 8655 if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
8656 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
8657 "tx checksumming: %s]\n",
8658 rtl_chip_infos[chipset].jumbo_max,
8659 rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
8660 }
8661
ee7a1beb
CHL		 8662 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
8663 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
935e2218
CHL		 8664 tp->mac_version == RTL_GIGA_MAC_VER_31 ||
8665 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
8666 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
8667 tp->mac_version == RTL_GIGA_MAC_VER_51) &&
ee7a1beb 8668 r8168_check_dash(tp)) {
3b6cf25d
FR		 8669 rtl8168_driver_start(tp);
8670 }
8671
3b6cf25d
FR		 8672 if (pci_dev_run_wake(pdev))
8673 pm_runtime_put_noidle(&pdev->dev);
8674
8675 netif_carrier_off(dev);
8676
3ef17c89 8677 return 0;
3b6cf25d
FR		 8678}
8679
1da177e4
LT		 8680static struct pci_driver rtl8169_pci_driver = {
8681 .name = MODULENAME,
8682 .id_table = rtl8169_pci_tbl,
3b6cf25d 8683 .probe = rtl_init_one,
baf63293 8684 .remove = rtl_remove_one,
1765f95d 8685 .shutdown = rtl_shutdown,
861ab440 8686 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 8687};
8688
3eeb7da9 8689module_pci_driver(rtl8169_pci_driver);
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