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Merge branch 'davem-next.r8169' of git://violet.fr.zoreil.com/romieu/linux
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / realtek / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
a6b7a407 25#include <linux/interrupt.h>
1da177e4 26#include <linux/dma-mapping.h>
e1759441 27#include <linux/pm_runtime.h>
bca03d5f 28#include <linux/firmware.h>
ba04c7c9 29#include <linux/pci-aspm.h>
70c71606 30#include <linux/prefetch.h>
1da177e4
LT		 31
32#include <asm/io.h>
33#include <asm/irq.h>
34
865c652d 35#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 36#define MODULENAME "r8169"
37#define PFX MODULENAME ": "
38
bca03d5f 39#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
40#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
01dc7fec 41#define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
42#define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
70090424 43#define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
c2218925
HW		 44#define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
45#define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
5a5e4443 46#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
7e18dca1 47#define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
b3d7b2f2 48#define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
5598bfe5 49#define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
c558386b 50#define FIRMWARE_8168G_1 "rtl_nic/rtl8168g-1.fw"
bca03d5f 51
1da177e4
LT		 52#ifdef RTL8169_DEBUG
53#define assert(expr) \
5b0384f4
FR		 54 if (!(expr)) { \
55 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
b39d66a8 56 #expr,__FILE__,__func__,__LINE__); \
5b0384f4 57 }
06fa7358
JP		 58#define dprintk(fmt, args...) \
59 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 60#else
61#define assert(expr) do {} while (0)
62#define dprintk(fmt, args...) do {} while (0)
63#endif /* RTL8169_DEBUG */
64
b57b7e5a 65#define R8169_MSG_DEFAULT \
f0e837d9 66 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 67
477206a0
JD		 68#define TX_SLOTS_AVAIL(tp) \
69 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
70
71/* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
72#define TX_FRAGS_READY_FOR(tp,nr_frags) \
73 (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
1da177e4 74
1da177e4
LT		 75/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
76 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 77static const int multicast_filter_limit = 32;
1da177e4 78
9c14ceaf 79#define MAX_READ_REQUEST_SHIFT 12
1da177e4 80#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
1da177e4
LT		 81#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
82#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
83
84#define R8169_REGS_SIZE 256
85#define R8169_NAPI_WEIGHT 64
86#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
87#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
88#define RX_BUF_SIZE 1536 /* Rx Buffer size */
89#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
90#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
91
92#define RTL8169_TX_TIMEOUT (6*HZ)
93#define RTL8169_PHY_TIMEOUT (10*HZ)
94
ea8dbdd1 95#define RTL_EEPROM_SIG cpu_to_le32(0x8129)
96#define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
e1564ec9
FR		 97#define RTL_EEPROM_SIG_ADDR 0x0000
98
1da177e4
LT		 99/* write/read MMIO register */
100#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
101#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
102#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
103#define RTL_R8(reg) readb (ioaddr + (reg))
104#define RTL_R16(reg) readw (ioaddr + (reg))
06f555f3 105#define RTL_R32(reg) readl (ioaddr + (reg))
1da177e4
LT		 106
107enum mac_version {
85bffe6c
FR		 108 RTL_GIGA_MAC_VER_01 = 0,
109 RTL_GIGA_MAC_VER_02,
110 RTL_GIGA_MAC_VER_03,
111 RTL_GIGA_MAC_VER_04,
112 RTL_GIGA_MAC_VER_05,
113 RTL_GIGA_MAC_VER_06,
114 RTL_GIGA_MAC_VER_07,
115 RTL_GIGA_MAC_VER_08,
116 RTL_GIGA_MAC_VER_09,
117 RTL_GIGA_MAC_VER_10,
118 RTL_GIGA_MAC_VER_11,
119 RTL_GIGA_MAC_VER_12,
120 RTL_GIGA_MAC_VER_13,
121 RTL_GIGA_MAC_VER_14,
122 RTL_GIGA_MAC_VER_15,
123 RTL_GIGA_MAC_VER_16,
124 RTL_GIGA_MAC_VER_17,
125 RTL_GIGA_MAC_VER_18,
126 RTL_GIGA_MAC_VER_19,
127 RTL_GIGA_MAC_VER_20,
128 RTL_GIGA_MAC_VER_21,
129 RTL_GIGA_MAC_VER_22,
130 RTL_GIGA_MAC_VER_23,
131 RTL_GIGA_MAC_VER_24,
132 RTL_GIGA_MAC_VER_25,
133 RTL_GIGA_MAC_VER_26,
134 RTL_GIGA_MAC_VER_27,
135 RTL_GIGA_MAC_VER_28,
136 RTL_GIGA_MAC_VER_29,
137 RTL_GIGA_MAC_VER_30,
138 RTL_GIGA_MAC_VER_31,
139 RTL_GIGA_MAC_VER_32,
140 RTL_GIGA_MAC_VER_33,
70090424 141 RTL_GIGA_MAC_VER_34,
c2218925
HW		 142 RTL_GIGA_MAC_VER_35,
143 RTL_GIGA_MAC_VER_36,
7e18dca1 144 RTL_GIGA_MAC_VER_37,
b3d7b2f2 145 RTL_GIGA_MAC_VER_38,
5598bfe5 146 RTL_GIGA_MAC_VER_39,
c558386b
HW		 147 RTL_GIGA_MAC_VER_40,
148 RTL_GIGA_MAC_VER_41,
85bffe6c 149 RTL_GIGA_MAC_NONE = 0xff,
1da177e4
LT		 150};
151
2b7b4318
FR		 152enum rtl_tx_desc_version {
153 RTL_TD_0 = 0,
154 RTL_TD_1 = 1,
155};
156
d58d46b5
FR		 157#define JUMBO_1K ETH_DATA_LEN
158#define JUMBO_4K (4*1024 - ETH_HLEN - 2)
159#define JUMBO_6K (6*1024 - ETH_HLEN - 2)
160#define JUMBO_7K (7*1024 - ETH_HLEN - 2)
161#define JUMBO_9K (9*1024 - ETH_HLEN - 2)
162
163#define _R(NAME,TD,FW,SZ,B) { \
164 .name = NAME, \
165 .txd_version = TD, \
166 .fw_name = FW, \
167 .jumbo_max = SZ, \
168 .jumbo_tx_csum = B \
169}
1da177e4 170
3c6bee1d 171static const struct {
1da177e4 172 const char *name;
2b7b4318 173 enum rtl_tx_desc_version txd_version;
953a12cc 174 const char *fw_name;
d58d46b5
FR		 175 u16 jumbo_max;
176 bool jumbo_tx_csum;
85bffe6c
FR		 177} rtl_chip_infos[] = {
178 /* PCI devices. */
179 [RTL_GIGA_MAC_VER_01] =
d58d46b5 180 _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 181 [RTL_GIGA_MAC_VER_02] =
d58d46b5 182 _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 183 [RTL_GIGA_MAC_VER_03] =
d58d46b5 184 _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 185 [RTL_GIGA_MAC_VER_04] =
d58d46b5 186 _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 187 [RTL_GIGA_MAC_VER_05] =
d58d46b5 188 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 189 [RTL_GIGA_MAC_VER_06] =
d58d46b5 190 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c
FR		 191 /* PCI-E devices. */
192 [RTL_GIGA_MAC_VER_07] =
d58d46b5 193 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 194 [RTL_GIGA_MAC_VER_08] =
d58d46b5 195 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 196 [RTL_GIGA_MAC_VER_09] =
d58d46b5 197 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 198 [RTL_GIGA_MAC_VER_10] =
d58d46b5 199 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 200 [RTL_GIGA_MAC_VER_11] =
d58d46b5 201 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
85bffe6c 202 [RTL_GIGA_MAC_VER_12] =
d58d46b5 203 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
85bffe6c 204 [RTL_GIGA_MAC_VER_13] =
d58d46b5 205 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 206 [RTL_GIGA_MAC_VER_14] =
d58d46b5 207 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 208 [RTL_GIGA_MAC_VER_15] =
d58d46b5 209 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 210 [RTL_GIGA_MAC_VER_16] =
d58d46b5 211 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 212 [RTL_GIGA_MAC_VER_17] =
d58d46b5 213 _R("RTL8168b/8111b", RTL_TD_1, NULL, JUMBO_4K, false),
85bffe6c 214 [RTL_GIGA_MAC_VER_18] =
d58d46b5 215 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 216 [RTL_GIGA_MAC_VER_19] =
d58d46b5 217 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 218 [RTL_GIGA_MAC_VER_20] =
d58d46b5 219 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 220 [RTL_GIGA_MAC_VER_21] =
d58d46b5 221 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 222 [RTL_GIGA_MAC_VER_22] =
d58d46b5 223 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 224 [RTL_GIGA_MAC_VER_23] =
d58d46b5 225 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 226 [RTL_GIGA_MAC_VER_24] =
d58d46b5 227 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 228 [RTL_GIGA_MAC_VER_25] =
d58d46b5
FR		 229 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1,
230 JUMBO_9K, false),
85bffe6c 231 [RTL_GIGA_MAC_VER_26] =
d58d46b5
FR		 232 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2,
233 JUMBO_9K, false),
85bffe6c 234 [RTL_GIGA_MAC_VER_27] =
d58d46b5 235 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 236 [RTL_GIGA_MAC_VER_28] =
d58d46b5 237 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 238 [RTL_GIGA_MAC_VER_29] =
d58d46b5
FR		 239 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
240 JUMBO_1K, true),
85bffe6c 241 [RTL_GIGA_MAC_VER_30] =
d58d46b5
FR		 242 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
243 JUMBO_1K, true),
85bffe6c 244 [RTL_GIGA_MAC_VER_31] =
d58d46b5 245 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 246 [RTL_GIGA_MAC_VER_32] =
d58d46b5
FR		 247 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1,
248 JUMBO_9K, false),
85bffe6c 249 [RTL_GIGA_MAC_VER_33] =
d58d46b5
FR		 250 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2,
251 JUMBO_9K, false),
70090424 252 [RTL_GIGA_MAC_VER_34] =
d58d46b5
FR		 253 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
254 JUMBO_9K, false),
c2218925 255 [RTL_GIGA_MAC_VER_35] =
d58d46b5
FR		 256 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1,
257 JUMBO_9K, false),
c2218925 258 [RTL_GIGA_MAC_VER_36] =
d58d46b5
FR		 259 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2,
260 JUMBO_9K, false),
7e18dca1
HW		 261 [RTL_GIGA_MAC_VER_37] =
262 _R("RTL8402", RTL_TD_1, FIRMWARE_8402_1,
263 JUMBO_1K, true),
b3d7b2f2
HW		 264 [RTL_GIGA_MAC_VER_38] =
265 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_1,
266 JUMBO_9K, false),
5598bfe5
HW		 267 [RTL_GIGA_MAC_VER_39] =
268 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_1,
269 JUMBO_1K, true),
c558386b
HW		 270 [RTL_GIGA_MAC_VER_40] =
271 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_1,
272 JUMBO_9K, false),
273 [RTL_GIGA_MAC_VER_41] =
274 _R("RTL8168g/8111g", RTL_TD_1, NULL, JUMBO_9K, false),
953a12cc 275};
85bffe6c 276#undef _R
953a12cc 277
bcf0bf90
FR		 278enum cfg_version {
279 RTL_CFG_0 = 0x00,
280 RTL_CFG_1,
281 RTL_CFG_2
282};
283
a3aa1884 284static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
bcf0bf90 285 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 286 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 287 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 288 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90
FR		 289 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
290 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
93a3aa25 291 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
bc1660b5 292 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 293 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
294 { PCI_VENDOR_ID_LINKSYS, 0x1032,
295 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 296 { 0x0001, 0x8168,
297 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 298 {0,},
299};
300
301MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
302
6f0333b8 303static int rx_buf_sz = 16383;
4300e8c7 304static int use_dac;
b57b7e5a
SH		 305static struct {
306 u32 msg_enable;
307} debug = { -1 };
1da177e4 308
07d3f51f
FR		 309enum rtl_registers {
310 MAC0 = 0, /* Ethernet hardware address. */
773d2021 311 MAC4 = 4,
07d3f51f
FR		 312 MAR0 = 8, /* Multicast filter. */
313 CounterAddrLow = 0x10,
314 CounterAddrHigh = 0x14,
315 TxDescStartAddrLow = 0x20,
316 TxDescStartAddrHigh = 0x24,
317 TxHDescStartAddrLow = 0x28,
318 TxHDescStartAddrHigh = 0x2c,
319 FLASH = 0x30,
320 ERSR = 0x36,
321 ChipCmd = 0x37,
322 TxPoll = 0x38,
323 IntrMask = 0x3c,
324 IntrStatus = 0x3e,
4f6b00e5 325
07d3f51f 326 TxConfig = 0x40,
4f6b00e5
HW		 327#define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
328#define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
2b7b4318 329
4f6b00e5
HW		 330 RxConfig = 0x44,
331#define RX128_INT_EN (1 << 15) /* 8111c and later */
332#define RX_MULTI_EN (1 << 14) /* 8111c only */
333#define RXCFG_FIFO_SHIFT 13
334 /* No threshold before first PCI xfer */
335#define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
336#define RXCFG_DMA_SHIFT 8
337 /* Unlimited maximum PCI burst. */
338#define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
2b7b4318 339
07d3f51f
FR		 340 RxMissed = 0x4c,
341 Cfg9346 = 0x50,
342 Config0 = 0x51,
343 Config1 = 0x52,
344 Config2 = 0x53,
d387b427
FR		 345#define PME_SIGNAL (1 << 5) /* 8168c and later */
346
07d3f51f
FR		 347 Config3 = 0x54,
348 Config4 = 0x55,
349 Config5 = 0x56,
350 MultiIntr = 0x5c,
351 PHYAR = 0x60,
07d3f51f
FR		 352 PHYstatus = 0x6c,
353 RxMaxSize = 0xda,
354 CPlusCmd = 0xe0,
355 IntrMitigate = 0xe2,
356 RxDescAddrLow = 0xe4,
357 RxDescAddrHigh = 0xe8,
f0298f81 358 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
359
360#define NoEarlyTx 0x3f /* Max value : no early transmit. */
361
362 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
363
364#define TxPacketMax (8064 >> 7)
3090bd9a 365#define EarlySize 0x27
f0298f81 366
07d3f51f
FR		 367 FuncEvent = 0xf0,
368 FuncEventMask = 0xf4,
369 FuncPresetState = 0xf8,
370 FuncForceEvent = 0xfc,
1da177e4
LT		 371};
372
f162a5d1
FR		 373enum rtl8110_registers {
374 TBICSR = 0x64,
375 TBI_ANAR = 0x68,
376 TBI_LPAR = 0x6a,
377};
378
379enum rtl8168_8101_registers {
380 CSIDR = 0x64,
381 CSIAR = 0x68,
382#define CSIAR_FLAG 0x80000000
383#define CSIAR_WRITE_CMD 0x80000000
384#define CSIAR_BYTE_ENABLE 0x0f
385#define CSIAR_BYTE_ENABLE_SHIFT 12
386#define CSIAR_ADDR_MASK 0x0fff
7e18dca1
HW		 387#define CSIAR_FUNC_CARD 0x00000000
388#define CSIAR_FUNC_SDIO 0x00010000
389#define CSIAR_FUNC_NIC 0x00020000
065c27c1 390 PMCH = 0x6f,
f162a5d1
FR		 391 EPHYAR = 0x80,
392#define EPHYAR_FLAG 0x80000000
393#define EPHYAR_WRITE_CMD 0x80000000
394#define EPHYAR_REG_MASK 0x1f
395#define EPHYAR_REG_SHIFT 16
396#define EPHYAR_DATA_MASK 0xffff
5a5e4443 397 DLLPR = 0xd0,
4f6b00e5 398#define PFM_EN (1 << 6)
f162a5d1
FR		 399 DBG_REG = 0xd1,
400#define FIX_NAK_1 (1 << 4)
401#define FIX_NAK_2 (1 << 3)
5a5e4443
HW		 402 TWSI = 0xd2,
403 MCU = 0xd3,
4f6b00e5 404#define NOW_IS_OOB (1 << 7)
c558386b
HW		 405#define TX_EMPTY (1 << 5)
406#define RX_EMPTY (1 << 4)
407#define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
5a5e4443
HW		 408#define EN_NDP (1 << 3)
409#define EN_OOB_RESET (1 << 2)
c558386b 410#define LINK_LIST_RDY (1 << 1)
daf9df6d 411 EFUSEAR = 0xdc,
412#define EFUSEAR_FLAG 0x80000000
413#define EFUSEAR_WRITE_CMD 0x80000000
414#define EFUSEAR_READ_CMD 0x00000000
415#define EFUSEAR_REG_MASK 0x03ff
416#define EFUSEAR_REG_SHIFT 8
417#define EFUSEAR_DATA_MASK 0xff
f162a5d1
FR		 418};
419
c0e45c1c 420enum rtl8168_registers {
4f6b00e5
HW		 421 LED_FREQ = 0x1a,
422 EEE_LED = 0x1b,
b646d900 423 ERIDR = 0x70,
424 ERIAR = 0x74,
425#define ERIAR_FLAG 0x80000000
426#define ERIAR_WRITE_CMD 0x80000000
427#define ERIAR_READ_CMD 0x00000000
428#define ERIAR_ADDR_BYTE_ALIGN 4
b646d900 429#define ERIAR_TYPE_SHIFT 16
4f6b00e5
HW		 430#define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
431#define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
432#define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
433#define ERIAR_MASK_SHIFT 12
434#define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
435#define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
c558386b 436#define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
4f6b00e5 437#define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
c0e45c1c 438 EPHY_RXER_NUM = 0x7c,
439 OCPDR = 0xb0, /* OCP GPHY access */
440#define OCPDR_WRITE_CMD 0x80000000
441#define OCPDR_READ_CMD 0x00000000
442#define OCPDR_REG_MASK 0x7f
443#define OCPDR_GPHY_REG_SHIFT 16
444#define OCPDR_DATA_MASK 0xffff
445 OCPAR = 0xb4,
446#define OCPAR_FLAG 0x80000000
447#define OCPAR_GPHY_WRITE_CMD 0x8000f060
448#define OCPAR_GPHY_READ_CMD 0x0000f060
c558386b 449 GPHY_OCP = 0xb8,
01dc7fec 450 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
451 MISC = 0xf0, /* 8168e only. */
cecb5fd7 452#define TXPLA_RST (1 << 29)
5598bfe5 453#define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
4f6b00e5 454#define PWM_EN (1 << 22)
c558386b 455#define RXDV_GATED_EN (1 << 19)
5598bfe5 456#define EARLY_TALLY_EN (1 << 16)
c0e45c1c 457};
458
07d3f51f 459enum rtl_register_content {
1da177e4 460 /* InterruptStatusBits */
07d3f51f
FR		 461 SYSErr = 0x8000,
462 PCSTimeout = 0x4000,
463 SWInt = 0x0100,
464 TxDescUnavail = 0x0080,
465 RxFIFOOver = 0x0040,
466 LinkChg = 0x0020,
467 RxOverflow = 0x0010,
468 TxErr = 0x0008,
469 TxOK = 0x0004,
470 RxErr = 0x0002,
471 RxOK = 0x0001,
1da177e4
LT		 472
473 /* RxStatusDesc */
e03f33af 474 RxBOVF = (1 << 24),
9dccf611
FR		 475 RxFOVF = (1 << 23),
476 RxRWT = (1 << 22),
477 RxRES = (1 << 21),
478 RxRUNT = (1 << 20),
479 RxCRC = (1 << 19),
1da177e4
LT		 480
481 /* ChipCmdBits */
4f6b00e5 482 StopReq = 0x80,
07d3f51f
FR		 483 CmdReset = 0x10,
484 CmdRxEnb = 0x08,
485 CmdTxEnb = 0x04,
486 RxBufEmpty = 0x01,
1da177e4 487
275391a4
FR		 488 /* TXPoll register p.5 */
489 HPQ = 0x80, /* Poll cmd on the high prio queue */
490 NPQ = 0x40, /* Poll cmd on the low prio queue */
491 FSWInt = 0x01, /* Forced software interrupt */
492
1da177e4 493 /* Cfg9346Bits */
07d3f51f
FR		 494 Cfg9346_Lock = 0x00,
495 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 496
497 /* rx_mode_bits */
07d3f51f
FR		 498 AcceptErr = 0x20,
499 AcceptRunt = 0x10,
500 AcceptBroadcast = 0x08,
501 AcceptMulticast = 0x04,
502 AcceptMyPhys = 0x02,
503 AcceptAllPhys = 0x01,
1687b566 504#define RX_CONFIG_ACCEPT_MASK 0x3f
1da177e4 505
1da177e4
LT		 506 /* TxConfigBits */
507 TxInterFrameGapShift = 24,
508 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
509
5d06a99f 510 /* Config1 register p.24 */
f162a5d1
FR		 511 LEDS1 = (1 << 7),
512 LEDS0 = (1 << 6),
f162a5d1
FR		 513 Speed_down = (1 << 4),
514 MEMMAP = (1 << 3),
515 IOMAP = (1 << 2),
516 VPD = (1 << 1),
5d06a99f
FR		 517 PMEnable = (1 << 0), /* Power Management Enable */
518
6dccd16b 519 /* Config2 register p. 25 */
2ca6cf06 520 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
6dccd16b
FR		 521 PCI_Clock_66MHz = 0x01,
522 PCI_Clock_33MHz = 0x00,
523
61a4dcc2
FR		 524 /* Config3 register p.25 */
525 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
526 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
d58d46b5 527 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
f162a5d1 528 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 529
d58d46b5
FR		 530 /* Config4 register */
531 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
532
5d06a99f 533 /* Config5 register p.27 */
61a4dcc2
FR		 534 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
535 MWF = (1 << 5), /* Accept Multicast wakeup frame */
536 UWF = (1 << 4), /* Accept Unicast wakeup frame */
cecb5fd7 537 Spi_en = (1 << 3),
61a4dcc2 538 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 539 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
540
1da177e4
LT		 541 /* TBICSR p.28 */
542 TBIReset = 0x80000000,
543 TBILoopback = 0x40000000,
544 TBINwEnable = 0x20000000,
545 TBINwRestart = 0x10000000,
546 TBILinkOk = 0x02000000,
547 TBINwComplete = 0x01000000,
548
549 /* CPlusCmd p.31 */
f162a5d1
FR		 550 EnableBist = (1 << 15), // 8168 8101
551 Mac_dbgo_oe = (1 << 14), // 8168 8101
552 Normal_mode = (1 << 13), // unused
553 Force_half_dup = (1 << 12), // 8168 8101
554 Force_rxflow_en = (1 << 11), // 8168 8101
555 Force_txflow_en = (1 << 10), // 8168 8101
556 Cxpl_dbg_sel = (1 << 9), // 8168 8101
557 ASF = (1 << 8), // 8168 8101
558 PktCntrDisable = (1 << 7), // 8168 8101
559 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 560 RxVlan = (1 << 6),
561 RxChkSum = (1 << 5),
562 PCIDAC = (1 << 4),
563 PCIMulRW = (1 << 3),
0e485150
FR		 564 INTT_0 = 0x0000, // 8168
565 INTT_1 = 0x0001, // 8168
566 INTT_2 = 0x0002, // 8168
567 INTT_3 = 0x0003, // 8168
1da177e4
LT		 568
569 /* rtl8169_PHYstatus */
07d3f51f
FR		 570 TBI_Enable = 0x80,
571 TxFlowCtrl = 0x40,
572 RxFlowCtrl = 0x20,
573 _1000bpsF = 0x10,
574 _100bps = 0x08,
575 _10bps = 0x04,
576 LinkStatus = 0x02,
577 FullDup = 0x01,
1da177e4 578
1da177e4 579 /* _TBICSRBit */
07d3f51f 580 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 581
582 /* DumpCounterCommand */
07d3f51f 583 CounterDump = 0x8,
1da177e4
LT		 584};
585
2b7b4318
FR		 586enum rtl_desc_bit {
587 /* First doubleword. */
1da177e4
LT		 588 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
589 RingEnd = (1 << 30), /* End of descriptor ring */
590 FirstFrag = (1 << 29), /* First segment of a packet */
591 LastFrag = (1 << 28), /* Final segment of a packet */
2b7b4318
FR		 592};
593
594/* Generic case. */
595enum rtl_tx_desc_bit {
596 /* First doubleword. */
597 TD_LSO = (1 << 27), /* Large Send Offload */
598#define TD_MSS_MAX 0x07ffu /* MSS value */
1da177e4 599
2b7b4318
FR		 600 /* Second doubleword. */
601 TxVlanTag = (1 << 17), /* Add VLAN tag */
602};
603
604/* 8169, 8168b and 810x except 8102e. */
605enum rtl_tx_desc_bit_0 {
606 /* First doubleword. */
607#define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
608 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
609 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
610 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
611};
612
613/* 8102e, 8168c and beyond. */
614enum rtl_tx_desc_bit_1 {
615 /* Second doubleword. */
616#define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
617 TD1_IP_CS = (1 << 29), /* Calculate IP checksum */
618 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
619 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
620};
1da177e4 621
2b7b4318
FR		 622static const struct rtl_tx_desc_info {
623 struct {
624 u32 udp;
625 u32 tcp;
626 } checksum;
627 u16 mss_shift;
628 u16 opts_offset;
629} tx_desc_info [] = {
630 [RTL_TD_0] = {
631 .checksum = {
632 .udp = TD0_IP_CS | TD0_UDP_CS,
633 .tcp = TD0_IP_CS | TD0_TCP_CS
634 },
635 .mss_shift = TD0_MSS_SHIFT,
636 .opts_offset = 0
637 },
638 [RTL_TD_1] = {
639 .checksum = {
640 .udp = TD1_IP_CS | TD1_UDP_CS,
641 .tcp = TD1_IP_CS | TD1_TCP_CS
642 },
643 .mss_shift = TD1_MSS_SHIFT,
644 .opts_offset = 1
645 }
646};
647
648enum rtl_rx_desc_bit {
1da177e4
LT		 649 /* Rx private */
650 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
651 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
652
653#define RxProtoUDP (PID1)
654#define RxProtoTCP (PID0)
655#define RxProtoIP (PID1 | PID0)
656#define RxProtoMask RxProtoIP
657
658 IPFail = (1 << 16), /* IP checksum failed */
659 UDPFail = (1 << 15), /* UDP/IP checksum failed */
660 TCPFail = (1 << 14), /* TCP/IP checksum failed */
661 RxVlanTag = (1 << 16), /* VLAN tag available */
662};
663
664#define RsvdMask 0x3fffc000
665
666struct TxDesc {
6cccd6e7
REB		 667 __le32 opts1;
668 __le32 opts2;
669 __le64 addr;
1da177e4
LT		 670};
671
672struct RxDesc {
6cccd6e7
REB		 673 __le32 opts1;
674 __le32 opts2;
675 __le64 addr;
1da177e4
LT		 676};
677
678struct ring_info {
679 struct sk_buff *skb;
680 u32 len;
681 u8 __pad[sizeof(void *) - sizeof(u32)];
682};
683
f23e7fda 684enum features {
ccdffb9a
FR		 685 RTL_FEATURE_WOL = (1 << 0),
686 RTL_FEATURE_MSI = (1 << 1),
687 RTL_FEATURE_GMII = (1 << 2),
f23e7fda
FR		 688};
689
355423d0
IV		 690struct rtl8169_counters {
691 __le64 tx_packets;
692 __le64 rx_packets;
693 __le64 tx_errors;
694 __le32 rx_errors;
695 __le16 rx_missed;
696 __le16 align_errors;
697 __le32 tx_one_collision;
698 __le32 tx_multi_collision;
699 __le64 rx_unicast;
700 __le64 rx_broadcast;
701 __le32 rx_multicast;
702 __le16 tx_aborted;
703 __le16 tx_underun;
704};
705
da78dbff 706enum rtl_flag {
6c4a70c5 707 RTL_FLAG_TASK_ENABLED,
da78dbff
FR		 708 RTL_FLAG_TASK_SLOW_PENDING,
709 RTL_FLAG_TASK_RESET_PENDING,
710 RTL_FLAG_TASK_PHY_PENDING,
711 RTL_FLAG_MAX
712};
713
8027aa24
JW		 714struct rtl8169_stats {
715 u64 packets;
716 u64 bytes;
717 struct u64_stats_sync syncp;
718};
719
1da177e4
LT		 720struct rtl8169_private {
721 void __iomem *mmio_addr; /* memory map physical address */
cecb5fd7 722 struct pci_dev *pci_dev;
c4028958 723 struct net_device *dev;
bea3348e 724 struct napi_struct napi;
b57b7e5a 725 u32 msg_enable;
2b7b4318
FR		 726 u16 txd_version;
727 u16 mac_version;
1da177e4
LT		 728 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
729 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
730 u32 dirty_rx;
731 u32 dirty_tx;
8027aa24
JW		 732 struct rtl8169_stats rx_stats;
733 struct rtl8169_stats tx_stats;
1da177e4
LT		 734 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
735 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
736 dma_addr_t TxPhyAddr;
737 dma_addr_t RxPhyAddr;
6f0333b8 738 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
1da177e4 739 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
1da177e4
LT		 740 struct timer_list timer;
741 u16 cp_cmd;
da78dbff
FR		 742
743 u16 event_slow;
c0e45c1c 744
745 struct mdio_ops {
24192210
FR		 746 void (*write)(struct rtl8169_private *, int, int);
747 int (*read)(struct rtl8169_private *, int);
c0e45c1c 748 } mdio_ops;
749
065c27c1 750 struct pll_power_ops {
751 void (*down)(struct rtl8169_private *);
752 void (*up)(struct rtl8169_private *);
753 } pll_power_ops;
754
d58d46b5
FR		 755 struct jumbo_ops {
756 void (*enable)(struct rtl8169_private *);
757 void (*disable)(struct rtl8169_private *);
758 } jumbo_ops;
759
beb1fe18 760 struct csi_ops {
52989f0e
FR		 761 void (*write)(struct rtl8169_private *, int, int);
762 u32 (*read)(struct rtl8169_private *, int);
beb1fe18
HW		 763 } csi_ops;
764
54405cde 765 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
ccdffb9a 766 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
4da19633 767 void (*phy_reset_enable)(struct rtl8169_private *tp);
07ce4064 768 void (*hw_start)(struct net_device *);
4da19633 769 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
1da177e4 770 unsigned int (*link_ok)(void __iomem *);
8b4ab28d 771 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
4422bcd4
FR		 772
773 struct {
da78dbff
FR		 774 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
775 struct mutex mutex;
4422bcd4
FR		 776 struct work_struct work;
777 } wk;
778
f23e7fda 779 unsigned features;
ccdffb9a
FR		 780
781 struct mii_if_info mii;
355423d0 782 struct rtl8169_counters counters;
e1759441 783 u32 saved_wolopts;
e03f33af 784 u32 opts1_mask;
f1e02ed1 785
b6ffd97f
FR		 786 struct rtl_fw {
787 const struct firmware *fw;
1c361efb
FR		 788
789#define RTL_VER_SIZE 32
790
791 char version[RTL_VER_SIZE];
792
793 struct rtl_fw_phy_action {
794 __le32 *code;
795 size_t size;
796 } phy_action;
b6ffd97f 797 } *rtl_fw;
497888cf 798#define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
c558386b
HW		 799
800 u32 ocp_base;
1da177e4
LT		 801};
802
979b6c13 803MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 804MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 805module_param(use_dac, int, 0);
4300e8c7 806MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 807module_param_named(debug, debug.msg_enable, int, 0);
808MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 809MODULE_LICENSE("GPL");
810MODULE_VERSION(RTL8169_VERSION);
bca03d5f 811MODULE_FIRMWARE(FIRMWARE_8168D_1);
812MODULE_FIRMWARE(FIRMWARE_8168D_2);
01dc7fec 813MODULE_FIRMWARE(FIRMWARE_8168E_1);
814MODULE_FIRMWARE(FIRMWARE_8168E_2);
bbb8af75 815MODULE_FIRMWARE(FIRMWARE_8168E_3);
5a5e4443 816MODULE_FIRMWARE(FIRMWARE_8105E_1);
c2218925
HW		 817MODULE_FIRMWARE(FIRMWARE_8168F_1);
818MODULE_FIRMWARE(FIRMWARE_8168F_2);
7e18dca1 819MODULE_FIRMWARE(FIRMWARE_8402_1);
b3d7b2f2 820MODULE_FIRMWARE(FIRMWARE_8411_1);
5598bfe5 821MODULE_FIRMWARE(FIRMWARE_8106E_1);
c558386b 822MODULE_FIRMWARE(FIRMWARE_8168G_1);
1da177e4 823
da78dbff
FR		 824static void rtl_lock_work(struct rtl8169_private *tp)
825{
826 mutex_lock(&tp->wk.mutex);
827}
828
829static void rtl_unlock_work(struct rtl8169_private *tp)
830{
831 mutex_unlock(&tp->wk.mutex);
832}
833
d58d46b5
FR		 834static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
835{
836 int cap = pci_pcie_cap(pdev);
837
838 if (cap) {
839 u16 ctl;
840
841 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
842 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
843 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
844 }
845}
846
ffc46952
FR		 847struct rtl_cond {
848 bool (*check)(struct rtl8169_private *);
849 const char *msg;
850};
851
852static void rtl_udelay(unsigned int d)
853{
854 udelay(d);
855}
856
857static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
858 void (*delay)(unsigned int), unsigned int d, int n,
859 bool high)
860{
861 int i;
862
863 for (i = 0; i < n; i++) {
864 delay(d);
865 if (c->check(tp) == high)
866 return true;
867 }
868 netif_err(tp, drv, tp->dev, c->msg);
869 return false;
870}
871
872static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
873 const struct rtl_cond *c,
874 unsigned int d, int n)
875{
876 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
877}
878
879static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
880 const struct rtl_cond *c,
881 unsigned int d, int n)
882{
883 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
884}
885
886static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
887 const struct rtl_cond *c,
888 unsigned int d, int n)
889{
890 return rtl_loop_wait(tp, c, msleep, d, n, true);
891}
892
893static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
894 const struct rtl_cond *c,
895 unsigned int d, int n)
896{
897 return rtl_loop_wait(tp, c, msleep, d, n, false);
898}
899
900#define DECLARE_RTL_COND(name) \
901static bool name ## _check(struct rtl8169_private *); \
902 \
903static const struct rtl_cond name = { \
904 .check = name ## _check, \
905 .msg = #name \
906}; \
907 \
908static bool name ## _check(struct rtl8169_private *tp)
909
910DECLARE_RTL_COND(rtl_ocpar_cond)
911{
912 void __iomem *ioaddr = tp->mmio_addr;
913
914 return RTL_R32(OCPAR) & OCPAR_FLAG;
915}
916
b646d900 917static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
918{
919 void __iomem *ioaddr = tp->mmio_addr;
b646d900 920
921 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
ffc46952
FR		 922
923 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
924 RTL_R32(OCPDR) : ~0;
b646d900 925}
926
927static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
928{
929 void __iomem *ioaddr = tp->mmio_addr;
b646d900 930
931 RTL_W32(OCPDR, data);
932 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
ffc46952
FR		 933
934 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
935}
936
937DECLARE_RTL_COND(rtl_eriar_cond)
938{
939 void __iomem *ioaddr = tp->mmio_addr;
940
941 return RTL_R32(ERIAR) & ERIAR_FLAG;
b646d900 942}
943
fac5b3ca 944static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
b646d900 945{
fac5b3ca 946 void __iomem *ioaddr = tp->mmio_addr;
b646d900 947
948 RTL_W8(ERIDR, cmd);
949 RTL_W32(ERIAR, 0x800010e8);
950 msleep(2);
ffc46952
FR		 951
952 if (!rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 5))
953 return;
b646d900 954
fac5b3ca 955 ocp_write(tp, 0x1, 0x30, 0x00000001);
b646d900 956}
957
958#define OOB_CMD_RESET 0x00
959#define OOB_CMD_DRIVER_START 0x05
960#define OOB_CMD_DRIVER_STOP 0x06
961
cecb5fd7
FR		 962static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
963{
964 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
965}
966
ffc46952 967DECLARE_RTL_COND(rtl_ocp_read_cond)
b646d900 968{
cecb5fd7 969 u16 reg;
b646d900 970
cecb5fd7 971 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 972
ffc46952 973 return ocp_read(tp, 0x0f, reg) & 0x00000800;
b646d900 974}
975
ffc46952 976static void rtl8168_driver_start(struct rtl8169_private *tp)
b646d900 977{
ffc46952 978 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
b646d900 979
ffc46952
FR		 980 rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
981}
b646d900 982
ffc46952
FR		 983static void rtl8168_driver_stop(struct rtl8169_private *tp)
984{
985 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
4804b3b3 986
ffc46952 987 rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
b646d900 988}
989
4804b3b3 990static int r8168dp_check_dash(struct rtl8169_private *tp)
991{
cecb5fd7 992 u16 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 993
cecb5fd7 994 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
4804b3b3 995}
b646d900 996
c558386b
HW		 997static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
998{
999 if (reg & 0xffff0001) {
1000 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
1001 return true;
1002 }
1003 return false;
1004}
1005
1006DECLARE_RTL_COND(rtl_ocp_gphy_cond)
1007{
1008 void __iomem *ioaddr = tp->mmio_addr;
1009
1010 return RTL_R32(GPHY_OCP) & OCPAR_FLAG;
1011}
1012
1013static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1014{
1015 void __iomem *ioaddr = tp->mmio_addr;
1016
1017 if (rtl_ocp_reg_failure(tp, reg))
1018 return;
1019
1020 RTL_W32(GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
1021
1022 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
1023}
1024
1025static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
1026{
1027 void __iomem *ioaddr = tp->mmio_addr;
1028
1029 if (rtl_ocp_reg_failure(tp, reg))
1030 return 0;
1031
1032 RTL_W32(GPHY_OCP, reg << 15);
1033
1034 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
1035 (RTL_R32(GPHY_OCP) & 0xffff) : ~0;
1036}
1037
1038static void rtl_w1w0_phy_ocp(struct rtl8169_private *tp, int reg, int p, int m)
1039{
1040 int val;
1041
1042 val = r8168_phy_ocp_read(tp, reg);
1043 r8168_phy_ocp_write(tp, reg, (val | p) & ~m);
1044}
1045
1046DECLARE_RTL_COND(rtl_ocpdr_cond)
1047{
1048 void __iomem *ioaddr = tp->mmio_addr;
1049
1050 return RTL_R32(OCPDR) & OCPAR_FLAG;
1051}
1052
1053static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1054{
1055 void __iomem *ioaddr = tp->mmio_addr;
1056
1057 if (rtl_ocp_reg_failure(tp, reg))
1058 return;
1059
1060 RTL_W32(OCPDR, OCPAR_FLAG | (reg << 15) | data);
1061
1062 rtl_udelay_loop_wait_low(tp, &rtl_ocpdr_cond, 25, 10);
1063}
1064
1065static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1066{
1067 void __iomem *ioaddr = tp->mmio_addr;
1068
1069 if (rtl_ocp_reg_failure(tp, reg))
1070 return 0;
1071
1072 RTL_W32(OCPDR, reg << 15);
1073
1074 return rtl_udelay_loop_wait_high(tp, &rtl_ocpdr_cond, 25, 10) ?
1075 RTL_R32(OCPDR) : ~0;
1076}
1077
1078#define OCP_STD_PHY_BASE 0xa400
1079
1080static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
1081{
1082 if (reg == 0x1f) {
1083 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
1084 return;
1085 }
1086
1087 if (tp->ocp_base != OCP_STD_PHY_BASE)
1088 reg -= 0x10;
1089
1090 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
1091}
1092
1093static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1094{
1095 if (tp->ocp_base != OCP_STD_PHY_BASE)
1096 reg -= 0x10;
1097
1098 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
1099}
1100
ffc46952
FR		 1101DECLARE_RTL_COND(rtl_phyar_cond)
1102{
1103 void __iomem *ioaddr = tp->mmio_addr;
1104
1105 return RTL_R32(PHYAR) & 0x80000000;
1106}
1107
24192210 1108static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1da177e4 1109{
24192210 1110 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 1111
24192210 1112 RTL_W32(PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1da177e4 1113
ffc46952 1114 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
024a07ba 1115 /*
81a95f04
TT		 1116 * According to hardware specs a 20us delay is required after write
1117 * complete indication, but before sending next command.
024a07ba 1118 */
81a95f04 1119 udelay(20);
1da177e4
LT		 1120}
1121
24192210 1122static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1da177e4 1123{
24192210 1124 void __iomem *ioaddr = tp->mmio_addr;
ffc46952 1125 int value;
1da177e4 1126
24192210 1127 RTL_W32(PHYAR, 0x0 | (reg & 0x1f) << 16);
1da177e4 1128
ffc46952
FR		 1129 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1130 RTL_R32(PHYAR) & 0xffff : ~0;
1131
81a95f04
TT		 1132 /*
1133 * According to hardware specs a 20us delay is required after read
1134 * complete indication, but before sending next command.
1135 */
1136 udelay(20);
1137
1da177e4
LT		 1138 return value;
1139}
1140
24192210 1141static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
c0e45c1c 1142{
24192210 1143 void __iomem *ioaddr = tp->mmio_addr;
c0e45c1c 1144
24192210 1145 RTL_W32(OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
c0e45c1c 1146 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
1147 RTL_W32(EPHY_RXER_NUM, 0);
1148
ffc46952 1149 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
c0e45c1c 1150}
1151
24192210 1152static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
c0e45c1c 1153{
24192210
FR		 1154 r8168dp_1_mdio_access(tp, reg,
1155 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
c0e45c1c 1156}
1157
24192210 1158static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
c0e45c1c 1159{
24192210 1160 void __iomem *ioaddr = tp->mmio_addr;
c0e45c1c 1161
24192210 1162 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
c0e45c1c 1163
1164 mdelay(1);
1165 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
1166 RTL_W32(EPHY_RXER_NUM, 0);
1167
ffc46952
FR		 1168 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1169 RTL_R32(OCPDR) & OCPDR_DATA_MASK : ~0;
c0e45c1c 1170}
1171
e6de30d6 1172#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1173
1174static void r8168dp_2_mdio_start(void __iomem *ioaddr)
1175{
1176 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1177}
1178
1179static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
1180{
1181 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1182}
1183
24192210 1184static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
e6de30d6 1185{
24192210
FR		 1186 void __iomem *ioaddr = tp->mmio_addr;
1187
e6de30d6 1188 r8168dp_2_mdio_start(ioaddr);
1189
24192210 1190 r8169_mdio_write(tp, reg, value);
e6de30d6 1191
1192 r8168dp_2_mdio_stop(ioaddr);
1193}
1194
24192210 1195static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
e6de30d6 1196{
24192210 1197 void __iomem *ioaddr = tp->mmio_addr;
e6de30d6 1198 int value;
1199
1200 r8168dp_2_mdio_start(ioaddr);
1201
24192210 1202 value = r8169_mdio_read(tp, reg);
e6de30d6 1203
1204 r8168dp_2_mdio_stop(ioaddr);
1205
1206 return value;
1207}
1208
4da19633 1209static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
dacf8154 1210{
24192210 1211 tp->mdio_ops.write(tp, location, val);
dacf8154
FR		 1212}
1213
4da19633 1214static int rtl_readphy(struct rtl8169_private *tp, int location)
1215{
24192210 1216 return tp->mdio_ops.read(tp, location);
4da19633 1217}
1218
1219static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1220{
1221 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1222}
1223
1224static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
daf9df6d 1225{
1226 int val;
1227
4da19633 1228 val = rtl_readphy(tp, reg_addr);
1229 rtl_writephy(tp, reg_addr, (val | p) & ~m);
daf9df6d 1230}
1231
ccdffb9a
FR		 1232static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1233 int val)
1234{
1235 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1236
4da19633 1237 rtl_writephy(tp, location, val);
ccdffb9a
FR		 1238}
1239
1240static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1241{
1242 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1243
4da19633 1244 return rtl_readphy(tp, location);
ccdffb9a
FR		 1245}
1246
ffc46952
FR		 1247DECLARE_RTL_COND(rtl_ephyar_cond)
1248{
1249 void __iomem *ioaddr = tp->mmio_addr;
1250
1251 return RTL_R32(EPHYAR) & EPHYAR_FLAG;
1252}
1253
fdf6fc06 1254static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
dacf8154 1255{
fdf6fc06 1256 void __iomem *ioaddr = tp->mmio_addr;
dacf8154
FR		 1257
1258 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1259 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1260
ffc46952
FR		 1261 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1262
1263 udelay(10);
dacf8154
FR		 1264}
1265
fdf6fc06 1266static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
dacf8154 1267{
fdf6fc06 1268 void __iomem *ioaddr = tp->mmio_addr;
dacf8154
FR		 1269
1270 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1271
ffc46952
FR		 1272 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1273 RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0;
dacf8154
FR		 1274}
1275
fdf6fc06
FR		 1276static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1277 u32 val, int type)
133ac40a 1278{
fdf6fc06 1279 void __iomem *ioaddr = tp->mmio_addr;
133ac40a
HW		 1280
1281 BUG_ON((addr & 3) || (mask == 0));
1282 RTL_W32(ERIDR, val);
1283 RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1284
ffc46952 1285 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
133ac40a
HW		 1286}
1287
fdf6fc06 1288static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
133ac40a 1289{
fdf6fc06 1290 void __iomem *ioaddr = tp->mmio_addr;
133ac40a
HW		 1291
1292 RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1293
ffc46952
FR		 1294 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1295 RTL_R32(ERIDR) : ~0;
133ac40a
HW		 1296}
1297
fdf6fc06
FR		 1298static void rtl_w1w0_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1299 u32 m, int type)
133ac40a
HW		 1300{
1301 u32 val;
1302
fdf6fc06
FR		 1303 val = rtl_eri_read(tp, addr, type);
1304 rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
133ac40a
HW		 1305}
1306
c28aa385 1307struct exgmac_reg {
1308 u16 addr;
1309 u16 mask;
1310 u32 val;
1311};
1312
fdf6fc06 1313static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
c28aa385 1314 const struct exgmac_reg *r, int len)
1315{
1316 while (len-- > 0) {
fdf6fc06 1317 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
c28aa385 1318 r++;
1319 }
1320}
1321
ffc46952
FR		 1322DECLARE_RTL_COND(rtl_efusear_cond)
1323{
1324 void __iomem *ioaddr = tp->mmio_addr;
1325
1326 return RTL_R32(EFUSEAR) & EFUSEAR_FLAG;
1327}
1328
fdf6fc06 1329static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
daf9df6d 1330{
fdf6fc06 1331 void __iomem *ioaddr = tp->mmio_addr;
daf9df6d 1332
1333 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1334
ffc46952
FR		 1335 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1336 RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
daf9df6d 1337}
1338
9085cdfa
FR		 1339static u16 rtl_get_events(struct rtl8169_private *tp)
1340{
1341 void __iomem *ioaddr = tp->mmio_addr;
1342
1343 return RTL_R16(IntrStatus);
1344}
1345
1346static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1347{
1348 void __iomem *ioaddr = tp->mmio_addr;
1349
1350 RTL_W16(IntrStatus, bits);
1351 mmiowb();
1352}
1353
1354static void rtl_irq_disable(struct rtl8169_private *tp)
1355{
1356 void __iomem *ioaddr = tp->mmio_addr;
1357
1358 RTL_W16(IntrMask, 0);
1359 mmiowb();
1360}
1361
3e990ff5
FR		 1362static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1363{
1364 void __iomem *ioaddr = tp->mmio_addr;
1365
1366 RTL_W16(IntrMask, bits);
1367}
1368
da78dbff
FR		 1369#define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1370#define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1371#define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1372
1373static void rtl_irq_enable_all(struct rtl8169_private *tp)
1374{
1375 rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1376}
1377
811fd301 1378static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1da177e4 1379{
811fd301 1380 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 1381
9085cdfa 1382 rtl_irq_disable(tp);
da78dbff 1383 rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
811fd301 1384 RTL_R8(ChipCmd);
1da177e4
LT		 1385}
1386
4da19633 1387static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1da177e4 1388{
4da19633 1389 void __iomem *ioaddr = tp->mmio_addr;
1390
1da177e4
LT		 1391 return RTL_R32(TBICSR) & TBIReset;
1392}
1393
4da19633 1394static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1da177e4 1395{
4da19633 1396 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 1397}
1398
1399static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1400{
1401 return RTL_R32(TBICSR) & TBILinkOk;
1402}
1403
1404static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1405{
1406 return RTL_R8(PHYstatus) & LinkStatus;
1407}
1408
4da19633 1409static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1da177e4 1410{
4da19633 1411 void __iomem *ioaddr = tp->mmio_addr;
1412
1da177e4
LT		 1413 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1414}
1415
4da19633 1416static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1da177e4
LT		 1417{
1418 unsigned int val;
1419
4da19633 1420 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1421 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1da177e4
LT		 1422}
1423
70090424
HW		 1424static void rtl_link_chg_patch(struct rtl8169_private *tp)
1425{
1426 void __iomem *ioaddr = tp->mmio_addr;
1427 struct net_device *dev = tp->dev;
1428
1429 if (!netif_running(dev))
1430 return;
1431
b3d7b2f2
HW		 1432 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1433 tp->mac_version == RTL_GIGA_MAC_VER_38) {
70090424 1434 if (RTL_R8(PHYstatus) & _1000bpsF) {
fdf6fc06
FR		 1435 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1436 ERIAR_EXGMAC);
1437 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1438 ERIAR_EXGMAC);
70090424 1439 } else if (RTL_R8(PHYstatus) & _100bps) {
fdf6fc06
FR		 1440 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1441 ERIAR_EXGMAC);
1442 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1443 ERIAR_EXGMAC);
70090424 1444 } else {
fdf6fc06
FR		 1445 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1446 ERIAR_EXGMAC);
1447 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1448 ERIAR_EXGMAC);
70090424
HW		 1449 }
1450 /* Reset packet filter */
fdf6fc06 1451 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
70090424 1452 ERIAR_EXGMAC);
fdf6fc06 1453 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
70090424 1454 ERIAR_EXGMAC);
c2218925
HW		 1455 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1456 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1457 if (RTL_R8(PHYstatus) & _1000bpsF) {
fdf6fc06
FR		 1458 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1459 ERIAR_EXGMAC);
1460 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1461 ERIAR_EXGMAC);
c2218925 1462 } else {
fdf6fc06
FR		 1463 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1464 ERIAR_EXGMAC);
1465 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1466 ERIAR_EXGMAC);
c2218925 1467 }
7e18dca1
HW		 1468 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1469 if (RTL_R8(PHYstatus) & _10bps) {
fdf6fc06
FR		 1470 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1471 ERIAR_EXGMAC);
1472 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1473 ERIAR_EXGMAC);
7e18dca1 1474 } else {
fdf6fc06
FR		 1475 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1476 ERIAR_EXGMAC);
7e18dca1 1477 }
70090424
HW		 1478 }
1479}
1480
e4fbce74 1481static void __rtl8169_check_link_status(struct net_device *dev,
cecb5fd7
FR		 1482 struct rtl8169_private *tp,
1483 void __iomem *ioaddr, bool pm)
1da177e4 1484{
1da177e4 1485 if (tp->link_ok(ioaddr)) {
70090424 1486 rtl_link_chg_patch(tp);
e1759441 1487 /* This is to cancel a scheduled suspend if there's one. */
e4fbce74
RW		 1488 if (pm)
1489 pm_request_resume(&tp->pci_dev->dev);
1da177e4 1490 netif_carrier_on(dev);
1519e57f
FR		 1491 if (net_ratelimit())
1492 netif_info(tp, ifup, dev, "link up\n");
b57b7e5a 1493 } else {
1da177e4 1494 netif_carrier_off(dev);
bf82c189 1495 netif_info(tp, ifdown, dev, "link down\n");
e4fbce74 1496 if (pm)
10953db8 1497 pm_schedule_suspend(&tp->pci_dev->dev, 5000);
b57b7e5a 1498 }
1da177e4
LT		 1499}
1500
e4fbce74
RW		 1501static void rtl8169_check_link_status(struct net_device *dev,
1502 struct rtl8169_private *tp,
1503 void __iomem *ioaddr)
1504{
1505 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1506}
1507
e1759441
RW		 1508#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1509
1510static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
61a4dcc2 1511{
61a4dcc2
FR		 1512 void __iomem *ioaddr = tp->mmio_addr;
1513 u8 options;
e1759441 1514 u32 wolopts = 0;
61a4dcc2
FR		 1515
1516 options = RTL_R8(Config1);
1517 if (!(options & PMEnable))
e1759441 1518 return 0;
61a4dcc2
FR		 1519
1520 options = RTL_R8(Config3);
1521 if (options & LinkUp)
e1759441 1522 wolopts |= WAKE_PHY;
61a4dcc2 1523 if (options & MagicPacket)
e1759441 1524 wolopts |= WAKE_MAGIC;
61a4dcc2
FR		 1525
1526 options = RTL_R8(Config5);
1527 if (options & UWF)
e1759441 1528 wolopts |= WAKE_UCAST;
61a4dcc2 1529 if (options & BWF)
e1759441 1530 wolopts |= WAKE_BCAST;
61a4dcc2 1531 if (options & MWF)
e1759441 1532 wolopts |= WAKE_MCAST;
61a4dcc2 1533
e1759441 1534 return wolopts;
61a4dcc2
FR		 1535}
1536
e1759441 1537static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
61a4dcc2
FR		 1538{
1539 struct rtl8169_private *tp = netdev_priv(dev);
e1759441 1540
da78dbff 1541 rtl_lock_work(tp);
e1759441
RW		 1542
1543 wol->supported = WAKE_ANY;
1544 wol->wolopts = __rtl8169_get_wol(tp);
1545
da78dbff 1546 rtl_unlock_work(tp);
e1759441
RW		 1547}
1548
1549static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1550{
61a4dcc2 1551 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1552 unsigned int i;
350f7596 1553 static const struct {
61a4dcc2
FR		 1554 u32 opt;
1555 u16 reg;
1556 u8 mask;
1557 } cfg[] = {
61a4dcc2
FR		 1558 { WAKE_PHY, Config3, LinkUp },
1559 { WAKE_MAGIC, Config3, MagicPacket },
1560 { WAKE_UCAST, Config5, UWF },
1561 { WAKE_BCAST, Config5, BWF },
1562 { WAKE_MCAST, Config5, MWF },
1563 { WAKE_ANY, Config5, LanWake }
1564 };
851e6022 1565 u8 options;
61a4dcc2 1566
61a4dcc2
FR		 1567 RTL_W8(Cfg9346, Cfg9346_Unlock);
1568
1569 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
851e6022 1570 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
e1759441 1571 if (wolopts & cfg[i].opt)
61a4dcc2
FR		 1572 options |= cfg[i].mask;
1573 RTL_W8(cfg[i].reg, options);
1574 }
1575
851e6022
FR		 1576 switch (tp->mac_version) {
1577 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1578 options = RTL_R8(Config1) & ~PMEnable;
1579 if (wolopts)
1580 options |= PMEnable;
1581 RTL_W8(Config1, options);
1582 break;
1583 default:
d387b427
FR		 1584 options = RTL_R8(Config2) & ~PME_SIGNAL;
1585 if (wolopts)
1586 options |= PME_SIGNAL;
1587 RTL_W8(Config2, options);
851e6022
FR		 1588 break;
1589 }
1590
61a4dcc2 1591 RTL_W8(Cfg9346, Cfg9346_Lock);
e1759441
RW		 1592}
1593
1594static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1595{
1596 struct rtl8169_private *tp = netdev_priv(dev);
1597
da78dbff 1598 rtl_lock_work(tp);
61a4dcc2 1599
f23e7fda
FR		 1600 if (wol->wolopts)
1601 tp->features |= RTL_FEATURE_WOL;
1602 else
1603 tp->features &= ~RTL_FEATURE_WOL;
e1759441 1604 __rtl8169_set_wol(tp, wol->wolopts);
da78dbff
FR		 1605
1606 rtl_unlock_work(tp);
61a4dcc2 1607
ea80907f 1608 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1609
61a4dcc2
FR		 1610 return 0;
1611}
1612
31bd204f
FR		 1613static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1614{
85bffe6c 1615 return rtl_chip_infos[tp->mac_version].fw_name;
31bd204f
FR		 1616}
1617
1da177e4
LT		 1618static void rtl8169_get_drvinfo(struct net_device *dev,
1619 struct ethtool_drvinfo *info)
1620{
1621 struct rtl8169_private *tp = netdev_priv(dev);
b6ffd97f 1622 struct rtl_fw *rtl_fw = tp->rtl_fw;
1da177e4 1623
68aad78c
RJ		 1624 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1625 strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1626 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1c361efb 1627 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
8ac72d16
RJ		 1628 if (!IS_ERR_OR_NULL(rtl_fw))
1629 strlcpy(info->fw_version, rtl_fw->version,
1630 sizeof(info->fw_version));
1da177e4
LT		 1631}
1632
1633static int rtl8169_get_regs_len(struct net_device *dev)
1634{
1635 return R8169_REGS_SIZE;
1636}
1637
1638static int rtl8169_set_speed_tbi(struct net_device *dev,
54405cde 1639 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1da177e4
LT		 1640{
1641 struct rtl8169_private *tp = netdev_priv(dev);
1642 void __iomem *ioaddr = tp->mmio_addr;
1643 int ret = 0;
1644 u32 reg;
1645
1646 reg = RTL_R32(TBICSR);
1647 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1648 (duplex == DUPLEX_FULL)) {
1649 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1650 } else if (autoneg == AUTONEG_ENABLE)
1651 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1652 else {
bf82c189
JP		 1653 netif_warn(tp, link, dev,
1654 "incorrect speed setting refused in TBI mode\n");
1da177e4
LT		 1655 ret = -EOPNOTSUPP;
1656 }
1657
1658 return ret;
1659}
1660
1661static int rtl8169_set_speed_xmii(struct net_device *dev,
54405cde 1662 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1da177e4
LT		 1663{
1664 struct rtl8169_private *tp = netdev_priv(dev);
3577aa1b 1665 int giga_ctrl, bmcr;
54405cde 1666 int rc = -EINVAL;
1da177e4 1667
716b50a3 1668 rtl_writephy(tp, 0x1f, 0x0000);
1da177e4
LT		 1669
1670 if (autoneg == AUTONEG_ENABLE) {
3577aa1b 1671 int auto_nego;
1672
4da19633 1673 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
54405cde
ON		 1674 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1675 ADVERTISE_100HALF | ADVERTISE_100FULL);
1676
1677 if (adv & ADVERTISED_10baseT_Half)
1678 auto_nego |= ADVERTISE_10HALF;
1679 if (adv & ADVERTISED_10baseT_Full)
1680 auto_nego |= ADVERTISE_10FULL;
1681 if (adv & ADVERTISED_100baseT_Half)
1682 auto_nego |= ADVERTISE_100HALF;
1683 if (adv & ADVERTISED_100baseT_Full)
1684 auto_nego |= ADVERTISE_100FULL;
1685
3577aa1b 1686 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1da177e4 1687
4da19633 1688 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
3577aa1b 1689 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
bcf0bf90 1690
3577aa1b 1691 /* The 8100e/8101e/8102e do Fast Ethernet only. */
826e6cbd 1692 if (tp->mii.supports_gmii) {
54405cde
ON		 1693 if (adv & ADVERTISED_1000baseT_Half)
1694 giga_ctrl |= ADVERTISE_1000HALF;
1695 if (adv & ADVERTISED_1000baseT_Full)
1696 giga_ctrl |= ADVERTISE_1000FULL;
1697 } else if (adv & (ADVERTISED_1000baseT_Half |
1698 ADVERTISED_1000baseT_Full)) {
bf82c189
JP		 1699 netif_info(tp, link, dev,
1700 "PHY does not support 1000Mbps\n");
54405cde 1701 goto out;
bcf0bf90 1702 }
1da177e4 1703
3577aa1b 1704 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1705
4da19633 1706 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1707 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
3577aa1b 1708 } else {
1709 giga_ctrl = 0;
1710
1711 if (speed == SPEED_10)
1712 bmcr = 0;
1713 else if (speed == SPEED_100)
1714 bmcr = BMCR_SPEED100;
1715 else
54405cde 1716 goto out;
3577aa1b 1717
1718 if (duplex == DUPLEX_FULL)
1719 bmcr |= BMCR_FULLDPLX;
2584fbc3
RS		 1720 }
1721
4da19633 1722 rtl_writephy(tp, MII_BMCR, bmcr);
3577aa1b 1723
cecb5fd7
FR		 1724 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1725 tp->mac_version == RTL_GIGA_MAC_VER_03) {
3577aa1b 1726 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
4da19633 1727 rtl_writephy(tp, 0x17, 0x2138);
1728 rtl_writephy(tp, 0x0e, 0x0260);
3577aa1b 1729 } else {
4da19633 1730 rtl_writephy(tp, 0x17, 0x2108);
1731 rtl_writephy(tp, 0x0e, 0x0000);
3577aa1b 1732 }
1733 }
1734
54405cde
ON		 1735 rc = 0;
1736out:
1737 return rc;
1da177e4
LT		 1738}
1739
1740static int rtl8169_set_speed(struct net_device *dev,
54405cde 1741 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1da177e4
LT		 1742{
1743 struct rtl8169_private *tp = netdev_priv(dev);
1744 int ret;
1745
54405cde 1746 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
4876cc1e
FR		 1747 if (ret < 0)
1748 goto out;
1da177e4 1749
4876cc1e
FR		 1750 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1751 (advertising & ADVERTISED_1000baseT_Full)) {
1da177e4 1752 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
4876cc1e
FR		 1753 }
1754out:
1da177e4
LT		 1755 return ret;
1756}
1757
1758static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1759{
1760 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4
LT		 1761 int ret;
1762
4876cc1e
FR		 1763 del_timer_sync(&tp->timer);
1764
da78dbff 1765 rtl_lock_work(tp);
cecb5fd7 1766 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
25db0338 1767 cmd->duplex, cmd->advertising);
da78dbff 1768 rtl_unlock_work(tp);
5b0384f4 1769
1da177e4
LT		 1770 return ret;
1771}
1772
c8f44aff
MM		 1773static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1774 netdev_features_t features)
1da177e4 1775{
d58d46b5
FR		 1776 struct rtl8169_private *tp = netdev_priv(dev);
1777
2b7b4318 1778 if (dev->mtu > TD_MSS_MAX)
350fb32a 1779 features &= ~NETIF_F_ALL_TSO;
1da177e4 1780
d58d46b5
FR		 1781 if (dev->mtu > JUMBO_1K &&
1782 !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1783 features &= ~NETIF_F_IP_CSUM;
1784
350fb32a 1785 return features;
1da177e4
LT		 1786}
1787
da78dbff
FR		 1788static void __rtl8169_set_features(struct net_device *dev,
1789 netdev_features_t features)
1da177e4
LT		 1790{
1791 struct rtl8169_private *tp = netdev_priv(dev);
6bbe021d 1792 netdev_features_t changed = features ^ dev->features;
da78dbff 1793 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 1794
6bbe021d
BG		 1795 if (!(changed & (NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)))
1796 return;
1da177e4 1797
6bbe021d
BG		 1798 if (changed & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)) {
1799 if (features & NETIF_F_RXCSUM)
1800 tp->cp_cmd |= RxChkSum;
1801 else
1802 tp->cp_cmd &= ~RxChkSum;
350fb32a 1803
6bbe021d
BG		 1804 if (dev->features & NETIF_F_HW_VLAN_RX)
1805 tp->cp_cmd |= RxVlan;
1806 else
1807 tp->cp_cmd &= ~RxVlan;
1808
1809 RTL_W16(CPlusCmd, tp->cp_cmd);
1810 RTL_R16(CPlusCmd);
1811 }
1812 if (changed & NETIF_F_RXALL) {
1813 int tmp = (RTL_R32(RxConfig) & ~(AcceptErr | AcceptRunt));
1814 if (features & NETIF_F_RXALL)
1815 tmp |= (AcceptErr | AcceptRunt);
1816 RTL_W32(RxConfig, tmp);
1817 }
da78dbff 1818}
1da177e4 1819
da78dbff
FR		 1820static int rtl8169_set_features(struct net_device *dev,
1821 netdev_features_t features)
1822{
1823 struct rtl8169_private *tp = netdev_priv(dev);
1824
1825 rtl_lock_work(tp);
1826 __rtl8169_set_features(dev, features);
1827 rtl_unlock_work(tp);
1da177e4
LT		 1828
1829 return 0;
1830}
1831
da78dbff 1832
1da177e4
LT		 1833static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1834 struct sk_buff *skb)
1835{
eab6d18d 1836 return (vlan_tx_tag_present(skb)) ?
1da177e4
LT		 1837 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1838}
1839
7a8fc77b 1840static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1da177e4
LT		 1841{
1842 u32 opts2 = le32_to_cpu(desc->opts2);
1da177e4 1843
7a8fc77b
FR		 1844 if (opts2 & RxVlanTag)
1845 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
2edae08e 1846
1da177e4 1847 desc->opts2 = 0;
1da177e4
LT		 1848}
1849
ccdffb9a 1850static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1851{
1852 struct rtl8169_private *tp = netdev_priv(dev);
1853 void __iomem *ioaddr = tp->mmio_addr;
1854 u32 status;
1855
1856 cmd->supported =
1857 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1858 cmd->port = PORT_FIBRE;
1859 cmd->transceiver = XCVR_INTERNAL;
1860
1861 status = RTL_R32(TBICSR);
1862 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1863 cmd->autoneg = !!(status & TBINwEnable);
1864
70739497 1865 ethtool_cmd_speed_set(cmd, SPEED_1000);
1da177e4 1866 cmd->duplex = DUPLEX_FULL; /* Always set */
ccdffb9a
FR		 1867
1868 return 0;
1da177e4
LT		 1869}
1870
ccdffb9a 1871static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1872{
1873 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a
FR		 1874
1875 return mii_ethtool_gset(&tp->mii, cmd);
1da177e4
LT		 1876}
1877
1878static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1879{
1880 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1881 int rc;
1da177e4 1882
da78dbff 1883 rtl_lock_work(tp);
ccdffb9a 1884 rc = tp->get_settings(dev, cmd);
da78dbff 1885 rtl_unlock_work(tp);
1da177e4 1886
ccdffb9a 1887 return rc;
1da177e4
LT		 1888}
1889
1890static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1891 void *p)
1892{
5b0384f4 1893 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 1894
5b0384f4
FR		 1895 if (regs->len > R8169_REGS_SIZE)
1896 regs->len = R8169_REGS_SIZE;
1da177e4 1897
da78dbff 1898 rtl_lock_work(tp);
5b0384f4 1899 memcpy_fromio(p, tp->mmio_addr, regs->len);
da78dbff 1900 rtl_unlock_work(tp);
1da177e4
LT		 1901}
1902
b57b7e5a
SH		 1903static u32 rtl8169_get_msglevel(struct net_device *dev)
1904{
1905 struct rtl8169_private *tp = netdev_priv(dev);
1906
1907 return tp->msg_enable;
1908}
1909
1910static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1911{
1912 struct rtl8169_private *tp = netdev_priv(dev);
1913
1914 tp->msg_enable = value;
1915}
1916
d4a3a0fc
SH		 1917static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1918 "tx_packets",
1919 "rx_packets",
1920 "tx_errors",
1921 "rx_errors",
1922 "rx_missed",
1923 "align_errors",
1924 "tx_single_collisions",
1925 "tx_multi_collisions",
1926 "unicast",
1927 "broadcast",
1928 "multicast",
1929 "tx_aborted",
1930 "tx_underrun",
1931};
1932
b9f2c044 1933static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1934{
b9f2c044
JG		 1935 switch (sset) {
1936 case ETH_SS_STATS:
1937 return ARRAY_SIZE(rtl8169_gstrings);
1938 default:
1939 return -EOPNOTSUPP;
1940 }
d4a3a0fc
SH		 1941}
1942
ffc46952
FR		 1943DECLARE_RTL_COND(rtl_counters_cond)
1944{
1945 void __iomem *ioaddr = tp->mmio_addr;
1946
1947 return RTL_R32(CounterAddrLow) & CounterDump;
1948}
1949
355423d0 1950static void rtl8169_update_counters(struct net_device *dev)
d4a3a0fc
SH		 1951{
1952 struct rtl8169_private *tp = netdev_priv(dev);
1953 void __iomem *ioaddr = tp->mmio_addr;
cecb5fd7 1954 struct device *d = &tp->pci_dev->dev;
d4a3a0fc
SH		 1955 struct rtl8169_counters *counters;
1956 dma_addr_t paddr;
1957 u32 cmd;
1958
355423d0
IV		 1959 /*
1960 * Some chips are unable to dump tally counters when the receiver
1961 * is disabled.
1962 */
1963 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1964 return;
d4a3a0fc 1965
48addcc9 1966 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
d4a3a0fc
SH		 1967 if (!counters)
1968 return;
1969
1970 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
284901a9 1971 cmd = (u64)paddr & DMA_BIT_MASK(32);
d4a3a0fc
SH		 1972 RTL_W32(CounterAddrLow, cmd);
1973 RTL_W32(CounterAddrLow, cmd | CounterDump);
1974
ffc46952
FR		 1975 if (rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000))
1976 memcpy(&tp->counters, counters, sizeof(*counters));
d4a3a0fc
SH		 1977
1978 RTL_W32(CounterAddrLow, 0);
1979 RTL_W32(CounterAddrHigh, 0);
1980
48addcc9 1981 dma_free_coherent(d, sizeof(*counters), counters, paddr);
d4a3a0fc
SH		 1982}
1983
355423d0
IV		 1984static void rtl8169_get_ethtool_stats(struct net_device *dev,
1985 struct ethtool_stats *stats, u64 *data)
1986{
1987 struct rtl8169_private *tp = netdev_priv(dev);
1988
1989 ASSERT_RTNL();
1990
1991 rtl8169_update_counters(dev);
1992
1993 data[0] = le64_to_cpu(tp->counters.tx_packets);
1994 data[1] = le64_to_cpu(tp->counters.rx_packets);
1995 data[2] = le64_to_cpu(tp->counters.tx_errors);
1996 data[3] = le32_to_cpu(tp->counters.rx_errors);
1997 data[4] = le16_to_cpu(tp->counters.rx_missed);
1998 data[5] = le16_to_cpu(tp->counters.align_errors);
1999 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
2000 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
2001 data[8] = le64_to_cpu(tp->counters.rx_unicast);
2002 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
2003 data[10] = le32_to_cpu(tp->counters.rx_multicast);
2004 data[11] = le16_to_cpu(tp->counters.tx_aborted);
2005 data[12] = le16_to_cpu(tp->counters.tx_underun);
2006}
2007
d4a3a0fc
SH		 2008static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2009{
2010 switch(stringset) {
2011 case ETH_SS_STATS:
2012 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
2013 break;
2014 }
2015}
2016
7282d491 2017static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 2018 .get_drvinfo = rtl8169_get_drvinfo,
2019 .get_regs_len = rtl8169_get_regs_len,
2020 .get_link = ethtool_op_get_link,
2021 .get_settings = rtl8169_get_settings,
2022 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 2023 .get_msglevel = rtl8169_get_msglevel,
2024 .set_msglevel = rtl8169_set_msglevel,
1da177e4 2025 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 2026 .get_wol = rtl8169_get_wol,
2027 .set_wol = rtl8169_set_wol,
d4a3a0fc 2028 .get_strings = rtl8169_get_strings,
b9f2c044 2029 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 2030 .get_ethtool_stats = rtl8169_get_ethtool_stats,
e1593bb1 2031 .get_ts_info = ethtool_op_get_ts_info,
1da177e4
LT		 2032};
2033
07d3f51f 2034static void rtl8169_get_mac_version(struct rtl8169_private *tp,
5d320a20 2035 struct net_device *dev, u8 default_version)
1da177e4 2036{
5d320a20 2037 void __iomem *ioaddr = tp->mmio_addr;
0e485150
FR		 2038 /*
2039 * The driver currently handles the 8168Bf and the 8168Be identically
2040 * but they can be identified more specifically through the test below
2041 * if needed:
2042 *
2043 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 2044 *
2045 * Same thing for the 8101Eb and the 8101Ec:
2046 *
2047 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 2048 */
3744100e 2049 static const struct rtl_mac_info {
1da177e4 2050 u32 mask;
e3cf0cc0 2051 u32 val;
1da177e4
LT		 2052 int mac_version;
2053 } mac_info[] = {
c558386b
HW		 2054 /* 8168G family. */
2055 { 0x7cf00000, 0x4c100000, RTL_GIGA_MAC_VER_41 },
2056 { 0x7cf00000, 0x4c000000, RTL_GIGA_MAC_VER_40 },
2057
c2218925 2058 /* 8168F family. */
b3d7b2f2 2059 { 0x7c800000, 0x48800000, RTL_GIGA_MAC_VER_38 },
c2218925
HW		 2060 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
2061 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
2062
01dc7fec 2063 /* 8168E family. */
70090424 2064 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
01dc7fec 2065 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
2066 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
2067 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
2068
5b538df9 2069 /* 8168D family. */
daf9df6d 2070 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
2071 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
daf9df6d 2072 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
5b538df9 2073
e6de30d6 2074 /* 8168DP family. */
2075 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
2076 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
4804b3b3 2077 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
e6de30d6 2078
ef808d50 2079 /* 8168C family. */
17c99297 2080 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
ef3386f0 2081 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 2082 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 2083 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 2084 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
2085 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 2086 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
6fb07058 2087 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
ef808d50 2088 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 2089
2090 /* 8168B family. */
2091 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
2092 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
2093 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
2094 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
2095
2096 /* 8101 family. */
5598bfe5
HW		 2097 { 0x7cf00000, 0x44900000, RTL_GIGA_MAC_VER_39 },
2098 { 0x7c800000, 0x44800000, RTL_GIGA_MAC_VER_39 },
7e18dca1 2099 { 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37 },
36a0e6c2 2100 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
5a5e4443
HW		 2101 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
2102 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
2103 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2857ffb7
FR		 2104 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
2105 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
2106 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
2107 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
2108 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
2109 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 2110 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 2111 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 2112 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 2113 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
2114 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 2115 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
2116 /* FIXME: where did these entries come from ? -- FR */
2117 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
2118 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
2119
2120 /* 8110 family. */
2121 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
2122 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
2123 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
2124 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
2125 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
2126 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
2127
f21b75e9
JD		 2128 /* Catch-all */
2129 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
3744100e
FR		 2130 };
2131 const struct rtl_mac_info *p = mac_info;
1da177e4
LT		 2132 u32 reg;
2133
e3cf0cc0
FR		 2134 reg = RTL_R32(TxConfig);
2135 while ((reg & p->mask) != p->val)
1da177e4
LT		 2136 p++;
2137 tp->mac_version = p->mac_version;
5d320a20
FR		 2138
2139 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2140 netif_notice(tp, probe, dev,
2141 "unknown MAC, using family default\n");
2142 tp->mac_version = default_version;
2143 }
1da177e4
LT		 2144}
2145
2146static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2147{
bcf0bf90 2148 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 2149}
2150
867763c1
FR		 2151struct phy_reg {
2152 u16 reg;
2153 u16 val;
2154};
2155
4da19633 2156static void rtl_writephy_batch(struct rtl8169_private *tp,
2157 const struct phy_reg *regs, int len)
867763c1
FR		 2158{
2159 while (len-- > 0) {
4da19633 2160 rtl_writephy(tp, regs->reg, regs->val);
867763c1
FR		 2161 regs++;
2162 }
2163}
2164
bca03d5f 2165#define PHY_READ 0x00000000
2166#define PHY_DATA_OR 0x10000000
2167#define PHY_DATA_AND 0x20000000
2168#define PHY_BJMPN 0x30000000
2169#define PHY_READ_EFUSE 0x40000000
2170#define PHY_READ_MAC_BYTE 0x50000000
2171#define PHY_WRITE_MAC_BYTE 0x60000000
2172#define PHY_CLEAR_READCOUNT 0x70000000
2173#define PHY_WRITE 0x80000000
2174#define PHY_READCOUNT_EQ_SKIP 0x90000000
2175#define PHY_COMP_EQ_SKIPN 0xa0000000
2176#define PHY_COMP_NEQ_SKIPN 0xb0000000
2177#define PHY_WRITE_PREVIOUS 0xc0000000
2178#define PHY_SKIPN 0xd0000000
2179#define PHY_DELAY_MS 0xe0000000
2180#define PHY_WRITE_ERI_WORD 0xf0000000
2181
960aee6c
HW		 2182struct fw_info {
2183 u32 magic;
2184 char version[RTL_VER_SIZE];
2185 __le32 fw_start;
2186 __le32 fw_len;
2187 u8 chksum;
2188} __packed;
2189
1c361efb
FR		 2190#define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2191
2192static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
bca03d5f 2193{
b6ffd97f 2194 const struct firmware *fw = rtl_fw->fw;
960aee6c 2195 struct fw_info *fw_info = (struct fw_info *)fw->data;
1c361efb
FR		 2196 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2197 char *version = rtl_fw->version;
2198 bool rc = false;
2199
2200 if (fw->size < FW_OPCODE_SIZE)
2201 goto out;
960aee6c
HW		 2202
2203 if (!fw_info->magic) {
2204 size_t i, size, start;
2205 u8 checksum = 0;
2206
2207 if (fw->size < sizeof(*fw_info))
2208 goto out;
2209
2210 for (i = 0; i < fw->size; i++)
2211 checksum += fw->data[i];
2212 if (checksum != 0)
2213 goto out;
2214
2215 start = le32_to_cpu(fw_info->fw_start);
2216 if (start > fw->size)
2217 goto out;
2218
2219 size = le32_to_cpu(fw_info->fw_len);
2220 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2221 goto out;
2222
2223 memcpy(version, fw_info->version, RTL_VER_SIZE);
2224
2225 pa->code = (__le32 *)(fw->data + start);
2226 pa->size = size;
2227 } else {
1c361efb
FR		 2228 if (fw->size % FW_OPCODE_SIZE)
2229 goto out;
2230
2231 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2232
2233 pa->code = (__le32 *)fw->data;
2234 pa->size = fw->size / FW_OPCODE_SIZE;
2235 }
2236 version[RTL_VER_SIZE - 1] = 0;
2237
2238 rc = true;
2239out:
2240 return rc;
2241}
2242
fd112f2e
FR		 2243static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2244 struct rtl_fw_phy_action *pa)
1c361efb 2245{
fd112f2e 2246 bool rc = false;
1c361efb 2247 size_t index;
bca03d5f 2248
1c361efb
FR		 2249 for (index = 0; index < pa->size; index++) {
2250 u32 action = le32_to_cpu(pa->code[index]);
42b82dc1 2251 u32 regno = (action & 0x0fff0000) >> 16;
bca03d5f 2252
42b82dc1 2253 switch(action & 0xf0000000) {
2254 case PHY_READ:
2255 case PHY_DATA_OR:
2256 case PHY_DATA_AND:
2257 case PHY_READ_EFUSE:
2258 case PHY_CLEAR_READCOUNT:
2259 case PHY_WRITE:
2260 case PHY_WRITE_PREVIOUS:
2261 case PHY_DELAY_MS:
2262 break;
2263
2264 case PHY_BJMPN:
2265 if (regno > index) {
fd112f2e 2266 netif_err(tp, ifup, tp->dev,
cecb5fd7 2267 "Out of range of firmware\n");
fd112f2e 2268 goto out;
42b82dc1 2269 }
2270 break;
2271 case PHY_READCOUNT_EQ_SKIP:
1c361efb 2272 if (index + 2 >= pa->size) {
fd112f2e 2273 netif_err(tp, ifup, tp->dev,
cecb5fd7 2274 "Out of range of firmware\n");
fd112f2e 2275 goto out;
42b82dc1 2276 }
2277 break;
2278 case PHY_COMP_EQ_SKIPN:
2279 case PHY_COMP_NEQ_SKIPN:
2280 case PHY_SKIPN:
1c361efb 2281 if (index + 1 + regno >= pa->size) {
fd112f2e 2282 netif_err(tp, ifup, tp->dev,
cecb5fd7 2283 "Out of range of firmware\n");
fd112f2e 2284 goto out;
42b82dc1 2285 }
bca03d5f 2286 break;
2287
42b82dc1 2288 case PHY_READ_MAC_BYTE:
2289 case PHY_WRITE_MAC_BYTE:
2290 case PHY_WRITE_ERI_WORD:
2291 default:
fd112f2e 2292 netif_err(tp, ifup, tp->dev,
42b82dc1 2293 "Invalid action 0x%08x\n", action);
fd112f2e 2294 goto out;
bca03d5f 2295 }
2296 }
fd112f2e
FR		 2297 rc = true;
2298out:
2299 return rc;
2300}
bca03d5f 2301
fd112f2e
FR		 2302static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2303{
2304 struct net_device *dev = tp->dev;
2305 int rc = -EINVAL;
2306
2307 if (!rtl_fw_format_ok(tp, rtl_fw)) {
2308 netif_err(tp, ifup, dev, "invalid firwmare\n");
2309 goto out;
2310 }
2311
2312 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2313 rc = 0;
2314out:
2315 return rc;
2316}
2317
2318static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2319{
2320 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2321 u32 predata, count;
2322 size_t index;
2323
2324 predata = count = 0;
42b82dc1 2325
1c361efb
FR		 2326 for (index = 0; index < pa->size; ) {
2327 u32 action = le32_to_cpu(pa->code[index]);
bca03d5f 2328 u32 data = action & 0x0000ffff;
42b82dc1 2329 u32 regno = (action & 0x0fff0000) >> 16;
2330
2331 if (!action)
2332 break;
bca03d5f 2333
2334 switch(action & 0xf0000000) {
42b82dc1 2335 case PHY_READ:
2336 predata = rtl_readphy(tp, regno);
2337 count++;
2338 index++;
2339 break;
2340 case PHY_DATA_OR:
2341 predata |= data;
2342 index++;
2343 break;
2344 case PHY_DATA_AND:
2345 predata &= data;
2346 index++;
2347 break;
2348 case PHY_BJMPN:
2349 index -= regno;
2350 break;
2351 case PHY_READ_EFUSE:
fdf6fc06 2352 predata = rtl8168d_efuse_read(tp, regno);
42b82dc1 2353 index++;
2354 break;
2355 case PHY_CLEAR_READCOUNT:
2356 count = 0;
2357 index++;
2358 break;
bca03d5f 2359 case PHY_WRITE:
42b82dc1 2360 rtl_writephy(tp, regno, data);
2361 index++;
2362 break;
2363 case PHY_READCOUNT_EQ_SKIP:
cecb5fd7 2364 index += (count == data) ? 2 : 1;
bca03d5f 2365 break;
42b82dc1 2366 case PHY_COMP_EQ_SKIPN:
2367 if (predata == data)
2368 index += regno;
2369 index++;
2370 break;
2371 case PHY_COMP_NEQ_SKIPN:
2372 if (predata != data)
2373 index += regno;
2374 index++;
2375 break;
2376 case PHY_WRITE_PREVIOUS:
2377 rtl_writephy(tp, regno, predata);
2378 index++;
2379 break;
2380 case PHY_SKIPN:
2381 index += regno + 1;
2382 break;
2383 case PHY_DELAY_MS:
2384 mdelay(data);
2385 index++;
2386 break;
2387
2388 case PHY_READ_MAC_BYTE:
2389 case PHY_WRITE_MAC_BYTE:
2390 case PHY_WRITE_ERI_WORD:
bca03d5f 2391 default:
2392 BUG();
2393 }
2394 }
2395}
2396
f1e02ed1 2397static void rtl_release_firmware(struct rtl8169_private *tp)
2398{
b6ffd97f
FR		 2399 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2400 release_firmware(tp->rtl_fw->fw);
2401 kfree(tp->rtl_fw);
2402 }
2403 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
f1e02ed1 2404}
2405
953a12cc 2406static void rtl_apply_firmware(struct rtl8169_private *tp)
f1e02ed1 2407{
b6ffd97f 2408 struct rtl_fw *rtl_fw = tp->rtl_fw;
f1e02ed1 2409
2410 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
b6ffd97f
FR		 2411 if (!IS_ERR_OR_NULL(rtl_fw))
2412 rtl_phy_write_fw(tp, rtl_fw);
953a12cc
FR		 2413}
2414
2415static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2416{
2417 if (rtl_readphy(tp, reg) != val)
2418 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2419 else
2420 rtl_apply_firmware(tp);
f1e02ed1 2421}
2422
4da19633 2423static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1da177e4 2424{
350f7596 2425 static const struct phy_reg phy_reg_init[] = {
0b9b571d 2426 { 0x1f, 0x0001 },
2427 { 0x06, 0x006e },
2428 { 0x08, 0x0708 },
2429 { 0x15, 0x4000 },
2430 { 0x18, 0x65c7 },
1da177e4 2431
0b9b571d 2432 { 0x1f, 0x0001 },
2433 { 0x03, 0x00a1 },
2434 { 0x02, 0x0008 },
2435 { 0x01, 0x0120 },
2436 { 0x00, 0x1000 },
2437 { 0x04, 0x0800 },
2438 { 0x04, 0x0000 },
1da177e4 2439
0b9b571d 2440 { 0x03, 0xff41 },
2441 { 0x02, 0xdf60 },
2442 { 0x01, 0x0140 },
2443 { 0x00, 0x0077 },
2444 { 0x04, 0x7800 },
2445 { 0x04, 0x7000 },
2446
2447 { 0x03, 0x802f },
2448 { 0x02, 0x4f02 },
2449 { 0x01, 0x0409 },
2450 { 0x00, 0xf0f9 },
2451 { 0x04, 0x9800 },
2452 { 0x04, 0x9000 },
2453
2454 { 0x03, 0xdf01 },
2455 { 0x02, 0xdf20 },
2456 { 0x01, 0xff95 },
2457 { 0x00, 0xba00 },
2458 { 0x04, 0xa800 },
2459 { 0x04, 0xa000 },
2460
2461 { 0x03, 0xff41 },
2462 { 0x02, 0xdf20 },
2463 { 0x01, 0x0140 },
2464 { 0x00, 0x00bb },
2465 { 0x04, 0xb800 },
2466 { 0x04, 0xb000 },
2467
2468 { 0x03, 0xdf41 },
2469 { 0x02, 0xdc60 },
2470 { 0x01, 0x6340 },
2471 { 0x00, 0x007d },
2472 { 0x04, 0xd800 },
2473 { 0x04, 0xd000 },
2474
2475 { 0x03, 0xdf01 },
2476 { 0x02, 0xdf20 },
2477 { 0x01, 0x100a },
2478 { 0x00, 0xa0ff },
2479 { 0x04, 0xf800 },
2480 { 0x04, 0xf000 },
2481
2482 { 0x1f, 0x0000 },
2483 { 0x0b, 0x0000 },
2484 { 0x00, 0x9200 }
2485 };
1da177e4 2486
4da19633 2487 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1da177e4
LT		 2488}
2489
4da19633 2490static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
5615d9f1 2491{
350f7596 2492 static const struct phy_reg phy_reg_init[] = {
a441d7b6
FR		 2493 { 0x1f, 0x0002 },
2494 { 0x01, 0x90d0 },
2495 { 0x1f, 0x0000 }
2496 };
2497
4da19633 2498 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 2499}
2500
4da19633 2501static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2e955856 2502{
2503 struct pci_dev *pdev = tp->pci_dev;
2e955856 2504
ccbae55e
SS		 2505 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2506 (pdev->subsystem_device != 0xe000))
2e955856 2507 return;
2508
4da19633 2509 rtl_writephy(tp, 0x1f, 0x0001);
2510 rtl_writephy(tp, 0x10, 0xf01b);
2511 rtl_writephy(tp, 0x1f, 0x0000);
2e955856 2512}
2513
4da19633 2514static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2e955856 2515{
350f7596 2516 static const struct phy_reg phy_reg_init[] = {
2e955856 2517 { 0x1f, 0x0001 },
2518 { 0x04, 0x0000 },
2519 { 0x03, 0x00a1 },
2520 { 0x02, 0x0008 },
2521 { 0x01, 0x0120 },
2522 { 0x00, 0x1000 },
2523 { 0x04, 0x0800 },
2524 { 0x04, 0x9000 },
2525 { 0x03, 0x802f },
2526 { 0x02, 0x4f02 },
2527 { 0x01, 0x0409 },
2528 { 0x00, 0xf099 },
2529 { 0x04, 0x9800 },
2530 { 0x04, 0xa000 },
2531 { 0x03, 0xdf01 },
2532 { 0x02, 0xdf20 },
2533 { 0x01, 0xff95 },
2534 { 0x00, 0xba00 },
2535 { 0x04, 0xa800 },
2536 { 0x04, 0xf000 },
2537 { 0x03, 0xdf01 },
2538 { 0x02, 0xdf20 },
2539 { 0x01, 0x101a },
2540 { 0x00, 0xa0ff },
2541 { 0x04, 0xf800 },
2542 { 0x04, 0x0000 },
2543 { 0x1f, 0x0000 },
2544
2545 { 0x1f, 0x0001 },
2546 { 0x10, 0xf41b },
2547 { 0x14, 0xfb54 },
2548 { 0x18, 0xf5c7 },
2549 { 0x1f, 0x0000 },
2550
2551 { 0x1f, 0x0001 },
2552 { 0x17, 0x0cc0 },
2553 { 0x1f, 0x0000 }
2554 };
2555
4da19633 2556 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2e955856 2557
4da19633 2558 rtl8169scd_hw_phy_config_quirk(tp);
2e955856 2559}
2560
4da19633 2561static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
8c7006aa 2562{
350f7596 2563 static const struct phy_reg phy_reg_init[] = {
8c7006aa 2564 { 0x1f, 0x0001 },
2565 { 0x04, 0x0000 },
2566 { 0x03, 0x00a1 },
2567 { 0x02, 0x0008 },
2568 { 0x01, 0x0120 },
2569 { 0x00, 0x1000 },
2570 { 0x04, 0x0800 },
2571 { 0x04, 0x9000 },
2572 { 0x03, 0x802f },
2573 { 0x02, 0x4f02 },
2574 { 0x01, 0x0409 },
2575 { 0x00, 0xf099 },
2576 { 0x04, 0x9800 },
2577 { 0x04, 0xa000 },
2578 { 0x03, 0xdf01 },
2579 { 0x02, 0xdf20 },
2580 { 0x01, 0xff95 },
2581 { 0x00, 0xba00 },
2582 { 0x04, 0xa800 },
2583 { 0x04, 0xf000 },
2584 { 0x03, 0xdf01 },
2585 { 0x02, 0xdf20 },
2586 { 0x01, 0x101a },
2587 { 0x00, 0xa0ff },
2588 { 0x04, 0xf800 },
2589 { 0x04, 0x0000 },
2590 { 0x1f, 0x0000 },
2591
2592 { 0x1f, 0x0001 },
2593 { 0x0b, 0x8480 },
2594 { 0x1f, 0x0000 },
2595
2596 { 0x1f, 0x0001 },
2597 { 0x18, 0x67c7 },
2598 { 0x04, 0x2000 },
2599 { 0x03, 0x002f },
2600 { 0x02, 0x4360 },
2601 { 0x01, 0x0109 },
2602 { 0x00, 0x3022 },
2603 { 0x04, 0x2800 },
2604 { 0x1f, 0x0000 },
2605
2606 { 0x1f, 0x0001 },
2607 { 0x17, 0x0cc0 },
2608 { 0x1f, 0x0000 }
2609 };
2610
4da19633 2611 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
8c7006aa 2612}
2613
4da19633 2614static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
236b8082 2615{
350f7596 2616 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2617 { 0x10, 0xf41b },
2618 { 0x1f, 0x0000 }
2619 };
2620
4da19633 2621 rtl_writephy(tp, 0x1f, 0x0001);
2622 rtl_patchphy(tp, 0x16, 1 << 0);
236b8082 2623
4da19633 2624 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2625}
2626
4da19633 2627static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
236b8082 2628{
350f7596 2629 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2630 { 0x1f, 0x0001 },
2631 { 0x10, 0xf41b },
2632 { 0x1f, 0x0000 }
2633 };
2634
4da19633 2635 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2636}
2637
4da19633 2638static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2639{
350f7596 2640 static const struct phy_reg phy_reg_init[] = {
867763c1
FR		 2641 { 0x1f, 0x0000 },
2642 { 0x1d, 0x0f00 },
2643 { 0x1f, 0x0002 },
2644 { 0x0c, 0x1ec8 },
2645 { 0x1f, 0x0000 }
2646 };
2647
4da19633 2648 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
867763c1
FR		 2649}
2650
4da19633 2651static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
ef3386f0 2652{
350f7596 2653 static const struct phy_reg phy_reg_init[] = {
ef3386f0
FR		 2654 { 0x1f, 0x0001 },
2655 { 0x1d, 0x3d98 },
2656 { 0x1f, 0x0000 }
2657 };
2658
4da19633 2659 rtl_writephy(tp, 0x1f, 0x0000);
2660 rtl_patchphy(tp, 0x14, 1 << 5);
2661 rtl_patchphy(tp, 0x0d, 1 << 5);
ef3386f0 2662
4da19633 2663 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
ef3386f0
FR		 2664}
2665
4da19633 2666static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2667{
350f7596 2668 static const struct phy_reg phy_reg_init[] = {
a3f80671
FR		 2669 { 0x1f, 0x0001 },
2670 { 0x12, 0x2300 },
867763c1
FR		 2671 { 0x1f, 0x0002 },
2672 { 0x00, 0x88d4 },
2673 { 0x01, 0x82b1 },
2674 { 0x03, 0x7002 },
2675 { 0x08, 0x9e30 },
2676 { 0x09, 0x01f0 },
2677 { 0x0a, 0x5500 },
2678 { 0x0c, 0x00c8 },
2679 { 0x1f, 0x0003 },
2680 { 0x12, 0xc096 },
2681 { 0x16, 0x000a },
f50d4275
FR		 2682 { 0x1f, 0x0000 },
2683 { 0x1f, 0x0000 },
2684 { 0x09, 0x2000 },
2685 { 0x09, 0x0000 }
867763c1
FR		 2686 };
2687
4da19633 2688 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2689
4da19633 2690 rtl_patchphy(tp, 0x14, 1 << 5);
2691 rtl_patchphy(tp, 0x0d, 1 << 5);
2692 rtl_writephy(tp, 0x1f, 0x0000);
867763c1
FR		 2693}
2694
4da19633 2695static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
7da97ec9 2696{
350f7596 2697 static const struct phy_reg phy_reg_init[] = {
f50d4275 2698 { 0x1f, 0x0001 },
7da97ec9 2699 { 0x12, 0x2300 },
f50d4275
FR		 2700 { 0x03, 0x802f },
2701 { 0x02, 0x4f02 },
2702 { 0x01, 0x0409 },
2703 { 0x00, 0xf099 },
2704 { 0x04, 0x9800 },
2705 { 0x04, 0x9000 },
2706 { 0x1d, 0x3d98 },
7da97ec9
FR		 2707 { 0x1f, 0x0002 },
2708 { 0x0c, 0x7eb8 },
f50d4275
FR		 2709 { 0x06, 0x0761 },
2710 { 0x1f, 0x0003 },
2711 { 0x16, 0x0f0a },
7da97ec9
FR		 2712 { 0x1f, 0x0000 }
2713 };
2714
4da19633 2715 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2716
4da19633 2717 rtl_patchphy(tp, 0x16, 1 << 0);
2718 rtl_patchphy(tp, 0x14, 1 << 5);
2719 rtl_patchphy(tp, 0x0d, 1 << 5);
2720 rtl_writephy(tp, 0x1f, 0x0000);
7da97ec9
FR		 2721}
2722
4da19633 2723static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
197ff761 2724{
350f7596 2725 static const struct phy_reg phy_reg_init[] = {
197ff761
FR		 2726 { 0x1f, 0x0001 },
2727 { 0x12, 0x2300 },
2728 { 0x1d, 0x3d98 },
2729 { 0x1f, 0x0002 },
2730 { 0x0c, 0x7eb8 },
2731 { 0x06, 0x5461 },
2732 { 0x1f, 0x0003 },
2733 { 0x16, 0x0f0a },
2734 { 0x1f, 0x0000 }
2735 };
2736
4da19633 2737 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
197ff761 2738
4da19633 2739 rtl_patchphy(tp, 0x16, 1 << 0);
2740 rtl_patchphy(tp, 0x14, 1 << 5);
2741 rtl_patchphy(tp, 0x0d, 1 << 5);
2742 rtl_writephy(tp, 0x1f, 0x0000);
197ff761
FR		 2743}
2744
4da19633 2745static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
6fb07058 2746{
4da19633 2747 rtl8168c_3_hw_phy_config(tp);
6fb07058
FR		 2748}
2749
bca03d5f 2750static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
5b538df9 2751{
350f7596 2752 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2753 /* Channel Estimation */
5b538df9 2754 { 0x1f, 0x0001 },
daf9df6d 2755 { 0x06, 0x4064 },
2756 { 0x07, 0x2863 },
2757 { 0x08, 0x059c },
2758 { 0x09, 0x26b4 },
2759 { 0x0a, 0x6a19 },
2760 { 0x0b, 0xdcc8 },
2761 { 0x10, 0xf06d },
2762 { 0x14, 0x7f68 },
2763 { 0x18, 0x7fd9 },
2764 { 0x1c, 0xf0ff },
2765 { 0x1d, 0x3d9c },
5b538df9 2766 { 0x1f, 0x0003 },
daf9df6d 2767 { 0x12, 0xf49f },
2768 { 0x13, 0x070b },
2769 { 0x1a, 0x05ad },
bca03d5f 2770 { 0x14, 0x94c0 },
2771
2772 /*
2773 * Tx Error Issue
cecb5fd7 2774 * Enhance line driver power
bca03d5f 2775 */
5b538df9 2776 { 0x1f, 0x0002 },
daf9df6d 2777 { 0x06, 0x5561 },
2778 { 0x1f, 0x0005 },
2779 { 0x05, 0x8332 },
bca03d5f 2780 { 0x06, 0x5561 },
2781
2782 /*
2783 * Can not link to 1Gbps with bad cable
2784 * Decrease SNR threshold form 21.07dB to 19.04dB
2785 */
2786 { 0x1f, 0x0001 },
2787 { 0x17, 0x0cc0 },
daf9df6d 2788
5b538df9 2789 { 0x1f, 0x0000 },
bca03d5f 2790 { 0x0d, 0xf880 }
daf9df6d 2791 };
2792
4da19633 2793 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
daf9df6d 2794
bca03d5f 2795 /*
2796 * Rx Error Issue
2797 * Fine Tune Switching regulator parameter
2798 */
4da19633 2799 rtl_writephy(tp, 0x1f, 0x0002);
2800 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2801 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
daf9df6d 2802
fdf6fc06 2803 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
350f7596 2804 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2805 { 0x1f, 0x0002 },
2806 { 0x05, 0x669a },
2807 { 0x1f, 0x0005 },
2808 { 0x05, 0x8330 },
2809 { 0x06, 0x669a },
2810 { 0x1f, 0x0002 }
2811 };
2812 int val;
2813
4da19633 2814 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2815
4da19633 2816 val = rtl_readphy(tp, 0x0d);
daf9df6d 2817
2818 if ((val & 0x00ff) != 0x006c) {
350f7596 2819 static const u32 set[] = {
daf9df6d 2820 0x0065, 0x0066, 0x0067, 0x0068,
2821 0x0069, 0x006a, 0x006b, 0x006c
2822 };
2823 int i;
2824
4da19633 2825 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2826
2827 val &= 0xff00;
2828 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2829 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2830 }
2831 } else {
350f7596 2832 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2833 { 0x1f, 0x0002 },
2834 { 0x05, 0x6662 },
2835 { 0x1f, 0x0005 },
2836 { 0x05, 0x8330 },
2837 { 0x06, 0x6662 }
2838 };
2839
4da19633 2840 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2841 }
2842
bca03d5f 2843 /* RSET couple improve */
4da19633 2844 rtl_writephy(tp, 0x1f, 0x0002);
2845 rtl_patchphy(tp, 0x0d, 0x0300);
2846 rtl_patchphy(tp, 0x0f, 0x0010);
daf9df6d 2847
bca03d5f 2848 /* Fine tune PLL performance */
4da19633 2849 rtl_writephy(tp, 0x1f, 0x0002);
2850 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2851 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2852
4da19633 2853 rtl_writephy(tp, 0x1f, 0x0005);
2854 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2855
2856 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
bca03d5f 2857
4da19633 2858 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2859}
2860
bca03d5f 2861static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2862{
350f7596 2863 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2864 /* Channel Estimation */
daf9df6d 2865 { 0x1f, 0x0001 },
2866 { 0x06, 0x4064 },
2867 { 0x07, 0x2863 },
2868 { 0x08, 0x059c },
2869 { 0x09, 0x26b4 },
2870 { 0x0a, 0x6a19 },
2871 { 0x0b, 0xdcc8 },
2872 { 0x10, 0xf06d },
2873 { 0x14, 0x7f68 },
2874 { 0x18, 0x7fd9 },
2875 { 0x1c, 0xf0ff },
2876 { 0x1d, 0x3d9c },
2877 { 0x1f, 0x0003 },
2878 { 0x12, 0xf49f },
2879 { 0x13, 0x070b },
2880 { 0x1a, 0x05ad },
2881 { 0x14, 0x94c0 },
2882
bca03d5f 2883 /*
2884 * Tx Error Issue
cecb5fd7 2885 * Enhance line driver power
bca03d5f 2886 */
daf9df6d 2887 { 0x1f, 0x0002 },
2888 { 0x06, 0x5561 },
2889 { 0x1f, 0x0005 },
2890 { 0x05, 0x8332 },
bca03d5f 2891 { 0x06, 0x5561 },
2892
2893 /*
2894 * Can not link to 1Gbps with bad cable
2895 * Decrease SNR threshold form 21.07dB to 19.04dB
2896 */
2897 { 0x1f, 0x0001 },
2898 { 0x17, 0x0cc0 },
daf9df6d 2899
2900 { 0x1f, 0x0000 },
bca03d5f 2901 { 0x0d, 0xf880 }
5b538df9
FR		 2902 };
2903
4da19633 2904 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
5b538df9 2905
fdf6fc06 2906 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
350f7596 2907 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2908 { 0x1f, 0x0002 },
2909 { 0x05, 0x669a },
5b538df9 2910 { 0x1f, 0x0005 },
daf9df6d 2911 { 0x05, 0x8330 },
2912 { 0x06, 0x669a },
2913
2914 { 0x1f, 0x0002 }
2915 };
2916 int val;
2917
4da19633 2918 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2919
4da19633 2920 val = rtl_readphy(tp, 0x0d);
daf9df6d 2921 if ((val & 0x00ff) != 0x006c) {
b6bc7650 2922 static const u32 set[] = {
daf9df6d 2923 0x0065, 0x0066, 0x0067, 0x0068,
2924 0x0069, 0x006a, 0x006b, 0x006c
2925 };
2926 int i;
2927
4da19633 2928 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2929
2930 val &= 0xff00;
2931 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2932 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2933 }
2934 } else {
350f7596 2935 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2936 { 0x1f, 0x0002 },
2937 { 0x05, 0x2642 },
5b538df9 2938 { 0x1f, 0x0005 },
daf9df6d 2939 { 0x05, 0x8330 },
2940 { 0x06, 0x2642 }
5b538df9
FR		 2941 };
2942
4da19633 2943 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2944 }
2945
bca03d5f 2946 /* Fine tune PLL performance */
4da19633 2947 rtl_writephy(tp, 0x1f, 0x0002);
2948 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2949 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2950
bca03d5f 2951 /* Switching regulator Slew rate */
4da19633 2952 rtl_writephy(tp, 0x1f, 0x0002);
2953 rtl_patchphy(tp, 0x0f, 0x0017);
daf9df6d 2954
4da19633 2955 rtl_writephy(tp, 0x1f, 0x0005);
2956 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2957
2958 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
bca03d5f 2959
4da19633 2960 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2961}
2962
4da19633 2963static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2964{
350f7596 2965 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2966 { 0x1f, 0x0002 },
2967 { 0x10, 0x0008 },
2968 { 0x0d, 0x006c },
2969
2970 { 0x1f, 0x0000 },
2971 { 0x0d, 0xf880 },
2972
2973 { 0x1f, 0x0001 },
2974 { 0x17, 0x0cc0 },
2975
2976 { 0x1f, 0x0001 },
2977 { 0x0b, 0xa4d8 },
2978 { 0x09, 0x281c },
2979 { 0x07, 0x2883 },
2980 { 0x0a, 0x6b35 },
2981 { 0x1d, 0x3da4 },
2982 { 0x1c, 0xeffd },
2983 { 0x14, 0x7f52 },
2984 { 0x18, 0x7fc6 },
2985 { 0x08, 0x0601 },
2986 { 0x06, 0x4063 },
2987 { 0x10, 0xf074 },
2988 { 0x1f, 0x0003 },
2989 { 0x13, 0x0789 },
2990 { 0x12, 0xf4bd },
2991 { 0x1a, 0x04fd },
2992 { 0x14, 0x84b0 },
2993 { 0x1f, 0x0000 },
2994 { 0x00, 0x9200 },
2995
2996 { 0x1f, 0x0005 },
2997 { 0x01, 0x0340 },
2998 { 0x1f, 0x0001 },
2999 { 0x04, 0x4000 },
3000 { 0x03, 0x1d21 },
3001 { 0x02, 0x0c32 },
3002 { 0x01, 0x0200 },
3003 { 0x00, 0x5554 },
3004 { 0x04, 0x4800 },
3005 { 0x04, 0x4000 },
3006 { 0x04, 0xf000 },
3007 { 0x03, 0xdf01 },
3008 { 0x02, 0xdf20 },
3009 { 0x01, 0x101a },
3010 { 0x00, 0xa0ff },
3011 { 0x04, 0xf800 },
3012 { 0x04, 0xf000 },
3013 { 0x1f, 0x0000 },
3014
3015 { 0x1f, 0x0007 },
3016 { 0x1e, 0x0023 },
3017 { 0x16, 0x0000 },
3018 { 0x1f, 0x0000 }
3019 };
3020
4da19633 3021 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 3022}
3023
e6de30d6 3024static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3025{
3026 static const struct phy_reg phy_reg_init[] = {
3027 { 0x1f, 0x0001 },
3028 { 0x17, 0x0cc0 },
3029
3030 { 0x1f, 0x0007 },
3031 { 0x1e, 0x002d },
3032 { 0x18, 0x0040 },
3033 { 0x1f, 0x0000 }
3034 };
3035
3036 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3037 rtl_patchphy(tp, 0x0d, 1 << 5);
3038}
3039
70090424 3040static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
01dc7fec 3041{
3042 static const struct phy_reg phy_reg_init[] = {
3043 /* Enable Delay cap */
3044 { 0x1f, 0x0005 },
3045 { 0x05, 0x8b80 },
3046 { 0x06, 0xc896 },
3047 { 0x1f, 0x0000 },
3048
3049 /* Channel estimation fine tune */
3050 { 0x1f, 0x0001 },
3051 { 0x0b, 0x6c20 },
3052 { 0x07, 0x2872 },
3053 { 0x1c, 0xefff },
3054 { 0x1f, 0x0003 },
3055 { 0x14, 0x6420 },
3056 { 0x1f, 0x0000 },
3057
3058 /* Update PFM & 10M TX idle timer */
3059 { 0x1f, 0x0007 },
3060 { 0x1e, 0x002f },
3061 { 0x15, 0x1919 },
3062 { 0x1f, 0x0000 },
3063
3064 { 0x1f, 0x0007 },
3065 { 0x1e, 0x00ac },
3066 { 0x18, 0x0006 },
3067 { 0x1f, 0x0000 }
3068 };
3069
15ecd039
FR		 3070 rtl_apply_firmware(tp);
3071
01dc7fec 3072 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3073
3074 /* DCO enable for 10M IDLE Power */
3075 rtl_writephy(tp, 0x1f, 0x0007);
3076 rtl_writephy(tp, 0x1e, 0x0023);
3077 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
3078 rtl_writephy(tp, 0x1f, 0x0000);
3079
3080 /* For impedance matching */
3081 rtl_writephy(tp, 0x1f, 0x0002);
3082 rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
cecb5fd7 3083 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3084
3085 /* PHY auto speed down */
3086 rtl_writephy(tp, 0x1f, 0x0007);
3087 rtl_writephy(tp, 0x1e, 0x002d);
3088 rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
3089 rtl_writephy(tp, 0x1f, 0x0000);
3090 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3091
3092 rtl_writephy(tp, 0x1f, 0x0005);
3093 rtl_writephy(tp, 0x05, 0x8b86);
3094 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3095 rtl_writephy(tp, 0x1f, 0x0000);
3096
3097 rtl_writephy(tp, 0x1f, 0x0005);
3098 rtl_writephy(tp, 0x05, 0x8b85);
3099 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3100 rtl_writephy(tp, 0x1f, 0x0007);
3101 rtl_writephy(tp, 0x1e, 0x0020);
3102 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
3103 rtl_writephy(tp, 0x1f, 0x0006);
3104 rtl_writephy(tp, 0x00, 0x5a00);
3105 rtl_writephy(tp, 0x1f, 0x0000);
3106 rtl_writephy(tp, 0x0d, 0x0007);
3107 rtl_writephy(tp, 0x0e, 0x003c);
3108 rtl_writephy(tp, 0x0d, 0x4007);
3109 rtl_writephy(tp, 0x0e, 0x0000);
3110 rtl_writephy(tp, 0x0d, 0x0000);
3111}
3112
70090424
HW		 3113static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3114{
3115 static const struct phy_reg phy_reg_init[] = {
3116 /* Enable Delay cap */
3117 { 0x1f, 0x0004 },
3118 { 0x1f, 0x0007 },
3119 { 0x1e, 0x00ac },
3120 { 0x18, 0x0006 },
3121 { 0x1f, 0x0002 },
3122 { 0x1f, 0x0000 },
3123 { 0x1f, 0x0000 },
3124
3125 /* Channel estimation fine tune */
3126 { 0x1f, 0x0003 },
3127 { 0x09, 0xa20f },
3128 { 0x1f, 0x0000 },
3129 { 0x1f, 0x0000 },
3130
3131 /* Green Setting */
3132 { 0x1f, 0x0005 },
3133 { 0x05, 0x8b5b },
3134 { 0x06, 0x9222 },
3135 { 0x05, 0x8b6d },
3136 { 0x06, 0x8000 },
3137 { 0x05, 0x8b76 },
3138 { 0x06, 0x8000 },
3139 { 0x1f, 0x0000 }
3140 };
3141
3142 rtl_apply_firmware(tp);
3143
3144 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3145
3146 /* For 4-corner performance improve */
3147 rtl_writephy(tp, 0x1f, 0x0005);
3148 rtl_writephy(tp, 0x05, 0x8b80);
3149 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
3150 rtl_writephy(tp, 0x1f, 0x0000);
3151
3152 /* PHY auto speed down */
3153 rtl_writephy(tp, 0x1f, 0x0004);
3154 rtl_writephy(tp, 0x1f, 0x0007);
3155 rtl_writephy(tp, 0x1e, 0x002d);
3156 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3157 rtl_writephy(tp, 0x1f, 0x0002);
3158 rtl_writephy(tp, 0x1f, 0x0000);
3159 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3160
3161 /* improve 10M EEE waveform */
3162 rtl_writephy(tp, 0x1f, 0x0005);
3163 rtl_writephy(tp, 0x05, 0x8b86);
3164 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3165 rtl_writephy(tp, 0x1f, 0x0000);
3166
3167 /* Improve 2-pair detection performance */
3168 rtl_writephy(tp, 0x1f, 0x0005);
3169 rtl_writephy(tp, 0x05, 0x8b85);
3170 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3171 rtl_writephy(tp, 0x1f, 0x0000);
3172
3173 /* EEE setting */
fdf6fc06 3174 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, ERIAR_EXGMAC);
70090424
HW		 3175 rtl_writephy(tp, 0x1f, 0x0005);
3176 rtl_writephy(tp, 0x05, 0x8b85);
3177 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3178 rtl_writephy(tp, 0x1f, 0x0004);
3179 rtl_writephy(tp, 0x1f, 0x0007);
3180 rtl_writephy(tp, 0x1e, 0x0020);
1b23a3e3 3181 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
70090424
HW		 3182 rtl_writephy(tp, 0x1f, 0x0002);
3183 rtl_writephy(tp, 0x1f, 0x0000);
3184 rtl_writephy(tp, 0x0d, 0x0007);
3185 rtl_writephy(tp, 0x0e, 0x003c);
3186 rtl_writephy(tp, 0x0d, 0x4007);
3187 rtl_writephy(tp, 0x0e, 0x0000);
3188 rtl_writephy(tp, 0x0d, 0x0000);
3189
3190 /* Green feature */
3191 rtl_writephy(tp, 0x1f, 0x0003);
3192 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3193 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3194 rtl_writephy(tp, 0x1f, 0x0000);
3195}
3196
5f886e08
HW		 3197static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3198{
3199 /* For 4-corner performance improve */
3200 rtl_writephy(tp, 0x1f, 0x0005);
3201 rtl_writephy(tp, 0x05, 0x8b80);
3202 rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3203 rtl_writephy(tp, 0x1f, 0x0000);
3204
3205 /* PHY auto speed down */
3206 rtl_writephy(tp, 0x1f, 0x0007);
3207 rtl_writephy(tp, 0x1e, 0x002d);
3208 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3209 rtl_writephy(tp, 0x1f, 0x0000);
3210 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3211
3212 /* Improve 10M EEE waveform */
3213 rtl_writephy(tp, 0x1f, 0x0005);
3214 rtl_writephy(tp, 0x05, 0x8b86);
3215 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3216 rtl_writephy(tp, 0x1f, 0x0000);
3217}
3218
c2218925
HW		 3219static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3220{
3221 static const struct phy_reg phy_reg_init[] = {
3222 /* Channel estimation fine tune */
3223 { 0x1f, 0x0003 },
3224 { 0x09, 0xa20f },
3225 { 0x1f, 0x0000 },
3226
3227 /* Modify green table for giga & fnet */
3228 { 0x1f, 0x0005 },
3229 { 0x05, 0x8b55 },
3230 { 0x06, 0x0000 },
3231 { 0x05, 0x8b5e },
3232 { 0x06, 0x0000 },
3233 { 0x05, 0x8b67 },
3234 { 0x06, 0x0000 },
3235 { 0x05, 0x8b70 },
3236 { 0x06, 0x0000 },
3237 { 0x1f, 0x0000 },
3238 { 0x1f, 0x0007 },
3239 { 0x1e, 0x0078 },
3240 { 0x17, 0x0000 },
3241 { 0x19, 0x00fb },
3242 { 0x1f, 0x0000 },
3243
3244 /* Modify green table for 10M */
3245 { 0x1f, 0x0005 },
3246 { 0x05, 0x8b79 },
3247 { 0x06, 0xaa00 },
3248 { 0x1f, 0x0000 },
3249
3250 /* Disable hiimpedance detection (RTCT) */
3251 { 0x1f, 0x0003 },
3252 { 0x01, 0x328a },
3253 { 0x1f, 0x0000 }
3254 };
3255
3256 rtl_apply_firmware(tp);
3257
3258 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3259
5f886e08 3260 rtl8168f_hw_phy_config(tp);
c2218925
HW		 3261
3262 /* Improve 2-pair detection performance */
3263 rtl_writephy(tp, 0x1f, 0x0005);
3264 rtl_writephy(tp, 0x05, 0x8b85);
3265 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3266 rtl_writephy(tp, 0x1f, 0x0000);
3267}
3268
3269static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3270{
3271 rtl_apply_firmware(tp);
3272
5f886e08 3273 rtl8168f_hw_phy_config(tp);
c2218925
HW		 3274}
3275
b3d7b2f2
HW		 3276static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3277{
b3d7b2f2
HW		 3278 static const struct phy_reg phy_reg_init[] = {
3279 /* Channel estimation fine tune */
3280 { 0x1f, 0x0003 },
3281 { 0x09, 0xa20f },
3282 { 0x1f, 0x0000 },
3283
3284 /* Modify green table for giga & fnet */
3285 { 0x1f, 0x0005 },
3286 { 0x05, 0x8b55 },
3287 { 0x06, 0x0000 },
3288 { 0x05, 0x8b5e },
3289 { 0x06, 0x0000 },
3290 { 0x05, 0x8b67 },
3291 { 0x06, 0x0000 },
3292 { 0x05, 0x8b70 },
3293 { 0x06, 0x0000 },
3294 { 0x1f, 0x0000 },
3295 { 0x1f, 0x0007 },
3296 { 0x1e, 0x0078 },
3297 { 0x17, 0x0000 },
3298 { 0x19, 0x00aa },
3299 { 0x1f, 0x0000 },
3300
3301 /* Modify green table for 10M */
3302 { 0x1f, 0x0005 },
3303 { 0x05, 0x8b79 },
3304 { 0x06, 0xaa00 },
3305 { 0x1f, 0x0000 },
3306
3307 /* Disable hiimpedance detection (RTCT) */
3308 { 0x1f, 0x0003 },
3309 { 0x01, 0x328a },
3310 { 0x1f, 0x0000 }
3311 };
3312
3313
3314 rtl_apply_firmware(tp);
3315
3316 rtl8168f_hw_phy_config(tp);
3317
3318 /* Improve 2-pair detection performance */
3319 rtl_writephy(tp, 0x1f, 0x0005);
3320 rtl_writephy(tp, 0x05, 0x8b85);
3321 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3322 rtl_writephy(tp, 0x1f, 0x0000);
3323
3324 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3325
3326 /* Modify green table for giga */
3327 rtl_writephy(tp, 0x1f, 0x0005);
3328 rtl_writephy(tp, 0x05, 0x8b54);
3329 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
3330 rtl_writephy(tp, 0x05, 0x8b5d);
3331 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
3332 rtl_writephy(tp, 0x05, 0x8a7c);
3333 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3334 rtl_writephy(tp, 0x05, 0x8a7f);
3335 rtl_w1w0_phy(tp, 0x06, 0x0100, 0x0000);
3336 rtl_writephy(tp, 0x05, 0x8a82);
3337 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3338 rtl_writephy(tp, 0x05, 0x8a85);
3339 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3340 rtl_writephy(tp, 0x05, 0x8a88);
3341 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3342 rtl_writephy(tp, 0x1f, 0x0000);
3343
3344 /* uc same-seed solution */
3345 rtl_writephy(tp, 0x1f, 0x0005);
3346 rtl_writephy(tp, 0x05, 0x8b85);
3347 rtl_w1w0_phy(tp, 0x06, 0x8000, 0x0000);
3348 rtl_writephy(tp, 0x1f, 0x0000);
3349
3350 /* eee setting */
fdf6fc06 3351 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
b3d7b2f2
HW		 3352 rtl_writephy(tp, 0x1f, 0x0005);
3353 rtl_writephy(tp, 0x05, 0x8b85);
3354 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3355 rtl_writephy(tp, 0x1f, 0x0004);
3356 rtl_writephy(tp, 0x1f, 0x0007);
3357 rtl_writephy(tp, 0x1e, 0x0020);
3358 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
3359 rtl_writephy(tp, 0x1f, 0x0000);
3360 rtl_writephy(tp, 0x0d, 0x0007);
3361 rtl_writephy(tp, 0x0e, 0x003c);
3362 rtl_writephy(tp, 0x0d, 0x4007);
3363 rtl_writephy(tp, 0x0e, 0x0000);
3364 rtl_writephy(tp, 0x0d, 0x0000);
3365
3366 /* Green feature */
3367 rtl_writephy(tp, 0x1f, 0x0003);
3368 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3369 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3370 rtl_writephy(tp, 0x1f, 0x0000);
3371}
3372
c558386b
HW		 3373static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3374{
3375 static const u16 mac_ocp_patch[] = {
3376 0xe008, 0xe01b, 0xe01d, 0xe01f,
3377 0xe021, 0xe023, 0xe025, 0xe027,
3378 0x49d2, 0xf10d, 0x766c, 0x49e2,
3379 0xf00a, 0x1ec0, 0x8ee1, 0xc60a,
3380
3381 0x77c0, 0x4870, 0x9fc0, 0x1ea0,
3382 0xc707, 0x8ee1, 0x9d6c, 0xc603,
3383 0xbe00, 0xb416, 0x0076, 0xe86c,
3384 0xc602, 0xbe00, 0x0000, 0xc602,
3385
3386 0xbe00, 0x0000, 0xc602, 0xbe00,
3387 0x0000, 0xc602, 0xbe00, 0x0000,
3388 0xc602, 0xbe00, 0x0000, 0xc602,
3389 0xbe00, 0x0000, 0xc602, 0xbe00,
3390
3391 0x0000, 0x0000, 0x0000, 0x0000
3392 };
3393 u32 i;
3394
3395 /* Patch code for GPHY reset */
3396 for (i = 0; i < ARRAY_SIZE(mac_ocp_patch); i++)
3397 r8168_mac_ocp_write(tp, 0xf800 + 2*i, mac_ocp_patch[i]);
3398 r8168_mac_ocp_write(tp, 0xfc26, 0x8000);
3399 r8168_mac_ocp_write(tp, 0xfc28, 0x0075);
3400
3401 rtl_apply_firmware(tp);
3402
3403 if (r8168_phy_ocp_read(tp, 0xa460) & 0x0100)
3404 rtl_w1w0_phy_ocp(tp, 0xbcc4, 0x0000, 0x8000);
3405 else
3406 rtl_w1w0_phy_ocp(tp, 0xbcc4, 0x8000, 0x0000);
3407
3408 if (r8168_phy_ocp_read(tp, 0xa466) & 0x0100)
3409 rtl_w1w0_phy_ocp(tp, 0xc41a, 0x0002, 0x0000);
3410 else
3411 rtl_w1w0_phy_ocp(tp, 0xbcc4, 0x0000, 0x0002);
3412
3413 rtl_w1w0_phy_ocp(tp, 0xa442, 0x000c, 0x0000);
3414 rtl_w1w0_phy_ocp(tp, 0xa4b2, 0x0004, 0x0000);
3415
3416 r8168_phy_ocp_write(tp, 0xa436, 0x8012);
3417 rtl_w1w0_phy_ocp(tp, 0xa438, 0x8000, 0x0000);
3418
3419 rtl_w1w0_phy_ocp(tp, 0xc422, 0x4000, 0x2000);
3420}
3421
4da19633 3422static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2857ffb7 3423{
350f7596 3424 static const struct phy_reg phy_reg_init[] = {
2857ffb7
FR		 3425 { 0x1f, 0x0003 },
3426 { 0x08, 0x441d },
3427 { 0x01, 0x9100 },
3428 { 0x1f, 0x0000 }
3429 };
3430
4da19633 3431 rtl_writephy(tp, 0x1f, 0x0000);
3432 rtl_patchphy(tp, 0x11, 1 << 12);
3433 rtl_patchphy(tp, 0x19, 1 << 13);
3434 rtl_patchphy(tp, 0x10, 1 << 15);
2857ffb7 3435
4da19633 3436 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2857ffb7
FR		 3437}
3438
5a5e4443
HW		 3439static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3440{
3441 static const struct phy_reg phy_reg_init[] = {
3442 { 0x1f, 0x0005 },
3443 { 0x1a, 0x0000 },
3444 { 0x1f, 0x0000 },
3445
3446 { 0x1f, 0x0004 },
3447 { 0x1c, 0x0000 },
3448 { 0x1f, 0x0000 },
3449
3450 { 0x1f, 0x0001 },
3451 { 0x15, 0x7701 },
3452 { 0x1f, 0x0000 }
3453 };
3454
3455 /* Disable ALDPS before ram code */
3456 rtl_writephy(tp, 0x1f, 0x0000);
3457 rtl_writephy(tp, 0x18, 0x0310);
3458 msleep(100);
3459
953a12cc 3460 rtl_apply_firmware(tp);
5a5e4443
HW		 3461
3462 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3463}
3464
7e18dca1
HW		 3465static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3466{
7e18dca1
HW		 3467 /* Disable ALDPS before setting firmware */
3468 rtl_writephy(tp, 0x1f, 0x0000);
3469 rtl_writephy(tp, 0x18, 0x0310);
3470 msleep(20);
3471
3472 rtl_apply_firmware(tp);
3473
3474 /* EEE setting */
fdf6fc06 3475 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
7e18dca1
HW		 3476 rtl_writephy(tp, 0x1f, 0x0004);
3477 rtl_writephy(tp, 0x10, 0x401f);
3478 rtl_writephy(tp, 0x19, 0x7030);
3479 rtl_writephy(tp, 0x1f, 0x0000);
3480}
3481
5598bfe5
HW		 3482static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3483{
5598bfe5
HW		 3484 static const struct phy_reg phy_reg_init[] = {
3485 { 0x1f, 0x0004 },
3486 { 0x10, 0xc07f },
3487 { 0x19, 0x7030 },
3488 { 0x1f, 0x0000 }
3489 };
3490
3491 /* Disable ALDPS before ram code */
3492 rtl_writephy(tp, 0x1f, 0x0000);
3493 rtl_writephy(tp, 0x18, 0x0310);
3494 msleep(100);
3495
3496 rtl_apply_firmware(tp);
3497
fdf6fc06 3498 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5598bfe5
HW		 3499 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3500
fdf6fc06 3501 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5598bfe5
HW		 3502}
3503
5615d9f1
FR		 3504static void rtl_hw_phy_config(struct net_device *dev)
3505{
3506 struct rtl8169_private *tp = netdev_priv(dev);
5615d9f1
FR		 3507
3508 rtl8169_print_mac_version(tp);
3509
3510 switch (tp->mac_version) {
3511 case RTL_GIGA_MAC_VER_01:
3512 break;
3513 case RTL_GIGA_MAC_VER_02:
3514 case RTL_GIGA_MAC_VER_03:
4da19633 3515 rtl8169s_hw_phy_config(tp);
5615d9f1
FR		 3516 break;
3517 case RTL_GIGA_MAC_VER_04:
4da19633 3518 rtl8169sb_hw_phy_config(tp);
5615d9f1 3519 break;
2e955856 3520 case RTL_GIGA_MAC_VER_05:
4da19633 3521 rtl8169scd_hw_phy_config(tp);
2e955856 3522 break;
8c7006aa 3523 case RTL_GIGA_MAC_VER_06:
4da19633 3524 rtl8169sce_hw_phy_config(tp);
8c7006aa 3525 break;
2857ffb7
FR		 3526 case RTL_GIGA_MAC_VER_07:
3527 case RTL_GIGA_MAC_VER_08:
3528 case RTL_GIGA_MAC_VER_09:
4da19633 3529 rtl8102e_hw_phy_config(tp);
2857ffb7 3530 break;
236b8082 3531 case RTL_GIGA_MAC_VER_11:
4da19633 3532 rtl8168bb_hw_phy_config(tp);
236b8082
FR		 3533 break;
3534 case RTL_GIGA_MAC_VER_12:
4da19633 3535 rtl8168bef_hw_phy_config(tp);
236b8082
FR		 3536 break;
3537 case RTL_GIGA_MAC_VER_17:
4da19633 3538 rtl8168bef_hw_phy_config(tp);
236b8082 3539 break;
867763c1 3540 case RTL_GIGA_MAC_VER_18:
4da19633 3541 rtl8168cp_1_hw_phy_config(tp);
867763c1
FR		 3542 break;
3543 case RTL_GIGA_MAC_VER_19:
4da19633 3544 rtl8168c_1_hw_phy_config(tp);
867763c1 3545 break;
7da97ec9 3546 case RTL_GIGA_MAC_VER_20:
4da19633 3547 rtl8168c_2_hw_phy_config(tp);
7da97ec9 3548 break;
197ff761 3549 case RTL_GIGA_MAC_VER_21:
4da19633 3550 rtl8168c_3_hw_phy_config(tp);
197ff761 3551 break;
6fb07058 3552 case RTL_GIGA_MAC_VER_22:
4da19633 3553 rtl8168c_4_hw_phy_config(tp);
6fb07058 3554 break;
ef3386f0 3555 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 3556 case RTL_GIGA_MAC_VER_24:
4da19633 3557 rtl8168cp_2_hw_phy_config(tp);
ef3386f0 3558 break;
5b538df9 3559 case RTL_GIGA_MAC_VER_25:
bca03d5f 3560 rtl8168d_1_hw_phy_config(tp);
daf9df6d 3561 break;
3562 case RTL_GIGA_MAC_VER_26:
bca03d5f 3563 rtl8168d_2_hw_phy_config(tp);
daf9df6d 3564 break;
3565 case RTL_GIGA_MAC_VER_27:
4da19633 3566 rtl8168d_3_hw_phy_config(tp);
5b538df9 3567 break;
e6de30d6 3568 case RTL_GIGA_MAC_VER_28:
3569 rtl8168d_4_hw_phy_config(tp);
3570 break;
5a5e4443
HW		 3571 case RTL_GIGA_MAC_VER_29:
3572 case RTL_GIGA_MAC_VER_30:
3573 rtl8105e_hw_phy_config(tp);
3574 break;
cecb5fd7
FR		 3575 case RTL_GIGA_MAC_VER_31:
3576 /* None. */
3577 break;
01dc7fec 3578 case RTL_GIGA_MAC_VER_32:
01dc7fec 3579 case RTL_GIGA_MAC_VER_33:
70090424
HW		 3580 rtl8168e_1_hw_phy_config(tp);
3581 break;
3582 case RTL_GIGA_MAC_VER_34:
3583 rtl8168e_2_hw_phy_config(tp);
01dc7fec 3584 break;
c2218925
HW		 3585 case RTL_GIGA_MAC_VER_35:
3586 rtl8168f_1_hw_phy_config(tp);
3587 break;
3588 case RTL_GIGA_MAC_VER_36:
3589 rtl8168f_2_hw_phy_config(tp);
3590 break;
ef3386f0 3591
7e18dca1
HW		 3592 case RTL_GIGA_MAC_VER_37:
3593 rtl8402_hw_phy_config(tp);
3594 break;
3595
b3d7b2f2
HW		 3596 case RTL_GIGA_MAC_VER_38:
3597 rtl8411_hw_phy_config(tp);
3598 break;
3599
5598bfe5
HW		 3600 case RTL_GIGA_MAC_VER_39:
3601 rtl8106e_hw_phy_config(tp);
3602 break;
3603
c558386b
HW		 3604 case RTL_GIGA_MAC_VER_40:
3605 rtl8168g_1_hw_phy_config(tp);
3606 break;
3607
3608 case RTL_GIGA_MAC_VER_41:
5615d9f1
FR		 3609 default:
3610 break;
3611 }
3612}
3613
da78dbff 3614static void rtl_phy_work(struct rtl8169_private *tp)
1da177e4 3615{
1da177e4
LT		 3616 struct timer_list *timer = &tp->timer;
3617 void __iomem *ioaddr = tp->mmio_addr;
3618 unsigned long timeout = RTL8169_PHY_TIMEOUT;
3619
bcf0bf90 3620 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 3621
4da19633 3622 if (tp->phy_reset_pending(tp)) {
5b0384f4 3623 /*
1da177e4
LT		 3624 * A busy loop could burn quite a few cycles on nowadays CPU.
3625 * Let's delay the execution of the timer for a few ticks.
3626 */
3627 timeout = HZ/10;
3628 goto out_mod_timer;
3629 }
3630
3631 if (tp->link_ok(ioaddr))
da78dbff 3632 return;
1da177e4 3633
da78dbff 3634 netif_warn(tp, link, tp->dev, "PHY reset until link up\n");
1da177e4 3635
4da19633 3636 tp->phy_reset_enable(tp);
1da177e4
LT		 3637
3638out_mod_timer:
3639 mod_timer(timer, jiffies + timeout);
da78dbff
FR		 3640}
3641
3642static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3643{
da78dbff
FR		 3644 if (!test_and_set_bit(flag, tp->wk.flags))
3645 schedule_work(&tp->wk.work);
da78dbff
FR		 3646}
3647
3648static void rtl8169_phy_timer(unsigned long __opaque)
3649{
3650 struct net_device *dev = (struct net_device *)__opaque;
3651 struct rtl8169_private *tp = netdev_priv(dev);
3652
98ddf986 3653 rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
1da177e4
LT		 3654}
3655
1da177e4
LT		 3656static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3657 void __iomem *ioaddr)
3658{
3659 iounmap(ioaddr);
3660 pci_release_regions(pdev);
87aeec76 3661 pci_clear_mwi(pdev);
1da177e4
LT		 3662 pci_disable_device(pdev);
3663 free_netdev(dev);
3664}
3665
ffc46952
FR		 3666DECLARE_RTL_COND(rtl_phy_reset_cond)
3667{
3668 return tp->phy_reset_pending(tp);
3669}
3670
bf793295
FR		 3671static void rtl8169_phy_reset(struct net_device *dev,
3672 struct rtl8169_private *tp)
3673{
4da19633 3674 tp->phy_reset_enable(tp);
ffc46952 3675 rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100);
bf793295
FR		 3676}
3677
2544bfc0
FR		 3678static bool rtl_tbi_enabled(struct rtl8169_private *tp)
3679{
3680 void __iomem *ioaddr = tp->mmio_addr;
3681
3682 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
3683 (RTL_R8(PHYstatus) & TBI_Enable);
3684}
3685
4ff96fa6
FR		 3686static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3687{
3688 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 3689
5615d9f1 3690 rtl_hw_phy_config(dev);
4ff96fa6 3691
77332894
MS		 3692 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3693 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3694 RTL_W8(0x82, 0x01);
3695 }
4ff96fa6 3696
6dccd16b
FR		 3697 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3698
3699 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3700 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 3701
bcf0bf90 3702 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 3703 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3704 RTL_W8(0x82, 0x01);
3705 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4da19633 3706 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4ff96fa6
FR		 3707 }
3708
bf793295
FR		 3709 rtl8169_phy_reset(dev, tp);
3710
54405cde 3711 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
cecb5fd7
FR		 3712 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3713 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3714 (tp->mii.supports_gmii ?
3715 ADVERTISED_1000baseT_Half |
3716 ADVERTISED_1000baseT_Full : 0));
4ff96fa6 3717
2544bfc0 3718 if (rtl_tbi_enabled(tp))
bf82c189 3719 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4ff96fa6
FR		 3720}
3721
773d2021
FR		 3722static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3723{
3724 void __iomem *ioaddr = tp->mmio_addr;
3725 u32 high;
3726 u32 low;
3727
3728 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
3729 high = addr[4] | (addr[5] << 8);
3730
da78dbff 3731 rtl_lock_work(tp);
773d2021
FR		 3732
3733 RTL_W8(Cfg9346, Cfg9346_Unlock);
908ba2bf 3734
773d2021 3735 RTL_W32(MAC4, high);
908ba2bf 3736 RTL_R32(MAC4);
3737
78f1cd02 3738 RTL_W32(MAC0, low);
908ba2bf 3739 RTL_R32(MAC0);
3740
c28aa385 3741 if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
3742 const struct exgmac_reg e[] = {
3743 { .addr = 0xe0, ERIAR_MASK_1111, .val = low },
3744 { .addr = 0xe4, ERIAR_MASK_1111, .val = high },
3745 { .addr = 0xf0, ERIAR_MASK_1111, .val = low << 16 },
3746 { .addr = 0xf4, ERIAR_MASK_1111, .val = high << 16 |
3747 low >> 16 },
3748 };
3749
fdf6fc06 3750 rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
c28aa385 3751 }
3752
773d2021
FR		 3753 RTL_W8(Cfg9346, Cfg9346_Lock);
3754
da78dbff 3755 rtl_unlock_work(tp);
773d2021
FR		 3756}
3757
3758static int rtl_set_mac_address(struct net_device *dev, void *p)
3759{
3760 struct rtl8169_private *tp = netdev_priv(dev);
3761 struct sockaddr *addr = p;
3762
3763 if (!is_valid_ether_addr(addr->sa_data))
3764 return -EADDRNOTAVAIL;
3765
3766 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3767
3768 rtl_rar_set(tp, dev->dev_addr);
3769
3770 return 0;
3771}
3772
5f787a1a
FR		 3773static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3774{
3775 struct rtl8169_private *tp = netdev_priv(dev);
3776 struct mii_ioctl_data *data = if_mii(ifr);
3777
8b4ab28d
FR		 3778 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
3779}
5f787a1a 3780
cecb5fd7
FR		 3781static int rtl_xmii_ioctl(struct rtl8169_private *tp,
3782 struct mii_ioctl_data *data, int cmd)
8b4ab28d 3783{
5f787a1a
FR		 3784 switch (cmd) {
3785 case SIOCGMIIPHY:
3786 data->phy_id = 32; /* Internal PHY */
3787 return 0;
3788
3789 case SIOCGMIIREG:
4da19633 3790 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
5f787a1a
FR		 3791 return 0;
3792
3793 case SIOCSMIIREG:
4da19633 3794 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
5f787a1a
FR		 3795 return 0;
3796 }
3797 return -EOPNOTSUPP;
3798}
3799
8b4ab28d
FR		 3800static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3801{
3802 return -EOPNOTSUPP;
3803}
3804
fbac58fc
FR		 3805static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3806{
3807 if (tp->features & RTL_FEATURE_MSI) {
3808 pci_disable_msi(pdev);
3809 tp->features &= ~RTL_FEATURE_MSI;
3810 }
3811}
3812
c0e45c1c 3813static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
3814{
3815 struct mdio_ops *ops = &tp->mdio_ops;
3816
3817 switch (tp->mac_version) {
3818 case RTL_GIGA_MAC_VER_27:
3819 ops->write = r8168dp_1_mdio_write;
3820 ops->read = r8168dp_1_mdio_read;
3821 break;
e6de30d6 3822 case RTL_GIGA_MAC_VER_28:
4804b3b3 3823 case RTL_GIGA_MAC_VER_31:
e6de30d6 3824 ops->write = r8168dp_2_mdio_write;
3825 ops->read = r8168dp_2_mdio_read;
3826 break;
c558386b
HW		 3827 case RTL_GIGA_MAC_VER_40:
3828 case RTL_GIGA_MAC_VER_41:
3829 ops->write = r8168g_mdio_write;
3830 ops->read = r8168g_mdio_read;
3831 break;
c0e45c1c 3832 default:
3833 ops->write = r8169_mdio_write;
3834 ops->read = r8169_mdio_read;
3835 break;
3836 }
3837}
3838
649b3b8c 3839static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3840{
3841 void __iomem *ioaddr = tp->mmio_addr;
3842
3843 switch (tp->mac_version) {
3844 case RTL_GIGA_MAC_VER_29:
3845 case RTL_GIGA_MAC_VER_30:
3846 case RTL_GIGA_MAC_VER_32:
3847 case RTL_GIGA_MAC_VER_33:
3848 case RTL_GIGA_MAC_VER_34:
7e18dca1 3849 case RTL_GIGA_MAC_VER_37:
b3d7b2f2 3850 case RTL_GIGA_MAC_VER_38:
5598bfe5 3851 case RTL_GIGA_MAC_VER_39:
c558386b
HW		 3852 case RTL_GIGA_MAC_VER_40:
3853 case RTL_GIGA_MAC_VER_41:
649b3b8c 3854 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3855 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3856 break;
3857 default:
3858 break;
3859 }
3860}
3861
3862static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
3863{
3864 if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
3865 return false;
3866
3867 rtl_writephy(tp, 0x1f, 0x0000);
3868 rtl_writephy(tp, MII_BMCR, 0x0000);
3869
3870 rtl_wol_suspend_quirk(tp);
3871
3872 return true;
3873}
3874
065c27c1 3875static void r810x_phy_power_down(struct rtl8169_private *tp)
3876{
3877 rtl_writephy(tp, 0x1f, 0x0000);
3878 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3879}
3880
3881static void r810x_phy_power_up(struct rtl8169_private *tp)
3882{
3883 rtl_writephy(tp, 0x1f, 0x0000);
3884 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3885}
3886
3887static void r810x_pll_power_down(struct rtl8169_private *tp)
3888{
0004299a
HW		 3889 void __iomem *ioaddr = tp->mmio_addr;
3890
649b3b8c 3891 if (rtl_wol_pll_power_down(tp))
065c27c1 3892 return;
065c27c1 3893
3894 r810x_phy_power_down(tp);
0004299a
HW		 3895
3896 switch (tp->mac_version) {
3897 case RTL_GIGA_MAC_VER_07:
3898 case RTL_GIGA_MAC_VER_08:
3899 case RTL_GIGA_MAC_VER_09:
3900 case RTL_GIGA_MAC_VER_10:
3901 case RTL_GIGA_MAC_VER_13:
3902 case RTL_GIGA_MAC_VER_16:
3903 break;
3904 default:
3905 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3906 break;
3907 }
065c27c1 3908}
3909
3910static void r810x_pll_power_up(struct rtl8169_private *tp)
3911{
0004299a
HW		 3912 void __iomem *ioaddr = tp->mmio_addr;
3913
065c27c1 3914 r810x_phy_power_up(tp);
0004299a
HW		 3915
3916 switch (tp->mac_version) {
3917 case RTL_GIGA_MAC_VER_07:
3918 case RTL_GIGA_MAC_VER_08:
3919 case RTL_GIGA_MAC_VER_09:
3920 case RTL_GIGA_MAC_VER_10:
3921 case RTL_GIGA_MAC_VER_13:
3922 case RTL_GIGA_MAC_VER_16:
3923 break;
3924 default:
3925 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3926 break;
3927 }
065c27c1 3928}
3929
3930static void r8168_phy_power_up(struct rtl8169_private *tp)
3931{
3932 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3933 switch (tp->mac_version) {
3934 case RTL_GIGA_MAC_VER_11:
3935 case RTL_GIGA_MAC_VER_12:
3936 case RTL_GIGA_MAC_VER_17:
3937 case RTL_GIGA_MAC_VER_18:
3938 case RTL_GIGA_MAC_VER_19:
3939 case RTL_GIGA_MAC_VER_20:
3940 case RTL_GIGA_MAC_VER_21:
3941 case RTL_GIGA_MAC_VER_22:
3942 case RTL_GIGA_MAC_VER_23:
3943 case RTL_GIGA_MAC_VER_24:
3944 case RTL_GIGA_MAC_VER_25:
3945 case RTL_GIGA_MAC_VER_26:
3946 case RTL_GIGA_MAC_VER_27:
3947 case RTL_GIGA_MAC_VER_28:
3948 case RTL_GIGA_MAC_VER_31:
3949 rtl_writephy(tp, 0x0e, 0x0000);
3950 break;
3951 default:
3952 break;
3953 }
065c27c1 3954 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3955}
3956
3957static void r8168_phy_power_down(struct rtl8169_private *tp)
3958{
3959 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3960 switch (tp->mac_version) {
3961 case RTL_GIGA_MAC_VER_32:
3962 case RTL_GIGA_MAC_VER_33:
3963 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3964 break;
3965
3966 case RTL_GIGA_MAC_VER_11:
3967 case RTL_GIGA_MAC_VER_12:
3968 case RTL_GIGA_MAC_VER_17:
3969 case RTL_GIGA_MAC_VER_18:
3970 case RTL_GIGA_MAC_VER_19:
3971 case RTL_GIGA_MAC_VER_20:
3972 case RTL_GIGA_MAC_VER_21:
3973 case RTL_GIGA_MAC_VER_22:
3974 case RTL_GIGA_MAC_VER_23:
3975 case RTL_GIGA_MAC_VER_24:
3976 case RTL_GIGA_MAC_VER_25:
3977 case RTL_GIGA_MAC_VER_26:
3978 case RTL_GIGA_MAC_VER_27:
3979 case RTL_GIGA_MAC_VER_28:
3980 case RTL_GIGA_MAC_VER_31:
3981 rtl_writephy(tp, 0x0e, 0x0200);
3982 default:
3983 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3984 break;
3985 }
065c27c1 3986}
3987
3988static void r8168_pll_power_down(struct rtl8169_private *tp)
3989{
3990 void __iomem *ioaddr = tp->mmio_addr;
3991
cecb5fd7
FR		 3992 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3993 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3994 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
4804b3b3 3995 r8168dp_check_dash(tp)) {
065c27c1 3996 return;
5d2e1957 3997 }
065c27c1 3998
cecb5fd7
FR		 3999 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
4000 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
065c27c1 4001 (RTL_R16(CPlusCmd) & ASF)) {
4002 return;
4003 }
4004
01dc7fec 4005 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4006 tp->mac_version == RTL_GIGA_MAC_VER_33)
fdf6fc06 4007 rtl_ephy_write(tp, 0x19, 0xff64);
01dc7fec 4008
649b3b8c 4009 if (rtl_wol_pll_power_down(tp))
065c27c1 4010 return;
065c27c1 4011
4012 r8168_phy_power_down(tp);
4013
4014 switch (tp->mac_version) {
4015 case RTL_GIGA_MAC_VER_25:
4016 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 4017 case RTL_GIGA_MAC_VER_27:
4018 case RTL_GIGA_MAC_VER_28:
4804b3b3 4019 case RTL_GIGA_MAC_VER_31:
01dc7fec 4020 case RTL_GIGA_MAC_VER_32:
4021 case RTL_GIGA_MAC_VER_33:
065c27c1 4022 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4023 break;
4024 }
4025}
4026
4027static void r8168_pll_power_up(struct rtl8169_private *tp)
4028{
4029 void __iomem *ioaddr = tp->mmio_addr;
4030
065c27c1 4031 switch (tp->mac_version) {
4032 case RTL_GIGA_MAC_VER_25:
4033 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 4034 case RTL_GIGA_MAC_VER_27:
4035 case RTL_GIGA_MAC_VER_28:
4804b3b3 4036 case RTL_GIGA_MAC_VER_31:
01dc7fec 4037 case RTL_GIGA_MAC_VER_32:
4038 case RTL_GIGA_MAC_VER_33:
065c27c1 4039 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4040 break;
4041 }
4042
4043 r8168_phy_power_up(tp);
4044}
4045
d58d46b5
FR		 4046static void rtl_generic_op(struct rtl8169_private *tp,
4047 void (*op)(struct rtl8169_private *))
065c27c1 4048{
4049 if (op)
4050 op(tp);
4051}
4052
4053static void rtl_pll_power_down(struct rtl8169_private *tp)
4054{
d58d46b5 4055 rtl_generic_op(tp, tp->pll_power_ops.down);
065c27c1 4056}
4057
4058static void rtl_pll_power_up(struct rtl8169_private *tp)
4059{
d58d46b5 4060 rtl_generic_op(tp, tp->pll_power_ops.up);
065c27c1 4061}
4062
4063static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
4064{
4065 struct pll_power_ops *ops = &tp->pll_power_ops;
4066
4067 switch (tp->mac_version) {
4068 case RTL_GIGA_MAC_VER_07:
4069 case RTL_GIGA_MAC_VER_08:
4070 case RTL_GIGA_MAC_VER_09:
4071 case RTL_GIGA_MAC_VER_10:
4072 case RTL_GIGA_MAC_VER_16:
5a5e4443
HW		 4073 case RTL_GIGA_MAC_VER_29:
4074 case RTL_GIGA_MAC_VER_30:
7e18dca1 4075 case RTL_GIGA_MAC_VER_37:
5598bfe5 4076 case RTL_GIGA_MAC_VER_39:
065c27c1 4077 ops->down = r810x_pll_power_down;
4078 ops->up = r810x_pll_power_up;
4079 break;
4080
4081 case RTL_GIGA_MAC_VER_11:
4082 case RTL_GIGA_MAC_VER_12:
4083 case RTL_GIGA_MAC_VER_17:
4084 case RTL_GIGA_MAC_VER_18:
4085 case RTL_GIGA_MAC_VER_19:
4086 case RTL_GIGA_MAC_VER_20:
4087 case RTL_GIGA_MAC_VER_21:
4088 case RTL_GIGA_MAC_VER_22:
4089 case RTL_GIGA_MAC_VER_23:
4090 case RTL_GIGA_MAC_VER_24:
4091 case RTL_GIGA_MAC_VER_25:
4092 case RTL_GIGA_MAC_VER_26:
4093 case RTL_GIGA_MAC_VER_27:
e6de30d6 4094 case RTL_GIGA_MAC_VER_28:
4804b3b3 4095 case RTL_GIGA_MAC_VER_31:
01dc7fec 4096 case RTL_GIGA_MAC_VER_32:
4097 case RTL_GIGA_MAC_VER_33:
70090424 4098 case RTL_GIGA_MAC_VER_34:
c2218925
HW		 4099 case RTL_GIGA_MAC_VER_35:
4100 case RTL_GIGA_MAC_VER_36:
b3d7b2f2 4101 case RTL_GIGA_MAC_VER_38:
c558386b
HW		 4102 case RTL_GIGA_MAC_VER_40:
4103 case RTL_GIGA_MAC_VER_41:
065c27c1 4104 ops->down = r8168_pll_power_down;
4105 ops->up = r8168_pll_power_up;
4106 break;
4107
4108 default:
4109 ops->down = NULL;
4110 ops->up = NULL;
4111 break;
4112 }
4113}
4114
e542a226
HW		 4115static void rtl_init_rxcfg(struct rtl8169_private *tp)
4116{
4117 void __iomem *ioaddr = tp->mmio_addr;
4118
4119 switch (tp->mac_version) {
4120 case RTL_GIGA_MAC_VER_01:
4121 case RTL_GIGA_MAC_VER_02:
4122 case RTL_GIGA_MAC_VER_03:
4123 case RTL_GIGA_MAC_VER_04:
4124 case RTL_GIGA_MAC_VER_05:
4125 case RTL_GIGA_MAC_VER_06:
4126 case RTL_GIGA_MAC_VER_10:
4127 case RTL_GIGA_MAC_VER_11:
4128 case RTL_GIGA_MAC_VER_12:
4129 case RTL_GIGA_MAC_VER_13:
4130 case RTL_GIGA_MAC_VER_14:
4131 case RTL_GIGA_MAC_VER_15:
4132 case RTL_GIGA_MAC_VER_16:
4133 case RTL_GIGA_MAC_VER_17:
4134 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4135 break;
4136 case RTL_GIGA_MAC_VER_18:
4137 case RTL_GIGA_MAC_VER_19:
4138 case RTL_GIGA_MAC_VER_20:
4139 case RTL_GIGA_MAC_VER_21:
4140 case RTL_GIGA_MAC_VER_22:
4141 case RTL_GIGA_MAC_VER_23:
4142 case RTL_GIGA_MAC_VER_24:
eb2dc35d 4143 case RTL_GIGA_MAC_VER_34:
e542a226
HW		 4144 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4145 break;
4146 default:
4147 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
4148 break;
4149 }
4150}
4151
92fc43b4
HW		 4152static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4153{
4154 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
4155}
4156
d58d46b5
FR		 4157static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4158{
9c5028e9 4159 void __iomem *ioaddr = tp->mmio_addr;
4160
4161 RTL_W8(Cfg9346, Cfg9346_Unlock);
d58d46b5 4162 rtl_generic_op(tp, tp->jumbo_ops.enable);
9c5028e9 4163 RTL_W8(Cfg9346, Cfg9346_Lock);
d58d46b5
FR		 4164}
4165
4166static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4167{
9c5028e9 4168 void __iomem *ioaddr = tp->mmio_addr;
4169
4170 RTL_W8(Cfg9346, Cfg9346_Unlock);
d58d46b5 4171 rtl_generic_op(tp, tp->jumbo_ops.disable);
9c5028e9 4172 RTL_W8(Cfg9346, Cfg9346_Lock);
d58d46b5
FR		 4173}
4174
4175static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4176{
4177 void __iomem *ioaddr = tp->mmio_addr;
4178
4179 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4180 RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
4181 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
4182}
4183
4184static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4185{
4186 void __iomem *ioaddr = tp->mmio_addr;
4187
4188 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4189 RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
4190 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
4191}
4192
4193static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4194{
4195 void __iomem *ioaddr = tp->mmio_addr;
4196
4197 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4198}
4199
4200static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4201{
4202 void __iomem *ioaddr = tp->mmio_addr;
4203
4204 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4205}
4206
4207static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4208{
4209 void __iomem *ioaddr = tp->mmio_addr;
d58d46b5
FR		 4210
4211 RTL_W8(MaxTxPacketSize, 0x3f);
4212 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4213 RTL_W8(Config4, RTL_R8(Config4) | 0x01);
4512ff9f 4214 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
d58d46b5
FR		 4215}
4216
4217static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4218{
4219 void __iomem *ioaddr = tp->mmio_addr;
d58d46b5
FR		 4220
4221 RTL_W8(MaxTxPacketSize, 0x0c);
4222 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4223 RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
4512ff9f 4224 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
d58d46b5
FR		 4225}
4226
4227static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4228{
4229 rtl_tx_performance_tweak(tp->pci_dev,
4230 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4231}
4232
4233static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4234{
4235 rtl_tx_performance_tweak(tp->pci_dev,
4236 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4237}
4238
4239static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4240{
4241 void __iomem *ioaddr = tp->mmio_addr;
4242
4243 r8168b_0_hw_jumbo_enable(tp);
4244
4245 RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
4246}
4247
4248static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4249{
4250 void __iomem *ioaddr = tp->mmio_addr;
4251
4252 r8168b_0_hw_jumbo_disable(tp);
4253
4254 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4255}
4256
4257static void __devinit rtl_init_jumbo_ops(struct rtl8169_private *tp)
4258{
4259 struct jumbo_ops *ops = &tp->jumbo_ops;
4260
4261 switch (tp->mac_version) {
4262 case RTL_GIGA_MAC_VER_11:
4263 ops->disable = r8168b_0_hw_jumbo_disable;
4264 ops->enable = r8168b_0_hw_jumbo_enable;
4265 break;
4266 case RTL_GIGA_MAC_VER_12:
4267 case RTL_GIGA_MAC_VER_17:
4268 ops->disable = r8168b_1_hw_jumbo_disable;
4269 ops->enable = r8168b_1_hw_jumbo_enable;
4270 break;
4271 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
4272 case RTL_GIGA_MAC_VER_19:
4273 case RTL_GIGA_MAC_VER_20:
4274 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
4275 case RTL_GIGA_MAC_VER_22:
4276 case RTL_GIGA_MAC_VER_23:
4277 case RTL_GIGA_MAC_VER_24:
4278 case RTL_GIGA_MAC_VER_25:
4279 case RTL_GIGA_MAC_VER_26:
4280 ops->disable = r8168c_hw_jumbo_disable;
4281 ops->enable = r8168c_hw_jumbo_enable;
4282 break;
4283 case RTL_GIGA_MAC_VER_27:
4284 case RTL_GIGA_MAC_VER_28:
4285 ops->disable = r8168dp_hw_jumbo_disable;
4286 ops->enable = r8168dp_hw_jumbo_enable;
4287 break;
4288 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
4289 case RTL_GIGA_MAC_VER_32:
4290 case RTL_GIGA_MAC_VER_33:
4291 case RTL_GIGA_MAC_VER_34:
4292 ops->disable = r8168e_hw_jumbo_disable;
4293 ops->enable = r8168e_hw_jumbo_enable;
4294 break;
4295
4296 /*
4297 * No action needed for jumbo frames with 8169.
4298 * No jumbo for 810x at all.
4299 */
c558386b
HW		 4300 case RTL_GIGA_MAC_VER_40:
4301 case RTL_GIGA_MAC_VER_41:
d58d46b5
FR		 4302 default:
4303 ops->disable = NULL;
4304 ops->enable = NULL;
4305 break;
4306 }
4307}
4308
ffc46952
FR		 4309DECLARE_RTL_COND(rtl_chipcmd_cond)
4310{
4311 void __iomem *ioaddr = tp->mmio_addr;
4312
4313 return RTL_R8(ChipCmd) & CmdReset;
4314}
4315
6f43adc8
FR		 4316static void rtl_hw_reset(struct rtl8169_private *tp)
4317{
4318 void __iomem *ioaddr = tp->mmio_addr;
6f43adc8 4319
6f43adc8
FR		 4320 RTL_W8(ChipCmd, CmdReset);
4321
ffc46952 4322 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
6f43adc8
FR		 4323}
4324
b6ffd97f 4325static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
953a12cc 4326{
b6ffd97f
FR		 4327 struct rtl_fw *rtl_fw;
4328 const char *name;
4329 int rc = -ENOMEM;
953a12cc 4330
b6ffd97f
FR		 4331 name = rtl_lookup_firmware_name(tp);
4332 if (!name)
4333 goto out_no_firmware;
953a12cc 4334
b6ffd97f
FR		 4335 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4336 if (!rtl_fw)
4337 goto err_warn;
31bd204f 4338
b6ffd97f
FR		 4339 rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
4340 if (rc < 0)
4341 goto err_free;
4342
fd112f2e
FR		 4343 rc = rtl_check_firmware(tp, rtl_fw);
4344 if (rc < 0)
4345 goto err_release_firmware;
4346
b6ffd97f
FR		 4347 tp->rtl_fw = rtl_fw;
4348out:
4349 return;
4350
fd112f2e
FR		 4351err_release_firmware:
4352 release_firmware(rtl_fw->fw);
b6ffd97f
FR		 4353err_free:
4354 kfree(rtl_fw);
4355err_warn:
4356 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4357 name, rc);
4358out_no_firmware:
4359 tp->rtl_fw = NULL;
4360 goto out;
4361}
4362
4363static void rtl_request_firmware(struct rtl8169_private *tp)
4364{
4365 if (IS_ERR(tp->rtl_fw))
4366 rtl_request_uncached_firmware(tp);
953a12cc
FR		 4367}
4368
92fc43b4
HW		 4369static void rtl_rx_close(struct rtl8169_private *tp)
4370{
4371 void __iomem *ioaddr = tp->mmio_addr;
92fc43b4 4372
1687b566 4373 RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
92fc43b4
HW		 4374}
4375
ffc46952
FR		 4376DECLARE_RTL_COND(rtl_npq_cond)
4377{
4378 void __iomem *ioaddr = tp->mmio_addr;
4379
4380 return RTL_R8(TxPoll) & NPQ;
4381}
4382
4383DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4384{
4385 void __iomem *ioaddr = tp->mmio_addr;
4386
4387 return RTL_R32(TxConfig) & TXCFG_EMPTY;
4388}
4389
e6de30d6 4390static void rtl8169_hw_reset(struct rtl8169_private *tp)
1da177e4 4391{
e6de30d6 4392 void __iomem *ioaddr = tp->mmio_addr;
4393
1da177e4 4394 /* Disable interrupts */
811fd301 4395 rtl8169_irq_mask_and_ack(tp);
1da177e4 4396
92fc43b4
HW		 4397 rtl_rx_close(tp);
4398
5d2e1957 4399 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4804b3b3 4400 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4401 tp->mac_version == RTL_GIGA_MAC_VER_31) {
ffc46952 4402 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
c2218925
HW		 4403 } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
4404 tp->mac_version == RTL_GIGA_MAC_VER_35 ||
7e18dca1 4405 tp->mac_version == RTL_GIGA_MAC_VER_36 ||
b3d7b2f2 4406 tp->mac_version == RTL_GIGA_MAC_VER_37 ||
c558386b
HW		 4407 tp->mac_version == RTL_GIGA_MAC_VER_40 ||
4408 tp->mac_version == RTL_GIGA_MAC_VER_41 ||
b3d7b2f2 4409 tp->mac_version == RTL_GIGA_MAC_VER_38) {
c2b0c1e7 4410 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
ffc46952 4411 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
92fc43b4
HW		 4412 } else {
4413 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4414 udelay(100);
e6de30d6 4415 }
4416
92fc43b4 4417 rtl_hw_reset(tp);
1da177e4
LT		 4418}
4419
7f796d83 4420static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 4421{
4422 void __iomem *ioaddr = tp->mmio_addr;
9cb427b6
FR		 4423
4424 /* Set DMA burst size and Interframe Gap Time */
4425 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4426 (InterFrameGap << TxInterFrameGapShift));
4427}
4428
07ce4064 4429static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 4430{
4431 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 4432
07ce4064
FR		 4433 tp->hw_start(dev);
4434
da78dbff 4435 rtl_irq_enable_all(tp);
07ce4064
FR		 4436}
4437
7f796d83
FR		 4438static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
4439 void __iomem *ioaddr)
4440{
4441 /*
4442 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4443 * register to be written before TxDescAddrLow to work.
4444 * Switching from MMIO to I/O access fixes the issue as well.
4445 */
4446 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
284901a9 4447 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
7f796d83 4448 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
284901a9 4449 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 4450}
4451
4452static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4453{
4454 u16 cmd;
4455
4456 cmd = RTL_R16(CPlusCmd);
4457 RTL_W16(CPlusCmd, cmd);
4458 return cmd;
4459}
4460
fdd7b4c3 4461static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
7f796d83
FR		 4462{
4463 /* Low hurts. Let's disable the filtering. */
207d6e87 4464 RTL_W16(RxMaxSize, rx_buf_sz + 1);
7f796d83
FR		 4465}
4466
6dccd16b
FR		 4467static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4468{
3744100e 4469 static const struct rtl_cfg2_info {
6dccd16b
FR		 4470 u32 mac_version;
4471 u32 clk;
4472 u32 val;
4473 } cfg2_info [] = {
4474 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4475 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4476 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4477 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3744100e
FR		 4478 };
4479 const struct rtl_cfg2_info *p = cfg2_info;
6dccd16b
FR		 4480 unsigned int i;
4481 u32 clk;
4482
4483 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 4484 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 4485 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4486 RTL_W32(0x7c, p->val);
4487 break;
4488 }
4489 }
4490}
4491
e6b763ea
FR		 4492static void rtl_set_rx_mode(struct net_device *dev)
4493{
4494 struct rtl8169_private *tp = netdev_priv(dev);
4495 void __iomem *ioaddr = tp->mmio_addr;
4496 u32 mc_filter[2]; /* Multicast hash filter */
4497 int rx_mode;
4498 u32 tmp = 0;
4499
4500 if (dev->flags & IFF_PROMISC) {
4501 /* Unconditionally log net taps. */
4502 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4503 rx_mode =
4504 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4505 AcceptAllPhys;
4506 mc_filter[1] = mc_filter[0] = 0xffffffff;
4507 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4508 (dev->flags & IFF_ALLMULTI)) {
4509 /* Too many to filter perfectly -- accept all multicasts. */
4510 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4511 mc_filter[1] = mc_filter[0] = 0xffffffff;
4512 } else {
4513 struct netdev_hw_addr *ha;
4514
4515 rx_mode = AcceptBroadcast | AcceptMyPhys;
4516 mc_filter[1] = mc_filter[0] = 0;
4517 netdev_for_each_mc_addr(ha, dev) {
4518 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4519 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4520 rx_mode |= AcceptMulticast;
4521 }
4522 }
4523
4524 if (dev->features & NETIF_F_RXALL)
4525 rx_mode |= (AcceptErr | AcceptRunt);
4526
4527 tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4528
4529 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4530 u32 data = mc_filter[0];
4531
4532 mc_filter[0] = swab32(mc_filter[1]);
4533 mc_filter[1] = swab32(data);
4534 }
4535
4536 RTL_W32(MAR0 + 4, mc_filter[1]);
4537 RTL_W32(MAR0 + 0, mc_filter[0]);
4538
4539 RTL_W32(RxConfig, tmp);
4540}
4541
07ce4064
FR		 4542static void rtl_hw_start_8169(struct net_device *dev)
4543{
4544 struct rtl8169_private *tp = netdev_priv(dev);
4545 void __iomem *ioaddr = tp->mmio_addr;
4546 struct pci_dev *pdev = tp->pci_dev;
07ce4064 4547
9cb427b6
FR		 4548 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4549 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4550 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4551 }
4552
1da177e4 4553 RTL_W8(Cfg9346, Cfg9346_Unlock);
cecb5fd7
FR		 4554 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4555 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4556 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4557 tp->mac_version == RTL_GIGA_MAC_VER_04)
9cb427b6
FR		 4558 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4559
e542a226
HW		 4560 rtl_init_rxcfg(tp);
4561
f0298f81 4562 RTL_W8(EarlyTxThres, NoEarlyTx);
1da177e4 4563
6f0333b8 4564 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
1da177e4 4565
cecb5fd7
FR		 4566 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4567 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4568 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4569 tp->mac_version == RTL_GIGA_MAC_VER_04)
c946b304 4570 rtl_set_rx_tx_config_registers(tp);
1da177e4 4571
7f796d83 4572 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 4573
cecb5fd7
FR		 4574 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4575 tp->mac_version == RTL_GIGA_MAC_VER_03) {
06fa7358 4576 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1da177e4 4577 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 4578 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 4579 }
4580
bcf0bf90
FR		 4581 RTL_W16(CPlusCmd, tp->cp_cmd);
4582
6dccd16b
FR		 4583 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4584
1da177e4
LT		 4585 /*
4586 * Undocumented corner. Supposedly:
4587 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4588 */
4589 RTL_W16(IntrMitigate, 0x0000);
4590
7f796d83 4591 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 4592
cecb5fd7
FR		 4593 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4594 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4595 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
4596 tp->mac_version != RTL_GIGA_MAC_VER_04) {
c946b304
FR		 4597 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4598 rtl_set_rx_tx_config_registers(tp);
4599 }
4600
1da177e4 4601 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 4602
4603 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4604 RTL_R8(IntrMask);
1da177e4
LT		 4605
4606 RTL_W32(RxMissed, 0);
4607
07ce4064 4608 rtl_set_rx_mode(dev);
1da177e4
LT		 4609
4610 /* no early-rx interrupts */
4611 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
07ce4064 4612}
1da177e4 4613
beb1fe18
HW		 4614static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4615{
4616 if (tp->csi_ops.write)
52989f0e 4617 tp->csi_ops.write(tp, addr, value);
beb1fe18
HW		 4618}
4619
4620static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4621{
52989f0e 4622 return tp->csi_ops.read ? tp->csi_ops.read(tp, addr) : ~0;
beb1fe18
HW		 4623}
4624
4625static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits)
dacf8154
FR		 4626{
4627 u32 csi;
4628
beb1fe18
HW		 4629 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4630 rtl_csi_write(tp, 0x070c, csi | bits);
4631}
4632
4633static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
4634{
4635 rtl_csi_access_enable(tp, 0x17000000);
650e8d5d 4636}
4637
beb1fe18 4638static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
e6de30d6 4639{
beb1fe18 4640 rtl_csi_access_enable(tp, 0x27000000);
e6de30d6 4641}
4642
ffc46952
FR		 4643DECLARE_RTL_COND(rtl_csiar_cond)
4644{
4645 void __iomem *ioaddr = tp->mmio_addr;
4646
4647 return RTL_R32(CSIAR) & CSIAR_FLAG;
4648}
4649
52989f0e 4650static void r8169_csi_write(struct rtl8169_private *tp, int addr, int value)
650e8d5d 4651{
52989f0e 4652 void __iomem *ioaddr = tp->mmio_addr;
beb1fe18
HW		 4653
4654 RTL_W32(CSIDR, value);
4655 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4656 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4657
ffc46952 4658 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
beb1fe18
HW		 4659}
4660
52989f0e 4661static u32 r8169_csi_read(struct rtl8169_private *tp, int addr)
beb1fe18 4662{
52989f0e 4663 void __iomem *ioaddr = tp->mmio_addr;
beb1fe18
HW		 4664
4665 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
4666 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4667
ffc46952
FR		 4668 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4669 RTL_R32(CSIDR) : ~0;
beb1fe18
HW		 4670}
4671
52989f0e 4672static void r8402_csi_write(struct rtl8169_private *tp, int addr, int value)
7e18dca1 4673{
52989f0e 4674 void __iomem *ioaddr = tp->mmio_addr;
7e18dca1
HW		 4675
4676 RTL_W32(CSIDR, value);
4677 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4678 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
4679 CSIAR_FUNC_NIC);
4680
ffc46952 4681 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
7e18dca1
HW		 4682}
4683
52989f0e 4684static u32 r8402_csi_read(struct rtl8169_private *tp, int addr)
7e18dca1 4685{
52989f0e 4686 void __iomem *ioaddr = tp->mmio_addr;
7e18dca1
HW		 4687
4688 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
4689 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4690
ffc46952
FR		 4691 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4692 RTL_R32(CSIDR) : ~0;
7e18dca1
HW		 4693}
4694
beb1fe18
HW		 4695static void __devinit rtl_init_csi_ops(struct rtl8169_private *tp)
4696{
4697 struct csi_ops *ops = &tp->csi_ops;
4698
4699 switch (tp->mac_version) {
4700 case RTL_GIGA_MAC_VER_01:
4701 case RTL_GIGA_MAC_VER_02:
4702 case RTL_GIGA_MAC_VER_03:
4703 case RTL_GIGA_MAC_VER_04:
4704 case RTL_GIGA_MAC_VER_05:
4705 case RTL_GIGA_MAC_VER_06:
4706 case RTL_GIGA_MAC_VER_10:
4707 case RTL_GIGA_MAC_VER_11:
4708 case RTL_GIGA_MAC_VER_12:
4709 case RTL_GIGA_MAC_VER_13:
4710 case RTL_GIGA_MAC_VER_14:
4711 case RTL_GIGA_MAC_VER_15:
4712 case RTL_GIGA_MAC_VER_16:
4713 case RTL_GIGA_MAC_VER_17:
4714 ops->write = NULL;
4715 ops->read = NULL;
4716 break;
4717
7e18dca1 4718 case RTL_GIGA_MAC_VER_37:
b3d7b2f2 4719 case RTL_GIGA_MAC_VER_38:
7e18dca1
HW		 4720 ops->write = r8402_csi_write;
4721 ops->read = r8402_csi_read;
4722 break;
4723
beb1fe18
HW		 4724 default:
4725 ops->write = r8169_csi_write;
4726 ops->read = r8169_csi_read;
4727 break;
4728 }
dacf8154
FR		 4729}
4730
4731struct ephy_info {
4732 unsigned int offset;
4733 u16 mask;
4734 u16 bits;
4735};
4736
fdf6fc06
FR		 4737static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
4738 int len)
dacf8154
FR		 4739{
4740 u16 w;
4741
4742 while (len-- > 0) {
fdf6fc06
FR		 4743 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4744 rtl_ephy_write(tp, e->offset, w);
dacf8154
FR		 4745 e++;
4746 }
4747}
4748
b726e493
FR		 4749static void rtl_disable_clock_request(struct pci_dev *pdev)
4750{
e44daade 4751 int cap = pci_pcie_cap(pdev);
b726e493
FR		 4752
4753 if (cap) {
4754 u16 ctl;
4755
4756 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4757 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
4758 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4759 }
4760}
4761
e6de30d6 4762static void rtl_enable_clock_request(struct pci_dev *pdev)
4763{
e44daade 4764 int cap = pci_pcie_cap(pdev);
e6de30d6 4765
4766 if (cap) {
4767 u16 ctl;
4768
4769 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4770 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
4771 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4772 }
4773}
4774
b726e493
FR		 4775#define R8168_CPCMD_QUIRK_MASK (\
4776 EnableBist | \
4777 Mac_dbgo_oe | \
4778 Force_half_dup | \
4779 Force_rxflow_en | \
4780 Force_txflow_en | \
4781 Cxpl_dbg_sel | \
4782 ASF | \
4783 PktCntrDisable | \
4784 Mac_dbgo_sel)
4785
beb1fe18 4786static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
219a1e9d 4787{
beb1fe18
HW		 4788 void __iomem *ioaddr = tp->mmio_addr;
4789 struct pci_dev *pdev = tp->pci_dev;
4790
b726e493
FR		 4791 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4792
4793 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4794
2e68ae44
FR		 4795 rtl_tx_performance_tweak(pdev,
4796 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
219a1e9d
FR		 4797}
4798
beb1fe18 4799static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
219a1e9d 4800{
beb1fe18
HW		 4801 void __iomem *ioaddr = tp->mmio_addr;
4802
4803 rtl_hw_start_8168bb(tp);
b726e493 4804
f0298f81 4805 RTL_W8(MaxTxPacketSize, TxPacketMax);
b726e493
FR		 4806
4807 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
219a1e9d
FR		 4808}
4809
beb1fe18 4810static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
219a1e9d 4811{
beb1fe18
HW		 4812 void __iomem *ioaddr = tp->mmio_addr;
4813 struct pci_dev *pdev = tp->pci_dev;
4814
b726e493
FR		 4815 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4816
4817 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4818
219a1e9d 4819 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
b726e493
FR		 4820
4821 rtl_disable_clock_request(pdev);
4822
4823 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
219a1e9d
FR		 4824}
4825
beb1fe18 4826static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
219a1e9d 4827{
350f7596 4828 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 4829 { 0x01, 0, 0x0001 },
4830 { 0x02, 0x0800, 0x1000 },
4831 { 0x03, 0, 0x0042 },
4832 { 0x06, 0x0080, 0x0000 },
4833 { 0x07, 0, 0x2000 }
4834 };
4835
beb1fe18 4836 rtl_csi_access_enable_2(tp);
b726e493 4837
fdf6fc06 4838 rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
b726e493 4839
beb1fe18 4840 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 4841}
4842
beb1fe18 4843static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
ef3386f0 4844{
beb1fe18
HW		 4845 void __iomem *ioaddr = tp->mmio_addr;
4846 struct pci_dev *pdev = tp->pci_dev;
4847
4848 rtl_csi_access_enable_2(tp);
ef3386f0
FR		 4849
4850 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4851
4852 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4853
4854 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4855}
4856
beb1fe18 4857static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
7f3e3d3a 4858{
beb1fe18
HW		 4859 void __iomem *ioaddr = tp->mmio_addr;
4860 struct pci_dev *pdev = tp->pci_dev;
4861
4862 rtl_csi_access_enable_2(tp);
7f3e3d3a
FR		 4863
4864 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4865
4866 /* Magic. */
4867 RTL_W8(DBG_REG, 0x20);
4868
f0298f81 4869 RTL_W8(MaxTxPacketSize, TxPacketMax);
7f3e3d3a
FR		 4870
4871 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4872
4873 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4874}
4875
beb1fe18 4876static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
219a1e9d 4877{
beb1fe18 4878 void __iomem *ioaddr = tp->mmio_addr;
350f7596 4879 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 4880 { 0x02, 0x0800, 0x1000 },
4881 { 0x03, 0, 0x0002 },
4882 { 0x06, 0x0080, 0x0000 }
4883 };
4884
beb1fe18 4885 rtl_csi_access_enable_2(tp);
b726e493
FR		 4886
4887 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4888
fdf6fc06 4889 rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
b726e493 4890
beb1fe18 4891 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 4892}
4893
beb1fe18 4894static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
219a1e9d 4895{
350f7596 4896 static const struct ephy_info e_info_8168c_2[] = {
b726e493
FR		 4897 { 0x01, 0, 0x0001 },
4898 { 0x03, 0x0400, 0x0220 }
4899 };
4900
beb1fe18 4901 rtl_csi_access_enable_2(tp);
b726e493 4902
fdf6fc06 4903 rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
b726e493 4904
beb1fe18 4905 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 4906}
4907
beb1fe18 4908static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
197ff761 4909{
beb1fe18 4910 rtl_hw_start_8168c_2(tp);
197ff761
FR		 4911}
4912
beb1fe18 4913static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
6fb07058 4914{
beb1fe18 4915 rtl_csi_access_enable_2(tp);
6fb07058 4916
beb1fe18 4917 __rtl_hw_start_8168cp(tp);
6fb07058
FR		 4918}
4919
beb1fe18 4920static void rtl_hw_start_8168d(struct rtl8169_private *tp)
5b538df9 4921{
beb1fe18
HW		 4922 void __iomem *ioaddr = tp->mmio_addr;
4923 struct pci_dev *pdev = tp->pci_dev;
4924
4925 rtl_csi_access_enable_2(tp);
5b538df9
FR		 4926
4927 rtl_disable_clock_request(pdev);
4928
f0298f81 4929 RTL_W8(MaxTxPacketSize, TxPacketMax);
5b538df9
FR		 4930
4931 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4932
4933 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4934}
4935
beb1fe18 4936static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4804b3b3 4937{
beb1fe18
HW		 4938 void __iomem *ioaddr = tp->mmio_addr;
4939 struct pci_dev *pdev = tp->pci_dev;
4940
4941 rtl_csi_access_enable_1(tp);
4804b3b3 4942
4943 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4944
4945 RTL_W8(MaxTxPacketSize, TxPacketMax);
4946
4947 rtl_disable_clock_request(pdev);
4948}
4949
beb1fe18 4950static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
e6de30d6 4951{
beb1fe18
HW		 4952 void __iomem *ioaddr = tp->mmio_addr;
4953 struct pci_dev *pdev = tp->pci_dev;
e6de30d6 4954 static const struct ephy_info e_info_8168d_4[] = {
4955 { 0x0b, ~0, 0x48 },
4956 { 0x19, 0x20, 0x50 },
4957 { 0x0c, ~0, 0x20 }
4958 };
4959 int i;
4960
beb1fe18 4961 rtl_csi_access_enable_1(tp);
e6de30d6 4962
4963 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4964
4965 RTL_W8(MaxTxPacketSize, TxPacketMax);
4966
4967 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4968 const struct ephy_info *e = e_info_8168d_4 + i;
4969 u16 w;
4970
fdf6fc06
FR		 4971 w = rtl_ephy_read(tp, e->offset);
4972 rtl_ephy_write(tp, 0x03, (w & e->mask) | e->bits);
e6de30d6 4973 }
4974
4975 rtl_enable_clock_request(pdev);
4976}
4977
beb1fe18 4978static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
01dc7fec 4979{
beb1fe18
HW		 4980 void __iomem *ioaddr = tp->mmio_addr;
4981 struct pci_dev *pdev = tp->pci_dev;
70090424 4982 static const struct ephy_info e_info_8168e_1[] = {
01dc7fec 4983 { 0x00, 0x0200, 0x0100 },
4984 { 0x00, 0x0000, 0x0004 },
4985 { 0x06, 0x0002, 0x0001 },
4986 { 0x06, 0x0000, 0x0030 },
4987 { 0x07, 0x0000, 0x2000 },
4988 { 0x00, 0x0000, 0x0020 },
4989 { 0x03, 0x5800, 0x2000 },
4990 { 0x03, 0x0000, 0x0001 },
4991 { 0x01, 0x0800, 0x1000 },
4992 { 0x07, 0x0000, 0x4000 },
4993 { 0x1e, 0x0000, 0x2000 },
4994 { 0x19, 0xffff, 0xfe6c },
4995 { 0x0a, 0x0000, 0x0040 }
4996 };
4997
beb1fe18 4998 rtl_csi_access_enable_2(tp);
01dc7fec 4999
fdf6fc06 5000 rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
01dc7fec 5001
5002 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5003
5004 RTL_W8(MaxTxPacketSize, TxPacketMax);
5005
5006 rtl_disable_clock_request(pdev);
5007
5008 /* Reset tx FIFO pointer */
cecb5fd7
FR		 5009 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
5010 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
01dc7fec 5011
cecb5fd7 5012 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
01dc7fec 5013}
5014
beb1fe18 5015static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
70090424 5016{
beb1fe18
HW		 5017 void __iomem *ioaddr = tp->mmio_addr;
5018 struct pci_dev *pdev = tp->pci_dev;
70090424
HW		 5019 static const struct ephy_info e_info_8168e_2[] = {
5020 { 0x09, 0x0000, 0x0080 },
5021 { 0x19, 0x0000, 0x0224 }
5022 };
5023
beb1fe18 5024 rtl_csi_access_enable_1(tp);
70090424 5025
fdf6fc06 5026 rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
70090424
HW		 5027
5028 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5029
fdf6fc06
FR		 5030 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5031 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5032 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5033 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5034 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5035 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
5036 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5037 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
70090424 5038
3090bd9a 5039 RTL_W8(MaxTxPacketSize, EarlySize);
70090424
HW		 5040
5041 rtl_disable_clock_request(pdev);
5042
5043 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5044 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5045
5046 /* Adjust EEE LED frequency */
5047 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5048
5049 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5050 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5051 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5052}
5053
5f886e08 5054static void rtl_hw_start_8168f(struct rtl8169_private *tp)
c2218925 5055{
beb1fe18
HW		 5056 void __iomem *ioaddr = tp->mmio_addr;
5057 struct pci_dev *pdev = tp->pci_dev;
c2218925 5058
5f886e08 5059 rtl_csi_access_enable_2(tp);
c2218925
HW		 5060
5061 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5062
fdf6fc06
FR		 5063 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5064 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5065 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5066 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5067 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5068 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5069 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5070 rtl_w1w0_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5071 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5072 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
c2218925
HW		 5073
5074 RTL_W8(MaxTxPacketSize, EarlySize);
5075
5076 rtl_disable_clock_request(pdev);
5077
5078 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5079 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
c2218925
HW		 5080 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5081 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5082 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5083}
5084
5f886e08
HW		 5085static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5086{
5087 void __iomem *ioaddr = tp->mmio_addr;
5088 static const struct ephy_info e_info_8168f_1[] = {
5089 { 0x06, 0x00c0, 0x0020 },
5090 { 0x08, 0x0001, 0x0002 },
5091 { 0x09, 0x0000, 0x0080 },
5092 { 0x19, 0x0000, 0x0224 }
5093 };
5094
5095 rtl_hw_start_8168f(tp);
5096
fdf6fc06 5097 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5f886e08 5098
fdf6fc06 5099 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5f886e08
HW		 5100
5101 /* Adjust EEE LED frequency */
5102 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5103}
5104
b3d7b2f2
HW		 5105static void rtl_hw_start_8411(struct rtl8169_private *tp)
5106{
b3d7b2f2
HW		 5107 static const struct ephy_info e_info_8168f_1[] = {
5108 { 0x06, 0x00c0, 0x0020 },
5109 { 0x0f, 0xffff, 0x5200 },
5110 { 0x1e, 0x0000, 0x4000 },
5111 { 0x19, 0x0000, 0x0224 }
5112 };
5113
5114 rtl_hw_start_8168f(tp);
5115
fdf6fc06 5116 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
b3d7b2f2 5117
fdf6fc06 5118 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
b3d7b2f2
HW		 5119}
5120
c558386b
HW		 5121static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5122{
5123 void __iomem *ioaddr = tp->mmio_addr;
5124 struct pci_dev *pdev = tp->pci_dev;
5125
5126 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
5127 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5128 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5129 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5130
5131 rtl_csi_access_enable_1(tp);
5132
5133 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5134
5135 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5136 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5137
5138 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5139 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
5140 RTL_W8(MaxTxPacketSize, EarlySize);
5141
5142 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5143 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5144
5145 /* Adjust EEE LED frequency */
5146 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5147
5148 rtl_w1w0_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x02, ERIAR_EXGMAC);
5149}
5150
07ce4064
FR		 5151static void rtl_hw_start_8168(struct net_device *dev)
5152{
2dd99530
FR		 5153 struct rtl8169_private *tp = netdev_priv(dev);
5154 void __iomem *ioaddr = tp->mmio_addr;
5155
5156 RTL_W8(Cfg9346, Cfg9346_Unlock);
5157
f0298f81 5158 RTL_W8(MaxTxPacketSize, TxPacketMax);
2dd99530 5159
6f0333b8 5160 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
2dd99530 5161
0e485150 5162 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 5163
5164 RTL_W16(CPlusCmd, tp->cp_cmd);
5165
0e485150 5166 RTL_W16(IntrMitigate, 0x5151);
2dd99530 5167
0e485150 5168 /* Work around for RxFIFO overflow. */
811fd301 5169 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
da78dbff
FR		 5170 tp->event_slow |= RxFIFOOver | PCSTimeout;
5171 tp->event_slow &= ~RxOverflow;
0e485150
FR		 5172 }
5173
5174 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530 5175
b8363901
FR		 5176 rtl_set_rx_mode(dev);
5177
5178 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
5179 (InterFrameGap << TxInterFrameGapShift));
2dd99530
FR		 5180
5181 RTL_R8(IntrMask);
5182
219a1e9d
FR		 5183 switch (tp->mac_version) {
5184 case RTL_GIGA_MAC_VER_11:
beb1fe18 5185 rtl_hw_start_8168bb(tp);
4804b3b3 5186 break;
219a1e9d
FR		 5187
5188 case RTL_GIGA_MAC_VER_12:
5189 case RTL_GIGA_MAC_VER_17:
beb1fe18 5190 rtl_hw_start_8168bef(tp);
4804b3b3 5191 break;
219a1e9d
FR		 5192
5193 case RTL_GIGA_MAC_VER_18:
beb1fe18 5194 rtl_hw_start_8168cp_1(tp);
4804b3b3 5195 break;
219a1e9d
FR		 5196
5197 case RTL_GIGA_MAC_VER_19:
beb1fe18 5198 rtl_hw_start_8168c_1(tp);
4804b3b3 5199 break;
219a1e9d
FR		 5200
5201 case RTL_GIGA_MAC_VER_20:
beb1fe18 5202 rtl_hw_start_8168c_2(tp);
4804b3b3 5203 break;
219a1e9d 5204
197ff761 5205 case RTL_GIGA_MAC_VER_21:
beb1fe18 5206 rtl_hw_start_8168c_3(tp);
4804b3b3 5207 break;
197ff761 5208
6fb07058 5209 case RTL_GIGA_MAC_VER_22:
beb1fe18 5210 rtl_hw_start_8168c_4(tp);
4804b3b3 5211 break;
6fb07058 5212
ef3386f0 5213 case RTL_GIGA_MAC_VER_23:
beb1fe18 5214 rtl_hw_start_8168cp_2(tp);
4804b3b3 5215 break;
ef3386f0 5216
7f3e3d3a 5217 case RTL_GIGA_MAC_VER_24:
beb1fe18 5218 rtl_hw_start_8168cp_3(tp);
4804b3b3 5219 break;
7f3e3d3a 5220
5b538df9 5221 case RTL_GIGA_MAC_VER_25:
daf9df6d 5222 case RTL_GIGA_MAC_VER_26:
5223 case RTL_GIGA_MAC_VER_27:
beb1fe18 5224 rtl_hw_start_8168d(tp);
4804b3b3 5225 break;
5b538df9 5226
e6de30d6 5227 case RTL_GIGA_MAC_VER_28:
beb1fe18 5228 rtl_hw_start_8168d_4(tp);
4804b3b3 5229 break;
cecb5fd7 5230
4804b3b3 5231 case RTL_GIGA_MAC_VER_31:
beb1fe18 5232 rtl_hw_start_8168dp(tp);
4804b3b3 5233 break;
5234
01dc7fec 5235 case RTL_GIGA_MAC_VER_32:
5236 case RTL_GIGA_MAC_VER_33:
beb1fe18 5237 rtl_hw_start_8168e_1(tp);
70090424
HW		 5238 break;
5239 case RTL_GIGA_MAC_VER_34:
beb1fe18 5240 rtl_hw_start_8168e_2(tp);
01dc7fec 5241 break;
e6de30d6 5242
c2218925
HW		 5243 case RTL_GIGA_MAC_VER_35:
5244 case RTL_GIGA_MAC_VER_36:
beb1fe18 5245 rtl_hw_start_8168f_1(tp);
c2218925
HW		 5246 break;
5247
b3d7b2f2
HW		 5248 case RTL_GIGA_MAC_VER_38:
5249 rtl_hw_start_8411(tp);
5250 break;
5251
c558386b
HW		 5252 case RTL_GIGA_MAC_VER_40:
5253 case RTL_GIGA_MAC_VER_41:
5254 rtl_hw_start_8168g_1(tp);
5255 break;
5256
219a1e9d
FR		 5257 default:
5258 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
5259 dev->name, tp->mac_version);
4804b3b3 5260 break;
219a1e9d 5261 }
2dd99530 5262
0e485150
FR		 5263 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5264
b8363901
FR		 5265 RTL_W8(Cfg9346, Cfg9346_Lock);
5266
2dd99530 5267 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
07ce4064 5268}
1da177e4 5269
2857ffb7
FR		 5270#define R810X_CPCMD_QUIRK_MASK (\
5271 EnableBist | \
5272 Mac_dbgo_oe | \
5273 Force_half_dup | \
5edcc537 5274 Force_rxflow_en | \
2857ffb7
FR		 5275 Force_txflow_en | \
5276 Cxpl_dbg_sel | \
5277 ASF | \
5278 PktCntrDisable | \
d24e9aaf 5279 Mac_dbgo_sel)
2857ffb7 5280
beb1fe18 5281static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
2857ffb7 5282{
beb1fe18
HW		 5283 void __iomem *ioaddr = tp->mmio_addr;
5284 struct pci_dev *pdev = tp->pci_dev;
350f7596 5285 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 5286 { 0x01, 0, 0x6e65 },
5287 { 0x02, 0, 0x091f },
5288 { 0x03, 0, 0xc2f9 },
5289 { 0x06, 0, 0xafb5 },
5290 { 0x07, 0, 0x0e00 },
5291 { 0x19, 0, 0xec80 },
5292 { 0x01, 0, 0x2e65 },
5293 { 0x01, 0, 0x6e65 }
5294 };
5295 u8 cfg1;
5296
beb1fe18 5297 rtl_csi_access_enable_2(tp);
2857ffb7
FR		 5298
5299 RTL_W8(DBG_REG, FIX_NAK_1);
5300
5301 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5302
5303 RTL_W8(Config1,
5304 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5305 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5306
5307 cfg1 = RTL_R8(Config1);
5308 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5309 RTL_W8(Config1, cfg1 & ~LEDS0);
5310
fdf6fc06 5311 rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
2857ffb7
FR		 5312}
5313
beb1fe18 5314static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
2857ffb7 5315{
beb1fe18
HW		 5316 void __iomem *ioaddr = tp->mmio_addr;
5317 struct pci_dev *pdev = tp->pci_dev;
5318
5319 rtl_csi_access_enable_2(tp);
2857ffb7
FR		 5320
5321 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5322
5323 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
5324 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2857ffb7
FR		 5325}
5326
beb1fe18 5327static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
2857ffb7 5328{
beb1fe18 5329 rtl_hw_start_8102e_2(tp);
2857ffb7 5330
fdf6fc06 5331 rtl_ephy_write(tp, 0x03, 0xc2f9);
2857ffb7
FR		 5332}
5333
beb1fe18 5334static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5a5e4443 5335{
beb1fe18 5336 void __iomem *ioaddr = tp->mmio_addr;
5a5e4443
HW		 5337 static const struct ephy_info e_info_8105e_1[] = {
5338 { 0x07, 0, 0x4000 },
5339 { 0x19, 0, 0x0200 },
5340 { 0x19, 0, 0x0020 },
5341 { 0x1e, 0, 0x2000 },
5342 { 0x03, 0, 0x0001 },
5343 { 0x19, 0, 0x0100 },
5344 { 0x19, 0, 0x0004 },
5345 { 0x0a, 0, 0x0020 }
5346 };
5347
cecb5fd7 5348 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5a5e4443
HW		 5349 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5350
cecb5fd7 5351 /* Disable Early Tally Counter */
5a5e4443
HW		 5352 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
5353
5354 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4f6b00e5 5355 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5a5e4443 5356
fdf6fc06 5357 rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
5a5e4443
HW		 5358}
5359
beb1fe18 5360static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5a5e4443 5361{
beb1fe18 5362 rtl_hw_start_8105e_1(tp);
fdf6fc06 5363 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5a5e4443
HW		 5364}
5365
7e18dca1
HW		 5366static void rtl_hw_start_8402(struct rtl8169_private *tp)
5367{
5368 void __iomem *ioaddr = tp->mmio_addr;
5369 static const struct ephy_info e_info_8402[] = {
5370 { 0x19, 0xffff, 0xff64 },
5371 { 0x1e, 0, 0x4000 }
5372 };
5373
5374 rtl_csi_access_enable_2(tp);
5375
5376 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5377 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5378
5379 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5380 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5381
fdf6fc06 5382 rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
7e18dca1
HW		 5383
5384 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
5385
fdf6fc06
FR		 5386 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
5387 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
5388 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5389 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5390 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5391 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5392 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
7e18dca1
HW		 5393}
5394
5598bfe5
HW		 5395static void rtl_hw_start_8106(struct rtl8169_private *tp)
5396{
5397 void __iomem *ioaddr = tp->mmio_addr;
5398
5399 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5400 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5401
5402 RTL_W32(MISC, (RTL_R32(MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5403 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
5404 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
5405}
5406
07ce4064
FR		 5407static void rtl_hw_start_8101(struct net_device *dev)
5408{
cdf1a608
FR		 5409 struct rtl8169_private *tp = netdev_priv(dev);
5410 void __iomem *ioaddr = tp->mmio_addr;
5411 struct pci_dev *pdev = tp->pci_dev;
5412
da78dbff
FR		 5413 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5414 tp->event_slow &= ~RxFIFOOver;
811fd301 5415
cecb5fd7
FR		 5416 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5417 tp->mac_version == RTL_GIGA_MAC_VER_16) {
e44daade 5418 int cap = pci_pcie_cap(pdev);
9c14ceaf
FR		 5419
5420 if (cap) {
5421 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
5422 PCI_EXP_DEVCTL_NOSNOOP_EN);
5423 }
cdf1a608
FR		 5424 }
5425
d24e9aaf
HW		 5426 RTL_W8(Cfg9346, Cfg9346_Unlock);
5427
2857ffb7
FR		 5428 switch (tp->mac_version) {
5429 case RTL_GIGA_MAC_VER_07:
beb1fe18 5430 rtl_hw_start_8102e_1(tp);
2857ffb7
FR		 5431 break;
5432
5433 case RTL_GIGA_MAC_VER_08:
beb1fe18 5434 rtl_hw_start_8102e_3(tp);
2857ffb7
FR		 5435 break;
5436
5437 case RTL_GIGA_MAC_VER_09:
beb1fe18 5438 rtl_hw_start_8102e_2(tp);
2857ffb7 5439 break;
5a5e4443
HW		 5440
5441 case RTL_GIGA_MAC_VER_29:
beb1fe18 5442 rtl_hw_start_8105e_1(tp);
5a5e4443
HW		 5443 break;
5444 case RTL_GIGA_MAC_VER_30:
beb1fe18 5445 rtl_hw_start_8105e_2(tp);
5a5e4443 5446 break;
7e18dca1
HW		 5447
5448 case RTL_GIGA_MAC_VER_37:
5449 rtl_hw_start_8402(tp);
5450 break;
5598bfe5
HW		 5451
5452 case RTL_GIGA_MAC_VER_39:
5453 rtl_hw_start_8106(tp);
5454 break;
cdf1a608
FR		 5455 }
5456
d24e9aaf 5457 RTL_W8(Cfg9346, Cfg9346_Lock);
cdf1a608 5458
f0298f81 5459 RTL_W8(MaxTxPacketSize, TxPacketMax);
cdf1a608 5460
6f0333b8 5461 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
cdf1a608 5462
d24e9aaf 5463 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
cdf1a608
FR		 5464 RTL_W16(CPlusCmd, tp->cp_cmd);
5465
5466 RTL_W16(IntrMitigate, 0x0000);
5467
5468 rtl_set_rx_tx_desc_registers(tp, ioaddr);
5469
5470 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5471 rtl_set_rx_tx_config_registers(tp);
5472
cdf1a608
FR		 5473 RTL_R8(IntrMask);
5474
cdf1a608
FR		 5475 rtl_set_rx_mode(dev);
5476
5477 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
1da177e4
LT		 5478}
5479
5480static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5481{
d58d46b5
FR		 5482 struct rtl8169_private *tp = netdev_priv(dev);
5483
5484 if (new_mtu < ETH_ZLEN ||
5485 new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
1da177e4
LT		 5486 return -EINVAL;
5487
d58d46b5
FR		 5488 if (new_mtu > ETH_DATA_LEN)
5489 rtl_hw_jumbo_enable(tp);
5490 else
5491 rtl_hw_jumbo_disable(tp);
5492
1da177e4 5493 dev->mtu = new_mtu;
350fb32a
MM		 5494 netdev_update_features(dev);
5495
323bb685 5496 return 0;
1da177e4
LT		 5497}
5498
5499static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5500{
95e0918d 5501 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 5502 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5503}
5504
6f0333b8
ED		 5505static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5506 void **data_buff, struct RxDesc *desc)
1da177e4 5507{
48addcc9 5508 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
231aee63 5509 DMA_FROM_DEVICE);
48addcc9 5510
6f0333b8
ED		 5511 kfree(*data_buff);
5512 *data_buff = NULL;
1da177e4
LT		 5513 rtl8169_make_unusable_by_asic(desc);
5514}
5515
5516static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
5517{
5518 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5519
5520 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
5521}
5522
5523static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
5524 u32 rx_buf_sz)
5525{
5526 desc->addr = cpu_to_le64(mapping);
5527 wmb();
5528 rtl8169_mark_to_asic(desc, rx_buf_sz);
5529}
5530
6f0333b8
ED		 5531static inline void *rtl8169_align(void *data)
5532{
5533 return (void *)ALIGN((long)data, 16);
5534}
5535
0ecbe1ca
SG		 5536static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5537 struct RxDesc *desc)
1da177e4 5538{
6f0333b8 5539 void *data;
1da177e4 5540 dma_addr_t mapping;
48addcc9 5541 struct device *d = &tp->pci_dev->dev;
0ecbe1ca 5542 struct net_device *dev = tp->dev;
6f0333b8 5543 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
1da177e4 5544
6f0333b8
ED		 5545 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
5546 if (!data)
5547 return NULL;
e9f63f30 5548
6f0333b8
ED		 5549 if (rtl8169_align(data) != data) {
5550 kfree(data);
5551 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
5552 if (!data)
5553 return NULL;
5554 }
3eafe507 5555
48addcc9 5556 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
231aee63 5557 DMA_FROM_DEVICE);
d827d86b
SG		 5558 if (unlikely(dma_mapping_error(d, mapping))) {
5559 if (net_ratelimit())
5560 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
3eafe507 5561 goto err_out;
d827d86b 5562 }
1da177e4
LT		 5563
5564 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6f0333b8 5565 return data;
3eafe507
SG		 5566
5567err_out:
5568 kfree(data);
5569 return NULL;
1da177e4
LT		 5570}
5571
5572static void rtl8169_rx_clear(struct rtl8169_private *tp)
5573{
07d3f51f 5574 unsigned int i;
1da177e4
LT		 5575
5576 for (i = 0; i < NUM_RX_DESC; i++) {
6f0333b8
ED		 5577 if (tp->Rx_databuff[i]) {
5578 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
1da177e4
LT		 5579 tp->RxDescArray + i);
5580 }
5581 }
5582}
5583
0ecbe1ca 5584static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1da177e4 5585{
0ecbe1ca
SG		 5586 desc->opts1 |= cpu_to_le32(RingEnd);
5587}
5b0384f4 5588
0ecbe1ca
SG		 5589static int rtl8169_rx_fill(struct rtl8169_private *tp)
5590{
5591 unsigned int i;
1da177e4 5592
0ecbe1ca
SG		 5593 for (i = 0; i < NUM_RX_DESC; i++) {
5594 void *data;
4ae47c2d 5595
6f0333b8 5596 if (tp->Rx_databuff[i])
1da177e4 5597 continue;
bcf0bf90 5598
0ecbe1ca 5599 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6f0333b8
ED		 5600 if (!data) {
5601 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
0ecbe1ca 5602 goto err_out;
6f0333b8
ED		 5603 }
5604 tp->Rx_databuff[i] = data;
1da177e4 5605 }
1da177e4 5606
0ecbe1ca
SG		 5607 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5608 return 0;
5609
5610err_out:
5611 rtl8169_rx_clear(tp);
5612 return -ENOMEM;
1da177e4
LT		 5613}
5614
1da177e4
LT		 5615static int rtl8169_init_ring(struct net_device *dev)
5616{
5617 struct rtl8169_private *tp = netdev_priv(dev);
5618
5619 rtl8169_init_ring_indexes(tp);
5620
5621 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
6f0333b8 5622 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
1da177e4 5623
0ecbe1ca 5624 return rtl8169_rx_fill(tp);
1da177e4
LT		 5625}
5626
48addcc9 5627static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
1da177e4
LT		 5628 struct TxDesc *desc)
5629{
5630 unsigned int len = tx_skb->len;
5631
48addcc9
SG		 5632 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5633
1da177e4
LT		 5634 desc->opts1 = 0x00;
5635 desc->opts2 = 0x00;
5636 desc->addr = 0x00;
5637 tx_skb->len = 0;
5638}
5639
3eafe507
SG		 5640static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5641 unsigned int n)
1da177e4
LT		 5642{
5643 unsigned int i;
5644
3eafe507
SG		 5645 for (i = 0; i < n; i++) {
5646 unsigned int entry = (start + i) % NUM_TX_DESC;
1da177e4
LT		 5647 struct ring_info *tx_skb = tp->tx_skb + entry;
5648 unsigned int len = tx_skb->len;
5649
5650 if (len) {
5651 struct sk_buff *skb = tx_skb->skb;
5652
48addcc9 5653 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
1da177e4
LT		 5654 tp->TxDescArray + entry);
5655 if (skb) {
cac4b22f 5656 tp->dev->stats.tx_dropped++;
1da177e4
LT		 5657 dev_kfree_skb(skb);
5658 tx_skb->skb = NULL;
5659 }
1da177e4
LT		 5660 }
5661 }
3eafe507
SG		 5662}
5663
5664static void rtl8169_tx_clear(struct rtl8169_private *tp)
5665{
5666 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
1da177e4 5667 tp->cur_tx = tp->dirty_tx = 0;
036dafa2 5668 netdev_reset_queue(tp->dev);
1da177e4
LT		 5669}
5670
4422bcd4 5671static void rtl_reset_work(struct rtl8169_private *tp)
1da177e4 5672{
c4028958 5673 struct net_device *dev = tp->dev;
56de414c 5674 int i;
1da177e4 5675
da78dbff
FR		 5676 napi_disable(&tp->napi);
5677 netif_stop_queue(dev);
5678 synchronize_sched();
1da177e4 5679
c7c2c39b 5680 rtl8169_hw_reset(tp);
5681
56de414c
FR		 5682 for (i = 0; i < NUM_RX_DESC; i++)
5683 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
5684
1da177e4 5685 rtl8169_tx_clear(tp);
c7c2c39b 5686 rtl8169_init_ring_indexes(tp);
1da177e4 5687
da78dbff 5688 napi_enable(&tp->napi);
56de414c
FR		 5689 rtl_hw_start(dev);
5690 netif_wake_queue(dev);
5691 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1da177e4
LT		 5692}
5693
5694static void rtl8169_tx_timeout(struct net_device *dev)
5695{
da78dbff
FR		 5696 struct rtl8169_private *tp = netdev_priv(dev);
5697
5698 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 5699}
5700
5701static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2b7b4318 5702 u32 *opts)
1da177e4
LT		 5703{
5704 struct skb_shared_info *info = skb_shinfo(skb);
5705 unsigned int cur_frag, entry;
a6343afb 5706 struct TxDesc * uninitialized_var(txd);
48addcc9 5707 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 5708
5709 entry = tp->cur_tx;
5710 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
9e903e08 5711 const skb_frag_t *frag = info->frags + cur_frag;
1da177e4
LT		 5712 dma_addr_t mapping;
5713 u32 status, len;
5714 void *addr;
5715
5716 entry = (entry + 1) % NUM_TX_DESC;
5717
5718 txd = tp->TxDescArray + entry;
9e903e08 5719 len = skb_frag_size(frag);
929f6189 5720 addr = skb_frag_address(frag);
48addcc9 5721 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
d827d86b
SG		 5722 if (unlikely(dma_mapping_error(d, mapping))) {
5723 if (net_ratelimit())
5724 netif_err(tp, drv, tp->dev,
5725 "Failed to map TX fragments DMA!\n");
3eafe507 5726 goto err_out;
d827d86b 5727 }
1da177e4 5728
cecb5fd7 5729 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318
FR		 5730 status = opts[0] | len |
5731 (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 5732
5733 txd->opts1 = cpu_to_le32(status);
2b7b4318 5734 txd->opts2 = cpu_to_le32(opts[1]);
1da177e4
LT		 5735 txd->addr = cpu_to_le64(mapping);
5736
5737 tp->tx_skb[entry].len = len;
5738 }
5739
5740 if (cur_frag) {
5741 tp->tx_skb[entry].skb = skb;
5742 txd->opts1 |= cpu_to_le32(LastFrag);
5743 }
5744
5745 return cur_frag;
3eafe507
SG		 5746
5747err_out:
5748 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5749 return -EIO;
1da177e4
LT		 5750}
5751
2b7b4318
FR		 5752static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
5753 struct sk_buff *skb, u32 *opts)
1da177e4 5754{
2b7b4318 5755 const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
350fb32a 5756 u32 mss = skb_shinfo(skb)->gso_size;
2b7b4318 5757 int offset = info->opts_offset;
350fb32a 5758
2b7b4318
FR		 5759 if (mss) {
5760 opts[0] |= TD_LSO;
5761 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
5762 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 5763 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 5764
5765 if (ip->protocol == IPPROTO_TCP)
2b7b4318 5766 opts[offset] |= info->checksum.tcp;
1da177e4 5767 else if (ip->protocol == IPPROTO_UDP)
2b7b4318
FR		 5768 opts[offset] |= info->checksum.udp;
5769 else
5770 WARN_ON_ONCE(1);
1da177e4 5771 }
1da177e4
LT		 5772}
5773
61357325
SH		 5774static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5775 struct net_device *dev)
1da177e4
LT		 5776{
5777 struct rtl8169_private *tp = netdev_priv(dev);
3eafe507 5778 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
1da177e4
LT		 5779 struct TxDesc *txd = tp->TxDescArray + entry;
5780 void __iomem *ioaddr = tp->mmio_addr;
48addcc9 5781 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 5782 dma_addr_t mapping;
5783 u32 status, len;
2b7b4318 5784 u32 opts[2];
3eafe507 5785 int frags;
5b0384f4 5786
477206a0 5787 if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
bf82c189 5788 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
3eafe507 5789 goto err_stop_0;
1da177e4
LT		 5790 }
5791
5792 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3eafe507
SG		 5793 goto err_stop_0;
5794
5795 len = skb_headlen(skb);
48addcc9 5796 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
d827d86b
SG		 5797 if (unlikely(dma_mapping_error(d, mapping))) {
5798 if (net_ratelimit())
5799 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
3eafe507 5800 goto err_dma_0;
d827d86b 5801 }
3eafe507
SG		 5802
5803 tp->tx_skb[entry].len = len;
5804 txd->addr = cpu_to_le64(mapping);
1da177e4 5805
2b7b4318
FR		 5806 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
5807 opts[0] = DescOwn;
1da177e4 5808
2b7b4318
FR		 5809 rtl8169_tso_csum(tp, skb, opts);
5810
5811 frags = rtl8169_xmit_frags(tp, skb, opts);
3eafe507
SG		 5812 if (frags < 0)
5813 goto err_dma_1;
5814 else if (frags)
2b7b4318 5815 opts[0] |= FirstFrag;
3eafe507 5816 else {
2b7b4318 5817 opts[0] |= FirstFrag | LastFrag;
1da177e4
LT		 5818 tp->tx_skb[entry].skb = skb;
5819 }
5820
2b7b4318
FR		 5821 txd->opts2 = cpu_to_le32(opts[1]);
5822
036dafa2
IM		 5823 netdev_sent_queue(dev, skb->len);
5824
5047fb5d
RC		 5825 skb_tx_timestamp(skb);
5826
1da177e4
LT		 5827 wmb();
5828
cecb5fd7 5829 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318 5830 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 5831 txd->opts1 = cpu_to_le32(status);
5832
1da177e4
LT		 5833 tp->cur_tx += frags + 1;
5834
4c020a96 5835 wmb();
1da177e4 5836
cecb5fd7 5837 RTL_W8(TxPoll, NPQ);
1da177e4 5838
da78dbff
FR		 5839 mmiowb();
5840
477206a0 5841 if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
ae1f23fb
FR		 5842 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
5843 * not miss a ring update when it notices a stopped queue.
5844 */
5845 smp_wmb();
1da177e4 5846 netif_stop_queue(dev);
ae1f23fb
FR		 5847 /* Sync with rtl_tx:
5848 * - publish queue status and cur_tx ring index (write barrier)
5849 * - refresh dirty_tx ring index (read barrier).
5850 * May the current thread have a pessimistic view of the ring
5851 * status and forget to wake up queue, a racing rtl_tx thread
5852 * can't.
5853 */
1e874e04 5854 smp_mb();
477206a0 5855 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
1da177e4
LT		 5856 netif_wake_queue(dev);
5857 }
5858
61357325 5859 return NETDEV_TX_OK;
1da177e4 5860
3eafe507 5861err_dma_1:
48addcc9 5862 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
3eafe507
SG		 5863err_dma_0:
5864 dev_kfree_skb(skb);
5865 dev->stats.tx_dropped++;
5866 return NETDEV_TX_OK;
5867
5868err_stop_0:
1da177e4 5869 netif_stop_queue(dev);
cebf8cc7 5870 dev->stats.tx_dropped++;
61357325 5871 return NETDEV_TX_BUSY;
1da177e4
LT		 5872}
5873
5874static void rtl8169_pcierr_interrupt(struct net_device *dev)
5875{
5876 struct rtl8169_private *tp = netdev_priv(dev);
5877 struct pci_dev *pdev = tp->pci_dev;
1da177e4
LT		 5878 u16 pci_status, pci_cmd;
5879
5880 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5881 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5882
bf82c189
JP		 5883 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5884 pci_cmd, pci_status);
1da177e4
LT		 5885
5886 /*
5887 * The recovery sequence below admits a very elaborated explanation:
5888 * - it seems to work;
d03902b8
FR		 5889 * - I did not see what else could be done;
5890 * - it makes iop3xx happy.
1da177e4
LT		 5891 *
5892 * Feel free to adjust to your needs.
5893 */
a27993f3 5894 if (pdev->broken_parity_status)
d03902b8
FR		 5895 pci_cmd &= ~PCI_COMMAND_PARITY;
5896 else
5897 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5898
5899 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 5900
5901 pci_write_config_word(pdev, PCI_STATUS,
5902 pci_status & (PCI_STATUS_DETECTED_PARITY |
5903 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5904 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5905
5906 /* The infamous DAC f*ckup only happens at boot time */
5907 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
e6de30d6 5908 void __iomem *ioaddr = tp->mmio_addr;
5909
bf82c189 5910 netif_info(tp, intr, dev, "disabling PCI DAC\n");
1da177e4
LT		 5911 tp->cp_cmd &= ~PCIDAC;
5912 RTL_W16(CPlusCmd, tp->cp_cmd);
5913 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 5914 }
5915
e6de30d6 5916 rtl8169_hw_reset(tp);
d03902b8 5917
98ddf986 5918 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 5919}
5920
036dafa2
IM		 5921struct rtl_txc {
5922 int packets;
5923 int bytes;
5924};
5925
da78dbff 5926static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
1da177e4 5927{
036dafa2 5928 struct rtl8169_stats *tx_stats = &tp->tx_stats;
1da177e4 5929 unsigned int dirty_tx, tx_left;
036dafa2 5930 struct rtl_txc txc = { 0, 0 };
1da177e4 5931
1da177e4
LT		 5932 dirty_tx = tp->dirty_tx;
5933 smp_rmb();
5934 tx_left = tp->cur_tx - dirty_tx;
5935
5936 while (tx_left > 0) {
5937 unsigned int entry = dirty_tx % NUM_TX_DESC;
5938 struct ring_info *tx_skb = tp->tx_skb + entry;
1da177e4
LT		 5939 u32 status;
5940
5941 rmb();
5942 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5943 if (status & DescOwn)
5944 break;
5945
48addcc9
SG		 5946 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5947 tp->TxDescArray + entry);
1da177e4 5948 if (status & LastFrag) {
036dafa2
IM		 5949 struct sk_buff *skb = tx_skb->skb;
5950
5951 txc.packets++;
5952 txc.bytes += skb->len;
5953 dev_kfree_skb(skb);
1da177e4
LT		 5954 tx_skb->skb = NULL;
5955 }
5956 dirty_tx++;
5957 tx_left--;
5958 }
5959
036dafa2
IM		 5960 u64_stats_update_begin(&tx_stats->syncp);
5961 tx_stats->packets += txc.packets;
5962 tx_stats->bytes += txc.bytes;
5963 u64_stats_update_end(&tx_stats->syncp);
5964
5965 netdev_completed_queue(dev, txc.packets, txc.bytes);
5966
1da177e4
LT		 5967 if (tp->dirty_tx != dirty_tx) {
5968 tp->dirty_tx = dirty_tx;
ae1f23fb
FR		 5969 /* Sync with rtl8169_start_xmit:
5970 * - publish dirty_tx ring index (write barrier)
5971 * - refresh cur_tx ring index and queue status (read barrier)
5972 * May the current thread miss the stopped queue condition,
5973 * a racing xmit thread can only have a right view of the
5974 * ring status.
5975 */
1e874e04 5976 smp_mb();
1da177e4 5977 if (netif_queue_stopped(dev) &&
477206a0 5978 TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
1da177e4
LT		 5979 netif_wake_queue(dev);
5980 }
d78ae2dc
FR		 5981 /*
5982 * 8168 hack: TxPoll requests are lost when the Tx packets are
5983 * too close. Let's kick an extra TxPoll request when a burst
5984 * of start_xmit activity is detected (if it is not detected,
5985 * it is slow enough). -- FR
5986 */
da78dbff
FR		 5987 if (tp->cur_tx != dirty_tx) {
5988 void __iomem *ioaddr = tp->mmio_addr;
5989
d78ae2dc 5990 RTL_W8(TxPoll, NPQ);
da78dbff 5991 }
1da177e4
LT		 5992 }
5993}
5994
126fa4b9
FR		 5995static inline int rtl8169_fragmented_frame(u32 status)
5996{
5997 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
5998}
5999
adea1ac7 6000static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
1da177e4 6001{
1da177e4
LT		 6002 u32 status = opts1 & RxProtoMask;
6003
6004 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
d5d3ebe3 6005 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
1da177e4
LT		 6006 skb->ip_summed = CHECKSUM_UNNECESSARY;
6007 else
bc8acf2c 6008 skb_checksum_none_assert(skb);
1da177e4
LT		 6009}
6010
6f0333b8
ED		 6011static struct sk_buff *rtl8169_try_rx_copy(void *data,
6012 struct rtl8169_private *tp,
6013 int pkt_size,
6014 dma_addr_t addr)
1da177e4 6015{
b449655f 6016 struct sk_buff *skb;
48addcc9 6017 struct device *d = &tp->pci_dev->dev;
b449655f 6018
6f0333b8 6019 data = rtl8169_align(data);
48addcc9 6020 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6f0333b8
ED		 6021 prefetch(data);
6022 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
6023 if (skb)
6024 memcpy(skb->data, data, pkt_size);
48addcc9
SG		 6025 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
6026
6f0333b8 6027 return skb;
1da177e4
LT		 6028}
6029
da78dbff 6030static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
1da177e4
LT		 6031{
6032 unsigned int cur_rx, rx_left;
6f0333b8 6033 unsigned int count;
1da177e4 6034
1da177e4
LT		 6035 cur_rx = tp->cur_rx;
6036 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
865c652d 6037 rx_left = min(rx_left, budget);
1da177e4 6038
4dcb7d33 6039 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 6040 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 6041 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 6042 u32 status;
6043
6044 rmb();
e03f33af 6045 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
1da177e4
LT		 6046
6047 if (status & DescOwn)
6048 break;
4dcb7d33 6049 if (unlikely(status & RxRES)) {
bf82c189
JP		 6050 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6051 status);
cebf8cc7 6052 dev->stats.rx_errors++;
1da177e4 6053 if (status & (RxRWT | RxRUNT))
cebf8cc7 6054 dev->stats.rx_length_errors++;
1da177e4 6055 if (status & RxCRC)
cebf8cc7 6056 dev->stats.rx_crc_errors++;
9dccf611 6057 if (status & RxFOVF) {
da78dbff 6058 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
cebf8cc7 6059 dev->stats.rx_fifo_errors++;
9dccf611 6060 }
6bbe021d
BG		 6061 if ((status & (RxRUNT | RxCRC)) &&
6062 !(status & (RxRWT | RxFOVF)) &&
6063 (dev->features & NETIF_F_RXALL))
6064 goto process_pkt;
6065
6f0333b8 6066 rtl8169_mark_to_asic(desc, rx_buf_sz);
1da177e4 6067 } else {
6f0333b8 6068 struct sk_buff *skb;
6bbe021d
BG		 6069 dma_addr_t addr;
6070 int pkt_size;
6071
6072process_pkt:
6073 addr = le64_to_cpu(desc->addr);
79d0c1d2
BG		 6074 if (likely(!(dev->features & NETIF_F_RXFCS)))
6075 pkt_size = (status & 0x00003fff) - 4;
6076 else
6077 pkt_size = status & 0x00003fff;
1da177e4 6078
126fa4b9
FR		 6079 /*
6080 * The driver does not support incoming fragmented
6081 * frames. They are seen as a symptom of over-mtu
6082 * sized frames.
6083 */
6084 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 6085 dev->stats.rx_dropped++;
6086 dev->stats.rx_length_errors++;
6f0333b8 6087 rtl8169_mark_to_asic(desc, rx_buf_sz);
4dcb7d33 6088 continue;
126fa4b9
FR		 6089 }
6090
6f0333b8
ED		 6091 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6092 tp, pkt_size, addr);
6093 rtl8169_mark_to_asic(desc, rx_buf_sz);
6094 if (!skb) {
6095 dev->stats.rx_dropped++;
6096 continue;
1da177e4
LT		 6097 }
6098
adea1ac7 6099 rtl8169_rx_csum(skb, status);
1da177e4
LT		 6100 skb_put(skb, pkt_size);
6101 skb->protocol = eth_type_trans(skb, dev);
6102
7a8fc77b
FR		 6103 rtl8169_rx_vlan_tag(desc, skb);
6104
56de414c 6105 napi_gro_receive(&tp->napi, skb);
1da177e4 6106
8027aa24
JW		 6107 u64_stats_update_begin(&tp->rx_stats.syncp);
6108 tp->rx_stats.packets++;
6109 tp->rx_stats.bytes += pkt_size;
6110 u64_stats_update_end(&tp->rx_stats.syncp);
1da177e4 6111 }
6dccd16b
FR		 6112
6113 /* Work around for AMD plateform. */
95e0918d 6114 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
6dccd16b
FR		 6115 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
6116 desc->opts2 = 0;
6117 cur_rx++;
6118 }
1da177e4
LT		 6119 }
6120
6121 count = cur_rx - tp->cur_rx;
6122 tp->cur_rx = cur_rx;
6123
6f0333b8 6124 tp->dirty_rx += count;
1da177e4
LT		 6125
6126 return count;
6127}
6128
07d3f51f 6129static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 6130{
07d3f51f 6131 struct net_device *dev = dev_instance;
1da177e4 6132 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 6133 int handled = 0;
9085cdfa 6134 u16 status;
1da177e4 6135
9085cdfa 6136 status = rtl_get_events(tp);
da78dbff
FR		 6137 if (status && status != 0xffff) {
6138 status &= RTL_EVENT_NAPI | tp->event_slow;
6139 if (status) {
6140 handled = 1;
1da177e4 6141
da78dbff
FR		 6142 rtl_irq_disable(tp);
6143 napi_schedule(&tp->napi);
f11a377b 6144 }
da78dbff
FR		 6145 }
6146 return IRQ_RETVAL(handled);
6147}
1da177e4 6148
da78dbff
FR		 6149/*
6150 * Workqueue context.
6151 */
6152static void rtl_slow_event_work(struct rtl8169_private *tp)
6153{
6154 struct net_device *dev = tp->dev;
6155 u16 status;
6156
6157 status = rtl_get_events(tp) & tp->event_slow;
6158 rtl_ack_events(tp, status);
1da177e4 6159
da78dbff
FR		 6160 if (unlikely(status & RxFIFOOver)) {
6161 switch (tp->mac_version) {
6162 /* Work around for rx fifo overflow */
6163 case RTL_GIGA_MAC_VER_11:
6164 netif_stop_queue(dev);
934714d0
FR		 6165 /* XXX - Hack alert. See rtl_task(). */
6166 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
da78dbff 6167 default:
f11a377b
DD		 6168 break;
6169 }
da78dbff 6170 }
1da177e4 6171
da78dbff
FR		 6172 if (unlikely(status & SYSErr))
6173 rtl8169_pcierr_interrupt(dev);
0e485150 6174
da78dbff
FR		 6175 if (status & LinkChg)
6176 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
1da177e4 6177
7dbb4918 6178 rtl_irq_enable_all(tp);
1da177e4
LT		 6179}
6180
4422bcd4
FR		 6181static void rtl_task(struct work_struct *work)
6182{
da78dbff
FR		 6183 static const struct {
6184 int bitnr;
6185 void (*action)(struct rtl8169_private *);
6186 } rtl_work[] = {
934714d0 6187 /* XXX - keep rtl_slow_event_work() as first element. */
da78dbff
FR		 6188 { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work },
6189 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
6190 { RTL_FLAG_TASK_PHY_PENDING, rtl_phy_work }
6191 };
4422bcd4
FR		 6192 struct rtl8169_private *tp =
6193 container_of(work, struct rtl8169_private, wk.work);
da78dbff
FR		 6194 struct net_device *dev = tp->dev;
6195 int i;
6196
6197 rtl_lock_work(tp);
6198
6c4a70c5
FR		 6199 if (!netif_running(dev) ||
6200 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
da78dbff
FR		 6201 goto out_unlock;
6202
6203 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6204 bool pending;
6205
da78dbff 6206 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
da78dbff
FR		 6207 if (pending)
6208 rtl_work[i].action(tp);
6209 }
4422bcd4 6210
da78dbff
FR		 6211out_unlock:
6212 rtl_unlock_work(tp);
4422bcd4
FR		 6213}
6214
bea3348e 6215static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 6216{
bea3348e
SH		 6217 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6218 struct net_device *dev = tp->dev;
da78dbff
FR		 6219 u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
6220 int work_done= 0;
6221 u16 status;
6222
6223 status = rtl_get_events(tp);
6224 rtl_ack_events(tp, status & ~tp->event_slow);
6225
6226 if (status & RTL_EVENT_NAPI_RX)
6227 work_done = rtl_rx(dev, tp, (u32) budget);
6228
6229 if (status & RTL_EVENT_NAPI_TX)
6230 rtl_tx(dev, tp);
1da177e4 6231
da78dbff
FR		 6232 if (status & tp->event_slow) {
6233 enable_mask &= ~tp->event_slow;
6234
6235 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
6236 }
1da177e4 6237
bea3348e 6238 if (work_done < budget) {
288379f0 6239 napi_complete(napi);
f11a377b 6240
da78dbff
FR		 6241 rtl_irq_enable(tp, enable_mask);
6242 mmiowb();
1da177e4
LT		 6243 }
6244
bea3348e 6245 return work_done;
1da177e4 6246}
1da177e4 6247
523a6094
FR		 6248static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
6249{
6250 struct rtl8169_private *tp = netdev_priv(dev);
6251
6252 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6253 return;
6254
6255 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
6256 RTL_W32(RxMissed, 0);
6257}
6258
1da177e4
LT		 6259static void rtl8169_down(struct net_device *dev)
6260{
6261 struct rtl8169_private *tp = netdev_priv(dev);
6262 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 6263
4876cc1e 6264 del_timer_sync(&tp->timer);
1da177e4 6265
93dd79e8 6266 napi_disable(&tp->napi);
da78dbff 6267 netif_stop_queue(dev);
1da177e4 6268
92fc43b4 6269 rtl8169_hw_reset(tp);
323bb685
SG		 6270 /*
6271 * At this point device interrupts can not be enabled in any function,
209e5ac8
FR		 6272 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6273 * and napi is disabled (rtl8169_poll).
323bb685 6274 */
523a6094 6275 rtl8169_rx_missed(dev, ioaddr);
1da177e4 6276
1da177e4 6277 /* Give a racing hard_start_xmit a few cycles to complete. */
da78dbff 6278 synchronize_sched();
1da177e4 6279
1da177e4
LT		 6280 rtl8169_tx_clear(tp);
6281
6282 rtl8169_rx_clear(tp);
065c27c1 6283
6284 rtl_pll_power_down(tp);
1da177e4
LT		 6285}
6286
6287static int rtl8169_close(struct net_device *dev)
6288{
6289 struct rtl8169_private *tp = netdev_priv(dev);
6290 struct pci_dev *pdev = tp->pci_dev;
6291
e1759441
RW		 6292 pm_runtime_get_sync(&pdev->dev);
6293
cecb5fd7 6294 /* Update counters before going down */
355423d0
IV		 6295 rtl8169_update_counters(dev);
6296
da78dbff 6297 rtl_lock_work(tp);
6c4a70c5 6298 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
da78dbff 6299
1da177e4 6300 rtl8169_down(dev);
da78dbff 6301 rtl_unlock_work(tp);
1da177e4 6302
92a7c4e7 6303 free_irq(pdev->irq, dev);
1da177e4 6304
82553bb6
SG		 6305 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6306 tp->RxPhyAddr);
6307 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6308 tp->TxPhyAddr);
1da177e4
LT		 6309 tp->TxDescArray = NULL;
6310 tp->RxDescArray = NULL;
6311
e1759441
RW		 6312 pm_runtime_put_sync(&pdev->dev);
6313
1da177e4
LT		 6314 return 0;
6315}
6316
dc1c00ce
FR		 6317#ifdef CONFIG_NET_POLL_CONTROLLER
6318static void rtl8169_netpoll(struct net_device *dev)
6319{
6320 struct rtl8169_private *tp = netdev_priv(dev);
6321
6322 rtl8169_interrupt(tp->pci_dev->irq, dev);
6323}
6324#endif
6325
df43ac78
FR		 6326static int rtl_open(struct net_device *dev)
6327{
6328 struct rtl8169_private *tp = netdev_priv(dev);
6329 void __iomem *ioaddr = tp->mmio_addr;
6330 struct pci_dev *pdev = tp->pci_dev;
6331 int retval = -ENOMEM;
6332
6333 pm_runtime_get_sync(&pdev->dev);
6334
6335 /*
e75d6606 6336 * Rx and Tx descriptors needs 256 bytes alignment.
df43ac78
FR		 6337 * dma_alloc_coherent provides more.
6338 */
6339 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6340 &tp->TxPhyAddr, GFP_KERNEL);
6341 if (!tp->TxDescArray)
6342 goto err_pm_runtime_put;
6343
6344 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6345 &tp->RxPhyAddr, GFP_KERNEL);
6346 if (!tp->RxDescArray)
6347 goto err_free_tx_0;
6348
6349 retval = rtl8169_init_ring(dev);
6350 if (retval < 0)
6351 goto err_free_rx_1;
6352
6353 INIT_WORK(&tp->wk.work, rtl_task);
6354
6355 smp_mb();
6356
6357 rtl_request_firmware(tp);
6358
92a7c4e7 6359 retval = request_irq(pdev->irq, rtl8169_interrupt,
df43ac78
FR		 6360 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
6361 dev->name, dev);
6362 if (retval < 0)
6363 goto err_release_fw_2;
6364
6365 rtl_lock_work(tp);
6366
6367 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6368
6369 napi_enable(&tp->napi);
6370
6371 rtl8169_init_phy(dev, tp);
6372
6373 __rtl8169_set_features(dev, dev->features);
6374
6375 rtl_pll_power_up(tp);
6376
6377 rtl_hw_start(dev);
6378
6379 netif_start_queue(dev);
6380
6381 rtl_unlock_work(tp);
6382
6383 tp->saved_wolopts = 0;
6384 pm_runtime_put_noidle(&pdev->dev);
6385
6386 rtl8169_check_link_status(dev, tp, ioaddr);
6387out:
6388 return retval;
6389
6390err_release_fw_2:
6391 rtl_release_firmware(tp);
6392 rtl8169_rx_clear(tp);
6393err_free_rx_1:
6394 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6395 tp->RxPhyAddr);
6396 tp->RxDescArray = NULL;
6397err_free_tx_0:
6398 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6399 tp->TxPhyAddr);
6400 tp->TxDescArray = NULL;
6401err_pm_runtime_put:
6402 pm_runtime_put_noidle(&pdev->dev);
6403 goto out;
6404}
6405
8027aa24
JW		 6406static struct rtnl_link_stats64 *
6407rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
1da177e4
LT		 6408{
6409 struct rtl8169_private *tp = netdev_priv(dev);
6410 void __iomem *ioaddr = tp->mmio_addr;
8027aa24 6411 unsigned int start;
1da177e4 6412
da78dbff 6413 if (netif_running(dev))
523a6094 6414 rtl8169_rx_missed(dev, ioaddr);
5b0384f4 6415
8027aa24
JW		 6416 do {
6417 start = u64_stats_fetch_begin_bh(&tp->rx_stats.syncp);
6418 stats->rx_packets = tp->rx_stats.packets;
6419 stats->rx_bytes = tp->rx_stats.bytes;
6420 } while (u64_stats_fetch_retry_bh(&tp->rx_stats.syncp, start));
6421
6422
6423 do {
6424 start = u64_stats_fetch_begin_bh(&tp->tx_stats.syncp);
6425 stats->tx_packets = tp->tx_stats.packets;
6426 stats->tx_bytes = tp->tx_stats.bytes;
6427 } while (u64_stats_fetch_retry_bh(&tp->tx_stats.syncp, start));
6428
6429 stats->rx_dropped = dev->stats.rx_dropped;
6430 stats->tx_dropped = dev->stats.tx_dropped;
6431 stats->rx_length_errors = dev->stats.rx_length_errors;
6432 stats->rx_errors = dev->stats.rx_errors;
6433 stats->rx_crc_errors = dev->stats.rx_crc_errors;
6434 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
6435 stats->rx_missed_errors = dev->stats.rx_missed_errors;
6436
6437 return stats;
1da177e4
LT		 6438}
6439
861ab440 6440static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 6441{
065c27c1 6442 struct rtl8169_private *tp = netdev_priv(dev);
6443
5d06a99f 6444 if (!netif_running(dev))
861ab440 6445 return;
5d06a99f
FR		 6446
6447 netif_device_detach(dev);
6448 netif_stop_queue(dev);
da78dbff
FR		 6449
6450 rtl_lock_work(tp);
6451 napi_disable(&tp->napi);
6c4a70c5 6452 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
da78dbff
FR		 6453 rtl_unlock_work(tp);
6454
6455 rtl_pll_power_down(tp);
861ab440
RW		 6456}
6457
6458#ifdef CONFIG_PM
6459
6460static int rtl8169_suspend(struct device *device)
6461{
6462 struct pci_dev *pdev = to_pci_dev(device);
6463 struct net_device *dev = pci_get_drvdata(pdev);
5d06a99f 6464
861ab440 6465 rtl8169_net_suspend(dev);
1371fa6d 6466
5d06a99f
FR		 6467 return 0;
6468}
6469
e1759441
RW		 6470static void __rtl8169_resume(struct net_device *dev)
6471{
065c27c1 6472 struct rtl8169_private *tp = netdev_priv(dev);
6473
e1759441 6474 netif_device_attach(dev);
065c27c1 6475
6476 rtl_pll_power_up(tp);
6477
cff4c162
AS		 6478 rtl_lock_work(tp);
6479 napi_enable(&tp->napi);
6c4a70c5 6480 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
cff4c162 6481 rtl_unlock_work(tp);
da78dbff 6482
98ddf986 6483 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
e1759441
RW		 6484}
6485
861ab440 6486static int rtl8169_resume(struct device *device)
5d06a99f 6487{
861ab440 6488 struct pci_dev *pdev = to_pci_dev(device);
5d06a99f 6489 struct net_device *dev = pci_get_drvdata(pdev);
fccec10b
SG		 6490 struct rtl8169_private *tp = netdev_priv(dev);
6491
6492 rtl8169_init_phy(dev, tp);
5d06a99f 6493
e1759441
RW		 6494 if (netif_running(dev))
6495 __rtl8169_resume(dev);
5d06a99f 6496
e1759441
RW		 6497 return 0;
6498}
6499
6500static int rtl8169_runtime_suspend(struct device *device)
6501{
6502 struct pci_dev *pdev = to_pci_dev(device);
6503 struct net_device *dev = pci_get_drvdata(pdev);
6504 struct rtl8169_private *tp = netdev_priv(dev);
6505
6506 if (!tp->TxDescArray)
6507 return 0;
6508
da78dbff 6509 rtl_lock_work(tp);
e1759441
RW		 6510 tp->saved_wolopts = __rtl8169_get_wol(tp);
6511 __rtl8169_set_wol(tp, WAKE_ANY);
da78dbff 6512 rtl_unlock_work(tp);
e1759441
RW		 6513
6514 rtl8169_net_suspend(dev);
6515
6516 return 0;
6517}
6518
6519static int rtl8169_runtime_resume(struct device *device)
6520{
6521 struct pci_dev *pdev = to_pci_dev(device);
6522 struct net_device *dev = pci_get_drvdata(pdev);
6523 struct rtl8169_private *tp = netdev_priv(dev);
6524
6525 if (!tp->TxDescArray)
6526 return 0;
6527
da78dbff 6528 rtl_lock_work(tp);
e1759441
RW		 6529 __rtl8169_set_wol(tp, tp->saved_wolopts);
6530 tp->saved_wolopts = 0;
da78dbff 6531 rtl_unlock_work(tp);
e1759441 6532
fccec10b
SG		 6533 rtl8169_init_phy(dev, tp);
6534
e1759441 6535 __rtl8169_resume(dev);
5d06a99f 6536
5d06a99f
FR		 6537 return 0;
6538}
6539
e1759441
RW		 6540static int rtl8169_runtime_idle(struct device *device)
6541{
6542 struct pci_dev *pdev = to_pci_dev(device);
6543 struct net_device *dev = pci_get_drvdata(pdev);
6544 struct rtl8169_private *tp = netdev_priv(dev);
6545
e4fbce74 6546 return tp->TxDescArray ? -EBUSY : 0;
e1759441
RW		 6547}
6548
47145210 6549static const struct dev_pm_ops rtl8169_pm_ops = {
cecb5fd7
FR		 6550 .suspend = rtl8169_suspend,
6551 .resume = rtl8169_resume,
6552 .freeze = rtl8169_suspend,
6553 .thaw = rtl8169_resume,
6554 .poweroff = rtl8169_suspend,
6555 .restore = rtl8169_resume,
6556 .runtime_suspend = rtl8169_runtime_suspend,
6557 .runtime_resume = rtl8169_runtime_resume,
6558 .runtime_idle = rtl8169_runtime_idle,
861ab440
RW		 6559};
6560
6561#define RTL8169_PM_OPS (&rtl8169_pm_ops)
6562
6563#else /* !CONFIG_PM */
6564
6565#define RTL8169_PM_OPS NULL
6566
6567#endif /* !CONFIG_PM */
6568
649b3b8c 6569static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6570{
6571 void __iomem *ioaddr = tp->mmio_addr;
6572
6573 /* WoL fails with 8168b when the receiver is disabled. */
6574 switch (tp->mac_version) {
6575 case RTL_GIGA_MAC_VER_11:
6576 case RTL_GIGA_MAC_VER_12:
6577 case RTL_GIGA_MAC_VER_17:
6578 pci_clear_master(tp->pci_dev);
6579
6580 RTL_W8(ChipCmd, CmdRxEnb);
6581 /* PCI commit */
6582 RTL_R8(ChipCmd);
6583 break;
6584 default:
6585 break;
6586 }
6587}
6588
1765f95d
FR		 6589static void rtl_shutdown(struct pci_dev *pdev)
6590{
861ab440 6591 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 6592 struct rtl8169_private *tp = netdev_priv(dev);
2a15cd2f 6593 struct device *d = &pdev->dev;
6594
6595 pm_runtime_get_sync(d);
861ab440
RW		 6596
6597 rtl8169_net_suspend(dev);
1765f95d 6598
cecb5fd7 6599 /* Restore original MAC address */
cc098dc7
IV		 6600 rtl_rar_set(tp, dev->perm_addr);
6601
92fc43b4 6602 rtl8169_hw_reset(tp);
4bb3f522 6603
861ab440 6604 if (system_state == SYSTEM_POWER_OFF) {
649b3b8c 6605 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
6606 rtl_wol_suspend_quirk(tp);
6607 rtl_wol_shutdown_quirk(tp);
ca52efd5 6608 }
6609
861ab440
RW		 6610 pci_wake_from_d3(pdev, true);
6611 pci_set_power_state(pdev, PCI_D3hot);
6612 }
2a15cd2f 6613
6614 pm_runtime_put_noidle(d);
861ab440 6615}
5d06a99f 6616
e27566ed
FR		 6617static void __devexit rtl_remove_one(struct pci_dev *pdev)
6618{
6619 struct net_device *dev = pci_get_drvdata(pdev);
6620 struct rtl8169_private *tp = netdev_priv(dev);
6621
6622 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
6623 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
6624 tp->mac_version == RTL_GIGA_MAC_VER_31) {
6625 rtl8168_driver_stop(tp);
6626 }
6627
6628 cancel_work_sync(&tp->wk.work);
6629
ad1be8d3
DN		 6630 netif_napi_del(&tp->napi);
6631
e27566ed
FR		 6632 unregister_netdev(dev);
6633
6634 rtl_release_firmware(tp);
6635
6636 if (pci_dev_run_wake(pdev))
6637 pm_runtime_get_noresume(&pdev->dev);
6638
6639 /* restore original MAC address */
6640 rtl_rar_set(tp, dev->perm_addr);
6641
6642 rtl_disable_msi(pdev, tp);
6643 rtl8169_release_board(pdev, dev, tp->mmio_addr);
6644 pci_set_drvdata(pdev, NULL);
6645}
6646
fa9c385e 6647static const struct net_device_ops rtl_netdev_ops = {
df43ac78 6648 .ndo_open = rtl_open,
fa9c385e
FR		 6649 .ndo_stop = rtl8169_close,
6650 .ndo_get_stats64 = rtl8169_get_stats64,
6651 .ndo_start_xmit = rtl8169_start_xmit,
6652 .ndo_tx_timeout = rtl8169_tx_timeout,
6653 .ndo_validate_addr = eth_validate_addr,
6654 .ndo_change_mtu = rtl8169_change_mtu,
6655 .ndo_fix_features = rtl8169_fix_features,
6656 .ndo_set_features = rtl8169_set_features,
6657 .ndo_set_mac_address = rtl_set_mac_address,
6658 .ndo_do_ioctl = rtl8169_ioctl,
6659 .ndo_set_rx_mode = rtl_set_rx_mode,
6660#ifdef CONFIG_NET_POLL_CONTROLLER
6661 .ndo_poll_controller = rtl8169_netpoll,
6662#endif
6663
6664};
6665
31fa8b18
FR		 6666static const struct rtl_cfg_info {
6667 void (*hw_start)(struct net_device *);
6668 unsigned int region;
6669 unsigned int align;
6670 u16 event_slow;
6671 unsigned features;
6672 u8 default_ver;
6673} rtl_cfg_infos [] = {
6674 [RTL_CFG_0] = {
6675 .hw_start = rtl_hw_start_8169,
6676 .region = 1,
6677 .align = 0,
6678 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
6679 .features = RTL_FEATURE_GMII,
6680 .default_ver = RTL_GIGA_MAC_VER_01,
6681 },
6682 [RTL_CFG_1] = {
6683 .hw_start = rtl_hw_start_8168,
6684 .region = 2,
6685 .align = 8,
6686 .event_slow = SYSErr | LinkChg | RxOverflow,
6687 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
6688 .default_ver = RTL_GIGA_MAC_VER_11,
6689 },
6690 [RTL_CFG_2] = {
6691 .hw_start = rtl_hw_start_8101,
6692 .region = 2,
6693 .align = 8,
6694 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
6695 PCSTimeout,
6696 .features = RTL_FEATURE_MSI,
6697 .default_ver = RTL_GIGA_MAC_VER_13,
6698 }
6699};
6700
6701/* Cfg9346_Unlock assumed. */
6702static unsigned rtl_try_msi(struct rtl8169_private *tp,
6703 const struct rtl_cfg_info *cfg)
6704{
6705 void __iomem *ioaddr = tp->mmio_addr;
6706 unsigned msi = 0;
6707 u8 cfg2;
6708
6709 cfg2 = RTL_R8(Config2) & ~MSIEnable;
6710 if (cfg->features & RTL_FEATURE_MSI) {
6711 if (pci_enable_msi(tp->pci_dev)) {
6712 netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
6713 } else {
6714 cfg2 |= MSIEnable;
6715 msi = RTL_FEATURE_MSI;
6716 }
6717 }
6718 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
6719 RTL_W8(Config2, cfg2);
6720 return msi;
6721}
6722
c558386b
HW		 6723DECLARE_RTL_COND(rtl_link_list_ready_cond)
6724{
6725 void __iomem *ioaddr = tp->mmio_addr;
6726
6727 return RTL_R8(MCU) & LINK_LIST_RDY;
6728}
6729
6730DECLARE_RTL_COND(rtl_rxtx_empty_cond)
6731{
6732 void __iomem *ioaddr = tp->mmio_addr;
6733
6734 return (RTL_R8(MCU) & RXTX_EMPTY) == RXTX_EMPTY;
6735}
6736
6737static void __devinit rtl_hw_init_8168g(struct rtl8169_private *tp)
6738{
6739 void __iomem *ioaddr = tp->mmio_addr;
6740 u32 data;
6741
6742 tp->ocp_base = OCP_STD_PHY_BASE;
6743
6744 RTL_W32(MISC, RTL_R32(MISC) | RXDV_GATED_EN);
6745
6746 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
6747 return;
6748
6749 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
6750 return;
6751
6752 RTL_W8(ChipCmd, RTL_R8(ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
6753 msleep(1);
6754 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
6755
6756 data = r8168_mac_ocp_read(ioaddr, 0xe8de);
6757 data &= ~(1 << 14);
6758 r8168_mac_ocp_write(tp, 0xe8de, data);
6759
6760 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6761 return;
6762
6763 data = r8168_mac_ocp_read(ioaddr, 0xe8de);
6764 data |= (1 << 15);
6765 r8168_mac_ocp_write(tp, 0xe8de, data);
6766
6767 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6768 return;
6769}
6770
6771static void __devinit rtl_hw_initialize(struct rtl8169_private *tp)
6772{
6773 switch (tp->mac_version) {
6774 case RTL_GIGA_MAC_VER_40:
6775 case RTL_GIGA_MAC_VER_41:
6776 rtl_hw_init_8168g(tp);
6777 break;
6778
6779 default:
6780 break;
6781 }
6782}
6783
3b6cf25d
FR		 6784static int __devinit
6785rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6786{
6787 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
6788 const unsigned int region = cfg->region;
6789 struct rtl8169_private *tp;
6790 struct mii_if_info *mii;
6791 struct net_device *dev;
6792 void __iomem *ioaddr;
6793 int chipset, i;
6794 int rc;
6795
6796 if (netif_msg_drv(&debug)) {
6797 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
6798 MODULENAME, RTL8169_VERSION);
6799 }
6800
6801 dev = alloc_etherdev(sizeof (*tp));
6802 if (!dev) {
6803 rc = -ENOMEM;
6804 goto out;
6805 }
6806
6807 SET_NETDEV_DEV(dev, &pdev->dev);
fa9c385e 6808 dev->netdev_ops = &rtl_netdev_ops;
3b6cf25d
FR		 6809 tp = netdev_priv(dev);
6810 tp->dev = dev;
6811 tp->pci_dev = pdev;
6812 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
6813
6814 mii = &tp->mii;
6815 mii->dev = dev;
6816 mii->mdio_read = rtl_mdio_read;
6817 mii->mdio_write = rtl_mdio_write;
6818 mii->phy_id_mask = 0x1f;
6819 mii->reg_num_mask = 0x1f;
6820 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
6821
6822 /* disable ASPM completely as that cause random device stop working
6823 * problems as well as full system hangs for some PCIe devices users */
6824 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
6825 PCIE_LINK_STATE_CLKPM);
6826
6827 /* enable device (incl. PCI PM wakeup and hotplug setup) */
6828 rc = pci_enable_device(pdev);
6829 if (rc < 0) {
6830 netif_err(tp, probe, dev, "enable failure\n");
6831 goto err_out_free_dev_1;
6832 }
6833
6834 if (pci_set_mwi(pdev) < 0)
6835 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
6836
6837 /* make sure PCI base addr 1 is MMIO */
6838 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
6839 netif_err(tp, probe, dev,
6840 "region #%d not an MMIO resource, aborting\n",
6841 region);
6842 rc = -ENODEV;
6843 goto err_out_mwi_2;
6844 }
6845
6846 /* check for weird/broken PCI region reporting */
6847 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
6848 netif_err(tp, probe, dev,
6849 "Invalid PCI region size(s), aborting\n");
6850 rc = -ENODEV;
6851 goto err_out_mwi_2;
6852 }
6853
6854 rc = pci_request_regions(pdev, MODULENAME);
6855 if (rc < 0) {
6856 netif_err(tp, probe, dev, "could not request regions\n");
6857 goto err_out_mwi_2;
6858 }
6859
6860 tp->cp_cmd = RxChkSum;
6861
6862 if ((sizeof(dma_addr_t) > 4) &&
6863 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
6864 tp->cp_cmd |= PCIDAC;
6865 dev->features |= NETIF_F_HIGHDMA;
6866 } else {
6867 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6868 if (rc < 0) {
6869 netif_err(tp, probe, dev, "DMA configuration failed\n");
6870 goto err_out_free_res_3;
6871 }
6872 }
6873
6874 /* ioremap MMIO region */
6875 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
6876 if (!ioaddr) {
6877 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
6878 rc = -EIO;
6879 goto err_out_free_res_3;
6880 }
6881 tp->mmio_addr = ioaddr;
6882
6883 if (!pci_is_pcie(pdev))
6884 netif_info(tp, probe, dev, "not PCI Express\n");
6885
6886 /* Identify chip attached to board */
6887 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
6888
6889 rtl_init_rxcfg(tp);
6890
6891 rtl_irq_disable(tp);
6892
c558386b
HW		 6893 rtl_hw_initialize(tp);
6894
3b6cf25d
FR		 6895 rtl_hw_reset(tp);
6896
6897 rtl_ack_events(tp, 0xffff);
6898
6899 pci_set_master(pdev);
6900
6901 /*
6902 * Pretend we are using VLANs; This bypasses a nasty bug where
6903 * Interrupts stop flowing on high load on 8110SCd controllers.
6904 */
6905 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6906 tp->cp_cmd |= RxVlan;
6907
6908 rtl_init_mdio_ops(tp);
6909 rtl_init_pll_power_ops(tp);
6910 rtl_init_jumbo_ops(tp);
beb1fe18 6911 rtl_init_csi_ops(tp);
3b6cf25d
FR		 6912
6913 rtl8169_print_mac_version(tp);
6914
6915 chipset = tp->mac_version;
6916 tp->txd_version = rtl_chip_infos[chipset].txd_version;
6917
6918 RTL_W8(Cfg9346, Cfg9346_Unlock);
6919 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
6920 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
6921 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
6922 tp->features |= RTL_FEATURE_WOL;
6923 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
6924 tp->features |= RTL_FEATURE_WOL;
6925 tp->features |= rtl_try_msi(tp, cfg);
6926 RTL_W8(Cfg9346, Cfg9346_Lock);
6927
6928 if (rtl_tbi_enabled(tp)) {
6929 tp->set_speed = rtl8169_set_speed_tbi;
6930 tp->get_settings = rtl8169_gset_tbi;
6931 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
6932 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
6933 tp->link_ok = rtl8169_tbi_link_ok;
6934 tp->do_ioctl = rtl_tbi_ioctl;
6935 } else {
6936 tp->set_speed = rtl8169_set_speed_xmii;
6937 tp->get_settings = rtl8169_gset_xmii;
6938 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
6939 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
6940 tp->link_ok = rtl8169_xmii_link_ok;
6941 tp->do_ioctl = rtl_xmii_ioctl;
6942 }
6943
6944 mutex_init(&tp->wk.mutex);
6945
6946 /* Get MAC address */
6947 for (i = 0; i < ETH_ALEN; i++)
6948 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6949 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
6950
6951 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
6952 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3b6cf25d
FR		 6953
6954 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
6955
6956 /* don't enable SG, IP_CSUM and TSO by default - it might not work
6957 * properly for all devices */
6958 dev->features |= NETIF_F_RXCSUM |
6959 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6960
6961 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6962 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6963 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6964 NETIF_F_HIGHDMA;
6965
6966 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6967 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
6968 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
6969
6970 dev->hw_features |= NETIF_F_RXALL;
6971 dev->hw_features |= NETIF_F_RXFCS;
6972
6973 tp->hw_start = cfg->hw_start;
6974 tp->event_slow = cfg->event_slow;
6975
6976 tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
6977 ~(RxBOVF | RxFOVF) : ~0;
6978
6979 init_timer(&tp->timer);
6980 tp->timer.data = (unsigned long) dev;
6981 tp->timer.function = rtl8169_phy_timer;
6982
6983 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
6984
6985 rc = register_netdev(dev);
6986 if (rc < 0)
6987 goto err_out_msi_4;
6988
6989 pci_set_drvdata(pdev, dev);
6990
92a7c4e7
FR		 6991 netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
6992 rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
6993 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
3b6cf25d
FR		 6994 if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
6995 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
6996 "tx checksumming: %s]\n",
6997 rtl_chip_infos[chipset].jumbo_max,
6998 rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
6999 }
7000
7001 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
7002 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
7003 tp->mac_version == RTL_GIGA_MAC_VER_31) {
7004 rtl8168_driver_start(tp);
7005 }
7006
7007 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
7008
7009 if (pci_dev_run_wake(pdev))
7010 pm_runtime_put_noidle(&pdev->dev);
7011
7012 netif_carrier_off(dev);
7013
7014out:
7015 return rc;
7016
7017err_out_msi_4:
ad1be8d3 7018 netif_napi_del(&tp->napi);
3b6cf25d
FR		 7019 rtl_disable_msi(pdev, tp);
7020 iounmap(ioaddr);
7021err_out_free_res_3:
7022 pci_release_regions(pdev);
7023err_out_mwi_2:
7024 pci_clear_mwi(pdev);
7025 pci_disable_device(pdev);
7026err_out_free_dev_1:
7027 free_netdev(dev);
7028 goto out;
7029}
7030
1da177e4
LT		 7031static struct pci_driver rtl8169_pci_driver = {
7032 .name = MODULENAME,
7033 .id_table = rtl8169_pci_tbl,
3b6cf25d 7034 .probe = rtl_init_one,
e27566ed 7035 .remove = __devexit_p(rtl_remove_one),
1765f95d 7036 .shutdown = rtl_shutdown,
861ab440 7037 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 7038};
7039
07d3f51f 7040static int __init rtl8169_init_module(void)
1da177e4 7041{
29917620 7042 return pci_register_driver(&rtl8169_pci_driver);
1da177e4
LT		 7043}
7044
07d3f51f 7045static void __exit rtl8169_cleanup_module(void)
1da177e4
LT		 7046{
7047 pci_unregister_driver(&rtl8169_pci_driver);
7048}
7049
7050module_init(rtl8169_init_module);
7051module_exit(rtl8169_cleanup_module);
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