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Commit | Line | Data |
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1da177e4 | 1 | /* |
07d3f51f FR |
2 | * r8169.c: RealTek 8169/8168/8101 ethernet driver. |
3 | * | |
4 | * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> | |
5 | * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> | |
6 | * Copyright (c) a lot of people too. Please respect their work. | |
7 | * | |
8 | * See MAINTAINERS file for support contact information. | |
1da177e4 LT |
9 | */ |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/moduleparam.h> | |
13 | #include <linux/pci.h> | |
14 | #include <linux/netdevice.h> | |
15 | #include <linux/etherdevice.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/ethtool.h> | |
18 | #include <linux/mii.h> | |
19 | #include <linux/if_vlan.h> | |
20 | #include <linux/crc32.h> | |
21 | #include <linux/in.h> | |
22 | #include <linux/ip.h> | |
23 | #include <linux/tcp.h> | |
a6b7a407 | 24 | #include <linux/interrupt.h> |
1da177e4 | 25 | #include <linux/dma-mapping.h> |
e1759441 | 26 | #include <linux/pm_runtime.h> |
bca03d5f | 27 | #include <linux/firmware.h> |
ba04c7c9 | 28 | #include <linux/pci-aspm.h> |
70c71606 | 29 | #include <linux/prefetch.h> |
e974604b | 30 | #include <linux/ipv6.h> |
31 | #include <net/ip6_checksum.h> | |
1da177e4 LT |
32 | |
33 | #include <asm/io.h> | |
34 | #include <asm/irq.h> | |
35 | ||
865c652d | 36 | #define RTL8169_VERSION "2.3LK-NAPI" |
1da177e4 LT |
37 | #define MODULENAME "r8169" |
38 | #define PFX MODULENAME ": " | |
39 | ||
bca03d5f | 40 | #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw" |
41 | #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" | |
01dc7fec | 42 | #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw" |
43 | #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw" | |
70090424 | 44 | #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw" |
c2218925 HW |
45 | #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw" |
46 | #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw" | |
5a5e4443 | 47 | #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" |
7e18dca1 | 48 | #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw" |
b3d7b2f2 | 49 | #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw" |
45dd95c4 | 50 | #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw" |
5598bfe5 | 51 | #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw" |
58152cd4 | 52 | #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw" |
beb330a4 | 53 | #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw" |
57538c4a | 54 | #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw" |
6e1d0b89 CHL |
55 | #define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw" |
56 | #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw" | |
57 | #define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw" | |
58 | #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw" | |
bca03d5f | 59 | |
1da177e4 LT |
60 | #ifdef RTL8169_DEBUG |
61 | #define assert(expr) \ | |
5b0384f4 FR |
62 | if (!(expr)) { \ |
63 | printk( "Assertion failed! %s,%s,%s,line=%d\n", \ | |
b39d66a8 | 64 | #expr,__FILE__,__func__,__LINE__); \ |
5b0384f4 | 65 | } |
06fa7358 JP |
66 | #define dprintk(fmt, args...) \ |
67 | do { printk(KERN_DEBUG PFX fmt, ## args); } while (0) | |
1da177e4 LT |
68 | #else |
69 | #define assert(expr) do {} while (0) | |
70 | #define dprintk(fmt, args...) do {} while (0) | |
71 | #endif /* RTL8169_DEBUG */ | |
72 | ||
b57b7e5a | 73 | #define R8169_MSG_DEFAULT \ |
f0e837d9 | 74 | (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN) |
b57b7e5a | 75 | |
477206a0 JD |
76 | #define TX_SLOTS_AVAIL(tp) \ |
77 | (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx) | |
78 | ||
79 | /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */ | |
80 | #define TX_FRAGS_READY_FOR(tp,nr_frags) \ | |
81 | (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1)) | |
1da177e4 | 82 | |
1da177e4 LT |
83 | /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). |
84 | The RTL chips use a 64 element hash table based on the Ethernet CRC. */ | |
f71e1309 | 85 | static const int multicast_filter_limit = 32; |
1da177e4 | 86 | |
aee77e4a | 87 | #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */ |
1da177e4 LT |
88 | #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ |
89 | ||
90 | #define R8169_REGS_SIZE 256 | |
1d0254dd | 91 | #define R8169_RX_BUF_SIZE (SZ_16K - 1) |
1da177e4 | 92 | #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */ |
9fba0812 | 93 | #define NUM_RX_DESC 256U /* Number of Rx descriptor registers */ |
1da177e4 LT |
94 | #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) |
95 | #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) | |
96 | ||
97 | #define RTL8169_TX_TIMEOUT (6*HZ) | |
98 | #define RTL8169_PHY_TIMEOUT (10*HZ) | |
99 | ||
100 | /* write/read MMIO register */ | |
1ef7286e AS |
101 | #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg)) |
102 | #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg)) | |
103 | #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg)) | |
104 | #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg)) | |
105 | #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg)) | |
106 | #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg)) | |
1da177e4 LT |
107 | |
108 | enum mac_version { | |
85bffe6c FR |
109 | RTL_GIGA_MAC_VER_01 = 0, |
110 | RTL_GIGA_MAC_VER_02, | |
111 | RTL_GIGA_MAC_VER_03, | |
112 | RTL_GIGA_MAC_VER_04, | |
113 | RTL_GIGA_MAC_VER_05, | |
114 | RTL_GIGA_MAC_VER_06, | |
115 | RTL_GIGA_MAC_VER_07, | |
116 | RTL_GIGA_MAC_VER_08, | |
117 | RTL_GIGA_MAC_VER_09, | |
118 | RTL_GIGA_MAC_VER_10, | |
119 | RTL_GIGA_MAC_VER_11, | |
120 | RTL_GIGA_MAC_VER_12, | |
121 | RTL_GIGA_MAC_VER_13, | |
122 | RTL_GIGA_MAC_VER_14, | |
123 | RTL_GIGA_MAC_VER_15, | |
124 | RTL_GIGA_MAC_VER_16, | |
125 | RTL_GIGA_MAC_VER_17, | |
126 | RTL_GIGA_MAC_VER_18, | |
127 | RTL_GIGA_MAC_VER_19, | |
128 | RTL_GIGA_MAC_VER_20, | |
129 | RTL_GIGA_MAC_VER_21, | |
130 | RTL_GIGA_MAC_VER_22, | |
131 | RTL_GIGA_MAC_VER_23, | |
132 | RTL_GIGA_MAC_VER_24, | |
133 | RTL_GIGA_MAC_VER_25, | |
134 | RTL_GIGA_MAC_VER_26, | |
135 | RTL_GIGA_MAC_VER_27, | |
136 | RTL_GIGA_MAC_VER_28, | |
137 | RTL_GIGA_MAC_VER_29, | |
138 | RTL_GIGA_MAC_VER_30, | |
139 | RTL_GIGA_MAC_VER_31, | |
140 | RTL_GIGA_MAC_VER_32, | |
141 | RTL_GIGA_MAC_VER_33, | |
70090424 | 142 | RTL_GIGA_MAC_VER_34, |
c2218925 HW |
143 | RTL_GIGA_MAC_VER_35, |
144 | RTL_GIGA_MAC_VER_36, | |
7e18dca1 | 145 | RTL_GIGA_MAC_VER_37, |
b3d7b2f2 | 146 | RTL_GIGA_MAC_VER_38, |
5598bfe5 | 147 | RTL_GIGA_MAC_VER_39, |
c558386b HW |
148 | RTL_GIGA_MAC_VER_40, |
149 | RTL_GIGA_MAC_VER_41, | |
57538c4a | 150 | RTL_GIGA_MAC_VER_42, |
58152cd4 | 151 | RTL_GIGA_MAC_VER_43, |
45dd95c4 | 152 | RTL_GIGA_MAC_VER_44, |
6e1d0b89 CHL |
153 | RTL_GIGA_MAC_VER_45, |
154 | RTL_GIGA_MAC_VER_46, | |
155 | RTL_GIGA_MAC_VER_47, | |
156 | RTL_GIGA_MAC_VER_48, | |
935e2218 CHL |
157 | RTL_GIGA_MAC_VER_49, |
158 | RTL_GIGA_MAC_VER_50, | |
159 | RTL_GIGA_MAC_VER_51, | |
85bffe6c | 160 | RTL_GIGA_MAC_NONE = 0xff, |
1da177e4 LT |
161 | }; |
162 | ||
2b7b4318 FR |
163 | enum rtl_tx_desc_version { |
164 | RTL_TD_0 = 0, | |
165 | RTL_TD_1 = 1, | |
166 | }; | |
167 | ||
d58d46b5 FR |
168 | #define JUMBO_1K ETH_DATA_LEN |
169 | #define JUMBO_4K (4*1024 - ETH_HLEN - 2) | |
170 | #define JUMBO_6K (6*1024 - ETH_HLEN - 2) | |
171 | #define JUMBO_7K (7*1024 - ETH_HLEN - 2) | |
172 | #define JUMBO_9K (9*1024 - ETH_HLEN - 2) | |
173 | ||
6ed0e08f | 174 | #define _R(NAME,TD,FW,SZ) { \ |
d58d46b5 FR |
175 | .name = NAME, \ |
176 | .txd_version = TD, \ | |
177 | .fw_name = FW, \ | |
178 | .jumbo_max = SZ, \ | |
d58d46b5 | 179 | } |
1da177e4 | 180 | |
3c6bee1d | 181 | static const struct { |
1da177e4 | 182 | const char *name; |
2b7b4318 | 183 | enum rtl_tx_desc_version txd_version; |
953a12cc | 184 | const char *fw_name; |
d58d46b5 | 185 | u16 jumbo_max; |
85bffe6c FR |
186 | } rtl_chip_infos[] = { |
187 | /* PCI devices. */ | |
188 | [RTL_GIGA_MAC_VER_01] = | |
6ed0e08f | 189 | _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K), |
85bffe6c | 190 | [RTL_GIGA_MAC_VER_02] = |
6ed0e08f | 191 | _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K), |
85bffe6c | 192 | [RTL_GIGA_MAC_VER_03] = |
6ed0e08f | 193 | _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K), |
85bffe6c | 194 | [RTL_GIGA_MAC_VER_04] = |
6ed0e08f | 195 | _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K), |
85bffe6c | 196 | [RTL_GIGA_MAC_VER_05] = |
6ed0e08f | 197 | _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K), |
85bffe6c | 198 | [RTL_GIGA_MAC_VER_06] = |
6ed0e08f | 199 | _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K), |
85bffe6c FR |
200 | /* PCI-E devices. */ |
201 | [RTL_GIGA_MAC_VER_07] = | |
6ed0e08f | 202 | _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K), |
85bffe6c | 203 | [RTL_GIGA_MAC_VER_08] = |
6ed0e08f | 204 | _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K), |
85bffe6c | 205 | [RTL_GIGA_MAC_VER_09] = |
6ed0e08f | 206 | _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K), |
85bffe6c | 207 | [RTL_GIGA_MAC_VER_10] = |
6ed0e08f | 208 | _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K), |
85bffe6c | 209 | [RTL_GIGA_MAC_VER_11] = |
6ed0e08f | 210 | _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K), |
85bffe6c | 211 | [RTL_GIGA_MAC_VER_12] = |
6ed0e08f | 212 | _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K), |
85bffe6c | 213 | [RTL_GIGA_MAC_VER_13] = |
6ed0e08f | 214 | _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K), |
85bffe6c | 215 | [RTL_GIGA_MAC_VER_14] = |
6ed0e08f | 216 | _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K), |
85bffe6c | 217 | [RTL_GIGA_MAC_VER_15] = |
6ed0e08f | 218 | _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K), |
85bffe6c | 219 | [RTL_GIGA_MAC_VER_16] = |
6ed0e08f | 220 | _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K), |
85bffe6c | 221 | [RTL_GIGA_MAC_VER_17] = |
6ed0e08f | 222 | _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K), |
85bffe6c | 223 | [RTL_GIGA_MAC_VER_18] = |
6ed0e08f | 224 | _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K), |
85bffe6c | 225 | [RTL_GIGA_MAC_VER_19] = |
6ed0e08f | 226 | _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K), |
85bffe6c | 227 | [RTL_GIGA_MAC_VER_20] = |
6ed0e08f | 228 | _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K), |
85bffe6c | 229 | [RTL_GIGA_MAC_VER_21] = |
6ed0e08f | 230 | _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K), |
85bffe6c | 231 | [RTL_GIGA_MAC_VER_22] = |
6ed0e08f | 232 | _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K), |
85bffe6c | 233 | [RTL_GIGA_MAC_VER_23] = |
6ed0e08f | 234 | _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K), |
85bffe6c | 235 | [RTL_GIGA_MAC_VER_24] = |
6ed0e08f | 236 | _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K), |
85bffe6c | 237 | [RTL_GIGA_MAC_VER_25] = |
6ed0e08f | 238 | _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1, JUMBO_9K), |
85bffe6c | 239 | [RTL_GIGA_MAC_VER_26] = |
6ed0e08f | 240 | _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2, JUMBO_9K), |
85bffe6c | 241 | [RTL_GIGA_MAC_VER_27] = |
6ed0e08f | 242 | _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K), |
85bffe6c | 243 | [RTL_GIGA_MAC_VER_28] = |
6ed0e08f | 244 | _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K), |
85bffe6c | 245 | [RTL_GIGA_MAC_VER_29] = |
6ed0e08f | 246 | _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1, JUMBO_1K), |
85bffe6c | 247 | [RTL_GIGA_MAC_VER_30] = |
6ed0e08f | 248 | _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1, JUMBO_1K), |
85bffe6c | 249 | [RTL_GIGA_MAC_VER_31] = |
6ed0e08f | 250 | _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K), |
85bffe6c | 251 | [RTL_GIGA_MAC_VER_32] = |
6ed0e08f | 252 | _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1, JUMBO_9K), |
85bffe6c | 253 | [RTL_GIGA_MAC_VER_33] = |
6ed0e08f | 254 | _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2, JUMBO_9K), |
70090424 | 255 | [RTL_GIGA_MAC_VER_34] = |
6ed0e08f | 256 | _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3, JUMBO_9K), |
c2218925 | 257 | [RTL_GIGA_MAC_VER_35] = |
6ed0e08f | 258 | _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1, JUMBO_9K), |
c2218925 | 259 | [RTL_GIGA_MAC_VER_36] = |
6ed0e08f | 260 | _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2, JUMBO_9K), |
7e18dca1 | 261 | [RTL_GIGA_MAC_VER_37] = |
6ed0e08f | 262 | _R("RTL8402", RTL_TD_1, FIRMWARE_8402_1, JUMBO_1K), |
b3d7b2f2 | 263 | [RTL_GIGA_MAC_VER_38] = |
6ed0e08f | 264 | _R("RTL8411", RTL_TD_1, FIRMWARE_8411_1, JUMBO_9K), |
5598bfe5 | 265 | [RTL_GIGA_MAC_VER_39] = |
6ed0e08f | 266 | _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_1, JUMBO_1K), |
c558386b | 267 | [RTL_GIGA_MAC_VER_40] = |
6ed0e08f | 268 | _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_2, JUMBO_9K), |
c558386b | 269 | [RTL_GIGA_MAC_VER_41] = |
6ed0e08f | 270 | _R("RTL8168g/8111g", RTL_TD_1, NULL, JUMBO_9K), |
57538c4a | 271 | [RTL_GIGA_MAC_VER_42] = |
6ed0e08f | 272 | _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_3, JUMBO_9K), |
58152cd4 | 273 | [RTL_GIGA_MAC_VER_43] = |
6ed0e08f | 274 | _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_2, JUMBO_1K), |
45dd95c4 | 275 | [RTL_GIGA_MAC_VER_44] = |
6ed0e08f | 276 | _R("RTL8411", RTL_TD_1, FIRMWARE_8411_2, JUMBO_9K), |
6e1d0b89 | 277 | [RTL_GIGA_MAC_VER_45] = |
6ed0e08f | 278 | _R("RTL8168h/8111h", RTL_TD_1, FIRMWARE_8168H_1, JUMBO_9K), |
6e1d0b89 | 279 | [RTL_GIGA_MAC_VER_46] = |
6ed0e08f | 280 | _R("RTL8168h/8111h", RTL_TD_1, FIRMWARE_8168H_2, JUMBO_9K), |
6e1d0b89 | 281 | [RTL_GIGA_MAC_VER_47] = |
6ed0e08f | 282 | _R("RTL8107e", RTL_TD_1, FIRMWARE_8107E_1, JUMBO_1K), |
6e1d0b89 | 283 | [RTL_GIGA_MAC_VER_48] = |
6ed0e08f | 284 | _R("RTL8107e", RTL_TD_1, FIRMWARE_8107E_2, JUMBO_1K), |
935e2218 | 285 | [RTL_GIGA_MAC_VER_49] = |
6ed0e08f | 286 | _R("RTL8168ep/8111ep", RTL_TD_1, NULL, JUMBO_9K), |
935e2218 | 287 | [RTL_GIGA_MAC_VER_50] = |
6ed0e08f | 288 | _R("RTL8168ep/8111ep", RTL_TD_1, NULL, JUMBO_9K), |
935e2218 | 289 | [RTL_GIGA_MAC_VER_51] = |
6ed0e08f | 290 | _R("RTL8168ep/8111ep", RTL_TD_1, NULL, JUMBO_9K), |
953a12cc | 291 | }; |
85bffe6c | 292 | #undef _R |
953a12cc | 293 | |
bcf0bf90 FR |
294 | enum cfg_version { |
295 | RTL_CFG_0 = 0x00, | |
296 | RTL_CFG_1, | |
297 | RTL_CFG_2 | |
298 | }; | |
299 | ||
9baa3c34 | 300 | static const struct pci_device_id rtl8169_pci_tbl[] = { |
bcf0bf90 | 301 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 }, |
d2eed8cf | 302 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 }, |
610c9087 | 303 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8161), 0, 0, RTL_CFG_1 }, |
d81bf551 | 304 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 }, |
07ce4064 | 305 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 }, |
bcf0bf90 | 306 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 }, |
2a35cfa5 FR |
307 | { PCI_VENDOR_ID_DLINK, 0x4300, |
308 | PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 }, | |
bcf0bf90 | 309 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 }, |
93a3aa25 | 310 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 }, |
bc1660b5 | 311 | { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 }, |
bcf0bf90 FR |
312 | { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 }, |
313 | { PCI_VENDOR_ID_LINKSYS, 0x1032, | |
314 | PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 }, | |
11d2e282 CM |
315 | { 0x0001, 0x8168, |
316 | PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 }, | |
1da177e4 LT |
317 | {0,}, |
318 | }; | |
319 | ||
320 | MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); | |
321 | ||
27896c83 | 322 | static int use_dac = -1; |
b57b7e5a SH |
323 | static struct { |
324 | u32 msg_enable; | |
325 | } debug = { -1 }; | |
1da177e4 | 326 | |
07d3f51f FR |
327 | enum rtl_registers { |
328 | MAC0 = 0, /* Ethernet hardware address. */ | |
773d2021 | 329 | MAC4 = 4, |
07d3f51f FR |
330 | MAR0 = 8, /* Multicast filter. */ |
331 | CounterAddrLow = 0x10, | |
332 | CounterAddrHigh = 0x14, | |
333 | TxDescStartAddrLow = 0x20, | |
334 | TxDescStartAddrHigh = 0x24, | |
335 | TxHDescStartAddrLow = 0x28, | |
336 | TxHDescStartAddrHigh = 0x2c, | |
337 | FLASH = 0x30, | |
338 | ERSR = 0x36, | |
339 | ChipCmd = 0x37, | |
340 | TxPoll = 0x38, | |
341 | IntrMask = 0x3c, | |
342 | IntrStatus = 0x3e, | |
4f6b00e5 | 343 | |
07d3f51f | 344 | TxConfig = 0x40, |
4f6b00e5 HW |
345 | #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */ |
346 | #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */ | |
2b7b4318 | 347 | |
4f6b00e5 HW |
348 | RxConfig = 0x44, |
349 | #define RX128_INT_EN (1 << 15) /* 8111c and later */ | |
350 | #define RX_MULTI_EN (1 << 14) /* 8111c only */ | |
351 | #define RXCFG_FIFO_SHIFT 13 | |
352 | /* No threshold before first PCI xfer */ | |
353 | #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT) | |
beb330a4 | 354 | #define RX_EARLY_OFF (1 << 11) |
4f6b00e5 HW |
355 | #define RXCFG_DMA_SHIFT 8 |
356 | /* Unlimited maximum PCI burst. */ | |
357 | #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT) | |
2b7b4318 | 358 | |
07d3f51f FR |
359 | RxMissed = 0x4c, |
360 | Cfg9346 = 0x50, | |
361 | Config0 = 0x51, | |
362 | Config1 = 0x52, | |
363 | Config2 = 0x53, | |
d387b427 FR |
364 | #define PME_SIGNAL (1 << 5) /* 8168c and later */ |
365 | ||
07d3f51f FR |
366 | Config3 = 0x54, |
367 | Config4 = 0x55, | |
368 | Config5 = 0x56, | |
369 | MultiIntr = 0x5c, | |
370 | PHYAR = 0x60, | |
07d3f51f FR |
371 | PHYstatus = 0x6c, |
372 | RxMaxSize = 0xda, | |
373 | CPlusCmd = 0xe0, | |
374 | IntrMitigate = 0xe2, | |
50970831 FR |
375 | |
376 | #define RTL_COALESCE_MASK 0x0f | |
377 | #define RTL_COALESCE_SHIFT 4 | |
378 | #define RTL_COALESCE_T_MAX (RTL_COALESCE_MASK) | |
379 | #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_MASK << 2) | |
380 | ||
07d3f51f FR |
381 | RxDescAddrLow = 0xe4, |
382 | RxDescAddrHigh = 0xe8, | |
f0298f81 | 383 | EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */ |
384 | ||
385 | #define NoEarlyTx 0x3f /* Max value : no early transmit. */ | |
386 | ||
387 | MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */ | |
388 | ||
389 | #define TxPacketMax (8064 >> 7) | |
3090bd9a | 390 | #define EarlySize 0x27 |
f0298f81 | 391 | |
07d3f51f FR |
392 | FuncEvent = 0xf0, |
393 | FuncEventMask = 0xf4, | |
394 | FuncPresetState = 0xf8, | |
935e2218 CHL |
395 | IBCR0 = 0xf8, |
396 | IBCR2 = 0xf9, | |
397 | IBIMR0 = 0xfa, | |
398 | IBISR0 = 0xfb, | |
07d3f51f | 399 | FuncForceEvent = 0xfc, |
1da177e4 LT |
400 | }; |
401 | ||
f162a5d1 FR |
402 | enum rtl8110_registers { |
403 | TBICSR = 0x64, | |
404 | TBI_ANAR = 0x68, | |
405 | TBI_LPAR = 0x6a, | |
406 | }; | |
407 | ||
408 | enum rtl8168_8101_registers { | |
409 | CSIDR = 0x64, | |
410 | CSIAR = 0x68, | |
411 | #define CSIAR_FLAG 0x80000000 | |
412 | #define CSIAR_WRITE_CMD 0x80000000 | |
ff1d7331 HK |
413 | #define CSIAR_BYTE_ENABLE 0x0000f000 |
414 | #define CSIAR_ADDR_MASK 0x00000fff | |
065c27c1 | 415 | PMCH = 0x6f, |
f162a5d1 FR |
416 | EPHYAR = 0x80, |
417 | #define EPHYAR_FLAG 0x80000000 | |
418 | #define EPHYAR_WRITE_CMD 0x80000000 | |
419 | #define EPHYAR_REG_MASK 0x1f | |
420 | #define EPHYAR_REG_SHIFT 16 | |
421 | #define EPHYAR_DATA_MASK 0xffff | |
5a5e4443 | 422 | DLLPR = 0xd0, |
4f6b00e5 | 423 | #define PFM_EN (1 << 6) |
6e1d0b89 | 424 | #define TX_10M_PS_EN (1 << 7) |
f162a5d1 FR |
425 | DBG_REG = 0xd1, |
426 | #define FIX_NAK_1 (1 << 4) | |
427 | #define FIX_NAK_2 (1 << 3) | |
5a5e4443 HW |
428 | TWSI = 0xd2, |
429 | MCU = 0xd3, | |
4f6b00e5 | 430 | #define NOW_IS_OOB (1 << 7) |
c558386b HW |
431 | #define TX_EMPTY (1 << 5) |
432 | #define RX_EMPTY (1 << 4) | |
433 | #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY) | |
5a5e4443 HW |
434 | #define EN_NDP (1 << 3) |
435 | #define EN_OOB_RESET (1 << 2) | |
c558386b | 436 | #define LINK_LIST_RDY (1 << 1) |
daf9df6d | 437 | EFUSEAR = 0xdc, |
438 | #define EFUSEAR_FLAG 0x80000000 | |
439 | #define EFUSEAR_WRITE_CMD 0x80000000 | |
440 | #define EFUSEAR_READ_CMD 0x00000000 | |
441 | #define EFUSEAR_REG_MASK 0x03ff | |
442 | #define EFUSEAR_REG_SHIFT 8 | |
443 | #define EFUSEAR_DATA_MASK 0xff | |
6e1d0b89 CHL |
444 | MISC_1 = 0xf2, |
445 | #define PFM_D3COLD_EN (1 << 6) | |
f162a5d1 FR |
446 | }; |
447 | ||
c0e45c1c | 448 | enum rtl8168_registers { |
4f6b00e5 HW |
449 | LED_FREQ = 0x1a, |
450 | EEE_LED = 0x1b, | |
b646d900 | 451 | ERIDR = 0x70, |
452 | ERIAR = 0x74, | |
453 | #define ERIAR_FLAG 0x80000000 | |
454 | #define ERIAR_WRITE_CMD 0x80000000 | |
455 | #define ERIAR_READ_CMD 0x00000000 | |
456 | #define ERIAR_ADDR_BYTE_ALIGN 4 | |
b646d900 | 457 | #define ERIAR_TYPE_SHIFT 16 |
4f6b00e5 HW |
458 | #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT) |
459 | #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT) | |
460 | #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT) | |
935e2218 | 461 | #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT) |
4f6b00e5 HW |
462 | #define ERIAR_MASK_SHIFT 12 |
463 | #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT) | |
464 | #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT) | |
6e1d0b89 | 465 | #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT) |
c558386b | 466 | #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT) |
4f6b00e5 | 467 | #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT) |
c0e45c1c | 468 | EPHY_RXER_NUM = 0x7c, |
469 | OCPDR = 0xb0, /* OCP GPHY access */ | |
470 | #define OCPDR_WRITE_CMD 0x80000000 | |
471 | #define OCPDR_READ_CMD 0x00000000 | |
472 | #define OCPDR_REG_MASK 0x7f | |
473 | #define OCPDR_GPHY_REG_SHIFT 16 | |
474 | #define OCPDR_DATA_MASK 0xffff | |
475 | OCPAR = 0xb4, | |
476 | #define OCPAR_FLAG 0x80000000 | |
477 | #define OCPAR_GPHY_WRITE_CMD 0x8000f060 | |
478 | #define OCPAR_GPHY_READ_CMD 0x0000f060 | |
c558386b | 479 | GPHY_OCP = 0xb8, |
01dc7fec | 480 | RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */ |
481 | MISC = 0xf0, /* 8168e only. */ | |
cecb5fd7 | 482 | #define TXPLA_RST (1 << 29) |
5598bfe5 | 483 | #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */ |
4f6b00e5 | 484 | #define PWM_EN (1 << 22) |
c558386b | 485 | #define RXDV_GATED_EN (1 << 19) |
5598bfe5 | 486 | #define EARLY_TALLY_EN (1 << 16) |
c0e45c1c | 487 | }; |
488 | ||
07d3f51f | 489 | enum rtl_register_content { |
1da177e4 | 490 | /* InterruptStatusBits */ |
07d3f51f FR |
491 | SYSErr = 0x8000, |
492 | PCSTimeout = 0x4000, | |
493 | SWInt = 0x0100, | |
494 | TxDescUnavail = 0x0080, | |
495 | RxFIFOOver = 0x0040, | |
496 | LinkChg = 0x0020, | |
497 | RxOverflow = 0x0010, | |
498 | TxErr = 0x0008, | |
499 | TxOK = 0x0004, | |
500 | RxErr = 0x0002, | |
501 | RxOK = 0x0001, | |
1da177e4 LT |
502 | |
503 | /* RxStatusDesc */ | |
e03f33af | 504 | RxBOVF = (1 << 24), |
9dccf611 FR |
505 | RxFOVF = (1 << 23), |
506 | RxRWT = (1 << 22), | |
507 | RxRES = (1 << 21), | |
508 | RxRUNT = (1 << 20), | |
509 | RxCRC = (1 << 19), | |
1da177e4 LT |
510 | |
511 | /* ChipCmdBits */ | |
4f6b00e5 | 512 | StopReq = 0x80, |
07d3f51f FR |
513 | CmdReset = 0x10, |
514 | CmdRxEnb = 0x08, | |
515 | CmdTxEnb = 0x04, | |
516 | RxBufEmpty = 0x01, | |
1da177e4 | 517 | |
275391a4 FR |
518 | /* TXPoll register p.5 */ |
519 | HPQ = 0x80, /* Poll cmd on the high prio queue */ | |
520 | NPQ = 0x40, /* Poll cmd on the low prio queue */ | |
521 | FSWInt = 0x01, /* Forced software interrupt */ | |
522 | ||
1da177e4 | 523 | /* Cfg9346Bits */ |
07d3f51f FR |
524 | Cfg9346_Lock = 0x00, |
525 | Cfg9346_Unlock = 0xc0, | |
1da177e4 LT |
526 | |
527 | /* rx_mode_bits */ | |
07d3f51f FR |
528 | AcceptErr = 0x20, |
529 | AcceptRunt = 0x10, | |
530 | AcceptBroadcast = 0x08, | |
531 | AcceptMulticast = 0x04, | |
532 | AcceptMyPhys = 0x02, | |
533 | AcceptAllPhys = 0x01, | |
1687b566 | 534 | #define RX_CONFIG_ACCEPT_MASK 0x3f |
1da177e4 | 535 | |
1da177e4 LT |
536 | /* TxConfigBits */ |
537 | TxInterFrameGapShift = 24, | |
538 | TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ | |
539 | ||
5d06a99f | 540 | /* Config1 register p.24 */ |
f162a5d1 FR |
541 | LEDS1 = (1 << 7), |
542 | LEDS0 = (1 << 6), | |
f162a5d1 FR |
543 | Speed_down = (1 << 4), |
544 | MEMMAP = (1 << 3), | |
545 | IOMAP = (1 << 2), | |
546 | VPD = (1 << 1), | |
5d06a99f FR |
547 | PMEnable = (1 << 0), /* Power Management Enable */ |
548 | ||
6dccd16b | 549 | /* Config2 register p. 25 */ |
57538c4a | 550 | ClkReqEn = (1 << 7), /* Clock Request Enable */ |
2ca6cf06 | 551 | MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */ |
6dccd16b FR |
552 | PCI_Clock_66MHz = 0x01, |
553 | PCI_Clock_33MHz = 0x00, | |
554 | ||
61a4dcc2 FR |
555 | /* Config3 register p.25 */ |
556 | MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ | |
557 | LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ | |
d58d46b5 | 558 | Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */ |
b51ecea8 | 559 | Rdy_to_L23 = (1 << 1), /* L23 Enable */ |
f162a5d1 | 560 | Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ |
61a4dcc2 | 561 | |
d58d46b5 FR |
562 | /* Config4 register */ |
563 | Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */ | |
564 | ||
5d06a99f | 565 | /* Config5 register p.27 */ |
61a4dcc2 FR |
566 | BWF = (1 << 6), /* Accept Broadcast wakeup frame */ |
567 | MWF = (1 << 5), /* Accept Multicast wakeup frame */ | |
568 | UWF = (1 << 4), /* Accept Unicast wakeup frame */ | |
cecb5fd7 | 569 | Spi_en = (1 << 3), |
61a4dcc2 | 570 | LanWake = (1 << 1), /* LanWake enable/disable */ |
5d06a99f | 571 | PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ |
57538c4a | 572 | ASPM_en = (1 << 0), /* ASPM enable */ |
5d06a99f | 573 | |
1da177e4 LT |
574 | /* TBICSR p.28 */ |
575 | TBIReset = 0x80000000, | |
576 | TBILoopback = 0x40000000, | |
577 | TBINwEnable = 0x20000000, | |
578 | TBINwRestart = 0x10000000, | |
579 | TBILinkOk = 0x02000000, | |
580 | TBINwComplete = 0x01000000, | |
581 | ||
582 | /* CPlusCmd p.31 */ | |
f162a5d1 FR |
583 | EnableBist = (1 << 15), // 8168 8101 |
584 | Mac_dbgo_oe = (1 << 14), // 8168 8101 | |
585 | Normal_mode = (1 << 13), // unused | |
586 | Force_half_dup = (1 << 12), // 8168 8101 | |
587 | Force_rxflow_en = (1 << 11), // 8168 8101 | |
588 | Force_txflow_en = (1 << 10), // 8168 8101 | |
589 | Cxpl_dbg_sel = (1 << 9), // 8168 8101 | |
590 | ASF = (1 << 8), // 8168 8101 | |
591 | PktCntrDisable = (1 << 7), // 8168 8101 | |
592 | Mac_dbgo_sel = 0x001c, // 8168 | |
1da177e4 LT |
593 | RxVlan = (1 << 6), |
594 | RxChkSum = (1 << 5), | |
595 | PCIDAC = (1 << 4), | |
596 | PCIMulRW = (1 << 3), | |
9a3c81fa | 597 | #define INTT_MASK GENMASK(1, 0) |
0e485150 FR |
598 | INTT_0 = 0x0000, // 8168 |
599 | INTT_1 = 0x0001, // 8168 | |
600 | INTT_2 = 0x0002, // 8168 | |
601 | INTT_3 = 0x0003, // 8168 | |
1da177e4 LT |
602 | |
603 | /* rtl8169_PHYstatus */ | |
07d3f51f FR |
604 | TBI_Enable = 0x80, |
605 | TxFlowCtrl = 0x40, | |
606 | RxFlowCtrl = 0x20, | |
607 | _1000bpsF = 0x10, | |
608 | _100bps = 0x08, | |
609 | _10bps = 0x04, | |
610 | LinkStatus = 0x02, | |
611 | FullDup = 0x01, | |
1da177e4 | 612 | |
1da177e4 | 613 | /* _TBICSRBit */ |
07d3f51f | 614 | TBILinkOK = 0x02000000, |
d4a3a0fc | 615 | |
6e85d5ad CV |
616 | /* ResetCounterCommand */ |
617 | CounterReset = 0x1, | |
618 | ||
d4a3a0fc | 619 | /* DumpCounterCommand */ |
07d3f51f | 620 | CounterDump = 0x8, |
6e1d0b89 CHL |
621 | |
622 | /* magic enable v2 */ | |
623 | MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */ | |
1da177e4 LT |
624 | }; |
625 | ||
2b7b4318 FR |
626 | enum rtl_desc_bit { |
627 | /* First doubleword. */ | |
1da177e4 LT |
628 | DescOwn = (1 << 31), /* Descriptor is owned by NIC */ |
629 | RingEnd = (1 << 30), /* End of descriptor ring */ | |
630 | FirstFrag = (1 << 29), /* First segment of a packet */ | |
631 | LastFrag = (1 << 28), /* Final segment of a packet */ | |
2b7b4318 FR |
632 | }; |
633 | ||
634 | /* Generic case. */ | |
635 | enum rtl_tx_desc_bit { | |
636 | /* First doubleword. */ | |
637 | TD_LSO = (1 << 27), /* Large Send Offload */ | |
638 | #define TD_MSS_MAX 0x07ffu /* MSS value */ | |
1da177e4 | 639 | |
2b7b4318 FR |
640 | /* Second doubleword. */ |
641 | TxVlanTag = (1 << 17), /* Add VLAN tag */ | |
642 | }; | |
643 | ||
644 | /* 8169, 8168b and 810x except 8102e. */ | |
645 | enum rtl_tx_desc_bit_0 { | |
646 | /* First doubleword. */ | |
647 | #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */ | |
648 | TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */ | |
649 | TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */ | |
650 | TD0_IP_CS = (1 << 18), /* Calculate IP checksum */ | |
651 | }; | |
652 | ||
653 | /* 8102e, 8168c and beyond. */ | |
654 | enum rtl_tx_desc_bit_1 { | |
bdfa4ed6 | 655 | /* First doubleword. */ |
656 | TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */ | |
e974604b | 657 | TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */ |
bdfa4ed6 | 658 | #define GTTCPHO_SHIFT 18 |
e974604b | 659 | #define GTTCPHO_MAX 0x7fU |
bdfa4ed6 | 660 | |
2b7b4318 | 661 | /* Second doubleword. */ |
e974604b | 662 | #define TCPHO_SHIFT 18 |
663 | #define TCPHO_MAX 0x3ffU | |
2b7b4318 | 664 | #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */ |
e974604b | 665 | TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */ |
666 | TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */ | |
2b7b4318 FR |
667 | TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */ |
668 | TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */ | |
669 | }; | |
1da177e4 | 670 | |
2b7b4318 | 671 | enum rtl_rx_desc_bit { |
1da177e4 LT |
672 | /* Rx private */ |
673 | PID1 = (1 << 18), /* Protocol ID bit 1/2 */ | |
9b60047a | 674 | PID0 = (1 << 17), /* Protocol ID bit 0/2 */ |
1da177e4 LT |
675 | |
676 | #define RxProtoUDP (PID1) | |
677 | #define RxProtoTCP (PID0) | |
678 | #define RxProtoIP (PID1 | PID0) | |
679 | #define RxProtoMask RxProtoIP | |
680 | ||
681 | IPFail = (1 << 16), /* IP checksum failed */ | |
682 | UDPFail = (1 << 15), /* UDP/IP checksum failed */ | |
683 | TCPFail = (1 << 14), /* TCP/IP checksum failed */ | |
684 | RxVlanTag = (1 << 16), /* VLAN tag available */ | |
685 | }; | |
686 | ||
687 | #define RsvdMask 0x3fffc000 | |
12d42c50 | 688 | #define CPCMD_QUIRK_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK) |
1da177e4 LT |
689 | |
690 | struct TxDesc { | |
6cccd6e7 REB |
691 | __le32 opts1; |
692 | __le32 opts2; | |
693 | __le64 addr; | |
1da177e4 LT |
694 | }; |
695 | ||
696 | struct RxDesc { | |
6cccd6e7 REB |
697 | __le32 opts1; |
698 | __le32 opts2; | |
699 | __le64 addr; | |
1da177e4 LT |
700 | }; |
701 | ||
702 | struct ring_info { | |
703 | struct sk_buff *skb; | |
704 | u32 len; | |
705 | u8 __pad[sizeof(void *) - sizeof(u32)]; | |
706 | }; | |
707 | ||
355423d0 IV |
708 | struct rtl8169_counters { |
709 | __le64 tx_packets; | |
710 | __le64 rx_packets; | |
711 | __le64 tx_errors; | |
712 | __le32 rx_errors; | |
713 | __le16 rx_missed; | |
714 | __le16 align_errors; | |
715 | __le32 tx_one_collision; | |
716 | __le32 tx_multi_collision; | |
717 | __le64 rx_unicast; | |
718 | __le64 rx_broadcast; | |
719 | __le32 rx_multicast; | |
720 | __le16 tx_aborted; | |
721 | __le16 tx_underun; | |
722 | }; | |
723 | ||
6e85d5ad CV |
724 | struct rtl8169_tc_offsets { |
725 | bool inited; | |
726 | __le64 tx_errors; | |
727 | __le32 tx_multi_collision; | |
6e85d5ad CV |
728 | __le16 tx_aborted; |
729 | }; | |
730 | ||
da78dbff | 731 | enum rtl_flag { |
6c4a70c5 | 732 | RTL_FLAG_TASK_ENABLED, |
da78dbff FR |
733 | RTL_FLAG_TASK_SLOW_PENDING, |
734 | RTL_FLAG_TASK_RESET_PENDING, | |
735 | RTL_FLAG_TASK_PHY_PENDING, | |
736 | RTL_FLAG_MAX | |
737 | }; | |
738 | ||
8027aa24 JW |
739 | struct rtl8169_stats { |
740 | u64 packets; | |
741 | u64 bytes; | |
742 | struct u64_stats_sync syncp; | |
743 | }; | |
744 | ||
1da177e4 LT |
745 | struct rtl8169_private { |
746 | void __iomem *mmio_addr; /* memory map physical address */ | |
cecb5fd7 | 747 | struct pci_dev *pci_dev; |
c4028958 | 748 | struct net_device *dev; |
bea3348e | 749 | struct napi_struct napi; |
b57b7e5a | 750 | u32 msg_enable; |
2b7b4318 | 751 | u16 mac_version; |
1da177e4 LT |
752 | u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ |
753 | u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ | |
1da177e4 | 754 | u32 dirty_tx; |
8027aa24 JW |
755 | struct rtl8169_stats rx_stats; |
756 | struct rtl8169_stats tx_stats; | |
1da177e4 LT |
757 | struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ |
758 | struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ | |
759 | dma_addr_t TxPhyAddr; | |
760 | dma_addr_t RxPhyAddr; | |
6f0333b8 | 761 | void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */ |
1da177e4 | 762 | struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ |
1da177e4 LT |
763 | struct timer_list timer; |
764 | u16 cp_cmd; | |
da78dbff FR |
765 | |
766 | u16 event_slow; | |
50970831 | 767 | const struct rtl_coalesce_info *coalesce_info; |
c0e45c1c | 768 | |
769 | struct mdio_ops { | |
24192210 FR |
770 | void (*write)(struct rtl8169_private *, int, int); |
771 | int (*read)(struct rtl8169_private *, int); | |
c0e45c1c | 772 | } mdio_ops; |
773 | ||
d58d46b5 FR |
774 | struct jumbo_ops { |
775 | void (*enable)(struct rtl8169_private *); | |
776 | void (*disable)(struct rtl8169_private *); | |
777 | } jumbo_ops; | |
778 | ||
54405cde | 779 | int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv); |
6fa1ba61 PR |
780 | int (*get_link_ksettings)(struct net_device *, |
781 | struct ethtool_link_ksettings *); | |
4da19633 | 782 | void (*phy_reset_enable)(struct rtl8169_private *tp); |
61cb532d | 783 | void (*hw_start)(struct rtl8169_private *tp); |
4da19633 | 784 | unsigned int (*phy_reset_pending)(struct rtl8169_private *tp); |
1ef7286e | 785 | unsigned int (*link_ok)(struct rtl8169_private *tp); |
8b4ab28d | 786 | int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd); |
5888d3fc | 787 | bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *); |
4422bcd4 FR |
788 | |
789 | struct { | |
da78dbff FR |
790 | DECLARE_BITMAP(flags, RTL_FLAG_MAX); |
791 | struct mutex mutex; | |
4422bcd4 FR |
792 | struct work_struct work; |
793 | } wk; | |
794 | ||
ccdffb9a | 795 | struct mii_if_info mii; |
42020320 CV |
796 | dma_addr_t counters_phys_addr; |
797 | struct rtl8169_counters *counters; | |
6e85d5ad | 798 | struct rtl8169_tc_offsets tc_offset; |
e1759441 | 799 | u32 saved_wolopts; |
f1e02ed1 | 800 | |
b6ffd97f FR |
801 | struct rtl_fw { |
802 | const struct firmware *fw; | |
1c361efb FR |
803 | |
804 | #define RTL_VER_SIZE 32 | |
805 | ||
806 | char version[RTL_VER_SIZE]; | |
807 | ||
808 | struct rtl_fw_phy_action { | |
809 | __le32 *code; | |
810 | size_t size; | |
811 | } phy_action; | |
b6ffd97f | 812 | } *rtl_fw; |
497888cf | 813 | #define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN) |
c558386b HW |
814 | |
815 | u32 ocp_base; | |
1da177e4 LT |
816 | }; |
817 | ||
979b6c13 | 818 | MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); |
1da177e4 | 819 | MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); |
1da177e4 | 820 | module_param(use_dac, int, 0); |
4300e8c7 | 821 | MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot."); |
b57b7e5a SH |
822 | module_param_named(debug, debug.msg_enable, int, 0); |
823 | MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)"); | |
1da177e4 LT |
824 | MODULE_LICENSE("GPL"); |
825 | MODULE_VERSION(RTL8169_VERSION); | |
bca03d5f | 826 | MODULE_FIRMWARE(FIRMWARE_8168D_1); |
827 | MODULE_FIRMWARE(FIRMWARE_8168D_2); | |
01dc7fec | 828 | MODULE_FIRMWARE(FIRMWARE_8168E_1); |
829 | MODULE_FIRMWARE(FIRMWARE_8168E_2); | |
bbb8af75 | 830 | MODULE_FIRMWARE(FIRMWARE_8168E_3); |
5a5e4443 | 831 | MODULE_FIRMWARE(FIRMWARE_8105E_1); |
c2218925 HW |
832 | MODULE_FIRMWARE(FIRMWARE_8168F_1); |
833 | MODULE_FIRMWARE(FIRMWARE_8168F_2); | |
7e18dca1 | 834 | MODULE_FIRMWARE(FIRMWARE_8402_1); |
b3d7b2f2 | 835 | MODULE_FIRMWARE(FIRMWARE_8411_1); |
45dd95c4 | 836 | MODULE_FIRMWARE(FIRMWARE_8411_2); |
5598bfe5 | 837 | MODULE_FIRMWARE(FIRMWARE_8106E_1); |
58152cd4 | 838 | MODULE_FIRMWARE(FIRMWARE_8106E_2); |
beb330a4 | 839 | MODULE_FIRMWARE(FIRMWARE_8168G_2); |
57538c4a | 840 | MODULE_FIRMWARE(FIRMWARE_8168G_3); |
6e1d0b89 CHL |
841 | MODULE_FIRMWARE(FIRMWARE_8168H_1); |
842 | MODULE_FIRMWARE(FIRMWARE_8168H_2); | |
a3bf5c42 FR |
843 | MODULE_FIRMWARE(FIRMWARE_8107E_1); |
844 | MODULE_FIRMWARE(FIRMWARE_8107E_2); | |
1da177e4 | 845 | |
1e1205b7 HK |
846 | static inline struct device *tp_to_dev(struct rtl8169_private *tp) |
847 | { | |
848 | return &tp->pci_dev->dev; | |
849 | } | |
850 | ||
da78dbff FR |
851 | static void rtl_lock_work(struct rtl8169_private *tp) |
852 | { | |
853 | mutex_lock(&tp->wk.mutex); | |
854 | } | |
855 | ||
856 | static void rtl_unlock_work(struct rtl8169_private *tp) | |
857 | { | |
858 | mutex_unlock(&tp->wk.mutex); | |
859 | } | |
860 | ||
cb73200c | 861 | static void rtl_tx_performance_tweak(struct rtl8169_private *tp, u16 force) |
d58d46b5 | 862 | { |
cb73200c | 863 | pcie_capability_clear_and_set_word(tp->pci_dev, PCI_EXP_DEVCTL, |
7d7903b2 | 864 | PCI_EXP_DEVCTL_READRQ, force); |
d58d46b5 FR |
865 | } |
866 | ||
ffc46952 FR |
867 | struct rtl_cond { |
868 | bool (*check)(struct rtl8169_private *); | |
869 | const char *msg; | |
870 | }; | |
871 | ||
872 | static void rtl_udelay(unsigned int d) | |
873 | { | |
874 | udelay(d); | |
875 | } | |
876 | ||
877 | static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c, | |
878 | void (*delay)(unsigned int), unsigned int d, int n, | |
879 | bool high) | |
880 | { | |
881 | int i; | |
882 | ||
883 | for (i = 0; i < n; i++) { | |
884 | delay(d); | |
885 | if (c->check(tp) == high) | |
886 | return true; | |
887 | } | |
82e316ef FR |
888 | netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n", |
889 | c->msg, !high, n, d); | |
ffc46952 FR |
890 | return false; |
891 | } | |
892 | ||
893 | static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp, | |
894 | const struct rtl_cond *c, | |
895 | unsigned int d, int n) | |
896 | { | |
897 | return rtl_loop_wait(tp, c, rtl_udelay, d, n, true); | |
898 | } | |
899 | ||
900 | static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp, | |
901 | const struct rtl_cond *c, | |
902 | unsigned int d, int n) | |
903 | { | |
904 | return rtl_loop_wait(tp, c, rtl_udelay, d, n, false); | |
905 | } | |
906 | ||
907 | static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp, | |
908 | const struct rtl_cond *c, | |
909 | unsigned int d, int n) | |
910 | { | |
911 | return rtl_loop_wait(tp, c, msleep, d, n, true); | |
912 | } | |
913 | ||
914 | static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp, | |
915 | const struct rtl_cond *c, | |
916 | unsigned int d, int n) | |
917 | { | |
918 | return rtl_loop_wait(tp, c, msleep, d, n, false); | |
919 | } | |
920 | ||
921 | #define DECLARE_RTL_COND(name) \ | |
922 | static bool name ## _check(struct rtl8169_private *); \ | |
923 | \ | |
924 | static const struct rtl_cond name = { \ | |
925 | .check = name ## _check, \ | |
926 | .msg = #name \ | |
927 | }; \ | |
928 | \ | |
929 | static bool name ## _check(struct rtl8169_private *tp) | |
930 | ||
c558386b HW |
931 | static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg) |
932 | { | |
933 | if (reg & 0xffff0001) { | |
934 | netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg); | |
935 | return true; | |
936 | } | |
937 | return false; | |
938 | } | |
939 | ||
940 | DECLARE_RTL_COND(rtl_ocp_gphy_cond) | |
941 | { | |
1ef7286e | 942 | return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG; |
c558386b HW |
943 | } |
944 | ||
945 | static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) | |
946 | { | |
c558386b HW |
947 | if (rtl_ocp_reg_failure(tp, reg)) |
948 | return; | |
949 | ||
1ef7286e | 950 | RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data); |
c558386b HW |
951 | |
952 | rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10); | |
953 | } | |
954 | ||
955 | static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg) | |
956 | { | |
c558386b HW |
957 | if (rtl_ocp_reg_failure(tp, reg)) |
958 | return 0; | |
959 | ||
1ef7286e | 960 | RTL_W32(tp, GPHY_OCP, reg << 15); |
c558386b HW |
961 | |
962 | return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ? | |
1ef7286e | 963 | (RTL_R32(tp, GPHY_OCP) & 0xffff) : ~0; |
c558386b HW |
964 | } |
965 | ||
c558386b HW |
966 | static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) |
967 | { | |
c558386b HW |
968 | if (rtl_ocp_reg_failure(tp, reg)) |
969 | return; | |
970 | ||
1ef7286e | 971 | RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data); |
c558386b HW |
972 | } |
973 | ||
974 | static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) | |
975 | { | |
c558386b HW |
976 | if (rtl_ocp_reg_failure(tp, reg)) |
977 | return 0; | |
978 | ||
1ef7286e | 979 | RTL_W32(tp, OCPDR, reg << 15); |
c558386b | 980 | |
1ef7286e | 981 | return RTL_R32(tp, OCPDR); |
c558386b HW |
982 | } |
983 | ||
984 | #define OCP_STD_PHY_BASE 0xa400 | |
985 | ||
986 | static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value) | |
987 | { | |
988 | if (reg == 0x1f) { | |
989 | tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE; | |
990 | return; | |
991 | } | |
992 | ||
993 | if (tp->ocp_base != OCP_STD_PHY_BASE) | |
994 | reg -= 0x10; | |
995 | ||
996 | r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value); | |
997 | } | |
998 | ||
999 | static int r8168g_mdio_read(struct rtl8169_private *tp, int reg) | |
1000 | { | |
1001 | if (tp->ocp_base != OCP_STD_PHY_BASE) | |
1002 | reg -= 0x10; | |
1003 | ||
1004 | return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2); | |
1005 | } | |
1006 | ||
eee3786f | 1007 | static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value) |
1008 | { | |
1009 | if (reg == 0x1f) { | |
1010 | tp->ocp_base = value << 4; | |
1011 | return; | |
1012 | } | |
1013 | ||
1014 | r8168_mac_ocp_write(tp, tp->ocp_base + reg, value); | |
1015 | } | |
1016 | ||
1017 | static int mac_mcu_read(struct rtl8169_private *tp, int reg) | |
1018 | { | |
1019 | return r8168_mac_ocp_read(tp, tp->ocp_base + reg); | |
1020 | } | |
1021 | ||
ffc46952 FR |
1022 | DECLARE_RTL_COND(rtl_phyar_cond) |
1023 | { | |
1ef7286e | 1024 | return RTL_R32(tp, PHYAR) & 0x80000000; |
ffc46952 FR |
1025 | } |
1026 | ||
24192210 | 1027 | static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value) |
1da177e4 | 1028 | { |
1ef7286e | 1029 | RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff)); |
1da177e4 | 1030 | |
ffc46952 | 1031 | rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20); |
024a07ba | 1032 | /* |
81a95f04 TT |
1033 | * According to hardware specs a 20us delay is required after write |
1034 | * complete indication, but before sending next command. | |
024a07ba | 1035 | */ |
81a95f04 | 1036 | udelay(20); |
1da177e4 LT |
1037 | } |
1038 | ||
24192210 | 1039 | static int r8169_mdio_read(struct rtl8169_private *tp, int reg) |
1da177e4 | 1040 | { |
ffc46952 | 1041 | int value; |
1da177e4 | 1042 | |
1ef7286e | 1043 | RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16); |
1da177e4 | 1044 | |
ffc46952 | 1045 | value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ? |
1ef7286e | 1046 | RTL_R32(tp, PHYAR) & 0xffff : ~0; |
ffc46952 | 1047 | |
81a95f04 TT |
1048 | /* |
1049 | * According to hardware specs a 20us delay is required after read | |
1050 | * complete indication, but before sending next command. | |
1051 | */ | |
1052 | udelay(20); | |
1053 | ||
1da177e4 LT |
1054 | return value; |
1055 | } | |
1056 | ||
935e2218 CHL |
1057 | DECLARE_RTL_COND(rtl_ocpar_cond) |
1058 | { | |
1ef7286e | 1059 | return RTL_R32(tp, OCPAR) & OCPAR_FLAG; |
935e2218 CHL |
1060 | } |
1061 | ||
24192210 | 1062 | static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data) |
c0e45c1c | 1063 | { |
1ef7286e AS |
1064 | RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT)); |
1065 | RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD); | |
1066 | RTL_W32(tp, EPHY_RXER_NUM, 0); | |
c0e45c1c | 1067 | |
ffc46952 | 1068 | rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100); |
c0e45c1c | 1069 | } |
1070 | ||
24192210 | 1071 | static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value) |
c0e45c1c | 1072 | { |
24192210 FR |
1073 | r8168dp_1_mdio_access(tp, reg, |
1074 | OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK)); | |
c0e45c1c | 1075 | } |
1076 | ||
24192210 | 1077 | static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg) |
c0e45c1c | 1078 | { |
24192210 | 1079 | r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD); |
c0e45c1c | 1080 | |
1081 | mdelay(1); | |
1ef7286e AS |
1082 | RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD); |
1083 | RTL_W32(tp, EPHY_RXER_NUM, 0); | |
c0e45c1c | 1084 | |
ffc46952 | 1085 | return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ? |
1ef7286e | 1086 | RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : ~0; |
c0e45c1c | 1087 | } |
1088 | ||
e6de30d6 | 1089 | #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000 |
1090 | ||
1ef7286e | 1091 | static void r8168dp_2_mdio_start(struct rtl8169_private *tp) |
e6de30d6 | 1092 | { |
1ef7286e | 1093 | RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); |
e6de30d6 | 1094 | } |
1095 | ||
1ef7286e | 1096 | static void r8168dp_2_mdio_stop(struct rtl8169_private *tp) |
e6de30d6 | 1097 | { |
1ef7286e | 1098 | RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT); |
e6de30d6 | 1099 | } |
1100 | ||
24192210 | 1101 | static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value) |
e6de30d6 | 1102 | { |
1ef7286e | 1103 | r8168dp_2_mdio_start(tp); |
e6de30d6 | 1104 | |
24192210 | 1105 | r8169_mdio_write(tp, reg, value); |
e6de30d6 | 1106 | |
1ef7286e | 1107 | r8168dp_2_mdio_stop(tp); |
e6de30d6 | 1108 | } |
1109 | ||
24192210 | 1110 | static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg) |
e6de30d6 | 1111 | { |
1112 | int value; | |
1113 | ||
1ef7286e | 1114 | r8168dp_2_mdio_start(tp); |
e6de30d6 | 1115 | |
24192210 | 1116 | value = r8169_mdio_read(tp, reg); |
e6de30d6 | 1117 | |
1ef7286e | 1118 | r8168dp_2_mdio_stop(tp); |
e6de30d6 | 1119 | |
1120 | return value; | |
1121 | } | |
1122 | ||
4da19633 | 1123 | static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val) |
dacf8154 | 1124 | { |
24192210 | 1125 | tp->mdio_ops.write(tp, location, val); |
dacf8154 FR |
1126 | } |
1127 | ||
4da19633 | 1128 | static int rtl_readphy(struct rtl8169_private *tp, int location) |
1129 | { | |
24192210 | 1130 | return tp->mdio_ops.read(tp, location); |
4da19633 | 1131 | } |
1132 | ||
1133 | static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value) | |
1134 | { | |
1135 | rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value); | |
1136 | } | |
1137 | ||
76564428 | 1138 | static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m) |
daf9df6d | 1139 | { |
1140 | int val; | |
1141 | ||
4da19633 | 1142 | val = rtl_readphy(tp, reg_addr); |
76564428 | 1143 | rtl_writephy(tp, reg_addr, (val & ~m) | p); |
daf9df6d | 1144 | } |
1145 | ||
ccdffb9a FR |
1146 | static void rtl_mdio_write(struct net_device *dev, int phy_id, int location, |
1147 | int val) | |
1148 | { | |
1149 | struct rtl8169_private *tp = netdev_priv(dev); | |
ccdffb9a | 1150 | |
4da19633 | 1151 | rtl_writephy(tp, location, val); |
ccdffb9a FR |
1152 | } |
1153 | ||
1154 | static int rtl_mdio_read(struct net_device *dev, int phy_id, int location) | |
1155 | { | |
1156 | struct rtl8169_private *tp = netdev_priv(dev); | |
ccdffb9a | 1157 | |
4da19633 | 1158 | return rtl_readphy(tp, location); |
ccdffb9a FR |
1159 | } |
1160 | ||
ffc46952 FR |
1161 | DECLARE_RTL_COND(rtl_ephyar_cond) |
1162 | { | |
1ef7286e | 1163 | return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG; |
ffc46952 FR |
1164 | } |
1165 | ||
fdf6fc06 | 1166 | static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value) |
dacf8154 | 1167 | { |
1ef7286e | 1168 | RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | |
dacf8154 FR |
1169 | (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); |
1170 | ||
ffc46952 FR |
1171 | rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100); |
1172 | ||
1173 | udelay(10); | |
dacf8154 FR |
1174 | } |
1175 | ||
fdf6fc06 | 1176 | static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr) |
dacf8154 | 1177 | { |
1ef7286e | 1178 | RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); |
dacf8154 | 1179 | |
ffc46952 | 1180 | return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ? |
1ef7286e | 1181 | RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0; |
dacf8154 FR |
1182 | } |
1183 | ||
935e2218 CHL |
1184 | DECLARE_RTL_COND(rtl_eriar_cond) |
1185 | { | |
1ef7286e | 1186 | return RTL_R32(tp, ERIAR) & ERIAR_FLAG; |
935e2218 CHL |
1187 | } |
1188 | ||
fdf6fc06 FR |
1189 | static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, |
1190 | u32 val, int type) | |
133ac40a | 1191 | { |
133ac40a | 1192 | BUG_ON((addr & 3) || (mask == 0)); |
1ef7286e AS |
1193 | RTL_W32(tp, ERIDR, val); |
1194 | RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr); | |
133ac40a | 1195 | |
ffc46952 | 1196 | rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100); |
133ac40a HW |
1197 | } |
1198 | ||
fdf6fc06 | 1199 | static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type) |
133ac40a | 1200 | { |
1ef7286e | 1201 | RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr); |
133ac40a | 1202 | |
ffc46952 | 1203 | return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ? |
1ef7286e | 1204 | RTL_R32(tp, ERIDR) : ~0; |
133ac40a HW |
1205 | } |
1206 | ||
706123d0 | 1207 | static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p, |
fdf6fc06 | 1208 | u32 m, int type) |
133ac40a HW |
1209 | { |
1210 | u32 val; | |
1211 | ||
fdf6fc06 FR |
1212 | val = rtl_eri_read(tp, addr, type); |
1213 | rtl_eri_write(tp, addr, mask, (val & ~m) | p, type); | |
133ac40a HW |
1214 | } |
1215 | ||
935e2218 CHL |
1216 | static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg) |
1217 | { | |
1ef7286e | 1218 | RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); |
935e2218 | 1219 | return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ? |
1ef7286e | 1220 | RTL_R32(tp, OCPDR) : ~0; |
935e2218 CHL |
1221 | } |
1222 | ||
1223 | static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg) | |
1224 | { | |
1225 | return rtl_eri_read(tp, reg, ERIAR_OOB); | |
1226 | } | |
1227 | ||
1228 | static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg) | |
1229 | { | |
1230 | switch (tp->mac_version) { | |
1231 | case RTL_GIGA_MAC_VER_27: | |
1232 | case RTL_GIGA_MAC_VER_28: | |
1233 | case RTL_GIGA_MAC_VER_31: | |
1234 | return r8168dp_ocp_read(tp, mask, reg); | |
1235 | case RTL_GIGA_MAC_VER_49: | |
1236 | case RTL_GIGA_MAC_VER_50: | |
1237 | case RTL_GIGA_MAC_VER_51: | |
1238 | return r8168ep_ocp_read(tp, mask, reg); | |
1239 | default: | |
1240 | BUG(); | |
1241 | return ~0; | |
1242 | } | |
1243 | } | |
1244 | ||
1245 | static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, | |
1246 | u32 data) | |
1247 | { | |
1ef7286e AS |
1248 | RTL_W32(tp, OCPDR, data); |
1249 | RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); | |
935e2218 CHL |
1250 | rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20); |
1251 | } | |
1252 | ||
1253 | static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, | |
1254 | u32 data) | |
1255 | { | |
1256 | rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT, | |
1257 | data, ERIAR_OOB); | |
1258 | } | |
1259 | ||
1260 | static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data) | |
1261 | { | |
1262 | switch (tp->mac_version) { | |
1263 | case RTL_GIGA_MAC_VER_27: | |
1264 | case RTL_GIGA_MAC_VER_28: | |
1265 | case RTL_GIGA_MAC_VER_31: | |
1266 | r8168dp_ocp_write(tp, mask, reg, data); | |
1267 | break; | |
1268 | case RTL_GIGA_MAC_VER_49: | |
1269 | case RTL_GIGA_MAC_VER_50: | |
1270 | case RTL_GIGA_MAC_VER_51: | |
1271 | r8168ep_ocp_write(tp, mask, reg, data); | |
1272 | break; | |
1273 | default: | |
1274 | BUG(); | |
1275 | break; | |
1276 | } | |
1277 | } | |
1278 | ||
2a9b4d96 CHL |
1279 | static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd) |
1280 | { | |
1281 | rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC); | |
1282 | ||
1283 | ocp_write(tp, 0x1, 0x30, 0x00000001); | |
1284 | } | |
1285 | ||
1286 | #define OOB_CMD_RESET 0x00 | |
1287 | #define OOB_CMD_DRIVER_START 0x05 | |
1288 | #define OOB_CMD_DRIVER_STOP 0x06 | |
1289 | ||
1290 | static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp) | |
1291 | { | |
1292 | return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10; | |
1293 | } | |
1294 | ||
1295 | DECLARE_RTL_COND(rtl_ocp_read_cond) | |
1296 | { | |
1297 | u16 reg; | |
1298 | ||
1299 | reg = rtl8168_get_ocp_reg(tp); | |
1300 | ||
1301 | return ocp_read(tp, 0x0f, reg) & 0x00000800; | |
1302 | } | |
1303 | ||
935e2218 | 1304 | DECLARE_RTL_COND(rtl_ep_ocp_read_cond) |
2a9b4d96 | 1305 | { |
935e2218 CHL |
1306 | return ocp_read(tp, 0x0f, 0x124) & 0x00000001; |
1307 | } | |
1308 | ||
1309 | DECLARE_RTL_COND(rtl_ocp_tx_cond) | |
1310 | { | |
1ef7286e | 1311 | return RTL_R8(tp, IBISR0) & 0x20; |
935e2218 | 1312 | } |
2a9b4d96 | 1313 | |
003609da CHL |
1314 | static void rtl8168ep_stop_cmac(struct rtl8169_private *tp) |
1315 | { | |
1ef7286e | 1316 | RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01); |
086ca23d | 1317 | rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000); |
1ef7286e AS |
1318 | RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20); |
1319 | RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01); | |
003609da CHL |
1320 | } |
1321 | ||
935e2218 CHL |
1322 | static void rtl8168dp_driver_start(struct rtl8169_private *tp) |
1323 | { | |
1324 | rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START); | |
2a9b4d96 CHL |
1325 | rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10); |
1326 | } | |
1327 | ||
935e2218 | 1328 | static void rtl8168ep_driver_start(struct rtl8169_private *tp) |
2a9b4d96 | 1329 | { |
935e2218 CHL |
1330 | ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START); |
1331 | ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01); | |
1332 | rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10); | |
1333 | } | |
1334 | ||
1335 | static void rtl8168_driver_start(struct rtl8169_private *tp) | |
1336 | { | |
1337 | switch (tp->mac_version) { | |
1338 | case RTL_GIGA_MAC_VER_27: | |
1339 | case RTL_GIGA_MAC_VER_28: | |
1340 | case RTL_GIGA_MAC_VER_31: | |
1341 | rtl8168dp_driver_start(tp); | |
1342 | break; | |
1343 | case RTL_GIGA_MAC_VER_49: | |
1344 | case RTL_GIGA_MAC_VER_50: | |
1345 | case RTL_GIGA_MAC_VER_51: | |
1346 | rtl8168ep_driver_start(tp); | |
1347 | break; | |
1348 | default: | |
1349 | BUG(); | |
1350 | break; | |
1351 | } | |
1352 | } | |
2a9b4d96 | 1353 | |
935e2218 CHL |
1354 | static void rtl8168dp_driver_stop(struct rtl8169_private *tp) |
1355 | { | |
1356 | rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP); | |
2a9b4d96 CHL |
1357 | rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10); |
1358 | } | |
1359 | ||
935e2218 CHL |
1360 | static void rtl8168ep_driver_stop(struct rtl8169_private *tp) |
1361 | { | |
003609da | 1362 | rtl8168ep_stop_cmac(tp); |
935e2218 CHL |
1363 | ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP); |
1364 | ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01); | |
1365 | rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10); | |
1366 | } | |
1367 | ||
1368 | static void rtl8168_driver_stop(struct rtl8169_private *tp) | |
1369 | { | |
1370 | switch (tp->mac_version) { | |
1371 | case RTL_GIGA_MAC_VER_27: | |
1372 | case RTL_GIGA_MAC_VER_28: | |
1373 | case RTL_GIGA_MAC_VER_31: | |
1374 | rtl8168dp_driver_stop(tp); | |
1375 | break; | |
1376 | case RTL_GIGA_MAC_VER_49: | |
1377 | case RTL_GIGA_MAC_VER_50: | |
1378 | case RTL_GIGA_MAC_VER_51: | |
1379 | rtl8168ep_driver_stop(tp); | |
1380 | break; | |
1381 | default: | |
1382 | BUG(); | |
1383 | break; | |
1384 | } | |
1385 | } | |
1386 | ||
9dbe7896 | 1387 | static bool r8168dp_check_dash(struct rtl8169_private *tp) |
2a9b4d96 CHL |
1388 | { |
1389 | u16 reg = rtl8168_get_ocp_reg(tp); | |
1390 | ||
9dbe7896 | 1391 | return !!(ocp_read(tp, 0x0f, reg) & 0x00008000); |
2a9b4d96 CHL |
1392 | } |
1393 | ||
9dbe7896 | 1394 | static bool r8168ep_check_dash(struct rtl8169_private *tp) |
935e2218 | 1395 | { |
9dbe7896 | 1396 | return !!(ocp_read(tp, 0x0f, 0x128) & 0x00000001); |
935e2218 CHL |
1397 | } |
1398 | ||
9dbe7896 | 1399 | static bool r8168_check_dash(struct rtl8169_private *tp) |
935e2218 CHL |
1400 | { |
1401 | switch (tp->mac_version) { | |
1402 | case RTL_GIGA_MAC_VER_27: | |
1403 | case RTL_GIGA_MAC_VER_28: | |
1404 | case RTL_GIGA_MAC_VER_31: | |
1405 | return r8168dp_check_dash(tp); | |
1406 | case RTL_GIGA_MAC_VER_49: | |
1407 | case RTL_GIGA_MAC_VER_50: | |
1408 | case RTL_GIGA_MAC_VER_51: | |
1409 | return r8168ep_check_dash(tp); | |
1410 | default: | |
9dbe7896 | 1411 | return false; |
935e2218 CHL |
1412 | } |
1413 | } | |
1414 | ||
c28aa385 | 1415 | struct exgmac_reg { |
1416 | u16 addr; | |
1417 | u16 mask; | |
1418 | u32 val; | |
1419 | }; | |
1420 | ||
fdf6fc06 | 1421 | static void rtl_write_exgmac_batch(struct rtl8169_private *tp, |
c28aa385 | 1422 | const struct exgmac_reg *r, int len) |
1423 | { | |
1424 | while (len-- > 0) { | |
fdf6fc06 | 1425 | rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC); |
c28aa385 | 1426 | r++; |
1427 | } | |
1428 | } | |
1429 | ||
ffc46952 FR |
1430 | DECLARE_RTL_COND(rtl_efusear_cond) |
1431 | { | |
1ef7286e | 1432 | return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG; |
ffc46952 FR |
1433 | } |
1434 | ||
fdf6fc06 | 1435 | static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr) |
daf9df6d | 1436 | { |
1ef7286e | 1437 | RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); |
daf9df6d | 1438 | |
ffc46952 | 1439 | return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ? |
1ef7286e | 1440 | RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0; |
daf9df6d | 1441 | } |
1442 | ||
9085cdfa FR |
1443 | static u16 rtl_get_events(struct rtl8169_private *tp) |
1444 | { | |
1ef7286e | 1445 | return RTL_R16(tp, IntrStatus); |
9085cdfa FR |
1446 | } |
1447 | ||
1448 | static void rtl_ack_events(struct rtl8169_private *tp, u16 bits) | |
1449 | { | |
1ef7286e | 1450 | RTL_W16(tp, IntrStatus, bits); |
9085cdfa FR |
1451 | mmiowb(); |
1452 | } | |
1453 | ||
1454 | static void rtl_irq_disable(struct rtl8169_private *tp) | |
1455 | { | |
1ef7286e | 1456 | RTL_W16(tp, IntrMask, 0); |
9085cdfa FR |
1457 | mmiowb(); |
1458 | } | |
1459 | ||
3e990ff5 FR |
1460 | static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits) |
1461 | { | |
1ef7286e | 1462 | RTL_W16(tp, IntrMask, bits); |
3e990ff5 FR |
1463 | } |
1464 | ||
da78dbff FR |
1465 | #define RTL_EVENT_NAPI_RX (RxOK | RxErr) |
1466 | #define RTL_EVENT_NAPI_TX (TxOK | TxErr) | |
1467 | #define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX) | |
1468 | ||
1469 | static void rtl_irq_enable_all(struct rtl8169_private *tp) | |
1470 | { | |
1471 | rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow); | |
1472 | } | |
1473 | ||
811fd301 | 1474 | static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp) |
1da177e4 | 1475 | { |
9085cdfa | 1476 | rtl_irq_disable(tp); |
da78dbff | 1477 | rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow); |
1ef7286e | 1478 | RTL_R8(tp, ChipCmd); |
1da177e4 LT |
1479 | } |
1480 | ||
4da19633 | 1481 | static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp) |
1da177e4 | 1482 | { |
1ef7286e | 1483 | return RTL_R32(tp, TBICSR) & TBIReset; |
1da177e4 LT |
1484 | } |
1485 | ||
4da19633 | 1486 | static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp) |
1da177e4 | 1487 | { |
4da19633 | 1488 | return rtl_readphy(tp, MII_BMCR) & BMCR_RESET; |
1da177e4 LT |
1489 | } |
1490 | ||
1ef7286e | 1491 | static unsigned int rtl8169_tbi_link_ok(struct rtl8169_private *tp) |
1da177e4 | 1492 | { |
1ef7286e | 1493 | return RTL_R32(tp, TBICSR) & TBILinkOk; |
1da177e4 LT |
1494 | } |
1495 | ||
1ef7286e | 1496 | static unsigned int rtl8169_xmii_link_ok(struct rtl8169_private *tp) |
1da177e4 | 1497 | { |
1ef7286e | 1498 | return RTL_R8(tp, PHYstatus) & LinkStatus; |
1da177e4 LT |
1499 | } |
1500 | ||
4da19633 | 1501 | static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp) |
1da177e4 | 1502 | { |
1ef7286e | 1503 | RTL_W32(tp, TBICSR, RTL_R32(tp, TBICSR) | TBIReset); |
1da177e4 LT |
1504 | } |
1505 | ||
4da19633 | 1506 | static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp) |
1da177e4 LT |
1507 | { |
1508 | unsigned int val; | |
1509 | ||
4da19633 | 1510 | val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET; |
1511 | rtl_writephy(tp, MII_BMCR, val & 0xffff); | |
1da177e4 LT |
1512 | } |
1513 | ||
70090424 HW |
1514 | static void rtl_link_chg_patch(struct rtl8169_private *tp) |
1515 | { | |
70090424 HW |
1516 | struct net_device *dev = tp->dev; |
1517 | ||
1518 | if (!netif_running(dev)) | |
1519 | return; | |
1520 | ||
b3d7b2f2 HW |
1521 | if (tp->mac_version == RTL_GIGA_MAC_VER_34 || |
1522 | tp->mac_version == RTL_GIGA_MAC_VER_38) { | |
1ef7286e | 1523 | if (RTL_R8(tp, PHYstatus) & _1000bpsF) { |
fdf6fc06 FR |
1524 | rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011, |
1525 | ERIAR_EXGMAC); | |
1526 | rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005, | |
1527 | ERIAR_EXGMAC); | |
1ef7286e | 1528 | } else if (RTL_R8(tp, PHYstatus) & _100bps) { |
fdf6fc06 FR |
1529 | rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f, |
1530 | ERIAR_EXGMAC); | |
1531 | rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005, | |
1532 | ERIAR_EXGMAC); | |
70090424 | 1533 | } else { |
fdf6fc06 FR |
1534 | rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f, |
1535 | ERIAR_EXGMAC); | |
1536 | rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f, | |
1537 | ERIAR_EXGMAC); | |
70090424 HW |
1538 | } |
1539 | /* Reset packet filter */ | |
706123d0 | 1540 | rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, |
70090424 | 1541 | ERIAR_EXGMAC); |
706123d0 | 1542 | rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, |
70090424 | 1543 | ERIAR_EXGMAC); |
c2218925 HW |
1544 | } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 || |
1545 | tp->mac_version == RTL_GIGA_MAC_VER_36) { | |
1ef7286e | 1546 | if (RTL_R8(tp, PHYstatus) & _1000bpsF) { |
fdf6fc06 FR |
1547 | rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011, |
1548 | ERIAR_EXGMAC); | |
1549 | rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005, | |
1550 | ERIAR_EXGMAC); | |
c2218925 | 1551 | } else { |
fdf6fc06 FR |
1552 | rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f, |
1553 | ERIAR_EXGMAC); | |
1554 | rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f, | |
1555 | ERIAR_EXGMAC); | |
c2218925 | 1556 | } |
7e18dca1 | 1557 | } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) { |
1ef7286e | 1558 | if (RTL_R8(tp, PHYstatus) & _10bps) { |
fdf6fc06 FR |
1559 | rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02, |
1560 | ERIAR_EXGMAC); | |
1561 | rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060, | |
1562 | ERIAR_EXGMAC); | |
7e18dca1 | 1563 | } else { |
fdf6fc06 FR |
1564 | rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, |
1565 | ERIAR_EXGMAC); | |
7e18dca1 | 1566 | } |
70090424 HW |
1567 | } |
1568 | } | |
1569 | ||
ef4d5fcc | 1570 | static void rtl8169_check_link_status(struct net_device *dev, |
1ef7286e | 1571 | struct rtl8169_private *tp) |
1da177e4 | 1572 | { |
1e1205b7 HK |
1573 | struct device *d = tp_to_dev(tp); |
1574 | ||
1ef7286e | 1575 | if (tp->link_ok(tp)) { |
70090424 | 1576 | rtl_link_chg_patch(tp); |
e1759441 | 1577 | /* This is to cancel a scheduled suspend if there's one. */ |
1e1205b7 | 1578 | pm_request_resume(d); |
1da177e4 | 1579 | netif_carrier_on(dev); |
1519e57f FR |
1580 | if (net_ratelimit()) |
1581 | netif_info(tp, ifup, dev, "link up\n"); | |
b57b7e5a | 1582 | } else { |
1da177e4 | 1583 | netif_carrier_off(dev); |
bf82c189 | 1584 | netif_info(tp, ifdown, dev, "link down\n"); |
1e1205b7 | 1585 | pm_runtime_idle(d); |
b57b7e5a | 1586 | } |
1da177e4 LT |
1587 | } |
1588 | ||
e1759441 RW |
1589 | #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) |
1590 | ||
1591 | static u32 __rtl8169_get_wol(struct rtl8169_private *tp) | |
61a4dcc2 | 1592 | { |
61a4dcc2 | 1593 | u8 options; |
e1759441 | 1594 | u32 wolopts = 0; |
61a4dcc2 | 1595 | |
1ef7286e | 1596 | options = RTL_R8(tp, Config1); |
61a4dcc2 | 1597 | if (!(options & PMEnable)) |
e1759441 | 1598 | return 0; |
61a4dcc2 | 1599 | |
1ef7286e | 1600 | options = RTL_R8(tp, Config3); |
61a4dcc2 | 1601 | if (options & LinkUp) |
e1759441 | 1602 | wolopts |= WAKE_PHY; |
6e1d0b89 | 1603 | switch (tp->mac_version) { |
2a71883c HK |
1604 | case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: |
1605 | case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51: | |
6e1d0b89 CHL |
1606 | if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2) |
1607 | wolopts |= WAKE_MAGIC; | |
1608 | break; | |
1609 | default: | |
1610 | if (options & MagicPacket) | |
1611 | wolopts |= WAKE_MAGIC; | |
1612 | break; | |
1613 | } | |
61a4dcc2 | 1614 | |
1ef7286e | 1615 | options = RTL_R8(tp, Config5); |
61a4dcc2 | 1616 | if (options & UWF) |
e1759441 | 1617 | wolopts |= WAKE_UCAST; |
61a4dcc2 | 1618 | if (options & BWF) |
e1759441 | 1619 | wolopts |= WAKE_BCAST; |
61a4dcc2 | 1620 | if (options & MWF) |
e1759441 | 1621 | wolopts |= WAKE_MCAST; |
61a4dcc2 | 1622 | |
e1759441 | 1623 | return wolopts; |
61a4dcc2 FR |
1624 | } |
1625 | ||
e1759441 | 1626 | static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
61a4dcc2 FR |
1627 | { |
1628 | struct rtl8169_private *tp = netdev_priv(dev); | |
1e1205b7 | 1629 | struct device *d = tp_to_dev(tp); |
5fa80a32 CHL |
1630 | |
1631 | pm_runtime_get_noresume(d); | |
e1759441 | 1632 | |
da78dbff | 1633 | rtl_lock_work(tp); |
e1759441 RW |
1634 | |
1635 | wol->supported = WAKE_ANY; | |
5fa80a32 CHL |
1636 | if (pm_runtime_active(d)) |
1637 | wol->wolopts = __rtl8169_get_wol(tp); | |
1638 | else | |
1639 | wol->wolopts = tp->saved_wolopts; | |
e1759441 | 1640 | |
da78dbff | 1641 | rtl_unlock_work(tp); |
5fa80a32 CHL |
1642 | |
1643 | pm_runtime_put_noidle(d); | |
e1759441 RW |
1644 | } |
1645 | ||
1646 | static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) | |
1647 | { | |
6e1d0b89 | 1648 | unsigned int i, tmp; |
350f7596 | 1649 | static const struct { |
61a4dcc2 FR |
1650 | u32 opt; |
1651 | u16 reg; | |
1652 | u8 mask; | |
1653 | } cfg[] = { | |
61a4dcc2 | 1654 | { WAKE_PHY, Config3, LinkUp }, |
61a4dcc2 FR |
1655 | { WAKE_UCAST, Config5, UWF }, |
1656 | { WAKE_BCAST, Config5, BWF }, | |
1657 | { WAKE_MCAST, Config5, MWF }, | |
6e1d0b89 CHL |
1658 | { WAKE_ANY, Config5, LanWake }, |
1659 | { WAKE_MAGIC, Config3, MagicPacket } | |
61a4dcc2 | 1660 | }; |
851e6022 | 1661 | u8 options; |
61a4dcc2 | 1662 | |
1ef7286e | 1663 | RTL_W8(tp, Cfg9346, Cfg9346_Unlock); |
61a4dcc2 | 1664 | |
6e1d0b89 | 1665 | switch (tp->mac_version) { |
2a71883c HK |
1666 | case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: |
1667 | case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51: | |
6e1d0b89 CHL |
1668 | tmp = ARRAY_SIZE(cfg) - 1; |
1669 | if (wolopts & WAKE_MAGIC) | |
706123d0 | 1670 | rtl_w0w1_eri(tp, |
6e1d0b89 CHL |
1671 | 0x0dc, |
1672 | ERIAR_MASK_0100, | |
1673 | MagicPacket_v2, | |
1674 | 0x0000, | |
1675 | ERIAR_EXGMAC); | |
1676 | else | |
706123d0 | 1677 | rtl_w0w1_eri(tp, |
6e1d0b89 CHL |
1678 | 0x0dc, |
1679 | ERIAR_MASK_0100, | |
1680 | 0x0000, | |
1681 | MagicPacket_v2, | |
1682 | ERIAR_EXGMAC); | |
1683 | break; | |
1684 | default: | |
1685 | tmp = ARRAY_SIZE(cfg); | |
1686 | break; | |
1687 | } | |
1688 | ||
1689 | for (i = 0; i < tmp; i++) { | |
1ef7286e | 1690 | options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask; |
e1759441 | 1691 | if (wolopts & cfg[i].opt) |
61a4dcc2 | 1692 | options |= cfg[i].mask; |
1ef7286e | 1693 | RTL_W8(tp, cfg[i].reg, options); |
61a4dcc2 FR |
1694 | } |
1695 | ||
851e6022 FR |
1696 | switch (tp->mac_version) { |
1697 | case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17: | |
1ef7286e | 1698 | options = RTL_R8(tp, Config1) & ~PMEnable; |
851e6022 FR |
1699 | if (wolopts) |
1700 | options |= PMEnable; | |
1ef7286e | 1701 | RTL_W8(tp, Config1, options); |
851e6022 FR |
1702 | break; |
1703 | default: | |
1ef7286e | 1704 | options = RTL_R8(tp, Config2) & ~PME_SIGNAL; |
d387b427 FR |
1705 | if (wolopts) |
1706 | options |= PME_SIGNAL; | |
1ef7286e | 1707 | RTL_W8(tp, Config2, options); |
851e6022 FR |
1708 | break; |
1709 | } | |
1710 | ||
1ef7286e | 1711 | RTL_W8(tp, Cfg9346, Cfg9346_Lock); |
e1759441 RW |
1712 | } |
1713 | ||
1714 | static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
1715 | { | |
1716 | struct rtl8169_private *tp = netdev_priv(dev); | |
1e1205b7 | 1717 | struct device *d = tp_to_dev(tp); |
5fa80a32 CHL |
1718 | |
1719 | pm_runtime_get_noresume(d); | |
e1759441 | 1720 | |
da78dbff | 1721 | rtl_lock_work(tp); |
61a4dcc2 | 1722 | |
5fa80a32 CHL |
1723 | if (pm_runtime_active(d)) |
1724 | __rtl8169_set_wol(tp, wol->wolopts); | |
1725 | else | |
1726 | tp->saved_wolopts = wol->wolopts; | |
da78dbff FR |
1727 | |
1728 | rtl_unlock_work(tp); | |
61a4dcc2 | 1729 | |
1e1205b7 | 1730 | device_set_wakeup_enable(d, wol->wolopts); |
ea80907f | 1731 | |
5fa80a32 CHL |
1732 | pm_runtime_put_noidle(d); |
1733 | ||
61a4dcc2 FR |
1734 | return 0; |
1735 | } | |
1736 | ||
31bd204f FR |
1737 | static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp) |
1738 | { | |
85bffe6c | 1739 | return rtl_chip_infos[tp->mac_version].fw_name; |
31bd204f FR |
1740 | } |
1741 | ||
1da177e4 LT |
1742 | static void rtl8169_get_drvinfo(struct net_device *dev, |
1743 | struct ethtool_drvinfo *info) | |
1744 | { | |
1745 | struct rtl8169_private *tp = netdev_priv(dev); | |
b6ffd97f | 1746 | struct rtl_fw *rtl_fw = tp->rtl_fw; |
1da177e4 | 1747 | |
68aad78c RJ |
1748 | strlcpy(info->driver, MODULENAME, sizeof(info->driver)); |
1749 | strlcpy(info->version, RTL8169_VERSION, sizeof(info->version)); | |
1750 | strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info)); | |
1c361efb | 1751 | BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version)); |
8ac72d16 RJ |
1752 | if (!IS_ERR_OR_NULL(rtl_fw)) |
1753 | strlcpy(info->fw_version, rtl_fw->version, | |
1754 | sizeof(info->fw_version)); | |
1da177e4 LT |
1755 | } |
1756 | ||
1757 | static int rtl8169_get_regs_len(struct net_device *dev) | |
1758 | { | |
1759 | return R8169_REGS_SIZE; | |
1760 | } | |
1761 | ||
1762 | static int rtl8169_set_speed_tbi(struct net_device *dev, | |
54405cde | 1763 | u8 autoneg, u16 speed, u8 duplex, u32 ignored) |
1da177e4 LT |
1764 | { |
1765 | struct rtl8169_private *tp = netdev_priv(dev); | |
1da177e4 LT |
1766 | int ret = 0; |
1767 | u32 reg; | |
1768 | ||
1ef7286e | 1769 | reg = RTL_R32(tp, TBICSR); |
1da177e4 LT |
1770 | if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) && |
1771 | (duplex == DUPLEX_FULL)) { | |
1ef7286e | 1772 | RTL_W32(tp, TBICSR, reg & ~(TBINwEnable | TBINwRestart)); |
1da177e4 | 1773 | } else if (autoneg == AUTONEG_ENABLE) |
1ef7286e | 1774 | RTL_W32(tp, TBICSR, reg | TBINwEnable | TBINwRestart); |
1da177e4 | 1775 | else { |
bf82c189 JP |
1776 | netif_warn(tp, link, dev, |
1777 | "incorrect speed setting refused in TBI mode\n"); | |
1da177e4 LT |
1778 | ret = -EOPNOTSUPP; |
1779 | } | |
1780 | ||
1781 | return ret; | |
1782 | } | |
1783 | ||
1784 | static int rtl8169_set_speed_xmii(struct net_device *dev, | |
54405cde | 1785 | u8 autoneg, u16 speed, u8 duplex, u32 adv) |
1da177e4 LT |
1786 | { |
1787 | struct rtl8169_private *tp = netdev_priv(dev); | |
3577aa1b | 1788 | int giga_ctrl, bmcr; |
54405cde | 1789 | int rc = -EINVAL; |
1da177e4 | 1790 | |
716b50a3 | 1791 | rtl_writephy(tp, 0x1f, 0x0000); |
1da177e4 LT |
1792 | |
1793 | if (autoneg == AUTONEG_ENABLE) { | |
3577aa1b | 1794 | int auto_nego; |
1795 | ||
4da19633 | 1796 | auto_nego = rtl_readphy(tp, MII_ADVERTISE); |
54405cde ON |
1797 | auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | |
1798 | ADVERTISE_100HALF | ADVERTISE_100FULL); | |
1799 | ||
1800 | if (adv & ADVERTISED_10baseT_Half) | |
1801 | auto_nego |= ADVERTISE_10HALF; | |
1802 | if (adv & ADVERTISED_10baseT_Full) | |
1803 | auto_nego |= ADVERTISE_10FULL; | |
1804 | if (adv & ADVERTISED_100baseT_Half) | |
1805 | auto_nego |= ADVERTISE_100HALF; | |
1806 | if (adv & ADVERTISED_100baseT_Full) | |
1807 | auto_nego |= ADVERTISE_100FULL; | |
1808 | ||
3577aa1b | 1809 | auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; |
1da177e4 | 1810 | |
4da19633 | 1811 | giga_ctrl = rtl_readphy(tp, MII_CTRL1000); |
3577aa1b | 1812 | giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); |
bcf0bf90 | 1813 | |
3577aa1b | 1814 | /* The 8100e/8101e/8102e do Fast Ethernet only. */ |
826e6cbd | 1815 | if (tp->mii.supports_gmii) { |
54405cde ON |
1816 | if (adv & ADVERTISED_1000baseT_Half) |
1817 | giga_ctrl |= ADVERTISE_1000HALF; | |
1818 | if (adv & ADVERTISED_1000baseT_Full) | |
1819 | giga_ctrl |= ADVERTISE_1000FULL; | |
1820 | } else if (adv & (ADVERTISED_1000baseT_Half | | |
1821 | ADVERTISED_1000baseT_Full)) { | |
bf82c189 JP |
1822 | netif_info(tp, link, dev, |
1823 | "PHY does not support 1000Mbps\n"); | |
54405cde | 1824 | goto out; |
bcf0bf90 | 1825 | } |
1da177e4 | 1826 | |
3577aa1b | 1827 | bmcr = BMCR_ANENABLE | BMCR_ANRESTART; |
1828 | ||
4da19633 | 1829 | rtl_writephy(tp, MII_ADVERTISE, auto_nego); |
1830 | rtl_writephy(tp, MII_CTRL1000, giga_ctrl); | |
3577aa1b | 1831 | } else { |
3577aa1b | 1832 | if (speed == SPEED_10) |
1833 | bmcr = 0; | |
1834 | else if (speed == SPEED_100) | |
1835 | bmcr = BMCR_SPEED100; | |
1836 | else | |
54405cde | 1837 | goto out; |
3577aa1b | 1838 | |
1839 | if (duplex == DUPLEX_FULL) | |
1840 | bmcr |= BMCR_FULLDPLX; | |
2584fbc3 RS |
1841 | } |
1842 | ||
4da19633 | 1843 | rtl_writephy(tp, MII_BMCR, bmcr); |
3577aa1b | 1844 | |
cecb5fd7 FR |
1845 | if (tp->mac_version == RTL_GIGA_MAC_VER_02 || |
1846 | tp->mac_version == RTL_GIGA_MAC_VER_03) { | |
3577aa1b | 1847 | if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) { |
4da19633 | 1848 | rtl_writephy(tp, 0x17, 0x2138); |
1849 | rtl_writephy(tp, 0x0e, 0x0260); | |
3577aa1b | 1850 | } else { |
4da19633 | 1851 | rtl_writephy(tp, 0x17, 0x2108); |
1852 | rtl_writephy(tp, 0x0e, 0x0000); | |
3577aa1b | 1853 | } |
1854 | } | |
1855 | ||
54405cde ON |
1856 | rc = 0; |
1857 | out: | |
1858 | return rc; | |
1da177e4 LT |
1859 | } |
1860 | ||
1861 | static int rtl8169_set_speed(struct net_device *dev, | |
54405cde | 1862 | u8 autoneg, u16 speed, u8 duplex, u32 advertising) |
1da177e4 LT |
1863 | { |
1864 | struct rtl8169_private *tp = netdev_priv(dev); | |
1865 | int ret; | |
1866 | ||
54405cde | 1867 | ret = tp->set_speed(dev, autoneg, speed, duplex, advertising); |
4876cc1e FR |
1868 | if (ret < 0) |
1869 | goto out; | |
1da177e4 | 1870 | |
4876cc1e | 1871 | if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) && |
c4556975 CHL |
1872 | (advertising & ADVERTISED_1000baseT_Full) && |
1873 | !pci_is_pcie(tp->pci_dev)) { | |
1da177e4 | 1874 | mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT); |
4876cc1e FR |
1875 | } |
1876 | out: | |
1da177e4 LT |
1877 | return ret; |
1878 | } | |
1879 | ||
c8f44aff MM |
1880 | static netdev_features_t rtl8169_fix_features(struct net_device *dev, |
1881 | netdev_features_t features) | |
1da177e4 | 1882 | { |
d58d46b5 FR |
1883 | struct rtl8169_private *tp = netdev_priv(dev); |
1884 | ||
2b7b4318 | 1885 | if (dev->mtu > TD_MSS_MAX) |
350fb32a | 1886 | features &= ~NETIF_F_ALL_TSO; |
1da177e4 | 1887 | |
d58d46b5 | 1888 | if (dev->mtu > JUMBO_1K && |
6ed0e08f | 1889 | tp->mac_version > RTL_GIGA_MAC_VER_06) |
d58d46b5 FR |
1890 | features &= ~NETIF_F_IP_CSUM; |
1891 | ||
350fb32a | 1892 | return features; |
1da177e4 LT |
1893 | } |
1894 | ||
a3984578 HK |
1895 | static int rtl8169_set_features(struct net_device *dev, |
1896 | netdev_features_t features) | |
1da177e4 LT |
1897 | { |
1898 | struct rtl8169_private *tp = netdev_priv(dev); | |
929a031d | 1899 | u32 rx_config; |
1da177e4 | 1900 | |
a3984578 HK |
1901 | rtl_lock_work(tp); |
1902 | ||
1ef7286e | 1903 | rx_config = RTL_R32(tp, RxConfig); |
929a031d | 1904 | if (features & NETIF_F_RXALL) |
1905 | rx_config |= (AcceptErr | AcceptRunt); | |
1906 | else | |
1907 | rx_config &= ~(AcceptErr | AcceptRunt); | |
1da177e4 | 1908 | |
1ef7286e | 1909 | RTL_W32(tp, RxConfig, rx_config); |
350fb32a | 1910 | |
929a031d | 1911 | if (features & NETIF_F_RXCSUM) |
1912 | tp->cp_cmd |= RxChkSum; | |
1913 | else | |
1914 | tp->cp_cmd &= ~RxChkSum; | |
6bbe021d | 1915 | |
929a031d | 1916 | if (features & NETIF_F_HW_VLAN_CTAG_RX) |
1917 | tp->cp_cmd |= RxVlan; | |
1918 | else | |
1919 | tp->cp_cmd &= ~RxVlan; | |
1920 | ||
1ef7286e AS |
1921 | RTL_W16(tp, CPlusCmd, tp->cp_cmd); |
1922 | RTL_R16(tp, CPlusCmd); | |
1da177e4 | 1923 | |
da78dbff | 1924 | rtl_unlock_work(tp); |
1da177e4 LT |
1925 | |
1926 | return 0; | |
1927 | } | |
1928 | ||
810f4893 | 1929 | static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb) |
1da177e4 | 1930 | { |
df8a39de JP |
1931 | return (skb_vlan_tag_present(skb)) ? |
1932 | TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00; | |
1da177e4 LT |
1933 | } |
1934 | ||
7a8fc77b | 1935 | static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb) |
1da177e4 LT |
1936 | { |
1937 | u32 opts2 = le32_to_cpu(desc->opts2); | |
1da177e4 | 1938 | |
7a8fc77b | 1939 | if (opts2 & RxVlanTag) |
86a9bad3 | 1940 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff)); |
1da177e4 LT |
1941 | } |
1942 | ||
6fa1ba61 PR |
1943 | static int rtl8169_get_link_ksettings_tbi(struct net_device *dev, |
1944 | struct ethtool_link_ksettings *cmd) | |
1da177e4 LT |
1945 | { |
1946 | struct rtl8169_private *tp = netdev_priv(dev); | |
1da177e4 | 1947 | u32 status; |
6fa1ba61 | 1948 | u32 supported, advertising; |
1da177e4 | 1949 | |
6fa1ba61 | 1950 | supported = |
1da177e4 | 1951 | SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE; |
6fa1ba61 | 1952 | cmd->base.port = PORT_FIBRE; |
1da177e4 | 1953 | |
1ef7286e | 1954 | status = RTL_R32(tp, TBICSR); |
6fa1ba61 PR |
1955 | advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0; |
1956 | cmd->base.autoneg = !!(status & TBINwEnable); | |
1da177e4 | 1957 | |
6fa1ba61 PR |
1958 | cmd->base.speed = SPEED_1000; |
1959 | cmd->base.duplex = DUPLEX_FULL; /* Always set */ | |
1960 | ||
1961 | ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, | |
1962 | supported); | |
1963 | ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, | |
1964 | advertising); | |
ccdffb9a FR |
1965 | |
1966 | return 0; | |
1da177e4 LT |
1967 | } |
1968 | ||
6fa1ba61 PR |
1969 | static int rtl8169_get_link_ksettings_xmii(struct net_device *dev, |
1970 | struct ethtool_link_ksettings *cmd) | |
1da177e4 LT |
1971 | { |
1972 | struct rtl8169_private *tp = netdev_priv(dev); | |
ccdffb9a | 1973 | |
82c01a84 | 1974 | mii_ethtool_get_link_ksettings(&tp->mii, cmd); |
1975 | ||
1976 | return 0; | |
1da177e4 LT |
1977 | } |
1978 | ||
6fa1ba61 PR |
1979 | static int rtl8169_get_link_ksettings(struct net_device *dev, |
1980 | struct ethtool_link_ksettings *cmd) | |
1da177e4 LT |
1981 | { |
1982 | struct rtl8169_private *tp = netdev_priv(dev); | |
ccdffb9a | 1983 | int rc; |
1da177e4 | 1984 | |
da78dbff | 1985 | rtl_lock_work(tp); |
6fa1ba61 | 1986 | rc = tp->get_link_ksettings(dev, cmd); |
da78dbff | 1987 | rtl_unlock_work(tp); |
1da177e4 | 1988 | |
ccdffb9a | 1989 | return rc; |
1da177e4 LT |
1990 | } |
1991 | ||
9e77d7a5 TJ |
1992 | static int rtl8169_set_link_ksettings(struct net_device *dev, |
1993 | const struct ethtool_link_ksettings *cmd) | |
1994 | { | |
1995 | struct rtl8169_private *tp = netdev_priv(dev); | |
1996 | int rc; | |
1997 | u32 advertising; | |
1998 | ||
1999 | if (!ethtool_convert_link_mode_to_legacy_u32(&advertising, | |
2000 | cmd->link_modes.advertising)) | |
2001 | return -EINVAL; | |
2002 | ||
2003 | del_timer_sync(&tp->timer); | |
2004 | ||
2005 | rtl_lock_work(tp); | |
2006 | rc = rtl8169_set_speed(dev, cmd->base.autoneg, cmd->base.speed, | |
2007 | cmd->base.duplex, advertising); | |
2008 | rtl_unlock_work(tp); | |
2009 | ||
2010 | return rc; | |
2011 | } | |
2012 | ||
1da177e4 LT |
2013 | static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, |
2014 | void *p) | |
2015 | { | |
5b0384f4 | 2016 | struct rtl8169_private *tp = netdev_priv(dev); |
15edae91 PW |
2017 | u32 __iomem *data = tp->mmio_addr; |
2018 | u32 *dw = p; | |
2019 | int i; | |
1da177e4 | 2020 | |
da78dbff | 2021 | rtl_lock_work(tp); |
15edae91 PW |
2022 | for (i = 0; i < R8169_REGS_SIZE; i += 4) |
2023 | memcpy_fromio(dw++, data++, 4); | |
da78dbff | 2024 | rtl_unlock_work(tp); |
1da177e4 LT |
2025 | } |
2026 | ||
b57b7e5a SH |
2027 | static u32 rtl8169_get_msglevel(struct net_device *dev) |
2028 | { | |
2029 | struct rtl8169_private *tp = netdev_priv(dev); | |
2030 | ||
2031 | return tp->msg_enable; | |
2032 | } | |
2033 | ||
2034 | static void rtl8169_set_msglevel(struct net_device *dev, u32 value) | |
2035 | { | |
2036 | struct rtl8169_private *tp = netdev_priv(dev); | |
2037 | ||
2038 | tp->msg_enable = value; | |
2039 | } | |
2040 | ||
d4a3a0fc SH |
2041 | static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { |
2042 | "tx_packets", | |
2043 | "rx_packets", | |
2044 | "tx_errors", | |
2045 | "rx_errors", | |
2046 | "rx_missed", | |
2047 | "align_errors", | |
2048 | "tx_single_collisions", | |
2049 | "tx_multi_collisions", | |
2050 | "unicast", | |
2051 | "broadcast", | |
2052 | "multicast", | |
2053 | "tx_aborted", | |
2054 | "tx_underrun", | |
2055 | }; | |
2056 | ||
b9f2c044 | 2057 | static int rtl8169_get_sset_count(struct net_device *dev, int sset) |
d4a3a0fc | 2058 | { |
b9f2c044 JG |
2059 | switch (sset) { |
2060 | case ETH_SS_STATS: | |
2061 | return ARRAY_SIZE(rtl8169_gstrings); | |
2062 | default: | |
2063 | return -EOPNOTSUPP; | |
2064 | } | |
d4a3a0fc SH |
2065 | } |
2066 | ||
42020320 | 2067 | DECLARE_RTL_COND(rtl_counters_cond) |
6e85d5ad | 2068 | { |
1ef7286e | 2069 | return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump); |
6e85d5ad CV |
2070 | } |
2071 | ||
e71c9ce2 | 2072 | static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd) |
6e85d5ad | 2073 | { |
42020320 CV |
2074 | dma_addr_t paddr = tp->counters_phys_addr; |
2075 | u32 cmd; | |
6e85d5ad | 2076 | |
1ef7286e AS |
2077 | RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32); |
2078 | RTL_R32(tp, CounterAddrHigh); | |
42020320 | 2079 | cmd = (u64)paddr & DMA_BIT_MASK(32); |
1ef7286e AS |
2080 | RTL_W32(tp, CounterAddrLow, cmd); |
2081 | RTL_W32(tp, CounterAddrLow, cmd | counter_cmd); | |
6e85d5ad | 2082 | |
a78e9366 | 2083 | return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000); |
6e85d5ad CV |
2084 | } |
2085 | ||
e71c9ce2 | 2086 | static bool rtl8169_reset_counters(struct rtl8169_private *tp) |
6e85d5ad | 2087 | { |
6e85d5ad CV |
2088 | /* |
2089 | * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the | |
2090 | * tally counters. | |
2091 | */ | |
2092 | if (tp->mac_version < RTL_GIGA_MAC_VER_19) | |
2093 | return true; | |
2094 | ||
e71c9ce2 | 2095 | return rtl8169_do_counters(tp, CounterReset); |
ffc46952 FR |
2096 | } |
2097 | ||
e71c9ce2 | 2098 | static bool rtl8169_update_counters(struct rtl8169_private *tp) |
d4a3a0fc | 2099 | { |
355423d0 IV |
2100 | /* |
2101 | * Some chips are unable to dump tally counters when the receiver | |
2102 | * is disabled. | |
2103 | */ | |
1ef7286e | 2104 | if ((RTL_R8(tp, ChipCmd) & CmdRxEnb) == 0) |
6e85d5ad | 2105 | return true; |
d4a3a0fc | 2106 | |
e71c9ce2 | 2107 | return rtl8169_do_counters(tp, CounterDump); |
6e85d5ad CV |
2108 | } |
2109 | ||
e71c9ce2 | 2110 | static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp) |
6e85d5ad | 2111 | { |
42020320 | 2112 | struct rtl8169_counters *counters = tp->counters; |
6e85d5ad CV |
2113 | bool ret = false; |
2114 | ||
2115 | /* | |
2116 | * rtl8169_init_counter_offsets is called from rtl_open. On chip | |
2117 | * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only | |
2118 | * reset by a power cycle, while the counter values collected by the | |
2119 | * driver are reset at every driver unload/load cycle. | |
2120 | * | |
2121 | * To make sure the HW values returned by @get_stats64 match the SW | |
2122 | * values, we collect the initial values at first open(*) and use them | |
2123 | * as offsets to normalize the values returned by @get_stats64. | |
2124 | * | |
2125 | * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one | |
2126 | * for the reason stated in rtl8169_update_counters; CmdRxEnb is only | |
2127 | * set at open time by rtl_hw_start. | |
2128 | */ | |
2129 | ||
2130 | if (tp->tc_offset.inited) | |
2131 | return true; | |
2132 | ||
2133 | /* If both, reset and update fail, propagate to caller. */ | |
e71c9ce2 | 2134 | if (rtl8169_reset_counters(tp)) |
6e85d5ad CV |
2135 | ret = true; |
2136 | ||
e71c9ce2 | 2137 | if (rtl8169_update_counters(tp)) |
6e85d5ad CV |
2138 | ret = true; |
2139 | ||
42020320 CV |
2140 | tp->tc_offset.tx_errors = counters->tx_errors; |
2141 | tp->tc_offset.tx_multi_collision = counters->tx_multi_collision; | |
2142 | tp->tc_offset.tx_aborted = counters->tx_aborted; | |
6e85d5ad CV |
2143 | tp->tc_offset.inited = true; |
2144 | ||
2145 | return ret; | |
d4a3a0fc SH |
2146 | } |
2147 | ||
355423d0 IV |
2148 | static void rtl8169_get_ethtool_stats(struct net_device *dev, |
2149 | struct ethtool_stats *stats, u64 *data) | |
2150 | { | |
2151 | struct rtl8169_private *tp = netdev_priv(dev); | |
1e1205b7 | 2152 | struct device *d = tp_to_dev(tp); |
42020320 | 2153 | struct rtl8169_counters *counters = tp->counters; |
355423d0 IV |
2154 | |
2155 | ASSERT_RTNL(); | |
2156 | ||
e0636236 CHL |
2157 | pm_runtime_get_noresume(d); |
2158 | ||
2159 | if (pm_runtime_active(d)) | |
e71c9ce2 | 2160 | rtl8169_update_counters(tp); |
e0636236 CHL |
2161 | |
2162 | pm_runtime_put_noidle(d); | |
355423d0 | 2163 | |
42020320 CV |
2164 | data[0] = le64_to_cpu(counters->tx_packets); |
2165 | data[1] = le64_to_cpu(counters->rx_packets); | |
2166 | data[2] = le64_to_cpu(counters->tx_errors); | |
2167 | data[3] = le32_to_cpu(counters->rx_errors); | |
2168 | data[4] = le16_to_cpu(counters->rx_missed); | |
2169 | data[5] = le16_to_cpu(counters->align_errors); | |
2170 | data[6] = le32_to_cpu(counters->tx_one_collision); | |
2171 | data[7] = le32_to_cpu(counters->tx_multi_collision); | |
2172 | data[8] = le64_to_cpu(counters->rx_unicast); | |
2173 | data[9] = le64_to_cpu(counters->rx_broadcast); | |
2174 | data[10] = le32_to_cpu(counters->rx_multicast); | |
2175 | data[11] = le16_to_cpu(counters->tx_aborted); | |
2176 | data[12] = le16_to_cpu(counters->tx_underun); | |
355423d0 IV |
2177 | } |
2178 | ||
d4a3a0fc SH |
2179 | static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) |
2180 | { | |
2181 | switch(stringset) { | |
2182 | case ETH_SS_STATS: | |
2183 | memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings)); | |
2184 | break; | |
2185 | } | |
2186 | } | |
2187 | ||
f0903ea3 FF |
2188 | static int rtl8169_nway_reset(struct net_device *dev) |
2189 | { | |
2190 | struct rtl8169_private *tp = netdev_priv(dev); | |
2191 | ||
2192 | return mii_nway_restart(&tp->mii); | |
2193 | } | |
2194 | ||
50970831 FR |
2195 | /* |
2196 | * Interrupt coalescing | |
2197 | * | |
2198 | * > 1 - the availability of the IntrMitigate (0xe2) register through the | |
2199 | * > 8169, 8168 and 810x line of chipsets | |
2200 | * | |
2201 | * 8169, 8168, and 8136(810x) serial chipsets support it. | |
2202 | * | |
2203 | * > 2 - the Tx timer unit at gigabit speed | |
2204 | * | |
2205 | * The unit of the timer depends on both the speed and the setting of CPlusCmd | |
2206 | * (0xe0) bit 1 and bit 0. | |
2207 | * | |
2208 | * For 8169 | |
2209 | * bit[1:0] \ speed 1000M 100M 10M | |
2210 | * 0 0 320ns 2.56us 40.96us | |
2211 | * 0 1 2.56us 20.48us 327.7us | |
2212 | * 1 0 5.12us 40.96us 655.4us | |
2213 | * 1 1 10.24us 81.92us 1.31ms | |
2214 | * | |
2215 | * For the other | |
2216 | * bit[1:0] \ speed 1000M 100M 10M | |
2217 | * 0 0 5us 2.56us 40.96us | |
2218 | * 0 1 40us 20.48us 327.7us | |
2219 | * 1 0 80us 40.96us 655.4us | |
2220 | * 1 1 160us 81.92us 1.31ms | |
2221 | */ | |
2222 | ||
2223 | /* rx/tx scale factors for one particular CPlusCmd[0:1] value */ | |
2224 | struct rtl_coalesce_scale { | |
2225 | /* Rx / Tx */ | |
2226 | u32 nsecs[2]; | |
2227 | }; | |
2228 | ||
2229 | /* rx/tx scale factors for all CPlusCmd[0:1] cases */ | |
2230 | struct rtl_coalesce_info { | |
2231 | u32 speed; | |
2232 | struct rtl_coalesce_scale scalev[4]; /* each CPlusCmd[0:1] case */ | |
2233 | }; | |
2234 | ||
2235 | /* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */ | |
2236 | #define rxtx_x1822(r, t) { \ | |
2237 | {{(r), (t)}}, \ | |
2238 | {{(r)*8, (t)*8}}, \ | |
2239 | {{(r)*8*2, (t)*8*2}}, \ | |
2240 | {{(r)*8*2*2, (t)*8*2*2}}, \ | |
2241 | } | |
2242 | static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = { | |
2243 | /* speed delays: rx00 tx00 */ | |
2244 | { SPEED_10, rxtx_x1822(40960, 40960) }, | |
2245 | { SPEED_100, rxtx_x1822( 2560, 2560) }, | |
2246 | { SPEED_1000, rxtx_x1822( 320, 320) }, | |
2247 | { 0 }, | |
2248 | }; | |
2249 | ||
2250 | static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = { | |
2251 | /* speed delays: rx00 tx00 */ | |
2252 | { SPEED_10, rxtx_x1822(40960, 40960) }, | |
2253 | { SPEED_100, rxtx_x1822( 2560, 2560) }, | |
2254 | { SPEED_1000, rxtx_x1822( 5000, 5000) }, | |
2255 | { 0 }, | |
2256 | }; | |
2257 | #undef rxtx_x1822 | |
2258 | ||
2259 | /* get rx/tx scale vector corresponding to current speed */ | |
2260 | static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev) | |
2261 | { | |
2262 | struct rtl8169_private *tp = netdev_priv(dev); | |
2263 | struct ethtool_link_ksettings ecmd; | |
2264 | const struct rtl_coalesce_info *ci; | |
2265 | int rc; | |
2266 | ||
2267 | rc = rtl8169_get_link_ksettings(dev, &ecmd); | |
2268 | if (rc < 0) | |
2269 | return ERR_PTR(rc); | |
2270 | ||
2271 | for (ci = tp->coalesce_info; ci->speed != 0; ci++) { | |
2272 | if (ecmd.base.speed == ci->speed) { | |
2273 | return ci; | |
2274 | } | |
2275 | } | |
2276 | ||
2277 | return ERR_PTR(-ELNRNG); | |
2278 | } | |
2279 | ||
2280 | static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) | |
2281 | { | |
2282 | struct rtl8169_private *tp = netdev_priv(dev); | |
50970831 FR |
2283 | const struct rtl_coalesce_info *ci; |
2284 | const struct rtl_coalesce_scale *scale; | |
2285 | struct { | |
2286 | u32 *max_frames; | |
2287 | u32 *usecs; | |
2288 | } coal_settings [] = { | |
2289 | { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs }, | |
2290 | { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs } | |
2291 | }, *p = coal_settings; | |
2292 | int i; | |
2293 | u16 w; | |
2294 | ||
2295 | memset(ec, 0, sizeof(*ec)); | |
2296 | ||
2297 | /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */ | |
2298 | ci = rtl_coalesce_info(dev); | |
2299 | if (IS_ERR(ci)) | |
2300 | return PTR_ERR(ci); | |
2301 | ||
0ae0974e | 2302 | scale = &ci->scalev[tp->cp_cmd & INTT_MASK]; |
50970831 FR |
2303 | |
2304 | /* read IntrMitigate and adjust according to scale */ | |
1ef7286e | 2305 | for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) { |
50970831 FR |
2306 | *p->max_frames = (w & RTL_COALESCE_MASK) << 2; |
2307 | w >>= RTL_COALESCE_SHIFT; | |
2308 | *p->usecs = w & RTL_COALESCE_MASK; | |
2309 | } | |
2310 | ||
2311 | for (i = 0; i < 2; i++) { | |
2312 | p = coal_settings + i; | |
2313 | *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000; | |
2314 | ||
2315 | /* | |
2316 | * ethtool_coalesce says it is illegal to set both usecs and | |
2317 | * max_frames to 0. | |
2318 | */ | |
2319 | if (!*p->usecs && !*p->max_frames) | |
2320 | *p->max_frames = 1; | |
2321 | } | |
2322 | ||
2323 | return 0; | |
2324 | } | |
2325 | ||
2326 | /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */ | |
2327 | static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale( | |
2328 | struct net_device *dev, u32 nsec, u16 *cp01) | |
2329 | { | |
2330 | const struct rtl_coalesce_info *ci; | |
2331 | u16 i; | |
2332 | ||
2333 | ci = rtl_coalesce_info(dev); | |
2334 | if (IS_ERR(ci)) | |
2335 | return ERR_CAST(ci); | |
2336 | ||
2337 | for (i = 0; i < 4; i++) { | |
2338 | u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0], | |
2339 | ci->scalev[i].nsecs[1]); | |
2340 | if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) { | |
2341 | *cp01 = i; | |
2342 | return &ci->scalev[i]; | |
2343 | } | |
2344 | } | |
2345 | ||
2346 | return ERR_PTR(-EINVAL); | |
2347 | } | |
2348 | ||
2349 | static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) | |
2350 | { | |
2351 | struct rtl8169_private *tp = netdev_priv(dev); | |
50970831 FR |
2352 | const struct rtl_coalesce_scale *scale; |
2353 | struct { | |
2354 | u32 frames; | |
2355 | u32 usecs; | |
2356 | } coal_settings [] = { | |
2357 | { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs }, | |
2358 | { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs } | |
2359 | }, *p = coal_settings; | |
2360 | u16 w = 0, cp01; | |
2361 | int i; | |
2362 | ||
2363 | scale = rtl_coalesce_choose_scale(dev, | |
2364 | max(p[0].usecs, p[1].usecs) * 1000, &cp01); | |
2365 | if (IS_ERR(scale)) | |
2366 | return PTR_ERR(scale); | |
2367 | ||
2368 | for (i = 0; i < 2; i++, p++) { | |
2369 | u32 units; | |
2370 | ||
2371 | /* | |
2372 | * accept max_frames=1 we returned in rtl_get_coalesce. | |
2373 | * accept it not only when usecs=0 because of e.g. the following scenario: | |
2374 | * | |
2375 | * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX) | |
2376 | * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1 | |
2377 | * - then user does `ethtool -C eth0 rx-usecs 100` | |
2378 | * | |
2379 | * since ethtool sends to kernel whole ethtool_coalesce | |
2380 | * settings, if we do not handle rx_usecs=!0, rx_frames=1 | |
2381 | * we'll reject it below in `frames % 4 != 0`. | |
2382 | */ | |
2383 | if (p->frames == 1) { | |
2384 | p->frames = 0; | |
2385 | } | |
2386 | ||
2387 | units = p->usecs * 1000 / scale->nsecs[i]; | |
2388 | if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4) | |
2389 | return -EINVAL; | |
2390 | ||
2391 | w <<= RTL_COALESCE_SHIFT; | |
2392 | w |= units; | |
2393 | w <<= RTL_COALESCE_SHIFT; | |
2394 | w |= p->frames >> 2; | |
2395 | } | |
2396 | ||
2397 | rtl_lock_work(tp); | |
2398 | ||
1ef7286e | 2399 | RTL_W16(tp, IntrMitigate, swab16(w)); |
50970831 | 2400 | |
9a3c81fa | 2401 | tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01; |
1ef7286e AS |
2402 | RTL_W16(tp, CPlusCmd, tp->cp_cmd); |
2403 | RTL_R16(tp, CPlusCmd); | |
50970831 FR |
2404 | |
2405 | rtl_unlock_work(tp); | |
2406 | ||
2407 | return 0; | |
2408 | } | |
2409 | ||
7282d491 | 2410 | static const struct ethtool_ops rtl8169_ethtool_ops = { |
1da177e4 LT |
2411 | .get_drvinfo = rtl8169_get_drvinfo, |
2412 | .get_regs_len = rtl8169_get_regs_len, | |
2413 | .get_link = ethtool_op_get_link, | |
50970831 FR |
2414 | .get_coalesce = rtl_get_coalesce, |
2415 | .set_coalesce = rtl_set_coalesce, | |
b57b7e5a SH |
2416 | .get_msglevel = rtl8169_get_msglevel, |
2417 | .set_msglevel = rtl8169_set_msglevel, | |
1da177e4 | 2418 | .get_regs = rtl8169_get_regs, |
61a4dcc2 FR |
2419 | .get_wol = rtl8169_get_wol, |
2420 | .set_wol = rtl8169_set_wol, | |
d4a3a0fc | 2421 | .get_strings = rtl8169_get_strings, |
b9f2c044 | 2422 | .get_sset_count = rtl8169_get_sset_count, |
d4a3a0fc | 2423 | .get_ethtool_stats = rtl8169_get_ethtool_stats, |
e1593bb1 | 2424 | .get_ts_info = ethtool_op_get_ts_info, |
f0903ea3 | 2425 | .nway_reset = rtl8169_nway_reset, |
6fa1ba61 | 2426 | .get_link_ksettings = rtl8169_get_link_ksettings, |
9e77d7a5 | 2427 | .set_link_ksettings = rtl8169_set_link_ksettings, |
1da177e4 LT |
2428 | }; |
2429 | ||
07d3f51f | 2430 | static void rtl8169_get_mac_version(struct rtl8169_private *tp, |
22148df0 | 2431 | u8 default_version) |
1da177e4 | 2432 | { |
0e485150 FR |
2433 | /* |
2434 | * The driver currently handles the 8168Bf and the 8168Be identically | |
2435 | * but they can be identified more specifically through the test below | |
2436 | * if needed: | |
2437 | * | |
1ef7286e | 2438 | * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be |
0127215c FR |
2439 | * |
2440 | * Same thing for the 8101Eb and the 8101Ec: | |
2441 | * | |
1ef7286e | 2442 | * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec |
0e485150 | 2443 | */ |
3744100e | 2444 | static const struct rtl_mac_info { |
1da177e4 | 2445 | u32 mask; |
e3cf0cc0 | 2446 | u32 val; |
1da177e4 LT |
2447 | int mac_version; |
2448 | } mac_info[] = { | |
935e2218 CHL |
2449 | /* 8168EP family. */ |
2450 | { 0x7cf00000, 0x50200000, RTL_GIGA_MAC_VER_51 }, | |
2451 | { 0x7cf00000, 0x50100000, RTL_GIGA_MAC_VER_50 }, | |
2452 | { 0x7cf00000, 0x50000000, RTL_GIGA_MAC_VER_49 }, | |
2453 | ||
6e1d0b89 CHL |
2454 | /* 8168H family. */ |
2455 | { 0x7cf00000, 0x54100000, RTL_GIGA_MAC_VER_46 }, | |
2456 | { 0x7cf00000, 0x54000000, RTL_GIGA_MAC_VER_45 }, | |
2457 | ||
c558386b | 2458 | /* 8168G family. */ |
45dd95c4 | 2459 | { 0x7cf00000, 0x5c800000, RTL_GIGA_MAC_VER_44 }, |
57538c4a | 2460 | { 0x7cf00000, 0x50900000, RTL_GIGA_MAC_VER_42 }, |
c558386b HW |
2461 | { 0x7cf00000, 0x4c100000, RTL_GIGA_MAC_VER_41 }, |
2462 | { 0x7cf00000, 0x4c000000, RTL_GIGA_MAC_VER_40 }, | |
2463 | ||
c2218925 | 2464 | /* 8168F family. */ |
b3d7b2f2 | 2465 | { 0x7c800000, 0x48800000, RTL_GIGA_MAC_VER_38 }, |
c2218925 HW |
2466 | { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 }, |
2467 | { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 }, | |
2468 | ||
01dc7fec | 2469 | /* 8168E family. */ |
70090424 | 2470 | { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 }, |
01dc7fec | 2471 | { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 }, |
2472 | { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 }, | |
2473 | ||
5b538df9 | 2474 | /* 8168D family. */ |
daf9df6d | 2475 | { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 }, |
daf9df6d | 2476 | { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 }, |
5b538df9 | 2477 | |
e6de30d6 | 2478 | /* 8168DP family. */ |
2479 | { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 }, | |
2480 | { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 }, | |
4804b3b3 | 2481 | { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 }, |
e6de30d6 | 2482 | |
ef808d50 | 2483 | /* 8168C family. */ |
ef3386f0 | 2484 | { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 }, |
ef808d50 | 2485 | { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 }, |
7f3e3d3a | 2486 | { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 }, |
e3cf0cc0 FR |
2487 | { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 }, |
2488 | { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 }, | |
197ff761 | 2489 | { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 }, |
ef808d50 | 2490 | { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 }, |
e3cf0cc0 FR |
2491 | |
2492 | /* 8168B family. */ | |
2493 | { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 }, | |
e3cf0cc0 FR |
2494 | { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 }, |
2495 | { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 }, | |
2496 | ||
2497 | /* 8101 family. */ | |
5598bfe5 | 2498 | { 0x7c800000, 0x44800000, RTL_GIGA_MAC_VER_39 }, |
7e18dca1 | 2499 | { 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37 }, |
5a5e4443 HW |
2500 | { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 }, |
2501 | { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 }, | |
2857ffb7 FR |
2502 | { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 }, |
2503 | { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 }, | |
2504 | { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 }, | |
2505 | { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 }, | |
e3cf0cc0 | 2506 | { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 }, |
2857ffb7 | 2507 | { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 }, |
e3cf0cc0 | 2508 | { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 }, |
2857ffb7 FR |
2509 | { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 }, |
2510 | { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 }, | |
e3cf0cc0 FR |
2511 | { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 }, |
2512 | /* FIXME: where did these entries come from ? -- FR */ | |
2513 | { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 }, | |
2514 | { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 }, | |
2515 | ||
2516 | /* 8110 family. */ | |
2517 | { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 }, | |
2518 | { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 }, | |
2519 | { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 }, | |
2520 | { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 }, | |
2521 | { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 }, | |
2522 | { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 }, | |
2523 | ||
f21b75e9 JD |
2524 | /* Catch-all */ |
2525 | { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE } | |
3744100e FR |
2526 | }; |
2527 | const struct rtl_mac_info *p = mac_info; | |
1da177e4 LT |
2528 | u32 reg; |
2529 | ||
1ef7286e | 2530 | reg = RTL_R32(tp, TxConfig); |
e3cf0cc0 | 2531 | while ((reg & p->mask) != p->val) |
1da177e4 LT |
2532 | p++; |
2533 | tp->mac_version = p->mac_version; | |
5d320a20 FR |
2534 | |
2535 | if (tp->mac_version == RTL_GIGA_MAC_NONE) { | |
22148df0 HK |
2536 | dev_notice(tp_to_dev(tp), |
2537 | "unknown MAC, using family default\n"); | |
5d320a20 | 2538 | tp->mac_version = default_version; |
58152cd4 | 2539 | } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) { |
2540 | tp->mac_version = tp->mii.supports_gmii ? | |
2541 | RTL_GIGA_MAC_VER_42 : | |
2542 | RTL_GIGA_MAC_VER_43; | |
6e1d0b89 CHL |
2543 | } else if (tp->mac_version == RTL_GIGA_MAC_VER_45) { |
2544 | tp->mac_version = tp->mii.supports_gmii ? | |
2545 | RTL_GIGA_MAC_VER_45 : | |
2546 | RTL_GIGA_MAC_VER_47; | |
2547 | } else if (tp->mac_version == RTL_GIGA_MAC_VER_46) { | |
2548 | tp->mac_version = tp->mii.supports_gmii ? | |
2549 | RTL_GIGA_MAC_VER_46 : | |
2550 | RTL_GIGA_MAC_VER_48; | |
5d320a20 | 2551 | } |
1da177e4 LT |
2552 | } |
2553 | ||
2554 | static void rtl8169_print_mac_version(struct rtl8169_private *tp) | |
2555 | { | |
bcf0bf90 | 2556 | dprintk("mac_version = 0x%02x\n", tp->mac_version); |
1da177e4 LT |
2557 | } |
2558 | ||
867763c1 FR |
2559 | struct phy_reg { |
2560 | u16 reg; | |
2561 | u16 val; | |
2562 | }; | |
2563 | ||
4da19633 | 2564 | static void rtl_writephy_batch(struct rtl8169_private *tp, |
2565 | const struct phy_reg *regs, int len) | |
867763c1 FR |
2566 | { |
2567 | while (len-- > 0) { | |
4da19633 | 2568 | rtl_writephy(tp, regs->reg, regs->val); |
867763c1 FR |
2569 | regs++; |
2570 | } | |
2571 | } | |
2572 | ||
bca03d5f | 2573 | #define PHY_READ 0x00000000 |
2574 | #define PHY_DATA_OR 0x10000000 | |
2575 | #define PHY_DATA_AND 0x20000000 | |
2576 | #define PHY_BJMPN 0x30000000 | |
eee3786f | 2577 | #define PHY_MDIO_CHG 0x40000000 |
bca03d5f | 2578 | #define PHY_CLEAR_READCOUNT 0x70000000 |
2579 | #define PHY_WRITE 0x80000000 | |
2580 | #define PHY_READCOUNT_EQ_SKIP 0x90000000 | |
2581 | #define PHY_COMP_EQ_SKIPN 0xa0000000 | |
2582 | #define PHY_COMP_NEQ_SKIPN 0xb0000000 | |
2583 | #define PHY_WRITE_PREVIOUS 0xc0000000 | |
2584 | #define PHY_SKIPN 0xd0000000 | |
2585 | #define PHY_DELAY_MS 0xe0000000 | |
bca03d5f | 2586 | |
960aee6c HW |
2587 | struct fw_info { |
2588 | u32 magic; | |
2589 | char version[RTL_VER_SIZE]; | |
2590 | __le32 fw_start; | |
2591 | __le32 fw_len; | |
2592 | u8 chksum; | |
2593 | } __packed; | |
2594 | ||
1c361efb FR |
2595 | #define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code)) |
2596 | ||
2597 | static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw) | |
bca03d5f | 2598 | { |
b6ffd97f | 2599 | const struct firmware *fw = rtl_fw->fw; |
960aee6c | 2600 | struct fw_info *fw_info = (struct fw_info *)fw->data; |
1c361efb FR |
2601 | struct rtl_fw_phy_action *pa = &rtl_fw->phy_action; |
2602 | char *version = rtl_fw->version; | |
2603 | bool rc = false; | |
2604 | ||
2605 | if (fw->size < FW_OPCODE_SIZE) | |
2606 | goto out; | |
960aee6c HW |
2607 | |
2608 | if (!fw_info->magic) { | |
2609 | size_t i, size, start; | |
2610 | u8 checksum = 0; | |
2611 | ||
2612 | if (fw->size < sizeof(*fw_info)) | |
2613 | goto out; | |
2614 | ||
2615 | for (i = 0; i < fw->size; i++) | |
2616 | checksum += fw->data[i]; | |
2617 | if (checksum != 0) | |
2618 | goto out; | |
2619 | ||
2620 | start = le32_to_cpu(fw_info->fw_start); | |
2621 | if (start > fw->size) | |
2622 | goto out; | |
2623 | ||
2624 | size = le32_to_cpu(fw_info->fw_len); | |
2625 | if (size > (fw->size - start) / FW_OPCODE_SIZE) | |
2626 | goto out; | |
2627 | ||
2628 | memcpy(version, fw_info->version, RTL_VER_SIZE); | |
2629 | ||
2630 | pa->code = (__le32 *)(fw->data + start); | |
2631 | pa->size = size; | |
2632 | } else { | |
1c361efb FR |
2633 | if (fw->size % FW_OPCODE_SIZE) |
2634 | goto out; | |
2635 | ||
2636 | strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE); | |
2637 | ||
2638 | pa->code = (__le32 *)fw->data; | |
2639 | pa->size = fw->size / FW_OPCODE_SIZE; | |
2640 | } | |
2641 | version[RTL_VER_SIZE - 1] = 0; | |
2642 | ||
2643 | rc = true; | |
2644 | out: | |
2645 | return rc; | |
2646 | } | |
2647 | ||
fd112f2e FR |
2648 | static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev, |
2649 | struct rtl_fw_phy_action *pa) | |
1c361efb | 2650 | { |
fd112f2e | 2651 | bool rc = false; |
1c361efb | 2652 | size_t index; |
bca03d5f | 2653 | |
1c361efb FR |
2654 | for (index = 0; index < pa->size; index++) { |
2655 | u32 action = le32_to_cpu(pa->code[index]); | |
42b82dc1 | 2656 | u32 regno = (action & 0x0fff0000) >> 16; |
bca03d5f | 2657 | |
42b82dc1 | 2658 | switch(action & 0xf0000000) { |
2659 | case PHY_READ: | |
2660 | case PHY_DATA_OR: | |
2661 | case PHY_DATA_AND: | |
eee3786f | 2662 | case PHY_MDIO_CHG: |
42b82dc1 | 2663 | case PHY_CLEAR_READCOUNT: |
2664 | case PHY_WRITE: | |
2665 | case PHY_WRITE_PREVIOUS: | |
2666 | case PHY_DELAY_MS: | |
2667 | break; | |
2668 | ||
2669 | case PHY_BJMPN: | |
2670 | if (regno > index) { | |
fd112f2e | 2671 | netif_err(tp, ifup, tp->dev, |
cecb5fd7 | 2672 | "Out of range of firmware\n"); |
fd112f2e | 2673 | goto out; |
42b82dc1 | 2674 | } |
2675 | break; | |
2676 | case PHY_READCOUNT_EQ_SKIP: | |
1c361efb | 2677 | if (index + 2 >= pa->size) { |
fd112f2e | 2678 | netif_err(tp, ifup, tp->dev, |
cecb5fd7 | 2679 | "Out of range of firmware\n"); |
fd112f2e | 2680 | goto out; |
42b82dc1 | 2681 | } |
2682 | break; | |
2683 | case PHY_COMP_EQ_SKIPN: | |
2684 | case PHY_COMP_NEQ_SKIPN: | |
2685 | case PHY_SKIPN: | |
1c361efb | 2686 | if (index + 1 + regno >= pa->size) { |
fd112f2e | 2687 | netif_err(tp, ifup, tp->dev, |
cecb5fd7 | 2688 | "Out of range of firmware\n"); |
fd112f2e | 2689 | goto out; |
42b82dc1 | 2690 | } |
bca03d5f | 2691 | break; |
2692 | ||
42b82dc1 | 2693 | default: |
fd112f2e | 2694 | netif_err(tp, ifup, tp->dev, |
42b82dc1 | 2695 | "Invalid action 0x%08x\n", action); |
fd112f2e | 2696 | goto out; |
bca03d5f | 2697 | } |
2698 | } | |
fd112f2e FR |
2699 | rc = true; |
2700 | out: | |
2701 | return rc; | |
2702 | } | |
bca03d5f | 2703 | |
fd112f2e FR |
2704 | static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw) |
2705 | { | |
2706 | struct net_device *dev = tp->dev; | |
2707 | int rc = -EINVAL; | |
2708 | ||
2709 | if (!rtl_fw_format_ok(tp, rtl_fw)) { | |
5c2d2b14 | 2710 | netif_err(tp, ifup, dev, "invalid firmware\n"); |
fd112f2e FR |
2711 | goto out; |
2712 | } | |
2713 | ||
2714 | if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action)) | |
2715 | rc = 0; | |
2716 | out: | |
2717 | return rc; | |
2718 | } | |
2719 | ||
2720 | static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw) | |
2721 | { | |
2722 | struct rtl_fw_phy_action *pa = &rtl_fw->phy_action; | |
eee3786f | 2723 | struct mdio_ops org, *ops = &tp->mdio_ops; |
fd112f2e FR |
2724 | u32 predata, count; |
2725 | size_t index; | |
2726 | ||
2727 | predata = count = 0; | |
eee3786f | 2728 | org.write = ops->write; |
2729 | org.read = ops->read; | |
42b82dc1 | 2730 | |
1c361efb FR |
2731 | for (index = 0; index < pa->size; ) { |
2732 | u32 action = le32_to_cpu(pa->code[index]); | |
bca03d5f | 2733 | u32 data = action & 0x0000ffff; |
42b82dc1 | 2734 | u32 regno = (action & 0x0fff0000) >> 16; |
2735 | ||
2736 | if (!action) | |
2737 | break; | |
bca03d5f | 2738 | |
2739 | switch(action & 0xf0000000) { | |
42b82dc1 | 2740 | case PHY_READ: |
2741 | predata = rtl_readphy(tp, regno); | |
2742 | count++; | |
2743 | index++; | |
2744 | break; | |
2745 | case PHY_DATA_OR: | |
2746 | predata |= data; | |
2747 | index++; | |
2748 | break; | |
2749 | case PHY_DATA_AND: | |
2750 | predata &= data; | |
2751 | index++; | |
2752 | break; | |
2753 | case PHY_BJMPN: | |
2754 | index -= regno; | |
2755 | break; | |
eee3786f | 2756 | case PHY_MDIO_CHG: |
2757 | if (data == 0) { | |
2758 | ops->write = org.write; | |
2759 | ops->read = org.read; | |
2760 | } else if (data == 1) { | |
2761 | ops->write = mac_mcu_write; | |
2762 | ops->read = mac_mcu_read; | |
2763 | } | |
2764 | ||
42b82dc1 | 2765 | index++; |
2766 | break; | |
2767 | case PHY_CLEAR_READCOUNT: | |
2768 | count = 0; | |
2769 | index++; | |
2770 | break; | |
bca03d5f | 2771 | case PHY_WRITE: |
42b82dc1 | 2772 | rtl_writephy(tp, regno, data); |
2773 | index++; | |
2774 | break; | |
2775 | case PHY_READCOUNT_EQ_SKIP: | |
cecb5fd7 | 2776 | index += (count == data) ? 2 : 1; |
bca03d5f | 2777 | break; |
42b82dc1 | 2778 | case PHY_COMP_EQ_SKIPN: |
2779 | if (predata == data) | |
2780 | index += regno; | |
2781 | index++; | |
2782 | break; | |
2783 | case PHY_COMP_NEQ_SKIPN: | |
2784 | if (predata != data) | |
2785 | index += regno; | |
2786 | index++; | |
2787 | break; | |
2788 | case PHY_WRITE_PREVIOUS: | |
2789 | rtl_writephy(tp, regno, predata); | |
2790 | index++; | |
2791 | break; | |
2792 | case PHY_SKIPN: | |
2793 | index += regno + 1; | |
2794 | break; | |
2795 | case PHY_DELAY_MS: | |
2796 | mdelay(data); | |
2797 | index++; | |
2798 | break; | |
2799 | ||
bca03d5f | 2800 | default: |
2801 | BUG(); | |
2802 | } | |
2803 | } | |
eee3786f | 2804 | |
2805 | ops->write = org.write; | |
2806 | ops->read = org.read; | |
bca03d5f | 2807 | } |
2808 | ||
f1e02ed1 | 2809 | static void rtl_release_firmware(struct rtl8169_private *tp) |
2810 | { | |
b6ffd97f FR |
2811 | if (!IS_ERR_OR_NULL(tp->rtl_fw)) { |
2812 | release_firmware(tp->rtl_fw->fw); | |
2813 | kfree(tp->rtl_fw); | |
2814 | } | |
2815 | tp->rtl_fw = RTL_FIRMWARE_UNKNOWN; | |
f1e02ed1 | 2816 | } |
2817 | ||
953a12cc | 2818 | static void rtl_apply_firmware(struct rtl8169_private *tp) |
f1e02ed1 | 2819 | { |
b6ffd97f | 2820 | struct rtl_fw *rtl_fw = tp->rtl_fw; |
f1e02ed1 | 2821 | |
2822 | /* TODO: release firmware once rtl_phy_write_fw signals failures. */ | |
eef63cc1 | 2823 | if (!IS_ERR_OR_NULL(rtl_fw)) |
b6ffd97f | 2824 | rtl_phy_write_fw(tp, rtl_fw); |
953a12cc FR |
2825 | } |
2826 | ||
2827 | static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val) | |
2828 | { | |
2829 | if (rtl_readphy(tp, reg) != val) | |
2830 | netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n"); | |
2831 | else | |
2832 | rtl_apply_firmware(tp); | |
f1e02ed1 | 2833 | } |
2834 | ||
4da19633 | 2835 | static void rtl8169s_hw_phy_config(struct rtl8169_private *tp) |
1da177e4 | 2836 | { |
350f7596 | 2837 | static const struct phy_reg phy_reg_init[] = { |
0b9b571d | 2838 | { 0x1f, 0x0001 }, |
2839 | { 0x06, 0x006e }, | |
2840 | { 0x08, 0x0708 }, | |
2841 | { 0x15, 0x4000 }, | |
2842 | { 0x18, 0x65c7 }, | |
1da177e4 | 2843 | |
0b9b571d | 2844 | { 0x1f, 0x0001 }, |
2845 | { 0x03, 0x00a1 }, | |
2846 | { 0x02, 0x0008 }, | |
2847 | { 0x01, 0x0120 }, | |
2848 | { 0x00, 0x1000 }, | |
2849 | { 0x04, 0x0800 }, | |
2850 | { 0x04, 0x0000 }, | |
1da177e4 | 2851 | |
0b9b571d | 2852 | { 0x03, 0xff41 }, |
2853 | { 0x02, 0xdf60 }, | |
2854 | { 0x01, 0x0140 }, | |
2855 | { 0x00, 0x0077 }, | |
2856 | { 0x04, 0x7800 }, | |
2857 | { 0x04, 0x7000 }, | |
2858 | ||
2859 | { 0x03, 0x802f }, | |
2860 | { 0x02, 0x4f02 }, | |
2861 | { 0x01, 0x0409 }, | |
2862 | { 0x00, 0xf0f9 }, | |
2863 | { 0x04, 0x9800 }, | |
2864 | { 0x04, 0x9000 }, | |
2865 | ||
2866 | { 0x03, 0xdf01 }, | |
2867 | { 0x02, 0xdf20 }, | |
2868 | { 0x01, 0xff95 }, | |
2869 | { 0x00, 0xba00 }, | |
2870 | { 0x04, 0xa800 }, | |
2871 | { 0x04, 0xa000 }, | |
2872 | ||
2873 | { 0x03, 0xff41 }, | |
2874 | { 0x02, 0xdf20 }, | |
2875 | { 0x01, 0x0140 }, | |
2876 | { 0x00, 0x00bb }, | |
2877 | { 0x04, 0xb800 }, | |
2878 | { 0x04, 0xb000 }, | |
2879 | ||
2880 | { 0x03, 0xdf41 }, | |
2881 | { 0x02, 0xdc60 }, | |
2882 | { 0x01, 0x6340 }, | |
2883 | { 0x00, 0x007d }, | |
2884 | { 0x04, 0xd800 }, | |
2885 | { 0x04, 0xd000 }, | |
2886 | ||
2887 | { 0x03, 0xdf01 }, | |
2888 | { 0x02, 0xdf20 }, | |
2889 | { 0x01, 0x100a }, | |
2890 | { 0x00, 0xa0ff }, | |
2891 | { 0x04, 0xf800 }, | |
2892 | { 0x04, 0xf000 }, | |
2893 | ||
2894 | { 0x1f, 0x0000 }, | |
2895 | { 0x0b, 0x0000 }, | |
2896 | { 0x00, 0x9200 } | |
2897 | }; | |
1da177e4 | 2898 | |
4da19633 | 2899 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
1da177e4 LT |
2900 | } |
2901 | ||
4da19633 | 2902 | static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp) |
5615d9f1 | 2903 | { |
350f7596 | 2904 | static const struct phy_reg phy_reg_init[] = { |
a441d7b6 FR |
2905 | { 0x1f, 0x0002 }, |
2906 | { 0x01, 0x90d0 }, | |
2907 | { 0x1f, 0x0000 } | |
2908 | }; | |
2909 | ||
4da19633 | 2910 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
5615d9f1 FR |
2911 | } |
2912 | ||
4da19633 | 2913 | static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp) |
2e955856 | 2914 | { |
2915 | struct pci_dev *pdev = tp->pci_dev; | |
2e955856 | 2916 | |
ccbae55e SS |
2917 | if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) || |
2918 | (pdev->subsystem_device != 0xe000)) | |
2e955856 | 2919 | return; |
2920 | ||
4da19633 | 2921 | rtl_writephy(tp, 0x1f, 0x0001); |
2922 | rtl_writephy(tp, 0x10, 0xf01b); | |
2923 | rtl_writephy(tp, 0x1f, 0x0000); | |
2e955856 | 2924 | } |
2925 | ||
4da19633 | 2926 | static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp) |
2e955856 | 2927 | { |
350f7596 | 2928 | static const struct phy_reg phy_reg_init[] = { |
2e955856 | 2929 | { 0x1f, 0x0001 }, |
2930 | { 0x04, 0x0000 }, | |
2931 | { 0x03, 0x00a1 }, | |
2932 | { 0x02, 0x0008 }, | |
2933 | { 0x01, 0x0120 }, | |
2934 | { 0x00, 0x1000 }, | |
2935 | { 0x04, 0x0800 }, | |
2936 | { 0x04, 0x9000 }, | |
2937 | { 0x03, 0x802f }, | |
2938 | { 0x02, 0x4f02 }, | |
2939 | { 0x01, 0x0409 }, | |
2940 | { 0x00, 0xf099 }, | |
2941 | { 0x04, 0x9800 }, | |
2942 | { 0x04, 0xa000 }, | |
2943 | { 0x03, 0xdf01 }, | |
2944 | { 0x02, 0xdf20 }, | |
2945 | { 0x01, 0xff95 }, | |
2946 | { 0x00, 0xba00 }, | |
2947 | { 0x04, 0xa800 }, | |
2948 | { 0x04, 0xf000 }, | |
2949 | { 0x03, 0xdf01 }, | |
2950 | { 0x02, 0xdf20 }, | |
2951 | { 0x01, 0x101a }, | |
2952 | { 0x00, 0xa0ff }, | |
2953 | { 0x04, 0xf800 }, | |
2954 | { 0x04, 0x0000 }, | |
2955 | { 0x1f, 0x0000 }, | |
2956 | ||
2957 | { 0x1f, 0x0001 }, | |
2958 | { 0x10, 0xf41b }, | |
2959 | { 0x14, 0xfb54 }, | |
2960 | { 0x18, 0xf5c7 }, | |
2961 | { 0x1f, 0x0000 }, | |
2962 | ||
2963 | { 0x1f, 0x0001 }, | |
2964 | { 0x17, 0x0cc0 }, | |
2965 | { 0x1f, 0x0000 } | |
2966 | }; | |
2967 | ||
4da19633 | 2968 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
2e955856 | 2969 | |
4da19633 | 2970 | rtl8169scd_hw_phy_config_quirk(tp); |
2e955856 | 2971 | } |
2972 | ||
4da19633 | 2973 | static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp) |
8c7006aa | 2974 | { |
350f7596 | 2975 | static const struct phy_reg phy_reg_init[] = { |
8c7006aa | 2976 | { 0x1f, 0x0001 }, |
2977 | { 0x04, 0x0000 }, | |
2978 | { 0x03, 0x00a1 }, | |
2979 | { 0x02, 0x0008 }, | |
2980 | { 0x01, 0x0120 }, | |
2981 | { 0x00, 0x1000 }, | |
2982 | { 0x04, 0x0800 }, | |
2983 | { 0x04, 0x9000 }, | |
2984 | { 0x03, 0x802f }, | |
2985 | { 0x02, 0x4f02 }, | |
2986 | { 0x01, 0x0409 }, | |
2987 | { 0x00, 0xf099 }, | |
2988 | { 0x04, 0x9800 }, | |
2989 | { 0x04, 0xa000 }, | |
2990 | { 0x03, 0xdf01 }, | |
2991 | { 0x02, 0xdf20 }, | |
2992 | { 0x01, 0xff95 }, | |
2993 | { 0x00, 0xba00 }, | |
2994 | { 0x04, 0xa800 }, | |
2995 | { 0x04, 0xf000 }, | |
2996 | { 0x03, 0xdf01 }, | |
2997 | { 0x02, 0xdf20 }, | |
2998 | { 0x01, 0x101a }, | |
2999 | { 0x00, 0xa0ff }, | |
3000 | { 0x04, 0xf800 }, | |
3001 | { 0x04, 0x0000 }, | |
3002 | { 0x1f, 0x0000 }, | |
3003 | ||
3004 | { 0x1f, 0x0001 }, | |
3005 | { 0x0b, 0x8480 }, | |
3006 | { 0x1f, 0x0000 }, | |
3007 | ||
3008 | { 0x1f, 0x0001 }, | |
3009 | { 0x18, 0x67c7 }, | |
3010 | { 0x04, 0x2000 }, | |
3011 | { 0x03, 0x002f }, | |
3012 | { 0x02, 0x4360 }, | |
3013 | { 0x01, 0x0109 }, | |
3014 | { 0x00, 0x3022 }, | |
3015 | { 0x04, 0x2800 }, | |
3016 | { 0x1f, 0x0000 }, | |
3017 | ||
3018 | { 0x1f, 0x0001 }, | |
3019 | { 0x17, 0x0cc0 }, | |
3020 | { 0x1f, 0x0000 } | |
3021 | }; | |
3022 | ||
4da19633 | 3023 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
8c7006aa | 3024 | } |
3025 | ||
4da19633 | 3026 | static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp) |
236b8082 | 3027 | { |
350f7596 | 3028 | static const struct phy_reg phy_reg_init[] = { |
236b8082 FR |
3029 | { 0x10, 0xf41b }, |
3030 | { 0x1f, 0x0000 } | |
3031 | }; | |
3032 | ||
4da19633 | 3033 | rtl_writephy(tp, 0x1f, 0x0001); |
3034 | rtl_patchphy(tp, 0x16, 1 << 0); | |
236b8082 | 3035 | |
4da19633 | 3036 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
236b8082 FR |
3037 | } |
3038 | ||
4da19633 | 3039 | static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp) |
236b8082 | 3040 | { |
350f7596 | 3041 | static const struct phy_reg phy_reg_init[] = { |
236b8082 FR |
3042 | { 0x1f, 0x0001 }, |
3043 | { 0x10, 0xf41b }, | |
3044 | { 0x1f, 0x0000 } | |
3045 | }; | |
3046 | ||
4da19633 | 3047 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
236b8082 FR |
3048 | } |
3049 | ||
4da19633 | 3050 | static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp) |
867763c1 | 3051 | { |
350f7596 | 3052 | static const struct phy_reg phy_reg_init[] = { |
867763c1 FR |
3053 | { 0x1f, 0x0000 }, |
3054 | { 0x1d, 0x0f00 }, | |
3055 | { 0x1f, 0x0002 }, | |
3056 | { 0x0c, 0x1ec8 }, | |
3057 | { 0x1f, 0x0000 } | |
3058 | }; | |
3059 | ||
4da19633 | 3060 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
867763c1 FR |
3061 | } |
3062 | ||
4da19633 | 3063 | static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp) |
ef3386f0 | 3064 | { |
350f7596 | 3065 | static const struct phy_reg phy_reg_init[] = { |
ef3386f0 FR |
3066 | { 0x1f, 0x0001 }, |
3067 | { 0x1d, 0x3d98 }, | |
3068 | { 0x1f, 0x0000 } | |
3069 | }; | |
3070 | ||
4da19633 | 3071 | rtl_writephy(tp, 0x1f, 0x0000); |
3072 | rtl_patchphy(tp, 0x14, 1 << 5); | |
3073 | rtl_patchphy(tp, 0x0d, 1 << 5); | |
ef3386f0 | 3074 | |
4da19633 | 3075 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
ef3386f0 FR |
3076 | } |
3077 | ||
4da19633 | 3078 | static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp) |
867763c1 | 3079 | { |
350f7596 | 3080 | static const struct phy_reg phy_reg_init[] = { |
a3f80671 FR |
3081 | { 0x1f, 0x0001 }, |
3082 | { 0x12, 0x2300 }, | |
867763c1 FR |
3083 | { 0x1f, 0x0002 }, |
3084 | { 0x00, 0x88d4 }, | |
3085 | { 0x01, 0x82b1 }, | |
3086 | { 0x03, 0x7002 }, | |
3087 | { 0x08, 0x9e30 }, | |
3088 | { 0x09, 0x01f0 }, | |
3089 | { 0x0a, 0x5500 }, | |
3090 | { 0x0c, 0x00c8 }, | |
3091 | { 0x1f, 0x0003 }, | |
3092 | { 0x12, 0xc096 }, | |
3093 | { 0x16, 0x000a }, | |
f50d4275 FR |
3094 | { 0x1f, 0x0000 }, |
3095 | { 0x1f, 0x0000 }, | |
3096 | { 0x09, 0x2000 }, | |
3097 | { 0x09, 0x0000 } | |
867763c1 FR |
3098 | }; |
3099 | ||
4da19633 | 3100 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
f50d4275 | 3101 | |
4da19633 | 3102 | rtl_patchphy(tp, 0x14, 1 << 5); |
3103 | rtl_patchphy(tp, 0x0d, 1 << 5); | |
3104 | rtl_writephy(tp, 0x1f, 0x0000); | |
867763c1 FR |
3105 | } |
3106 | ||
4da19633 | 3107 | static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp) |
7da97ec9 | 3108 | { |
350f7596 | 3109 | static const struct phy_reg phy_reg_init[] = { |
f50d4275 | 3110 | { 0x1f, 0x0001 }, |
7da97ec9 | 3111 | { 0x12, 0x2300 }, |
f50d4275 FR |
3112 | { 0x03, 0x802f }, |
3113 | { 0x02, 0x4f02 }, | |
3114 | { 0x01, 0x0409 }, | |
3115 | { 0x00, 0xf099 }, | |
3116 | { 0x04, 0x9800 }, | |
3117 | { 0x04, 0x9000 }, | |
3118 | { 0x1d, 0x3d98 }, | |
7da97ec9 FR |
3119 | { 0x1f, 0x0002 }, |
3120 | { 0x0c, 0x7eb8 }, | |
f50d4275 FR |
3121 | { 0x06, 0x0761 }, |
3122 | { 0x1f, 0x0003 }, | |
3123 | { 0x16, 0x0f0a }, | |
7da97ec9 FR |
3124 | { 0x1f, 0x0000 } |
3125 | }; | |
3126 | ||
4da19633 | 3127 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
f50d4275 | 3128 | |
4da19633 | 3129 | rtl_patchphy(tp, 0x16, 1 << 0); |
3130 | rtl_patchphy(tp, 0x14, 1 << 5); | |
3131 | rtl_patchphy(tp, 0x0d, 1 << 5); | |
3132 | rtl_writephy(tp, 0x1f, 0x0000); | |
7da97ec9 FR |
3133 | } |
3134 | ||
4da19633 | 3135 | static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp) |
197ff761 | 3136 | { |
350f7596 | 3137 | static const struct phy_reg phy_reg_init[] = { |
197ff761 FR |
3138 | { 0x1f, 0x0001 }, |
3139 | { 0x12, 0x2300 }, | |
3140 | { 0x1d, 0x3d98 }, | |
3141 | { 0x1f, 0x0002 }, | |
3142 | { 0x0c, 0x7eb8 }, | |
3143 | { 0x06, 0x5461 }, | |
3144 | { 0x1f, 0x0003 }, | |
3145 | { 0x16, 0x0f0a }, | |
3146 | { 0x1f, 0x0000 } | |
3147 | }; | |
3148 | ||
4da19633 | 3149 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
197ff761 | 3150 | |
4da19633 | 3151 | rtl_patchphy(tp, 0x16, 1 << 0); |
3152 | rtl_patchphy(tp, 0x14, 1 << 5); | |
3153 | rtl_patchphy(tp, 0x0d, 1 << 5); | |
3154 | rtl_writephy(tp, 0x1f, 0x0000); | |
197ff761 FR |
3155 | } |
3156 | ||
4da19633 | 3157 | static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp) |
6fb07058 | 3158 | { |
4da19633 | 3159 | rtl8168c_3_hw_phy_config(tp); |
6fb07058 FR |
3160 | } |
3161 | ||
bca03d5f | 3162 | static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp) |
5b538df9 | 3163 | { |
350f7596 | 3164 | static const struct phy_reg phy_reg_init_0[] = { |
bca03d5f | 3165 | /* Channel Estimation */ |
5b538df9 | 3166 | { 0x1f, 0x0001 }, |
daf9df6d | 3167 | { 0x06, 0x4064 }, |
3168 | { 0x07, 0x2863 }, | |
3169 | { 0x08, 0x059c }, | |
3170 | { 0x09, 0x26b4 }, | |
3171 | { 0x0a, 0x6a19 }, | |
3172 | { 0x0b, 0xdcc8 }, | |
3173 | { 0x10, 0xf06d }, | |
3174 | { 0x14, 0x7f68 }, | |
3175 | { 0x18, 0x7fd9 }, | |
3176 | { 0x1c, 0xf0ff }, | |
3177 | { 0x1d, 0x3d9c }, | |
5b538df9 | 3178 | { 0x1f, 0x0003 }, |
daf9df6d | 3179 | { 0x12, 0xf49f }, |
3180 | { 0x13, 0x070b }, | |
3181 | { 0x1a, 0x05ad }, | |
bca03d5f | 3182 | { 0x14, 0x94c0 }, |
3183 | ||
3184 | /* | |
3185 | * Tx Error Issue | |
cecb5fd7 | 3186 | * Enhance line driver power |
bca03d5f | 3187 | */ |
5b538df9 | 3188 | { 0x1f, 0x0002 }, |
daf9df6d | 3189 | { 0x06, 0x5561 }, |
3190 | { 0x1f, 0x0005 }, | |
3191 | { 0x05, 0x8332 }, | |
bca03d5f | 3192 | { 0x06, 0x5561 }, |
3193 | ||
3194 | /* | |
3195 | * Can not link to 1Gbps with bad cable | |
3196 | * Decrease SNR threshold form 21.07dB to 19.04dB | |
3197 | */ | |
3198 | { 0x1f, 0x0001 }, | |
3199 | { 0x17, 0x0cc0 }, | |
daf9df6d | 3200 | |
5b538df9 | 3201 | { 0x1f, 0x0000 }, |
bca03d5f | 3202 | { 0x0d, 0xf880 } |
daf9df6d | 3203 | }; |
3204 | ||
4da19633 | 3205 | rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0)); |
daf9df6d | 3206 | |
bca03d5f | 3207 | /* |
3208 | * Rx Error Issue | |
3209 | * Fine Tune Switching regulator parameter | |
3210 | */ | |
4da19633 | 3211 | rtl_writephy(tp, 0x1f, 0x0002); |
76564428 CHL |
3212 | rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef); |
3213 | rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00); | |
daf9df6d | 3214 | |
fdf6fc06 | 3215 | if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) { |
350f7596 | 3216 | static const struct phy_reg phy_reg_init[] = { |
daf9df6d | 3217 | { 0x1f, 0x0002 }, |
3218 | { 0x05, 0x669a }, | |
3219 | { 0x1f, 0x0005 }, | |
3220 | { 0x05, 0x8330 }, | |
3221 | { 0x06, 0x669a }, | |
3222 | { 0x1f, 0x0002 } | |
3223 | }; | |
3224 | int val; | |
3225 | ||
4da19633 | 3226 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
daf9df6d | 3227 | |
4da19633 | 3228 | val = rtl_readphy(tp, 0x0d); |
daf9df6d | 3229 | |
3230 | if ((val & 0x00ff) != 0x006c) { | |
350f7596 | 3231 | static const u32 set[] = { |
daf9df6d | 3232 | 0x0065, 0x0066, 0x0067, 0x0068, |
3233 | 0x0069, 0x006a, 0x006b, 0x006c | |
3234 | }; | |
3235 | int i; | |
3236 | ||
4da19633 | 3237 | rtl_writephy(tp, 0x1f, 0x0002); |
daf9df6d | 3238 | |
3239 | val &= 0xff00; | |
3240 | for (i = 0; i < ARRAY_SIZE(set); i++) | |
4da19633 | 3241 | rtl_writephy(tp, 0x0d, val | set[i]); |
daf9df6d | 3242 | } |
3243 | } else { | |
350f7596 | 3244 | static const struct phy_reg phy_reg_init[] = { |
daf9df6d | 3245 | { 0x1f, 0x0002 }, |
3246 | { 0x05, 0x6662 }, | |
3247 | { 0x1f, 0x0005 }, | |
3248 | { 0x05, 0x8330 }, | |
3249 | { 0x06, 0x6662 } | |
3250 | }; | |
3251 | ||
4da19633 | 3252 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
daf9df6d | 3253 | } |
3254 | ||
bca03d5f | 3255 | /* RSET couple improve */ |
4da19633 | 3256 | rtl_writephy(tp, 0x1f, 0x0002); |
3257 | rtl_patchphy(tp, 0x0d, 0x0300); | |
3258 | rtl_patchphy(tp, 0x0f, 0x0010); | |
daf9df6d | 3259 | |
bca03d5f | 3260 | /* Fine tune PLL performance */ |
4da19633 | 3261 | rtl_writephy(tp, 0x1f, 0x0002); |
76564428 CHL |
3262 | rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600); |
3263 | rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000); | |
daf9df6d | 3264 | |
4da19633 | 3265 | rtl_writephy(tp, 0x1f, 0x0005); |
3266 | rtl_writephy(tp, 0x05, 0x001b); | |
953a12cc FR |
3267 | |
3268 | rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00); | |
bca03d5f | 3269 | |
4da19633 | 3270 | rtl_writephy(tp, 0x1f, 0x0000); |
daf9df6d | 3271 | } |
3272 | ||
bca03d5f | 3273 | static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp) |
daf9df6d | 3274 | { |
350f7596 | 3275 | static const struct phy_reg phy_reg_init_0[] = { |
bca03d5f | 3276 | /* Channel Estimation */ |
daf9df6d | 3277 | { 0x1f, 0x0001 }, |
3278 | { 0x06, 0x4064 }, | |
3279 | { 0x07, 0x2863 }, | |
3280 | { 0x08, 0x059c }, | |
3281 | { 0x09, 0x26b4 }, | |
3282 | { 0x0a, 0x6a19 }, | |
3283 | { 0x0b, 0xdcc8 }, | |
3284 | { 0x10, 0xf06d }, | |
3285 | { 0x14, 0x7f68 }, | |
3286 | { 0x18, 0x7fd9 }, | |
3287 | { 0x1c, 0xf0ff }, | |
3288 | { 0x1d, 0x3d9c }, | |
3289 | { 0x1f, 0x0003 }, | |
3290 | { 0x12, 0xf49f }, | |
3291 | { 0x13, 0x070b }, | |
3292 | { 0x1a, 0x05ad }, | |
3293 | { 0x14, 0x94c0 }, | |
3294 | ||
bca03d5f | 3295 | /* |
3296 | * Tx Error Issue | |
cecb5fd7 | 3297 | * Enhance line driver power |
bca03d5f | 3298 | */ |
daf9df6d | 3299 | { 0x1f, 0x0002 }, |
3300 | { 0x06, 0x5561 }, | |
3301 | { 0x1f, 0x0005 }, | |
3302 | { 0x05, 0x8332 }, | |
bca03d5f | 3303 | { 0x06, 0x5561 }, |
3304 | ||
3305 | /* | |
3306 | * Can not link to 1Gbps with bad cable | |
3307 | * Decrease SNR threshold form 21.07dB to 19.04dB | |
3308 | */ | |
3309 | { 0x1f, 0x0001 }, | |
3310 | { 0x17, 0x0cc0 }, | |
daf9df6d | 3311 | |
3312 | { 0x1f, 0x0000 }, | |
bca03d5f | 3313 | { 0x0d, 0xf880 } |
5b538df9 FR |
3314 | }; |
3315 | ||
4da19633 | 3316 | rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0)); |
5b538df9 | 3317 | |
fdf6fc06 | 3318 | if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) { |
350f7596 | 3319 | static const struct phy_reg phy_reg_init[] = { |
daf9df6d | 3320 | { 0x1f, 0x0002 }, |
3321 | { 0x05, 0x669a }, | |
5b538df9 | 3322 | { 0x1f, 0x0005 }, |
daf9df6d | 3323 | { 0x05, 0x8330 }, |
3324 | { 0x06, 0x669a }, | |
3325 | ||
3326 | { 0x1f, 0x0002 } | |
3327 | }; | |
3328 | int val; | |
3329 | ||
4da19633 | 3330 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
daf9df6d | 3331 | |
4da19633 | 3332 | val = rtl_readphy(tp, 0x0d); |
daf9df6d | 3333 | if ((val & 0x00ff) != 0x006c) { |
b6bc7650 | 3334 | static const u32 set[] = { |
daf9df6d | 3335 | 0x0065, 0x0066, 0x0067, 0x0068, |
3336 | 0x0069, 0x006a, 0x006b, 0x006c | |
3337 | }; | |
3338 | int i; | |
3339 | ||
4da19633 | 3340 | rtl_writephy(tp, 0x1f, 0x0002); |
daf9df6d | 3341 | |
3342 | val &= 0xff00; | |
3343 | for (i = 0; i < ARRAY_SIZE(set); i++) | |
4da19633 | 3344 | rtl_writephy(tp, 0x0d, val | set[i]); |
daf9df6d | 3345 | } |
3346 | } else { | |
350f7596 | 3347 | static const struct phy_reg phy_reg_init[] = { |
daf9df6d | 3348 | { 0x1f, 0x0002 }, |
3349 | { 0x05, 0x2642 }, | |
5b538df9 | 3350 | { 0x1f, 0x0005 }, |
daf9df6d | 3351 | { 0x05, 0x8330 }, |
3352 | { 0x06, 0x2642 } | |
5b538df9 FR |
3353 | }; |
3354 | ||
4da19633 | 3355 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
5b538df9 FR |
3356 | } |
3357 | ||
bca03d5f | 3358 | /* Fine tune PLL performance */ |
4da19633 | 3359 | rtl_writephy(tp, 0x1f, 0x0002); |
76564428 CHL |
3360 | rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600); |
3361 | rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000); | |
daf9df6d | 3362 | |
bca03d5f | 3363 | /* Switching regulator Slew rate */ |
4da19633 | 3364 | rtl_writephy(tp, 0x1f, 0x0002); |
3365 | rtl_patchphy(tp, 0x0f, 0x0017); | |
daf9df6d | 3366 | |
4da19633 | 3367 | rtl_writephy(tp, 0x1f, 0x0005); |
3368 | rtl_writephy(tp, 0x05, 0x001b); | |
953a12cc FR |
3369 | |
3370 | rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300); | |
bca03d5f | 3371 | |
4da19633 | 3372 | rtl_writephy(tp, 0x1f, 0x0000); |
daf9df6d | 3373 | } |
3374 | ||
4da19633 | 3375 | static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp) |
daf9df6d | 3376 | { |
350f7596 | 3377 | static const struct phy_reg phy_reg_init[] = { |
daf9df6d | 3378 | { 0x1f, 0x0002 }, |
3379 | { 0x10, 0x0008 }, | |
3380 | { 0x0d, 0x006c }, | |
3381 | ||
3382 | { 0x1f, 0x0000 }, | |
3383 | { 0x0d, 0xf880 }, | |
3384 | ||
3385 | { 0x1f, 0x0001 }, | |
3386 | { 0x17, 0x0cc0 }, | |
3387 | ||
3388 | { 0x1f, 0x0001 }, | |
3389 | { 0x0b, 0xa4d8 }, | |
3390 | { 0x09, 0x281c }, | |
3391 | { 0x07, 0x2883 }, | |
3392 | { 0x0a, 0x6b35 }, | |
3393 | { 0x1d, 0x3da4 }, | |
3394 | { 0x1c, 0xeffd }, | |
3395 | { 0x14, 0x7f52 }, | |
3396 | { 0x18, 0x7fc6 }, | |
3397 | { 0x08, 0x0601 }, | |
3398 | { 0x06, 0x4063 }, | |
3399 | { 0x10, 0xf074 }, | |
3400 | { 0x1f, 0x0003 }, | |
3401 | { 0x13, 0x0789 }, | |
3402 | { 0x12, 0xf4bd }, | |
3403 | { 0x1a, 0x04fd }, | |
3404 | { 0x14, 0x84b0 }, | |
3405 | { 0x1f, 0x0000 }, | |
3406 | { 0x00, 0x9200 }, | |
3407 | ||
3408 | { 0x1f, 0x0005 }, | |
3409 | { 0x01, 0x0340 }, | |
3410 | { 0x1f, 0x0001 }, | |
3411 | { 0x04, 0x4000 }, | |
3412 | { 0x03, 0x1d21 }, | |
3413 | { 0x02, 0x0c32 }, | |
3414 | { 0x01, 0x0200 }, | |
3415 | { 0x00, 0x5554 }, | |
3416 | { 0x04, 0x4800 }, | |
3417 | { 0x04, 0x4000 }, | |
3418 | { 0x04, 0xf000 }, | |
3419 | { 0x03, 0xdf01 }, | |
3420 | { 0x02, 0xdf20 }, | |
3421 | { 0x01, 0x101a }, | |
3422 | { 0x00, 0xa0ff }, | |
3423 | { 0x04, 0xf800 }, | |
3424 | { 0x04, 0xf000 }, | |
3425 | { 0x1f, 0x0000 }, | |
3426 | ||
3427 | { 0x1f, 0x0007 }, | |
3428 | { 0x1e, 0x0023 }, | |
3429 | { 0x16, 0x0000 }, | |
3430 | { 0x1f, 0x0000 } | |
3431 | }; | |
3432 | ||
4da19633 | 3433 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
5b538df9 FR |
3434 | } |
3435 | ||
e6de30d6 | 3436 | static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp) |
3437 | { | |
3438 | static const struct phy_reg phy_reg_init[] = { | |
3439 | { 0x1f, 0x0001 }, | |
3440 | { 0x17, 0x0cc0 }, | |
3441 | ||
3442 | { 0x1f, 0x0007 }, | |
3443 | { 0x1e, 0x002d }, | |
3444 | { 0x18, 0x0040 }, | |
3445 | { 0x1f, 0x0000 } | |
3446 | }; | |
3447 | ||
3448 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | |
3449 | rtl_patchphy(tp, 0x0d, 1 << 5); | |
3450 | } | |
3451 | ||
70090424 | 3452 | static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp) |
01dc7fec | 3453 | { |
3454 | static const struct phy_reg phy_reg_init[] = { | |
3455 | /* Enable Delay cap */ | |
3456 | { 0x1f, 0x0005 }, | |
3457 | { 0x05, 0x8b80 }, | |
3458 | { 0x06, 0xc896 }, | |
3459 | { 0x1f, 0x0000 }, | |
3460 | ||
3461 | /* Channel estimation fine tune */ | |
3462 | { 0x1f, 0x0001 }, | |
3463 | { 0x0b, 0x6c20 }, | |
3464 | { 0x07, 0x2872 }, | |
3465 | { 0x1c, 0xefff }, | |
3466 | { 0x1f, 0x0003 }, | |
3467 | { 0x14, 0x6420 }, | |
3468 | { 0x1f, 0x0000 }, | |
3469 | ||
3470 | /* Update PFM & 10M TX idle timer */ | |
3471 | { 0x1f, 0x0007 }, | |
3472 | { 0x1e, 0x002f }, | |
3473 | { 0x15, 0x1919 }, | |
3474 | { 0x1f, 0x0000 }, | |
3475 | ||
3476 | { 0x1f, 0x0007 }, | |
3477 | { 0x1e, 0x00ac }, | |
3478 | { 0x18, 0x0006 }, | |
3479 | { 0x1f, 0x0000 } | |
3480 | }; | |
3481 | ||
15ecd039 FR |
3482 | rtl_apply_firmware(tp); |
3483 | ||
01dc7fec | 3484 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
3485 | ||
3486 | /* DCO enable for 10M IDLE Power */ | |
3487 | rtl_writephy(tp, 0x1f, 0x0007); | |
3488 | rtl_writephy(tp, 0x1e, 0x0023); | |
76564428 | 3489 | rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000); |
01dc7fec | 3490 | rtl_writephy(tp, 0x1f, 0x0000); |
3491 | ||
3492 | /* For impedance matching */ | |
3493 | rtl_writephy(tp, 0x1f, 0x0002); | |
76564428 | 3494 | rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00); |
cecb5fd7 | 3495 | rtl_writephy(tp, 0x1f, 0x0000); |
01dc7fec | 3496 | |
3497 | /* PHY auto speed down */ | |
3498 | rtl_writephy(tp, 0x1f, 0x0007); | |
3499 | rtl_writephy(tp, 0x1e, 0x002d); | |
76564428 | 3500 | rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000); |
01dc7fec | 3501 | rtl_writephy(tp, 0x1f, 0x0000); |
76564428 | 3502 | rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000); |
01dc7fec | 3503 | |
3504 | rtl_writephy(tp, 0x1f, 0x0005); | |
3505 | rtl_writephy(tp, 0x05, 0x8b86); | |
76564428 | 3506 | rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000); |
01dc7fec | 3507 | rtl_writephy(tp, 0x1f, 0x0000); |
3508 | ||
3509 | rtl_writephy(tp, 0x1f, 0x0005); | |
3510 | rtl_writephy(tp, 0x05, 0x8b85); | |
76564428 | 3511 | rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000); |
01dc7fec | 3512 | rtl_writephy(tp, 0x1f, 0x0007); |
3513 | rtl_writephy(tp, 0x1e, 0x0020); | |
76564428 | 3514 | rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100); |
01dc7fec | 3515 | rtl_writephy(tp, 0x1f, 0x0006); |
3516 | rtl_writephy(tp, 0x00, 0x5a00); | |
3517 | rtl_writephy(tp, 0x1f, 0x0000); | |
3518 | rtl_writephy(tp, 0x0d, 0x0007); | |
3519 | rtl_writephy(tp, 0x0e, 0x003c); | |
3520 | rtl_writephy(tp, 0x0d, 0x4007); | |
3521 | rtl_writephy(tp, 0x0e, 0x0000); | |
3522 | rtl_writephy(tp, 0x0d, 0x0000); | |
3523 | } | |
3524 | ||
9ecb9aab | 3525 | static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr) |
3526 | { | |
3527 | const u16 w[] = { | |
3528 | addr[0] | (addr[1] << 8), | |
3529 | addr[2] | (addr[3] << 8), | |
3530 | addr[4] | (addr[5] << 8) | |
3531 | }; | |
3532 | const struct exgmac_reg e[] = { | |
3533 | { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) }, | |
3534 | { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] }, | |
3535 | { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 }, | |
3536 | { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) } | |
3537 | }; | |
3538 | ||
3539 | rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e)); | |
3540 | } | |
3541 | ||
70090424 HW |
3542 | static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp) |
3543 | { | |
3544 | static const struct phy_reg phy_reg_init[] = { | |
3545 | /* Enable Delay cap */ | |
3546 | { 0x1f, 0x0004 }, | |
3547 | { 0x1f, 0x0007 }, | |
3548 | { 0x1e, 0x00ac }, | |
3549 | { 0x18, 0x0006 }, | |
3550 | { 0x1f, 0x0002 }, | |
3551 | { 0x1f, 0x0000 }, | |
3552 | { 0x1f, 0x0000 }, | |
3553 | ||
3554 | /* Channel estimation fine tune */ | |
3555 | { 0x1f, 0x0003 }, | |
3556 | { 0x09, 0xa20f }, | |
3557 | { 0x1f, 0x0000 }, | |
3558 | { 0x1f, 0x0000 }, | |
3559 | ||
3560 | /* Green Setting */ | |
3561 | { 0x1f, 0x0005 }, | |
3562 | { 0x05, 0x8b5b }, | |
3563 | { 0x06, 0x9222 }, | |
3564 | { 0x05, 0x8b6d }, | |
3565 | { 0x06, 0x8000 }, | |
3566 | { 0x05, 0x8b76 }, | |
3567 | { 0x06, 0x8000 }, | |
3568 | { 0x1f, 0x0000 } | |
3569 | }; | |
3570 | ||
3571 | rtl_apply_firmware(tp); | |
3572 | ||
3573 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | |
3574 | ||
3575 | /* For 4-corner performance improve */ | |
3576 | rtl_writephy(tp, 0x1f, 0x0005); | |
3577 | rtl_writephy(tp, 0x05, 0x8b80); | |
76564428 | 3578 | rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000); |
70090424 HW |
3579 | rtl_writephy(tp, 0x1f, 0x0000); |
3580 | ||
3581 | /* PHY auto speed down */ | |
3582 | rtl_writephy(tp, 0x1f, 0x0004); | |
3583 | rtl_writephy(tp, 0x1f, 0x0007); | |
3584 | rtl_writephy(tp, 0x1e, 0x002d); | |
76564428 | 3585 | rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000); |
70090424 HW |
3586 | rtl_writephy(tp, 0x1f, 0x0002); |
3587 | rtl_writephy(tp, 0x1f, 0x0000); | |
76564428 | 3588 | rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000); |
70090424 HW |
3589 | |
3590 | /* improve 10M EEE waveform */ | |
3591 | rtl_writephy(tp, 0x1f, 0x0005); | |
3592 | rtl_writephy(tp, 0x05, 0x8b86); | |
76564428 | 3593 | rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000); |
70090424 HW |
3594 | rtl_writephy(tp, 0x1f, 0x0000); |
3595 | ||
3596 | /* Improve 2-pair detection performance */ | |
3597 | rtl_writephy(tp, 0x1f, 0x0005); | |
3598 | rtl_writephy(tp, 0x05, 0x8b85); | |
76564428 | 3599 | rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000); |
70090424 HW |
3600 | rtl_writephy(tp, 0x1f, 0x0000); |
3601 | ||
3602 | /* EEE setting */ | |
1814d6a8 | 3603 | rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0003, 0x0000, ERIAR_EXGMAC); |
70090424 HW |
3604 | rtl_writephy(tp, 0x1f, 0x0005); |
3605 | rtl_writephy(tp, 0x05, 0x8b85); | |
1814d6a8 | 3606 | rtl_w0w1_phy(tp, 0x06, 0x2000, 0x0000); |
70090424 HW |
3607 | rtl_writephy(tp, 0x1f, 0x0004); |
3608 | rtl_writephy(tp, 0x1f, 0x0007); | |
3609 | rtl_writephy(tp, 0x1e, 0x0020); | |
1814d6a8 | 3610 | rtl_w0w1_phy(tp, 0x15, 0x0100, 0x0000); |
70090424 HW |
3611 | rtl_writephy(tp, 0x1f, 0x0002); |
3612 | rtl_writephy(tp, 0x1f, 0x0000); | |
3613 | rtl_writephy(tp, 0x0d, 0x0007); | |
3614 | rtl_writephy(tp, 0x0e, 0x003c); | |
3615 | rtl_writephy(tp, 0x0d, 0x4007); | |
1814d6a8 | 3616 | rtl_writephy(tp, 0x0e, 0x0006); |
70090424 HW |
3617 | rtl_writephy(tp, 0x0d, 0x0000); |
3618 | ||
3619 | /* Green feature */ | |
3620 | rtl_writephy(tp, 0x1f, 0x0003); | |
1814d6a8 HK |
3621 | rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000); |
3622 | rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000); | |
70090424 | 3623 | rtl_writephy(tp, 0x1f, 0x0000); |
b399a394 HK |
3624 | rtl_writephy(tp, 0x1f, 0x0005); |
3625 | rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000); | |
3626 | rtl_writephy(tp, 0x1f, 0x0000); | |
e0c07557 | 3627 | |
9ecb9aab | 3628 | /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */ |
3629 | rtl_rar_exgmac_set(tp, tp->dev->dev_addr); | |
70090424 HW |
3630 | } |
3631 | ||
5f886e08 HW |
3632 | static void rtl8168f_hw_phy_config(struct rtl8169_private *tp) |
3633 | { | |
3634 | /* For 4-corner performance improve */ | |
3635 | rtl_writephy(tp, 0x1f, 0x0005); | |
3636 | rtl_writephy(tp, 0x05, 0x8b80); | |
76564428 | 3637 | rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000); |
5f886e08 HW |
3638 | rtl_writephy(tp, 0x1f, 0x0000); |
3639 | ||
3640 | /* PHY auto speed down */ | |
3641 | rtl_writephy(tp, 0x1f, 0x0007); | |
3642 | rtl_writephy(tp, 0x1e, 0x002d); | |
76564428 | 3643 | rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000); |
5f886e08 | 3644 | rtl_writephy(tp, 0x1f, 0x0000); |
76564428 | 3645 | rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000); |
5f886e08 HW |
3646 | |
3647 | /* Improve 10M EEE waveform */ | |
3648 | rtl_writephy(tp, 0x1f, 0x0005); | |
3649 | rtl_writephy(tp, 0x05, 0x8b86); | |
76564428 | 3650 | rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000); |
5f886e08 HW |
3651 | rtl_writephy(tp, 0x1f, 0x0000); |
3652 | } | |
3653 | ||
c2218925 HW |
3654 | static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp) |
3655 | { | |
3656 | static const struct phy_reg phy_reg_init[] = { | |
3657 | /* Channel estimation fine tune */ | |
3658 | { 0x1f, 0x0003 }, | |
3659 | { 0x09, 0xa20f }, | |
3660 | { 0x1f, 0x0000 }, | |
3661 | ||
3662 | /* Modify green table for giga & fnet */ | |
3663 | { 0x1f, 0x0005 }, | |
3664 | { 0x05, 0x8b55 }, | |
3665 | { 0x06, 0x0000 }, | |
3666 | { 0x05, 0x8b5e }, | |
3667 | { 0x06, 0x0000 }, | |
3668 | { 0x05, 0x8b67 }, | |
3669 | { 0x06, 0x0000 }, | |
3670 | { 0x05, 0x8b70 }, | |
3671 | { 0x06, 0x0000 }, | |
3672 | { 0x1f, 0x0000 }, | |
3673 | { 0x1f, 0x0007 }, | |
3674 | { 0x1e, 0x0078 }, | |
3675 | { 0x17, 0x0000 }, | |
3676 | { 0x19, 0x00fb }, | |
3677 | { 0x1f, 0x0000 }, | |
3678 | ||
3679 | /* Modify green table for 10M */ | |
3680 | { 0x1f, 0x0005 }, | |
3681 | { 0x05, 0x8b79 }, | |
3682 | { 0x06, 0xaa00 }, | |
3683 | { 0x1f, 0x0000 }, | |
3684 | ||
3685 | /* Disable hiimpedance detection (RTCT) */ | |
3686 | { 0x1f, 0x0003 }, | |
3687 | { 0x01, 0x328a }, | |
3688 | { 0x1f, 0x0000 } | |
3689 | }; | |
3690 | ||
3691 | rtl_apply_firmware(tp); | |
3692 | ||
3693 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | |
3694 | ||
5f886e08 | 3695 | rtl8168f_hw_phy_config(tp); |
c2218925 HW |
3696 | |
3697 | /* Improve 2-pair detection performance */ | |
3698 | rtl_writephy(tp, 0x1f, 0x0005); | |
3699 | rtl_writephy(tp, 0x05, 0x8b85); | |
76564428 | 3700 | rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000); |
c2218925 HW |
3701 | rtl_writephy(tp, 0x1f, 0x0000); |
3702 | } | |
3703 | ||
3704 | static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp) | |
3705 | { | |
3706 | rtl_apply_firmware(tp); | |
3707 | ||
5f886e08 | 3708 | rtl8168f_hw_phy_config(tp); |
c2218925 HW |
3709 | } |
3710 | ||
b3d7b2f2 HW |
3711 | static void rtl8411_hw_phy_config(struct rtl8169_private *tp) |
3712 | { | |
b3d7b2f2 HW |
3713 | static const struct phy_reg phy_reg_init[] = { |
3714 | /* Channel estimation fine tune */ | |
3715 | { 0x1f, 0x0003 }, | |
3716 | { 0x09, 0xa20f }, | |
3717 | { 0x1f, 0x0000 }, | |
3718 | ||
3719 | /* Modify green table for giga & fnet */ | |
3720 | { 0x1f, 0x0005 }, | |
3721 | { 0x05, 0x8b55 }, | |
3722 | { 0x06, 0x0000 }, | |
3723 | { 0x05, 0x8b5e }, | |
3724 | { 0x06, 0x0000 }, | |
3725 | { 0x05, 0x8b67 }, | |
3726 | { 0x06, 0x0000 }, | |
3727 | { 0x05, 0x8b70 }, | |
3728 | { 0x06, 0x0000 }, | |
3729 | { 0x1f, 0x0000 }, | |
3730 | { 0x1f, 0x0007 }, | |
3731 | { 0x1e, 0x0078 }, | |
3732 | { 0x17, 0x0000 }, | |
3733 | { 0x19, 0x00aa }, | |
3734 | { 0x1f, 0x0000 }, | |
3735 | ||
3736 | /* Modify green table for 10M */ | |
3737 | { 0x1f, 0x0005 }, | |
3738 | { 0x05, 0x8b79 }, | |
3739 | { 0x06, 0xaa00 }, | |
3740 | { 0x1f, 0x0000 }, | |
3741 | ||
3742 | /* Disable hiimpedance detection (RTCT) */ | |
3743 | { 0x1f, 0x0003 }, | |
3744 | { 0x01, 0x328a }, | |
3745 | { 0x1f, 0x0000 } | |
3746 | }; | |
3747 | ||
3748 | ||
3749 | rtl_apply_firmware(tp); | |
3750 | ||
3751 | rtl8168f_hw_phy_config(tp); | |
3752 | ||
3753 | /* Improve 2-pair detection performance */ | |
3754 | rtl_writephy(tp, 0x1f, 0x0005); | |
3755 | rtl_writephy(tp, 0x05, 0x8b85); | |
76564428 | 3756 | rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000); |
b3d7b2f2 HW |
3757 | rtl_writephy(tp, 0x1f, 0x0000); |
3758 | ||
3759 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | |
3760 | ||
3761 | /* Modify green table for giga */ | |
3762 | rtl_writephy(tp, 0x1f, 0x0005); | |
3763 | rtl_writephy(tp, 0x05, 0x8b54); | |
76564428 | 3764 | rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800); |
b3d7b2f2 | 3765 | rtl_writephy(tp, 0x05, 0x8b5d); |
76564428 | 3766 | rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800); |
b3d7b2f2 | 3767 | rtl_writephy(tp, 0x05, 0x8a7c); |
76564428 | 3768 | rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100); |
b3d7b2f2 | 3769 | rtl_writephy(tp, 0x05, 0x8a7f); |
76564428 | 3770 | rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000); |
b3d7b2f2 | 3771 | rtl_writephy(tp, 0x05, 0x8a82); |
76564428 | 3772 | rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100); |
b3d7b2f2 | 3773 | rtl_writephy(tp, 0x05, 0x8a85); |
76564428 | 3774 | rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100); |
b3d7b2f2 | 3775 | rtl_writephy(tp, 0x05, 0x8a88); |
76564428 | 3776 | rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100); |
b3d7b2f2 HW |
3777 | rtl_writephy(tp, 0x1f, 0x0000); |
3778 | ||
3779 | /* uc same-seed solution */ | |
3780 | rtl_writephy(tp, 0x1f, 0x0005); | |
3781 | rtl_writephy(tp, 0x05, 0x8b85); | |
76564428 | 3782 | rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000); |
b3d7b2f2 HW |
3783 | rtl_writephy(tp, 0x1f, 0x0000); |
3784 | ||
3785 | /* eee setting */ | |
706123d0 | 3786 | rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC); |
b3d7b2f2 HW |
3787 | rtl_writephy(tp, 0x1f, 0x0005); |
3788 | rtl_writephy(tp, 0x05, 0x8b85); | |
76564428 | 3789 | rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000); |
b3d7b2f2 HW |
3790 | rtl_writephy(tp, 0x1f, 0x0004); |
3791 | rtl_writephy(tp, 0x1f, 0x0007); | |
3792 | rtl_writephy(tp, 0x1e, 0x0020); | |
76564428 | 3793 | rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100); |
b3d7b2f2 HW |
3794 | rtl_writephy(tp, 0x1f, 0x0000); |
3795 | rtl_writephy(tp, 0x0d, 0x0007); | |
3796 | rtl_writephy(tp, 0x0e, 0x003c); | |
3797 | rtl_writephy(tp, 0x0d, 0x4007); | |
3798 | rtl_writephy(tp, 0x0e, 0x0000); | |
3799 | rtl_writephy(tp, 0x0d, 0x0000); | |
3800 | ||
3801 | /* Green feature */ | |
3802 | rtl_writephy(tp, 0x1f, 0x0003); | |
76564428 CHL |
3803 | rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001); |
3804 | rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400); | |
b3d7b2f2 HW |
3805 | rtl_writephy(tp, 0x1f, 0x0000); |
3806 | } | |
3807 | ||
c558386b HW |
3808 | static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp) |
3809 | { | |
c558386b HW |
3810 | rtl_apply_firmware(tp); |
3811 | ||
41f44d13 | 3812 | rtl_writephy(tp, 0x1f, 0x0a46); |
3813 | if (rtl_readphy(tp, 0x10) & 0x0100) { | |
3814 | rtl_writephy(tp, 0x1f, 0x0bcc); | |
76564428 | 3815 | rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000); |
41f44d13 | 3816 | } else { |
3817 | rtl_writephy(tp, 0x1f, 0x0bcc); | |
76564428 | 3818 | rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000); |
41f44d13 | 3819 | } |
c558386b | 3820 | |
41f44d13 | 3821 | rtl_writephy(tp, 0x1f, 0x0a46); |
3822 | if (rtl_readphy(tp, 0x13) & 0x0100) { | |
3823 | rtl_writephy(tp, 0x1f, 0x0c41); | |
76564428 | 3824 | rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000); |
41f44d13 | 3825 | } else { |
fe7524c0 | 3826 | rtl_writephy(tp, 0x1f, 0x0c41); |
76564428 | 3827 | rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002); |
41f44d13 | 3828 | } |
c558386b | 3829 | |
41f44d13 | 3830 | /* Enable PHY auto speed down */ |
3831 | rtl_writephy(tp, 0x1f, 0x0a44); | |
76564428 | 3832 | rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000); |
c558386b | 3833 | |
fe7524c0 | 3834 | rtl_writephy(tp, 0x1f, 0x0bcc); |
76564428 | 3835 | rtl_w0w1_phy(tp, 0x14, 0x0100, 0x0000); |
fe7524c0 | 3836 | rtl_writephy(tp, 0x1f, 0x0a44); |
76564428 | 3837 | rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000); |
fe7524c0 | 3838 | rtl_writephy(tp, 0x1f, 0x0a43); |
3839 | rtl_writephy(tp, 0x13, 0x8084); | |
76564428 CHL |
3840 | rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000); |
3841 | rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000); | |
fe7524c0 | 3842 | |
41f44d13 | 3843 | /* EEE auto-fallback function */ |
3844 | rtl_writephy(tp, 0x1f, 0x0a4b); | |
76564428 | 3845 | rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000); |
c558386b | 3846 | |
41f44d13 | 3847 | /* Enable UC LPF tune function */ |
3848 | rtl_writephy(tp, 0x1f, 0x0a43); | |
3849 | rtl_writephy(tp, 0x13, 0x8012); | |
76564428 | 3850 | rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000); |
41f44d13 | 3851 | |
3852 | rtl_writephy(tp, 0x1f, 0x0c42); | |
76564428 | 3853 | rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000); |
41f44d13 | 3854 | |
fe7524c0 | 3855 | /* Improve SWR Efficiency */ |
3856 | rtl_writephy(tp, 0x1f, 0x0bcd); | |
3857 | rtl_writephy(tp, 0x14, 0x5065); | |
3858 | rtl_writephy(tp, 0x14, 0xd065); | |
3859 | rtl_writephy(tp, 0x1f, 0x0bc8); | |
3860 | rtl_writephy(tp, 0x11, 0x5655); | |
3861 | rtl_writephy(tp, 0x1f, 0x0bcd); | |
3862 | rtl_writephy(tp, 0x14, 0x1065); | |
3863 | rtl_writephy(tp, 0x14, 0x9065); | |
3864 | rtl_writephy(tp, 0x14, 0x1065); | |
3865 | ||
1bac1072 DC |
3866 | /* Check ALDPS bit, disable it if enabled */ |
3867 | rtl_writephy(tp, 0x1f, 0x0a43); | |
3868 | if (rtl_readphy(tp, 0x10) & 0x0004) | |
76564428 | 3869 | rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004); |
1bac1072 | 3870 | |
41f44d13 | 3871 | rtl_writephy(tp, 0x1f, 0x0000); |
c558386b HW |
3872 | } |
3873 | ||
57538c4a | 3874 | static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp) |
3875 | { | |
3876 | rtl_apply_firmware(tp); | |
3877 | } | |
3878 | ||
6e1d0b89 CHL |
3879 | static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp) |
3880 | { | |
3881 | u16 dout_tapbin; | |
3882 | u32 data; | |
3883 | ||
3884 | rtl_apply_firmware(tp); | |
3885 | ||
3886 | /* CHN EST parameters adjust - giga master */ | |
3887 | rtl_writephy(tp, 0x1f, 0x0a43); | |
3888 | rtl_writephy(tp, 0x13, 0x809b); | |
76564428 | 3889 | rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800); |
6e1d0b89 | 3890 | rtl_writephy(tp, 0x13, 0x80a2); |
76564428 | 3891 | rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00); |
6e1d0b89 | 3892 | rtl_writephy(tp, 0x13, 0x80a4); |
76564428 | 3893 | rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00); |
6e1d0b89 | 3894 | rtl_writephy(tp, 0x13, 0x809c); |
76564428 | 3895 | rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00); |
6e1d0b89 CHL |
3896 | rtl_writephy(tp, 0x1f, 0x0000); |
3897 | ||
3898 | /* CHN EST parameters adjust - giga slave */ | |
3899 | rtl_writephy(tp, 0x1f, 0x0a43); | |
3900 | rtl_writephy(tp, 0x13, 0x80ad); | |
76564428 | 3901 | rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800); |
6e1d0b89 | 3902 | rtl_writephy(tp, 0x13, 0x80b4); |
76564428 | 3903 | rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00); |
6e1d0b89 | 3904 | rtl_writephy(tp, 0x13, 0x80ac); |
76564428 | 3905 | rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00); |
6e1d0b89 CHL |
3906 | rtl_writephy(tp, 0x1f, 0x0000); |
3907 | ||
3908 | /* CHN EST parameters adjust - fnet */ | |
3909 | rtl_writephy(tp, 0x1f, 0x0a43); | |
3910 | rtl_writephy(tp, 0x13, 0x808e); | |
76564428 | 3911 | rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00); |
6e1d0b89 | 3912 | rtl_writephy(tp, 0x13, 0x8090); |
76564428 | 3913 | rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00); |
6e1d0b89 | 3914 | rtl_writephy(tp, 0x13, 0x8092); |
76564428 | 3915 | rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00); |
6e1d0b89 CHL |
3916 | rtl_writephy(tp, 0x1f, 0x0000); |
3917 | ||
3918 | /* enable R-tune & PGA-retune function */ | |
3919 | dout_tapbin = 0; | |
3920 | rtl_writephy(tp, 0x1f, 0x0a46); | |
3921 | data = rtl_readphy(tp, 0x13); | |
3922 | data &= 3; | |
3923 | data <<= 2; | |
3924 | dout_tapbin |= data; | |
3925 | data = rtl_readphy(tp, 0x12); | |
3926 | data &= 0xc000; | |
3927 | data >>= 14; | |
3928 | dout_tapbin |= data; | |
3929 | dout_tapbin = ~(dout_tapbin^0x08); | |
3930 | dout_tapbin <<= 12; | |
3931 | dout_tapbin &= 0xf000; | |
3932 | rtl_writephy(tp, 0x1f, 0x0a43); | |
3933 | rtl_writephy(tp, 0x13, 0x827a); | |
76564428 | 3934 | rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000); |
6e1d0b89 | 3935 | rtl_writephy(tp, 0x13, 0x827b); |
76564428 | 3936 | rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000); |
6e1d0b89 | 3937 | rtl_writephy(tp, 0x13, 0x827c); |
76564428 | 3938 | rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000); |
6e1d0b89 | 3939 | rtl_writephy(tp, 0x13, 0x827d); |
76564428 | 3940 | rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000); |
6e1d0b89 CHL |
3941 | |
3942 | rtl_writephy(tp, 0x1f, 0x0a43); | |
3943 | rtl_writephy(tp, 0x13, 0x0811); | |
76564428 | 3944 | rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000); |
6e1d0b89 | 3945 | rtl_writephy(tp, 0x1f, 0x0a42); |
76564428 | 3946 | rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000); |
6e1d0b89 CHL |
3947 | rtl_writephy(tp, 0x1f, 0x0000); |
3948 | ||
3949 | /* enable GPHY 10M */ | |
3950 | rtl_writephy(tp, 0x1f, 0x0a44); | |
76564428 | 3951 | rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000); |
6e1d0b89 CHL |
3952 | rtl_writephy(tp, 0x1f, 0x0000); |
3953 | ||
3954 | /* SAR ADC performance */ | |
3955 | rtl_writephy(tp, 0x1f, 0x0bca); | |
76564428 | 3956 | rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000); |
6e1d0b89 CHL |
3957 | rtl_writephy(tp, 0x1f, 0x0000); |
3958 | ||
3959 | rtl_writephy(tp, 0x1f, 0x0a43); | |
3960 | rtl_writephy(tp, 0x13, 0x803f); | |
76564428 | 3961 | rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000); |
6e1d0b89 | 3962 | rtl_writephy(tp, 0x13, 0x8047); |
76564428 | 3963 | rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000); |
6e1d0b89 | 3964 | rtl_writephy(tp, 0x13, 0x804f); |
76564428 | 3965 | rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000); |
6e1d0b89 | 3966 | rtl_writephy(tp, 0x13, 0x8057); |
76564428 | 3967 | rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000); |
6e1d0b89 | 3968 | rtl_writephy(tp, 0x13, 0x805f); |
76564428 | 3969 | rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000); |
6e1d0b89 | 3970 | rtl_writephy(tp, 0x13, 0x8067); |
76564428 | 3971 | rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000); |
6e1d0b89 | 3972 | rtl_writephy(tp, 0x13, 0x806f); |
76564428 | 3973 | rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000); |
6e1d0b89 CHL |
3974 | rtl_writephy(tp, 0x1f, 0x0000); |
3975 | ||
3976 | /* disable phy pfm mode */ | |
3977 | rtl_writephy(tp, 0x1f, 0x0a44); | |
c832c35f | 3978 | rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080); |
6e1d0b89 CHL |
3979 | rtl_writephy(tp, 0x1f, 0x0000); |
3980 | ||
3981 | /* Check ALDPS bit, disable it if enabled */ | |
3982 | rtl_writephy(tp, 0x1f, 0x0a43); | |
3983 | if (rtl_readphy(tp, 0x10) & 0x0004) | |
76564428 | 3984 | rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004); |
6e1d0b89 CHL |
3985 | |
3986 | rtl_writephy(tp, 0x1f, 0x0000); | |
3987 | } | |
3988 | ||
3989 | static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp) | |
3990 | { | |
3991 | u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0; | |
3992 | u16 rlen; | |
3993 | u32 data; | |
3994 | ||
3995 | rtl_apply_firmware(tp); | |
3996 | ||
3997 | /* CHIN EST parameter update */ | |
3998 | rtl_writephy(tp, 0x1f, 0x0a43); | |
3999 | rtl_writephy(tp, 0x13, 0x808a); | |
76564428 | 4000 | rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f); |
6e1d0b89 CHL |
4001 | rtl_writephy(tp, 0x1f, 0x0000); |
4002 | ||
4003 | /* enable R-tune & PGA-retune function */ | |
4004 | rtl_writephy(tp, 0x1f, 0x0a43); | |
4005 | rtl_writephy(tp, 0x13, 0x0811); | |
76564428 | 4006 | rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000); |
6e1d0b89 | 4007 | rtl_writephy(tp, 0x1f, 0x0a42); |
76564428 | 4008 | rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000); |
6e1d0b89 CHL |
4009 | rtl_writephy(tp, 0x1f, 0x0000); |
4010 | ||
4011 | /* enable GPHY 10M */ | |
4012 | rtl_writephy(tp, 0x1f, 0x0a44); | |
76564428 | 4013 | rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000); |
6e1d0b89 CHL |
4014 | rtl_writephy(tp, 0x1f, 0x0000); |
4015 | ||
4016 | r8168_mac_ocp_write(tp, 0xdd02, 0x807d); | |
4017 | data = r8168_mac_ocp_read(tp, 0xdd02); | |
4018 | ioffset_p3 = ((data & 0x80)>>7); | |
4019 | ioffset_p3 <<= 3; | |
4020 | ||
4021 | data = r8168_mac_ocp_read(tp, 0xdd00); | |
4022 | ioffset_p3 |= ((data & (0xe000))>>13); | |
4023 | ioffset_p2 = ((data & (0x1e00))>>9); | |
4024 | ioffset_p1 = ((data & (0x01e0))>>5); | |
4025 | ioffset_p0 = ((data & 0x0010)>>4); | |
4026 | ioffset_p0 <<= 3; | |
4027 | ioffset_p0 |= (data & (0x07)); | |
4028 | data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0); | |
4029 | ||
05b9687b | 4030 | if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) || |
e2e2788e | 4031 | (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) { |
6e1d0b89 CHL |
4032 | rtl_writephy(tp, 0x1f, 0x0bcf); |
4033 | rtl_writephy(tp, 0x16, data); | |
4034 | rtl_writephy(tp, 0x1f, 0x0000); | |
4035 | } | |
4036 | ||
4037 | /* Modify rlen (TX LPF corner frequency) level */ | |
4038 | rtl_writephy(tp, 0x1f, 0x0bcd); | |
4039 | data = rtl_readphy(tp, 0x16); | |
4040 | data &= 0x000f; | |
4041 | rlen = 0; | |
4042 | if (data > 3) | |
4043 | rlen = data - 3; | |
4044 | data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12); | |
4045 | rtl_writephy(tp, 0x17, data); | |
4046 | rtl_writephy(tp, 0x1f, 0x0bcd); | |
4047 | rtl_writephy(tp, 0x1f, 0x0000); | |
4048 | ||
4049 | /* disable phy pfm mode */ | |
4050 | rtl_writephy(tp, 0x1f, 0x0a44); | |
c832c35f | 4051 | rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080); |
6e1d0b89 CHL |
4052 | rtl_writephy(tp, 0x1f, 0x0000); |
4053 | ||
4054 | /* Check ALDPS bit, disable it if enabled */ | |
4055 | rtl_writephy(tp, 0x1f, 0x0a43); | |
4056 | if (rtl_readphy(tp, 0x10) & 0x0004) | |
76564428 | 4057 | rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004); |
6e1d0b89 CHL |
4058 | |
4059 | rtl_writephy(tp, 0x1f, 0x0000); | |
4060 | } | |
4061 | ||
935e2218 CHL |
4062 | static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp) |
4063 | { | |
4064 | /* Enable PHY auto speed down */ | |
4065 | rtl_writephy(tp, 0x1f, 0x0a44); | |
4066 | rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000); | |
4067 | rtl_writephy(tp, 0x1f, 0x0000); | |
4068 | ||
4069 | /* patch 10M & ALDPS */ | |
4070 | rtl_writephy(tp, 0x1f, 0x0bcc); | |
4071 | rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100); | |
4072 | rtl_writephy(tp, 0x1f, 0x0a44); | |
4073 | rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000); | |
4074 | rtl_writephy(tp, 0x1f, 0x0a43); | |
4075 | rtl_writephy(tp, 0x13, 0x8084); | |
4076 | rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000); | |
4077 | rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000); | |
4078 | rtl_writephy(tp, 0x1f, 0x0000); | |
4079 | ||
4080 | /* Enable EEE auto-fallback function */ | |
4081 | rtl_writephy(tp, 0x1f, 0x0a4b); | |
4082 | rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000); | |
4083 | rtl_writephy(tp, 0x1f, 0x0000); | |
4084 | ||
4085 | /* Enable UC LPF tune function */ | |
4086 | rtl_writephy(tp, 0x1f, 0x0a43); | |
4087 | rtl_writephy(tp, 0x13, 0x8012); | |
4088 | rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000); | |
4089 | rtl_writephy(tp, 0x1f, 0x0000); | |
4090 | ||
4091 | /* set rg_sel_sdm_rate */ | |
4092 | rtl_writephy(tp, 0x1f, 0x0c42); | |
4093 | rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000); | |
4094 | rtl_writephy(tp, 0x1f, 0x0000); | |
4095 | ||
4096 | /* Check ALDPS bit, disable it if enabled */ | |
4097 | rtl_writephy(tp, 0x1f, 0x0a43); | |
4098 | if (rtl_readphy(tp, 0x10) & 0x0004) | |
4099 | rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004); | |
4100 | ||
4101 | rtl_writephy(tp, 0x1f, 0x0000); | |
4102 | } | |
4103 | ||
4104 | static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp) | |
4105 | { | |
4106 | /* patch 10M & ALDPS */ | |
4107 | rtl_writephy(tp, 0x1f, 0x0bcc); | |
4108 | rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100); | |
4109 | rtl_writephy(tp, 0x1f, 0x0a44); | |
4110 | rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000); | |
4111 | rtl_writephy(tp, 0x1f, 0x0a43); | |
4112 | rtl_writephy(tp, 0x13, 0x8084); | |
4113 | rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000); | |
4114 | rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000); | |
4115 | rtl_writephy(tp, 0x1f, 0x0000); | |
4116 | ||
4117 | /* Enable UC LPF tune function */ | |
4118 | rtl_writephy(tp, 0x1f, 0x0a43); | |
4119 | rtl_writephy(tp, 0x13, 0x8012); | |
4120 | rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000); | |
4121 | rtl_writephy(tp, 0x1f, 0x0000); | |
4122 | ||
4123 | /* Set rg_sel_sdm_rate */ | |
4124 | rtl_writephy(tp, 0x1f, 0x0c42); | |
4125 | rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000); | |
4126 | rtl_writephy(tp, 0x1f, 0x0000); | |
4127 | ||
4128 | /* Channel estimation parameters */ | |
4129 | rtl_writephy(tp, 0x1f, 0x0a43); | |
4130 | rtl_writephy(tp, 0x13, 0x80f3); | |
4131 | rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff); | |
4132 | rtl_writephy(tp, 0x13, 0x80f0); | |
4133 | rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff); | |
4134 | rtl_writephy(tp, 0x13, 0x80ef); | |
4135 | rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff); | |
4136 | rtl_writephy(tp, 0x13, 0x80f6); | |
4137 | rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff); | |
4138 | rtl_writephy(tp, 0x13, 0x80ec); | |
4139 | rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff); | |
4140 | rtl_writephy(tp, 0x13, 0x80ed); | |
4141 | rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff); | |
4142 | rtl_writephy(tp, 0x13, 0x80f2); | |
4143 | rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff); | |
4144 | rtl_writephy(tp, 0x13, 0x80f4); | |
4145 | rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff); | |
4146 | rtl_writephy(tp, 0x1f, 0x0a43); | |
4147 | rtl_writephy(tp, 0x13, 0x8110); | |
4148 | rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff); | |
4149 | rtl_writephy(tp, 0x13, 0x810f); | |
4150 | rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff); | |
4151 | rtl_writephy(tp, 0x13, 0x8111); | |
4152 | rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff); | |
4153 | rtl_writephy(tp, 0x13, 0x8113); | |
4154 | rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff); | |
4155 | rtl_writephy(tp, 0x13, 0x8115); | |
4156 | rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff); | |
4157 | rtl_writephy(tp, 0x13, 0x810e); | |
4158 | rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff); | |
4159 | rtl_writephy(tp, 0x13, 0x810c); | |
4160 | rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff); | |
4161 | rtl_writephy(tp, 0x13, 0x810b); | |
4162 | rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff); | |
4163 | rtl_writephy(tp, 0x1f, 0x0a43); | |
4164 | rtl_writephy(tp, 0x13, 0x80d1); | |
4165 | rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff); | |
4166 | rtl_writephy(tp, 0x13, 0x80cd); | |
4167 | rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff); | |
4168 | rtl_writephy(tp, 0x13, 0x80d3); | |
4169 | rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff); | |
4170 | rtl_writephy(tp, 0x13, 0x80d5); | |
4171 | rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff); | |
4172 | rtl_writephy(tp, 0x13, 0x80d7); | |
4173 | rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff); | |
4174 | ||
4175 | /* Force PWM-mode */ | |
4176 | rtl_writephy(tp, 0x1f, 0x0bcd); | |
4177 | rtl_writephy(tp, 0x14, 0x5065); | |
4178 | rtl_writephy(tp, 0x14, 0xd065); | |
4179 | rtl_writephy(tp, 0x1f, 0x0bc8); | |
4180 | rtl_writephy(tp, 0x12, 0x00ed); | |
4181 | rtl_writephy(tp, 0x1f, 0x0bcd); | |
4182 | rtl_writephy(tp, 0x14, 0x1065); | |
4183 | rtl_writephy(tp, 0x14, 0x9065); | |
4184 | rtl_writephy(tp, 0x14, 0x1065); | |
4185 | rtl_writephy(tp, 0x1f, 0x0000); | |
4186 | ||
4187 | /* Check ALDPS bit, disable it if enabled */ | |
4188 | rtl_writephy(tp, 0x1f, 0x0a43); | |
4189 | if (rtl_readphy(tp, 0x10) & 0x0004) | |
4190 | rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004); | |
4191 | ||
4192 | rtl_writephy(tp, 0x1f, 0x0000); | |
4193 | } | |
4194 | ||
4da19633 | 4195 | static void rtl8102e_hw_phy_config(struct rtl8169_private *tp) |
2857ffb7 | 4196 | { |
350f7596 | 4197 | static const struct phy_reg phy_reg_init[] = { |
2857ffb7 FR |
4198 | { 0x1f, 0x0003 }, |
4199 | { 0x08, 0x441d }, | |
4200 | { 0x01, 0x9100 }, | |
4201 | { 0x1f, 0x0000 } | |
4202 | }; | |
4203 | ||
4da19633 | 4204 | rtl_writephy(tp, 0x1f, 0x0000); |
4205 | rtl_patchphy(tp, 0x11, 1 << 12); | |
4206 | rtl_patchphy(tp, 0x19, 1 << 13); | |
4207 | rtl_patchphy(tp, 0x10, 1 << 15); | |
2857ffb7 | 4208 | |
4da19633 | 4209 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
2857ffb7 FR |
4210 | } |
4211 | ||
5a5e4443 HW |
4212 | static void rtl8105e_hw_phy_config(struct rtl8169_private *tp) |
4213 | { | |
4214 | static const struct phy_reg phy_reg_init[] = { | |
4215 | { 0x1f, 0x0005 }, | |
4216 | { 0x1a, 0x0000 }, | |
4217 | { 0x1f, 0x0000 }, | |
4218 | ||
4219 | { 0x1f, 0x0004 }, | |
4220 | { 0x1c, 0x0000 }, | |
4221 | { 0x1f, 0x0000 }, | |
4222 | ||
4223 | { 0x1f, 0x0001 }, | |
4224 | { 0x15, 0x7701 }, | |
4225 | { 0x1f, 0x0000 } | |
4226 | }; | |
4227 | ||
4228 | /* Disable ALDPS before ram code */ | |
eef63cc1 FR |
4229 | rtl_writephy(tp, 0x1f, 0x0000); |
4230 | rtl_writephy(tp, 0x18, 0x0310); | |
4231 | msleep(100); | |
5a5e4443 | 4232 | |
953a12cc | 4233 | rtl_apply_firmware(tp); |
5a5e4443 HW |
4234 | |
4235 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | |
4236 | } | |
4237 | ||
7e18dca1 HW |
4238 | static void rtl8402_hw_phy_config(struct rtl8169_private *tp) |
4239 | { | |
7e18dca1 | 4240 | /* Disable ALDPS before setting firmware */ |
eef63cc1 FR |
4241 | rtl_writephy(tp, 0x1f, 0x0000); |
4242 | rtl_writephy(tp, 0x18, 0x0310); | |
4243 | msleep(20); | |
7e18dca1 HW |
4244 | |
4245 | rtl_apply_firmware(tp); | |
4246 | ||
4247 | /* EEE setting */ | |
fdf6fc06 | 4248 | rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); |
7e18dca1 HW |
4249 | rtl_writephy(tp, 0x1f, 0x0004); |
4250 | rtl_writephy(tp, 0x10, 0x401f); | |
4251 | rtl_writephy(tp, 0x19, 0x7030); | |
4252 | rtl_writephy(tp, 0x1f, 0x0000); | |
4253 | } | |
4254 | ||
5598bfe5 HW |
4255 | static void rtl8106e_hw_phy_config(struct rtl8169_private *tp) |
4256 | { | |
5598bfe5 HW |
4257 | static const struct phy_reg phy_reg_init[] = { |
4258 | { 0x1f, 0x0004 }, | |
4259 | { 0x10, 0xc07f }, | |
4260 | { 0x19, 0x7030 }, | |
4261 | { 0x1f, 0x0000 } | |
4262 | }; | |
4263 | ||
4264 | /* Disable ALDPS before ram code */ | |
eef63cc1 FR |
4265 | rtl_writephy(tp, 0x1f, 0x0000); |
4266 | rtl_writephy(tp, 0x18, 0x0310); | |
4267 | msleep(100); | |
5598bfe5 HW |
4268 | |
4269 | rtl_apply_firmware(tp); | |
4270 | ||
fdf6fc06 | 4271 | rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); |
5598bfe5 HW |
4272 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
4273 | ||
fdf6fc06 | 4274 | rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); |
5598bfe5 HW |
4275 | } |
4276 | ||
5615d9f1 FR |
4277 | static void rtl_hw_phy_config(struct net_device *dev) |
4278 | { | |
4279 | struct rtl8169_private *tp = netdev_priv(dev); | |
5615d9f1 FR |
4280 | |
4281 | rtl8169_print_mac_version(tp); | |
4282 | ||
4283 | switch (tp->mac_version) { | |
4284 | case RTL_GIGA_MAC_VER_01: | |
4285 | break; | |
4286 | case RTL_GIGA_MAC_VER_02: | |
4287 | case RTL_GIGA_MAC_VER_03: | |
4da19633 | 4288 | rtl8169s_hw_phy_config(tp); |
5615d9f1 FR |
4289 | break; |
4290 | case RTL_GIGA_MAC_VER_04: | |
4da19633 | 4291 | rtl8169sb_hw_phy_config(tp); |
5615d9f1 | 4292 | break; |
2e955856 | 4293 | case RTL_GIGA_MAC_VER_05: |
4da19633 | 4294 | rtl8169scd_hw_phy_config(tp); |
2e955856 | 4295 | break; |
8c7006aa | 4296 | case RTL_GIGA_MAC_VER_06: |
4da19633 | 4297 | rtl8169sce_hw_phy_config(tp); |
8c7006aa | 4298 | break; |
2857ffb7 FR |
4299 | case RTL_GIGA_MAC_VER_07: |
4300 | case RTL_GIGA_MAC_VER_08: | |
4301 | case RTL_GIGA_MAC_VER_09: | |
4da19633 | 4302 | rtl8102e_hw_phy_config(tp); |
2857ffb7 | 4303 | break; |
236b8082 | 4304 | case RTL_GIGA_MAC_VER_11: |
4da19633 | 4305 | rtl8168bb_hw_phy_config(tp); |
236b8082 FR |
4306 | break; |
4307 | case RTL_GIGA_MAC_VER_12: | |
4da19633 | 4308 | rtl8168bef_hw_phy_config(tp); |
236b8082 FR |
4309 | break; |
4310 | case RTL_GIGA_MAC_VER_17: | |
4da19633 | 4311 | rtl8168bef_hw_phy_config(tp); |
236b8082 | 4312 | break; |
867763c1 | 4313 | case RTL_GIGA_MAC_VER_18: |
4da19633 | 4314 | rtl8168cp_1_hw_phy_config(tp); |
867763c1 FR |
4315 | break; |
4316 | case RTL_GIGA_MAC_VER_19: | |
4da19633 | 4317 | rtl8168c_1_hw_phy_config(tp); |
867763c1 | 4318 | break; |
7da97ec9 | 4319 | case RTL_GIGA_MAC_VER_20: |
4da19633 | 4320 | rtl8168c_2_hw_phy_config(tp); |
7da97ec9 | 4321 | break; |
197ff761 | 4322 | case RTL_GIGA_MAC_VER_21: |
4da19633 | 4323 | rtl8168c_3_hw_phy_config(tp); |
197ff761 | 4324 | break; |
6fb07058 | 4325 | case RTL_GIGA_MAC_VER_22: |
4da19633 | 4326 | rtl8168c_4_hw_phy_config(tp); |
6fb07058 | 4327 | break; |
ef3386f0 | 4328 | case RTL_GIGA_MAC_VER_23: |
7f3e3d3a | 4329 | case RTL_GIGA_MAC_VER_24: |
4da19633 | 4330 | rtl8168cp_2_hw_phy_config(tp); |
ef3386f0 | 4331 | break; |
5b538df9 | 4332 | case RTL_GIGA_MAC_VER_25: |
bca03d5f | 4333 | rtl8168d_1_hw_phy_config(tp); |
daf9df6d | 4334 | break; |
4335 | case RTL_GIGA_MAC_VER_26: | |
bca03d5f | 4336 | rtl8168d_2_hw_phy_config(tp); |
daf9df6d | 4337 | break; |
4338 | case RTL_GIGA_MAC_VER_27: | |
4da19633 | 4339 | rtl8168d_3_hw_phy_config(tp); |
5b538df9 | 4340 | break; |
e6de30d6 | 4341 | case RTL_GIGA_MAC_VER_28: |
4342 | rtl8168d_4_hw_phy_config(tp); | |
4343 | break; | |
5a5e4443 HW |
4344 | case RTL_GIGA_MAC_VER_29: |
4345 | case RTL_GIGA_MAC_VER_30: | |
4346 | rtl8105e_hw_phy_config(tp); | |
4347 | break; | |
cecb5fd7 FR |
4348 | case RTL_GIGA_MAC_VER_31: |
4349 | /* None. */ | |
4350 | break; | |
01dc7fec | 4351 | case RTL_GIGA_MAC_VER_32: |
01dc7fec | 4352 | case RTL_GIGA_MAC_VER_33: |
70090424 HW |
4353 | rtl8168e_1_hw_phy_config(tp); |
4354 | break; | |
4355 | case RTL_GIGA_MAC_VER_34: | |
4356 | rtl8168e_2_hw_phy_config(tp); | |
01dc7fec | 4357 | break; |
c2218925 HW |
4358 | case RTL_GIGA_MAC_VER_35: |
4359 | rtl8168f_1_hw_phy_config(tp); | |
4360 | break; | |
4361 | case RTL_GIGA_MAC_VER_36: | |
4362 | rtl8168f_2_hw_phy_config(tp); | |
4363 | break; | |
ef3386f0 | 4364 | |
7e18dca1 HW |
4365 | case RTL_GIGA_MAC_VER_37: |
4366 | rtl8402_hw_phy_config(tp); | |
4367 | break; | |
4368 | ||
b3d7b2f2 HW |
4369 | case RTL_GIGA_MAC_VER_38: |
4370 | rtl8411_hw_phy_config(tp); | |
4371 | break; | |
4372 | ||
5598bfe5 HW |
4373 | case RTL_GIGA_MAC_VER_39: |
4374 | rtl8106e_hw_phy_config(tp); | |
4375 | break; | |
4376 | ||
c558386b HW |
4377 | case RTL_GIGA_MAC_VER_40: |
4378 | rtl8168g_1_hw_phy_config(tp); | |
4379 | break; | |
57538c4a | 4380 | case RTL_GIGA_MAC_VER_42: |
58152cd4 | 4381 | case RTL_GIGA_MAC_VER_43: |
45dd95c4 | 4382 | case RTL_GIGA_MAC_VER_44: |
57538c4a | 4383 | rtl8168g_2_hw_phy_config(tp); |
4384 | break; | |
6e1d0b89 CHL |
4385 | case RTL_GIGA_MAC_VER_45: |
4386 | case RTL_GIGA_MAC_VER_47: | |
4387 | rtl8168h_1_hw_phy_config(tp); | |
4388 | break; | |
4389 | case RTL_GIGA_MAC_VER_46: | |
4390 | case RTL_GIGA_MAC_VER_48: | |
4391 | rtl8168h_2_hw_phy_config(tp); | |
4392 | break; | |
c558386b | 4393 | |
935e2218 CHL |
4394 | case RTL_GIGA_MAC_VER_49: |
4395 | rtl8168ep_1_hw_phy_config(tp); | |
4396 | break; | |
4397 | case RTL_GIGA_MAC_VER_50: | |
4398 | case RTL_GIGA_MAC_VER_51: | |
4399 | rtl8168ep_2_hw_phy_config(tp); | |
4400 | break; | |
4401 | ||
c558386b | 4402 | case RTL_GIGA_MAC_VER_41: |
5615d9f1 FR |
4403 | default: |
4404 | break; | |
4405 | } | |
4406 | } | |
4407 | ||
da78dbff | 4408 | static void rtl_phy_work(struct rtl8169_private *tp) |
1da177e4 | 4409 | { |
1da177e4 | 4410 | struct timer_list *timer = &tp->timer; |
1da177e4 LT |
4411 | unsigned long timeout = RTL8169_PHY_TIMEOUT; |
4412 | ||
bcf0bf90 | 4413 | assert(tp->mac_version > RTL_GIGA_MAC_VER_01); |
1da177e4 | 4414 | |
4da19633 | 4415 | if (tp->phy_reset_pending(tp)) { |
5b0384f4 | 4416 | /* |
1da177e4 LT |
4417 | * A busy loop could burn quite a few cycles on nowadays CPU. |
4418 | * Let's delay the execution of the timer for a few ticks. | |
4419 | */ | |
4420 | timeout = HZ/10; | |
4421 | goto out_mod_timer; | |
4422 | } | |
4423 | ||
1ef7286e | 4424 | if (tp->link_ok(tp)) |
da78dbff | 4425 | return; |
1da177e4 | 4426 | |
9bb8eeb5 | 4427 | netif_dbg(tp, link, tp->dev, "PHY reset until link up\n"); |
1da177e4 | 4428 | |
4da19633 | 4429 | tp->phy_reset_enable(tp); |
1da177e4 LT |
4430 | |
4431 | out_mod_timer: | |
4432 | mod_timer(timer, jiffies + timeout); | |
da78dbff FR |
4433 | } |
4434 | ||
4435 | static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag) | |
4436 | { | |
da78dbff FR |
4437 | if (!test_and_set_bit(flag, tp->wk.flags)) |
4438 | schedule_work(&tp->wk.work); | |
da78dbff FR |
4439 | } |
4440 | ||
9de36ccf | 4441 | static void rtl8169_phy_timer(struct timer_list *t) |
da78dbff | 4442 | { |
9de36ccf | 4443 | struct rtl8169_private *tp = from_timer(tp, t, timer); |
da78dbff | 4444 | |
98ddf986 | 4445 | rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING); |
1da177e4 LT |
4446 | } |
4447 | ||
ffc46952 FR |
4448 | DECLARE_RTL_COND(rtl_phy_reset_cond) |
4449 | { | |
4450 | return tp->phy_reset_pending(tp); | |
4451 | } | |
4452 | ||
bf793295 FR |
4453 | static void rtl8169_phy_reset(struct net_device *dev, |
4454 | struct rtl8169_private *tp) | |
4455 | { | |
4da19633 | 4456 | tp->phy_reset_enable(tp); |
ffc46952 | 4457 | rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100); |
bf793295 FR |
4458 | } |
4459 | ||
2544bfc0 FR |
4460 | static bool rtl_tbi_enabled(struct rtl8169_private *tp) |
4461 | { | |
2544bfc0 | 4462 | return (tp->mac_version == RTL_GIGA_MAC_VER_01) && |
1ef7286e | 4463 | (RTL_R8(tp, PHYstatus) & TBI_Enable); |
2544bfc0 FR |
4464 | } |
4465 | ||
4ff96fa6 FR |
4466 | static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp) |
4467 | { | |
5615d9f1 | 4468 | rtl_hw_phy_config(dev); |
4ff96fa6 | 4469 | |
77332894 MS |
4470 | if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { |
4471 | dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); | |
1ef7286e | 4472 | RTL_W8(tp, 0x82, 0x01); |
77332894 | 4473 | } |
4ff96fa6 | 4474 | |
6dccd16b FR |
4475 | pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); |
4476 | ||
4477 | if (tp->mac_version <= RTL_GIGA_MAC_VER_06) | |
4478 | pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); | |
4ff96fa6 | 4479 | |
bcf0bf90 | 4480 | if (tp->mac_version == RTL_GIGA_MAC_VER_02) { |
4ff96fa6 | 4481 | dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); |
1ef7286e | 4482 | RTL_W8(tp, 0x82, 0x01); |
4ff96fa6 | 4483 | dprintk("Set PHY Reg 0x0bh = 0x00h\n"); |
4da19633 | 4484 | rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0 |
4ff96fa6 FR |
4485 | } |
4486 | ||
bf793295 FR |
4487 | rtl8169_phy_reset(dev, tp); |
4488 | ||
54405cde | 4489 | rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL, |
cecb5fd7 FR |
4490 | ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | |
4491 | ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | | |
4492 | (tp->mii.supports_gmii ? | |
4493 | ADVERTISED_1000baseT_Half | | |
4494 | ADVERTISED_1000baseT_Full : 0)); | |
4ff96fa6 | 4495 | |
2544bfc0 | 4496 | if (rtl_tbi_enabled(tp)) |
bf82c189 | 4497 | netif_info(tp, link, dev, "TBI auto-negotiating\n"); |
4ff96fa6 FR |
4498 | } |
4499 | ||
773d2021 FR |
4500 | static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr) |
4501 | { | |
da78dbff | 4502 | rtl_lock_work(tp); |
773d2021 | 4503 | |
1ef7286e | 4504 | RTL_W8(tp, Cfg9346, Cfg9346_Unlock); |
908ba2bf | 4505 | |
1ef7286e AS |
4506 | RTL_W32(tp, MAC4, addr[4] | addr[5] << 8); |
4507 | RTL_R32(tp, MAC4); | |
908ba2bf | 4508 | |
1ef7286e AS |
4509 | RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); |
4510 | RTL_R32(tp, MAC0); | |
908ba2bf | 4511 | |
9ecb9aab | 4512 | if (tp->mac_version == RTL_GIGA_MAC_VER_34) |
4513 | rtl_rar_exgmac_set(tp, addr); | |
c28aa385 | 4514 | |
1ef7286e | 4515 | RTL_W8(tp, Cfg9346, Cfg9346_Lock); |
773d2021 | 4516 | |
da78dbff | 4517 | rtl_unlock_work(tp); |
773d2021 FR |
4518 | } |
4519 | ||
4520 | static int rtl_set_mac_address(struct net_device *dev, void *p) | |
4521 | { | |
4522 | struct rtl8169_private *tp = netdev_priv(dev); | |
1e1205b7 | 4523 | struct device *d = tp_to_dev(tp); |
1f7aa2bc | 4524 | int ret; |
773d2021 | 4525 | |
1f7aa2bc HK |
4526 | ret = eth_mac_addr(dev, p); |
4527 | if (ret) | |
4528 | return ret; | |
773d2021 | 4529 | |
f51d4a10 CHL |
4530 | pm_runtime_get_noresume(d); |
4531 | ||
4532 | if (pm_runtime_active(d)) | |
4533 | rtl_rar_set(tp, dev->dev_addr); | |
4534 | ||
4535 | pm_runtime_put_noidle(d); | |
773d2021 FR |
4536 | |
4537 | return 0; | |
4538 | } | |
4539 | ||
5f787a1a FR |
4540 | static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
4541 | { | |
4542 | struct rtl8169_private *tp = netdev_priv(dev); | |
4543 | struct mii_ioctl_data *data = if_mii(ifr); | |
4544 | ||
8b4ab28d FR |
4545 | return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV; |
4546 | } | |
5f787a1a | 4547 | |
cecb5fd7 FR |
4548 | static int rtl_xmii_ioctl(struct rtl8169_private *tp, |
4549 | struct mii_ioctl_data *data, int cmd) | |
8b4ab28d | 4550 | { |
5f787a1a FR |
4551 | switch (cmd) { |
4552 | case SIOCGMIIPHY: | |
4553 | data->phy_id = 32; /* Internal PHY */ | |
4554 | return 0; | |
4555 | ||
4556 | case SIOCGMIIREG: | |
4da19633 | 4557 | data->val_out = rtl_readphy(tp, data->reg_num & 0x1f); |
5f787a1a FR |
4558 | return 0; |
4559 | ||
4560 | case SIOCSMIIREG: | |
4da19633 | 4561 | rtl_writephy(tp, data->reg_num & 0x1f, data->val_in); |
5f787a1a FR |
4562 | return 0; |
4563 | } | |
4564 | return -EOPNOTSUPP; | |
4565 | } | |
4566 | ||
8b4ab28d FR |
4567 | static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd) |
4568 | { | |
4569 | return -EOPNOTSUPP; | |
4570 | } | |
4571 | ||
baf63293 | 4572 | static void rtl_init_mdio_ops(struct rtl8169_private *tp) |
c0e45c1c | 4573 | { |
4574 | struct mdio_ops *ops = &tp->mdio_ops; | |
4575 | ||
4576 | switch (tp->mac_version) { | |
4577 | case RTL_GIGA_MAC_VER_27: | |
4578 | ops->write = r8168dp_1_mdio_write; | |
4579 | ops->read = r8168dp_1_mdio_read; | |
4580 | break; | |
e6de30d6 | 4581 | case RTL_GIGA_MAC_VER_28: |
4804b3b3 | 4582 | case RTL_GIGA_MAC_VER_31: |
e6de30d6 | 4583 | ops->write = r8168dp_2_mdio_write; |
4584 | ops->read = r8168dp_2_mdio_read; | |
4585 | break; | |
2a71883c | 4586 | case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51: |
c558386b HW |
4587 | ops->write = r8168g_mdio_write; |
4588 | ops->read = r8168g_mdio_read; | |
4589 | break; | |
c0e45c1c | 4590 | default: |
4591 | ops->write = r8169_mdio_write; | |
4592 | ops->read = r8169_mdio_read; | |
4593 | break; | |
4594 | } | |
4595 | } | |
4596 | ||
e2409d83 | 4597 | static void rtl_speed_down(struct rtl8169_private *tp) |
4598 | { | |
4599 | u32 adv; | |
4600 | int lpa; | |
4601 | ||
4602 | rtl_writephy(tp, 0x1f, 0x0000); | |
4603 | lpa = rtl_readphy(tp, MII_LPA); | |
4604 | ||
4605 | if (lpa & (LPA_10HALF | LPA_10FULL)) | |
4606 | adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full; | |
4607 | else if (lpa & (LPA_100HALF | LPA_100FULL)) | |
4608 | adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | | |
4609 | ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full; | |
4610 | else | |
4611 | adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | | |
4612 | ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | | |
4613 | (tp->mii.supports_gmii ? | |
4614 | ADVERTISED_1000baseT_Half | | |
4615 | ADVERTISED_1000baseT_Full : 0); | |
4616 | ||
4617 | rtl8169_set_speed(tp->dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL, | |
4618 | adv); | |
4619 | } | |
4620 | ||
649b3b8c | 4621 | static void rtl_wol_suspend_quirk(struct rtl8169_private *tp) |
4622 | { | |
649b3b8c | 4623 | switch (tp->mac_version) { |
b00e69de CB |
4624 | case RTL_GIGA_MAC_VER_25: |
4625 | case RTL_GIGA_MAC_VER_26: | |
649b3b8c | 4626 | case RTL_GIGA_MAC_VER_29: |
4627 | case RTL_GIGA_MAC_VER_30: | |
4628 | case RTL_GIGA_MAC_VER_32: | |
4629 | case RTL_GIGA_MAC_VER_33: | |
4630 | case RTL_GIGA_MAC_VER_34: | |
2a71883c | 4631 | case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_51: |
1ef7286e | 4632 | RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) | |
649b3b8c | 4633 | AcceptBroadcast | AcceptMulticast | AcceptMyPhys); |
4634 | break; | |
4635 | default: | |
4636 | break; | |
4637 | } | |
4638 | } | |
4639 | ||
4640 | static bool rtl_wol_pll_power_down(struct rtl8169_private *tp) | |
4641 | { | |
4642 | if (!(__rtl8169_get_wol(tp) & WAKE_ANY)) | |
4643 | return false; | |
4644 | ||
e2409d83 | 4645 | rtl_speed_down(tp); |
649b3b8c | 4646 | rtl_wol_suspend_quirk(tp); |
4647 | ||
4648 | return true; | |
4649 | } | |
4650 | ||
065c27c1 | 4651 | static void r8168_phy_power_up(struct rtl8169_private *tp) |
4652 | { | |
4653 | rtl_writephy(tp, 0x1f, 0x0000); | |
01dc7fec | 4654 | switch (tp->mac_version) { |
4655 | case RTL_GIGA_MAC_VER_11: | |
4656 | case RTL_GIGA_MAC_VER_12: | |
2a71883c | 4657 | case RTL_GIGA_MAC_VER_17 ... RTL_GIGA_MAC_VER_28: |
01dc7fec | 4658 | case RTL_GIGA_MAC_VER_31: |
4659 | rtl_writephy(tp, 0x0e, 0x0000); | |
4660 | break; | |
4661 | default: | |
4662 | break; | |
4663 | } | |
065c27c1 | 4664 | rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE); |
b2d6cee1 DM |
4665 | |
4666 | /* give MAC/PHY some time to resume */ | |
4667 | msleep(20); | |
065c27c1 | 4668 | } |
4669 | ||
4670 | static void r8168_phy_power_down(struct rtl8169_private *tp) | |
4671 | { | |
4672 | rtl_writephy(tp, 0x1f, 0x0000); | |
01dc7fec | 4673 | switch (tp->mac_version) { |
4674 | case RTL_GIGA_MAC_VER_32: | |
4675 | case RTL_GIGA_MAC_VER_33: | |
beb330a4 | 4676 | case RTL_GIGA_MAC_VER_40: |
4677 | case RTL_GIGA_MAC_VER_41: | |
01dc7fec | 4678 | rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN); |
4679 | break; | |
4680 | ||
4681 | case RTL_GIGA_MAC_VER_11: | |
4682 | case RTL_GIGA_MAC_VER_12: | |
2a71883c | 4683 | case RTL_GIGA_MAC_VER_17 ... RTL_GIGA_MAC_VER_28: |
01dc7fec | 4684 | case RTL_GIGA_MAC_VER_31: |
4685 | rtl_writephy(tp, 0x0e, 0x0200); | |
4686 | default: | |
4687 | rtl_writephy(tp, MII_BMCR, BMCR_PDOWN); | |
4688 | break; | |
4689 | } | |
065c27c1 | 4690 | } |
4691 | ||
4692 | static void r8168_pll_power_down(struct rtl8169_private *tp) | |
4693 | { | |
9dbe7896 | 4694 | if (r8168_check_dash(tp)) |
065c27c1 | 4695 | return; |
4696 | ||
01dc7fec | 4697 | if (tp->mac_version == RTL_GIGA_MAC_VER_32 || |
4698 | tp->mac_version == RTL_GIGA_MAC_VER_33) | |
fdf6fc06 | 4699 | rtl_ephy_write(tp, 0x19, 0xff64); |
01dc7fec | 4700 | |
649b3b8c | 4701 | if (rtl_wol_pll_power_down(tp)) |
065c27c1 | 4702 | return; |
065c27c1 | 4703 | |
4704 | r8168_phy_power_down(tp); | |
4705 | ||
4706 | switch (tp->mac_version) { | |
2a71883c | 4707 | case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33: |
73570bf1 HK |
4708 | case RTL_GIGA_MAC_VER_37: |
4709 | case RTL_GIGA_MAC_VER_39: | |
4710 | case RTL_GIGA_MAC_VER_43: | |
42fde737 | 4711 | case RTL_GIGA_MAC_VER_44: |
6e1d0b89 CHL |
4712 | case RTL_GIGA_MAC_VER_45: |
4713 | case RTL_GIGA_MAC_VER_46: | |
73570bf1 HK |
4714 | case RTL_GIGA_MAC_VER_47: |
4715 | case RTL_GIGA_MAC_VER_48: | |
935e2218 CHL |
4716 | case RTL_GIGA_MAC_VER_50: |
4717 | case RTL_GIGA_MAC_VER_51: | |
1ef7286e | 4718 | RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80); |
065c27c1 | 4719 | break; |
beb330a4 | 4720 | case RTL_GIGA_MAC_VER_40: |
4721 | case RTL_GIGA_MAC_VER_41: | |
935e2218 | 4722 | case RTL_GIGA_MAC_VER_49: |
706123d0 | 4723 | rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000, |
beb330a4 | 4724 | 0xfc000000, ERIAR_EXGMAC); |
1ef7286e | 4725 | RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80); |
beb330a4 | 4726 | break; |
065c27c1 | 4727 | } |
4728 | } | |
4729 | ||
4730 | static void r8168_pll_power_up(struct rtl8169_private *tp) | |
4731 | { | |
065c27c1 | 4732 | switch (tp->mac_version) { |
2a71883c | 4733 | case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33: |
73570bf1 HK |
4734 | case RTL_GIGA_MAC_VER_37: |
4735 | case RTL_GIGA_MAC_VER_39: | |
4736 | case RTL_GIGA_MAC_VER_43: | |
1ef7286e | 4737 | RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80); |
065c27c1 | 4738 | break; |
42fde737 | 4739 | case RTL_GIGA_MAC_VER_44: |
6e1d0b89 CHL |
4740 | case RTL_GIGA_MAC_VER_45: |
4741 | case RTL_GIGA_MAC_VER_46: | |
73570bf1 HK |
4742 | case RTL_GIGA_MAC_VER_47: |
4743 | case RTL_GIGA_MAC_VER_48: | |
935e2218 CHL |
4744 | case RTL_GIGA_MAC_VER_50: |
4745 | case RTL_GIGA_MAC_VER_51: | |
1ef7286e | 4746 | RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0); |
6e1d0b89 | 4747 | break; |
beb330a4 | 4748 | case RTL_GIGA_MAC_VER_40: |
4749 | case RTL_GIGA_MAC_VER_41: | |
935e2218 | 4750 | case RTL_GIGA_MAC_VER_49: |
1ef7286e | 4751 | RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0); |
706123d0 | 4752 | rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000, |
beb330a4 | 4753 | 0x00000000, ERIAR_EXGMAC); |
4754 | break; | |
065c27c1 | 4755 | } |
4756 | ||
4757 | r8168_phy_power_up(tp); | |
4758 | } | |
4759 | ||
065c27c1 | 4760 | static void rtl_pll_power_down(struct rtl8169_private *tp) |
4761 | { | |
4f447d29 HK |
4762 | switch (tp->mac_version) { |
4763 | case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06: | |
4764 | case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15: | |
4765 | break; | |
4766 | default: | |
4767 | r8168_pll_power_down(tp); | |
4768 | } | |
065c27c1 | 4769 | } |
4770 | ||
4771 | static void rtl_pll_power_up(struct rtl8169_private *tp) | |
4772 | { | |
065c27c1 | 4773 | switch (tp->mac_version) { |
4f447d29 HK |
4774 | case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06: |
4775 | case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15: | |
065c27c1 | 4776 | break; |
065c27c1 | 4777 | default: |
4f447d29 | 4778 | r8168_pll_power_up(tp); |
065c27c1 | 4779 | } |
4780 | } | |
4781 | ||
e542a226 HW |
4782 | static void rtl_init_rxcfg(struct rtl8169_private *tp) |
4783 | { | |
e542a226 | 4784 | switch (tp->mac_version) { |
2a71883c HK |
4785 | case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06: |
4786 | case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: | |
1ef7286e | 4787 | RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST); |
e542a226 | 4788 | break; |
2a71883c | 4789 | case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: |
eb2dc35d | 4790 | case RTL_GIGA_MAC_VER_34: |
3ced8c95 | 4791 | case RTL_GIGA_MAC_VER_35: |
1ef7286e | 4792 | RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST); |
e542a226 | 4793 | break; |
2a71883c | 4794 | case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51: |
1ef7286e | 4795 | RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF); |
beb330a4 | 4796 | break; |
e542a226 | 4797 | default: |
1ef7286e | 4798 | RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST); |
e542a226 HW |
4799 | break; |
4800 | } | |
4801 | } | |
4802 | ||
92fc43b4 HW |
4803 | static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) |
4804 | { | |
9fba0812 | 4805 | tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0; |
92fc43b4 HW |
4806 | } |
4807 | ||
d58d46b5 FR |
4808 | static void rtl_hw_jumbo_enable(struct rtl8169_private *tp) |
4809 | { | |
eda40b8c HK |
4810 | if (tp->jumbo_ops.enable) { |
4811 | RTL_W8(tp, Cfg9346, Cfg9346_Unlock); | |
4812 | tp->jumbo_ops.enable(tp); | |
4813 | RTL_W8(tp, Cfg9346, Cfg9346_Lock); | |
4814 | } | |
d58d46b5 FR |
4815 | } |
4816 | ||
4817 | static void rtl_hw_jumbo_disable(struct rtl8169_private *tp) | |
4818 | { | |
eda40b8c HK |
4819 | if (tp->jumbo_ops.disable) { |
4820 | RTL_W8(tp, Cfg9346, Cfg9346_Unlock); | |
4821 | tp->jumbo_ops.disable(tp); | |
4822 | RTL_W8(tp, Cfg9346, Cfg9346_Lock); | |
4823 | } | |
d58d46b5 FR |
4824 | } |
4825 | ||
4826 | static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp) | |
4827 | { | |
1ef7286e AS |
4828 | RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); |
4829 | RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1); | |
cb73200c | 4830 | rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B); |
d58d46b5 FR |
4831 | } |
4832 | ||
4833 | static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp) | |
4834 | { | |
1ef7286e AS |
4835 | RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); |
4836 | RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1); | |
8d98aa39 | 4837 | rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); |
d58d46b5 FR |
4838 | } |
4839 | ||
4840 | static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp) | |
4841 | { | |
1ef7286e | 4842 | RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); |
d58d46b5 FR |
4843 | } |
4844 | ||
4845 | static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp) | |
4846 | { | |
1ef7286e | 4847 | RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); |
d58d46b5 FR |
4848 | } |
4849 | ||
4850 | static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp) | |
4851 | { | |
1ef7286e AS |
4852 | RTL_W8(tp, MaxTxPacketSize, 0x3f); |
4853 | RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); | |
4854 | RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01); | |
cb73200c | 4855 | rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B); |
d58d46b5 FR |
4856 | } |
4857 | ||
4858 | static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp) | |
4859 | { | |
1ef7286e AS |
4860 | RTL_W8(tp, MaxTxPacketSize, 0x0c); |
4861 | RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); | |
4862 | RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01); | |
8d98aa39 | 4863 | rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); |
d58d46b5 FR |
4864 | } |
4865 | ||
4866 | static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp) | |
4867 | { | |
cb73200c | 4868 | rtl_tx_performance_tweak(tp, |
f65d539c | 4869 | PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN); |
d58d46b5 FR |
4870 | } |
4871 | ||
4872 | static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp) | |
4873 | { | |
cb73200c | 4874 | rtl_tx_performance_tweak(tp, |
8d98aa39 | 4875 | PCI_EXP_DEVCTL_READRQ_4096B | PCI_EXP_DEVCTL_NOSNOOP_EN); |
d58d46b5 FR |
4876 | } |
4877 | ||
4878 | static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp) | |
4879 | { | |
d58d46b5 FR |
4880 | r8168b_0_hw_jumbo_enable(tp); |
4881 | ||
1ef7286e | 4882 | RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0)); |
d58d46b5 FR |
4883 | } |
4884 | ||
4885 | static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp) | |
4886 | { | |
d58d46b5 FR |
4887 | r8168b_0_hw_jumbo_disable(tp); |
4888 | ||
1ef7286e | 4889 | RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0)); |
d58d46b5 FR |
4890 | } |
4891 | ||
baf63293 | 4892 | static void rtl_init_jumbo_ops(struct rtl8169_private *tp) |
d58d46b5 FR |
4893 | { |
4894 | struct jumbo_ops *ops = &tp->jumbo_ops; | |
4895 | ||
4896 | switch (tp->mac_version) { | |
4897 | case RTL_GIGA_MAC_VER_11: | |
4898 | ops->disable = r8168b_0_hw_jumbo_disable; | |
4899 | ops->enable = r8168b_0_hw_jumbo_enable; | |
4900 | break; | |
4901 | case RTL_GIGA_MAC_VER_12: | |
4902 | case RTL_GIGA_MAC_VER_17: | |
4903 | ops->disable = r8168b_1_hw_jumbo_disable; | |
4904 | ops->enable = r8168b_1_hw_jumbo_enable; | |
4905 | break; | |
4906 | case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */ | |
4907 | case RTL_GIGA_MAC_VER_19: | |
4908 | case RTL_GIGA_MAC_VER_20: | |
4909 | case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */ | |
4910 | case RTL_GIGA_MAC_VER_22: | |
4911 | case RTL_GIGA_MAC_VER_23: | |
4912 | case RTL_GIGA_MAC_VER_24: | |
4913 | case RTL_GIGA_MAC_VER_25: | |
4914 | case RTL_GIGA_MAC_VER_26: | |
4915 | ops->disable = r8168c_hw_jumbo_disable; | |
4916 | ops->enable = r8168c_hw_jumbo_enable; | |
4917 | break; | |
4918 | case RTL_GIGA_MAC_VER_27: | |
4919 | case RTL_GIGA_MAC_VER_28: | |
4920 | ops->disable = r8168dp_hw_jumbo_disable; | |
4921 | ops->enable = r8168dp_hw_jumbo_enable; | |
4922 | break; | |
4923 | case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */ | |
4924 | case RTL_GIGA_MAC_VER_32: | |
4925 | case RTL_GIGA_MAC_VER_33: | |
4926 | case RTL_GIGA_MAC_VER_34: | |
4927 | ops->disable = r8168e_hw_jumbo_disable; | |
4928 | ops->enable = r8168e_hw_jumbo_enable; | |
4929 | break; | |
4930 | ||
4931 | /* | |
4932 | * No action needed for jumbo frames with 8169. | |
4933 | * No jumbo for 810x at all. | |
4934 | */ | |
2a71883c | 4935 | case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51: |
d58d46b5 FR |
4936 | default: |
4937 | ops->disable = NULL; | |
4938 | ops->enable = NULL; | |
4939 | break; | |
4940 | } | |
4941 | } | |
4942 | ||
ffc46952 FR |
4943 | DECLARE_RTL_COND(rtl_chipcmd_cond) |
4944 | { | |
1ef7286e | 4945 | return RTL_R8(tp, ChipCmd) & CmdReset; |
ffc46952 FR |
4946 | } |
4947 | ||
6f43adc8 FR |
4948 | static void rtl_hw_reset(struct rtl8169_private *tp) |
4949 | { | |
1ef7286e | 4950 | RTL_W8(tp, ChipCmd, CmdReset); |
6f43adc8 | 4951 | |
ffc46952 | 4952 | rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100); |
6f43adc8 FR |
4953 | } |
4954 | ||
b6ffd97f | 4955 | static void rtl_request_uncached_firmware(struct rtl8169_private *tp) |
953a12cc | 4956 | { |
b6ffd97f FR |
4957 | struct rtl_fw *rtl_fw; |
4958 | const char *name; | |
4959 | int rc = -ENOMEM; | |
953a12cc | 4960 | |
b6ffd97f FR |
4961 | name = rtl_lookup_firmware_name(tp); |
4962 | if (!name) | |
4963 | goto out_no_firmware; | |
953a12cc | 4964 | |
b6ffd97f FR |
4965 | rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL); |
4966 | if (!rtl_fw) | |
4967 | goto err_warn; | |
31bd204f | 4968 | |
1e1205b7 | 4969 | rc = request_firmware(&rtl_fw->fw, name, tp_to_dev(tp)); |
b6ffd97f FR |
4970 | if (rc < 0) |
4971 | goto err_free; | |
4972 | ||
fd112f2e FR |
4973 | rc = rtl_check_firmware(tp, rtl_fw); |
4974 | if (rc < 0) | |
4975 | goto err_release_firmware; | |
4976 | ||
b6ffd97f FR |
4977 | tp->rtl_fw = rtl_fw; |
4978 | out: | |
4979 | return; | |
4980 | ||
fd112f2e FR |
4981 | err_release_firmware: |
4982 | release_firmware(rtl_fw->fw); | |
b6ffd97f FR |
4983 | err_free: |
4984 | kfree(rtl_fw); | |
4985 | err_warn: | |
4986 | netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n", | |
4987 | name, rc); | |
4988 | out_no_firmware: | |
4989 | tp->rtl_fw = NULL; | |
4990 | goto out; | |
4991 | } | |
4992 | ||
4993 | static void rtl_request_firmware(struct rtl8169_private *tp) | |
4994 | { | |
4995 | if (IS_ERR(tp->rtl_fw)) | |
4996 | rtl_request_uncached_firmware(tp); | |
953a12cc FR |
4997 | } |
4998 | ||
92fc43b4 HW |
4999 | static void rtl_rx_close(struct rtl8169_private *tp) |
5000 | { | |
1ef7286e | 5001 | RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK); |
92fc43b4 HW |
5002 | } |
5003 | ||
ffc46952 FR |
5004 | DECLARE_RTL_COND(rtl_npq_cond) |
5005 | { | |
1ef7286e | 5006 | return RTL_R8(tp, TxPoll) & NPQ; |
ffc46952 FR |
5007 | } |
5008 | ||
5009 | DECLARE_RTL_COND(rtl_txcfg_empty_cond) | |
5010 | { | |
1ef7286e | 5011 | return RTL_R32(tp, TxConfig) & TXCFG_EMPTY; |
ffc46952 FR |
5012 | } |
5013 | ||
e6de30d6 | 5014 | static void rtl8169_hw_reset(struct rtl8169_private *tp) |
1da177e4 LT |
5015 | { |
5016 | /* Disable interrupts */ | |
811fd301 | 5017 | rtl8169_irq_mask_and_ack(tp); |
1da177e4 | 5018 | |
92fc43b4 HW |
5019 | rtl_rx_close(tp); |
5020 | ||
b2d43e6e HK |
5021 | switch (tp->mac_version) { |
5022 | case RTL_GIGA_MAC_VER_27: | |
5023 | case RTL_GIGA_MAC_VER_28: | |
5024 | case RTL_GIGA_MAC_VER_31: | |
ffc46952 | 5025 | rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42); |
b2d43e6e HK |
5026 | break; |
5027 | case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: | |
5028 | case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51: | |
1ef7286e | 5029 | RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); |
ffc46952 | 5030 | rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666); |
b2d43e6e HK |
5031 | break; |
5032 | default: | |
1ef7286e | 5033 | RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); |
92fc43b4 | 5034 | udelay(100); |
b2d43e6e | 5035 | break; |
e6de30d6 | 5036 | } |
5037 | ||
92fc43b4 | 5038 | rtl_hw_reset(tp); |
1da177e4 LT |
5039 | } |
5040 | ||
7f796d83 | 5041 | static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp) |
9cb427b6 | 5042 | { |
9cb427b6 | 5043 | /* Set DMA burst size and Interframe Gap Time */ |
1ef7286e | 5044 | RTL_W32(tp, TxConfig, (TX_DMA_BURST << TxDMAShift) | |
9cb427b6 FR |
5045 | (InterFrameGap << TxInterFrameGapShift)); |
5046 | } | |
5047 | ||
4fd48c4a | 5048 | static void rtl_set_rx_max_size(struct rtl8169_private *tp) |
1da177e4 | 5049 | { |
4fd48c4a HK |
5050 | /* Low hurts. Let's disable the filtering. */ |
5051 | RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1); | |
07ce4064 FR |
5052 | } |
5053 | ||
1ef7286e | 5054 | static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp) |
7f796d83 FR |
5055 | { |
5056 | /* | |
5057 | * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh | |
5058 | * register to be written before TxDescAddrLow to work. | |
5059 | * Switching from MMIO to I/O access fixes the issue as well. | |
5060 | */ | |
1ef7286e AS |
5061 | RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); |
5062 | RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); | |
5063 | RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); | |
5064 | RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); | |
7f796d83 FR |
5065 | } |
5066 | ||
1ef7286e | 5067 | static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version) |
6dccd16b | 5068 | { |
3744100e | 5069 | static const struct rtl_cfg2_info { |
6dccd16b FR |
5070 | u32 mac_version; |
5071 | u32 clk; | |
5072 | u32 val; | |
5073 | } cfg2_info [] = { | |
5074 | { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd | |
5075 | { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff }, | |
5076 | { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe | |
5077 | { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff } | |
3744100e FR |
5078 | }; |
5079 | const struct rtl_cfg2_info *p = cfg2_info; | |
6dccd16b FR |
5080 | unsigned int i; |
5081 | u32 clk; | |
5082 | ||
1ef7286e | 5083 | clk = RTL_R8(tp, Config2) & PCI_Clock_66MHz; |
cadf1855 | 5084 | for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) { |
6dccd16b | 5085 | if ((p->mac_version == mac_version) && (p->clk == clk)) { |
1ef7286e | 5086 | RTL_W32(tp, 0x7c, p->val); |
6dccd16b FR |
5087 | break; |
5088 | } | |
5089 | } | |
5090 | } | |
5091 | ||
e6b763ea FR |
5092 | static void rtl_set_rx_mode(struct net_device *dev) |
5093 | { | |
5094 | struct rtl8169_private *tp = netdev_priv(dev); | |
e6b763ea FR |
5095 | u32 mc_filter[2]; /* Multicast hash filter */ |
5096 | int rx_mode; | |
5097 | u32 tmp = 0; | |
5098 | ||
5099 | if (dev->flags & IFF_PROMISC) { | |
5100 | /* Unconditionally log net taps. */ | |
5101 | netif_notice(tp, link, dev, "Promiscuous mode enabled\n"); | |
5102 | rx_mode = | |
5103 | AcceptBroadcast | AcceptMulticast | AcceptMyPhys | | |
5104 | AcceptAllPhys; | |
5105 | mc_filter[1] = mc_filter[0] = 0xffffffff; | |
5106 | } else if ((netdev_mc_count(dev) > multicast_filter_limit) || | |
5107 | (dev->flags & IFF_ALLMULTI)) { | |
5108 | /* Too many to filter perfectly -- accept all multicasts. */ | |
5109 | rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; | |
5110 | mc_filter[1] = mc_filter[0] = 0xffffffff; | |
5111 | } else { | |
5112 | struct netdev_hw_addr *ha; | |
5113 | ||
5114 | rx_mode = AcceptBroadcast | AcceptMyPhys; | |
5115 | mc_filter[1] = mc_filter[0] = 0; | |
5116 | netdev_for_each_mc_addr(ha, dev) { | |
5117 | int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; | |
5118 | mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); | |
5119 | rx_mode |= AcceptMulticast; | |
5120 | } | |
5121 | } | |
5122 | ||
5123 | if (dev->features & NETIF_F_RXALL) | |
5124 | rx_mode |= (AcceptErr | AcceptRunt); | |
5125 | ||
1ef7286e | 5126 | tmp = (RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode; |
e6b763ea FR |
5127 | |
5128 | if (tp->mac_version > RTL_GIGA_MAC_VER_06) { | |
5129 | u32 data = mc_filter[0]; | |
5130 | ||
5131 | mc_filter[0] = swab32(mc_filter[1]); | |
5132 | mc_filter[1] = swab32(data); | |
5133 | } | |
5134 | ||
0481776b NW |
5135 | if (tp->mac_version == RTL_GIGA_MAC_VER_35) |
5136 | mc_filter[1] = mc_filter[0] = 0xffffffff; | |
5137 | ||
1ef7286e AS |
5138 | RTL_W32(tp, MAR0 + 4, mc_filter[1]); |
5139 | RTL_W32(tp, MAR0 + 0, mc_filter[0]); | |
e6b763ea | 5140 | |
1ef7286e | 5141 | RTL_W32(tp, RxConfig, tmp); |
e6b763ea FR |
5142 | } |
5143 | ||
52f8560e HK |
5144 | static void rtl_hw_start(struct rtl8169_private *tp) |
5145 | { | |
5146 | RTL_W8(tp, Cfg9346, Cfg9346_Unlock); | |
5147 | ||
5148 | tp->hw_start(tp); | |
5149 | ||
5150 | rtl_set_rx_max_size(tp); | |
5151 | rtl_set_rx_tx_desc_registers(tp); | |
5152 | rtl_set_rx_tx_config_registers(tp); | |
5153 | RTL_W8(tp, Cfg9346, Cfg9346_Lock); | |
5154 | ||
5155 | /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ | |
5156 | RTL_R8(tp, IntrMask); | |
5157 | RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb); | |
5158 | rtl_set_rx_mode(tp->dev); | |
5159 | /* no early-rx interrupts */ | |
5160 | RTL_W16(tp, MultiIntr, RTL_R16(tp, MultiIntr) & 0xf000); | |
5161 | rtl_irq_enable_all(tp); | |
5162 | } | |
5163 | ||
61cb532d | 5164 | static void rtl_hw_start_8169(struct rtl8169_private *tp) |
07ce4064 | 5165 | { |
0ae0974e | 5166 | if (tp->mac_version == RTL_GIGA_MAC_VER_05) |
61cb532d | 5167 | pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); |
9cb427b6 | 5168 | |
1ef7286e | 5169 | RTL_W8(tp, EarlyTxThres, NoEarlyTx); |
1da177e4 | 5170 | |
0ae0974e | 5171 | tp->cp_cmd |= PCIMulRW; |
1da177e4 | 5172 | |
cecb5fd7 FR |
5173 | if (tp->mac_version == RTL_GIGA_MAC_VER_02 || |
5174 | tp->mac_version == RTL_GIGA_MAC_VER_03) { | |
05b9687b | 5175 | dprintk("Set MAC Reg C+CR Offset 0xe0. " |
1da177e4 | 5176 | "Bit-3 and bit-14 MUST be 1\n"); |
bcf0bf90 | 5177 | tp->cp_cmd |= (1 << 14); |
1da177e4 LT |
5178 | } |
5179 | ||
1ef7286e | 5180 | RTL_W16(tp, CPlusCmd, tp->cp_cmd); |
bcf0bf90 | 5181 | |
1ef7286e | 5182 | rtl8169_set_magic_reg(tp, tp->mac_version); |
6dccd16b | 5183 | |
1da177e4 LT |
5184 | /* |
5185 | * Undocumented corner. Supposedly: | |
5186 | * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets | |
5187 | */ | |
1ef7286e | 5188 | RTL_W16(tp, IntrMitigate, 0x0000); |
1da177e4 | 5189 | |
1ef7286e | 5190 | RTL_W32(tp, RxMissed, 0); |
07ce4064 | 5191 | } |
1da177e4 | 5192 | |
ffc46952 FR |
5193 | DECLARE_RTL_COND(rtl_csiar_cond) |
5194 | { | |
1ef7286e | 5195 | return RTL_R32(tp, CSIAR) & CSIAR_FLAG; |
ffc46952 FR |
5196 | } |
5197 | ||
ff1d7331 | 5198 | static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value) |
beb1fe18 | 5199 | { |
ff1d7331 | 5200 | u32 func = PCI_FUNC(tp->pci_dev->devfn); |
beb1fe18 | 5201 | |
1ef7286e AS |
5202 | RTL_W32(tp, CSIDR, value); |
5203 | RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | | |
ff1d7331 | 5204 | CSIAR_BYTE_ENABLE | func << 16); |
7e18dca1 | 5205 | |
ffc46952 | 5206 | rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100); |
7e18dca1 HW |
5207 | } |
5208 | ||
ff1d7331 | 5209 | static u32 rtl_csi_read(struct rtl8169_private *tp, int addr) |
7e18dca1 | 5210 | { |
ff1d7331 HK |
5211 | u32 func = PCI_FUNC(tp->pci_dev->devfn); |
5212 | ||
5213 | RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 | | |
5214 | CSIAR_BYTE_ENABLE); | |
7e18dca1 | 5215 | |
ffc46952 | 5216 | return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ? |
1ef7286e | 5217 | RTL_R32(tp, CSIDR) : ~0; |
7e18dca1 HW |
5218 | } |
5219 | ||
ff1d7331 | 5220 | static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val) |
45dd95c4 | 5221 | { |
ff1d7331 HK |
5222 | struct pci_dev *pdev = tp->pci_dev; |
5223 | u32 csi; | |
45dd95c4 | 5224 | |
ff1d7331 HK |
5225 | /* According to Realtek the value at config space address 0x070f |
5226 | * controls the L0s/L1 entrance latency. We try standard ECAM access | |
5227 | * first and if it fails fall back to CSI. | |
5228 | */ | |
5229 | if (pdev->cfg_size > 0x070f && | |
5230 | pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL) | |
5231 | return; | |
5232 | ||
5233 | netdev_notice_once(tp->dev, | |
5234 | "No native access to PCI extended config space, falling back to CSI\n"); | |
5235 | csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff; | |
5236 | rtl_csi_write(tp, 0x070c, csi | val << 24); | |
45dd95c4 | 5237 | } |
5238 | ||
ff1d7331 | 5239 | static void rtl_csi_access_enable_1(struct rtl8169_private *tp) |
45dd95c4 | 5240 | { |
ff1d7331 | 5241 | rtl_csi_access_enable(tp, 0x17); |
45dd95c4 | 5242 | } |
5243 | ||
ff1d7331 | 5244 | static void rtl_csi_access_enable_2(struct rtl8169_private *tp) |
beb1fe18 | 5245 | { |
ff1d7331 | 5246 | rtl_csi_access_enable(tp, 0x27); |
dacf8154 FR |
5247 | } |
5248 | ||
5249 | struct ephy_info { | |
5250 | unsigned int offset; | |
5251 | u16 mask; | |
5252 | u16 bits; | |
5253 | }; | |
5254 | ||
fdf6fc06 FR |
5255 | static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e, |
5256 | int len) | |
dacf8154 FR |
5257 | { |
5258 | u16 w; | |
5259 | ||
5260 | while (len-- > 0) { | |
fdf6fc06 FR |
5261 | w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits; |
5262 | rtl_ephy_write(tp, e->offset, w); | |
dacf8154 FR |
5263 | e++; |
5264 | } | |
5265 | } | |
5266 | ||
73c86ee3 | 5267 | static void rtl_disable_clock_request(struct rtl8169_private *tp) |
b726e493 | 5268 | { |
73c86ee3 | 5269 | pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL, |
7d7903b2 | 5270 | PCI_EXP_LNKCTL_CLKREQ_EN); |
b726e493 FR |
5271 | } |
5272 | ||
73c86ee3 | 5273 | static void rtl_enable_clock_request(struct rtl8169_private *tp) |
e6de30d6 | 5274 | { |
73c86ee3 | 5275 | pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL, |
7d7903b2 | 5276 | PCI_EXP_LNKCTL_CLKREQ_EN); |
e6de30d6 | 5277 | } |
5278 | ||
b51ecea8 | 5279 | static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable) |
5280 | { | |
b51ecea8 | 5281 | u8 data; |
5282 | ||
1ef7286e | 5283 | data = RTL_R8(tp, Config3); |
b51ecea8 | 5284 | |
5285 | if (enable) | |
5286 | data |= Rdy_to_L23; | |
5287 | else | |
5288 | data &= ~Rdy_to_L23; | |
5289 | ||
1ef7286e | 5290 | RTL_W8(tp, Config3, data); |
b51ecea8 | 5291 | } |
5292 | ||
beb1fe18 | 5293 | static void rtl_hw_start_8168bb(struct rtl8169_private *tp) |
219a1e9d | 5294 | { |
1ef7286e | 5295 | RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); |
b726e493 | 5296 | |
12d42c50 | 5297 | tp->cp_cmd &= CPCMD_QUIRK_MASK; |
0ae0974e | 5298 | RTL_W16(tp, CPlusCmd, tp->cp_cmd); |
b726e493 | 5299 | |
faf1e785 | 5300 | if (tp->dev->mtu <= ETH_DATA_LEN) { |
8d98aa39 | 5301 | rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B | |
faf1e785 | 5302 | PCI_EXP_DEVCTL_NOSNOOP_EN); |
5303 | } | |
219a1e9d FR |
5304 | } |
5305 | ||
beb1fe18 | 5306 | static void rtl_hw_start_8168bef(struct rtl8169_private *tp) |
219a1e9d | 5307 | { |
beb1fe18 | 5308 | rtl_hw_start_8168bb(tp); |
b726e493 | 5309 | |
1ef7286e | 5310 | RTL_W8(tp, MaxTxPacketSize, TxPacketMax); |
b726e493 | 5311 | |
1ef7286e | 5312 | RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0)); |
219a1e9d FR |
5313 | } |
5314 | ||
beb1fe18 | 5315 | static void __rtl_hw_start_8168cp(struct rtl8169_private *tp) |
219a1e9d | 5316 | { |
1ef7286e | 5317 | RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down); |
b726e493 | 5318 | |
1ef7286e | 5319 | RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); |
b726e493 | 5320 | |
faf1e785 | 5321 | if (tp->dev->mtu <= ETH_DATA_LEN) |
8d98aa39 | 5322 | rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); |
b726e493 | 5323 | |
73c86ee3 | 5324 | rtl_disable_clock_request(tp); |
b726e493 | 5325 | |
12d42c50 | 5326 | tp->cp_cmd &= CPCMD_QUIRK_MASK; |
0ae0974e | 5327 | RTL_W16(tp, CPlusCmd, tp->cp_cmd); |
219a1e9d FR |
5328 | } |
5329 | ||
beb1fe18 | 5330 | static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp) |
219a1e9d | 5331 | { |
350f7596 | 5332 | static const struct ephy_info e_info_8168cp[] = { |
b726e493 FR |
5333 | { 0x01, 0, 0x0001 }, |
5334 | { 0x02, 0x0800, 0x1000 }, | |
5335 | { 0x03, 0, 0x0042 }, | |
5336 | { 0x06, 0x0080, 0x0000 }, | |
5337 | { 0x07, 0, 0x2000 } | |
5338 | }; | |
5339 | ||
beb1fe18 | 5340 | rtl_csi_access_enable_2(tp); |
b726e493 | 5341 | |
fdf6fc06 | 5342 | rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp)); |
b726e493 | 5343 | |
beb1fe18 | 5344 | __rtl_hw_start_8168cp(tp); |
219a1e9d FR |
5345 | } |
5346 | ||
beb1fe18 | 5347 | static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp) |
ef3386f0 | 5348 | { |
beb1fe18 | 5349 | rtl_csi_access_enable_2(tp); |
ef3386f0 | 5350 | |
1ef7286e | 5351 | RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); |
ef3386f0 | 5352 | |
faf1e785 | 5353 | if (tp->dev->mtu <= ETH_DATA_LEN) |
8d98aa39 | 5354 | rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); |
ef3386f0 | 5355 | |
12d42c50 | 5356 | tp->cp_cmd &= CPCMD_QUIRK_MASK; |
0ae0974e | 5357 | RTL_W16(tp, CPlusCmd, tp->cp_cmd); |
ef3386f0 FR |
5358 | } |
5359 | ||
beb1fe18 | 5360 | static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp) |
7f3e3d3a | 5361 | { |
beb1fe18 | 5362 | rtl_csi_access_enable_2(tp); |
7f3e3d3a | 5363 | |
1ef7286e | 5364 | RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); |
7f3e3d3a FR |
5365 | |
5366 | /* Magic. */ | |
1ef7286e | 5367 | RTL_W8(tp, DBG_REG, 0x20); |
7f3e3d3a | 5368 | |
1ef7286e | 5369 | RTL_W8(tp, MaxTxPacketSize, TxPacketMax); |
7f3e3d3a | 5370 | |
faf1e785 | 5371 | if (tp->dev->mtu <= ETH_DATA_LEN) |
8d98aa39 | 5372 | rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); |
7f3e3d3a | 5373 | |
12d42c50 | 5374 | tp->cp_cmd &= CPCMD_QUIRK_MASK; |
0ae0974e | 5375 | RTL_W16(tp, CPlusCmd, tp->cp_cmd); |
7f3e3d3a FR |
5376 | } |
5377 | ||
beb1fe18 | 5378 | static void rtl_hw_start_8168c_1(struct rtl8169_private *tp) |
219a1e9d | 5379 | { |
350f7596 | 5380 | static const struct ephy_info e_info_8168c_1[] = { |
b726e493 FR |
5381 | { 0x02, 0x0800, 0x1000 }, |
5382 | { 0x03, 0, 0x0002 }, | |
5383 | { 0x06, 0x0080, 0x0000 } | |
5384 | }; | |
5385 | ||
beb1fe18 | 5386 | rtl_csi_access_enable_2(tp); |
b726e493 | 5387 | |
1ef7286e | 5388 | RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); |
b726e493 | 5389 | |
fdf6fc06 | 5390 | rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1)); |
b726e493 | 5391 | |
beb1fe18 | 5392 | __rtl_hw_start_8168cp(tp); |
219a1e9d FR |
5393 | } |
5394 | ||
beb1fe18 | 5395 | static void rtl_hw_start_8168c_2(struct rtl8169_private *tp) |
219a1e9d | 5396 | { |
350f7596 | 5397 | static const struct ephy_info e_info_8168c_2[] = { |
b726e493 FR |
5398 | { 0x01, 0, 0x0001 }, |
5399 | { 0x03, 0x0400, 0x0220 } | |
5400 | }; | |
5401 | ||
beb1fe18 | 5402 | rtl_csi_access_enable_2(tp); |
b726e493 | 5403 | |
fdf6fc06 | 5404 | rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2)); |
b726e493 | 5405 | |
beb1fe18 | 5406 | __rtl_hw_start_8168cp(tp); |
219a1e9d FR |
5407 | } |
5408 | ||
beb1fe18 | 5409 | static void rtl_hw_start_8168c_3(struct rtl8169_private *tp) |
197ff761 | 5410 | { |
beb1fe18 | 5411 | rtl_hw_start_8168c_2(tp); |
197ff761 FR |
5412 | } |
5413 | ||
beb1fe18 | 5414 | static void rtl_hw_start_8168c_4(struct rtl8169_private *tp) |
6fb07058 | 5415 | { |
beb1fe18 | 5416 | rtl_csi_access_enable_2(tp); |
6fb07058 | 5417 | |
beb1fe18 | 5418 | __rtl_hw_start_8168cp(tp); |
6fb07058 FR |
5419 | } |
5420 | ||
beb1fe18 | 5421 | static void rtl_hw_start_8168d(struct rtl8169_private *tp) |
5b538df9 | 5422 | { |
beb1fe18 | 5423 | rtl_csi_access_enable_2(tp); |
5b538df9 | 5424 | |
73c86ee3 | 5425 | rtl_disable_clock_request(tp); |
5b538df9 | 5426 | |
1ef7286e | 5427 | RTL_W8(tp, MaxTxPacketSize, TxPacketMax); |
5b538df9 | 5428 | |
faf1e785 | 5429 | if (tp->dev->mtu <= ETH_DATA_LEN) |
8d98aa39 | 5430 | rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); |
5b538df9 | 5431 | |
12d42c50 | 5432 | tp->cp_cmd &= CPCMD_QUIRK_MASK; |
0ae0974e | 5433 | RTL_W16(tp, CPlusCmd, tp->cp_cmd); |
5b538df9 FR |
5434 | } |
5435 | ||
beb1fe18 | 5436 | static void rtl_hw_start_8168dp(struct rtl8169_private *tp) |
4804b3b3 | 5437 | { |
beb1fe18 | 5438 | rtl_csi_access_enable_1(tp); |
4804b3b3 | 5439 | |
faf1e785 | 5440 | if (tp->dev->mtu <= ETH_DATA_LEN) |
8d98aa39 | 5441 | rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); |
4804b3b3 | 5442 | |
1ef7286e | 5443 | RTL_W8(tp, MaxTxPacketSize, TxPacketMax); |
4804b3b3 | 5444 | |
73c86ee3 | 5445 | rtl_disable_clock_request(tp); |
4804b3b3 | 5446 | } |
5447 | ||
beb1fe18 | 5448 | static void rtl_hw_start_8168d_4(struct rtl8169_private *tp) |
e6de30d6 | 5449 | { |
5450 | static const struct ephy_info e_info_8168d_4[] = { | |
1016a4a1 CHL |
5451 | { 0x0b, 0x0000, 0x0048 }, |
5452 | { 0x19, 0x0020, 0x0050 }, | |
5453 | { 0x0c, 0x0100, 0x0020 } | |
e6de30d6 | 5454 | }; |
e6de30d6 | 5455 | |
beb1fe18 | 5456 | rtl_csi_access_enable_1(tp); |
e6de30d6 | 5457 | |
8d98aa39 | 5458 | rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); |
e6de30d6 | 5459 | |
1ef7286e | 5460 | RTL_W8(tp, MaxTxPacketSize, TxPacketMax); |
e6de30d6 | 5461 | |
1016a4a1 | 5462 | rtl_ephy_init(tp, e_info_8168d_4, ARRAY_SIZE(e_info_8168d_4)); |
e6de30d6 | 5463 | |
73c86ee3 | 5464 | rtl_enable_clock_request(tp); |
e6de30d6 | 5465 | } |
5466 | ||
beb1fe18 | 5467 | static void rtl_hw_start_8168e_1(struct rtl8169_private *tp) |
01dc7fec | 5468 | { |
70090424 | 5469 | static const struct ephy_info e_info_8168e_1[] = { |
01dc7fec | 5470 | { 0x00, 0x0200, 0x0100 }, |
5471 | { 0x00, 0x0000, 0x0004 }, | |
5472 | { 0x06, 0x0002, 0x0001 }, | |
5473 | { 0x06, 0x0000, 0x0030 }, | |
5474 | { 0x07, 0x0000, 0x2000 }, | |
5475 | { 0x00, 0x0000, 0x0020 }, | |
5476 | { 0x03, 0x5800, 0x2000 }, | |
5477 | { 0x03, 0x0000, 0x0001 }, | |
5478 | { 0x01, 0x0800, 0x1000 }, | |
5479 | { 0x07, 0x0000, 0x4000 }, | |
5480 | { 0x1e, 0x0000, 0x2000 }, | |
5481 | { 0x19, 0xffff, 0xfe6c }, | |
5482 | { 0x0a, 0x0000, 0x0040 } | |
5483 | }; | |
5484 | ||
beb1fe18 | 5485 | rtl_csi_access_enable_2(tp); |
01dc7fec | 5486 | |
fdf6fc06 | 5487 | rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1)); |
01dc7fec | 5488 | |
faf1e785 | 5489 | if (tp->dev->mtu <= ETH_DATA_LEN) |
8d98aa39 | 5490 | rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); |
01dc7fec | 5491 | |
1ef7286e | 5492 | RTL_W8(tp, MaxTxPacketSize, TxPacketMax); |
01dc7fec | 5493 | |
73c86ee3 | 5494 | rtl_disable_clock_request(tp); |
01dc7fec | 5495 | |
5496 | /* Reset tx FIFO pointer */ | |
1ef7286e AS |
5497 | RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST); |
5498 | RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST); | |
01dc7fec | 5499 | |
1ef7286e | 5500 | RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); |
01dc7fec | 5501 | } |
5502 | ||
beb1fe18 | 5503 | static void rtl_hw_start_8168e_2(struct rtl8169_private *tp) |
70090424 HW |
5504 | { |
5505 | static const struct ephy_info e_info_8168e_2[] = { | |
5506 | { 0x09, 0x0000, 0x0080 }, | |
5507 | { 0x19, 0x0000, 0x0224 } | |
5508 | }; | |
5509 | ||
beb1fe18 | 5510 | rtl_csi_access_enable_1(tp); |
70090424 | 5511 | |
fdf6fc06 | 5512 | rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2)); |
70090424 | 5513 | |
faf1e785 | 5514 | if (tp->dev->mtu <= ETH_DATA_LEN) |
8d98aa39 | 5515 | rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); |
70090424 | 5516 | |
fdf6fc06 FR |
5517 | rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); |
5518 | rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); | |
5519 | rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC); | |
5520 | rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC); | |
5521 | rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC); | |
5522 | rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC); | |
706123d0 CHL |
5523 | rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC); |
5524 | rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC); | |
70090424 | 5525 | |
1ef7286e | 5526 | RTL_W8(tp, MaxTxPacketSize, EarlySize); |
70090424 | 5527 | |
73c86ee3 | 5528 | rtl_disable_clock_request(tp); |
4521e1a9 | 5529 | |
1ef7286e AS |
5530 | RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO); |
5531 | RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); | |
70090424 HW |
5532 | |
5533 | /* Adjust EEE LED frequency */ | |
1ef7286e | 5534 | RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07); |
70090424 | 5535 | |
1ef7286e AS |
5536 | RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); |
5537 | RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); | |
5538 | RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); | |
70090424 HW |
5539 | } |
5540 | ||
5f886e08 | 5541 | static void rtl_hw_start_8168f(struct rtl8169_private *tp) |
c2218925 | 5542 | { |
5f886e08 | 5543 | rtl_csi_access_enable_2(tp); |
c2218925 | 5544 | |
8d98aa39 | 5545 | rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); |
c2218925 | 5546 | |
fdf6fc06 FR |
5547 | rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); |
5548 | rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); | |
5549 | rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC); | |
5550 | rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC); | |
706123d0 CHL |
5551 | rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC); |
5552 | rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC); | |
5553 | rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC); | |
5554 | rtl_w0w1_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC); | |
fdf6fc06 FR |
5555 | rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC); |
5556 | rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC); | |
c2218925 | 5557 | |
1ef7286e | 5558 | RTL_W8(tp, MaxTxPacketSize, EarlySize); |
c2218925 | 5559 | |
73c86ee3 | 5560 | rtl_disable_clock_request(tp); |
4521e1a9 | 5561 | |
1ef7286e AS |
5562 | RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO); |
5563 | RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); | |
5564 | RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); | |
5565 | RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); | |
5566 | RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); | |
c2218925 HW |
5567 | } |
5568 | ||
5f886e08 HW |
5569 | static void rtl_hw_start_8168f_1(struct rtl8169_private *tp) |
5570 | { | |
5f886e08 HW |
5571 | static const struct ephy_info e_info_8168f_1[] = { |
5572 | { 0x06, 0x00c0, 0x0020 }, | |
5573 | { 0x08, 0x0001, 0x0002 }, | |
5574 | { 0x09, 0x0000, 0x0080 }, | |
5575 | { 0x19, 0x0000, 0x0224 } | |
5576 | }; | |
5577 | ||
5578 | rtl_hw_start_8168f(tp); | |
5579 | ||
fdf6fc06 | 5580 | rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1)); |
5f886e08 | 5581 | |
706123d0 | 5582 | rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC); |
5f886e08 HW |
5583 | |
5584 | /* Adjust EEE LED frequency */ | |
1ef7286e | 5585 | RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07); |
5f886e08 HW |
5586 | } |
5587 | ||
b3d7b2f2 HW |
5588 | static void rtl_hw_start_8411(struct rtl8169_private *tp) |
5589 | { | |
b3d7b2f2 HW |
5590 | static const struct ephy_info e_info_8168f_1[] = { |
5591 | { 0x06, 0x00c0, 0x0020 }, | |
5592 | { 0x0f, 0xffff, 0x5200 }, | |
5593 | { 0x1e, 0x0000, 0x4000 }, | |
5594 | { 0x19, 0x0000, 0x0224 } | |
5595 | }; | |
5596 | ||
5597 | rtl_hw_start_8168f(tp); | |
b51ecea8 | 5598 | rtl_pcie_state_l2l3_enable(tp, false); |
b3d7b2f2 | 5599 | |
fdf6fc06 | 5600 | rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1)); |
b3d7b2f2 | 5601 | |
706123d0 | 5602 | rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC); |
b3d7b2f2 HW |
5603 | } |
5604 | ||
5fbea337 | 5605 | static void rtl_hw_start_8168g(struct rtl8169_private *tp) |
c558386b | 5606 | { |
1ef7286e | 5607 | RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO); |
beb330a4 | 5608 | |
c558386b HW |
5609 | rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC); |
5610 | rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC); | |
5611 | rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC); | |
5612 | rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC); | |
5613 | ||
5614 | rtl_csi_access_enable_1(tp); | |
5615 | ||
8d98aa39 | 5616 | rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); |
c558386b | 5617 | |
706123d0 CHL |
5618 | rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC); |
5619 | rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC); | |
beb330a4 | 5620 | rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC); |
c558386b | 5621 | |
1ef7286e AS |
5622 | RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); |
5623 | RTL_W8(tp, MaxTxPacketSize, EarlySize); | |
c558386b HW |
5624 | |
5625 | rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); | |
5626 | rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); | |
5627 | ||
5628 | /* Adjust EEE LED frequency */ | |
1ef7286e | 5629 | RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07); |
c558386b | 5630 | |
706123d0 CHL |
5631 | rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC); |
5632 | rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC); | |
b51ecea8 | 5633 | |
5634 | rtl_pcie_state_l2l3_enable(tp, false); | |
c558386b HW |
5635 | } |
5636 | ||
5fbea337 CHL |
5637 | static void rtl_hw_start_8168g_1(struct rtl8169_private *tp) |
5638 | { | |
5fbea337 CHL |
5639 | static const struct ephy_info e_info_8168g_1[] = { |
5640 | { 0x00, 0x0000, 0x0008 }, | |
5641 | { 0x0c, 0x37d0, 0x0820 }, | |
5642 | { 0x1e, 0x0000, 0x0001 }, | |
5643 | { 0x19, 0x8000, 0x0000 } | |
5644 | }; | |
5645 | ||
5646 | rtl_hw_start_8168g(tp); | |
5647 | ||
5648 | /* disable aspm and clock request before access ephy */ | |
1ef7286e AS |
5649 | RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn); |
5650 | RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en); | |
5fbea337 CHL |
5651 | rtl_ephy_init(tp, e_info_8168g_1, ARRAY_SIZE(e_info_8168g_1)); |
5652 | } | |
5653 | ||
57538c4a | 5654 | static void rtl_hw_start_8168g_2(struct rtl8169_private *tp) |
5655 | { | |
57538c4a | 5656 | static const struct ephy_info e_info_8168g_2[] = { |
5657 | { 0x00, 0x0000, 0x0008 }, | |
5658 | { 0x0c, 0x3df0, 0x0200 }, | |
5659 | { 0x19, 0xffff, 0xfc00 }, | |
5660 | { 0x1e, 0xffff, 0x20eb } | |
5661 | }; | |
5662 | ||
5fbea337 | 5663 | rtl_hw_start_8168g(tp); |
57538c4a | 5664 | |
5665 | /* disable aspm and clock request before access ephy */ | |
1ef7286e AS |
5666 | RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn); |
5667 | RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en); | |
57538c4a | 5668 | rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2)); |
5669 | } | |
5670 | ||
45dd95c4 | 5671 | static void rtl_hw_start_8411_2(struct rtl8169_private *tp) |
5672 | { | |
45dd95c4 | 5673 | static const struct ephy_info e_info_8411_2[] = { |
5674 | { 0x00, 0x0000, 0x0008 }, | |
5675 | { 0x0c, 0x3df0, 0x0200 }, | |
5676 | { 0x0f, 0xffff, 0x5200 }, | |
5677 | { 0x19, 0x0020, 0x0000 }, | |
5678 | { 0x1e, 0x0000, 0x2000 } | |
5679 | }; | |
5680 | ||
5fbea337 | 5681 | rtl_hw_start_8168g(tp); |
45dd95c4 | 5682 | |
5683 | /* disable aspm and clock request before access ephy */ | |
1ef7286e AS |
5684 | RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn); |
5685 | RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en); | |
45dd95c4 | 5686 | rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2)); |
5687 | } | |
5688 | ||
6e1d0b89 CHL |
5689 | static void rtl_hw_start_8168h_1(struct rtl8169_private *tp) |
5690 | { | |
72521ea0 | 5691 | int rg_saw_cnt; |
6e1d0b89 CHL |
5692 | u32 data; |
5693 | static const struct ephy_info e_info_8168h_1[] = { | |
5694 | { 0x1e, 0x0800, 0x0001 }, | |
5695 | { 0x1d, 0x0000, 0x0800 }, | |
5696 | { 0x05, 0xffff, 0x2089 }, | |
5697 | { 0x06, 0xffff, 0x5881 }, | |
5698 | { 0x04, 0xffff, 0x154a }, | |
5699 | { 0x01, 0xffff, 0x068b } | |
5700 | }; | |
5701 | ||
5702 | /* disable aspm and clock request before access ephy */ | |
1ef7286e AS |
5703 | RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn); |
5704 | RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en); | |
6e1d0b89 CHL |
5705 | rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1)); |
5706 | ||
1ef7286e | 5707 | RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO); |
6e1d0b89 CHL |
5708 | |
5709 | rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC); | |
5710 | rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC); | |
5711 | rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC); | |
5712 | rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC); | |
5713 | ||
5714 | rtl_csi_access_enable_1(tp); | |
5715 | ||
8d98aa39 | 5716 | rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); |
6e1d0b89 | 5717 | |
706123d0 CHL |
5718 | rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC); |
5719 | rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC); | |
6e1d0b89 | 5720 | |
706123d0 | 5721 | rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC); |
6e1d0b89 | 5722 | |
706123d0 | 5723 | rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC); |
6e1d0b89 CHL |
5724 | |
5725 | rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC); | |
5726 | ||
1ef7286e AS |
5727 | RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); |
5728 | RTL_W8(tp, MaxTxPacketSize, EarlySize); | |
6e1d0b89 CHL |
5729 | |
5730 | rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); | |
5731 | rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); | |
5732 | ||
5733 | /* Adjust EEE LED frequency */ | |
1ef7286e | 5734 | RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07); |
6e1d0b89 | 5735 | |
1ef7286e AS |
5736 | RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); |
5737 | RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); | |
6e1d0b89 | 5738 | |
1ef7286e | 5739 | RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); |
6e1d0b89 | 5740 | |
706123d0 | 5741 | rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC); |
6e1d0b89 CHL |
5742 | |
5743 | rtl_pcie_state_l2l3_enable(tp, false); | |
5744 | ||
5745 | rtl_writephy(tp, 0x1f, 0x0c42); | |
58493333 | 5746 | rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff); |
6e1d0b89 CHL |
5747 | rtl_writephy(tp, 0x1f, 0x0000); |
5748 | if (rg_saw_cnt > 0) { | |
5749 | u16 sw_cnt_1ms_ini; | |
5750 | ||
5751 | sw_cnt_1ms_ini = 16000000/rg_saw_cnt; | |
5752 | sw_cnt_1ms_ini &= 0x0fff; | |
5753 | data = r8168_mac_ocp_read(tp, 0xd412); | |
a2cb7ec0 | 5754 | data &= ~0x0fff; |
6e1d0b89 CHL |
5755 | data |= sw_cnt_1ms_ini; |
5756 | r8168_mac_ocp_write(tp, 0xd412, data); | |
5757 | } | |
5758 | ||
5759 | data = r8168_mac_ocp_read(tp, 0xe056); | |
a2cb7ec0 CHL |
5760 | data &= ~0xf0; |
5761 | data |= 0x70; | |
6e1d0b89 CHL |
5762 | r8168_mac_ocp_write(tp, 0xe056, data); |
5763 | ||
5764 | data = r8168_mac_ocp_read(tp, 0xe052); | |
a2cb7ec0 CHL |
5765 | data &= ~0x6000; |
5766 | data |= 0x8008; | |
6e1d0b89 CHL |
5767 | r8168_mac_ocp_write(tp, 0xe052, data); |
5768 | ||
5769 | data = r8168_mac_ocp_read(tp, 0xe0d6); | |
a2cb7ec0 | 5770 | data &= ~0x01ff; |
6e1d0b89 CHL |
5771 | data |= 0x017f; |
5772 | r8168_mac_ocp_write(tp, 0xe0d6, data); | |
5773 | ||
5774 | data = r8168_mac_ocp_read(tp, 0xd420); | |
a2cb7ec0 | 5775 | data &= ~0x0fff; |
6e1d0b89 CHL |
5776 | data |= 0x047f; |
5777 | r8168_mac_ocp_write(tp, 0xd420, data); | |
5778 | ||
5779 | r8168_mac_ocp_write(tp, 0xe63e, 0x0001); | |
5780 | r8168_mac_ocp_write(tp, 0xe63e, 0x0000); | |
5781 | r8168_mac_ocp_write(tp, 0xc094, 0x0000); | |
5782 | r8168_mac_ocp_write(tp, 0xc09e, 0x0000); | |
5783 | } | |
5784 | ||
935e2218 CHL |
5785 | static void rtl_hw_start_8168ep(struct rtl8169_private *tp) |
5786 | { | |
003609da CHL |
5787 | rtl8168ep_stop_cmac(tp); |
5788 | ||
1ef7286e | 5789 | RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO); |
935e2218 CHL |
5790 | |
5791 | rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC); | |
5792 | rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x2f, ERIAR_EXGMAC); | |
5793 | rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x5f, ERIAR_EXGMAC); | |
5794 | rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC); | |
5795 | ||
5796 | rtl_csi_access_enable_1(tp); | |
5797 | ||
8d98aa39 | 5798 | rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); |
935e2218 CHL |
5799 | |
5800 | rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC); | |
5801 | rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC); | |
5802 | ||
5803 | rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f80, 0x00, ERIAR_EXGMAC); | |
5804 | ||
5805 | rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC); | |
5806 | ||
1ef7286e AS |
5807 | RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); |
5808 | RTL_W8(tp, MaxTxPacketSize, EarlySize); | |
935e2218 CHL |
5809 | |
5810 | rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); | |
5811 | rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); | |
5812 | ||
5813 | /* Adjust EEE LED frequency */ | |
1ef7286e | 5814 | RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07); |
935e2218 CHL |
5815 | |
5816 | rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC); | |
5817 | ||
1ef7286e | 5818 | RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); |
935e2218 CHL |
5819 | |
5820 | rtl_pcie_state_l2l3_enable(tp, false); | |
5821 | } | |
5822 | ||
5823 | static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp) | |
5824 | { | |
935e2218 CHL |
5825 | static const struct ephy_info e_info_8168ep_1[] = { |
5826 | { 0x00, 0xffff, 0x10ab }, | |
5827 | { 0x06, 0xffff, 0xf030 }, | |
5828 | { 0x08, 0xffff, 0x2006 }, | |
5829 | { 0x0d, 0xffff, 0x1666 }, | |
5830 | { 0x0c, 0x3ff0, 0x0000 } | |
5831 | }; | |
5832 | ||
5833 | /* disable aspm and clock request before access ephy */ | |
1ef7286e AS |
5834 | RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn); |
5835 | RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en); | |
935e2218 CHL |
5836 | rtl_ephy_init(tp, e_info_8168ep_1, ARRAY_SIZE(e_info_8168ep_1)); |
5837 | ||
5838 | rtl_hw_start_8168ep(tp); | |
5839 | } | |
5840 | ||
5841 | static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp) | |
5842 | { | |
935e2218 CHL |
5843 | static const struct ephy_info e_info_8168ep_2[] = { |
5844 | { 0x00, 0xffff, 0x10a3 }, | |
5845 | { 0x19, 0xffff, 0xfc00 }, | |
5846 | { 0x1e, 0xffff, 0x20ea } | |
5847 | }; | |
5848 | ||
5849 | /* disable aspm and clock request before access ephy */ | |
1ef7286e AS |
5850 | RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn); |
5851 | RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en); | |
935e2218 CHL |
5852 | rtl_ephy_init(tp, e_info_8168ep_2, ARRAY_SIZE(e_info_8168ep_2)); |
5853 | ||
5854 | rtl_hw_start_8168ep(tp); | |
5855 | ||
1ef7286e AS |
5856 | RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); |
5857 | RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); | |
935e2218 CHL |
5858 | } |
5859 | ||
5860 | static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp) | |
5861 | { | |
935e2218 CHL |
5862 | u32 data; |
5863 | static const struct ephy_info e_info_8168ep_3[] = { | |
5864 | { 0x00, 0xffff, 0x10a3 }, | |
5865 | { 0x19, 0xffff, 0x7c00 }, | |
5866 | { 0x1e, 0xffff, 0x20eb }, | |
5867 | { 0x0d, 0xffff, 0x1666 } | |
5868 | }; | |
5869 | ||
5870 | /* disable aspm and clock request before access ephy */ | |
1ef7286e AS |
5871 | RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn); |
5872 | RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en); | |
935e2218 CHL |
5873 | rtl_ephy_init(tp, e_info_8168ep_3, ARRAY_SIZE(e_info_8168ep_3)); |
5874 | ||
5875 | rtl_hw_start_8168ep(tp); | |
5876 | ||
1ef7286e AS |
5877 | RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); |
5878 | RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); | |
935e2218 CHL |
5879 | |
5880 | data = r8168_mac_ocp_read(tp, 0xd3e2); | |
5881 | data &= 0xf000; | |
5882 | data |= 0x0271; | |
5883 | r8168_mac_ocp_write(tp, 0xd3e2, data); | |
5884 | ||
5885 | data = r8168_mac_ocp_read(tp, 0xd3e4); | |
5886 | data &= 0xff00; | |
5887 | r8168_mac_ocp_write(tp, 0xd3e4, data); | |
5888 | ||
5889 | data = r8168_mac_ocp_read(tp, 0xe860); | |
5890 | data |= 0x0080; | |
5891 | r8168_mac_ocp_write(tp, 0xe860, data); | |
5892 | } | |
5893 | ||
61cb532d | 5894 | static void rtl_hw_start_8168(struct rtl8169_private *tp) |
07ce4064 | 5895 | { |
1ef7286e | 5896 | RTL_W8(tp, MaxTxPacketSize, TxPacketMax); |
2dd99530 | 5897 | |
0ae0974e HK |
5898 | tp->cp_cmd &= ~INTT_MASK; |
5899 | tp->cp_cmd |= PktCntrDisable | INTT_1; | |
1ef7286e | 5900 | RTL_W16(tp, CPlusCmd, tp->cp_cmd); |
2dd99530 | 5901 | |
1ef7286e | 5902 | RTL_W16(tp, IntrMitigate, 0x5151); |
2dd99530 | 5903 | |
0e485150 | 5904 | /* Work around for RxFIFO overflow. */ |
811fd301 | 5905 | if (tp->mac_version == RTL_GIGA_MAC_VER_11) { |
da78dbff FR |
5906 | tp->event_slow |= RxFIFOOver | PCSTimeout; |
5907 | tp->event_slow &= ~RxOverflow; | |
0e485150 FR |
5908 | } |
5909 | ||
219a1e9d FR |
5910 | switch (tp->mac_version) { |
5911 | case RTL_GIGA_MAC_VER_11: | |
beb1fe18 | 5912 | rtl_hw_start_8168bb(tp); |
4804b3b3 | 5913 | break; |
219a1e9d FR |
5914 | |
5915 | case RTL_GIGA_MAC_VER_12: | |
5916 | case RTL_GIGA_MAC_VER_17: | |
beb1fe18 | 5917 | rtl_hw_start_8168bef(tp); |
4804b3b3 | 5918 | break; |
219a1e9d FR |
5919 | |
5920 | case RTL_GIGA_MAC_VER_18: | |
beb1fe18 | 5921 | rtl_hw_start_8168cp_1(tp); |
4804b3b3 | 5922 | break; |
219a1e9d FR |
5923 | |
5924 | case RTL_GIGA_MAC_VER_19: | |
beb1fe18 | 5925 | rtl_hw_start_8168c_1(tp); |
4804b3b3 | 5926 | break; |
219a1e9d FR |
5927 | |
5928 | case RTL_GIGA_MAC_VER_20: | |
beb1fe18 | 5929 | rtl_hw_start_8168c_2(tp); |
4804b3b3 | 5930 | break; |
219a1e9d | 5931 | |
197ff761 | 5932 | case RTL_GIGA_MAC_VER_21: |
beb1fe18 | 5933 | rtl_hw_start_8168c_3(tp); |
4804b3b3 | 5934 | break; |
197ff761 | 5935 | |
6fb07058 | 5936 | case RTL_GIGA_MAC_VER_22: |
beb1fe18 | 5937 | rtl_hw_start_8168c_4(tp); |
4804b3b3 | 5938 | break; |
6fb07058 | 5939 | |
ef3386f0 | 5940 | case RTL_GIGA_MAC_VER_23: |
beb1fe18 | 5941 | rtl_hw_start_8168cp_2(tp); |
4804b3b3 | 5942 | break; |
ef3386f0 | 5943 | |
7f3e3d3a | 5944 | case RTL_GIGA_MAC_VER_24: |
beb1fe18 | 5945 | rtl_hw_start_8168cp_3(tp); |
4804b3b3 | 5946 | break; |
7f3e3d3a | 5947 | |
5b538df9 | 5948 | case RTL_GIGA_MAC_VER_25: |
daf9df6d | 5949 | case RTL_GIGA_MAC_VER_26: |
5950 | case RTL_GIGA_MAC_VER_27: | |
beb1fe18 | 5951 | rtl_hw_start_8168d(tp); |
4804b3b3 | 5952 | break; |
5b538df9 | 5953 | |
e6de30d6 | 5954 | case RTL_GIGA_MAC_VER_28: |
beb1fe18 | 5955 | rtl_hw_start_8168d_4(tp); |
4804b3b3 | 5956 | break; |
cecb5fd7 | 5957 | |
4804b3b3 | 5958 | case RTL_GIGA_MAC_VER_31: |
beb1fe18 | 5959 | rtl_hw_start_8168dp(tp); |
4804b3b3 | 5960 | break; |
5961 | ||
01dc7fec | 5962 | case RTL_GIGA_MAC_VER_32: |
5963 | case RTL_GIGA_MAC_VER_33: | |
beb1fe18 | 5964 | rtl_hw_start_8168e_1(tp); |
70090424 HW |
5965 | break; |
5966 | case RTL_GIGA_MAC_VER_34: | |
beb1fe18 | 5967 | rtl_hw_start_8168e_2(tp); |
01dc7fec | 5968 | break; |
e6de30d6 | 5969 | |
c2218925 HW |
5970 | case RTL_GIGA_MAC_VER_35: |
5971 | case RTL_GIGA_MAC_VER_36: | |
beb1fe18 | 5972 | rtl_hw_start_8168f_1(tp); |
c2218925 HW |
5973 | break; |
5974 | ||
b3d7b2f2 HW |
5975 | case RTL_GIGA_MAC_VER_38: |
5976 | rtl_hw_start_8411(tp); | |
5977 | break; | |
5978 | ||
c558386b HW |
5979 | case RTL_GIGA_MAC_VER_40: |
5980 | case RTL_GIGA_MAC_VER_41: | |
5981 | rtl_hw_start_8168g_1(tp); | |
5982 | break; | |
57538c4a | 5983 | case RTL_GIGA_MAC_VER_42: |
5984 | rtl_hw_start_8168g_2(tp); | |
5985 | break; | |
c558386b | 5986 | |
45dd95c4 | 5987 | case RTL_GIGA_MAC_VER_44: |
5988 | rtl_hw_start_8411_2(tp); | |
5989 | break; | |
5990 | ||
6e1d0b89 CHL |
5991 | case RTL_GIGA_MAC_VER_45: |
5992 | case RTL_GIGA_MAC_VER_46: | |
5993 | rtl_hw_start_8168h_1(tp); | |
5994 | break; | |
5995 | ||
935e2218 CHL |
5996 | case RTL_GIGA_MAC_VER_49: |
5997 | rtl_hw_start_8168ep_1(tp); | |
5998 | break; | |
5999 | ||
6000 | case RTL_GIGA_MAC_VER_50: | |
6001 | rtl_hw_start_8168ep_2(tp); | |
6002 | break; | |
6003 | ||
6004 | case RTL_GIGA_MAC_VER_51: | |
6005 | rtl_hw_start_8168ep_3(tp); | |
6006 | break; | |
6007 | ||
219a1e9d FR |
6008 | default: |
6009 | printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n", | |
61cb532d | 6010 | tp->dev->name, tp->mac_version); |
4804b3b3 | 6011 | break; |
219a1e9d | 6012 | } |
07ce4064 | 6013 | } |
1da177e4 | 6014 | |
beb1fe18 | 6015 | static void rtl_hw_start_8102e_1(struct rtl8169_private *tp) |
2857ffb7 | 6016 | { |
350f7596 | 6017 | static const struct ephy_info e_info_8102e_1[] = { |
2857ffb7 FR |
6018 | { 0x01, 0, 0x6e65 }, |
6019 | { 0x02, 0, 0x091f }, | |
6020 | { 0x03, 0, 0xc2f9 }, | |
6021 | { 0x06, 0, 0xafb5 }, | |
6022 | { 0x07, 0, 0x0e00 }, | |
6023 | { 0x19, 0, 0xec80 }, | |
6024 | { 0x01, 0, 0x2e65 }, | |
6025 | { 0x01, 0, 0x6e65 } | |
6026 | }; | |
6027 | u8 cfg1; | |
6028 | ||
beb1fe18 | 6029 | rtl_csi_access_enable_2(tp); |
2857ffb7 | 6030 | |
1ef7286e | 6031 | RTL_W8(tp, DBG_REG, FIX_NAK_1); |
2857ffb7 | 6032 | |
8d98aa39 | 6033 | rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); |
2857ffb7 | 6034 | |
1ef7286e | 6035 | RTL_W8(tp, Config1, |
2857ffb7 | 6036 | LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); |
1ef7286e | 6037 | RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); |
2857ffb7 | 6038 | |
1ef7286e | 6039 | cfg1 = RTL_R8(tp, Config1); |
2857ffb7 | 6040 | if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) |
1ef7286e | 6041 | RTL_W8(tp, Config1, cfg1 & ~LEDS0); |
2857ffb7 | 6042 | |
fdf6fc06 | 6043 | rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1)); |
2857ffb7 FR |
6044 | } |
6045 | ||
beb1fe18 | 6046 | static void rtl_hw_start_8102e_2(struct rtl8169_private *tp) |
2857ffb7 | 6047 | { |
beb1fe18 | 6048 | rtl_csi_access_enable_2(tp); |
2857ffb7 | 6049 | |
8d98aa39 | 6050 | rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); |
2857ffb7 | 6051 | |
1ef7286e AS |
6052 | RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable); |
6053 | RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); | |
2857ffb7 FR |
6054 | } |
6055 | ||
beb1fe18 | 6056 | static void rtl_hw_start_8102e_3(struct rtl8169_private *tp) |
2857ffb7 | 6057 | { |
beb1fe18 | 6058 | rtl_hw_start_8102e_2(tp); |
2857ffb7 | 6059 | |
fdf6fc06 | 6060 | rtl_ephy_write(tp, 0x03, 0xc2f9); |
2857ffb7 FR |
6061 | } |
6062 | ||
beb1fe18 | 6063 | static void rtl_hw_start_8105e_1(struct rtl8169_private *tp) |
5a5e4443 HW |
6064 | { |
6065 | static const struct ephy_info e_info_8105e_1[] = { | |
6066 | { 0x07, 0, 0x4000 }, | |
6067 | { 0x19, 0, 0x0200 }, | |
6068 | { 0x19, 0, 0x0020 }, | |
6069 | { 0x1e, 0, 0x2000 }, | |
6070 | { 0x03, 0, 0x0001 }, | |
6071 | { 0x19, 0, 0x0100 }, | |
6072 | { 0x19, 0, 0x0004 }, | |
6073 | { 0x0a, 0, 0x0020 } | |
6074 | }; | |
6075 | ||
cecb5fd7 | 6076 | /* Force LAN exit from ASPM if Rx/Tx are not idle */ |
1ef7286e | 6077 | RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); |
5a5e4443 | 6078 | |
cecb5fd7 | 6079 | /* Disable Early Tally Counter */ |
1ef7286e | 6080 | RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000); |
5a5e4443 | 6081 | |
1ef7286e AS |
6082 | RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); |
6083 | RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); | |
5a5e4443 | 6084 | |
fdf6fc06 | 6085 | rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1)); |
b51ecea8 | 6086 | |
6087 | rtl_pcie_state_l2l3_enable(tp, false); | |
5a5e4443 HW |
6088 | } |
6089 | ||
beb1fe18 | 6090 | static void rtl_hw_start_8105e_2(struct rtl8169_private *tp) |
5a5e4443 | 6091 | { |
beb1fe18 | 6092 | rtl_hw_start_8105e_1(tp); |
fdf6fc06 | 6093 | rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000); |
5a5e4443 HW |
6094 | } |
6095 | ||
7e18dca1 HW |
6096 | static void rtl_hw_start_8402(struct rtl8169_private *tp) |
6097 | { | |
7e18dca1 HW |
6098 | static const struct ephy_info e_info_8402[] = { |
6099 | { 0x19, 0xffff, 0xff64 }, | |
6100 | { 0x1e, 0, 0x4000 } | |
6101 | }; | |
6102 | ||
6103 | rtl_csi_access_enable_2(tp); | |
6104 | ||
6105 | /* Force LAN exit from ASPM if Rx/Tx are not idle */ | |
1ef7286e | 6106 | RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); |
7e18dca1 | 6107 | |
1ef7286e AS |
6108 | RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO); |
6109 | RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); | |
7e18dca1 | 6110 | |
fdf6fc06 | 6111 | rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402)); |
7e18dca1 | 6112 | |
8d98aa39 | 6113 | rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); |
7e18dca1 | 6114 | |
fdf6fc06 FR |
6115 | rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC); |
6116 | rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC); | |
706123d0 CHL |
6117 | rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC); |
6118 | rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC); | |
fdf6fc06 FR |
6119 | rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); |
6120 | rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); | |
706123d0 | 6121 | rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC); |
b51ecea8 | 6122 | |
6123 | rtl_pcie_state_l2l3_enable(tp, false); | |
7e18dca1 HW |
6124 | } |
6125 | ||
5598bfe5 HW |
6126 | static void rtl_hw_start_8106(struct rtl8169_private *tp) |
6127 | { | |
5598bfe5 | 6128 | /* Force LAN exit from ASPM if Rx/Tx are not idle */ |
1ef7286e | 6129 | RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); |
5598bfe5 | 6130 | |
1ef7286e AS |
6131 | RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN); |
6132 | RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); | |
6133 | RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); | |
b51ecea8 | 6134 | |
6135 | rtl_pcie_state_l2l3_enable(tp, false); | |
5598bfe5 HW |
6136 | } |
6137 | ||
61cb532d | 6138 | static void rtl_hw_start_8101(struct rtl8169_private *tp) |
07ce4064 | 6139 | { |
da78dbff FR |
6140 | if (tp->mac_version >= RTL_GIGA_MAC_VER_30) |
6141 | tp->event_slow &= ~RxFIFOOver; | |
811fd301 | 6142 | |
cecb5fd7 | 6143 | if (tp->mac_version == RTL_GIGA_MAC_VER_13 || |
7d7903b2 | 6144 | tp->mac_version == RTL_GIGA_MAC_VER_16) |
61cb532d | 6145 | pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL, |
8200bc72 | 6146 | PCI_EXP_DEVCTL_NOSNOOP_EN); |
cdf1a608 | 6147 | |
1ef7286e | 6148 | RTL_W8(tp, MaxTxPacketSize, TxPacketMax); |
1a964649 | 6149 | |
12d42c50 | 6150 | tp->cp_cmd &= CPCMD_QUIRK_MASK; |
1ef7286e | 6151 | RTL_W16(tp, CPlusCmd, tp->cp_cmd); |
1a964649 | 6152 | |
2857ffb7 FR |
6153 | switch (tp->mac_version) { |
6154 | case RTL_GIGA_MAC_VER_07: | |
beb1fe18 | 6155 | rtl_hw_start_8102e_1(tp); |
2857ffb7 FR |
6156 | break; |
6157 | ||
6158 | case RTL_GIGA_MAC_VER_08: | |
beb1fe18 | 6159 | rtl_hw_start_8102e_3(tp); |
2857ffb7 FR |
6160 | break; |
6161 | ||
6162 | case RTL_GIGA_MAC_VER_09: | |
beb1fe18 | 6163 | rtl_hw_start_8102e_2(tp); |
2857ffb7 | 6164 | break; |
5a5e4443 HW |
6165 | |
6166 | case RTL_GIGA_MAC_VER_29: | |
beb1fe18 | 6167 | rtl_hw_start_8105e_1(tp); |
5a5e4443 HW |
6168 | break; |
6169 | case RTL_GIGA_MAC_VER_30: | |
beb1fe18 | 6170 | rtl_hw_start_8105e_2(tp); |
5a5e4443 | 6171 | break; |
7e18dca1 HW |
6172 | |
6173 | case RTL_GIGA_MAC_VER_37: | |
6174 | rtl_hw_start_8402(tp); | |
6175 | break; | |
5598bfe5 HW |
6176 | |
6177 | case RTL_GIGA_MAC_VER_39: | |
6178 | rtl_hw_start_8106(tp); | |
6179 | break; | |
58152cd4 | 6180 | case RTL_GIGA_MAC_VER_43: |
6181 | rtl_hw_start_8168g_2(tp); | |
6182 | break; | |
6e1d0b89 CHL |
6183 | case RTL_GIGA_MAC_VER_47: |
6184 | case RTL_GIGA_MAC_VER_48: | |
6185 | rtl_hw_start_8168h_1(tp); | |
6186 | break; | |
cdf1a608 FR |
6187 | } |
6188 | ||
1ef7286e | 6189 | RTL_W16(tp, IntrMitigate, 0x0000); |
1da177e4 LT |
6190 | } |
6191 | ||
6192 | static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) | |
6193 | { | |
d58d46b5 FR |
6194 | struct rtl8169_private *tp = netdev_priv(dev); |
6195 | ||
d58d46b5 FR |
6196 | if (new_mtu > ETH_DATA_LEN) |
6197 | rtl_hw_jumbo_enable(tp); | |
6198 | else | |
6199 | rtl_hw_jumbo_disable(tp); | |
6200 | ||
1da177e4 | 6201 | dev->mtu = new_mtu; |
350fb32a MM |
6202 | netdev_update_features(dev); |
6203 | ||
323bb685 | 6204 | return 0; |
1da177e4 LT |
6205 | } |
6206 | ||
6207 | static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc) | |
6208 | { | |
95e0918d | 6209 | desc->addr = cpu_to_le64(0x0badbadbadbadbadull); |
1da177e4 LT |
6210 | desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask); |
6211 | } | |
6212 | ||
6f0333b8 ED |
6213 | static void rtl8169_free_rx_databuff(struct rtl8169_private *tp, |
6214 | void **data_buff, struct RxDesc *desc) | |
1da177e4 | 6215 | { |
1d0254dd HK |
6216 | dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), |
6217 | R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); | |
48addcc9 | 6218 | |
6f0333b8 ED |
6219 | kfree(*data_buff); |
6220 | *data_buff = NULL; | |
1da177e4 LT |
6221 | rtl8169_make_unusable_by_asic(desc); |
6222 | } | |
6223 | ||
1d0254dd | 6224 | static inline void rtl8169_mark_to_asic(struct RxDesc *desc) |
1da177e4 LT |
6225 | { |
6226 | u32 eor = le32_to_cpu(desc->opts1) & RingEnd; | |
6227 | ||
a0750138 AD |
6228 | /* Force memory writes to complete before releasing descriptor */ |
6229 | dma_wmb(); | |
6230 | ||
1d0254dd | 6231 | desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE); |
1da177e4 LT |
6232 | } |
6233 | ||
6f0333b8 ED |
6234 | static inline void *rtl8169_align(void *data) |
6235 | { | |
6236 | return (void *)ALIGN((long)data, 16); | |
6237 | } | |
6238 | ||
0ecbe1ca SG |
6239 | static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp, |
6240 | struct RxDesc *desc) | |
1da177e4 | 6241 | { |
6f0333b8 | 6242 | void *data; |
1da177e4 | 6243 | dma_addr_t mapping; |
1e1205b7 | 6244 | struct device *d = tp_to_dev(tp); |
d3b404c2 | 6245 | int node = dev_to_node(d); |
1da177e4 | 6246 | |
1d0254dd | 6247 | data = kmalloc_node(R8169_RX_BUF_SIZE, GFP_KERNEL, node); |
6f0333b8 ED |
6248 | if (!data) |
6249 | return NULL; | |
e9f63f30 | 6250 | |
6f0333b8 ED |
6251 | if (rtl8169_align(data) != data) { |
6252 | kfree(data); | |
1d0254dd | 6253 | data = kmalloc_node(R8169_RX_BUF_SIZE + 15, GFP_KERNEL, node); |
6f0333b8 ED |
6254 | if (!data) |
6255 | return NULL; | |
6256 | } | |
3eafe507 | 6257 | |
1d0254dd | 6258 | mapping = dma_map_single(d, rtl8169_align(data), R8169_RX_BUF_SIZE, |
231aee63 | 6259 | DMA_FROM_DEVICE); |
d827d86b SG |
6260 | if (unlikely(dma_mapping_error(d, mapping))) { |
6261 | if (net_ratelimit()) | |
6262 | netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n"); | |
3eafe507 | 6263 | goto err_out; |
d827d86b | 6264 | } |
1da177e4 | 6265 | |
d731af78 HK |
6266 | desc->addr = cpu_to_le64(mapping); |
6267 | rtl8169_mark_to_asic(desc); | |
6f0333b8 | 6268 | return data; |
3eafe507 SG |
6269 | |
6270 | err_out: | |
6271 | kfree(data); | |
6272 | return NULL; | |
1da177e4 LT |
6273 | } |
6274 | ||
6275 | static void rtl8169_rx_clear(struct rtl8169_private *tp) | |
6276 | { | |
07d3f51f | 6277 | unsigned int i; |
1da177e4 LT |
6278 | |
6279 | for (i = 0; i < NUM_RX_DESC; i++) { | |
6f0333b8 ED |
6280 | if (tp->Rx_databuff[i]) { |
6281 | rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i, | |
1da177e4 LT |
6282 | tp->RxDescArray + i); |
6283 | } | |
6284 | } | |
6285 | } | |
6286 | ||
0ecbe1ca | 6287 | static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc) |
1da177e4 | 6288 | { |
0ecbe1ca SG |
6289 | desc->opts1 |= cpu_to_le32(RingEnd); |
6290 | } | |
5b0384f4 | 6291 | |
0ecbe1ca SG |
6292 | static int rtl8169_rx_fill(struct rtl8169_private *tp) |
6293 | { | |
6294 | unsigned int i; | |
1da177e4 | 6295 | |
0ecbe1ca SG |
6296 | for (i = 0; i < NUM_RX_DESC; i++) { |
6297 | void *data; | |
4ae47c2d | 6298 | |
0ecbe1ca | 6299 | data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i); |
6f0333b8 ED |
6300 | if (!data) { |
6301 | rtl8169_make_unusable_by_asic(tp->RxDescArray + i); | |
0ecbe1ca | 6302 | goto err_out; |
6f0333b8 ED |
6303 | } |
6304 | tp->Rx_databuff[i] = data; | |
1da177e4 | 6305 | } |
1da177e4 | 6306 | |
0ecbe1ca SG |
6307 | rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1); |
6308 | return 0; | |
6309 | ||
6310 | err_out: | |
6311 | rtl8169_rx_clear(tp); | |
6312 | return -ENOMEM; | |
1da177e4 LT |
6313 | } |
6314 | ||
b1127e64 | 6315 | static int rtl8169_init_ring(struct rtl8169_private *tp) |
1da177e4 | 6316 | { |
1da177e4 LT |
6317 | rtl8169_init_ring_indexes(tp); |
6318 | ||
b1127e64 HK |
6319 | memset(tp->tx_skb, 0, sizeof(tp->tx_skb)); |
6320 | memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff)); | |
1da177e4 | 6321 | |
0ecbe1ca | 6322 | return rtl8169_rx_fill(tp); |
1da177e4 LT |
6323 | } |
6324 | ||
48addcc9 | 6325 | static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb, |
1da177e4 LT |
6326 | struct TxDesc *desc) |
6327 | { | |
6328 | unsigned int len = tx_skb->len; | |
6329 | ||
48addcc9 SG |
6330 | dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE); |
6331 | ||
1da177e4 LT |
6332 | desc->opts1 = 0x00; |
6333 | desc->opts2 = 0x00; | |
6334 | desc->addr = 0x00; | |
6335 | tx_skb->len = 0; | |
6336 | } | |
6337 | ||
3eafe507 SG |
6338 | static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start, |
6339 | unsigned int n) | |
1da177e4 LT |
6340 | { |
6341 | unsigned int i; | |
6342 | ||
3eafe507 SG |
6343 | for (i = 0; i < n; i++) { |
6344 | unsigned int entry = (start + i) % NUM_TX_DESC; | |
1da177e4 LT |
6345 | struct ring_info *tx_skb = tp->tx_skb + entry; |
6346 | unsigned int len = tx_skb->len; | |
6347 | ||
6348 | if (len) { | |
6349 | struct sk_buff *skb = tx_skb->skb; | |
6350 | ||
1e1205b7 | 6351 | rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb, |
1da177e4 LT |
6352 | tp->TxDescArray + entry); |
6353 | if (skb) { | |
7a4b813c | 6354 | dev_consume_skb_any(skb); |
1da177e4 LT |
6355 | tx_skb->skb = NULL; |
6356 | } | |
1da177e4 LT |
6357 | } |
6358 | } | |
3eafe507 SG |
6359 | } |
6360 | ||
6361 | static void rtl8169_tx_clear(struct rtl8169_private *tp) | |
6362 | { | |
6363 | rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC); | |
1da177e4 LT |
6364 | tp->cur_tx = tp->dirty_tx = 0; |
6365 | } | |
6366 | ||
4422bcd4 | 6367 | static void rtl_reset_work(struct rtl8169_private *tp) |
1da177e4 | 6368 | { |
c4028958 | 6369 | struct net_device *dev = tp->dev; |
56de414c | 6370 | int i; |
1da177e4 | 6371 | |
da78dbff FR |
6372 | napi_disable(&tp->napi); |
6373 | netif_stop_queue(dev); | |
6374 | synchronize_sched(); | |
1da177e4 | 6375 | |
c7c2c39b | 6376 | rtl8169_hw_reset(tp); |
6377 | ||
56de414c | 6378 | for (i = 0; i < NUM_RX_DESC; i++) |
1d0254dd | 6379 | rtl8169_mark_to_asic(tp->RxDescArray + i); |
56de414c | 6380 | |
1da177e4 | 6381 | rtl8169_tx_clear(tp); |
c7c2c39b | 6382 | rtl8169_init_ring_indexes(tp); |
1da177e4 | 6383 | |
da78dbff | 6384 | napi_enable(&tp->napi); |
61cb532d | 6385 | rtl_hw_start(tp); |
56de414c | 6386 | netif_wake_queue(dev); |
1ef7286e | 6387 | rtl8169_check_link_status(dev, tp); |
1da177e4 LT |
6388 | } |
6389 | ||
6390 | static void rtl8169_tx_timeout(struct net_device *dev) | |
6391 | { | |
da78dbff FR |
6392 | struct rtl8169_private *tp = netdev_priv(dev); |
6393 | ||
6394 | rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); | |
1da177e4 LT |
6395 | } |
6396 | ||
6397 | static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, | |
2b7b4318 | 6398 | u32 *opts) |
1da177e4 LT |
6399 | { |
6400 | struct skb_shared_info *info = skb_shinfo(skb); | |
6401 | unsigned int cur_frag, entry; | |
6e1d0b89 | 6402 | struct TxDesc *uninitialized_var(txd); |
1e1205b7 | 6403 | struct device *d = tp_to_dev(tp); |
1da177e4 LT |
6404 | |
6405 | entry = tp->cur_tx; | |
6406 | for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { | |
9e903e08 | 6407 | const skb_frag_t *frag = info->frags + cur_frag; |
1da177e4 LT |
6408 | dma_addr_t mapping; |
6409 | u32 status, len; | |
6410 | void *addr; | |
6411 | ||
6412 | entry = (entry + 1) % NUM_TX_DESC; | |
6413 | ||
6414 | txd = tp->TxDescArray + entry; | |
9e903e08 | 6415 | len = skb_frag_size(frag); |
929f6189 | 6416 | addr = skb_frag_address(frag); |
48addcc9 | 6417 | mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE); |
d827d86b SG |
6418 | if (unlikely(dma_mapping_error(d, mapping))) { |
6419 | if (net_ratelimit()) | |
6420 | netif_err(tp, drv, tp->dev, | |
6421 | "Failed to map TX fragments DMA!\n"); | |
3eafe507 | 6422 | goto err_out; |
d827d86b | 6423 | } |
1da177e4 | 6424 | |
cecb5fd7 | 6425 | /* Anti gcc 2.95.3 bugware (sic) */ |
2b7b4318 FR |
6426 | status = opts[0] | len | |
6427 | (RingEnd * !((entry + 1) % NUM_TX_DESC)); | |
1da177e4 LT |
6428 | |
6429 | txd->opts1 = cpu_to_le32(status); | |
2b7b4318 | 6430 | txd->opts2 = cpu_to_le32(opts[1]); |
1da177e4 LT |
6431 | txd->addr = cpu_to_le64(mapping); |
6432 | ||
6433 | tp->tx_skb[entry].len = len; | |
6434 | } | |
6435 | ||
6436 | if (cur_frag) { | |
6437 | tp->tx_skb[entry].skb = skb; | |
6438 | txd->opts1 |= cpu_to_le32(LastFrag); | |
6439 | } | |
6440 | ||
6441 | return cur_frag; | |
3eafe507 SG |
6442 | |
6443 | err_out: | |
6444 | rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag); | |
6445 | return -EIO; | |
1da177e4 LT |
6446 | } |
6447 | ||
b423e9ae | 6448 | static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb) |
6449 | { | |
6450 | return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34; | |
6451 | } | |
6452 | ||
e974604b | 6453 | static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, |
6454 | struct net_device *dev); | |
6455 | /* r8169_csum_workaround() | |
6456 | * The hw limites the value the transport offset. When the offset is out of the | |
6457 | * range, calculate the checksum by sw. | |
6458 | */ | |
6459 | static void r8169_csum_workaround(struct rtl8169_private *tp, | |
6460 | struct sk_buff *skb) | |
6461 | { | |
6462 | if (skb_shinfo(skb)->gso_size) { | |
6463 | netdev_features_t features = tp->dev->features; | |
6464 | struct sk_buff *segs, *nskb; | |
6465 | ||
6466 | features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6); | |
6467 | segs = skb_gso_segment(skb, features); | |
6468 | if (IS_ERR(segs) || !segs) | |
6469 | goto drop; | |
6470 | ||
6471 | do { | |
6472 | nskb = segs; | |
6473 | segs = segs->next; | |
6474 | nskb->next = NULL; | |
6475 | rtl8169_start_xmit(nskb, tp->dev); | |
6476 | } while (segs); | |
6477 | ||
eb781397 | 6478 | dev_consume_skb_any(skb); |
e974604b | 6479 | } else if (skb->ip_summed == CHECKSUM_PARTIAL) { |
6480 | if (skb_checksum_help(skb) < 0) | |
6481 | goto drop; | |
6482 | ||
6483 | rtl8169_start_xmit(skb, tp->dev); | |
6484 | } else { | |
6485 | struct net_device_stats *stats; | |
6486 | ||
6487 | drop: | |
6488 | stats = &tp->dev->stats; | |
6489 | stats->tx_dropped++; | |
eb781397 | 6490 | dev_kfree_skb_any(skb); |
e974604b | 6491 | } |
6492 | } | |
6493 | ||
6494 | /* msdn_giant_send_check() | |
6495 | * According to the document of microsoft, the TCP Pseudo Header excludes the | |
6496 | * packet length for IPv6 TCP large packets. | |
6497 | */ | |
6498 | static int msdn_giant_send_check(struct sk_buff *skb) | |
6499 | { | |
6500 | const struct ipv6hdr *ipv6h; | |
6501 | struct tcphdr *th; | |
6502 | int ret; | |
6503 | ||
6504 | ret = skb_cow_head(skb, 0); | |
6505 | if (ret) | |
6506 | return ret; | |
6507 | ||
6508 | ipv6h = ipv6_hdr(skb); | |
6509 | th = tcp_hdr(skb); | |
6510 | ||
6511 | th->check = 0; | |
6512 | th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0); | |
6513 | ||
6514 | return ret; | |
6515 | } | |
6516 | ||
5888d3fc | 6517 | static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp, |
6518 | struct sk_buff *skb, u32 *opts) | |
1da177e4 | 6519 | { |
350fb32a MM |
6520 | u32 mss = skb_shinfo(skb)->gso_size; |
6521 | ||
2b7b4318 FR |
6522 | if (mss) { |
6523 | opts[0] |= TD_LSO; | |
5888d3fc | 6524 | opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT; |
6525 | } else if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
6526 | const struct iphdr *ip = ip_hdr(skb); | |
6527 | ||
6528 | if (ip->protocol == IPPROTO_TCP) | |
6529 | opts[0] |= TD0_IP_CS | TD0_TCP_CS; | |
6530 | else if (ip->protocol == IPPROTO_UDP) | |
6531 | opts[0] |= TD0_IP_CS | TD0_UDP_CS; | |
6532 | else | |
6533 | WARN_ON_ONCE(1); | |
6534 | } | |
6535 | ||
6536 | return true; | |
6537 | } | |
6538 | ||
6539 | static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp, | |
6540 | struct sk_buff *skb, u32 *opts) | |
6541 | { | |
bdfa4ed6 | 6542 | u32 transport_offset = (u32)skb_transport_offset(skb); |
5888d3fc | 6543 | u32 mss = skb_shinfo(skb)->gso_size; |
6544 | ||
6545 | if (mss) { | |
e974604b | 6546 | if (transport_offset > GTTCPHO_MAX) { |
6547 | netif_warn(tp, tx_err, tp->dev, | |
6548 | "Invalid transport offset 0x%x for TSO\n", | |
6549 | transport_offset); | |
6550 | return false; | |
6551 | } | |
6552 | ||
4ff36466 | 6553 | switch (vlan_get_protocol(skb)) { |
e974604b | 6554 | case htons(ETH_P_IP): |
6555 | opts[0] |= TD1_GTSENV4; | |
6556 | break; | |
6557 | ||
6558 | case htons(ETH_P_IPV6): | |
6559 | if (msdn_giant_send_check(skb)) | |
6560 | return false; | |
6561 | ||
6562 | opts[0] |= TD1_GTSENV6; | |
6563 | break; | |
6564 | ||
6565 | default: | |
6566 | WARN_ON_ONCE(1); | |
6567 | break; | |
6568 | } | |
6569 | ||
bdfa4ed6 | 6570 | opts[0] |= transport_offset << GTTCPHO_SHIFT; |
5888d3fc | 6571 | opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT; |
2b7b4318 | 6572 | } else if (skb->ip_summed == CHECKSUM_PARTIAL) { |
e974604b | 6573 | u8 ip_protocol; |
1da177e4 | 6574 | |
b423e9ae | 6575 | if (unlikely(rtl_test_hw_pad_bug(tp, skb))) |
207c5f44 | 6576 | return !(skb_checksum_help(skb) || eth_skb_pad(skb)); |
b423e9ae | 6577 | |
e974604b | 6578 | if (transport_offset > TCPHO_MAX) { |
6579 | netif_warn(tp, tx_err, tp->dev, | |
6580 | "Invalid transport offset 0x%x\n", | |
6581 | transport_offset); | |
6582 | return false; | |
6583 | } | |
6584 | ||
4ff36466 | 6585 | switch (vlan_get_protocol(skb)) { |
e974604b | 6586 | case htons(ETH_P_IP): |
6587 | opts[1] |= TD1_IPv4_CS; | |
6588 | ip_protocol = ip_hdr(skb)->protocol; | |
6589 | break; | |
6590 | ||
6591 | case htons(ETH_P_IPV6): | |
6592 | opts[1] |= TD1_IPv6_CS; | |
6593 | ip_protocol = ipv6_hdr(skb)->nexthdr; | |
6594 | break; | |
6595 | ||
6596 | default: | |
6597 | ip_protocol = IPPROTO_RAW; | |
6598 | break; | |
6599 | } | |
6600 | ||
6601 | if (ip_protocol == IPPROTO_TCP) | |
6602 | opts[1] |= TD1_TCP_CS; | |
6603 | else if (ip_protocol == IPPROTO_UDP) | |
6604 | opts[1] |= TD1_UDP_CS; | |
2b7b4318 FR |
6605 | else |
6606 | WARN_ON_ONCE(1); | |
e974604b | 6607 | |
6608 | opts[1] |= transport_offset << TCPHO_SHIFT; | |
b423e9ae | 6609 | } else { |
6610 | if (unlikely(rtl_test_hw_pad_bug(tp, skb))) | |
207c5f44 | 6611 | return !eth_skb_pad(skb); |
1da177e4 | 6612 | } |
5888d3fc | 6613 | |
b423e9ae | 6614 | return true; |
1da177e4 LT |
6615 | } |
6616 | ||
61357325 SH |
6617 | static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, |
6618 | struct net_device *dev) | |
1da177e4 LT |
6619 | { |
6620 | struct rtl8169_private *tp = netdev_priv(dev); | |
3eafe507 | 6621 | unsigned int entry = tp->cur_tx % NUM_TX_DESC; |
1da177e4 | 6622 | struct TxDesc *txd = tp->TxDescArray + entry; |
1e1205b7 | 6623 | struct device *d = tp_to_dev(tp); |
1da177e4 LT |
6624 | dma_addr_t mapping; |
6625 | u32 status, len; | |
2b7b4318 | 6626 | u32 opts[2]; |
3eafe507 | 6627 | int frags; |
5b0384f4 | 6628 | |
477206a0 | 6629 | if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) { |
bf82c189 | 6630 | netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n"); |
3eafe507 | 6631 | goto err_stop_0; |
1da177e4 LT |
6632 | } |
6633 | ||
6634 | if (unlikely(le32_to_cpu(txd->opts1) & DescOwn)) | |
3eafe507 SG |
6635 | goto err_stop_0; |
6636 | ||
b423e9ae | 6637 | opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb)); |
6638 | opts[0] = DescOwn; | |
6639 | ||
e974604b | 6640 | if (!tp->tso_csum(tp, skb, opts)) { |
6641 | r8169_csum_workaround(tp, skb); | |
6642 | return NETDEV_TX_OK; | |
6643 | } | |
b423e9ae | 6644 | |
3eafe507 | 6645 | len = skb_headlen(skb); |
48addcc9 | 6646 | mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE); |
d827d86b SG |
6647 | if (unlikely(dma_mapping_error(d, mapping))) { |
6648 | if (net_ratelimit()) | |
6649 | netif_err(tp, drv, dev, "Failed to map TX DMA!\n"); | |
3eafe507 | 6650 | goto err_dma_0; |
d827d86b | 6651 | } |
3eafe507 SG |
6652 | |
6653 | tp->tx_skb[entry].len = len; | |
6654 | txd->addr = cpu_to_le64(mapping); | |
1da177e4 | 6655 | |
2b7b4318 | 6656 | frags = rtl8169_xmit_frags(tp, skb, opts); |
3eafe507 SG |
6657 | if (frags < 0) |
6658 | goto err_dma_1; | |
6659 | else if (frags) | |
2b7b4318 | 6660 | opts[0] |= FirstFrag; |
3eafe507 | 6661 | else { |
2b7b4318 | 6662 | opts[0] |= FirstFrag | LastFrag; |
1da177e4 LT |
6663 | tp->tx_skb[entry].skb = skb; |
6664 | } | |
6665 | ||
2b7b4318 FR |
6666 | txd->opts2 = cpu_to_le32(opts[1]); |
6667 | ||
5047fb5d RC |
6668 | skb_tx_timestamp(skb); |
6669 | ||
a0750138 AD |
6670 | /* Force memory writes to complete before releasing descriptor */ |
6671 | dma_wmb(); | |
1da177e4 | 6672 | |
cecb5fd7 | 6673 | /* Anti gcc 2.95.3 bugware (sic) */ |
2b7b4318 | 6674 | status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC)); |
1da177e4 LT |
6675 | txd->opts1 = cpu_to_le32(status); |
6676 | ||
a0750138 | 6677 | /* Force all memory writes to complete before notifying device */ |
4c020a96 | 6678 | wmb(); |
1da177e4 | 6679 | |
a0750138 AD |
6680 | tp->cur_tx += frags + 1; |
6681 | ||
1ef7286e | 6682 | RTL_W8(tp, TxPoll, NPQ); |
1da177e4 | 6683 | |
87cda7cb | 6684 | mmiowb(); |
da78dbff | 6685 | |
87cda7cb | 6686 | if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) { |
ae1f23fb FR |
6687 | /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must |
6688 | * not miss a ring update when it notices a stopped queue. | |
6689 | */ | |
6690 | smp_wmb(); | |
1da177e4 | 6691 | netif_stop_queue(dev); |
ae1f23fb FR |
6692 | /* Sync with rtl_tx: |
6693 | * - publish queue status and cur_tx ring index (write barrier) | |
6694 | * - refresh dirty_tx ring index (read barrier). | |
6695 | * May the current thread have a pessimistic view of the ring | |
6696 | * status and forget to wake up queue, a racing rtl_tx thread | |
6697 | * can't. | |
6698 | */ | |
1e874e04 | 6699 | smp_mb(); |
477206a0 | 6700 | if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) |
1da177e4 LT |
6701 | netif_wake_queue(dev); |
6702 | } | |
6703 | ||
61357325 | 6704 | return NETDEV_TX_OK; |
1da177e4 | 6705 | |
3eafe507 | 6706 | err_dma_1: |
48addcc9 | 6707 | rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd); |
3eafe507 | 6708 | err_dma_0: |
989c9ba1 | 6709 | dev_kfree_skb_any(skb); |
3eafe507 SG |
6710 | dev->stats.tx_dropped++; |
6711 | return NETDEV_TX_OK; | |
6712 | ||
6713 | err_stop_0: | |
1da177e4 | 6714 | netif_stop_queue(dev); |
cebf8cc7 | 6715 | dev->stats.tx_dropped++; |
61357325 | 6716 | return NETDEV_TX_BUSY; |
1da177e4 LT |
6717 | } |
6718 | ||
6719 | static void rtl8169_pcierr_interrupt(struct net_device *dev) | |
6720 | { | |
6721 | struct rtl8169_private *tp = netdev_priv(dev); | |
6722 | struct pci_dev *pdev = tp->pci_dev; | |
1da177e4 LT |
6723 | u16 pci_status, pci_cmd; |
6724 | ||
6725 | pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); | |
6726 | pci_read_config_word(pdev, PCI_STATUS, &pci_status); | |
6727 | ||
bf82c189 JP |
6728 | netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n", |
6729 | pci_cmd, pci_status); | |
1da177e4 LT |
6730 | |
6731 | /* | |
6732 | * The recovery sequence below admits a very elaborated explanation: | |
6733 | * - it seems to work; | |
d03902b8 FR |
6734 | * - I did not see what else could be done; |
6735 | * - it makes iop3xx happy. | |
1da177e4 LT |
6736 | * |
6737 | * Feel free to adjust to your needs. | |
6738 | */ | |
a27993f3 | 6739 | if (pdev->broken_parity_status) |
d03902b8 FR |
6740 | pci_cmd &= ~PCI_COMMAND_PARITY; |
6741 | else | |
6742 | pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY; | |
6743 | ||
6744 | pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); | |
1da177e4 LT |
6745 | |
6746 | pci_write_config_word(pdev, PCI_STATUS, | |
6747 | pci_status & (PCI_STATUS_DETECTED_PARITY | | |
6748 | PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT | | |
6749 | PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT)); | |
6750 | ||
6751 | /* The infamous DAC f*ckup only happens at boot time */ | |
9fba0812 | 6752 | if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) { |
bf82c189 | 6753 | netif_info(tp, intr, dev, "disabling PCI DAC\n"); |
1da177e4 | 6754 | tp->cp_cmd &= ~PCIDAC; |
1ef7286e | 6755 | RTL_W16(tp, CPlusCmd, tp->cp_cmd); |
1da177e4 | 6756 | dev->features &= ~NETIF_F_HIGHDMA; |
1da177e4 LT |
6757 | } |
6758 | ||
e6de30d6 | 6759 | rtl8169_hw_reset(tp); |
d03902b8 | 6760 | |
98ddf986 | 6761 | rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); |
1da177e4 LT |
6762 | } |
6763 | ||
da78dbff | 6764 | static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp) |
1da177e4 LT |
6765 | { |
6766 | unsigned int dirty_tx, tx_left; | |
6767 | ||
1da177e4 LT |
6768 | dirty_tx = tp->dirty_tx; |
6769 | smp_rmb(); | |
6770 | tx_left = tp->cur_tx - dirty_tx; | |
6771 | ||
6772 | while (tx_left > 0) { | |
6773 | unsigned int entry = dirty_tx % NUM_TX_DESC; | |
6774 | struct ring_info *tx_skb = tp->tx_skb + entry; | |
1da177e4 LT |
6775 | u32 status; |
6776 | ||
1da177e4 LT |
6777 | status = le32_to_cpu(tp->TxDescArray[entry].opts1); |
6778 | if (status & DescOwn) | |
6779 | break; | |
6780 | ||
a0750138 AD |
6781 | /* This barrier is needed to keep us from reading |
6782 | * any other fields out of the Tx descriptor until | |
6783 | * we know the status of DescOwn | |
6784 | */ | |
6785 | dma_rmb(); | |
6786 | ||
1e1205b7 | 6787 | rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb, |
48addcc9 | 6788 | tp->TxDescArray + entry); |
1da177e4 | 6789 | if (status & LastFrag) { |
87cda7cb DM |
6790 | u64_stats_update_begin(&tp->tx_stats.syncp); |
6791 | tp->tx_stats.packets++; | |
6792 | tp->tx_stats.bytes += tx_skb->skb->len; | |
6793 | u64_stats_update_end(&tp->tx_stats.syncp); | |
7a4b813c | 6794 | dev_consume_skb_any(tx_skb->skb); |
1da177e4 LT |
6795 | tx_skb->skb = NULL; |
6796 | } | |
6797 | dirty_tx++; | |
6798 | tx_left--; | |
6799 | } | |
6800 | ||
6801 | if (tp->dirty_tx != dirty_tx) { | |
6802 | tp->dirty_tx = dirty_tx; | |
ae1f23fb FR |
6803 | /* Sync with rtl8169_start_xmit: |
6804 | * - publish dirty_tx ring index (write barrier) | |
6805 | * - refresh cur_tx ring index and queue status (read barrier) | |
6806 | * May the current thread miss the stopped queue condition, | |
6807 | * a racing xmit thread can only have a right view of the | |
6808 | * ring status. | |
6809 | */ | |
1e874e04 | 6810 | smp_mb(); |
1da177e4 | 6811 | if (netif_queue_stopped(dev) && |
477206a0 | 6812 | TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) { |
1da177e4 LT |
6813 | netif_wake_queue(dev); |
6814 | } | |
d78ae2dc FR |
6815 | /* |
6816 | * 8168 hack: TxPoll requests are lost when the Tx packets are | |
6817 | * too close. Let's kick an extra TxPoll request when a burst | |
6818 | * of start_xmit activity is detected (if it is not detected, | |
6819 | * it is slow enough). -- FR | |
6820 | */ | |
1ef7286e AS |
6821 | if (tp->cur_tx != dirty_tx) |
6822 | RTL_W8(tp, TxPoll, NPQ); | |
1da177e4 LT |
6823 | } |
6824 | } | |
6825 | ||
126fa4b9 FR |
6826 | static inline int rtl8169_fragmented_frame(u32 status) |
6827 | { | |
6828 | return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); | |
6829 | } | |
6830 | ||
adea1ac7 | 6831 | static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1) |
1da177e4 | 6832 | { |
1da177e4 LT |
6833 | u32 status = opts1 & RxProtoMask; |
6834 | ||
6835 | if (((status == RxProtoTCP) && !(opts1 & TCPFail)) || | |
d5d3ebe3 | 6836 | ((status == RxProtoUDP) && !(opts1 & UDPFail))) |
1da177e4 LT |
6837 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
6838 | else | |
bc8acf2c | 6839 | skb_checksum_none_assert(skb); |
1da177e4 LT |
6840 | } |
6841 | ||
6f0333b8 ED |
6842 | static struct sk_buff *rtl8169_try_rx_copy(void *data, |
6843 | struct rtl8169_private *tp, | |
6844 | int pkt_size, | |
6845 | dma_addr_t addr) | |
1da177e4 | 6846 | { |
b449655f | 6847 | struct sk_buff *skb; |
1e1205b7 | 6848 | struct device *d = tp_to_dev(tp); |
b449655f | 6849 | |
6f0333b8 | 6850 | data = rtl8169_align(data); |
48addcc9 | 6851 | dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE); |
6f0333b8 | 6852 | prefetch(data); |
e2338f86 | 6853 | skb = napi_alloc_skb(&tp->napi, pkt_size); |
6f0333b8 | 6854 | if (skb) |
8a67aa86 | 6855 | skb_copy_to_linear_data(skb, data, pkt_size); |
48addcc9 SG |
6856 | dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE); |
6857 | ||
6f0333b8 | 6858 | return skb; |
1da177e4 LT |
6859 | } |
6860 | ||
da78dbff | 6861 | static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget) |
1da177e4 LT |
6862 | { |
6863 | unsigned int cur_rx, rx_left; | |
6f0333b8 | 6864 | unsigned int count; |
1da177e4 | 6865 | |
1da177e4 | 6866 | cur_rx = tp->cur_rx; |
1da177e4 | 6867 | |
9fba0812 | 6868 | for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) { |
1da177e4 | 6869 | unsigned int entry = cur_rx % NUM_RX_DESC; |
126fa4b9 | 6870 | struct RxDesc *desc = tp->RxDescArray + entry; |
1da177e4 LT |
6871 | u32 status; |
6872 | ||
6202806e | 6873 | status = le32_to_cpu(desc->opts1); |
1da177e4 LT |
6874 | if (status & DescOwn) |
6875 | break; | |
a0750138 AD |
6876 | |
6877 | /* This barrier is needed to keep us from reading | |
6878 | * any other fields out of the Rx descriptor until | |
6879 | * we know the status of DescOwn | |
6880 | */ | |
6881 | dma_rmb(); | |
6882 | ||
4dcb7d33 | 6883 | if (unlikely(status & RxRES)) { |
bf82c189 JP |
6884 | netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n", |
6885 | status); | |
cebf8cc7 | 6886 | dev->stats.rx_errors++; |
1da177e4 | 6887 | if (status & (RxRWT | RxRUNT)) |
cebf8cc7 | 6888 | dev->stats.rx_length_errors++; |
1da177e4 | 6889 | if (status & RxCRC) |
cebf8cc7 | 6890 | dev->stats.rx_crc_errors++; |
6202806e HK |
6891 | /* RxFOVF is a reserved bit on later chip versions */ |
6892 | if (tp->mac_version == RTL_GIGA_MAC_VER_01 && | |
6893 | status & RxFOVF) { | |
da78dbff | 6894 | rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); |
cebf8cc7 | 6895 | dev->stats.rx_fifo_errors++; |
6202806e HK |
6896 | } else if (status & (RxRUNT | RxCRC) && |
6897 | !(status & RxRWT) && | |
6898 | dev->features & NETIF_F_RXALL) { | |
6bbe021d | 6899 | goto process_pkt; |
6202806e | 6900 | } |
1da177e4 | 6901 | } else { |
6f0333b8 | 6902 | struct sk_buff *skb; |
6bbe021d BG |
6903 | dma_addr_t addr; |
6904 | int pkt_size; | |
6905 | ||
6906 | process_pkt: | |
6907 | addr = le64_to_cpu(desc->addr); | |
79d0c1d2 BG |
6908 | if (likely(!(dev->features & NETIF_F_RXFCS))) |
6909 | pkt_size = (status & 0x00003fff) - 4; | |
6910 | else | |
6911 | pkt_size = status & 0x00003fff; | |
1da177e4 | 6912 | |
126fa4b9 FR |
6913 | /* |
6914 | * The driver does not support incoming fragmented | |
6915 | * frames. They are seen as a symptom of over-mtu | |
6916 | * sized frames. | |
6917 | */ | |
6918 | if (unlikely(rtl8169_fragmented_frame(status))) { | |
cebf8cc7 FR |
6919 | dev->stats.rx_dropped++; |
6920 | dev->stats.rx_length_errors++; | |
ce11ff5e | 6921 | goto release_descriptor; |
126fa4b9 FR |
6922 | } |
6923 | ||
6f0333b8 ED |
6924 | skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry], |
6925 | tp, pkt_size, addr); | |
6f0333b8 ED |
6926 | if (!skb) { |
6927 | dev->stats.rx_dropped++; | |
ce11ff5e | 6928 | goto release_descriptor; |
1da177e4 LT |
6929 | } |
6930 | ||
adea1ac7 | 6931 | rtl8169_rx_csum(skb, status); |
1da177e4 LT |
6932 | skb_put(skb, pkt_size); |
6933 | skb->protocol = eth_type_trans(skb, dev); | |
6934 | ||
7a8fc77b FR |
6935 | rtl8169_rx_vlan_tag(desc, skb); |
6936 | ||
39174291 | 6937 | if (skb->pkt_type == PACKET_MULTICAST) |
6938 | dev->stats.multicast++; | |
6939 | ||
56de414c | 6940 | napi_gro_receive(&tp->napi, skb); |
1da177e4 | 6941 | |
8027aa24 JW |
6942 | u64_stats_update_begin(&tp->rx_stats.syncp); |
6943 | tp->rx_stats.packets++; | |
6944 | tp->rx_stats.bytes += pkt_size; | |
6945 | u64_stats_update_end(&tp->rx_stats.syncp); | |
1da177e4 | 6946 | } |
ce11ff5e | 6947 | release_descriptor: |
6948 | desc->opts2 = 0; | |
1d0254dd | 6949 | rtl8169_mark_to_asic(desc); |
1da177e4 LT |
6950 | } |
6951 | ||
6952 | count = cur_rx - tp->cur_rx; | |
6953 | tp->cur_rx = cur_rx; | |
6954 | ||
1da177e4 LT |
6955 | return count; |
6956 | } | |
6957 | ||
07d3f51f | 6958 | static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) |
1da177e4 | 6959 | { |
ebcd5daa | 6960 | struct rtl8169_private *tp = dev_instance; |
1da177e4 | 6961 | int handled = 0; |
9085cdfa | 6962 | u16 status; |
1da177e4 | 6963 | |
9085cdfa | 6964 | status = rtl_get_events(tp); |
da78dbff FR |
6965 | if (status && status != 0xffff) { |
6966 | status &= RTL_EVENT_NAPI | tp->event_slow; | |
6967 | if (status) { | |
6968 | handled = 1; | |
1da177e4 | 6969 | |
da78dbff | 6970 | rtl_irq_disable(tp); |
9a899a35 | 6971 | napi_schedule_irqoff(&tp->napi); |
f11a377b | 6972 | } |
da78dbff FR |
6973 | } |
6974 | return IRQ_RETVAL(handled); | |
6975 | } | |
1da177e4 | 6976 | |
da78dbff FR |
6977 | /* |
6978 | * Workqueue context. | |
6979 | */ | |
6980 | static void rtl_slow_event_work(struct rtl8169_private *tp) | |
6981 | { | |
6982 | struct net_device *dev = tp->dev; | |
6983 | u16 status; | |
6984 | ||
6985 | status = rtl_get_events(tp) & tp->event_slow; | |
6986 | rtl_ack_events(tp, status); | |
1da177e4 | 6987 | |
da78dbff FR |
6988 | if (unlikely(status & RxFIFOOver)) { |
6989 | switch (tp->mac_version) { | |
6990 | /* Work around for rx fifo overflow */ | |
6991 | case RTL_GIGA_MAC_VER_11: | |
6992 | netif_stop_queue(dev); | |
934714d0 FR |
6993 | /* XXX - Hack alert. See rtl_task(). */ |
6994 | set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags); | |
da78dbff | 6995 | default: |
f11a377b DD |
6996 | break; |
6997 | } | |
da78dbff | 6998 | } |
1da177e4 | 6999 | |
da78dbff FR |
7000 | if (unlikely(status & SYSErr)) |
7001 | rtl8169_pcierr_interrupt(dev); | |
0e485150 | 7002 | |
da78dbff | 7003 | if (status & LinkChg) |
1ef7286e | 7004 | rtl8169_check_link_status(dev, tp); |
1da177e4 | 7005 | |
7dbb4918 | 7006 | rtl_irq_enable_all(tp); |
1da177e4 LT |
7007 | } |
7008 | ||
4422bcd4 FR |
7009 | static void rtl_task(struct work_struct *work) |
7010 | { | |
da78dbff FR |
7011 | static const struct { |
7012 | int bitnr; | |
7013 | void (*action)(struct rtl8169_private *); | |
7014 | } rtl_work[] = { | |
934714d0 | 7015 | /* XXX - keep rtl_slow_event_work() as first element. */ |
da78dbff FR |
7016 | { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work }, |
7017 | { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work }, | |
7018 | { RTL_FLAG_TASK_PHY_PENDING, rtl_phy_work } | |
7019 | }; | |
4422bcd4 FR |
7020 | struct rtl8169_private *tp = |
7021 | container_of(work, struct rtl8169_private, wk.work); | |
da78dbff FR |
7022 | struct net_device *dev = tp->dev; |
7023 | int i; | |
7024 | ||
7025 | rtl_lock_work(tp); | |
7026 | ||
6c4a70c5 FR |
7027 | if (!netif_running(dev) || |
7028 | !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags)) | |
da78dbff FR |
7029 | goto out_unlock; |
7030 | ||
7031 | for (i = 0; i < ARRAY_SIZE(rtl_work); i++) { | |
7032 | bool pending; | |
7033 | ||
da78dbff | 7034 | pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags); |
da78dbff FR |
7035 | if (pending) |
7036 | rtl_work[i].action(tp); | |
7037 | } | |
4422bcd4 | 7038 | |
da78dbff FR |
7039 | out_unlock: |
7040 | rtl_unlock_work(tp); | |
4422bcd4 FR |
7041 | } |
7042 | ||
bea3348e | 7043 | static int rtl8169_poll(struct napi_struct *napi, int budget) |
1da177e4 | 7044 | { |
bea3348e SH |
7045 | struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); |
7046 | struct net_device *dev = tp->dev; | |
da78dbff FR |
7047 | u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow; |
7048 | int work_done= 0; | |
7049 | u16 status; | |
7050 | ||
7051 | status = rtl_get_events(tp); | |
7052 | rtl_ack_events(tp, status & ~tp->event_slow); | |
7053 | ||
7054 | if (status & RTL_EVENT_NAPI_RX) | |
7055 | work_done = rtl_rx(dev, tp, (u32) budget); | |
7056 | ||
7057 | if (status & RTL_EVENT_NAPI_TX) | |
7058 | rtl_tx(dev, tp); | |
1da177e4 | 7059 | |
da78dbff FR |
7060 | if (status & tp->event_slow) { |
7061 | enable_mask &= ~tp->event_slow; | |
7062 | ||
7063 | rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING); | |
7064 | } | |
1da177e4 | 7065 | |
bea3348e | 7066 | if (work_done < budget) { |
6ad20165 | 7067 | napi_complete_done(napi, work_done); |
f11a377b | 7068 | |
da78dbff FR |
7069 | rtl_irq_enable(tp, enable_mask); |
7070 | mmiowb(); | |
1da177e4 LT |
7071 | } |
7072 | ||
bea3348e | 7073 | return work_done; |
1da177e4 | 7074 | } |
1da177e4 | 7075 | |
1ef7286e | 7076 | static void rtl8169_rx_missed(struct net_device *dev) |
523a6094 FR |
7077 | { |
7078 | struct rtl8169_private *tp = netdev_priv(dev); | |
7079 | ||
7080 | if (tp->mac_version > RTL_GIGA_MAC_VER_06) | |
7081 | return; | |
7082 | ||
1ef7286e AS |
7083 | dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff; |
7084 | RTL_W32(tp, RxMissed, 0); | |
523a6094 FR |
7085 | } |
7086 | ||
1da177e4 LT |
7087 | static void rtl8169_down(struct net_device *dev) |
7088 | { | |
7089 | struct rtl8169_private *tp = netdev_priv(dev); | |
1da177e4 | 7090 | |
4876cc1e | 7091 | del_timer_sync(&tp->timer); |
1da177e4 | 7092 | |
93dd79e8 | 7093 | napi_disable(&tp->napi); |
da78dbff | 7094 | netif_stop_queue(dev); |
1da177e4 | 7095 | |
92fc43b4 | 7096 | rtl8169_hw_reset(tp); |
323bb685 SG |
7097 | /* |
7098 | * At this point device interrupts can not be enabled in any function, | |
209e5ac8 FR |
7099 | * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task) |
7100 | * and napi is disabled (rtl8169_poll). | |
323bb685 | 7101 | */ |
1ef7286e | 7102 | rtl8169_rx_missed(dev); |
1da177e4 | 7103 | |
1da177e4 | 7104 | /* Give a racing hard_start_xmit a few cycles to complete. */ |
da78dbff | 7105 | synchronize_sched(); |
1da177e4 | 7106 | |
1da177e4 LT |
7107 | rtl8169_tx_clear(tp); |
7108 | ||
7109 | rtl8169_rx_clear(tp); | |
065c27c1 | 7110 | |
7111 | rtl_pll_power_down(tp); | |
1da177e4 LT |
7112 | } |
7113 | ||
7114 | static int rtl8169_close(struct net_device *dev) | |
7115 | { | |
7116 | struct rtl8169_private *tp = netdev_priv(dev); | |
7117 | struct pci_dev *pdev = tp->pci_dev; | |
7118 | ||
e1759441 RW |
7119 | pm_runtime_get_sync(&pdev->dev); |
7120 | ||
cecb5fd7 | 7121 | /* Update counters before going down */ |
e71c9ce2 | 7122 | rtl8169_update_counters(tp); |
355423d0 | 7123 | |
da78dbff | 7124 | rtl_lock_work(tp); |
6c4a70c5 | 7125 | clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); |
da78dbff | 7126 | |
1da177e4 | 7127 | rtl8169_down(dev); |
da78dbff | 7128 | rtl_unlock_work(tp); |
1da177e4 | 7129 | |
4ea72445 L |
7130 | cancel_work_sync(&tp->wk.work); |
7131 | ||
ebcd5daa | 7132 | pci_free_irq(pdev, 0, tp); |
1da177e4 | 7133 | |
82553bb6 SG |
7134 | dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, |
7135 | tp->RxPhyAddr); | |
7136 | dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, | |
7137 | tp->TxPhyAddr); | |
1da177e4 LT |
7138 | tp->TxDescArray = NULL; |
7139 | tp->RxDescArray = NULL; | |
7140 | ||
e1759441 RW |
7141 | pm_runtime_put_sync(&pdev->dev); |
7142 | ||
1da177e4 LT |
7143 | return 0; |
7144 | } | |
7145 | ||
dc1c00ce FR |
7146 | #ifdef CONFIG_NET_POLL_CONTROLLER |
7147 | static void rtl8169_netpoll(struct net_device *dev) | |
7148 | { | |
7149 | struct rtl8169_private *tp = netdev_priv(dev); | |
7150 | ||
6d8b8349 | 7151 | rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp); |
dc1c00ce FR |
7152 | } |
7153 | #endif | |
7154 | ||
df43ac78 FR |
7155 | static int rtl_open(struct net_device *dev) |
7156 | { | |
7157 | struct rtl8169_private *tp = netdev_priv(dev); | |
df43ac78 FR |
7158 | struct pci_dev *pdev = tp->pci_dev; |
7159 | int retval = -ENOMEM; | |
7160 | ||
7161 | pm_runtime_get_sync(&pdev->dev); | |
7162 | ||
7163 | /* | |
e75d6606 | 7164 | * Rx and Tx descriptors needs 256 bytes alignment. |
df43ac78 FR |
7165 | * dma_alloc_coherent provides more. |
7166 | */ | |
7167 | tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES, | |
7168 | &tp->TxPhyAddr, GFP_KERNEL); | |
7169 | if (!tp->TxDescArray) | |
7170 | goto err_pm_runtime_put; | |
7171 | ||
7172 | tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES, | |
7173 | &tp->RxPhyAddr, GFP_KERNEL); | |
7174 | if (!tp->RxDescArray) | |
7175 | goto err_free_tx_0; | |
7176 | ||
b1127e64 | 7177 | retval = rtl8169_init_ring(tp); |
df43ac78 FR |
7178 | if (retval < 0) |
7179 | goto err_free_rx_1; | |
7180 | ||
7181 | INIT_WORK(&tp->wk.work, rtl_task); | |
7182 | ||
7183 | smp_mb(); | |
7184 | ||
7185 | rtl_request_firmware(tp); | |
7186 | ||
ebcd5daa | 7187 | retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp, |
6c6aa15f | 7188 | dev->name); |
df43ac78 FR |
7189 | if (retval < 0) |
7190 | goto err_release_fw_2; | |
7191 | ||
7192 | rtl_lock_work(tp); | |
7193 | ||
7194 | set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); | |
7195 | ||
7196 | napi_enable(&tp->napi); | |
7197 | ||
7198 | rtl8169_init_phy(dev, tp); | |
7199 | ||
df43ac78 FR |
7200 | rtl_pll_power_up(tp); |
7201 | ||
61cb532d | 7202 | rtl_hw_start(tp); |
df43ac78 | 7203 | |
e71c9ce2 | 7204 | if (!rtl8169_init_counter_offsets(tp)) |
6e85d5ad CV |
7205 | netif_warn(tp, hw, dev, "counter reset/update failed\n"); |
7206 | ||
df43ac78 FR |
7207 | netif_start_queue(dev); |
7208 | ||
7209 | rtl_unlock_work(tp); | |
7210 | ||
7211 | tp->saved_wolopts = 0; | |
a92a0849 | 7212 | pm_runtime_put_sync(&pdev->dev); |
df43ac78 | 7213 | |
1ef7286e | 7214 | rtl8169_check_link_status(dev, tp); |
df43ac78 FR |
7215 | out: |
7216 | return retval; | |
7217 | ||
7218 | err_release_fw_2: | |
7219 | rtl_release_firmware(tp); | |
7220 | rtl8169_rx_clear(tp); | |
7221 | err_free_rx_1: | |
7222 | dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, | |
7223 | tp->RxPhyAddr); | |
7224 | tp->RxDescArray = NULL; | |
7225 | err_free_tx_0: | |
7226 | dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, | |
7227 | tp->TxPhyAddr); | |
7228 | tp->TxDescArray = NULL; | |
7229 | err_pm_runtime_put: | |
7230 | pm_runtime_put_noidle(&pdev->dev); | |
7231 | goto out; | |
7232 | } | |
7233 | ||
bc1f4470 | 7234 | static void |
8027aa24 | 7235 | rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) |
1da177e4 LT |
7236 | { |
7237 | struct rtl8169_private *tp = netdev_priv(dev); | |
f09cf4b7 | 7238 | struct pci_dev *pdev = tp->pci_dev; |
42020320 | 7239 | struct rtl8169_counters *counters = tp->counters; |
8027aa24 | 7240 | unsigned int start; |
1da177e4 | 7241 | |
f09cf4b7 CHL |
7242 | pm_runtime_get_noresume(&pdev->dev); |
7243 | ||
7244 | if (netif_running(dev) && pm_runtime_active(&pdev->dev)) | |
1ef7286e | 7245 | rtl8169_rx_missed(dev); |
5b0384f4 | 7246 | |
8027aa24 | 7247 | do { |
57a7744e | 7248 | start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp); |
8027aa24 JW |
7249 | stats->rx_packets = tp->rx_stats.packets; |
7250 | stats->rx_bytes = tp->rx_stats.bytes; | |
57a7744e | 7251 | } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start)); |
8027aa24 | 7252 | |
8027aa24 | 7253 | do { |
57a7744e | 7254 | start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp); |
8027aa24 JW |
7255 | stats->tx_packets = tp->tx_stats.packets; |
7256 | stats->tx_bytes = tp->tx_stats.bytes; | |
57a7744e | 7257 | } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start)); |
8027aa24 JW |
7258 | |
7259 | stats->rx_dropped = dev->stats.rx_dropped; | |
7260 | stats->tx_dropped = dev->stats.tx_dropped; | |
7261 | stats->rx_length_errors = dev->stats.rx_length_errors; | |
7262 | stats->rx_errors = dev->stats.rx_errors; | |
7263 | stats->rx_crc_errors = dev->stats.rx_crc_errors; | |
7264 | stats->rx_fifo_errors = dev->stats.rx_fifo_errors; | |
7265 | stats->rx_missed_errors = dev->stats.rx_missed_errors; | |
d7d2d89d | 7266 | stats->multicast = dev->stats.multicast; |
8027aa24 | 7267 | |
6e85d5ad CV |
7268 | /* |
7269 | * Fetch additonal counter values missing in stats collected by driver | |
7270 | * from tally counters. | |
7271 | */ | |
f09cf4b7 | 7272 | if (pm_runtime_active(&pdev->dev)) |
e71c9ce2 | 7273 | rtl8169_update_counters(tp); |
6e85d5ad CV |
7274 | |
7275 | /* | |
7276 | * Subtract values fetched during initalization. | |
7277 | * See rtl8169_init_counter_offsets for a description why we do that. | |
7278 | */ | |
42020320 | 7279 | stats->tx_errors = le64_to_cpu(counters->tx_errors) - |
6e85d5ad | 7280 | le64_to_cpu(tp->tc_offset.tx_errors); |
42020320 | 7281 | stats->collisions = le32_to_cpu(counters->tx_multi_collision) - |
6e85d5ad | 7282 | le32_to_cpu(tp->tc_offset.tx_multi_collision); |
42020320 | 7283 | stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) - |
6e85d5ad CV |
7284 | le16_to_cpu(tp->tc_offset.tx_aborted); |
7285 | ||
f09cf4b7 | 7286 | pm_runtime_put_noidle(&pdev->dev); |
1da177e4 LT |
7287 | } |
7288 | ||
861ab440 | 7289 | static void rtl8169_net_suspend(struct net_device *dev) |
5d06a99f | 7290 | { |
065c27c1 | 7291 | struct rtl8169_private *tp = netdev_priv(dev); |
7292 | ||
5d06a99f | 7293 | if (!netif_running(dev)) |
861ab440 | 7294 | return; |
5d06a99f FR |
7295 | |
7296 | netif_device_detach(dev); | |
7297 | netif_stop_queue(dev); | |
da78dbff FR |
7298 | |
7299 | rtl_lock_work(tp); | |
7300 | napi_disable(&tp->napi); | |
6c4a70c5 | 7301 | clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); |
da78dbff FR |
7302 | rtl_unlock_work(tp); |
7303 | ||
7304 | rtl_pll_power_down(tp); | |
861ab440 RW |
7305 | } |
7306 | ||
7307 | #ifdef CONFIG_PM | |
7308 | ||
7309 | static int rtl8169_suspend(struct device *device) | |
7310 | { | |
7311 | struct pci_dev *pdev = to_pci_dev(device); | |
7312 | struct net_device *dev = pci_get_drvdata(pdev); | |
5d06a99f | 7313 | |
861ab440 | 7314 | rtl8169_net_suspend(dev); |
1371fa6d | 7315 | |
5d06a99f FR |
7316 | return 0; |
7317 | } | |
7318 | ||
e1759441 RW |
7319 | static void __rtl8169_resume(struct net_device *dev) |
7320 | { | |
065c27c1 | 7321 | struct rtl8169_private *tp = netdev_priv(dev); |
7322 | ||
e1759441 | 7323 | netif_device_attach(dev); |
065c27c1 | 7324 | |
7325 | rtl_pll_power_up(tp); | |
7326 | ||
cff4c162 AS |
7327 | rtl_lock_work(tp); |
7328 | napi_enable(&tp->napi); | |
6c4a70c5 | 7329 | set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); |
cff4c162 | 7330 | rtl_unlock_work(tp); |
da78dbff | 7331 | |
98ddf986 | 7332 | rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); |
e1759441 RW |
7333 | } |
7334 | ||
861ab440 | 7335 | static int rtl8169_resume(struct device *device) |
5d06a99f | 7336 | { |
861ab440 | 7337 | struct pci_dev *pdev = to_pci_dev(device); |
5d06a99f | 7338 | struct net_device *dev = pci_get_drvdata(pdev); |
fccec10b SG |
7339 | struct rtl8169_private *tp = netdev_priv(dev); |
7340 | ||
7341 | rtl8169_init_phy(dev, tp); | |
5d06a99f | 7342 | |
e1759441 RW |
7343 | if (netif_running(dev)) |
7344 | __rtl8169_resume(dev); | |
5d06a99f | 7345 | |
e1759441 RW |
7346 | return 0; |
7347 | } | |
7348 | ||
7349 | static int rtl8169_runtime_suspend(struct device *device) | |
7350 | { | |
7351 | struct pci_dev *pdev = to_pci_dev(device); | |
7352 | struct net_device *dev = pci_get_drvdata(pdev); | |
7353 | struct rtl8169_private *tp = netdev_priv(dev); | |
7354 | ||
a92a0849 HK |
7355 | if (!tp->TxDescArray) { |
7356 | rtl_pll_power_down(tp); | |
e1759441 | 7357 | return 0; |
a92a0849 | 7358 | } |
e1759441 | 7359 | |
da78dbff | 7360 | rtl_lock_work(tp); |
e1759441 RW |
7361 | tp->saved_wolopts = __rtl8169_get_wol(tp); |
7362 | __rtl8169_set_wol(tp, WAKE_ANY); | |
da78dbff | 7363 | rtl_unlock_work(tp); |
e1759441 RW |
7364 | |
7365 | rtl8169_net_suspend(dev); | |
7366 | ||
f09cf4b7 | 7367 | /* Update counters before going runtime suspend */ |
1ef7286e | 7368 | rtl8169_rx_missed(dev); |
e71c9ce2 | 7369 | rtl8169_update_counters(tp); |
f09cf4b7 | 7370 | |
e1759441 RW |
7371 | return 0; |
7372 | } | |
7373 | ||
7374 | static int rtl8169_runtime_resume(struct device *device) | |
7375 | { | |
7376 | struct pci_dev *pdev = to_pci_dev(device); | |
7377 | struct net_device *dev = pci_get_drvdata(pdev); | |
7378 | struct rtl8169_private *tp = netdev_priv(dev); | |
f51d4a10 | 7379 | rtl_rar_set(tp, dev->dev_addr); |
e1759441 RW |
7380 | |
7381 | if (!tp->TxDescArray) | |
7382 | return 0; | |
7383 | ||
da78dbff | 7384 | rtl_lock_work(tp); |
e1759441 RW |
7385 | __rtl8169_set_wol(tp, tp->saved_wolopts); |
7386 | tp->saved_wolopts = 0; | |
da78dbff | 7387 | rtl_unlock_work(tp); |
e1759441 | 7388 | |
fccec10b SG |
7389 | rtl8169_init_phy(dev, tp); |
7390 | ||
e1759441 | 7391 | __rtl8169_resume(dev); |
5d06a99f | 7392 | |
5d06a99f FR |
7393 | return 0; |
7394 | } | |
7395 | ||
e1759441 RW |
7396 | static int rtl8169_runtime_idle(struct device *device) |
7397 | { | |
7398 | struct pci_dev *pdev = to_pci_dev(device); | |
7399 | struct net_device *dev = pci_get_drvdata(pdev); | |
e1759441 | 7400 | |
a92a0849 HK |
7401 | if (!netif_running(dev) || !netif_carrier_ok(dev)) |
7402 | pm_schedule_suspend(device, 10000); | |
7403 | ||
7404 | return -EBUSY; | |
e1759441 RW |
7405 | } |
7406 | ||
47145210 | 7407 | static const struct dev_pm_ops rtl8169_pm_ops = { |
cecb5fd7 FR |
7408 | .suspend = rtl8169_suspend, |
7409 | .resume = rtl8169_resume, | |
7410 | .freeze = rtl8169_suspend, | |
7411 | .thaw = rtl8169_resume, | |
7412 | .poweroff = rtl8169_suspend, | |
7413 | .restore = rtl8169_resume, | |
7414 | .runtime_suspend = rtl8169_runtime_suspend, | |
7415 | .runtime_resume = rtl8169_runtime_resume, | |
7416 | .runtime_idle = rtl8169_runtime_idle, | |
861ab440 RW |
7417 | }; |
7418 | ||
7419 | #define RTL8169_PM_OPS (&rtl8169_pm_ops) | |
7420 | ||
7421 | #else /* !CONFIG_PM */ | |
7422 | ||
7423 | #define RTL8169_PM_OPS NULL | |
7424 | ||
7425 | #endif /* !CONFIG_PM */ | |
7426 | ||
649b3b8c | 7427 | static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp) |
7428 | { | |
649b3b8c | 7429 | /* WoL fails with 8168b when the receiver is disabled. */ |
7430 | switch (tp->mac_version) { | |
7431 | case RTL_GIGA_MAC_VER_11: | |
7432 | case RTL_GIGA_MAC_VER_12: | |
7433 | case RTL_GIGA_MAC_VER_17: | |
7434 | pci_clear_master(tp->pci_dev); | |
7435 | ||
1ef7286e | 7436 | RTL_W8(tp, ChipCmd, CmdRxEnb); |
649b3b8c | 7437 | /* PCI commit */ |
1ef7286e | 7438 | RTL_R8(tp, ChipCmd); |
649b3b8c | 7439 | break; |
7440 | default: | |
7441 | break; | |
7442 | } | |
7443 | } | |
7444 | ||
1765f95d FR |
7445 | static void rtl_shutdown(struct pci_dev *pdev) |
7446 | { | |
861ab440 | 7447 | struct net_device *dev = pci_get_drvdata(pdev); |
4bb3f522 | 7448 | struct rtl8169_private *tp = netdev_priv(dev); |
861ab440 RW |
7449 | |
7450 | rtl8169_net_suspend(dev); | |
1765f95d | 7451 | |
cecb5fd7 | 7452 | /* Restore original MAC address */ |
cc098dc7 IV |
7453 | rtl_rar_set(tp, dev->perm_addr); |
7454 | ||
92fc43b4 | 7455 | rtl8169_hw_reset(tp); |
4bb3f522 | 7456 | |
861ab440 | 7457 | if (system_state == SYSTEM_POWER_OFF) { |
649b3b8c | 7458 | if (__rtl8169_get_wol(tp) & WAKE_ANY) { |
7459 | rtl_wol_suspend_quirk(tp); | |
7460 | rtl_wol_shutdown_quirk(tp); | |
ca52efd5 | 7461 | } |
7462 | ||
861ab440 RW |
7463 | pci_wake_from_d3(pdev, true); |
7464 | pci_set_power_state(pdev, PCI_D3hot); | |
7465 | } | |
7466 | } | |
5d06a99f | 7467 | |
baf63293 | 7468 | static void rtl_remove_one(struct pci_dev *pdev) |
e27566ed FR |
7469 | { |
7470 | struct net_device *dev = pci_get_drvdata(pdev); | |
7471 | struct rtl8169_private *tp = netdev_priv(dev); | |
7472 | ||
9dbe7896 | 7473 | if (r8168_check_dash(tp)) |
e27566ed | 7474 | rtl8168_driver_stop(tp); |
e27566ed | 7475 | |
ad1be8d3 DN |
7476 | netif_napi_del(&tp->napi); |
7477 | ||
e27566ed FR |
7478 | unregister_netdev(dev); |
7479 | ||
7480 | rtl_release_firmware(tp); | |
7481 | ||
7482 | if (pci_dev_run_wake(pdev)) | |
7483 | pm_runtime_get_noresume(&pdev->dev); | |
7484 | ||
7485 | /* restore original MAC address */ | |
7486 | rtl_rar_set(tp, dev->perm_addr); | |
e27566ed FR |
7487 | } |
7488 | ||
fa9c385e | 7489 | static const struct net_device_ops rtl_netdev_ops = { |
df43ac78 | 7490 | .ndo_open = rtl_open, |
fa9c385e FR |
7491 | .ndo_stop = rtl8169_close, |
7492 | .ndo_get_stats64 = rtl8169_get_stats64, | |
7493 | .ndo_start_xmit = rtl8169_start_xmit, | |
7494 | .ndo_tx_timeout = rtl8169_tx_timeout, | |
7495 | .ndo_validate_addr = eth_validate_addr, | |
7496 | .ndo_change_mtu = rtl8169_change_mtu, | |
7497 | .ndo_fix_features = rtl8169_fix_features, | |
7498 | .ndo_set_features = rtl8169_set_features, | |
7499 | .ndo_set_mac_address = rtl_set_mac_address, | |
7500 | .ndo_do_ioctl = rtl8169_ioctl, | |
7501 | .ndo_set_rx_mode = rtl_set_rx_mode, | |
7502 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
7503 | .ndo_poll_controller = rtl8169_netpoll, | |
7504 | #endif | |
7505 | ||
7506 | }; | |
7507 | ||
31fa8b18 | 7508 | static const struct rtl_cfg_info { |
61cb532d | 7509 | void (*hw_start)(struct rtl8169_private *tp); |
31fa8b18 | 7510 | u16 event_slow; |
14967f94 | 7511 | unsigned int has_gmii:1; |
50970831 | 7512 | const struct rtl_coalesce_info *coalesce_info; |
31fa8b18 FR |
7513 | u8 default_ver; |
7514 | } rtl_cfg_infos [] = { | |
7515 | [RTL_CFG_0] = { | |
7516 | .hw_start = rtl_hw_start_8169, | |
31fa8b18 | 7517 | .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver, |
14967f94 | 7518 | .has_gmii = 1, |
50970831 | 7519 | .coalesce_info = rtl_coalesce_info_8169, |
31fa8b18 FR |
7520 | .default_ver = RTL_GIGA_MAC_VER_01, |
7521 | }, | |
7522 | [RTL_CFG_1] = { | |
7523 | .hw_start = rtl_hw_start_8168, | |
31fa8b18 | 7524 | .event_slow = SYSErr | LinkChg | RxOverflow, |
14967f94 | 7525 | .has_gmii = 1, |
50970831 | 7526 | .coalesce_info = rtl_coalesce_info_8168_8136, |
31fa8b18 FR |
7527 | .default_ver = RTL_GIGA_MAC_VER_11, |
7528 | }, | |
7529 | [RTL_CFG_2] = { | |
7530 | .hw_start = rtl_hw_start_8101, | |
31fa8b18 FR |
7531 | .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver | |
7532 | PCSTimeout, | |
50970831 | 7533 | .coalesce_info = rtl_coalesce_info_8168_8136, |
31fa8b18 FR |
7534 | .default_ver = RTL_GIGA_MAC_VER_13, |
7535 | } | |
7536 | }; | |
7537 | ||
6c6aa15f | 7538 | static int rtl_alloc_irq(struct rtl8169_private *tp) |
31fa8b18 | 7539 | { |
6c6aa15f | 7540 | unsigned int flags; |
31fa8b18 | 7541 | |
6c6aa15f | 7542 | if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { |
1ef7286e AS |
7543 | RTL_W8(tp, Cfg9346, Cfg9346_Unlock); |
7544 | RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable); | |
7545 | RTL_W8(tp, Cfg9346, Cfg9346_Lock); | |
6c6aa15f HK |
7546 | flags = PCI_IRQ_LEGACY; |
7547 | } else { | |
7548 | flags = PCI_IRQ_ALL_TYPES; | |
31fa8b18 | 7549 | } |
6c6aa15f HK |
7550 | |
7551 | return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags); | |
31fa8b18 FR |
7552 | } |
7553 | ||
c558386b HW |
7554 | DECLARE_RTL_COND(rtl_link_list_ready_cond) |
7555 | { | |
1ef7286e | 7556 | return RTL_R8(tp, MCU) & LINK_LIST_RDY; |
c558386b HW |
7557 | } |
7558 | ||
7559 | DECLARE_RTL_COND(rtl_rxtx_empty_cond) | |
7560 | { | |
1ef7286e | 7561 | return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY; |
c558386b HW |
7562 | } |
7563 | ||
baf63293 | 7564 | static void rtl_hw_init_8168g(struct rtl8169_private *tp) |
c558386b | 7565 | { |
c558386b HW |
7566 | u32 data; |
7567 | ||
7568 | tp->ocp_base = OCP_STD_PHY_BASE; | |
7569 | ||
1ef7286e | 7570 | RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN); |
c558386b HW |
7571 | |
7572 | if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42)) | |
7573 | return; | |
7574 | ||
7575 | if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42)) | |
7576 | return; | |
7577 | ||
1ef7286e | 7578 | RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); |
c558386b | 7579 | msleep(1); |
1ef7286e | 7580 | RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); |
c558386b | 7581 | |
5f8bcce9 | 7582 | data = r8168_mac_ocp_read(tp, 0xe8de); |
c558386b HW |
7583 | data &= ~(1 << 14); |
7584 | r8168_mac_ocp_write(tp, 0xe8de, data); | |
7585 | ||
7586 | if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42)) | |
7587 | return; | |
7588 | ||
5f8bcce9 | 7589 | data = r8168_mac_ocp_read(tp, 0xe8de); |
c558386b HW |
7590 | data |= (1 << 15); |
7591 | r8168_mac_ocp_write(tp, 0xe8de, data); | |
7592 | ||
7593 | if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42)) | |
7594 | return; | |
7595 | } | |
7596 | ||
003609da CHL |
7597 | static void rtl_hw_init_8168ep(struct rtl8169_private *tp) |
7598 | { | |
7599 | rtl8168ep_stop_cmac(tp); | |
7600 | rtl_hw_init_8168g(tp); | |
7601 | } | |
7602 | ||
baf63293 | 7603 | static void rtl_hw_initialize(struct rtl8169_private *tp) |
c558386b HW |
7604 | { |
7605 | switch (tp->mac_version) { | |
2a71883c | 7606 | case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48: |
003609da CHL |
7607 | rtl_hw_init_8168g(tp); |
7608 | break; | |
2a71883c | 7609 | case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_51: |
003609da | 7610 | rtl_hw_init_8168ep(tp); |
c558386b | 7611 | break; |
c558386b HW |
7612 | default: |
7613 | break; | |
7614 | } | |
7615 | } | |
7616 | ||
929a031d | 7617 | static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
3b6cf25d FR |
7618 | { |
7619 | const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data; | |
3b6cf25d FR |
7620 | struct rtl8169_private *tp; |
7621 | struct mii_if_info *mii; | |
7622 | struct net_device *dev; | |
c8d48d9c | 7623 | int chipset, region, i; |
3b6cf25d FR |
7624 | int rc; |
7625 | ||
7626 | if (netif_msg_drv(&debug)) { | |
7627 | printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n", | |
7628 | MODULENAME, RTL8169_VERSION); | |
7629 | } | |
7630 | ||
4c45d24a HK |
7631 | dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp)); |
7632 | if (!dev) | |
7633 | return -ENOMEM; | |
3b6cf25d FR |
7634 | |
7635 | SET_NETDEV_DEV(dev, &pdev->dev); | |
fa9c385e | 7636 | dev->netdev_ops = &rtl_netdev_ops; |
3b6cf25d FR |
7637 | tp = netdev_priv(dev); |
7638 | tp->dev = dev; | |
7639 | tp->pci_dev = pdev; | |
7640 | tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT); | |
7641 | ||
7642 | mii = &tp->mii; | |
7643 | mii->dev = dev; | |
7644 | mii->mdio_read = rtl_mdio_read; | |
7645 | mii->mdio_write = rtl_mdio_write; | |
7646 | mii->phy_id_mask = 0x1f; | |
7647 | mii->reg_num_mask = 0x1f; | |
14967f94 | 7648 | mii->supports_gmii = cfg->has_gmii; |
3b6cf25d FR |
7649 | |
7650 | /* disable ASPM completely as that cause random device stop working | |
7651 | * problems as well as full system hangs for some PCIe devices users */ | |
7652 | pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 | | |
7653 | PCIE_LINK_STATE_CLKPM); | |
7654 | ||
7655 | /* enable device (incl. PCI PM wakeup and hotplug setup) */ | |
4c45d24a | 7656 | rc = pcim_enable_device(pdev); |
3b6cf25d | 7657 | if (rc < 0) { |
22148df0 | 7658 | dev_err(&pdev->dev, "enable failure\n"); |
4c45d24a | 7659 | return rc; |
3b6cf25d FR |
7660 | } |
7661 | ||
4c45d24a | 7662 | if (pcim_set_mwi(pdev) < 0) |
22148df0 | 7663 | dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n"); |
3b6cf25d | 7664 | |
c8d48d9c HK |
7665 | /* use first MMIO region */ |
7666 | region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1; | |
7667 | if (region < 0) { | |
22148df0 | 7668 | dev_err(&pdev->dev, "no MMIO resource found\n"); |
4c45d24a | 7669 | return -ENODEV; |
3b6cf25d FR |
7670 | } |
7671 | ||
7672 | /* check for weird/broken PCI region reporting */ | |
7673 | if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) { | |
22148df0 | 7674 | dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n"); |
4c45d24a | 7675 | return -ENODEV; |
3b6cf25d FR |
7676 | } |
7677 | ||
93a00d4d | 7678 | rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME); |
3b6cf25d | 7679 | if (rc < 0) { |
22148df0 | 7680 | dev_err(&pdev->dev, "cannot remap MMIO, aborting\n"); |
4c45d24a | 7681 | return rc; |
3b6cf25d FR |
7682 | } |
7683 | ||
93a00d4d | 7684 | tp->mmio_addr = pcim_iomap_table(pdev)[region]; |
3b6cf25d FR |
7685 | |
7686 | if (!pci_is_pcie(pdev)) | |
22148df0 | 7687 | dev_info(&pdev->dev, "not PCI Express\n"); |
3b6cf25d FR |
7688 | |
7689 | /* Identify chip attached to board */ | |
22148df0 | 7690 | rtl8169_get_mac_version(tp, cfg->default_ver); |
3b6cf25d | 7691 | |
0ae0974e | 7692 | tp->cp_cmd = RTL_R16(tp, CPlusCmd); |
27896c83 AB |
7693 | |
7694 | if ((sizeof(dma_addr_t) > 4) && | |
7695 | (use_dac == 1 || (use_dac == -1 && pci_is_pcie(pdev) && | |
7696 | tp->mac_version >= RTL_GIGA_MAC_VER_18)) && | |
f0076436 AB |
7697 | !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && |
7698 | !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) { | |
27896c83 AB |
7699 | |
7700 | /* CPlusCmd Dual Access Cycle is only needed for non-PCIe */ | |
7701 | if (!pci_is_pcie(pdev)) | |
7702 | tp->cp_cmd |= PCIDAC; | |
7703 | dev->features |= NETIF_F_HIGHDMA; | |
7704 | } else { | |
7705 | rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); | |
7706 | if (rc < 0) { | |
22148df0 | 7707 | dev_err(&pdev->dev, "DMA configuration failed\n"); |
4c45d24a | 7708 | return rc; |
27896c83 AB |
7709 | } |
7710 | } | |
7711 | ||
3b6cf25d FR |
7712 | rtl_init_rxcfg(tp); |
7713 | ||
7714 | rtl_irq_disable(tp); | |
7715 | ||
c558386b HW |
7716 | rtl_hw_initialize(tp); |
7717 | ||
3b6cf25d FR |
7718 | rtl_hw_reset(tp); |
7719 | ||
7720 | rtl_ack_events(tp, 0xffff); | |
7721 | ||
7722 | pci_set_master(pdev); | |
7723 | ||
3b6cf25d | 7724 | rtl_init_mdio_ops(tp); |
3b6cf25d FR |
7725 | rtl_init_jumbo_ops(tp); |
7726 | ||
7727 | rtl8169_print_mac_version(tp); | |
7728 | ||
7729 | chipset = tp->mac_version; | |
3b6cf25d | 7730 | |
6c6aa15f HK |
7731 | rc = rtl_alloc_irq(tp); |
7732 | if (rc < 0) { | |
22148df0 | 7733 | dev_err(&pdev->dev, "Can't allocate interrupt\n"); |
6c6aa15f HK |
7734 | return rc; |
7735 | } | |
3b6cf25d | 7736 | |
18041b52 | 7737 | tp->saved_wolopts = __rtl8169_get_wol(tp); |
7edf6d31 | 7738 | |
3b6cf25d FR |
7739 | if (rtl_tbi_enabled(tp)) { |
7740 | tp->set_speed = rtl8169_set_speed_tbi; | |
6fa1ba61 | 7741 | tp->get_link_ksettings = rtl8169_get_link_ksettings_tbi; |
3b6cf25d FR |
7742 | tp->phy_reset_enable = rtl8169_tbi_reset_enable; |
7743 | tp->phy_reset_pending = rtl8169_tbi_reset_pending; | |
7744 | tp->link_ok = rtl8169_tbi_link_ok; | |
7745 | tp->do_ioctl = rtl_tbi_ioctl; | |
7746 | } else { | |
7747 | tp->set_speed = rtl8169_set_speed_xmii; | |
6fa1ba61 | 7748 | tp->get_link_ksettings = rtl8169_get_link_ksettings_xmii; |
3b6cf25d FR |
7749 | tp->phy_reset_enable = rtl8169_xmii_reset_enable; |
7750 | tp->phy_reset_pending = rtl8169_xmii_reset_pending; | |
7751 | tp->link_ok = rtl8169_xmii_link_ok; | |
7752 | tp->do_ioctl = rtl_xmii_ioctl; | |
7753 | } | |
7754 | ||
7755 | mutex_init(&tp->wk.mutex); | |
340fea3d KM |
7756 | u64_stats_init(&tp->rx_stats.syncp); |
7757 | u64_stats_init(&tp->tx_stats.syncp); | |
3b6cf25d FR |
7758 | |
7759 | /* Get MAC address */ | |
b2d43e6e | 7760 | switch (tp->mac_version) { |
353af85e | 7761 | u8 mac_addr[ETH_ALEN] __aligned(4); |
b2d43e6e HK |
7762 | case RTL_GIGA_MAC_VER_35 ... RTL_GIGA_MAC_VER_38: |
7763 | case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51: | |
05b9687b | 7764 | *(u32 *)&mac_addr[0] = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC); |
353af85e | 7765 | *(u16 *)&mac_addr[4] = rtl_eri_read(tp, 0xe4, ERIAR_EXGMAC); |
6e1d0b89 | 7766 | |
353af85e HK |
7767 | if (is_valid_ether_addr(mac_addr)) |
7768 | rtl_rar_set(tp, mac_addr); | |
b2d43e6e HK |
7769 | break; |
7770 | default: | |
7771 | break; | |
6e1d0b89 | 7772 | } |
3b6cf25d | 7773 | for (i = 0; i < ETH_ALEN; i++) |
1ef7286e | 7774 | dev->dev_addr[i] = RTL_R8(tp, MAC0 + i); |
3b6cf25d | 7775 | |
7ad24ea4 | 7776 | dev->ethtool_ops = &rtl8169_ethtool_ops; |
3b6cf25d | 7777 | dev->watchdog_timeo = RTL8169_TX_TIMEOUT; |
3b6cf25d | 7778 | |
37621493 | 7779 | netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT); |
3b6cf25d FR |
7780 | |
7781 | /* don't enable SG, IP_CSUM and TSO by default - it might not work | |
7782 | * properly for all devices */ | |
7783 | dev->features |= NETIF_F_RXCSUM | | |
f646968f | 7784 | NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; |
3b6cf25d FR |
7785 | |
7786 | dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | | |
f646968f PM |
7787 | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX | |
7788 | NETIF_F_HW_VLAN_CTAG_RX; | |
3b6cf25d FR |
7789 | dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | |
7790 | NETIF_F_HIGHDMA; | |
2d0ec544 | 7791 | dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; |
3b6cf25d | 7792 | |
929a031d | 7793 | tp->cp_cmd |= RxChkSum | RxVlan; |
7794 | ||
7795 | /* | |
7796 | * Pretend we are using VLANs; This bypasses a nasty bug where | |
7797 | * Interrupts stop flowing on high load on 8110SCd controllers. | |
7798 | */ | |
3b6cf25d | 7799 | if (tp->mac_version == RTL_GIGA_MAC_VER_05) |
929a031d | 7800 | /* Disallow toggling */ |
f646968f | 7801 | dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX; |
3b6cf25d | 7802 | |
a4328ddb HK |
7803 | switch (rtl_chip_infos[chipset].txd_version) { |
7804 | case RTL_TD_0: | |
5888d3fc | 7805 | tp->tso_csum = rtl8169_tso_csum_v1; |
a4328ddb HK |
7806 | break; |
7807 | case RTL_TD_1: | |
5888d3fc | 7808 | tp->tso_csum = rtl8169_tso_csum_v2; |
e974604b | 7809 | dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6; |
a4328ddb HK |
7810 | break; |
7811 | default: | |
5888d3fc | 7812 | WARN_ON_ONCE(1); |
a4328ddb | 7813 | } |
5888d3fc | 7814 | |
3b6cf25d FR |
7815 | dev->hw_features |= NETIF_F_RXALL; |
7816 | dev->hw_features |= NETIF_F_RXFCS; | |
7817 | ||
c7315a95 JW |
7818 | /* MTU range: 60 - hw-specific max */ |
7819 | dev->min_mtu = ETH_ZLEN; | |
7820 | dev->max_mtu = rtl_chip_infos[chipset].jumbo_max; | |
7821 | ||
3b6cf25d FR |
7822 | tp->hw_start = cfg->hw_start; |
7823 | tp->event_slow = cfg->event_slow; | |
50970831 | 7824 | tp->coalesce_info = cfg->coalesce_info; |
3b6cf25d | 7825 | |
9de36ccf | 7826 | timer_setup(&tp->timer, rtl8169_phy_timer, 0); |
3b6cf25d FR |
7827 | |
7828 | tp->rtl_fw = RTL_FIRMWARE_UNKNOWN; | |
7829 | ||
4c45d24a HK |
7830 | tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters), |
7831 | &tp->counters_phys_addr, | |
7832 | GFP_KERNEL); | |
4cf964af HK |
7833 | if (!tp->counters) |
7834 | return -ENOMEM; | |
42020320 | 7835 | |
19c9ea36 HK |
7836 | pci_set_drvdata(pdev, dev); |
7837 | ||
3b6cf25d FR |
7838 | rc = register_netdev(dev); |
7839 | if (rc < 0) | |
4cf964af | 7840 | return rc; |
3b6cf25d | 7841 | |
2d6c5a61 HK |
7842 | netif_info(tp, probe, dev, "%s, %pM, XID %08x, IRQ %d\n", |
7843 | rtl_chip_infos[chipset].name, dev->dev_addr, | |
90b989c5 | 7844 | (u32)(RTL_R32(tp, TxConfig) & 0xfcf0f8ff), |
29274991 | 7845 | pci_irq_vector(pdev, 0)); |
3b6cf25d FR |
7846 | if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) { |
7847 | netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, " | |
7848 | "tx checksumming: %s]\n", | |
7849 | rtl_chip_infos[chipset].jumbo_max, | |
6ed0e08f | 7850 | tp->mac_version <= RTL_GIGA_MAC_VER_06 ? "ok" : "ko"); |
3b6cf25d FR |
7851 | } |
7852 | ||
9dbe7896 | 7853 | if (r8168_check_dash(tp)) |
3b6cf25d | 7854 | rtl8168_driver_start(tp); |
3b6cf25d | 7855 | |
3b6cf25d FR |
7856 | netif_carrier_off(dev); |
7857 | ||
a92a0849 HK |
7858 | if (pci_dev_run_wake(pdev)) |
7859 | pm_runtime_put_sync(&pdev->dev); | |
7860 | ||
4c45d24a | 7861 | return 0; |
3b6cf25d FR |
7862 | } |
7863 | ||
1da177e4 LT |
7864 | static struct pci_driver rtl8169_pci_driver = { |
7865 | .name = MODULENAME, | |
7866 | .id_table = rtl8169_pci_tbl, | |
3b6cf25d | 7867 | .probe = rtl_init_one, |
baf63293 | 7868 | .remove = rtl_remove_one, |
1765f95d | 7869 | .shutdown = rtl_shutdown, |
861ab440 | 7870 | .driver.pm = RTL8169_PM_OPS, |
1da177e4 LT |
7871 | }; |
7872 | ||
3eeb7da9 | 7873 | module_pci_driver(rtl8169_pci_driver); |