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Merge tag 'batman-adv-for-davem' of git://git.open-mesh.org/linux-merge
[mirror_ubuntu-focal-kernel.git] / drivers / net / ethernet / realtek / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
a6b7a407 25#include <linux/interrupt.h>
1da177e4 26#include <linux/dma-mapping.h>
e1759441 27#include <linux/pm_runtime.h>
bca03d5f 28#include <linux/firmware.h>
ba04c7c9 29#include <linux/pci-aspm.h>
70c71606 30#include <linux/prefetch.h>
1da177e4
LT		 31
32#include <asm/io.h>
33#include <asm/irq.h>
34
865c652d 35#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 36#define MODULENAME "r8169"
37#define PFX MODULENAME ": "
38
bca03d5f 39#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
40#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
01dc7fec 41#define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
42#define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
70090424 43#define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
c2218925
HW		 44#define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
45#define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
5a5e4443 46#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
7e18dca1 47#define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
b3d7b2f2 48#define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
5598bfe5 49#define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
c558386b 50#define FIRMWARE_8168G_1 "rtl_nic/rtl8168g-1.fw"
bca03d5f 51
1da177e4
LT		 52#ifdef RTL8169_DEBUG
53#define assert(expr) \
5b0384f4
FR		 54 if (!(expr)) { \
55 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
b39d66a8 56 #expr,__FILE__,__func__,__LINE__); \
5b0384f4 57 }
06fa7358
JP		 58#define dprintk(fmt, args...) \
59 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 60#else
61#define assert(expr) do {} while (0)
62#define dprintk(fmt, args...) do {} while (0)
63#endif /* RTL8169_DEBUG */
64
b57b7e5a 65#define R8169_MSG_DEFAULT \
f0e837d9 66 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 67
477206a0
JD		 68#define TX_SLOTS_AVAIL(tp) \
69 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
70
71/* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
72#define TX_FRAGS_READY_FOR(tp,nr_frags) \
73 (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
1da177e4 74
1da177e4
LT		 75/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
76 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 77static const int multicast_filter_limit = 32;
1da177e4 78
9c14ceaf 79#define MAX_READ_REQUEST_SHIFT 12
aee77e4a 80#define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
1da177e4
LT		 81#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
82#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
83
84#define R8169_REGS_SIZE 256
85#define R8169_NAPI_WEIGHT 64
86#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
87#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
88#define RX_BUF_SIZE 1536 /* Rx Buffer size */
89#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
90#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
91
92#define RTL8169_TX_TIMEOUT (6*HZ)
93#define RTL8169_PHY_TIMEOUT (10*HZ)
94
ea8dbdd1 95#define RTL_EEPROM_SIG cpu_to_le32(0x8129)
96#define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
e1564ec9
FR		 97#define RTL_EEPROM_SIG_ADDR 0x0000
98
1da177e4
LT		 99/* write/read MMIO register */
100#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
101#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
102#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
103#define RTL_R8(reg) readb (ioaddr + (reg))
104#define RTL_R16(reg) readw (ioaddr + (reg))
06f555f3 105#define RTL_R32(reg) readl (ioaddr + (reg))
1da177e4
LT		 106
107enum mac_version {
85bffe6c
FR		 108 RTL_GIGA_MAC_VER_01 = 0,
109 RTL_GIGA_MAC_VER_02,
110 RTL_GIGA_MAC_VER_03,
111 RTL_GIGA_MAC_VER_04,
112 RTL_GIGA_MAC_VER_05,
113 RTL_GIGA_MAC_VER_06,
114 RTL_GIGA_MAC_VER_07,
115 RTL_GIGA_MAC_VER_08,
116 RTL_GIGA_MAC_VER_09,
117 RTL_GIGA_MAC_VER_10,
118 RTL_GIGA_MAC_VER_11,
119 RTL_GIGA_MAC_VER_12,
120 RTL_GIGA_MAC_VER_13,
121 RTL_GIGA_MAC_VER_14,
122 RTL_GIGA_MAC_VER_15,
123 RTL_GIGA_MAC_VER_16,
124 RTL_GIGA_MAC_VER_17,
125 RTL_GIGA_MAC_VER_18,
126 RTL_GIGA_MAC_VER_19,
127 RTL_GIGA_MAC_VER_20,
128 RTL_GIGA_MAC_VER_21,
129 RTL_GIGA_MAC_VER_22,
130 RTL_GIGA_MAC_VER_23,
131 RTL_GIGA_MAC_VER_24,
132 RTL_GIGA_MAC_VER_25,
133 RTL_GIGA_MAC_VER_26,
134 RTL_GIGA_MAC_VER_27,
135 RTL_GIGA_MAC_VER_28,
136 RTL_GIGA_MAC_VER_29,
137 RTL_GIGA_MAC_VER_30,
138 RTL_GIGA_MAC_VER_31,
139 RTL_GIGA_MAC_VER_32,
140 RTL_GIGA_MAC_VER_33,
70090424 141 RTL_GIGA_MAC_VER_34,
c2218925
HW		 142 RTL_GIGA_MAC_VER_35,
143 RTL_GIGA_MAC_VER_36,
7e18dca1 144 RTL_GIGA_MAC_VER_37,
b3d7b2f2 145 RTL_GIGA_MAC_VER_38,
5598bfe5 146 RTL_GIGA_MAC_VER_39,
c558386b
HW		 147 RTL_GIGA_MAC_VER_40,
148 RTL_GIGA_MAC_VER_41,
85bffe6c 149 RTL_GIGA_MAC_NONE = 0xff,
1da177e4
LT		 150};
151
2b7b4318
FR		 152enum rtl_tx_desc_version {
153 RTL_TD_0 = 0,
154 RTL_TD_1 = 1,
155};
156
d58d46b5
FR		 157#define JUMBO_1K ETH_DATA_LEN
158#define JUMBO_4K (4*1024 - ETH_HLEN - 2)
159#define JUMBO_6K (6*1024 - ETH_HLEN - 2)
160#define JUMBO_7K (7*1024 - ETH_HLEN - 2)
161#define JUMBO_9K (9*1024 - ETH_HLEN - 2)
162
163#define _R(NAME,TD,FW,SZ,B) { \
164 .name = NAME, \
165 .txd_version = TD, \
166 .fw_name = FW, \
167 .jumbo_max = SZ, \
168 .jumbo_tx_csum = B \
169}
1da177e4 170
3c6bee1d 171static const struct {
1da177e4 172 const char *name;
2b7b4318 173 enum rtl_tx_desc_version txd_version;
953a12cc 174 const char *fw_name;
d58d46b5
FR		 175 u16 jumbo_max;
176 bool jumbo_tx_csum;
85bffe6c
FR		 177} rtl_chip_infos[] = {
178 /* PCI devices. */
179 [RTL_GIGA_MAC_VER_01] =
d58d46b5 180 _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 181 [RTL_GIGA_MAC_VER_02] =
d58d46b5 182 _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 183 [RTL_GIGA_MAC_VER_03] =
d58d46b5 184 _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 185 [RTL_GIGA_MAC_VER_04] =
d58d46b5 186 _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 187 [RTL_GIGA_MAC_VER_05] =
d58d46b5 188 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 189 [RTL_GIGA_MAC_VER_06] =
d58d46b5 190 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c
FR		 191 /* PCI-E devices. */
192 [RTL_GIGA_MAC_VER_07] =
d58d46b5 193 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 194 [RTL_GIGA_MAC_VER_08] =
d58d46b5 195 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 196 [RTL_GIGA_MAC_VER_09] =
d58d46b5 197 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 198 [RTL_GIGA_MAC_VER_10] =
d58d46b5 199 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 200 [RTL_GIGA_MAC_VER_11] =
d58d46b5 201 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
85bffe6c 202 [RTL_GIGA_MAC_VER_12] =
d58d46b5 203 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
85bffe6c 204 [RTL_GIGA_MAC_VER_13] =
d58d46b5 205 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 206 [RTL_GIGA_MAC_VER_14] =
d58d46b5 207 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 208 [RTL_GIGA_MAC_VER_15] =
d58d46b5 209 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 210 [RTL_GIGA_MAC_VER_16] =
d58d46b5 211 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 212 [RTL_GIGA_MAC_VER_17] =
d58d46b5 213 _R("RTL8168b/8111b", RTL_TD_1, NULL, JUMBO_4K, false),
85bffe6c 214 [RTL_GIGA_MAC_VER_18] =
d58d46b5 215 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 216 [RTL_GIGA_MAC_VER_19] =
d58d46b5 217 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 218 [RTL_GIGA_MAC_VER_20] =
d58d46b5 219 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 220 [RTL_GIGA_MAC_VER_21] =
d58d46b5 221 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 222 [RTL_GIGA_MAC_VER_22] =
d58d46b5 223 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 224 [RTL_GIGA_MAC_VER_23] =
d58d46b5 225 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 226 [RTL_GIGA_MAC_VER_24] =
d58d46b5 227 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 228 [RTL_GIGA_MAC_VER_25] =
d58d46b5
FR		 229 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1,
230 JUMBO_9K, false),
85bffe6c 231 [RTL_GIGA_MAC_VER_26] =
d58d46b5
FR		 232 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2,
233 JUMBO_9K, false),
85bffe6c 234 [RTL_GIGA_MAC_VER_27] =
d58d46b5 235 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 236 [RTL_GIGA_MAC_VER_28] =
d58d46b5 237 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 238 [RTL_GIGA_MAC_VER_29] =
d58d46b5
FR		 239 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
240 JUMBO_1K, true),
85bffe6c 241 [RTL_GIGA_MAC_VER_30] =
d58d46b5
FR		 242 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
243 JUMBO_1K, true),
85bffe6c 244 [RTL_GIGA_MAC_VER_31] =
d58d46b5 245 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 246 [RTL_GIGA_MAC_VER_32] =
d58d46b5
FR		 247 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1,
248 JUMBO_9K, false),
85bffe6c 249 [RTL_GIGA_MAC_VER_33] =
d58d46b5
FR		 250 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2,
251 JUMBO_9K, false),
70090424 252 [RTL_GIGA_MAC_VER_34] =
d58d46b5
FR		 253 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
254 JUMBO_9K, false),
c2218925 255 [RTL_GIGA_MAC_VER_35] =
d58d46b5
FR		 256 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1,
257 JUMBO_9K, false),
c2218925 258 [RTL_GIGA_MAC_VER_36] =
d58d46b5
FR		 259 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2,
260 JUMBO_9K, false),
7e18dca1
HW		 261 [RTL_GIGA_MAC_VER_37] =
262 _R("RTL8402", RTL_TD_1, FIRMWARE_8402_1,
263 JUMBO_1K, true),
b3d7b2f2
HW		 264 [RTL_GIGA_MAC_VER_38] =
265 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_1,
266 JUMBO_9K, false),
5598bfe5
HW		 267 [RTL_GIGA_MAC_VER_39] =
268 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_1,
269 JUMBO_1K, true),
c558386b
HW		 270 [RTL_GIGA_MAC_VER_40] =
271 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_1,
272 JUMBO_9K, false),
273 [RTL_GIGA_MAC_VER_41] =
274 _R("RTL8168g/8111g", RTL_TD_1, NULL, JUMBO_9K, false),
953a12cc 275};
85bffe6c 276#undef _R
953a12cc 277
bcf0bf90
FR		 278enum cfg_version {
279 RTL_CFG_0 = 0x00,
280 RTL_CFG_1,
281 RTL_CFG_2
282};
283
a3aa1884 284static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
bcf0bf90 285 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 286 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 287 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 288 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90 289 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
2a35cfa5
FR		 290 { PCI_VENDOR_ID_DLINK, 0x4300,
291 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
bcf0bf90 292 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
93a3aa25 293 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
bc1660b5 294 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 295 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
296 { PCI_VENDOR_ID_LINKSYS, 0x1032,
297 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 298 { 0x0001, 0x8168,
299 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 300 {0,},
301};
302
303MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
304
6f0333b8 305static int rx_buf_sz = 16383;
4300e8c7 306static int use_dac;
b57b7e5a
SH		 307static struct {
308 u32 msg_enable;
309} debug = { -1 };
1da177e4 310
07d3f51f
FR		 311enum rtl_registers {
312 MAC0 = 0, /* Ethernet hardware address. */
773d2021 313 MAC4 = 4,
07d3f51f
FR		 314 MAR0 = 8, /* Multicast filter. */
315 CounterAddrLow = 0x10,
316 CounterAddrHigh = 0x14,
317 TxDescStartAddrLow = 0x20,
318 TxDescStartAddrHigh = 0x24,
319 TxHDescStartAddrLow = 0x28,
320 TxHDescStartAddrHigh = 0x2c,
321 FLASH = 0x30,
322 ERSR = 0x36,
323 ChipCmd = 0x37,
324 TxPoll = 0x38,
325 IntrMask = 0x3c,
326 IntrStatus = 0x3e,
4f6b00e5 327
07d3f51f 328 TxConfig = 0x40,
4f6b00e5
HW		 329#define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
330#define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
2b7b4318 331
4f6b00e5
HW		 332 RxConfig = 0x44,
333#define RX128_INT_EN (1 << 15) /* 8111c and later */
334#define RX_MULTI_EN (1 << 14) /* 8111c only */
335#define RXCFG_FIFO_SHIFT 13
336 /* No threshold before first PCI xfer */
337#define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
338#define RXCFG_DMA_SHIFT 8
339 /* Unlimited maximum PCI burst. */
340#define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
2b7b4318 341
07d3f51f
FR		 342 RxMissed = 0x4c,
343 Cfg9346 = 0x50,
344 Config0 = 0x51,
345 Config1 = 0x52,
346 Config2 = 0x53,
d387b427
FR		 347#define PME_SIGNAL (1 << 5) /* 8168c and later */
348
07d3f51f
FR		 349 Config3 = 0x54,
350 Config4 = 0x55,
351 Config5 = 0x56,
352 MultiIntr = 0x5c,
353 PHYAR = 0x60,
07d3f51f
FR		 354 PHYstatus = 0x6c,
355 RxMaxSize = 0xda,
356 CPlusCmd = 0xe0,
357 IntrMitigate = 0xe2,
358 RxDescAddrLow = 0xe4,
359 RxDescAddrHigh = 0xe8,
f0298f81 360 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
361
362#define NoEarlyTx 0x3f /* Max value : no early transmit. */
363
364 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
365
366#define TxPacketMax (8064 >> 7)
3090bd9a 367#define EarlySize 0x27
f0298f81 368
07d3f51f
FR		 369 FuncEvent = 0xf0,
370 FuncEventMask = 0xf4,
371 FuncPresetState = 0xf8,
372 FuncForceEvent = 0xfc,
1da177e4
LT		 373};
374
f162a5d1
FR		 375enum rtl8110_registers {
376 TBICSR = 0x64,
377 TBI_ANAR = 0x68,
378 TBI_LPAR = 0x6a,
379};
380
381enum rtl8168_8101_registers {
382 CSIDR = 0x64,
383 CSIAR = 0x68,
384#define CSIAR_FLAG 0x80000000
385#define CSIAR_WRITE_CMD 0x80000000
386#define CSIAR_BYTE_ENABLE 0x0f
387#define CSIAR_BYTE_ENABLE_SHIFT 12
388#define CSIAR_ADDR_MASK 0x0fff
7e18dca1
HW		 389#define CSIAR_FUNC_CARD 0x00000000
390#define CSIAR_FUNC_SDIO 0x00010000
391#define CSIAR_FUNC_NIC 0x00020000
065c27c1 392 PMCH = 0x6f,
f162a5d1
FR		 393 EPHYAR = 0x80,
394#define EPHYAR_FLAG 0x80000000
395#define EPHYAR_WRITE_CMD 0x80000000
396#define EPHYAR_REG_MASK 0x1f
397#define EPHYAR_REG_SHIFT 16
398#define EPHYAR_DATA_MASK 0xffff
5a5e4443 399 DLLPR = 0xd0,
4f6b00e5 400#define PFM_EN (1 << 6)
f162a5d1
FR		 401 DBG_REG = 0xd1,
402#define FIX_NAK_1 (1 << 4)
403#define FIX_NAK_2 (1 << 3)
5a5e4443
HW		 404 TWSI = 0xd2,
405 MCU = 0xd3,
4f6b00e5 406#define NOW_IS_OOB (1 << 7)
c558386b
HW		 407#define TX_EMPTY (1 << 5)
408#define RX_EMPTY (1 << 4)
409#define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
5a5e4443
HW		 410#define EN_NDP (1 << 3)
411#define EN_OOB_RESET (1 << 2)
c558386b 412#define LINK_LIST_RDY (1 << 1)
daf9df6d 413 EFUSEAR = 0xdc,
414#define EFUSEAR_FLAG 0x80000000
415#define EFUSEAR_WRITE_CMD 0x80000000
416#define EFUSEAR_READ_CMD 0x00000000
417#define EFUSEAR_REG_MASK 0x03ff
418#define EFUSEAR_REG_SHIFT 8
419#define EFUSEAR_DATA_MASK 0xff
f162a5d1
FR		 420};
421
c0e45c1c 422enum rtl8168_registers {
4f6b00e5
HW		 423 LED_FREQ = 0x1a,
424 EEE_LED = 0x1b,
b646d900 425 ERIDR = 0x70,
426 ERIAR = 0x74,
427#define ERIAR_FLAG 0x80000000
428#define ERIAR_WRITE_CMD 0x80000000
429#define ERIAR_READ_CMD 0x00000000
430#define ERIAR_ADDR_BYTE_ALIGN 4
b646d900 431#define ERIAR_TYPE_SHIFT 16
4f6b00e5
HW		 432#define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
433#define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
434#define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
435#define ERIAR_MASK_SHIFT 12
436#define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
437#define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
c558386b 438#define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
4f6b00e5 439#define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
c0e45c1c 440 EPHY_RXER_NUM = 0x7c,
441 OCPDR = 0xb0, /* OCP GPHY access */
442#define OCPDR_WRITE_CMD 0x80000000
443#define OCPDR_READ_CMD 0x00000000
444#define OCPDR_REG_MASK 0x7f
445#define OCPDR_GPHY_REG_SHIFT 16
446#define OCPDR_DATA_MASK 0xffff
447 OCPAR = 0xb4,
448#define OCPAR_FLAG 0x80000000
449#define OCPAR_GPHY_WRITE_CMD 0x8000f060
450#define OCPAR_GPHY_READ_CMD 0x0000f060
c558386b 451 GPHY_OCP = 0xb8,
01dc7fec 452 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
453 MISC = 0xf0, /* 8168e only. */
cecb5fd7 454#define TXPLA_RST (1 << 29)
5598bfe5 455#define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
4f6b00e5 456#define PWM_EN (1 << 22)
c558386b 457#define RXDV_GATED_EN (1 << 19)
5598bfe5 458#define EARLY_TALLY_EN (1 << 16)
c0e45c1c 459};
460
07d3f51f 461enum rtl_register_content {
1da177e4 462 /* InterruptStatusBits */
07d3f51f
FR		 463 SYSErr = 0x8000,
464 PCSTimeout = 0x4000,
465 SWInt = 0x0100,
466 TxDescUnavail = 0x0080,
467 RxFIFOOver = 0x0040,
468 LinkChg = 0x0020,
469 RxOverflow = 0x0010,
470 TxErr = 0x0008,
471 TxOK = 0x0004,
472 RxErr = 0x0002,
473 RxOK = 0x0001,
1da177e4
LT		 474
475 /* RxStatusDesc */
e03f33af 476 RxBOVF = (1 << 24),
9dccf611
FR		 477 RxFOVF = (1 << 23),
478 RxRWT = (1 << 22),
479 RxRES = (1 << 21),
480 RxRUNT = (1 << 20),
481 RxCRC = (1 << 19),
1da177e4
LT		 482
483 /* ChipCmdBits */
4f6b00e5 484 StopReq = 0x80,
07d3f51f
FR		 485 CmdReset = 0x10,
486 CmdRxEnb = 0x08,
487 CmdTxEnb = 0x04,
488 RxBufEmpty = 0x01,
1da177e4 489
275391a4
FR		 490 /* TXPoll register p.5 */
491 HPQ = 0x80, /* Poll cmd on the high prio queue */
492 NPQ = 0x40, /* Poll cmd on the low prio queue */
493 FSWInt = 0x01, /* Forced software interrupt */
494
1da177e4 495 /* Cfg9346Bits */
07d3f51f
FR		 496 Cfg9346_Lock = 0x00,
497 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 498
499 /* rx_mode_bits */
07d3f51f
FR		 500 AcceptErr = 0x20,
501 AcceptRunt = 0x10,
502 AcceptBroadcast = 0x08,
503 AcceptMulticast = 0x04,
504 AcceptMyPhys = 0x02,
505 AcceptAllPhys = 0x01,
1687b566 506#define RX_CONFIG_ACCEPT_MASK 0x3f
1da177e4 507
1da177e4
LT		 508 /* TxConfigBits */
509 TxInterFrameGapShift = 24,
510 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
511
5d06a99f 512 /* Config1 register p.24 */
f162a5d1
FR		 513 LEDS1 = (1 << 7),
514 LEDS0 = (1 << 6),
f162a5d1
FR		 515 Speed_down = (1 << 4),
516 MEMMAP = (1 << 3),
517 IOMAP = (1 << 2),
518 VPD = (1 << 1),
5d06a99f
FR		 519 PMEnable = (1 << 0), /* Power Management Enable */
520
6dccd16b 521 /* Config2 register p. 25 */
2ca6cf06 522 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
6dccd16b
FR		 523 PCI_Clock_66MHz = 0x01,
524 PCI_Clock_33MHz = 0x00,
525
61a4dcc2
FR		 526 /* Config3 register p.25 */
527 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
528 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
d58d46b5 529 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
f162a5d1 530 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 531
d58d46b5
FR		 532 /* Config4 register */
533 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
534
5d06a99f 535 /* Config5 register p.27 */
61a4dcc2
FR		 536 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
537 MWF = (1 << 5), /* Accept Multicast wakeup frame */
538 UWF = (1 << 4), /* Accept Unicast wakeup frame */
cecb5fd7 539 Spi_en = (1 << 3),
61a4dcc2 540 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 541 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
542
1da177e4
LT		 543 /* TBICSR p.28 */
544 TBIReset = 0x80000000,
545 TBILoopback = 0x40000000,
546 TBINwEnable = 0x20000000,
547 TBINwRestart = 0x10000000,
548 TBILinkOk = 0x02000000,
549 TBINwComplete = 0x01000000,
550
551 /* CPlusCmd p.31 */
f162a5d1
FR		 552 EnableBist = (1 << 15), // 8168 8101
553 Mac_dbgo_oe = (1 << 14), // 8168 8101
554 Normal_mode = (1 << 13), // unused
555 Force_half_dup = (1 << 12), // 8168 8101
556 Force_rxflow_en = (1 << 11), // 8168 8101
557 Force_txflow_en = (1 << 10), // 8168 8101
558 Cxpl_dbg_sel = (1 << 9), // 8168 8101
559 ASF = (1 << 8), // 8168 8101
560 PktCntrDisable = (1 << 7), // 8168 8101
561 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 562 RxVlan = (1 << 6),
563 RxChkSum = (1 << 5),
564 PCIDAC = (1 << 4),
565 PCIMulRW = (1 << 3),
0e485150
FR		 566 INTT_0 = 0x0000, // 8168
567 INTT_1 = 0x0001, // 8168
568 INTT_2 = 0x0002, // 8168
569 INTT_3 = 0x0003, // 8168
1da177e4
LT		 570
571 /* rtl8169_PHYstatus */
07d3f51f
FR		 572 TBI_Enable = 0x80,
573 TxFlowCtrl = 0x40,
574 RxFlowCtrl = 0x20,
575 _1000bpsF = 0x10,
576 _100bps = 0x08,
577 _10bps = 0x04,
578 LinkStatus = 0x02,
579 FullDup = 0x01,
1da177e4 580
1da177e4 581 /* _TBICSRBit */
07d3f51f 582 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 583
584 /* DumpCounterCommand */
07d3f51f 585 CounterDump = 0x8,
1da177e4
LT		 586};
587
2b7b4318
FR		 588enum rtl_desc_bit {
589 /* First doubleword. */
1da177e4
LT		 590 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
591 RingEnd = (1 << 30), /* End of descriptor ring */
592 FirstFrag = (1 << 29), /* First segment of a packet */
593 LastFrag = (1 << 28), /* Final segment of a packet */
2b7b4318
FR		 594};
595
596/* Generic case. */
597enum rtl_tx_desc_bit {
598 /* First doubleword. */
599 TD_LSO = (1 << 27), /* Large Send Offload */
600#define TD_MSS_MAX 0x07ffu /* MSS value */
1da177e4 601
2b7b4318
FR		 602 /* Second doubleword. */
603 TxVlanTag = (1 << 17), /* Add VLAN tag */
604};
605
606/* 8169, 8168b and 810x except 8102e. */
607enum rtl_tx_desc_bit_0 {
608 /* First doubleword. */
609#define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
610 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
611 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
612 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
613};
614
615/* 8102e, 8168c and beyond. */
616enum rtl_tx_desc_bit_1 {
617 /* Second doubleword. */
618#define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
619 TD1_IP_CS = (1 << 29), /* Calculate IP checksum */
620 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
621 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
622};
1da177e4 623
2b7b4318
FR		 624static const struct rtl_tx_desc_info {
625 struct {
626 u32 udp;
627 u32 tcp;
628 } checksum;
629 u16 mss_shift;
630 u16 opts_offset;
631} tx_desc_info [] = {
632 [RTL_TD_0] = {
633 .checksum = {
634 .udp = TD0_IP_CS | TD0_UDP_CS,
635 .tcp = TD0_IP_CS | TD0_TCP_CS
636 },
637 .mss_shift = TD0_MSS_SHIFT,
638 .opts_offset = 0
639 },
640 [RTL_TD_1] = {
641 .checksum = {
642 .udp = TD1_IP_CS | TD1_UDP_CS,
643 .tcp = TD1_IP_CS | TD1_TCP_CS
644 },
645 .mss_shift = TD1_MSS_SHIFT,
646 .opts_offset = 1
647 }
648};
649
650enum rtl_rx_desc_bit {
1da177e4
LT		 651 /* Rx private */
652 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
653 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
654
655#define RxProtoUDP (PID1)
656#define RxProtoTCP (PID0)
657#define RxProtoIP (PID1 | PID0)
658#define RxProtoMask RxProtoIP
659
660 IPFail = (1 << 16), /* IP checksum failed */
661 UDPFail = (1 << 15), /* UDP/IP checksum failed */
662 TCPFail = (1 << 14), /* TCP/IP checksum failed */
663 RxVlanTag = (1 << 16), /* VLAN tag available */
664};
665
666#define RsvdMask 0x3fffc000
667
668struct TxDesc {
6cccd6e7
REB		 669 __le32 opts1;
670 __le32 opts2;
671 __le64 addr;
1da177e4
LT		 672};
673
674struct RxDesc {
6cccd6e7
REB		 675 __le32 opts1;
676 __le32 opts2;
677 __le64 addr;
1da177e4
LT		 678};
679
680struct ring_info {
681 struct sk_buff *skb;
682 u32 len;
683 u8 __pad[sizeof(void *) - sizeof(u32)];
684};
685
f23e7fda 686enum features {
ccdffb9a
FR		 687 RTL_FEATURE_WOL = (1 << 0),
688 RTL_FEATURE_MSI = (1 << 1),
689 RTL_FEATURE_GMII = (1 << 2),
e0c07557 690 RTL_FEATURE_FW_LOADED = (1 << 3),
f23e7fda
FR		 691};
692
355423d0
IV		 693struct rtl8169_counters {
694 __le64 tx_packets;
695 __le64 rx_packets;
696 __le64 tx_errors;
697 __le32 rx_errors;
698 __le16 rx_missed;
699 __le16 align_errors;
700 __le32 tx_one_collision;
701 __le32 tx_multi_collision;
702 __le64 rx_unicast;
703 __le64 rx_broadcast;
704 __le32 rx_multicast;
705 __le16 tx_aborted;
706 __le16 tx_underun;
707};
708
da78dbff 709enum rtl_flag {
6c4a70c5 710 RTL_FLAG_TASK_ENABLED,
da78dbff
FR		 711 RTL_FLAG_TASK_SLOW_PENDING,
712 RTL_FLAG_TASK_RESET_PENDING,
713 RTL_FLAG_TASK_PHY_PENDING,
714 RTL_FLAG_MAX
715};
716
8027aa24
JW		 717struct rtl8169_stats {
718 u64 packets;
719 u64 bytes;
720 struct u64_stats_sync syncp;
721};
722
1da177e4
LT		 723struct rtl8169_private {
724 void __iomem *mmio_addr; /* memory map physical address */
cecb5fd7 725 struct pci_dev *pci_dev;
c4028958 726 struct net_device *dev;
bea3348e 727 struct napi_struct napi;
b57b7e5a 728 u32 msg_enable;
2b7b4318
FR		 729 u16 txd_version;
730 u16 mac_version;
1da177e4
LT		 731 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
732 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
733 u32 dirty_rx;
734 u32 dirty_tx;
8027aa24
JW		 735 struct rtl8169_stats rx_stats;
736 struct rtl8169_stats tx_stats;
1da177e4
LT		 737 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
738 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
739 dma_addr_t TxPhyAddr;
740 dma_addr_t RxPhyAddr;
6f0333b8 741 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
1da177e4 742 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
1da177e4
LT		 743 struct timer_list timer;
744 u16 cp_cmd;
da78dbff
FR		 745
746 u16 event_slow;
c0e45c1c 747
748 struct mdio_ops {
24192210
FR		 749 void (*write)(struct rtl8169_private *, int, int);
750 int (*read)(struct rtl8169_private *, int);
c0e45c1c 751 } mdio_ops;
752
065c27c1 753 struct pll_power_ops {
754 void (*down)(struct rtl8169_private *);
755 void (*up)(struct rtl8169_private *);
756 } pll_power_ops;
757
d58d46b5
FR		 758 struct jumbo_ops {
759 void (*enable)(struct rtl8169_private *);
760 void (*disable)(struct rtl8169_private *);
761 } jumbo_ops;
762
beb1fe18 763 struct csi_ops {
52989f0e
FR		 764 void (*write)(struct rtl8169_private *, int, int);
765 u32 (*read)(struct rtl8169_private *, int);
beb1fe18
HW		 766 } csi_ops;
767
54405cde 768 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
ccdffb9a 769 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
4da19633 770 void (*phy_reset_enable)(struct rtl8169_private *tp);
07ce4064 771 void (*hw_start)(struct net_device *);
4da19633 772 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
1da177e4 773 unsigned int (*link_ok)(void __iomem *);
8b4ab28d 774 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
4422bcd4
FR		 775
776 struct {
da78dbff
FR		 777 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
778 struct mutex mutex;
4422bcd4
FR		 779 struct work_struct work;
780 } wk;
781
f23e7fda 782 unsigned features;
ccdffb9a
FR		 783
784 struct mii_if_info mii;
355423d0 785 struct rtl8169_counters counters;
e1759441 786 u32 saved_wolopts;
e03f33af 787 u32 opts1_mask;
f1e02ed1 788
b6ffd97f
FR		 789 struct rtl_fw {
790 const struct firmware *fw;
1c361efb
FR		 791
792#define RTL_VER_SIZE 32
793
794 char version[RTL_VER_SIZE];
795
796 struct rtl_fw_phy_action {
797 __le32 *code;
798 size_t size;
799 } phy_action;
b6ffd97f 800 } *rtl_fw;
497888cf 801#define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
c558386b
HW		 802
803 u32 ocp_base;
1da177e4
LT		 804};
805
979b6c13 806MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 807MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 808module_param(use_dac, int, 0);
4300e8c7 809MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 810module_param_named(debug, debug.msg_enable, int, 0);
811MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 812MODULE_LICENSE("GPL");
813MODULE_VERSION(RTL8169_VERSION);
bca03d5f 814MODULE_FIRMWARE(FIRMWARE_8168D_1);
815MODULE_FIRMWARE(FIRMWARE_8168D_2);
01dc7fec 816MODULE_FIRMWARE(FIRMWARE_8168E_1);
817MODULE_FIRMWARE(FIRMWARE_8168E_2);
bbb8af75 818MODULE_FIRMWARE(FIRMWARE_8168E_3);
5a5e4443 819MODULE_FIRMWARE(FIRMWARE_8105E_1);
c2218925
HW		 820MODULE_FIRMWARE(FIRMWARE_8168F_1);
821MODULE_FIRMWARE(FIRMWARE_8168F_2);
7e18dca1 822MODULE_FIRMWARE(FIRMWARE_8402_1);
b3d7b2f2 823MODULE_FIRMWARE(FIRMWARE_8411_1);
5598bfe5 824MODULE_FIRMWARE(FIRMWARE_8106E_1);
c558386b 825MODULE_FIRMWARE(FIRMWARE_8168G_1);
1da177e4 826
da78dbff
FR		 827static void rtl_lock_work(struct rtl8169_private *tp)
828{
829 mutex_lock(&tp->wk.mutex);
830}
831
832static void rtl_unlock_work(struct rtl8169_private *tp)
833{
834 mutex_unlock(&tp->wk.mutex);
835}
836
d58d46b5
FR		 837static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
838{
7d7903b2
JL		 839 pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
840 PCI_EXP_DEVCTL_READRQ, force);
d58d46b5
FR		 841}
842
ffc46952
FR		 843struct rtl_cond {
844 bool (*check)(struct rtl8169_private *);
845 const char *msg;
846};
847
848static void rtl_udelay(unsigned int d)
849{
850 udelay(d);
851}
852
853static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
854 void (*delay)(unsigned int), unsigned int d, int n,
855 bool high)
856{
857 int i;
858
859 for (i = 0; i < n; i++) {
860 delay(d);
861 if (c->check(tp) == high)
862 return true;
863 }
82e316ef
FR		 864 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
865 c->msg, !high, n, d);
ffc46952
FR		 866 return false;
867}
868
869static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
870 const struct rtl_cond *c,
871 unsigned int d, int n)
872{
873 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
874}
875
876static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
877 const struct rtl_cond *c,
878 unsigned int d, int n)
879{
880 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
881}
882
883static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
884 const struct rtl_cond *c,
885 unsigned int d, int n)
886{
887 return rtl_loop_wait(tp, c, msleep, d, n, true);
888}
889
890static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
891 const struct rtl_cond *c,
892 unsigned int d, int n)
893{
894 return rtl_loop_wait(tp, c, msleep, d, n, false);
895}
896
897#define DECLARE_RTL_COND(name) \
898static bool name ## _check(struct rtl8169_private *); \
899 \
900static const struct rtl_cond name = { \
901 .check = name ## _check, \
902 .msg = #name \
903}; \
904 \
905static bool name ## _check(struct rtl8169_private *tp)
906
907DECLARE_RTL_COND(rtl_ocpar_cond)
908{
909 void __iomem *ioaddr = tp->mmio_addr;
910
911 return RTL_R32(OCPAR) & OCPAR_FLAG;
912}
913
b646d900 914static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
915{
916 void __iomem *ioaddr = tp->mmio_addr;
b646d900 917
918 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
ffc46952
FR		 919
920 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
921 RTL_R32(OCPDR) : ~0;
b646d900 922}
923
924static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
925{
926 void __iomem *ioaddr = tp->mmio_addr;
b646d900 927
928 RTL_W32(OCPDR, data);
929 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
ffc46952
FR		 930
931 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
932}
933
934DECLARE_RTL_COND(rtl_eriar_cond)
935{
936 void __iomem *ioaddr = tp->mmio_addr;
937
938 return RTL_R32(ERIAR) & ERIAR_FLAG;
b646d900 939}
940
fac5b3ca 941static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
b646d900 942{
fac5b3ca 943 void __iomem *ioaddr = tp->mmio_addr;
b646d900 944
945 RTL_W8(ERIDR, cmd);
946 RTL_W32(ERIAR, 0x800010e8);
947 msleep(2);
ffc46952
FR		 948
949 if (!rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 5))
950 return;
b646d900 951
fac5b3ca 952 ocp_write(tp, 0x1, 0x30, 0x00000001);
b646d900 953}
954
955#define OOB_CMD_RESET 0x00
956#define OOB_CMD_DRIVER_START 0x05
957#define OOB_CMD_DRIVER_STOP 0x06
958
cecb5fd7
FR		 959static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
960{
961 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
962}
963
ffc46952 964DECLARE_RTL_COND(rtl_ocp_read_cond)
b646d900 965{
cecb5fd7 966 u16 reg;
b646d900 967
cecb5fd7 968 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 969
ffc46952 970 return ocp_read(tp, 0x0f, reg) & 0x00000800;
b646d900 971}
972
ffc46952 973static void rtl8168_driver_start(struct rtl8169_private *tp)
b646d900 974{
ffc46952 975 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
b646d900 976
ffc46952
FR		 977 rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
978}
b646d900 979
ffc46952
FR		 980static void rtl8168_driver_stop(struct rtl8169_private *tp)
981{
982 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
4804b3b3 983
ffc46952 984 rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
b646d900 985}
986
4804b3b3 987static int r8168dp_check_dash(struct rtl8169_private *tp)
988{
cecb5fd7 989 u16 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 990
cecb5fd7 991 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
4804b3b3 992}
b646d900 993
c558386b
HW		 994static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
995{
996 if (reg & 0xffff0001) {
997 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
998 return true;
999 }
1000 return false;
1001}
1002
1003DECLARE_RTL_COND(rtl_ocp_gphy_cond)
1004{
1005 void __iomem *ioaddr = tp->mmio_addr;
1006
1007 return RTL_R32(GPHY_OCP) & OCPAR_FLAG;
1008}
1009
1010static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1011{
1012 void __iomem *ioaddr = tp->mmio_addr;
1013
1014 if (rtl_ocp_reg_failure(tp, reg))
1015 return;
1016
1017 RTL_W32(GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
1018
1019 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
1020}
1021
1022static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
1023{
1024 void __iomem *ioaddr = tp->mmio_addr;
1025
1026 if (rtl_ocp_reg_failure(tp, reg))
1027 return 0;
1028
1029 RTL_W32(GPHY_OCP, reg << 15);
1030
1031 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
1032 (RTL_R32(GPHY_OCP) & 0xffff) : ~0;
1033}
1034
1035static void rtl_w1w0_phy_ocp(struct rtl8169_private *tp, int reg, int p, int m)
1036{
1037 int val;
1038
1039 val = r8168_phy_ocp_read(tp, reg);
1040 r8168_phy_ocp_write(tp, reg, (val | p) & ~m);
1041}
1042
c558386b
HW		 1043static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1044{
1045 void __iomem *ioaddr = tp->mmio_addr;
1046
1047 if (rtl_ocp_reg_failure(tp, reg))
1048 return;
1049
1050 RTL_W32(OCPDR, OCPAR_FLAG | (reg << 15) | data);
c558386b
HW		 1051}
1052
1053static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1054{
1055 void __iomem *ioaddr = tp->mmio_addr;
1056
1057 if (rtl_ocp_reg_failure(tp, reg))
1058 return 0;
1059
1060 RTL_W32(OCPDR, reg << 15);
1061
3a83ad12 1062 return RTL_R32(OCPDR);
c558386b
HW		 1063}
1064
1065#define OCP_STD_PHY_BASE 0xa400
1066
1067static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
1068{
1069 if (reg == 0x1f) {
1070 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
1071 return;
1072 }
1073
1074 if (tp->ocp_base != OCP_STD_PHY_BASE)
1075 reg -= 0x10;
1076
1077 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
1078}
1079
1080static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1081{
1082 if (tp->ocp_base != OCP_STD_PHY_BASE)
1083 reg -= 0x10;
1084
1085 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
1086}
1087
ffc46952
FR		 1088DECLARE_RTL_COND(rtl_phyar_cond)
1089{
1090 void __iomem *ioaddr = tp->mmio_addr;
1091
1092 return RTL_R32(PHYAR) & 0x80000000;
1093}
1094
24192210 1095static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1da177e4 1096{
24192210 1097 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 1098
24192210 1099 RTL_W32(PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1da177e4 1100
ffc46952 1101 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
024a07ba 1102 /*
81a95f04
TT		 1103 * According to hardware specs a 20us delay is required after write
1104 * complete indication, but before sending next command.
024a07ba 1105 */
81a95f04 1106 udelay(20);
1da177e4
LT		 1107}
1108
24192210 1109static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1da177e4 1110{
24192210 1111 void __iomem *ioaddr = tp->mmio_addr;
ffc46952 1112 int value;
1da177e4 1113
24192210 1114 RTL_W32(PHYAR, 0x0 | (reg & 0x1f) << 16);
1da177e4 1115
ffc46952
FR		 1116 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1117 RTL_R32(PHYAR) & 0xffff : ~0;
1118
81a95f04
TT		 1119 /*
1120 * According to hardware specs a 20us delay is required after read
1121 * complete indication, but before sending next command.
1122 */
1123 udelay(20);
1124
1da177e4
LT		 1125 return value;
1126}
1127
24192210 1128static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
c0e45c1c 1129{
24192210 1130 void __iomem *ioaddr = tp->mmio_addr;
c0e45c1c 1131
24192210 1132 RTL_W32(OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
c0e45c1c 1133 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
1134 RTL_W32(EPHY_RXER_NUM, 0);
1135
ffc46952 1136 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
c0e45c1c 1137}
1138
24192210 1139static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
c0e45c1c 1140{
24192210
FR		 1141 r8168dp_1_mdio_access(tp, reg,
1142 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
c0e45c1c 1143}
1144
24192210 1145static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
c0e45c1c 1146{
24192210 1147 void __iomem *ioaddr = tp->mmio_addr;
c0e45c1c 1148
24192210 1149 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
c0e45c1c 1150
1151 mdelay(1);
1152 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
1153 RTL_W32(EPHY_RXER_NUM, 0);
1154
ffc46952
FR		 1155 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1156 RTL_R32(OCPDR) & OCPDR_DATA_MASK : ~0;
c0e45c1c 1157}
1158
e6de30d6 1159#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1160
1161static void r8168dp_2_mdio_start(void __iomem *ioaddr)
1162{
1163 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1164}
1165
1166static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
1167{
1168 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1169}
1170
24192210 1171static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
e6de30d6 1172{
24192210
FR		 1173 void __iomem *ioaddr = tp->mmio_addr;
1174
e6de30d6 1175 r8168dp_2_mdio_start(ioaddr);
1176
24192210 1177 r8169_mdio_write(tp, reg, value);
e6de30d6 1178
1179 r8168dp_2_mdio_stop(ioaddr);
1180}
1181
24192210 1182static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
e6de30d6 1183{
24192210 1184 void __iomem *ioaddr = tp->mmio_addr;
e6de30d6 1185 int value;
1186
1187 r8168dp_2_mdio_start(ioaddr);
1188
24192210 1189 value = r8169_mdio_read(tp, reg);
e6de30d6 1190
1191 r8168dp_2_mdio_stop(ioaddr);
1192
1193 return value;
1194}
1195
4da19633 1196static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
dacf8154 1197{
24192210 1198 tp->mdio_ops.write(tp, location, val);
dacf8154
FR		 1199}
1200
4da19633 1201static int rtl_readphy(struct rtl8169_private *tp, int location)
1202{
24192210 1203 return tp->mdio_ops.read(tp, location);
4da19633 1204}
1205
1206static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1207{
1208 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1209}
1210
1211static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
daf9df6d 1212{
1213 int val;
1214
4da19633 1215 val = rtl_readphy(tp, reg_addr);
1216 rtl_writephy(tp, reg_addr, (val | p) & ~m);
daf9df6d 1217}
1218
ccdffb9a
FR		 1219static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1220 int val)
1221{
1222 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1223
4da19633 1224 rtl_writephy(tp, location, val);
ccdffb9a
FR		 1225}
1226
1227static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1228{
1229 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1230
4da19633 1231 return rtl_readphy(tp, location);
ccdffb9a
FR		 1232}
1233
ffc46952
FR		 1234DECLARE_RTL_COND(rtl_ephyar_cond)
1235{
1236 void __iomem *ioaddr = tp->mmio_addr;
1237
1238 return RTL_R32(EPHYAR) & EPHYAR_FLAG;
1239}
1240
fdf6fc06 1241static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
dacf8154 1242{
fdf6fc06 1243 void __iomem *ioaddr = tp->mmio_addr;
dacf8154
FR		 1244
1245 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1246 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1247
ffc46952
FR		 1248 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1249
1250 udelay(10);
dacf8154
FR		 1251}
1252
fdf6fc06 1253static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
dacf8154 1254{
fdf6fc06 1255 void __iomem *ioaddr = tp->mmio_addr;
dacf8154
FR		 1256
1257 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1258
ffc46952
FR		 1259 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1260 RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0;
dacf8154
FR		 1261}
1262
fdf6fc06
FR		 1263static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1264 u32 val, int type)
133ac40a 1265{
fdf6fc06 1266 void __iomem *ioaddr = tp->mmio_addr;
133ac40a
HW		 1267
1268 BUG_ON((addr & 3) || (mask == 0));
1269 RTL_W32(ERIDR, val);
1270 RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1271
ffc46952 1272 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
133ac40a
HW		 1273}
1274
fdf6fc06 1275static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
133ac40a 1276{
fdf6fc06 1277 void __iomem *ioaddr = tp->mmio_addr;
133ac40a
HW		 1278
1279 RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1280
ffc46952
FR		 1281 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1282 RTL_R32(ERIDR) : ~0;
133ac40a
HW		 1283}
1284
fdf6fc06
FR		 1285static void rtl_w1w0_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1286 u32 m, int type)
133ac40a
HW		 1287{
1288 u32 val;
1289
fdf6fc06
FR		 1290 val = rtl_eri_read(tp, addr, type);
1291 rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
133ac40a
HW		 1292}
1293
c28aa385 1294struct exgmac_reg {
1295 u16 addr;
1296 u16 mask;
1297 u32 val;
1298};
1299
fdf6fc06 1300static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
c28aa385 1301 const struct exgmac_reg *r, int len)
1302{
1303 while (len-- > 0) {
fdf6fc06 1304 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
c28aa385 1305 r++;
1306 }
1307}
1308
ffc46952
FR		 1309DECLARE_RTL_COND(rtl_efusear_cond)
1310{
1311 void __iomem *ioaddr = tp->mmio_addr;
1312
1313 return RTL_R32(EFUSEAR) & EFUSEAR_FLAG;
1314}
1315
fdf6fc06 1316static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
daf9df6d 1317{
fdf6fc06 1318 void __iomem *ioaddr = tp->mmio_addr;
daf9df6d 1319
1320 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1321
ffc46952
FR		 1322 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1323 RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
daf9df6d 1324}
1325
9085cdfa
FR		 1326static u16 rtl_get_events(struct rtl8169_private *tp)
1327{
1328 void __iomem *ioaddr = tp->mmio_addr;
1329
1330 return RTL_R16(IntrStatus);
1331}
1332
1333static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1334{
1335 void __iomem *ioaddr = tp->mmio_addr;
1336
1337 RTL_W16(IntrStatus, bits);
1338 mmiowb();
1339}
1340
1341static void rtl_irq_disable(struct rtl8169_private *tp)
1342{
1343 void __iomem *ioaddr = tp->mmio_addr;
1344
1345 RTL_W16(IntrMask, 0);
1346 mmiowb();
1347}
1348
3e990ff5
FR		 1349static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1350{
1351 void __iomem *ioaddr = tp->mmio_addr;
1352
1353 RTL_W16(IntrMask, bits);
1354}
1355
da78dbff
FR		 1356#define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1357#define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1358#define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1359
1360static void rtl_irq_enable_all(struct rtl8169_private *tp)
1361{
1362 rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1363}
1364
811fd301 1365static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1da177e4 1366{
811fd301 1367 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 1368
9085cdfa 1369 rtl_irq_disable(tp);
da78dbff 1370 rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
811fd301 1371 RTL_R8(ChipCmd);
1da177e4
LT		 1372}
1373
4da19633 1374static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1da177e4 1375{
4da19633 1376 void __iomem *ioaddr = tp->mmio_addr;
1377
1da177e4
LT		 1378 return RTL_R32(TBICSR) & TBIReset;
1379}
1380
4da19633 1381static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1da177e4 1382{
4da19633 1383 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 1384}
1385
1386static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1387{
1388 return RTL_R32(TBICSR) & TBILinkOk;
1389}
1390
1391static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1392{
1393 return RTL_R8(PHYstatus) & LinkStatus;
1394}
1395
4da19633 1396static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1da177e4 1397{
4da19633 1398 void __iomem *ioaddr = tp->mmio_addr;
1399
1da177e4
LT		 1400 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1401}
1402
4da19633 1403static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1da177e4
LT		 1404{
1405 unsigned int val;
1406
4da19633 1407 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1408 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1da177e4
LT		 1409}
1410
70090424
HW		 1411static void rtl_link_chg_patch(struct rtl8169_private *tp)
1412{
1413 void __iomem *ioaddr = tp->mmio_addr;
1414 struct net_device *dev = tp->dev;
1415
1416 if (!netif_running(dev))
1417 return;
1418
b3d7b2f2
HW		 1419 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1420 tp->mac_version == RTL_GIGA_MAC_VER_38) {
70090424 1421 if (RTL_R8(PHYstatus) & _1000bpsF) {
fdf6fc06
FR		 1422 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1423 ERIAR_EXGMAC);
1424 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1425 ERIAR_EXGMAC);
70090424 1426 } else if (RTL_R8(PHYstatus) & _100bps) {
fdf6fc06
FR		 1427 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1428 ERIAR_EXGMAC);
1429 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1430 ERIAR_EXGMAC);
70090424 1431 } else {
fdf6fc06
FR		 1432 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1433 ERIAR_EXGMAC);
1434 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1435 ERIAR_EXGMAC);
70090424
HW		 1436 }
1437 /* Reset packet filter */
fdf6fc06 1438 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
70090424 1439 ERIAR_EXGMAC);
fdf6fc06 1440 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
70090424 1441 ERIAR_EXGMAC);
c2218925
HW		 1442 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1443 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1444 if (RTL_R8(PHYstatus) & _1000bpsF) {
fdf6fc06
FR		 1445 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1446 ERIAR_EXGMAC);
1447 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1448 ERIAR_EXGMAC);
c2218925 1449 } else {
fdf6fc06
FR		 1450 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1451 ERIAR_EXGMAC);
1452 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1453 ERIAR_EXGMAC);
c2218925 1454 }
7e18dca1
HW		 1455 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1456 if (RTL_R8(PHYstatus) & _10bps) {
fdf6fc06
FR		 1457 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1458 ERIAR_EXGMAC);
1459 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1460 ERIAR_EXGMAC);
7e18dca1 1461 } else {
fdf6fc06
FR		 1462 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1463 ERIAR_EXGMAC);
7e18dca1 1464 }
70090424
HW		 1465 }
1466}
1467
e4fbce74 1468static void __rtl8169_check_link_status(struct net_device *dev,
cecb5fd7
FR		 1469 struct rtl8169_private *tp,
1470 void __iomem *ioaddr, bool pm)
1da177e4 1471{
1da177e4 1472 if (tp->link_ok(ioaddr)) {
70090424 1473 rtl_link_chg_patch(tp);
e1759441 1474 /* This is to cancel a scheduled suspend if there's one. */
e4fbce74
RW		 1475 if (pm)
1476 pm_request_resume(&tp->pci_dev->dev);
1da177e4 1477 netif_carrier_on(dev);
1519e57f
FR		 1478 if (net_ratelimit())
1479 netif_info(tp, ifup, dev, "link up\n");
b57b7e5a 1480 } else {
1da177e4 1481 netif_carrier_off(dev);
bf82c189 1482 netif_info(tp, ifdown, dev, "link down\n");
e4fbce74 1483 if (pm)
10953db8 1484 pm_schedule_suspend(&tp->pci_dev->dev, 5000);
b57b7e5a 1485 }
1da177e4
LT		 1486}
1487
e4fbce74
RW		 1488static void rtl8169_check_link_status(struct net_device *dev,
1489 struct rtl8169_private *tp,
1490 void __iomem *ioaddr)
1491{
1492 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1493}
1494
e1759441
RW		 1495#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1496
1497static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
61a4dcc2 1498{
61a4dcc2
FR		 1499 void __iomem *ioaddr = tp->mmio_addr;
1500 u8 options;
e1759441 1501 u32 wolopts = 0;
61a4dcc2
FR		 1502
1503 options = RTL_R8(Config1);
1504 if (!(options & PMEnable))
e1759441 1505 return 0;
61a4dcc2
FR		 1506
1507 options = RTL_R8(Config3);
1508 if (options & LinkUp)
e1759441 1509 wolopts |= WAKE_PHY;
61a4dcc2 1510 if (options & MagicPacket)
e1759441 1511 wolopts |= WAKE_MAGIC;
61a4dcc2
FR		 1512
1513 options = RTL_R8(Config5);
1514 if (options & UWF)
e1759441 1515 wolopts |= WAKE_UCAST;
61a4dcc2 1516 if (options & BWF)
e1759441 1517 wolopts |= WAKE_BCAST;
61a4dcc2 1518 if (options & MWF)
e1759441 1519 wolopts |= WAKE_MCAST;
61a4dcc2 1520
e1759441 1521 return wolopts;
61a4dcc2
FR		 1522}
1523
e1759441 1524static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
61a4dcc2
FR		 1525{
1526 struct rtl8169_private *tp = netdev_priv(dev);
e1759441 1527
da78dbff 1528 rtl_lock_work(tp);
e1759441
RW		 1529
1530 wol->supported = WAKE_ANY;
1531 wol->wolopts = __rtl8169_get_wol(tp);
1532
da78dbff 1533 rtl_unlock_work(tp);
e1759441
RW		 1534}
1535
1536static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1537{
61a4dcc2 1538 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1539 unsigned int i;
350f7596 1540 static const struct {
61a4dcc2
FR		 1541 u32 opt;
1542 u16 reg;
1543 u8 mask;
1544 } cfg[] = {
61a4dcc2
FR		 1545 { WAKE_PHY, Config3, LinkUp },
1546 { WAKE_MAGIC, Config3, MagicPacket },
1547 { WAKE_UCAST, Config5, UWF },
1548 { WAKE_BCAST, Config5, BWF },
1549 { WAKE_MCAST, Config5, MWF },
1550 { WAKE_ANY, Config5, LanWake }
1551 };
851e6022 1552 u8 options;
61a4dcc2 1553
61a4dcc2
FR		 1554 RTL_W8(Cfg9346, Cfg9346_Unlock);
1555
1556 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
851e6022 1557 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
e1759441 1558 if (wolopts & cfg[i].opt)
61a4dcc2
FR		 1559 options |= cfg[i].mask;
1560 RTL_W8(cfg[i].reg, options);
1561 }
1562
851e6022
FR		 1563 switch (tp->mac_version) {
1564 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1565 options = RTL_R8(Config1) & ~PMEnable;
1566 if (wolopts)
1567 options |= PMEnable;
1568 RTL_W8(Config1, options);
1569 break;
1570 default:
d387b427
FR		 1571 options = RTL_R8(Config2) & ~PME_SIGNAL;
1572 if (wolopts)
1573 options |= PME_SIGNAL;
1574 RTL_W8(Config2, options);
851e6022
FR		 1575 break;
1576 }
1577
61a4dcc2 1578 RTL_W8(Cfg9346, Cfg9346_Lock);
e1759441
RW		 1579}
1580
1581static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1582{
1583 struct rtl8169_private *tp = netdev_priv(dev);
1584
da78dbff 1585 rtl_lock_work(tp);
61a4dcc2 1586
f23e7fda
FR		 1587 if (wol->wolopts)
1588 tp->features |= RTL_FEATURE_WOL;
1589 else
1590 tp->features &= ~RTL_FEATURE_WOL;
e1759441 1591 __rtl8169_set_wol(tp, wol->wolopts);
da78dbff
FR		 1592
1593 rtl_unlock_work(tp);
61a4dcc2 1594
ea80907f 1595 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1596
61a4dcc2
FR		 1597 return 0;
1598}
1599
31bd204f
FR		 1600static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1601{
85bffe6c 1602 return rtl_chip_infos[tp->mac_version].fw_name;
31bd204f
FR		 1603}
1604
1da177e4
LT		 1605static void rtl8169_get_drvinfo(struct net_device *dev,
1606 struct ethtool_drvinfo *info)
1607{
1608 struct rtl8169_private *tp = netdev_priv(dev);
b6ffd97f 1609 struct rtl_fw *rtl_fw = tp->rtl_fw;
1da177e4 1610
68aad78c
RJ		 1611 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1612 strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1613 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1c361efb 1614 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
8ac72d16
RJ		 1615 if (!IS_ERR_OR_NULL(rtl_fw))
1616 strlcpy(info->fw_version, rtl_fw->version,
1617 sizeof(info->fw_version));
1da177e4
LT		 1618}
1619
1620static int rtl8169_get_regs_len(struct net_device *dev)
1621{
1622 return R8169_REGS_SIZE;
1623}
1624
1625static int rtl8169_set_speed_tbi(struct net_device *dev,
54405cde 1626 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1da177e4
LT		 1627{
1628 struct rtl8169_private *tp = netdev_priv(dev);
1629 void __iomem *ioaddr = tp->mmio_addr;
1630 int ret = 0;
1631 u32 reg;
1632
1633 reg = RTL_R32(TBICSR);
1634 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1635 (duplex == DUPLEX_FULL)) {
1636 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1637 } else if (autoneg == AUTONEG_ENABLE)
1638 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1639 else {
bf82c189
JP		 1640 netif_warn(tp, link, dev,
1641 "incorrect speed setting refused in TBI mode\n");
1da177e4
LT		 1642 ret = -EOPNOTSUPP;
1643 }
1644
1645 return ret;
1646}
1647
1648static int rtl8169_set_speed_xmii(struct net_device *dev,
54405cde 1649 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1da177e4
LT		 1650{
1651 struct rtl8169_private *tp = netdev_priv(dev);
3577aa1b 1652 int giga_ctrl, bmcr;
54405cde 1653 int rc = -EINVAL;
1da177e4 1654
716b50a3 1655 rtl_writephy(tp, 0x1f, 0x0000);
1da177e4
LT		 1656
1657 if (autoneg == AUTONEG_ENABLE) {
3577aa1b 1658 int auto_nego;
1659
4da19633 1660 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
54405cde
ON		 1661 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1662 ADVERTISE_100HALF | ADVERTISE_100FULL);
1663
1664 if (adv & ADVERTISED_10baseT_Half)
1665 auto_nego |= ADVERTISE_10HALF;
1666 if (adv & ADVERTISED_10baseT_Full)
1667 auto_nego |= ADVERTISE_10FULL;
1668 if (adv & ADVERTISED_100baseT_Half)
1669 auto_nego |= ADVERTISE_100HALF;
1670 if (adv & ADVERTISED_100baseT_Full)
1671 auto_nego |= ADVERTISE_100FULL;
1672
3577aa1b 1673 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1da177e4 1674
4da19633 1675 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
3577aa1b 1676 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
bcf0bf90 1677
3577aa1b 1678 /* The 8100e/8101e/8102e do Fast Ethernet only. */
826e6cbd 1679 if (tp->mii.supports_gmii) {
54405cde
ON		 1680 if (adv & ADVERTISED_1000baseT_Half)
1681 giga_ctrl |= ADVERTISE_1000HALF;
1682 if (adv & ADVERTISED_1000baseT_Full)
1683 giga_ctrl |= ADVERTISE_1000FULL;
1684 } else if (adv & (ADVERTISED_1000baseT_Half |
1685 ADVERTISED_1000baseT_Full)) {
bf82c189
JP		 1686 netif_info(tp, link, dev,
1687 "PHY does not support 1000Mbps\n");
54405cde 1688 goto out;
bcf0bf90 1689 }
1da177e4 1690
3577aa1b 1691 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1692
4da19633 1693 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1694 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
3577aa1b 1695 } else {
1696 giga_ctrl = 0;
1697
1698 if (speed == SPEED_10)
1699 bmcr = 0;
1700 else if (speed == SPEED_100)
1701 bmcr = BMCR_SPEED100;
1702 else
54405cde 1703 goto out;
3577aa1b 1704
1705 if (duplex == DUPLEX_FULL)
1706 bmcr |= BMCR_FULLDPLX;
2584fbc3
RS		 1707 }
1708
4da19633 1709 rtl_writephy(tp, MII_BMCR, bmcr);
3577aa1b 1710
cecb5fd7
FR		 1711 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1712 tp->mac_version == RTL_GIGA_MAC_VER_03) {
3577aa1b 1713 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
4da19633 1714 rtl_writephy(tp, 0x17, 0x2138);
1715 rtl_writephy(tp, 0x0e, 0x0260);
3577aa1b 1716 } else {
4da19633 1717 rtl_writephy(tp, 0x17, 0x2108);
1718 rtl_writephy(tp, 0x0e, 0x0000);
3577aa1b 1719 }
1720 }
1721
54405cde
ON		 1722 rc = 0;
1723out:
1724 return rc;
1da177e4
LT		 1725}
1726
1727static int rtl8169_set_speed(struct net_device *dev,
54405cde 1728 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1da177e4
LT		 1729{
1730 struct rtl8169_private *tp = netdev_priv(dev);
1731 int ret;
1732
54405cde 1733 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
4876cc1e
FR		 1734 if (ret < 0)
1735 goto out;
1da177e4 1736
4876cc1e
FR		 1737 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1738 (advertising & ADVERTISED_1000baseT_Full)) {
1da177e4 1739 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
4876cc1e
FR		 1740 }
1741out:
1da177e4
LT		 1742 return ret;
1743}
1744
1745static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1746{
1747 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4
LT		 1748 int ret;
1749
4876cc1e
FR		 1750 del_timer_sync(&tp->timer);
1751
da78dbff 1752 rtl_lock_work(tp);
cecb5fd7 1753 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
25db0338 1754 cmd->duplex, cmd->advertising);
da78dbff 1755 rtl_unlock_work(tp);
5b0384f4 1756
1da177e4
LT		 1757 return ret;
1758}
1759
c8f44aff
MM		 1760static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1761 netdev_features_t features)
1da177e4 1762{
d58d46b5
FR		 1763 struct rtl8169_private *tp = netdev_priv(dev);
1764
2b7b4318 1765 if (dev->mtu > TD_MSS_MAX)
350fb32a 1766 features &= ~NETIF_F_ALL_TSO;
1da177e4 1767
d58d46b5
FR		 1768 if (dev->mtu > JUMBO_1K &&
1769 !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1770 features &= ~NETIF_F_IP_CSUM;
1771
350fb32a 1772 return features;
1da177e4
LT		 1773}
1774
da78dbff
FR		 1775static void __rtl8169_set_features(struct net_device *dev,
1776 netdev_features_t features)
1da177e4
LT		 1777{
1778 struct rtl8169_private *tp = netdev_priv(dev);
6bbe021d 1779 netdev_features_t changed = features ^ dev->features;
da78dbff 1780 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 1781
6bbe021d
BG		 1782 if (!(changed & (NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)))
1783 return;
1da177e4 1784
6bbe021d
BG		 1785 if (changed & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)) {
1786 if (features & NETIF_F_RXCSUM)
1787 tp->cp_cmd |= RxChkSum;
1788 else
1789 tp->cp_cmd &= ~RxChkSum;
350fb32a 1790
6bbe021d
BG		 1791 if (dev->features & NETIF_F_HW_VLAN_RX)
1792 tp->cp_cmd |= RxVlan;
1793 else
1794 tp->cp_cmd &= ~RxVlan;
1795
1796 RTL_W16(CPlusCmd, tp->cp_cmd);
1797 RTL_R16(CPlusCmd);
1798 }
1799 if (changed & NETIF_F_RXALL) {
1800 int tmp = (RTL_R32(RxConfig) & ~(AcceptErr | AcceptRunt));
1801 if (features & NETIF_F_RXALL)
1802 tmp |= (AcceptErr | AcceptRunt);
1803 RTL_W32(RxConfig, tmp);
1804 }
da78dbff 1805}
1da177e4 1806
da78dbff
FR		 1807static int rtl8169_set_features(struct net_device *dev,
1808 netdev_features_t features)
1809{
1810 struct rtl8169_private *tp = netdev_priv(dev);
1811
1812 rtl_lock_work(tp);
1813 __rtl8169_set_features(dev, features);
1814 rtl_unlock_work(tp);
1da177e4
LT		 1815
1816 return 0;
1817}
1818
da78dbff 1819
1da177e4
LT		 1820static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1821 struct sk_buff *skb)
1822{
eab6d18d 1823 return (vlan_tx_tag_present(skb)) ?
1da177e4
LT		 1824 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1825}
1826
7a8fc77b 1827static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1da177e4
LT		 1828{
1829 u32 opts2 = le32_to_cpu(desc->opts2);
1da177e4 1830
7a8fc77b
FR		 1831 if (opts2 & RxVlanTag)
1832 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
2edae08e 1833
1da177e4 1834 desc->opts2 = 0;
1da177e4
LT		 1835}
1836
ccdffb9a 1837static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1838{
1839 struct rtl8169_private *tp = netdev_priv(dev);
1840 void __iomem *ioaddr = tp->mmio_addr;
1841 u32 status;
1842
1843 cmd->supported =
1844 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1845 cmd->port = PORT_FIBRE;
1846 cmd->transceiver = XCVR_INTERNAL;
1847
1848 status = RTL_R32(TBICSR);
1849 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1850 cmd->autoneg = !!(status & TBINwEnable);
1851
70739497 1852 ethtool_cmd_speed_set(cmd, SPEED_1000);
1da177e4 1853 cmd->duplex = DUPLEX_FULL; /* Always set */
ccdffb9a
FR		 1854
1855 return 0;
1da177e4
LT		 1856}
1857
ccdffb9a 1858static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1859{
1860 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a
FR		 1861
1862 return mii_ethtool_gset(&tp->mii, cmd);
1da177e4
LT		 1863}
1864
1865static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1866{
1867 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1868 int rc;
1da177e4 1869
da78dbff 1870 rtl_lock_work(tp);
ccdffb9a 1871 rc = tp->get_settings(dev, cmd);
da78dbff 1872 rtl_unlock_work(tp);
1da177e4 1873
ccdffb9a 1874 return rc;
1da177e4
LT		 1875}
1876
1877static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1878 void *p)
1879{
5b0384f4 1880 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 1881
5b0384f4
FR		 1882 if (regs->len > R8169_REGS_SIZE)
1883 regs->len = R8169_REGS_SIZE;
1da177e4 1884
da78dbff 1885 rtl_lock_work(tp);
5b0384f4 1886 memcpy_fromio(p, tp->mmio_addr, regs->len);
da78dbff 1887 rtl_unlock_work(tp);
1da177e4
LT		 1888}
1889
b57b7e5a
SH		 1890static u32 rtl8169_get_msglevel(struct net_device *dev)
1891{
1892 struct rtl8169_private *tp = netdev_priv(dev);
1893
1894 return tp->msg_enable;
1895}
1896
1897static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1898{
1899 struct rtl8169_private *tp = netdev_priv(dev);
1900
1901 tp->msg_enable = value;
1902}
1903
d4a3a0fc
SH		 1904static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1905 "tx_packets",
1906 "rx_packets",
1907 "tx_errors",
1908 "rx_errors",
1909 "rx_missed",
1910 "align_errors",
1911 "tx_single_collisions",
1912 "tx_multi_collisions",
1913 "unicast",
1914 "broadcast",
1915 "multicast",
1916 "tx_aborted",
1917 "tx_underrun",
1918};
1919
b9f2c044 1920static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1921{
b9f2c044
JG		 1922 switch (sset) {
1923 case ETH_SS_STATS:
1924 return ARRAY_SIZE(rtl8169_gstrings);
1925 default:
1926 return -EOPNOTSUPP;
1927 }
d4a3a0fc
SH		 1928}
1929
ffc46952
FR		 1930DECLARE_RTL_COND(rtl_counters_cond)
1931{
1932 void __iomem *ioaddr = tp->mmio_addr;
1933
1934 return RTL_R32(CounterAddrLow) & CounterDump;
1935}
1936
355423d0 1937static void rtl8169_update_counters(struct net_device *dev)
d4a3a0fc
SH		 1938{
1939 struct rtl8169_private *tp = netdev_priv(dev);
1940 void __iomem *ioaddr = tp->mmio_addr;
cecb5fd7 1941 struct device *d = &tp->pci_dev->dev;
d4a3a0fc
SH		 1942 struct rtl8169_counters *counters;
1943 dma_addr_t paddr;
1944 u32 cmd;
1945
355423d0
IV		 1946 /*
1947 * Some chips are unable to dump tally counters when the receiver
1948 * is disabled.
1949 */
1950 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1951 return;
d4a3a0fc 1952
48addcc9 1953 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
d4a3a0fc
SH		 1954 if (!counters)
1955 return;
1956
1957 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
284901a9 1958 cmd = (u64)paddr & DMA_BIT_MASK(32);
d4a3a0fc
SH		 1959 RTL_W32(CounterAddrLow, cmd);
1960 RTL_W32(CounterAddrLow, cmd | CounterDump);
1961
ffc46952
FR		 1962 if (rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000))
1963 memcpy(&tp->counters, counters, sizeof(*counters));
d4a3a0fc
SH		 1964
1965 RTL_W32(CounterAddrLow, 0);
1966 RTL_W32(CounterAddrHigh, 0);
1967
48addcc9 1968 dma_free_coherent(d, sizeof(*counters), counters, paddr);
d4a3a0fc
SH		 1969}
1970
355423d0
IV		 1971static void rtl8169_get_ethtool_stats(struct net_device *dev,
1972 struct ethtool_stats *stats, u64 *data)
1973{
1974 struct rtl8169_private *tp = netdev_priv(dev);
1975
1976 ASSERT_RTNL();
1977
1978 rtl8169_update_counters(dev);
1979
1980 data[0] = le64_to_cpu(tp->counters.tx_packets);
1981 data[1] = le64_to_cpu(tp->counters.rx_packets);
1982 data[2] = le64_to_cpu(tp->counters.tx_errors);
1983 data[3] = le32_to_cpu(tp->counters.rx_errors);
1984 data[4] = le16_to_cpu(tp->counters.rx_missed);
1985 data[5] = le16_to_cpu(tp->counters.align_errors);
1986 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1987 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1988 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1989 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1990 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1991 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1992 data[12] = le16_to_cpu(tp->counters.tx_underun);
1993}
1994
d4a3a0fc
SH		 1995static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1996{
1997 switch(stringset) {
1998 case ETH_SS_STATS:
1999 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
2000 break;
2001 }
2002}
2003
7282d491 2004static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 2005 .get_drvinfo = rtl8169_get_drvinfo,
2006 .get_regs_len = rtl8169_get_regs_len,
2007 .get_link = ethtool_op_get_link,
2008 .get_settings = rtl8169_get_settings,
2009 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 2010 .get_msglevel = rtl8169_get_msglevel,
2011 .set_msglevel = rtl8169_set_msglevel,
1da177e4 2012 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 2013 .get_wol = rtl8169_get_wol,
2014 .set_wol = rtl8169_set_wol,
d4a3a0fc 2015 .get_strings = rtl8169_get_strings,
b9f2c044 2016 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 2017 .get_ethtool_stats = rtl8169_get_ethtool_stats,
e1593bb1 2018 .get_ts_info = ethtool_op_get_ts_info,
1da177e4
LT		 2019};
2020
07d3f51f 2021static void rtl8169_get_mac_version(struct rtl8169_private *tp,
5d320a20 2022 struct net_device *dev, u8 default_version)
1da177e4 2023{
5d320a20 2024 void __iomem *ioaddr = tp->mmio_addr;
0e485150
FR		 2025 /*
2026 * The driver currently handles the 8168Bf and the 8168Be identically
2027 * but they can be identified more specifically through the test below
2028 * if needed:
2029 *
2030 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 2031 *
2032 * Same thing for the 8101Eb and the 8101Ec:
2033 *
2034 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 2035 */
3744100e 2036 static const struct rtl_mac_info {
1da177e4 2037 u32 mask;
e3cf0cc0 2038 u32 val;
1da177e4
LT		 2039 int mac_version;
2040 } mac_info[] = {
c558386b
HW		 2041 /* 8168G family. */
2042 { 0x7cf00000, 0x4c100000, RTL_GIGA_MAC_VER_41 },
2043 { 0x7cf00000, 0x4c000000, RTL_GIGA_MAC_VER_40 },
2044
c2218925 2045 /* 8168F family. */
b3d7b2f2 2046 { 0x7c800000, 0x48800000, RTL_GIGA_MAC_VER_38 },
c2218925
HW		 2047 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
2048 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
2049
01dc7fec 2050 /* 8168E family. */
70090424 2051 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
01dc7fec 2052 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
2053 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
2054 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
2055
5b538df9 2056 /* 8168D family. */
daf9df6d 2057 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
2058 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
daf9df6d 2059 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
5b538df9 2060
e6de30d6 2061 /* 8168DP family. */
2062 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
2063 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
4804b3b3 2064 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
e6de30d6 2065
ef808d50 2066 /* 8168C family. */
17c99297 2067 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
ef3386f0 2068 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 2069 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 2070 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 2071 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
2072 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 2073 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
6fb07058 2074 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
ef808d50 2075 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 2076
2077 /* 8168B family. */
2078 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
2079 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
2080 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
2081 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
2082
2083 /* 8101 family. */
5598bfe5
HW		 2084 { 0x7cf00000, 0x44900000, RTL_GIGA_MAC_VER_39 },
2085 { 0x7c800000, 0x44800000, RTL_GIGA_MAC_VER_39 },
7e18dca1 2086 { 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37 },
36a0e6c2 2087 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
5a5e4443
HW		 2088 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
2089 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
2090 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2857ffb7
FR		 2091 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
2092 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
2093 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
2094 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
2095 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
2096 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 2097 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 2098 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 2099 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 2100 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
2101 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 2102 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
2103 /* FIXME: where did these entries come from ? -- FR */
2104 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
2105 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
2106
2107 /* 8110 family. */
2108 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
2109 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
2110 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
2111 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
2112 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
2113 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
2114
f21b75e9
JD		 2115 /* Catch-all */
2116 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
3744100e
FR		 2117 };
2118 const struct rtl_mac_info *p = mac_info;
1da177e4
LT		 2119 u32 reg;
2120
e3cf0cc0
FR		 2121 reg = RTL_R32(TxConfig);
2122 while ((reg & p->mask) != p->val)
1da177e4
LT		 2123 p++;
2124 tp->mac_version = p->mac_version;
5d320a20
FR		 2125
2126 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2127 netif_notice(tp, probe, dev,
2128 "unknown MAC, using family default\n");
2129 tp->mac_version = default_version;
2130 }
1da177e4
LT		 2131}
2132
2133static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2134{
bcf0bf90 2135 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 2136}
2137
867763c1
FR		 2138struct phy_reg {
2139 u16 reg;
2140 u16 val;
2141};
2142
4da19633 2143static void rtl_writephy_batch(struct rtl8169_private *tp,
2144 const struct phy_reg *regs, int len)
867763c1
FR		 2145{
2146 while (len-- > 0) {
4da19633 2147 rtl_writephy(tp, regs->reg, regs->val);
867763c1
FR		 2148 regs++;
2149 }
2150}
2151
bca03d5f 2152#define PHY_READ 0x00000000
2153#define PHY_DATA_OR 0x10000000
2154#define PHY_DATA_AND 0x20000000
2155#define PHY_BJMPN 0x30000000
2156#define PHY_READ_EFUSE 0x40000000
2157#define PHY_READ_MAC_BYTE 0x50000000
2158#define PHY_WRITE_MAC_BYTE 0x60000000
2159#define PHY_CLEAR_READCOUNT 0x70000000
2160#define PHY_WRITE 0x80000000
2161#define PHY_READCOUNT_EQ_SKIP 0x90000000
2162#define PHY_COMP_EQ_SKIPN 0xa0000000
2163#define PHY_COMP_NEQ_SKIPN 0xb0000000
2164#define PHY_WRITE_PREVIOUS 0xc0000000
2165#define PHY_SKIPN 0xd0000000
2166#define PHY_DELAY_MS 0xe0000000
2167#define PHY_WRITE_ERI_WORD 0xf0000000
2168
960aee6c
HW		 2169struct fw_info {
2170 u32 magic;
2171 char version[RTL_VER_SIZE];
2172 __le32 fw_start;
2173 __le32 fw_len;
2174 u8 chksum;
2175} __packed;
2176
1c361efb
FR		 2177#define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2178
2179static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
bca03d5f 2180{
b6ffd97f 2181 const struct firmware *fw = rtl_fw->fw;
960aee6c 2182 struct fw_info *fw_info = (struct fw_info *)fw->data;
1c361efb
FR		 2183 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2184 char *version = rtl_fw->version;
2185 bool rc = false;
2186
2187 if (fw->size < FW_OPCODE_SIZE)
2188 goto out;
960aee6c
HW		 2189
2190 if (!fw_info->magic) {
2191 size_t i, size, start;
2192 u8 checksum = 0;
2193
2194 if (fw->size < sizeof(*fw_info))
2195 goto out;
2196
2197 for (i = 0; i < fw->size; i++)
2198 checksum += fw->data[i];
2199 if (checksum != 0)
2200 goto out;
2201
2202 start = le32_to_cpu(fw_info->fw_start);
2203 if (start > fw->size)
2204 goto out;
2205
2206 size = le32_to_cpu(fw_info->fw_len);
2207 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2208 goto out;
2209
2210 memcpy(version, fw_info->version, RTL_VER_SIZE);
2211
2212 pa->code = (__le32 *)(fw->data + start);
2213 pa->size = size;
2214 } else {
1c361efb
FR		 2215 if (fw->size % FW_OPCODE_SIZE)
2216 goto out;
2217
2218 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2219
2220 pa->code = (__le32 *)fw->data;
2221 pa->size = fw->size / FW_OPCODE_SIZE;
2222 }
2223 version[RTL_VER_SIZE - 1] = 0;
2224
2225 rc = true;
2226out:
2227 return rc;
2228}
2229
fd112f2e
FR		 2230static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2231 struct rtl_fw_phy_action *pa)
1c361efb 2232{
fd112f2e 2233 bool rc = false;
1c361efb 2234 size_t index;
bca03d5f 2235
1c361efb
FR		 2236 for (index = 0; index < pa->size; index++) {
2237 u32 action = le32_to_cpu(pa->code[index]);
42b82dc1 2238 u32 regno = (action & 0x0fff0000) >> 16;
bca03d5f 2239
42b82dc1 2240 switch(action & 0xf0000000) {
2241 case PHY_READ:
2242 case PHY_DATA_OR:
2243 case PHY_DATA_AND:
2244 case PHY_READ_EFUSE:
2245 case PHY_CLEAR_READCOUNT:
2246 case PHY_WRITE:
2247 case PHY_WRITE_PREVIOUS:
2248 case PHY_DELAY_MS:
2249 break;
2250
2251 case PHY_BJMPN:
2252 if (regno > index) {
fd112f2e 2253 netif_err(tp, ifup, tp->dev,
cecb5fd7 2254 "Out of range of firmware\n");
fd112f2e 2255 goto out;
42b82dc1 2256 }
2257 break;
2258 case PHY_READCOUNT_EQ_SKIP:
1c361efb 2259 if (index + 2 >= pa->size) {
fd112f2e 2260 netif_err(tp, ifup, tp->dev,
cecb5fd7 2261 "Out of range of firmware\n");
fd112f2e 2262 goto out;
42b82dc1 2263 }
2264 break;
2265 case PHY_COMP_EQ_SKIPN:
2266 case PHY_COMP_NEQ_SKIPN:
2267 case PHY_SKIPN:
1c361efb 2268 if (index + 1 + regno >= pa->size) {
fd112f2e 2269 netif_err(tp, ifup, tp->dev,
cecb5fd7 2270 "Out of range of firmware\n");
fd112f2e 2271 goto out;
42b82dc1 2272 }
bca03d5f 2273 break;
2274
42b82dc1 2275 case PHY_READ_MAC_BYTE:
2276 case PHY_WRITE_MAC_BYTE:
2277 case PHY_WRITE_ERI_WORD:
2278 default:
fd112f2e 2279 netif_err(tp, ifup, tp->dev,
42b82dc1 2280 "Invalid action 0x%08x\n", action);
fd112f2e 2281 goto out;
bca03d5f 2282 }
2283 }
fd112f2e
FR		 2284 rc = true;
2285out:
2286 return rc;
2287}
bca03d5f 2288
fd112f2e
FR		 2289static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2290{
2291 struct net_device *dev = tp->dev;
2292 int rc = -EINVAL;
2293
2294 if (!rtl_fw_format_ok(tp, rtl_fw)) {
2295 netif_err(tp, ifup, dev, "invalid firwmare\n");
2296 goto out;
2297 }
2298
2299 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2300 rc = 0;
2301out:
2302 return rc;
2303}
2304
2305static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2306{
2307 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2308 u32 predata, count;
2309 size_t index;
2310
2311 predata = count = 0;
42b82dc1 2312
1c361efb
FR		 2313 for (index = 0; index < pa->size; ) {
2314 u32 action = le32_to_cpu(pa->code[index]);
bca03d5f 2315 u32 data = action & 0x0000ffff;
42b82dc1 2316 u32 regno = (action & 0x0fff0000) >> 16;
2317
2318 if (!action)
2319 break;
bca03d5f 2320
2321 switch(action & 0xf0000000) {
42b82dc1 2322 case PHY_READ:
2323 predata = rtl_readphy(tp, regno);
2324 count++;
2325 index++;
2326 break;
2327 case PHY_DATA_OR:
2328 predata |= data;
2329 index++;
2330 break;
2331 case PHY_DATA_AND:
2332 predata &= data;
2333 index++;
2334 break;
2335 case PHY_BJMPN:
2336 index -= regno;
2337 break;
2338 case PHY_READ_EFUSE:
fdf6fc06 2339 predata = rtl8168d_efuse_read(tp, regno);
42b82dc1 2340 index++;
2341 break;
2342 case PHY_CLEAR_READCOUNT:
2343 count = 0;
2344 index++;
2345 break;
bca03d5f 2346 case PHY_WRITE:
42b82dc1 2347 rtl_writephy(tp, regno, data);
2348 index++;
2349 break;
2350 case PHY_READCOUNT_EQ_SKIP:
cecb5fd7 2351 index += (count == data) ? 2 : 1;
bca03d5f 2352 break;
42b82dc1 2353 case PHY_COMP_EQ_SKIPN:
2354 if (predata == data)
2355 index += regno;
2356 index++;
2357 break;
2358 case PHY_COMP_NEQ_SKIPN:
2359 if (predata != data)
2360 index += regno;
2361 index++;
2362 break;
2363 case PHY_WRITE_PREVIOUS:
2364 rtl_writephy(tp, regno, predata);
2365 index++;
2366 break;
2367 case PHY_SKIPN:
2368 index += regno + 1;
2369 break;
2370 case PHY_DELAY_MS:
2371 mdelay(data);
2372 index++;
2373 break;
2374
2375 case PHY_READ_MAC_BYTE:
2376 case PHY_WRITE_MAC_BYTE:
2377 case PHY_WRITE_ERI_WORD:
bca03d5f 2378 default:
2379 BUG();
2380 }
2381 }
2382}
2383
f1e02ed1 2384static void rtl_release_firmware(struct rtl8169_private *tp)
2385{
b6ffd97f
FR		 2386 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2387 release_firmware(tp->rtl_fw->fw);
2388 kfree(tp->rtl_fw);
2389 }
2390 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
f1e02ed1 2391}
2392
953a12cc 2393static void rtl_apply_firmware(struct rtl8169_private *tp)
f1e02ed1 2394{
b6ffd97f 2395 struct rtl_fw *rtl_fw = tp->rtl_fw;
f1e02ed1 2396
2397 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
e0c07557 2398 if (!IS_ERR_OR_NULL(rtl_fw)) {
b6ffd97f 2399 rtl_phy_write_fw(tp, rtl_fw);
e0c07557 2400 tp->features |= RTL_FEATURE_FW_LOADED;
2401 }
953a12cc
FR		 2402}
2403
2404static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2405{
2406 if (rtl_readphy(tp, reg) != val)
2407 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2408 else
2409 rtl_apply_firmware(tp);
f1e02ed1 2410}
2411
e0c07557 2412static void r810x_aldps_disable(struct rtl8169_private *tp)
2413{
2414 rtl_writephy(tp, 0x1f, 0x0000);
2415 rtl_writephy(tp, 0x18, 0x0310);
2416 msleep(100);
2417}
2418
2419static void r810x_aldps_enable(struct rtl8169_private *tp)
2420{
2421 if (!(tp->features & RTL_FEATURE_FW_LOADED))
2422 return;
2423
2424 rtl_writephy(tp, 0x1f, 0x0000);
2425 rtl_writephy(tp, 0x18, 0x8310);
2426}
2427
2428static void r8168_aldps_enable_1(struct rtl8169_private *tp)
2429{
2430 if (!(tp->features & RTL_FEATURE_FW_LOADED))
2431 return;
2432
2433 rtl_writephy(tp, 0x1f, 0x0000);
2434 rtl_w1w0_phy(tp, 0x15, 0x1000, 0x0000);
2435}
2436
4da19633 2437static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1da177e4 2438{
350f7596 2439 static const struct phy_reg phy_reg_init[] = {
0b9b571d 2440 { 0x1f, 0x0001 },
2441 { 0x06, 0x006e },
2442 { 0x08, 0x0708 },
2443 { 0x15, 0x4000 },
2444 { 0x18, 0x65c7 },
1da177e4 2445
0b9b571d 2446 { 0x1f, 0x0001 },
2447 { 0x03, 0x00a1 },
2448 { 0x02, 0x0008 },
2449 { 0x01, 0x0120 },
2450 { 0x00, 0x1000 },
2451 { 0x04, 0x0800 },
2452 { 0x04, 0x0000 },
1da177e4 2453
0b9b571d 2454 { 0x03, 0xff41 },
2455 { 0x02, 0xdf60 },
2456 { 0x01, 0x0140 },
2457 { 0x00, 0x0077 },
2458 { 0x04, 0x7800 },
2459 { 0x04, 0x7000 },
2460
2461 { 0x03, 0x802f },
2462 { 0x02, 0x4f02 },
2463 { 0x01, 0x0409 },
2464 { 0x00, 0xf0f9 },
2465 { 0x04, 0x9800 },
2466 { 0x04, 0x9000 },
2467
2468 { 0x03, 0xdf01 },
2469 { 0x02, 0xdf20 },
2470 { 0x01, 0xff95 },
2471 { 0x00, 0xba00 },
2472 { 0x04, 0xa800 },
2473 { 0x04, 0xa000 },
2474
2475 { 0x03, 0xff41 },
2476 { 0x02, 0xdf20 },
2477 { 0x01, 0x0140 },
2478 { 0x00, 0x00bb },
2479 { 0x04, 0xb800 },
2480 { 0x04, 0xb000 },
2481
2482 { 0x03, 0xdf41 },
2483 { 0x02, 0xdc60 },
2484 { 0x01, 0x6340 },
2485 { 0x00, 0x007d },
2486 { 0x04, 0xd800 },
2487 { 0x04, 0xd000 },
2488
2489 { 0x03, 0xdf01 },
2490 { 0x02, 0xdf20 },
2491 { 0x01, 0x100a },
2492 { 0x00, 0xa0ff },
2493 { 0x04, 0xf800 },
2494 { 0x04, 0xf000 },
2495
2496 { 0x1f, 0x0000 },
2497 { 0x0b, 0x0000 },
2498 { 0x00, 0x9200 }
2499 };
1da177e4 2500
4da19633 2501 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1da177e4
LT		 2502}
2503
4da19633 2504static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
5615d9f1 2505{
350f7596 2506 static const struct phy_reg phy_reg_init[] = {
a441d7b6
FR		 2507 { 0x1f, 0x0002 },
2508 { 0x01, 0x90d0 },
2509 { 0x1f, 0x0000 }
2510 };
2511
4da19633 2512 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 2513}
2514
4da19633 2515static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2e955856 2516{
2517 struct pci_dev *pdev = tp->pci_dev;
2e955856 2518
ccbae55e
SS		 2519 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2520 (pdev->subsystem_device != 0xe000))
2e955856 2521 return;
2522
4da19633 2523 rtl_writephy(tp, 0x1f, 0x0001);
2524 rtl_writephy(tp, 0x10, 0xf01b);
2525 rtl_writephy(tp, 0x1f, 0x0000);
2e955856 2526}
2527
4da19633 2528static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2e955856 2529{
350f7596 2530 static const struct phy_reg phy_reg_init[] = {
2e955856 2531 { 0x1f, 0x0001 },
2532 { 0x04, 0x0000 },
2533 { 0x03, 0x00a1 },
2534 { 0x02, 0x0008 },
2535 { 0x01, 0x0120 },
2536 { 0x00, 0x1000 },
2537 { 0x04, 0x0800 },
2538 { 0x04, 0x9000 },
2539 { 0x03, 0x802f },
2540 { 0x02, 0x4f02 },
2541 { 0x01, 0x0409 },
2542 { 0x00, 0xf099 },
2543 { 0x04, 0x9800 },
2544 { 0x04, 0xa000 },
2545 { 0x03, 0xdf01 },
2546 { 0x02, 0xdf20 },
2547 { 0x01, 0xff95 },
2548 { 0x00, 0xba00 },
2549 { 0x04, 0xa800 },
2550 { 0x04, 0xf000 },
2551 { 0x03, 0xdf01 },
2552 { 0x02, 0xdf20 },
2553 { 0x01, 0x101a },
2554 { 0x00, 0xa0ff },
2555 { 0x04, 0xf800 },
2556 { 0x04, 0x0000 },
2557 { 0x1f, 0x0000 },
2558
2559 { 0x1f, 0x0001 },
2560 { 0x10, 0xf41b },
2561 { 0x14, 0xfb54 },
2562 { 0x18, 0xf5c7 },
2563 { 0x1f, 0x0000 },
2564
2565 { 0x1f, 0x0001 },
2566 { 0x17, 0x0cc0 },
2567 { 0x1f, 0x0000 }
2568 };
2569
4da19633 2570 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2e955856 2571
4da19633 2572 rtl8169scd_hw_phy_config_quirk(tp);
2e955856 2573}
2574
4da19633 2575static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
8c7006aa 2576{
350f7596 2577 static const struct phy_reg phy_reg_init[] = {
8c7006aa 2578 { 0x1f, 0x0001 },
2579 { 0x04, 0x0000 },
2580 { 0x03, 0x00a1 },
2581 { 0x02, 0x0008 },
2582 { 0x01, 0x0120 },
2583 { 0x00, 0x1000 },
2584 { 0x04, 0x0800 },
2585 { 0x04, 0x9000 },
2586 { 0x03, 0x802f },
2587 { 0x02, 0x4f02 },
2588 { 0x01, 0x0409 },
2589 { 0x00, 0xf099 },
2590 { 0x04, 0x9800 },
2591 { 0x04, 0xa000 },
2592 { 0x03, 0xdf01 },
2593 { 0x02, 0xdf20 },
2594 { 0x01, 0xff95 },
2595 { 0x00, 0xba00 },
2596 { 0x04, 0xa800 },
2597 { 0x04, 0xf000 },
2598 { 0x03, 0xdf01 },
2599 { 0x02, 0xdf20 },
2600 { 0x01, 0x101a },
2601 { 0x00, 0xa0ff },
2602 { 0x04, 0xf800 },
2603 { 0x04, 0x0000 },
2604 { 0x1f, 0x0000 },
2605
2606 { 0x1f, 0x0001 },
2607 { 0x0b, 0x8480 },
2608 { 0x1f, 0x0000 },
2609
2610 { 0x1f, 0x0001 },
2611 { 0x18, 0x67c7 },
2612 { 0x04, 0x2000 },
2613 { 0x03, 0x002f },
2614 { 0x02, 0x4360 },
2615 { 0x01, 0x0109 },
2616 { 0x00, 0x3022 },
2617 { 0x04, 0x2800 },
2618 { 0x1f, 0x0000 },
2619
2620 { 0x1f, 0x0001 },
2621 { 0x17, 0x0cc0 },
2622 { 0x1f, 0x0000 }
2623 };
2624
4da19633 2625 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
8c7006aa 2626}
2627
4da19633 2628static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
236b8082 2629{
350f7596 2630 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2631 { 0x10, 0xf41b },
2632 { 0x1f, 0x0000 }
2633 };
2634
4da19633 2635 rtl_writephy(tp, 0x1f, 0x0001);
2636 rtl_patchphy(tp, 0x16, 1 << 0);
236b8082 2637
4da19633 2638 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2639}
2640
4da19633 2641static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
236b8082 2642{
350f7596 2643 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2644 { 0x1f, 0x0001 },
2645 { 0x10, 0xf41b },
2646 { 0x1f, 0x0000 }
2647 };
2648
4da19633 2649 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2650}
2651
4da19633 2652static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2653{
350f7596 2654 static const struct phy_reg phy_reg_init[] = {
867763c1
FR		 2655 { 0x1f, 0x0000 },
2656 { 0x1d, 0x0f00 },
2657 { 0x1f, 0x0002 },
2658 { 0x0c, 0x1ec8 },
2659 { 0x1f, 0x0000 }
2660 };
2661
4da19633 2662 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
867763c1
FR		 2663}
2664
4da19633 2665static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
ef3386f0 2666{
350f7596 2667 static const struct phy_reg phy_reg_init[] = {
ef3386f0
FR		 2668 { 0x1f, 0x0001 },
2669 { 0x1d, 0x3d98 },
2670 { 0x1f, 0x0000 }
2671 };
2672
4da19633 2673 rtl_writephy(tp, 0x1f, 0x0000);
2674 rtl_patchphy(tp, 0x14, 1 << 5);
2675 rtl_patchphy(tp, 0x0d, 1 << 5);
ef3386f0 2676
4da19633 2677 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
ef3386f0
FR		 2678}
2679
4da19633 2680static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2681{
350f7596 2682 static const struct phy_reg phy_reg_init[] = {
a3f80671
FR		 2683 { 0x1f, 0x0001 },
2684 { 0x12, 0x2300 },
867763c1
FR		 2685 { 0x1f, 0x0002 },
2686 { 0x00, 0x88d4 },
2687 { 0x01, 0x82b1 },
2688 { 0x03, 0x7002 },
2689 { 0x08, 0x9e30 },
2690 { 0x09, 0x01f0 },
2691 { 0x0a, 0x5500 },
2692 { 0x0c, 0x00c8 },
2693 { 0x1f, 0x0003 },
2694 { 0x12, 0xc096 },
2695 { 0x16, 0x000a },
f50d4275
FR		 2696 { 0x1f, 0x0000 },
2697 { 0x1f, 0x0000 },
2698 { 0x09, 0x2000 },
2699 { 0x09, 0x0000 }
867763c1
FR		 2700 };
2701
4da19633 2702 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2703
4da19633 2704 rtl_patchphy(tp, 0x14, 1 << 5);
2705 rtl_patchphy(tp, 0x0d, 1 << 5);
2706 rtl_writephy(tp, 0x1f, 0x0000);
867763c1
FR		 2707}
2708
4da19633 2709static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
7da97ec9 2710{
350f7596 2711 static const struct phy_reg phy_reg_init[] = {
f50d4275 2712 { 0x1f, 0x0001 },
7da97ec9 2713 { 0x12, 0x2300 },
f50d4275
FR		 2714 { 0x03, 0x802f },
2715 { 0x02, 0x4f02 },
2716 { 0x01, 0x0409 },
2717 { 0x00, 0xf099 },
2718 { 0x04, 0x9800 },
2719 { 0x04, 0x9000 },
2720 { 0x1d, 0x3d98 },
7da97ec9
FR		 2721 { 0x1f, 0x0002 },
2722 { 0x0c, 0x7eb8 },
f50d4275
FR		 2723 { 0x06, 0x0761 },
2724 { 0x1f, 0x0003 },
2725 { 0x16, 0x0f0a },
7da97ec9
FR		 2726 { 0x1f, 0x0000 }
2727 };
2728
4da19633 2729 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2730
4da19633 2731 rtl_patchphy(tp, 0x16, 1 << 0);
2732 rtl_patchphy(tp, 0x14, 1 << 5);
2733 rtl_patchphy(tp, 0x0d, 1 << 5);
2734 rtl_writephy(tp, 0x1f, 0x0000);
7da97ec9
FR		 2735}
2736
4da19633 2737static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
197ff761 2738{
350f7596 2739 static const struct phy_reg phy_reg_init[] = {
197ff761
FR		 2740 { 0x1f, 0x0001 },
2741 { 0x12, 0x2300 },
2742 { 0x1d, 0x3d98 },
2743 { 0x1f, 0x0002 },
2744 { 0x0c, 0x7eb8 },
2745 { 0x06, 0x5461 },
2746 { 0x1f, 0x0003 },
2747 { 0x16, 0x0f0a },
2748 { 0x1f, 0x0000 }
2749 };
2750
4da19633 2751 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
197ff761 2752
4da19633 2753 rtl_patchphy(tp, 0x16, 1 << 0);
2754 rtl_patchphy(tp, 0x14, 1 << 5);
2755 rtl_patchphy(tp, 0x0d, 1 << 5);
2756 rtl_writephy(tp, 0x1f, 0x0000);
197ff761
FR		 2757}
2758
4da19633 2759static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
6fb07058 2760{
4da19633 2761 rtl8168c_3_hw_phy_config(tp);
6fb07058
FR		 2762}
2763
bca03d5f 2764static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
5b538df9 2765{
350f7596 2766 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2767 /* Channel Estimation */
5b538df9 2768 { 0x1f, 0x0001 },
daf9df6d 2769 { 0x06, 0x4064 },
2770 { 0x07, 0x2863 },
2771 { 0x08, 0x059c },
2772 { 0x09, 0x26b4 },
2773 { 0x0a, 0x6a19 },
2774 { 0x0b, 0xdcc8 },
2775 { 0x10, 0xf06d },
2776 { 0x14, 0x7f68 },
2777 { 0x18, 0x7fd9 },
2778 { 0x1c, 0xf0ff },
2779 { 0x1d, 0x3d9c },
5b538df9 2780 { 0x1f, 0x0003 },
daf9df6d 2781 { 0x12, 0xf49f },
2782 { 0x13, 0x070b },
2783 { 0x1a, 0x05ad },
bca03d5f 2784 { 0x14, 0x94c0 },
2785
2786 /*
2787 * Tx Error Issue
cecb5fd7 2788 * Enhance line driver power
bca03d5f 2789 */
5b538df9 2790 { 0x1f, 0x0002 },
daf9df6d 2791 { 0x06, 0x5561 },
2792 { 0x1f, 0x0005 },
2793 { 0x05, 0x8332 },
bca03d5f 2794 { 0x06, 0x5561 },
2795
2796 /*
2797 * Can not link to 1Gbps with bad cable
2798 * Decrease SNR threshold form 21.07dB to 19.04dB
2799 */
2800 { 0x1f, 0x0001 },
2801 { 0x17, 0x0cc0 },
daf9df6d 2802
5b538df9 2803 { 0x1f, 0x0000 },
bca03d5f 2804 { 0x0d, 0xf880 }
daf9df6d 2805 };
2806
4da19633 2807 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
daf9df6d 2808
bca03d5f 2809 /*
2810 * Rx Error Issue
2811 * Fine Tune Switching regulator parameter
2812 */
4da19633 2813 rtl_writephy(tp, 0x1f, 0x0002);
2814 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2815 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
daf9df6d 2816
fdf6fc06 2817 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
350f7596 2818 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2819 { 0x1f, 0x0002 },
2820 { 0x05, 0x669a },
2821 { 0x1f, 0x0005 },
2822 { 0x05, 0x8330 },
2823 { 0x06, 0x669a },
2824 { 0x1f, 0x0002 }
2825 };
2826 int val;
2827
4da19633 2828 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2829
4da19633 2830 val = rtl_readphy(tp, 0x0d);
daf9df6d 2831
2832 if ((val & 0x00ff) != 0x006c) {
350f7596 2833 static const u32 set[] = {
daf9df6d 2834 0x0065, 0x0066, 0x0067, 0x0068,
2835 0x0069, 0x006a, 0x006b, 0x006c
2836 };
2837 int i;
2838
4da19633 2839 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2840
2841 val &= 0xff00;
2842 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2843 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2844 }
2845 } else {
350f7596 2846 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2847 { 0x1f, 0x0002 },
2848 { 0x05, 0x6662 },
2849 { 0x1f, 0x0005 },
2850 { 0x05, 0x8330 },
2851 { 0x06, 0x6662 }
2852 };
2853
4da19633 2854 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2855 }
2856
bca03d5f 2857 /* RSET couple improve */
4da19633 2858 rtl_writephy(tp, 0x1f, 0x0002);
2859 rtl_patchphy(tp, 0x0d, 0x0300);
2860 rtl_patchphy(tp, 0x0f, 0x0010);
daf9df6d 2861
bca03d5f 2862 /* Fine tune PLL performance */
4da19633 2863 rtl_writephy(tp, 0x1f, 0x0002);
2864 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2865 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2866
4da19633 2867 rtl_writephy(tp, 0x1f, 0x0005);
2868 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2869
2870 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
bca03d5f 2871
4da19633 2872 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2873}
2874
bca03d5f 2875static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2876{
350f7596 2877 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2878 /* Channel Estimation */
daf9df6d 2879 { 0x1f, 0x0001 },
2880 { 0x06, 0x4064 },
2881 { 0x07, 0x2863 },
2882 { 0x08, 0x059c },
2883 { 0x09, 0x26b4 },
2884 { 0x0a, 0x6a19 },
2885 { 0x0b, 0xdcc8 },
2886 { 0x10, 0xf06d },
2887 { 0x14, 0x7f68 },
2888 { 0x18, 0x7fd9 },
2889 { 0x1c, 0xf0ff },
2890 { 0x1d, 0x3d9c },
2891 { 0x1f, 0x0003 },
2892 { 0x12, 0xf49f },
2893 { 0x13, 0x070b },
2894 { 0x1a, 0x05ad },
2895 { 0x14, 0x94c0 },
2896
bca03d5f 2897 /*
2898 * Tx Error Issue
cecb5fd7 2899 * Enhance line driver power
bca03d5f 2900 */
daf9df6d 2901 { 0x1f, 0x0002 },
2902 { 0x06, 0x5561 },
2903 { 0x1f, 0x0005 },
2904 { 0x05, 0x8332 },
bca03d5f 2905 { 0x06, 0x5561 },
2906
2907 /*
2908 * Can not link to 1Gbps with bad cable
2909 * Decrease SNR threshold form 21.07dB to 19.04dB
2910 */
2911 { 0x1f, 0x0001 },
2912 { 0x17, 0x0cc0 },
daf9df6d 2913
2914 { 0x1f, 0x0000 },
bca03d5f 2915 { 0x0d, 0xf880 }
5b538df9
FR		 2916 };
2917
4da19633 2918 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
5b538df9 2919
fdf6fc06 2920 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
350f7596 2921 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2922 { 0x1f, 0x0002 },
2923 { 0x05, 0x669a },
5b538df9 2924 { 0x1f, 0x0005 },
daf9df6d 2925 { 0x05, 0x8330 },
2926 { 0x06, 0x669a },
2927
2928 { 0x1f, 0x0002 }
2929 };
2930 int val;
2931
4da19633 2932 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2933
4da19633 2934 val = rtl_readphy(tp, 0x0d);
daf9df6d 2935 if ((val & 0x00ff) != 0x006c) {
b6bc7650 2936 static const u32 set[] = {
daf9df6d 2937 0x0065, 0x0066, 0x0067, 0x0068,
2938 0x0069, 0x006a, 0x006b, 0x006c
2939 };
2940 int i;
2941
4da19633 2942 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2943
2944 val &= 0xff00;
2945 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2946 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2947 }
2948 } else {
350f7596 2949 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2950 { 0x1f, 0x0002 },
2951 { 0x05, 0x2642 },
5b538df9 2952 { 0x1f, 0x0005 },
daf9df6d 2953 { 0x05, 0x8330 },
2954 { 0x06, 0x2642 }
5b538df9
FR		 2955 };
2956
4da19633 2957 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2958 }
2959
bca03d5f 2960 /* Fine tune PLL performance */
4da19633 2961 rtl_writephy(tp, 0x1f, 0x0002);
2962 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2963 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2964
bca03d5f 2965 /* Switching regulator Slew rate */
4da19633 2966 rtl_writephy(tp, 0x1f, 0x0002);
2967 rtl_patchphy(tp, 0x0f, 0x0017);
daf9df6d 2968
4da19633 2969 rtl_writephy(tp, 0x1f, 0x0005);
2970 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2971
2972 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
bca03d5f 2973
4da19633 2974 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2975}
2976
4da19633 2977static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2978{
350f7596 2979 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2980 { 0x1f, 0x0002 },
2981 { 0x10, 0x0008 },
2982 { 0x0d, 0x006c },
2983
2984 { 0x1f, 0x0000 },
2985 { 0x0d, 0xf880 },
2986
2987 { 0x1f, 0x0001 },
2988 { 0x17, 0x0cc0 },
2989
2990 { 0x1f, 0x0001 },
2991 { 0x0b, 0xa4d8 },
2992 { 0x09, 0x281c },
2993 { 0x07, 0x2883 },
2994 { 0x0a, 0x6b35 },
2995 { 0x1d, 0x3da4 },
2996 { 0x1c, 0xeffd },
2997 { 0x14, 0x7f52 },
2998 { 0x18, 0x7fc6 },
2999 { 0x08, 0x0601 },
3000 { 0x06, 0x4063 },
3001 { 0x10, 0xf074 },
3002 { 0x1f, 0x0003 },
3003 { 0x13, 0x0789 },
3004 { 0x12, 0xf4bd },
3005 { 0x1a, 0x04fd },
3006 { 0x14, 0x84b0 },
3007 { 0x1f, 0x0000 },
3008 { 0x00, 0x9200 },
3009
3010 { 0x1f, 0x0005 },
3011 { 0x01, 0x0340 },
3012 { 0x1f, 0x0001 },
3013 { 0x04, 0x4000 },
3014 { 0x03, 0x1d21 },
3015 { 0x02, 0x0c32 },
3016 { 0x01, 0x0200 },
3017 { 0x00, 0x5554 },
3018 { 0x04, 0x4800 },
3019 { 0x04, 0x4000 },
3020 { 0x04, 0xf000 },
3021 { 0x03, 0xdf01 },
3022 { 0x02, 0xdf20 },
3023 { 0x01, 0x101a },
3024 { 0x00, 0xa0ff },
3025 { 0x04, 0xf800 },
3026 { 0x04, 0xf000 },
3027 { 0x1f, 0x0000 },
3028
3029 { 0x1f, 0x0007 },
3030 { 0x1e, 0x0023 },
3031 { 0x16, 0x0000 },
3032 { 0x1f, 0x0000 }
3033 };
3034
4da19633 3035 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 3036}
3037
e6de30d6 3038static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3039{
3040 static const struct phy_reg phy_reg_init[] = {
3041 { 0x1f, 0x0001 },
3042 { 0x17, 0x0cc0 },
3043
3044 { 0x1f, 0x0007 },
3045 { 0x1e, 0x002d },
3046 { 0x18, 0x0040 },
3047 { 0x1f, 0x0000 }
3048 };
3049
3050 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3051 rtl_patchphy(tp, 0x0d, 1 << 5);
3052}
3053
70090424 3054static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
01dc7fec 3055{
3056 static const struct phy_reg phy_reg_init[] = {
3057 /* Enable Delay cap */
3058 { 0x1f, 0x0005 },
3059 { 0x05, 0x8b80 },
3060 { 0x06, 0xc896 },
3061 { 0x1f, 0x0000 },
3062
3063 /* Channel estimation fine tune */
3064 { 0x1f, 0x0001 },
3065 { 0x0b, 0x6c20 },
3066 { 0x07, 0x2872 },
3067 { 0x1c, 0xefff },
3068 { 0x1f, 0x0003 },
3069 { 0x14, 0x6420 },
3070 { 0x1f, 0x0000 },
3071
3072 /* Update PFM & 10M TX idle timer */
3073 { 0x1f, 0x0007 },
3074 { 0x1e, 0x002f },
3075 { 0x15, 0x1919 },
3076 { 0x1f, 0x0000 },
3077
3078 { 0x1f, 0x0007 },
3079 { 0x1e, 0x00ac },
3080 { 0x18, 0x0006 },
3081 { 0x1f, 0x0000 }
3082 };
3083
15ecd039
FR		 3084 rtl_apply_firmware(tp);
3085
01dc7fec 3086 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3087
3088 /* DCO enable for 10M IDLE Power */
3089 rtl_writephy(tp, 0x1f, 0x0007);
3090 rtl_writephy(tp, 0x1e, 0x0023);
3091 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
3092 rtl_writephy(tp, 0x1f, 0x0000);
3093
3094 /* For impedance matching */
3095 rtl_writephy(tp, 0x1f, 0x0002);
3096 rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
cecb5fd7 3097 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3098
3099 /* PHY auto speed down */
3100 rtl_writephy(tp, 0x1f, 0x0007);
3101 rtl_writephy(tp, 0x1e, 0x002d);
3102 rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
3103 rtl_writephy(tp, 0x1f, 0x0000);
3104 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3105
3106 rtl_writephy(tp, 0x1f, 0x0005);
3107 rtl_writephy(tp, 0x05, 0x8b86);
3108 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3109 rtl_writephy(tp, 0x1f, 0x0000);
3110
3111 rtl_writephy(tp, 0x1f, 0x0005);
3112 rtl_writephy(tp, 0x05, 0x8b85);
3113 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3114 rtl_writephy(tp, 0x1f, 0x0007);
3115 rtl_writephy(tp, 0x1e, 0x0020);
3116 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
3117 rtl_writephy(tp, 0x1f, 0x0006);
3118 rtl_writephy(tp, 0x00, 0x5a00);
3119 rtl_writephy(tp, 0x1f, 0x0000);
3120 rtl_writephy(tp, 0x0d, 0x0007);
3121 rtl_writephy(tp, 0x0e, 0x003c);
3122 rtl_writephy(tp, 0x0d, 0x4007);
3123 rtl_writephy(tp, 0x0e, 0x0000);
3124 rtl_writephy(tp, 0x0d, 0x0000);
3125}
3126
70090424
HW		 3127static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3128{
3129 static const struct phy_reg phy_reg_init[] = {
3130 /* Enable Delay cap */
3131 { 0x1f, 0x0004 },
3132 { 0x1f, 0x0007 },
3133 { 0x1e, 0x00ac },
3134 { 0x18, 0x0006 },
3135 { 0x1f, 0x0002 },
3136 { 0x1f, 0x0000 },
3137 { 0x1f, 0x0000 },
3138
3139 /* Channel estimation fine tune */
3140 { 0x1f, 0x0003 },
3141 { 0x09, 0xa20f },
3142 { 0x1f, 0x0000 },
3143 { 0x1f, 0x0000 },
3144
3145 /* Green Setting */
3146 { 0x1f, 0x0005 },
3147 { 0x05, 0x8b5b },
3148 { 0x06, 0x9222 },
3149 { 0x05, 0x8b6d },
3150 { 0x06, 0x8000 },
3151 { 0x05, 0x8b76 },
3152 { 0x06, 0x8000 },
3153 { 0x1f, 0x0000 }
3154 };
3155
3156 rtl_apply_firmware(tp);
3157
3158 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3159
3160 /* For 4-corner performance improve */
3161 rtl_writephy(tp, 0x1f, 0x0005);
3162 rtl_writephy(tp, 0x05, 0x8b80);
3163 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
3164 rtl_writephy(tp, 0x1f, 0x0000);
3165
3166 /* PHY auto speed down */
3167 rtl_writephy(tp, 0x1f, 0x0004);
3168 rtl_writephy(tp, 0x1f, 0x0007);
3169 rtl_writephy(tp, 0x1e, 0x002d);
3170 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3171 rtl_writephy(tp, 0x1f, 0x0002);
3172 rtl_writephy(tp, 0x1f, 0x0000);
3173 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3174
3175 /* improve 10M EEE waveform */
3176 rtl_writephy(tp, 0x1f, 0x0005);
3177 rtl_writephy(tp, 0x05, 0x8b86);
3178 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3179 rtl_writephy(tp, 0x1f, 0x0000);
3180
3181 /* Improve 2-pair detection performance */
3182 rtl_writephy(tp, 0x1f, 0x0005);
3183 rtl_writephy(tp, 0x05, 0x8b85);
3184 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3185 rtl_writephy(tp, 0x1f, 0x0000);
3186
3187 /* EEE setting */
fdf6fc06 3188 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, ERIAR_EXGMAC);
70090424
HW		 3189 rtl_writephy(tp, 0x1f, 0x0005);
3190 rtl_writephy(tp, 0x05, 0x8b85);
3191 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3192 rtl_writephy(tp, 0x1f, 0x0004);
3193 rtl_writephy(tp, 0x1f, 0x0007);
3194 rtl_writephy(tp, 0x1e, 0x0020);
1b23a3e3 3195 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
70090424
HW		 3196 rtl_writephy(tp, 0x1f, 0x0002);
3197 rtl_writephy(tp, 0x1f, 0x0000);
3198 rtl_writephy(tp, 0x0d, 0x0007);
3199 rtl_writephy(tp, 0x0e, 0x003c);
3200 rtl_writephy(tp, 0x0d, 0x4007);
3201 rtl_writephy(tp, 0x0e, 0x0000);
3202 rtl_writephy(tp, 0x0d, 0x0000);
3203
3204 /* Green feature */
3205 rtl_writephy(tp, 0x1f, 0x0003);
3206 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3207 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3208 rtl_writephy(tp, 0x1f, 0x0000);
e0c07557 3209
3210 r8168_aldps_enable_1(tp);
70090424
HW		 3211}
3212
5f886e08
HW		 3213static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3214{
3215 /* For 4-corner performance improve */
3216 rtl_writephy(tp, 0x1f, 0x0005);
3217 rtl_writephy(tp, 0x05, 0x8b80);
3218 rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3219 rtl_writephy(tp, 0x1f, 0x0000);
3220
3221 /* PHY auto speed down */
3222 rtl_writephy(tp, 0x1f, 0x0007);
3223 rtl_writephy(tp, 0x1e, 0x002d);
3224 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3225 rtl_writephy(tp, 0x1f, 0x0000);
3226 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3227
3228 /* Improve 10M EEE waveform */
3229 rtl_writephy(tp, 0x1f, 0x0005);
3230 rtl_writephy(tp, 0x05, 0x8b86);
3231 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3232 rtl_writephy(tp, 0x1f, 0x0000);
3233}
3234
c2218925
HW		 3235static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3236{
3237 static const struct phy_reg phy_reg_init[] = {
3238 /* Channel estimation fine tune */
3239 { 0x1f, 0x0003 },
3240 { 0x09, 0xa20f },
3241 { 0x1f, 0x0000 },
3242
3243 /* Modify green table for giga & fnet */
3244 { 0x1f, 0x0005 },
3245 { 0x05, 0x8b55 },
3246 { 0x06, 0x0000 },
3247 { 0x05, 0x8b5e },
3248 { 0x06, 0x0000 },
3249 { 0x05, 0x8b67 },
3250 { 0x06, 0x0000 },
3251 { 0x05, 0x8b70 },
3252 { 0x06, 0x0000 },
3253 { 0x1f, 0x0000 },
3254 { 0x1f, 0x0007 },
3255 { 0x1e, 0x0078 },
3256 { 0x17, 0x0000 },
3257 { 0x19, 0x00fb },
3258 { 0x1f, 0x0000 },
3259
3260 /* Modify green table for 10M */
3261 { 0x1f, 0x0005 },
3262 { 0x05, 0x8b79 },
3263 { 0x06, 0xaa00 },
3264 { 0x1f, 0x0000 },
3265
3266 /* Disable hiimpedance detection (RTCT) */
3267 { 0x1f, 0x0003 },
3268 { 0x01, 0x328a },
3269 { 0x1f, 0x0000 }
3270 };
3271
3272 rtl_apply_firmware(tp);
3273
3274 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3275
5f886e08 3276 rtl8168f_hw_phy_config(tp);
c2218925
HW		 3277
3278 /* Improve 2-pair detection performance */
3279 rtl_writephy(tp, 0x1f, 0x0005);
3280 rtl_writephy(tp, 0x05, 0x8b85);
3281 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3282 rtl_writephy(tp, 0x1f, 0x0000);
e0c07557 3283
3284 r8168_aldps_enable_1(tp);
c2218925
HW		 3285}
3286
3287static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3288{
3289 rtl_apply_firmware(tp);
3290
5f886e08 3291 rtl8168f_hw_phy_config(tp);
e0c07557 3292
3293 r8168_aldps_enable_1(tp);
c2218925
HW		 3294}
3295
b3d7b2f2
HW		 3296static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3297{
b3d7b2f2
HW		 3298 static const struct phy_reg phy_reg_init[] = {
3299 /* Channel estimation fine tune */
3300 { 0x1f, 0x0003 },
3301 { 0x09, 0xa20f },
3302 { 0x1f, 0x0000 },
3303
3304 /* Modify green table for giga & fnet */
3305 { 0x1f, 0x0005 },
3306 { 0x05, 0x8b55 },
3307 { 0x06, 0x0000 },
3308 { 0x05, 0x8b5e },
3309 { 0x06, 0x0000 },
3310 { 0x05, 0x8b67 },
3311 { 0x06, 0x0000 },
3312 { 0x05, 0x8b70 },
3313 { 0x06, 0x0000 },
3314 { 0x1f, 0x0000 },
3315 { 0x1f, 0x0007 },
3316 { 0x1e, 0x0078 },
3317 { 0x17, 0x0000 },
3318 { 0x19, 0x00aa },
3319 { 0x1f, 0x0000 },
3320
3321 /* Modify green table for 10M */
3322 { 0x1f, 0x0005 },
3323 { 0x05, 0x8b79 },
3324 { 0x06, 0xaa00 },
3325 { 0x1f, 0x0000 },
3326
3327 /* Disable hiimpedance detection (RTCT) */
3328 { 0x1f, 0x0003 },
3329 { 0x01, 0x328a },
3330 { 0x1f, 0x0000 }
3331 };
3332
3333
3334 rtl_apply_firmware(tp);
3335
3336 rtl8168f_hw_phy_config(tp);
3337
3338 /* Improve 2-pair detection performance */
3339 rtl_writephy(tp, 0x1f, 0x0005);
3340 rtl_writephy(tp, 0x05, 0x8b85);
3341 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3342 rtl_writephy(tp, 0x1f, 0x0000);
3343
3344 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3345
3346 /* Modify green table for giga */
3347 rtl_writephy(tp, 0x1f, 0x0005);
3348 rtl_writephy(tp, 0x05, 0x8b54);
3349 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
3350 rtl_writephy(tp, 0x05, 0x8b5d);
3351 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
3352 rtl_writephy(tp, 0x05, 0x8a7c);
3353 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3354 rtl_writephy(tp, 0x05, 0x8a7f);
3355 rtl_w1w0_phy(tp, 0x06, 0x0100, 0x0000);
3356 rtl_writephy(tp, 0x05, 0x8a82);
3357 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3358 rtl_writephy(tp, 0x05, 0x8a85);
3359 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3360 rtl_writephy(tp, 0x05, 0x8a88);
3361 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3362 rtl_writephy(tp, 0x1f, 0x0000);
3363
3364 /* uc same-seed solution */
3365 rtl_writephy(tp, 0x1f, 0x0005);
3366 rtl_writephy(tp, 0x05, 0x8b85);
3367 rtl_w1w0_phy(tp, 0x06, 0x8000, 0x0000);
3368 rtl_writephy(tp, 0x1f, 0x0000);
3369
3370 /* eee setting */
fdf6fc06 3371 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
b3d7b2f2
HW		 3372 rtl_writephy(tp, 0x1f, 0x0005);
3373 rtl_writephy(tp, 0x05, 0x8b85);
3374 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3375 rtl_writephy(tp, 0x1f, 0x0004);
3376 rtl_writephy(tp, 0x1f, 0x0007);
3377 rtl_writephy(tp, 0x1e, 0x0020);
3378 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
3379 rtl_writephy(tp, 0x1f, 0x0000);
3380 rtl_writephy(tp, 0x0d, 0x0007);
3381 rtl_writephy(tp, 0x0e, 0x003c);
3382 rtl_writephy(tp, 0x0d, 0x4007);
3383 rtl_writephy(tp, 0x0e, 0x0000);
3384 rtl_writephy(tp, 0x0d, 0x0000);
3385
3386 /* Green feature */
3387 rtl_writephy(tp, 0x1f, 0x0003);
3388 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3389 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3390 rtl_writephy(tp, 0x1f, 0x0000);
e0c07557 3391
3392 r8168_aldps_enable_1(tp);
b3d7b2f2
HW		 3393}
3394
c558386b
HW		 3395static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3396{
3397 static const u16 mac_ocp_patch[] = {
3398 0xe008, 0xe01b, 0xe01d, 0xe01f,
3399 0xe021, 0xe023, 0xe025, 0xe027,
3400 0x49d2, 0xf10d, 0x766c, 0x49e2,
3401 0xf00a, 0x1ec0, 0x8ee1, 0xc60a,
3402
3403 0x77c0, 0x4870, 0x9fc0, 0x1ea0,
3404 0xc707, 0x8ee1, 0x9d6c, 0xc603,
3405 0xbe00, 0xb416, 0x0076, 0xe86c,
3406 0xc602, 0xbe00, 0x0000, 0xc602,
3407
3408 0xbe00, 0x0000, 0xc602, 0xbe00,
3409 0x0000, 0xc602, 0xbe00, 0x0000,
3410 0xc602, 0xbe00, 0x0000, 0xc602,
3411 0xbe00, 0x0000, 0xc602, 0xbe00,
3412
3413 0x0000, 0x0000, 0x0000, 0x0000
3414 };
3415 u32 i;
3416
3417 /* Patch code for GPHY reset */
3418 for (i = 0; i < ARRAY_SIZE(mac_ocp_patch); i++)
3419 r8168_mac_ocp_write(tp, 0xf800 + 2*i, mac_ocp_patch[i]);
3420 r8168_mac_ocp_write(tp, 0xfc26, 0x8000);
3421 r8168_mac_ocp_write(tp, 0xfc28, 0x0075);
3422
3423 rtl_apply_firmware(tp);
3424
3425 if (r8168_phy_ocp_read(tp, 0xa460) & 0x0100)
3426 rtl_w1w0_phy_ocp(tp, 0xbcc4, 0x0000, 0x8000);
3427 else
3428 rtl_w1w0_phy_ocp(tp, 0xbcc4, 0x8000, 0x0000);
3429
3430 if (r8168_phy_ocp_read(tp, 0xa466) & 0x0100)
3431 rtl_w1w0_phy_ocp(tp, 0xc41a, 0x0002, 0x0000);
3432 else
3433 rtl_w1w0_phy_ocp(tp, 0xbcc4, 0x0000, 0x0002);
3434
3435 rtl_w1w0_phy_ocp(tp, 0xa442, 0x000c, 0x0000);
3436 rtl_w1w0_phy_ocp(tp, 0xa4b2, 0x0004, 0x0000);
3437
3438 r8168_phy_ocp_write(tp, 0xa436, 0x8012);
3439 rtl_w1w0_phy_ocp(tp, 0xa438, 0x8000, 0x0000);
3440
3441 rtl_w1w0_phy_ocp(tp, 0xc422, 0x4000, 0x2000);
3442}
3443
4da19633 3444static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2857ffb7 3445{
350f7596 3446 static const struct phy_reg phy_reg_init[] = {
2857ffb7
FR		 3447 { 0x1f, 0x0003 },
3448 { 0x08, 0x441d },
3449 { 0x01, 0x9100 },
3450 { 0x1f, 0x0000 }
3451 };
3452
4da19633 3453 rtl_writephy(tp, 0x1f, 0x0000);
3454 rtl_patchphy(tp, 0x11, 1 << 12);
3455 rtl_patchphy(tp, 0x19, 1 << 13);
3456 rtl_patchphy(tp, 0x10, 1 << 15);
2857ffb7 3457
4da19633 3458 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2857ffb7
FR		 3459}
3460
5a5e4443
HW		 3461static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3462{
3463 static const struct phy_reg phy_reg_init[] = {
3464 { 0x1f, 0x0005 },
3465 { 0x1a, 0x0000 },
3466 { 0x1f, 0x0000 },
3467
3468 { 0x1f, 0x0004 },
3469 { 0x1c, 0x0000 },
3470 { 0x1f, 0x0000 },
3471
3472 { 0x1f, 0x0001 },
3473 { 0x15, 0x7701 },
3474 { 0x1f, 0x0000 }
3475 };
3476
3477 /* Disable ALDPS before ram code */
e0c07557 3478 r810x_aldps_disable(tp);
5a5e4443 3479
953a12cc 3480 rtl_apply_firmware(tp);
5a5e4443
HW		 3481
3482 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
e0c07557 3483
3484 r810x_aldps_enable(tp);
5a5e4443
HW		 3485}
3486
7e18dca1
HW		 3487static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3488{
7e18dca1 3489 /* Disable ALDPS before setting firmware */
e0c07557 3490 r810x_aldps_disable(tp);
7e18dca1
HW		 3491
3492 rtl_apply_firmware(tp);
3493
3494 /* EEE setting */
fdf6fc06 3495 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
7e18dca1
HW		 3496 rtl_writephy(tp, 0x1f, 0x0004);
3497 rtl_writephy(tp, 0x10, 0x401f);
3498 rtl_writephy(tp, 0x19, 0x7030);
3499 rtl_writephy(tp, 0x1f, 0x0000);
e0c07557 3500
3501 r810x_aldps_enable(tp);
7e18dca1
HW		 3502}
3503
5598bfe5
HW		 3504static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3505{
5598bfe5
HW		 3506 static const struct phy_reg phy_reg_init[] = {
3507 { 0x1f, 0x0004 },
3508 { 0x10, 0xc07f },
3509 { 0x19, 0x7030 },
3510 { 0x1f, 0x0000 }
3511 };
3512
3513 /* Disable ALDPS before ram code */
e0c07557 3514 r810x_aldps_disable(tp);
5598bfe5
HW		 3515
3516 rtl_apply_firmware(tp);
3517
fdf6fc06 3518 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5598bfe5
HW		 3519 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3520
fdf6fc06 3521 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
e0c07557 3522
3523 r810x_aldps_enable(tp);
5598bfe5
HW		 3524}
3525
5615d9f1
FR		 3526static void rtl_hw_phy_config(struct net_device *dev)
3527{
3528 struct rtl8169_private *tp = netdev_priv(dev);
5615d9f1
FR		 3529
3530 rtl8169_print_mac_version(tp);
3531
3532 switch (tp->mac_version) {
3533 case RTL_GIGA_MAC_VER_01:
3534 break;
3535 case RTL_GIGA_MAC_VER_02:
3536 case RTL_GIGA_MAC_VER_03:
4da19633 3537 rtl8169s_hw_phy_config(tp);
5615d9f1
FR		 3538 break;
3539 case RTL_GIGA_MAC_VER_04:
4da19633 3540 rtl8169sb_hw_phy_config(tp);
5615d9f1 3541 break;
2e955856 3542 case RTL_GIGA_MAC_VER_05:
4da19633 3543 rtl8169scd_hw_phy_config(tp);
2e955856 3544 break;
8c7006aa 3545 case RTL_GIGA_MAC_VER_06:
4da19633 3546 rtl8169sce_hw_phy_config(tp);
8c7006aa 3547 break;
2857ffb7
FR		 3548 case RTL_GIGA_MAC_VER_07:
3549 case RTL_GIGA_MAC_VER_08:
3550 case RTL_GIGA_MAC_VER_09:
4da19633 3551 rtl8102e_hw_phy_config(tp);
2857ffb7 3552 break;
236b8082 3553 case RTL_GIGA_MAC_VER_11:
4da19633 3554 rtl8168bb_hw_phy_config(tp);
236b8082
FR		 3555 break;
3556 case RTL_GIGA_MAC_VER_12:
4da19633 3557 rtl8168bef_hw_phy_config(tp);
236b8082
FR		 3558 break;
3559 case RTL_GIGA_MAC_VER_17:
4da19633 3560 rtl8168bef_hw_phy_config(tp);
236b8082 3561 break;
867763c1 3562 case RTL_GIGA_MAC_VER_18:
4da19633 3563 rtl8168cp_1_hw_phy_config(tp);
867763c1
FR		 3564 break;
3565 case RTL_GIGA_MAC_VER_19:
4da19633 3566 rtl8168c_1_hw_phy_config(tp);
867763c1 3567 break;
7da97ec9 3568 case RTL_GIGA_MAC_VER_20:
4da19633 3569 rtl8168c_2_hw_phy_config(tp);
7da97ec9 3570 break;
197ff761 3571 case RTL_GIGA_MAC_VER_21:
4da19633 3572 rtl8168c_3_hw_phy_config(tp);
197ff761 3573 break;
6fb07058 3574 case RTL_GIGA_MAC_VER_22:
4da19633 3575 rtl8168c_4_hw_phy_config(tp);
6fb07058 3576 break;
ef3386f0 3577 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 3578 case RTL_GIGA_MAC_VER_24:
4da19633 3579 rtl8168cp_2_hw_phy_config(tp);
ef3386f0 3580 break;
5b538df9 3581 case RTL_GIGA_MAC_VER_25:
bca03d5f 3582 rtl8168d_1_hw_phy_config(tp);
daf9df6d 3583 break;
3584 case RTL_GIGA_MAC_VER_26:
bca03d5f 3585 rtl8168d_2_hw_phy_config(tp);
daf9df6d 3586 break;
3587 case RTL_GIGA_MAC_VER_27:
4da19633 3588 rtl8168d_3_hw_phy_config(tp);
5b538df9 3589 break;
e6de30d6 3590 case RTL_GIGA_MAC_VER_28:
3591 rtl8168d_4_hw_phy_config(tp);
3592 break;
5a5e4443
HW		 3593 case RTL_GIGA_MAC_VER_29:
3594 case RTL_GIGA_MAC_VER_30:
3595 rtl8105e_hw_phy_config(tp);
3596 break;
cecb5fd7
FR		 3597 case RTL_GIGA_MAC_VER_31:
3598 /* None. */
3599 break;
01dc7fec 3600 case RTL_GIGA_MAC_VER_32:
01dc7fec 3601 case RTL_GIGA_MAC_VER_33:
70090424
HW		 3602 rtl8168e_1_hw_phy_config(tp);
3603 break;
3604 case RTL_GIGA_MAC_VER_34:
3605 rtl8168e_2_hw_phy_config(tp);
01dc7fec 3606 break;
c2218925
HW		 3607 case RTL_GIGA_MAC_VER_35:
3608 rtl8168f_1_hw_phy_config(tp);
3609 break;
3610 case RTL_GIGA_MAC_VER_36:
3611 rtl8168f_2_hw_phy_config(tp);
3612 break;
ef3386f0 3613
7e18dca1
HW		 3614 case RTL_GIGA_MAC_VER_37:
3615 rtl8402_hw_phy_config(tp);
3616 break;
3617
b3d7b2f2
HW		 3618 case RTL_GIGA_MAC_VER_38:
3619 rtl8411_hw_phy_config(tp);
3620 break;
3621
5598bfe5
HW		 3622 case RTL_GIGA_MAC_VER_39:
3623 rtl8106e_hw_phy_config(tp);
3624 break;
3625
c558386b
HW		 3626 case RTL_GIGA_MAC_VER_40:
3627 rtl8168g_1_hw_phy_config(tp);
3628 break;
3629
3630 case RTL_GIGA_MAC_VER_41:
5615d9f1
FR		 3631 default:
3632 break;
3633 }
3634}
3635
da78dbff 3636static void rtl_phy_work(struct rtl8169_private *tp)
1da177e4 3637{
1da177e4
LT		 3638 struct timer_list *timer = &tp->timer;
3639 void __iomem *ioaddr = tp->mmio_addr;
3640 unsigned long timeout = RTL8169_PHY_TIMEOUT;
3641
bcf0bf90 3642 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 3643
4da19633 3644 if (tp->phy_reset_pending(tp)) {
5b0384f4 3645 /*
1da177e4
LT		 3646 * A busy loop could burn quite a few cycles on nowadays CPU.
3647 * Let's delay the execution of the timer for a few ticks.
3648 */
3649 timeout = HZ/10;
3650 goto out_mod_timer;
3651 }
3652
3653 if (tp->link_ok(ioaddr))
da78dbff 3654 return;
1da177e4 3655
da78dbff 3656 netif_warn(tp, link, tp->dev, "PHY reset until link up\n");
1da177e4 3657
4da19633 3658 tp->phy_reset_enable(tp);
1da177e4
LT		 3659
3660out_mod_timer:
3661 mod_timer(timer, jiffies + timeout);
da78dbff
FR		 3662}
3663
3664static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3665{
da78dbff
FR		 3666 if (!test_and_set_bit(flag, tp->wk.flags))
3667 schedule_work(&tp->wk.work);
da78dbff
FR		 3668}
3669
3670static void rtl8169_phy_timer(unsigned long __opaque)
3671{
3672 struct net_device *dev = (struct net_device *)__opaque;
3673 struct rtl8169_private *tp = netdev_priv(dev);
3674
98ddf986 3675 rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
1da177e4
LT		 3676}
3677
1da177e4
LT		 3678static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3679 void __iomem *ioaddr)
3680{
3681 iounmap(ioaddr);
3682 pci_release_regions(pdev);
87aeec76 3683 pci_clear_mwi(pdev);
1da177e4
LT		 3684 pci_disable_device(pdev);
3685 free_netdev(dev);
3686}
3687
ffc46952
FR		 3688DECLARE_RTL_COND(rtl_phy_reset_cond)
3689{
3690 return tp->phy_reset_pending(tp);
3691}
3692
bf793295
FR		 3693static void rtl8169_phy_reset(struct net_device *dev,
3694 struct rtl8169_private *tp)
3695{
4da19633 3696 tp->phy_reset_enable(tp);
ffc46952 3697 rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100);
bf793295
FR		 3698}
3699
2544bfc0
FR		 3700static bool rtl_tbi_enabled(struct rtl8169_private *tp)
3701{
3702 void __iomem *ioaddr = tp->mmio_addr;
3703
3704 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
3705 (RTL_R8(PHYstatus) & TBI_Enable);
3706}
3707
4ff96fa6
FR		 3708static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3709{
3710 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 3711
5615d9f1 3712 rtl_hw_phy_config(dev);
4ff96fa6 3713
77332894
MS		 3714 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3715 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3716 RTL_W8(0x82, 0x01);
3717 }
4ff96fa6 3718
6dccd16b
FR		 3719 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3720
3721 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3722 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 3723
bcf0bf90 3724 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 3725 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3726 RTL_W8(0x82, 0x01);
3727 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4da19633 3728 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4ff96fa6
FR		 3729 }
3730
bf793295
FR		 3731 rtl8169_phy_reset(dev, tp);
3732
54405cde 3733 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
cecb5fd7
FR		 3734 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3735 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3736 (tp->mii.supports_gmii ?
3737 ADVERTISED_1000baseT_Half |
3738 ADVERTISED_1000baseT_Full : 0));
4ff96fa6 3739
2544bfc0 3740 if (rtl_tbi_enabled(tp))
bf82c189 3741 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4ff96fa6
FR		 3742}
3743
773d2021
FR		 3744static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3745{
3746 void __iomem *ioaddr = tp->mmio_addr;
3747 u32 high;
3748 u32 low;
3749
3750 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
3751 high = addr[4] | (addr[5] << 8);
3752
da78dbff 3753 rtl_lock_work(tp);
773d2021
FR		 3754
3755 RTL_W8(Cfg9346, Cfg9346_Unlock);
908ba2bf 3756
773d2021 3757 RTL_W32(MAC4, high);
908ba2bf 3758 RTL_R32(MAC4);
3759
78f1cd02 3760 RTL_W32(MAC0, low);
908ba2bf 3761 RTL_R32(MAC0);
3762
c28aa385 3763 if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
3764 const struct exgmac_reg e[] = {
3765 { .addr = 0xe0, ERIAR_MASK_1111, .val = low },
3766 { .addr = 0xe4, ERIAR_MASK_1111, .val = high },
3767 { .addr = 0xf0, ERIAR_MASK_1111, .val = low << 16 },
3768 { .addr = 0xf4, ERIAR_MASK_1111, .val = high << 16 |
3769 low >> 16 },
3770 };
3771
fdf6fc06 3772 rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
c28aa385 3773 }
3774
773d2021
FR		 3775 RTL_W8(Cfg9346, Cfg9346_Lock);
3776
da78dbff 3777 rtl_unlock_work(tp);
773d2021
FR		 3778}
3779
3780static int rtl_set_mac_address(struct net_device *dev, void *p)
3781{
3782 struct rtl8169_private *tp = netdev_priv(dev);
3783 struct sockaddr *addr = p;
3784
3785 if (!is_valid_ether_addr(addr->sa_data))
3786 return -EADDRNOTAVAIL;
3787
3788 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3789
3790 rtl_rar_set(tp, dev->dev_addr);
3791
3792 return 0;
3793}
3794
5f787a1a
FR		 3795static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3796{
3797 struct rtl8169_private *tp = netdev_priv(dev);
3798 struct mii_ioctl_data *data = if_mii(ifr);
3799
8b4ab28d
FR		 3800 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
3801}
5f787a1a 3802
cecb5fd7
FR		 3803static int rtl_xmii_ioctl(struct rtl8169_private *tp,
3804 struct mii_ioctl_data *data, int cmd)
8b4ab28d 3805{
5f787a1a
FR		 3806 switch (cmd) {
3807 case SIOCGMIIPHY:
3808 data->phy_id = 32; /* Internal PHY */
3809 return 0;
3810
3811 case SIOCGMIIREG:
4da19633 3812 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
5f787a1a
FR		 3813 return 0;
3814
3815 case SIOCSMIIREG:
4da19633 3816 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
5f787a1a
FR		 3817 return 0;
3818 }
3819 return -EOPNOTSUPP;
3820}
3821
8b4ab28d
FR		 3822static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3823{
3824 return -EOPNOTSUPP;
3825}
3826
fbac58fc
FR		 3827static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3828{
3829 if (tp->features & RTL_FEATURE_MSI) {
3830 pci_disable_msi(pdev);
3831 tp->features &= ~RTL_FEATURE_MSI;
3832 }
3833}
3834
c0e45c1c 3835static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
3836{
3837 struct mdio_ops *ops = &tp->mdio_ops;
3838
3839 switch (tp->mac_version) {
3840 case RTL_GIGA_MAC_VER_27:
3841 ops->write = r8168dp_1_mdio_write;
3842 ops->read = r8168dp_1_mdio_read;
3843 break;
e6de30d6 3844 case RTL_GIGA_MAC_VER_28:
4804b3b3 3845 case RTL_GIGA_MAC_VER_31:
e6de30d6 3846 ops->write = r8168dp_2_mdio_write;
3847 ops->read = r8168dp_2_mdio_read;
3848 break;
c558386b
HW		 3849 case RTL_GIGA_MAC_VER_40:
3850 case RTL_GIGA_MAC_VER_41:
3851 ops->write = r8168g_mdio_write;
3852 ops->read = r8168g_mdio_read;
3853 break;
c0e45c1c 3854 default:
3855 ops->write = r8169_mdio_write;
3856 ops->read = r8169_mdio_read;
3857 break;
3858 }
3859}
3860
649b3b8c 3861static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3862{
3863 void __iomem *ioaddr = tp->mmio_addr;
3864
3865 switch (tp->mac_version) {
3866 case RTL_GIGA_MAC_VER_29:
3867 case RTL_GIGA_MAC_VER_30:
3868 case RTL_GIGA_MAC_VER_32:
3869 case RTL_GIGA_MAC_VER_33:
3870 case RTL_GIGA_MAC_VER_34:
7e18dca1 3871 case RTL_GIGA_MAC_VER_37:
b3d7b2f2 3872 case RTL_GIGA_MAC_VER_38:
5598bfe5 3873 case RTL_GIGA_MAC_VER_39:
c558386b
HW		 3874 case RTL_GIGA_MAC_VER_40:
3875 case RTL_GIGA_MAC_VER_41:
649b3b8c 3876 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3877 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3878 break;
3879 default:
3880 break;
3881 }
3882}
3883
3884static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
3885{
3886 if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
3887 return false;
3888
3889 rtl_writephy(tp, 0x1f, 0x0000);
3890 rtl_writephy(tp, MII_BMCR, 0x0000);
3891
3892 rtl_wol_suspend_quirk(tp);
3893
3894 return true;
3895}
3896
065c27c1 3897static void r810x_phy_power_down(struct rtl8169_private *tp)
3898{
3899 rtl_writephy(tp, 0x1f, 0x0000);
3900 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3901}
3902
3903static void r810x_phy_power_up(struct rtl8169_private *tp)
3904{
3905 rtl_writephy(tp, 0x1f, 0x0000);
3906 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3907}
3908
3909static void r810x_pll_power_down(struct rtl8169_private *tp)
3910{
0004299a
HW		 3911 void __iomem *ioaddr = tp->mmio_addr;
3912
649b3b8c 3913 if (rtl_wol_pll_power_down(tp))
065c27c1 3914 return;
065c27c1 3915
3916 r810x_phy_power_down(tp);
0004299a
HW		 3917
3918 switch (tp->mac_version) {
3919 case RTL_GIGA_MAC_VER_07:
3920 case RTL_GIGA_MAC_VER_08:
3921 case RTL_GIGA_MAC_VER_09:
3922 case RTL_GIGA_MAC_VER_10:
3923 case RTL_GIGA_MAC_VER_13:
3924 case RTL_GIGA_MAC_VER_16:
3925 break;
3926 default:
3927 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3928 break;
3929 }
065c27c1 3930}
3931
3932static void r810x_pll_power_up(struct rtl8169_private *tp)
3933{
0004299a
HW		 3934 void __iomem *ioaddr = tp->mmio_addr;
3935
065c27c1 3936 r810x_phy_power_up(tp);
0004299a
HW		 3937
3938 switch (tp->mac_version) {
3939 case RTL_GIGA_MAC_VER_07:
3940 case RTL_GIGA_MAC_VER_08:
3941 case RTL_GIGA_MAC_VER_09:
3942 case RTL_GIGA_MAC_VER_10:
3943 case RTL_GIGA_MAC_VER_13:
3944 case RTL_GIGA_MAC_VER_16:
3945 break;
3946 default:
3947 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3948 break;
3949 }
065c27c1 3950}
3951
3952static void r8168_phy_power_up(struct rtl8169_private *tp)
3953{
3954 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3955 switch (tp->mac_version) {
3956 case RTL_GIGA_MAC_VER_11:
3957 case RTL_GIGA_MAC_VER_12:
3958 case RTL_GIGA_MAC_VER_17:
3959 case RTL_GIGA_MAC_VER_18:
3960 case RTL_GIGA_MAC_VER_19:
3961 case RTL_GIGA_MAC_VER_20:
3962 case RTL_GIGA_MAC_VER_21:
3963 case RTL_GIGA_MAC_VER_22:
3964 case RTL_GIGA_MAC_VER_23:
3965 case RTL_GIGA_MAC_VER_24:
3966 case RTL_GIGA_MAC_VER_25:
3967 case RTL_GIGA_MAC_VER_26:
3968 case RTL_GIGA_MAC_VER_27:
3969 case RTL_GIGA_MAC_VER_28:
3970 case RTL_GIGA_MAC_VER_31:
3971 rtl_writephy(tp, 0x0e, 0x0000);
3972 break;
3973 default:
3974 break;
3975 }
065c27c1 3976 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3977}
3978
3979static void r8168_phy_power_down(struct rtl8169_private *tp)
3980{
3981 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3982 switch (tp->mac_version) {
3983 case RTL_GIGA_MAC_VER_32:
3984 case RTL_GIGA_MAC_VER_33:
3985 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3986 break;
3987
3988 case RTL_GIGA_MAC_VER_11:
3989 case RTL_GIGA_MAC_VER_12:
3990 case RTL_GIGA_MAC_VER_17:
3991 case RTL_GIGA_MAC_VER_18:
3992 case RTL_GIGA_MAC_VER_19:
3993 case RTL_GIGA_MAC_VER_20:
3994 case RTL_GIGA_MAC_VER_21:
3995 case RTL_GIGA_MAC_VER_22:
3996 case RTL_GIGA_MAC_VER_23:
3997 case RTL_GIGA_MAC_VER_24:
3998 case RTL_GIGA_MAC_VER_25:
3999 case RTL_GIGA_MAC_VER_26:
4000 case RTL_GIGA_MAC_VER_27:
4001 case RTL_GIGA_MAC_VER_28:
4002 case RTL_GIGA_MAC_VER_31:
4003 rtl_writephy(tp, 0x0e, 0x0200);
4004 default:
4005 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4006 break;
4007 }
065c27c1 4008}
4009
4010static void r8168_pll_power_down(struct rtl8169_private *tp)
4011{
4012 void __iomem *ioaddr = tp->mmio_addr;
4013
cecb5fd7
FR		 4014 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4015 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4016 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
4804b3b3 4017 r8168dp_check_dash(tp)) {
065c27c1 4018 return;
5d2e1957 4019 }
065c27c1 4020
cecb5fd7
FR		 4021 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
4022 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
065c27c1 4023 (RTL_R16(CPlusCmd) & ASF)) {
4024 return;
4025 }
4026
01dc7fec 4027 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4028 tp->mac_version == RTL_GIGA_MAC_VER_33)
fdf6fc06 4029 rtl_ephy_write(tp, 0x19, 0xff64);
01dc7fec 4030
649b3b8c 4031 if (rtl_wol_pll_power_down(tp))
065c27c1 4032 return;
065c27c1 4033
4034 r8168_phy_power_down(tp);
4035
4036 switch (tp->mac_version) {
4037 case RTL_GIGA_MAC_VER_25:
4038 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 4039 case RTL_GIGA_MAC_VER_27:
4040 case RTL_GIGA_MAC_VER_28:
4804b3b3 4041 case RTL_GIGA_MAC_VER_31:
01dc7fec 4042 case RTL_GIGA_MAC_VER_32:
4043 case RTL_GIGA_MAC_VER_33:
065c27c1 4044 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4045 break;
4046 }
4047}
4048
4049static void r8168_pll_power_up(struct rtl8169_private *tp)
4050{
4051 void __iomem *ioaddr = tp->mmio_addr;
4052
065c27c1 4053 switch (tp->mac_version) {
4054 case RTL_GIGA_MAC_VER_25:
4055 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 4056 case RTL_GIGA_MAC_VER_27:
4057 case RTL_GIGA_MAC_VER_28:
4804b3b3 4058 case RTL_GIGA_MAC_VER_31:
01dc7fec 4059 case RTL_GIGA_MAC_VER_32:
4060 case RTL_GIGA_MAC_VER_33:
065c27c1 4061 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4062 break;
4063 }
4064
4065 r8168_phy_power_up(tp);
4066}
4067
d58d46b5
FR		 4068static void rtl_generic_op(struct rtl8169_private *tp,
4069 void (*op)(struct rtl8169_private *))
065c27c1 4070{
4071 if (op)
4072 op(tp);
4073}
4074
4075static void rtl_pll_power_down(struct rtl8169_private *tp)
4076{
d58d46b5 4077 rtl_generic_op(tp, tp->pll_power_ops.down);
065c27c1 4078}
4079
4080static void rtl_pll_power_up(struct rtl8169_private *tp)
4081{
d58d46b5 4082 rtl_generic_op(tp, tp->pll_power_ops.up);
065c27c1 4083}
4084
4085static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
4086{
4087 struct pll_power_ops *ops = &tp->pll_power_ops;
4088
4089 switch (tp->mac_version) {
4090 case RTL_GIGA_MAC_VER_07:
4091 case RTL_GIGA_MAC_VER_08:
4092 case RTL_GIGA_MAC_VER_09:
4093 case RTL_GIGA_MAC_VER_10:
4094 case RTL_GIGA_MAC_VER_16:
5a5e4443
HW		 4095 case RTL_GIGA_MAC_VER_29:
4096 case RTL_GIGA_MAC_VER_30:
7e18dca1 4097 case RTL_GIGA_MAC_VER_37:
5598bfe5 4098 case RTL_GIGA_MAC_VER_39:
065c27c1 4099 ops->down = r810x_pll_power_down;
4100 ops->up = r810x_pll_power_up;
4101 break;
4102
4103 case RTL_GIGA_MAC_VER_11:
4104 case RTL_GIGA_MAC_VER_12:
4105 case RTL_GIGA_MAC_VER_17:
4106 case RTL_GIGA_MAC_VER_18:
4107 case RTL_GIGA_MAC_VER_19:
4108 case RTL_GIGA_MAC_VER_20:
4109 case RTL_GIGA_MAC_VER_21:
4110 case RTL_GIGA_MAC_VER_22:
4111 case RTL_GIGA_MAC_VER_23:
4112 case RTL_GIGA_MAC_VER_24:
4113 case RTL_GIGA_MAC_VER_25:
4114 case RTL_GIGA_MAC_VER_26:
4115 case RTL_GIGA_MAC_VER_27:
e6de30d6 4116 case RTL_GIGA_MAC_VER_28:
4804b3b3 4117 case RTL_GIGA_MAC_VER_31:
01dc7fec 4118 case RTL_GIGA_MAC_VER_32:
4119 case RTL_GIGA_MAC_VER_33:
70090424 4120 case RTL_GIGA_MAC_VER_34:
c2218925
HW		 4121 case RTL_GIGA_MAC_VER_35:
4122 case RTL_GIGA_MAC_VER_36:
b3d7b2f2 4123 case RTL_GIGA_MAC_VER_38:
c558386b
HW		 4124 case RTL_GIGA_MAC_VER_40:
4125 case RTL_GIGA_MAC_VER_41:
065c27c1 4126 ops->down = r8168_pll_power_down;
4127 ops->up = r8168_pll_power_up;
4128 break;
4129
4130 default:
4131 ops->down = NULL;
4132 ops->up = NULL;
4133 break;
4134 }
4135}
4136
e542a226
HW		 4137static void rtl_init_rxcfg(struct rtl8169_private *tp)
4138{
4139 void __iomem *ioaddr = tp->mmio_addr;
4140
4141 switch (tp->mac_version) {
4142 case RTL_GIGA_MAC_VER_01:
4143 case RTL_GIGA_MAC_VER_02:
4144 case RTL_GIGA_MAC_VER_03:
4145 case RTL_GIGA_MAC_VER_04:
4146 case RTL_GIGA_MAC_VER_05:
4147 case RTL_GIGA_MAC_VER_06:
4148 case RTL_GIGA_MAC_VER_10:
4149 case RTL_GIGA_MAC_VER_11:
4150 case RTL_GIGA_MAC_VER_12:
4151 case RTL_GIGA_MAC_VER_13:
4152 case RTL_GIGA_MAC_VER_14:
4153 case RTL_GIGA_MAC_VER_15:
4154 case RTL_GIGA_MAC_VER_16:
4155 case RTL_GIGA_MAC_VER_17:
4156 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4157 break;
4158 case RTL_GIGA_MAC_VER_18:
4159 case RTL_GIGA_MAC_VER_19:
4160 case RTL_GIGA_MAC_VER_20:
4161 case RTL_GIGA_MAC_VER_21:
4162 case RTL_GIGA_MAC_VER_22:
4163 case RTL_GIGA_MAC_VER_23:
4164 case RTL_GIGA_MAC_VER_24:
eb2dc35d 4165 case RTL_GIGA_MAC_VER_34:
e542a226
HW		 4166 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4167 break;
4168 default:
4169 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
4170 break;
4171 }
4172}
4173
92fc43b4
HW		 4174static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4175{
4176 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
4177}
4178
d58d46b5
FR		 4179static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4180{
9c5028e9 4181 void __iomem *ioaddr = tp->mmio_addr;
4182
4183 RTL_W8(Cfg9346, Cfg9346_Unlock);
d58d46b5 4184 rtl_generic_op(tp, tp->jumbo_ops.enable);
9c5028e9 4185 RTL_W8(Cfg9346, Cfg9346_Lock);
d58d46b5
FR		 4186}
4187
4188static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4189{
9c5028e9 4190 void __iomem *ioaddr = tp->mmio_addr;
4191
4192 RTL_W8(Cfg9346, Cfg9346_Unlock);
d58d46b5 4193 rtl_generic_op(tp, tp->jumbo_ops.disable);
9c5028e9 4194 RTL_W8(Cfg9346, Cfg9346_Lock);
d58d46b5
FR		 4195}
4196
4197static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4198{
4199 void __iomem *ioaddr = tp->mmio_addr;
4200
4201 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4202 RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
4203 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
4204}
4205
4206static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4207{
4208 void __iomem *ioaddr = tp->mmio_addr;
4209
4210 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4211 RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
4212 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
4213}
4214
4215static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4216{
4217 void __iomem *ioaddr = tp->mmio_addr;
4218
4219 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4220}
4221
4222static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4223{
4224 void __iomem *ioaddr = tp->mmio_addr;
4225
4226 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4227}
4228
4229static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4230{
4231 void __iomem *ioaddr = tp->mmio_addr;
d58d46b5
FR		 4232
4233 RTL_W8(MaxTxPacketSize, 0x3f);
4234 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4235 RTL_W8(Config4, RTL_R8(Config4) | 0x01);
4512ff9f 4236 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
d58d46b5
FR		 4237}
4238
4239static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4240{
4241 void __iomem *ioaddr = tp->mmio_addr;
d58d46b5
FR		 4242
4243 RTL_W8(MaxTxPacketSize, 0x0c);
4244 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4245 RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
4512ff9f 4246 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
d58d46b5
FR		 4247}
4248
4249static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4250{
4251 rtl_tx_performance_tweak(tp->pci_dev,
4252 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4253}
4254
4255static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4256{
4257 rtl_tx_performance_tweak(tp->pci_dev,
4258 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4259}
4260
4261static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4262{
4263 void __iomem *ioaddr = tp->mmio_addr;
4264
4265 r8168b_0_hw_jumbo_enable(tp);
4266
4267 RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
4268}
4269
4270static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4271{
4272 void __iomem *ioaddr = tp->mmio_addr;
4273
4274 r8168b_0_hw_jumbo_disable(tp);
4275
4276 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4277}
4278
4279static void __devinit rtl_init_jumbo_ops(struct rtl8169_private *tp)
4280{
4281 struct jumbo_ops *ops = &tp->jumbo_ops;
4282
4283 switch (tp->mac_version) {
4284 case RTL_GIGA_MAC_VER_11:
4285 ops->disable = r8168b_0_hw_jumbo_disable;
4286 ops->enable = r8168b_0_hw_jumbo_enable;
4287 break;
4288 case RTL_GIGA_MAC_VER_12:
4289 case RTL_GIGA_MAC_VER_17:
4290 ops->disable = r8168b_1_hw_jumbo_disable;
4291 ops->enable = r8168b_1_hw_jumbo_enable;
4292 break;
4293 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
4294 case RTL_GIGA_MAC_VER_19:
4295 case RTL_GIGA_MAC_VER_20:
4296 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
4297 case RTL_GIGA_MAC_VER_22:
4298 case RTL_GIGA_MAC_VER_23:
4299 case RTL_GIGA_MAC_VER_24:
4300 case RTL_GIGA_MAC_VER_25:
4301 case RTL_GIGA_MAC_VER_26:
4302 ops->disable = r8168c_hw_jumbo_disable;
4303 ops->enable = r8168c_hw_jumbo_enable;
4304 break;
4305 case RTL_GIGA_MAC_VER_27:
4306 case RTL_GIGA_MAC_VER_28:
4307 ops->disable = r8168dp_hw_jumbo_disable;
4308 ops->enable = r8168dp_hw_jumbo_enable;
4309 break;
4310 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
4311 case RTL_GIGA_MAC_VER_32:
4312 case RTL_GIGA_MAC_VER_33:
4313 case RTL_GIGA_MAC_VER_34:
4314 ops->disable = r8168e_hw_jumbo_disable;
4315 ops->enable = r8168e_hw_jumbo_enable;
4316 break;
4317
4318 /*
4319 * No action needed for jumbo frames with 8169.
4320 * No jumbo for 810x at all.
4321 */
c558386b
HW		 4322 case RTL_GIGA_MAC_VER_40:
4323 case RTL_GIGA_MAC_VER_41:
d58d46b5
FR		 4324 default:
4325 ops->disable = NULL;
4326 ops->enable = NULL;
4327 break;
4328 }
4329}
4330
ffc46952
FR		 4331DECLARE_RTL_COND(rtl_chipcmd_cond)
4332{
4333 void __iomem *ioaddr = tp->mmio_addr;
4334
4335 return RTL_R8(ChipCmd) & CmdReset;
4336}
4337
6f43adc8
FR		 4338static void rtl_hw_reset(struct rtl8169_private *tp)
4339{
4340 void __iomem *ioaddr = tp->mmio_addr;
6f43adc8 4341
6f43adc8
FR		 4342 RTL_W8(ChipCmd, CmdReset);
4343
ffc46952 4344 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
6f43adc8
FR		 4345}
4346
b6ffd97f 4347static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
953a12cc 4348{
b6ffd97f
FR		 4349 struct rtl_fw *rtl_fw;
4350 const char *name;
4351 int rc = -ENOMEM;
953a12cc 4352
b6ffd97f
FR		 4353 name = rtl_lookup_firmware_name(tp);
4354 if (!name)
4355 goto out_no_firmware;
953a12cc 4356
b6ffd97f
FR		 4357 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4358 if (!rtl_fw)
4359 goto err_warn;
31bd204f 4360
b6ffd97f
FR		 4361 rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
4362 if (rc < 0)
4363 goto err_free;
4364
fd112f2e
FR		 4365 rc = rtl_check_firmware(tp, rtl_fw);
4366 if (rc < 0)
4367 goto err_release_firmware;
4368
b6ffd97f
FR		 4369 tp->rtl_fw = rtl_fw;
4370out:
4371 return;
4372
fd112f2e
FR		 4373err_release_firmware:
4374 release_firmware(rtl_fw->fw);
b6ffd97f
FR		 4375err_free:
4376 kfree(rtl_fw);
4377err_warn:
4378 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4379 name, rc);
4380out_no_firmware:
4381 tp->rtl_fw = NULL;
4382 goto out;
4383}
4384
4385static void rtl_request_firmware(struct rtl8169_private *tp)
4386{
4387 if (IS_ERR(tp->rtl_fw))
4388 rtl_request_uncached_firmware(tp);
953a12cc
FR		 4389}
4390
92fc43b4
HW		 4391static void rtl_rx_close(struct rtl8169_private *tp)
4392{
4393 void __iomem *ioaddr = tp->mmio_addr;
92fc43b4 4394
1687b566 4395 RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
92fc43b4
HW		 4396}
4397
ffc46952
FR		 4398DECLARE_RTL_COND(rtl_npq_cond)
4399{
4400 void __iomem *ioaddr = tp->mmio_addr;
4401
4402 return RTL_R8(TxPoll) & NPQ;
4403}
4404
4405DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4406{
4407 void __iomem *ioaddr = tp->mmio_addr;
4408
4409 return RTL_R32(TxConfig) & TXCFG_EMPTY;
4410}
4411
e6de30d6 4412static void rtl8169_hw_reset(struct rtl8169_private *tp)
1da177e4 4413{
e6de30d6 4414 void __iomem *ioaddr = tp->mmio_addr;
4415
1da177e4 4416 /* Disable interrupts */
811fd301 4417 rtl8169_irq_mask_and_ack(tp);
1da177e4 4418
92fc43b4
HW		 4419 rtl_rx_close(tp);
4420
5d2e1957 4421 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4804b3b3 4422 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4423 tp->mac_version == RTL_GIGA_MAC_VER_31) {
ffc46952 4424 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
c2218925
HW		 4425 } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
4426 tp->mac_version == RTL_GIGA_MAC_VER_35 ||
7e18dca1 4427 tp->mac_version == RTL_GIGA_MAC_VER_36 ||
b3d7b2f2 4428 tp->mac_version == RTL_GIGA_MAC_VER_37 ||
c558386b
HW		 4429 tp->mac_version == RTL_GIGA_MAC_VER_40 ||
4430 tp->mac_version == RTL_GIGA_MAC_VER_41 ||
b3d7b2f2 4431 tp->mac_version == RTL_GIGA_MAC_VER_38) {
c2b0c1e7 4432 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
ffc46952 4433 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
92fc43b4
HW		 4434 } else {
4435 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4436 udelay(100);
e6de30d6 4437 }
4438
92fc43b4 4439 rtl_hw_reset(tp);
1da177e4
LT		 4440}
4441
7f796d83 4442static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 4443{
4444 void __iomem *ioaddr = tp->mmio_addr;
9cb427b6
FR		 4445
4446 /* Set DMA burst size and Interframe Gap Time */
4447 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4448 (InterFrameGap << TxInterFrameGapShift));
4449}
4450
07ce4064 4451static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 4452{
4453 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 4454
07ce4064
FR		 4455 tp->hw_start(dev);
4456
da78dbff 4457 rtl_irq_enable_all(tp);
07ce4064
FR		 4458}
4459
7f796d83
FR		 4460static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
4461 void __iomem *ioaddr)
4462{
4463 /*
4464 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4465 * register to be written before TxDescAddrLow to work.
4466 * Switching from MMIO to I/O access fixes the issue as well.
4467 */
4468 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
284901a9 4469 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
7f796d83 4470 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
284901a9 4471 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 4472}
4473
4474static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4475{
4476 u16 cmd;
4477
4478 cmd = RTL_R16(CPlusCmd);
4479 RTL_W16(CPlusCmd, cmd);
4480 return cmd;
4481}
4482
fdd7b4c3 4483static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
7f796d83
FR		 4484{
4485 /* Low hurts. Let's disable the filtering. */
207d6e87 4486 RTL_W16(RxMaxSize, rx_buf_sz + 1);
7f796d83
FR		 4487}
4488
6dccd16b
FR		 4489static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4490{
3744100e 4491 static const struct rtl_cfg2_info {
6dccd16b
FR		 4492 u32 mac_version;
4493 u32 clk;
4494 u32 val;
4495 } cfg2_info [] = {
4496 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4497 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4498 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4499 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3744100e
FR		 4500 };
4501 const struct rtl_cfg2_info *p = cfg2_info;
6dccd16b
FR		 4502 unsigned int i;
4503 u32 clk;
4504
4505 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 4506 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 4507 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4508 RTL_W32(0x7c, p->val);
4509 break;
4510 }
4511 }
4512}
4513
e6b763ea
FR		 4514static void rtl_set_rx_mode(struct net_device *dev)
4515{
4516 struct rtl8169_private *tp = netdev_priv(dev);
4517 void __iomem *ioaddr = tp->mmio_addr;
4518 u32 mc_filter[2]; /* Multicast hash filter */
4519 int rx_mode;
4520 u32 tmp = 0;
4521
4522 if (dev->flags & IFF_PROMISC) {
4523 /* Unconditionally log net taps. */
4524 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4525 rx_mode =
4526 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4527 AcceptAllPhys;
4528 mc_filter[1] = mc_filter[0] = 0xffffffff;
4529 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4530 (dev->flags & IFF_ALLMULTI)) {
4531 /* Too many to filter perfectly -- accept all multicasts. */
4532 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4533 mc_filter[1] = mc_filter[0] = 0xffffffff;
4534 } else {
4535 struct netdev_hw_addr *ha;
4536
4537 rx_mode = AcceptBroadcast | AcceptMyPhys;
4538 mc_filter[1] = mc_filter[0] = 0;
4539 netdev_for_each_mc_addr(ha, dev) {
4540 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4541 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4542 rx_mode |= AcceptMulticast;
4543 }
4544 }
4545
4546 if (dev->features & NETIF_F_RXALL)
4547 rx_mode |= (AcceptErr | AcceptRunt);
4548
4549 tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4550
4551 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4552 u32 data = mc_filter[0];
4553
4554 mc_filter[0] = swab32(mc_filter[1]);
4555 mc_filter[1] = swab32(data);
4556 }
4557
4558 RTL_W32(MAR0 + 4, mc_filter[1]);
4559 RTL_W32(MAR0 + 0, mc_filter[0]);
4560
4561 RTL_W32(RxConfig, tmp);
4562}
4563
07ce4064
FR		 4564static void rtl_hw_start_8169(struct net_device *dev)
4565{
4566 struct rtl8169_private *tp = netdev_priv(dev);
4567 void __iomem *ioaddr = tp->mmio_addr;
4568 struct pci_dev *pdev = tp->pci_dev;
07ce4064 4569
9cb427b6
FR		 4570 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4571 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4572 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4573 }
4574
1da177e4 4575 RTL_W8(Cfg9346, Cfg9346_Unlock);
cecb5fd7
FR		 4576 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4577 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4578 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4579 tp->mac_version == RTL_GIGA_MAC_VER_04)
9cb427b6
FR		 4580 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4581
e542a226
HW		 4582 rtl_init_rxcfg(tp);
4583
f0298f81 4584 RTL_W8(EarlyTxThres, NoEarlyTx);
1da177e4 4585
6f0333b8 4586 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
1da177e4 4587
cecb5fd7
FR		 4588 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4589 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4590 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4591 tp->mac_version == RTL_GIGA_MAC_VER_04)
c946b304 4592 rtl_set_rx_tx_config_registers(tp);
1da177e4 4593
7f796d83 4594 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 4595
cecb5fd7
FR		 4596 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4597 tp->mac_version == RTL_GIGA_MAC_VER_03) {
06fa7358 4598 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1da177e4 4599 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 4600 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 4601 }
4602
bcf0bf90
FR		 4603 RTL_W16(CPlusCmd, tp->cp_cmd);
4604
6dccd16b
FR		 4605 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4606
1da177e4
LT		 4607 /*
4608 * Undocumented corner. Supposedly:
4609 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4610 */
4611 RTL_W16(IntrMitigate, 0x0000);
4612
7f796d83 4613 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 4614
cecb5fd7
FR		 4615 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4616 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4617 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
4618 tp->mac_version != RTL_GIGA_MAC_VER_04) {
c946b304
FR		 4619 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4620 rtl_set_rx_tx_config_registers(tp);
4621 }
4622
1da177e4 4623 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 4624
4625 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4626 RTL_R8(IntrMask);
1da177e4
LT		 4627
4628 RTL_W32(RxMissed, 0);
4629
07ce4064 4630 rtl_set_rx_mode(dev);
1da177e4
LT		 4631
4632 /* no early-rx interrupts */
4633 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
07ce4064 4634}
1da177e4 4635
beb1fe18
HW		 4636static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4637{
4638 if (tp->csi_ops.write)
52989f0e 4639 tp->csi_ops.write(tp, addr, value);
beb1fe18
HW		 4640}
4641
4642static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4643{
52989f0e 4644 return tp->csi_ops.read ? tp->csi_ops.read(tp, addr) : ~0;
beb1fe18
HW		 4645}
4646
4647static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits)
dacf8154
FR		 4648{
4649 u32 csi;
4650
beb1fe18
HW		 4651 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4652 rtl_csi_write(tp, 0x070c, csi | bits);
4653}
4654
4655static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
4656{
4657 rtl_csi_access_enable(tp, 0x17000000);
650e8d5d 4658}
4659
beb1fe18 4660static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
e6de30d6 4661{
beb1fe18 4662 rtl_csi_access_enable(tp, 0x27000000);
e6de30d6 4663}
4664
ffc46952
FR		 4665DECLARE_RTL_COND(rtl_csiar_cond)
4666{
4667 void __iomem *ioaddr = tp->mmio_addr;
4668
4669 return RTL_R32(CSIAR) & CSIAR_FLAG;
4670}
4671
52989f0e 4672static void r8169_csi_write(struct rtl8169_private *tp, int addr, int value)
650e8d5d 4673{
52989f0e 4674 void __iomem *ioaddr = tp->mmio_addr;
beb1fe18
HW		 4675
4676 RTL_W32(CSIDR, value);
4677 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4678 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4679
ffc46952 4680 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
beb1fe18
HW		 4681}
4682
52989f0e 4683static u32 r8169_csi_read(struct rtl8169_private *tp, int addr)
beb1fe18 4684{
52989f0e 4685 void __iomem *ioaddr = tp->mmio_addr;
beb1fe18
HW		 4686
4687 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
4688 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4689
ffc46952
FR		 4690 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4691 RTL_R32(CSIDR) : ~0;
beb1fe18
HW		 4692}
4693
52989f0e 4694static void r8402_csi_write(struct rtl8169_private *tp, int addr, int value)
7e18dca1 4695{
52989f0e 4696 void __iomem *ioaddr = tp->mmio_addr;
7e18dca1
HW		 4697
4698 RTL_W32(CSIDR, value);
4699 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4700 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
4701 CSIAR_FUNC_NIC);
4702
ffc46952 4703 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
7e18dca1
HW		 4704}
4705
52989f0e 4706static u32 r8402_csi_read(struct rtl8169_private *tp, int addr)
7e18dca1 4707{
52989f0e 4708 void __iomem *ioaddr = tp->mmio_addr;
7e18dca1
HW		 4709
4710 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
4711 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4712
ffc46952
FR		 4713 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4714 RTL_R32(CSIDR) : ~0;
7e18dca1
HW		 4715}
4716
beb1fe18
HW		 4717static void __devinit rtl_init_csi_ops(struct rtl8169_private *tp)
4718{
4719 struct csi_ops *ops = &tp->csi_ops;
4720
4721 switch (tp->mac_version) {
4722 case RTL_GIGA_MAC_VER_01:
4723 case RTL_GIGA_MAC_VER_02:
4724 case RTL_GIGA_MAC_VER_03:
4725 case RTL_GIGA_MAC_VER_04:
4726 case RTL_GIGA_MAC_VER_05:
4727 case RTL_GIGA_MAC_VER_06:
4728 case RTL_GIGA_MAC_VER_10:
4729 case RTL_GIGA_MAC_VER_11:
4730 case RTL_GIGA_MAC_VER_12:
4731 case RTL_GIGA_MAC_VER_13:
4732 case RTL_GIGA_MAC_VER_14:
4733 case RTL_GIGA_MAC_VER_15:
4734 case RTL_GIGA_MAC_VER_16:
4735 case RTL_GIGA_MAC_VER_17:
4736 ops->write = NULL;
4737 ops->read = NULL;
4738 break;
4739
7e18dca1 4740 case RTL_GIGA_MAC_VER_37:
b3d7b2f2 4741 case RTL_GIGA_MAC_VER_38:
7e18dca1
HW		 4742 ops->write = r8402_csi_write;
4743 ops->read = r8402_csi_read;
4744 break;
4745
beb1fe18
HW		 4746 default:
4747 ops->write = r8169_csi_write;
4748 ops->read = r8169_csi_read;
4749 break;
4750 }
dacf8154
FR		 4751}
4752
4753struct ephy_info {
4754 unsigned int offset;
4755 u16 mask;
4756 u16 bits;
4757};
4758
fdf6fc06
FR		 4759static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
4760 int len)
dacf8154
FR		 4761{
4762 u16 w;
4763
4764 while (len-- > 0) {
fdf6fc06
FR		 4765 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4766 rtl_ephy_write(tp, e->offset, w);
dacf8154
FR		 4767 e++;
4768 }
4769}
4770
b726e493
FR		 4771static void rtl_disable_clock_request(struct pci_dev *pdev)
4772{
7d7903b2
JL		 4773 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
4774 PCI_EXP_LNKCTL_CLKREQ_EN);
b726e493
FR		 4775}
4776
e6de30d6 4777static void rtl_enable_clock_request(struct pci_dev *pdev)
4778{
7d7903b2
JL		 4779 pcie_capability_set_word(pdev, PCI_EXP_LNKCTL,
4780 PCI_EXP_LNKCTL_CLKREQ_EN);
e6de30d6 4781}
4782
b726e493
FR		 4783#define R8168_CPCMD_QUIRK_MASK (\
4784 EnableBist | \
4785 Mac_dbgo_oe | \
4786 Force_half_dup | \
4787 Force_rxflow_en | \
4788 Force_txflow_en | \
4789 Cxpl_dbg_sel | \
4790 ASF | \
4791 PktCntrDisable | \
4792 Mac_dbgo_sel)
4793
beb1fe18 4794static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
219a1e9d 4795{
beb1fe18
HW		 4796 void __iomem *ioaddr = tp->mmio_addr;
4797 struct pci_dev *pdev = tp->pci_dev;
4798
b726e493
FR		 4799 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4800
4801 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4802
2e68ae44
FR		 4803 rtl_tx_performance_tweak(pdev,
4804 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
219a1e9d
FR		 4805}
4806
beb1fe18 4807static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
219a1e9d 4808{
beb1fe18
HW		 4809 void __iomem *ioaddr = tp->mmio_addr;
4810
4811 rtl_hw_start_8168bb(tp);
b726e493 4812
f0298f81 4813 RTL_W8(MaxTxPacketSize, TxPacketMax);
b726e493
FR		 4814
4815 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
219a1e9d
FR		 4816}
4817
beb1fe18 4818static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
219a1e9d 4819{
beb1fe18
HW		 4820 void __iomem *ioaddr = tp->mmio_addr;
4821 struct pci_dev *pdev = tp->pci_dev;
4822
b726e493
FR		 4823 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4824
4825 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4826
219a1e9d 4827 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
b726e493
FR		 4828
4829 rtl_disable_clock_request(pdev);
4830
4831 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
219a1e9d
FR		 4832}
4833
beb1fe18 4834static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
219a1e9d 4835{
350f7596 4836 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 4837 { 0x01, 0, 0x0001 },
4838 { 0x02, 0x0800, 0x1000 },
4839 { 0x03, 0, 0x0042 },
4840 { 0x06, 0x0080, 0x0000 },
4841 { 0x07, 0, 0x2000 }
4842 };
4843
beb1fe18 4844 rtl_csi_access_enable_2(tp);
b726e493 4845
fdf6fc06 4846 rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
b726e493 4847
beb1fe18 4848 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 4849}
4850
beb1fe18 4851static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
ef3386f0 4852{
beb1fe18
HW		 4853 void __iomem *ioaddr = tp->mmio_addr;
4854 struct pci_dev *pdev = tp->pci_dev;
4855
4856 rtl_csi_access_enable_2(tp);
ef3386f0
FR		 4857
4858 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4859
4860 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4861
4862 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4863}
4864
beb1fe18 4865static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
7f3e3d3a 4866{
beb1fe18
HW		 4867 void __iomem *ioaddr = tp->mmio_addr;
4868 struct pci_dev *pdev = tp->pci_dev;
4869
4870 rtl_csi_access_enable_2(tp);
7f3e3d3a
FR		 4871
4872 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4873
4874 /* Magic. */
4875 RTL_W8(DBG_REG, 0x20);
4876
f0298f81 4877 RTL_W8(MaxTxPacketSize, TxPacketMax);
7f3e3d3a
FR		 4878
4879 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4880
4881 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4882}
4883
beb1fe18 4884static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
219a1e9d 4885{
beb1fe18 4886 void __iomem *ioaddr = tp->mmio_addr;
350f7596 4887 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 4888 { 0x02, 0x0800, 0x1000 },
4889 { 0x03, 0, 0x0002 },
4890 { 0x06, 0x0080, 0x0000 }
4891 };
4892
beb1fe18 4893 rtl_csi_access_enable_2(tp);
b726e493
FR		 4894
4895 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4896
fdf6fc06 4897 rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
b726e493 4898
beb1fe18 4899 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 4900}
4901
beb1fe18 4902static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
219a1e9d 4903{
350f7596 4904 static const struct ephy_info e_info_8168c_2[] = {
b726e493
FR		 4905 { 0x01, 0, 0x0001 },
4906 { 0x03, 0x0400, 0x0220 }
4907 };
4908
beb1fe18 4909 rtl_csi_access_enable_2(tp);
b726e493 4910
fdf6fc06 4911 rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
b726e493 4912
beb1fe18 4913 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 4914}
4915
beb1fe18 4916static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
197ff761 4917{
beb1fe18 4918 rtl_hw_start_8168c_2(tp);
197ff761
FR		 4919}
4920
beb1fe18 4921static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
6fb07058 4922{
beb1fe18 4923 rtl_csi_access_enable_2(tp);
6fb07058 4924
beb1fe18 4925 __rtl_hw_start_8168cp(tp);
6fb07058
FR		 4926}
4927
beb1fe18 4928static void rtl_hw_start_8168d(struct rtl8169_private *tp)
5b538df9 4929{
beb1fe18
HW		 4930 void __iomem *ioaddr = tp->mmio_addr;
4931 struct pci_dev *pdev = tp->pci_dev;
4932
4933 rtl_csi_access_enable_2(tp);
5b538df9
FR		 4934
4935 rtl_disable_clock_request(pdev);
4936
f0298f81 4937 RTL_W8(MaxTxPacketSize, TxPacketMax);
5b538df9
FR		 4938
4939 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4940
4941 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4942}
4943
beb1fe18 4944static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4804b3b3 4945{
beb1fe18
HW		 4946 void __iomem *ioaddr = tp->mmio_addr;
4947 struct pci_dev *pdev = tp->pci_dev;
4948
4949 rtl_csi_access_enable_1(tp);
4804b3b3 4950
4951 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4952
4953 RTL_W8(MaxTxPacketSize, TxPacketMax);
4954
4955 rtl_disable_clock_request(pdev);
4956}
4957
beb1fe18 4958static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
e6de30d6 4959{
beb1fe18
HW		 4960 void __iomem *ioaddr = tp->mmio_addr;
4961 struct pci_dev *pdev = tp->pci_dev;
e6de30d6 4962 static const struct ephy_info e_info_8168d_4[] = {
4963 { 0x0b, ~0, 0x48 },
4964 { 0x19, 0x20, 0x50 },
4965 { 0x0c, ~0, 0x20 }
4966 };
4967 int i;
4968
beb1fe18 4969 rtl_csi_access_enable_1(tp);
e6de30d6 4970
4971 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4972
4973 RTL_W8(MaxTxPacketSize, TxPacketMax);
4974
4975 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4976 const struct ephy_info *e = e_info_8168d_4 + i;
4977 u16 w;
4978
fdf6fc06
FR		 4979 w = rtl_ephy_read(tp, e->offset);
4980 rtl_ephy_write(tp, 0x03, (w & e->mask) | e->bits);
e6de30d6 4981 }
4982
4983 rtl_enable_clock_request(pdev);
4984}
4985
beb1fe18 4986static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
01dc7fec 4987{
beb1fe18
HW		 4988 void __iomem *ioaddr = tp->mmio_addr;
4989 struct pci_dev *pdev = tp->pci_dev;
70090424 4990 static const struct ephy_info e_info_8168e_1[] = {
01dc7fec 4991 { 0x00, 0x0200, 0x0100 },
4992 { 0x00, 0x0000, 0x0004 },
4993 { 0x06, 0x0002, 0x0001 },
4994 { 0x06, 0x0000, 0x0030 },
4995 { 0x07, 0x0000, 0x2000 },
4996 { 0x00, 0x0000, 0x0020 },
4997 { 0x03, 0x5800, 0x2000 },
4998 { 0x03, 0x0000, 0x0001 },
4999 { 0x01, 0x0800, 0x1000 },
5000 { 0x07, 0x0000, 0x4000 },
5001 { 0x1e, 0x0000, 0x2000 },
5002 { 0x19, 0xffff, 0xfe6c },
5003 { 0x0a, 0x0000, 0x0040 }
5004 };
5005
beb1fe18 5006 rtl_csi_access_enable_2(tp);
01dc7fec 5007
fdf6fc06 5008 rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
01dc7fec 5009
5010 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5011
5012 RTL_W8(MaxTxPacketSize, TxPacketMax);
5013
5014 rtl_disable_clock_request(pdev);
5015
5016 /* Reset tx FIFO pointer */
cecb5fd7
FR		 5017 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
5018 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
01dc7fec 5019
cecb5fd7 5020 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
01dc7fec 5021}
5022
beb1fe18 5023static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
70090424 5024{
beb1fe18
HW		 5025 void __iomem *ioaddr = tp->mmio_addr;
5026 struct pci_dev *pdev = tp->pci_dev;
70090424
HW		 5027 static const struct ephy_info e_info_8168e_2[] = {
5028 { 0x09, 0x0000, 0x0080 },
5029 { 0x19, 0x0000, 0x0224 }
5030 };
5031
beb1fe18 5032 rtl_csi_access_enable_1(tp);
70090424 5033
fdf6fc06 5034 rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
70090424
HW		 5035
5036 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5037
fdf6fc06
FR		 5038 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5039 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5040 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5041 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5042 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5043 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
5044 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5045 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
70090424 5046
3090bd9a 5047 RTL_W8(MaxTxPacketSize, EarlySize);
70090424
HW		 5048
5049 rtl_disable_clock_request(pdev);
5050
5051 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5052 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5053
5054 /* Adjust EEE LED frequency */
5055 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5056
5057 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5058 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5059 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5060}
5061
5f886e08 5062static void rtl_hw_start_8168f(struct rtl8169_private *tp)
c2218925 5063{
beb1fe18
HW		 5064 void __iomem *ioaddr = tp->mmio_addr;
5065 struct pci_dev *pdev = tp->pci_dev;
c2218925 5066
5f886e08 5067 rtl_csi_access_enable_2(tp);
c2218925
HW		 5068
5069 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5070
fdf6fc06
FR		 5071 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5072 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5073 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5074 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5075 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5076 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5077 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5078 rtl_w1w0_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5079 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5080 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
c2218925
HW		 5081
5082 RTL_W8(MaxTxPacketSize, EarlySize);
5083
5084 rtl_disable_clock_request(pdev);
5085
5086 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5087 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
c2218925
HW		 5088 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5089 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5090 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5091}
5092
5f886e08
HW		 5093static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5094{
5095 void __iomem *ioaddr = tp->mmio_addr;
5096 static const struct ephy_info e_info_8168f_1[] = {
5097 { 0x06, 0x00c0, 0x0020 },
5098 { 0x08, 0x0001, 0x0002 },
5099 { 0x09, 0x0000, 0x0080 },
5100 { 0x19, 0x0000, 0x0224 }
5101 };
5102
5103 rtl_hw_start_8168f(tp);
5104
fdf6fc06 5105 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5f886e08 5106
fdf6fc06 5107 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5f886e08
HW		 5108
5109 /* Adjust EEE LED frequency */
5110 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5111}
5112
b3d7b2f2
HW		 5113static void rtl_hw_start_8411(struct rtl8169_private *tp)
5114{
b3d7b2f2
HW		 5115 static const struct ephy_info e_info_8168f_1[] = {
5116 { 0x06, 0x00c0, 0x0020 },
5117 { 0x0f, 0xffff, 0x5200 },
5118 { 0x1e, 0x0000, 0x4000 },
5119 { 0x19, 0x0000, 0x0224 }
5120 };
5121
5122 rtl_hw_start_8168f(tp);
5123
fdf6fc06 5124 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
b3d7b2f2 5125
fdf6fc06 5126 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
b3d7b2f2
HW		 5127}
5128
c558386b
HW		 5129static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5130{
5131 void __iomem *ioaddr = tp->mmio_addr;
5132 struct pci_dev *pdev = tp->pci_dev;
5133
5134 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
5135 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5136 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5137 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5138
5139 rtl_csi_access_enable_1(tp);
5140
5141 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5142
5143 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5144 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5145
5146 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5147 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
5148 RTL_W8(MaxTxPacketSize, EarlySize);
5149
5150 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5151 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5152
5153 /* Adjust EEE LED frequency */
5154 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5155
5156 rtl_w1w0_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x02, ERIAR_EXGMAC);
5157}
5158
07ce4064
FR		 5159static void rtl_hw_start_8168(struct net_device *dev)
5160{
2dd99530
FR		 5161 struct rtl8169_private *tp = netdev_priv(dev);
5162 void __iomem *ioaddr = tp->mmio_addr;
5163
5164 RTL_W8(Cfg9346, Cfg9346_Unlock);
5165
f0298f81 5166 RTL_W8(MaxTxPacketSize, TxPacketMax);
2dd99530 5167
6f0333b8 5168 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
2dd99530 5169
0e485150 5170 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 5171
5172 RTL_W16(CPlusCmd, tp->cp_cmd);
5173
0e485150 5174 RTL_W16(IntrMitigate, 0x5151);
2dd99530 5175
0e485150 5176 /* Work around for RxFIFO overflow. */
811fd301 5177 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
da78dbff
FR		 5178 tp->event_slow |= RxFIFOOver | PCSTimeout;
5179 tp->event_slow &= ~RxOverflow;
0e485150
FR		 5180 }
5181
5182 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530 5183
b8363901
FR		 5184 rtl_set_rx_mode(dev);
5185
5186 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
5187 (InterFrameGap << TxInterFrameGapShift));
2dd99530
FR		 5188
5189 RTL_R8(IntrMask);
5190
219a1e9d
FR		 5191 switch (tp->mac_version) {
5192 case RTL_GIGA_MAC_VER_11:
beb1fe18 5193 rtl_hw_start_8168bb(tp);
4804b3b3 5194 break;
219a1e9d
FR		 5195
5196 case RTL_GIGA_MAC_VER_12:
5197 case RTL_GIGA_MAC_VER_17:
beb1fe18 5198 rtl_hw_start_8168bef(tp);
4804b3b3 5199 break;
219a1e9d
FR		 5200
5201 case RTL_GIGA_MAC_VER_18:
beb1fe18 5202 rtl_hw_start_8168cp_1(tp);
4804b3b3 5203 break;
219a1e9d
FR		 5204
5205 case RTL_GIGA_MAC_VER_19:
beb1fe18 5206 rtl_hw_start_8168c_1(tp);
4804b3b3 5207 break;
219a1e9d
FR		 5208
5209 case RTL_GIGA_MAC_VER_20:
beb1fe18 5210 rtl_hw_start_8168c_2(tp);
4804b3b3 5211 break;
219a1e9d 5212
197ff761 5213 case RTL_GIGA_MAC_VER_21:
beb1fe18 5214 rtl_hw_start_8168c_3(tp);
4804b3b3 5215 break;
197ff761 5216
6fb07058 5217 case RTL_GIGA_MAC_VER_22:
beb1fe18 5218 rtl_hw_start_8168c_4(tp);
4804b3b3 5219 break;
6fb07058 5220
ef3386f0 5221 case RTL_GIGA_MAC_VER_23:
beb1fe18 5222 rtl_hw_start_8168cp_2(tp);
4804b3b3 5223 break;
ef3386f0 5224
7f3e3d3a 5225 case RTL_GIGA_MAC_VER_24:
beb1fe18 5226 rtl_hw_start_8168cp_3(tp);
4804b3b3 5227 break;
7f3e3d3a 5228
5b538df9 5229 case RTL_GIGA_MAC_VER_25:
daf9df6d 5230 case RTL_GIGA_MAC_VER_26:
5231 case RTL_GIGA_MAC_VER_27:
beb1fe18 5232 rtl_hw_start_8168d(tp);
4804b3b3 5233 break;
5b538df9 5234
e6de30d6 5235 case RTL_GIGA_MAC_VER_28:
beb1fe18 5236 rtl_hw_start_8168d_4(tp);
4804b3b3 5237 break;
cecb5fd7 5238
4804b3b3 5239 case RTL_GIGA_MAC_VER_31:
beb1fe18 5240 rtl_hw_start_8168dp(tp);
4804b3b3 5241 break;
5242
01dc7fec 5243 case RTL_GIGA_MAC_VER_32:
5244 case RTL_GIGA_MAC_VER_33:
beb1fe18 5245 rtl_hw_start_8168e_1(tp);
70090424
HW		 5246 break;
5247 case RTL_GIGA_MAC_VER_34:
beb1fe18 5248 rtl_hw_start_8168e_2(tp);
01dc7fec 5249 break;
e6de30d6 5250
c2218925
HW		 5251 case RTL_GIGA_MAC_VER_35:
5252 case RTL_GIGA_MAC_VER_36:
beb1fe18 5253 rtl_hw_start_8168f_1(tp);
c2218925
HW		 5254 break;
5255
b3d7b2f2
HW		 5256 case RTL_GIGA_MAC_VER_38:
5257 rtl_hw_start_8411(tp);
5258 break;
5259
c558386b
HW		 5260 case RTL_GIGA_MAC_VER_40:
5261 case RTL_GIGA_MAC_VER_41:
5262 rtl_hw_start_8168g_1(tp);
5263 break;
5264
219a1e9d
FR		 5265 default:
5266 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
5267 dev->name, tp->mac_version);
4804b3b3 5268 break;
219a1e9d 5269 }
2dd99530 5270
0e485150
FR		 5271 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5272
b8363901
FR		 5273 RTL_W8(Cfg9346, Cfg9346_Lock);
5274
2dd99530 5275 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
07ce4064 5276}
1da177e4 5277
2857ffb7
FR		 5278#define R810X_CPCMD_QUIRK_MASK (\
5279 EnableBist | \
5280 Mac_dbgo_oe | \
5281 Force_half_dup | \
5edcc537 5282 Force_rxflow_en | \
2857ffb7
FR		 5283 Force_txflow_en | \
5284 Cxpl_dbg_sel | \
5285 ASF | \
5286 PktCntrDisable | \
d24e9aaf 5287 Mac_dbgo_sel)
2857ffb7 5288
beb1fe18 5289static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
2857ffb7 5290{
beb1fe18
HW		 5291 void __iomem *ioaddr = tp->mmio_addr;
5292 struct pci_dev *pdev = tp->pci_dev;
350f7596 5293 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 5294 { 0x01, 0, 0x6e65 },
5295 { 0x02, 0, 0x091f },
5296 { 0x03, 0, 0xc2f9 },
5297 { 0x06, 0, 0xafb5 },
5298 { 0x07, 0, 0x0e00 },
5299 { 0x19, 0, 0xec80 },
5300 { 0x01, 0, 0x2e65 },
5301 { 0x01, 0, 0x6e65 }
5302 };
5303 u8 cfg1;
5304
beb1fe18 5305 rtl_csi_access_enable_2(tp);
2857ffb7
FR		 5306
5307 RTL_W8(DBG_REG, FIX_NAK_1);
5308
5309 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5310
5311 RTL_W8(Config1,
5312 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5313 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5314
5315 cfg1 = RTL_R8(Config1);
5316 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5317 RTL_W8(Config1, cfg1 & ~LEDS0);
5318
fdf6fc06 5319 rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
2857ffb7
FR		 5320}
5321
beb1fe18 5322static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
2857ffb7 5323{
beb1fe18
HW		 5324 void __iomem *ioaddr = tp->mmio_addr;
5325 struct pci_dev *pdev = tp->pci_dev;
5326
5327 rtl_csi_access_enable_2(tp);
2857ffb7
FR		 5328
5329 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5330
5331 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
5332 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2857ffb7
FR		 5333}
5334
beb1fe18 5335static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
2857ffb7 5336{
beb1fe18 5337 rtl_hw_start_8102e_2(tp);
2857ffb7 5338
fdf6fc06 5339 rtl_ephy_write(tp, 0x03, 0xc2f9);
2857ffb7
FR		 5340}
5341
beb1fe18 5342static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5a5e4443 5343{
beb1fe18 5344 void __iomem *ioaddr = tp->mmio_addr;
5a5e4443
HW		 5345 static const struct ephy_info e_info_8105e_1[] = {
5346 { 0x07, 0, 0x4000 },
5347 { 0x19, 0, 0x0200 },
5348 { 0x19, 0, 0x0020 },
5349 { 0x1e, 0, 0x2000 },
5350 { 0x03, 0, 0x0001 },
5351 { 0x19, 0, 0x0100 },
5352 { 0x19, 0, 0x0004 },
5353 { 0x0a, 0, 0x0020 }
5354 };
5355
cecb5fd7 5356 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5a5e4443
HW		 5357 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5358
cecb5fd7 5359 /* Disable Early Tally Counter */
5a5e4443
HW		 5360 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
5361
5362 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4f6b00e5 5363 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5a5e4443 5364
fdf6fc06 5365 rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
5a5e4443
HW		 5366}
5367
beb1fe18 5368static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5a5e4443 5369{
beb1fe18 5370 rtl_hw_start_8105e_1(tp);
fdf6fc06 5371 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5a5e4443
HW		 5372}
5373
7e18dca1
HW		 5374static void rtl_hw_start_8402(struct rtl8169_private *tp)
5375{
5376 void __iomem *ioaddr = tp->mmio_addr;
5377 static const struct ephy_info e_info_8402[] = {
5378 { 0x19, 0xffff, 0xff64 },
5379 { 0x1e, 0, 0x4000 }
5380 };
5381
5382 rtl_csi_access_enable_2(tp);
5383
5384 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5385 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5386
5387 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5388 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5389
fdf6fc06 5390 rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
7e18dca1
HW		 5391
5392 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
5393
fdf6fc06
FR		 5394 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
5395 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
5396 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5397 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5398 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5399 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5400 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
7e18dca1
HW		 5401}
5402
5598bfe5
HW		 5403static void rtl_hw_start_8106(struct rtl8169_private *tp)
5404{
5405 void __iomem *ioaddr = tp->mmio_addr;
5406
5407 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5408 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5409
5410 RTL_W32(MISC, (RTL_R32(MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5411 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
5412 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
5413}
5414
07ce4064
FR		 5415static void rtl_hw_start_8101(struct net_device *dev)
5416{
cdf1a608
FR		 5417 struct rtl8169_private *tp = netdev_priv(dev);
5418 void __iomem *ioaddr = tp->mmio_addr;
5419 struct pci_dev *pdev = tp->pci_dev;
5420
da78dbff
FR		 5421 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5422 tp->event_slow &= ~RxFIFOOver;
811fd301 5423
cecb5fd7 5424 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
7d7903b2 5425 tp->mac_version == RTL_GIGA_MAC_VER_16)
8200bc72
BH		 5426 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL,
5427 PCI_EXP_DEVCTL_NOSNOOP_EN);
cdf1a608 5428
d24e9aaf
HW		 5429 RTL_W8(Cfg9346, Cfg9346_Unlock);
5430
2857ffb7
FR		 5431 switch (tp->mac_version) {
5432 case RTL_GIGA_MAC_VER_07:
beb1fe18 5433 rtl_hw_start_8102e_1(tp);
2857ffb7
FR		 5434 break;
5435
5436 case RTL_GIGA_MAC_VER_08:
beb1fe18 5437 rtl_hw_start_8102e_3(tp);
2857ffb7
FR		 5438 break;
5439
5440 case RTL_GIGA_MAC_VER_09:
beb1fe18 5441 rtl_hw_start_8102e_2(tp);
2857ffb7 5442 break;
5a5e4443
HW		 5443
5444 case RTL_GIGA_MAC_VER_29:
beb1fe18 5445 rtl_hw_start_8105e_1(tp);
5a5e4443
HW		 5446 break;
5447 case RTL_GIGA_MAC_VER_30:
beb1fe18 5448 rtl_hw_start_8105e_2(tp);
5a5e4443 5449 break;
7e18dca1
HW		 5450
5451 case RTL_GIGA_MAC_VER_37:
5452 rtl_hw_start_8402(tp);
5453 break;
5598bfe5
HW		 5454
5455 case RTL_GIGA_MAC_VER_39:
5456 rtl_hw_start_8106(tp);
5457 break;
cdf1a608
FR		 5458 }
5459
d24e9aaf 5460 RTL_W8(Cfg9346, Cfg9346_Lock);
cdf1a608 5461
f0298f81 5462 RTL_W8(MaxTxPacketSize, TxPacketMax);
cdf1a608 5463
6f0333b8 5464 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
cdf1a608 5465
d24e9aaf 5466 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
cdf1a608
FR		 5467 RTL_W16(CPlusCmd, tp->cp_cmd);
5468
5469 RTL_W16(IntrMitigate, 0x0000);
5470
5471 rtl_set_rx_tx_desc_registers(tp, ioaddr);
5472
5473 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5474 rtl_set_rx_tx_config_registers(tp);
5475
cdf1a608
FR		 5476 RTL_R8(IntrMask);
5477
cdf1a608
FR		 5478 rtl_set_rx_mode(dev);
5479
5480 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
1da177e4
LT		 5481}
5482
5483static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5484{
d58d46b5
FR		 5485 struct rtl8169_private *tp = netdev_priv(dev);
5486
5487 if (new_mtu < ETH_ZLEN ||
5488 new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
1da177e4
LT		 5489 return -EINVAL;
5490
d58d46b5
FR		 5491 if (new_mtu > ETH_DATA_LEN)
5492 rtl_hw_jumbo_enable(tp);
5493 else
5494 rtl_hw_jumbo_disable(tp);
5495
1da177e4 5496 dev->mtu = new_mtu;
350fb32a
MM		 5497 netdev_update_features(dev);
5498
323bb685 5499 return 0;
1da177e4
LT		 5500}
5501
5502static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5503{
95e0918d 5504 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 5505 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5506}
5507
6f0333b8
ED		 5508static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5509 void **data_buff, struct RxDesc *desc)
1da177e4 5510{
48addcc9 5511 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
231aee63 5512 DMA_FROM_DEVICE);
48addcc9 5513
6f0333b8
ED		 5514 kfree(*data_buff);
5515 *data_buff = NULL;
1da177e4
LT		 5516 rtl8169_make_unusable_by_asic(desc);
5517}
5518
5519static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
5520{
5521 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5522
5523 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
5524}
5525
5526static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
5527 u32 rx_buf_sz)
5528{
5529 desc->addr = cpu_to_le64(mapping);
5530 wmb();
5531 rtl8169_mark_to_asic(desc, rx_buf_sz);
5532}
5533
6f0333b8
ED		 5534static inline void *rtl8169_align(void *data)
5535{
5536 return (void *)ALIGN((long)data, 16);
5537}
5538
0ecbe1ca
SG		 5539static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5540 struct RxDesc *desc)
1da177e4 5541{
6f0333b8 5542 void *data;
1da177e4 5543 dma_addr_t mapping;
48addcc9 5544 struct device *d = &tp->pci_dev->dev;
0ecbe1ca 5545 struct net_device *dev = tp->dev;
6f0333b8 5546 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
1da177e4 5547
6f0333b8
ED		 5548 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
5549 if (!data)
5550 return NULL;
e9f63f30 5551
6f0333b8
ED		 5552 if (rtl8169_align(data) != data) {
5553 kfree(data);
5554 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
5555 if (!data)
5556 return NULL;
5557 }
3eafe507 5558
48addcc9 5559 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
231aee63 5560 DMA_FROM_DEVICE);
d827d86b
SG		 5561 if (unlikely(dma_mapping_error(d, mapping))) {
5562 if (net_ratelimit())
5563 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
3eafe507 5564 goto err_out;
d827d86b 5565 }
1da177e4
LT		 5566
5567 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6f0333b8 5568 return data;
3eafe507
SG		 5569
5570err_out:
5571 kfree(data);
5572 return NULL;
1da177e4
LT		 5573}
5574
5575static void rtl8169_rx_clear(struct rtl8169_private *tp)
5576{
07d3f51f 5577 unsigned int i;
1da177e4
LT		 5578
5579 for (i = 0; i < NUM_RX_DESC; i++) {
6f0333b8
ED		 5580 if (tp->Rx_databuff[i]) {
5581 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
1da177e4
LT		 5582 tp->RxDescArray + i);
5583 }
5584 }
5585}
5586
0ecbe1ca 5587static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1da177e4 5588{
0ecbe1ca
SG		 5589 desc->opts1 |= cpu_to_le32(RingEnd);
5590}
5b0384f4 5591
0ecbe1ca
SG		 5592static int rtl8169_rx_fill(struct rtl8169_private *tp)
5593{
5594 unsigned int i;
1da177e4 5595
0ecbe1ca
SG		 5596 for (i = 0; i < NUM_RX_DESC; i++) {
5597 void *data;
4ae47c2d 5598
6f0333b8 5599 if (tp->Rx_databuff[i])
1da177e4 5600 continue;
bcf0bf90 5601
0ecbe1ca 5602 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6f0333b8
ED		 5603 if (!data) {
5604 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
0ecbe1ca 5605 goto err_out;
6f0333b8
ED		 5606 }
5607 tp->Rx_databuff[i] = data;
1da177e4 5608 }
1da177e4 5609
0ecbe1ca
SG		 5610 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5611 return 0;
5612
5613err_out:
5614 rtl8169_rx_clear(tp);
5615 return -ENOMEM;
1da177e4
LT		 5616}
5617
1da177e4
LT		 5618static int rtl8169_init_ring(struct net_device *dev)
5619{
5620 struct rtl8169_private *tp = netdev_priv(dev);
5621
5622 rtl8169_init_ring_indexes(tp);
5623
5624 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
6f0333b8 5625 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
1da177e4 5626
0ecbe1ca 5627 return rtl8169_rx_fill(tp);
1da177e4
LT		 5628}
5629
48addcc9 5630static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
1da177e4
LT		 5631 struct TxDesc *desc)
5632{
5633 unsigned int len = tx_skb->len;
5634
48addcc9
SG		 5635 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5636
1da177e4
LT		 5637 desc->opts1 = 0x00;
5638 desc->opts2 = 0x00;
5639 desc->addr = 0x00;
5640 tx_skb->len = 0;
5641}
5642
3eafe507
SG		 5643static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5644 unsigned int n)
1da177e4
LT		 5645{
5646 unsigned int i;
5647
3eafe507
SG		 5648 for (i = 0; i < n; i++) {
5649 unsigned int entry = (start + i) % NUM_TX_DESC;
1da177e4
LT		 5650 struct ring_info *tx_skb = tp->tx_skb + entry;
5651 unsigned int len = tx_skb->len;
5652
5653 if (len) {
5654 struct sk_buff *skb = tx_skb->skb;
5655
48addcc9 5656 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
1da177e4
LT		 5657 tp->TxDescArray + entry);
5658 if (skb) {
cac4b22f 5659 tp->dev->stats.tx_dropped++;
1da177e4
LT		 5660 dev_kfree_skb(skb);
5661 tx_skb->skb = NULL;
5662 }
1da177e4
LT		 5663 }
5664 }
3eafe507
SG		 5665}
5666
5667static void rtl8169_tx_clear(struct rtl8169_private *tp)
5668{
5669 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
1da177e4
LT		 5670 tp->cur_tx = tp->dirty_tx = 0;
5671}
5672
4422bcd4 5673static void rtl_reset_work(struct rtl8169_private *tp)
1da177e4 5674{
c4028958 5675 struct net_device *dev = tp->dev;
56de414c 5676 int i;
1da177e4 5677
da78dbff
FR		 5678 napi_disable(&tp->napi);
5679 netif_stop_queue(dev);
5680 synchronize_sched();
1da177e4 5681
c7c2c39b 5682 rtl8169_hw_reset(tp);
5683
56de414c
FR		 5684 for (i = 0; i < NUM_RX_DESC; i++)
5685 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
5686
1da177e4 5687 rtl8169_tx_clear(tp);
c7c2c39b 5688 rtl8169_init_ring_indexes(tp);
1da177e4 5689
da78dbff 5690 napi_enable(&tp->napi);
56de414c
FR		 5691 rtl_hw_start(dev);
5692 netif_wake_queue(dev);
5693 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1da177e4
LT		 5694}
5695
5696static void rtl8169_tx_timeout(struct net_device *dev)
5697{
da78dbff
FR		 5698 struct rtl8169_private *tp = netdev_priv(dev);
5699
5700 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 5701}
5702
5703static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2b7b4318 5704 u32 *opts)
1da177e4
LT		 5705{
5706 struct skb_shared_info *info = skb_shinfo(skb);
5707 unsigned int cur_frag, entry;
a6343afb 5708 struct TxDesc * uninitialized_var(txd);
48addcc9 5709 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 5710
5711 entry = tp->cur_tx;
5712 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
9e903e08 5713 const skb_frag_t *frag = info->frags + cur_frag;
1da177e4
LT		 5714 dma_addr_t mapping;
5715 u32 status, len;
5716 void *addr;
5717
5718 entry = (entry + 1) % NUM_TX_DESC;
5719
5720 txd = tp->TxDescArray + entry;
9e903e08 5721 len = skb_frag_size(frag);
929f6189 5722 addr = skb_frag_address(frag);
48addcc9 5723 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
d827d86b
SG		 5724 if (unlikely(dma_mapping_error(d, mapping))) {
5725 if (net_ratelimit())
5726 netif_err(tp, drv, tp->dev,
5727 "Failed to map TX fragments DMA!\n");
3eafe507 5728 goto err_out;
d827d86b 5729 }
1da177e4 5730
cecb5fd7 5731 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318
FR		 5732 status = opts[0] | len |
5733 (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 5734
5735 txd->opts1 = cpu_to_le32(status);
2b7b4318 5736 txd->opts2 = cpu_to_le32(opts[1]);
1da177e4
LT		 5737 txd->addr = cpu_to_le64(mapping);
5738
5739 tp->tx_skb[entry].len = len;
5740 }
5741
5742 if (cur_frag) {
5743 tp->tx_skb[entry].skb = skb;
5744 txd->opts1 |= cpu_to_le32(LastFrag);
5745 }
5746
5747 return cur_frag;
3eafe507
SG		 5748
5749err_out:
5750 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5751 return -EIO;
1da177e4
LT		 5752}
5753
2b7b4318
FR		 5754static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
5755 struct sk_buff *skb, u32 *opts)
1da177e4 5756{
2b7b4318 5757 const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
350fb32a 5758 u32 mss = skb_shinfo(skb)->gso_size;
2b7b4318 5759 int offset = info->opts_offset;
350fb32a 5760
2b7b4318
FR		 5761 if (mss) {
5762 opts[0] |= TD_LSO;
5763 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
5764 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 5765 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 5766
5767 if (ip->protocol == IPPROTO_TCP)
2b7b4318 5768 opts[offset] |= info->checksum.tcp;
1da177e4 5769 else if (ip->protocol == IPPROTO_UDP)
2b7b4318
FR		 5770 opts[offset] |= info->checksum.udp;
5771 else
5772 WARN_ON_ONCE(1);
1da177e4 5773 }
1da177e4
LT		 5774}
5775
61357325
SH		 5776static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5777 struct net_device *dev)
1da177e4
LT		 5778{
5779 struct rtl8169_private *tp = netdev_priv(dev);
3eafe507 5780 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
1da177e4
LT		 5781 struct TxDesc *txd = tp->TxDescArray + entry;
5782 void __iomem *ioaddr = tp->mmio_addr;
48addcc9 5783 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 5784 dma_addr_t mapping;
5785 u32 status, len;
2b7b4318 5786 u32 opts[2];
3eafe507 5787 int frags;
5b0384f4 5788
477206a0 5789 if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
bf82c189 5790 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
3eafe507 5791 goto err_stop_0;
1da177e4
LT		 5792 }
5793
5794 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3eafe507
SG		 5795 goto err_stop_0;
5796
5797 len = skb_headlen(skb);
48addcc9 5798 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
d827d86b
SG		 5799 if (unlikely(dma_mapping_error(d, mapping))) {
5800 if (net_ratelimit())
5801 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
3eafe507 5802 goto err_dma_0;
d827d86b 5803 }
3eafe507
SG		 5804
5805 tp->tx_skb[entry].len = len;
5806 txd->addr = cpu_to_le64(mapping);
1da177e4 5807
2b7b4318
FR		 5808 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
5809 opts[0] = DescOwn;
1da177e4 5810
2b7b4318
FR		 5811 rtl8169_tso_csum(tp, skb, opts);
5812
5813 frags = rtl8169_xmit_frags(tp, skb, opts);
3eafe507
SG		 5814 if (frags < 0)
5815 goto err_dma_1;
5816 else if (frags)
2b7b4318 5817 opts[0] |= FirstFrag;
3eafe507 5818 else {
2b7b4318 5819 opts[0] |= FirstFrag | LastFrag;
1da177e4
LT		 5820 tp->tx_skb[entry].skb = skb;
5821 }
5822
2b7b4318
FR		 5823 txd->opts2 = cpu_to_le32(opts[1]);
5824
5047fb5d
RC		 5825 skb_tx_timestamp(skb);
5826
1da177e4
LT		 5827 wmb();
5828
cecb5fd7 5829 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318 5830 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 5831 txd->opts1 = cpu_to_le32(status);
5832
1da177e4
LT		 5833 tp->cur_tx += frags + 1;
5834
4c020a96 5835 wmb();
1da177e4 5836
cecb5fd7 5837 RTL_W8(TxPoll, NPQ);
1da177e4 5838
da78dbff
FR		 5839 mmiowb();
5840
477206a0 5841 if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
ae1f23fb
FR		 5842 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
5843 * not miss a ring update when it notices a stopped queue.
5844 */
5845 smp_wmb();
1da177e4 5846 netif_stop_queue(dev);
ae1f23fb
FR		 5847 /* Sync with rtl_tx:
5848 * - publish queue status and cur_tx ring index (write barrier)
5849 * - refresh dirty_tx ring index (read barrier).
5850 * May the current thread have a pessimistic view of the ring
5851 * status and forget to wake up queue, a racing rtl_tx thread
5852 * can't.
5853 */
1e874e04 5854 smp_mb();
477206a0 5855 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
1da177e4
LT		 5856 netif_wake_queue(dev);
5857 }
5858
61357325 5859 return NETDEV_TX_OK;
1da177e4 5860
3eafe507 5861err_dma_1:
48addcc9 5862 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
3eafe507
SG		 5863err_dma_0:
5864 dev_kfree_skb(skb);
5865 dev->stats.tx_dropped++;
5866 return NETDEV_TX_OK;
5867
5868err_stop_0:
1da177e4 5869 netif_stop_queue(dev);
cebf8cc7 5870 dev->stats.tx_dropped++;
61357325 5871 return NETDEV_TX_BUSY;
1da177e4
LT		 5872}
5873
5874static void rtl8169_pcierr_interrupt(struct net_device *dev)
5875{
5876 struct rtl8169_private *tp = netdev_priv(dev);
5877 struct pci_dev *pdev = tp->pci_dev;
1da177e4
LT		 5878 u16 pci_status, pci_cmd;
5879
5880 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5881 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5882
bf82c189
JP		 5883 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5884 pci_cmd, pci_status);
1da177e4
LT		 5885
5886 /*
5887 * The recovery sequence below admits a very elaborated explanation:
5888 * - it seems to work;
d03902b8
FR		 5889 * - I did not see what else could be done;
5890 * - it makes iop3xx happy.
1da177e4
LT		 5891 *
5892 * Feel free to adjust to your needs.
5893 */
a27993f3 5894 if (pdev->broken_parity_status)
d03902b8
FR		 5895 pci_cmd &= ~PCI_COMMAND_PARITY;
5896 else
5897 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5898
5899 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 5900
5901 pci_write_config_word(pdev, PCI_STATUS,
5902 pci_status & (PCI_STATUS_DETECTED_PARITY |
5903 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5904 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5905
5906 /* The infamous DAC f*ckup only happens at boot time */
5907 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
e6de30d6 5908 void __iomem *ioaddr = tp->mmio_addr;
5909
bf82c189 5910 netif_info(tp, intr, dev, "disabling PCI DAC\n");
1da177e4
LT		 5911 tp->cp_cmd &= ~PCIDAC;
5912 RTL_W16(CPlusCmd, tp->cp_cmd);
5913 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 5914 }
5915
e6de30d6 5916 rtl8169_hw_reset(tp);
d03902b8 5917
98ddf986 5918 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 5919}
5920
da78dbff 5921static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
1da177e4
LT		 5922{
5923 unsigned int dirty_tx, tx_left;
5924
1da177e4
LT		 5925 dirty_tx = tp->dirty_tx;
5926 smp_rmb();
5927 tx_left = tp->cur_tx - dirty_tx;
5928
5929 while (tx_left > 0) {
5930 unsigned int entry = dirty_tx % NUM_TX_DESC;
5931 struct ring_info *tx_skb = tp->tx_skb + entry;
1da177e4
LT		 5932 u32 status;
5933
5934 rmb();
5935 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5936 if (status & DescOwn)
5937 break;
5938
48addcc9
SG		 5939 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5940 tp->TxDescArray + entry);
1da177e4 5941 if (status & LastFrag) {
17bcb684
FR		 5942 u64_stats_update_begin(&tp->tx_stats.syncp);
5943 tp->tx_stats.packets++;
5944 tp->tx_stats.bytes += tx_skb->skb->len;
5945 u64_stats_update_end(&tp->tx_stats.syncp);
5946 dev_kfree_skb(tx_skb->skb);
1da177e4
LT		 5947 tx_skb->skb = NULL;
5948 }
5949 dirty_tx++;
5950 tx_left--;
5951 }
5952
5953 if (tp->dirty_tx != dirty_tx) {
5954 tp->dirty_tx = dirty_tx;
ae1f23fb
FR		 5955 /* Sync with rtl8169_start_xmit:
5956 * - publish dirty_tx ring index (write barrier)
5957 * - refresh cur_tx ring index and queue status (read barrier)
5958 * May the current thread miss the stopped queue condition,
5959 * a racing xmit thread can only have a right view of the
5960 * ring status.
5961 */
1e874e04 5962 smp_mb();
1da177e4 5963 if (netif_queue_stopped(dev) &&
477206a0 5964 TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
1da177e4
LT		 5965 netif_wake_queue(dev);
5966 }
d78ae2dc
FR		 5967 /*
5968 * 8168 hack: TxPoll requests are lost when the Tx packets are
5969 * too close. Let's kick an extra TxPoll request when a burst
5970 * of start_xmit activity is detected (if it is not detected,
5971 * it is slow enough). -- FR
5972 */
da78dbff
FR		 5973 if (tp->cur_tx != dirty_tx) {
5974 void __iomem *ioaddr = tp->mmio_addr;
5975
d78ae2dc 5976 RTL_W8(TxPoll, NPQ);
da78dbff 5977 }
1da177e4
LT		 5978 }
5979}
5980
126fa4b9
FR		 5981static inline int rtl8169_fragmented_frame(u32 status)
5982{
5983 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
5984}
5985
adea1ac7 5986static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
1da177e4 5987{
1da177e4
LT		 5988 u32 status = opts1 & RxProtoMask;
5989
5990 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
d5d3ebe3 5991 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
1da177e4
LT		 5992 skb->ip_summed = CHECKSUM_UNNECESSARY;
5993 else
bc8acf2c 5994 skb_checksum_none_assert(skb);
1da177e4
LT		 5995}
5996
6f0333b8
ED		 5997static struct sk_buff *rtl8169_try_rx_copy(void *data,
5998 struct rtl8169_private *tp,
5999 int pkt_size,
6000 dma_addr_t addr)
1da177e4 6001{
b449655f 6002 struct sk_buff *skb;
48addcc9 6003 struct device *d = &tp->pci_dev->dev;
b449655f 6004
6f0333b8 6005 data = rtl8169_align(data);
48addcc9 6006 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6f0333b8
ED		 6007 prefetch(data);
6008 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
6009 if (skb)
6010 memcpy(skb->data, data, pkt_size);
48addcc9
SG		 6011 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
6012
6f0333b8 6013 return skb;
1da177e4
LT		 6014}
6015
da78dbff 6016static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
1da177e4
LT		 6017{
6018 unsigned int cur_rx, rx_left;
6f0333b8 6019 unsigned int count;
1da177e4 6020
1da177e4
LT		 6021 cur_rx = tp->cur_rx;
6022 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
865c652d 6023 rx_left = min(rx_left, budget);
1da177e4 6024
4dcb7d33 6025 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 6026 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 6027 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 6028 u32 status;
6029
6030 rmb();
e03f33af 6031 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
1da177e4
LT		 6032
6033 if (status & DescOwn)
6034 break;
4dcb7d33 6035 if (unlikely(status & RxRES)) {
bf82c189
JP		 6036 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6037 status);
cebf8cc7 6038 dev->stats.rx_errors++;
1da177e4 6039 if (status & (RxRWT | RxRUNT))
cebf8cc7 6040 dev->stats.rx_length_errors++;
1da177e4 6041 if (status & RxCRC)
cebf8cc7 6042 dev->stats.rx_crc_errors++;
9dccf611 6043 if (status & RxFOVF) {
da78dbff 6044 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
cebf8cc7 6045 dev->stats.rx_fifo_errors++;
9dccf611 6046 }
6bbe021d
BG		 6047 if ((status & (RxRUNT | RxCRC)) &&
6048 !(status & (RxRWT | RxFOVF)) &&
6049 (dev->features & NETIF_F_RXALL))
6050 goto process_pkt;
6051
6f0333b8 6052 rtl8169_mark_to_asic(desc, rx_buf_sz);
1da177e4 6053 } else {
6f0333b8 6054 struct sk_buff *skb;
6bbe021d
BG		 6055 dma_addr_t addr;
6056 int pkt_size;
6057
6058process_pkt:
6059 addr = le64_to_cpu(desc->addr);
79d0c1d2
BG		 6060 if (likely(!(dev->features & NETIF_F_RXFCS)))
6061 pkt_size = (status & 0x00003fff) - 4;
6062 else
6063 pkt_size = status & 0x00003fff;
1da177e4 6064
126fa4b9
FR		 6065 /*
6066 * The driver does not support incoming fragmented
6067 * frames. They are seen as a symptom of over-mtu
6068 * sized frames.
6069 */
6070 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 6071 dev->stats.rx_dropped++;
6072 dev->stats.rx_length_errors++;
6f0333b8 6073 rtl8169_mark_to_asic(desc, rx_buf_sz);
4dcb7d33 6074 continue;
126fa4b9
FR		 6075 }
6076
6f0333b8
ED		 6077 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6078 tp, pkt_size, addr);
6079 rtl8169_mark_to_asic(desc, rx_buf_sz);
6080 if (!skb) {
6081 dev->stats.rx_dropped++;
6082 continue;
1da177e4
LT		 6083 }
6084
adea1ac7 6085 rtl8169_rx_csum(skb, status);
1da177e4
LT		 6086 skb_put(skb, pkt_size);
6087 skb->protocol = eth_type_trans(skb, dev);
6088
7a8fc77b
FR		 6089 rtl8169_rx_vlan_tag(desc, skb);
6090
56de414c 6091 napi_gro_receive(&tp->napi, skb);
1da177e4 6092
8027aa24
JW		 6093 u64_stats_update_begin(&tp->rx_stats.syncp);
6094 tp->rx_stats.packets++;
6095 tp->rx_stats.bytes += pkt_size;
6096 u64_stats_update_end(&tp->rx_stats.syncp);
1da177e4 6097 }
6dccd16b
FR		 6098
6099 /* Work around for AMD plateform. */
95e0918d 6100 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
6dccd16b
FR		 6101 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
6102 desc->opts2 = 0;
6103 cur_rx++;
6104 }
1da177e4
LT		 6105 }
6106
6107 count = cur_rx - tp->cur_rx;
6108 tp->cur_rx = cur_rx;
6109
6f0333b8 6110 tp->dirty_rx += count;
1da177e4
LT		 6111
6112 return count;
6113}
6114
07d3f51f 6115static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 6116{
07d3f51f 6117 struct net_device *dev = dev_instance;
1da177e4 6118 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 6119 int handled = 0;
9085cdfa 6120 u16 status;
1da177e4 6121
9085cdfa 6122 status = rtl_get_events(tp);
da78dbff
FR		 6123 if (status && status != 0xffff) {
6124 status &= RTL_EVENT_NAPI | tp->event_slow;
6125 if (status) {
6126 handled = 1;
1da177e4 6127
da78dbff
FR		 6128 rtl_irq_disable(tp);
6129 napi_schedule(&tp->napi);
f11a377b 6130 }
da78dbff
FR		 6131 }
6132 return IRQ_RETVAL(handled);
6133}
1da177e4 6134
da78dbff
FR		 6135/*
6136 * Workqueue context.
6137 */
6138static void rtl_slow_event_work(struct rtl8169_private *tp)
6139{
6140 struct net_device *dev = tp->dev;
6141 u16 status;
6142
6143 status = rtl_get_events(tp) & tp->event_slow;
6144 rtl_ack_events(tp, status);
1da177e4 6145
da78dbff
FR		 6146 if (unlikely(status & RxFIFOOver)) {
6147 switch (tp->mac_version) {
6148 /* Work around for rx fifo overflow */
6149 case RTL_GIGA_MAC_VER_11:
6150 netif_stop_queue(dev);
934714d0
FR		 6151 /* XXX - Hack alert. See rtl_task(). */
6152 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
da78dbff 6153 default:
f11a377b
DD		 6154 break;
6155 }
da78dbff 6156 }
1da177e4 6157
da78dbff
FR		 6158 if (unlikely(status & SYSErr))
6159 rtl8169_pcierr_interrupt(dev);
0e485150 6160
da78dbff
FR		 6161 if (status & LinkChg)
6162 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
1da177e4 6163
7dbb4918 6164 rtl_irq_enable_all(tp);
1da177e4
LT		 6165}
6166
4422bcd4
FR		 6167static void rtl_task(struct work_struct *work)
6168{
da78dbff
FR		 6169 static const struct {
6170 int bitnr;
6171 void (*action)(struct rtl8169_private *);
6172 } rtl_work[] = {
934714d0 6173 /* XXX - keep rtl_slow_event_work() as first element. */
da78dbff
FR		 6174 { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work },
6175 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
6176 { RTL_FLAG_TASK_PHY_PENDING, rtl_phy_work }
6177 };
4422bcd4
FR		 6178 struct rtl8169_private *tp =
6179 container_of(work, struct rtl8169_private, wk.work);
da78dbff
FR		 6180 struct net_device *dev = tp->dev;
6181 int i;
6182
6183 rtl_lock_work(tp);
6184
6c4a70c5
FR		 6185 if (!netif_running(dev) ||
6186 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
da78dbff
FR		 6187 goto out_unlock;
6188
6189 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6190 bool pending;
6191
da78dbff 6192 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
da78dbff
FR		 6193 if (pending)
6194 rtl_work[i].action(tp);
6195 }
4422bcd4 6196
da78dbff
FR		 6197out_unlock:
6198 rtl_unlock_work(tp);
4422bcd4
FR		 6199}
6200
bea3348e 6201static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 6202{
bea3348e
SH		 6203 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6204 struct net_device *dev = tp->dev;
da78dbff
FR		 6205 u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
6206 int work_done= 0;
6207 u16 status;
6208
6209 status = rtl_get_events(tp);
6210 rtl_ack_events(tp, status & ~tp->event_slow);
6211
6212 if (status & RTL_EVENT_NAPI_RX)
6213 work_done = rtl_rx(dev, tp, (u32) budget);
6214
6215 if (status & RTL_EVENT_NAPI_TX)
6216 rtl_tx(dev, tp);
1da177e4 6217
da78dbff
FR		 6218 if (status & tp->event_slow) {
6219 enable_mask &= ~tp->event_slow;
6220
6221 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
6222 }
1da177e4 6223
bea3348e 6224 if (work_done < budget) {
288379f0 6225 napi_complete(napi);
f11a377b 6226
da78dbff
FR		 6227 rtl_irq_enable(tp, enable_mask);
6228 mmiowb();
1da177e4
LT		 6229 }
6230
bea3348e 6231 return work_done;
1da177e4 6232}
1da177e4 6233
523a6094
FR		 6234static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
6235{
6236 struct rtl8169_private *tp = netdev_priv(dev);
6237
6238 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6239 return;
6240
6241 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
6242 RTL_W32(RxMissed, 0);
6243}
6244
1da177e4
LT		 6245static void rtl8169_down(struct net_device *dev)
6246{
6247 struct rtl8169_private *tp = netdev_priv(dev);
6248 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 6249
4876cc1e 6250 del_timer_sync(&tp->timer);
1da177e4 6251
93dd79e8 6252 napi_disable(&tp->napi);
da78dbff 6253 netif_stop_queue(dev);
1da177e4 6254
92fc43b4 6255 rtl8169_hw_reset(tp);
323bb685
SG		 6256 /*
6257 * At this point device interrupts can not be enabled in any function,
209e5ac8
FR		 6258 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6259 * and napi is disabled (rtl8169_poll).
323bb685 6260 */
523a6094 6261 rtl8169_rx_missed(dev, ioaddr);
1da177e4 6262
1da177e4 6263 /* Give a racing hard_start_xmit a few cycles to complete. */
da78dbff 6264 synchronize_sched();
1da177e4 6265
1da177e4
LT		 6266 rtl8169_tx_clear(tp);
6267
6268 rtl8169_rx_clear(tp);
065c27c1 6269
6270 rtl_pll_power_down(tp);
1da177e4
LT		 6271}
6272
6273static int rtl8169_close(struct net_device *dev)
6274{
6275 struct rtl8169_private *tp = netdev_priv(dev);
6276 struct pci_dev *pdev = tp->pci_dev;
6277
e1759441
RW		 6278 pm_runtime_get_sync(&pdev->dev);
6279
cecb5fd7 6280 /* Update counters before going down */
355423d0
IV		 6281 rtl8169_update_counters(dev);
6282
da78dbff 6283 rtl_lock_work(tp);
6c4a70c5 6284 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
da78dbff 6285
1da177e4 6286 rtl8169_down(dev);
da78dbff 6287 rtl_unlock_work(tp);
1da177e4 6288
92a7c4e7 6289 free_irq(pdev->irq, dev);
1da177e4 6290
82553bb6
SG		 6291 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6292 tp->RxPhyAddr);
6293 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6294 tp->TxPhyAddr);
1da177e4
LT		 6295 tp->TxDescArray = NULL;
6296 tp->RxDescArray = NULL;
6297
e1759441
RW		 6298 pm_runtime_put_sync(&pdev->dev);
6299
1da177e4
LT		 6300 return 0;
6301}
6302
dc1c00ce
FR		 6303#ifdef CONFIG_NET_POLL_CONTROLLER
6304static void rtl8169_netpoll(struct net_device *dev)
6305{
6306 struct rtl8169_private *tp = netdev_priv(dev);
6307
6308 rtl8169_interrupt(tp->pci_dev->irq, dev);
6309}
6310#endif
6311
df43ac78
FR		 6312static int rtl_open(struct net_device *dev)
6313{
6314 struct rtl8169_private *tp = netdev_priv(dev);
6315 void __iomem *ioaddr = tp->mmio_addr;
6316 struct pci_dev *pdev = tp->pci_dev;
6317 int retval = -ENOMEM;
6318
6319 pm_runtime_get_sync(&pdev->dev);
6320
6321 /*
e75d6606 6322 * Rx and Tx descriptors needs 256 bytes alignment.
df43ac78
FR		 6323 * dma_alloc_coherent provides more.
6324 */
6325 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6326 &tp->TxPhyAddr, GFP_KERNEL);
6327 if (!tp->TxDescArray)
6328 goto err_pm_runtime_put;
6329
6330 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6331 &tp->RxPhyAddr, GFP_KERNEL);
6332 if (!tp->RxDescArray)
6333 goto err_free_tx_0;
6334
6335 retval = rtl8169_init_ring(dev);
6336 if (retval < 0)
6337 goto err_free_rx_1;
6338
6339 INIT_WORK(&tp->wk.work, rtl_task);
6340
6341 smp_mb();
6342
6343 rtl_request_firmware(tp);
6344
92a7c4e7 6345 retval = request_irq(pdev->irq, rtl8169_interrupt,
df43ac78
FR		 6346 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
6347 dev->name, dev);
6348 if (retval < 0)
6349 goto err_release_fw_2;
6350
6351 rtl_lock_work(tp);
6352
6353 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6354
6355 napi_enable(&tp->napi);
6356
6357 rtl8169_init_phy(dev, tp);
6358
6359 __rtl8169_set_features(dev, dev->features);
6360
6361 rtl_pll_power_up(tp);
6362
6363 rtl_hw_start(dev);
6364
6365 netif_start_queue(dev);
6366
6367 rtl_unlock_work(tp);
6368
6369 tp->saved_wolopts = 0;
6370 pm_runtime_put_noidle(&pdev->dev);
6371
6372 rtl8169_check_link_status(dev, tp, ioaddr);
6373out:
6374 return retval;
6375
6376err_release_fw_2:
6377 rtl_release_firmware(tp);
6378 rtl8169_rx_clear(tp);
6379err_free_rx_1:
6380 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6381 tp->RxPhyAddr);
6382 tp->RxDescArray = NULL;
6383err_free_tx_0:
6384 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6385 tp->TxPhyAddr);
6386 tp->TxDescArray = NULL;
6387err_pm_runtime_put:
6388 pm_runtime_put_noidle(&pdev->dev);
6389 goto out;
6390}
6391
8027aa24
JW		 6392static struct rtnl_link_stats64 *
6393rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
1da177e4
LT		 6394{
6395 struct rtl8169_private *tp = netdev_priv(dev);
6396 void __iomem *ioaddr = tp->mmio_addr;
8027aa24 6397 unsigned int start;
1da177e4 6398
da78dbff 6399 if (netif_running(dev))
523a6094 6400 rtl8169_rx_missed(dev, ioaddr);
5b0384f4 6401
8027aa24
JW		 6402 do {
6403 start = u64_stats_fetch_begin_bh(&tp->rx_stats.syncp);
6404 stats->rx_packets = tp->rx_stats.packets;
6405 stats->rx_bytes = tp->rx_stats.bytes;
6406 } while (u64_stats_fetch_retry_bh(&tp->rx_stats.syncp, start));
6407
6408
6409 do {
6410 start = u64_stats_fetch_begin_bh(&tp->tx_stats.syncp);
6411 stats->tx_packets = tp->tx_stats.packets;
6412 stats->tx_bytes = tp->tx_stats.bytes;
6413 } while (u64_stats_fetch_retry_bh(&tp->tx_stats.syncp, start));
6414
6415 stats->rx_dropped = dev->stats.rx_dropped;
6416 stats->tx_dropped = dev->stats.tx_dropped;
6417 stats->rx_length_errors = dev->stats.rx_length_errors;
6418 stats->rx_errors = dev->stats.rx_errors;
6419 stats->rx_crc_errors = dev->stats.rx_crc_errors;
6420 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
6421 stats->rx_missed_errors = dev->stats.rx_missed_errors;
6422
6423 return stats;
1da177e4
LT		 6424}
6425
861ab440 6426static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 6427{
065c27c1 6428 struct rtl8169_private *tp = netdev_priv(dev);
6429
5d06a99f 6430 if (!netif_running(dev))
861ab440 6431 return;
5d06a99f
FR		 6432
6433 netif_device_detach(dev);
6434 netif_stop_queue(dev);
da78dbff
FR		 6435
6436 rtl_lock_work(tp);
6437 napi_disable(&tp->napi);
6c4a70c5 6438 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
da78dbff
FR		 6439 rtl_unlock_work(tp);
6440
6441 rtl_pll_power_down(tp);
861ab440
RW		 6442}
6443
6444#ifdef CONFIG_PM
6445
6446static int rtl8169_suspend(struct device *device)
6447{
6448 struct pci_dev *pdev = to_pci_dev(device);
6449 struct net_device *dev = pci_get_drvdata(pdev);
5d06a99f 6450
861ab440 6451 rtl8169_net_suspend(dev);
1371fa6d 6452
5d06a99f
FR		 6453 return 0;
6454}
6455
e1759441
RW		 6456static void __rtl8169_resume(struct net_device *dev)
6457{
065c27c1 6458 struct rtl8169_private *tp = netdev_priv(dev);
6459
e1759441 6460 netif_device_attach(dev);
065c27c1 6461
6462 rtl_pll_power_up(tp);
6463
cff4c162
AS		 6464 rtl_lock_work(tp);
6465 napi_enable(&tp->napi);
6c4a70c5 6466 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
cff4c162 6467 rtl_unlock_work(tp);
da78dbff 6468
98ddf986 6469 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
e1759441
RW		 6470}
6471
861ab440 6472static int rtl8169_resume(struct device *device)
5d06a99f 6473{
861ab440 6474 struct pci_dev *pdev = to_pci_dev(device);
5d06a99f 6475 struct net_device *dev = pci_get_drvdata(pdev);
fccec10b
SG		 6476 struct rtl8169_private *tp = netdev_priv(dev);
6477
6478 rtl8169_init_phy(dev, tp);
5d06a99f 6479
e1759441
RW		 6480 if (netif_running(dev))
6481 __rtl8169_resume(dev);
5d06a99f 6482
e1759441
RW		 6483 return 0;
6484}
6485
6486static int rtl8169_runtime_suspend(struct device *device)
6487{
6488 struct pci_dev *pdev = to_pci_dev(device);
6489 struct net_device *dev = pci_get_drvdata(pdev);
6490 struct rtl8169_private *tp = netdev_priv(dev);
6491
6492 if (!tp->TxDescArray)
6493 return 0;
6494
da78dbff 6495 rtl_lock_work(tp);
e1759441
RW		 6496 tp->saved_wolopts = __rtl8169_get_wol(tp);
6497 __rtl8169_set_wol(tp, WAKE_ANY);
da78dbff 6498 rtl_unlock_work(tp);
e1759441
RW		 6499
6500 rtl8169_net_suspend(dev);
6501
6502 return 0;
6503}
6504
6505static int rtl8169_runtime_resume(struct device *device)
6506{
6507 struct pci_dev *pdev = to_pci_dev(device);
6508 struct net_device *dev = pci_get_drvdata(pdev);
6509 struct rtl8169_private *tp = netdev_priv(dev);
6510
6511 if (!tp->TxDescArray)
6512 return 0;
6513
da78dbff 6514 rtl_lock_work(tp);
e1759441
RW		 6515 __rtl8169_set_wol(tp, tp->saved_wolopts);
6516 tp->saved_wolopts = 0;
da78dbff 6517 rtl_unlock_work(tp);
e1759441 6518
fccec10b
SG		 6519 rtl8169_init_phy(dev, tp);
6520
e1759441 6521 __rtl8169_resume(dev);
5d06a99f 6522
5d06a99f
FR		 6523 return 0;
6524}
6525
e1759441
RW		 6526static int rtl8169_runtime_idle(struct device *device)
6527{
6528 struct pci_dev *pdev = to_pci_dev(device);
6529 struct net_device *dev = pci_get_drvdata(pdev);
6530 struct rtl8169_private *tp = netdev_priv(dev);
6531
e4fbce74 6532 return tp->TxDescArray ? -EBUSY : 0;
e1759441
RW		 6533}
6534
47145210 6535static const struct dev_pm_ops rtl8169_pm_ops = {
cecb5fd7
FR		 6536 .suspend = rtl8169_suspend,
6537 .resume = rtl8169_resume,
6538 .freeze = rtl8169_suspend,
6539 .thaw = rtl8169_resume,
6540 .poweroff = rtl8169_suspend,
6541 .restore = rtl8169_resume,
6542 .runtime_suspend = rtl8169_runtime_suspend,
6543 .runtime_resume = rtl8169_runtime_resume,
6544 .runtime_idle = rtl8169_runtime_idle,
861ab440
RW		 6545};
6546
6547#define RTL8169_PM_OPS (&rtl8169_pm_ops)
6548
6549#else /* !CONFIG_PM */
6550
6551#define RTL8169_PM_OPS NULL
6552
6553#endif /* !CONFIG_PM */
6554
649b3b8c 6555static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6556{
6557 void __iomem *ioaddr = tp->mmio_addr;
6558
6559 /* WoL fails with 8168b when the receiver is disabled. */
6560 switch (tp->mac_version) {
6561 case RTL_GIGA_MAC_VER_11:
6562 case RTL_GIGA_MAC_VER_12:
6563 case RTL_GIGA_MAC_VER_17:
6564 pci_clear_master(tp->pci_dev);
6565
6566 RTL_W8(ChipCmd, CmdRxEnb);
6567 /* PCI commit */
6568 RTL_R8(ChipCmd);
6569 break;
6570 default:
6571 break;
6572 }
6573}
6574
1765f95d
FR		 6575static void rtl_shutdown(struct pci_dev *pdev)
6576{
861ab440 6577 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 6578 struct rtl8169_private *tp = netdev_priv(dev);
2a15cd2f 6579 struct device *d = &pdev->dev;
6580
6581 pm_runtime_get_sync(d);
861ab440
RW		 6582
6583 rtl8169_net_suspend(dev);
1765f95d 6584
cecb5fd7 6585 /* Restore original MAC address */
cc098dc7
IV		 6586 rtl_rar_set(tp, dev->perm_addr);
6587
92fc43b4 6588 rtl8169_hw_reset(tp);
4bb3f522 6589
861ab440 6590 if (system_state == SYSTEM_POWER_OFF) {
649b3b8c 6591 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
6592 rtl_wol_suspend_quirk(tp);
6593 rtl_wol_shutdown_quirk(tp);
ca52efd5 6594 }
6595
861ab440
RW		 6596 pci_wake_from_d3(pdev, true);
6597 pci_set_power_state(pdev, PCI_D3hot);
6598 }
2a15cd2f 6599
6600 pm_runtime_put_noidle(d);
861ab440 6601}
5d06a99f 6602
e27566ed
FR		 6603static void __devexit rtl_remove_one(struct pci_dev *pdev)
6604{
6605 struct net_device *dev = pci_get_drvdata(pdev);
6606 struct rtl8169_private *tp = netdev_priv(dev);
6607
6608 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
6609 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
6610 tp->mac_version == RTL_GIGA_MAC_VER_31) {
6611 rtl8168_driver_stop(tp);
6612 }
6613
6614 cancel_work_sync(&tp->wk.work);
6615
ad1be8d3
DN		 6616 netif_napi_del(&tp->napi);
6617
e27566ed
FR		 6618 unregister_netdev(dev);
6619
6620 rtl_release_firmware(tp);
6621
6622 if (pci_dev_run_wake(pdev))
6623 pm_runtime_get_noresume(&pdev->dev);
6624
6625 /* restore original MAC address */
6626 rtl_rar_set(tp, dev->perm_addr);
6627
6628 rtl_disable_msi(pdev, tp);
6629 rtl8169_release_board(pdev, dev, tp->mmio_addr);
6630 pci_set_drvdata(pdev, NULL);
6631}
6632
fa9c385e 6633static const struct net_device_ops rtl_netdev_ops = {
df43ac78 6634 .ndo_open = rtl_open,
fa9c385e
FR		 6635 .ndo_stop = rtl8169_close,
6636 .ndo_get_stats64 = rtl8169_get_stats64,
6637 .ndo_start_xmit = rtl8169_start_xmit,
6638 .ndo_tx_timeout = rtl8169_tx_timeout,
6639 .ndo_validate_addr = eth_validate_addr,
6640 .ndo_change_mtu = rtl8169_change_mtu,
6641 .ndo_fix_features = rtl8169_fix_features,
6642 .ndo_set_features = rtl8169_set_features,
6643 .ndo_set_mac_address = rtl_set_mac_address,
6644 .ndo_do_ioctl = rtl8169_ioctl,
6645 .ndo_set_rx_mode = rtl_set_rx_mode,
6646#ifdef CONFIG_NET_POLL_CONTROLLER
6647 .ndo_poll_controller = rtl8169_netpoll,
6648#endif
6649
6650};
6651
31fa8b18
FR		 6652static const struct rtl_cfg_info {
6653 void (*hw_start)(struct net_device *);
6654 unsigned int region;
6655 unsigned int align;
6656 u16 event_slow;
6657 unsigned features;
6658 u8 default_ver;
6659} rtl_cfg_infos [] = {
6660 [RTL_CFG_0] = {
6661 .hw_start = rtl_hw_start_8169,
6662 .region = 1,
6663 .align = 0,
6664 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
6665 .features = RTL_FEATURE_GMII,
6666 .default_ver = RTL_GIGA_MAC_VER_01,
6667 },
6668 [RTL_CFG_1] = {
6669 .hw_start = rtl_hw_start_8168,
6670 .region = 2,
6671 .align = 8,
6672 .event_slow = SYSErr | LinkChg | RxOverflow,
6673 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
6674 .default_ver = RTL_GIGA_MAC_VER_11,
6675 },
6676 [RTL_CFG_2] = {
6677 .hw_start = rtl_hw_start_8101,
6678 .region = 2,
6679 .align = 8,
6680 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
6681 PCSTimeout,
6682 .features = RTL_FEATURE_MSI,
6683 .default_ver = RTL_GIGA_MAC_VER_13,
6684 }
6685};
6686
6687/* Cfg9346_Unlock assumed. */
6688static unsigned rtl_try_msi(struct rtl8169_private *tp,
6689 const struct rtl_cfg_info *cfg)
6690{
6691 void __iomem *ioaddr = tp->mmio_addr;
6692 unsigned msi = 0;
6693 u8 cfg2;
6694
6695 cfg2 = RTL_R8(Config2) & ~MSIEnable;
6696 if (cfg->features & RTL_FEATURE_MSI) {
6697 if (pci_enable_msi(tp->pci_dev)) {
6698 netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
6699 } else {
6700 cfg2 |= MSIEnable;
6701 msi = RTL_FEATURE_MSI;
6702 }
6703 }
6704 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
6705 RTL_W8(Config2, cfg2);
6706 return msi;
6707}
6708
c558386b
HW		 6709DECLARE_RTL_COND(rtl_link_list_ready_cond)
6710{
6711 void __iomem *ioaddr = tp->mmio_addr;
6712
6713 return RTL_R8(MCU) & LINK_LIST_RDY;
6714}
6715
6716DECLARE_RTL_COND(rtl_rxtx_empty_cond)
6717{
6718 void __iomem *ioaddr = tp->mmio_addr;
6719
6720 return (RTL_R8(MCU) & RXTX_EMPTY) == RXTX_EMPTY;
6721}
6722
6723static void __devinit rtl_hw_init_8168g(struct rtl8169_private *tp)
6724{
6725 void __iomem *ioaddr = tp->mmio_addr;
6726 u32 data;
6727
6728 tp->ocp_base = OCP_STD_PHY_BASE;
6729
6730 RTL_W32(MISC, RTL_R32(MISC) | RXDV_GATED_EN);
6731
6732 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
6733 return;
6734
6735 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
6736 return;
6737
6738 RTL_W8(ChipCmd, RTL_R8(ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
6739 msleep(1);
6740 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
6741
5f8bcce9 6742 data = r8168_mac_ocp_read(tp, 0xe8de);
c558386b
HW		 6743 data &= ~(1 << 14);
6744 r8168_mac_ocp_write(tp, 0xe8de, data);
6745
6746 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6747 return;
6748
5f8bcce9 6749 data = r8168_mac_ocp_read(tp, 0xe8de);
c558386b
HW		 6750 data |= (1 << 15);
6751 r8168_mac_ocp_write(tp, 0xe8de, data);
6752
6753 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6754 return;
6755}
6756
6757static void __devinit rtl_hw_initialize(struct rtl8169_private *tp)
6758{
6759 switch (tp->mac_version) {
6760 case RTL_GIGA_MAC_VER_40:
6761 case RTL_GIGA_MAC_VER_41:
6762 rtl_hw_init_8168g(tp);
6763 break;
6764
6765 default:
6766 break;
6767 }
6768}
6769
3b6cf25d
FR		 6770static int __devinit
6771rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6772{
6773 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
6774 const unsigned int region = cfg->region;
6775 struct rtl8169_private *tp;
6776 struct mii_if_info *mii;
6777 struct net_device *dev;
6778 void __iomem *ioaddr;
6779 int chipset, i;
6780 int rc;
6781
6782 if (netif_msg_drv(&debug)) {
6783 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
6784 MODULENAME, RTL8169_VERSION);
6785 }
6786
6787 dev = alloc_etherdev(sizeof (*tp));
6788 if (!dev) {
6789 rc = -ENOMEM;
6790 goto out;
6791 }
6792
6793 SET_NETDEV_DEV(dev, &pdev->dev);
fa9c385e 6794 dev->netdev_ops = &rtl_netdev_ops;
3b6cf25d
FR		 6795 tp = netdev_priv(dev);
6796 tp->dev = dev;
6797 tp->pci_dev = pdev;
6798 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
6799
6800 mii = &tp->mii;
6801 mii->dev = dev;
6802 mii->mdio_read = rtl_mdio_read;
6803 mii->mdio_write = rtl_mdio_write;
6804 mii->phy_id_mask = 0x1f;
6805 mii->reg_num_mask = 0x1f;
6806 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
6807
6808 /* disable ASPM completely as that cause random device stop working
6809 * problems as well as full system hangs for some PCIe devices users */
6810 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
6811 PCIE_LINK_STATE_CLKPM);
6812
6813 /* enable device (incl. PCI PM wakeup and hotplug setup) */
6814 rc = pci_enable_device(pdev);
6815 if (rc < 0) {
6816 netif_err(tp, probe, dev, "enable failure\n");
6817 goto err_out_free_dev_1;
6818 }
6819
6820 if (pci_set_mwi(pdev) < 0)
6821 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
6822
6823 /* make sure PCI base addr 1 is MMIO */
6824 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
6825 netif_err(tp, probe, dev,
6826 "region #%d not an MMIO resource, aborting\n",
6827 region);
6828 rc = -ENODEV;
6829 goto err_out_mwi_2;
6830 }
6831
6832 /* check for weird/broken PCI region reporting */
6833 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
6834 netif_err(tp, probe, dev,
6835 "Invalid PCI region size(s), aborting\n");
6836 rc = -ENODEV;
6837 goto err_out_mwi_2;
6838 }
6839
6840 rc = pci_request_regions(pdev, MODULENAME);
6841 if (rc < 0) {
6842 netif_err(tp, probe, dev, "could not request regions\n");
6843 goto err_out_mwi_2;
6844 }
6845
6846 tp->cp_cmd = RxChkSum;
6847
6848 if ((sizeof(dma_addr_t) > 4) &&
6849 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
6850 tp->cp_cmd |= PCIDAC;
6851 dev->features |= NETIF_F_HIGHDMA;
6852 } else {
6853 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6854 if (rc < 0) {
6855 netif_err(tp, probe, dev, "DMA configuration failed\n");
6856 goto err_out_free_res_3;
6857 }
6858 }
6859
6860 /* ioremap MMIO region */
6861 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
6862 if (!ioaddr) {
6863 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
6864 rc = -EIO;
6865 goto err_out_free_res_3;
6866 }
6867 tp->mmio_addr = ioaddr;
6868
6869 if (!pci_is_pcie(pdev))
6870 netif_info(tp, probe, dev, "not PCI Express\n");
6871
6872 /* Identify chip attached to board */
6873 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
6874
6875 rtl_init_rxcfg(tp);
6876
6877 rtl_irq_disable(tp);
6878
c558386b
HW		 6879 rtl_hw_initialize(tp);
6880
3b6cf25d
FR		 6881 rtl_hw_reset(tp);
6882
6883 rtl_ack_events(tp, 0xffff);
6884
6885 pci_set_master(pdev);
6886
6887 /*
6888 * Pretend we are using VLANs; This bypasses a nasty bug where
6889 * Interrupts stop flowing on high load on 8110SCd controllers.
6890 */
6891 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6892 tp->cp_cmd |= RxVlan;
6893
6894 rtl_init_mdio_ops(tp);
6895 rtl_init_pll_power_ops(tp);
6896 rtl_init_jumbo_ops(tp);
beb1fe18 6897 rtl_init_csi_ops(tp);
3b6cf25d
FR		 6898
6899 rtl8169_print_mac_version(tp);
6900
6901 chipset = tp->mac_version;
6902 tp->txd_version = rtl_chip_infos[chipset].txd_version;
6903
6904 RTL_W8(Cfg9346, Cfg9346_Unlock);
6905 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
6906 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
6907 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
6908 tp->features |= RTL_FEATURE_WOL;
6909 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
6910 tp->features |= RTL_FEATURE_WOL;
6911 tp->features |= rtl_try_msi(tp, cfg);
6912 RTL_W8(Cfg9346, Cfg9346_Lock);
6913
6914 if (rtl_tbi_enabled(tp)) {
6915 tp->set_speed = rtl8169_set_speed_tbi;
6916 tp->get_settings = rtl8169_gset_tbi;
6917 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
6918 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
6919 tp->link_ok = rtl8169_tbi_link_ok;
6920 tp->do_ioctl = rtl_tbi_ioctl;
6921 } else {
6922 tp->set_speed = rtl8169_set_speed_xmii;
6923 tp->get_settings = rtl8169_gset_xmii;
6924 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
6925 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
6926 tp->link_ok = rtl8169_xmii_link_ok;
6927 tp->do_ioctl = rtl_xmii_ioctl;
6928 }
6929
6930 mutex_init(&tp->wk.mutex);
6931
6932 /* Get MAC address */
6933 for (i = 0; i < ETH_ALEN; i++)
6934 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6935 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
6936
6937 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
6938 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3b6cf25d
FR		 6939
6940 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
6941
6942 /* don't enable SG, IP_CSUM and TSO by default - it might not work
6943 * properly for all devices */
6944 dev->features |= NETIF_F_RXCSUM |
6945 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6946
6947 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6948 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6949 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6950 NETIF_F_HIGHDMA;
6951
6952 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6953 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
6954 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
6955
6956 dev->hw_features |= NETIF_F_RXALL;
6957 dev->hw_features |= NETIF_F_RXFCS;
6958
6959 tp->hw_start = cfg->hw_start;
6960 tp->event_slow = cfg->event_slow;
6961
6962 tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
6963 ~(RxBOVF | RxFOVF) : ~0;
6964
6965 init_timer(&tp->timer);
6966 tp->timer.data = (unsigned long) dev;
6967 tp->timer.function = rtl8169_phy_timer;
6968
6969 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
6970
6971 rc = register_netdev(dev);
6972 if (rc < 0)
6973 goto err_out_msi_4;
6974
6975 pci_set_drvdata(pdev, dev);
6976
92a7c4e7
FR		 6977 netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
6978 rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
6979 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
3b6cf25d
FR		 6980 if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
6981 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
6982 "tx checksumming: %s]\n",
6983 rtl_chip_infos[chipset].jumbo_max,
6984 rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
6985 }
6986
6987 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
6988 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
6989 tp->mac_version == RTL_GIGA_MAC_VER_31) {
6990 rtl8168_driver_start(tp);
6991 }
6992
6993 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
6994
6995 if (pci_dev_run_wake(pdev))
6996 pm_runtime_put_noidle(&pdev->dev);
6997
6998 netif_carrier_off(dev);
6999
7000out:
7001 return rc;
7002
7003err_out_msi_4:
ad1be8d3 7004 netif_napi_del(&tp->napi);
3b6cf25d
FR		 7005 rtl_disable_msi(pdev, tp);
7006 iounmap(ioaddr);
7007err_out_free_res_3:
7008 pci_release_regions(pdev);
7009err_out_mwi_2:
7010 pci_clear_mwi(pdev);
7011 pci_disable_device(pdev);
7012err_out_free_dev_1:
7013 free_netdev(dev);
7014 goto out;
7015}
7016
1da177e4
LT		 7017static struct pci_driver rtl8169_pci_driver = {
7018 .name = MODULENAME,
7019 .id_table = rtl8169_pci_tbl,
3b6cf25d 7020 .probe = rtl_init_one,
e27566ed 7021 .remove = __devexit_p(rtl_remove_one),
1765f95d 7022 .shutdown = rtl_shutdown,
861ab440 7023 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 7024};
7025
07d3f51f 7026static int __init rtl8169_init_module(void)
1da177e4 7027{
29917620 7028 return pci_register_driver(&rtl8169_pci_driver);
1da177e4
LT		 7029}
7030
07d3f51f 7031static void __exit rtl8169_cleanup_module(void)
1da177e4
LT		 7032{
7033 pci_unregister_driver(&rtl8169_pci_driver);
7034}
7035
7036module_init(rtl8169_init_module);
7037module_exit(rtl8169_cleanup_module);
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