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[mirror_ubuntu-focal-kernel.git] / drivers / net / ethernet / realtek / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
a6b7a407 24#include <linux/interrupt.h>
1da177e4 25#include <linux/dma-mapping.h>
e1759441 26#include <linux/pm_runtime.h>
bca03d5f 27#include <linux/firmware.h>
ba04c7c9 28#include <linux/pci-aspm.h>
70c71606 29#include <linux/prefetch.h>
e974604b 30#include <linux/ipv6.h>
31#include <net/ip6_checksum.h>
1da177e4
LT		 32
33#include <asm/io.h>
34#include <asm/irq.h>
35
865c652d 36#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 37#define MODULENAME "r8169"
38#define PFX MODULENAME ": "
39
bca03d5f 40#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
41#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
01dc7fec 42#define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
43#define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
70090424 44#define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
c2218925
HW		 45#define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
46#define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
5a5e4443 47#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
7e18dca1 48#define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
b3d7b2f2 49#define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
45dd95c4 50#define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
5598bfe5 51#define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
58152cd4 52#define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
beb330a4 53#define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
57538c4a 54#define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
6e1d0b89
CHL		 55#define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw"
56#define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
57#define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw"
58#define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
bca03d5f 59
1da177e4
LT		 60#ifdef RTL8169_DEBUG
61#define assert(expr) \
5b0384f4
FR		 62 if (!(expr)) { \
63 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
b39d66a8 64 #expr,__FILE__,__func__,__LINE__); \
5b0384f4 65 }
06fa7358
JP		 66#define dprintk(fmt, args...) \
67 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 68#else
69#define assert(expr) do {} while (0)
70#define dprintk(fmt, args...) do {} while (0)
71#endif /* RTL8169_DEBUG */
72
b57b7e5a 73#define R8169_MSG_DEFAULT \
f0e837d9 74 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 75
477206a0
JD		 76#define TX_SLOTS_AVAIL(tp) \
77 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
78
79/* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
80#define TX_FRAGS_READY_FOR(tp,nr_frags) \
81 (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
1da177e4 82
1da177e4
LT		 83/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
84 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 85static const int multicast_filter_limit = 32;
1da177e4 86
9c14ceaf 87#define MAX_READ_REQUEST_SHIFT 12
aee77e4a 88#define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
1da177e4
LT		 89#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
90
91#define R8169_REGS_SIZE 256
92#define R8169_NAPI_WEIGHT 64
93#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
9fba0812 94#define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
1da177e4
LT		 95#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
96#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
97
98#define RTL8169_TX_TIMEOUT (6*HZ)
99#define RTL8169_PHY_TIMEOUT (10*HZ)
100
101/* write/read MMIO register */
102#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
103#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
104#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
105#define RTL_R8(reg) readb (ioaddr + (reg))
106#define RTL_R16(reg) readw (ioaddr + (reg))
06f555f3 107#define RTL_R32(reg) readl (ioaddr + (reg))
1da177e4
LT		 108
109enum mac_version {
85bffe6c
FR		 110 RTL_GIGA_MAC_VER_01 = 0,
111 RTL_GIGA_MAC_VER_02,
112 RTL_GIGA_MAC_VER_03,
113 RTL_GIGA_MAC_VER_04,
114 RTL_GIGA_MAC_VER_05,
115 RTL_GIGA_MAC_VER_06,
116 RTL_GIGA_MAC_VER_07,
117 RTL_GIGA_MAC_VER_08,
118 RTL_GIGA_MAC_VER_09,
119 RTL_GIGA_MAC_VER_10,
120 RTL_GIGA_MAC_VER_11,
121 RTL_GIGA_MAC_VER_12,
122 RTL_GIGA_MAC_VER_13,
123 RTL_GIGA_MAC_VER_14,
124 RTL_GIGA_MAC_VER_15,
125 RTL_GIGA_MAC_VER_16,
126 RTL_GIGA_MAC_VER_17,
127 RTL_GIGA_MAC_VER_18,
128 RTL_GIGA_MAC_VER_19,
129 RTL_GIGA_MAC_VER_20,
130 RTL_GIGA_MAC_VER_21,
131 RTL_GIGA_MAC_VER_22,
132 RTL_GIGA_MAC_VER_23,
133 RTL_GIGA_MAC_VER_24,
134 RTL_GIGA_MAC_VER_25,
135 RTL_GIGA_MAC_VER_26,
136 RTL_GIGA_MAC_VER_27,
137 RTL_GIGA_MAC_VER_28,
138 RTL_GIGA_MAC_VER_29,
139 RTL_GIGA_MAC_VER_30,
140 RTL_GIGA_MAC_VER_31,
141 RTL_GIGA_MAC_VER_32,
142 RTL_GIGA_MAC_VER_33,
70090424 143 RTL_GIGA_MAC_VER_34,
c2218925
HW		 144 RTL_GIGA_MAC_VER_35,
145 RTL_GIGA_MAC_VER_36,
7e18dca1 146 RTL_GIGA_MAC_VER_37,
b3d7b2f2 147 RTL_GIGA_MAC_VER_38,
5598bfe5 148 RTL_GIGA_MAC_VER_39,
c558386b
HW		 149 RTL_GIGA_MAC_VER_40,
150 RTL_GIGA_MAC_VER_41,
57538c4a 151 RTL_GIGA_MAC_VER_42,
58152cd4 152 RTL_GIGA_MAC_VER_43,
45dd95c4 153 RTL_GIGA_MAC_VER_44,
6e1d0b89
CHL		 154 RTL_GIGA_MAC_VER_45,
155 RTL_GIGA_MAC_VER_46,
156 RTL_GIGA_MAC_VER_47,
157 RTL_GIGA_MAC_VER_48,
935e2218
CHL		 158 RTL_GIGA_MAC_VER_49,
159 RTL_GIGA_MAC_VER_50,
160 RTL_GIGA_MAC_VER_51,
85bffe6c 161 RTL_GIGA_MAC_NONE = 0xff,
1da177e4
LT		 162};
163
2b7b4318
FR		 164enum rtl_tx_desc_version {
165 RTL_TD_0 = 0,
166 RTL_TD_1 = 1,
167};
168
d58d46b5
FR		 169#define JUMBO_1K ETH_DATA_LEN
170#define JUMBO_4K (4*1024 - ETH_HLEN - 2)
171#define JUMBO_6K (6*1024 - ETH_HLEN - 2)
172#define JUMBO_7K (7*1024 - ETH_HLEN - 2)
173#define JUMBO_9K (9*1024 - ETH_HLEN - 2)
174
175#define _R(NAME,TD,FW,SZ,B) { \
176 .name = NAME, \
177 .txd_version = TD, \
178 .fw_name = FW, \
179 .jumbo_max = SZ, \
180 .jumbo_tx_csum = B \
181}
1da177e4 182
3c6bee1d 183static const struct {
1da177e4 184 const char *name;
2b7b4318 185 enum rtl_tx_desc_version txd_version;
953a12cc 186 const char *fw_name;
d58d46b5
FR		 187 u16 jumbo_max;
188 bool jumbo_tx_csum;
85bffe6c
FR		 189} rtl_chip_infos[] = {
190 /* PCI devices. */
191 [RTL_GIGA_MAC_VER_01] =
d58d46b5 192 _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 193 [RTL_GIGA_MAC_VER_02] =
d58d46b5 194 _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 195 [RTL_GIGA_MAC_VER_03] =
d58d46b5 196 _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 197 [RTL_GIGA_MAC_VER_04] =
d58d46b5 198 _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 199 [RTL_GIGA_MAC_VER_05] =
d58d46b5 200 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 201 [RTL_GIGA_MAC_VER_06] =
d58d46b5 202 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c
FR		 203 /* PCI-E devices. */
204 [RTL_GIGA_MAC_VER_07] =
d58d46b5 205 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 206 [RTL_GIGA_MAC_VER_08] =
d58d46b5 207 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 208 [RTL_GIGA_MAC_VER_09] =
d58d46b5 209 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 210 [RTL_GIGA_MAC_VER_10] =
d58d46b5 211 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 212 [RTL_GIGA_MAC_VER_11] =
d58d46b5 213 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
85bffe6c 214 [RTL_GIGA_MAC_VER_12] =
d58d46b5 215 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
85bffe6c 216 [RTL_GIGA_MAC_VER_13] =
d58d46b5 217 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 218 [RTL_GIGA_MAC_VER_14] =
d58d46b5 219 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 220 [RTL_GIGA_MAC_VER_15] =
d58d46b5 221 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 222 [RTL_GIGA_MAC_VER_16] =
d58d46b5 223 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 224 [RTL_GIGA_MAC_VER_17] =
f75761b6 225 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
85bffe6c 226 [RTL_GIGA_MAC_VER_18] =
d58d46b5 227 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 228 [RTL_GIGA_MAC_VER_19] =
d58d46b5 229 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 230 [RTL_GIGA_MAC_VER_20] =
d58d46b5 231 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 232 [RTL_GIGA_MAC_VER_21] =
d58d46b5 233 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 234 [RTL_GIGA_MAC_VER_22] =
d58d46b5 235 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 236 [RTL_GIGA_MAC_VER_23] =
d58d46b5 237 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 238 [RTL_GIGA_MAC_VER_24] =
d58d46b5 239 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 240 [RTL_GIGA_MAC_VER_25] =
d58d46b5
FR		 241 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1,
242 JUMBO_9K, false),
85bffe6c 243 [RTL_GIGA_MAC_VER_26] =
d58d46b5
FR		 244 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2,
245 JUMBO_9K, false),
85bffe6c 246 [RTL_GIGA_MAC_VER_27] =
d58d46b5 247 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 248 [RTL_GIGA_MAC_VER_28] =
d58d46b5 249 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 250 [RTL_GIGA_MAC_VER_29] =
d58d46b5
FR		 251 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
252 JUMBO_1K, true),
85bffe6c 253 [RTL_GIGA_MAC_VER_30] =
d58d46b5
FR		 254 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
255 JUMBO_1K, true),
85bffe6c 256 [RTL_GIGA_MAC_VER_31] =
d58d46b5 257 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 258 [RTL_GIGA_MAC_VER_32] =
d58d46b5
FR		 259 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1,
260 JUMBO_9K, false),
85bffe6c 261 [RTL_GIGA_MAC_VER_33] =
d58d46b5
FR		 262 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2,
263 JUMBO_9K, false),
70090424 264 [RTL_GIGA_MAC_VER_34] =
d58d46b5
FR		 265 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
266 JUMBO_9K, false),
c2218925 267 [RTL_GIGA_MAC_VER_35] =
d58d46b5
FR		 268 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1,
269 JUMBO_9K, false),
c2218925 270 [RTL_GIGA_MAC_VER_36] =
d58d46b5
FR		 271 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2,
272 JUMBO_9K, false),
7e18dca1
HW		 273 [RTL_GIGA_MAC_VER_37] =
274 _R("RTL8402", RTL_TD_1, FIRMWARE_8402_1,
275 JUMBO_1K, true),
b3d7b2f2
HW		 276 [RTL_GIGA_MAC_VER_38] =
277 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_1,
278 JUMBO_9K, false),
5598bfe5
HW		 279 [RTL_GIGA_MAC_VER_39] =
280 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_1,
281 JUMBO_1K, true),
c558386b 282 [RTL_GIGA_MAC_VER_40] =
beb330a4 283 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_2,
c558386b
HW		 284 JUMBO_9K, false),
285 [RTL_GIGA_MAC_VER_41] =
286 _R("RTL8168g/8111g", RTL_TD_1, NULL, JUMBO_9K, false),
57538c4a 287 [RTL_GIGA_MAC_VER_42] =
288 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_3,
289 JUMBO_9K, false),
58152cd4 290 [RTL_GIGA_MAC_VER_43] =
291 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_2,
292 JUMBO_1K, true),
45dd95c4 293 [RTL_GIGA_MAC_VER_44] =
294 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_2,
295 JUMBO_9K, false),
6e1d0b89
CHL		 296 [RTL_GIGA_MAC_VER_45] =
297 _R("RTL8168h/8111h", RTL_TD_1, FIRMWARE_8168H_1,
298 JUMBO_9K, false),
299 [RTL_GIGA_MAC_VER_46] =
300 _R("RTL8168h/8111h", RTL_TD_1, FIRMWARE_8168H_2,
301 JUMBO_9K, false),
302 [RTL_GIGA_MAC_VER_47] =
303 _R("RTL8107e", RTL_TD_1, FIRMWARE_8107E_1,
304 JUMBO_1K, false),
305 [RTL_GIGA_MAC_VER_48] =
306 _R("RTL8107e", RTL_TD_1, FIRMWARE_8107E_2,
307 JUMBO_1K, false),
935e2218
CHL		 308 [RTL_GIGA_MAC_VER_49] =
309 _R("RTL8168ep/8111ep", RTL_TD_1, NULL,
310 JUMBO_9K, false),
311 [RTL_GIGA_MAC_VER_50] =
312 _R("RTL8168ep/8111ep", RTL_TD_1, NULL,
313 JUMBO_9K, false),
314 [RTL_GIGA_MAC_VER_51] =
315 _R("RTL8168ep/8111ep", RTL_TD_1, NULL,
316 JUMBO_9K, false),
953a12cc 317};
85bffe6c 318#undef _R
953a12cc 319
bcf0bf90
FR		 320enum cfg_version {
321 RTL_CFG_0 = 0x00,
322 RTL_CFG_1,
323 RTL_CFG_2
324};
325
9baa3c34 326static const struct pci_device_id rtl8169_pci_tbl[] = {
bcf0bf90 327 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 328 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 329 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 330 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90 331 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
2a35cfa5
FR		 332 { PCI_VENDOR_ID_DLINK, 0x4300,
333 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
bcf0bf90 334 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
93a3aa25 335 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
bc1660b5 336 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 337 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
338 { PCI_VENDOR_ID_LINKSYS, 0x1032,
339 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 340 { 0x0001, 0x8168,
341 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 342 {0,},
343};
344
345MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
346
6f0333b8 347static int rx_buf_sz = 16383;
4300e8c7 348static int use_dac;
b57b7e5a
SH		 349static struct {
350 u32 msg_enable;
351} debug = { -1 };
1da177e4 352
07d3f51f
FR		 353enum rtl_registers {
354 MAC0 = 0, /* Ethernet hardware address. */
773d2021 355 MAC4 = 4,
07d3f51f
FR		 356 MAR0 = 8, /* Multicast filter. */
357 CounterAddrLow = 0x10,
358 CounterAddrHigh = 0x14,
359 TxDescStartAddrLow = 0x20,
360 TxDescStartAddrHigh = 0x24,
361 TxHDescStartAddrLow = 0x28,
362 TxHDescStartAddrHigh = 0x2c,
363 FLASH = 0x30,
364 ERSR = 0x36,
365 ChipCmd = 0x37,
366 TxPoll = 0x38,
367 IntrMask = 0x3c,
368 IntrStatus = 0x3e,
4f6b00e5 369
07d3f51f 370 TxConfig = 0x40,
4f6b00e5
HW		 371#define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
372#define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
2b7b4318 373
4f6b00e5
HW		 374 RxConfig = 0x44,
375#define RX128_INT_EN (1 << 15) /* 8111c and later */
376#define RX_MULTI_EN (1 << 14) /* 8111c only */
377#define RXCFG_FIFO_SHIFT 13
378 /* No threshold before first PCI xfer */
379#define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
beb330a4 380#define RX_EARLY_OFF (1 << 11)
4f6b00e5
HW		 381#define RXCFG_DMA_SHIFT 8
382 /* Unlimited maximum PCI burst. */
383#define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
2b7b4318 384
07d3f51f
FR		 385 RxMissed = 0x4c,
386 Cfg9346 = 0x50,
387 Config0 = 0x51,
388 Config1 = 0x52,
389 Config2 = 0x53,
d387b427
FR		 390#define PME_SIGNAL (1 << 5) /* 8168c and later */
391
07d3f51f
FR		 392 Config3 = 0x54,
393 Config4 = 0x55,
394 Config5 = 0x56,
395 MultiIntr = 0x5c,
396 PHYAR = 0x60,
07d3f51f
FR		 397 PHYstatus = 0x6c,
398 RxMaxSize = 0xda,
399 CPlusCmd = 0xe0,
400 IntrMitigate = 0xe2,
401 RxDescAddrLow = 0xe4,
402 RxDescAddrHigh = 0xe8,
f0298f81 403 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
404
405#define NoEarlyTx 0x3f /* Max value : no early transmit. */
406
407 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
408
409#define TxPacketMax (8064 >> 7)
3090bd9a 410#define EarlySize 0x27
f0298f81 411
07d3f51f
FR		 412 FuncEvent = 0xf0,
413 FuncEventMask = 0xf4,
414 FuncPresetState = 0xf8,
935e2218
CHL		 415 IBCR0 = 0xf8,
416 IBCR2 = 0xf9,
417 IBIMR0 = 0xfa,
418 IBISR0 = 0xfb,
07d3f51f 419 FuncForceEvent = 0xfc,
1da177e4
LT		 420};
421
f162a5d1
FR		 422enum rtl8110_registers {
423 TBICSR = 0x64,
424 TBI_ANAR = 0x68,
425 TBI_LPAR = 0x6a,
426};
427
428enum rtl8168_8101_registers {
429 CSIDR = 0x64,
430 CSIAR = 0x68,
431#define CSIAR_FLAG 0x80000000
432#define CSIAR_WRITE_CMD 0x80000000
433#define CSIAR_BYTE_ENABLE 0x0f
434#define CSIAR_BYTE_ENABLE_SHIFT 12
435#define CSIAR_ADDR_MASK 0x0fff
7e18dca1
HW		 436#define CSIAR_FUNC_CARD 0x00000000
437#define CSIAR_FUNC_SDIO 0x00010000
438#define CSIAR_FUNC_NIC 0x00020000
45dd95c4 439#define CSIAR_FUNC_NIC2 0x00010000
065c27c1 440 PMCH = 0x6f,
f162a5d1
FR		 441 EPHYAR = 0x80,
442#define EPHYAR_FLAG 0x80000000
443#define EPHYAR_WRITE_CMD 0x80000000
444#define EPHYAR_REG_MASK 0x1f
445#define EPHYAR_REG_SHIFT 16
446#define EPHYAR_DATA_MASK 0xffff
5a5e4443 447 DLLPR = 0xd0,
4f6b00e5 448#define PFM_EN (1 << 6)
6e1d0b89 449#define TX_10M_PS_EN (1 << 7)
f162a5d1
FR		 450 DBG_REG = 0xd1,
451#define FIX_NAK_1 (1 << 4)
452#define FIX_NAK_2 (1 << 3)
5a5e4443
HW		 453 TWSI = 0xd2,
454 MCU = 0xd3,
4f6b00e5 455#define NOW_IS_OOB (1 << 7)
c558386b
HW		 456#define TX_EMPTY (1 << 5)
457#define RX_EMPTY (1 << 4)
458#define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
5a5e4443
HW		 459#define EN_NDP (1 << 3)
460#define EN_OOB_RESET (1 << 2)
c558386b 461#define LINK_LIST_RDY (1 << 1)
daf9df6d 462 EFUSEAR = 0xdc,
463#define EFUSEAR_FLAG 0x80000000
464#define EFUSEAR_WRITE_CMD 0x80000000
465#define EFUSEAR_READ_CMD 0x00000000
466#define EFUSEAR_REG_MASK 0x03ff
467#define EFUSEAR_REG_SHIFT 8
468#define EFUSEAR_DATA_MASK 0xff
6e1d0b89
CHL		 469 MISC_1 = 0xf2,
470#define PFM_D3COLD_EN (1 << 6)
f162a5d1
FR		 471};
472
c0e45c1c 473enum rtl8168_registers {
4f6b00e5
HW		 474 LED_FREQ = 0x1a,
475 EEE_LED = 0x1b,
b646d900 476 ERIDR = 0x70,
477 ERIAR = 0x74,
478#define ERIAR_FLAG 0x80000000
479#define ERIAR_WRITE_CMD 0x80000000
480#define ERIAR_READ_CMD 0x00000000
481#define ERIAR_ADDR_BYTE_ALIGN 4
b646d900 482#define ERIAR_TYPE_SHIFT 16
4f6b00e5
HW		 483#define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
484#define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
485#define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
935e2218 486#define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
4f6b00e5
HW		 487#define ERIAR_MASK_SHIFT 12
488#define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
489#define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
6e1d0b89 490#define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
c558386b 491#define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
4f6b00e5 492#define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
c0e45c1c 493 EPHY_RXER_NUM = 0x7c,
494 OCPDR = 0xb0, /* OCP GPHY access */
495#define OCPDR_WRITE_CMD 0x80000000
496#define OCPDR_READ_CMD 0x00000000
497#define OCPDR_REG_MASK 0x7f
498#define OCPDR_GPHY_REG_SHIFT 16
499#define OCPDR_DATA_MASK 0xffff
500 OCPAR = 0xb4,
501#define OCPAR_FLAG 0x80000000
502#define OCPAR_GPHY_WRITE_CMD 0x8000f060
503#define OCPAR_GPHY_READ_CMD 0x0000f060
c558386b 504 GPHY_OCP = 0xb8,
01dc7fec 505 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
506 MISC = 0xf0, /* 8168e only. */
cecb5fd7 507#define TXPLA_RST (1 << 29)
5598bfe5 508#define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
4f6b00e5 509#define PWM_EN (1 << 22)
c558386b 510#define RXDV_GATED_EN (1 << 19)
5598bfe5 511#define EARLY_TALLY_EN (1 << 16)
c0e45c1c 512};
513
07d3f51f 514enum rtl_register_content {
1da177e4 515 /* InterruptStatusBits */
07d3f51f
FR		 516 SYSErr = 0x8000,
517 PCSTimeout = 0x4000,
518 SWInt = 0x0100,
519 TxDescUnavail = 0x0080,
520 RxFIFOOver = 0x0040,
521 LinkChg = 0x0020,
522 RxOverflow = 0x0010,
523 TxErr = 0x0008,
524 TxOK = 0x0004,
525 RxErr = 0x0002,
526 RxOK = 0x0001,
1da177e4
LT		 527
528 /* RxStatusDesc */
e03f33af 529 RxBOVF = (1 << 24),
9dccf611
FR		 530 RxFOVF = (1 << 23),
531 RxRWT = (1 << 22),
532 RxRES = (1 << 21),
533 RxRUNT = (1 << 20),
534 RxCRC = (1 << 19),
1da177e4
LT		 535
536 /* ChipCmdBits */
4f6b00e5 537 StopReq = 0x80,
07d3f51f
FR		 538 CmdReset = 0x10,
539 CmdRxEnb = 0x08,
540 CmdTxEnb = 0x04,
541 RxBufEmpty = 0x01,
1da177e4 542
275391a4
FR		 543 /* TXPoll register p.5 */
544 HPQ = 0x80, /* Poll cmd on the high prio queue */
545 NPQ = 0x40, /* Poll cmd on the low prio queue */
546 FSWInt = 0x01, /* Forced software interrupt */
547
1da177e4 548 /* Cfg9346Bits */
07d3f51f
FR		 549 Cfg9346_Lock = 0x00,
550 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 551
552 /* rx_mode_bits */
07d3f51f
FR		 553 AcceptErr = 0x20,
554 AcceptRunt = 0x10,
555 AcceptBroadcast = 0x08,
556 AcceptMulticast = 0x04,
557 AcceptMyPhys = 0x02,
558 AcceptAllPhys = 0x01,
1687b566 559#define RX_CONFIG_ACCEPT_MASK 0x3f
1da177e4 560
1da177e4
LT		 561 /* TxConfigBits */
562 TxInterFrameGapShift = 24,
563 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
564
5d06a99f 565 /* Config1 register p.24 */
f162a5d1
FR		 566 LEDS1 = (1 << 7),
567 LEDS0 = (1 << 6),
f162a5d1
FR		 568 Speed_down = (1 << 4),
569 MEMMAP = (1 << 3),
570 IOMAP = (1 << 2),
571 VPD = (1 << 1),
5d06a99f
FR		 572 PMEnable = (1 << 0), /* Power Management Enable */
573
6dccd16b 574 /* Config2 register p. 25 */
57538c4a 575 ClkReqEn = (1 << 7), /* Clock Request Enable */
2ca6cf06 576 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
6dccd16b
FR		 577 PCI_Clock_66MHz = 0x01,
578 PCI_Clock_33MHz = 0x00,
579
61a4dcc2
FR		 580 /* Config3 register p.25 */
581 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
582 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
d58d46b5 583 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
b51ecea8 584 Rdy_to_L23 = (1 << 1), /* L23 Enable */
f162a5d1 585 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 586
d58d46b5
FR		 587 /* Config4 register */
588 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
589
5d06a99f 590 /* Config5 register p.27 */
61a4dcc2
FR		 591 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
592 MWF = (1 << 5), /* Accept Multicast wakeup frame */
593 UWF = (1 << 4), /* Accept Unicast wakeup frame */
cecb5fd7 594 Spi_en = (1 << 3),
61a4dcc2 595 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f 596 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
57538c4a 597 ASPM_en = (1 << 0), /* ASPM enable */
5d06a99f 598
1da177e4
LT		 599 /* TBICSR p.28 */
600 TBIReset = 0x80000000,
601 TBILoopback = 0x40000000,
602 TBINwEnable = 0x20000000,
603 TBINwRestart = 0x10000000,
604 TBILinkOk = 0x02000000,
605 TBINwComplete = 0x01000000,
606
607 /* CPlusCmd p.31 */
f162a5d1
FR		 608 EnableBist = (1 << 15), // 8168 8101
609 Mac_dbgo_oe = (1 << 14), // 8168 8101
610 Normal_mode = (1 << 13), // unused
611 Force_half_dup = (1 << 12), // 8168 8101
612 Force_rxflow_en = (1 << 11), // 8168 8101
613 Force_txflow_en = (1 << 10), // 8168 8101
614 Cxpl_dbg_sel = (1 << 9), // 8168 8101
615 ASF = (1 << 8), // 8168 8101
616 PktCntrDisable = (1 << 7), // 8168 8101
617 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 618 RxVlan = (1 << 6),
619 RxChkSum = (1 << 5),
620 PCIDAC = (1 << 4),
621 PCIMulRW = (1 << 3),
0e485150
FR		 622 INTT_0 = 0x0000, // 8168
623 INTT_1 = 0x0001, // 8168
624 INTT_2 = 0x0002, // 8168
625 INTT_3 = 0x0003, // 8168
1da177e4
LT		 626
627 /* rtl8169_PHYstatus */
07d3f51f
FR		 628 TBI_Enable = 0x80,
629 TxFlowCtrl = 0x40,
630 RxFlowCtrl = 0x20,
631 _1000bpsF = 0x10,
632 _100bps = 0x08,
633 _10bps = 0x04,
634 LinkStatus = 0x02,
635 FullDup = 0x01,
1da177e4 636
1da177e4 637 /* _TBICSRBit */
07d3f51f 638 TBILinkOK = 0x02000000,
d4a3a0fc 639
6e85d5ad
CV		 640 /* ResetCounterCommand */
641 CounterReset = 0x1,
642
d4a3a0fc 643 /* DumpCounterCommand */
07d3f51f 644 CounterDump = 0x8,
6e1d0b89
CHL		 645
646 /* magic enable v2 */
647 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */
1da177e4
LT		 648};
649
2b7b4318
FR		 650enum rtl_desc_bit {
651 /* First doubleword. */
1da177e4
LT		 652 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
653 RingEnd = (1 << 30), /* End of descriptor ring */
654 FirstFrag = (1 << 29), /* First segment of a packet */
655 LastFrag = (1 << 28), /* Final segment of a packet */
2b7b4318
FR		 656};
657
658/* Generic case. */
659enum rtl_tx_desc_bit {
660 /* First doubleword. */
661 TD_LSO = (1 << 27), /* Large Send Offload */
662#define TD_MSS_MAX 0x07ffu /* MSS value */
1da177e4 663
2b7b4318
FR		 664 /* Second doubleword. */
665 TxVlanTag = (1 << 17), /* Add VLAN tag */
666};
667
668/* 8169, 8168b and 810x except 8102e. */
669enum rtl_tx_desc_bit_0 {
670 /* First doubleword. */
671#define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
672 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
673 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
674 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
675};
676
677/* 8102e, 8168c and beyond. */
678enum rtl_tx_desc_bit_1 {
bdfa4ed6 679 /* First doubleword. */
680 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */
e974604b 681 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */
bdfa4ed6 682#define GTTCPHO_SHIFT 18
e974604b 683#define GTTCPHO_MAX 0x7fU
bdfa4ed6 684
2b7b4318 685 /* Second doubleword. */
e974604b 686#define TCPHO_SHIFT 18
687#define TCPHO_MAX 0x3ffU
2b7b4318 688#define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
e974604b 689 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */
690 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */
2b7b4318
FR		 691 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
692 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
693};
1da177e4 694
2b7b4318 695enum rtl_rx_desc_bit {
1da177e4
LT		 696 /* Rx private */
697 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
698 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
699
700#define RxProtoUDP (PID1)
701#define RxProtoTCP (PID0)
702#define RxProtoIP (PID1 | PID0)
703#define RxProtoMask RxProtoIP
704
705 IPFail = (1 << 16), /* IP checksum failed */
706 UDPFail = (1 << 15), /* UDP/IP checksum failed */
707 TCPFail = (1 << 14), /* TCP/IP checksum failed */
708 RxVlanTag = (1 << 16), /* VLAN tag available */
709};
710
711#define RsvdMask 0x3fffc000
712
713struct TxDesc {
6cccd6e7
REB		 714 __le32 opts1;
715 __le32 opts2;
716 __le64 addr;
1da177e4
LT		 717};
718
719struct RxDesc {
6cccd6e7
REB		 720 __le32 opts1;
721 __le32 opts2;
722 __le64 addr;
1da177e4
LT		 723};
724
725struct ring_info {
726 struct sk_buff *skb;
727 u32 len;
728 u8 __pad[sizeof(void *) - sizeof(u32)];
729};
730
f23e7fda 731enum features {
ccdffb9a
FR		 732 RTL_FEATURE_WOL = (1 << 0),
733 RTL_FEATURE_MSI = (1 << 1),
734 RTL_FEATURE_GMII = (1 << 2),
f23e7fda
FR		 735};
736
355423d0
IV		 737struct rtl8169_counters {
738 __le64 tx_packets;
739 __le64 rx_packets;
740 __le64 tx_errors;
741 __le32 rx_errors;
742 __le16 rx_missed;
743 __le16 align_errors;
744 __le32 tx_one_collision;
745 __le32 tx_multi_collision;
746 __le64 rx_unicast;
747 __le64 rx_broadcast;
748 __le32 rx_multicast;
749 __le16 tx_aborted;
750 __le16 tx_underun;
751};
752
6e85d5ad
CV		 753struct rtl8169_tc_offsets {
754 bool inited;
755 __le64 tx_errors;
756 __le32 tx_multi_collision;
6e85d5ad
CV		 757 __le16 tx_aborted;
758};
759
da78dbff 760enum rtl_flag {
6c4a70c5 761 RTL_FLAG_TASK_ENABLED,
da78dbff
FR		 762 RTL_FLAG_TASK_SLOW_PENDING,
763 RTL_FLAG_TASK_RESET_PENDING,
764 RTL_FLAG_TASK_PHY_PENDING,
765 RTL_FLAG_MAX
766};
767
8027aa24
JW		 768struct rtl8169_stats {
769 u64 packets;
770 u64 bytes;
771 struct u64_stats_sync syncp;
772};
773
1da177e4
LT		 774struct rtl8169_private {
775 void __iomem *mmio_addr; /* memory map physical address */
cecb5fd7 776 struct pci_dev *pci_dev;
c4028958 777 struct net_device *dev;
bea3348e 778 struct napi_struct napi;
b57b7e5a 779 u32 msg_enable;
2b7b4318
FR		 780 u16 txd_version;
781 u16 mac_version;
1da177e4
LT		 782 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
783 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
1da177e4 784 u32 dirty_tx;
8027aa24
JW		 785 struct rtl8169_stats rx_stats;
786 struct rtl8169_stats tx_stats;
1da177e4
LT		 787 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
788 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
789 dma_addr_t TxPhyAddr;
790 dma_addr_t RxPhyAddr;
6f0333b8 791 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
1da177e4 792 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
1da177e4
LT		 793 struct timer_list timer;
794 u16 cp_cmd;
da78dbff
FR		 795
796 u16 event_slow;
c0e45c1c 797
798 struct mdio_ops {
24192210
FR		 799 void (*write)(struct rtl8169_private *, int, int);
800 int (*read)(struct rtl8169_private *, int);
c0e45c1c 801 } mdio_ops;
802
065c27c1 803 struct pll_power_ops {
804 void (*down)(struct rtl8169_private *);
805 void (*up)(struct rtl8169_private *);
806 } pll_power_ops;
807
d58d46b5
FR		 808 struct jumbo_ops {
809 void (*enable)(struct rtl8169_private *);
810 void (*disable)(struct rtl8169_private *);
811 } jumbo_ops;
812
beb1fe18 813 struct csi_ops {
52989f0e
FR		 814 void (*write)(struct rtl8169_private *, int, int);
815 u32 (*read)(struct rtl8169_private *, int);
beb1fe18
HW		 816 } csi_ops;
817
54405cde 818 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
ccdffb9a 819 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
4da19633 820 void (*phy_reset_enable)(struct rtl8169_private *tp);
07ce4064 821 void (*hw_start)(struct net_device *);
4da19633 822 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
1da177e4 823 unsigned int (*link_ok)(void __iomem *);
8b4ab28d 824 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
5888d3fc 825 bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
4422bcd4
FR		 826
827 struct {
da78dbff
FR		 828 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
829 struct mutex mutex;
4422bcd4
FR		 830 struct work_struct work;
831 } wk;
832
f23e7fda 833 unsigned features;
ccdffb9a
FR		 834
835 struct mii_if_info mii;
42020320
CV		 836 dma_addr_t counters_phys_addr;
837 struct rtl8169_counters *counters;
6e85d5ad 838 struct rtl8169_tc_offsets tc_offset;
e1759441 839 u32 saved_wolopts;
e03f33af 840 u32 opts1_mask;
f1e02ed1 841
b6ffd97f
FR		 842 struct rtl_fw {
843 const struct firmware *fw;
1c361efb
FR		 844
845#define RTL_VER_SIZE 32
846
847 char version[RTL_VER_SIZE];
848
849 struct rtl_fw_phy_action {
850 __le32 *code;
851 size_t size;
852 } phy_action;
b6ffd97f 853 } *rtl_fw;
497888cf 854#define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
c558386b
HW		 855
856 u32 ocp_base;
1da177e4
LT		 857};
858
979b6c13 859MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 860MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 861module_param(use_dac, int, 0);
4300e8c7 862MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 863module_param_named(debug, debug.msg_enable, int, 0);
864MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 865MODULE_LICENSE("GPL");
866MODULE_VERSION(RTL8169_VERSION);
bca03d5f 867MODULE_FIRMWARE(FIRMWARE_8168D_1);
868MODULE_FIRMWARE(FIRMWARE_8168D_2);
01dc7fec 869MODULE_FIRMWARE(FIRMWARE_8168E_1);
870MODULE_FIRMWARE(FIRMWARE_8168E_2);
bbb8af75 871MODULE_FIRMWARE(FIRMWARE_8168E_3);
5a5e4443 872MODULE_FIRMWARE(FIRMWARE_8105E_1);
c2218925
HW		 873MODULE_FIRMWARE(FIRMWARE_8168F_1);
874MODULE_FIRMWARE(FIRMWARE_8168F_2);
7e18dca1 875MODULE_FIRMWARE(FIRMWARE_8402_1);
b3d7b2f2 876MODULE_FIRMWARE(FIRMWARE_8411_1);
45dd95c4 877MODULE_FIRMWARE(FIRMWARE_8411_2);
5598bfe5 878MODULE_FIRMWARE(FIRMWARE_8106E_1);
58152cd4 879MODULE_FIRMWARE(FIRMWARE_8106E_2);
beb330a4 880MODULE_FIRMWARE(FIRMWARE_8168G_2);
57538c4a 881MODULE_FIRMWARE(FIRMWARE_8168G_3);
6e1d0b89
CHL		 882MODULE_FIRMWARE(FIRMWARE_8168H_1);
883MODULE_FIRMWARE(FIRMWARE_8168H_2);
a3bf5c42
FR		 884MODULE_FIRMWARE(FIRMWARE_8107E_1);
885MODULE_FIRMWARE(FIRMWARE_8107E_2);
1da177e4 886
da78dbff
FR		 887static void rtl_lock_work(struct rtl8169_private *tp)
888{
889 mutex_lock(&tp->wk.mutex);
890}
891
892static void rtl_unlock_work(struct rtl8169_private *tp)
893{
894 mutex_unlock(&tp->wk.mutex);
895}
896
d58d46b5
FR		 897static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
898{
7d7903b2
JL		 899 pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
900 PCI_EXP_DEVCTL_READRQ, force);
d58d46b5
FR		 901}
902
ffc46952
FR		 903struct rtl_cond {
904 bool (*check)(struct rtl8169_private *);
905 const char *msg;
906};
907
908static void rtl_udelay(unsigned int d)
909{
910 udelay(d);
911}
912
913static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
914 void (*delay)(unsigned int), unsigned int d, int n,
915 bool high)
916{
917 int i;
918
919 for (i = 0; i < n; i++) {
920 delay(d);
921 if (c->check(tp) == high)
922 return true;
923 }
82e316ef
FR		 924 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
925 c->msg, !high, n, d);
ffc46952
FR		 926 return false;
927}
928
929static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
930 const struct rtl_cond *c,
931 unsigned int d, int n)
932{
933 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
934}
935
936static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
937 const struct rtl_cond *c,
938 unsigned int d, int n)
939{
940 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
941}
942
943static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
944 const struct rtl_cond *c,
945 unsigned int d, int n)
946{
947 return rtl_loop_wait(tp, c, msleep, d, n, true);
948}
949
950static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
951 const struct rtl_cond *c,
952 unsigned int d, int n)
953{
954 return rtl_loop_wait(tp, c, msleep, d, n, false);
955}
956
957#define DECLARE_RTL_COND(name) \
958static bool name ## _check(struct rtl8169_private *); \
959 \
960static const struct rtl_cond name = { \
961 .check = name ## _check, \
962 .msg = #name \
963}; \
964 \
965static bool name ## _check(struct rtl8169_private *tp)
966
c558386b
HW		 967static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
968{
969 if (reg & 0xffff0001) {
970 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
971 return true;
972 }
973 return false;
974}
975
976DECLARE_RTL_COND(rtl_ocp_gphy_cond)
977{
978 void __iomem *ioaddr = tp->mmio_addr;
979
980 return RTL_R32(GPHY_OCP) & OCPAR_FLAG;
981}
982
983static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
984{
985 void __iomem *ioaddr = tp->mmio_addr;
986
987 if (rtl_ocp_reg_failure(tp, reg))
988 return;
989
990 RTL_W32(GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
991
992 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
993}
994
995static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
996{
997 void __iomem *ioaddr = tp->mmio_addr;
998
999 if (rtl_ocp_reg_failure(tp, reg))
1000 return 0;
1001
1002 RTL_W32(GPHY_OCP, reg << 15);
1003
1004 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
1005 (RTL_R32(GPHY_OCP) & 0xffff) : ~0;
1006}
1007
c558386b
HW		 1008static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1009{
1010 void __iomem *ioaddr = tp->mmio_addr;
1011
1012 if (rtl_ocp_reg_failure(tp, reg))
1013 return;
1014
1015 RTL_W32(OCPDR, OCPAR_FLAG | (reg << 15) | data);
c558386b
HW		 1016}
1017
1018static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1019{
1020 void __iomem *ioaddr = tp->mmio_addr;
1021
1022 if (rtl_ocp_reg_failure(tp, reg))
1023 return 0;
1024
1025 RTL_W32(OCPDR, reg << 15);
1026
3a83ad12 1027 return RTL_R32(OCPDR);
c558386b
HW		 1028}
1029
1030#define OCP_STD_PHY_BASE 0xa400
1031
1032static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
1033{
1034 if (reg == 0x1f) {
1035 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
1036 return;
1037 }
1038
1039 if (tp->ocp_base != OCP_STD_PHY_BASE)
1040 reg -= 0x10;
1041
1042 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
1043}
1044
1045static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1046{
1047 if (tp->ocp_base != OCP_STD_PHY_BASE)
1048 reg -= 0x10;
1049
1050 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
1051}
1052
eee3786f 1053static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
1054{
1055 if (reg == 0x1f) {
1056 tp->ocp_base = value << 4;
1057 return;
1058 }
1059
1060 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
1061}
1062
1063static int mac_mcu_read(struct rtl8169_private *tp, int reg)
1064{
1065 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
1066}
1067
ffc46952
FR		 1068DECLARE_RTL_COND(rtl_phyar_cond)
1069{
1070 void __iomem *ioaddr = tp->mmio_addr;
1071
1072 return RTL_R32(PHYAR) & 0x80000000;
1073}
1074
24192210 1075static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1da177e4 1076{
24192210 1077 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 1078
24192210 1079 RTL_W32(PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1da177e4 1080
ffc46952 1081 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
024a07ba 1082 /*
81a95f04
TT		 1083 * According to hardware specs a 20us delay is required after write
1084 * complete indication, but before sending next command.
024a07ba 1085 */
81a95f04 1086 udelay(20);
1da177e4
LT		 1087}
1088
24192210 1089static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1da177e4 1090{
24192210 1091 void __iomem *ioaddr = tp->mmio_addr;
ffc46952 1092 int value;
1da177e4 1093
24192210 1094 RTL_W32(PHYAR, 0x0 | (reg & 0x1f) << 16);
1da177e4 1095
ffc46952
FR		 1096 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1097 RTL_R32(PHYAR) & 0xffff : ~0;
1098
81a95f04
TT		 1099 /*
1100 * According to hardware specs a 20us delay is required after read
1101 * complete indication, but before sending next command.
1102 */
1103 udelay(20);
1104
1da177e4
LT		 1105 return value;
1106}
1107
935e2218
CHL		 1108DECLARE_RTL_COND(rtl_ocpar_cond)
1109{
1110 void __iomem *ioaddr = tp->mmio_addr;
1111
1112 return RTL_R32(OCPAR) & OCPAR_FLAG;
1113}
1114
24192210 1115static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
c0e45c1c 1116{
24192210 1117 void __iomem *ioaddr = tp->mmio_addr;
c0e45c1c 1118
24192210 1119 RTL_W32(OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
c0e45c1c 1120 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
1121 RTL_W32(EPHY_RXER_NUM, 0);
1122
ffc46952 1123 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
c0e45c1c 1124}
1125
24192210 1126static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
c0e45c1c 1127{
24192210
FR		 1128 r8168dp_1_mdio_access(tp, reg,
1129 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
c0e45c1c 1130}
1131
24192210 1132static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
c0e45c1c 1133{
24192210 1134 void __iomem *ioaddr = tp->mmio_addr;
c0e45c1c 1135
24192210 1136 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
c0e45c1c 1137
1138 mdelay(1);
1139 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
1140 RTL_W32(EPHY_RXER_NUM, 0);
1141
ffc46952
FR		 1142 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1143 RTL_R32(OCPDR) & OCPDR_DATA_MASK : ~0;
c0e45c1c 1144}
1145
e6de30d6 1146#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1147
1148static void r8168dp_2_mdio_start(void __iomem *ioaddr)
1149{
1150 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1151}
1152
1153static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
1154{
1155 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1156}
1157
24192210 1158static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
e6de30d6 1159{
24192210
FR		 1160 void __iomem *ioaddr = tp->mmio_addr;
1161
e6de30d6 1162 r8168dp_2_mdio_start(ioaddr);
1163
24192210 1164 r8169_mdio_write(tp, reg, value);
e6de30d6 1165
1166 r8168dp_2_mdio_stop(ioaddr);
1167}
1168
24192210 1169static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
e6de30d6 1170{
24192210 1171 void __iomem *ioaddr = tp->mmio_addr;
e6de30d6 1172 int value;
1173
1174 r8168dp_2_mdio_start(ioaddr);
1175
24192210 1176 value = r8169_mdio_read(tp, reg);
e6de30d6 1177
1178 r8168dp_2_mdio_stop(ioaddr);
1179
1180 return value;
1181}
1182
4da19633 1183static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
dacf8154 1184{
24192210 1185 tp->mdio_ops.write(tp, location, val);
dacf8154
FR		 1186}
1187
4da19633 1188static int rtl_readphy(struct rtl8169_private *tp, int location)
1189{
24192210 1190 return tp->mdio_ops.read(tp, location);
4da19633 1191}
1192
1193static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1194{
1195 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1196}
1197
76564428 1198static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
daf9df6d 1199{
1200 int val;
1201
4da19633 1202 val = rtl_readphy(tp, reg_addr);
76564428 1203 rtl_writephy(tp, reg_addr, (val & ~m) | p);
daf9df6d 1204}
1205
ccdffb9a
FR		 1206static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1207 int val)
1208{
1209 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1210
4da19633 1211 rtl_writephy(tp, location, val);
ccdffb9a
FR		 1212}
1213
1214static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1215{
1216 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1217
4da19633 1218 return rtl_readphy(tp, location);
ccdffb9a
FR		 1219}
1220
ffc46952
FR		 1221DECLARE_RTL_COND(rtl_ephyar_cond)
1222{
1223 void __iomem *ioaddr = tp->mmio_addr;
1224
1225 return RTL_R32(EPHYAR) & EPHYAR_FLAG;
1226}
1227
fdf6fc06 1228static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
dacf8154 1229{
fdf6fc06 1230 void __iomem *ioaddr = tp->mmio_addr;
dacf8154
FR		 1231
1232 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1233 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1234
ffc46952
FR		 1235 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1236
1237 udelay(10);
dacf8154
FR		 1238}
1239
fdf6fc06 1240static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
dacf8154 1241{
fdf6fc06 1242 void __iomem *ioaddr = tp->mmio_addr;
dacf8154
FR		 1243
1244 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1245
ffc46952
FR		 1246 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1247 RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0;
dacf8154
FR		 1248}
1249
935e2218
CHL		 1250DECLARE_RTL_COND(rtl_eriar_cond)
1251{
1252 void __iomem *ioaddr = tp->mmio_addr;
1253
1254 return RTL_R32(ERIAR) & ERIAR_FLAG;
1255}
1256
fdf6fc06
FR		 1257static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1258 u32 val, int type)
133ac40a 1259{
fdf6fc06 1260 void __iomem *ioaddr = tp->mmio_addr;
133ac40a
HW		 1261
1262 BUG_ON((addr & 3) || (mask == 0));
1263 RTL_W32(ERIDR, val);
1264 RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1265
ffc46952 1266 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
133ac40a
HW		 1267}
1268
fdf6fc06 1269static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
133ac40a 1270{
fdf6fc06 1271 void __iomem *ioaddr = tp->mmio_addr;
133ac40a
HW		 1272
1273 RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1274
ffc46952
FR		 1275 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1276 RTL_R32(ERIDR) : ~0;
133ac40a
HW		 1277}
1278
706123d0 1279static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
fdf6fc06 1280 u32 m, int type)
133ac40a
HW		 1281{
1282 u32 val;
1283
fdf6fc06
FR		 1284 val = rtl_eri_read(tp, addr, type);
1285 rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
133ac40a
HW		 1286}
1287
935e2218
CHL		 1288static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1289{
1290 void __iomem *ioaddr = tp->mmio_addr;
1291
1292 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1293 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1294 RTL_R32(OCPDR) : ~0;
1295}
1296
1297static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1298{
1299 return rtl_eri_read(tp, reg, ERIAR_OOB);
1300}
1301
1302static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1303{
1304 switch (tp->mac_version) {
1305 case RTL_GIGA_MAC_VER_27:
1306 case RTL_GIGA_MAC_VER_28:
1307 case RTL_GIGA_MAC_VER_31:
1308 return r8168dp_ocp_read(tp, mask, reg);
1309 case RTL_GIGA_MAC_VER_49:
1310 case RTL_GIGA_MAC_VER_50:
1311 case RTL_GIGA_MAC_VER_51:
1312 return r8168ep_ocp_read(tp, mask, reg);
1313 default:
1314 BUG();
1315 return ~0;
1316 }
1317}
1318
1319static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1320 u32 data)
1321{
1322 void __iomem *ioaddr = tp->mmio_addr;
1323
1324 RTL_W32(OCPDR, data);
1325 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1326 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1327}
1328
1329static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1330 u32 data)
1331{
1332 rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1333 data, ERIAR_OOB);
1334}
1335
1336static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
1337{
1338 switch (tp->mac_version) {
1339 case RTL_GIGA_MAC_VER_27:
1340 case RTL_GIGA_MAC_VER_28:
1341 case RTL_GIGA_MAC_VER_31:
1342 r8168dp_ocp_write(tp, mask, reg, data);
1343 break;
1344 case RTL_GIGA_MAC_VER_49:
1345 case RTL_GIGA_MAC_VER_50:
1346 case RTL_GIGA_MAC_VER_51:
1347 r8168ep_ocp_write(tp, mask, reg, data);
1348 break;
1349 default:
1350 BUG();
1351 break;
1352 }
1353}
1354
2a9b4d96
CHL		 1355static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
1356{
1357 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC);
1358
1359 ocp_write(tp, 0x1, 0x30, 0x00000001);
1360}
1361
1362#define OOB_CMD_RESET 0x00
1363#define OOB_CMD_DRIVER_START 0x05
1364#define OOB_CMD_DRIVER_STOP 0x06
1365
1366static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1367{
1368 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1369}
1370
1371DECLARE_RTL_COND(rtl_ocp_read_cond)
1372{
1373 u16 reg;
1374
1375 reg = rtl8168_get_ocp_reg(tp);
1376
1377 return ocp_read(tp, 0x0f, reg) & 0x00000800;
1378}
1379
935e2218 1380DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
2a9b4d96 1381{
935e2218
CHL		 1382 return ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1383}
1384
1385DECLARE_RTL_COND(rtl_ocp_tx_cond)
1386{
1387 void __iomem *ioaddr = tp->mmio_addr;
1388
1389 return RTL_R8(IBISR0) & 0x02;
1390}
2a9b4d96 1391
003609da
CHL		 1392static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1393{
1394 void __iomem *ioaddr = tp->mmio_addr;
1395
1396 RTL_W8(IBCR2, RTL_R8(IBCR2) & ~0x01);
1397 rtl_msleep_loop_wait_low(tp, &rtl_ocp_tx_cond, 50, 2000);
1398 RTL_W8(IBISR0, RTL_R8(IBISR0) | 0x20);
1399 RTL_W8(IBCR0, RTL_R8(IBCR0) & ~0x01);
1400}
1401
935e2218
CHL		 1402static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1403{
1404 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
2a9b4d96
CHL		 1405 rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
1406}
1407
935e2218 1408static void rtl8168ep_driver_start(struct rtl8169_private *tp)
2a9b4d96 1409{
935e2218
CHL		 1410 ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1411 ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1412 rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1413}
1414
1415static void rtl8168_driver_start(struct rtl8169_private *tp)
1416{
1417 switch (tp->mac_version) {
1418 case RTL_GIGA_MAC_VER_27:
1419 case RTL_GIGA_MAC_VER_28:
1420 case RTL_GIGA_MAC_VER_31:
1421 rtl8168dp_driver_start(tp);
1422 break;
1423 case RTL_GIGA_MAC_VER_49:
1424 case RTL_GIGA_MAC_VER_50:
1425 case RTL_GIGA_MAC_VER_51:
1426 rtl8168ep_driver_start(tp);
1427 break;
1428 default:
1429 BUG();
1430 break;
1431 }
1432}
2a9b4d96 1433
935e2218
CHL		 1434static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1435{
1436 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
2a9b4d96
CHL		 1437 rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
1438}
1439
935e2218
CHL		 1440static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1441{
003609da 1442 rtl8168ep_stop_cmac(tp);
935e2218
CHL		 1443 ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1444 ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1445 rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1446}
1447
1448static void rtl8168_driver_stop(struct rtl8169_private *tp)
1449{
1450 switch (tp->mac_version) {
1451 case RTL_GIGA_MAC_VER_27:
1452 case RTL_GIGA_MAC_VER_28:
1453 case RTL_GIGA_MAC_VER_31:
1454 rtl8168dp_driver_stop(tp);
1455 break;
1456 case RTL_GIGA_MAC_VER_49:
1457 case RTL_GIGA_MAC_VER_50:
1458 case RTL_GIGA_MAC_VER_51:
1459 rtl8168ep_driver_stop(tp);
1460 break;
1461 default:
1462 BUG();
1463 break;
1464 }
1465}
1466
1467static int r8168dp_check_dash(struct rtl8169_private *tp)
2a9b4d96
CHL		 1468{
1469 u16 reg = rtl8168_get_ocp_reg(tp);
1470
1471 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
1472}
1473
935e2218
CHL		 1474static int r8168ep_check_dash(struct rtl8169_private *tp)
1475{
1476 return (ocp_read(tp, 0x0f, 0x128) & 0x00000001) ? 1 : 0;
1477}
1478
1479static int r8168_check_dash(struct rtl8169_private *tp)
1480{
1481 switch (tp->mac_version) {
1482 case RTL_GIGA_MAC_VER_27:
1483 case RTL_GIGA_MAC_VER_28:
1484 case RTL_GIGA_MAC_VER_31:
1485 return r8168dp_check_dash(tp);
1486 case RTL_GIGA_MAC_VER_49:
1487 case RTL_GIGA_MAC_VER_50:
1488 case RTL_GIGA_MAC_VER_51:
1489 return r8168ep_check_dash(tp);
1490 default:
1491 return 0;
1492 }
1493}
1494
c28aa385 1495struct exgmac_reg {
1496 u16 addr;
1497 u16 mask;
1498 u32 val;
1499};
1500
fdf6fc06 1501static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
c28aa385 1502 const struct exgmac_reg *r, int len)
1503{
1504 while (len-- > 0) {
fdf6fc06 1505 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
c28aa385 1506 r++;
1507 }
1508}
1509
ffc46952
FR		 1510DECLARE_RTL_COND(rtl_efusear_cond)
1511{
1512 void __iomem *ioaddr = tp->mmio_addr;
1513
1514 return RTL_R32(EFUSEAR) & EFUSEAR_FLAG;
1515}
1516
fdf6fc06 1517static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
daf9df6d 1518{
fdf6fc06 1519 void __iomem *ioaddr = tp->mmio_addr;
daf9df6d 1520
1521 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1522
ffc46952
FR		 1523 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1524 RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
daf9df6d 1525}
1526
9085cdfa
FR		 1527static u16 rtl_get_events(struct rtl8169_private *tp)
1528{
1529 void __iomem *ioaddr = tp->mmio_addr;
1530
1531 return RTL_R16(IntrStatus);
1532}
1533
1534static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1535{
1536 void __iomem *ioaddr = tp->mmio_addr;
1537
1538 RTL_W16(IntrStatus, bits);
1539 mmiowb();
1540}
1541
1542static void rtl_irq_disable(struct rtl8169_private *tp)
1543{
1544 void __iomem *ioaddr = tp->mmio_addr;
1545
1546 RTL_W16(IntrMask, 0);
1547 mmiowb();
1548}
1549
3e990ff5
FR		 1550static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1551{
1552 void __iomem *ioaddr = tp->mmio_addr;
1553
1554 RTL_W16(IntrMask, bits);
1555}
1556
da78dbff
FR		 1557#define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1558#define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1559#define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1560
1561static void rtl_irq_enable_all(struct rtl8169_private *tp)
1562{
1563 rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1564}
1565
811fd301 1566static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1da177e4 1567{
811fd301 1568 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 1569
9085cdfa 1570 rtl_irq_disable(tp);
da78dbff 1571 rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
811fd301 1572 RTL_R8(ChipCmd);
1da177e4
LT		 1573}
1574
4da19633 1575static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1da177e4 1576{
4da19633 1577 void __iomem *ioaddr = tp->mmio_addr;
1578
1da177e4
LT		 1579 return RTL_R32(TBICSR) & TBIReset;
1580}
1581
4da19633 1582static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1da177e4 1583{
4da19633 1584 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 1585}
1586
1587static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1588{
1589 return RTL_R32(TBICSR) & TBILinkOk;
1590}
1591
1592static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1593{
1594 return RTL_R8(PHYstatus) & LinkStatus;
1595}
1596
4da19633 1597static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1da177e4 1598{
4da19633 1599 void __iomem *ioaddr = tp->mmio_addr;
1600
1da177e4
LT		 1601 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1602}
1603
4da19633 1604static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1da177e4
LT		 1605{
1606 unsigned int val;
1607
4da19633 1608 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1609 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1da177e4
LT		 1610}
1611
70090424
HW		 1612static void rtl_link_chg_patch(struct rtl8169_private *tp)
1613{
1614 void __iomem *ioaddr = tp->mmio_addr;
1615 struct net_device *dev = tp->dev;
1616
1617 if (!netif_running(dev))
1618 return;
1619
b3d7b2f2
HW		 1620 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1621 tp->mac_version == RTL_GIGA_MAC_VER_38) {
70090424 1622 if (RTL_R8(PHYstatus) & _1000bpsF) {
fdf6fc06
FR		 1623 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1624 ERIAR_EXGMAC);
1625 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1626 ERIAR_EXGMAC);
70090424 1627 } else if (RTL_R8(PHYstatus) & _100bps) {
fdf6fc06
FR		 1628 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1629 ERIAR_EXGMAC);
1630 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1631 ERIAR_EXGMAC);
70090424 1632 } else {
fdf6fc06
FR		 1633 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1634 ERIAR_EXGMAC);
1635 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1636 ERIAR_EXGMAC);
70090424
HW		 1637 }
1638 /* Reset packet filter */
706123d0 1639 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
70090424 1640 ERIAR_EXGMAC);
706123d0 1641 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
70090424 1642 ERIAR_EXGMAC);
c2218925
HW		 1643 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1644 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1645 if (RTL_R8(PHYstatus) & _1000bpsF) {
fdf6fc06
FR		 1646 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1647 ERIAR_EXGMAC);
1648 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1649 ERIAR_EXGMAC);
c2218925 1650 } else {
fdf6fc06
FR		 1651 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1652 ERIAR_EXGMAC);
1653 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1654 ERIAR_EXGMAC);
c2218925 1655 }
7e18dca1
HW		 1656 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1657 if (RTL_R8(PHYstatus) & _10bps) {
fdf6fc06
FR		 1658 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1659 ERIAR_EXGMAC);
1660 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1661 ERIAR_EXGMAC);
7e18dca1 1662 } else {
fdf6fc06
FR		 1663 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1664 ERIAR_EXGMAC);
7e18dca1 1665 }
70090424
HW		 1666 }
1667}
1668
e4fbce74 1669static void __rtl8169_check_link_status(struct net_device *dev,
cecb5fd7
FR		 1670 struct rtl8169_private *tp,
1671 void __iomem *ioaddr, bool pm)
1da177e4 1672{
1da177e4 1673 if (tp->link_ok(ioaddr)) {
70090424 1674 rtl_link_chg_patch(tp);
e1759441 1675 /* This is to cancel a scheduled suspend if there's one. */
e4fbce74
RW		 1676 if (pm)
1677 pm_request_resume(&tp->pci_dev->dev);
1da177e4 1678 netif_carrier_on(dev);
1519e57f
FR		 1679 if (net_ratelimit())
1680 netif_info(tp, ifup, dev, "link up\n");
b57b7e5a 1681 } else {
1da177e4 1682 netif_carrier_off(dev);
bf82c189 1683 netif_info(tp, ifdown, dev, "link down\n");
e4fbce74 1684 if (pm)
10953db8 1685 pm_schedule_suspend(&tp->pci_dev->dev, 5000);
b57b7e5a 1686 }
1da177e4
LT		 1687}
1688
e4fbce74
RW		 1689static void rtl8169_check_link_status(struct net_device *dev,
1690 struct rtl8169_private *tp,
1691 void __iomem *ioaddr)
1692{
1693 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1694}
1695
e1759441
RW		 1696#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1697
1698static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
61a4dcc2 1699{
61a4dcc2
FR		 1700 void __iomem *ioaddr = tp->mmio_addr;
1701 u8 options;
e1759441 1702 u32 wolopts = 0;
61a4dcc2
FR		 1703
1704 options = RTL_R8(Config1);
1705 if (!(options & PMEnable))
e1759441 1706 return 0;
61a4dcc2
FR		 1707
1708 options = RTL_R8(Config3);
1709 if (options & LinkUp)
e1759441 1710 wolopts |= WAKE_PHY;
6e1d0b89 1711 switch (tp->mac_version) {
ac85bcdb
CHL		 1712 case RTL_GIGA_MAC_VER_34:
1713 case RTL_GIGA_MAC_VER_35:
1714 case RTL_GIGA_MAC_VER_36:
1715 case RTL_GIGA_MAC_VER_37:
1716 case RTL_GIGA_MAC_VER_38:
1717 case RTL_GIGA_MAC_VER_40:
1718 case RTL_GIGA_MAC_VER_41:
1719 case RTL_GIGA_MAC_VER_42:
1720 case RTL_GIGA_MAC_VER_43:
1721 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 1722 case RTL_GIGA_MAC_VER_45:
1723 case RTL_GIGA_MAC_VER_46:
ac85bcdb
CHL		 1724 case RTL_GIGA_MAC_VER_47:
1725 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 1726 case RTL_GIGA_MAC_VER_49:
1727 case RTL_GIGA_MAC_VER_50:
1728 case RTL_GIGA_MAC_VER_51:
6e1d0b89
CHL		 1729 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
1730 wolopts |= WAKE_MAGIC;
1731 break;
1732 default:
1733 if (options & MagicPacket)
1734 wolopts |= WAKE_MAGIC;
1735 break;
1736 }
61a4dcc2
FR		 1737
1738 options = RTL_R8(Config5);
1739 if (options & UWF)
e1759441 1740 wolopts |= WAKE_UCAST;
61a4dcc2 1741 if (options & BWF)
e1759441 1742 wolopts |= WAKE_BCAST;
61a4dcc2 1743 if (options & MWF)
e1759441 1744 wolopts |= WAKE_MCAST;
61a4dcc2 1745
e1759441 1746 return wolopts;
61a4dcc2
FR		 1747}
1748
e1759441 1749static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
61a4dcc2
FR		 1750{
1751 struct rtl8169_private *tp = netdev_priv(dev);
e1759441 1752
da78dbff 1753 rtl_lock_work(tp);
e1759441
RW		 1754
1755 wol->supported = WAKE_ANY;
1756 wol->wolopts = __rtl8169_get_wol(tp);
1757
da78dbff 1758 rtl_unlock_work(tp);
e1759441
RW		 1759}
1760
1761static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1762{
61a4dcc2 1763 void __iomem *ioaddr = tp->mmio_addr;
6e1d0b89 1764 unsigned int i, tmp;
350f7596 1765 static const struct {
61a4dcc2
FR		 1766 u32 opt;
1767 u16 reg;
1768 u8 mask;
1769 } cfg[] = {
61a4dcc2 1770 { WAKE_PHY, Config3, LinkUp },
61a4dcc2
FR		 1771 { WAKE_UCAST, Config5, UWF },
1772 { WAKE_BCAST, Config5, BWF },
1773 { WAKE_MCAST, Config5, MWF },
6e1d0b89
CHL		 1774 { WAKE_ANY, Config5, LanWake },
1775 { WAKE_MAGIC, Config3, MagicPacket }
61a4dcc2 1776 };
851e6022 1777 u8 options;
61a4dcc2 1778
61a4dcc2
FR		 1779 RTL_W8(Cfg9346, Cfg9346_Unlock);
1780
6e1d0b89 1781 switch (tp->mac_version) {
ac85bcdb
CHL		 1782 case RTL_GIGA_MAC_VER_34:
1783 case RTL_GIGA_MAC_VER_35:
1784 case RTL_GIGA_MAC_VER_36:
1785 case RTL_GIGA_MAC_VER_37:
1786 case RTL_GIGA_MAC_VER_38:
1787 case RTL_GIGA_MAC_VER_40:
1788 case RTL_GIGA_MAC_VER_41:
1789 case RTL_GIGA_MAC_VER_42:
1790 case RTL_GIGA_MAC_VER_43:
1791 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 1792 case RTL_GIGA_MAC_VER_45:
1793 case RTL_GIGA_MAC_VER_46:
ac85bcdb
CHL		 1794 case RTL_GIGA_MAC_VER_47:
1795 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 1796 case RTL_GIGA_MAC_VER_49:
1797 case RTL_GIGA_MAC_VER_50:
1798 case RTL_GIGA_MAC_VER_51:
6e1d0b89
CHL		 1799 tmp = ARRAY_SIZE(cfg) - 1;
1800 if (wolopts & WAKE_MAGIC)
706123d0 1801 rtl_w0w1_eri(tp,
6e1d0b89
CHL		 1802 0x0dc,
1803 ERIAR_MASK_0100,
1804 MagicPacket_v2,
1805 0x0000,
1806 ERIAR_EXGMAC);
1807 else
706123d0 1808 rtl_w0w1_eri(tp,
6e1d0b89
CHL		 1809 0x0dc,
1810 ERIAR_MASK_0100,
1811 0x0000,
1812 MagicPacket_v2,
1813 ERIAR_EXGMAC);
1814 break;
1815 default:
1816 tmp = ARRAY_SIZE(cfg);
1817 break;
1818 }
1819
1820 for (i = 0; i < tmp; i++) {
851e6022 1821 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
e1759441 1822 if (wolopts & cfg[i].opt)
61a4dcc2
FR		 1823 options |= cfg[i].mask;
1824 RTL_W8(cfg[i].reg, options);
1825 }
1826
851e6022
FR		 1827 switch (tp->mac_version) {
1828 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1829 options = RTL_R8(Config1) & ~PMEnable;
1830 if (wolopts)
1831 options |= PMEnable;
1832 RTL_W8(Config1, options);
1833 break;
1834 default:
d387b427
FR		 1835 options = RTL_R8(Config2) & ~PME_SIGNAL;
1836 if (wolopts)
1837 options |= PME_SIGNAL;
1838 RTL_W8(Config2, options);
851e6022
FR		 1839 break;
1840 }
1841
61a4dcc2 1842 RTL_W8(Cfg9346, Cfg9346_Lock);
e1759441
RW		 1843}
1844
1845static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1846{
1847 struct rtl8169_private *tp = netdev_priv(dev);
1848
da78dbff 1849 rtl_lock_work(tp);
61a4dcc2 1850
f23e7fda
FR		 1851 if (wol->wolopts)
1852 tp->features |= RTL_FEATURE_WOL;
1853 else
1854 tp->features &= ~RTL_FEATURE_WOL;
e1759441 1855 __rtl8169_set_wol(tp, wol->wolopts);
da78dbff
FR		 1856
1857 rtl_unlock_work(tp);
61a4dcc2 1858
ea80907f 1859 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1860
61a4dcc2
FR		 1861 return 0;
1862}
1863
31bd204f
FR		 1864static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1865{
85bffe6c 1866 return rtl_chip_infos[tp->mac_version].fw_name;
31bd204f
FR		 1867}
1868
1da177e4
LT		 1869static void rtl8169_get_drvinfo(struct net_device *dev,
1870 struct ethtool_drvinfo *info)
1871{
1872 struct rtl8169_private *tp = netdev_priv(dev);
b6ffd97f 1873 struct rtl_fw *rtl_fw = tp->rtl_fw;
1da177e4 1874
68aad78c
RJ		 1875 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1876 strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1877 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1c361efb 1878 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
8ac72d16
RJ		 1879 if (!IS_ERR_OR_NULL(rtl_fw))
1880 strlcpy(info->fw_version, rtl_fw->version,
1881 sizeof(info->fw_version));
1da177e4
LT		 1882}
1883
1884static int rtl8169_get_regs_len(struct net_device *dev)
1885{
1886 return R8169_REGS_SIZE;
1887}
1888
1889static int rtl8169_set_speed_tbi(struct net_device *dev,
54405cde 1890 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1da177e4
LT		 1891{
1892 struct rtl8169_private *tp = netdev_priv(dev);
1893 void __iomem *ioaddr = tp->mmio_addr;
1894 int ret = 0;
1895 u32 reg;
1896
1897 reg = RTL_R32(TBICSR);
1898 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1899 (duplex == DUPLEX_FULL)) {
1900 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1901 } else if (autoneg == AUTONEG_ENABLE)
1902 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1903 else {
bf82c189
JP		 1904 netif_warn(tp, link, dev,
1905 "incorrect speed setting refused in TBI mode\n");
1da177e4
LT		 1906 ret = -EOPNOTSUPP;
1907 }
1908
1909 return ret;
1910}
1911
1912static int rtl8169_set_speed_xmii(struct net_device *dev,
54405cde 1913 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1da177e4
LT		 1914{
1915 struct rtl8169_private *tp = netdev_priv(dev);
3577aa1b 1916 int giga_ctrl, bmcr;
54405cde 1917 int rc = -EINVAL;
1da177e4 1918
716b50a3 1919 rtl_writephy(tp, 0x1f, 0x0000);
1da177e4
LT		 1920
1921 if (autoneg == AUTONEG_ENABLE) {
3577aa1b 1922 int auto_nego;
1923
4da19633 1924 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
54405cde
ON		 1925 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1926 ADVERTISE_100HALF | ADVERTISE_100FULL);
1927
1928 if (adv & ADVERTISED_10baseT_Half)
1929 auto_nego |= ADVERTISE_10HALF;
1930 if (adv & ADVERTISED_10baseT_Full)
1931 auto_nego |= ADVERTISE_10FULL;
1932 if (adv & ADVERTISED_100baseT_Half)
1933 auto_nego |= ADVERTISE_100HALF;
1934 if (adv & ADVERTISED_100baseT_Full)
1935 auto_nego |= ADVERTISE_100FULL;
1936
3577aa1b 1937 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1da177e4 1938
4da19633 1939 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
3577aa1b 1940 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
bcf0bf90 1941
3577aa1b 1942 /* The 8100e/8101e/8102e do Fast Ethernet only. */
826e6cbd 1943 if (tp->mii.supports_gmii) {
54405cde
ON		 1944 if (adv & ADVERTISED_1000baseT_Half)
1945 giga_ctrl |= ADVERTISE_1000HALF;
1946 if (adv & ADVERTISED_1000baseT_Full)
1947 giga_ctrl |= ADVERTISE_1000FULL;
1948 } else if (adv & (ADVERTISED_1000baseT_Half |
1949 ADVERTISED_1000baseT_Full)) {
bf82c189
JP		 1950 netif_info(tp, link, dev,
1951 "PHY does not support 1000Mbps\n");
54405cde 1952 goto out;
bcf0bf90 1953 }
1da177e4 1954
3577aa1b 1955 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1956
4da19633 1957 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1958 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
3577aa1b 1959 } else {
1960 giga_ctrl = 0;
1961
1962 if (speed == SPEED_10)
1963 bmcr = 0;
1964 else if (speed == SPEED_100)
1965 bmcr = BMCR_SPEED100;
1966 else
54405cde 1967 goto out;
3577aa1b 1968
1969 if (duplex == DUPLEX_FULL)
1970 bmcr |= BMCR_FULLDPLX;
2584fbc3
RS		 1971 }
1972
4da19633 1973 rtl_writephy(tp, MII_BMCR, bmcr);
3577aa1b 1974
cecb5fd7
FR		 1975 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1976 tp->mac_version == RTL_GIGA_MAC_VER_03) {
3577aa1b 1977 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
4da19633 1978 rtl_writephy(tp, 0x17, 0x2138);
1979 rtl_writephy(tp, 0x0e, 0x0260);
3577aa1b 1980 } else {
4da19633 1981 rtl_writephy(tp, 0x17, 0x2108);
1982 rtl_writephy(tp, 0x0e, 0x0000);
3577aa1b 1983 }
1984 }
1985
54405cde
ON		 1986 rc = 0;
1987out:
1988 return rc;
1da177e4
LT		 1989}
1990
1991static int rtl8169_set_speed(struct net_device *dev,
54405cde 1992 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1da177e4
LT		 1993{
1994 struct rtl8169_private *tp = netdev_priv(dev);
1995 int ret;
1996
54405cde 1997 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
4876cc1e
FR		 1998 if (ret < 0)
1999 goto out;
1da177e4 2000
4876cc1e
FR		 2001 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
2002 (advertising & ADVERTISED_1000baseT_Full)) {
1da177e4 2003 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
4876cc1e
FR		 2004 }
2005out:
1da177e4
LT		 2006 return ret;
2007}
2008
2009static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2010{
2011 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4
LT		 2012 int ret;
2013
4876cc1e
FR		 2014 del_timer_sync(&tp->timer);
2015
da78dbff 2016 rtl_lock_work(tp);
cecb5fd7 2017 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
25db0338 2018 cmd->duplex, cmd->advertising);
da78dbff 2019 rtl_unlock_work(tp);
5b0384f4 2020
1da177e4
LT		 2021 return ret;
2022}
2023
c8f44aff
MM		 2024static netdev_features_t rtl8169_fix_features(struct net_device *dev,
2025 netdev_features_t features)
1da177e4 2026{
d58d46b5
FR		 2027 struct rtl8169_private *tp = netdev_priv(dev);
2028
2b7b4318 2029 if (dev->mtu > TD_MSS_MAX)
350fb32a 2030 features &= ~NETIF_F_ALL_TSO;
1da177e4 2031
d58d46b5
FR		 2032 if (dev->mtu > JUMBO_1K &&
2033 !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
2034 features &= ~NETIF_F_IP_CSUM;
2035
350fb32a 2036 return features;
1da177e4
LT		 2037}
2038
da78dbff
FR		 2039static void __rtl8169_set_features(struct net_device *dev,
2040 netdev_features_t features)
1da177e4
LT		 2041{
2042 struct rtl8169_private *tp = netdev_priv(dev);
da78dbff 2043 void __iomem *ioaddr = tp->mmio_addr;
929a031d 2044 u32 rx_config;
1da177e4 2045
929a031d 2046 rx_config = RTL_R32(RxConfig);
2047 if (features & NETIF_F_RXALL)
2048 rx_config |= (AcceptErr | AcceptRunt);
2049 else
2050 rx_config &= ~(AcceptErr | AcceptRunt);
1da177e4 2051
929a031d 2052 RTL_W32(RxConfig, rx_config);
350fb32a 2053
929a031d 2054 if (features & NETIF_F_RXCSUM)
2055 tp->cp_cmd |= RxChkSum;
2056 else
2057 tp->cp_cmd &= ~RxChkSum;
6bbe021d 2058
929a031d 2059 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2060 tp->cp_cmd |= RxVlan;
2061 else
2062 tp->cp_cmd &= ~RxVlan;
2063
2064 tp->cp_cmd |= RTL_R16(CPlusCmd) & ~(RxVlan | RxChkSum);
2065
2066 RTL_W16(CPlusCmd, tp->cp_cmd);
2067 RTL_R16(CPlusCmd);
da78dbff 2068}
1da177e4 2069
da78dbff
FR		 2070static int rtl8169_set_features(struct net_device *dev,
2071 netdev_features_t features)
2072{
2073 struct rtl8169_private *tp = netdev_priv(dev);
2074
929a031d 2075 features &= NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX;
2076
da78dbff 2077 rtl_lock_work(tp);
85911d71 2078 if (features ^ dev->features)
929a031d 2079 __rtl8169_set_features(dev, features);
da78dbff 2080 rtl_unlock_work(tp);
1da177e4
LT		 2081
2082 return 0;
2083}
2084
da78dbff 2085
810f4893 2086static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1da177e4 2087{
df8a39de
JP		 2088 return (skb_vlan_tag_present(skb)) ?
2089 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1da177e4
LT		 2090}
2091
7a8fc77b 2092static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1da177e4
LT		 2093{
2094 u32 opts2 = le32_to_cpu(desc->opts2);
1da177e4 2095
7a8fc77b 2096 if (opts2 & RxVlanTag)
86a9bad3 2097 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1da177e4
LT		 2098}
2099
ccdffb9a 2100static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 2101{
2102 struct rtl8169_private *tp = netdev_priv(dev);
2103 void __iomem *ioaddr = tp->mmio_addr;
2104 u32 status;
2105
2106 cmd->supported =
2107 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
2108 cmd->port = PORT_FIBRE;
2109 cmd->transceiver = XCVR_INTERNAL;
2110
2111 status = RTL_R32(TBICSR);
2112 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
2113 cmd->autoneg = !!(status & TBINwEnable);
2114
70739497 2115 ethtool_cmd_speed_set(cmd, SPEED_1000);
1da177e4 2116 cmd->duplex = DUPLEX_FULL; /* Always set */
ccdffb9a
FR		 2117
2118 return 0;
1da177e4
LT		 2119}
2120
ccdffb9a 2121static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 2122{
2123 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a
FR		 2124
2125 return mii_ethtool_gset(&tp->mii, cmd);
1da177e4
LT		 2126}
2127
2128static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2129{
2130 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 2131 int rc;
1da177e4 2132
da78dbff 2133 rtl_lock_work(tp);
ccdffb9a 2134 rc = tp->get_settings(dev, cmd);
da78dbff 2135 rtl_unlock_work(tp);
1da177e4 2136
ccdffb9a 2137 return rc;
1da177e4
LT		 2138}
2139
2140static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2141 void *p)
2142{
5b0384f4 2143 struct rtl8169_private *tp = netdev_priv(dev);
15edae91
PW		 2144 u32 __iomem *data = tp->mmio_addr;
2145 u32 *dw = p;
2146 int i;
1da177e4 2147
da78dbff 2148 rtl_lock_work(tp);
15edae91
PW		 2149 for (i = 0; i < R8169_REGS_SIZE; i += 4)
2150 memcpy_fromio(dw++, data++, 4);
da78dbff 2151 rtl_unlock_work(tp);
1da177e4
LT		 2152}
2153
b57b7e5a
SH		 2154static u32 rtl8169_get_msglevel(struct net_device *dev)
2155{
2156 struct rtl8169_private *tp = netdev_priv(dev);
2157
2158 return tp->msg_enable;
2159}
2160
2161static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
2162{
2163 struct rtl8169_private *tp = netdev_priv(dev);
2164
2165 tp->msg_enable = value;
2166}
2167
d4a3a0fc
SH		 2168static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
2169 "tx_packets",
2170 "rx_packets",
2171 "tx_errors",
2172 "rx_errors",
2173 "rx_missed",
2174 "align_errors",
2175 "tx_single_collisions",
2176 "tx_multi_collisions",
2177 "unicast",
2178 "broadcast",
2179 "multicast",
2180 "tx_aborted",
2181 "tx_underrun",
2182};
2183
b9f2c044 2184static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 2185{
b9f2c044
JG		 2186 switch (sset) {
2187 case ETH_SS_STATS:
2188 return ARRAY_SIZE(rtl8169_gstrings);
2189 default:
2190 return -EOPNOTSUPP;
2191 }
d4a3a0fc
SH		 2192}
2193
42020320 2194DECLARE_RTL_COND(rtl_counters_cond)
6e85d5ad 2195{
6e85d5ad 2196 void __iomem *ioaddr = tp->mmio_addr;
6e85d5ad 2197
42020320 2198 return RTL_R32(CounterAddrLow) & (CounterReset | CounterDump);
6e85d5ad
CV		 2199}
2200
42020320 2201static bool rtl8169_do_counters(struct net_device *dev, u32 counter_cmd)
6e85d5ad
CV		 2202{
2203 struct rtl8169_private *tp = netdev_priv(dev);
2204 void __iomem *ioaddr = tp->mmio_addr;
42020320
CV		 2205 dma_addr_t paddr = tp->counters_phys_addr;
2206 u32 cmd;
2207 bool ret;
6e85d5ad 2208
42020320
CV		 2209 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
2210 cmd = (u64)paddr & DMA_BIT_MASK(32);
2211 RTL_W32(CounterAddrLow, cmd);
2212 RTL_W32(CounterAddrLow, cmd | counter_cmd);
6e85d5ad 2213
42020320 2214 ret = rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
6e85d5ad 2215
42020320
CV		 2216 RTL_W32(CounterAddrLow, 0);
2217 RTL_W32(CounterAddrHigh, 0);
6e85d5ad 2218
42020320 2219 return ret;
6e85d5ad
CV		 2220}
2221
2222static bool rtl8169_reset_counters(struct net_device *dev)
2223{
2224 struct rtl8169_private *tp = netdev_priv(dev);
6e85d5ad
CV		 2225
2226 /*
2227 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
2228 * tally counters.
2229 */
2230 if (tp->mac_version < RTL_GIGA_MAC_VER_19)
2231 return true;
2232
42020320 2233 return rtl8169_do_counters(dev, CounterReset);
ffc46952
FR		 2234}
2235
6e85d5ad 2236static bool rtl8169_update_counters(struct net_device *dev)
d4a3a0fc
SH		 2237{
2238 struct rtl8169_private *tp = netdev_priv(dev);
2239 void __iomem *ioaddr = tp->mmio_addr;
d4a3a0fc 2240
355423d0
IV		 2241 /*
2242 * Some chips are unable to dump tally counters when the receiver
2243 * is disabled.
2244 */
2245 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
6e85d5ad 2246 return true;
d4a3a0fc 2247
42020320 2248 return rtl8169_do_counters(dev, CounterDump);
6e85d5ad
CV		 2249}
2250
2251static bool rtl8169_init_counter_offsets(struct net_device *dev)
2252{
2253 struct rtl8169_private *tp = netdev_priv(dev);
42020320 2254 struct rtl8169_counters *counters = tp->counters;
6e85d5ad
CV		 2255 bool ret = false;
2256
2257 /*
2258 * rtl8169_init_counter_offsets is called from rtl_open. On chip
2259 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
2260 * reset by a power cycle, while the counter values collected by the
2261 * driver are reset at every driver unload/load cycle.
2262 *
2263 * To make sure the HW values returned by @get_stats64 match the SW
2264 * values, we collect the initial values at first open(*) and use them
2265 * as offsets to normalize the values returned by @get_stats64.
2266 *
2267 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
2268 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
2269 * set at open time by rtl_hw_start.
2270 */
2271
2272 if (tp->tc_offset.inited)
2273 return true;
2274
2275 /* If both, reset and update fail, propagate to caller. */
2276 if (rtl8169_reset_counters(dev))
2277 ret = true;
2278
2279 if (rtl8169_update_counters(dev))
2280 ret = true;
2281
42020320
CV		 2282 tp->tc_offset.tx_errors = counters->tx_errors;
2283 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
2284 tp->tc_offset.tx_aborted = counters->tx_aborted;
6e85d5ad
CV		 2285 tp->tc_offset.inited = true;
2286
2287 return ret;
d4a3a0fc
SH		 2288}
2289
355423d0
IV		 2290static void rtl8169_get_ethtool_stats(struct net_device *dev,
2291 struct ethtool_stats *stats, u64 *data)
2292{
2293 struct rtl8169_private *tp = netdev_priv(dev);
42020320 2294 struct rtl8169_counters *counters = tp->counters;
355423d0
IV		 2295
2296 ASSERT_RTNL();
2297
2298 rtl8169_update_counters(dev);
2299
42020320
CV		 2300 data[0] = le64_to_cpu(counters->tx_packets);
2301 data[1] = le64_to_cpu(counters->rx_packets);
2302 data[2] = le64_to_cpu(counters->tx_errors);
2303 data[3] = le32_to_cpu(counters->rx_errors);
2304 data[4] = le16_to_cpu(counters->rx_missed);
2305 data[5] = le16_to_cpu(counters->align_errors);
2306 data[6] = le32_to_cpu(counters->tx_one_collision);
2307 data[7] = le32_to_cpu(counters->tx_multi_collision);
2308 data[8] = le64_to_cpu(counters->rx_unicast);
2309 data[9] = le64_to_cpu(counters->rx_broadcast);
2310 data[10] = le32_to_cpu(counters->rx_multicast);
2311 data[11] = le16_to_cpu(counters->tx_aborted);
2312 data[12] = le16_to_cpu(counters->tx_underun);
355423d0
IV		 2313}
2314
d4a3a0fc
SH		 2315static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2316{
2317 switch(stringset) {
2318 case ETH_SS_STATS:
2319 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
2320 break;
2321 }
2322}
2323
7282d491 2324static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 2325 .get_drvinfo = rtl8169_get_drvinfo,
2326 .get_regs_len = rtl8169_get_regs_len,
2327 .get_link = ethtool_op_get_link,
2328 .get_settings = rtl8169_get_settings,
2329 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 2330 .get_msglevel = rtl8169_get_msglevel,
2331 .set_msglevel = rtl8169_set_msglevel,
1da177e4 2332 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 2333 .get_wol = rtl8169_get_wol,
2334 .set_wol = rtl8169_set_wol,
d4a3a0fc 2335 .get_strings = rtl8169_get_strings,
b9f2c044 2336 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 2337 .get_ethtool_stats = rtl8169_get_ethtool_stats,
e1593bb1 2338 .get_ts_info = ethtool_op_get_ts_info,
1da177e4
LT		 2339};
2340
07d3f51f 2341static void rtl8169_get_mac_version(struct rtl8169_private *tp,
5d320a20 2342 struct net_device *dev, u8 default_version)
1da177e4 2343{
5d320a20 2344 void __iomem *ioaddr = tp->mmio_addr;
0e485150
FR		 2345 /*
2346 * The driver currently handles the 8168Bf and the 8168Be identically
2347 * but they can be identified more specifically through the test below
2348 * if needed:
2349 *
2350 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 2351 *
2352 * Same thing for the 8101Eb and the 8101Ec:
2353 *
2354 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 2355 */
3744100e 2356 static const struct rtl_mac_info {
1da177e4 2357 u32 mask;
e3cf0cc0 2358 u32 val;
1da177e4
LT		 2359 int mac_version;
2360 } mac_info[] = {
935e2218
CHL		 2361 /* 8168EP family. */
2362 { 0x7cf00000, 0x50200000, RTL_GIGA_MAC_VER_51 },
2363 { 0x7cf00000, 0x50100000, RTL_GIGA_MAC_VER_50 },
2364 { 0x7cf00000, 0x50000000, RTL_GIGA_MAC_VER_49 },
2365
6e1d0b89
CHL		 2366 /* 8168H family. */
2367 { 0x7cf00000, 0x54100000, RTL_GIGA_MAC_VER_46 },
2368 { 0x7cf00000, 0x54000000, RTL_GIGA_MAC_VER_45 },
2369
c558386b 2370 /* 8168G family. */
45dd95c4 2371 { 0x7cf00000, 0x5c800000, RTL_GIGA_MAC_VER_44 },
57538c4a 2372 { 0x7cf00000, 0x50900000, RTL_GIGA_MAC_VER_42 },
c558386b
HW		 2373 { 0x7cf00000, 0x4c100000, RTL_GIGA_MAC_VER_41 },
2374 { 0x7cf00000, 0x4c000000, RTL_GIGA_MAC_VER_40 },
2375
c2218925 2376 /* 8168F family. */
b3d7b2f2 2377 { 0x7c800000, 0x48800000, RTL_GIGA_MAC_VER_38 },
c2218925
HW		 2378 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
2379 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
2380
01dc7fec 2381 /* 8168E family. */
70090424 2382 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
01dc7fec 2383 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
2384 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
2385 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
2386
5b538df9 2387 /* 8168D family. */
daf9df6d 2388 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
2389 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
daf9df6d 2390 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
5b538df9 2391
e6de30d6 2392 /* 8168DP family. */
2393 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
2394 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
4804b3b3 2395 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
e6de30d6 2396
ef808d50 2397 /* 8168C family. */
17c99297 2398 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
ef3386f0 2399 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 2400 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 2401 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 2402 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
2403 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 2404 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
6fb07058 2405 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
ef808d50 2406 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 2407
2408 /* 8168B family. */
2409 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
2410 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
2411 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
2412 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
2413
2414 /* 8101 family. */
5598bfe5
HW		 2415 { 0x7cf00000, 0x44900000, RTL_GIGA_MAC_VER_39 },
2416 { 0x7c800000, 0x44800000, RTL_GIGA_MAC_VER_39 },
7e18dca1 2417 { 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37 },
36a0e6c2 2418 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
5a5e4443
HW		 2419 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
2420 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
2421 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2857ffb7
FR		 2422 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
2423 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
2424 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
2425 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
2426 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
2427 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 2428 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 2429 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 2430 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 2431 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
2432 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 2433 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
2434 /* FIXME: where did these entries come from ? -- FR */
2435 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
2436 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
2437
2438 /* 8110 family. */
2439 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
2440 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
2441 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
2442 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
2443 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
2444 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
2445
f21b75e9
JD		 2446 /* Catch-all */
2447 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
3744100e
FR		 2448 };
2449 const struct rtl_mac_info *p = mac_info;
1da177e4
LT		 2450 u32 reg;
2451
e3cf0cc0
FR		 2452 reg = RTL_R32(TxConfig);
2453 while ((reg & p->mask) != p->val)
1da177e4
LT		 2454 p++;
2455 tp->mac_version = p->mac_version;
5d320a20
FR		 2456
2457 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2458 netif_notice(tp, probe, dev,
2459 "unknown MAC, using family default\n");
2460 tp->mac_version = default_version;
58152cd4 2461 } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
2462 tp->mac_version = tp->mii.supports_gmii ?
2463 RTL_GIGA_MAC_VER_42 :
2464 RTL_GIGA_MAC_VER_43;
6e1d0b89
CHL		 2465 } else if (tp->mac_version == RTL_GIGA_MAC_VER_45) {
2466 tp->mac_version = tp->mii.supports_gmii ?
2467 RTL_GIGA_MAC_VER_45 :
2468 RTL_GIGA_MAC_VER_47;
2469 } else if (tp->mac_version == RTL_GIGA_MAC_VER_46) {
2470 tp->mac_version = tp->mii.supports_gmii ?
2471 RTL_GIGA_MAC_VER_46 :
2472 RTL_GIGA_MAC_VER_48;
5d320a20 2473 }
1da177e4
LT		 2474}
2475
2476static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2477{
bcf0bf90 2478 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 2479}
2480
867763c1
FR		 2481struct phy_reg {
2482 u16 reg;
2483 u16 val;
2484};
2485
4da19633 2486static void rtl_writephy_batch(struct rtl8169_private *tp,
2487 const struct phy_reg *regs, int len)
867763c1
FR		 2488{
2489 while (len-- > 0) {
4da19633 2490 rtl_writephy(tp, regs->reg, regs->val);
867763c1
FR		 2491 regs++;
2492 }
2493}
2494
bca03d5f 2495#define PHY_READ 0x00000000
2496#define PHY_DATA_OR 0x10000000
2497#define PHY_DATA_AND 0x20000000
2498#define PHY_BJMPN 0x30000000
eee3786f 2499#define PHY_MDIO_CHG 0x40000000
bca03d5f 2500#define PHY_CLEAR_READCOUNT 0x70000000
2501#define PHY_WRITE 0x80000000
2502#define PHY_READCOUNT_EQ_SKIP 0x90000000
2503#define PHY_COMP_EQ_SKIPN 0xa0000000
2504#define PHY_COMP_NEQ_SKIPN 0xb0000000
2505#define PHY_WRITE_PREVIOUS 0xc0000000
2506#define PHY_SKIPN 0xd0000000
2507#define PHY_DELAY_MS 0xe0000000
bca03d5f 2508
960aee6c
HW		 2509struct fw_info {
2510 u32 magic;
2511 char version[RTL_VER_SIZE];
2512 __le32 fw_start;
2513 __le32 fw_len;
2514 u8 chksum;
2515} __packed;
2516
1c361efb
FR		 2517#define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2518
2519static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
bca03d5f 2520{
b6ffd97f 2521 const struct firmware *fw = rtl_fw->fw;
960aee6c 2522 struct fw_info *fw_info = (struct fw_info *)fw->data;
1c361efb
FR		 2523 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2524 char *version = rtl_fw->version;
2525 bool rc = false;
2526
2527 if (fw->size < FW_OPCODE_SIZE)
2528 goto out;
960aee6c
HW		 2529
2530 if (!fw_info->magic) {
2531 size_t i, size, start;
2532 u8 checksum = 0;
2533
2534 if (fw->size < sizeof(*fw_info))
2535 goto out;
2536
2537 for (i = 0; i < fw->size; i++)
2538 checksum += fw->data[i];
2539 if (checksum != 0)
2540 goto out;
2541
2542 start = le32_to_cpu(fw_info->fw_start);
2543 if (start > fw->size)
2544 goto out;
2545
2546 size = le32_to_cpu(fw_info->fw_len);
2547 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2548 goto out;
2549
2550 memcpy(version, fw_info->version, RTL_VER_SIZE);
2551
2552 pa->code = (__le32 *)(fw->data + start);
2553 pa->size = size;
2554 } else {
1c361efb
FR		 2555 if (fw->size % FW_OPCODE_SIZE)
2556 goto out;
2557
2558 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2559
2560 pa->code = (__le32 *)fw->data;
2561 pa->size = fw->size / FW_OPCODE_SIZE;
2562 }
2563 version[RTL_VER_SIZE - 1] = 0;
2564
2565 rc = true;
2566out:
2567 return rc;
2568}
2569
fd112f2e
FR		 2570static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2571 struct rtl_fw_phy_action *pa)
1c361efb 2572{
fd112f2e 2573 bool rc = false;
1c361efb 2574 size_t index;
bca03d5f 2575
1c361efb
FR		 2576 for (index = 0; index < pa->size; index++) {
2577 u32 action = le32_to_cpu(pa->code[index]);
42b82dc1 2578 u32 regno = (action & 0x0fff0000) >> 16;
bca03d5f 2579
42b82dc1 2580 switch(action & 0xf0000000) {
2581 case PHY_READ:
2582 case PHY_DATA_OR:
2583 case PHY_DATA_AND:
eee3786f 2584 case PHY_MDIO_CHG:
42b82dc1 2585 case PHY_CLEAR_READCOUNT:
2586 case PHY_WRITE:
2587 case PHY_WRITE_PREVIOUS:
2588 case PHY_DELAY_MS:
2589 break;
2590
2591 case PHY_BJMPN:
2592 if (regno > index) {
fd112f2e 2593 netif_err(tp, ifup, tp->dev,
cecb5fd7 2594 "Out of range of firmware\n");
fd112f2e 2595 goto out;
42b82dc1 2596 }
2597 break;
2598 case PHY_READCOUNT_EQ_SKIP:
1c361efb 2599 if (index + 2 >= pa->size) {
fd112f2e 2600 netif_err(tp, ifup, tp->dev,
cecb5fd7 2601 "Out of range of firmware\n");
fd112f2e 2602 goto out;
42b82dc1 2603 }
2604 break;
2605 case PHY_COMP_EQ_SKIPN:
2606 case PHY_COMP_NEQ_SKIPN:
2607 case PHY_SKIPN:
1c361efb 2608 if (index + 1 + regno >= pa->size) {
fd112f2e 2609 netif_err(tp, ifup, tp->dev,
cecb5fd7 2610 "Out of range of firmware\n");
fd112f2e 2611 goto out;
42b82dc1 2612 }
bca03d5f 2613 break;
2614
42b82dc1 2615 default:
fd112f2e 2616 netif_err(tp, ifup, tp->dev,
42b82dc1 2617 "Invalid action 0x%08x\n", action);
fd112f2e 2618 goto out;
bca03d5f 2619 }
2620 }
fd112f2e
FR		 2621 rc = true;
2622out:
2623 return rc;
2624}
bca03d5f 2625
fd112f2e
FR		 2626static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2627{
2628 struct net_device *dev = tp->dev;
2629 int rc = -EINVAL;
2630
2631 if (!rtl_fw_format_ok(tp, rtl_fw)) {
5c2d2b14 2632 netif_err(tp, ifup, dev, "invalid firmware\n");
fd112f2e
FR		 2633 goto out;
2634 }
2635
2636 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2637 rc = 0;
2638out:
2639 return rc;
2640}
2641
2642static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2643{
2644 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
eee3786f 2645 struct mdio_ops org, *ops = &tp->mdio_ops;
fd112f2e
FR		 2646 u32 predata, count;
2647 size_t index;
2648
2649 predata = count = 0;
eee3786f 2650 org.write = ops->write;
2651 org.read = ops->read;
42b82dc1 2652
1c361efb
FR		 2653 for (index = 0; index < pa->size; ) {
2654 u32 action = le32_to_cpu(pa->code[index]);
bca03d5f 2655 u32 data = action & 0x0000ffff;
42b82dc1 2656 u32 regno = (action & 0x0fff0000) >> 16;
2657
2658 if (!action)
2659 break;
bca03d5f 2660
2661 switch(action & 0xf0000000) {
42b82dc1 2662 case PHY_READ:
2663 predata = rtl_readphy(tp, regno);
2664 count++;
2665 index++;
2666 break;
2667 case PHY_DATA_OR:
2668 predata |= data;
2669 index++;
2670 break;
2671 case PHY_DATA_AND:
2672 predata &= data;
2673 index++;
2674 break;
2675 case PHY_BJMPN:
2676 index -= regno;
2677 break;
eee3786f 2678 case PHY_MDIO_CHG:
2679 if (data == 0) {
2680 ops->write = org.write;
2681 ops->read = org.read;
2682 } else if (data == 1) {
2683 ops->write = mac_mcu_write;
2684 ops->read = mac_mcu_read;
2685 }
2686
42b82dc1 2687 index++;
2688 break;
2689 case PHY_CLEAR_READCOUNT:
2690 count = 0;
2691 index++;
2692 break;
bca03d5f 2693 case PHY_WRITE:
42b82dc1 2694 rtl_writephy(tp, regno, data);
2695 index++;
2696 break;
2697 case PHY_READCOUNT_EQ_SKIP:
cecb5fd7 2698 index += (count == data) ? 2 : 1;
bca03d5f 2699 break;
42b82dc1 2700 case PHY_COMP_EQ_SKIPN:
2701 if (predata == data)
2702 index += regno;
2703 index++;
2704 break;
2705 case PHY_COMP_NEQ_SKIPN:
2706 if (predata != data)
2707 index += regno;
2708 index++;
2709 break;
2710 case PHY_WRITE_PREVIOUS:
2711 rtl_writephy(tp, regno, predata);
2712 index++;
2713 break;
2714 case PHY_SKIPN:
2715 index += regno + 1;
2716 break;
2717 case PHY_DELAY_MS:
2718 mdelay(data);
2719 index++;
2720 break;
2721
bca03d5f 2722 default:
2723 BUG();
2724 }
2725 }
eee3786f 2726
2727 ops->write = org.write;
2728 ops->read = org.read;
bca03d5f 2729}
2730
f1e02ed1 2731static void rtl_release_firmware(struct rtl8169_private *tp)
2732{
b6ffd97f
FR		 2733 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2734 release_firmware(tp->rtl_fw->fw);
2735 kfree(tp->rtl_fw);
2736 }
2737 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
f1e02ed1 2738}
2739
953a12cc 2740static void rtl_apply_firmware(struct rtl8169_private *tp)
f1e02ed1 2741{
b6ffd97f 2742 struct rtl_fw *rtl_fw = tp->rtl_fw;
f1e02ed1 2743
2744 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
eef63cc1 2745 if (!IS_ERR_OR_NULL(rtl_fw))
b6ffd97f 2746 rtl_phy_write_fw(tp, rtl_fw);
953a12cc
FR		 2747}
2748
2749static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2750{
2751 if (rtl_readphy(tp, reg) != val)
2752 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2753 else
2754 rtl_apply_firmware(tp);
f1e02ed1 2755}
2756
4da19633 2757static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1da177e4 2758{
350f7596 2759 static const struct phy_reg phy_reg_init[] = {
0b9b571d 2760 { 0x1f, 0x0001 },
2761 { 0x06, 0x006e },
2762 { 0x08, 0x0708 },
2763 { 0x15, 0x4000 },
2764 { 0x18, 0x65c7 },
1da177e4 2765
0b9b571d 2766 { 0x1f, 0x0001 },
2767 { 0x03, 0x00a1 },
2768 { 0x02, 0x0008 },
2769 { 0x01, 0x0120 },
2770 { 0x00, 0x1000 },
2771 { 0x04, 0x0800 },
2772 { 0x04, 0x0000 },
1da177e4 2773
0b9b571d 2774 { 0x03, 0xff41 },
2775 { 0x02, 0xdf60 },
2776 { 0x01, 0x0140 },
2777 { 0x00, 0x0077 },
2778 { 0x04, 0x7800 },
2779 { 0x04, 0x7000 },
2780
2781 { 0x03, 0x802f },
2782 { 0x02, 0x4f02 },
2783 { 0x01, 0x0409 },
2784 { 0x00, 0xf0f9 },
2785 { 0x04, 0x9800 },
2786 { 0x04, 0x9000 },
2787
2788 { 0x03, 0xdf01 },
2789 { 0x02, 0xdf20 },
2790 { 0x01, 0xff95 },
2791 { 0x00, 0xba00 },
2792 { 0x04, 0xa800 },
2793 { 0x04, 0xa000 },
2794
2795 { 0x03, 0xff41 },
2796 { 0x02, 0xdf20 },
2797 { 0x01, 0x0140 },
2798 { 0x00, 0x00bb },
2799 { 0x04, 0xb800 },
2800 { 0x04, 0xb000 },
2801
2802 { 0x03, 0xdf41 },
2803 { 0x02, 0xdc60 },
2804 { 0x01, 0x6340 },
2805 { 0x00, 0x007d },
2806 { 0x04, 0xd800 },
2807 { 0x04, 0xd000 },
2808
2809 { 0x03, 0xdf01 },
2810 { 0x02, 0xdf20 },
2811 { 0x01, 0x100a },
2812 { 0x00, 0xa0ff },
2813 { 0x04, 0xf800 },
2814 { 0x04, 0xf000 },
2815
2816 { 0x1f, 0x0000 },
2817 { 0x0b, 0x0000 },
2818 { 0x00, 0x9200 }
2819 };
1da177e4 2820
4da19633 2821 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1da177e4
LT		 2822}
2823
4da19633 2824static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
5615d9f1 2825{
350f7596 2826 static const struct phy_reg phy_reg_init[] = {
a441d7b6
FR		 2827 { 0x1f, 0x0002 },
2828 { 0x01, 0x90d0 },
2829 { 0x1f, 0x0000 }
2830 };
2831
4da19633 2832 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 2833}
2834
4da19633 2835static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2e955856 2836{
2837 struct pci_dev *pdev = tp->pci_dev;
2e955856 2838
ccbae55e
SS		 2839 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2840 (pdev->subsystem_device != 0xe000))
2e955856 2841 return;
2842
4da19633 2843 rtl_writephy(tp, 0x1f, 0x0001);
2844 rtl_writephy(tp, 0x10, 0xf01b);
2845 rtl_writephy(tp, 0x1f, 0x0000);
2e955856 2846}
2847
4da19633 2848static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2e955856 2849{
350f7596 2850 static const struct phy_reg phy_reg_init[] = {
2e955856 2851 { 0x1f, 0x0001 },
2852 { 0x04, 0x0000 },
2853 { 0x03, 0x00a1 },
2854 { 0x02, 0x0008 },
2855 { 0x01, 0x0120 },
2856 { 0x00, 0x1000 },
2857 { 0x04, 0x0800 },
2858 { 0x04, 0x9000 },
2859 { 0x03, 0x802f },
2860 { 0x02, 0x4f02 },
2861 { 0x01, 0x0409 },
2862 { 0x00, 0xf099 },
2863 { 0x04, 0x9800 },
2864 { 0x04, 0xa000 },
2865 { 0x03, 0xdf01 },
2866 { 0x02, 0xdf20 },
2867 { 0x01, 0xff95 },
2868 { 0x00, 0xba00 },
2869 { 0x04, 0xa800 },
2870 { 0x04, 0xf000 },
2871 { 0x03, 0xdf01 },
2872 { 0x02, 0xdf20 },
2873 { 0x01, 0x101a },
2874 { 0x00, 0xa0ff },
2875 { 0x04, 0xf800 },
2876 { 0x04, 0x0000 },
2877 { 0x1f, 0x0000 },
2878
2879 { 0x1f, 0x0001 },
2880 { 0x10, 0xf41b },
2881 { 0x14, 0xfb54 },
2882 { 0x18, 0xf5c7 },
2883 { 0x1f, 0x0000 },
2884
2885 { 0x1f, 0x0001 },
2886 { 0x17, 0x0cc0 },
2887 { 0x1f, 0x0000 }
2888 };
2889
4da19633 2890 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2e955856 2891
4da19633 2892 rtl8169scd_hw_phy_config_quirk(tp);
2e955856 2893}
2894
4da19633 2895static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
8c7006aa 2896{
350f7596 2897 static const struct phy_reg phy_reg_init[] = {
8c7006aa 2898 { 0x1f, 0x0001 },
2899 { 0x04, 0x0000 },
2900 { 0x03, 0x00a1 },
2901 { 0x02, 0x0008 },
2902 { 0x01, 0x0120 },
2903 { 0x00, 0x1000 },
2904 { 0x04, 0x0800 },
2905 { 0x04, 0x9000 },
2906 { 0x03, 0x802f },
2907 { 0x02, 0x4f02 },
2908 { 0x01, 0x0409 },
2909 { 0x00, 0xf099 },
2910 { 0x04, 0x9800 },
2911 { 0x04, 0xa000 },
2912 { 0x03, 0xdf01 },
2913 { 0x02, 0xdf20 },
2914 { 0x01, 0xff95 },
2915 { 0x00, 0xba00 },
2916 { 0x04, 0xa800 },
2917 { 0x04, 0xf000 },
2918 { 0x03, 0xdf01 },
2919 { 0x02, 0xdf20 },
2920 { 0x01, 0x101a },
2921 { 0x00, 0xa0ff },
2922 { 0x04, 0xf800 },
2923 { 0x04, 0x0000 },
2924 { 0x1f, 0x0000 },
2925
2926 { 0x1f, 0x0001 },
2927 { 0x0b, 0x8480 },
2928 { 0x1f, 0x0000 },
2929
2930 { 0x1f, 0x0001 },
2931 { 0x18, 0x67c7 },
2932 { 0x04, 0x2000 },
2933 { 0x03, 0x002f },
2934 { 0x02, 0x4360 },
2935 { 0x01, 0x0109 },
2936 { 0x00, 0x3022 },
2937 { 0x04, 0x2800 },
2938 { 0x1f, 0x0000 },
2939
2940 { 0x1f, 0x0001 },
2941 { 0x17, 0x0cc0 },
2942 { 0x1f, 0x0000 }
2943 };
2944
4da19633 2945 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
8c7006aa 2946}
2947
4da19633 2948static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
236b8082 2949{
350f7596 2950 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2951 { 0x10, 0xf41b },
2952 { 0x1f, 0x0000 }
2953 };
2954
4da19633 2955 rtl_writephy(tp, 0x1f, 0x0001);
2956 rtl_patchphy(tp, 0x16, 1 << 0);
236b8082 2957
4da19633 2958 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2959}
2960
4da19633 2961static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
236b8082 2962{
350f7596 2963 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2964 { 0x1f, 0x0001 },
2965 { 0x10, 0xf41b },
2966 { 0x1f, 0x0000 }
2967 };
2968
4da19633 2969 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2970}
2971
4da19633 2972static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2973{
350f7596 2974 static const struct phy_reg phy_reg_init[] = {
867763c1
FR		 2975 { 0x1f, 0x0000 },
2976 { 0x1d, 0x0f00 },
2977 { 0x1f, 0x0002 },
2978 { 0x0c, 0x1ec8 },
2979 { 0x1f, 0x0000 }
2980 };
2981
4da19633 2982 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
867763c1
FR		 2983}
2984
4da19633 2985static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
ef3386f0 2986{
350f7596 2987 static const struct phy_reg phy_reg_init[] = {
ef3386f0
FR		 2988 { 0x1f, 0x0001 },
2989 { 0x1d, 0x3d98 },
2990 { 0x1f, 0x0000 }
2991 };
2992
4da19633 2993 rtl_writephy(tp, 0x1f, 0x0000);
2994 rtl_patchphy(tp, 0x14, 1 << 5);
2995 rtl_patchphy(tp, 0x0d, 1 << 5);
ef3386f0 2996
4da19633 2997 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
ef3386f0
FR		 2998}
2999
4da19633 3000static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 3001{
350f7596 3002 static const struct phy_reg phy_reg_init[] = {
a3f80671
FR		 3003 { 0x1f, 0x0001 },
3004 { 0x12, 0x2300 },
867763c1
FR		 3005 { 0x1f, 0x0002 },
3006 { 0x00, 0x88d4 },
3007 { 0x01, 0x82b1 },
3008 { 0x03, 0x7002 },
3009 { 0x08, 0x9e30 },
3010 { 0x09, 0x01f0 },
3011 { 0x0a, 0x5500 },
3012 { 0x0c, 0x00c8 },
3013 { 0x1f, 0x0003 },
3014 { 0x12, 0xc096 },
3015 { 0x16, 0x000a },
f50d4275
FR		 3016 { 0x1f, 0x0000 },
3017 { 0x1f, 0x0000 },
3018 { 0x09, 0x2000 },
3019 { 0x09, 0x0000 }
867763c1
FR		 3020 };
3021
4da19633 3022 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 3023
4da19633 3024 rtl_patchphy(tp, 0x14, 1 << 5);
3025 rtl_patchphy(tp, 0x0d, 1 << 5);
3026 rtl_writephy(tp, 0x1f, 0x0000);
867763c1
FR		 3027}
3028
4da19633 3029static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
7da97ec9 3030{
350f7596 3031 static const struct phy_reg phy_reg_init[] = {
f50d4275 3032 { 0x1f, 0x0001 },
7da97ec9 3033 { 0x12, 0x2300 },
f50d4275
FR		 3034 { 0x03, 0x802f },
3035 { 0x02, 0x4f02 },
3036 { 0x01, 0x0409 },
3037 { 0x00, 0xf099 },
3038 { 0x04, 0x9800 },
3039 { 0x04, 0x9000 },
3040 { 0x1d, 0x3d98 },
7da97ec9
FR		 3041 { 0x1f, 0x0002 },
3042 { 0x0c, 0x7eb8 },
f50d4275
FR		 3043 { 0x06, 0x0761 },
3044 { 0x1f, 0x0003 },
3045 { 0x16, 0x0f0a },
7da97ec9
FR		 3046 { 0x1f, 0x0000 }
3047 };
3048
4da19633 3049 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 3050
4da19633 3051 rtl_patchphy(tp, 0x16, 1 << 0);
3052 rtl_patchphy(tp, 0x14, 1 << 5);
3053 rtl_patchphy(tp, 0x0d, 1 << 5);
3054 rtl_writephy(tp, 0x1f, 0x0000);
7da97ec9
FR		 3055}
3056
4da19633 3057static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
197ff761 3058{
350f7596 3059 static const struct phy_reg phy_reg_init[] = {
197ff761
FR		 3060 { 0x1f, 0x0001 },
3061 { 0x12, 0x2300 },
3062 { 0x1d, 0x3d98 },
3063 { 0x1f, 0x0002 },
3064 { 0x0c, 0x7eb8 },
3065 { 0x06, 0x5461 },
3066 { 0x1f, 0x0003 },
3067 { 0x16, 0x0f0a },
3068 { 0x1f, 0x0000 }
3069 };
3070
4da19633 3071 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
197ff761 3072
4da19633 3073 rtl_patchphy(tp, 0x16, 1 << 0);
3074 rtl_patchphy(tp, 0x14, 1 << 5);
3075 rtl_patchphy(tp, 0x0d, 1 << 5);
3076 rtl_writephy(tp, 0x1f, 0x0000);
197ff761
FR		 3077}
3078
4da19633 3079static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
6fb07058 3080{
4da19633 3081 rtl8168c_3_hw_phy_config(tp);
6fb07058
FR		 3082}
3083
bca03d5f 3084static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
5b538df9 3085{
350f7596 3086 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 3087 /* Channel Estimation */
5b538df9 3088 { 0x1f, 0x0001 },
daf9df6d 3089 { 0x06, 0x4064 },
3090 { 0x07, 0x2863 },
3091 { 0x08, 0x059c },
3092 { 0x09, 0x26b4 },
3093 { 0x0a, 0x6a19 },
3094 { 0x0b, 0xdcc8 },
3095 { 0x10, 0xf06d },
3096 { 0x14, 0x7f68 },
3097 { 0x18, 0x7fd9 },
3098 { 0x1c, 0xf0ff },
3099 { 0x1d, 0x3d9c },
5b538df9 3100 { 0x1f, 0x0003 },
daf9df6d 3101 { 0x12, 0xf49f },
3102 { 0x13, 0x070b },
3103 { 0x1a, 0x05ad },
bca03d5f 3104 { 0x14, 0x94c0 },
3105
3106 /*
3107 * Tx Error Issue
cecb5fd7 3108 * Enhance line driver power
bca03d5f 3109 */
5b538df9 3110 { 0x1f, 0x0002 },
daf9df6d 3111 { 0x06, 0x5561 },
3112 { 0x1f, 0x0005 },
3113 { 0x05, 0x8332 },
bca03d5f 3114 { 0x06, 0x5561 },
3115
3116 /*
3117 * Can not link to 1Gbps with bad cable
3118 * Decrease SNR threshold form 21.07dB to 19.04dB
3119 */
3120 { 0x1f, 0x0001 },
3121 { 0x17, 0x0cc0 },
daf9df6d 3122
5b538df9 3123 { 0x1f, 0x0000 },
bca03d5f 3124 { 0x0d, 0xf880 }
daf9df6d 3125 };
3126
4da19633 3127 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
daf9df6d 3128
bca03d5f 3129 /*
3130 * Rx Error Issue
3131 * Fine Tune Switching regulator parameter
3132 */
4da19633 3133 rtl_writephy(tp, 0x1f, 0x0002);
76564428
CHL		 3134 rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
3135 rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
daf9df6d 3136
fdf6fc06 3137 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
350f7596 3138 static const struct phy_reg phy_reg_init[] = {
daf9df6d 3139 { 0x1f, 0x0002 },
3140 { 0x05, 0x669a },
3141 { 0x1f, 0x0005 },
3142 { 0x05, 0x8330 },
3143 { 0x06, 0x669a },
3144 { 0x1f, 0x0002 }
3145 };
3146 int val;
3147
4da19633 3148 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 3149
4da19633 3150 val = rtl_readphy(tp, 0x0d);
daf9df6d 3151
3152 if ((val & 0x00ff) != 0x006c) {
350f7596 3153 static const u32 set[] = {
daf9df6d 3154 0x0065, 0x0066, 0x0067, 0x0068,
3155 0x0069, 0x006a, 0x006b, 0x006c
3156 };
3157 int i;
3158
4da19633 3159 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 3160
3161 val &= 0xff00;
3162 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 3163 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 3164 }
3165 } else {
350f7596 3166 static const struct phy_reg phy_reg_init[] = {
daf9df6d 3167 { 0x1f, 0x0002 },
3168 { 0x05, 0x6662 },
3169 { 0x1f, 0x0005 },
3170 { 0x05, 0x8330 },
3171 { 0x06, 0x6662 }
3172 };
3173
4da19633 3174 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 3175 }
3176
bca03d5f 3177 /* RSET couple improve */
4da19633 3178 rtl_writephy(tp, 0x1f, 0x0002);
3179 rtl_patchphy(tp, 0x0d, 0x0300);
3180 rtl_patchphy(tp, 0x0f, 0x0010);
daf9df6d 3181
bca03d5f 3182 /* Fine tune PLL performance */
4da19633 3183 rtl_writephy(tp, 0x1f, 0x0002);
76564428
CHL		 3184 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3185 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 3186
4da19633 3187 rtl_writephy(tp, 0x1f, 0x0005);
3188 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 3189
3190 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
bca03d5f 3191
4da19633 3192 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 3193}
3194
bca03d5f 3195static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 3196{
350f7596 3197 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 3198 /* Channel Estimation */
daf9df6d 3199 { 0x1f, 0x0001 },
3200 { 0x06, 0x4064 },
3201 { 0x07, 0x2863 },
3202 { 0x08, 0x059c },
3203 { 0x09, 0x26b4 },
3204 { 0x0a, 0x6a19 },
3205 { 0x0b, 0xdcc8 },
3206 { 0x10, 0xf06d },
3207 { 0x14, 0x7f68 },
3208 { 0x18, 0x7fd9 },
3209 { 0x1c, 0xf0ff },
3210 { 0x1d, 0x3d9c },
3211 { 0x1f, 0x0003 },
3212 { 0x12, 0xf49f },
3213 { 0x13, 0x070b },
3214 { 0x1a, 0x05ad },
3215 { 0x14, 0x94c0 },
3216
bca03d5f 3217 /*
3218 * Tx Error Issue
cecb5fd7 3219 * Enhance line driver power
bca03d5f 3220 */
daf9df6d 3221 { 0x1f, 0x0002 },
3222 { 0x06, 0x5561 },
3223 { 0x1f, 0x0005 },
3224 { 0x05, 0x8332 },
bca03d5f 3225 { 0x06, 0x5561 },
3226
3227 /*
3228 * Can not link to 1Gbps with bad cable
3229 * Decrease SNR threshold form 21.07dB to 19.04dB
3230 */
3231 { 0x1f, 0x0001 },
3232 { 0x17, 0x0cc0 },
daf9df6d 3233
3234 { 0x1f, 0x0000 },
bca03d5f 3235 { 0x0d, 0xf880 }
5b538df9
FR		 3236 };
3237
4da19633 3238 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
5b538df9 3239
fdf6fc06 3240 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
350f7596 3241 static const struct phy_reg phy_reg_init[] = {
daf9df6d 3242 { 0x1f, 0x0002 },
3243 { 0x05, 0x669a },
5b538df9 3244 { 0x1f, 0x0005 },
daf9df6d 3245 { 0x05, 0x8330 },
3246 { 0x06, 0x669a },
3247
3248 { 0x1f, 0x0002 }
3249 };
3250 int val;
3251
4da19633 3252 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 3253
4da19633 3254 val = rtl_readphy(tp, 0x0d);
daf9df6d 3255 if ((val & 0x00ff) != 0x006c) {
b6bc7650 3256 static const u32 set[] = {
daf9df6d 3257 0x0065, 0x0066, 0x0067, 0x0068,
3258 0x0069, 0x006a, 0x006b, 0x006c
3259 };
3260 int i;
3261
4da19633 3262 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 3263
3264 val &= 0xff00;
3265 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 3266 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 3267 }
3268 } else {
350f7596 3269 static const struct phy_reg phy_reg_init[] = {
daf9df6d 3270 { 0x1f, 0x0002 },
3271 { 0x05, 0x2642 },
5b538df9 3272 { 0x1f, 0x0005 },
daf9df6d 3273 { 0x05, 0x8330 },
3274 { 0x06, 0x2642 }
5b538df9
FR		 3275 };
3276
4da19633 3277 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 3278 }
3279
bca03d5f 3280 /* Fine tune PLL performance */
4da19633 3281 rtl_writephy(tp, 0x1f, 0x0002);
76564428
CHL		 3282 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3283 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 3284
bca03d5f 3285 /* Switching regulator Slew rate */
4da19633 3286 rtl_writephy(tp, 0x1f, 0x0002);
3287 rtl_patchphy(tp, 0x0f, 0x0017);
daf9df6d 3288
4da19633 3289 rtl_writephy(tp, 0x1f, 0x0005);
3290 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 3291
3292 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
bca03d5f 3293
4da19633 3294 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 3295}
3296
4da19633 3297static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 3298{
350f7596 3299 static const struct phy_reg phy_reg_init[] = {
daf9df6d 3300 { 0x1f, 0x0002 },
3301 { 0x10, 0x0008 },
3302 { 0x0d, 0x006c },
3303
3304 { 0x1f, 0x0000 },
3305 { 0x0d, 0xf880 },
3306
3307 { 0x1f, 0x0001 },
3308 { 0x17, 0x0cc0 },
3309
3310 { 0x1f, 0x0001 },
3311 { 0x0b, 0xa4d8 },
3312 { 0x09, 0x281c },
3313 { 0x07, 0x2883 },
3314 { 0x0a, 0x6b35 },
3315 { 0x1d, 0x3da4 },
3316 { 0x1c, 0xeffd },
3317 { 0x14, 0x7f52 },
3318 { 0x18, 0x7fc6 },
3319 { 0x08, 0x0601 },
3320 { 0x06, 0x4063 },
3321 { 0x10, 0xf074 },
3322 { 0x1f, 0x0003 },
3323 { 0x13, 0x0789 },
3324 { 0x12, 0xf4bd },
3325 { 0x1a, 0x04fd },
3326 { 0x14, 0x84b0 },
3327 { 0x1f, 0x0000 },
3328 { 0x00, 0x9200 },
3329
3330 { 0x1f, 0x0005 },
3331 { 0x01, 0x0340 },
3332 { 0x1f, 0x0001 },
3333 { 0x04, 0x4000 },
3334 { 0x03, 0x1d21 },
3335 { 0x02, 0x0c32 },
3336 { 0x01, 0x0200 },
3337 { 0x00, 0x5554 },
3338 { 0x04, 0x4800 },
3339 { 0x04, 0x4000 },
3340 { 0x04, 0xf000 },
3341 { 0x03, 0xdf01 },
3342 { 0x02, 0xdf20 },
3343 { 0x01, 0x101a },
3344 { 0x00, 0xa0ff },
3345 { 0x04, 0xf800 },
3346 { 0x04, 0xf000 },
3347 { 0x1f, 0x0000 },
3348
3349 { 0x1f, 0x0007 },
3350 { 0x1e, 0x0023 },
3351 { 0x16, 0x0000 },
3352 { 0x1f, 0x0000 }
3353 };
3354
4da19633 3355 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 3356}
3357
e6de30d6 3358static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3359{
3360 static const struct phy_reg phy_reg_init[] = {
3361 { 0x1f, 0x0001 },
3362 { 0x17, 0x0cc0 },
3363
3364 { 0x1f, 0x0007 },
3365 { 0x1e, 0x002d },
3366 { 0x18, 0x0040 },
3367 { 0x1f, 0x0000 }
3368 };
3369
3370 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3371 rtl_patchphy(tp, 0x0d, 1 << 5);
3372}
3373
70090424 3374static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
01dc7fec 3375{
3376 static const struct phy_reg phy_reg_init[] = {
3377 /* Enable Delay cap */
3378 { 0x1f, 0x0005 },
3379 { 0x05, 0x8b80 },
3380 { 0x06, 0xc896 },
3381 { 0x1f, 0x0000 },
3382
3383 /* Channel estimation fine tune */
3384 { 0x1f, 0x0001 },
3385 { 0x0b, 0x6c20 },
3386 { 0x07, 0x2872 },
3387 { 0x1c, 0xefff },
3388 { 0x1f, 0x0003 },
3389 { 0x14, 0x6420 },
3390 { 0x1f, 0x0000 },
3391
3392 /* Update PFM & 10M TX idle timer */
3393 { 0x1f, 0x0007 },
3394 { 0x1e, 0x002f },
3395 { 0x15, 0x1919 },
3396 { 0x1f, 0x0000 },
3397
3398 { 0x1f, 0x0007 },
3399 { 0x1e, 0x00ac },
3400 { 0x18, 0x0006 },
3401 { 0x1f, 0x0000 }
3402 };
3403
15ecd039
FR		 3404 rtl_apply_firmware(tp);
3405
01dc7fec 3406 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3407
3408 /* DCO enable for 10M IDLE Power */
3409 rtl_writephy(tp, 0x1f, 0x0007);
3410 rtl_writephy(tp, 0x1e, 0x0023);
76564428 3411 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
01dc7fec 3412 rtl_writephy(tp, 0x1f, 0x0000);
3413
3414 /* For impedance matching */
3415 rtl_writephy(tp, 0x1f, 0x0002);
76564428 3416 rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
cecb5fd7 3417 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3418
3419 /* PHY auto speed down */
3420 rtl_writephy(tp, 0x1f, 0x0007);
3421 rtl_writephy(tp, 0x1e, 0x002d);
76564428 3422 rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
01dc7fec 3423 rtl_writephy(tp, 0x1f, 0x0000);
76564428 3424 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
01dc7fec 3425
3426 rtl_writephy(tp, 0x1f, 0x0005);
3427 rtl_writephy(tp, 0x05, 0x8b86);
76564428 3428 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
01dc7fec 3429 rtl_writephy(tp, 0x1f, 0x0000);
3430
3431 rtl_writephy(tp, 0x1f, 0x0005);
3432 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3433 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
01dc7fec 3434 rtl_writephy(tp, 0x1f, 0x0007);
3435 rtl_writephy(tp, 0x1e, 0x0020);
76564428 3436 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
01dc7fec 3437 rtl_writephy(tp, 0x1f, 0x0006);
3438 rtl_writephy(tp, 0x00, 0x5a00);
3439 rtl_writephy(tp, 0x1f, 0x0000);
3440 rtl_writephy(tp, 0x0d, 0x0007);
3441 rtl_writephy(tp, 0x0e, 0x003c);
3442 rtl_writephy(tp, 0x0d, 0x4007);
3443 rtl_writephy(tp, 0x0e, 0x0000);
3444 rtl_writephy(tp, 0x0d, 0x0000);
3445}
3446
9ecb9aab 3447static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3448{
3449 const u16 w[] = {
3450 addr[0] | (addr[1] << 8),
3451 addr[2] | (addr[3] << 8),
3452 addr[4] | (addr[5] << 8)
3453 };
3454 const struct exgmac_reg e[] = {
3455 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3456 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3457 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3458 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3459 };
3460
3461 rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3462}
3463
70090424
HW		 3464static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3465{
3466 static const struct phy_reg phy_reg_init[] = {
3467 /* Enable Delay cap */
3468 { 0x1f, 0x0004 },
3469 { 0x1f, 0x0007 },
3470 { 0x1e, 0x00ac },
3471 { 0x18, 0x0006 },
3472 { 0x1f, 0x0002 },
3473 { 0x1f, 0x0000 },
3474 { 0x1f, 0x0000 },
3475
3476 /* Channel estimation fine tune */
3477 { 0x1f, 0x0003 },
3478 { 0x09, 0xa20f },
3479 { 0x1f, 0x0000 },
3480 { 0x1f, 0x0000 },
3481
3482 /* Green Setting */
3483 { 0x1f, 0x0005 },
3484 { 0x05, 0x8b5b },
3485 { 0x06, 0x9222 },
3486 { 0x05, 0x8b6d },
3487 { 0x06, 0x8000 },
3488 { 0x05, 0x8b76 },
3489 { 0x06, 0x8000 },
3490 { 0x1f, 0x0000 }
3491 };
3492
3493 rtl_apply_firmware(tp);
3494
3495 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3496
3497 /* For 4-corner performance improve */
3498 rtl_writephy(tp, 0x1f, 0x0005);
3499 rtl_writephy(tp, 0x05, 0x8b80);
76564428 3500 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
70090424
HW		 3501 rtl_writephy(tp, 0x1f, 0x0000);
3502
3503 /* PHY auto speed down */
3504 rtl_writephy(tp, 0x1f, 0x0004);
3505 rtl_writephy(tp, 0x1f, 0x0007);
3506 rtl_writephy(tp, 0x1e, 0x002d);
76564428 3507 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
70090424
HW		 3508 rtl_writephy(tp, 0x1f, 0x0002);
3509 rtl_writephy(tp, 0x1f, 0x0000);
76564428 3510 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
70090424
HW		 3511
3512 /* improve 10M EEE waveform */
3513 rtl_writephy(tp, 0x1f, 0x0005);
3514 rtl_writephy(tp, 0x05, 0x8b86);
76564428 3515 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
70090424
HW		 3516 rtl_writephy(tp, 0x1f, 0x0000);
3517
3518 /* Improve 2-pair detection performance */
3519 rtl_writephy(tp, 0x1f, 0x0005);
3520 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3521 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
70090424
HW		 3522 rtl_writephy(tp, 0x1f, 0x0000);
3523
3524 /* EEE setting */
706123d0 3525 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, ERIAR_EXGMAC);
70090424
HW		 3526 rtl_writephy(tp, 0x1f, 0x0005);
3527 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3528 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
70090424
HW		 3529 rtl_writephy(tp, 0x1f, 0x0004);
3530 rtl_writephy(tp, 0x1f, 0x0007);
3531 rtl_writephy(tp, 0x1e, 0x0020);
76564428 3532 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
70090424
HW		 3533 rtl_writephy(tp, 0x1f, 0x0002);
3534 rtl_writephy(tp, 0x1f, 0x0000);
3535 rtl_writephy(tp, 0x0d, 0x0007);
3536 rtl_writephy(tp, 0x0e, 0x003c);
3537 rtl_writephy(tp, 0x0d, 0x4007);
3538 rtl_writephy(tp, 0x0e, 0x0000);
3539 rtl_writephy(tp, 0x0d, 0x0000);
3540
3541 /* Green feature */
3542 rtl_writephy(tp, 0x1f, 0x0003);
76564428
CHL		 3543 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3544 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
70090424 3545 rtl_writephy(tp, 0x1f, 0x0000);
e0c07557 3546
9ecb9aab 3547 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3548 rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
70090424
HW		 3549}
3550
5f886e08
HW		 3551static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3552{
3553 /* For 4-corner performance improve */
3554 rtl_writephy(tp, 0x1f, 0x0005);
3555 rtl_writephy(tp, 0x05, 0x8b80);
76564428 3556 rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
5f886e08
HW		 3557 rtl_writephy(tp, 0x1f, 0x0000);
3558
3559 /* PHY auto speed down */
3560 rtl_writephy(tp, 0x1f, 0x0007);
3561 rtl_writephy(tp, 0x1e, 0x002d);
76564428 3562 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
5f886e08 3563 rtl_writephy(tp, 0x1f, 0x0000);
76564428 3564 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
5f886e08
HW		 3565
3566 /* Improve 10M EEE waveform */
3567 rtl_writephy(tp, 0x1f, 0x0005);
3568 rtl_writephy(tp, 0x05, 0x8b86);
76564428 3569 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
5f886e08
HW		 3570 rtl_writephy(tp, 0x1f, 0x0000);
3571}
3572
c2218925
HW		 3573static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3574{
3575 static const struct phy_reg phy_reg_init[] = {
3576 /* Channel estimation fine tune */
3577 { 0x1f, 0x0003 },
3578 { 0x09, 0xa20f },
3579 { 0x1f, 0x0000 },
3580
3581 /* Modify green table for giga & fnet */
3582 { 0x1f, 0x0005 },
3583 { 0x05, 0x8b55 },
3584 { 0x06, 0x0000 },
3585 { 0x05, 0x8b5e },
3586 { 0x06, 0x0000 },
3587 { 0x05, 0x8b67 },
3588 { 0x06, 0x0000 },
3589 { 0x05, 0x8b70 },
3590 { 0x06, 0x0000 },
3591 { 0x1f, 0x0000 },
3592 { 0x1f, 0x0007 },
3593 { 0x1e, 0x0078 },
3594 { 0x17, 0x0000 },
3595 { 0x19, 0x00fb },
3596 { 0x1f, 0x0000 },
3597
3598 /* Modify green table for 10M */
3599 { 0x1f, 0x0005 },
3600 { 0x05, 0x8b79 },
3601 { 0x06, 0xaa00 },
3602 { 0x1f, 0x0000 },
3603
3604 /* Disable hiimpedance detection (RTCT) */
3605 { 0x1f, 0x0003 },
3606 { 0x01, 0x328a },
3607 { 0x1f, 0x0000 }
3608 };
3609
3610 rtl_apply_firmware(tp);
3611
3612 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3613
5f886e08 3614 rtl8168f_hw_phy_config(tp);
c2218925
HW		 3615
3616 /* Improve 2-pair detection performance */
3617 rtl_writephy(tp, 0x1f, 0x0005);
3618 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3619 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
c2218925
HW		 3620 rtl_writephy(tp, 0x1f, 0x0000);
3621}
3622
3623static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3624{
3625 rtl_apply_firmware(tp);
3626
5f886e08 3627 rtl8168f_hw_phy_config(tp);
c2218925
HW		 3628}
3629
b3d7b2f2
HW		 3630static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3631{
b3d7b2f2
HW		 3632 static const struct phy_reg phy_reg_init[] = {
3633 /* Channel estimation fine tune */
3634 { 0x1f, 0x0003 },
3635 { 0x09, 0xa20f },
3636 { 0x1f, 0x0000 },
3637
3638 /* Modify green table for giga & fnet */
3639 { 0x1f, 0x0005 },
3640 { 0x05, 0x8b55 },
3641 { 0x06, 0x0000 },
3642 { 0x05, 0x8b5e },
3643 { 0x06, 0x0000 },
3644 { 0x05, 0x8b67 },
3645 { 0x06, 0x0000 },
3646 { 0x05, 0x8b70 },
3647 { 0x06, 0x0000 },
3648 { 0x1f, 0x0000 },
3649 { 0x1f, 0x0007 },
3650 { 0x1e, 0x0078 },
3651 { 0x17, 0x0000 },
3652 { 0x19, 0x00aa },
3653 { 0x1f, 0x0000 },
3654
3655 /* Modify green table for 10M */
3656 { 0x1f, 0x0005 },
3657 { 0x05, 0x8b79 },
3658 { 0x06, 0xaa00 },
3659 { 0x1f, 0x0000 },
3660
3661 /* Disable hiimpedance detection (RTCT) */
3662 { 0x1f, 0x0003 },
3663 { 0x01, 0x328a },
3664 { 0x1f, 0x0000 }
3665 };
3666
3667
3668 rtl_apply_firmware(tp);
3669
3670 rtl8168f_hw_phy_config(tp);
3671
3672 /* Improve 2-pair detection performance */
3673 rtl_writephy(tp, 0x1f, 0x0005);
3674 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3675 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
b3d7b2f2
HW		 3676 rtl_writephy(tp, 0x1f, 0x0000);
3677
3678 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3679
3680 /* Modify green table for giga */
3681 rtl_writephy(tp, 0x1f, 0x0005);
3682 rtl_writephy(tp, 0x05, 0x8b54);
76564428 3683 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
b3d7b2f2 3684 rtl_writephy(tp, 0x05, 0x8b5d);
76564428 3685 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
b3d7b2f2 3686 rtl_writephy(tp, 0x05, 0x8a7c);
76564428 3687 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2 3688 rtl_writephy(tp, 0x05, 0x8a7f);
76564428 3689 rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
b3d7b2f2 3690 rtl_writephy(tp, 0x05, 0x8a82);
76564428 3691 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2 3692 rtl_writephy(tp, 0x05, 0x8a85);
76564428 3693 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2 3694 rtl_writephy(tp, 0x05, 0x8a88);
76564428 3695 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2
HW		 3696 rtl_writephy(tp, 0x1f, 0x0000);
3697
3698 /* uc same-seed solution */
3699 rtl_writephy(tp, 0x1f, 0x0005);
3700 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3701 rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
b3d7b2f2
HW		 3702 rtl_writephy(tp, 0x1f, 0x0000);
3703
3704 /* eee setting */
706123d0 3705 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
b3d7b2f2
HW		 3706 rtl_writephy(tp, 0x1f, 0x0005);
3707 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3708 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
b3d7b2f2
HW		 3709 rtl_writephy(tp, 0x1f, 0x0004);
3710 rtl_writephy(tp, 0x1f, 0x0007);
3711 rtl_writephy(tp, 0x1e, 0x0020);
76564428 3712 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
b3d7b2f2
HW		 3713 rtl_writephy(tp, 0x1f, 0x0000);
3714 rtl_writephy(tp, 0x0d, 0x0007);
3715 rtl_writephy(tp, 0x0e, 0x003c);
3716 rtl_writephy(tp, 0x0d, 0x4007);
3717 rtl_writephy(tp, 0x0e, 0x0000);
3718 rtl_writephy(tp, 0x0d, 0x0000);
3719
3720 /* Green feature */
3721 rtl_writephy(tp, 0x1f, 0x0003);
76564428
CHL		 3722 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3723 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
b3d7b2f2
HW		 3724 rtl_writephy(tp, 0x1f, 0x0000);
3725}
3726
c558386b
HW		 3727static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3728{
c558386b
HW		 3729 rtl_apply_firmware(tp);
3730
41f44d13 3731 rtl_writephy(tp, 0x1f, 0x0a46);
3732 if (rtl_readphy(tp, 0x10) & 0x0100) {
3733 rtl_writephy(tp, 0x1f, 0x0bcc);
76564428 3734 rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
41f44d13 3735 } else {
3736 rtl_writephy(tp, 0x1f, 0x0bcc);
76564428 3737 rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
41f44d13 3738 }
c558386b 3739
41f44d13 3740 rtl_writephy(tp, 0x1f, 0x0a46);
3741 if (rtl_readphy(tp, 0x13) & 0x0100) {
3742 rtl_writephy(tp, 0x1f, 0x0c41);
76564428 3743 rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
41f44d13 3744 } else {
fe7524c0 3745 rtl_writephy(tp, 0x1f, 0x0c41);
76564428 3746 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
41f44d13 3747 }
c558386b 3748
41f44d13 3749 /* Enable PHY auto speed down */
3750 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 3751 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
c558386b 3752
fe7524c0 3753 rtl_writephy(tp, 0x1f, 0x0bcc);
76564428 3754 rtl_w0w1_phy(tp, 0x14, 0x0100, 0x0000);
fe7524c0 3755 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 3756 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
fe7524c0 3757 rtl_writephy(tp, 0x1f, 0x0a43);
3758 rtl_writephy(tp, 0x13, 0x8084);
76564428
CHL		 3759 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3760 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
fe7524c0 3761
41f44d13 3762 /* EEE auto-fallback function */
3763 rtl_writephy(tp, 0x1f, 0x0a4b);
76564428 3764 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
c558386b 3765
41f44d13 3766 /* Enable UC LPF tune function */
3767 rtl_writephy(tp, 0x1f, 0x0a43);
3768 rtl_writephy(tp, 0x13, 0x8012);
76564428 3769 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
41f44d13 3770
3771 rtl_writephy(tp, 0x1f, 0x0c42);
76564428 3772 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
41f44d13 3773
fe7524c0 3774 /* Improve SWR Efficiency */
3775 rtl_writephy(tp, 0x1f, 0x0bcd);
3776 rtl_writephy(tp, 0x14, 0x5065);
3777 rtl_writephy(tp, 0x14, 0xd065);
3778 rtl_writephy(tp, 0x1f, 0x0bc8);
3779 rtl_writephy(tp, 0x11, 0x5655);
3780 rtl_writephy(tp, 0x1f, 0x0bcd);
3781 rtl_writephy(tp, 0x14, 0x1065);
3782 rtl_writephy(tp, 0x14, 0x9065);
3783 rtl_writephy(tp, 0x14, 0x1065);
3784
1bac1072
DC		 3785 /* Check ALDPS bit, disable it if enabled */
3786 rtl_writephy(tp, 0x1f, 0x0a43);
3787 if (rtl_readphy(tp, 0x10) & 0x0004)
76564428 3788 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
1bac1072 3789
41f44d13 3790 rtl_writephy(tp, 0x1f, 0x0000);
c558386b
HW		 3791}
3792
57538c4a 3793static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3794{
3795 rtl_apply_firmware(tp);
3796}
3797
6e1d0b89
CHL		 3798static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3799{
3800 u16 dout_tapbin;
3801 u32 data;
3802
3803 rtl_apply_firmware(tp);
3804
3805 /* CHN EST parameters adjust - giga master */
3806 rtl_writephy(tp, 0x1f, 0x0a43);
3807 rtl_writephy(tp, 0x13, 0x809b);
76564428 3808 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
6e1d0b89 3809 rtl_writephy(tp, 0x13, 0x80a2);
76564428 3810 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
6e1d0b89 3811 rtl_writephy(tp, 0x13, 0x80a4);
76564428 3812 rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
6e1d0b89 3813 rtl_writephy(tp, 0x13, 0x809c);
76564428 3814 rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
6e1d0b89
CHL		 3815 rtl_writephy(tp, 0x1f, 0x0000);
3816
3817 /* CHN EST parameters adjust - giga slave */
3818 rtl_writephy(tp, 0x1f, 0x0a43);
3819 rtl_writephy(tp, 0x13, 0x80ad);
76564428 3820 rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
6e1d0b89 3821 rtl_writephy(tp, 0x13, 0x80b4);
76564428 3822 rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
6e1d0b89 3823 rtl_writephy(tp, 0x13, 0x80ac);
76564428 3824 rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
6e1d0b89
CHL		 3825 rtl_writephy(tp, 0x1f, 0x0000);
3826
3827 /* CHN EST parameters adjust - fnet */
3828 rtl_writephy(tp, 0x1f, 0x0a43);
3829 rtl_writephy(tp, 0x13, 0x808e);
76564428 3830 rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
6e1d0b89 3831 rtl_writephy(tp, 0x13, 0x8090);
76564428 3832 rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
6e1d0b89 3833 rtl_writephy(tp, 0x13, 0x8092);
76564428 3834 rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
6e1d0b89
CHL		 3835 rtl_writephy(tp, 0x1f, 0x0000);
3836
3837 /* enable R-tune & PGA-retune function */
3838 dout_tapbin = 0;
3839 rtl_writephy(tp, 0x1f, 0x0a46);
3840 data = rtl_readphy(tp, 0x13);
3841 data &= 3;
3842 data <<= 2;
3843 dout_tapbin |= data;
3844 data = rtl_readphy(tp, 0x12);
3845 data &= 0xc000;
3846 data >>= 14;
3847 dout_tapbin |= data;
3848 dout_tapbin = ~(dout_tapbin^0x08);
3849 dout_tapbin <<= 12;
3850 dout_tapbin &= 0xf000;
3851 rtl_writephy(tp, 0x1f, 0x0a43);
3852 rtl_writephy(tp, 0x13, 0x827a);
76564428 3853 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
6e1d0b89 3854 rtl_writephy(tp, 0x13, 0x827b);
76564428 3855 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
6e1d0b89 3856 rtl_writephy(tp, 0x13, 0x827c);
76564428 3857 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
6e1d0b89 3858 rtl_writephy(tp, 0x13, 0x827d);
76564428 3859 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
6e1d0b89
CHL		 3860
3861 rtl_writephy(tp, 0x1f, 0x0a43);
3862 rtl_writephy(tp, 0x13, 0x0811);
76564428 3863 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
6e1d0b89 3864 rtl_writephy(tp, 0x1f, 0x0a42);
76564428 3865 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
6e1d0b89
CHL		 3866 rtl_writephy(tp, 0x1f, 0x0000);
3867
3868 /* enable GPHY 10M */
3869 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 3870 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
6e1d0b89
CHL		 3871 rtl_writephy(tp, 0x1f, 0x0000);
3872
3873 /* SAR ADC performance */
3874 rtl_writephy(tp, 0x1f, 0x0bca);
76564428 3875 rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
6e1d0b89
CHL		 3876 rtl_writephy(tp, 0x1f, 0x0000);
3877
3878 rtl_writephy(tp, 0x1f, 0x0a43);
3879 rtl_writephy(tp, 0x13, 0x803f);
76564428 3880 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3881 rtl_writephy(tp, 0x13, 0x8047);
76564428 3882 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3883 rtl_writephy(tp, 0x13, 0x804f);
76564428 3884 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3885 rtl_writephy(tp, 0x13, 0x8057);
76564428 3886 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3887 rtl_writephy(tp, 0x13, 0x805f);
76564428 3888 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3889 rtl_writephy(tp, 0x13, 0x8067);
76564428 3890 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3891 rtl_writephy(tp, 0x13, 0x806f);
76564428 3892 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89
CHL		 3893 rtl_writephy(tp, 0x1f, 0x0000);
3894
3895 /* disable phy pfm mode */
3896 rtl_writephy(tp, 0x1f, 0x0a44);
c832c35f 3897 rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
6e1d0b89
CHL		 3898 rtl_writephy(tp, 0x1f, 0x0000);
3899
3900 /* Check ALDPS bit, disable it if enabled */
3901 rtl_writephy(tp, 0x1f, 0x0a43);
3902 if (rtl_readphy(tp, 0x10) & 0x0004)
76564428 3903 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
6e1d0b89
CHL		 3904
3905 rtl_writephy(tp, 0x1f, 0x0000);
3906}
3907
3908static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3909{
3910 u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3911 u16 rlen;
3912 u32 data;
3913
3914 rtl_apply_firmware(tp);
3915
3916 /* CHIN EST parameter update */
3917 rtl_writephy(tp, 0x1f, 0x0a43);
3918 rtl_writephy(tp, 0x13, 0x808a);
76564428 3919 rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
6e1d0b89
CHL		 3920 rtl_writephy(tp, 0x1f, 0x0000);
3921
3922 /* enable R-tune & PGA-retune function */
3923 rtl_writephy(tp, 0x1f, 0x0a43);
3924 rtl_writephy(tp, 0x13, 0x0811);
76564428 3925 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
6e1d0b89 3926 rtl_writephy(tp, 0x1f, 0x0a42);
76564428 3927 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
6e1d0b89
CHL		 3928 rtl_writephy(tp, 0x1f, 0x0000);
3929
3930 /* enable GPHY 10M */
3931 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 3932 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
6e1d0b89
CHL		 3933 rtl_writephy(tp, 0x1f, 0x0000);
3934
3935 r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3936 data = r8168_mac_ocp_read(tp, 0xdd02);
3937 ioffset_p3 = ((data & 0x80)>>7);
3938 ioffset_p3 <<= 3;
3939
3940 data = r8168_mac_ocp_read(tp, 0xdd00);
3941 ioffset_p3 |= ((data & (0xe000))>>13);
3942 ioffset_p2 = ((data & (0x1e00))>>9);
3943 ioffset_p1 = ((data & (0x01e0))>>5);
3944 ioffset_p0 = ((data & 0x0010)>>4);
3945 ioffset_p0 <<= 3;
3946 ioffset_p0 |= (data & (0x07));
3947 data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3948
05b9687b 3949 if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
e2e2788e 3950 (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
6e1d0b89
CHL		 3951 rtl_writephy(tp, 0x1f, 0x0bcf);
3952 rtl_writephy(tp, 0x16, data);
3953 rtl_writephy(tp, 0x1f, 0x0000);
3954 }
3955
3956 /* Modify rlen (TX LPF corner frequency) level */
3957 rtl_writephy(tp, 0x1f, 0x0bcd);
3958 data = rtl_readphy(tp, 0x16);
3959 data &= 0x000f;
3960 rlen = 0;
3961 if (data > 3)
3962 rlen = data - 3;
3963 data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3964 rtl_writephy(tp, 0x17, data);
3965 rtl_writephy(tp, 0x1f, 0x0bcd);
3966 rtl_writephy(tp, 0x1f, 0x0000);
3967
3968 /* disable phy pfm mode */
3969 rtl_writephy(tp, 0x1f, 0x0a44);
c832c35f 3970 rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
6e1d0b89
CHL		 3971 rtl_writephy(tp, 0x1f, 0x0000);
3972
3973 /* Check ALDPS bit, disable it if enabled */
3974 rtl_writephy(tp, 0x1f, 0x0a43);
3975 if (rtl_readphy(tp, 0x10) & 0x0004)
76564428 3976 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
6e1d0b89
CHL		 3977
3978 rtl_writephy(tp, 0x1f, 0x0000);
3979}
3980
935e2218
CHL		 3981static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
3982{
3983 /* Enable PHY auto speed down */
3984 rtl_writephy(tp, 0x1f, 0x0a44);
3985 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3986 rtl_writephy(tp, 0x1f, 0x0000);
3987
3988 /* patch 10M & ALDPS */
3989 rtl_writephy(tp, 0x1f, 0x0bcc);
3990 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
3991 rtl_writephy(tp, 0x1f, 0x0a44);
3992 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3993 rtl_writephy(tp, 0x1f, 0x0a43);
3994 rtl_writephy(tp, 0x13, 0x8084);
3995 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3996 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3997 rtl_writephy(tp, 0x1f, 0x0000);
3998
3999 /* Enable EEE auto-fallback function */
4000 rtl_writephy(tp, 0x1f, 0x0a4b);
4001 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
4002 rtl_writephy(tp, 0x1f, 0x0000);
4003
4004 /* Enable UC LPF tune function */
4005 rtl_writephy(tp, 0x1f, 0x0a43);
4006 rtl_writephy(tp, 0x13, 0x8012);
4007 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
4008 rtl_writephy(tp, 0x1f, 0x0000);
4009
4010 /* set rg_sel_sdm_rate */
4011 rtl_writephy(tp, 0x1f, 0x0c42);
4012 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
4013 rtl_writephy(tp, 0x1f, 0x0000);
4014
4015 /* Check ALDPS bit, disable it if enabled */
4016 rtl_writephy(tp, 0x1f, 0x0a43);
4017 if (rtl_readphy(tp, 0x10) & 0x0004)
4018 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4019
4020 rtl_writephy(tp, 0x1f, 0x0000);
4021}
4022
4023static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
4024{
4025 /* patch 10M & ALDPS */
4026 rtl_writephy(tp, 0x1f, 0x0bcc);
4027 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
4028 rtl_writephy(tp, 0x1f, 0x0a44);
4029 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
4030 rtl_writephy(tp, 0x1f, 0x0a43);
4031 rtl_writephy(tp, 0x13, 0x8084);
4032 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
4033 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
4034 rtl_writephy(tp, 0x1f, 0x0000);
4035
4036 /* Enable UC LPF tune function */
4037 rtl_writephy(tp, 0x1f, 0x0a43);
4038 rtl_writephy(tp, 0x13, 0x8012);
4039 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
4040 rtl_writephy(tp, 0x1f, 0x0000);
4041
4042 /* Set rg_sel_sdm_rate */
4043 rtl_writephy(tp, 0x1f, 0x0c42);
4044 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
4045 rtl_writephy(tp, 0x1f, 0x0000);
4046
4047 /* Channel estimation parameters */
4048 rtl_writephy(tp, 0x1f, 0x0a43);
4049 rtl_writephy(tp, 0x13, 0x80f3);
4050 rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
4051 rtl_writephy(tp, 0x13, 0x80f0);
4052 rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
4053 rtl_writephy(tp, 0x13, 0x80ef);
4054 rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
4055 rtl_writephy(tp, 0x13, 0x80f6);
4056 rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
4057 rtl_writephy(tp, 0x13, 0x80ec);
4058 rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
4059 rtl_writephy(tp, 0x13, 0x80ed);
4060 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
4061 rtl_writephy(tp, 0x13, 0x80f2);
4062 rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
4063 rtl_writephy(tp, 0x13, 0x80f4);
4064 rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
4065 rtl_writephy(tp, 0x1f, 0x0a43);
4066 rtl_writephy(tp, 0x13, 0x8110);
4067 rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
4068 rtl_writephy(tp, 0x13, 0x810f);
4069 rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
4070 rtl_writephy(tp, 0x13, 0x8111);
4071 rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
4072 rtl_writephy(tp, 0x13, 0x8113);
4073 rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
4074 rtl_writephy(tp, 0x13, 0x8115);
4075 rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
4076 rtl_writephy(tp, 0x13, 0x810e);
4077 rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
4078 rtl_writephy(tp, 0x13, 0x810c);
4079 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
4080 rtl_writephy(tp, 0x13, 0x810b);
4081 rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
4082 rtl_writephy(tp, 0x1f, 0x0a43);
4083 rtl_writephy(tp, 0x13, 0x80d1);
4084 rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
4085 rtl_writephy(tp, 0x13, 0x80cd);
4086 rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
4087 rtl_writephy(tp, 0x13, 0x80d3);
4088 rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
4089 rtl_writephy(tp, 0x13, 0x80d5);
4090 rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
4091 rtl_writephy(tp, 0x13, 0x80d7);
4092 rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
4093
4094 /* Force PWM-mode */
4095 rtl_writephy(tp, 0x1f, 0x0bcd);
4096 rtl_writephy(tp, 0x14, 0x5065);
4097 rtl_writephy(tp, 0x14, 0xd065);
4098 rtl_writephy(tp, 0x1f, 0x0bc8);
4099 rtl_writephy(tp, 0x12, 0x00ed);
4100 rtl_writephy(tp, 0x1f, 0x0bcd);
4101 rtl_writephy(tp, 0x14, 0x1065);
4102 rtl_writephy(tp, 0x14, 0x9065);
4103 rtl_writephy(tp, 0x14, 0x1065);
4104 rtl_writephy(tp, 0x1f, 0x0000);
4105
4106 /* Check ALDPS bit, disable it if enabled */
4107 rtl_writephy(tp, 0x1f, 0x0a43);
4108 if (rtl_readphy(tp, 0x10) & 0x0004)
4109 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4110
4111 rtl_writephy(tp, 0x1f, 0x0000);
4112}
4113
4da19633 4114static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2857ffb7 4115{
350f7596 4116 static const struct phy_reg phy_reg_init[] = {
2857ffb7
FR		 4117 { 0x1f, 0x0003 },
4118 { 0x08, 0x441d },
4119 { 0x01, 0x9100 },
4120 { 0x1f, 0x0000 }
4121 };
4122
4da19633 4123 rtl_writephy(tp, 0x1f, 0x0000);
4124 rtl_patchphy(tp, 0x11, 1 << 12);
4125 rtl_patchphy(tp, 0x19, 1 << 13);
4126 rtl_patchphy(tp, 0x10, 1 << 15);
2857ffb7 4127
4da19633 4128 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2857ffb7
FR		 4129}
4130
5a5e4443
HW		 4131static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
4132{
4133 static const struct phy_reg phy_reg_init[] = {
4134 { 0x1f, 0x0005 },
4135 { 0x1a, 0x0000 },
4136 { 0x1f, 0x0000 },
4137
4138 { 0x1f, 0x0004 },
4139 { 0x1c, 0x0000 },
4140 { 0x1f, 0x0000 },
4141
4142 { 0x1f, 0x0001 },
4143 { 0x15, 0x7701 },
4144 { 0x1f, 0x0000 }
4145 };
4146
4147 /* Disable ALDPS before ram code */
eef63cc1
FR		 4148 rtl_writephy(tp, 0x1f, 0x0000);
4149 rtl_writephy(tp, 0x18, 0x0310);
4150 msleep(100);
5a5e4443 4151
953a12cc 4152 rtl_apply_firmware(tp);
5a5e4443
HW		 4153
4154 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4155}
4156
7e18dca1
HW		 4157static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
4158{
7e18dca1 4159 /* Disable ALDPS before setting firmware */
eef63cc1
FR		 4160 rtl_writephy(tp, 0x1f, 0x0000);
4161 rtl_writephy(tp, 0x18, 0x0310);
4162 msleep(20);
7e18dca1
HW		 4163
4164 rtl_apply_firmware(tp);
4165
4166 /* EEE setting */
fdf6fc06 4167 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
7e18dca1
HW		 4168 rtl_writephy(tp, 0x1f, 0x0004);
4169 rtl_writephy(tp, 0x10, 0x401f);
4170 rtl_writephy(tp, 0x19, 0x7030);
4171 rtl_writephy(tp, 0x1f, 0x0000);
4172}
4173
5598bfe5
HW		 4174static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
4175{
5598bfe5
HW		 4176 static const struct phy_reg phy_reg_init[] = {
4177 { 0x1f, 0x0004 },
4178 { 0x10, 0xc07f },
4179 { 0x19, 0x7030 },
4180 { 0x1f, 0x0000 }
4181 };
4182
4183 /* Disable ALDPS before ram code */
eef63cc1
FR		 4184 rtl_writephy(tp, 0x1f, 0x0000);
4185 rtl_writephy(tp, 0x18, 0x0310);
4186 msleep(100);
5598bfe5
HW		 4187
4188 rtl_apply_firmware(tp);
4189
fdf6fc06 4190 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5598bfe5
HW		 4191 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4192
fdf6fc06 4193 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5598bfe5
HW		 4194}
4195
5615d9f1
FR		 4196static void rtl_hw_phy_config(struct net_device *dev)
4197{
4198 struct rtl8169_private *tp = netdev_priv(dev);
5615d9f1
FR		 4199
4200 rtl8169_print_mac_version(tp);
4201
4202 switch (tp->mac_version) {
4203 case RTL_GIGA_MAC_VER_01:
4204 break;
4205 case RTL_GIGA_MAC_VER_02:
4206 case RTL_GIGA_MAC_VER_03:
4da19633 4207 rtl8169s_hw_phy_config(tp);
5615d9f1
FR		 4208 break;
4209 case RTL_GIGA_MAC_VER_04:
4da19633 4210 rtl8169sb_hw_phy_config(tp);
5615d9f1 4211 break;
2e955856 4212 case RTL_GIGA_MAC_VER_05:
4da19633 4213 rtl8169scd_hw_phy_config(tp);
2e955856 4214 break;
8c7006aa 4215 case RTL_GIGA_MAC_VER_06:
4da19633 4216 rtl8169sce_hw_phy_config(tp);
8c7006aa 4217 break;
2857ffb7
FR		 4218 case RTL_GIGA_MAC_VER_07:
4219 case RTL_GIGA_MAC_VER_08:
4220 case RTL_GIGA_MAC_VER_09:
4da19633 4221 rtl8102e_hw_phy_config(tp);
2857ffb7 4222 break;
236b8082 4223 case RTL_GIGA_MAC_VER_11:
4da19633 4224 rtl8168bb_hw_phy_config(tp);
236b8082
FR		 4225 break;
4226 case RTL_GIGA_MAC_VER_12:
4da19633 4227 rtl8168bef_hw_phy_config(tp);
236b8082
FR		 4228 break;
4229 case RTL_GIGA_MAC_VER_17:
4da19633 4230 rtl8168bef_hw_phy_config(tp);
236b8082 4231 break;
867763c1 4232 case RTL_GIGA_MAC_VER_18:
4da19633 4233 rtl8168cp_1_hw_phy_config(tp);
867763c1
FR		 4234 break;
4235 case RTL_GIGA_MAC_VER_19:
4da19633 4236 rtl8168c_1_hw_phy_config(tp);
867763c1 4237 break;
7da97ec9 4238 case RTL_GIGA_MAC_VER_20:
4da19633 4239 rtl8168c_2_hw_phy_config(tp);
7da97ec9 4240 break;
197ff761 4241 case RTL_GIGA_MAC_VER_21:
4da19633 4242 rtl8168c_3_hw_phy_config(tp);
197ff761 4243 break;
6fb07058 4244 case RTL_GIGA_MAC_VER_22:
4da19633 4245 rtl8168c_4_hw_phy_config(tp);
6fb07058 4246 break;
ef3386f0 4247 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 4248 case RTL_GIGA_MAC_VER_24:
4da19633 4249 rtl8168cp_2_hw_phy_config(tp);
ef3386f0 4250 break;
5b538df9 4251 case RTL_GIGA_MAC_VER_25:
bca03d5f 4252 rtl8168d_1_hw_phy_config(tp);
daf9df6d 4253 break;
4254 case RTL_GIGA_MAC_VER_26:
bca03d5f 4255 rtl8168d_2_hw_phy_config(tp);
daf9df6d 4256 break;
4257 case RTL_GIGA_MAC_VER_27:
4da19633 4258 rtl8168d_3_hw_phy_config(tp);
5b538df9 4259 break;
e6de30d6 4260 case RTL_GIGA_MAC_VER_28:
4261 rtl8168d_4_hw_phy_config(tp);
4262 break;
5a5e4443
HW		 4263 case RTL_GIGA_MAC_VER_29:
4264 case RTL_GIGA_MAC_VER_30:
4265 rtl8105e_hw_phy_config(tp);
4266 break;
cecb5fd7
FR		 4267 case RTL_GIGA_MAC_VER_31:
4268 /* None. */
4269 break;
01dc7fec 4270 case RTL_GIGA_MAC_VER_32:
01dc7fec 4271 case RTL_GIGA_MAC_VER_33:
70090424
HW		 4272 rtl8168e_1_hw_phy_config(tp);
4273 break;
4274 case RTL_GIGA_MAC_VER_34:
4275 rtl8168e_2_hw_phy_config(tp);
01dc7fec 4276 break;
c2218925
HW		 4277 case RTL_GIGA_MAC_VER_35:
4278 rtl8168f_1_hw_phy_config(tp);
4279 break;
4280 case RTL_GIGA_MAC_VER_36:
4281 rtl8168f_2_hw_phy_config(tp);
4282 break;
ef3386f0 4283
7e18dca1
HW		 4284 case RTL_GIGA_MAC_VER_37:
4285 rtl8402_hw_phy_config(tp);
4286 break;
4287
b3d7b2f2
HW		 4288 case RTL_GIGA_MAC_VER_38:
4289 rtl8411_hw_phy_config(tp);
4290 break;
4291
5598bfe5
HW		 4292 case RTL_GIGA_MAC_VER_39:
4293 rtl8106e_hw_phy_config(tp);
4294 break;
4295
c558386b
HW		 4296 case RTL_GIGA_MAC_VER_40:
4297 rtl8168g_1_hw_phy_config(tp);
4298 break;
57538c4a 4299 case RTL_GIGA_MAC_VER_42:
58152cd4 4300 case RTL_GIGA_MAC_VER_43:
45dd95c4 4301 case RTL_GIGA_MAC_VER_44:
57538c4a 4302 rtl8168g_2_hw_phy_config(tp);
4303 break;
6e1d0b89
CHL		 4304 case RTL_GIGA_MAC_VER_45:
4305 case RTL_GIGA_MAC_VER_47:
4306 rtl8168h_1_hw_phy_config(tp);
4307 break;
4308 case RTL_GIGA_MAC_VER_46:
4309 case RTL_GIGA_MAC_VER_48:
4310 rtl8168h_2_hw_phy_config(tp);
4311 break;
c558386b 4312
935e2218
CHL		 4313 case RTL_GIGA_MAC_VER_49:
4314 rtl8168ep_1_hw_phy_config(tp);
4315 break;
4316 case RTL_GIGA_MAC_VER_50:
4317 case RTL_GIGA_MAC_VER_51:
4318 rtl8168ep_2_hw_phy_config(tp);
4319 break;
4320
c558386b 4321 case RTL_GIGA_MAC_VER_41:
5615d9f1
FR		 4322 default:
4323 break;
4324 }
4325}
4326
da78dbff 4327static void rtl_phy_work(struct rtl8169_private *tp)
1da177e4 4328{
1da177e4
LT		 4329 struct timer_list *timer = &tp->timer;
4330 void __iomem *ioaddr = tp->mmio_addr;
4331 unsigned long timeout = RTL8169_PHY_TIMEOUT;
4332
bcf0bf90 4333 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 4334
4da19633 4335 if (tp->phy_reset_pending(tp)) {
5b0384f4 4336 /*
1da177e4
LT		 4337 * A busy loop could burn quite a few cycles on nowadays CPU.
4338 * Let's delay the execution of the timer for a few ticks.
4339 */
4340 timeout = HZ/10;
4341 goto out_mod_timer;
4342 }
4343
4344 if (tp->link_ok(ioaddr))
da78dbff 4345 return;
1da177e4 4346
9bb8eeb5 4347 netif_dbg(tp, link, tp->dev, "PHY reset until link up\n");
1da177e4 4348
4da19633 4349 tp->phy_reset_enable(tp);
1da177e4
LT		 4350
4351out_mod_timer:
4352 mod_timer(timer, jiffies + timeout);
da78dbff
FR		 4353}
4354
4355static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
4356{
da78dbff
FR		 4357 if (!test_and_set_bit(flag, tp->wk.flags))
4358 schedule_work(&tp->wk.work);
da78dbff
FR		 4359}
4360
4361static void rtl8169_phy_timer(unsigned long __opaque)
4362{
4363 struct net_device *dev = (struct net_device *)__opaque;
4364 struct rtl8169_private *tp = netdev_priv(dev);
4365
98ddf986 4366 rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
1da177e4
LT		 4367}
4368
1da177e4
LT		 4369static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
4370 void __iomem *ioaddr)
4371{
4372 iounmap(ioaddr);
4373 pci_release_regions(pdev);
87aeec76 4374 pci_clear_mwi(pdev);
1da177e4
LT		 4375 pci_disable_device(pdev);
4376 free_netdev(dev);
4377}
4378
ffc46952
FR		 4379DECLARE_RTL_COND(rtl_phy_reset_cond)
4380{
4381 return tp->phy_reset_pending(tp);
4382}
4383
bf793295
FR		 4384static void rtl8169_phy_reset(struct net_device *dev,
4385 struct rtl8169_private *tp)
4386{
4da19633 4387 tp->phy_reset_enable(tp);
ffc46952 4388 rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100);
bf793295
FR		 4389}
4390
2544bfc0
FR		 4391static bool rtl_tbi_enabled(struct rtl8169_private *tp)
4392{
4393 void __iomem *ioaddr = tp->mmio_addr;
4394
4395 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
4396 (RTL_R8(PHYstatus) & TBI_Enable);
4397}
4398
4ff96fa6
FR		 4399static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
4400{
4401 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 4402
5615d9f1 4403 rtl_hw_phy_config(dev);
4ff96fa6 4404
77332894
MS		 4405 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
4406 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4407 RTL_W8(0x82, 0x01);
4408 }
4ff96fa6 4409
6dccd16b
FR		 4410 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
4411
4412 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
4413 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 4414
bcf0bf90 4415 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 4416 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4417 RTL_W8(0x82, 0x01);
4418 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4da19633 4419 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4ff96fa6
FR		 4420 }
4421
bf793295
FR		 4422 rtl8169_phy_reset(dev, tp);
4423
54405cde 4424 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
cecb5fd7
FR		 4425 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4426 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4427 (tp->mii.supports_gmii ?
4428 ADVERTISED_1000baseT_Half |
4429 ADVERTISED_1000baseT_Full : 0));
4ff96fa6 4430
2544bfc0 4431 if (rtl_tbi_enabled(tp))
bf82c189 4432 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4ff96fa6
FR		 4433}
4434
773d2021
FR		 4435static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4436{
4437 void __iomem *ioaddr = tp->mmio_addr;
773d2021 4438
da78dbff 4439 rtl_lock_work(tp);
773d2021
FR		 4440
4441 RTL_W8(Cfg9346, Cfg9346_Unlock);
908ba2bf 4442
9ecb9aab 4443 RTL_W32(MAC4, addr[4] | addr[5] << 8);
908ba2bf 4444 RTL_R32(MAC4);
4445
9ecb9aab 4446 RTL_W32(MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
908ba2bf 4447 RTL_R32(MAC0);
4448
9ecb9aab 4449 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4450 rtl_rar_exgmac_set(tp, addr);
c28aa385 4451
773d2021
FR		 4452 RTL_W8(Cfg9346, Cfg9346_Lock);
4453
da78dbff 4454 rtl_unlock_work(tp);
773d2021
FR		 4455}
4456
4457static int rtl_set_mac_address(struct net_device *dev, void *p)
4458{
4459 struct rtl8169_private *tp = netdev_priv(dev);
4460 struct sockaddr *addr = p;
4461
4462 if (!is_valid_ether_addr(addr->sa_data))
4463 return -EADDRNOTAVAIL;
4464
4465 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
4466
4467 rtl_rar_set(tp, dev->dev_addr);
4468
4469 return 0;
4470}
4471
5f787a1a
FR		 4472static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4473{
4474 struct rtl8169_private *tp = netdev_priv(dev);
4475 struct mii_ioctl_data *data = if_mii(ifr);
4476
8b4ab28d
FR		 4477 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
4478}
5f787a1a 4479
cecb5fd7
FR		 4480static int rtl_xmii_ioctl(struct rtl8169_private *tp,
4481 struct mii_ioctl_data *data, int cmd)
8b4ab28d 4482{
5f787a1a
FR		 4483 switch (cmd) {
4484 case SIOCGMIIPHY:
4485 data->phy_id = 32; /* Internal PHY */
4486 return 0;
4487
4488 case SIOCGMIIREG:
4da19633 4489 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
5f787a1a
FR		 4490 return 0;
4491
4492 case SIOCSMIIREG:
4da19633 4493 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
5f787a1a
FR		 4494 return 0;
4495 }
4496 return -EOPNOTSUPP;
4497}
4498
8b4ab28d
FR		 4499static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
4500{
4501 return -EOPNOTSUPP;
4502}
4503
fbac58fc
FR		 4504static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
4505{
4506 if (tp->features & RTL_FEATURE_MSI) {
4507 pci_disable_msi(pdev);
4508 tp->features &= ~RTL_FEATURE_MSI;
4509 }
4510}
4511
baf63293 4512static void rtl_init_mdio_ops(struct rtl8169_private *tp)
c0e45c1c 4513{
4514 struct mdio_ops *ops = &tp->mdio_ops;
4515
4516 switch (tp->mac_version) {
4517 case RTL_GIGA_MAC_VER_27:
4518 ops->write = r8168dp_1_mdio_write;
4519 ops->read = r8168dp_1_mdio_read;
4520 break;
e6de30d6 4521 case RTL_GIGA_MAC_VER_28:
4804b3b3 4522 case RTL_GIGA_MAC_VER_31:
e6de30d6 4523 ops->write = r8168dp_2_mdio_write;
4524 ops->read = r8168dp_2_mdio_read;
4525 break;
c558386b
HW		 4526 case RTL_GIGA_MAC_VER_40:
4527 case RTL_GIGA_MAC_VER_41:
57538c4a 4528 case RTL_GIGA_MAC_VER_42:
58152cd4 4529 case RTL_GIGA_MAC_VER_43:
45dd95c4 4530 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4531 case RTL_GIGA_MAC_VER_45:
4532 case RTL_GIGA_MAC_VER_46:
4533 case RTL_GIGA_MAC_VER_47:
4534 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 4535 case RTL_GIGA_MAC_VER_49:
4536 case RTL_GIGA_MAC_VER_50:
4537 case RTL_GIGA_MAC_VER_51:
c558386b
HW		 4538 ops->write = r8168g_mdio_write;
4539 ops->read = r8168g_mdio_read;
4540 break;
c0e45c1c 4541 default:
4542 ops->write = r8169_mdio_write;
4543 ops->read = r8169_mdio_read;
4544 break;
4545 }
4546}
4547
e2409d83 4548static void rtl_speed_down(struct rtl8169_private *tp)
4549{
4550 u32 adv;
4551 int lpa;
4552
4553 rtl_writephy(tp, 0x1f, 0x0000);
4554 lpa = rtl_readphy(tp, MII_LPA);
4555
4556 if (lpa & (LPA_10HALF | LPA_10FULL))
4557 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
4558 else if (lpa & (LPA_100HALF | LPA_100FULL))
4559 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4560 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4561 else
4562 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4563 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4564 (tp->mii.supports_gmii ?
4565 ADVERTISED_1000baseT_Half |
4566 ADVERTISED_1000baseT_Full : 0);
4567
4568 rtl8169_set_speed(tp->dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
4569 adv);
4570}
4571
649b3b8c 4572static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4573{
4574 void __iomem *ioaddr = tp->mmio_addr;
4575
4576 switch (tp->mac_version) {
b00e69de
CB		 4577 case RTL_GIGA_MAC_VER_25:
4578 case RTL_GIGA_MAC_VER_26:
649b3b8c 4579 case RTL_GIGA_MAC_VER_29:
4580 case RTL_GIGA_MAC_VER_30:
4581 case RTL_GIGA_MAC_VER_32:
4582 case RTL_GIGA_MAC_VER_33:
4583 case RTL_GIGA_MAC_VER_34:
7e18dca1 4584 case RTL_GIGA_MAC_VER_37:
b3d7b2f2 4585 case RTL_GIGA_MAC_VER_38:
5598bfe5 4586 case RTL_GIGA_MAC_VER_39:
c558386b
HW		 4587 case RTL_GIGA_MAC_VER_40:
4588 case RTL_GIGA_MAC_VER_41:
57538c4a 4589 case RTL_GIGA_MAC_VER_42:
58152cd4 4590 case RTL_GIGA_MAC_VER_43:
45dd95c4 4591 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4592 case RTL_GIGA_MAC_VER_45:
4593 case RTL_GIGA_MAC_VER_46:
4594 case RTL_GIGA_MAC_VER_47:
4595 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 4596 case RTL_GIGA_MAC_VER_49:
4597 case RTL_GIGA_MAC_VER_50:
4598 case RTL_GIGA_MAC_VER_51:
649b3b8c 4599 RTL_W32(RxConfig, RTL_R32(RxConfig) |
4600 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4601 break;
4602 default:
4603 break;
4604 }
4605}
4606
4607static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
4608{
4609 if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
4610 return false;
4611
e2409d83 4612 rtl_speed_down(tp);
649b3b8c 4613 rtl_wol_suspend_quirk(tp);
4614
4615 return true;
4616}
4617
065c27c1 4618static void r810x_phy_power_down(struct rtl8169_private *tp)
4619{
4620 rtl_writephy(tp, 0x1f, 0x0000);
4621 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4622}
4623
4624static void r810x_phy_power_up(struct rtl8169_private *tp)
4625{
4626 rtl_writephy(tp, 0x1f, 0x0000);
4627 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4628}
4629
4630static void r810x_pll_power_down(struct rtl8169_private *tp)
4631{
0004299a
HW		 4632 void __iomem *ioaddr = tp->mmio_addr;
4633
649b3b8c 4634 if (rtl_wol_pll_power_down(tp))
065c27c1 4635 return;
065c27c1 4636
4637 r810x_phy_power_down(tp);
0004299a
HW		 4638
4639 switch (tp->mac_version) {
4640 case RTL_GIGA_MAC_VER_07:
4641 case RTL_GIGA_MAC_VER_08:
4642 case RTL_GIGA_MAC_VER_09:
4643 case RTL_GIGA_MAC_VER_10:
4644 case RTL_GIGA_MAC_VER_13:
4645 case RTL_GIGA_MAC_VER_16:
4646 break;
4647 default:
4648 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4649 break;
4650 }
065c27c1 4651}
4652
4653static void r810x_pll_power_up(struct rtl8169_private *tp)
4654{
0004299a
HW		 4655 void __iomem *ioaddr = tp->mmio_addr;
4656
065c27c1 4657 r810x_phy_power_up(tp);
0004299a
HW		 4658
4659 switch (tp->mac_version) {
4660 case RTL_GIGA_MAC_VER_07:
4661 case RTL_GIGA_MAC_VER_08:
4662 case RTL_GIGA_MAC_VER_09:
4663 case RTL_GIGA_MAC_VER_10:
4664 case RTL_GIGA_MAC_VER_13:
4665 case RTL_GIGA_MAC_VER_16:
4666 break;
6e1d0b89
CHL		 4667 case RTL_GIGA_MAC_VER_47:
4668 case RTL_GIGA_MAC_VER_48:
05b9687b 4669 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
6e1d0b89 4670 break;
0004299a
HW		 4671 default:
4672 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4673 break;
4674 }
065c27c1 4675}
4676
4677static void r8168_phy_power_up(struct rtl8169_private *tp)
4678{
4679 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 4680 switch (tp->mac_version) {
4681 case RTL_GIGA_MAC_VER_11:
4682 case RTL_GIGA_MAC_VER_12:
4683 case RTL_GIGA_MAC_VER_17:
4684 case RTL_GIGA_MAC_VER_18:
4685 case RTL_GIGA_MAC_VER_19:
4686 case RTL_GIGA_MAC_VER_20:
4687 case RTL_GIGA_MAC_VER_21:
4688 case RTL_GIGA_MAC_VER_22:
4689 case RTL_GIGA_MAC_VER_23:
4690 case RTL_GIGA_MAC_VER_24:
4691 case RTL_GIGA_MAC_VER_25:
4692 case RTL_GIGA_MAC_VER_26:
4693 case RTL_GIGA_MAC_VER_27:
4694 case RTL_GIGA_MAC_VER_28:
4695 case RTL_GIGA_MAC_VER_31:
4696 rtl_writephy(tp, 0x0e, 0x0000);
4697 break;
4698 default:
4699 break;
4700 }
065c27c1 4701 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4702}
4703
4704static void r8168_phy_power_down(struct rtl8169_private *tp)
4705{
4706 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 4707 switch (tp->mac_version) {
4708 case RTL_GIGA_MAC_VER_32:
4709 case RTL_GIGA_MAC_VER_33:
beb330a4 4710 case RTL_GIGA_MAC_VER_40:
4711 case RTL_GIGA_MAC_VER_41:
01dc7fec 4712 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
4713 break;
4714
4715 case RTL_GIGA_MAC_VER_11:
4716 case RTL_GIGA_MAC_VER_12:
4717 case RTL_GIGA_MAC_VER_17:
4718 case RTL_GIGA_MAC_VER_18:
4719 case RTL_GIGA_MAC_VER_19:
4720 case RTL_GIGA_MAC_VER_20:
4721 case RTL_GIGA_MAC_VER_21:
4722 case RTL_GIGA_MAC_VER_22:
4723 case RTL_GIGA_MAC_VER_23:
4724 case RTL_GIGA_MAC_VER_24:
4725 case RTL_GIGA_MAC_VER_25:
4726 case RTL_GIGA_MAC_VER_26:
4727 case RTL_GIGA_MAC_VER_27:
4728 case RTL_GIGA_MAC_VER_28:
4729 case RTL_GIGA_MAC_VER_31:
4730 rtl_writephy(tp, 0x0e, 0x0200);
4731 default:
4732 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4733 break;
4734 }
065c27c1 4735}
4736
4737static void r8168_pll_power_down(struct rtl8169_private *tp)
4738{
4739 void __iomem *ioaddr = tp->mmio_addr;
4740
cecb5fd7
FR		 4741 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4742 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
935e2218
CHL		 4743 tp->mac_version == RTL_GIGA_MAC_VER_31 ||
4744 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
4745 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
4746 tp->mac_version == RTL_GIGA_MAC_VER_51) &&
2f8c040c 4747 r8168_check_dash(tp)) {
065c27c1 4748 return;
5d2e1957 4749 }
065c27c1 4750
cecb5fd7
FR		 4751 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
4752 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
065c27c1 4753 (RTL_R16(CPlusCmd) & ASF)) {
4754 return;
4755 }
4756
01dc7fec 4757 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4758 tp->mac_version == RTL_GIGA_MAC_VER_33)
fdf6fc06 4759 rtl_ephy_write(tp, 0x19, 0xff64);
01dc7fec 4760
649b3b8c 4761 if (rtl_wol_pll_power_down(tp))
065c27c1 4762 return;
065c27c1 4763
4764 r8168_phy_power_down(tp);
4765
4766 switch (tp->mac_version) {
4767 case RTL_GIGA_MAC_VER_25:
4768 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 4769 case RTL_GIGA_MAC_VER_27:
4770 case RTL_GIGA_MAC_VER_28:
4804b3b3 4771 case RTL_GIGA_MAC_VER_31:
01dc7fec 4772 case RTL_GIGA_MAC_VER_32:
4773 case RTL_GIGA_MAC_VER_33:
42fde737 4774 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4775 case RTL_GIGA_MAC_VER_45:
4776 case RTL_GIGA_MAC_VER_46:
935e2218
CHL		 4777 case RTL_GIGA_MAC_VER_50:
4778 case RTL_GIGA_MAC_VER_51:
065c27c1 4779 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4780 break;
beb330a4 4781 case RTL_GIGA_MAC_VER_40:
4782 case RTL_GIGA_MAC_VER_41:
935e2218 4783 case RTL_GIGA_MAC_VER_49:
706123d0 4784 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
beb330a4 4785 0xfc000000, ERIAR_EXGMAC);
b8e5e6ad 4786 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
beb330a4 4787 break;
065c27c1 4788 }
4789}
4790
4791static void r8168_pll_power_up(struct rtl8169_private *tp)
4792{
4793 void __iomem *ioaddr = tp->mmio_addr;
4794
065c27c1 4795 switch (tp->mac_version) {
4796 case RTL_GIGA_MAC_VER_25:
4797 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 4798 case RTL_GIGA_MAC_VER_27:
4799 case RTL_GIGA_MAC_VER_28:
4804b3b3 4800 case RTL_GIGA_MAC_VER_31:
01dc7fec 4801 case RTL_GIGA_MAC_VER_32:
4802 case RTL_GIGA_MAC_VER_33:
065c27c1 4803 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4804 break;
42fde737 4805 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4806 case RTL_GIGA_MAC_VER_45:
4807 case RTL_GIGA_MAC_VER_46:
935e2218
CHL		 4808 case RTL_GIGA_MAC_VER_50:
4809 case RTL_GIGA_MAC_VER_51:
05b9687b 4810 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
6e1d0b89 4811 break;
beb330a4 4812 case RTL_GIGA_MAC_VER_40:
4813 case RTL_GIGA_MAC_VER_41:
935e2218 4814 case RTL_GIGA_MAC_VER_49:
b8e5e6ad 4815 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
706123d0 4816 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
beb330a4 4817 0x00000000, ERIAR_EXGMAC);
4818 break;
065c27c1 4819 }
4820
4821 r8168_phy_power_up(tp);
4822}
4823
d58d46b5
FR		 4824static void rtl_generic_op(struct rtl8169_private *tp,
4825 void (*op)(struct rtl8169_private *))
065c27c1 4826{
4827 if (op)
4828 op(tp);
4829}
4830
4831static void rtl_pll_power_down(struct rtl8169_private *tp)
4832{
d58d46b5 4833 rtl_generic_op(tp, tp->pll_power_ops.down);
065c27c1 4834}
4835
4836static void rtl_pll_power_up(struct rtl8169_private *tp)
4837{
d58d46b5 4838 rtl_generic_op(tp, tp->pll_power_ops.up);
065c27c1 4839}
4840
baf63293 4841static void rtl_init_pll_power_ops(struct rtl8169_private *tp)
065c27c1 4842{
4843 struct pll_power_ops *ops = &tp->pll_power_ops;
4844
4845 switch (tp->mac_version) {
4846 case RTL_GIGA_MAC_VER_07:
4847 case RTL_GIGA_MAC_VER_08:
4848 case RTL_GIGA_MAC_VER_09:
4849 case RTL_GIGA_MAC_VER_10:
4850 case RTL_GIGA_MAC_VER_16:
5a5e4443
HW		 4851 case RTL_GIGA_MAC_VER_29:
4852 case RTL_GIGA_MAC_VER_30:
7e18dca1 4853 case RTL_GIGA_MAC_VER_37:
5598bfe5 4854 case RTL_GIGA_MAC_VER_39:
58152cd4 4855 case RTL_GIGA_MAC_VER_43:
6e1d0b89
CHL		 4856 case RTL_GIGA_MAC_VER_47:
4857 case RTL_GIGA_MAC_VER_48:
065c27c1 4858 ops->down = r810x_pll_power_down;
4859 ops->up = r810x_pll_power_up;
4860 break;
4861
4862 case RTL_GIGA_MAC_VER_11:
4863 case RTL_GIGA_MAC_VER_12:
4864 case RTL_GIGA_MAC_VER_17:
4865 case RTL_GIGA_MAC_VER_18:
4866 case RTL_GIGA_MAC_VER_19:
4867 case RTL_GIGA_MAC_VER_20:
4868 case RTL_GIGA_MAC_VER_21:
4869 case RTL_GIGA_MAC_VER_22:
4870 case RTL_GIGA_MAC_VER_23:
4871 case RTL_GIGA_MAC_VER_24:
4872 case RTL_GIGA_MAC_VER_25:
4873 case RTL_GIGA_MAC_VER_26:
4874 case RTL_GIGA_MAC_VER_27:
e6de30d6 4875 case RTL_GIGA_MAC_VER_28:
4804b3b3 4876 case RTL_GIGA_MAC_VER_31:
01dc7fec 4877 case RTL_GIGA_MAC_VER_32:
4878 case RTL_GIGA_MAC_VER_33:
70090424 4879 case RTL_GIGA_MAC_VER_34:
c2218925
HW		 4880 case RTL_GIGA_MAC_VER_35:
4881 case RTL_GIGA_MAC_VER_36:
b3d7b2f2 4882 case RTL_GIGA_MAC_VER_38:
c558386b
HW		 4883 case RTL_GIGA_MAC_VER_40:
4884 case RTL_GIGA_MAC_VER_41:
57538c4a 4885 case RTL_GIGA_MAC_VER_42:
45dd95c4 4886 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4887 case RTL_GIGA_MAC_VER_45:
4888 case RTL_GIGA_MAC_VER_46:
935e2218
CHL		 4889 case RTL_GIGA_MAC_VER_49:
4890 case RTL_GIGA_MAC_VER_50:
4891 case RTL_GIGA_MAC_VER_51:
065c27c1 4892 ops->down = r8168_pll_power_down;
4893 ops->up = r8168_pll_power_up;
4894 break;
4895
4896 default:
4897 ops->down = NULL;
4898 ops->up = NULL;
4899 break;
4900 }
4901}
4902
e542a226
HW		 4903static void rtl_init_rxcfg(struct rtl8169_private *tp)
4904{
4905 void __iomem *ioaddr = tp->mmio_addr;
4906
4907 switch (tp->mac_version) {
4908 case RTL_GIGA_MAC_VER_01:
4909 case RTL_GIGA_MAC_VER_02:
4910 case RTL_GIGA_MAC_VER_03:
4911 case RTL_GIGA_MAC_VER_04:
4912 case RTL_GIGA_MAC_VER_05:
4913 case RTL_GIGA_MAC_VER_06:
4914 case RTL_GIGA_MAC_VER_10:
4915 case RTL_GIGA_MAC_VER_11:
4916 case RTL_GIGA_MAC_VER_12:
4917 case RTL_GIGA_MAC_VER_13:
4918 case RTL_GIGA_MAC_VER_14:
4919 case RTL_GIGA_MAC_VER_15:
4920 case RTL_GIGA_MAC_VER_16:
4921 case RTL_GIGA_MAC_VER_17:
4922 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4923 break;
4924 case RTL_GIGA_MAC_VER_18:
4925 case RTL_GIGA_MAC_VER_19:
4926 case RTL_GIGA_MAC_VER_20:
4927 case RTL_GIGA_MAC_VER_21:
4928 case RTL_GIGA_MAC_VER_22:
4929 case RTL_GIGA_MAC_VER_23:
4930 case RTL_GIGA_MAC_VER_24:
eb2dc35d 4931 case RTL_GIGA_MAC_VER_34:
3ced8c95 4932 case RTL_GIGA_MAC_VER_35:
e542a226
HW		 4933 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4934 break;
beb330a4 4935 case RTL_GIGA_MAC_VER_40:
4936 case RTL_GIGA_MAC_VER_41:
57538c4a 4937 case RTL_GIGA_MAC_VER_42:
58152cd4 4938 case RTL_GIGA_MAC_VER_43:
45dd95c4 4939 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4940 case RTL_GIGA_MAC_VER_45:
4941 case RTL_GIGA_MAC_VER_46:
4942 case RTL_GIGA_MAC_VER_47:
4943 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 4944 case RTL_GIGA_MAC_VER_49:
4945 case RTL_GIGA_MAC_VER_50:
4946 case RTL_GIGA_MAC_VER_51:
7ebc4822 4947 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
beb330a4 4948 break;
e542a226
HW		 4949 default:
4950 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
4951 break;
4952 }
4953}
4954
92fc43b4
HW		 4955static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4956{
9fba0812 4957 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
92fc43b4
HW		 4958}
4959
d58d46b5
FR		 4960static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4961{
9c5028e9 4962 void __iomem *ioaddr = tp->mmio_addr;
4963
4964 RTL_W8(Cfg9346, Cfg9346_Unlock);
d58d46b5 4965 rtl_generic_op(tp, tp->jumbo_ops.enable);
9c5028e9 4966 RTL_W8(Cfg9346, Cfg9346_Lock);
d58d46b5
FR		 4967}
4968
4969static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4970{
9c5028e9 4971 void __iomem *ioaddr = tp->mmio_addr;
4972
4973 RTL_W8(Cfg9346, Cfg9346_Unlock);
d58d46b5 4974 rtl_generic_op(tp, tp->jumbo_ops.disable);
9c5028e9 4975 RTL_W8(Cfg9346, Cfg9346_Lock);
d58d46b5
FR		 4976}
4977
4978static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4979{
4980 void __iomem *ioaddr = tp->mmio_addr;
4981
4982 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4983 RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
f65d539c 4984 rtl_tx_performance_tweak(tp->pci_dev, PCI_EXP_DEVCTL_READRQ_512B);
d58d46b5
FR		 4985}
4986
4987static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4988{
4989 void __iomem *ioaddr = tp->mmio_addr;
4990
4991 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4992 RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
4993 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
4994}
4995
4996static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4997{
4998 void __iomem *ioaddr = tp->mmio_addr;
4999
5000 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
5001}
5002
5003static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
5004{
5005 void __iomem *ioaddr = tp->mmio_addr;
5006
5007 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
5008}
5009
5010static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
5011{
5012 void __iomem *ioaddr = tp->mmio_addr;
d58d46b5
FR		 5013
5014 RTL_W8(MaxTxPacketSize, 0x3f);
5015 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
5016 RTL_W8(Config4, RTL_R8(Config4) | 0x01);
f65d539c 5017 rtl_tx_performance_tweak(tp->pci_dev, PCI_EXP_DEVCTL_READRQ_512B);
d58d46b5
FR		 5018}
5019
5020static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
5021{
5022 void __iomem *ioaddr = tp->mmio_addr;
d58d46b5
FR		 5023
5024 RTL_W8(MaxTxPacketSize, 0x0c);
5025 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
5026 RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
4512ff9f 5027 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
d58d46b5
FR		 5028}
5029
5030static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
5031{
5032 rtl_tx_performance_tweak(tp->pci_dev,
f65d539c 5033 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
d58d46b5
FR		 5034}
5035
5036static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
5037{
5038 rtl_tx_performance_tweak(tp->pci_dev,
5039 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
5040}
5041
5042static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
5043{
5044 void __iomem *ioaddr = tp->mmio_addr;
5045
5046 r8168b_0_hw_jumbo_enable(tp);
5047
5048 RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
5049}
5050
5051static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
5052{
5053 void __iomem *ioaddr = tp->mmio_addr;
5054
5055 r8168b_0_hw_jumbo_disable(tp);
5056
5057 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
5058}
5059
baf63293 5060static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
d58d46b5
FR		 5061{
5062 struct jumbo_ops *ops = &tp->jumbo_ops;
5063
5064 switch (tp->mac_version) {
5065 case RTL_GIGA_MAC_VER_11:
5066 ops->disable = r8168b_0_hw_jumbo_disable;
5067 ops->enable = r8168b_0_hw_jumbo_enable;
5068 break;
5069 case RTL_GIGA_MAC_VER_12:
5070 case RTL_GIGA_MAC_VER_17:
5071 ops->disable = r8168b_1_hw_jumbo_disable;
5072 ops->enable = r8168b_1_hw_jumbo_enable;
5073 break;
5074 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
5075 case RTL_GIGA_MAC_VER_19:
5076 case RTL_GIGA_MAC_VER_20:
5077 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
5078 case RTL_GIGA_MAC_VER_22:
5079 case RTL_GIGA_MAC_VER_23:
5080 case RTL_GIGA_MAC_VER_24:
5081 case RTL_GIGA_MAC_VER_25:
5082 case RTL_GIGA_MAC_VER_26:
5083 ops->disable = r8168c_hw_jumbo_disable;
5084 ops->enable = r8168c_hw_jumbo_enable;
5085 break;
5086 case RTL_GIGA_MAC_VER_27:
5087 case RTL_GIGA_MAC_VER_28:
5088 ops->disable = r8168dp_hw_jumbo_disable;
5089 ops->enable = r8168dp_hw_jumbo_enable;
5090 break;
5091 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
5092 case RTL_GIGA_MAC_VER_32:
5093 case RTL_GIGA_MAC_VER_33:
5094 case RTL_GIGA_MAC_VER_34:
5095 ops->disable = r8168e_hw_jumbo_disable;
5096 ops->enable = r8168e_hw_jumbo_enable;
5097 break;
5098
5099 /*
5100 * No action needed for jumbo frames with 8169.
5101 * No jumbo for 810x at all.
5102 */
c558386b
HW		 5103 case RTL_GIGA_MAC_VER_40:
5104 case RTL_GIGA_MAC_VER_41:
57538c4a 5105 case RTL_GIGA_MAC_VER_42:
58152cd4 5106 case RTL_GIGA_MAC_VER_43:
45dd95c4 5107 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 5108 case RTL_GIGA_MAC_VER_45:
5109 case RTL_GIGA_MAC_VER_46:
5110 case RTL_GIGA_MAC_VER_47:
5111 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 5112 case RTL_GIGA_MAC_VER_49:
5113 case RTL_GIGA_MAC_VER_50:
5114 case RTL_GIGA_MAC_VER_51:
d58d46b5
FR		 5115 default:
5116 ops->disable = NULL;
5117 ops->enable = NULL;
5118 break;
5119 }
5120}
5121
ffc46952
FR		 5122DECLARE_RTL_COND(rtl_chipcmd_cond)
5123{
5124 void __iomem *ioaddr = tp->mmio_addr;
5125
5126 return RTL_R8(ChipCmd) & CmdReset;
5127}
5128
6f43adc8
FR		 5129static void rtl_hw_reset(struct rtl8169_private *tp)
5130{
5131 void __iomem *ioaddr = tp->mmio_addr;
6f43adc8 5132
6f43adc8
FR		 5133 RTL_W8(ChipCmd, CmdReset);
5134
ffc46952 5135 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
6f43adc8
FR		 5136}
5137
b6ffd97f 5138static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
953a12cc 5139{
b6ffd97f
FR		 5140 struct rtl_fw *rtl_fw;
5141 const char *name;
5142 int rc = -ENOMEM;
953a12cc 5143
b6ffd97f
FR		 5144 name = rtl_lookup_firmware_name(tp);
5145 if (!name)
5146 goto out_no_firmware;
953a12cc 5147
b6ffd97f
FR		 5148 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
5149 if (!rtl_fw)
5150 goto err_warn;
31bd204f 5151
b6ffd97f
FR		 5152 rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
5153 if (rc < 0)
5154 goto err_free;
5155
fd112f2e
FR		 5156 rc = rtl_check_firmware(tp, rtl_fw);
5157 if (rc < 0)
5158 goto err_release_firmware;
5159
b6ffd97f
FR		 5160 tp->rtl_fw = rtl_fw;
5161out:
5162 return;
5163
fd112f2e
FR		 5164err_release_firmware:
5165 release_firmware(rtl_fw->fw);
b6ffd97f
FR		 5166err_free:
5167 kfree(rtl_fw);
5168err_warn:
5169 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
5170 name, rc);
5171out_no_firmware:
5172 tp->rtl_fw = NULL;
5173 goto out;
5174}
5175
5176static void rtl_request_firmware(struct rtl8169_private *tp)
5177{
5178 if (IS_ERR(tp->rtl_fw))
5179 rtl_request_uncached_firmware(tp);
953a12cc
FR		 5180}
5181
92fc43b4
HW		 5182static void rtl_rx_close(struct rtl8169_private *tp)
5183{
5184 void __iomem *ioaddr = tp->mmio_addr;
92fc43b4 5185
1687b566 5186 RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
92fc43b4
HW		 5187}
5188
ffc46952
FR		 5189DECLARE_RTL_COND(rtl_npq_cond)
5190{
5191 void __iomem *ioaddr = tp->mmio_addr;
5192
5193 return RTL_R8(TxPoll) & NPQ;
5194}
5195
5196DECLARE_RTL_COND(rtl_txcfg_empty_cond)
5197{
5198 void __iomem *ioaddr = tp->mmio_addr;
5199
5200 return RTL_R32(TxConfig) & TXCFG_EMPTY;
5201}
5202
e6de30d6 5203static void rtl8169_hw_reset(struct rtl8169_private *tp)
1da177e4 5204{
e6de30d6 5205 void __iomem *ioaddr = tp->mmio_addr;
5206
1da177e4 5207 /* Disable interrupts */
811fd301 5208 rtl8169_irq_mask_and_ack(tp);
1da177e4 5209
92fc43b4
HW		 5210 rtl_rx_close(tp);
5211
5d2e1957 5212 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4804b3b3 5213 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
5214 tp->mac_version == RTL_GIGA_MAC_VER_31) {
ffc46952 5215 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
c2218925 5216 } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
6e1d0b89
CHL		 5217 tp->mac_version == RTL_GIGA_MAC_VER_35 ||
5218 tp->mac_version == RTL_GIGA_MAC_VER_36 ||
5219 tp->mac_version == RTL_GIGA_MAC_VER_37 ||
5220 tp->mac_version == RTL_GIGA_MAC_VER_38 ||
5221 tp->mac_version == RTL_GIGA_MAC_VER_40 ||
5222 tp->mac_version == RTL_GIGA_MAC_VER_41 ||
5223 tp->mac_version == RTL_GIGA_MAC_VER_42 ||
5224 tp->mac_version == RTL_GIGA_MAC_VER_43 ||
5225 tp->mac_version == RTL_GIGA_MAC_VER_44 ||
5226 tp->mac_version == RTL_GIGA_MAC_VER_45 ||
5227 tp->mac_version == RTL_GIGA_MAC_VER_46 ||
5228 tp->mac_version == RTL_GIGA_MAC_VER_47 ||
935e2218
CHL		 5229 tp->mac_version == RTL_GIGA_MAC_VER_48 ||
5230 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
5231 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
5232 tp->mac_version == RTL_GIGA_MAC_VER_51) {
c2b0c1e7 5233 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
ffc46952 5234 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
92fc43b4
HW		 5235 } else {
5236 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
5237 udelay(100);
e6de30d6 5238 }
5239
92fc43b4 5240 rtl_hw_reset(tp);
1da177e4
LT		 5241}
5242
7f796d83 5243static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 5244{
5245 void __iomem *ioaddr = tp->mmio_addr;
9cb427b6
FR		 5246
5247 /* Set DMA burst size and Interframe Gap Time */
5248 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
5249 (InterFrameGap << TxInterFrameGapShift));
5250}
5251
07ce4064 5252static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 5253{
5254 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 5255
07ce4064
FR		 5256 tp->hw_start(dev);
5257
da78dbff 5258 rtl_irq_enable_all(tp);
07ce4064
FR		 5259}
5260
7f796d83
FR		 5261static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
5262 void __iomem *ioaddr)
5263{
5264 /*
5265 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
5266 * register to be written before TxDescAddrLow to work.
5267 * Switching from MMIO to I/O access fixes the issue as well.
5268 */
5269 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
284901a9 5270 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
7f796d83 5271 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
284901a9 5272 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 5273}
5274
5275static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
5276{
5277 u16 cmd;
5278
5279 cmd = RTL_R16(CPlusCmd);
5280 RTL_W16(CPlusCmd, cmd);
5281 return cmd;
5282}
5283
fdd7b4c3 5284static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
7f796d83
FR		 5285{
5286 /* Low hurts. Let's disable the filtering. */
207d6e87 5287 RTL_W16(RxMaxSize, rx_buf_sz + 1);
7f796d83
FR		 5288}
5289
6dccd16b
FR		 5290static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
5291{
3744100e 5292 static const struct rtl_cfg2_info {
6dccd16b
FR		 5293 u32 mac_version;
5294 u32 clk;
5295 u32 val;
5296 } cfg2_info [] = {
5297 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
5298 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
5299 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
5300 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3744100e
FR		 5301 };
5302 const struct rtl_cfg2_info *p = cfg2_info;
6dccd16b
FR		 5303 unsigned int i;
5304 u32 clk;
5305
5306 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 5307 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 5308 if ((p->mac_version == mac_version) && (p->clk == clk)) {
5309 RTL_W32(0x7c, p->val);
5310 break;
5311 }
5312 }
5313}
5314
e6b763ea
FR		 5315static void rtl_set_rx_mode(struct net_device *dev)
5316{
5317 struct rtl8169_private *tp = netdev_priv(dev);
5318 void __iomem *ioaddr = tp->mmio_addr;
5319 u32 mc_filter[2]; /* Multicast hash filter */
5320 int rx_mode;
5321 u32 tmp = 0;
5322
5323 if (dev->flags & IFF_PROMISC) {
5324 /* Unconditionally log net taps. */
5325 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
5326 rx_mode =
5327 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5328 AcceptAllPhys;
5329 mc_filter[1] = mc_filter[0] = 0xffffffff;
5330 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
5331 (dev->flags & IFF_ALLMULTI)) {
5332 /* Too many to filter perfectly -- accept all multicasts. */
5333 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5334 mc_filter[1] = mc_filter[0] = 0xffffffff;
5335 } else {
5336 struct netdev_hw_addr *ha;
5337
5338 rx_mode = AcceptBroadcast | AcceptMyPhys;
5339 mc_filter[1] = mc_filter[0] = 0;
5340 netdev_for_each_mc_addr(ha, dev) {
5341 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
5342 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5343 rx_mode |= AcceptMulticast;
5344 }
5345 }
5346
5347 if (dev->features & NETIF_F_RXALL)
5348 rx_mode |= (AcceptErr | AcceptRunt);
5349
5350 tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
5351
5352 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
5353 u32 data = mc_filter[0];
5354
5355 mc_filter[0] = swab32(mc_filter[1]);
5356 mc_filter[1] = swab32(data);
5357 }
5358
0481776b
NW		 5359 if (tp->mac_version == RTL_GIGA_MAC_VER_35)
5360 mc_filter[1] = mc_filter[0] = 0xffffffff;
5361
e6b763ea
FR		 5362 RTL_W32(MAR0 + 4, mc_filter[1]);
5363 RTL_W32(MAR0 + 0, mc_filter[0]);
5364
5365 RTL_W32(RxConfig, tmp);
5366}
5367
07ce4064
FR		 5368static void rtl_hw_start_8169(struct net_device *dev)
5369{
5370 struct rtl8169_private *tp = netdev_priv(dev);
5371 void __iomem *ioaddr = tp->mmio_addr;
5372 struct pci_dev *pdev = tp->pci_dev;
07ce4064 5373
9cb427b6
FR		 5374 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
5375 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
5376 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
5377 }
5378
1da177e4 5379 RTL_W8(Cfg9346, Cfg9346_Unlock);
cecb5fd7
FR		 5380 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
5381 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5382 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
5383 tp->mac_version == RTL_GIGA_MAC_VER_04)
9cb427b6
FR		 5384 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5385
e542a226
HW		 5386 rtl_init_rxcfg(tp);
5387
f0298f81 5388 RTL_W8(EarlyTxThres, NoEarlyTx);
1da177e4 5389
6f0333b8 5390 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
1da177e4 5391
cecb5fd7
FR		 5392 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
5393 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5394 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
5395 tp->mac_version == RTL_GIGA_MAC_VER_04)
c946b304 5396 rtl_set_rx_tx_config_registers(tp);
1da177e4 5397
7f796d83 5398 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 5399
cecb5fd7
FR		 5400 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5401 tp->mac_version == RTL_GIGA_MAC_VER_03) {
05b9687b 5402 dprintk("Set MAC Reg C+CR Offset 0xe0. "
1da177e4 5403 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 5404 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 5405 }
5406
bcf0bf90
FR		 5407 RTL_W16(CPlusCmd, tp->cp_cmd);
5408
6dccd16b
FR		 5409 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
5410
1da177e4
LT		 5411 /*
5412 * Undocumented corner. Supposedly:
5413 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
5414 */
5415 RTL_W16(IntrMitigate, 0x0000);
5416
7f796d83 5417 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 5418
cecb5fd7
FR		 5419 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
5420 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
5421 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
5422 tp->mac_version != RTL_GIGA_MAC_VER_04) {
c946b304
FR		 5423 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5424 rtl_set_rx_tx_config_registers(tp);
5425 }
5426
1da177e4 5427 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 5428
5429 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
5430 RTL_R8(IntrMask);
1da177e4
LT		 5431
5432 RTL_W32(RxMissed, 0);
5433
07ce4064 5434 rtl_set_rx_mode(dev);
1da177e4
LT		 5435
5436 /* no early-rx interrupts */
05b9687b 5437 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
07ce4064 5438}
1da177e4 5439
beb1fe18
HW		 5440static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
5441{
5442 if (tp->csi_ops.write)
52989f0e 5443 tp->csi_ops.write(tp, addr, value);
beb1fe18
HW		 5444}
5445
5446static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
5447{
52989f0e 5448 return tp->csi_ops.read ? tp->csi_ops.read(tp, addr) : ~0;
beb1fe18
HW		 5449}
5450
5451static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits)
dacf8154
FR		 5452{
5453 u32 csi;
5454
beb1fe18
HW		 5455 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
5456 rtl_csi_write(tp, 0x070c, csi | bits);
5457}
5458
5459static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
5460{
5461 rtl_csi_access_enable(tp, 0x17000000);
650e8d5d 5462}
5463
beb1fe18 5464static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
e6de30d6 5465{
beb1fe18 5466 rtl_csi_access_enable(tp, 0x27000000);
e6de30d6 5467}
5468
ffc46952
FR		 5469DECLARE_RTL_COND(rtl_csiar_cond)
5470{
5471 void __iomem *ioaddr = tp->mmio_addr;
5472
5473 return RTL_R32(CSIAR) & CSIAR_FLAG;
5474}
5475
52989f0e 5476static void r8169_csi_write(struct rtl8169_private *tp, int addr, int value)
650e8d5d 5477{
52989f0e 5478 void __iomem *ioaddr = tp->mmio_addr;
beb1fe18
HW		 5479
5480 RTL_W32(CSIDR, value);
5481 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5482 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5483
ffc46952 5484 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
beb1fe18
HW		 5485}
5486
52989f0e 5487static u32 r8169_csi_read(struct rtl8169_private *tp, int addr)
beb1fe18 5488{
52989f0e 5489 void __iomem *ioaddr = tp->mmio_addr;
beb1fe18
HW		 5490
5491 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
5492 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5493
ffc46952
FR		 5494 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5495 RTL_R32(CSIDR) : ~0;
beb1fe18
HW		 5496}
5497
52989f0e 5498static void r8402_csi_write(struct rtl8169_private *tp, int addr, int value)
7e18dca1 5499{
52989f0e 5500 void __iomem *ioaddr = tp->mmio_addr;
7e18dca1
HW		 5501
5502 RTL_W32(CSIDR, value);
5503 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5504 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
5505 CSIAR_FUNC_NIC);
5506
ffc46952 5507 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
7e18dca1
HW		 5508}
5509
52989f0e 5510static u32 r8402_csi_read(struct rtl8169_private *tp, int addr)
7e18dca1 5511{
52989f0e 5512 void __iomem *ioaddr = tp->mmio_addr;
7e18dca1
HW		 5513
5514 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
5515 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5516
ffc46952
FR		 5517 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5518 RTL_R32(CSIDR) : ~0;
7e18dca1
HW		 5519}
5520
45dd95c4 5521static void r8411_csi_write(struct rtl8169_private *tp, int addr, int value)
5522{
5523 void __iomem *ioaddr = tp->mmio_addr;
5524
5525 RTL_W32(CSIDR, value);
5526 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5527 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
5528 CSIAR_FUNC_NIC2);
5529
5530 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5531}
5532
5533static u32 r8411_csi_read(struct rtl8169_private *tp, int addr)
5534{
5535 void __iomem *ioaddr = tp->mmio_addr;
5536
5537 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC2 |
5538 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5539
5540 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5541 RTL_R32(CSIDR) : ~0;
5542}
5543
baf63293 5544static void rtl_init_csi_ops(struct rtl8169_private *tp)
beb1fe18
HW		 5545{
5546 struct csi_ops *ops = &tp->csi_ops;
5547
5548 switch (tp->mac_version) {
5549 case RTL_GIGA_MAC_VER_01:
5550 case RTL_GIGA_MAC_VER_02:
5551 case RTL_GIGA_MAC_VER_03:
5552 case RTL_GIGA_MAC_VER_04:
5553 case RTL_GIGA_MAC_VER_05:
5554 case RTL_GIGA_MAC_VER_06:
5555 case RTL_GIGA_MAC_VER_10:
5556 case RTL_GIGA_MAC_VER_11:
5557 case RTL_GIGA_MAC_VER_12:
5558 case RTL_GIGA_MAC_VER_13:
5559 case RTL_GIGA_MAC_VER_14:
5560 case RTL_GIGA_MAC_VER_15:
5561 case RTL_GIGA_MAC_VER_16:
5562 case RTL_GIGA_MAC_VER_17:
5563 ops->write = NULL;
5564 ops->read = NULL;
5565 break;
5566
7e18dca1 5567 case RTL_GIGA_MAC_VER_37:
b3d7b2f2 5568 case RTL_GIGA_MAC_VER_38:
7e18dca1
HW		 5569 ops->write = r8402_csi_write;
5570 ops->read = r8402_csi_read;
5571 break;
5572
45dd95c4 5573 case RTL_GIGA_MAC_VER_44:
5574 ops->write = r8411_csi_write;
5575 ops->read = r8411_csi_read;
5576 break;
5577
beb1fe18
HW		 5578 default:
5579 ops->write = r8169_csi_write;
5580 ops->read = r8169_csi_read;
5581 break;
5582 }
dacf8154
FR		 5583}
5584
5585struct ephy_info {
5586 unsigned int offset;
5587 u16 mask;
5588 u16 bits;
5589};
5590
fdf6fc06
FR		 5591static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
5592 int len)
dacf8154
FR		 5593{
5594 u16 w;
5595
5596 while (len-- > 0) {
fdf6fc06
FR		 5597 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
5598 rtl_ephy_write(tp, e->offset, w);
dacf8154
FR		 5599 e++;
5600 }
5601}
5602
b726e493
FR		 5603static void rtl_disable_clock_request(struct pci_dev *pdev)
5604{
7d7903b2
JL		 5605 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
5606 PCI_EXP_LNKCTL_CLKREQ_EN);
b726e493
FR		 5607}
5608
e6de30d6 5609static void rtl_enable_clock_request(struct pci_dev *pdev)
5610{
7d7903b2
JL		 5611 pcie_capability_set_word(pdev, PCI_EXP_LNKCTL,
5612 PCI_EXP_LNKCTL_CLKREQ_EN);
e6de30d6 5613}
5614
b51ecea8 5615static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable)
5616{
5617 void __iomem *ioaddr = tp->mmio_addr;
5618 u8 data;
5619
5620 data = RTL_R8(Config3);
5621
5622 if (enable)
5623 data |= Rdy_to_L23;
5624 else
5625 data &= ~Rdy_to_L23;
5626
5627 RTL_W8(Config3, data);
5628}
5629
b726e493
FR		 5630#define R8168_CPCMD_QUIRK_MASK (\
5631 EnableBist | \
5632 Mac_dbgo_oe | \
5633 Force_half_dup | \
5634 Force_rxflow_en | \
5635 Force_txflow_en | \
5636 Cxpl_dbg_sel | \
5637 ASF | \
5638 PktCntrDisable | \
5639 Mac_dbgo_sel)
5640
beb1fe18 5641static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
219a1e9d 5642{
beb1fe18
HW		 5643 void __iomem *ioaddr = tp->mmio_addr;
5644 struct pci_dev *pdev = tp->pci_dev;
5645
b726e493
FR		 5646 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5647
5648 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5649
faf1e785 5650 if (tp->dev->mtu <= ETH_DATA_LEN) {
5651 rtl_tx_performance_tweak(pdev, (0x5 << MAX_READ_REQUEST_SHIFT) |
5652 PCI_EXP_DEVCTL_NOSNOOP_EN);
5653 }
219a1e9d
FR		 5654}
5655
beb1fe18 5656static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
219a1e9d 5657{
beb1fe18
HW		 5658 void __iomem *ioaddr = tp->mmio_addr;
5659
5660 rtl_hw_start_8168bb(tp);
b726e493 5661
f0298f81 5662 RTL_W8(MaxTxPacketSize, TxPacketMax);
b726e493
FR		 5663
5664 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
219a1e9d
FR		 5665}
5666
beb1fe18 5667static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
219a1e9d 5668{
beb1fe18
HW		 5669 void __iomem *ioaddr = tp->mmio_addr;
5670 struct pci_dev *pdev = tp->pci_dev;
5671
b726e493
FR		 5672 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
5673
5674 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5675
faf1e785 5676 if (tp->dev->mtu <= ETH_DATA_LEN)
5677 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
b726e493
FR		 5678
5679 rtl_disable_clock_request(pdev);
5680
5681 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
219a1e9d
FR		 5682}
5683
beb1fe18 5684static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
219a1e9d 5685{
350f7596 5686 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 5687 { 0x01, 0, 0x0001 },
5688 { 0x02, 0x0800, 0x1000 },
5689 { 0x03, 0, 0x0042 },
5690 { 0x06, 0x0080, 0x0000 },
5691 { 0x07, 0, 0x2000 }
5692 };
5693
beb1fe18 5694 rtl_csi_access_enable_2(tp);
b726e493 5695
fdf6fc06 5696 rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
b726e493 5697
beb1fe18 5698 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 5699}
5700
beb1fe18 5701static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
ef3386f0 5702{
beb1fe18
HW		 5703 void __iomem *ioaddr = tp->mmio_addr;
5704 struct pci_dev *pdev = tp->pci_dev;
5705
5706 rtl_csi_access_enable_2(tp);
ef3386f0
FR		 5707
5708 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5709
faf1e785 5710 if (tp->dev->mtu <= ETH_DATA_LEN)
5711 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
ef3386f0
FR		 5712
5713 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5714}
5715
beb1fe18 5716static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
7f3e3d3a 5717{
beb1fe18
HW		 5718 void __iomem *ioaddr = tp->mmio_addr;
5719 struct pci_dev *pdev = tp->pci_dev;
5720
5721 rtl_csi_access_enable_2(tp);
7f3e3d3a
FR		 5722
5723 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5724
5725 /* Magic. */
5726 RTL_W8(DBG_REG, 0x20);
5727
f0298f81 5728 RTL_W8(MaxTxPacketSize, TxPacketMax);
7f3e3d3a 5729
faf1e785 5730 if (tp->dev->mtu <= ETH_DATA_LEN)
5731 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
7f3e3d3a
FR		 5732
5733 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5734}
5735
beb1fe18 5736static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
219a1e9d 5737{
beb1fe18 5738 void __iomem *ioaddr = tp->mmio_addr;
350f7596 5739 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 5740 { 0x02, 0x0800, 0x1000 },
5741 { 0x03, 0, 0x0002 },
5742 { 0x06, 0x0080, 0x0000 }
5743 };
5744
beb1fe18 5745 rtl_csi_access_enable_2(tp);
b726e493
FR		 5746
5747 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
5748
fdf6fc06 5749 rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
b726e493 5750
beb1fe18 5751 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 5752}
5753
beb1fe18 5754static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
219a1e9d 5755{
350f7596 5756 static const struct ephy_info e_info_8168c_2[] = {
b726e493
FR		 5757 { 0x01, 0, 0x0001 },
5758 { 0x03, 0x0400, 0x0220 }
5759 };
5760
beb1fe18 5761 rtl_csi_access_enable_2(tp);
b726e493 5762
fdf6fc06 5763 rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
b726e493 5764
beb1fe18 5765 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 5766}
5767
beb1fe18 5768static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
197ff761 5769{
beb1fe18 5770 rtl_hw_start_8168c_2(tp);
197ff761
FR		 5771}
5772
beb1fe18 5773static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
6fb07058 5774{
beb1fe18 5775 rtl_csi_access_enable_2(tp);
6fb07058 5776
beb1fe18 5777 __rtl_hw_start_8168cp(tp);
6fb07058
FR		 5778}
5779
beb1fe18 5780static void rtl_hw_start_8168d(struct rtl8169_private *tp)
5b538df9 5781{
beb1fe18
HW		 5782 void __iomem *ioaddr = tp->mmio_addr;
5783 struct pci_dev *pdev = tp->pci_dev;
5784
5785 rtl_csi_access_enable_2(tp);
5b538df9
FR		 5786
5787 rtl_disable_clock_request(pdev);
5788
f0298f81 5789 RTL_W8(MaxTxPacketSize, TxPacketMax);
5b538df9 5790
faf1e785 5791 if (tp->dev->mtu <= ETH_DATA_LEN)
5792 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5b538df9
FR		 5793
5794 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5795}
5796
beb1fe18 5797static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4804b3b3 5798{
beb1fe18
HW		 5799 void __iomem *ioaddr = tp->mmio_addr;
5800 struct pci_dev *pdev = tp->pci_dev;
5801
5802 rtl_csi_access_enable_1(tp);
4804b3b3 5803
faf1e785 5804 if (tp->dev->mtu <= ETH_DATA_LEN)
5805 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4804b3b3 5806
5807 RTL_W8(MaxTxPacketSize, TxPacketMax);
5808
5809 rtl_disable_clock_request(pdev);
5810}
5811
beb1fe18 5812static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
e6de30d6 5813{
beb1fe18
HW		 5814 void __iomem *ioaddr = tp->mmio_addr;
5815 struct pci_dev *pdev = tp->pci_dev;
e6de30d6 5816 static const struct ephy_info e_info_8168d_4[] = {
1016a4a1
CHL		 5817 { 0x0b, 0x0000, 0x0048 },
5818 { 0x19, 0x0020, 0x0050 },
5819 { 0x0c, 0x0100, 0x0020 }
e6de30d6 5820 };
e6de30d6 5821
beb1fe18 5822 rtl_csi_access_enable_1(tp);
e6de30d6 5823
5824 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5825
5826 RTL_W8(MaxTxPacketSize, TxPacketMax);
5827
1016a4a1 5828 rtl_ephy_init(tp, e_info_8168d_4, ARRAY_SIZE(e_info_8168d_4));
e6de30d6 5829
5830 rtl_enable_clock_request(pdev);
5831}
5832
beb1fe18 5833static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
01dc7fec 5834{
beb1fe18
HW		 5835 void __iomem *ioaddr = tp->mmio_addr;
5836 struct pci_dev *pdev = tp->pci_dev;
70090424 5837 static const struct ephy_info e_info_8168e_1[] = {
01dc7fec 5838 { 0x00, 0x0200, 0x0100 },
5839 { 0x00, 0x0000, 0x0004 },
5840 { 0x06, 0x0002, 0x0001 },
5841 { 0x06, 0x0000, 0x0030 },
5842 { 0x07, 0x0000, 0x2000 },
5843 { 0x00, 0x0000, 0x0020 },
5844 { 0x03, 0x5800, 0x2000 },
5845 { 0x03, 0x0000, 0x0001 },
5846 { 0x01, 0x0800, 0x1000 },
5847 { 0x07, 0x0000, 0x4000 },
5848 { 0x1e, 0x0000, 0x2000 },
5849 { 0x19, 0xffff, 0xfe6c },
5850 { 0x0a, 0x0000, 0x0040 }
5851 };
5852
beb1fe18 5853 rtl_csi_access_enable_2(tp);
01dc7fec 5854
fdf6fc06 5855 rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
01dc7fec 5856
faf1e785 5857 if (tp->dev->mtu <= ETH_DATA_LEN)
5858 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
01dc7fec 5859
5860 RTL_W8(MaxTxPacketSize, TxPacketMax);
5861
5862 rtl_disable_clock_request(pdev);
5863
5864 /* Reset tx FIFO pointer */
cecb5fd7
FR		 5865 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
5866 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
01dc7fec 5867
cecb5fd7 5868 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
01dc7fec 5869}
5870
beb1fe18 5871static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
70090424 5872{
beb1fe18
HW		 5873 void __iomem *ioaddr = tp->mmio_addr;
5874 struct pci_dev *pdev = tp->pci_dev;
70090424
HW		 5875 static const struct ephy_info e_info_8168e_2[] = {
5876 { 0x09, 0x0000, 0x0080 },
5877 { 0x19, 0x0000, 0x0224 }
5878 };
5879
beb1fe18 5880 rtl_csi_access_enable_1(tp);
70090424 5881
fdf6fc06 5882 rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
70090424 5883
faf1e785 5884 if (tp->dev->mtu <= ETH_DATA_LEN)
5885 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
70090424 5886
fdf6fc06
FR		 5887 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5888 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5889 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5890 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5891 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5892 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
706123d0
CHL		 5893 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5894 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
70090424 5895
3090bd9a 5896 RTL_W8(MaxTxPacketSize, EarlySize);
70090424 5897
4521e1a9
FR		 5898 rtl_disable_clock_request(pdev);
5899
70090424
HW		 5900 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5901 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5902
5903 /* Adjust EEE LED frequency */
5904 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5905
5906 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5907 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4521e1a9 5908 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
70090424
HW		 5909}
5910
5f886e08 5911static void rtl_hw_start_8168f(struct rtl8169_private *tp)
c2218925 5912{
beb1fe18
HW		 5913 void __iomem *ioaddr = tp->mmio_addr;
5914 struct pci_dev *pdev = tp->pci_dev;
c2218925 5915
5f886e08 5916 rtl_csi_access_enable_2(tp);
c2218925
HW		 5917
5918 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5919
fdf6fc06
FR		 5920 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5921 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5922 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5923 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
706123d0
CHL		 5924 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5925 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5926 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5927 rtl_w0w1_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
fdf6fc06
FR		 5928 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5929 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
c2218925
HW		 5930
5931 RTL_W8(MaxTxPacketSize, EarlySize);
5932
4521e1a9
FR		 5933 rtl_disable_clock_request(pdev);
5934
c2218925
HW		 5935 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5936 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
c2218925 5937 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4521e1a9
FR		 5938 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5939 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
c2218925
HW		 5940}
5941
5f886e08
HW		 5942static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5943{
5944 void __iomem *ioaddr = tp->mmio_addr;
5945 static const struct ephy_info e_info_8168f_1[] = {
5946 { 0x06, 0x00c0, 0x0020 },
5947 { 0x08, 0x0001, 0x0002 },
5948 { 0x09, 0x0000, 0x0080 },
5949 { 0x19, 0x0000, 0x0224 }
5950 };
5951
5952 rtl_hw_start_8168f(tp);
5953
fdf6fc06 5954 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5f886e08 5955
706123d0 5956 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5f886e08
HW		 5957
5958 /* Adjust EEE LED frequency */
5959 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5960}
5961
b3d7b2f2
HW		 5962static void rtl_hw_start_8411(struct rtl8169_private *tp)
5963{
b3d7b2f2
HW		 5964 static const struct ephy_info e_info_8168f_1[] = {
5965 { 0x06, 0x00c0, 0x0020 },
5966 { 0x0f, 0xffff, 0x5200 },
5967 { 0x1e, 0x0000, 0x4000 },
5968 { 0x19, 0x0000, 0x0224 }
5969 };
5970
5971 rtl_hw_start_8168f(tp);
b51ecea8 5972 rtl_pcie_state_l2l3_enable(tp, false);
b3d7b2f2 5973
fdf6fc06 5974 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
b3d7b2f2 5975
706123d0 5976 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
b3d7b2f2
HW		 5977}
5978
5fbea337 5979static void rtl_hw_start_8168g(struct rtl8169_private *tp)
c558386b
HW		 5980{
5981 void __iomem *ioaddr = tp->mmio_addr;
5982 struct pci_dev *pdev = tp->pci_dev;
5983
beb330a4 5984 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5985
c558386b
HW		 5986 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
5987 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5988 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5989 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5990
5991 rtl_csi_access_enable_1(tp);
5992
5993 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5994
706123d0
CHL		 5995 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5996 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
beb330a4 5997 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
c558386b 5998
4521e1a9 5999 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
c558386b
HW		 6000 RTL_W8(MaxTxPacketSize, EarlySize);
6001
6002 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6003 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6004
6005 /* Adjust EEE LED frequency */
6006 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6007
706123d0
CHL		 6008 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
6009 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
b51ecea8 6010
6011 rtl_pcie_state_l2l3_enable(tp, false);
c558386b
HW		 6012}
6013
5fbea337
CHL		 6014static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
6015{
6016 void __iomem *ioaddr = tp->mmio_addr;
6017 static const struct ephy_info e_info_8168g_1[] = {
6018 { 0x00, 0x0000, 0x0008 },
6019 { 0x0c, 0x37d0, 0x0820 },
6020 { 0x1e, 0x0000, 0x0001 },
6021 { 0x19, 0x8000, 0x0000 }
6022 };
6023
6024 rtl_hw_start_8168g(tp);
6025
6026 /* disable aspm and clock request before access ephy */
6027 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6028 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6029 rtl_ephy_init(tp, e_info_8168g_1, ARRAY_SIZE(e_info_8168g_1));
6030}
6031
57538c4a 6032static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
6033{
6034 void __iomem *ioaddr = tp->mmio_addr;
6035 static const struct ephy_info e_info_8168g_2[] = {
6036 { 0x00, 0x0000, 0x0008 },
6037 { 0x0c, 0x3df0, 0x0200 },
6038 { 0x19, 0xffff, 0xfc00 },
6039 { 0x1e, 0xffff, 0x20eb }
6040 };
6041
5fbea337 6042 rtl_hw_start_8168g(tp);
57538c4a 6043
6044 /* disable aspm and clock request before access ephy */
6045 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6046 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6047 rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
6048}
6049
45dd95c4 6050static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
6051{
6052 void __iomem *ioaddr = tp->mmio_addr;
6053 static const struct ephy_info e_info_8411_2[] = {
6054 { 0x00, 0x0000, 0x0008 },
6055 { 0x0c, 0x3df0, 0x0200 },
6056 { 0x0f, 0xffff, 0x5200 },
6057 { 0x19, 0x0020, 0x0000 },
6058 { 0x1e, 0x0000, 0x2000 }
6059 };
6060
5fbea337 6061 rtl_hw_start_8168g(tp);
45dd95c4 6062
6063 /* disable aspm and clock request before access ephy */
6064 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6065 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6066 rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
6067}
6068
6e1d0b89
CHL		 6069static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
6070{
6071 void __iomem *ioaddr = tp->mmio_addr;
6072 struct pci_dev *pdev = tp->pci_dev;
72521ea0 6073 int rg_saw_cnt;
6e1d0b89
CHL		 6074 u32 data;
6075 static const struct ephy_info e_info_8168h_1[] = {
6076 { 0x1e, 0x0800, 0x0001 },
6077 { 0x1d, 0x0000, 0x0800 },
6078 { 0x05, 0xffff, 0x2089 },
6079 { 0x06, 0xffff, 0x5881 },
6080 { 0x04, 0xffff, 0x154a },
6081 { 0x01, 0xffff, 0x068b }
6082 };
6083
6084 /* disable aspm and clock request before access ephy */
6085 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6086 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6087 rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));
6088
6089 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6090
6091 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
6092 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
6093 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
6094 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6095
6096 rtl_csi_access_enable_1(tp);
6097
6098 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6099
706123d0
CHL		 6100 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6101 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6e1d0b89 6102
706123d0 6103 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);
6e1d0b89 6104
706123d0 6105 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);
6e1d0b89
CHL		 6106
6107 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
6108
6e1d0b89
CHL		 6109 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
6110 RTL_W8(MaxTxPacketSize, EarlySize);
6111
6112 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6113 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6114
6115 /* Adjust EEE LED frequency */
6116 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6117
6118 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
69f3dc37 6119 RTL_W8(MISC_1, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
6e1d0b89
CHL		 6120
6121 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~TX_10M_PS_EN);
6122
706123d0 6123 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
6e1d0b89
CHL		 6124
6125 rtl_pcie_state_l2l3_enable(tp, false);
6126
6127 rtl_writephy(tp, 0x1f, 0x0c42);
58493333 6128 rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
6e1d0b89
CHL		 6129 rtl_writephy(tp, 0x1f, 0x0000);
6130 if (rg_saw_cnt > 0) {
6131 u16 sw_cnt_1ms_ini;
6132
6133 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
6134 sw_cnt_1ms_ini &= 0x0fff;
6135 data = r8168_mac_ocp_read(tp, 0xd412);
a2cb7ec0 6136 data &= ~0x0fff;
6e1d0b89
CHL		 6137 data |= sw_cnt_1ms_ini;
6138 r8168_mac_ocp_write(tp, 0xd412, data);
6139 }
6140
6141 data = r8168_mac_ocp_read(tp, 0xe056);
a2cb7ec0
CHL		 6142 data &= ~0xf0;
6143 data |= 0x70;
6e1d0b89
CHL		 6144 r8168_mac_ocp_write(tp, 0xe056, data);
6145
6146 data = r8168_mac_ocp_read(tp, 0xe052);
a2cb7ec0
CHL		 6147 data &= ~0x6000;
6148 data |= 0x8008;
6e1d0b89
CHL		 6149 r8168_mac_ocp_write(tp, 0xe052, data);
6150
6151 data = r8168_mac_ocp_read(tp, 0xe0d6);
a2cb7ec0 6152 data &= ~0x01ff;
6e1d0b89
CHL		 6153 data |= 0x017f;
6154 r8168_mac_ocp_write(tp, 0xe0d6, data);
6155
6156 data = r8168_mac_ocp_read(tp, 0xd420);
a2cb7ec0 6157 data &= ~0x0fff;
6e1d0b89
CHL		 6158 data |= 0x047f;
6159 r8168_mac_ocp_write(tp, 0xd420, data);
6160
6161 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
6162 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
6163 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
6164 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
6165}
6166
935e2218
CHL		 6167static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
6168{
6169 void __iomem *ioaddr = tp->mmio_addr;
6170 struct pci_dev *pdev = tp->pci_dev;
6171
003609da
CHL		 6172 rtl8168ep_stop_cmac(tp);
6173
935e2218
CHL		 6174 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6175
6176 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
6177 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x2f, ERIAR_EXGMAC);
6178 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x5f, ERIAR_EXGMAC);
6179 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6180
6181 rtl_csi_access_enable_1(tp);
6182
6183 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6184
6185 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6186 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6187
6188 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f80, 0x00, ERIAR_EXGMAC);
6189
6190 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
6191
935e2218
CHL		 6192 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
6193 RTL_W8(MaxTxPacketSize, EarlySize);
6194
6195 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6196 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6197
6198 /* Adjust EEE LED frequency */
6199 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6200
6201 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
6202
6203 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~TX_10M_PS_EN);
6204
6205 rtl_pcie_state_l2l3_enable(tp, false);
6206}
6207
6208static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
6209{
6210 void __iomem *ioaddr = tp->mmio_addr;
6211 static const struct ephy_info e_info_8168ep_1[] = {
6212 { 0x00, 0xffff, 0x10ab },
6213 { 0x06, 0xffff, 0xf030 },
6214 { 0x08, 0xffff, 0x2006 },
6215 { 0x0d, 0xffff, 0x1666 },
6216 { 0x0c, 0x3ff0, 0x0000 }
6217 };
6218
6219 /* disable aspm and clock request before access ephy */
6220 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6221 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6222 rtl_ephy_init(tp, e_info_8168ep_1, ARRAY_SIZE(e_info_8168ep_1));
6223
6224 rtl_hw_start_8168ep(tp);
6225}
6226
6227static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
6228{
6229 void __iomem *ioaddr = tp->mmio_addr;
6230 static const struct ephy_info e_info_8168ep_2[] = {
6231 { 0x00, 0xffff, 0x10a3 },
6232 { 0x19, 0xffff, 0xfc00 },
6233 { 0x1e, 0xffff, 0x20ea }
6234 };
6235
6236 /* disable aspm and clock request before access ephy */
6237 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6238 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6239 rtl_ephy_init(tp, e_info_8168ep_2, ARRAY_SIZE(e_info_8168ep_2));
6240
6241 rtl_hw_start_8168ep(tp);
6242
6243 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
69f3dc37 6244 RTL_W8(MISC_1, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
935e2218
CHL		 6245}
6246
6247static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
6248{
6249 void __iomem *ioaddr = tp->mmio_addr;
6250 u32 data;
6251 static const struct ephy_info e_info_8168ep_3[] = {
6252 { 0x00, 0xffff, 0x10a3 },
6253 { 0x19, 0xffff, 0x7c00 },
6254 { 0x1e, 0xffff, 0x20eb },
6255 { 0x0d, 0xffff, 0x1666 }
6256 };
6257
6258 /* disable aspm and clock request before access ephy */
6259 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6260 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6261 rtl_ephy_init(tp, e_info_8168ep_3, ARRAY_SIZE(e_info_8168ep_3));
6262
6263 rtl_hw_start_8168ep(tp);
6264
6265 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
69f3dc37 6266 RTL_W8(MISC_1, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
935e2218
CHL		 6267
6268 data = r8168_mac_ocp_read(tp, 0xd3e2);
6269 data &= 0xf000;
6270 data |= 0x0271;
6271 r8168_mac_ocp_write(tp, 0xd3e2, data);
6272
6273 data = r8168_mac_ocp_read(tp, 0xd3e4);
6274 data &= 0xff00;
6275 r8168_mac_ocp_write(tp, 0xd3e4, data);
6276
6277 data = r8168_mac_ocp_read(tp, 0xe860);
6278 data |= 0x0080;
6279 r8168_mac_ocp_write(tp, 0xe860, data);
6280}
6281
07ce4064
FR		 6282static void rtl_hw_start_8168(struct net_device *dev)
6283{
2dd99530
FR		 6284 struct rtl8169_private *tp = netdev_priv(dev);
6285 void __iomem *ioaddr = tp->mmio_addr;
6286
6287 RTL_W8(Cfg9346, Cfg9346_Unlock);
6288
f0298f81 6289 RTL_W8(MaxTxPacketSize, TxPacketMax);
2dd99530 6290
6f0333b8 6291 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
2dd99530 6292
0e485150 6293 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 6294
6295 RTL_W16(CPlusCmd, tp->cp_cmd);
6296
0e485150 6297 RTL_W16(IntrMitigate, 0x5151);
2dd99530 6298
0e485150 6299 /* Work around for RxFIFO overflow. */
811fd301 6300 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
da78dbff
FR		 6301 tp->event_slow |= RxFIFOOver | PCSTimeout;
6302 tp->event_slow &= ~RxOverflow;
0e485150
FR		 6303 }
6304
6305 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530 6306
1a964649 6307 rtl_set_rx_tx_config_registers(tp);
2dd99530
FR		 6308
6309 RTL_R8(IntrMask);
6310
219a1e9d
FR		 6311 switch (tp->mac_version) {
6312 case RTL_GIGA_MAC_VER_11:
beb1fe18 6313 rtl_hw_start_8168bb(tp);
4804b3b3 6314 break;
219a1e9d
FR		 6315
6316 case RTL_GIGA_MAC_VER_12:
6317 case RTL_GIGA_MAC_VER_17:
beb1fe18 6318 rtl_hw_start_8168bef(tp);
4804b3b3 6319 break;
219a1e9d
FR		 6320
6321 case RTL_GIGA_MAC_VER_18:
beb1fe18 6322 rtl_hw_start_8168cp_1(tp);
4804b3b3 6323 break;
219a1e9d
FR		 6324
6325 case RTL_GIGA_MAC_VER_19:
beb1fe18 6326 rtl_hw_start_8168c_1(tp);
4804b3b3 6327 break;
219a1e9d
FR		 6328
6329 case RTL_GIGA_MAC_VER_20:
beb1fe18 6330 rtl_hw_start_8168c_2(tp);
4804b3b3 6331 break;
219a1e9d 6332
197ff761 6333 case RTL_GIGA_MAC_VER_21:
beb1fe18 6334 rtl_hw_start_8168c_3(tp);
4804b3b3 6335 break;
197ff761 6336
6fb07058 6337 case RTL_GIGA_MAC_VER_22:
beb1fe18 6338 rtl_hw_start_8168c_4(tp);
4804b3b3 6339 break;
6fb07058 6340
ef3386f0 6341 case RTL_GIGA_MAC_VER_23:
beb1fe18 6342 rtl_hw_start_8168cp_2(tp);
4804b3b3 6343 break;
ef3386f0 6344
7f3e3d3a 6345 case RTL_GIGA_MAC_VER_24:
beb1fe18 6346 rtl_hw_start_8168cp_3(tp);
4804b3b3 6347 break;
7f3e3d3a 6348
5b538df9 6349 case RTL_GIGA_MAC_VER_25:
daf9df6d 6350 case RTL_GIGA_MAC_VER_26:
6351 case RTL_GIGA_MAC_VER_27:
beb1fe18 6352 rtl_hw_start_8168d(tp);
4804b3b3 6353 break;
5b538df9 6354
e6de30d6 6355 case RTL_GIGA_MAC_VER_28:
beb1fe18 6356 rtl_hw_start_8168d_4(tp);
4804b3b3 6357 break;
cecb5fd7 6358
4804b3b3 6359 case RTL_GIGA_MAC_VER_31:
beb1fe18 6360 rtl_hw_start_8168dp(tp);
4804b3b3 6361 break;
6362
01dc7fec 6363 case RTL_GIGA_MAC_VER_32:
6364 case RTL_GIGA_MAC_VER_33:
beb1fe18 6365 rtl_hw_start_8168e_1(tp);
70090424
HW		 6366 break;
6367 case RTL_GIGA_MAC_VER_34:
beb1fe18 6368 rtl_hw_start_8168e_2(tp);
01dc7fec 6369 break;
e6de30d6 6370
c2218925
HW		 6371 case RTL_GIGA_MAC_VER_35:
6372 case RTL_GIGA_MAC_VER_36:
beb1fe18 6373 rtl_hw_start_8168f_1(tp);
c2218925
HW		 6374 break;
6375
b3d7b2f2
HW		 6376 case RTL_GIGA_MAC_VER_38:
6377 rtl_hw_start_8411(tp);
6378 break;
6379
c558386b
HW		 6380 case RTL_GIGA_MAC_VER_40:
6381 case RTL_GIGA_MAC_VER_41:
6382 rtl_hw_start_8168g_1(tp);
6383 break;
57538c4a 6384 case RTL_GIGA_MAC_VER_42:
6385 rtl_hw_start_8168g_2(tp);
6386 break;
c558386b 6387
45dd95c4 6388 case RTL_GIGA_MAC_VER_44:
6389 rtl_hw_start_8411_2(tp);
6390 break;
6391
6e1d0b89
CHL		 6392 case RTL_GIGA_MAC_VER_45:
6393 case RTL_GIGA_MAC_VER_46:
6394 rtl_hw_start_8168h_1(tp);
6395 break;
6396
935e2218
CHL		 6397 case RTL_GIGA_MAC_VER_49:
6398 rtl_hw_start_8168ep_1(tp);
6399 break;
6400
6401 case RTL_GIGA_MAC_VER_50:
6402 rtl_hw_start_8168ep_2(tp);
6403 break;
6404
6405 case RTL_GIGA_MAC_VER_51:
6406 rtl_hw_start_8168ep_3(tp);
6407 break;
6408
219a1e9d
FR		 6409 default:
6410 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
6411 dev->name, tp->mac_version);
4804b3b3 6412 break;
219a1e9d 6413 }
2dd99530 6414
1a964649 6415 RTL_W8(Cfg9346, Cfg9346_Lock);
6416
0e485150
FR		 6417 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
6418
1a964649 6419 rtl_set_rx_mode(dev);
b8363901 6420
05b9687b 6421 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
07ce4064 6422}
1da177e4 6423
2857ffb7
FR		 6424#define R810X_CPCMD_QUIRK_MASK (\
6425 EnableBist | \
6426 Mac_dbgo_oe | \
6427 Force_half_dup | \
5edcc537 6428 Force_rxflow_en | \
2857ffb7
FR		 6429 Force_txflow_en | \
6430 Cxpl_dbg_sel | \
6431 ASF | \
6432 PktCntrDisable | \
d24e9aaf 6433 Mac_dbgo_sel)
2857ffb7 6434
beb1fe18 6435static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
2857ffb7 6436{
beb1fe18
HW		 6437 void __iomem *ioaddr = tp->mmio_addr;
6438 struct pci_dev *pdev = tp->pci_dev;
350f7596 6439 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 6440 { 0x01, 0, 0x6e65 },
6441 { 0x02, 0, 0x091f },
6442 { 0x03, 0, 0xc2f9 },
6443 { 0x06, 0, 0xafb5 },
6444 { 0x07, 0, 0x0e00 },
6445 { 0x19, 0, 0xec80 },
6446 { 0x01, 0, 0x2e65 },
6447 { 0x01, 0, 0x6e65 }
6448 };
6449 u8 cfg1;
6450
beb1fe18 6451 rtl_csi_access_enable_2(tp);
2857ffb7
FR		 6452
6453 RTL_W8(DBG_REG, FIX_NAK_1);
6454
6455 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6456
6457 RTL_W8(Config1,
6458 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
6459 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
6460
6461 cfg1 = RTL_R8(Config1);
6462 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
6463 RTL_W8(Config1, cfg1 & ~LEDS0);
6464
fdf6fc06 6465 rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
2857ffb7
FR		 6466}
6467
beb1fe18 6468static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
2857ffb7 6469{
beb1fe18
HW		 6470 void __iomem *ioaddr = tp->mmio_addr;
6471 struct pci_dev *pdev = tp->pci_dev;
6472
6473 rtl_csi_access_enable_2(tp);
2857ffb7
FR		 6474
6475 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6476
6477 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
6478 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2857ffb7
FR		 6479}
6480
beb1fe18 6481static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
2857ffb7 6482{
beb1fe18 6483 rtl_hw_start_8102e_2(tp);
2857ffb7 6484
fdf6fc06 6485 rtl_ephy_write(tp, 0x03, 0xc2f9);
2857ffb7
FR		 6486}
6487
beb1fe18 6488static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5a5e4443 6489{
beb1fe18 6490 void __iomem *ioaddr = tp->mmio_addr;
5a5e4443
HW		 6491 static const struct ephy_info e_info_8105e_1[] = {
6492 { 0x07, 0, 0x4000 },
6493 { 0x19, 0, 0x0200 },
6494 { 0x19, 0, 0x0020 },
6495 { 0x1e, 0, 0x2000 },
6496 { 0x03, 0, 0x0001 },
6497 { 0x19, 0, 0x0100 },
6498 { 0x19, 0, 0x0004 },
6499 { 0x0a, 0, 0x0020 }
6500 };
6501
cecb5fd7 6502 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5a5e4443
HW		 6503 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6504
cecb5fd7 6505 /* Disable Early Tally Counter */
5a5e4443
HW		 6506 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
6507
6508 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4f6b00e5 6509 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5a5e4443 6510
fdf6fc06 6511 rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
b51ecea8 6512
6513 rtl_pcie_state_l2l3_enable(tp, false);
5a5e4443
HW		 6514}
6515
beb1fe18 6516static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5a5e4443 6517{
beb1fe18 6518 rtl_hw_start_8105e_1(tp);
fdf6fc06 6519 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5a5e4443
HW		 6520}
6521
7e18dca1
HW		 6522static void rtl_hw_start_8402(struct rtl8169_private *tp)
6523{
6524 void __iomem *ioaddr = tp->mmio_addr;
6525 static const struct ephy_info e_info_8402[] = {
6526 { 0x19, 0xffff, 0xff64 },
6527 { 0x1e, 0, 0x4000 }
6528 };
6529
6530 rtl_csi_access_enable_2(tp);
6531
6532 /* Force LAN exit from ASPM if Rx/Tx are not idle */
6533 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6534
6535 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6536 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
6537
fdf6fc06 6538 rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
7e18dca1
HW		 6539
6540 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
6541
fdf6fc06
FR		 6542 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
6543 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
706123d0
CHL		 6544 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6545 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
fdf6fc06
FR		 6546 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6547 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
706123d0 6548 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
b51ecea8 6549
6550 rtl_pcie_state_l2l3_enable(tp, false);
7e18dca1
HW		 6551}
6552
5598bfe5
HW		 6553static void rtl_hw_start_8106(struct rtl8169_private *tp)
6554{
6555 void __iomem *ioaddr = tp->mmio_addr;
6556
6557 /* Force LAN exit from ASPM if Rx/Tx are not idle */
6558 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6559
4521e1a9 6560 RTL_W32(MISC, (RTL_R32(MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5598bfe5
HW		 6561 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
6562 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
b51ecea8 6563
6564 rtl_pcie_state_l2l3_enable(tp, false);
5598bfe5
HW		 6565}
6566
07ce4064
FR		 6567static void rtl_hw_start_8101(struct net_device *dev)
6568{
cdf1a608
FR		 6569 struct rtl8169_private *tp = netdev_priv(dev);
6570 void __iomem *ioaddr = tp->mmio_addr;
6571 struct pci_dev *pdev = tp->pci_dev;
6572
da78dbff
FR		 6573 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
6574 tp->event_slow &= ~RxFIFOOver;
811fd301 6575
cecb5fd7 6576 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
7d7903b2 6577 tp->mac_version == RTL_GIGA_MAC_VER_16)
8200bc72
BH		 6578 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL,
6579 PCI_EXP_DEVCTL_NOSNOOP_EN);
cdf1a608 6580
d24e9aaf
HW		 6581 RTL_W8(Cfg9346, Cfg9346_Unlock);
6582
1a964649 6583 RTL_W8(MaxTxPacketSize, TxPacketMax);
6584
6585 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
6586
6587 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
6588 RTL_W16(CPlusCmd, tp->cp_cmd);
6589
6590 rtl_set_rx_tx_desc_registers(tp, ioaddr);
6591
6592 rtl_set_rx_tx_config_registers(tp);
6593
2857ffb7
FR		 6594 switch (tp->mac_version) {
6595 case RTL_GIGA_MAC_VER_07:
beb1fe18 6596 rtl_hw_start_8102e_1(tp);
2857ffb7
FR		 6597 break;
6598
6599 case RTL_GIGA_MAC_VER_08:
beb1fe18 6600 rtl_hw_start_8102e_3(tp);
2857ffb7
FR		 6601 break;
6602
6603 case RTL_GIGA_MAC_VER_09:
beb1fe18 6604 rtl_hw_start_8102e_2(tp);
2857ffb7 6605 break;
5a5e4443
HW		 6606
6607 case RTL_GIGA_MAC_VER_29:
beb1fe18 6608 rtl_hw_start_8105e_1(tp);
5a5e4443
HW		 6609 break;
6610 case RTL_GIGA_MAC_VER_30:
beb1fe18 6611 rtl_hw_start_8105e_2(tp);
5a5e4443 6612 break;
7e18dca1
HW		 6613
6614 case RTL_GIGA_MAC_VER_37:
6615 rtl_hw_start_8402(tp);
6616 break;
5598bfe5
HW		 6617
6618 case RTL_GIGA_MAC_VER_39:
6619 rtl_hw_start_8106(tp);
6620 break;
58152cd4 6621 case RTL_GIGA_MAC_VER_43:
6622 rtl_hw_start_8168g_2(tp);
6623 break;
6e1d0b89
CHL		 6624 case RTL_GIGA_MAC_VER_47:
6625 case RTL_GIGA_MAC_VER_48:
6626 rtl_hw_start_8168h_1(tp);
6627 break;
cdf1a608
FR		 6628 }
6629
d24e9aaf 6630 RTL_W8(Cfg9346, Cfg9346_Lock);
cdf1a608 6631
cdf1a608
FR		 6632 RTL_W16(IntrMitigate, 0x0000);
6633
cdf1a608 6634 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
cdf1a608 6635
cdf1a608
FR		 6636 rtl_set_rx_mode(dev);
6637
1a964649 6638 RTL_R8(IntrMask);
6639
cdf1a608 6640 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
1da177e4
LT		 6641}
6642
6643static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
6644{
d58d46b5
FR		 6645 struct rtl8169_private *tp = netdev_priv(dev);
6646
6647 if (new_mtu < ETH_ZLEN ||
6648 new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
1da177e4
LT		 6649 return -EINVAL;
6650
d58d46b5
FR		 6651 if (new_mtu > ETH_DATA_LEN)
6652 rtl_hw_jumbo_enable(tp);
6653 else
6654 rtl_hw_jumbo_disable(tp);
6655
1da177e4 6656 dev->mtu = new_mtu;
350fb32a
MM		 6657 netdev_update_features(dev);
6658
323bb685 6659 return 0;
1da177e4
LT		 6660}
6661
6662static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
6663{
95e0918d 6664 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 6665 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
6666}
6667
6f0333b8
ED		 6668static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
6669 void **data_buff, struct RxDesc *desc)
1da177e4 6670{
48addcc9 6671 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
231aee63 6672 DMA_FROM_DEVICE);
48addcc9 6673
6f0333b8
ED		 6674 kfree(*data_buff);
6675 *data_buff = NULL;
1da177e4
LT		 6676 rtl8169_make_unusable_by_asic(desc);
6677}
6678
6679static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
6680{
6681 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
6682
a0750138
AD		 6683 /* Force memory writes to complete before releasing descriptor */
6684 dma_wmb();
6685
1da177e4
LT		 6686 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
6687}
6688
6689static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
6690 u32 rx_buf_sz)
6691{
6692 desc->addr = cpu_to_le64(mapping);
1da177e4
LT		 6693 rtl8169_mark_to_asic(desc, rx_buf_sz);
6694}
6695
6f0333b8
ED		 6696static inline void *rtl8169_align(void *data)
6697{
6698 return (void *)ALIGN((long)data, 16);
6699}
6700
0ecbe1ca
SG		 6701static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
6702 struct RxDesc *desc)
1da177e4 6703{
6f0333b8 6704 void *data;
1da177e4 6705 dma_addr_t mapping;
48addcc9 6706 struct device *d = &tp->pci_dev->dev;
0ecbe1ca 6707 struct net_device *dev = tp->dev;
6f0333b8 6708 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
1da177e4 6709
6f0333b8
ED		 6710 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
6711 if (!data)
6712 return NULL;
e9f63f30 6713
6f0333b8
ED		 6714 if (rtl8169_align(data) != data) {
6715 kfree(data);
6716 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
6717 if (!data)
6718 return NULL;
6719 }
3eafe507 6720
48addcc9 6721 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
231aee63 6722 DMA_FROM_DEVICE);
d827d86b
SG		 6723 if (unlikely(dma_mapping_error(d, mapping))) {
6724 if (net_ratelimit())
6725 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
3eafe507 6726 goto err_out;
d827d86b 6727 }
1da177e4
LT		 6728
6729 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6f0333b8 6730 return data;
3eafe507
SG		 6731
6732err_out:
6733 kfree(data);
6734 return NULL;
1da177e4
LT		 6735}
6736
6737static void rtl8169_rx_clear(struct rtl8169_private *tp)
6738{
07d3f51f 6739 unsigned int i;
1da177e4
LT		 6740
6741 for (i = 0; i < NUM_RX_DESC; i++) {
6f0333b8
ED		 6742 if (tp->Rx_databuff[i]) {
6743 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
1da177e4
LT		 6744 tp->RxDescArray + i);
6745 }
6746 }
6747}
6748
0ecbe1ca 6749static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1da177e4 6750{
0ecbe1ca
SG		 6751 desc->opts1 |= cpu_to_le32(RingEnd);
6752}
5b0384f4 6753
0ecbe1ca
SG		 6754static int rtl8169_rx_fill(struct rtl8169_private *tp)
6755{
6756 unsigned int i;
1da177e4 6757
0ecbe1ca
SG		 6758 for (i = 0; i < NUM_RX_DESC; i++) {
6759 void *data;
4ae47c2d 6760
6f0333b8 6761 if (tp->Rx_databuff[i])
1da177e4 6762 continue;
bcf0bf90 6763
0ecbe1ca 6764 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6f0333b8
ED		 6765 if (!data) {
6766 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
0ecbe1ca 6767 goto err_out;
6f0333b8
ED		 6768 }
6769 tp->Rx_databuff[i] = data;
1da177e4 6770 }
1da177e4 6771
0ecbe1ca
SG		 6772 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
6773 return 0;
6774
6775err_out:
6776 rtl8169_rx_clear(tp);
6777 return -ENOMEM;
1da177e4
LT		 6778}
6779
1da177e4
LT		 6780static int rtl8169_init_ring(struct net_device *dev)
6781{
6782 struct rtl8169_private *tp = netdev_priv(dev);
6783
6784 rtl8169_init_ring_indexes(tp);
6785
6786 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
6f0333b8 6787 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
1da177e4 6788
0ecbe1ca 6789 return rtl8169_rx_fill(tp);
1da177e4
LT		 6790}
6791
48addcc9 6792static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
1da177e4
LT		 6793 struct TxDesc *desc)
6794{
6795 unsigned int len = tx_skb->len;
6796
48addcc9
SG		 6797 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
6798
1da177e4
LT		 6799 desc->opts1 = 0x00;
6800 desc->opts2 = 0x00;
6801 desc->addr = 0x00;
6802 tx_skb->len = 0;
6803}
6804
3eafe507
SG		 6805static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
6806 unsigned int n)
1da177e4
LT		 6807{
6808 unsigned int i;
6809
3eafe507
SG		 6810 for (i = 0; i < n; i++) {
6811 unsigned int entry = (start + i) % NUM_TX_DESC;
1da177e4
LT		 6812 struct ring_info *tx_skb = tp->tx_skb + entry;
6813 unsigned int len = tx_skb->len;
6814
6815 if (len) {
6816 struct sk_buff *skb = tx_skb->skb;
6817
48addcc9 6818 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
1da177e4
LT		 6819 tp->TxDescArray + entry);
6820 if (skb) {
cac4b22f 6821 tp->dev->stats.tx_dropped++;
989c9ba1 6822 dev_kfree_skb_any(skb);
1da177e4
LT		 6823 tx_skb->skb = NULL;
6824 }
1da177e4
LT		 6825 }
6826 }
3eafe507
SG		 6827}
6828
6829static void rtl8169_tx_clear(struct rtl8169_private *tp)
6830{
6831 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
1da177e4
LT		 6832 tp->cur_tx = tp->dirty_tx = 0;
6833}
6834
4422bcd4 6835static void rtl_reset_work(struct rtl8169_private *tp)
1da177e4 6836{
c4028958 6837 struct net_device *dev = tp->dev;
56de414c 6838 int i;
1da177e4 6839
da78dbff
FR		 6840 napi_disable(&tp->napi);
6841 netif_stop_queue(dev);
6842 synchronize_sched();
1da177e4 6843
c7c2c39b 6844 rtl8169_hw_reset(tp);
6845
56de414c
FR		 6846 for (i = 0; i < NUM_RX_DESC; i++)
6847 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
6848
1da177e4 6849 rtl8169_tx_clear(tp);
c7c2c39b 6850 rtl8169_init_ring_indexes(tp);
1da177e4 6851
da78dbff 6852 napi_enable(&tp->napi);
56de414c
FR		 6853 rtl_hw_start(dev);
6854 netif_wake_queue(dev);
6855 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1da177e4
LT		 6856}
6857
6858static void rtl8169_tx_timeout(struct net_device *dev)
6859{
da78dbff
FR		 6860 struct rtl8169_private *tp = netdev_priv(dev);
6861
6862 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 6863}
6864
6865static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2b7b4318 6866 u32 *opts)
1da177e4
LT		 6867{
6868 struct skb_shared_info *info = skb_shinfo(skb);
6869 unsigned int cur_frag, entry;
6e1d0b89 6870 struct TxDesc *uninitialized_var(txd);
48addcc9 6871 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 6872
6873 entry = tp->cur_tx;
6874 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
9e903e08 6875 const skb_frag_t *frag = info->frags + cur_frag;
1da177e4
LT		 6876 dma_addr_t mapping;
6877 u32 status, len;
6878 void *addr;
6879
6880 entry = (entry + 1) % NUM_TX_DESC;
6881
6882 txd = tp->TxDescArray + entry;
9e903e08 6883 len = skb_frag_size(frag);
929f6189 6884 addr = skb_frag_address(frag);
48addcc9 6885 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
d827d86b
SG		 6886 if (unlikely(dma_mapping_error(d, mapping))) {
6887 if (net_ratelimit())
6888 netif_err(tp, drv, tp->dev,
6889 "Failed to map TX fragments DMA!\n");
3eafe507 6890 goto err_out;
d827d86b 6891 }
1da177e4 6892
cecb5fd7 6893 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318
FR		 6894 status = opts[0] | len |
6895 (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 6896
6897 txd->opts1 = cpu_to_le32(status);
2b7b4318 6898 txd->opts2 = cpu_to_le32(opts[1]);
1da177e4
LT		 6899 txd->addr = cpu_to_le64(mapping);
6900
6901 tp->tx_skb[entry].len = len;
6902 }
6903
6904 if (cur_frag) {
6905 tp->tx_skb[entry].skb = skb;
6906 txd->opts1 |= cpu_to_le32(LastFrag);
6907 }
6908
6909 return cur_frag;
3eafe507
SG		 6910
6911err_out:
6912 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
6913 return -EIO;
1da177e4
LT		 6914}
6915
b423e9ae 6916static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
6917{
6918 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
6919}
6920
e974604b 6921static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6922 struct net_device *dev);
6923/* r8169_csum_workaround()
6924 * The hw limites the value the transport offset. When the offset is out of the
6925 * range, calculate the checksum by sw.
6926 */
6927static void r8169_csum_workaround(struct rtl8169_private *tp,
6928 struct sk_buff *skb)
6929{
6930 if (skb_shinfo(skb)->gso_size) {
6931 netdev_features_t features = tp->dev->features;
6932 struct sk_buff *segs, *nskb;
6933
6934 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
6935 segs = skb_gso_segment(skb, features);
6936 if (IS_ERR(segs) || !segs)
6937 goto drop;
6938
6939 do {
6940 nskb = segs;
6941 segs = segs->next;
6942 nskb->next = NULL;
6943 rtl8169_start_xmit(nskb, tp->dev);
6944 } while (segs);
6945
eb781397 6946 dev_consume_skb_any(skb);
e974604b 6947 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6948 if (skb_checksum_help(skb) < 0)
6949 goto drop;
6950
6951 rtl8169_start_xmit(skb, tp->dev);
6952 } else {
6953 struct net_device_stats *stats;
6954
6955drop:
6956 stats = &tp->dev->stats;
6957 stats->tx_dropped++;
eb781397 6958 dev_kfree_skb_any(skb);
e974604b 6959 }
6960}
6961
6962/* msdn_giant_send_check()
6963 * According to the document of microsoft, the TCP Pseudo Header excludes the
6964 * packet length for IPv6 TCP large packets.
6965 */
6966static int msdn_giant_send_check(struct sk_buff *skb)
6967{
6968 const struct ipv6hdr *ipv6h;
6969 struct tcphdr *th;
6970 int ret;
6971
6972 ret = skb_cow_head(skb, 0);
6973 if (ret)
6974 return ret;
6975
6976 ipv6h = ipv6_hdr(skb);
6977 th = tcp_hdr(skb);
6978
6979 th->check = 0;
6980 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
6981
6982 return ret;
6983}
6984
6985static inline __be16 get_protocol(struct sk_buff *skb)
6986{
6987 __be16 protocol;
6988
6989 if (skb->protocol == htons(ETH_P_8021Q))
6990 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
6991 else
6992 protocol = skb->protocol;
6993
6994 return protocol;
6995}
6996
5888d3fc 6997static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
6998 struct sk_buff *skb, u32 *opts)
1da177e4 6999{
350fb32a
MM		 7000 u32 mss = skb_shinfo(skb)->gso_size;
7001
2b7b4318
FR		 7002 if (mss) {
7003 opts[0] |= TD_LSO;
5888d3fc 7004 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
7005 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
7006 const struct iphdr *ip = ip_hdr(skb);
7007
7008 if (ip->protocol == IPPROTO_TCP)
7009 opts[0] |= TD0_IP_CS | TD0_TCP_CS;
7010 else if (ip->protocol == IPPROTO_UDP)
7011 opts[0] |= TD0_IP_CS | TD0_UDP_CS;
7012 else
7013 WARN_ON_ONCE(1);
7014 }
7015
7016 return true;
7017}
7018
7019static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
7020 struct sk_buff *skb, u32 *opts)
7021{
bdfa4ed6 7022 u32 transport_offset = (u32)skb_transport_offset(skb);
5888d3fc 7023 u32 mss = skb_shinfo(skb)->gso_size;
7024
7025 if (mss) {
e974604b 7026 if (transport_offset > GTTCPHO_MAX) {
7027 netif_warn(tp, tx_err, tp->dev,
7028 "Invalid transport offset 0x%x for TSO\n",
7029 transport_offset);
7030 return false;
7031 }
7032
7033 switch (get_protocol(skb)) {
7034 case htons(ETH_P_IP):
7035 opts[0] |= TD1_GTSENV4;
7036 break;
7037
7038 case htons(ETH_P_IPV6):
7039 if (msdn_giant_send_check(skb))
7040 return false;
7041
7042 opts[0] |= TD1_GTSENV6;
7043 break;
7044
7045 default:
7046 WARN_ON_ONCE(1);
7047 break;
7048 }
7049
bdfa4ed6 7050 opts[0] |= transport_offset << GTTCPHO_SHIFT;
5888d3fc 7051 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
2b7b4318 7052 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
e974604b 7053 u8 ip_protocol;
1da177e4 7054
b423e9ae 7055 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
207c5f44 7056 return !(skb_checksum_help(skb) || eth_skb_pad(skb));
b423e9ae 7057
e974604b 7058 if (transport_offset > TCPHO_MAX) {
7059 netif_warn(tp, tx_err, tp->dev,
7060 "Invalid transport offset 0x%x\n",
7061 transport_offset);
7062 return false;
7063 }
7064
7065 switch (get_protocol(skb)) {
7066 case htons(ETH_P_IP):
7067 opts[1] |= TD1_IPv4_CS;
7068 ip_protocol = ip_hdr(skb)->protocol;
7069 break;
7070
7071 case htons(ETH_P_IPV6):
7072 opts[1] |= TD1_IPv6_CS;
7073 ip_protocol = ipv6_hdr(skb)->nexthdr;
7074 break;
7075
7076 default:
7077 ip_protocol = IPPROTO_RAW;
7078 break;
7079 }
7080
7081 if (ip_protocol == IPPROTO_TCP)
7082 opts[1] |= TD1_TCP_CS;
7083 else if (ip_protocol == IPPROTO_UDP)
7084 opts[1] |= TD1_UDP_CS;
2b7b4318
FR		 7085 else
7086 WARN_ON_ONCE(1);
e974604b 7087
7088 opts[1] |= transport_offset << TCPHO_SHIFT;
b423e9ae 7089 } else {
7090 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
207c5f44 7091 return !eth_skb_pad(skb);
1da177e4 7092 }
5888d3fc 7093
b423e9ae 7094 return true;
1da177e4
LT		 7095}
7096
61357325
SH		 7097static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
7098 struct net_device *dev)
1da177e4
LT		 7099{
7100 struct rtl8169_private *tp = netdev_priv(dev);
3eafe507 7101 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
1da177e4
LT		 7102 struct TxDesc *txd = tp->TxDescArray + entry;
7103 void __iomem *ioaddr = tp->mmio_addr;
48addcc9 7104 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 7105 dma_addr_t mapping;
7106 u32 status, len;
2b7b4318 7107 u32 opts[2];
3eafe507 7108 int frags;
5b0384f4 7109
477206a0 7110 if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
bf82c189 7111 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
3eafe507 7112 goto err_stop_0;
1da177e4
LT		 7113 }
7114
7115 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3eafe507
SG		 7116 goto err_stop_0;
7117
b423e9ae 7118 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
7119 opts[0] = DescOwn;
7120
e974604b 7121 if (!tp->tso_csum(tp, skb, opts)) {
7122 r8169_csum_workaround(tp, skb);
7123 return NETDEV_TX_OK;
7124 }
b423e9ae 7125
3eafe507 7126 len = skb_headlen(skb);
48addcc9 7127 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
d827d86b
SG		 7128 if (unlikely(dma_mapping_error(d, mapping))) {
7129 if (net_ratelimit())
7130 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
3eafe507 7131 goto err_dma_0;
d827d86b 7132 }
3eafe507
SG		 7133
7134 tp->tx_skb[entry].len = len;
7135 txd->addr = cpu_to_le64(mapping);
1da177e4 7136
2b7b4318 7137 frags = rtl8169_xmit_frags(tp, skb, opts);
3eafe507
SG		 7138 if (frags < 0)
7139 goto err_dma_1;
7140 else if (frags)
2b7b4318 7141 opts[0] |= FirstFrag;
3eafe507 7142 else {
2b7b4318 7143 opts[0] |= FirstFrag | LastFrag;
1da177e4
LT		 7144 tp->tx_skb[entry].skb = skb;
7145 }
7146
2b7b4318
FR		 7147 txd->opts2 = cpu_to_le32(opts[1]);
7148
5047fb5d
RC		 7149 skb_tx_timestamp(skb);
7150
a0750138
AD		 7151 /* Force memory writes to complete before releasing descriptor */
7152 dma_wmb();
1da177e4 7153
cecb5fd7 7154 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318 7155 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 7156 txd->opts1 = cpu_to_le32(status);
7157
a0750138 7158 /* Force all memory writes to complete before notifying device */
4c020a96 7159 wmb();
1da177e4 7160
a0750138
AD		 7161 tp->cur_tx += frags + 1;
7162
87cda7cb 7163 RTL_W8(TxPoll, NPQ);
1da177e4 7164
87cda7cb 7165 mmiowb();
da78dbff 7166
87cda7cb 7167 if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
ae1f23fb
FR		 7168 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
7169 * not miss a ring update when it notices a stopped queue.
7170 */
7171 smp_wmb();
1da177e4 7172 netif_stop_queue(dev);
ae1f23fb
FR		 7173 /* Sync with rtl_tx:
7174 * - publish queue status and cur_tx ring index (write barrier)
7175 * - refresh dirty_tx ring index (read barrier).
7176 * May the current thread have a pessimistic view of the ring
7177 * status and forget to wake up queue, a racing rtl_tx thread
7178 * can't.
7179 */
1e874e04 7180 smp_mb();
477206a0 7181 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
1da177e4
LT		 7182 netif_wake_queue(dev);
7183 }
7184
61357325 7185 return NETDEV_TX_OK;
1da177e4 7186
3eafe507 7187err_dma_1:
48addcc9 7188 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
3eafe507 7189err_dma_0:
989c9ba1 7190 dev_kfree_skb_any(skb);
3eafe507
SG		 7191 dev->stats.tx_dropped++;
7192 return NETDEV_TX_OK;
7193
7194err_stop_0:
1da177e4 7195 netif_stop_queue(dev);
cebf8cc7 7196 dev->stats.tx_dropped++;
61357325 7197 return NETDEV_TX_BUSY;
1da177e4
LT		 7198}
7199
7200static void rtl8169_pcierr_interrupt(struct net_device *dev)
7201{
7202 struct rtl8169_private *tp = netdev_priv(dev);
7203 struct pci_dev *pdev = tp->pci_dev;
1da177e4
LT		 7204 u16 pci_status, pci_cmd;
7205
7206 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
7207 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
7208
bf82c189
JP		 7209 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
7210 pci_cmd, pci_status);
1da177e4
LT		 7211
7212 /*
7213 * The recovery sequence below admits a very elaborated explanation:
7214 * - it seems to work;
d03902b8
FR		 7215 * - I did not see what else could be done;
7216 * - it makes iop3xx happy.
1da177e4
LT		 7217 *
7218 * Feel free to adjust to your needs.
7219 */
a27993f3 7220 if (pdev->broken_parity_status)
d03902b8
FR		 7221 pci_cmd &= ~PCI_COMMAND_PARITY;
7222 else
7223 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
7224
7225 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 7226
7227 pci_write_config_word(pdev, PCI_STATUS,
7228 pci_status & (PCI_STATUS_DETECTED_PARITY |
7229 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
7230 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
7231
7232 /* The infamous DAC f*ckup only happens at boot time */
9fba0812 7233 if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
e6de30d6 7234 void __iomem *ioaddr = tp->mmio_addr;
7235
bf82c189 7236 netif_info(tp, intr, dev, "disabling PCI DAC\n");
1da177e4
LT		 7237 tp->cp_cmd &= ~PCIDAC;
7238 RTL_W16(CPlusCmd, tp->cp_cmd);
7239 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 7240 }
7241
e6de30d6 7242 rtl8169_hw_reset(tp);
d03902b8 7243
98ddf986 7244 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 7245}
7246
da78dbff 7247static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
1da177e4
LT		 7248{
7249 unsigned int dirty_tx, tx_left;
7250
1da177e4
LT		 7251 dirty_tx = tp->dirty_tx;
7252 smp_rmb();
7253 tx_left = tp->cur_tx - dirty_tx;
7254
7255 while (tx_left > 0) {
7256 unsigned int entry = dirty_tx % NUM_TX_DESC;
7257 struct ring_info *tx_skb = tp->tx_skb + entry;
1da177e4
LT		 7258 u32 status;
7259
1da177e4
LT		 7260 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
7261 if (status & DescOwn)
7262 break;
7263
a0750138
AD		 7264 /* This barrier is needed to keep us from reading
7265 * any other fields out of the Tx descriptor until
7266 * we know the status of DescOwn
7267 */
7268 dma_rmb();
7269
48addcc9
SG		 7270 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
7271 tp->TxDescArray + entry);
1da177e4 7272 if (status & LastFrag) {
87cda7cb
DM		 7273 u64_stats_update_begin(&tp->tx_stats.syncp);
7274 tp->tx_stats.packets++;
7275 tp->tx_stats.bytes += tx_skb->skb->len;
7276 u64_stats_update_end(&tp->tx_stats.syncp);
989c9ba1 7277 dev_kfree_skb_any(tx_skb->skb);
1da177e4
LT		 7278 tx_skb->skb = NULL;
7279 }
7280 dirty_tx++;
7281 tx_left--;
7282 }
7283
7284 if (tp->dirty_tx != dirty_tx) {
7285 tp->dirty_tx = dirty_tx;
ae1f23fb
FR		 7286 /* Sync with rtl8169_start_xmit:
7287 * - publish dirty_tx ring index (write barrier)
7288 * - refresh cur_tx ring index and queue status (read barrier)
7289 * May the current thread miss the stopped queue condition,
7290 * a racing xmit thread can only have a right view of the
7291 * ring status.
7292 */
1e874e04 7293 smp_mb();
1da177e4 7294 if (netif_queue_stopped(dev) &&
477206a0 7295 TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
1da177e4
LT		 7296 netif_wake_queue(dev);
7297 }
d78ae2dc
FR		 7298 /*
7299 * 8168 hack: TxPoll requests are lost when the Tx packets are
7300 * too close. Let's kick an extra TxPoll request when a burst
7301 * of start_xmit activity is detected (if it is not detected,
7302 * it is slow enough). -- FR
7303 */
da78dbff
FR		 7304 if (tp->cur_tx != dirty_tx) {
7305 void __iomem *ioaddr = tp->mmio_addr;
7306
d78ae2dc 7307 RTL_W8(TxPoll, NPQ);
da78dbff 7308 }
1da177e4
LT		 7309 }
7310}
7311
126fa4b9
FR		 7312static inline int rtl8169_fragmented_frame(u32 status)
7313{
7314 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
7315}
7316
adea1ac7 7317static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
1da177e4 7318{
1da177e4
LT		 7319 u32 status = opts1 & RxProtoMask;
7320
7321 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
d5d3ebe3 7322 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
1da177e4
LT		 7323 skb->ip_summed = CHECKSUM_UNNECESSARY;
7324 else
bc8acf2c 7325 skb_checksum_none_assert(skb);
1da177e4
LT		 7326}
7327
6f0333b8
ED		 7328static struct sk_buff *rtl8169_try_rx_copy(void *data,
7329 struct rtl8169_private *tp,
7330 int pkt_size,
7331 dma_addr_t addr)
1da177e4 7332{
b449655f 7333 struct sk_buff *skb;
48addcc9 7334 struct device *d = &tp->pci_dev->dev;
b449655f 7335
6f0333b8 7336 data = rtl8169_align(data);
48addcc9 7337 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6f0333b8 7338 prefetch(data);
e2338f86 7339 skb = napi_alloc_skb(&tp->napi, pkt_size);
6f0333b8
ED		 7340 if (skb)
7341 memcpy(skb->data, data, pkt_size);
48addcc9
SG		 7342 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
7343
6f0333b8 7344 return skb;
1da177e4
LT		 7345}
7346
da78dbff 7347static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
1da177e4
LT		 7348{
7349 unsigned int cur_rx, rx_left;
6f0333b8 7350 unsigned int count;
1da177e4 7351
1da177e4 7352 cur_rx = tp->cur_rx;
1da177e4 7353
9fba0812 7354 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
1da177e4 7355 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 7356 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 7357 u32 status;
7358
e03f33af 7359 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
1da177e4
LT		 7360 if (status & DescOwn)
7361 break;
a0750138
AD		 7362
7363 /* This barrier is needed to keep us from reading
7364 * any other fields out of the Rx descriptor until
7365 * we know the status of DescOwn
7366 */
7367 dma_rmb();
7368
4dcb7d33 7369 if (unlikely(status & RxRES)) {
bf82c189
JP		 7370 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
7371 status);
cebf8cc7 7372 dev->stats.rx_errors++;
1da177e4 7373 if (status & (RxRWT | RxRUNT))
cebf8cc7 7374 dev->stats.rx_length_errors++;
1da177e4 7375 if (status & RxCRC)
cebf8cc7 7376 dev->stats.rx_crc_errors++;
9dccf611 7377 if (status & RxFOVF) {
da78dbff 7378 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
cebf8cc7 7379 dev->stats.rx_fifo_errors++;
9dccf611 7380 }
6bbe021d
BG		 7381 if ((status & (RxRUNT | RxCRC)) &&
7382 !(status & (RxRWT | RxFOVF)) &&
7383 (dev->features & NETIF_F_RXALL))
7384 goto process_pkt;
1da177e4 7385 } else {
6f0333b8 7386 struct sk_buff *skb;
6bbe021d
BG		 7387 dma_addr_t addr;
7388 int pkt_size;
7389
7390process_pkt:
7391 addr = le64_to_cpu(desc->addr);
79d0c1d2
BG		 7392 if (likely(!(dev->features & NETIF_F_RXFCS)))
7393 pkt_size = (status & 0x00003fff) - 4;
7394 else
7395 pkt_size = status & 0x00003fff;
1da177e4 7396
126fa4b9
FR		 7397 /*
7398 * The driver does not support incoming fragmented
7399 * frames. They are seen as a symptom of over-mtu
7400 * sized frames.
7401 */
7402 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 7403 dev->stats.rx_dropped++;
7404 dev->stats.rx_length_errors++;
ce11ff5e 7405 goto release_descriptor;
126fa4b9
FR		 7406 }
7407
6f0333b8
ED		 7408 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
7409 tp, pkt_size, addr);
6f0333b8
ED		 7410 if (!skb) {
7411 dev->stats.rx_dropped++;
ce11ff5e 7412 goto release_descriptor;
1da177e4
LT		 7413 }
7414
adea1ac7 7415 rtl8169_rx_csum(skb, status);
1da177e4
LT		 7416 skb_put(skb, pkt_size);
7417 skb->protocol = eth_type_trans(skb, dev);
7418
7a8fc77b
FR		 7419 rtl8169_rx_vlan_tag(desc, skb);
7420
39174291 7421 if (skb->pkt_type == PACKET_MULTICAST)
7422 dev->stats.multicast++;
7423
56de414c 7424 napi_gro_receive(&tp->napi, skb);
1da177e4 7425
8027aa24
JW		 7426 u64_stats_update_begin(&tp->rx_stats.syncp);
7427 tp->rx_stats.packets++;
7428 tp->rx_stats.bytes += pkt_size;
7429 u64_stats_update_end(&tp->rx_stats.syncp);
1da177e4 7430 }
ce11ff5e 7431release_descriptor:
7432 desc->opts2 = 0;
ce11ff5e 7433 rtl8169_mark_to_asic(desc, rx_buf_sz);
1da177e4
LT		 7434 }
7435
7436 count = cur_rx - tp->cur_rx;
7437 tp->cur_rx = cur_rx;
7438
1da177e4
LT		 7439 return count;
7440}
7441
07d3f51f 7442static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 7443{
07d3f51f 7444 struct net_device *dev = dev_instance;
1da177e4 7445 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 7446 int handled = 0;
9085cdfa 7447 u16 status;
1da177e4 7448
9085cdfa 7449 status = rtl_get_events(tp);
da78dbff
FR		 7450 if (status && status != 0xffff) {
7451 status &= RTL_EVENT_NAPI | tp->event_slow;
7452 if (status) {
7453 handled = 1;
1da177e4 7454
da78dbff
FR		 7455 rtl_irq_disable(tp);
7456 napi_schedule(&tp->napi);
f11a377b 7457 }
da78dbff
FR		 7458 }
7459 return IRQ_RETVAL(handled);
7460}
1da177e4 7461
da78dbff
FR		 7462/*
7463 * Workqueue context.
7464 */
7465static void rtl_slow_event_work(struct rtl8169_private *tp)
7466{
7467 struct net_device *dev = tp->dev;
7468 u16 status;
7469
7470 status = rtl_get_events(tp) & tp->event_slow;
7471 rtl_ack_events(tp, status);
1da177e4 7472
da78dbff
FR		 7473 if (unlikely(status & RxFIFOOver)) {
7474 switch (tp->mac_version) {
7475 /* Work around for rx fifo overflow */
7476 case RTL_GIGA_MAC_VER_11:
7477 netif_stop_queue(dev);
934714d0
FR		 7478 /* XXX - Hack alert. See rtl_task(). */
7479 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
da78dbff 7480 default:
f11a377b
DD		 7481 break;
7482 }
da78dbff 7483 }
1da177e4 7484
da78dbff
FR		 7485 if (unlikely(status & SYSErr))
7486 rtl8169_pcierr_interrupt(dev);
0e485150 7487
da78dbff
FR		 7488 if (status & LinkChg)
7489 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
1da177e4 7490
7dbb4918 7491 rtl_irq_enable_all(tp);
1da177e4
LT		 7492}
7493
4422bcd4
FR		 7494static void rtl_task(struct work_struct *work)
7495{
da78dbff
FR		 7496 static const struct {
7497 int bitnr;
7498 void (*action)(struct rtl8169_private *);
7499 } rtl_work[] = {
934714d0 7500 /* XXX - keep rtl_slow_event_work() as first element. */
da78dbff
FR		 7501 { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work },
7502 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
7503 { RTL_FLAG_TASK_PHY_PENDING, rtl_phy_work }
7504 };
4422bcd4
FR		 7505 struct rtl8169_private *tp =
7506 container_of(work, struct rtl8169_private, wk.work);
da78dbff
FR		 7507 struct net_device *dev = tp->dev;
7508 int i;
7509
7510 rtl_lock_work(tp);
7511
6c4a70c5
FR		 7512 if (!netif_running(dev) ||
7513 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
da78dbff
FR		 7514 goto out_unlock;
7515
7516 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
7517 bool pending;
7518
da78dbff 7519 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
da78dbff
FR		 7520 if (pending)
7521 rtl_work[i].action(tp);
7522 }
4422bcd4 7523
da78dbff
FR		 7524out_unlock:
7525 rtl_unlock_work(tp);
4422bcd4
FR		 7526}
7527
bea3348e 7528static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 7529{
bea3348e
SH		 7530 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
7531 struct net_device *dev = tp->dev;
da78dbff
FR		 7532 u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
7533 int work_done= 0;
7534 u16 status;
7535
7536 status = rtl_get_events(tp);
7537 rtl_ack_events(tp, status & ~tp->event_slow);
7538
7539 if (status & RTL_EVENT_NAPI_RX)
7540 work_done = rtl_rx(dev, tp, (u32) budget);
7541
7542 if (status & RTL_EVENT_NAPI_TX)
7543 rtl_tx(dev, tp);
1da177e4 7544
da78dbff
FR		 7545 if (status & tp->event_slow) {
7546 enable_mask &= ~tp->event_slow;
7547
7548 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
7549 }
1da177e4 7550
bea3348e 7551 if (work_done < budget) {
288379f0 7552 napi_complete(napi);
f11a377b 7553
da78dbff
FR		 7554 rtl_irq_enable(tp, enable_mask);
7555 mmiowb();
1da177e4
LT		 7556 }
7557
bea3348e 7558 return work_done;
1da177e4 7559}
1da177e4 7560
523a6094
FR		 7561static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
7562{
7563 struct rtl8169_private *tp = netdev_priv(dev);
7564
7565 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
7566 return;
7567
7568 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
7569 RTL_W32(RxMissed, 0);
7570}
7571
1da177e4
LT		 7572static void rtl8169_down(struct net_device *dev)
7573{
7574 struct rtl8169_private *tp = netdev_priv(dev);
7575 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 7576
4876cc1e 7577 del_timer_sync(&tp->timer);
1da177e4 7578
93dd79e8 7579 napi_disable(&tp->napi);
da78dbff 7580 netif_stop_queue(dev);
1da177e4 7581
92fc43b4 7582 rtl8169_hw_reset(tp);
323bb685
SG		 7583 /*
7584 * At this point device interrupts can not be enabled in any function,
209e5ac8
FR		 7585 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
7586 * and napi is disabled (rtl8169_poll).
323bb685 7587 */
523a6094 7588 rtl8169_rx_missed(dev, ioaddr);
1da177e4 7589
1da177e4 7590 /* Give a racing hard_start_xmit a few cycles to complete. */
da78dbff 7591 synchronize_sched();
1da177e4 7592
1da177e4
LT		 7593 rtl8169_tx_clear(tp);
7594
7595 rtl8169_rx_clear(tp);
065c27c1 7596
7597 rtl_pll_power_down(tp);
1da177e4
LT		 7598}
7599
7600static int rtl8169_close(struct net_device *dev)
7601{
7602 struct rtl8169_private *tp = netdev_priv(dev);
7603 struct pci_dev *pdev = tp->pci_dev;
7604
e1759441
RW		 7605 pm_runtime_get_sync(&pdev->dev);
7606
cecb5fd7 7607 /* Update counters before going down */
355423d0
IV		 7608 rtl8169_update_counters(dev);
7609
da78dbff 7610 rtl_lock_work(tp);
6c4a70c5 7611 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
da78dbff 7612
1da177e4 7613 rtl8169_down(dev);
da78dbff 7614 rtl_unlock_work(tp);
1da177e4 7615
4ea72445
L		 7616 cancel_work_sync(&tp->wk.work);
7617
92a7c4e7 7618 free_irq(pdev->irq, dev);
1da177e4 7619
82553bb6
SG		 7620 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7621 tp->RxPhyAddr);
7622 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7623 tp->TxPhyAddr);
1da177e4
LT		 7624 tp->TxDescArray = NULL;
7625 tp->RxDescArray = NULL;
7626
e1759441
RW		 7627 pm_runtime_put_sync(&pdev->dev);
7628
1da177e4
LT		 7629 return 0;
7630}
7631
dc1c00ce
FR		 7632#ifdef CONFIG_NET_POLL_CONTROLLER
7633static void rtl8169_netpoll(struct net_device *dev)
7634{
7635 struct rtl8169_private *tp = netdev_priv(dev);
7636
7637 rtl8169_interrupt(tp->pci_dev->irq, dev);
7638}
7639#endif
7640
df43ac78
FR		 7641static int rtl_open(struct net_device *dev)
7642{
7643 struct rtl8169_private *tp = netdev_priv(dev);
7644 void __iomem *ioaddr = tp->mmio_addr;
7645 struct pci_dev *pdev = tp->pci_dev;
7646 int retval = -ENOMEM;
7647
7648 pm_runtime_get_sync(&pdev->dev);
7649
7650 /*
e75d6606 7651 * Rx and Tx descriptors needs 256 bytes alignment.
df43ac78
FR		 7652 * dma_alloc_coherent provides more.
7653 */
7654 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
7655 &tp->TxPhyAddr, GFP_KERNEL);
7656 if (!tp->TxDescArray)
7657 goto err_pm_runtime_put;
7658
7659 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
7660 &tp->RxPhyAddr, GFP_KERNEL);
7661 if (!tp->RxDescArray)
7662 goto err_free_tx_0;
7663
7664 retval = rtl8169_init_ring(dev);
7665 if (retval < 0)
7666 goto err_free_rx_1;
7667
7668 INIT_WORK(&tp->wk.work, rtl_task);
7669
7670 smp_mb();
7671
7672 rtl_request_firmware(tp);
7673
92a7c4e7 7674 retval = request_irq(pdev->irq, rtl8169_interrupt,
df43ac78
FR		 7675 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
7676 dev->name, dev);
7677 if (retval < 0)
7678 goto err_release_fw_2;
7679
7680 rtl_lock_work(tp);
7681
7682 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7683
7684 napi_enable(&tp->napi);
7685
7686 rtl8169_init_phy(dev, tp);
7687
7688 __rtl8169_set_features(dev, dev->features);
7689
7690 rtl_pll_power_up(tp);
7691
7692 rtl_hw_start(dev);
7693
6e85d5ad
CV		 7694 if (!rtl8169_init_counter_offsets(dev))
7695 netif_warn(tp, hw, dev, "counter reset/update failed\n");
7696
df43ac78
FR		 7697 netif_start_queue(dev);
7698
7699 rtl_unlock_work(tp);
7700
7701 tp->saved_wolopts = 0;
7702 pm_runtime_put_noidle(&pdev->dev);
7703
7704 rtl8169_check_link_status(dev, tp, ioaddr);
7705out:
7706 return retval;
7707
7708err_release_fw_2:
7709 rtl_release_firmware(tp);
7710 rtl8169_rx_clear(tp);
7711err_free_rx_1:
7712 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7713 tp->RxPhyAddr);
7714 tp->RxDescArray = NULL;
7715err_free_tx_0:
7716 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7717 tp->TxPhyAddr);
7718 tp->TxDescArray = NULL;
7719err_pm_runtime_put:
7720 pm_runtime_put_noidle(&pdev->dev);
7721 goto out;
7722}
7723
8027aa24
JW		 7724static struct rtnl_link_stats64 *
7725rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
1da177e4
LT		 7726{
7727 struct rtl8169_private *tp = netdev_priv(dev);
7728 void __iomem *ioaddr = tp->mmio_addr;
f09cf4b7 7729 struct pci_dev *pdev = tp->pci_dev;
42020320 7730 struct rtl8169_counters *counters = tp->counters;
8027aa24 7731 unsigned int start;
1da177e4 7732
f09cf4b7
CHL		 7733 pm_runtime_get_noresume(&pdev->dev);
7734
7735 if (netif_running(dev) && pm_runtime_active(&pdev->dev))
523a6094 7736 rtl8169_rx_missed(dev, ioaddr);
5b0384f4 7737
8027aa24 7738 do {
57a7744e 7739 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
8027aa24
JW		 7740 stats->rx_packets = tp->rx_stats.packets;
7741 stats->rx_bytes = tp->rx_stats.bytes;
57a7744e 7742 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
8027aa24 7743
8027aa24 7744 do {
57a7744e 7745 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
8027aa24
JW		 7746 stats->tx_packets = tp->tx_stats.packets;
7747 stats->tx_bytes = tp->tx_stats.bytes;
57a7744e 7748 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
8027aa24
JW		 7749
7750 stats->rx_dropped = dev->stats.rx_dropped;
7751 stats->tx_dropped = dev->stats.tx_dropped;
7752 stats->rx_length_errors = dev->stats.rx_length_errors;
7753 stats->rx_errors = dev->stats.rx_errors;
7754 stats->rx_crc_errors = dev->stats.rx_crc_errors;
7755 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
7756 stats->rx_missed_errors = dev->stats.rx_missed_errors;
d7d2d89d 7757 stats->multicast = dev->stats.multicast;
8027aa24 7758
6e85d5ad
CV		 7759 /*
7760 * Fetch additonal counter values missing in stats collected by driver
7761 * from tally counters.
7762 */
f09cf4b7
CHL		 7763 if (pm_runtime_active(&pdev->dev))
7764 rtl8169_update_counters(dev);
6e85d5ad
CV		 7765
7766 /*
7767 * Subtract values fetched during initalization.
7768 * See rtl8169_init_counter_offsets for a description why we do that.
7769 */
42020320 7770 stats->tx_errors = le64_to_cpu(counters->tx_errors) -
6e85d5ad 7771 le64_to_cpu(tp->tc_offset.tx_errors);
42020320 7772 stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
6e85d5ad 7773 le32_to_cpu(tp->tc_offset.tx_multi_collision);
42020320 7774 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
6e85d5ad
CV		 7775 le16_to_cpu(tp->tc_offset.tx_aborted);
7776
f09cf4b7
CHL		 7777 pm_runtime_put_noidle(&pdev->dev);
7778
8027aa24 7779 return stats;
1da177e4
LT		 7780}
7781
861ab440 7782static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 7783{
065c27c1 7784 struct rtl8169_private *tp = netdev_priv(dev);
7785
5d06a99f 7786 if (!netif_running(dev))
861ab440 7787 return;
5d06a99f
FR		 7788
7789 netif_device_detach(dev);
7790 netif_stop_queue(dev);
da78dbff
FR		 7791
7792 rtl_lock_work(tp);
7793 napi_disable(&tp->napi);
6c4a70c5 7794 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
da78dbff
FR		 7795 rtl_unlock_work(tp);
7796
7797 rtl_pll_power_down(tp);
861ab440
RW		 7798}
7799
7800#ifdef CONFIG_PM
7801
7802static int rtl8169_suspend(struct device *device)
7803{
7804 struct pci_dev *pdev = to_pci_dev(device);
7805 struct net_device *dev = pci_get_drvdata(pdev);
5d06a99f 7806
861ab440 7807 rtl8169_net_suspend(dev);
1371fa6d 7808
5d06a99f
FR		 7809 return 0;
7810}
7811
e1759441
RW		 7812static void __rtl8169_resume(struct net_device *dev)
7813{
065c27c1 7814 struct rtl8169_private *tp = netdev_priv(dev);
7815
e1759441 7816 netif_device_attach(dev);
065c27c1 7817
7818 rtl_pll_power_up(tp);
7819
cff4c162
AS		 7820 rtl_lock_work(tp);
7821 napi_enable(&tp->napi);
6c4a70c5 7822 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
cff4c162 7823 rtl_unlock_work(tp);
da78dbff 7824
98ddf986 7825 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
e1759441
RW		 7826}
7827
861ab440 7828static int rtl8169_resume(struct device *device)
5d06a99f 7829{
861ab440 7830 struct pci_dev *pdev = to_pci_dev(device);
5d06a99f 7831 struct net_device *dev = pci_get_drvdata(pdev);
fccec10b
SG		 7832 struct rtl8169_private *tp = netdev_priv(dev);
7833
7834 rtl8169_init_phy(dev, tp);
5d06a99f 7835
e1759441
RW		 7836 if (netif_running(dev))
7837 __rtl8169_resume(dev);
5d06a99f 7838
e1759441
RW		 7839 return 0;
7840}
7841
7842static int rtl8169_runtime_suspend(struct device *device)
7843{
7844 struct pci_dev *pdev = to_pci_dev(device);
7845 struct net_device *dev = pci_get_drvdata(pdev);
7846 struct rtl8169_private *tp = netdev_priv(dev);
7847
7848 if (!tp->TxDescArray)
7849 return 0;
7850
da78dbff 7851 rtl_lock_work(tp);
e1759441
RW		 7852 tp->saved_wolopts = __rtl8169_get_wol(tp);
7853 __rtl8169_set_wol(tp, WAKE_ANY);
da78dbff 7854 rtl_unlock_work(tp);
e1759441
RW		 7855
7856 rtl8169_net_suspend(dev);
7857
f09cf4b7
CHL		 7858 /* Update counters before going runtime suspend */
7859 rtl8169_rx_missed(dev, tp->mmio_addr);
7860 rtl8169_update_counters(dev);
7861
e1759441
RW		 7862 return 0;
7863}
7864
7865static int rtl8169_runtime_resume(struct device *device)
7866{
7867 struct pci_dev *pdev = to_pci_dev(device);
7868 struct net_device *dev = pci_get_drvdata(pdev);
7869 struct rtl8169_private *tp = netdev_priv(dev);
7870
7871 if (!tp->TxDescArray)
7872 return 0;
7873
da78dbff 7874 rtl_lock_work(tp);
e1759441
RW		 7875 __rtl8169_set_wol(tp, tp->saved_wolopts);
7876 tp->saved_wolopts = 0;
da78dbff 7877 rtl_unlock_work(tp);
e1759441 7878
fccec10b
SG		 7879 rtl8169_init_phy(dev, tp);
7880
e1759441 7881 __rtl8169_resume(dev);
5d06a99f 7882
5d06a99f
FR		 7883 return 0;
7884}
7885
e1759441
RW		 7886static int rtl8169_runtime_idle(struct device *device)
7887{
7888 struct pci_dev *pdev = to_pci_dev(device);
7889 struct net_device *dev = pci_get_drvdata(pdev);
7890 struct rtl8169_private *tp = netdev_priv(dev);
7891
e4fbce74 7892 return tp->TxDescArray ? -EBUSY : 0;
e1759441
RW		 7893}
7894
47145210 7895static const struct dev_pm_ops rtl8169_pm_ops = {
cecb5fd7
FR		 7896 .suspend = rtl8169_suspend,
7897 .resume = rtl8169_resume,
7898 .freeze = rtl8169_suspend,
7899 .thaw = rtl8169_resume,
7900 .poweroff = rtl8169_suspend,
7901 .restore = rtl8169_resume,
7902 .runtime_suspend = rtl8169_runtime_suspend,
7903 .runtime_resume = rtl8169_runtime_resume,
7904 .runtime_idle = rtl8169_runtime_idle,
861ab440
RW		 7905};
7906
7907#define RTL8169_PM_OPS (&rtl8169_pm_ops)
7908
7909#else /* !CONFIG_PM */
7910
7911#define RTL8169_PM_OPS NULL
7912
7913#endif /* !CONFIG_PM */
7914
649b3b8c 7915static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
7916{
7917 void __iomem *ioaddr = tp->mmio_addr;
7918
7919 /* WoL fails with 8168b when the receiver is disabled. */
7920 switch (tp->mac_version) {
7921 case RTL_GIGA_MAC_VER_11:
7922 case RTL_GIGA_MAC_VER_12:
7923 case RTL_GIGA_MAC_VER_17:
7924 pci_clear_master(tp->pci_dev);
7925
7926 RTL_W8(ChipCmd, CmdRxEnb);
7927 /* PCI commit */
7928 RTL_R8(ChipCmd);
7929 break;
7930 default:
7931 break;
7932 }
7933}
7934
1765f95d
FR		 7935static void rtl_shutdown(struct pci_dev *pdev)
7936{
861ab440 7937 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 7938 struct rtl8169_private *tp = netdev_priv(dev);
2a15cd2f 7939 struct device *d = &pdev->dev;
7940
7941 pm_runtime_get_sync(d);
861ab440
RW		 7942
7943 rtl8169_net_suspend(dev);
1765f95d 7944
cecb5fd7 7945 /* Restore original MAC address */
cc098dc7
IV		 7946 rtl_rar_set(tp, dev->perm_addr);
7947
92fc43b4 7948 rtl8169_hw_reset(tp);
4bb3f522 7949
861ab440 7950 if (system_state == SYSTEM_POWER_OFF) {
649b3b8c 7951 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
7952 rtl_wol_suspend_quirk(tp);
7953 rtl_wol_shutdown_quirk(tp);
ca52efd5 7954 }
7955
861ab440
RW		 7956 pci_wake_from_d3(pdev, true);
7957 pci_set_power_state(pdev, PCI_D3hot);
7958 }
2a15cd2f 7959
7960 pm_runtime_put_noidle(d);
861ab440 7961}
5d06a99f 7962
baf63293 7963static void rtl_remove_one(struct pci_dev *pdev)
e27566ed
FR		 7964{
7965 struct net_device *dev = pci_get_drvdata(pdev);
7966 struct rtl8169_private *tp = netdev_priv(dev);
7967
ee7a1beb
CHL		 7968 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
7969 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
935e2218
CHL		 7970 tp->mac_version == RTL_GIGA_MAC_VER_31 ||
7971 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
7972 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
7973 tp->mac_version == RTL_GIGA_MAC_VER_51) &&
ee7a1beb 7974 r8168_check_dash(tp)) {
e27566ed
FR		 7975 rtl8168_driver_stop(tp);
7976 }
7977
ad1be8d3
DN		 7978 netif_napi_del(&tp->napi);
7979
e27566ed
FR		 7980 unregister_netdev(dev);
7981
42020320
CV		 7982 dma_free_coherent(&tp->pci_dev->dev, sizeof(*tp->counters),
7983 tp->counters, tp->counters_phys_addr);
7984
e27566ed
FR		 7985 rtl_release_firmware(tp);
7986
7987 if (pci_dev_run_wake(pdev))
7988 pm_runtime_get_noresume(&pdev->dev);
7989
7990 /* restore original MAC address */
7991 rtl_rar_set(tp, dev->perm_addr);
7992
7993 rtl_disable_msi(pdev, tp);
7994 rtl8169_release_board(pdev, dev, tp->mmio_addr);
e27566ed
FR		 7995}
7996
fa9c385e 7997static const struct net_device_ops rtl_netdev_ops = {
df43ac78 7998 .ndo_open = rtl_open,
fa9c385e
FR		 7999 .ndo_stop = rtl8169_close,
8000 .ndo_get_stats64 = rtl8169_get_stats64,
8001 .ndo_start_xmit = rtl8169_start_xmit,
8002 .ndo_tx_timeout = rtl8169_tx_timeout,
8003 .ndo_validate_addr = eth_validate_addr,
8004 .ndo_change_mtu = rtl8169_change_mtu,
8005 .ndo_fix_features = rtl8169_fix_features,
8006 .ndo_set_features = rtl8169_set_features,
8007 .ndo_set_mac_address = rtl_set_mac_address,
8008 .ndo_do_ioctl = rtl8169_ioctl,
8009 .ndo_set_rx_mode = rtl_set_rx_mode,
8010#ifdef CONFIG_NET_POLL_CONTROLLER
8011 .ndo_poll_controller = rtl8169_netpoll,
8012#endif
8013
8014};
8015
31fa8b18
FR		 8016static const struct rtl_cfg_info {
8017 void (*hw_start)(struct net_device *);
8018 unsigned int region;
8019 unsigned int align;
8020 u16 event_slow;
8021 unsigned features;
8022 u8 default_ver;
8023} rtl_cfg_infos [] = {
8024 [RTL_CFG_0] = {
8025 .hw_start = rtl_hw_start_8169,
8026 .region = 1,
8027 .align = 0,
8028 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
8029 .features = RTL_FEATURE_GMII,
8030 .default_ver = RTL_GIGA_MAC_VER_01,
8031 },
8032 [RTL_CFG_1] = {
8033 .hw_start = rtl_hw_start_8168,
8034 .region = 2,
8035 .align = 8,
8036 .event_slow = SYSErr | LinkChg | RxOverflow,
8037 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
8038 .default_ver = RTL_GIGA_MAC_VER_11,
8039 },
8040 [RTL_CFG_2] = {
8041 .hw_start = rtl_hw_start_8101,
8042 .region = 2,
8043 .align = 8,
8044 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
8045 PCSTimeout,
8046 .features = RTL_FEATURE_MSI,
8047 .default_ver = RTL_GIGA_MAC_VER_13,
8048 }
8049};
8050
8051/* Cfg9346_Unlock assumed. */
8052static unsigned rtl_try_msi(struct rtl8169_private *tp,
8053 const struct rtl_cfg_info *cfg)
8054{
8055 void __iomem *ioaddr = tp->mmio_addr;
8056 unsigned msi = 0;
8057 u8 cfg2;
8058
8059 cfg2 = RTL_R8(Config2) & ~MSIEnable;
8060 if (cfg->features & RTL_FEATURE_MSI) {
8061 if (pci_enable_msi(tp->pci_dev)) {
8062 netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
8063 } else {
8064 cfg2 |= MSIEnable;
8065 msi = RTL_FEATURE_MSI;
8066 }
8067 }
8068 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
8069 RTL_W8(Config2, cfg2);
8070 return msi;
8071}
8072
c558386b
HW		 8073DECLARE_RTL_COND(rtl_link_list_ready_cond)
8074{
8075 void __iomem *ioaddr = tp->mmio_addr;
8076
8077 return RTL_R8(MCU) & LINK_LIST_RDY;
8078}
8079
8080DECLARE_RTL_COND(rtl_rxtx_empty_cond)
8081{
8082 void __iomem *ioaddr = tp->mmio_addr;
8083
8084 return (RTL_R8(MCU) & RXTX_EMPTY) == RXTX_EMPTY;
8085}
8086
baf63293 8087static void rtl_hw_init_8168g(struct rtl8169_private *tp)
c558386b
HW		 8088{
8089 void __iomem *ioaddr = tp->mmio_addr;
8090 u32 data;
8091
8092 tp->ocp_base = OCP_STD_PHY_BASE;
8093
8094 RTL_W32(MISC, RTL_R32(MISC) | RXDV_GATED_EN);
8095
8096 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
8097 return;
8098
8099 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
8100 return;
8101
8102 RTL_W8(ChipCmd, RTL_R8(ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
8103 msleep(1);
8104 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
8105
5f8bcce9 8106 data = r8168_mac_ocp_read(tp, 0xe8de);
c558386b
HW		 8107 data &= ~(1 << 14);
8108 r8168_mac_ocp_write(tp, 0xe8de, data);
8109
8110 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
8111 return;
8112
5f8bcce9 8113 data = r8168_mac_ocp_read(tp, 0xe8de);
c558386b
HW		 8114 data |= (1 << 15);
8115 r8168_mac_ocp_write(tp, 0xe8de, data);
8116
8117 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
8118 return;
8119}
8120
003609da
CHL		 8121static void rtl_hw_init_8168ep(struct rtl8169_private *tp)
8122{
8123 rtl8168ep_stop_cmac(tp);
8124 rtl_hw_init_8168g(tp);
8125}
8126
baf63293 8127static void rtl_hw_initialize(struct rtl8169_private *tp)
c558386b
HW		 8128{
8129 switch (tp->mac_version) {
8130 case RTL_GIGA_MAC_VER_40:
8131 case RTL_GIGA_MAC_VER_41:
57538c4a 8132 case RTL_GIGA_MAC_VER_42:
58152cd4 8133 case RTL_GIGA_MAC_VER_43:
45dd95c4 8134 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 8135 case RTL_GIGA_MAC_VER_45:
8136 case RTL_GIGA_MAC_VER_46:
8137 case RTL_GIGA_MAC_VER_47:
8138 case RTL_GIGA_MAC_VER_48:
003609da
CHL		 8139 rtl_hw_init_8168g(tp);
8140 break;
935e2218
CHL		 8141 case RTL_GIGA_MAC_VER_49:
8142 case RTL_GIGA_MAC_VER_50:
8143 case RTL_GIGA_MAC_VER_51:
003609da 8144 rtl_hw_init_8168ep(tp);
c558386b 8145 break;
c558386b
HW		 8146 default:
8147 break;
8148 }
8149}
8150
929a031d 8151static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3b6cf25d
FR		 8152{
8153 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
8154 const unsigned int region = cfg->region;
8155 struct rtl8169_private *tp;
8156 struct mii_if_info *mii;
8157 struct net_device *dev;
8158 void __iomem *ioaddr;
8159 int chipset, i;
8160 int rc;
8161
8162 if (netif_msg_drv(&debug)) {
8163 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
8164 MODULENAME, RTL8169_VERSION);
8165 }
8166
8167 dev = alloc_etherdev(sizeof (*tp));
8168 if (!dev) {
8169 rc = -ENOMEM;
8170 goto out;
8171 }
8172
8173 SET_NETDEV_DEV(dev, &pdev->dev);
fa9c385e 8174 dev->netdev_ops = &rtl_netdev_ops;
3b6cf25d
FR		 8175 tp = netdev_priv(dev);
8176 tp->dev = dev;
8177 tp->pci_dev = pdev;
8178 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
8179
8180 mii = &tp->mii;
8181 mii->dev = dev;
8182 mii->mdio_read = rtl_mdio_read;
8183 mii->mdio_write = rtl_mdio_write;
8184 mii->phy_id_mask = 0x1f;
8185 mii->reg_num_mask = 0x1f;
8186 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
8187
8188 /* disable ASPM completely as that cause random device stop working
8189 * problems as well as full system hangs for some PCIe devices users */
8190 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
8191 PCIE_LINK_STATE_CLKPM);
8192
8193 /* enable device (incl. PCI PM wakeup and hotplug setup) */
8194 rc = pci_enable_device(pdev);
8195 if (rc < 0) {
8196 netif_err(tp, probe, dev, "enable failure\n");
8197 goto err_out_free_dev_1;
8198 }
8199
8200 if (pci_set_mwi(pdev) < 0)
8201 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
8202
8203 /* make sure PCI base addr 1 is MMIO */
8204 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
8205 netif_err(tp, probe, dev,
8206 "region #%d not an MMIO resource, aborting\n",
8207 region);
8208 rc = -ENODEV;
8209 goto err_out_mwi_2;
8210 }
8211
8212 /* check for weird/broken PCI region reporting */
8213 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
8214 netif_err(tp, probe, dev,
8215 "Invalid PCI region size(s), aborting\n");
8216 rc = -ENODEV;
8217 goto err_out_mwi_2;
8218 }
8219
8220 rc = pci_request_regions(pdev, MODULENAME);
8221 if (rc < 0) {
8222 netif_err(tp, probe, dev, "could not request regions\n");
8223 goto err_out_mwi_2;
8224 }
8225
929a031d 8226 tp->cp_cmd = 0;
3b6cf25d
FR		 8227
8228 if ((sizeof(dma_addr_t) > 4) &&
8229 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
8230 tp->cp_cmd |= PCIDAC;
8231 dev->features |= NETIF_F_HIGHDMA;
8232 } else {
8233 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
8234 if (rc < 0) {
8235 netif_err(tp, probe, dev, "DMA configuration failed\n");
8236 goto err_out_free_res_3;
8237 }
8238 }
8239
8240 /* ioremap MMIO region */
8241 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
8242 if (!ioaddr) {
8243 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
8244 rc = -EIO;
8245 goto err_out_free_res_3;
8246 }
8247 tp->mmio_addr = ioaddr;
8248
8249 if (!pci_is_pcie(pdev))
8250 netif_info(tp, probe, dev, "not PCI Express\n");
8251
8252 /* Identify chip attached to board */
8253 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
8254
8255 rtl_init_rxcfg(tp);
8256
8257 rtl_irq_disable(tp);
8258
c558386b
HW		 8259 rtl_hw_initialize(tp);
8260
3b6cf25d
FR		 8261 rtl_hw_reset(tp);
8262
8263 rtl_ack_events(tp, 0xffff);
8264
8265 pci_set_master(pdev);
8266
3b6cf25d
FR		 8267 rtl_init_mdio_ops(tp);
8268 rtl_init_pll_power_ops(tp);
8269 rtl_init_jumbo_ops(tp);
beb1fe18 8270 rtl_init_csi_ops(tp);
3b6cf25d
FR		 8271
8272 rtl8169_print_mac_version(tp);
8273
8274 chipset = tp->mac_version;
8275 tp->txd_version = rtl_chip_infos[chipset].txd_version;
8276
8277 RTL_W8(Cfg9346, Cfg9346_Unlock);
8278 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
8f9d5138 8279 RTL_W8(Config5, RTL_R8(Config5) & (BWF | MWF | UWF | LanWake | PMEStatus));
6e1d0b89 8280 switch (tp->mac_version) {
ac85bcdb
CHL		 8281 case RTL_GIGA_MAC_VER_34:
8282 case RTL_GIGA_MAC_VER_35:
8283 case RTL_GIGA_MAC_VER_36:
8284 case RTL_GIGA_MAC_VER_37:
8285 case RTL_GIGA_MAC_VER_38:
8286 case RTL_GIGA_MAC_VER_40:
8287 case RTL_GIGA_MAC_VER_41:
8288 case RTL_GIGA_MAC_VER_42:
8289 case RTL_GIGA_MAC_VER_43:
8290 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 8291 case RTL_GIGA_MAC_VER_45:
8292 case RTL_GIGA_MAC_VER_46:
ac85bcdb
CHL		 8293 case RTL_GIGA_MAC_VER_47:
8294 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 8295 case RTL_GIGA_MAC_VER_49:
8296 case RTL_GIGA_MAC_VER_50:
8297 case RTL_GIGA_MAC_VER_51:
6e1d0b89
CHL		 8298 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
8299 tp->features |= RTL_FEATURE_WOL;
8300 if ((RTL_R8(Config3) & LinkUp) != 0)
8301 tp->features |= RTL_FEATURE_WOL;
8302 break;
8303 default:
8304 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
8305 tp->features |= RTL_FEATURE_WOL;
8306 break;
8307 }
3b6cf25d
FR		 8308 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
8309 tp->features |= RTL_FEATURE_WOL;
8310 tp->features |= rtl_try_msi(tp, cfg);
8311 RTL_W8(Cfg9346, Cfg9346_Lock);
8312
8313 if (rtl_tbi_enabled(tp)) {
8314 tp->set_speed = rtl8169_set_speed_tbi;
8315 tp->get_settings = rtl8169_gset_tbi;
8316 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
8317 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
8318 tp->link_ok = rtl8169_tbi_link_ok;
8319 tp->do_ioctl = rtl_tbi_ioctl;
8320 } else {
8321 tp->set_speed = rtl8169_set_speed_xmii;
8322 tp->get_settings = rtl8169_gset_xmii;
8323 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
8324 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
8325 tp->link_ok = rtl8169_xmii_link_ok;
8326 tp->do_ioctl = rtl_xmii_ioctl;
8327 }
8328
8329 mutex_init(&tp->wk.mutex);
340fea3d
KM		 8330 u64_stats_init(&tp->rx_stats.syncp);
8331 u64_stats_init(&tp->tx_stats.syncp);
3b6cf25d
FR		 8332
8333 /* Get MAC address */
89cceb27
CHL		 8334 if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
8335 tp->mac_version == RTL_GIGA_MAC_VER_36 ||
8336 tp->mac_version == RTL_GIGA_MAC_VER_37 ||
8337 tp->mac_version == RTL_GIGA_MAC_VER_38 ||
8338 tp->mac_version == RTL_GIGA_MAC_VER_40 ||
8339 tp->mac_version == RTL_GIGA_MAC_VER_41 ||
8340 tp->mac_version == RTL_GIGA_MAC_VER_42 ||
8341 tp->mac_version == RTL_GIGA_MAC_VER_43 ||
8342 tp->mac_version == RTL_GIGA_MAC_VER_44 ||
8343 tp->mac_version == RTL_GIGA_MAC_VER_45 ||
6e1d0b89
CHL		 8344 tp->mac_version == RTL_GIGA_MAC_VER_46 ||
8345 tp->mac_version == RTL_GIGA_MAC_VER_47 ||
935e2218
CHL		 8346 tp->mac_version == RTL_GIGA_MAC_VER_48 ||
8347 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
8348 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
8349 tp->mac_version == RTL_GIGA_MAC_VER_51) {
6e1d0b89
CHL		 8350 u16 mac_addr[3];
8351
05b9687b
CHL		 8352 *(u32 *)&mac_addr[0] = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC);
8353 *(u16 *)&mac_addr[2] = rtl_eri_read(tp, 0xe4, ERIAR_EXGMAC);
6e1d0b89
CHL		 8354
8355 if (is_valid_ether_addr((u8 *)mac_addr))
8356 rtl_rar_set(tp, (u8 *)mac_addr);
8357 }
3b6cf25d
FR		 8358 for (i = 0; i < ETH_ALEN; i++)
8359 dev->dev_addr[i] = RTL_R8(MAC0 + i);
3b6cf25d 8360
7ad24ea4 8361 dev->ethtool_ops = &rtl8169_ethtool_ops;
3b6cf25d 8362 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3b6cf25d
FR		 8363
8364 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
8365
8366 /* don't enable SG, IP_CSUM and TSO by default - it might not work
8367 * properly for all devices */
8368 dev->features |= NETIF_F_RXCSUM |
f646968f 8369 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d
FR		 8370
8371 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
f646968f
PM		 8372 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
8373 NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d
FR		 8374 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
8375 NETIF_F_HIGHDMA;
8376
929a031d 8377 tp->cp_cmd |= RxChkSum | RxVlan;
8378
8379 /*
8380 * Pretend we are using VLANs; This bypasses a nasty bug where
8381 * Interrupts stop flowing on high load on 8110SCd controllers.
8382 */
3b6cf25d 8383 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
929a031d 8384 /* Disallow toggling */
f646968f 8385 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d 8386
5888d3fc 8387 if (tp->txd_version == RTL_TD_0)
8388 tp->tso_csum = rtl8169_tso_csum_v1;
e974604b 8389 else if (tp->txd_version == RTL_TD_1) {
5888d3fc 8390 tp->tso_csum = rtl8169_tso_csum_v2;
e974604b 8391 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
8392 } else
5888d3fc 8393 WARN_ON_ONCE(1);
8394
3b6cf25d
FR		 8395 dev->hw_features |= NETIF_F_RXALL;
8396 dev->hw_features |= NETIF_F_RXFCS;
8397
8398 tp->hw_start = cfg->hw_start;
8399 tp->event_slow = cfg->event_slow;
8400
8401 tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
8402 ~(RxBOVF | RxFOVF) : ~0;
8403
8404 init_timer(&tp->timer);
8405 tp->timer.data = (unsigned long) dev;
8406 tp->timer.function = rtl8169_phy_timer;
8407
8408 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
8409
42020320
CV		 8410 tp->counters = dma_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
8411 &tp->counters_phys_addr, GFP_KERNEL);
8412 if (!tp->counters) {
8413 rc = -ENOMEM;
8414 goto err_out_msi_4;
8415 }
8416
3b6cf25d
FR		 8417 rc = register_netdev(dev);
8418 if (rc < 0)
42020320 8419 goto err_out_cnt_5;
3b6cf25d
FR		 8420
8421 pci_set_drvdata(pdev, dev);
8422
92a7c4e7
FR		 8423 netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
8424 rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
8425 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
3b6cf25d
FR		 8426 if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
8427 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
8428 "tx checksumming: %s]\n",
8429 rtl_chip_infos[chipset].jumbo_max,
8430 rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
8431 }
8432
ee7a1beb
CHL		 8433 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
8434 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
935e2218
CHL		 8435 tp->mac_version == RTL_GIGA_MAC_VER_31 ||
8436 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
8437 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
8438 tp->mac_version == RTL_GIGA_MAC_VER_51) &&
ee7a1beb 8439 r8168_check_dash(tp)) {
3b6cf25d
FR		 8440 rtl8168_driver_start(tp);
8441 }
8442
8443 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
8444
8445 if (pci_dev_run_wake(pdev))
8446 pm_runtime_put_noidle(&pdev->dev);
8447
8448 netif_carrier_off(dev);
8449
8450out:
8451 return rc;
8452
42020320
CV		 8453err_out_cnt_5:
8454 dma_free_coherent(&pdev->dev, sizeof(*tp->counters), tp->counters,
8455 tp->counters_phys_addr);
3b6cf25d 8456err_out_msi_4:
ad1be8d3 8457 netif_napi_del(&tp->napi);
3b6cf25d
FR		 8458 rtl_disable_msi(pdev, tp);
8459 iounmap(ioaddr);
8460err_out_free_res_3:
8461 pci_release_regions(pdev);
8462err_out_mwi_2:
8463 pci_clear_mwi(pdev);
8464 pci_disable_device(pdev);
8465err_out_free_dev_1:
8466 free_netdev(dev);
8467 goto out;
8468}
8469
1da177e4
LT		 8470static struct pci_driver rtl8169_pci_driver = {
8471 .name = MODULENAME,
8472 .id_table = rtl8169_pci_tbl,
3b6cf25d 8473 .probe = rtl_init_one,
baf63293 8474 .remove = rtl_remove_one,
1765f95d 8475 .shutdown = rtl_shutdown,
861ab440 8476 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 8477};
8478
3eeb7da9 8479module_pci_driver(rtl8169_pci_driver);
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