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Commit | Line | Data |
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1da177e4 | 1 | /* |
07d3f51f FR |
2 | * r8169.c: RealTek 8169/8168/8101 ethernet driver. |
3 | * | |
4 | * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> | |
5 | * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> | |
6 | * Copyright (c) a lot of people too. Please respect their work. | |
7 | * | |
8 | * See MAINTAINERS file for support contact information. | |
1da177e4 LT |
9 | */ |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/moduleparam.h> | |
13 | #include <linux/pci.h> | |
14 | #include <linux/netdevice.h> | |
15 | #include <linux/etherdevice.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/ethtool.h> | |
18 | #include <linux/mii.h> | |
19 | #include <linux/if_vlan.h> | |
20 | #include <linux/crc32.h> | |
21 | #include <linux/in.h> | |
22 | #include <linux/ip.h> | |
23 | #include <linux/tcp.h> | |
a6b7a407 | 24 | #include <linux/interrupt.h> |
1da177e4 | 25 | #include <linux/dma-mapping.h> |
e1759441 | 26 | #include <linux/pm_runtime.h> |
bca03d5f | 27 | #include <linux/firmware.h> |
ba04c7c9 | 28 | #include <linux/pci-aspm.h> |
70c71606 | 29 | #include <linux/prefetch.h> |
e974604b | 30 | #include <linux/ipv6.h> |
31 | #include <net/ip6_checksum.h> | |
1da177e4 LT |
32 | |
33 | #include <asm/io.h> | |
34 | #include <asm/irq.h> | |
35 | ||
865c652d | 36 | #define RTL8169_VERSION "2.3LK-NAPI" |
1da177e4 LT |
37 | #define MODULENAME "r8169" |
38 | #define PFX MODULENAME ": " | |
39 | ||
bca03d5f | 40 | #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw" |
41 | #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" | |
01dc7fec | 42 | #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw" |
43 | #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw" | |
70090424 | 44 | #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw" |
c2218925 HW |
45 | #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw" |
46 | #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw" | |
5a5e4443 | 47 | #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" |
7e18dca1 | 48 | #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw" |
b3d7b2f2 | 49 | #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw" |
45dd95c4 | 50 | #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw" |
5598bfe5 | 51 | #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw" |
58152cd4 | 52 | #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw" |
beb330a4 | 53 | #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw" |
57538c4a | 54 | #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw" |
6e1d0b89 CHL |
55 | #define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw" |
56 | #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw" | |
57 | #define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw" | |
58 | #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw" | |
bca03d5f | 59 | |
1da177e4 LT |
60 | #ifdef RTL8169_DEBUG |
61 | #define assert(expr) \ | |
5b0384f4 FR |
62 | if (!(expr)) { \ |
63 | printk( "Assertion failed! %s,%s,%s,line=%d\n", \ | |
b39d66a8 | 64 | #expr,__FILE__,__func__,__LINE__); \ |
5b0384f4 | 65 | } |
06fa7358 JP |
66 | #define dprintk(fmt, args...) \ |
67 | do { printk(KERN_DEBUG PFX fmt, ## args); } while (0) | |
1da177e4 LT |
68 | #else |
69 | #define assert(expr) do {} while (0) | |
70 | #define dprintk(fmt, args...) do {} while (0) | |
71 | #endif /* RTL8169_DEBUG */ | |
72 | ||
b57b7e5a | 73 | #define R8169_MSG_DEFAULT \ |
f0e837d9 | 74 | (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN) |
b57b7e5a | 75 | |
477206a0 JD |
76 | #define TX_SLOTS_AVAIL(tp) \ |
77 | (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx) | |
78 | ||
79 | /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */ | |
80 | #define TX_FRAGS_READY_FOR(tp,nr_frags) \ | |
81 | (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1)) | |
1da177e4 | 82 | |
1da177e4 LT |
83 | /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). |
84 | The RTL chips use a 64 element hash table based on the Ethernet CRC. */ | |
f71e1309 | 85 | static const int multicast_filter_limit = 32; |
1da177e4 | 86 | |
9c14ceaf | 87 | #define MAX_READ_REQUEST_SHIFT 12 |
aee77e4a | 88 | #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */ |
1da177e4 LT |
89 | #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ |
90 | ||
91 | #define R8169_REGS_SIZE 256 | |
92 | #define R8169_NAPI_WEIGHT 64 | |
93 | #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */ | |
9fba0812 | 94 | #define NUM_RX_DESC 256U /* Number of Rx descriptor registers */ |
1da177e4 LT |
95 | #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) |
96 | #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) | |
97 | ||
98 | #define RTL8169_TX_TIMEOUT (6*HZ) | |
99 | #define RTL8169_PHY_TIMEOUT (10*HZ) | |
100 | ||
101 | /* write/read MMIO register */ | |
102 | #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg)) | |
103 | #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg)) | |
104 | #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg)) | |
105 | #define RTL_R8(reg) readb (ioaddr + (reg)) | |
106 | #define RTL_R16(reg) readw (ioaddr + (reg)) | |
06f555f3 | 107 | #define RTL_R32(reg) readl (ioaddr + (reg)) |
1da177e4 LT |
108 | |
109 | enum mac_version { | |
85bffe6c FR |
110 | RTL_GIGA_MAC_VER_01 = 0, |
111 | RTL_GIGA_MAC_VER_02, | |
112 | RTL_GIGA_MAC_VER_03, | |
113 | RTL_GIGA_MAC_VER_04, | |
114 | RTL_GIGA_MAC_VER_05, | |
115 | RTL_GIGA_MAC_VER_06, | |
116 | RTL_GIGA_MAC_VER_07, | |
117 | RTL_GIGA_MAC_VER_08, | |
118 | RTL_GIGA_MAC_VER_09, | |
119 | RTL_GIGA_MAC_VER_10, | |
120 | RTL_GIGA_MAC_VER_11, | |
121 | RTL_GIGA_MAC_VER_12, | |
122 | RTL_GIGA_MAC_VER_13, | |
123 | RTL_GIGA_MAC_VER_14, | |
124 | RTL_GIGA_MAC_VER_15, | |
125 | RTL_GIGA_MAC_VER_16, | |
126 | RTL_GIGA_MAC_VER_17, | |
127 | RTL_GIGA_MAC_VER_18, | |
128 | RTL_GIGA_MAC_VER_19, | |
129 | RTL_GIGA_MAC_VER_20, | |
130 | RTL_GIGA_MAC_VER_21, | |
131 | RTL_GIGA_MAC_VER_22, | |
132 | RTL_GIGA_MAC_VER_23, | |
133 | RTL_GIGA_MAC_VER_24, | |
134 | RTL_GIGA_MAC_VER_25, | |
135 | RTL_GIGA_MAC_VER_26, | |
136 | RTL_GIGA_MAC_VER_27, | |
137 | RTL_GIGA_MAC_VER_28, | |
138 | RTL_GIGA_MAC_VER_29, | |
139 | RTL_GIGA_MAC_VER_30, | |
140 | RTL_GIGA_MAC_VER_31, | |
141 | RTL_GIGA_MAC_VER_32, | |
142 | RTL_GIGA_MAC_VER_33, | |
70090424 | 143 | RTL_GIGA_MAC_VER_34, |
c2218925 HW |
144 | RTL_GIGA_MAC_VER_35, |
145 | RTL_GIGA_MAC_VER_36, | |
7e18dca1 | 146 | RTL_GIGA_MAC_VER_37, |
b3d7b2f2 | 147 | RTL_GIGA_MAC_VER_38, |
5598bfe5 | 148 | RTL_GIGA_MAC_VER_39, |
c558386b HW |
149 | RTL_GIGA_MAC_VER_40, |
150 | RTL_GIGA_MAC_VER_41, | |
57538c4a | 151 | RTL_GIGA_MAC_VER_42, |
58152cd4 | 152 | RTL_GIGA_MAC_VER_43, |
45dd95c4 | 153 | RTL_GIGA_MAC_VER_44, |
6e1d0b89 CHL |
154 | RTL_GIGA_MAC_VER_45, |
155 | RTL_GIGA_MAC_VER_46, | |
156 | RTL_GIGA_MAC_VER_47, | |
157 | RTL_GIGA_MAC_VER_48, | |
85bffe6c | 158 | RTL_GIGA_MAC_NONE = 0xff, |
1da177e4 LT |
159 | }; |
160 | ||
2b7b4318 FR |
161 | enum rtl_tx_desc_version { |
162 | RTL_TD_0 = 0, | |
163 | RTL_TD_1 = 1, | |
164 | }; | |
165 | ||
d58d46b5 FR |
166 | #define JUMBO_1K ETH_DATA_LEN |
167 | #define JUMBO_4K (4*1024 - ETH_HLEN - 2) | |
168 | #define JUMBO_6K (6*1024 - ETH_HLEN - 2) | |
169 | #define JUMBO_7K (7*1024 - ETH_HLEN - 2) | |
170 | #define JUMBO_9K (9*1024 - ETH_HLEN - 2) | |
171 | ||
172 | #define _R(NAME,TD,FW,SZ,B) { \ | |
173 | .name = NAME, \ | |
174 | .txd_version = TD, \ | |
175 | .fw_name = FW, \ | |
176 | .jumbo_max = SZ, \ | |
177 | .jumbo_tx_csum = B \ | |
178 | } | |
1da177e4 | 179 | |
3c6bee1d | 180 | static const struct { |
1da177e4 | 181 | const char *name; |
2b7b4318 | 182 | enum rtl_tx_desc_version txd_version; |
953a12cc | 183 | const char *fw_name; |
d58d46b5 FR |
184 | u16 jumbo_max; |
185 | bool jumbo_tx_csum; | |
85bffe6c FR |
186 | } rtl_chip_infos[] = { |
187 | /* PCI devices. */ | |
188 | [RTL_GIGA_MAC_VER_01] = | |
d58d46b5 | 189 | _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K, true), |
85bffe6c | 190 | [RTL_GIGA_MAC_VER_02] = |
d58d46b5 | 191 | _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K, true), |
85bffe6c | 192 | [RTL_GIGA_MAC_VER_03] = |
d58d46b5 | 193 | _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K, true), |
85bffe6c | 194 | [RTL_GIGA_MAC_VER_04] = |
d58d46b5 | 195 | _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K, true), |
85bffe6c | 196 | [RTL_GIGA_MAC_VER_05] = |
d58d46b5 | 197 | _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true), |
85bffe6c | 198 | [RTL_GIGA_MAC_VER_06] = |
d58d46b5 | 199 | _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true), |
85bffe6c FR |
200 | /* PCI-E devices. */ |
201 | [RTL_GIGA_MAC_VER_07] = | |
d58d46b5 | 202 | _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true), |
85bffe6c | 203 | [RTL_GIGA_MAC_VER_08] = |
d58d46b5 | 204 | _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true), |
85bffe6c | 205 | [RTL_GIGA_MAC_VER_09] = |
d58d46b5 | 206 | _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true), |
85bffe6c | 207 | [RTL_GIGA_MAC_VER_10] = |
d58d46b5 | 208 | _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true), |
85bffe6c | 209 | [RTL_GIGA_MAC_VER_11] = |
d58d46b5 | 210 | _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false), |
85bffe6c | 211 | [RTL_GIGA_MAC_VER_12] = |
d58d46b5 | 212 | _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false), |
85bffe6c | 213 | [RTL_GIGA_MAC_VER_13] = |
d58d46b5 | 214 | _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true), |
85bffe6c | 215 | [RTL_GIGA_MAC_VER_14] = |
d58d46b5 | 216 | _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true), |
85bffe6c | 217 | [RTL_GIGA_MAC_VER_15] = |
d58d46b5 | 218 | _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true), |
85bffe6c | 219 | [RTL_GIGA_MAC_VER_16] = |
d58d46b5 | 220 | _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true), |
85bffe6c | 221 | [RTL_GIGA_MAC_VER_17] = |
f75761b6 | 222 | _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false), |
85bffe6c | 223 | [RTL_GIGA_MAC_VER_18] = |
d58d46b5 | 224 | _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false), |
85bffe6c | 225 | [RTL_GIGA_MAC_VER_19] = |
d58d46b5 | 226 | _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false), |
85bffe6c | 227 | [RTL_GIGA_MAC_VER_20] = |
d58d46b5 | 228 | _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false), |
85bffe6c | 229 | [RTL_GIGA_MAC_VER_21] = |
d58d46b5 | 230 | _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false), |
85bffe6c | 231 | [RTL_GIGA_MAC_VER_22] = |
d58d46b5 | 232 | _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false), |
85bffe6c | 233 | [RTL_GIGA_MAC_VER_23] = |
d58d46b5 | 234 | _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false), |
85bffe6c | 235 | [RTL_GIGA_MAC_VER_24] = |
d58d46b5 | 236 | _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false), |
85bffe6c | 237 | [RTL_GIGA_MAC_VER_25] = |
d58d46b5 FR |
238 | _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1, |
239 | JUMBO_9K, false), | |
85bffe6c | 240 | [RTL_GIGA_MAC_VER_26] = |
d58d46b5 FR |
241 | _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2, |
242 | JUMBO_9K, false), | |
85bffe6c | 243 | [RTL_GIGA_MAC_VER_27] = |
d58d46b5 | 244 | _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false), |
85bffe6c | 245 | [RTL_GIGA_MAC_VER_28] = |
d58d46b5 | 246 | _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false), |
85bffe6c | 247 | [RTL_GIGA_MAC_VER_29] = |
d58d46b5 FR |
248 | _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1, |
249 | JUMBO_1K, true), | |
85bffe6c | 250 | [RTL_GIGA_MAC_VER_30] = |
d58d46b5 FR |
251 | _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1, |
252 | JUMBO_1K, true), | |
85bffe6c | 253 | [RTL_GIGA_MAC_VER_31] = |
d58d46b5 | 254 | _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false), |
85bffe6c | 255 | [RTL_GIGA_MAC_VER_32] = |
d58d46b5 FR |
256 | _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1, |
257 | JUMBO_9K, false), | |
85bffe6c | 258 | [RTL_GIGA_MAC_VER_33] = |
d58d46b5 FR |
259 | _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2, |
260 | JUMBO_9K, false), | |
70090424 | 261 | [RTL_GIGA_MAC_VER_34] = |
d58d46b5 FR |
262 | _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3, |
263 | JUMBO_9K, false), | |
c2218925 | 264 | [RTL_GIGA_MAC_VER_35] = |
d58d46b5 FR |
265 | _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1, |
266 | JUMBO_9K, false), | |
c2218925 | 267 | [RTL_GIGA_MAC_VER_36] = |
d58d46b5 FR |
268 | _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2, |
269 | JUMBO_9K, false), | |
7e18dca1 HW |
270 | [RTL_GIGA_MAC_VER_37] = |
271 | _R("RTL8402", RTL_TD_1, FIRMWARE_8402_1, | |
272 | JUMBO_1K, true), | |
b3d7b2f2 HW |
273 | [RTL_GIGA_MAC_VER_38] = |
274 | _R("RTL8411", RTL_TD_1, FIRMWARE_8411_1, | |
275 | JUMBO_9K, false), | |
5598bfe5 HW |
276 | [RTL_GIGA_MAC_VER_39] = |
277 | _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_1, | |
278 | JUMBO_1K, true), | |
c558386b | 279 | [RTL_GIGA_MAC_VER_40] = |
beb330a4 | 280 | _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_2, |
c558386b HW |
281 | JUMBO_9K, false), |
282 | [RTL_GIGA_MAC_VER_41] = | |
283 | _R("RTL8168g/8111g", RTL_TD_1, NULL, JUMBO_9K, false), | |
57538c4a | 284 | [RTL_GIGA_MAC_VER_42] = |
285 | _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_3, | |
286 | JUMBO_9K, false), | |
58152cd4 | 287 | [RTL_GIGA_MAC_VER_43] = |
288 | _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_2, | |
289 | JUMBO_1K, true), | |
45dd95c4 | 290 | [RTL_GIGA_MAC_VER_44] = |
291 | _R("RTL8411", RTL_TD_1, FIRMWARE_8411_2, | |
292 | JUMBO_9K, false), | |
6e1d0b89 CHL |
293 | [RTL_GIGA_MAC_VER_45] = |
294 | _R("RTL8168h/8111h", RTL_TD_1, FIRMWARE_8168H_1, | |
295 | JUMBO_9K, false), | |
296 | [RTL_GIGA_MAC_VER_46] = | |
297 | _R("RTL8168h/8111h", RTL_TD_1, FIRMWARE_8168H_2, | |
298 | JUMBO_9K, false), | |
299 | [RTL_GIGA_MAC_VER_47] = | |
300 | _R("RTL8107e", RTL_TD_1, FIRMWARE_8107E_1, | |
301 | JUMBO_1K, false), | |
302 | [RTL_GIGA_MAC_VER_48] = | |
303 | _R("RTL8107e", RTL_TD_1, FIRMWARE_8107E_2, | |
304 | JUMBO_1K, false), | |
953a12cc | 305 | }; |
85bffe6c | 306 | #undef _R |
953a12cc | 307 | |
bcf0bf90 FR |
308 | enum cfg_version { |
309 | RTL_CFG_0 = 0x00, | |
310 | RTL_CFG_1, | |
311 | RTL_CFG_2 | |
312 | }; | |
313 | ||
9baa3c34 | 314 | static const struct pci_device_id rtl8169_pci_tbl[] = { |
bcf0bf90 | 315 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 }, |
d2eed8cf | 316 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 }, |
d81bf551 | 317 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 }, |
07ce4064 | 318 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 }, |
bcf0bf90 | 319 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 }, |
2a35cfa5 FR |
320 | { PCI_VENDOR_ID_DLINK, 0x4300, |
321 | PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 }, | |
bcf0bf90 | 322 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 }, |
93a3aa25 | 323 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 }, |
bc1660b5 | 324 | { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 }, |
bcf0bf90 FR |
325 | { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 }, |
326 | { PCI_VENDOR_ID_LINKSYS, 0x1032, | |
327 | PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 }, | |
11d2e282 CM |
328 | { 0x0001, 0x8168, |
329 | PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 }, | |
1da177e4 LT |
330 | {0,}, |
331 | }; | |
332 | ||
333 | MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); | |
334 | ||
6f0333b8 | 335 | static int rx_buf_sz = 16383; |
4300e8c7 | 336 | static int use_dac; |
b57b7e5a SH |
337 | static struct { |
338 | u32 msg_enable; | |
339 | } debug = { -1 }; | |
1da177e4 | 340 | |
07d3f51f FR |
341 | enum rtl_registers { |
342 | MAC0 = 0, /* Ethernet hardware address. */ | |
773d2021 | 343 | MAC4 = 4, |
07d3f51f FR |
344 | MAR0 = 8, /* Multicast filter. */ |
345 | CounterAddrLow = 0x10, | |
346 | CounterAddrHigh = 0x14, | |
347 | TxDescStartAddrLow = 0x20, | |
348 | TxDescStartAddrHigh = 0x24, | |
349 | TxHDescStartAddrLow = 0x28, | |
350 | TxHDescStartAddrHigh = 0x2c, | |
351 | FLASH = 0x30, | |
352 | ERSR = 0x36, | |
353 | ChipCmd = 0x37, | |
354 | TxPoll = 0x38, | |
355 | IntrMask = 0x3c, | |
356 | IntrStatus = 0x3e, | |
4f6b00e5 | 357 | |
07d3f51f | 358 | TxConfig = 0x40, |
4f6b00e5 HW |
359 | #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */ |
360 | #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */ | |
2b7b4318 | 361 | |
4f6b00e5 HW |
362 | RxConfig = 0x44, |
363 | #define RX128_INT_EN (1 << 15) /* 8111c and later */ | |
364 | #define RX_MULTI_EN (1 << 14) /* 8111c only */ | |
365 | #define RXCFG_FIFO_SHIFT 13 | |
366 | /* No threshold before first PCI xfer */ | |
367 | #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT) | |
beb330a4 | 368 | #define RX_EARLY_OFF (1 << 11) |
4f6b00e5 HW |
369 | #define RXCFG_DMA_SHIFT 8 |
370 | /* Unlimited maximum PCI burst. */ | |
371 | #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT) | |
2b7b4318 | 372 | |
07d3f51f FR |
373 | RxMissed = 0x4c, |
374 | Cfg9346 = 0x50, | |
375 | Config0 = 0x51, | |
376 | Config1 = 0x52, | |
377 | Config2 = 0x53, | |
d387b427 FR |
378 | #define PME_SIGNAL (1 << 5) /* 8168c and later */ |
379 | ||
07d3f51f FR |
380 | Config3 = 0x54, |
381 | Config4 = 0x55, | |
382 | Config5 = 0x56, | |
383 | MultiIntr = 0x5c, | |
384 | PHYAR = 0x60, | |
07d3f51f FR |
385 | PHYstatus = 0x6c, |
386 | RxMaxSize = 0xda, | |
387 | CPlusCmd = 0xe0, | |
388 | IntrMitigate = 0xe2, | |
389 | RxDescAddrLow = 0xe4, | |
390 | RxDescAddrHigh = 0xe8, | |
f0298f81 | 391 | EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */ |
392 | ||
393 | #define NoEarlyTx 0x3f /* Max value : no early transmit. */ | |
394 | ||
395 | MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */ | |
396 | ||
397 | #define TxPacketMax (8064 >> 7) | |
3090bd9a | 398 | #define EarlySize 0x27 |
f0298f81 | 399 | |
07d3f51f FR |
400 | FuncEvent = 0xf0, |
401 | FuncEventMask = 0xf4, | |
402 | FuncPresetState = 0xf8, | |
403 | FuncForceEvent = 0xfc, | |
1da177e4 LT |
404 | }; |
405 | ||
f162a5d1 FR |
406 | enum rtl8110_registers { |
407 | TBICSR = 0x64, | |
408 | TBI_ANAR = 0x68, | |
409 | TBI_LPAR = 0x6a, | |
410 | }; | |
411 | ||
412 | enum rtl8168_8101_registers { | |
413 | CSIDR = 0x64, | |
414 | CSIAR = 0x68, | |
415 | #define CSIAR_FLAG 0x80000000 | |
416 | #define CSIAR_WRITE_CMD 0x80000000 | |
417 | #define CSIAR_BYTE_ENABLE 0x0f | |
418 | #define CSIAR_BYTE_ENABLE_SHIFT 12 | |
419 | #define CSIAR_ADDR_MASK 0x0fff | |
7e18dca1 HW |
420 | #define CSIAR_FUNC_CARD 0x00000000 |
421 | #define CSIAR_FUNC_SDIO 0x00010000 | |
422 | #define CSIAR_FUNC_NIC 0x00020000 | |
45dd95c4 | 423 | #define CSIAR_FUNC_NIC2 0x00010000 |
065c27c1 | 424 | PMCH = 0x6f, |
f162a5d1 FR |
425 | EPHYAR = 0x80, |
426 | #define EPHYAR_FLAG 0x80000000 | |
427 | #define EPHYAR_WRITE_CMD 0x80000000 | |
428 | #define EPHYAR_REG_MASK 0x1f | |
429 | #define EPHYAR_REG_SHIFT 16 | |
430 | #define EPHYAR_DATA_MASK 0xffff | |
5a5e4443 | 431 | DLLPR = 0xd0, |
4f6b00e5 | 432 | #define PFM_EN (1 << 6) |
6e1d0b89 | 433 | #define TX_10M_PS_EN (1 << 7) |
f162a5d1 FR |
434 | DBG_REG = 0xd1, |
435 | #define FIX_NAK_1 (1 << 4) | |
436 | #define FIX_NAK_2 (1 << 3) | |
5a5e4443 HW |
437 | TWSI = 0xd2, |
438 | MCU = 0xd3, | |
4f6b00e5 | 439 | #define NOW_IS_OOB (1 << 7) |
c558386b HW |
440 | #define TX_EMPTY (1 << 5) |
441 | #define RX_EMPTY (1 << 4) | |
442 | #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY) | |
5a5e4443 HW |
443 | #define EN_NDP (1 << 3) |
444 | #define EN_OOB_RESET (1 << 2) | |
c558386b | 445 | #define LINK_LIST_RDY (1 << 1) |
daf9df6d | 446 | EFUSEAR = 0xdc, |
447 | #define EFUSEAR_FLAG 0x80000000 | |
448 | #define EFUSEAR_WRITE_CMD 0x80000000 | |
449 | #define EFUSEAR_READ_CMD 0x00000000 | |
450 | #define EFUSEAR_REG_MASK 0x03ff | |
451 | #define EFUSEAR_REG_SHIFT 8 | |
452 | #define EFUSEAR_DATA_MASK 0xff | |
6e1d0b89 CHL |
453 | MISC_1 = 0xf2, |
454 | #define PFM_D3COLD_EN (1 << 6) | |
f162a5d1 FR |
455 | }; |
456 | ||
c0e45c1c | 457 | enum rtl8168_registers { |
4f6b00e5 HW |
458 | LED_FREQ = 0x1a, |
459 | EEE_LED = 0x1b, | |
b646d900 | 460 | ERIDR = 0x70, |
461 | ERIAR = 0x74, | |
462 | #define ERIAR_FLAG 0x80000000 | |
463 | #define ERIAR_WRITE_CMD 0x80000000 | |
464 | #define ERIAR_READ_CMD 0x00000000 | |
465 | #define ERIAR_ADDR_BYTE_ALIGN 4 | |
b646d900 | 466 | #define ERIAR_TYPE_SHIFT 16 |
4f6b00e5 HW |
467 | #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT) |
468 | #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT) | |
469 | #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT) | |
470 | #define ERIAR_MASK_SHIFT 12 | |
471 | #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT) | |
472 | #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT) | |
6e1d0b89 | 473 | #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT) |
c558386b | 474 | #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT) |
4f6b00e5 | 475 | #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT) |
c0e45c1c | 476 | EPHY_RXER_NUM = 0x7c, |
477 | OCPDR = 0xb0, /* OCP GPHY access */ | |
478 | #define OCPDR_WRITE_CMD 0x80000000 | |
479 | #define OCPDR_READ_CMD 0x00000000 | |
480 | #define OCPDR_REG_MASK 0x7f | |
481 | #define OCPDR_GPHY_REG_SHIFT 16 | |
482 | #define OCPDR_DATA_MASK 0xffff | |
483 | OCPAR = 0xb4, | |
484 | #define OCPAR_FLAG 0x80000000 | |
485 | #define OCPAR_GPHY_WRITE_CMD 0x8000f060 | |
486 | #define OCPAR_GPHY_READ_CMD 0x0000f060 | |
c558386b | 487 | GPHY_OCP = 0xb8, |
01dc7fec | 488 | RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */ |
489 | MISC = 0xf0, /* 8168e only. */ | |
cecb5fd7 | 490 | #define TXPLA_RST (1 << 29) |
5598bfe5 | 491 | #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */ |
4f6b00e5 | 492 | #define PWM_EN (1 << 22) |
c558386b | 493 | #define RXDV_GATED_EN (1 << 19) |
5598bfe5 | 494 | #define EARLY_TALLY_EN (1 << 16) |
c0e45c1c | 495 | }; |
496 | ||
07d3f51f | 497 | enum rtl_register_content { |
1da177e4 | 498 | /* InterruptStatusBits */ |
07d3f51f FR |
499 | SYSErr = 0x8000, |
500 | PCSTimeout = 0x4000, | |
501 | SWInt = 0x0100, | |
502 | TxDescUnavail = 0x0080, | |
503 | RxFIFOOver = 0x0040, | |
504 | LinkChg = 0x0020, | |
505 | RxOverflow = 0x0010, | |
506 | TxErr = 0x0008, | |
507 | TxOK = 0x0004, | |
508 | RxErr = 0x0002, | |
509 | RxOK = 0x0001, | |
1da177e4 LT |
510 | |
511 | /* RxStatusDesc */ | |
e03f33af | 512 | RxBOVF = (1 << 24), |
9dccf611 FR |
513 | RxFOVF = (1 << 23), |
514 | RxRWT = (1 << 22), | |
515 | RxRES = (1 << 21), | |
516 | RxRUNT = (1 << 20), | |
517 | RxCRC = (1 << 19), | |
1da177e4 LT |
518 | |
519 | /* ChipCmdBits */ | |
4f6b00e5 | 520 | StopReq = 0x80, |
07d3f51f FR |
521 | CmdReset = 0x10, |
522 | CmdRxEnb = 0x08, | |
523 | CmdTxEnb = 0x04, | |
524 | RxBufEmpty = 0x01, | |
1da177e4 | 525 | |
275391a4 FR |
526 | /* TXPoll register p.5 */ |
527 | HPQ = 0x80, /* Poll cmd on the high prio queue */ | |
528 | NPQ = 0x40, /* Poll cmd on the low prio queue */ | |
529 | FSWInt = 0x01, /* Forced software interrupt */ | |
530 | ||
1da177e4 | 531 | /* Cfg9346Bits */ |
07d3f51f FR |
532 | Cfg9346_Lock = 0x00, |
533 | Cfg9346_Unlock = 0xc0, | |
1da177e4 LT |
534 | |
535 | /* rx_mode_bits */ | |
07d3f51f FR |
536 | AcceptErr = 0x20, |
537 | AcceptRunt = 0x10, | |
538 | AcceptBroadcast = 0x08, | |
539 | AcceptMulticast = 0x04, | |
540 | AcceptMyPhys = 0x02, | |
541 | AcceptAllPhys = 0x01, | |
1687b566 | 542 | #define RX_CONFIG_ACCEPT_MASK 0x3f |
1da177e4 | 543 | |
1da177e4 LT |
544 | /* TxConfigBits */ |
545 | TxInterFrameGapShift = 24, | |
546 | TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ | |
547 | ||
5d06a99f | 548 | /* Config1 register p.24 */ |
f162a5d1 FR |
549 | LEDS1 = (1 << 7), |
550 | LEDS0 = (1 << 6), | |
f162a5d1 FR |
551 | Speed_down = (1 << 4), |
552 | MEMMAP = (1 << 3), | |
553 | IOMAP = (1 << 2), | |
554 | VPD = (1 << 1), | |
5d06a99f FR |
555 | PMEnable = (1 << 0), /* Power Management Enable */ |
556 | ||
6dccd16b | 557 | /* Config2 register p. 25 */ |
57538c4a | 558 | ClkReqEn = (1 << 7), /* Clock Request Enable */ |
2ca6cf06 | 559 | MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */ |
6dccd16b FR |
560 | PCI_Clock_66MHz = 0x01, |
561 | PCI_Clock_33MHz = 0x00, | |
562 | ||
61a4dcc2 FR |
563 | /* Config3 register p.25 */ |
564 | MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ | |
565 | LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ | |
d58d46b5 | 566 | Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */ |
b51ecea8 | 567 | Rdy_to_L23 = (1 << 1), /* L23 Enable */ |
f162a5d1 | 568 | Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ |
61a4dcc2 | 569 | |
d58d46b5 FR |
570 | /* Config4 register */ |
571 | Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */ | |
572 | ||
5d06a99f | 573 | /* Config5 register p.27 */ |
61a4dcc2 FR |
574 | BWF = (1 << 6), /* Accept Broadcast wakeup frame */ |
575 | MWF = (1 << 5), /* Accept Multicast wakeup frame */ | |
576 | UWF = (1 << 4), /* Accept Unicast wakeup frame */ | |
cecb5fd7 | 577 | Spi_en = (1 << 3), |
61a4dcc2 | 578 | LanWake = (1 << 1), /* LanWake enable/disable */ |
5d06a99f | 579 | PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ |
57538c4a | 580 | ASPM_en = (1 << 0), /* ASPM enable */ |
5d06a99f | 581 | |
1da177e4 LT |
582 | /* TBICSR p.28 */ |
583 | TBIReset = 0x80000000, | |
584 | TBILoopback = 0x40000000, | |
585 | TBINwEnable = 0x20000000, | |
586 | TBINwRestart = 0x10000000, | |
587 | TBILinkOk = 0x02000000, | |
588 | TBINwComplete = 0x01000000, | |
589 | ||
590 | /* CPlusCmd p.31 */ | |
f162a5d1 FR |
591 | EnableBist = (1 << 15), // 8168 8101 |
592 | Mac_dbgo_oe = (1 << 14), // 8168 8101 | |
593 | Normal_mode = (1 << 13), // unused | |
594 | Force_half_dup = (1 << 12), // 8168 8101 | |
595 | Force_rxflow_en = (1 << 11), // 8168 8101 | |
596 | Force_txflow_en = (1 << 10), // 8168 8101 | |
597 | Cxpl_dbg_sel = (1 << 9), // 8168 8101 | |
598 | ASF = (1 << 8), // 8168 8101 | |
599 | PktCntrDisable = (1 << 7), // 8168 8101 | |
600 | Mac_dbgo_sel = 0x001c, // 8168 | |
1da177e4 LT |
601 | RxVlan = (1 << 6), |
602 | RxChkSum = (1 << 5), | |
603 | PCIDAC = (1 << 4), | |
604 | PCIMulRW = (1 << 3), | |
0e485150 FR |
605 | INTT_0 = 0x0000, // 8168 |
606 | INTT_1 = 0x0001, // 8168 | |
607 | INTT_2 = 0x0002, // 8168 | |
608 | INTT_3 = 0x0003, // 8168 | |
1da177e4 LT |
609 | |
610 | /* rtl8169_PHYstatus */ | |
07d3f51f FR |
611 | TBI_Enable = 0x80, |
612 | TxFlowCtrl = 0x40, | |
613 | RxFlowCtrl = 0x20, | |
614 | _1000bpsF = 0x10, | |
615 | _100bps = 0x08, | |
616 | _10bps = 0x04, | |
617 | LinkStatus = 0x02, | |
618 | FullDup = 0x01, | |
1da177e4 | 619 | |
1da177e4 | 620 | /* _TBICSRBit */ |
07d3f51f | 621 | TBILinkOK = 0x02000000, |
d4a3a0fc SH |
622 | |
623 | /* DumpCounterCommand */ | |
07d3f51f | 624 | CounterDump = 0x8, |
6e1d0b89 CHL |
625 | |
626 | /* magic enable v2 */ | |
627 | MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */ | |
1da177e4 LT |
628 | }; |
629 | ||
2b7b4318 FR |
630 | enum rtl_desc_bit { |
631 | /* First doubleword. */ | |
1da177e4 LT |
632 | DescOwn = (1 << 31), /* Descriptor is owned by NIC */ |
633 | RingEnd = (1 << 30), /* End of descriptor ring */ | |
634 | FirstFrag = (1 << 29), /* First segment of a packet */ | |
635 | LastFrag = (1 << 28), /* Final segment of a packet */ | |
2b7b4318 FR |
636 | }; |
637 | ||
638 | /* Generic case. */ | |
639 | enum rtl_tx_desc_bit { | |
640 | /* First doubleword. */ | |
641 | TD_LSO = (1 << 27), /* Large Send Offload */ | |
642 | #define TD_MSS_MAX 0x07ffu /* MSS value */ | |
1da177e4 | 643 | |
2b7b4318 FR |
644 | /* Second doubleword. */ |
645 | TxVlanTag = (1 << 17), /* Add VLAN tag */ | |
646 | }; | |
647 | ||
648 | /* 8169, 8168b and 810x except 8102e. */ | |
649 | enum rtl_tx_desc_bit_0 { | |
650 | /* First doubleword. */ | |
651 | #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */ | |
652 | TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */ | |
653 | TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */ | |
654 | TD0_IP_CS = (1 << 18), /* Calculate IP checksum */ | |
655 | }; | |
656 | ||
657 | /* 8102e, 8168c and beyond. */ | |
658 | enum rtl_tx_desc_bit_1 { | |
bdfa4ed6 | 659 | /* First doubleword. */ |
660 | TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */ | |
e974604b | 661 | TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */ |
bdfa4ed6 | 662 | #define GTTCPHO_SHIFT 18 |
e974604b | 663 | #define GTTCPHO_MAX 0x7fU |
bdfa4ed6 | 664 | |
2b7b4318 | 665 | /* Second doubleword. */ |
e974604b | 666 | #define TCPHO_SHIFT 18 |
667 | #define TCPHO_MAX 0x3ffU | |
2b7b4318 | 668 | #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */ |
e974604b | 669 | TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */ |
670 | TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */ | |
2b7b4318 FR |
671 | TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */ |
672 | TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */ | |
673 | }; | |
1da177e4 | 674 | |
2b7b4318 | 675 | enum rtl_rx_desc_bit { |
1da177e4 LT |
676 | /* Rx private */ |
677 | PID1 = (1 << 18), /* Protocol ID bit 1/2 */ | |
678 | PID0 = (1 << 17), /* Protocol ID bit 2/2 */ | |
679 | ||
680 | #define RxProtoUDP (PID1) | |
681 | #define RxProtoTCP (PID0) | |
682 | #define RxProtoIP (PID1 | PID0) | |
683 | #define RxProtoMask RxProtoIP | |
684 | ||
685 | IPFail = (1 << 16), /* IP checksum failed */ | |
686 | UDPFail = (1 << 15), /* UDP/IP checksum failed */ | |
687 | TCPFail = (1 << 14), /* TCP/IP checksum failed */ | |
688 | RxVlanTag = (1 << 16), /* VLAN tag available */ | |
689 | }; | |
690 | ||
691 | #define RsvdMask 0x3fffc000 | |
692 | ||
693 | struct TxDesc { | |
6cccd6e7 REB |
694 | __le32 opts1; |
695 | __le32 opts2; | |
696 | __le64 addr; | |
1da177e4 LT |
697 | }; |
698 | ||
699 | struct RxDesc { | |
6cccd6e7 REB |
700 | __le32 opts1; |
701 | __le32 opts2; | |
702 | __le64 addr; | |
1da177e4 LT |
703 | }; |
704 | ||
705 | struct ring_info { | |
706 | struct sk_buff *skb; | |
707 | u32 len; | |
708 | u8 __pad[sizeof(void *) - sizeof(u32)]; | |
709 | }; | |
710 | ||
f23e7fda | 711 | enum features { |
ccdffb9a FR |
712 | RTL_FEATURE_WOL = (1 << 0), |
713 | RTL_FEATURE_MSI = (1 << 1), | |
714 | RTL_FEATURE_GMII = (1 << 2), | |
f23e7fda FR |
715 | }; |
716 | ||
355423d0 IV |
717 | struct rtl8169_counters { |
718 | __le64 tx_packets; | |
719 | __le64 rx_packets; | |
720 | __le64 tx_errors; | |
721 | __le32 rx_errors; | |
722 | __le16 rx_missed; | |
723 | __le16 align_errors; | |
724 | __le32 tx_one_collision; | |
725 | __le32 tx_multi_collision; | |
726 | __le64 rx_unicast; | |
727 | __le64 rx_broadcast; | |
728 | __le32 rx_multicast; | |
729 | __le16 tx_aborted; | |
730 | __le16 tx_underun; | |
731 | }; | |
732 | ||
da78dbff | 733 | enum rtl_flag { |
6c4a70c5 | 734 | RTL_FLAG_TASK_ENABLED, |
da78dbff FR |
735 | RTL_FLAG_TASK_SLOW_PENDING, |
736 | RTL_FLAG_TASK_RESET_PENDING, | |
737 | RTL_FLAG_TASK_PHY_PENDING, | |
738 | RTL_FLAG_MAX | |
739 | }; | |
740 | ||
8027aa24 JW |
741 | struct rtl8169_stats { |
742 | u64 packets; | |
743 | u64 bytes; | |
744 | struct u64_stats_sync syncp; | |
745 | }; | |
746 | ||
1da177e4 LT |
747 | struct rtl8169_private { |
748 | void __iomem *mmio_addr; /* memory map physical address */ | |
cecb5fd7 | 749 | struct pci_dev *pci_dev; |
c4028958 | 750 | struct net_device *dev; |
bea3348e | 751 | struct napi_struct napi; |
b57b7e5a | 752 | u32 msg_enable; |
2b7b4318 FR |
753 | u16 txd_version; |
754 | u16 mac_version; | |
1da177e4 LT |
755 | u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ |
756 | u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ | |
1da177e4 | 757 | u32 dirty_tx; |
8027aa24 JW |
758 | struct rtl8169_stats rx_stats; |
759 | struct rtl8169_stats tx_stats; | |
1da177e4 LT |
760 | struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ |
761 | struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ | |
762 | dma_addr_t TxPhyAddr; | |
763 | dma_addr_t RxPhyAddr; | |
6f0333b8 | 764 | void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */ |
1da177e4 | 765 | struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ |
1da177e4 LT |
766 | struct timer_list timer; |
767 | u16 cp_cmd; | |
da78dbff FR |
768 | |
769 | u16 event_slow; | |
c0e45c1c | 770 | |
771 | struct mdio_ops { | |
24192210 FR |
772 | void (*write)(struct rtl8169_private *, int, int); |
773 | int (*read)(struct rtl8169_private *, int); | |
c0e45c1c | 774 | } mdio_ops; |
775 | ||
065c27c1 | 776 | struct pll_power_ops { |
777 | void (*down)(struct rtl8169_private *); | |
778 | void (*up)(struct rtl8169_private *); | |
779 | } pll_power_ops; | |
780 | ||
d58d46b5 FR |
781 | struct jumbo_ops { |
782 | void (*enable)(struct rtl8169_private *); | |
783 | void (*disable)(struct rtl8169_private *); | |
784 | } jumbo_ops; | |
785 | ||
beb1fe18 | 786 | struct csi_ops { |
52989f0e FR |
787 | void (*write)(struct rtl8169_private *, int, int); |
788 | u32 (*read)(struct rtl8169_private *, int); | |
beb1fe18 HW |
789 | } csi_ops; |
790 | ||
54405cde | 791 | int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv); |
ccdffb9a | 792 | int (*get_settings)(struct net_device *, struct ethtool_cmd *); |
4da19633 | 793 | void (*phy_reset_enable)(struct rtl8169_private *tp); |
07ce4064 | 794 | void (*hw_start)(struct net_device *); |
4da19633 | 795 | unsigned int (*phy_reset_pending)(struct rtl8169_private *tp); |
1da177e4 | 796 | unsigned int (*link_ok)(void __iomem *); |
8b4ab28d | 797 | int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd); |
5888d3fc | 798 | bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *); |
4422bcd4 FR |
799 | |
800 | struct { | |
da78dbff FR |
801 | DECLARE_BITMAP(flags, RTL_FLAG_MAX); |
802 | struct mutex mutex; | |
4422bcd4 FR |
803 | struct work_struct work; |
804 | } wk; | |
805 | ||
f23e7fda | 806 | unsigned features; |
ccdffb9a FR |
807 | |
808 | struct mii_if_info mii; | |
355423d0 | 809 | struct rtl8169_counters counters; |
e1759441 | 810 | u32 saved_wolopts; |
e03f33af | 811 | u32 opts1_mask; |
f1e02ed1 | 812 | |
b6ffd97f FR |
813 | struct rtl_fw { |
814 | const struct firmware *fw; | |
1c361efb FR |
815 | |
816 | #define RTL_VER_SIZE 32 | |
817 | ||
818 | char version[RTL_VER_SIZE]; | |
819 | ||
820 | struct rtl_fw_phy_action { | |
821 | __le32 *code; | |
822 | size_t size; | |
823 | } phy_action; | |
b6ffd97f | 824 | } *rtl_fw; |
497888cf | 825 | #define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN) |
c558386b HW |
826 | |
827 | u32 ocp_base; | |
1da177e4 LT |
828 | }; |
829 | ||
979b6c13 | 830 | MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); |
1da177e4 | 831 | MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); |
1da177e4 | 832 | module_param(use_dac, int, 0); |
4300e8c7 | 833 | MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot."); |
b57b7e5a SH |
834 | module_param_named(debug, debug.msg_enable, int, 0); |
835 | MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)"); | |
1da177e4 LT |
836 | MODULE_LICENSE("GPL"); |
837 | MODULE_VERSION(RTL8169_VERSION); | |
bca03d5f | 838 | MODULE_FIRMWARE(FIRMWARE_8168D_1); |
839 | MODULE_FIRMWARE(FIRMWARE_8168D_2); | |
01dc7fec | 840 | MODULE_FIRMWARE(FIRMWARE_8168E_1); |
841 | MODULE_FIRMWARE(FIRMWARE_8168E_2); | |
bbb8af75 | 842 | MODULE_FIRMWARE(FIRMWARE_8168E_3); |
5a5e4443 | 843 | MODULE_FIRMWARE(FIRMWARE_8105E_1); |
c2218925 HW |
844 | MODULE_FIRMWARE(FIRMWARE_8168F_1); |
845 | MODULE_FIRMWARE(FIRMWARE_8168F_2); | |
7e18dca1 | 846 | MODULE_FIRMWARE(FIRMWARE_8402_1); |
b3d7b2f2 | 847 | MODULE_FIRMWARE(FIRMWARE_8411_1); |
45dd95c4 | 848 | MODULE_FIRMWARE(FIRMWARE_8411_2); |
5598bfe5 | 849 | MODULE_FIRMWARE(FIRMWARE_8106E_1); |
58152cd4 | 850 | MODULE_FIRMWARE(FIRMWARE_8106E_2); |
beb330a4 | 851 | MODULE_FIRMWARE(FIRMWARE_8168G_2); |
57538c4a | 852 | MODULE_FIRMWARE(FIRMWARE_8168G_3); |
6e1d0b89 CHL |
853 | MODULE_FIRMWARE(FIRMWARE_8168H_1); |
854 | MODULE_FIRMWARE(FIRMWARE_8168H_2); | |
1da177e4 | 855 | |
da78dbff FR |
856 | static void rtl_lock_work(struct rtl8169_private *tp) |
857 | { | |
858 | mutex_lock(&tp->wk.mutex); | |
859 | } | |
860 | ||
861 | static void rtl_unlock_work(struct rtl8169_private *tp) | |
862 | { | |
863 | mutex_unlock(&tp->wk.mutex); | |
864 | } | |
865 | ||
d58d46b5 FR |
866 | static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force) |
867 | { | |
7d7903b2 JL |
868 | pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL, |
869 | PCI_EXP_DEVCTL_READRQ, force); | |
d58d46b5 FR |
870 | } |
871 | ||
ffc46952 FR |
872 | struct rtl_cond { |
873 | bool (*check)(struct rtl8169_private *); | |
874 | const char *msg; | |
875 | }; | |
876 | ||
877 | static void rtl_udelay(unsigned int d) | |
878 | { | |
879 | udelay(d); | |
880 | } | |
881 | ||
882 | static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c, | |
883 | void (*delay)(unsigned int), unsigned int d, int n, | |
884 | bool high) | |
885 | { | |
886 | int i; | |
887 | ||
888 | for (i = 0; i < n; i++) { | |
889 | delay(d); | |
890 | if (c->check(tp) == high) | |
891 | return true; | |
892 | } | |
82e316ef FR |
893 | netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n", |
894 | c->msg, !high, n, d); | |
ffc46952 FR |
895 | return false; |
896 | } | |
897 | ||
898 | static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp, | |
899 | const struct rtl_cond *c, | |
900 | unsigned int d, int n) | |
901 | { | |
902 | return rtl_loop_wait(tp, c, rtl_udelay, d, n, true); | |
903 | } | |
904 | ||
905 | static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp, | |
906 | const struct rtl_cond *c, | |
907 | unsigned int d, int n) | |
908 | { | |
909 | return rtl_loop_wait(tp, c, rtl_udelay, d, n, false); | |
910 | } | |
911 | ||
912 | static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp, | |
913 | const struct rtl_cond *c, | |
914 | unsigned int d, int n) | |
915 | { | |
916 | return rtl_loop_wait(tp, c, msleep, d, n, true); | |
917 | } | |
918 | ||
919 | static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp, | |
920 | const struct rtl_cond *c, | |
921 | unsigned int d, int n) | |
922 | { | |
923 | return rtl_loop_wait(tp, c, msleep, d, n, false); | |
924 | } | |
925 | ||
926 | #define DECLARE_RTL_COND(name) \ | |
927 | static bool name ## _check(struct rtl8169_private *); \ | |
928 | \ | |
929 | static const struct rtl_cond name = { \ | |
930 | .check = name ## _check, \ | |
931 | .msg = #name \ | |
932 | }; \ | |
933 | \ | |
934 | static bool name ## _check(struct rtl8169_private *tp) | |
935 | ||
936 | DECLARE_RTL_COND(rtl_ocpar_cond) | |
937 | { | |
938 | void __iomem *ioaddr = tp->mmio_addr; | |
939 | ||
940 | return RTL_R32(OCPAR) & OCPAR_FLAG; | |
941 | } | |
942 | ||
b646d900 | 943 | static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg) |
944 | { | |
945 | void __iomem *ioaddr = tp->mmio_addr; | |
b646d900 | 946 | |
947 | RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); | |
ffc46952 FR |
948 | |
949 | return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ? | |
950 | RTL_R32(OCPDR) : ~0; | |
b646d900 | 951 | } |
952 | ||
953 | static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data) | |
954 | { | |
955 | void __iomem *ioaddr = tp->mmio_addr; | |
b646d900 | 956 | |
957 | RTL_W32(OCPDR, data); | |
958 | RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); | |
ffc46952 FR |
959 | |
960 | rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20); | |
961 | } | |
962 | ||
963 | DECLARE_RTL_COND(rtl_eriar_cond) | |
964 | { | |
965 | void __iomem *ioaddr = tp->mmio_addr; | |
966 | ||
967 | return RTL_R32(ERIAR) & ERIAR_FLAG; | |
b646d900 | 968 | } |
969 | ||
fac5b3ca | 970 | static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd) |
b646d900 | 971 | { |
fac5b3ca | 972 | void __iomem *ioaddr = tp->mmio_addr; |
b646d900 | 973 | |
974 | RTL_W8(ERIDR, cmd); | |
975 | RTL_W32(ERIAR, 0x800010e8); | |
976 | msleep(2); | |
ffc46952 FR |
977 | |
978 | if (!rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 5)) | |
979 | return; | |
b646d900 | 980 | |
fac5b3ca | 981 | ocp_write(tp, 0x1, 0x30, 0x00000001); |
b646d900 | 982 | } |
983 | ||
984 | #define OOB_CMD_RESET 0x00 | |
985 | #define OOB_CMD_DRIVER_START 0x05 | |
986 | #define OOB_CMD_DRIVER_STOP 0x06 | |
987 | ||
cecb5fd7 FR |
988 | static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp) |
989 | { | |
990 | return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10; | |
991 | } | |
992 | ||
ffc46952 | 993 | DECLARE_RTL_COND(rtl_ocp_read_cond) |
b646d900 | 994 | { |
cecb5fd7 | 995 | u16 reg; |
b646d900 | 996 | |
cecb5fd7 | 997 | reg = rtl8168_get_ocp_reg(tp); |
4804b3b3 | 998 | |
ffc46952 | 999 | return ocp_read(tp, 0x0f, reg) & 0x00000800; |
b646d900 | 1000 | } |
1001 | ||
ffc46952 | 1002 | static void rtl8168_driver_start(struct rtl8169_private *tp) |
b646d900 | 1003 | { |
ffc46952 | 1004 | rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START); |
b646d900 | 1005 | |
ffc46952 FR |
1006 | rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10); |
1007 | } | |
b646d900 | 1008 | |
ffc46952 FR |
1009 | static void rtl8168_driver_stop(struct rtl8169_private *tp) |
1010 | { | |
1011 | rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP); | |
4804b3b3 | 1012 | |
ffc46952 | 1013 | rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10); |
b646d900 | 1014 | } |
1015 | ||
4804b3b3 | 1016 | static int r8168dp_check_dash(struct rtl8169_private *tp) |
1017 | { | |
cecb5fd7 | 1018 | u16 reg = rtl8168_get_ocp_reg(tp); |
4804b3b3 | 1019 | |
cecb5fd7 | 1020 | return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0; |
4804b3b3 | 1021 | } |
b646d900 | 1022 | |
c558386b HW |
1023 | static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg) |
1024 | { | |
1025 | if (reg & 0xffff0001) { | |
1026 | netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg); | |
1027 | return true; | |
1028 | } | |
1029 | return false; | |
1030 | } | |
1031 | ||
1032 | DECLARE_RTL_COND(rtl_ocp_gphy_cond) | |
1033 | { | |
1034 | void __iomem *ioaddr = tp->mmio_addr; | |
1035 | ||
1036 | return RTL_R32(GPHY_OCP) & OCPAR_FLAG; | |
1037 | } | |
1038 | ||
1039 | static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) | |
1040 | { | |
1041 | void __iomem *ioaddr = tp->mmio_addr; | |
1042 | ||
1043 | if (rtl_ocp_reg_failure(tp, reg)) | |
1044 | return; | |
1045 | ||
1046 | RTL_W32(GPHY_OCP, OCPAR_FLAG | (reg << 15) | data); | |
1047 | ||
1048 | rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10); | |
1049 | } | |
1050 | ||
1051 | static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg) | |
1052 | { | |
1053 | void __iomem *ioaddr = tp->mmio_addr; | |
1054 | ||
1055 | if (rtl_ocp_reg_failure(tp, reg)) | |
1056 | return 0; | |
1057 | ||
1058 | RTL_W32(GPHY_OCP, reg << 15); | |
1059 | ||
1060 | return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ? | |
1061 | (RTL_R32(GPHY_OCP) & 0xffff) : ~0; | |
1062 | } | |
1063 | ||
c558386b HW |
1064 | static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) |
1065 | { | |
1066 | void __iomem *ioaddr = tp->mmio_addr; | |
1067 | ||
1068 | if (rtl_ocp_reg_failure(tp, reg)) | |
1069 | return; | |
1070 | ||
1071 | RTL_W32(OCPDR, OCPAR_FLAG | (reg << 15) | data); | |
c558386b HW |
1072 | } |
1073 | ||
1074 | static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) | |
1075 | { | |
1076 | void __iomem *ioaddr = tp->mmio_addr; | |
1077 | ||
1078 | if (rtl_ocp_reg_failure(tp, reg)) | |
1079 | return 0; | |
1080 | ||
1081 | RTL_W32(OCPDR, reg << 15); | |
1082 | ||
3a83ad12 | 1083 | return RTL_R32(OCPDR); |
c558386b HW |
1084 | } |
1085 | ||
1086 | #define OCP_STD_PHY_BASE 0xa400 | |
1087 | ||
1088 | static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value) | |
1089 | { | |
1090 | if (reg == 0x1f) { | |
1091 | tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE; | |
1092 | return; | |
1093 | } | |
1094 | ||
1095 | if (tp->ocp_base != OCP_STD_PHY_BASE) | |
1096 | reg -= 0x10; | |
1097 | ||
1098 | r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value); | |
1099 | } | |
1100 | ||
1101 | static int r8168g_mdio_read(struct rtl8169_private *tp, int reg) | |
1102 | { | |
1103 | if (tp->ocp_base != OCP_STD_PHY_BASE) | |
1104 | reg -= 0x10; | |
1105 | ||
1106 | return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2); | |
1107 | } | |
1108 | ||
eee3786f | 1109 | static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value) |
1110 | { | |
1111 | if (reg == 0x1f) { | |
1112 | tp->ocp_base = value << 4; | |
1113 | return; | |
1114 | } | |
1115 | ||
1116 | r8168_mac_ocp_write(tp, tp->ocp_base + reg, value); | |
1117 | } | |
1118 | ||
1119 | static int mac_mcu_read(struct rtl8169_private *tp, int reg) | |
1120 | { | |
1121 | return r8168_mac_ocp_read(tp, tp->ocp_base + reg); | |
1122 | } | |
1123 | ||
ffc46952 FR |
1124 | DECLARE_RTL_COND(rtl_phyar_cond) |
1125 | { | |
1126 | void __iomem *ioaddr = tp->mmio_addr; | |
1127 | ||
1128 | return RTL_R32(PHYAR) & 0x80000000; | |
1129 | } | |
1130 | ||
24192210 | 1131 | static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value) |
1da177e4 | 1132 | { |
24192210 | 1133 | void __iomem *ioaddr = tp->mmio_addr; |
1da177e4 | 1134 | |
24192210 | 1135 | RTL_W32(PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff)); |
1da177e4 | 1136 | |
ffc46952 | 1137 | rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20); |
024a07ba | 1138 | /* |
81a95f04 TT |
1139 | * According to hardware specs a 20us delay is required after write |
1140 | * complete indication, but before sending next command. | |
024a07ba | 1141 | */ |
81a95f04 | 1142 | udelay(20); |
1da177e4 LT |
1143 | } |
1144 | ||
24192210 | 1145 | static int r8169_mdio_read(struct rtl8169_private *tp, int reg) |
1da177e4 | 1146 | { |
24192210 | 1147 | void __iomem *ioaddr = tp->mmio_addr; |
ffc46952 | 1148 | int value; |
1da177e4 | 1149 | |
24192210 | 1150 | RTL_W32(PHYAR, 0x0 | (reg & 0x1f) << 16); |
1da177e4 | 1151 | |
ffc46952 FR |
1152 | value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ? |
1153 | RTL_R32(PHYAR) & 0xffff : ~0; | |
1154 | ||
81a95f04 TT |
1155 | /* |
1156 | * According to hardware specs a 20us delay is required after read | |
1157 | * complete indication, but before sending next command. | |
1158 | */ | |
1159 | udelay(20); | |
1160 | ||
1da177e4 LT |
1161 | return value; |
1162 | } | |
1163 | ||
24192210 | 1164 | static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data) |
c0e45c1c | 1165 | { |
24192210 | 1166 | void __iomem *ioaddr = tp->mmio_addr; |
c0e45c1c | 1167 | |
24192210 | 1168 | RTL_W32(OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT)); |
c0e45c1c | 1169 | RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD); |
1170 | RTL_W32(EPHY_RXER_NUM, 0); | |
1171 | ||
ffc46952 | 1172 | rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100); |
c0e45c1c | 1173 | } |
1174 | ||
24192210 | 1175 | static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value) |
c0e45c1c | 1176 | { |
24192210 FR |
1177 | r8168dp_1_mdio_access(tp, reg, |
1178 | OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK)); | |
c0e45c1c | 1179 | } |
1180 | ||
24192210 | 1181 | static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg) |
c0e45c1c | 1182 | { |
24192210 | 1183 | void __iomem *ioaddr = tp->mmio_addr; |
c0e45c1c | 1184 | |
24192210 | 1185 | r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD); |
c0e45c1c | 1186 | |
1187 | mdelay(1); | |
1188 | RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD); | |
1189 | RTL_W32(EPHY_RXER_NUM, 0); | |
1190 | ||
ffc46952 FR |
1191 | return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ? |
1192 | RTL_R32(OCPDR) & OCPDR_DATA_MASK : ~0; | |
c0e45c1c | 1193 | } |
1194 | ||
e6de30d6 | 1195 | #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000 |
1196 | ||
1197 | static void r8168dp_2_mdio_start(void __iomem *ioaddr) | |
1198 | { | |
1199 | RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); | |
1200 | } | |
1201 | ||
1202 | static void r8168dp_2_mdio_stop(void __iomem *ioaddr) | |
1203 | { | |
1204 | RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT); | |
1205 | } | |
1206 | ||
24192210 | 1207 | static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value) |
e6de30d6 | 1208 | { |
24192210 FR |
1209 | void __iomem *ioaddr = tp->mmio_addr; |
1210 | ||
e6de30d6 | 1211 | r8168dp_2_mdio_start(ioaddr); |
1212 | ||
24192210 | 1213 | r8169_mdio_write(tp, reg, value); |
e6de30d6 | 1214 | |
1215 | r8168dp_2_mdio_stop(ioaddr); | |
1216 | } | |
1217 | ||
24192210 | 1218 | static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg) |
e6de30d6 | 1219 | { |
24192210 | 1220 | void __iomem *ioaddr = tp->mmio_addr; |
e6de30d6 | 1221 | int value; |
1222 | ||
1223 | r8168dp_2_mdio_start(ioaddr); | |
1224 | ||
24192210 | 1225 | value = r8169_mdio_read(tp, reg); |
e6de30d6 | 1226 | |
1227 | r8168dp_2_mdio_stop(ioaddr); | |
1228 | ||
1229 | return value; | |
1230 | } | |
1231 | ||
4da19633 | 1232 | static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val) |
dacf8154 | 1233 | { |
24192210 | 1234 | tp->mdio_ops.write(tp, location, val); |
dacf8154 FR |
1235 | } |
1236 | ||
4da19633 | 1237 | static int rtl_readphy(struct rtl8169_private *tp, int location) |
1238 | { | |
24192210 | 1239 | return tp->mdio_ops.read(tp, location); |
4da19633 | 1240 | } |
1241 | ||
1242 | static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value) | |
1243 | { | |
1244 | rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value); | |
1245 | } | |
1246 | ||
1247 | static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m) | |
daf9df6d | 1248 | { |
1249 | int val; | |
1250 | ||
4da19633 | 1251 | val = rtl_readphy(tp, reg_addr); |
1252 | rtl_writephy(tp, reg_addr, (val | p) & ~m); | |
daf9df6d | 1253 | } |
1254 | ||
ccdffb9a FR |
1255 | static void rtl_mdio_write(struct net_device *dev, int phy_id, int location, |
1256 | int val) | |
1257 | { | |
1258 | struct rtl8169_private *tp = netdev_priv(dev); | |
ccdffb9a | 1259 | |
4da19633 | 1260 | rtl_writephy(tp, location, val); |
ccdffb9a FR |
1261 | } |
1262 | ||
1263 | static int rtl_mdio_read(struct net_device *dev, int phy_id, int location) | |
1264 | { | |
1265 | struct rtl8169_private *tp = netdev_priv(dev); | |
ccdffb9a | 1266 | |
4da19633 | 1267 | return rtl_readphy(tp, location); |
ccdffb9a FR |
1268 | } |
1269 | ||
ffc46952 FR |
1270 | DECLARE_RTL_COND(rtl_ephyar_cond) |
1271 | { | |
1272 | void __iomem *ioaddr = tp->mmio_addr; | |
1273 | ||
1274 | return RTL_R32(EPHYAR) & EPHYAR_FLAG; | |
1275 | } | |
1276 | ||
fdf6fc06 | 1277 | static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value) |
dacf8154 | 1278 | { |
fdf6fc06 | 1279 | void __iomem *ioaddr = tp->mmio_addr; |
dacf8154 FR |
1280 | |
1281 | RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | | |
1282 | (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); | |
1283 | ||
ffc46952 FR |
1284 | rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100); |
1285 | ||
1286 | udelay(10); | |
dacf8154 FR |
1287 | } |
1288 | ||
fdf6fc06 | 1289 | static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr) |
dacf8154 | 1290 | { |
fdf6fc06 | 1291 | void __iomem *ioaddr = tp->mmio_addr; |
dacf8154 FR |
1292 | |
1293 | RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); | |
1294 | ||
ffc46952 FR |
1295 | return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ? |
1296 | RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0; | |
dacf8154 FR |
1297 | } |
1298 | ||
fdf6fc06 FR |
1299 | static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, |
1300 | u32 val, int type) | |
133ac40a | 1301 | { |
fdf6fc06 | 1302 | void __iomem *ioaddr = tp->mmio_addr; |
133ac40a HW |
1303 | |
1304 | BUG_ON((addr & 3) || (mask == 0)); | |
1305 | RTL_W32(ERIDR, val); | |
1306 | RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr); | |
1307 | ||
ffc46952 | 1308 | rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100); |
133ac40a HW |
1309 | } |
1310 | ||
fdf6fc06 | 1311 | static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type) |
133ac40a | 1312 | { |
fdf6fc06 | 1313 | void __iomem *ioaddr = tp->mmio_addr; |
133ac40a HW |
1314 | |
1315 | RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr); | |
1316 | ||
ffc46952 FR |
1317 | return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ? |
1318 | RTL_R32(ERIDR) : ~0; | |
133ac40a HW |
1319 | } |
1320 | ||
fdf6fc06 FR |
1321 | static void rtl_w1w0_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p, |
1322 | u32 m, int type) | |
133ac40a HW |
1323 | { |
1324 | u32 val; | |
1325 | ||
fdf6fc06 FR |
1326 | val = rtl_eri_read(tp, addr, type); |
1327 | rtl_eri_write(tp, addr, mask, (val & ~m) | p, type); | |
133ac40a HW |
1328 | } |
1329 | ||
c28aa385 | 1330 | struct exgmac_reg { |
1331 | u16 addr; | |
1332 | u16 mask; | |
1333 | u32 val; | |
1334 | }; | |
1335 | ||
fdf6fc06 | 1336 | static void rtl_write_exgmac_batch(struct rtl8169_private *tp, |
c28aa385 | 1337 | const struct exgmac_reg *r, int len) |
1338 | { | |
1339 | while (len-- > 0) { | |
fdf6fc06 | 1340 | rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC); |
c28aa385 | 1341 | r++; |
1342 | } | |
1343 | } | |
1344 | ||
ffc46952 FR |
1345 | DECLARE_RTL_COND(rtl_efusear_cond) |
1346 | { | |
1347 | void __iomem *ioaddr = tp->mmio_addr; | |
1348 | ||
1349 | return RTL_R32(EFUSEAR) & EFUSEAR_FLAG; | |
1350 | } | |
1351 | ||
fdf6fc06 | 1352 | static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr) |
daf9df6d | 1353 | { |
fdf6fc06 | 1354 | void __iomem *ioaddr = tp->mmio_addr; |
daf9df6d | 1355 | |
1356 | RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); | |
1357 | ||
ffc46952 FR |
1358 | return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ? |
1359 | RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK : ~0; | |
daf9df6d | 1360 | } |
1361 | ||
9085cdfa FR |
1362 | static u16 rtl_get_events(struct rtl8169_private *tp) |
1363 | { | |
1364 | void __iomem *ioaddr = tp->mmio_addr; | |
1365 | ||
1366 | return RTL_R16(IntrStatus); | |
1367 | } | |
1368 | ||
1369 | static void rtl_ack_events(struct rtl8169_private *tp, u16 bits) | |
1370 | { | |
1371 | void __iomem *ioaddr = tp->mmio_addr; | |
1372 | ||
1373 | RTL_W16(IntrStatus, bits); | |
1374 | mmiowb(); | |
1375 | } | |
1376 | ||
1377 | static void rtl_irq_disable(struct rtl8169_private *tp) | |
1378 | { | |
1379 | void __iomem *ioaddr = tp->mmio_addr; | |
1380 | ||
1381 | RTL_W16(IntrMask, 0); | |
1382 | mmiowb(); | |
1383 | } | |
1384 | ||
3e990ff5 FR |
1385 | static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits) |
1386 | { | |
1387 | void __iomem *ioaddr = tp->mmio_addr; | |
1388 | ||
1389 | RTL_W16(IntrMask, bits); | |
1390 | } | |
1391 | ||
da78dbff FR |
1392 | #define RTL_EVENT_NAPI_RX (RxOK | RxErr) |
1393 | #define RTL_EVENT_NAPI_TX (TxOK | TxErr) | |
1394 | #define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX) | |
1395 | ||
1396 | static void rtl_irq_enable_all(struct rtl8169_private *tp) | |
1397 | { | |
1398 | rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow); | |
1399 | } | |
1400 | ||
811fd301 | 1401 | static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp) |
1da177e4 | 1402 | { |
811fd301 | 1403 | void __iomem *ioaddr = tp->mmio_addr; |
1da177e4 | 1404 | |
9085cdfa | 1405 | rtl_irq_disable(tp); |
da78dbff | 1406 | rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow); |
811fd301 | 1407 | RTL_R8(ChipCmd); |
1da177e4 LT |
1408 | } |
1409 | ||
4da19633 | 1410 | static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp) |
1da177e4 | 1411 | { |
4da19633 | 1412 | void __iomem *ioaddr = tp->mmio_addr; |
1413 | ||
1da177e4 LT |
1414 | return RTL_R32(TBICSR) & TBIReset; |
1415 | } | |
1416 | ||
4da19633 | 1417 | static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp) |
1da177e4 | 1418 | { |
4da19633 | 1419 | return rtl_readphy(tp, MII_BMCR) & BMCR_RESET; |
1da177e4 LT |
1420 | } |
1421 | ||
1422 | static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr) | |
1423 | { | |
1424 | return RTL_R32(TBICSR) & TBILinkOk; | |
1425 | } | |
1426 | ||
1427 | static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr) | |
1428 | { | |
1429 | return RTL_R8(PHYstatus) & LinkStatus; | |
1430 | } | |
1431 | ||
4da19633 | 1432 | static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp) |
1da177e4 | 1433 | { |
4da19633 | 1434 | void __iomem *ioaddr = tp->mmio_addr; |
1435 | ||
1da177e4 LT |
1436 | RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset); |
1437 | } | |
1438 | ||
4da19633 | 1439 | static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp) |
1da177e4 LT |
1440 | { |
1441 | unsigned int val; | |
1442 | ||
4da19633 | 1443 | val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET; |
1444 | rtl_writephy(tp, MII_BMCR, val & 0xffff); | |
1da177e4 LT |
1445 | } |
1446 | ||
70090424 HW |
1447 | static void rtl_link_chg_patch(struct rtl8169_private *tp) |
1448 | { | |
1449 | void __iomem *ioaddr = tp->mmio_addr; | |
1450 | struct net_device *dev = tp->dev; | |
1451 | ||
1452 | if (!netif_running(dev)) | |
1453 | return; | |
1454 | ||
b3d7b2f2 HW |
1455 | if (tp->mac_version == RTL_GIGA_MAC_VER_34 || |
1456 | tp->mac_version == RTL_GIGA_MAC_VER_38) { | |
70090424 | 1457 | if (RTL_R8(PHYstatus) & _1000bpsF) { |
fdf6fc06 FR |
1458 | rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011, |
1459 | ERIAR_EXGMAC); | |
1460 | rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005, | |
1461 | ERIAR_EXGMAC); | |
70090424 | 1462 | } else if (RTL_R8(PHYstatus) & _100bps) { |
fdf6fc06 FR |
1463 | rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f, |
1464 | ERIAR_EXGMAC); | |
1465 | rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005, | |
1466 | ERIAR_EXGMAC); | |
70090424 | 1467 | } else { |
fdf6fc06 FR |
1468 | rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f, |
1469 | ERIAR_EXGMAC); | |
1470 | rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f, | |
1471 | ERIAR_EXGMAC); | |
70090424 HW |
1472 | } |
1473 | /* Reset packet filter */ | |
fdf6fc06 | 1474 | rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, |
70090424 | 1475 | ERIAR_EXGMAC); |
fdf6fc06 | 1476 | rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, |
70090424 | 1477 | ERIAR_EXGMAC); |
c2218925 HW |
1478 | } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 || |
1479 | tp->mac_version == RTL_GIGA_MAC_VER_36) { | |
1480 | if (RTL_R8(PHYstatus) & _1000bpsF) { | |
fdf6fc06 FR |
1481 | rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011, |
1482 | ERIAR_EXGMAC); | |
1483 | rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005, | |
1484 | ERIAR_EXGMAC); | |
c2218925 | 1485 | } else { |
fdf6fc06 FR |
1486 | rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f, |
1487 | ERIAR_EXGMAC); | |
1488 | rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f, | |
1489 | ERIAR_EXGMAC); | |
c2218925 | 1490 | } |
7e18dca1 HW |
1491 | } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) { |
1492 | if (RTL_R8(PHYstatus) & _10bps) { | |
fdf6fc06 FR |
1493 | rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02, |
1494 | ERIAR_EXGMAC); | |
1495 | rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060, | |
1496 | ERIAR_EXGMAC); | |
7e18dca1 | 1497 | } else { |
fdf6fc06 FR |
1498 | rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, |
1499 | ERIAR_EXGMAC); | |
7e18dca1 | 1500 | } |
70090424 HW |
1501 | } |
1502 | } | |
1503 | ||
e4fbce74 | 1504 | static void __rtl8169_check_link_status(struct net_device *dev, |
cecb5fd7 FR |
1505 | struct rtl8169_private *tp, |
1506 | void __iomem *ioaddr, bool pm) | |
1da177e4 | 1507 | { |
1da177e4 | 1508 | if (tp->link_ok(ioaddr)) { |
70090424 | 1509 | rtl_link_chg_patch(tp); |
e1759441 | 1510 | /* This is to cancel a scheduled suspend if there's one. */ |
e4fbce74 RW |
1511 | if (pm) |
1512 | pm_request_resume(&tp->pci_dev->dev); | |
1da177e4 | 1513 | netif_carrier_on(dev); |
1519e57f FR |
1514 | if (net_ratelimit()) |
1515 | netif_info(tp, ifup, dev, "link up\n"); | |
b57b7e5a | 1516 | } else { |
1da177e4 | 1517 | netif_carrier_off(dev); |
bf82c189 | 1518 | netif_info(tp, ifdown, dev, "link down\n"); |
e4fbce74 | 1519 | if (pm) |
10953db8 | 1520 | pm_schedule_suspend(&tp->pci_dev->dev, 5000); |
b57b7e5a | 1521 | } |
1da177e4 LT |
1522 | } |
1523 | ||
e4fbce74 RW |
1524 | static void rtl8169_check_link_status(struct net_device *dev, |
1525 | struct rtl8169_private *tp, | |
1526 | void __iomem *ioaddr) | |
1527 | { | |
1528 | __rtl8169_check_link_status(dev, tp, ioaddr, false); | |
1529 | } | |
1530 | ||
e1759441 RW |
1531 | #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) |
1532 | ||
1533 | static u32 __rtl8169_get_wol(struct rtl8169_private *tp) | |
61a4dcc2 | 1534 | { |
61a4dcc2 FR |
1535 | void __iomem *ioaddr = tp->mmio_addr; |
1536 | u8 options; | |
e1759441 | 1537 | u32 wolopts = 0; |
61a4dcc2 FR |
1538 | |
1539 | options = RTL_R8(Config1); | |
1540 | if (!(options & PMEnable)) | |
e1759441 | 1541 | return 0; |
61a4dcc2 FR |
1542 | |
1543 | options = RTL_R8(Config3); | |
1544 | if (options & LinkUp) | |
e1759441 | 1545 | wolopts |= WAKE_PHY; |
6e1d0b89 CHL |
1546 | switch (tp->mac_version) { |
1547 | case RTL_GIGA_MAC_VER_45: | |
1548 | case RTL_GIGA_MAC_VER_46: | |
1549 | if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2) | |
1550 | wolopts |= WAKE_MAGIC; | |
1551 | break; | |
1552 | default: | |
1553 | if (options & MagicPacket) | |
1554 | wolopts |= WAKE_MAGIC; | |
1555 | break; | |
1556 | } | |
61a4dcc2 FR |
1557 | |
1558 | options = RTL_R8(Config5); | |
1559 | if (options & UWF) | |
e1759441 | 1560 | wolopts |= WAKE_UCAST; |
61a4dcc2 | 1561 | if (options & BWF) |
e1759441 | 1562 | wolopts |= WAKE_BCAST; |
61a4dcc2 | 1563 | if (options & MWF) |
e1759441 | 1564 | wolopts |= WAKE_MCAST; |
61a4dcc2 | 1565 | |
e1759441 | 1566 | return wolopts; |
61a4dcc2 FR |
1567 | } |
1568 | ||
e1759441 | 1569 | static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
61a4dcc2 FR |
1570 | { |
1571 | struct rtl8169_private *tp = netdev_priv(dev); | |
e1759441 | 1572 | |
da78dbff | 1573 | rtl_lock_work(tp); |
e1759441 RW |
1574 | |
1575 | wol->supported = WAKE_ANY; | |
1576 | wol->wolopts = __rtl8169_get_wol(tp); | |
1577 | ||
da78dbff | 1578 | rtl_unlock_work(tp); |
e1759441 RW |
1579 | } |
1580 | ||
1581 | static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) | |
1582 | { | |
61a4dcc2 | 1583 | void __iomem *ioaddr = tp->mmio_addr; |
6e1d0b89 | 1584 | unsigned int i, tmp; |
350f7596 | 1585 | static const struct { |
61a4dcc2 FR |
1586 | u32 opt; |
1587 | u16 reg; | |
1588 | u8 mask; | |
1589 | } cfg[] = { | |
61a4dcc2 | 1590 | { WAKE_PHY, Config3, LinkUp }, |
61a4dcc2 FR |
1591 | { WAKE_UCAST, Config5, UWF }, |
1592 | { WAKE_BCAST, Config5, BWF }, | |
1593 | { WAKE_MCAST, Config5, MWF }, | |
6e1d0b89 CHL |
1594 | { WAKE_ANY, Config5, LanWake }, |
1595 | { WAKE_MAGIC, Config3, MagicPacket } | |
61a4dcc2 | 1596 | }; |
851e6022 | 1597 | u8 options; |
61a4dcc2 | 1598 | |
61a4dcc2 FR |
1599 | RTL_W8(Cfg9346, Cfg9346_Unlock); |
1600 | ||
6e1d0b89 CHL |
1601 | switch (tp->mac_version) { |
1602 | case RTL_GIGA_MAC_VER_45: | |
1603 | case RTL_GIGA_MAC_VER_46: | |
1604 | tmp = ARRAY_SIZE(cfg) - 1; | |
1605 | if (wolopts & WAKE_MAGIC) | |
1606 | rtl_w1w0_eri(tp, | |
1607 | 0x0dc, | |
1608 | ERIAR_MASK_0100, | |
1609 | MagicPacket_v2, | |
1610 | 0x0000, | |
1611 | ERIAR_EXGMAC); | |
1612 | else | |
1613 | rtl_w1w0_eri(tp, | |
1614 | 0x0dc, | |
1615 | ERIAR_MASK_0100, | |
1616 | 0x0000, | |
1617 | MagicPacket_v2, | |
1618 | ERIAR_EXGMAC); | |
1619 | break; | |
1620 | default: | |
1621 | tmp = ARRAY_SIZE(cfg); | |
1622 | break; | |
1623 | } | |
1624 | ||
1625 | for (i = 0; i < tmp; i++) { | |
851e6022 | 1626 | options = RTL_R8(cfg[i].reg) & ~cfg[i].mask; |
e1759441 | 1627 | if (wolopts & cfg[i].opt) |
61a4dcc2 FR |
1628 | options |= cfg[i].mask; |
1629 | RTL_W8(cfg[i].reg, options); | |
1630 | } | |
1631 | ||
851e6022 FR |
1632 | switch (tp->mac_version) { |
1633 | case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17: | |
1634 | options = RTL_R8(Config1) & ~PMEnable; | |
1635 | if (wolopts) | |
1636 | options |= PMEnable; | |
1637 | RTL_W8(Config1, options); | |
1638 | break; | |
1639 | default: | |
d387b427 FR |
1640 | options = RTL_R8(Config2) & ~PME_SIGNAL; |
1641 | if (wolopts) | |
1642 | options |= PME_SIGNAL; | |
1643 | RTL_W8(Config2, options); | |
851e6022 FR |
1644 | break; |
1645 | } | |
1646 | ||
61a4dcc2 | 1647 | RTL_W8(Cfg9346, Cfg9346_Lock); |
e1759441 RW |
1648 | } |
1649 | ||
1650 | static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
1651 | { | |
1652 | struct rtl8169_private *tp = netdev_priv(dev); | |
1653 | ||
da78dbff | 1654 | rtl_lock_work(tp); |
61a4dcc2 | 1655 | |
f23e7fda FR |
1656 | if (wol->wolopts) |
1657 | tp->features |= RTL_FEATURE_WOL; | |
1658 | else | |
1659 | tp->features &= ~RTL_FEATURE_WOL; | |
e1759441 | 1660 | __rtl8169_set_wol(tp, wol->wolopts); |
da78dbff FR |
1661 | |
1662 | rtl_unlock_work(tp); | |
61a4dcc2 | 1663 | |
ea80907f | 1664 | device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts); |
1665 | ||
61a4dcc2 FR |
1666 | return 0; |
1667 | } | |
1668 | ||
31bd204f FR |
1669 | static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp) |
1670 | { | |
85bffe6c | 1671 | return rtl_chip_infos[tp->mac_version].fw_name; |
31bd204f FR |
1672 | } |
1673 | ||
1da177e4 LT |
1674 | static void rtl8169_get_drvinfo(struct net_device *dev, |
1675 | struct ethtool_drvinfo *info) | |
1676 | { | |
1677 | struct rtl8169_private *tp = netdev_priv(dev); | |
b6ffd97f | 1678 | struct rtl_fw *rtl_fw = tp->rtl_fw; |
1da177e4 | 1679 | |
68aad78c RJ |
1680 | strlcpy(info->driver, MODULENAME, sizeof(info->driver)); |
1681 | strlcpy(info->version, RTL8169_VERSION, sizeof(info->version)); | |
1682 | strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info)); | |
1c361efb | 1683 | BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version)); |
8ac72d16 RJ |
1684 | if (!IS_ERR_OR_NULL(rtl_fw)) |
1685 | strlcpy(info->fw_version, rtl_fw->version, | |
1686 | sizeof(info->fw_version)); | |
1da177e4 LT |
1687 | } |
1688 | ||
1689 | static int rtl8169_get_regs_len(struct net_device *dev) | |
1690 | { | |
1691 | return R8169_REGS_SIZE; | |
1692 | } | |
1693 | ||
1694 | static int rtl8169_set_speed_tbi(struct net_device *dev, | |
54405cde | 1695 | u8 autoneg, u16 speed, u8 duplex, u32 ignored) |
1da177e4 LT |
1696 | { |
1697 | struct rtl8169_private *tp = netdev_priv(dev); | |
1698 | void __iomem *ioaddr = tp->mmio_addr; | |
1699 | int ret = 0; | |
1700 | u32 reg; | |
1701 | ||
1702 | reg = RTL_R32(TBICSR); | |
1703 | if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) && | |
1704 | (duplex == DUPLEX_FULL)) { | |
1705 | RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart)); | |
1706 | } else if (autoneg == AUTONEG_ENABLE) | |
1707 | RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart); | |
1708 | else { | |
bf82c189 JP |
1709 | netif_warn(tp, link, dev, |
1710 | "incorrect speed setting refused in TBI mode\n"); | |
1da177e4 LT |
1711 | ret = -EOPNOTSUPP; |
1712 | } | |
1713 | ||
1714 | return ret; | |
1715 | } | |
1716 | ||
1717 | static int rtl8169_set_speed_xmii(struct net_device *dev, | |
54405cde | 1718 | u8 autoneg, u16 speed, u8 duplex, u32 adv) |
1da177e4 LT |
1719 | { |
1720 | struct rtl8169_private *tp = netdev_priv(dev); | |
3577aa1b | 1721 | int giga_ctrl, bmcr; |
54405cde | 1722 | int rc = -EINVAL; |
1da177e4 | 1723 | |
716b50a3 | 1724 | rtl_writephy(tp, 0x1f, 0x0000); |
1da177e4 LT |
1725 | |
1726 | if (autoneg == AUTONEG_ENABLE) { | |
3577aa1b | 1727 | int auto_nego; |
1728 | ||
4da19633 | 1729 | auto_nego = rtl_readphy(tp, MII_ADVERTISE); |
54405cde ON |
1730 | auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | |
1731 | ADVERTISE_100HALF | ADVERTISE_100FULL); | |
1732 | ||
1733 | if (adv & ADVERTISED_10baseT_Half) | |
1734 | auto_nego |= ADVERTISE_10HALF; | |
1735 | if (adv & ADVERTISED_10baseT_Full) | |
1736 | auto_nego |= ADVERTISE_10FULL; | |
1737 | if (adv & ADVERTISED_100baseT_Half) | |
1738 | auto_nego |= ADVERTISE_100HALF; | |
1739 | if (adv & ADVERTISED_100baseT_Full) | |
1740 | auto_nego |= ADVERTISE_100FULL; | |
1741 | ||
3577aa1b | 1742 | auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; |
1da177e4 | 1743 | |
4da19633 | 1744 | giga_ctrl = rtl_readphy(tp, MII_CTRL1000); |
3577aa1b | 1745 | giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); |
bcf0bf90 | 1746 | |
3577aa1b | 1747 | /* The 8100e/8101e/8102e do Fast Ethernet only. */ |
826e6cbd | 1748 | if (tp->mii.supports_gmii) { |
54405cde ON |
1749 | if (adv & ADVERTISED_1000baseT_Half) |
1750 | giga_ctrl |= ADVERTISE_1000HALF; | |
1751 | if (adv & ADVERTISED_1000baseT_Full) | |
1752 | giga_ctrl |= ADVERTISE_1000FULL; | |
1753 | } else if (adv & (ADVERTISED_1000baseT_Half | | |
1754 | ADVERTISED_1000baseT_Full)) { | |
bf82c189 JP |
1755 | netif_info(tp, link, dev, |
1756 | "PHY does not support 1000Mbps\n"); | |
54405cde | 1757 | goto out; |
bcf0bf90 | 1758 | } |
1da177e4 | 1759 | |
3577aa1b | 1760 | bmcr = BMCR_ANENABLE | BMCR_ANRESTART; |
1761 | ||
4da19633 | 1762 | rtl_writephy(tp, MII_ADVERTISE, auto_nego); |
1763 | rtl_writephy(tp, MII_CTRL1000, giga_ctrl); | |
3577aa1b | 1764 | } else { |
1765 | giga_ctrl = 0; | |
1766 | ||
1767 | if (speed == SPEED_10) | |
1768 | bmcr = 0; | |
1769 | else if (speed == SPEED_100) | |
1770 | bmcr = BMCR_SPEED100; | |
1771 | else | |
54405cde | 1772 | goto out; |
3577aa1b | 1773 | |
1774 | if (duplex == DUPLEX_FULL) | |
1775 | bmcr |= BMCR_FULLDPLX; | |
2584fbc3 RS |
1776 | } |
1777 | ||
4da19633 | 1778 | rtl_writephy(tp, MII_BMCR, bmcr); |
3577aa1b | 1779 | |
cecb5fd7 FR |
1780 | if (tp->mac_version == RTL_GIGA_MAC_VER_02 || |
1781 | tp->mac_version == RTL_GIGA_MAC_VER_03) { | |
3577aa1b | 1782 | if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) { |
4da19633 | 1783 | rtl_writephy(tp, 0x17, 0x2138); |
1784 | rtl_writephy(tp, 0x0e, 0x0260); | |
3577aa1b | 1785 | } else { |
4da19633 | 1786 | rtl_writephy(tp, 0x17, 0x2108); |
1787 | rtl_writephy(tp, 0x0e, 0x0000); | |
3577aa1b | 1788 | } |
1789 | } | |
1790 | ||
54405cde ON |
1791 | rc = 0; |
1792 | out: | |
1793 | return rc; | |
1da177e4 LT |
1794 | } |
1795 | ||
1796 | static int rtl8169_set_speed(struct net_device *dev, | |
54405cde | 1797 | u8 autoneg, u16 speed, u8 duplex, u32 advertising) |
1da177e4 LT |
1798 | { |
1799 | struct rtl8169_private *tp = netdev_priv(dev); | |
1800 | int ret; | |
1801 | ||
54405cde | 1802 | ret = tp->set_speed(dev, autoneg, speed, duplex, advertising); |
4876cc1e FR |
1803 | if (ret < 0) |
1804 | goto out; | |
1da177e4 | 1805 | |
4876cc1e FR |
1806 | if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) && |
1807 | (advertising & ADVERTISED_1000baseT_Full)) { | |
1da177e4 | 1808 | mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT); |
4876cc1e FR |
1809 | } |
1810 | out: | |
1da177e4 LT |
1811 | return ret; |
1812 | } | |
1813 | ||
1814 | static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1815 | { | |
1816 | struct rtl8169_private *tp = netdev_priv(dev); | |
1da177e4 LT |
1817 | int ret; |
1818 | ||
4876cc1e FR |
1819 | del_timer_sync(&tp->timer); |
1820 | ||
da78dbff | 1821 | rtl_lock_work(tp); |
cecb5fd7 | 1822 | ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd), |
25db0338 | 1823 | cmd->duplex, cmd->advertising); |
da78dbff | 1824 | rtl_unlock_work(tp); |
5b0384f4 | 1825 | |
1da177e4 LT |
1826 | return ret; |
1827 | } | |
1828 | ||
c8f44aff MM |
1829 | static netdev_features_t rtl8169_fix_features(struct net_device *dev, |
1830 | netdev_features_t features) | |
1da177e4 | 1831 | { |
d58d46b5 FR |
1832 | struct rtl8169_private *tp = netdev_priv(dev); |
1833 | ||
2b7b4318 | 1834 | if (dev->mtu > TD_MSS_MAX) |
350fb32a | 1835 | features &= ~NETIF_F_ALL_TSO; |
1da177e4 | 1836 | |
d58d46b5 FR |
1837 | if (dev->mtu > JUMBO_1K && |
1838 | !rtl_chip_infos[tp->mac_version].jumbo_tx_csum) | |
1839 | features &= ~NETIF_F_IP_CSUM; | |
1840 | ||
350fb32a | 1841 | return features; |
1da177e4 LT |
1842 | } |
1843 | ||
da78dbff FR |
1844 | static void __rtl8169_set_features(struct net_device *dev, |
1845 | netdev_features_t features) | |
1da177e4 LT |
1846 | { |
1847 | struct rtl8169_private *tp = netdev_priv(dev); | |
6bbe021d | 1848 | netdev_features_t changed = features ^ dev->features; |
da78dbff | 1849 | void __iomem *ioaddr = tp->mmio_addr; |
1da177e4 | 1850 | |
f646968f PM |
1851 | if (!(changed & (NETIF_F_RXALL | NETIF_F_RXCSUM | |
1852 | NETIF_F_HW_VLAN_CTAG_RX))) | |
6bbe021d | 1853 | return; |
1da177e4 | 1854 | |
f646968f | 1855 | if (changed & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX)) { |
6bbe021d BG |
1856 | if (features & NETIF_F_RXCSUM) |
1857 | tp->cp_cmd |= RxChkSum; | |
1858 | else | |
1859 | tp->cp_cmd &= ~RxChkSum; | |
350fb32a | 1860 | |
f646968f | 1861 | if (dev->features & NETIF_F_HW_VLAN_CTAG_RX) |
6bbe021d BG |
1862 | tp->cp_cmd |= RxVlan; |
1863 | else | |
1864 | tp->cp_cmd &= ~RxVlan; | |
1865 | ||
1866 | RTL_W16(CPlusCmd, tp->cp_cmd); | |
1867 | RTL_R16(CPlusCmd); | |
1868 | } | |
1869 | if (changed & NETIF_F_RXALL) { | |
1870 | int tmp = (RTL_R32(RxConfig) & ~(AcceptErr | AcceptRunt)); | |
1871 | if (features & NETIF_F_RXALL) | |
1872 | tmp |= (AcceptErr | AcceptRunt); | |
1873 | RTL_W32(RxConfig, tmp); | |
1874 | } | |
da78dbff | 1875 | } |
1da177e4 | 1876 | |
da78dbff FR |
1877 | static int rtl8169_set_features(struct net_device *dev, |
1878 | netdev_features_t features) | |
1879 | { | |
1880 | struct rtl8169_private *tp = netdev_priv(dev); | |
1881 | ||
1882 | rtl_lock_work(tp); | |
1883 | __rtl8169_set_features(dev, features); | |
1884 | rtl_unlock_work(tp); | |
1da177e4 LT |
1885 | |
1886 | return 0; | |
1887 | } | |
1888 | ||
da78dbff | 1889 | |
810f4893 | 1890 | static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb) |
1da177e4 | 1891 | { |
eab6d18d | 1892 | return (vlan_tx_tag_present(skb)) ? |
1da177e4 LT |
1893 | TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00; |
1894 | } | |
1895 | ||
7a8fc77b | 1896 | static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb) |
1da177e4 LT |
1897 | { |
1898 | u32 opts2 = le32_to_cpu(desc->opts2); | |
1da177e4 | 1899 | |
7a8fc77b | 1900 | if (opts2 & RxVlanTag) |
86a9bad3 | 1901 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff)); |
1da177e4 LT |
1902 | } |
1903 | ||
ccdffb9a | 1904 | static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd) |
1da177e4 LT |
1905 | { |
1906 | struct rtl8169_private *tp = netdev_priv(dev); | |
1907 | void __iomem *ioaddr = tp->mmio_addr; | |
1908 | u32 status; | |
1909 | ||
1910 | cmd->supported = | |
1911 | SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE; | |
1912 | cmd->port = PORT_FIBRE; | |
1913 | cmd->transceiver = XCVR_INTERNAL; | |
1914 | ||
1915 | status = RTL_R32(TBICSR); | |
1916 | cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0; | |
1917 | cmd->autoneg = !!(status & TBINwEnable); | |
1918 | ||
70739497 | 1919 | ethtool_cmd_speed_set(cmd, SPEED_1000); |
1da177e4 | 1920 | cmd->duplex = DUPLEX_FULL; /* Always set */ |
ccdffb9a FR |
1921 | |
1922 | return 0; | |
1da177e4 LT |
1923 | } |
1924 | ||
ccdffb9a | 1925 | static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd) |
1da177e4 LT |
1926 | { |
1927 | struct rtl8169_private *tp = netdev_priv(dev); | |
ccdffb9a FR |
1928 | |
1929 | return mii_ethtool_gset(&tp->mii, cmd); | |
1da177e4 LT |
1930 | } |
1931 | ||
1932 | static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1933 | { | |
1934 | struct rtl8169_private *tp = netdev_priv(dev); | |
ccdffb9a | 1935 | int rc; |
1da177e4 | 1936 | |
da78dbff | 1937 | rtl_lock_work(tp); |
ccdffb9a | 1938 | rc = tp->get_settings(dev, cmd); |
da78dbff | 1939 | rtl_unlock_work(tp); |
1da177e4 | 1940 | |
ccdffb9a | 1941 | return rc; |
1da177e4 LT |
1942 | } |
1943 | ||
1944 | static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, | |
1945 | void *p) | |
1946 | { | |
5b0384f4 | 1947 | struct rtl8169_private *tp = netdev_priv(dev); |
15edae91 PW |
1948 | u32 __iomem *data = tp->mmio_addr; |
1949 | u32 *dw = p; | |
1950 | int i; | |
1da177e4 | 1951 | |
da78dbff | 1952 | rtl_lock_work(tp); |
15edae91 PW |
1953 | for (i = 0; i < R8169_REGS_SIZE; i += 4) |
1954 | memcpy_fromio(dw++, data++, 4); | |
da78dbff | 1955 | rtl_unlock_work(tp); |
1da177e4 LT |
1956 | } |
1957 | ||
b57b7e5a SH |
1958 | static u32 rtl8169_get_msglevel(struct net_device *dev) |
1959 | { | |
1960 | struct rtl8169_private *tp = netdev_priv(dev); | |
1961 | ||
1962 | return tp->msg_enable; | |
1963 | } | |
1964 | ||
1965 | static void rtl8169_set_msglevel(struct net_device *dev, u32 value) | |
1966 | { | |
1967 | struct rtl8169_private *tp = netdev_priv(dev); | |
1968 | ||
1969 | tp->msg_enable = value; | |
1970 | } | |
1971 | ||
d4a3a0fc SH |
1972 | static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { |
1973 | "tx_packets", | |
1974 | "rx_packets", | |
1975 | "tx_errors", | |
1976 | "rx_errors", | |
1977 | "rx_missed", | |
1978 | "align_errors", | |
1979 | "tx_single_collisions", | |
1980 | "tx_multi_collisions", | |
1981 | "unicast", | |
1982 | "broadcast", | |
1983 | "multicast", | |
1984 | "tx_aborted", | |
1985 | "tx_underrun", | |
1986 | }; | |
1987 | ||
b9f2c044 | 1988 | static int rtl8169_get_sset_count(struct net_device *dev, int sset) |
d4a3a0fc | 1989 | { |
b9f2c044 JG |
1990 | switch (sset) { |
1991 | case ETH_SS_STATS: | |
1992 | return ARRAY_SIZE(rtl8169_gstrings); | |
1993 | default: | |
1994 | return -EOPNOTSUPP; | |
1995 | } | |
d4a3a0fc SH |
1996 | } |
1997 | ||
ffc46952 FR |
1998 | DECLARE_RTL_COND(rtl_counters_cond) |
1999 | { | |
2000 | void __iomem *ioaddr = tp->mmio_addr; | |
2001 | ||
2002 | return RTL_R32(CounterAddrLow) & CounterDump; | |
2003 | } | |
2004 | ||
355423d0 | 2005 | static void rtl8169_update_counters(struct net_device *dev) |
d4a3a0fc SH |
2006 | { |
2007 | struct rtl8169_private *tp = netdev_priv(dev); | |
2008 | void __iomem *ioaddr = tp->mmio_addr; | |
cecb5fd7 | 2009 | struct device *d = &tp->pci_dev->dev; |
d4a3a0fc SH |
2010 | struct rtl8169_counters *counters; |
2011 | dma_addr_t paddr; | |
2012 | u32 cmd; | |
2013 | ||
355423d0 IV |
2014 | /* |
2015 | * Some chips are unable to dump tally counters when the receiver | |
2016 | * is disabled. | |
2017 | */ | |
2018 | if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0) | |
2019 | return; | |
d4a3a0fc | 2020 | |
48addcc9 | 2021 | counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL); |
d4a3a0fc SH |
2022 | if (!counters) |
2023 | return; | |
2024 | ||
2025 | RTL_W32(CounterAddrHigh, (u64)paddr >> 32); | |
284901a9 | 2026 | cmd = (u64)paddr & DMA_BIT_MASK(32); |
d4a3a0fc SH |
2027 | RTL_W32(CounterAddrLow, cmd); |
2028 | RTL_W32(CounterAddrLow, cmd | CounterDump); | |
2029 | ||
ffc46952 FR |
2030 | if (rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000)) |
2031 | memcpy(&tp->counters, counters, sizeof(*counters)); | |
d4a3a0fc SH |
2032 | |
2033 | RTL_W32(CounterAddrLow, 0); | |
2034 | RTL_W32(CounterAddrHigh, 0); | |
2035 | ||
48addcc9 | 2036 | dma_free_coherent(d, sizeof(*counters), counters, paddr); |
d4a3a0fc SH |
2037 | } |
2038 | ||
355423d0 IV |
2039 | static void rtl8169_get_ethtool_stats(struct net_device *dev, |
2040 | struct ethtool_stats *stats, u64 *data) | |
2041 | { | |
2042 | struct rtl8169_private *tp = netdev_priv(dev); | |
2043 | ||
2044 | ASSERT_RTNL(); | |
2045 | ||
2046 | rtl8169_update_counters(dev); | |
2047 | ||
2048 | data[0] = le64_to_cpu(tp->counters.tx_packets); | |
2049 | data[1] = le64_to_cpu(tp->counters.rx_packets); | |
2050 | data[2] = le64_to_cpu(tp->counters.tx_errors); | |
2051 | data[3] = le32_to_cpu(tp->counters.rx_errors); | |
2052 | data[4] = le16_to_cpu(tp->counters.rx_missed); | |
2053 | data[5] = le16_to_cpu(tp->counters.align_errors); | |
2054 | data[6] = le32_to_cpu(tp->counters.tx_one_collision); | |
2055 | data[7] = le32_to_cpu(tp->counters.tx_multi_collision); | |
2056 | data[8] = le64_to_cpu(tp->counters.rx_unicast); | |
2057 | data[9] = le64_to_cpu(tp->counters.rx_broadcast); | |
2058 | data[10] = le32_to_cpu(tp->counters.rx_multicast); | |
2059 | data[11] = le16_to_cpu(tp->counters.tx_aborted); | |
2060 | data[12] = le16_to_cpu(tp->counters.tx_underun); | |
2061 | } | |
2062 | ||
d4a3a0fc SH |
2063 | static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) |
2064 | { | |
2065 | switch(stringset) { | |
2066 | case ETH_SS_STATS: | |
2067 | memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings)); | |
2068 | break; | |
2069 | } | |
2070 | } | |
2071 | ||
7282d491 | 2072 | static const struct ethtool_ops rtl8169_ethtool_ops = { |
1da177e4 LT |
2073 | .get_drvinfo = rtl8169_get_drvinfo, |
2074 | .get_regs_len = rtl8169_get_regs_len, | |
2075 | .get_link = ethtool_op_get_link, | |
2076 | .get_settings = rtl8169_get_settings, | |
2077 | .set_settings = rtl8169_set_settings, | |
b57b7e5a SH |
2078 | .get_msglevel = rtl8169_get_msglevel, |
2079 | .set_msglevel = rtl8169_set_msglevel, | |
1da177e4 | 2080 | .get_regs = rtl8169_get_regs, |
61a4dcc2 FR |
2081 | .get_wol = rtl8169_get_wol, |
2082 | .set_wol = rtl8169_set_wol, | |
d4a3a0fc | 2083 | .get_strings = rtl8169_get_strings, |
b9f2c044 | 2084 | .get_sset_count = rtl8169_get_sset_count, |
d4a3a0fc | 2085 | .get_ethtool_stats = rtl8169_get_ethtool_stats, |
e1593bb1 | 2086 | .get_ts_info = ethtool_op_get_ts_info, |
1da177e4 LT |
2087 | }; |
2088 | ||
07d3f51f | 2089 | static void rtl8169_get_mac_version(struct rtl8169_private *tp, |
5d320a20 | 2090 | struct net_device *dev, u8 default_version) |
1da177e4 | 2091 | { |
5d320a20 | 2092 | void __iomem *ioaddr = tp->mmio_addr; |
0e485150 FR |
2093 | /* |
2094 | * The driver currently handles the 8168Bf and the 8168Be identically | |
2095 | * but they can be identified more specifically through the test below | |
2096 | * if needed: | |
2097 | * | |
2098 | * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be | |
0127215c FR |
2099 | * |
2100 | * Same thing for the 8101Eb and the 8101Ec: | |
2101 | * | |
2102 | * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec | |
0e485150 | 2103 | */ |
3744100e | 2104 | static const struct rtl_mac_info { |
1da177e4 | 2105 | u32 mask; |
e3cf0cc0 | 2106 | u32 val; |
1da177e4 LT |
2107 | int mac_version; |
2108 | } mac_info[] = { | |
6e1d0b89 CHL |
2109 | /* 8168H family. */ |
2110 | { 0x7cf00000, 0x54100000, RTL_GIGA_MAC_VER_46 }, | |
2111 | { 0x7cf00000, 0x54000000, RTL_GIGA_MAC_VER_45 }, | |
2112 | ||
c558386b | 2113 | /* 8168G family. */ |
45dd95c4 | 2114 | { 0x7cf00000, 0x5c800000, RTL_GIGA_MAC_VER_44 }, |
57538c4a | 2115 | { 0x7cf00000, 0x50900000, RTL_GIGA_MAC_VER_42 }, |
c558386b HW |
2116 | { 0x7cf00000, 0x4c100000, RTL_GIGA_MAC_VER_41 }, |
2117 | { 0x7cf00000, 0x4c000000, RTL_GIGA_MAC_VER_40 }, | |
2118 | ||
c2218925 | 2119 | /* 8168F family. */ |
b3d7b2f2 | 2120 | { 0x7c800000, 0x48800000, RTL_GIGA_MAC_VER_38 }, |
c2218925 HW |
2121 | { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 }, |
2122 | { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 }, | |
2123 | ||
01dc7fec | 2124 | /* 8168E family. */ |
70090424 | 2125 | { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 }, |
01dc7fec | 2126 | { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 }, |
2127 | { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 }, | |
2128 | { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 }, | |
2129 | ||
5b538df9 | 2130 | /* 8168D family. */ |
daf9df6d | 2131 | { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 }, |
2132 | { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 }, | |
daf9df6d | 2133 | { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 }, |
5b538df9 | 2134 | |
e6de30d6 | 2135 | /* 8168DP family. */ |
2136 | { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 }, | |
2137 | { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 }, | |
4804b3b3 | 2138 | { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 }, |
e6de30d6 | 2139 | |
ef808d50 | 2140 | /* 8168C family. */ |
17c99297 | 2141 | { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 }, |
ef3386f0 | 2142 | { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 }, |
ef808d50 | 2143 | { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 }, |
7f3e3d3a | 2144 | { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 }, |
e3cf0cc0 FR |
2145 | { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 }, |
2146 | { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 }, | |
197ff761 | 2147 | { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 }, |
6fb07058 | 2148 | { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 }, |
ef808d50 | 2149 | { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 }, |
e3cf0cc0 FR |
2150 | |
2151 | /* 8168B family. */ | |
2152 | { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 }, | |
2153 | { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 }, | |
2154 | { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 }, | |
2155 | { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 }, | |
2156 | ||
2157 | /* 8101 family. */ | |
5598bfe5 HW |
2158 | { 0x7cf00000, 0x44900000, RTL_GIGA_MAC_VER_39 }, |
2159 | { 0x7c800000, 0x44800000, RTL_GIGA_MAC_VER_39 }, | |
7e18dca1 | 2160 | { 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37 }, |
36a0e6c2 | 2161 | { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 }, |
5a5e4443 HW |
2162 | { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 }, |
2163 | { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 }, | |
2164 | { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 }, | |
2857ffb7 FR |
2165 | { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 }, |
2166 | { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 }, | |
2167 | { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 }, | |
2168 | { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 }, | |
2169 | { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 }, | |
2170 | { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 }, | |
e3cf0cc0 | 2171 | { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 }, |
2857ffb7 | 2172 | { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 }, |
e3cf0cc0 | 2173 | { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 }, |
2857ffb7 FR |
2174 | { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 }, |
2175 | { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 }, | |
e3cf0cc0 FR |
2176 | { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 }, |
2177 | /* FIXME: where did these entries come from ? -- FR */ | |
2178 | { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 }, | |
2179 | { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 }, | |
2180 | ||
2181 | /* 8110 family. */ | |
2182 | { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 }, | |
2183 | { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 }, | |
2184 | { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 }, | |
2185 | { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 }, | |
2186 | { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 }, | |
2187 | { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 }, | |
2188 | ||
f21b75e9 JD |
2189 | /* Catch-all */ |
2190 | { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE } | |
3744100e FR |
2191 | }; |
2192 | const struct rtl_mac_info *p = mac_info; | |
1da177e4 LT |
2193 | u32 reg; |
2194 | ||
e3cf0cc0 FR |
2195 | reg = RTL_R32(TxConfig); |
2196 | while ((reg & p->mask) != p->val) | |
1da177e4 LT |
2197 | p++; |
2198 | tp->mac_version = p->mac_version; | |
5d320a20 FR |
2199 | |
2200 | if (tp->mac_version == RTL_GIGA_MAC_NONE) { | |
2201 | netif_notice(tp, probe, dev, | |
2202 | "unknown MAC, using family default\n"); | |
2203 | tp->mac_version = default_version; | |
58152cd4 | 2204 | } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) { |
2205 | tp->mac_version = tp->mii.supports_gmii ? | |
2206 | RTL_GIGA_MAC_VER_42 : | |
2207 | RTL_GIGA_MAC_VER_43; | |
6e1d0b89 CHL |
2208 | } else if (tp->mac_version == RTL_GIGA_MAC_VER_45) { |
2209 | tp->mac_version = tp->mii.supports_gmii ? | |
2210 | RTL_GIGA_MAC_VER_45 : | |
2211 | RTL_GIGA_MAC_VER_47; | |
2212 | } else if (tp->mac_version == RTL_GIGA_MAC_VER_46) { | |
2213 | tp->mac_version = tp->mii.supports_gmii ? | |
2214 | RTL_GIGA_MAC_VER_46 : | |
2215 | RTL_GIGA_MAC_VER_48; | |
5d320a20 | 2216 | } |
1da177e4 LT |
2217 | } |
2218 | ||
2219 | static void rtl8169_print_mac_version(struct rtl8169_private *tp) | |
2220 | { | |
bcf0bf90 | 2221 | dprintk("mac_version = 0x%02x\n", tp->mac_version); |
1da177e4 LT |
2222 | } |
2223 | ||
867763c1 FR |
2224 | struct phy_reg { |
2225 | u16 reg; | |
2226 | u16 val; | |
2227 | }; | |
2228 | ||
4da19633 | 2229 | static void rtl_writephy_batch(struct rtl8169_private *tp, |
2230 | const struct phy_reg *regs, int len) | |
867763c1 FR |
2231 | { |
2232 | while (len-- > 0) { | |
4da19633 | 2233 | rtl_writephy(tp, regs->reg, regs->val); |
867763c1 FR |
2234 | regs++; |
2235 | } | |
2236 | } | |
2237 | ||
bca03d5f | 2238 | #define PHY_READ 0x00000000 |
2239 | #define PHY_DATA_OR 0x10000000 | |
2240 | #define PHY_DATA_AND 0x20000000 | |
2241 | #define PHY_BJMPN 0x30000000 | |
eee3786f | 2242 | #define PHY_MDIO_CHG 0x40000000 |
bca03d5f | 2243 | #define PHY_CLEAR_READCOUNT 0x70000000 |
2244 | #define PHY_WRITE 0x80000000 | |
2245 | #define PHY_READCOUNT_EQ_SKIP 0x90000000 | |
2246 | #define PHY_COMP_EQ_SKIPN 0xa0000000 | |
2247 | #define PHY_COMP_NEQ_SKIPN 0xb0000000 | |
2248 | #define PHY_WRITE_PREVIOUS 0xc0000000 | |
2249 | #define PHY_SKIPN 0xd0000000 | |
2250 | #define PHY_DELAY_MS 0xe0000000 | |
bca03d5f | 2251 | |
960aee6c HW |
2252 | struct fw_info { |
2253 | u32 magic; | |
2254 | char version[RTL_VER_SIZE]; | |
2255 | __le32 fw_start; | |
2256 | __le32 fw_len; | |
2257 | u8 chksum; | |
2258 | } __packed; | |
2259 | ||
1c361efb FR |
2260 | #define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code)) |
2261 | ||
2262 | static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw) | |
bca03d5f | 2263 | { |
b6ffd97f | 2264 | const struct firmware *fw = rtl_fw->fw; |
960aee6c | 2265 | struct fw_info *fw_info = (struct fw_info *)fw->data; |
1c361efb FR |
2266 | struct rtl_fw_phy_action *pa = &rtl_fw->phy_action; |
2267 | char *version = rtl_fw->version; | |
2268 | bool rc = false; | |
2269 | ||
2270 | if (fw->size < FW_OPCODE_SIZE) | |
2271 | goto out; | |
960aee6c HW |
2272 | |
2273 | if (!fw_info->magic) { | |
2274 | size_t i, size, start; | |
2275 | u8 checksum = 0; | |
2276 | ||
2277 | if (fw->size < sizeof(*fw_info)) | |
2278 | goto out; | |
2279 | ||
2280 | for (i = 0; i < fw->size; i++) | |
2281 | checksum += fw->data[i]; | |
2282 | if (checksum != 0) | |
2283 | goto out; | |
2284 | ||
2285 | start = le32_to_cpu(fw_info->fw_start); | |
2286 | if (start > fw->size) | |
2287 | goto out; | |
2288 | ||
2289 | size = le32_to_cpu(fw_info->fw_len); | |
2290 | if (size > (fw->size - start) / FW_OPCODE_SIZE) | |
2291 | goto out; | |
2292 | ||
2293 | memcpy(version, fw_info->version, RTL_VER_SIZE); | |
2294 | ||
2295 | pa->code = (__le32 *)(fw->data + start); | |
2296 | pa->size = size; | |
2297 | } else { | |
1c361efb FR |
2298 | if (fw->size % FW_OPCODE_SIZE) |
2299 | goto out; | |
2300 | ||
2301 | strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE); | |
2302 | ||
2303 | pa->code = (__le32 *)fw->data; | |
2304 | pa->size = fw->size / FW_OPCODE_SIZE; | |
2305 | } | |
2306 | version[RTL_VER_SIZE - 1] = 0; | |
2307 | ||
2308 | rc = true; | |
2309 | out: | |
2310 | return rc; | |
2311 | } | |
2312 | ||
fd112f2e FR |
2313 | static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev, |
2314 | struct rtl_fw_phy_action *pa) | |
1c361efb | 2315 | { |
fd112f2e | 2316 | bool rc = false; |
1c361efb | 2317 | size_t index; |
bca03d5f | 2318 | |
1c361efb FR |
2319 | for (index = 0; index < pa->size; index++) { |
2320 | u32 action = le32_to_cpu(pa->code[index]); | |
42b82dc1 | 2321 | u32 regno = (action & 0x0fff0000) >> 16; |
bca03d5f | 2322 | |
42b82dc1 | 2323 | switch(action & 0xf0000000) { |
2324 | case PHY_READ: | |
2325 | case PHY_DATA_OR: | |
2326 | case PHY_DATA_AND: | |
eee3786f | 2327 | case PHY_MDIO_CHG: |
42b82dc1 | 2328 | case PHY_CLEAR_READCOUNT: |
2329 | case PHY_WRITE: | |
2330 | case PHY_WRITE_PREVIOUS: | |
2331 | case PHY_DELAY_MS: | |
2332 | break; | |
2333 | ||
2334 | case PHY_BJMPN: | |
2335 | if (regno > index) { | |
fd112f2e | 2336 | netif_err(tp, ifup, tp->dev, |
cecb5fd7 | 2337 | "Out of range of firmware\n"); |
fd112f2e | 2338 | goto out; |
42b82dc1 | 2339 | } |
2340 | break; | |
2341 | case PHY_READCOUNT_EQ_SKIP: | |
1c361efb | 2342 | if (index + 2 >= pa->size) { |
fd112f2e | 2343 | netif_err(tp, ifup, tp->dev, |
cecb5fd7 | 2344 | "Out of range of firmware\n"); |
fd112f2e | 2345 | goto out; |
42b82dc1 | 2346 | } |
2347 | break; | |
2348 | case PHY_COMP_EQ_SKIPN: | |
2349 | case PHY_COMP_NEQ_SKIPN: | |
2350 | case PHY_SKIPN: | |
1c361efb | 2351 | if (index + 1 + regno >= pa->size) { |
fd112f2e | 2352 | netif_err(tp, ifup, tp->dev, |
cecb5fd7 | 2353 | "Out of range of firmware\n"); |
fd112f2e | 2354 | goto out; |
42b82dc1 | 2355 | } |
bca03d5f | 2356 | break; |
2357 | ||
42b82dc1 | 2358 | default: |
fd112f2e | 2359 | netif_err(tp, ifup, tp->dev, |
42b82dc1 | 2360 | "Invalid action 0x%08x\n", action); |
fd112f2e | 2361 | goto out; |
bca03d5f | 2362 | } |
2363 | } | |
fd112f2e FR |
2364 | rc = true; |
2365 | out: | |
2366 | return rc; | |
2367 | } | |
bca03d5f | 2368 | |
fd112f2e FR |
2369 | static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw) |
2370 | { | |
2371 | struct net_device *dev = tp->dev; | |
2372 | int rc = -EINVAL; | |
2373 | ||
2374 | if (!rtl_fw_format_ok(tp, rtl_fw)) { | |
2375 | netif_err(tp, ifup, dev, "invalid firwmare\n"); | |
2376 | goto out; | |
2377 | } | |
2378 | ||
2379 | if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action)) | |
2380 | rc = 0; | |
2381 | out: | |
2382 | return rc; | |
2383 | } | |
2384 | ||
2385 | static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw) | |
2386 | { | |
2387 | struct rtl_fw_phy_action *pa = &rtl_fw->phy_action; | |
eee3786f | 2388 | struct mdio_ops org, *ops = &tp->mdio_ops; |
fd112f2e FR |
2389 | u32 predata, count; |
2390 | size_t index; | |
2391 | ||
2392 | predata = count = 0; | |
eee3786f | 2393 | org.write = ops->write; |
2394 | org.read = ops->read; | |
42b82dc1 | 2395 | |
1c361efb FR |
2396 | for (index = 0; index < pa->size; ) { |
2397 | u32 action = le32_to_cpu(pa->code[index]); | |
bca03d5f | 2398 | u32 data = action & 0x0000ffff; |
42b82dc1 | 2399 | u32 regno = (action & 0x0fff0000) >> 16; |
2400 | ||
2401 | if (!action) | |
2402 | break; | |
bca03d5f | 2403 | |
2404 | switch(action & 0xf0000000) { | |
42b82dc1 | 2405 | case PHY_READ: |
2406 | predata = rtl_readphy(tp, regno); | |
2407 | count++; | |
2408 | index++; | |
2409 | break; | |
2410 | case PHY_DATA_OR: | |
2411 | predata |= data; | |
2412 | index++; | |
2413 | break; | |
2414 | case PHY_DATA_AND: | |
2415 | predata &= data; | |
2416 | index++; | |
2417 | break; | |
2418 | case PHY_BJMPN: | |
2419 | index -= regno; | |
2420 | break; | |
eee3786f | 2421 | case PHY_MDIO_CHG: |
2422 | if (data == 0) { | |
2423 | ops->write = org.write; | |
2424 | ops->read = org.read; | |
2425 | } else if (data == 1) { | |
2426 | ops->write = mac_mcu_write; | |
2427 | ops->read = mac_mcu_read; | |
2428 | } | |
2429 | ||
42b82dc1 | 2430 | index++; |
2431 | break; | |
2432 | case PHY_CLEAR_READCOUNT: | |
2433 | count = 0; | |
2434 | index++; | |
2435 | break; | |
bca03d5f | 2436 | case PHY_WRITE: |
42b82dc1 | 2437 | rtl_writephy(tp, regno, data); |
2438 | index++; | |
2439 | break; | |
2440 | case PHY_READCOUNT_EQ_SKIP: | |
cecb5fd7 | 2441 | index += (count == data) ? 2 : 1; |
bca03d5f | 2442 | break; |
42b82dc1 | 2443 | case PHY_COMP_EQ_SKIPN: |
2444 | if (predata == data) | |
2445 | index += regno; | |
2446 | index++; | |
2447 | break; | |
2448 | case PHY_COMP_NEQ_SKIPN: | |
2449 | if (predata != data) | |
2450 | index += regno; | |
2451 | index++; | |
2452 | break; | |
2453 | case PHY_WRITE_PREVIOUS: | |
2454 | rtl_writephy(tp, regno, predata); | |
2455 | index++; | |
2456 | break; | |
2457 | case PHY_SKIPN: | |
2458 | index += regno + 1; | |
2459 | break; | |
2460 | case PHY_DELAY_MS: | |
2461 | mdelay(data); | |
2462 | index++; | |
2463 | break; | |
2464 | ||
bca03d5f | 2465 | default: |
2466 | BUG(); | |
2467 | } | |
2468 | } | |
eee3786f | 2469 | |
2470 | ops->write = org.write; | |
2471 | ops->read = org.read; | |
bca03d5f | 2472 | } |
2473 | ||
f1e02ed1 | 2474 | static void rtl_release_firmware(struct rtl8169_private *tp) |
2475 | { | |
b6ffd97f FR |
2476 | if (!IS_ERR_OR_NULL(tp->rtl_fw)) { |
2477 | release_firmware(tp->rtl_fw->fw); | |
2478 | kfree(tp->rtl_fw); | |
2479 | } | |
2480 | tp->rtl_fw = RTL_FIRMWARE_UNKNOWN; | |
f1e02ed1 | 2481 | } |
2482 | ||
953a12cc | 2483 | static void rtl_apply_firmware(struct rtl8169_private *tp) |
f1e02ed1 | 2484 | { |
b6ffd97f | 2485 | struct rtl_fw *rtl_fw = tp->rtl_fw; |
f1e02ed1 | 2486 | |
2487 | /* TODO: release firmware once rtl_phy_write_fw signals failures. */ | |
eef63cc1 | 2488 | if (!IS_ERR_OR_NULL(rtl_fw)) |
b6ffd97f | 2489 | rtl_phy_write_fw(tp, rtl_fw); |
953a12cc FR |
2490 | } |
2491 | ||
2492 | static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val) | |
2493 | { | |
2494 | if (rtl_readphy(tp, reg) != val) | |
2495 | netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n"); | |
2496 | else | |
2497 | rtl_apply_firmware(tp); | |
f1e02ed1 | 2498 | } |
2499 | ||
4da19633 | 2500 | static void rtl8169s_hw_phy_config(struct rtl8169_private *tp) |
1da177e4 | 2501 | { |
350f7596 | 2502 | static const struct phy_reg phy_reg_init[] = { |
0b9b571d | 2503 | { 0x1f, 0x0001 }, |
2504 | { 0x06, 0x006e }, | |
2505 | { 0x08, 0x0708 }, | |
2506 | { 0x15, 0x4000 }, | |
2507 | { 0x18, 0x65c7 }, | |
1da177e4 | 2508 | |
0b9b571d | 2509 | { 0x1f, 0x0001 }, |
2510 | { 0x03, 0x00a1 }, | |
2511 | { 0x02, 0x0008 }, | |
2512 | { 0x01, 0x0120 }, | |
2513 | { 0x00, 0x1000 }, | |
2514 | { 0x04, 0x0800 }, | |
2515 | { 0x04, 0x0000 }, | |
1da177e4 | 2516 | |
0b9b571d | 2517 | { 0x03, 0xff41 }, |
2518 | { 0x02, 0xdf60 }, | |
2519 | { 0x01, 0x0140 }, | |
2520 | { 0x00, 0x0077 }, | |
2521 | { 0x04, 0x7800 }, | |
2522 | { 0x04, 0x7000 }, | |
2523 | ||
2524 | { 0x03, 0x802f }, | |
2525 | { 0x02, 0x4f02 }, | |
2526 | { 0x01, 0x0409 }, | |
2527 | { 0x00, 0xf0f9 }, | |
2528 | { 0x04, 0x9800 }, | |
2529 | { 0x04, 0x9000 }, | |
2530 | ||
2531 | { 0x03, 0xdf01 }, | |
2532 | { 0x02, 0xdf20 }, | |
2533 | { 0x01, 0xff95 }, | |
2534 | { 0x00, 0xba00 }, | |
2535 | { 0x04, 0xa800 }, | |
2536 | { 0x04, 0xa000 }, | |
2537 | ||
2538 | { 0x03, 0xff41 }, | |
2539 | { 0x02, 0xdf20 }, | |
2540 | { 0x01, 0x0140 }, | |
2541 | { 0x00, 0x00bb }, | |
2542 | { 0x04, 0xb800 }, | |
2543 | { 0x04, 0xb000 }, | |
2544 | ||
2545 | { 0x03, 0xdf41 }, | |
2546 | { 0x02, 0xdc60 }, | |
2547 | { 0x01, 0x6340 }, | |
2548 | { 0x00, 0x007d }, | |
2549 | { 0x04, 0xd800 }, | |
2550 | { 0x04, 0xd000 }, | |
2551 | ||
2552 | { 0x03, 0xdf01 }, | |
2553 | { 0x02, 0xdf20 }, | |
2554 | { 0x01, 0x100a }, | |
2555 | { 0x00, 0xa0ff }, | |
2556 | { 0x04, 0xf800 }, | |
2557 | { 0x04, 0xf000 }, | |
2558 | ||
2559 | { 0x1f, 0x0000 }, | |
2560 | { 0x0b, 0x0000 }, | |
2561 | { 0x00, 0x9200 } | |
2562 | }; | |
1da177e4 | 2563 | |
4da19633 | 2564 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
1da177e4 LT |
2565 | } |
2566 | ||
4da19633 | 2567 | static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp) |
5615d9f1 | 2568 | { |
350f7596 | 2569 | static const struct phy_reg phy_reg_init[] = { |
a441d7b6 FR |
2570 | { 0x1f, 0x0002 }, |
2571 | { 0x01, 0x90d0 }, | |
2572 | { 0x1f, 0x0000 } | |
2573 | }; | |
2574 | ||
4da19633 | 2575 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
5615d9f1 FR |
2576 | } |
2577 | ||
4da19633 | 2578 | static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp) |
2e955856 | 2579 | { |
2580 | struct pci_dev *pdev = tp->pci_dev; | |
2e955856 | 2581 | |
ccbae55e SS |
2582 | if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) || |
2583 | (pdev->subsystem_device != 0xe000)) | |
2e955856 | 2584 | return; |
2585 | ||
4da19633 | 2586 | rtl_writephy(tp, 0x1f, 0x0001); |
2587 | rtl_writephy(tp, 0x10, 0xf01b); | |
2588 | rtl_writephy(tp, 0x1f, 0x0000); | |
2e955856 | 2589 | } |
2590 | ||
4da19633 | 2591 | static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp) |
2e955856 | 2592 | { |
350f7596 | 2593 | static const struct phy_reg phy_reg_init[] = { |
2e955856 | 2594 | { 0x1f, 0x0001 }, |
2595 | { 0x04, 0x0000 }, | |
2596 | { 0x03, 0x00a1 }, | |
2597 | { 0x02, 0x0008 }, | |
2598 | { 0x01, 0x0120 }, | |
2599 | { 0x00, 0x1000 }, | |
2600 | { 0x04, 0x0800 }, | |
2601 | { 0x04, 0x9000 }, | |
2602 | { 0x03, 0x802f }, | |
2603 | { 0x02, 0x4f02 }, | |
2604 | { 0x01, 0x0409 }, | |
2605 | { 0x00, 0xf099 }, | |
2606 | { 0x04, 0x9800 }, | |
2607 | { 0x04, 0xa000 }, | |
2608 | { 0x03, 0xdf01 }, | |
2609 | { 0x02, 0xdf20 }, | |
2610 | { 0x01, 0xff95 }, | |
2611 | { 0x00, 0xba00 }, | |
2612 | { 0x04, 0xa800 }, | |
2613 | { 0x04, 0xf000 }, | |
2614 | { 0x03, 0xdf01 }, | |
2615 | { 0x02, 0xdf20 }, | |
2616 | { 0x01, 0x101a }, | |
2617 | { 0x00, 0xa0ff }, | |
2618 | { 0x04, 0xf800 }, | |
2619 | { 0x04, 0x0000 }, | |
2620 | { 0x1f, 0x0000 }, | |
2621 | ||
2622 | { 0x1f, 0x0001 }, | |
2623 | { 0x10, 0xf41b }, | |
2624 | { 0x14, 0xfb54 }, | |
2625 | { 0x18, 0xf5c7 }, | |
2626 | { 0x1f, 0x0000 }, | |
2627 | ||
2628 | { 0x1f, 0x0001 }, | |
2629 | { 0x17, 0x0cc0 }, | |
2630 | { 0x1f, 0x0000 } | |
2631 | }; | |
2632 | ||
4da19633 | 2633 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
2e955856 | 2634 | |
4da19633 | 2635 | rtl8169scd_hw_phy_config_quirk(tp); |
2e955856 | 2636 | } |
2637 | ||
4da19633 | 2638 | static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp) |
8c7006aa | 2639 | { |
350f7596 | 2640 | static const struct phy_reg phy_reg_init[] = { |
8c7006aa | 2641 | { 0x1f, 0x0001 }, |
2642 | { 0x04, 0x0000 }, | |
2643 | { 0x03, 0x00a1 }, | |
2644 | { 0x02, 0x0008 }, | |
2645 | { 0x01, 0x0120 }, | |
2646 | { 0x00, 0x1000 }, | |
2647 | { 0x04, 0x0800 }, | |
2648 | { 0x04, 0x9000 }, | |
2649 | { 0x03, 0x802f }, | |
2650 | { 0x02, 0x4f02 }, | |
2651 | { 0x01, 0x0409 }, | |
2652 | { 0x00, 0xf099 }, | |
2653 | { 0x04, 0x9800 }, | |
2654 | { 0x04, 0xa000 }, | |
2655 | { 0x03, 0xdf01 }, | |
2656 | { 0x02, 0xdf20 }, | |
2657 | { 0x01, 0xff95 }, | |
2658 | { 0x00, 0xba00 }, | |
2659 | { 0x04, 0xa800 }, | |
2660 | { 0x04, 0xf000 }, | |
2661 | { 0x03, 0xdf01 }, | |
2662 | { 0x02, 0xdf20 }, | |
2663 | { 0x01, 0x101a }, | |
2664 | { 0x00, 0xa0ff }, | |
2665 | { 0x04, 0xf800 }, | |
2666 | { 0x04, 0x0000 }, | |
2667 | { 0x1f, 0x0000 }, | |
2668 | ||
2669 | { 0x1f, 0x0001 }, | |
2670 | { 0x0b, 0x8480 }, | |
2671 | { 0x1f, 0x0000 }, | |
2672 | ||
2673 | { 0x1f, 0x0001 }, | |
2674 | { 0x18, 0x67c7 }, | |
2675 | { 0x04, 0x2000 }, | |
2676 | { 0x03, 0x002f }, | |
2677 | { 0x02, 0x4360 }, | |
2678 | { 0x01, 0x0109 }, | |
2679 | { 0x00, 0x3022 }, | |
2680 | { 0x04, 0x2800 }, | |
2681 | { 0x1f, 0x0000 }, | |
2682 | ||
2683 | { 0x1f, 0x0001 }, | |
2684 | { 0x17, 0x0cc0 }, | |
2685 | { 0x1f, 0x0000 } | |
2686 | }; | |
2687 | ||
4da19633 | 2688 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
8c7006aa | 2689 | } |
2690 | ||
4da19633 | 2691 | static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp) |
236b8082 | 2692 | { |
350f7596 | 2693 | static const struct phy_reg phy_reg_init[] = { |
236b8082 FR |
2694 | { 0x10, 0xf41b }, |
2695 | { 0x1f, 0x0000 } | |
2696 | }; | |
2697 | ||
4da19633 | 2698 | rtl_writephy(tp, 0x1f, 0x0001); |
2699 | rtl_patchphy(tp, 0x16, 1 << 0); | |
236b8082 | 2700 | |
4da19633 | 2701 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
236b8082 FR |
2702 | } |
2703 | ||
4da19633 | 2704 | static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp) |
236b8082 | 2705 | { |
350f7596 | 2706 | static const struct phy_reg phy_reg_init[] = { |
236b8082 FR |
2707 | { 0x1f, 0x0001 }, |
2708 | { 0x10, 0xf41b }, | |
2709 | { 0x1f, 0x0000 } | |
2710 | }; | |
2711 | ||
4da19633 | 2712 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
236b8082 FR |
2713 | } |
2714 | ||
4da19633 | 2715 | static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp) |
867763c1 | 2716 | { |
350f7596 | 2717 | static const struct phy_reg phy_reg_init[] = { |
867763c1 FR |
2718 | { 0x1f, 0x0000 }, |
2719 | { 0x1d, 0x0f00 }, | |
2720 | { 0x1f, 0x0002 }, | |
2721 | { 0x0c, 0x1ec8 }, | |
2722 | { 0x1f, 0x0000 } | |
2723 | }; | |
2724 | ||
4da19633 | 2725 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
867763c1 FR |
2726 | } |
2727 | ||
4da19633 | 2728 | static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp) |
ef3386f0 | 2729 | { |
350f7596 | 2730 | static const struct phy_reg phy_reg_init[] = { |
ef3386f0 FR |
2731 | { 0x1f, 0x0001 }, |
2732 | { 0x1d, 0x3d98 }, | |
2733 | { 0x1f, 0x0000 } | |
2734 | }; | |
2735 | ||
4da19633 | 2736 | rtl_writephy(tp, 0x1f, 0x0000); |
2737 | rtl_patchphy(tp, 0x14, 1 << 5); | |
2738 | rtl_patchphy(tp, 0x0d, 1 << 5); | |
ef3386f0 | 2739 | |
4da19633 | 2740 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
ef3386f0 FR |
2741 | } |
2742 | ||
4da19633 | 2743 | static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp) |
867763c1 | 2744 | { |
350f7596 | 2745 | static const struct phy_reg phy_reg_init[] = { |
a3f80671 FR |
2746 | { 0x1f, 0x0001 }, |
2747 | { 0x12, 0x2300 }, | |
867763c1 FR |
2748 | { 0x1f, 0x0002 }, |
2749 | { 0x00, 0x88d4 }, | |
2750 | { 0x01, 0x82b1 }, | |
2751 | { 0x03, 0x7002 }, | |
2752 | { 0x08, 0x9e30 }, | |
2753 | { 0x09, 0x01f0 }, | |
2754 | { 0x0a, 0x5500 }, | |
2755 | { 0x0c, 0x00c8 }, | |
2756 | { 0x1f, 0x0003 }, | |
2757 | { 0x12, 0xc096 }, | |
2758 | { 0x16, 0x000a }, | |
f50d4275 FR |
2759 | { 0x1f, 0x0000 }, |
2760 | { 0x1f, 0x0000 }, | |
2761 | { 0x09, 0x2000 }, | |
2762 | { 0x09, 0x0000 } | |
867763c1 FR |
2763 | }; |
2764 | ||
4da19633 | 2765 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
f50d4275 | 2766 | |
4da19633 | 2767 | rtl_patchphy(tp, 0x14, 1 << 5); |
2768 | rtl_patchphy(tp, 0x0d, 1 << 5); | |
2769 | rtl_writephy(tp, 0x1f, 0x0000); | |
867763c1 FR |
2770 | } |
2771 | ||
4da19633 | 2772 | static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp) |
7da97ec9 | 2773 | { |
350f7596 | 2774 | static const struct phy_reg phy_reg_init[] = { |
f50d4275 | 2775 | { 0x1f, 0x0001 }, |
7da97ec9 | 2776 | { 0x12, 0x2300 }, |
f50d4275 FR |
2777 | { 0x03, 0x802f }, |
2778 | { 0x02, 0x4f02 }, | |
2779 | { 0x01, 0x0409 }, | |
2780 | { 0x00, 0xf099 }, | |
2781 | { 0x04, 0x9800 }, | |
2782 | { 0x04, 0x9000 }, | |
2783 | { 0x1d, 0x3d98 }, | |
7da97ec9 FR |
2784 | { 0x1f, 0x0002 }, |
2785 | { 0x0c, 0x7eb8 }, | |
f50d4275 FR |
2786 | { 0x06, 0x0761 }, |
2787 | { 0x1f, 0x0003 }, | |
2788 | { 0x16, 0x0f0a }, | |
7da97ec9 FR |
2789 | { 0x1f, 0x0000 } |
2790 | }; | |
2791 | ||
4da19633 | 2792 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
f50d4275 | 2793 | |
4da19633 | 2794 | rtl_patchphy(tp, 0x16, 1 << 0); |
2795 | rtl_patchphy(tp, 0x14, 1 << 5); | |
2796 | rtl_patchphy(tp, 0x0d, 1 << 5); | |
2797 | rtl_writephy(tp, 0x1f, 0x0000); | |
7da97ec9 FR |
2798 | } |
2799 | ||
4da19633 | 2800 | static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp) |
197ff761 | 2801 | { |
350f7596 | 2802 | static const struct phy_reg phy_reg_init[] = { |
197ff761 FR |
2803 | { 0x1f, 0x0001 }, |
2804 | { 0x12, 0x2300 }, | |
2805 | { 0x1d, 0x3d98 }, | |
2806 | { 0x1f, 0x0002 }, | |
2807 | { 0x0c, 0x7eb8 }, | |
2808 | { 0x06, 0x5461 }, | |
2809 | { 0x1f, 0x0003 }, | |
2810 | { 0x16, 0x0f0a }, | |
2811 | { 0x1f, 0x0000 } | |
2812 | }; | |
2813 | ||
4da19633 | 2814 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
197ff761 | 2815 | |
4da19633 | 2816 | rtl_patchphy(tp, 0x16, 1 << 0); |
2817 | rtl_patchphy(tp, 0x14, 1 << 5); | |
2818 | rtl_patchphy(tp, 0x0d, 1 << 5); | |
2819 | rtl_writephy(tp, 0x1f, 0x0000); | |
197ff761 FR |
2820 | } |
2821 | ||
4da19633 | 2822 | static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp) |
6fb07058 | 2823 | { |
4da19633 | 2824 | rtl8168c_3_hw_phy_config(tp); |
6fb07058 FR |
2825 | } |
2826 | ||
bca03d5f | 2827 | static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp) |
5b538df9 | 2828 | { |
350f7596 | 2829 | static const struct phy_reg phy_reg_init_0[] = { |
bca03d5f | 2830 | /* Channel Estimation */ |
5b538df9 | 2831 | { 0x1f, 0x0001 }, |
daf9df6d | 2832 | { 0x06, 0x4064 }, |
2833 | { 0x07, 0x2863 }, | |
2834 | { 0x08, 0x059c }, | |
2835 | { 0x09, 0x26b4 }, | |
2836 | { 0x0a, 0x6a19 }, | |
2837 | { 0x0b, 0xdcc8 }, | |
2838 | { 0x10, 0xf06d }, | |
2839 | { 0x14, 0x7f68 }, | |
2840 | { 0x18, 0x7fd9 }, | |
2841 | { 0x1c, 0xf0ff }, | |
2842 | { 0x1d, 0x3d9c }, | |
5b538df9 | 2843 | { 0x1f, 0x0003 }, |
daf9df6d | 2844 | { 0x12, 0xf49f }, |
2845 | { 0x13, 0x070b }, | |
2846 | { 0x1a, 0x05ad }, | |
bca03d5f | 2847 | { 0x14, 0x94c0 }, |
2848 | ||
2849 | /* | |
2850 | * Tx Error Issue | |
cecb5fd7 | 2851 | * Enhance line driver power |
bca03d5f | 2852 | */ |
5b538df9 | 2853 | { 0x1f, 0x0002 }, |
daf9df6d | 2854 | { 0x06, 0x5561 }, |
2855 | { 0x1f, 0x0005 }, | |
2856 | { 0x05, 0x8332 }, | |
bca03d5f | 2857 | { 0x06, 0x5561 }, |
2858 | ||
2859 | /* | |
2860 | * Can not link to 1Gbps with bad cable | |
2861 | * Decrease SNR threshold form 21.07dB to 19.04dB | |
2862 | */ | |
2863 | { 0x1f, 0x0001 }, | |
2864 | { 0x17, 0x0cc0 }, | |
daf9df6d | 2865 | |
5b538df9 | 2866 | { 0x1f, 0x0000 }, |
bca03d5f | 2867 | { 0x0d, 0xf880 } |
daf9df6d | 2868 | }; |
2869 | ||
4da19633 | 2870 | rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0)); |
daf9df6d | 2871 | |
bca03d5f | 2872 | /* |
2873 | * Rx Error Issue | |
2874 | * Fine Tune Switching regulator parameter | |
2875 | */ | |
4da19633 | 2876 | rtl_writephy(tp, 0x1f, 0x0002); |
2877 | rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef); | |
2878 | rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00); | |
daf9df6d | 2879 | |
fdf6fc06 | 2880 | if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) { |
350f7596 | 2881 | static const struct phy_reg phy_reg_init[] = { |
daf9df6d | 2882 | { 0x1f, 0x0002 }, |
2883 | { 0x05, 0x669a }, | |
2884 | { 0x1f, 0x0005 }, | |
2885 | { 0x05, 0x8330 }, | |
2886 | { 0x06, 0x669a }, | |
2887 | { 0x1f, 0x0002 } | |
2888 | }; | |
2889 | int val; | |
2890 | ||
4da19633 | 2891 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
daf9df6d | 2892 | |
4da19633 | 2893 | val = rtl_readphy(tp, 0x0d); |
daf9df6d | 2894 | |
2895 | if ((val & 0x00ff) != 0x006c) { | |
350f7596 | 2896 | static const u32 set[] = { |
daf9df6d | 2897 | 0x0065, 0x0066, 0x0067, 0x0068, |
2898 | 0x0069, 0x006a, 0x006b, 0x006c | |
2899 | }; | |
2900 | int i; | |
2901 | ||
4da19633 | 2902 | rtl_writephy(tp, 0x1f, 0x0002); |
daf9df6d | 2903 | |
2904 | val &= 0xff00; | |
2905 | for (i = 0; i < ARRAY_SIZE(set); i++) | |
4da19633 | 2906 | rtl_writephy(tp, 0x0d, val | set[i]); |
daf9df6d | 2907 | } |
2908 | } else { | |
350f7596 | 2909 | static const struct phy_reg phy_reg_init[] = { |
daf9df6d | 2910 | { 0x1f, 0x0002 }, |
2911 | { 0x05, 0x6662 }, | |
2912 | { 0x1f, 0x0005 }, | |
2913 | { 0x05, 0x8330 }, | |
2914 | { 0x06, 0x6662 } | |
2915 | }; | |
2916 | ||
4da19633 | 2917 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
daf9df6d | 2918 | } |
2919 | ||
bca03d5f | 2920 | /* RSET couple improve */ |
4da19633 | 2921 | rtl_writephy(tp, 0x1f, 0x0002); |
2922 | rtl_patchphy(tp, 0x0d, 0x0300); | |
2923 | rtl_patchphy(tp, 0x0f, 0x0010); | |
daf9df6d | 2924 | |
bca03d5f | 2925 | /* Fine tune PLL performance */ |
4da19633 | 2926 | rtl_writephy(tp, 0x1f, 0x0002); |
2927 | rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600); | |
2928 | rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000); | |
daf9df6d | 2929 | |
4da19633 | 2930 | rtl_writephy(tp, 0x1f, 0x0005); |
2931 | rtl_writephy(tp, 0x05, 0x001b); | |
953a12cc FR |
2932 | |
2933 | rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00); | |
bca03d5f | 2934 | |
4da19633 | 2935 | rtl_writephy(tp, 0x1f, 0x0000); |
daf9df6d | 2936 | } |
2937 | ||
bca03d5f | 2938 | static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp) |
daf9df6d | 2939 | { |
350f7596 | 2940 | static const struct phy_reg phy_reg_init_0[] = { |
bca03d5f | 2941 | /* Channel Estimation */ |
daf9df6d | 2942 | { 0x1f, 0x0001 }, |
2943 | { 0x06, 0x4064 }, | |
2944 | { 0x07, 0x2863 }, | |
2945 | { 0x08, 0x059c }, | |
2946 | { 0x09, 0x26b4 }, | |
2947 | { 0x0a, 0x6a19 }, | |
2948 | { 0x0b, 0xdcc8 }, | |
2949 | { 0x10, 0xf06d }, | |
2950 | { 0x14, 0x7f68 }, | |
2951 | { 0x18, 0x7fd9 }, | |
2952 | { 0x1c, 0xf0ff }, | |
2953 | { 0x1d, 0x3d9c }, | |
2954 | { 0x1f, 0x0003 }, | |
2955 | { 0x12, 0xf49f }, | |
2956 | { 0x13, 0x070b }, | |
2957 | { 0x1a, 0x05ad }, | |
2958 | { 0x14, 0x94c0 }, | |
2959 | ||
bca03d5f | 2960 | /* |
2961 | * Tx Error Issue | |
cecb5fd7 | 2962 | * Enhance line driver power |
bca03d5f | 2963 | */ |
daf9df6d | 2964 | { 0x1f, 0x0002 }, |
2965 | { 0x06, 0x5561 }, | |
2966 | { 0x1f, 0x0005 }, | |
2967 | { 0x05, 0x8332 }, | |
bca03d5f | 2968 | { 0x06, 0x5561 }, |
2969 | ||
2970 | /* | |
2971 | * Can not link to 1Gbps with bad cable | |
2972 | * Decrease SNR threshold form 21.07dB to 19.04dB | |
2973 | */ | |
2974 | { 0x1f, 0x0001 }, | |
2975 | { 0x17, 0x0cc0 }, | |
daf9df6d | 2976 | |
2977 | { 0x1f, 0x0000 }, | |
bca03d5f | 2978 | { 0x0d, 0xf880 } |
5b538df9 FR |
2979 | }; |
2980 | ||
4da19633 | 2981 | rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0)); |
5b538df9 | 2982 | |
fdf6fc06 | 2983 | if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) { |
350f7596 | 2984 | static const struct phy_reg phy_reg_init[] = { |
daf9df6d | 2985 | { 0x1f, 0x0002 }, |
2986 | { 0x05, 0x669a }, | |
5b538df9 | 2987 | { 0x1f, 0x0005 }, |
daf9df6d | 2988 | { 0x05, 0x8330 }, |
2989 | { 0x06, 0x669a }, | |
2990 | ||
2991 | { 0x1f, 0x0002 } | |
2992 | }; | |
2993 | int val; | |
2994 | ||
4da19633 | 2995 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
daf9df6d | 2996 | |
4da19633 | 2997 | val = rtl_readphy(tp, 0x0d); |
daf9df6d | 2998 | if ((val & 0x00ff) != 0x006c) { |
b6bc7650 | 2999 | static const u32 set[] = { |
daf9df6d | 3000 | 0x0065, 0x0066, 0x0067, 0x0068, |
3001 | 0x0069, 0x006a, 0x006b, 0x006c | |
3002 | }; | |
3003 | int i; | |
3004 | ||
4da19633 | 3005 | rtl_writephy(tp, 0x1f, 0x0002); |
daf9df6d | 3006 | |
3007 | val &= 0xff00; | |
3008 | for (i = 0; i < ARRAY_SIZE(set); i++) | |
4da19633 | 3009 | rtl_writephy(tp, 0x0d, val | set[i]); |
daf9df6d | 3010 | } |
3011 | } else { | |
350f7596 | 3012 | static const struct phy_reg phy_reg_init[] = { |
daf9df6d | 3013 | { 0x1f, 0x0002 }, |
3014 | { 0x05, 0x2642 }, | |
5b538df9 | 3015 | { 0x1f, 0x0005 }, |
daf9df6d | 3016 | { 0x05, 0x8330 }, |
3017 | { 0x06, 0x2642 } | |
5b538df9 FR |
3018 | }; |
3019 | ||
4da19633 | 3020 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
5b538df9 FR |
3021 | } |
3022 | ||
bca03d5f | 3023 | /* Fine tune PLL performance */ |
4da19633 | 3024 | rtl_writephy(tp, 0x1f, 0x0002); |
3025 | rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600); | |
3026 | rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000); | |
daf9df6d | 3027 | |
bca03d5f | 3028 | /* Switching regulator Slew rate */ |
4da19633 | 3029 | rtl_writephy(tp, 0x1f, 0x0002); |
3030 | rtl_patchphy(tp, 0x0f, 0x0017); | |
daf9df6d | 3031 | |
4da19633 | 3032 | rtl_writephy(tp, 0x1f, 0x0005); |
3033 | rtl_writephy(tp, 0x05, 0x001b); | |
953a12cc FR |
3034 | |
3035 | rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300); | |
bca03d5f | 3036 | |
4da19633 | 3037 | rtl_writephy(tp, 0x1f, 0x0000); |
daf9df6d | 3038 | } |
3039 | ||
4da19633 | 3040 | static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp) |
daf9df6d | 3041 | { |
350f7596 | 3042 | static const struct phy_reg phy_reg_init[] = { |
daf9df6d | 3043 | { 0x1f, 0x0002 }, |
3044 | { 0x10, 0x0008 }, | |
3045 | { 0x0d, 0x006c }, | |
3046 | ||
3047 | { 0x1f, 0x0000 }, | |
3048 | { 0x0d, 0xf880 }, | |
3049 | ||
3050 | { 0x1f, 0x0001 }, | |
3051 | { 0x17, 0x0cc0 }, | |
3052 | ||
3053 | { 0x1f, 0x0001 }, | |
3054 | { 0x0b, 0xa4d8 }, | |
3055 | { 0x09, 0x281c }, | |
3056 | { 0x07, 0x2883 }, | |
3057 | { 0x0a, 0x6b35 }, | |
3058 | { 0x1d, 0x3da4 }, | |
3059 | { 0x1c, 0xeffd }, | |
3060 | { 0x14, 0x7f52 }, | |
3061 | { 0x18, 0x7fc6 }, | |
3062 | { 0x08, 0x0601 }, | |
3063 | { 0x06, 0x4063 }, | |
3064 | { 0x10, 0xf074 }, | |
3065 | { 0x1f, 0x0003 }, | |
3066 | { 0x13, 0x0789 }, | |
3067 | { 0x12, 0xf4bd }, | |
3068 | { 0x1a, 0x04fd }, | |
3069 | { 0x14, 0x84b0 }, | |
3070 | { 0x1f, 0x0000 }, | |
3071 | { 0x00, 0x9200 }, | |
3072 | ||
3073 | { 0x1f, 0x0005 }, | |
3074 | { 0x01, 0x0340 }, | |
3075 | { 0x1f, 0x0001 }, | |
3076 | { 0x04, 0x4000 }, | |
3077 | { 0x03, 0x1d21 }, | |
3078 | { 0x02, 0x0c32 }, | |
3079 | { 0x01, 0x0200 }, | |
3080 | { 0x00, 0x5554 }, | |
3081 | { 0x04, 0x4800 }, | |
3082 | { 0x04, 0x4000 }, | |
3083 | { 0x04, 0xf000 }, | |
3084 | { 0x03, 0xdf01 }, | |
3085 | { 0x02, 0xdf20 }, | |
3086 | { 0x01, 0x101a }, | |
3087 | { 0x00, 0xa0ff }, | |
3088 | { 0x04, 0xf800 }, | |
3089 | { 0x04, 0xf000 }, | |
3090 | { 0x1f, 0x0000 }, | |
3091 | ||
3092 | { 0x1f, 0x0007 }, | |
3093 | { 0x1e, 0x0023 }, | |
3094 | { 0x16, 0x0000 }, | |
3095 | { 0x1f, 0x0000 } | |
3096 | }; | |
3097 | ||
4da19633 | 3098 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
5b538df9 FR |
3099 | } |
3100 | ||
e6de30d6 | 3101 | static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp) |
3102 | { | |
3103 | static const struct phy_reg phy_reg_init[] = { | |
3104 | { 0x1f, 0x0001 }, | |
3105 | { 0x17, 0x0cc0 }, | |
3106 | ||
3107 | { 0x1f, 0x0007 }, | |
3108 | { 0x1e, 0x002d }, | |
3109 | { 0x18, 0x0040 }, | |
3110 | { 0x1f, 0x0000 } | |
3111 | }; | |
3112 | ||
3113 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | |
3114 | rtl_patchphy(tp, 0x0d, 1 << 5); | |
3115 | } | |
3116 | ||
70090424 | 3117 | static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp) |
01dc7fec | 3118 | { |
3119 | static const struct phy_reg phy_reg_init[] = { | |
3120 | /* Enable Delay cap */ | |
3121 | { 0x1f, 0x0005 }, | |
3122 | { 0x05, 0x8b80 }, | |
3123 | { 0x06, 0xc896 }, | |
3124 | { 0x1f, 0x0000 }, | |
3125 | ||
3126 | /* Channel estimation fine tune */ | |
3127 | { 0x1f, 0x0001 }, | |
3128 | { 0x0b, 0x6c20 }, | |
3129 | { 0x07, 0x2872 }, | |
3130 | { 0x1c, 0xefff }, | |
3131 | { 0x1f, 0x0003 }, | |
3132 | { 0x14, 0x6420 }, | |
3133 | { 0x1f, 0x0000 }, | |
3134 | ||
3135 | /* Update PFM & 10M TX idle timer */ | |
3136 | { 0x1f, 0x0007 }, | |
3137 | { 0x1e, 0x002f }, | |
3138 | { 0x15, 0x1919 }, | |
3139 | { 0x1f, 0x0000 }, | |
3140 | ||
3141 | { 0x1f, 0x0007 }, | |
3142 | { 0x1e, 0x00ac }, | |
3143 | { 0x18, 0x0006 }, | |
3144 | { 0x1f, 0x0000 } | |
3145 | }; | |
3146 | ||
15ecd039 FR |
3147 | rtl_apply_firmware(tp); |
3148 | ||
01dc7fec | 3149 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
3150 | ||
3151 | /* DCO enable for 10M IDLE Power */ | |
3152 | rtl_writephy(tp, 0x1f, 0x0007); | |
3153 | rtl_writephy(tp, 0x1e, 0x0023); | |
3154 | rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000); | |
3155 | rtl_writephy(tp, 0x1f, 0x0000); | |
3156 | ||
3157 | /* For impedance matching */ | |
3158 | rtl_writephy(tp, 0x1f, 0x0002); | |
3159 | rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00); | |
cecb5fd7 | 3160 | rtl_writephy(tp, 0x1f, 0x0000); |
01dc7fec | 3161 | |
3162 | /* PHY auto speed down */ | |
3163 | rtl_writephy(tp, 0x1f, 0x0007); | |
3164 | rtl_writephy(tp, 0x1e, 0x002d); | |
3165 | rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000); | |
3166 | rtl_writephy(tp, 0x1f, 0x0000); | |
3167 | rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000); | |
3168 | ||
3169 | rtl_writephy(tp, 0x1f, 0x0005); | |
3170 | rtl_writephy(tp, 0x05, 0x8b86); | |
3171 | rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000); | |
3172 | rtl_writephy(tp, 0x1f, 0x0000); | |
3173 | ||
3174 | rtl_writephy(tp, 0x1f, 0x0005); | |
3175 | rtl_writephy(tp, 0x05, 0x8b85); | |
3176 | rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000); | |
3177 | rtl_writephy(tp, 0x1f, 0x0007); | |
3178 | rtl_writephy(tp, 0x1e, 0x0020); | |
3179 | rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100); | |
3180 | rtl_writephy(tp, 0x1f, 0x0006); | |
3181 | rtl_writephy(tp, 0x00, 0x5a00); | |
3182 | rtl_writephy(tp, 0x1f, 0x0000); | |
3183 | rtl_writephy(tp, 0x0d, 0x0007); | |
3184 | rtl_writephy(tp, 0x0e, 0x003c); | |
3185 | rtl_writephy(tp, 0x0d, 0x4007); | |
3186 | rtl_writephy(tp, 0x0e, 0x0000); | |
3187 | rtl_writephy(tp, 0x0d, 0x0000); | |
3188 | } | |
3189 | ||
9ecb9aab | 3190 | static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr) |
3191 | { | |
3192 | const u16 w[] = { | |
3193 | addr[0] | (addr[1] << 8), | |
3194 | addr[2] | (addr[3] << 8), | |
3195 | addr[4] | (addr[5] << 8) | |
3196 | }; | |
3197 | const struct exgmac_reg e[] = { | |
3198 | { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) }, | |
3199 | { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] }, | |
3200 | { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 }, | |
3201 | { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) } | |
3202 | }; | |
3203 | ||
3204 | rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e)); | |
3205 | } | |
3206 | ||
70090424 HW |
3207 | static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp) |
3208 | { | |
3209 | static const struct phy_reg phy_reg_init[] = { | |
3210 | /* Enable Delay cap */ | |
3211 | { 0x1f, 0x0004 }, | |
3212 | { 0x1f, 0x0007 }, | |
3213 | { 0x1e, 0x00ac }, | |
3214 | { 0x18, 0x0006 }, | |
3215 | { 0x1f, 0x0002 }, | |
3216 | { 0x1f, 0x0000 }, | |
3217 | { 0x1f, 0x0000 }, | |
3218 | ||
3219 | /* Channel estimation fine tune */ | |
3220 | { 0x1f, 0x0003 }, | |
3221 | { 0x09, 0xa20f }, | |
3222 | { 0x1f, 0x0000 }, | |
3223 | { 0x1f, 0x0000 }, | |
3224 | ||
3225 | /* Green Setting */ | |
3226 | { 0x1f, 0x0005 }, | |
3227 | { 0x05, 0x8b5b }, | |
3228 | { 0x06, 0x9222 }, | |
3229 | { 0x05, 0x8b6d }, | |
3230 | { 0x06, 0x8000 }, | |
3231 | { 0x05, 0x8b76 }, | |
3232 | { 0x06, 0x8000 }, | |
3233 | { 0x1f, 0x0000 } | |
3234 | }; | |
3235 | ||
3236 | rtl_apply_firmware(tp); | |
3237 | ||
3238 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | |
3239 | ||
3240 | /* For 4-corner performance improve */ | |
3241 | rtl_writephy(tp, 0x1f, 0x0005); | |
3242 | rtl_writephy(tp, 0x05, 0x8b80); | |
3243 | rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000); | |
3244 | rtl_writephy(tp, 0x1f, 0x0000); | |
3245 | ||
3246 | /* PHY auto speed down */ | |
3247 | rtl_writephy(tp, 0x1f, 0x0004); | |
3248 | rtl_writephy(tp, 0x1f, 0x0007); | |
3249 | rtl_writephy(tp, 0x1e, 0x002d); | |
3250 | rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000); | |
3251 | rtl_writephy(tp, 0x1f, 0x0002); | |
3252 | rtl_writephy(tp, 0x1f, 0x0000); | |
3253 | rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000); | |
3254 | ||
3255 | /* improve 10M EEE waveform */ | |
3256 | rtl_writephy(tp, 0x1f, 0x0005); | |
3257 | rtl_writephy(tp, 0x05, 0x8b86); | |
3258 | rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000); | |
3259 | rtl_writephy(tp, 0x1f, 0x0000); | |
3260 | ||
3261 | /* Improve 2-pair detection performance */ | |
3262 | rtl_writephy(tp, 0x1f, 0x0005); | |
3263 | rtl_writephy(tp, 0x05, 0x8b85); | |
3264 | rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000); | |
3265 | rtl_writephy(tp, 0x1f, 0x0000); | |
3266 | ||
3267 | /* EEE setting */ | |
fdf6fc06 | 3268 | rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, ERIAR_EXGMAC); |
70090424 HW |
3269 | rtl_writephy(tp, 0x1f, 0x0005); |
3270 | rtl_writephy(tp, 0x05, 0x8b85); | |
3271 | rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000); | |
3272 | rtl_writephy(tp, 0x1f, 0x0004); | |
3273 | rtl_writephy(tp, 0x1f, 0x0007); | |
3274 | rtl_writephy(tp, 0x1e, 0x0020); | |
1b23a3e3 | 3275 | rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100); |
70090424 HW |
3276 | rtl_writephy(tp, 0x1f, 0x0002); |
3277 | rtl_writephy(tp, 0x1f, 0x0000); | |
3278 | rtl_writephy(tp, 0x0d, 0x0007); | |
3279 | rtl_writephy(tp, 0x0e, 0x003c); | |
3280 | rtl_writephy(tp, 0x0d, 0x4007); | |
3281 | rtl_writephy(tp, 0x0e, 0x0000); | |
3282 | rtl_writephy(tp, 0x0d, 0x0000); | |
3283 | ||
3284 | /* Green feature */ | |
3285 | rtl_writephy(tp, 0x1f, 0x0003); | |
3286 | rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001); | |
3287 | rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400); | |
3288 | rtl_writephy(tp, 0x1f, 0x0000); | |
e0c07557 | 3289 | |
9ecb9aab | 3290 | /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */ |
3291 | rtl_rar_exgmac_set(tp, tp->dev->dev_addr); | |
70090424 HW |
3292 | } |
3293 | ||
5f886e08 HW |
3294 | static void rtl8168f_hw_phy_config(struct rtl8169_private *tp) |
3295 | { | |
3296 | /* For 4-corner performance improve */ | |
3297 | rtl_writephy(tp, 0x1f, 0x0005); | |
3298 | rtl_writephy(tp, 0x05, 0x8b80); | |
3299 | rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000); | |
3300 | rtl_writephy(tp, 0x1f, 0x0000); | |
3301 | ||
3302 | /* PHY auto speed down */ | |
3303 | rtl_writephy(tp, 0x1f, 0x0007); | |
3304 | rtl_writephy(tp, 0x1e, 0x002d); | |
3305 | rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000); | |
3306 | rtl_writephy(tp, 0x1f, 0x0000); | |
3307 | rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000); | |
3308 | ||
3309 | /* Improve 10M EEE waveform */ | |
3310 | rtl_writephy(tp, 0x1f, 0x0005); | |
3311 | rtl_writephy(tp, 0x05, 0x8b86); | |
3312 | rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000); | |
3313 | rtl_writephy(tp, 0x1f, 0x0000); | |
3314 | } | |
3315 | ||
c2218925 HW |
3316 | static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp) |
3317 | { | |
3318 | static const struct phy_reg phy_reg_init[] = { | |
3319 | /* Channel estimation fine tune */ | |
3320 | { 0x1f, 0x0003 }, | |
3321 | { 0x09, 0xa20f }, | |
3322 | { 0x1f, 0x0000 }, | |
3323 | ||
3324 | /* Modify green table for giga & fnet */ | |
3325 | { 0x1f, 0x0005 }, | |
3326 | { 0x05, 0x8b55 }, | |
3327 | { 0x06, 0x0000 }, | |
3328 | { 0x05, 0x8b5e }, | |
3329 | { 0x06, 0x0000 }, | |
3330 | { 0x05, 0x8b67 }, | |
3331 | { 0x06, 0x0000 }, | |
3332 | { 0x05, 0x8b70 }, | |
3333 | { 0x06, 0x0000 }, | |
3334 | { 0x1f, 0x0000 }, | |
3335 | { 0x1f, 0x0007 }, | |
3336 | { 0x1e, 0x0078 }, | |
3337 | { 0x17, 0x0000 }, | |
3338 | { 0x19, 0x00fb }, | |
3339 | { 0x1f, 0x0000 }, | |
3340 | ||
3341 | /* Modify green table for 10M */ | |
3342 | { 0x1f, 0x0005 }, | |
3343 | { 0x05, 0x8b79 }, | |
3344 | { 0x06, 0xaa00 }, | |
3345 | { 0x1f, 0x0000 }, | |
3346 | ||
3347 | /* Disable hiimpedance detection (RTCT) */ | |
3348 | { 0x1f, 0x0003 }, | |
3349 | { 0x01, 0x328a }, | |
3350 | { 0x1f, 0x0000 } | |
3351 | }; | |
3352 | ||
3353 | rtl_apply_firmware(tp); | |
3354 | ||
3355 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | |
3356 | ||
5f886e08 | 3357 | rtl8168f_hw_phy_config(tp); |
c2218925 HW |
3358 | |
3359 | /* Improve 2-pair detection performance */ | |
3360 | rtl_writephy(tp, 0x1f, 0x0005); | |
3361 | rtl_writephy(tp, 0x05, 0x8b85); | |
3362 | rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000); | |
3363 | rtl_writephy(tp, 0x1f, 0x0000); | |
3364 | } | |
3365 | ||
3366 | static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp) | |
3367 | { | |
3368 | rtl_apply_firmware(tp); | |
3369 | ||
5f886e08 | 3370 | rtl8168f_hw_phy_config(tp); |
c2218925 HW |
3371 | } |
3372 | ||
b3d7b2f2 HW |
3373 | static void rtl8411_hw_phy_config(struct rtl8169_private *tp) |
3374 | { | |
b3d7b2f2 HW |
3375 | static const struct phy_reg phy_reg_init[] = { |
3376 | /* Channel estimation fine tune */ | |
3377 | { 0x1f, 0x0003 }, | |
3378 | { 0x09, 0xa20f }, | |
3379 | { 0x1f, 0x0000 }, | |
3380 | ||
3381 | /* Modify green table for giga & fnet */ | |
3382 | { 0x1f, 0x0005 }, | |
3383 | { 0x05, 0x8b55 }, | |
3384 | { 0x06, 0x0000 }, | |
3385 | { 0x05, 0x8b5e }, | |
3386 | { 0x06, 0x0000 }, | |
3387 | { 0x05, 0x8b67 }, | |
3388 | { 0x06, 0x0000 }, | |
3389 | { 0x05, 0x8b70 }, | |
3390 | { 0x06, 0x0000 }, | |
3391 | { 0x1f, 0x0000 }, | |
3392 | { 0x1f, 0x0007 }, | |
3393 | { 0x1e, 0x0078 }, | |
3394 | { 0x17, 0x0000 }, | |
3395 | { 0x19, 0x00aa }, | |
3396 | { 0x1f, 0x0000 }, | |
3397 | ||
3398 | /* Modify green table for 10M */ | |
3399 | { 0x1f, 0x0005 }, | |
3400 | { 0x05, 0x8b79 }, | |
3401 | { 0x06, 0xaa00 }, | |
3402 | { 0x1f, 0x0000 }, | |
3403 | ||
3404 | /* Disable hiimpedance detection (RTCT) */ | |
3405 | { 0x1f, 0x0003 }, | |
3406 | { 0x01, 0x328a }, | |
3407 | { 0x1f, 0x0000 } | |
3408 | }; | |
3409 | ||
3410 | ||
3411 | rtl_apply_firmware(tp); | |
3412 | ||
3413 | rtl8168f_hw_phy_config(tp); | |
3414 | ||
3415 | /* Improve 2-pair detection performance */ | |
3416 | rtl_writephy(tp, 0x1f, 0x0005); | |
3417 | rtl_writephy(tp, 0x05, 0x8b85); | |
3418 | rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000); | |
3419 | rtl_writephy(tp, 0x1f, 0x0000); | |
3420 | ||
3421 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | |
3422 | ||
3423 | /* Modify green table for giga */ | |
3424 | rtl_writephy(tp, 0x1f, 0x0005); | |
3425 | rtl_writephy(tp, 0x05, 0x8b54); | |
3426 | rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800); | |
3427 | rtl_writephy(tp, 0x05, 0x8b5d); | |
3428 | rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800); | |
3429 | rtl_writephy(tp, 0x05, 0x8a7c); | |
3430 | rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100); | |
3431 | rtl_writephy(tp, 0x05, 0x8a7f); | |
3432 | rtl_w1w0_phy(tp, 0x06, 0x0100, 0x0000); | |
3433 | rtl_writephy(tp, 0x05, 0x8a82); | |
3434 | rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100); | |
3435 | rtl_writephy(tp, 0x05, 0x8a85); | |
3436 | rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100); | |
3437 | rtl_writephy(tp, 0x05, 0x8a88); | |
3438 | rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100); | |
3439 | rtl_writephy(tp, 0x1f, 0x0000); | |
3440 | ||
3441 | /* uc same-seed solution */ | |
3442 | rtl_writephy(tp, 0x1f, 0x0005); | |
3443 | rtl_writephy(tp, 0x05, 0x8b85); | |
3444 | rtl_w1w0_phy(tp, 0x06, 0x8000, 0x0000); | |
3445 | rtl_writephy(tp, 0x1f, 0x0000); | |
3446 | ||
3447 | /* eee setting */ | |
fdf6fc06 | 3448 | rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC); |
b3d7b2f2 HW |
3449 | rtl_writephy(tp, 0x1f, 0x0005); |
3450 | rtl_writephy(tp, 0x05, 0x8b85); | |
3451 | rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000); | |
3452 | rtl_writephy(tp, 0x1f, 0x0004); | |
3453 | rtl_writephy(tp, 0x1f, 0x0007); | |
3454 | rtl_writephy(tp, 0x1e, 0x0020); | |
3455 | rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100); | |
3456 | rtl_writephy(tp, 0x1f, 0x0000); | |
3457 | rtl_writephy(tp, 0x0d, 0x0007); | |
3458 | rtl_writephy(tp, 0x0e, 0x003c); | |
3459 | rtl_writephy(tp, 0x0d, 0x4007); | |
3460 | rtl_writephy(tp, 0x0e, 0x0000); | |
3461 | rtl_writephy(tp, 0x0d, 0x0000); | |
3462 | ||
3463 | /* Green feature */ | |
3464 | rtl_writephy(tp, 0x1f, 0x0003); | |
3465 | rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001); | |
3466 | rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400); | |
3467 | rtl_writephy(tp, 0x1f, 0x0000); | |
3468 | } | |
3469 | ||
c558386b HW |
3470 | static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp) |
3471 | { | |
c558386b HW |
3472 | rtl_apply_firmware(tp); |
3473 | ||
41f44d13 | 3474 | rtl_writephy(tp, 0x1f, 0x0a46); |
3475 | if (rtl_readphy(tp, 0x10) & 0x0100) { | |
3476 | rtl_writephy(tp, 0x1f, 0x0bcc); | |
3477 | rtl_w1w0_phy(tp, 0x12, 0x0000, 0x8000); | |
3478 | } else { | |
3479 | rtl_writephy(tp, 0x1f, 0x0bcc); | |
3480 | rtl_w1w0_phy(tp, 0x12, 0x8000, 0x0000); | |
3481 | } | |
c558386b | 3482 | |
41f44d13 | 3483 | rtl_writephy(tp, 0x1f, 0x0a46); |
3484 | if (rtl_readphy(tp, 0x13) & 0x0100) { | |
3485 | rtl_writephy(tp, 0x1f, 0x0c41); | |
3486 | rtl_w1w0_phy(tp, 0x15, 0x0002, 0x0000); | |
3487 | } else { | |
fe7524c0 | 3488 | rtl_writephy(tp, 0x1f, 0x0c41); |
3489 | rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0002); | |
41f44d13 | 3490 | } |
c558386b | 3491 | |
41f44d13 | 3492 | /* Enable PHY auto speed down */ |
3493 | rtl_writephy(tp, 0x1f, 0x0a44); | |
3494 | rtl_w1w0_phy(tp, 0x11, 0x000c, 0x0000); | |
c558386b | 3495 | |
fe7524c0 | 3496 | rtl_writephy(tp, 0x1f, 0x0bcc); |
3497 | rtl_w1w0_phy(tp, 0x14, 0x0100, 0x0000); | |
3498 | rtl_writephy(tp, 0x1f, 0x0a44); | |
3499 | rtl_w1w0_phy(tp, 0x11, 0x00c0, 0x0000); | |
3500 | rtl_writephy(tp, 0x1f, 0x0a43); | |
3501 | rtl_writephy(tp, 0x13, 0x8084); | |
3502 | rtl_w1w0_phy(tp, 0x14, 0x0000, 0x6000); | |
3503 | rtl_w1w0_phy(tp, 0x10, 0x1003, 0x0000); | |
3504 | ||
41f44d13 | 3505 | /* EEE auto-fallback function */ |
3506 | rtl_writephy(tp, 0x1f, 0x0a4b); | |
3507 | rtl_w1w0_phy(tp, 0x11, 0x0004, 0x0000); | |
c558386b | 3508 | |
41f44d13 | 3509 | /* Enable UC LPF tune function */ |
3510 | rtl_writephy(tp, 0x1f, 0x0a43); | |
3511 | rtl_writephy(tp, 0x13, 0x8012); | |
3512 | rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000); | |
3513 | ||
3514 | rtl_writephy(tp, 0x1f, 0x0c42); | |
3515 | rtl_w1w0_phy(tp, 0x11, 0x4000, 0x2000); | |
3516 | ||
fe7524c0 | 3517 | /* Improve SWR Efficiency */ |
3518 | rtl_writephy(tp, 0x1f, 0x0bcd); | |
3519 | rtl_writephy(tp, 0x14, 0x5065); | |
3520 | rtl_writephy(tp, 0x14, 0xd065); | |
3521 | rtl_writephy(tp, 0x1f, 0x0bc8); | |
3522 | rtl_writephy(tp, 0x11, 0x5655); | |
3523 | rtl_writephy(tp, 0x1f, 0x0bcd); | |
3524 | rtl_writephy(tp, 0x14, 0x1065); | |
3525 | rtl_writephy(tp, 0x14, 0x9065); | |
3526 | rtl_writephy(tp, 0x14, 0x1065); | |
3527 | ||
1bac1072 DC |
3528 | /* Check ALDPS bit, disable it if enabled */ |
3529 | rtl_writephy(tp, 0x1f, 0x0a43); | |
3530 | if (rtl_readphy(tp, 0x10) & 0x0004) | |
3531 | rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0004); | |
3532 | ||
41f44d13 | 3533 | rtl_writephy(tp, 0x1f, 0x0000); |
c558386b HW |
3534 | } |
3535 | ||
57538c4a | 3536 | static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp) |
3537 | { | |
3538 | rtl_apply_firmware(tp); | |
3539 | } | |
3540 | ||
6e1d0b89 CHL |
3541 | static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp) |
3542 | { | |
3543 | u16 dout_tapbin; | |
3544 | u32 data; | |
3545 | ||
3546 | rtl_apply_firmware(tp); | |
3547 | ||
3548 | /* CHN EST parameters adjust - giga master */ | |
3549 | rtl_writephy(tp, 0x1f, 0x0a43); | |
3550 | rtl_writephy(tp, 0x13, 0x809b); | |
3551 | rtl_w1w0_phy(tp, 0x14, 0x8000, 0xf800); | |
3552 | rtl_writephy(tp, 0x13, 0x80a2); | |
3553 | rtl_w1w0_phy(tp, 0x14, 0x8000, 0xff00); | |
3554 | rtl_writephy(tp, 0x13, 0x80a4); | |
3555 | rtl_w1w0_phy(tp, 0x14, 0x8500, 0xff00); | |
3556 | rtl_writephy(tp, 0x13, 0x809c); | |
3557 | rtl_w1w0_phy(tp, 0x14, 0xbd00, 0xff00); | |
3558 | rtl_writephy(tp, 0x1f, 0x0000); | |
3559 | ||
3560 | /* CHN EST parameters adjust - giga slave */ | |
3561 | rtl_writephy(tp, 0x1f, 0x0a43); | |
3562 | rtl_writephy(tp, 0x13, 0x80ad); | |
3563 | rtl_w1w0_phy(tp, 0x14, 0x7000, 0xf800); | |
3564 | rtl_writephy(tp, 0x13, 0x80b4); | |
3565 | rtl_w1w0_phy(tp, 0x14, 0x5000, 0xff00); | |
3566 | rtl_writephy(tp, 0x13, 0x80ac); | |
3567 | rtl_w1w0_phy(tp, 0x14, 0x4000, 0xff00); | |
3568 | rtl_writephy(tp, 0x1f, 0x0000); | |
3569 | ||
3570 | /* CHN EST parameters adjust - fnet */ | |
3571 | rtl_writephy(tp, 0x1f, 0x0a43); | |
3572 | rtl_writephy(tp, 0x13, 0x808e); | |
3573 | rtl_w1w0_phy(tp, 0x14, 0x1200, 0xff00); | |
3574 | rtl_writephy(tp, 0x13, 0x8090); | |
3575 | rtl_w1w0_phy(tp, 0x14, 0xe500, 0xff00); | |
3576 | rtl_writephy(tp, 0x13, 0x8092); | |
3577 | rtl_w1w0_phy(tp, 0x14, 0x9f00, 0xff00); | |
3578 | rtl_writephy(tp, 0x1f, 0x0000); | |
3579 | ||
3580 | /* enable R-tune & PGA-retune function */ | |
3581 | dout_tapbin = 0; | |
3582 | rtl_writephy(tp, 0x1f, 0x0a46); | |
3583 | data = rtl_readphy(tp, 0x13); | |
3584 | data &= 3; | |
3585 | data <<= 2; | |
3586 | dout_tapbin |= data; | |
3587 | data = rtl_readphy(tp, 0x12); | |
3588 | data &= 0xc000; | |
3589 | data >>= 14; | |
3590 | dout_tapbin |= data; | |
3591 | dout_tapbin = ~(dout_tapbin^0x08); | |
3592 | dout_tapbin <<= 12; | |
3593 | dout_tapbin &= 0xf000; | |
3594 | rtl_writephy(tp, 0x1f, 0x0a43); | |
3595 | rtl_writephy(tp, 0x13, 0x827a); | |
3596 | rtl_w1w0_phy(tp, 0x14, dout_tapbin, 0xf000); | |
3597 | rtl_writephy(tp, 0x13, 0x827b); | |
3598 | rtl_w1w0_phy(tp, 0x14, dout_tapbin, 0xf000); | |
3599 | rtl_writephy(tp, 0x13, 0x827c); | |
3600 | rtl_w1w0_phy(tp, 0x14, dout_tapbin, 0xf000); | |
3601 | rtl_writephy(tp, 0x13, 0x827d); | |
3602 | rtl_w1w0_phy(tp, 0x14, dout_tapbin, 0xf000); | |
3603 | ||
3604 | rtl_writephy(tp, 0x1f, 0x0a43); | |
3605 | rtl_writephy(tp, 0x13, 0x0811); | |
3606 | rtl_w1w0_phy(tp, 0x14, 0x0800, 0x0000); | |
3607 | rtl_writephy(tp, 0x1f, 0x0a42); | |
3608 | rtl_w1w0_phy(tp, 0x16, 0x0002, 0x0000); | |
3609 | rtl_writephy(tp, 0x1f, 0x0000); | |
3610 | ||
3611 | /* enable GPHY 10M */ | |
3612 | rtl_writephy(tp, 0x1f, 0x0a44); | |
3613 | rtl_w1w0_phy(tp, 0x11, 0x0800, 0x0000); | |
3614 | rtl_writephy(tp, 0x1f, 0x0000); | |
3615 | ||
3616 | /* SAR ADC performance */ | |
3617 | rtl_writephy(tp, 0x1f, 0x0bca); | |
3618 | rtl_w1w0_phy(tp, 0x17, 0x4000, 0x3000); | |
3619 | rtl_writephy(tp, 0x1f, 0x0000); | |
3620 | ||
3621 | rtl_writephy(tp, 0x1f, 0x0a43); | |
3622 | rtl_writephy(tp, 0x13, 0x803f); | |
3623 | rtl_w1w0_phy(tp, 0x14, 0x0000, 0x3000); | |
3624 | rtl_writephy(tp, 0x13, 0x8047); | |
3625 | rtl_w1w0_phy(tp, 0x14, 0x0000, 0x3000); | |
3626 | rtl_writephy(tp, 0x13, 0x804f); | |
3627 | rtl_w1w0_phy(tp, 0x14, 0x0000, 0x3000); | |
3628 | rtl_writephy(tp, 0x13, 0x8057); | |
3629 | rtl_w1w0_phy(tp, 0x14, 0x0000, 0x3000); | |
3630 | rtl_writephy(tp, 0x13, 0x805f); | |
3631 | rtl_w1w0_phy(tp, 0x14, 0x0000, 0x3000); | |
3632 | rtl_writephy(tp, 0x13, 0x8067); | |
3633 | rtl_w1w0_phy(tp, 0x14, 0x0000, 0x3000); | |
3634 | rtl_writephy(tp, 0x13, 0x806f); | |
3635 | rtl_w1w0_phy(tp, 0x14, 0x0000, 0x3000); | |
3636 | rtl_writephy(tp, 0x1f, 0x0000); | |
3637 | ||
3638 | /* disable phy pfm mode */ | |
3639 | rtl_writephy(tp, 0x1f, 0x0a44); | |
3640 | rtl_w1w0_phy(tp, 0x14, 0x0000, 0x0080); | |
3641 | rtl_writephy(tp, 0x1f, 0x0000); | |
3642 | ||
3643 | /* Check ALDPS bit, disable it if enabled */ | |
3644 | rtl_writephy(tp, 0x1f, 0x0a43); | |
3645 | if (rtl_readphy(tp, 0x10) & 0x0004) | |
3646 | rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0004); | |
3647 | ||
3648 | rtl_writephy(tp, 0x1f, 0x0000); | |
3649 | } | |
3650 | ||
3651 | static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp) | |
3652 | { | |
3653 | u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0; | |
3654 | u16 rlen; | |
3655 | u32 data; | |
3656 | ||
3657 | rtl_apply_firmware(tp); | |
3658 | ||
3659 | /* CHIN EST parameter update */ | |
3660 | rtl_writephy(tp, 0x1f, 0x0a43); | |
3661 | rtl_writephy(tp, 0x13, 0x808a); | |
3662 | rtl_w1w0_phy(tp, 0x14, 0x000a, 0x003f); | |
3663 | rtl_writephy(tp, 0x1f, 0x0000); | |
3664 | ||
3665 | /* enable R-tune & PGA-retune function */ | |
3666 | rtl_writephy(tp, 0x1f, 0x0a43); | |
3667 | rtl_writephy(tp, 0x13, 0x0811); | |
3668 | rtl_w1w0_phy(tp, 0x14, 0x0800, 0x0000); | |
3669 | rtl_writephy(tp, 0x1f, 0x0a42); | |
3670 | rtl_w1w0_phy(tp, 0x16, 0x0002, 0x0000); | |
3671 | rtl_writephy(tp, 0x1f, 0x0000); | |
3672 | ||
3673 | /* enable GPHY 10M */ | |
3674 | rtl_writephy(tp, 0x1f, 0x0a44); | |
3675 | rtl_w1w0_phy(tp, 0x11, 0x0800, 0x0000); | |
3676 | rtl_writephy(tp, 0x1f, 0x0000); | |
3677 | ||
3678 | r8168_mac_ocp_write(tp, 0xdd02, 0x807d); | |
3679 | data = r8168_mac_ocp_read(tp, 0xdd02); | |
3680 | ioffset_p3 = ((data & 0x80)>>7); | |
3681 | ioffset_p3 <<= 3; | |
3682 | ||
3683 | data = r8168_mac_ocp_read(tp, 0xdd00); | |
3684 | ioffset_p3 |= ((data & (0xe000))>>13); | |
3685 | ioffset_p2 = ((data & (0x1e00))>>9); | |
3686 | ioffset_p1 = ((data & (0x01e0))>>5); | |
3687 | ioffset_p0 = ((data & 0x0010)>>4); | |
3688 | ioffset_p0 <<= 3; | |
3689 | ioffset_p0 |= (data & (0x07)); | |
3690 | data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0); | |
3691 | ||
3692 | if ((ioffset_p3 != 0x0F) || (ioffset_p2 != 0x0F) || | |
3693 | (ioffset_p1 != 0x0F) || (ioffset_p0 == 0x0F)) { | |
3694 | rtl_writephy(tp, 0x1f, 0x0bcf); | |
3695 | rtl_writephy(tp, 0x16, data); | |
3696 | rtl_writephy(tp, 0x1f, 0x0000); | |
3697 | } | |
3698 | ||
3699 | /* Modify rlen (TX LPF corner frequency) level */ | |
3700 | rtl_writephy(tp, 0x1f, 0x0bcd); | |
3701 | data = rtl_readphy(tp, 0x16); | |
3702 | data &= 0x000f; | |
3703 | rlen = 0; | |
3704 | if (data > 3) | |
3705 | rlen = data - 3; | |
3706 | data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12); | |
3707 | rtl_writephy(tp, 0x17, data); | |
3708 | rtl_writephy(tp, 0x1f, 0x0bcd); | |
3709 | rtl_writephy(tp, 0x1f, 0x0000); | |
3710 | ||
3711 | /* disable phy pfm mode */ | |
3712 | rtl_writephy(tp, 0x1f, 0x0a44); | |
3713 | rtl_w1w0_phy(tp, 0x14, 0x0000, 0x0080); | |
3714 | rtl_writephy(tp, 0x1f, 0x0000); | |
3715 | ||
3716 | /* Check ALDPS bit, disable it if enabled */ | |
3717 | rtl_writephy(tp, 0x1f, 0x0a43); | |
3718 | if (rtl_readphy(tp, 0x10) & 0x0004) | |
3719 | rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0004); | |
3720 | ||
3721 | rtl_writephy(tp, 0x1f, 0x0000); | |
3722 | } | |
3723 | ||
4da19633 | 3724 | static void rtl8102e_hw_phy_config(struct rtl8169_private *tp) |
2857ffb7 | 3725 | { |
350f7596 | 3726 | static const struct phy_reg phy_reg_init[] = { |
2857ffb7 FR |
3727 | { 0x1f, 0x0003 }, |
3728 | { 0x08, 0x441d }, | |
3729 | { 0x01, 0x9100 }, | |
3730 | { 0x1f, 0x0000 } | |
3731 | }; | |
3732 | ||
4da19633 | 3733 | rtl_writephy(tp, 0x1f, 0x0000); |
3734 | rtl_patchphy(tp, 0x11, 1 << 12); | |
3735 | rtl_patchphy(tp, 0x19, 1 << 13); | |
3736 | rtl_patchphy(tp, 0x10, 1 << 15); | |
2857ffb7 | 3737 | |
4da19633 | 3738 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
2857ffb7 FR |
3739 | } |
3740 | ||
5a5e4443 HW |
3741 | static void rtl8105e_hw_phy_config(struct rtl8169_private *tp) |
3742 | { | |
3743 | static const struct phy_reg phy_reg_init[] = { | |
3744 | { 0x1f, 0x0005 }, | |
3745 | { 0x1a, 0x0000 }, | |
3746 | { 0x1f, 0x0000 }, | |
3747 | ||
3748 | { 0x1f, 0x0004 }, | |
3749 | { 0x1c, 0x0000 }, | |
3750 | { 0x1f, 0x0000 }, | |
3751 | ||
3752 | { 0x1f, 0x0001 }, | |
3753 | { 0x15, 0x7701 }, | |
3754 | { 0x1f, 0x0000 } | |
3755 | }; | |
3756 | ||
3757 | /* Disable ALDPS before ram code */ | |
eef63cc1 FR |
3758 | rtl_writephy(tp, 0x1f, 0x0000); |
3759 | rtl_writephy(tp, 0x18, 0x0310); | |
3760 | msleep(100); | |
5a5e4443 | 3761 | |
953a12cc | 3762 | rtl_apply_firmware(tp); |
5a5e4443 HW |
3763 | |
3764 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | |
3765 | } | |
3766 | ||
7e18dca1 HW |
3767 | static void rtl8402_hw_phy_config(struct rtl8169_private *tp) |
3768 | { | |
7e18dca1 | 3769 | /* Disable ALDPS before setting firmware */ |
eef63cc1 FR |
3770 | rtl_writephy(tp, 0x1f, 0x0000); |
3771 | rtl_writephy(tp, 0x18, 0x0310); | |
3772 | msleep(20); | |
7e18dca1 HW |
3773 | |
3774 | rtl_apply_firmware(tp); | |
3775 | ||
3776 | /* EEE setting */ | |
fdf6fc06 | 3777 | rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); |
7e18dca1 HW |
3778 | rtl_writephy(tp, 0x1f, 0x0004); |
3779 | rtl_writephy(tp, 0x10, 0x401f); | |
3780 | rtl_writephy(tp, 0x19, 0x7030); | |
3781 | rtl_writephy(tp, 0x1f, 0x0000); | |
3782 | } | |
3783 | ||
5598bfe5 HW |
3784 | static void rtl8106e_hw_phy_config(struct rtl8169_private *tp) |
3785 | { | |
5598bfe5 HW |
3786 | static const struct phy_reg phy_reg_init[] = { |
3787 | { 0x1f, 0x0004 }, | |
3788 | { 0x10, 0xc07f }, | |
3789 | { 0x19, 0x7030 }, | |
3790 | { 0x1f, 0x0000 } | |
3791 | }; | |
3792 | ||
3793 | /* Disable ALDPS before ram code */ | |
eef63cc1 FR |
3794 | rtl_writephy(tp, 0x1f, 0x0000); |
3795 | rtl_writephy(tp, 0x18, 0x0310); | |
3796 | msleep(100); | |
5598bfe5 HW |
3797 | |
3798 | rtl_apply_firmware(tp); | |
3799 | ||
fdf6fc06 | 3800 | rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); |
5598bfe5 HW |
3801 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
3802 | ||
fdf6fc06 | 3803 | rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); |
5598bfe5 HW |
3804 | } |
3805 | ||
5615d9f1 FR |
3806 | static void rtl_hw_phy_config(struct net_device *dev) |
3807 | { | |
3808 | struct rtl8169_private *tp = netdev_priv(dev); | |
5615d9f1 FR |
3809 | |
3810 | rtl8169_print_mac_version(tp); | |
3811 | ||
3812 | switch (tp->mac_version) { | |
3813 | case RTL_GIGA_MAC_VER_01: | |
3814 | break; | |
3815 | case RTL_GIGA_MAC_VER_02: | |
3816 | case RTL_GIGA_MAC_VER_03: | |
4da19633 | 3817 | rtl8169s_hw_phy_config(tp); |
5615d9f1 FR |
3818 | break; |
3819 | case RTL_GIGA_MAC_VER_04: | |
4da19633 | 3820 | rtl8169sb_hw_phy_config(tp); |
5615d9f1 | 3821 | break; |
2e955856 | 3822 | case RTL_GIGA_MAC_VER_05: |
4da19633 | 3823 | rtl8169scd_hw_phy_config(tp); |
2e955856 | 3824 | break; |
8c7006aa | 3825 | case RTL_GIGA_MAC_VER_06: |
4da19633 | 3826 | rtl8169sce_hw_phy_config(tp); |
8c7006aa | 3827 | break; |
2857ffb7 FR |
3828 | case RTL_GIGA_MAC_VER_07: |
3829 | case RTL_GIGA_MAC_VER_08: | |
3830 | case RTL_GIGA_MAC_VER_09: | |
4da19633 | 3831 | rtl8102e_hw_phy_config(tp); |
2857ffb7 | 3832 | break; |
236b8082 | 3833 | case RTL_GIGA_MAC_VER_11: |
4da19633 | 3834 | rtl8168bb_hw_phy_config(tp); |
236b8082 FR |
3835 | break; |
3836 | case RTL_GIGA_MAC_VER_12: | |
4da19633 | 3837 | rtl8168bef_hw_phy_config(tp); |
236b8082 FR |
3838 | break; |
3839 | case RTL_GIGA_MAC_VER_17: | |
4da19633 | 3840 | rtl8168bef_hw_phy_config(tp); |
236b8082 | 3841 | break; |
867763c1 | 3842 | case RTL_GIGA_MAC_VER_18: |
4da19633 | 3843 | rtl8168cp_1_hw_phy_config(tp); |
867763c1 FR |
3844 | break; |
3845 | case RTL_GIGA_MAC_VER_19: | |
4da19633 | 3846 | rtl8168c_1_hw_phy_config(tp); |
867763c1 | 3847 | break; |
7da97ec9 | 3848 | case RTL_GIGA_MAC_VER_20: |
4da19633 | 3849 | rtl8168c_2_hw_phy_config(tp); |
7da97ec9 | 3850 | break; |
197ff761 | 3851 | case RTL_GIGA_MAC_VER_21: |
4da19633 | 3852 | rtl8168c_3_hw_phy_config(tp); |
197ff761 | 3853 | break; |
6fb07058 | 3854 | case RTL_GIGA_MAC_VER_22: |
4da19633 | 3855 | rtl8168c_4_hw_phy_config(tp); |
6fb07058 | 3856 | break; |
ef3386f0 | 3857 | case RTL_GIGA_MAC_VER_23: |
7f3e3d3a | 3858 | case RTL_GIGA_MAC_VER_24: |
4da19633 | 3859 | rtl8168cp_2_hw_phy_config(tp); |
ef3386f0 | 3860 | break; |
5b538df9 | 3861 | case RTL_GIGA_MAC_VER_25: |
bca03d5f | 3862 | rtl8168d_1_hw_phy_config(tp); |
daf9df6d | 3863 | break; |
3864 | case RTL_GIGA_MAC_VER_26: | |
bca03d5f | 3865 | rtl8168d_2_hw_phy_config(tp); |
daf9df6d | 3866 | break; |
3867 | case RTL_GIGA_MAC_VER_27: | |
4da19633 | 3868 | rtl8168d_3_hw_phy_config(tp); |
5b538df9 | 3869 | break; |
e6de30d6 | 3870 | case RTL_GIGA_MAC_VER_28: |
3871 | rtl8168d_4_hw_phy_config(tp); | |
3872 | break; | |
5a5e4443 HW |
3873 | case RTL_GIGA_MAC_VER_29: |
3874 | case RTL_GIGA_MAC_VER_30: | |
3875 | rtl8105e_hw_phy_config(tp); | |
3876 | break; | |
cecb5fd7 FR |
3877 | case RTL_GIGA_MAC_VER_31: |
3878 | /* None. */ | |
3879 | break; | |
01dc7fec | 3880 | case RTL_GIGA_MAC_VER_32: |
01dc7fec | 3881 | case RTL_GIGA_MAC_VER_33: |
70090424 HW |
3882 | rtl8168e_1_hw_phy_config(tp); |
3883 | break; | |
3884 | case RTL_GIGA_MAC_VER_34: | |
3885 | rtl8168e_2_hw_phy_config(tp); | |
01dc7fec | 3886 | break; |
c2218925 HW |
3887 | case RTL_GIGA_MAC_VER_35: |
3888 | rtl8168f_1_hw_phy_config(tp); | |
3889 | break; | |
3890 | case RTL_GIGA_MAC_VER_36: | |
3891 | rtl8168f_2_hw_phy_config(tp); | |
3892 | break; | |
ef3386f0 | 3893 | |
7e18dca1 HW |
3894 | case RTL_GIGA_MAC_VER_37: |
3895 | rtl8402_hw_phy_config(tp); | |
3896 | break; | |
3897 | ||
b3d7b2f2 HW |
3898 | case RTL_GIGA_MAC_VER_38: |
3899 | rtl8411_hw_phy_config(tp); | |
3900 | break; | |
3901 | ||
5598bfe5 HW |
3902 | case RTL_GIGA_MAC_VER_39: |
3903 | rtl8106e_hw_phy_config(tp); | |
3904 | break; | |
3905 | ||
c558386b HW |
3906 | case RTL_GIGA_MAC_VER_40: |
3907 | rtl8168g_1_hw_phy_config(tp); | |
3908 | break; | |
57538c4a | 3909 | case RTL_GIGA_MAC_VER_42: |
58152cd4 | 3910 | case RTL_GIGA_MAC_VER_43: |
45dd95c4 | 3911 | case RTL_GIGA_MAC_VER_44: |
57538c4a | 3912 | rtl8168g_2_hw_phy_config(tp); |
3913 | break; | |
6e1d0b89 CHL |
3914 | case RTL_GIGA_MAC_VER_45: |
3915 | case RTL_GIGA_MAC_VER_47: | |
3916 | rtl8168h_1_hw_phy_config(tp); | |
3917 | break; | |
3918 | case RTL_GIGA_MAC_VER_46: | |
3919 | case RTL_GIGA_MAC_VER_48: | |
3920 | rtl8168h_2_hw_phy_config(tp); | |
3921 | break; | |
c558386b HW |
3922 | |
3923 | case RTL_GIGA_MAC_VER_41: | |
5615d9f1 FR |
3924 | default: |
3925 | break; | |
3926 | } | |
3927 | } | |
3928 | ||
da78dbff | 3929 | static void rtl_phy_work(struct rtl8169_private *tp) |
1da177e4 | 3930 | { |
1da177e4 LT |
3931 | struct timer_list *timer = &tp->timer; |
3932 | void __iomem *ioaddr = tp->mmio_addr; | |
3933 | unsigned long timeout = RTL8169_PHY_TIMEOUT; | |
3934 | ||
bcf0bf90 | 3935 | assert(tp->mac_version > RTL_GIGA_MAC_VER_01); |
1da177e4 | 3936 | |
4da19633 | 3937 | if (tp->phy_reset_pending(tp)) { |
5b0384f4 | 3938 | /* |
1da177e4 LT |
3939 | * A busy loop could burn quite a few cycles on nowadays CPU. |
3940 | * Let's delay the execution of the timer for a few ticks. | |
3941 | */ | |
3942 | timeout = HZ/10; | |
3943 | goto out_mod_timer; | |
3944 | } | |
3945 | ||
3946 | if (tp->link_ok(ioaddr)) | |
da78dbff | 3947 | return; |
1da177e4 | 3948 | |
9bb8eeb5 | 3949 | netif_dbg(tp, link, tp->dev, "PHY reset until link up\n"); |
1da177e4 | 3950 | |
4da19633 | 3951 | tp->phy_reset_enable(tp); |
1da177e4 LT |
3952 | |
3953 | out_mod_timer: | |
3954 | mod_timer(timer, jiffies + timeout); | |
da78dbff FR |
3955 | } |
3956 | ||
3957 | static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag) | |
3958 | { | |
da78dbff FR |
3959 | if (!test_and_set_bit(flag, tp->wk.flags)) |
3960 | schedule_work(&tp->wk.work); | |
da78dbff FR |
3961 | } |
3962 | ||
3963 | static void rtl8169_phy_timer(unsigned long __opaque) | |
3964 | { | |
3965 | struct net_device *dev = (struct net_device *)__opaque; | |
3966 | struct rtl8169_private *tp = netdev_priv(dev); | |
3967 | ||
98ddf986 | 3968 | rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING); |
1da177e4 LT |
3969 | } |
3970 | ||
1da177e4 LT |
3971 | static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev, |
3972 | void __iomem *ioaddr) | |
3973 | { | |
3974 | iounmap(ioaddr); | |
3975 | pci_release_regions(pdev); | |
87aeec76 | 3976 | pci_clear_mwi(pdev); |
1da177e4 LT |
3977 | pci_disable_device(pdev); |
3978 | free_netdev(dev); | |
3979 | } | |
3980 | ||
ffc46952 FR |
3981 | DECLARE_RTL_COND(rtl_phy_reset_cond) |
3982 | { | |
3983 | return tp->phy_reset_pending(tp); | |
3984 | } | |
3985 | ||
bf793295 FR |
3986 | static void rtl8169_phy_reset(struct net_device *dev, |
3987 | struct rtl8169_private *tp) | |
3988 | { | |
4da19633 | 3989 | tp->phy_reset_enable(tp); |
ffc46952 | 3990 | rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100); |
bf793295 FR |
3991 | } |
3992 | ||
2544bfc0 FR |
3993 | static bool rtl_tbi_enabled(struct rtl8169_private *tp) |
3994 | { | |
3995 | void __iomem *ioaddr = tp->mmio_addr; | |
3996 | ||
3997 | return (tp->mac_version == RTL_GIGA_MAC_VER_01) && | |
3998 | (RTL_R8(PHYstatus) & TBI_Enable); | |
3999 | } | |
4000 | ||
4ff96fa6 FR |
4001 | static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp) |
4002 | { | |
4003 | void __iomem *ioaddr = tp->mmio_addr; | |
4ff96fa6 | 4004 | |
5615d9f1 | 4005 | rtl_hw_phy_config(dev); |
4ff96fa6 | 4006 | |
77332894 MS |
4007 | if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { |
4008 | dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); | |
4009 | RTL_W8(0x82, 0x01); | |
4010 | } | |
4ff96fa6 | 4011 | |
6dccd16b FR |
4012 | pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); |
4013 | ||
4014 | if (tp->mac_version <= RTL_GIGA_MAC_VER_06) | |
4015 | pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); | |
4ff96fa6 | 4016 | |
bcf0bf90 | 4017 | if (tp->mac_version == RTL_GIGA_MAC_VER_02) { |
4ff96fa6 FR |
4018 | dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); |
4019 | RTL_W8(0x82, 0x01); | |
4020 | dprintk("Set PHY Reg 0x0bh = 0x00h\n"); | |
4da19633 | 4021 | rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0 |
4ff96fa6 FR |
4022 | } |
4023 | ||
bf793295 FR |
4024 | rtl8169_phy_reset(dev, tp); |
4025 | ||
54405cde | 4026 | rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL, |
cecb5fd7 FR |
4027 | ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | |
4028 | ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | | |
4029 | (tp->mii.supports_gmii ? | |
4030 | ADVERTISED_1000baseT_Half | | |
4031 | ADVERTISED_1000baseT_Full : 0)); | |
4ff96fa6 | 4032 | |
2544bfc0 | 4033 | if (rtl_tbi_enabled(tp)) |
bf82c189 | 4034 | netif_info(tp, link, dev, "TBI auto-negotiating\n"); |
4ff96fa6 FR |
4035 | } |
4036 | ||
773d2021 FR |
4037 | static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr) |
4038 | { | |
4039 | void __iomem *ioaddr = tp->mmio_addr; | |
773d2021 | 4040 | |
da78dbff | 4041 | rtl_lock_work(tp); |
773d2021 FR |
4042 | |
4043 | RTL_W8(Cfg9346, Cfg9346_Unlock); | |
908ba2bf | 4044 | |
9ecb9aab | 4045 | RTL_W32(MAC4, addr[4] | addr[5] << 8); |
908ba2bf | 4046 | RTL_R32(MAC4); |
4047 | ||
9ecb9aab | 4048 | RTL_W32(MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); |
908ba2bf | 4049 | RTL_R32(MAC0); |
4050 | ||
9ecb9aab | 4051 | if (tp->mac_version == RTL_GIGA_MAC_VER_34) |
4052 | rtl_rar_exgmac_set(tp, addr); | |
c28aa385 | 4053 | |
773d2021 FR |
4054 | RTL_W8(Cfg9346, Cfg9346_Lock); |
4055 | ||
da78dbff | 4056 | rtl_unlock_work(tp); |
773d2021 FR |
4057 | } |
4058 | ||
4059 | static int rtl_set_mac_address(struct net_device *dev, void *p) | |
4060 | { | |
4061 | struct rtl8169_private *tp = netdev_priv(dev); | |
4062 | struct sockaddr *addr = p; | |
4063 | ||
4064 | if (!is_valid_ether_addr(addr->sa_data)) | |
4065 | return -EADDRNOTAVAIL; | |
4066 | ||
4067 | memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); | |
4068 | ||
4069 | rtl_rar_set(tp, dev->dev_addr); | |
4070 | ||
4071 | return 0; | |
4072 | } | |
4073 | ||
5f787a1a FR |
4074 | static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
4075 | { | |
4076 | struct rtl8169_private *tp = netdev_priv(dev); | |
4077 | struct mii_ioctl_data *data = if_mii(ifr); | |
4078 | ||
8b4ab28d FR |
4079 | return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV; |
4080 | } | |
5f787a1a | 4081 | |
cecb5fd7 FR |
4082 | static int rtl_xmii_ioctl(struct rtl8169_private *tp, |
4083 | struct mii_ioctl_data *data, int cmd) | |
8b4ab28d | 4084 | { |
5f787a1a FR |
4085 | switch (cmd) { |
4086 | case SIOCGMIIPHY: | |
4087 | data->phy_id = 32; /* Internal PHY */ | |
4088 | return 0; | |
4089 | ||
4090 | case SIOCGMIIREG: | |
4da19633 | 4091 | data->val_out = rtl_readphy(tp, data->reg_num & 0x1f); |
5f787a1a FR |
4092 | return 0; |
4093 | ||
4094 | case SIOCSMIIREG: | |
4da19633 | 4095 | rtl_writephy(tp, data->reg_num & 0x1f, data->val_in); |
5f787a1a FR |
4096 | return 0; |
4097 | } | |
4098 | return -EOPNOTSUPP; | |
4099 | } | |
4100 | ||
8b4ab28d FR |
4101 | static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd) |
4102 | { | |
4103 | return -EOPNOTSUPP; | |
4104 | } | |
4105 | ||
fbac58fc FR |
4106 | static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp) |
4107 | { | |
4108 | if (tp->features & RTL_FEATURE_MSI) { | |
4109 | pci_disable_msi(pdev); | |
4110 | tp->features &= ~RTL_FEATURE_MSI; | |
4111 | } | |
4112 | } | |
4113 | ||
baf63293 | 4114 | static void rtl_init_mdio_ops(struct rtl8169_private *tp) |
c0e45c1c | 4115 | { |
4116 | struct mdio_ops *ops = &tp->mdio_ops; | |
4117 | ||
4118 | switch (tp->mac_version) { | |
4119 | case RTL_GIGA_MAC_VER_27: | |
4120 | ops->write = r8168dp_1_mdio_write; | |
4121 | ops->read = r8168dp_1_mdio_read; | |
4122 | break; | |
e6de30d6 | 4123 | case RTL_GIGA_MAC_VER_28: |
4804b3b3 | 4124 | case RTL_GIGA_MAC_VER_31: |
e6de30d6 | 4125 | ops->write = r8168dp_2_mdio_write; |
4126 | ops->read = r8168dp_2_mdio_read; | |
4127 | break; | |
c558386b HW |
4128 | case RTL_GIGA_MAC_VER_40: |
4129 | case RTL_GIGA_MAC_VER_41: | |
57538c4a | 4130 | case RTL_GIGA_MAC_VER_42: |
58152cd4 | 4131 | case RTL_GIGA_MAC_VER_43: |
45dd95c4 | 4132 | case RTL_GIGA_MAC_VER_44: |
6e1d0b89 CHL |
4133 | case RTL_GIGA_MAC_VER_45: |
4134 | case RTL_GIGA_MAC_VER_46: | |
4135 | case RTL_GIGA_MAC_VER_47: | |
4136 | case RTL_GIGA_MAC_VER_48: | |
c558386b HW |
4137 | ops->write = r8168g_mdio_write; |
4138 | ops->read = r8168g_mdio_read; | |
4139 | break; | |
c0e45c1c | 4140 | default: |
4141 | ops->write = r8169_mdio_write; | |
4142 | ops->read = r8169_mdio_read; | |
4143 | break; | |
4144 | } | |
4145 | } | |
4146 | ||
e2409d83 | 4147 | static void rtl_speed_down(struct rtl8169_private *tp) |
4148 | { | |
4149 | u32 adv; | |
4150 | int lpa; | |
4151 | ||
4152 | rtl_writephy(tp, 0x1f, 0x0000); | |
4153 | lpa = rtl_readphy(tp, MII_LPA); | |
4154 | ||
4155 | if (lpa & (LPA_10HALF | LPA_10FULL)) | |
4156 | adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full; | |
4157 | else if (lpa & (LPA_100HALF | LPA_100FULL)) | |
4158 | adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | | |
4159 | ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full; | |
4160 | else | |
4161 | adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | | |
4162 | ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | | |
4163 | (tp->mii.supports_gmii ? | |
4164 | ADVERTISED_1000baseT_Half | | |
4165 | ADVERTISED_1000baseT_Full : 0); | |
4166 | ||
4167 | rtl8169_set_speed(tp->dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL, | |
4168 | adv); | |
4169 | } | |
4170 | ||
649b3b8c | 4171 | static void rtl_wol_suspend_quirk(struct rtl8169_private *tp) |
4172 | { | |
4173 | void __iomem *ioaddr = tp->mmio_addr; | |
4174 | ||
4175 | switch (tp->mac_version) { | |
b00e69de CB |
4176 | case RTL_GIGA_MAC_VER_25: |
4177 | case RTL_GIGA_MAC_VER_26: | |
649b3b8c | 4178 | case RTL_GIGA_MAC_VER_29: |
4179 | case RTL_GIGA_MAC_VER_30: | |
4180 | case RTL_GIGA_MAC_VER_32: | |
4181 | case RTL_GIGA_MAC_VER_33: | |
4182 | case RTL_GIGA_MAC_VER_34: | |
7e18dca1 | 4183 | case RTL_GIGA_MAC_VER_37: |
b3d7b2f2 | 4184 | case RTL_GIGA_MAC_VER_38: |
5598bfe5 | 4185 | case RTL_GIGA_MAC_VER_39: |
c558386b HW |
4186 | case RTL_GIGA_MAC_VER_40: |
4187 | case RTL_GIGA_MAC_VER_41: | |
57538c4a | 4188 | case RTL_GIGA_MAC_VER_42: |
58152cd4 | 4189 | case RTL_GIGA_MAC_VER_43: |
45dd95c4 | 4190 | case RTL_GIGA_MAC_VER_44: |
6e1d0b89 CHL |
4191 | case RTL_GIGA_MAC_VER_45: |
4192 | case RTL_GIGA_MAC_VER_46: | |
4193 | case RTL_GIGA_MAC_VER_47: | |
4194 | case RTL_GIGA_MAC_VER_48: | |
649b3b8c | 4195 | RTL_W32(RxConfig, RTL_R32(RxConfig) | |
4196 | AcceptBroadcast | AcceptMulticast | AcceptMyPhys); | |
4197 | break; | |
4198 | default: | |
4199 | break; | |
4200 | } | |
4201 | } | |
4202 | ||
4203 | static bool rtl_wol_pll_power_down(struct rtl8169_private *tp) | |
4204 | { | |
4205 | if (!(__rtl8169_get_wol(tp) & WAKE_ANY)) | |
4206 | return false; | |
4207 | ||
e2409d83 | 4208 | rtl_speed_down(tp); |
649b3b8c | 4209 | rtl_wol_suspend_quirk(tp); |
4210 | ||
4211 | return true; | |
4212 | } | |
4213 | ||
065c27c1 | 4214 | static void r810x_phy_power_down(struct rtl8169_private *tp) |
4215 | { | |
4216 | rtl_writephy(tp, 0x1f, 0x0000); | |
4217 | rtl_writephy(tp, MII_BMCR, BMCR_PDOWN); | |
4218 | } | |
4219 | ||
4220 | static void r810x_phy_power_up(struct rtl8169_private *tp) | |
4221 | { | |
4222 | rtl_writephy(tp, 0x1f, 0x0000); | |
4223 | rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE); | |
4224 | } | |
4225 | ||
4226 | static void r810x_pll_power_down(struct rtl8169_private *tp) | |
4227 | { | |
0004299a HW |
4228 | void __iomem *ioaddr = tp->mmio_addr; |
4229 | ||
649b3b8c | 4230 | if (rtl_wol_pll_power_down(tp)) |
065c27c1 | 4231 | return; |
065c27c1 | 4232 | |
4233 | r810x_phy_power_down(tp); | |
0004299a HW |
4234 | |
4235 | switch (tp->mac_version) { | |
4236 | case RTL_GIGA_MAC_VER_07: | |
4237 | case RTL_GIGA_MAC_VER_08: | |
4238 | case RTL_GIGA_MAC_VER_09: | |
4239 | case RTL_GIGA_MAC_VER_10: | |
4240 | case RTL_GIGA_MAC_VER_13: | |
4241 | case RTL_GIGA_MAC_VER_16: | |
4242 | break; | |
4243 | default: | |
4244 | RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80); | |
4245 | break; | |
4246 | } | |
065c27c1 | 4247 | } |
4248 | ||
4249 | static void r810x_pll_power_up(struct rtl8169_private *tp) | |
4250 | { | |
0004299a HW |
4251 | void __iomem *ioaddr = tp->mmio_addr; |
4252 | ||
065c27c1 | 4253 | r810x_phy_power_up(tp); |
0004299a HW |
4254 | |
4255 | switch (tp->mac_version) { | |
4256 | case RTL_GIGA_MAC_VER_07: | |
4257 | case RTL_GIGA_MAC_VER_08: | |
4258 | case RTL_GIGA_MAC_VER_09: | |
4259 | case RTL_GIGA_MAC_VER_10: | |
4260 | case RTL_GIGA_MAC_VER_13: | |
4261 | case RTL_GIGA_MAC_VER_16: | |
4262 | break; | |
6e1d0b89 CHL |
4263 | case RTL_GIGA_MAC_VER_47: |
4264 | case RTL_GIGA_MAC_VER_48: | |
4265 | RTL_W8(PMCH, RTL_R8(PMCH) | 0xC0); | |
4266 | break; | |
0004299a HW |
4267 | default: |
4268 | RTL_W8(PMCH, RTL_R8(PMCH) | 0x80); | |
4269 | break; | |
4270 | } | |
065c27c1 | 4271 | } |
4272 | ||
4273 | static void r8168_phy_power_up(struct rtl8169_private *tp) | |
4274 | { | |
4275 | rtl_writephy(tp, 0x1f, 0x0000); | |
01dc7fec | 4276 | switch (tp->mac_version) { |
4277 | case RTL_GIGA_MAC_VER_11: | |
4278 | case RTL_GIGA_MAC_VER_12: | |
4279 | case RTL_GIGA_MAC_VER_17: | |
4280 | case RTL_GIGA_MAC_VER_18: | |
4281 | case RTL_GIGA_MAC_VER_19: | |
4282 | case RTL_GIGA_MAC_VER_20: | |
4283 | case RTL_GIGA_MAC_VER_21: | |
4284 | case RTL_GIGA_MAC_VER_22: | |
4285 | case RTL_GIGA_MAC_VER_23: | |
4286 | case RTL_GIGA_MAC_VER_24: | |
4287 | case RTL_GIGA_MAC_VER_25: | |
4288 | case RTL_GIGA_MAC_VER_26: | |
4289 | case RTL_GIGA_MAC_VER_27: | |
4290 | case RTL_GIGA_MAC_VER_28: | |
4291 | case RTL_GIGA_MAC_VER_31: | |
4292 | rtl_writephy(tp, 0x0e, 0x0000); | |
4293 | break; | |
4294 | default: | |
4295 | break; | |
4296 | } | |
065c27c1 | 4297 | rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE); |
4298 | } | |
4299 | ||
4300 | static void r8168_phy_power_down(struct rtl8169_private *tp) | |
4301 | { | |
4302 | rtl_writephy(tp, 0x1f, 0x0000); | |
01dc7fec | 4303 | switch (tp->mac_version) { |
4304 | case RTL_GIGA_MAC_VER_32: | |
4305 | case RTL_GIGA_MAC_VER_33: | |
beb330a4 | 4306 | case RTL_GIGA_MAC_VER_40: |
4307 | case RTL_GIGA_MAC_VER_41: | |
01dc7fec | 4308 | rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN); |
4309 | break; | |
4310 | ||
4311 | case RTL_GIGA_MAC_VER_11: | |
4312 | case RTL_GIGA_MAC_VER_12: | |
4313 | case RTL_GIGA_MAC_VER_17: | |
4314 | case RTL_GIGA_MAC_VER_18: | |
4315 | case RTL_GIGA_MAC_VER_19: | |
4316 | case RTL_GIGA_MAC_VER_20: | |
4317 | case RTL_GIGA_MAC_VER_21: | |
4318 | case RTL_GIGA_MAC_VER_22: | |
4319 | case RTL_GIGA_MAC_VER_23: | |
4320 | case RTL_GIGA_MAC_VER_24: | |
4321 | case RTL_GIGA_MAC_VER_25: | |
4322 | case RTL_GIGA_MAC_VER_26: | |
4323 | case RTL_GIGA_MAC_VER_27: | |
4324 | case RTL_GIGA_MAC_VER_28: | |
4325 | case RTL_GIGA_MAC_VER_31: | |
4326 | rtl_writephy(tp, 0x0e, 0x0200); | |
4327 | default: | |
4328 | rtl_writephy(tp, MII_BMCR, BMCR_PDOWN); | |
4329 | break; | |
4330 | } | |
065c27c1 | 4331 | } |
4332 | ||
4333 | static void r8168_pll_power_down(struct rtl8169_private *tp) | |
4334 | { | |
4335 | void __iomem *ioaddr = tp->mmio_addr; | |
4336 | ||
cecb5fd7 FR |
4337 | if ((tp->mac_version == RTL_GIGA_MAC_VER_27 || |
4338 | tp->mac_version == RTL_GIGA_MAC_VER_28 || | |
4339 | tp->mac_version == RTL_GIGA_MAC_VER_31) && | |
4804b3b3 | 4340 | r8168dp_check_dash(tp)) { |
065c27c1 | 4341 | return; |
5d2e1957 | 4342 | } |
065c27c1 | 4343 | |
cecb5fd7 FR |
4344 | if ((tp->mac_version == RTL_GIGA_MAC_VER_23 || |
4345 | tp->mac_version == RTL_GIGA_MAC_VER_24) && | |
065c27c1 | 4346 | (RTL_R16(CPlusCmd) & ASF)) { |
4347 | return; | |
4348 | } | |
4349 | ||
01dc7fec | 4350 | if (tp->mac_version == RTL_GIGA_MAC_VER_32 || |
4351 | tp->mac_version == RTL_GIGA_MAC_VER_33) | |
fdf6fc06 | 4352 | rtl_ephy_write(tp, 0x19, 0xff64); |
01dc7fec | 4353 | |
649b3b8c | 4354 | if (rtl_wol_pll_power_down(tp)) |
065c27c1 | 4355 | return; |
065c27c1 | 4356 | |
4357 | r8168_phy_power_down(tp); | |
4358 | ||
4359 | switch (tp->mac_version) { | |
4360 | case RTL_GIGA_MAC_VER_25: | |
4361 | case RTL_GIGA_MAC_VER_26: | |
5d2e1957 HW |
4362 | case RTL_GIGA_MAC_VER_27: |
4363 | case RTL_GIGA_MAC_VER_28: | |
4804b3b3 | 4364 | case RTL_GIGA_MAC_VER_31: |
01dc7fec | 4365 | case RTL_GIGA_MAC_VER_32: |
4366 | case RTL_GIGA_MAC_VER_33: | |
6e1d0b89 CHL |
4367 | case RTL_GIGA_MAC_VER_45: |
4368 | case RTL_GIGA_MAC_VER_46: | |
065c27c1 | 4369 | RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80); |
4370 | break; | |
beb330a4 | 4371 | case RTL_GIGA_MAC_VER_40: |
4372 | case RTL_GIGA_MAC_VER_41: | |
4373 | rtl_w1w0_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000, | |
4374 | 0xfc000000, ERIAR_EXGMAC); | |
4375 | break; | |
065c27c1 | 4376 | } |
4377 | } | |
4378 | ||
4379 | static void r8168_pll_power_up(struct rtl8169_private *tp) | |
4380 | { | |
4381 | void __iomem *ioaddr = tp->mmio_addr; | |
4382 | ||
065c27c1 | 4383 | switch (tp->mac_version) { |
4384 | case RTL_GIGA_MAC_VER_25: | |
4385 | case RTL_GIGA_MAC_VER_26: | |
5d2e1957 HW |
4386 | case RTL_GIGA_MAC_VER_27: |
4387 | case RTL_GIGA_MAC_VER_28: | |
4804b3b3 | 4388 | case RTL_GIGA_MAC_VER_31: |
01dc7fec | 4389 | case RTL_GIGA_MAC_VER_32: |
4390 | case RTL_GIGA_MAC_VER_33: | |
065c27c1 | 4391 | RTL_W8(PMCH, RTL_R8(PMCH) | 0x80); |
4392 | break; | |
6e1d0b89 CHL |
4393 | case RTL_GIGA_MAC_VER_45: |
4394 | case RTL_GIGA_MAC_VER_46: | |
4395 | RTL_W8(PMCH, RTL_R8(PMCH) | 0xC0); | |
4396 | break; | |
beb330a4 | 4397 | case RTL_GIGA_MAC_VER_40: |
4398 | case RTL_GIGA_MAC_VER_41: | |
4399 | rtl_w1w0_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000, | |
4400 | 0x00000000, ERIAR_EXGMAC); | |
4401 | break; | |
065c27c1 | 4402 | } |
4403 | ||
4404 | r8168_phy_power_up(tp); | |
4405 | } | |
4406 | ||
d58d46b5 FR |
4407 | static void rtl_generic_op(struct rtl8169_private *tp, |
4408 | void (*op)(struct rtl8169_private *)) | |
065c27c1 | 4409 | { |
4410 | if (op) | |
4411 | op(tp); | |
4412 | } | |
4413 | ||
4414 | static void rtl_pll_power_down(struct rtl8169_private *tp) | |
4415 | { | |
d58d46b5 | 4416 | rtl_generic_op(tp, tp->pll_power_ops.down); |
065c27c1 | 4417 | } |
4418 | ||
4419 | static void rtl_pll_power_up(struct rtl8169_private *tp) | |
4420 | { | |
d58d46b5 | 4421 | rtl_generic_op(tp, tp->pll_power_ops.up); |
065c27c1 | 4422 | } |
4423 | ||
baf63293 | 4424 | static void rtl_init_pll_power_ops(struct rtl8169_private *tp) |
065c27c1 | 4425 | { |
4426 | struct pll_power_ops *ops = &tp->pll_power_ops; | |
4427 | ||
4428 | switch (tp->mac_version) { | |
4429 | case RTL_GIGA_MAC_VER_07: | |
4430 | case RTL_GIGA_MAC_VER_08: | |
4431 | case RTL_GIGA_MAC_VER_09: | |
4432 | case RTL_GIGA_MAC_VER_10: | |
4433 | case RTL_GIGA_MAC_VER_16: | |
5a5e4443 HW |
4434 | case RTL_GIGA_MAC_VER_29: |
4435 | case RTL_GIGA_MAC_VER_30: | |
7e18dca1 | 4436 | case RTL_GIGA_MAC_VER_37: |
5598bfe5 | 4437 | case RTL_GIGA_MAC_VER_39: |
58152cd4 | 4438 | case RTL_GIGA_MAC_VER_43: |
6e1d0b89 CHL |
4439 | case RTL_GIGA_MAC_VER_47: |
4440 | case RTL_GIGA_MAC_VER_48: | |
065c27c1 | 4441 | ops->down = r810x_pll_power_down; |
4442 | ops->up = r810x_pll_power_up; | |
4443 | break; | |
4444 | ||
4445 | case RTL_GIGA_MAC_VER_11: | |
4446 | case RTL_GIGA_MAC_VER_12: | |
4447 | case RTL_GIGA_MAC_VER_17: | |
4448 | case RTL_GIGA_MAC_VER_18: | |
4449 | case RTL_GIGA_MAC_VER_19: | |
4450 | case RTL_GIGA_MAC_VER_20: | |
4451 | case RTL_GIGA_MAC_VER_21: | |
4452 | case RTL_GIGA_MAC_VER_22: | |
4453 | case RTL_GIGA_MAC_VER_23: | |
4454 | case RTL_GIGA_MAC_VER_24: | |
4455 | case RTL_GIGA_MAC_VER_25: | |
4456 | case RTL_GIGA_MAC_VER_26: | |
4457 | case RTL_GIGA_MAC_VER_27: | |
e6de30d6 | 4458 | case RTL_GIGA_MAC_VER_28: |
4804b3b3 | 4459 | case RTL_GIGA_MAC_VER_31: |
01dc7fec | 4460 | case RTL_GIGA_MAC_VER_32: |
4461 | case RTL_GIGA_MAC_VER_33: | |
70090424 | 4462 | case RTL_GIGA_MAC_VER_34: |
c2218925 HW |
4463 | case RTL_GIGA_MAC_VER_35: |
4464 | case RTL_GIGA_MAC_VER_36: | |
b3d7b2f2 | 4465 | case RTL_GIGA_MAC_VER_38: |
c558386b HW |
4466 | case RTL_GIGA_MAC_VER_40: |
4467 | case RTL_GIGA_MAC_VER_41: | |
57538c4a | 4468 | case RTL_GIGA_MAC_VER_42: |
45dd95c4 | 4469 | case RTL_GIGA_MAC_VER_44: |
6e1d0b89 CHL |
4470 | case RTL_GIGA_MAC_VER_45: |
4471 | case RTL_GIGA_MAC_VER_46: | |
065c27c1 | 4472 | ops->down = r8168_pll_power_down; |
4473 | ops->up = r8168_pll_power_up; | |
4474 | break; | |
4475 | ||
4476 | default: | |
4477 | ops->down = NULL; | |
4478 | ops->up = NULL; | |
4479 | break; | |
4480 | } | |
4481 | } | |
4482 | ||
e542a226 HW |
4483 | static void rtl_init_rxcfg(struct rtl8169_private *tp) |
4484 | { | |
4485 | void __iomem *ioaddr = tp->mmio_addr; | |
4486 | ||
4487 | switch (tp->mac_version) { | |
4488 | case RTL_GIGA_MAC_VER_01: | |
4489 | case RTL_GIGA_MAC_VER_02: | |
4490 | case RTL_GIGA_MAC_VER_03: | |
4491 | case RTL_GIGA_MAC_VER_04: | |
4492 | case RTL_GIGA_MAC_VER_05: | |
4493 | case RTL_GIGA_MAC_VER_06: | |
4494 | case RTL_GIGA_MAC_VER_10: | |
4495 | case RTL_GIGA_MAC_VER_11: | |
4496 | case RTL_GIGA_MAC_VER_12: | |
4497 | case RTL_GIGA_MAC_VER_13: | |
4498 | case RTL_GIGA_MAC_VER_14: | |
4499 | case RTL_GIGA_MAC_VER_15: | |
4500 | case RTL_GIGA_MAC_VER_16: | |
4501 | case RTL_GIGA_MAC_VER_17: | |
4502 | RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST); | |
4503 | break; | |
4504 | case RTL_GIGA_MAC_VER_18: | |
4505 | case RTL_GIGA_MAC_VER_19: | |
4506 | case RTL_GIGA_MAC_VER_20: | |
4507 | case RTL_GIGA_MAC_VER_21: | |
4508 | case RTL_GIGA_MAC_VER_22: | |
4509 | case RTL_GIGA_MAC_VER_23: | |
4510 | case RTL_GIGA_MAC_VER_24: | |
eb2dc35d | 4511 | case RTL_GIGA_MAC_VER_34: |
3ced8c95 | 4512 | case RTL_GIGA_MAC_VER_35: |
e542a226 HW |
4513 | RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST); |
4514 | break; | |
beb330a4 | 4515 | case RTL_GIGA_MAC_VER_40: |
7a9810e7 MD |
4516 | RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF); |
4517 | break; | |
beb330a4 | 4518 | case RTL_GIGA_MAC_VER_41: |
57538c4a | 4519 | case RTL_GIGA_MAC_VER_42: |
58152cd4 | 4520 | case RTL_GIGA_MAC_VER_43: |
45dd95c4 | 4521 | case RTL_GIGA_MAC_VER_44: |
6e1d0b89 CHL |
4522 | case RTL_GIGA_MAC_VER_45: |
4523 | case RTL_GIGA_MAC_VER_46: | |
4524 | case RTL_GIGA_MAC_VER_47: | |
4525 | case RTL_GIGA_MAC_VER_48: | |
beb330a4 | 4526 | RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST | RX_EARLY_OFF); |
4527 | break; | |
e542a226 HW |
4528 | default: |
4529 | RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST); | |
4530 | break; | |
4531 | } | |
4532 | } | |
4533 | ||
92fc43b4 HW |
4534 | static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) |
4535 | { | |
9fba0812 | 4536 | tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0; |
92fc43b4 HW |
4537 | } |
4538 | ||
d58d46b5 FR |
4539 | static void rtl_hw_jumbo_enable(struct rtl8169_private *tp) |
4540 | { | |
9c5028e9 | 4541 | void __iomem *ioaddr = tp->mmio_addr; |
4542 | ||
4543 | RTL_W8(Cfg9346, Cfg9346_Unlock); | |
d58d46b5 | 4544 | rtl_generic_op(tp, tp->jumbo_ops.enable); |
9c5028e9 | 4545 | RTL_W8(Cfg9346, Cfg9346_Lock); |
d58d46b5 FR |
4546 | } |
4547 | ||
4548 | static void rtl_hw_jumbo_disable(struct rtl8169_private *tp) | |
4549 | { | |
9c5028e9 | 4550 | void __iomem *ioaddr = tp->mmio_addr; |
4551 | ||
4552 | RTL_W8(Cfg9346, Cfg9346_Unlock); | |
d58d46b5 | 4553 | rtl_generic_op(tp, tp->jumbo_ops.disable); |
9c5028e9 | 4554 | RTL_W8(Cfg9346, Cfg9346_Lock); |
d58d46b5 FR |
4555 | } |
4556 | ||
4557 | static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp) | |
4558 | { | |
4559 | void __iomem *ioaddr = tp->mmio_addr; | |
4560 | ||
4561 | RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0); | |
4562 | RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1); | |
4563 | rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT); | |
4564 | } | |
4565 | ||
4566 | static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp) | |
4567 | { | |
4568 | void __iomem *ioaddr = tp->mmio_addr; | |
4569 | ||
4570 | RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0); | |
4571 | RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1); | |
4572 | rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
4573 | } | |
4574 | ||
4575 | static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp) | |
4576 | { | |
4577 | void __iomem *ioaddr = tp->mmio_addr; | |
4578 | ||
4579 | RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0); | |
4580 | } | |
4581 | ||
4582 | static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp) | |
4583 | { | |
4584 | void __iomem *ioaddr = tp->mmio_addr; | |
4585 | ||
4586 | RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0); | |
4587 | } | |
4588 | ||
4589 | static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp) | |
4590 | { | |
4591 | void __iomem *ioaddr = tp->mmio_addr; | |
d58d46b5 FR |
4592 | |
4593 | RTL_W8(MaxTxPacketSize, 0x3f); | |
4594 | RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0); | |
4595 | RTL_W8(Config4, RTL_R8(Config4) | 0x01); | |
4512ff9f | 4596 | rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT); |
d58d46b5 FR |
4597 | } |
4598 | ||
4599 | static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp) | |
4600 | { | |
4601 | void __iomem *ioaddr = tp->mmio_addr; | |
d58d46b5 FR |
4602 | |
4603 | RTL_W8(MaxTxPacketSize, 0x0c); | |
4604 | RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0); | |
4605 | RTL_W8(Config4, RTL_R8(Config4) & ~0x01); | |
4512ff9f | 4606 | rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT); |
d58d46b5 FR |
4607 | } |
4608 | ||
4609 | static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp) | |
4610 | { | |
4611 | rtl_tx_performance_tweak(tp->pci_dev, | |
4612 | (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN); | |
4613 | } | |
4614 | ||
4615 | static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp) | |
4616 | { | |
4617 | rtl_tx_performance_tweak(tp->pci_dev, | |
4618 | (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN); | |
4619 | } | |
4620 | ||
4621 | static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp) | |
4622 | { | |
4623 | void __iomem *ioaddr = tp->mmio_addr; | |
4624 | ||
4625 | r8168b_0_hw_jumbo_enable(tp); | |
4626 | ||
4627 | RTL_W8(Config4, RTL_R8(Config4) | (1 << 0)); | |
4628 | } | |
4629 | ||
4630 | static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp) | |
4631 | { | |
4632 | void __iomem *ioaddr = tp->mmio_addr; | |
4633 | ||
4634 | r8168b_0_hw_jumbo_disable(tp); | |
4635 | ||
4636 | RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0)); | |
4637 | } | |
4638 | ||
baf63293 | 4639 | static void rtl_init_jumbo_ops(struct rtl8169_private *tp) |
d58d46b5 FR |
4640 | { |
4641 | struct jumbo_ops *ops = &tp->jumbo_ops; | |
4642 | ||
4643 | switch (tp->mac_version) { | |
4644 | case RTL_GIGA_MAC_VER_11: | |
4645 | ops->disable = r8168b_0_hw_jumbo_disable; | |
4646 | ops->enable = r8168b_0_hw_jumbo_enable; | |
4647 | break; | |
4648 | case RTL_GIGA_MAC_VER_12: | |
4649 | case RTL_GIGA_MAC_VER_17: | |
4650 | ops->disable = r8168b_1_hw_jumbo_disable; | |
4651 | ops->enable = r8168b_1_hw_jumbo_enable; | |
4652 | break; | |
4653 | case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */ | |
4654 | case RTL_GIGA_MAC_VER_19: | |
4655 | case RTL_GIGA_MAC_VER_20: | |
4656 | case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */ | |
4657 | case RTL_GIGA_MAC_VER_22: | |
4658 | case RTL_GIGA_MAC_VER_23: | |
4659 | case RTL_GIGA_MAC_VER_24: | |
4660 | case RTL_GIGA_MAC_VER_25: | |
4661 | case RTL_GIGA_MAC_VER_26: | |
4662 | ops->disable = r8168c_hw_jumbo_disable; | |
4663 | ops->enable = r8168c_hw_jumbo_enable; | |
4664 | break; | |
4665 | case RTL_GIGA_MAC_VER_27: | |
4666 | case RTL_GIGA_MAC_VER_28: | |
4667 | ops->disable = r8168dp_hw_jumbo_disable; | |
4668 | ops->enable = r8168dp_hw_jumbo_enable; | |
4669 | break; | |
4670 | case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */ | |
4671 | case RTL_GIGA_MAC_VER_32: | |
4672 | case RTL_GIGA_MAC_VER_33: | |
4673 | case RTL_GIGA_MAC_VER_34: | |
4674 | ops->disable = r8168e_hw_jumbo_disable; | |
4675 | ops->enable = r8168e_hw_jumbo_enable; | |
4676 | break; | |
4677 | ||
4678 | /* | |
4679 | * No action needed for jumbo frames with 8169. | |
4680 | * No jumbo for 810x at all. | |
4681 | */ | |
c558386b HW |
4682 | case RTL_GIGA_MAC_VER_40: |
4683 | case RTL_GIGA_MAC_VER_41: | |
57538c4a | 4684 | case RTL_GIGA_MAC_VER_42: |
58152cd4 | 4685 | case RTL_GIGA_MAC_VER_43: |
45dd95c4 | 4686 | case RTL_GIGA_MAC_VER_44: |
6e1d0b89 CHL |
4687 | case RTL_GIGA_MAC_VER_45: |
4688 | case RTL_GIGA_MAC_VER_46: | |
4689 | case RTL_GIGA_MAC_VER_47: | |
4690 | case RTL_GIGA_MAC_VER_48: | |
d58d46b5 FR |
4691 | default: |
4692 | ops->disable = NULL; | |
4693 | ops->enable = NULL; | |
4694 | break; | |
4695 | } | |
4696 | } | |
4697 | ||
ffc46952 FR |
4698 | DECLARE_RTL_COND(rtl_chipcmd_cond) |
4699 | { | |
4700 | void __iomem *ioaddr = tp->mmio_addr; | |
4701 | ||
4702 | return RTL_R8(ChipCmd) & CmdReset; | |
4703 | } | |
4704 | ||
6f43adc8 FR |
4705 | static void rtl_hw_reset(struct rtl8169_private *tp) |
4706 | { | |
4707 | void __iomem *ioaddr = tp->mmio_addr; | |
6f43adc8 | 4708 | |
6f43adc8 FR |
4709 | RTL_W8(ChipCmd, CmdReset); |
4710 | ||
ffc46952 | 4711 | rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100); |
6f43adc8 FR |
4712 | } |
4713 | ||
b6ffd97f | 4714 | static void rtl_request_uncached_firmware(struct rtl8169_private *tp) |
953a12cc | 4715 | { |
b6ffd97f FR |
4716 | struct rtl_fw *rtl_fw; |
4717 | const char *name; | |
4718 | int rc = -ENOMEM; | |
953a12cc | 4719 | |
b6ffd97f FR |
4720 | name = rtl_lookup_firmware_name(tp); |
4721 | if (!name) | |
4722 | goto out_no_firmware; | |
953a12cc | 4723 | |
b6ffd97f FR |
4724 | rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL); |
4725 | if (!rtl_fw) | |
4726 | goto err_warn; | |
31bd204f | 4727 | |
b6ffd97f FR |
4728 | rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev); |
4729 | if (rc < 0) | |
4730 | goto err_free; | |
4731 | ||
fd112f2e FR |
4732 | rc = rtl_check_firmware(tp, rtl_fw); |
4733 | if (rc < 0) | |
4734 | goto err_release_firmware; | |
4735 | ||
b6ffd97f FR |
4736 | tp->rtl_fw = rtl_fw; |
4737 | out: | |
4738 | return; | |
4739 | ||
fd112f2e FR |
4740 | err_release_firmware: |
4741 | release_firmware(rtl_fw->fw); | |
b6ffd97f FR |
4742 | err_free: |
4743 | kfree(rtl_fw); | |
4744 | err_warn: | |
4745 | netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n", | |
4746 | name, rc); | |
4747 | out_no_firmware: | |
4748 | tp->rtl_fw = NULL; | |
4749 | goto out; | |
4750 | } | |
4751 | ||
4752 | static void rtl_request_firmware(struct rtl8169_private *tp) | |
4753 | { | |
4754 | if (IS_ERR(tp->rtl_fw)) | |
4755 | rtl_request_uncached_firmware(tp); | |
953a12cc FR |
4756 | } |
4757 | ||
92fc43b4 HW |
4758 | static void rtl_rx_close(struct rtl8169_private *tp) |
4759 | { | |
4760 | void __iomem *ioaddr = tp->mmio_addr; | |
92fc43b4 | 4761 | |
1687b566 | 4762 | RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK); |
92fc43b4 HW |
4763 | } |
4764 | ||
ffc46952 FR |
4765 | DECLARE_RTL_COND(rtl_npq_cond) |
4766 | { | |
4767 | void __iomem *ioaddr = tp->mmio_addr; | |
4768 | ||
4769 | return RTL_R8(TxPoll) & NPQ; | |
4770 | } | |
4771 | ||
4772 | DECLARE_RTL_COND(rtl_txcfg_empty_cond) | |
4773 | { | |
4774 | void __iomem *ioaddr = tp->mmio_addr; | |
4775 | ||
4776 | return RTL_R32(TxConfig) & TXCFG_EMPTY; | |
4777 | } | |
4778 | ||
e6de30d6 | 4779 | static void rtl8169_hw_reset(struct rtl8169_private *tp) |
1da177e4 | 4780 | { |
e6de30d6 | 4781 | void __iomem *ioaddr = tp->mmio_addr; |
4782 | ||
1da177e4 | 4783 | /* Disable interrupts */ |
811fd301 | 4784 | rtl8169_irq_mask_and_ack(tp); |
1da177e4 | 4785 | |
92fc43b4 HW |
4786 | rtl_rx_close(tp); |
4787 | ||
5d2e1957 | 4788 | if (tp->mac_version == RTL_GIGA_MAC_VER_27 || |
4804b3b3 | 4789 | tp->mac_version == RTL_GIGA_MAC_VER_28 || |
4790 | tp->mac_version == RTL_GIGA_MAC_VER_31) { | |
ffc46952 | 4791 | rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42); |
c2218925 | 4792 | } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 || |
6e1d0b89 CHL |
4793 | tp->mac_version == RTL_GIGA_MAC_VER_35 || |
4794 | tp->mac_version == RTL_GIGA_MAC_VER_36 || | |
4795 | tp->mac_version == RTL_GIGA_MAC_VER_37 || | |
4796 | tp->mac_version == RTL_GIGA_MAC_VER_38 || | |
4797 | tp->mac_version == RTL_GIGA_MAC_VER_40 || | |
4798 | tp->mac_version == RTL_GIGA_MAC_VER_41 || | |
4799 | tp->mac_version == RTL_GIGA_MAC_VER_42 || | |
4800 | tp->mac_version == RTL_GIGA_MAC_VER_43 || | |
4801 | tp->mac_version == RTL_GIGA_MAC_VER_44 || | |
4802 | tp->mac_version == RTL_GIGA_MAC_VER_45 || | |
4803 | tp->mac_version == RTL_GIGA_MAC_VER_46 || | |
4804 | tp->mac_version == RTL_GIGA_MAC_VER_47 || | |
4805 | tp->mac_version == RTL_GIGA_MAC_VER_48) { | |
c2b0c1e7 | 4806 | RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq); |
ffc46952 | 4807 | rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666); |
92fc43b4 HW |
4808 | } else { |
4809 | RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq); | |
4810 | udelay(100); | |
e6de30d6 | 4811 | } |
4812 | ||
92fc43b4 | 4813 | rtl_hw_reset(tp); |
1da177e4 LT |
4814 | } |
4815 | ||
7f796d83 | 4816 | static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp) |
9cb427b6 FR |
4817 | { |
4818 | void __iomem *ioaddr = tp->mmio_addr; | |
9cb427b6 FR |
4819 | |
4820 | /* Set DMA burst size and Interframe Gap Time */ | |
4821 | RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | | |
4822 | (InterFrameGap << TxInterFrameGapShift)); | |
4823 | } | |
4824 | ||
07ce4064 | 4825 | static void rtl_hw_start(struct net_device *dev) |
1da177e4 LT |
4826 | { |
4827 | struct rtl8169_private *tp = netdev_priv(dev); | |
1da177e4 | 4828 | |
07ce4064 FR |
4829 | tp->hw_start(dev); |
4830 | ||
da78dbff | 4831 | rtl_irq_enable_all(tp); |
07ce4064 FR |
4832 | } |
4833 | ||
7f796d83 FR |
4834 | static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp, |
4835 | void __iomem *ioaddr) | |
4836 | { | |
4837 | /* | |
4838 | * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh | |
4839 | * register to be written before TxDescAddrLow to work. | |
4840 | * Switching from MMIO to I/O access fixes the issue as well. | |
4841 | */ | |
4842 | RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); | |
284901a9 | 4843 | RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); |
7f796d83 | 4844 | RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); |
284901a9 | 4845 | RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); |
7f796d83 FR |
4846 | } |
4847 | ||
4848 | static u16 rtl_rw_cpluscmd(void __iomem *ioaddr) | |
4849 | { | |
4850 | u16 cmd; | |
4851 | ||
4852 | cmd = RTL_R16(CPlusCmd); | |
4853 | RTL_W16(CPlusCmd, cmd); | |
4854 | return cmd; | |
4855 | } | |
4856 | ||
fdd7b4c3 | 4857 | static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz) |
7f796d83 FR |
4858 | { |
4859 | /* Low hurts. Let's disable the filtering. */ | |
207d6e87 | 4860 | RTL_W16(RxMaxSize, rx_buf_sz + 1); |
7f796d83 FR |
4861 | } |
4862 | ||
6dccd16b FR |
4863 | static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version) |
4864 | { | |
3744100e | 4865 | static const struct rtl_cfg2_info { |
6dccd16b FR |
4866 | u32 mac_version; |
4867 | u32 clk; | |
4868 | u32 val; | |
4869 | } cfg2_info [] = { | |
4870 | { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd | |
4871 | { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff }, | |
4872 | { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe | |
4873 | { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff } | |
3744100e FR |
4874 | }; |
4875 | const struct rtl_cfg2_info *p = cfg2_info; | |
6dccd16b FR |
4876 | unsigned int i; |
4877 | u32 clk; | |
4878 | ||
4879 | clk = RTL_R8(Config2) & PCI_Clock_66MHz; | |
cadf1855 | 4880 | for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) { |
6dccd16b FR |
4881 | if ((p->mac_version == mac_version) && (p->clk == clk)) { |
4882 | RTL_W32(0x7c, p->val); | |
4883 | break; | |
4884 | } | |
4885 | } | |
4886 | } | |
4887 | ||
e6b763ea FR |
4888 | static void rtl_set_rx_mode(struct net_device *dev) |
4889 | { | |
4890 | struct rtl8169_private *tp = netdev_priv(dev); | |
4891 | void __iomem *ioaddr = tp->mmio_addr; | |
4892 | u32 mc_filter[2]; /* Multicast hash filter */ | |
4893 | int rx_mode; | |
4894 | u32 tmp = 0; | |
4895 | ||
4896 | if (dev->flags & IFF_PROMISC) { | |
4897 | /* Unconditionally log net taps. */ | |
4898 | netif_notice(tp, link, dev, "Promiscuous mode enabled\n"); | |
4899 | rx_mode = | |
4900 | AcceptBroadcast | AcceptMulticast | AcceptMyPhys | | |
4901 | AcceptAllPhys; | |
4902 | mc_filter[1] = mc_filter[0] = 0xffffffff; | |
4903 | } else if ((netdev_mc_count(dev) > multicast_filter_limit) || | |
4904 | (dev->flags & IFF_ALLMULTI)) { | |
4905 | /* Too many to filter perfectly -- accept all multicasts. */ | |
4906 | rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; | |
4907 | mc_filter[1] = mc_filter[0] = 0xffffffff; | |
4908 | } else { | |
4909 | struct netdev_hw_addr *ha; | |
4910 | ||
4911 | rx_mode = AcceptBroadcast | AcceptMyPhys; | |
4912 | mc_filter[1] = mc_filter[0] = 0; | |
4913 | netdev_for_each_mc_addr(ha, dev) { | |
4914 | int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; | |
4915 | mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); | |
4916 | rx_mode |= AcceptMulticast; | |
4917 | } | |
4918 | } | |
4919 | ||
4920 | if (dev->features & NETIF_F_RXALL) | |
4921 | rx_mode |= (AcceptErr | AcceptRunt); | |
4922 | ||
4923 | tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode; | |
4924 | ||
4925 | if (tp->mac_version > RTL_GIGA_MAC_VER_06) { | |
4926 | u32 data = mc_filter[0]; | |
4927 | ||
4928 | mc_filter[0] = swab32(mc_filter[1]); | |
4929 | mc_filter[1] = swab32(data); | |
4930 | } | |
4931 | ||
0481776b NW |
4932 | if (tp->mac_version == RTL_GIGA_MAC_VER_35) |
4933 | mc_filter[1] = mc_filter[0] = 0xffffffff; | |
4934 | ||
e6b763ea FR |
4935 | RTL_W32(MAR0 + 4, mc_filter[1]); |
4936 | RTL_W32(MAR0 + 0, mc_filter[0]); | |
4937 | ||
4938 | RTL_W32(RxConfig, tmp); | |
4939 | } | |
4940 | ||
07ce4064 FR |
4941 | static void rtl_hw_start_8169(struct net_device *dev) |
4942 | { | |
4943 | struct rtl8169_private *tp = netdev_priv(dev); | |
4944 | void __iomem *ioaddr = tp->mmio_addr; | |
4945 | struct pci_dev *pdev = tp->pci_dev; | |
07ce4064 | 4946 | |
9cb427b6 FR |
4947 | if (tp->mac_version == RTL_GIGA_MAC_VER_05) { |
4948 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW); | |
4949 | pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08); | |
4950 | } | |
4951 | ||
1da177e4 | 4952 | RTL_W8(Cfg9346, Cfg9346_Unlock); |
cecb5fd7 FR |
4953 | if (tp->mac_version == RTL_GIGA_MAC_VER_01 || |
4954 | tp->mac_version == RTL_GIGA_MAC_VER_02 || | |
4955 | tp->mac_version == RTL_GIGA_MAC_VER_03 || | |
4956 | tp->mac_version == RTL_GIGA_MAC_VER_04) | |
9cb427b6 FR |
4957 | RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
4958 | ||
e542a226 HW |
4959 | rtl_init_rxcfg(tp); |
4960 | ||
f0298f81 | 4961 | RTL_W8(EarlyTxThres, NoEarlyTx); |
1da177e4 | 4962 | |
6f0333b8 | 4963 | rtl_set_rx_max_size(ioaddr, rx_buf_sz); |
1da177e4 | 4964 | |
cecb5fd7 FR |
4965 | if (tp->mac_version == RTL_GIGA_MAC_VER_01 || |
4966 | tp->mac_version == RTL_GIGA_MAC_VER_02 || | |
4967 | tp->mac_version == RTL_GIGA_MAC_VER_03 || | |
4968 | tp->mac_version == RTL_GIGA_MAC_VER_04) | |
c946b304 | 4969 | rtl_set_rx_tx_config_registers(tp); |
1da177e4 | 4970 | |
7f796d83 | 4971 | tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW; |
1da177e4 | 4972 | |
cecb5fd7 FR |
4973 | if (tp->mac_version == RTL_GIGA_MAC_VER_02 || |
4974 | tp->mac_version == RTL_GIGA_MAC_VER_03) { | |
06fa7358 | 4975 | dprintk("Set MAC Reg C+CR Offset 0xE0. " |
1da177e4 | 4976 | "Bit-3 and bit-14 MUST be 1\n"); |
bcf0bf90 | 4977 | tp->cp_cmd |= (1 << 14); |
1da177e4 LT |
4978 | } |
4979 | ||
bcf0bf90 FR |
4980 | RTL_W16(CPlusCmd, tp->cp_cmd); |
4981 | ||
6dccd16b FR |
4982 | rtl8169_set_magic_reg(ioaddr, tp->mac_version); |
4983 | ||
1da177e4 LT |
4984 | /* |
4985 | * Undocumented corner. Supposedly: | |
4986 | * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets | |
4987 | */ | |
4988 | RTL_W16(IntrMitigate, 0x0000); | |
4989 | ||
7f796d83 | 4990 | rtl_set_rx_tx_desc_registers(tp, ioaddr); |
9cb427b6 | 4991 | |
cecb5fd7 FR |
4992 | if (tp->mac_version != RTL_GIGA_MAC_VER_01 && |
4993 | tp->mac_version != RTL_GIGA_MAC_VER_02 && | |
4994 | tp->mac_version != RTL_GIGA_MAC_VER_03 && | |
4995 | tp->mac_version != RTL_GIGA_MAC_VER_04) { | |
c946b304 FR |
4996 | RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
4997 | rtl_set_rx_tx_config_registers(tp); | |
4998 | } | |
4999 | ||
1da177e4 | 5000 | RTL_W8(Cfg9346, Cfg9346_Lock); |
b518fa8e FR |
5001 | |
5002 | /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ | |
5003 | RTL_R8(IntrMask); | |
1da177e4 LT |
5004 | |
5005 | RTL_W32(RxMissed, 0); | |
5006 | ||
07ce4064 | 5007 | rtl_set_rx_mode(dev); |
1da177e4 LT |
5008 | |
5009 | /* no early-rx interrupts */ | |
5010 | RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); | |
07ce4064 | 5011 | } |
1da177e4 | 5012 | |
beb1fe18 HW |
5013 | static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value) |
5014 | { | |
5015 | if (tp->csi_ops.write) | |
52989f0e | 5016 | tp->csi_ops.write(tp, addr, value); |
beb1fe18 HW |
5017 | } |
5018 | ||
5019 | static u32 rtl_csi_read(struct rtl8169_private *tp, int addr) | |
5020 | { | |
52989f0e | 5021 | return tp->csi_ops.read ? tp->csi_ops.read(tp, addr) : ~0; |
beb1fe18 HW |
5022 | } |
5023 | ||
5024 | static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits) | |
dacf8154 FR |
5025 | { |
5026 | u32 csi; | |
5027 | ||
beb1fe18 HW |
5028 | csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff; |
5029 | rtl_csi_write(tp, 0x070c, csi | bits); | |
5030 | } | |
5031 | ||
5032 | static void rtl_csi_access_enable_1(struct rtl8169_private *tp) | |
5033 | { | |
5034 | rtl_csi_access_enable(tp, 0x17000000); | |
650e8d5d | 5035 | } |
5036 | ||
beb1fe18 | 5037 | static void rtl_csi_access_enable_2(struct rtl8169_private *tp) |
e6de30d6 | 5038 | { |
beb1fe18 | 5039 | rtl_csi_access_enable(tp, 0x27000000); |
e6de30d6 | 5040 | } |
5041 | ||
ffc46952 FR |
5042 | DECLARE_RTL_COND(rtl_csiar_cond) |
5043 | { | |
5044 | void __iomem *ioaddr = tp->mmio_addr; | |
5045 | ||
5046 | return RTL_R32(CSIAR) & CSIAR_FLAG; | |
5047 | } | |
5048 | ||
52989f0e | 5049 | static void r8169_csi_write(struct rtl8169_private *tp, int addr, int value) |
650e8d5d | 5050 | { |
52989f0e | 5051 | void __iomem *ioaddr = tp->mmio_addr; |
beb1fe18 HW |
5052 | |
5053 | RTL_W32(CSIDR, value); | |
5054 | RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | | |
5055 | CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT); | |
5056 | ||
ffc46952 | 5057 | rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100); |
beb1fe18 HW |
5058 | } |
5059 | ||
52989f0e | 5060 | static u32 r8169_csi_read(struct rtl8169_private *tp, int addr) |
beb1fe18 | 5061 | { |
52989f0e | 5062 | void __iomem *ioaddr = tp->mmio_addr; |
beb1fe18 HW |
5063 | |
5064 | RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | | |
5065 | CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT); | |
5066 | ||
ffc46952 FR |
5067 | return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ? |
5068 | RTL_R32(CSIDR) : ~0; | |
beb1fe18 HW |
5069 | } |
5070 | ||
52989f0e | 5071 | static void r8402_csi_write(struct rtl8169_private *tp, int addr, int value) |
7e18dca1 | 5072 | { |
52989f0e | 5073 | void __iomem *ioaddr = tp->mmio_addr; |
7e18dca1 HW |
5074 | |
5075 | RTL_W32(CSIDR, value); | |
5076 | RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | | |
5077 | CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT | | |
5078 | CSIAR_FUNC_NIC); | |
5079 | ||
ffc46952 | 5080 | rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100); |
7e18dca1 HW |
5081 | } |
5082 | ||
52989f0e | 5083 | static u32 r8402_csi_read(struct rtl8169_private *tp, int addr) |
7e18dca1 | 5084 | { |
52989f0e | 5085 | void __iomem *ioaddr = tp->mmio_addr; |
7e18dca1 HW |
5086 | |
5087 | RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC | | |
5088 | CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT); | |
5089 | ||
ffc46952 FR |
5090 | return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ? |
5091 | RTL_R32(CSIDR) : ~0; | |
7e18dca1 HW |
5092 | } |
5093 | ||
45dd95c4 | 5094 | static void r8411_csi_write(struct rtl8169_private *tp, int addr, int value) |
5095 | { | |
5096 | void __iomem *ioaddr = tp->mmio_addr; | |
5097 | ||
5098 | RTL_W32(CSIDR, value); | |
5099 | RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | | |
5100 | CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT | | |
5101 | CSIAR_FUNC_NIC2); | |
5102 | ||
5103 | rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100); | |
5104 | } | |
5105 | ||
5106 | static u32 r8411_csi_read(struct rtl8169_private *tp, int addr) | |
5107 | { | |
5108 | void __iomem *ioaddr = tp->mmio_addr; | |
5109 | ||
5110 | RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC2 | | |
5111 | CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT); | |
5112 | ||
5113 | return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ? | |
5114 | RTL_R32(CSIDR) : ~0; | |
5115 | } | |
5116 | ||
baf63293 | 5117 | static void rtl_init_csi_ops(struct rtl8169_private *tp) |
beb1fe18 HW |
5118 | { |
5119 | struct csi_ops *ops = &tp->csi_ops; | |
5120 | ||
5121 | switch (tp->mac_version) { | |
5122 | case RTL_GIGA_MAC_VER_01: | |
5123 | case RTL_GIGA_MAC_VER_02: | |
5124 | case RTL_GIGA_MAC_VER_03: | |
5125 | case RTL_GIGA_MAC_VER_04: | |
5126 | case RTL_GIGA_MAC_VER_05: | |
5127 | case RTL_GIGA_MAC_VER_06: | |
5128 | case RTL_GIGA_MAC_VER_10: | |
5129 | case RTL_GIGA_MAC_VER_11: | |
5130 | case RTL_GIGA_MAC_VER_12: | |
5131 | case RTL_GIGA_MAC_VER_13: | |
5132 | case RTL_GIGA_MAC_VER_14: | |
5133 | case RTL_GIGA_MAC_VER_15: | |
5134 | case RTL_GIGA_MAC_VER_16: | |
5135 | case RTL_GIGA_MAC_VER_17: | |
5136 | ops->write = NULL; | |
5137 | ops->read = NULL; | |
5138 | break; | |
5139 | ||
7e18dca1 | 5140 | case RTL_GIGA_MAC_VER_37: |
b3d7b2f2 | 5141 | case RTL_GIGA_MAC_VER_38: |
7e18dca1 HW |
5142 | ops->write = r8402_csi_write; |
5143 | ops->read = r8402_csi_read; | |
5144 | break; | |
5145 | ||
45dd95c4 | 5146 | case RTL_GIGA_MAC_VER_44: |
5147 | ops->write = r8411_csi_write; | |
5148 | ops->read = r8411_csi_read; | |
5149 | break; | |
5150 | ||
beb1fe18 HW |
5151 | default: |
5152 | ops->write = r8169_csi_write; | |
5153 | ops->read = r8169_csi_read; | |
5154 | break; | |
5155 | } | |
dacf8154 FR |
5156 | } |
5157 | ||
5158 | struct ephy_info { | |
5159 | unsigned int offset; | |
5160 | u16 mask; | |
5161 | u16 bits; | |
5162 | }; | |
5163 | ||
fdf6fc06 FR |
5164 | static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e, |
5165 | int len) | |
dacf8154 FR |
5166 | { |
5167 | u16 w; | |
5168 | ||
5169 | while (len-- > 0) { | |
fdf6fc06 FR |
5170 | w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits; |
5171 | rtl_ephy_write(tp, e->offset, w); | |
dacf8154 FR |
5172 | e++; |
5173 | } | |
5174 | } | |
5175 | ||
b726e493 FR |
5176 | static void rtl_disable_clock_request(struct pci_dev *pdev) |
5177 | { | |
7d7903b2 JL |
5178 | pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, |
5179 | PCI_EXP_LNKCTL_CLKREQ_EN); | |
b726e493 FR |
5180 | } |
5181 | ||
e6de30d6 | 5182 | static void rtl_enable_clock_request(struct pci_dev *pdev) |
5183 | { | |
7d7903b2 JL |
5184 | pcie_capability_set_word(pdev, PCI_EXP_LNKCTL, |
5185 | PCI_EXP_LNKCTL_CLKREQ_EN); | |
e6de30d6 | 5186 | } |
5187 | ||
b51ecea8 | 5188 | static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable) |
5189 | { | |
5190 | void __iomem *ioaddr = tp->mmio_addr; | |
5191 | u8 data; | |
5192 | ||
5193 | data = RTL_R8(Config3); | |
5194 | ||
5195 | if (enable) | |
5196 | data |= Rdy_to_L23; | |
5197 | else | |
5198 | data &= ~Rdy_to_L23; | |
5199 | ||
5200 | RTL_W8(Config3, data); | |
5201 | } | |
5202 | ||
b726e493 FR |
5203 | #define R8168_CPCMD_QUIRK_MASK (\ |
5204 | EnableBist | \ | |
5205 | Mac_dbgo_oe | \ | |
5206 | Force_half_dup | \ | |
5207 | Force_rxflow_en | \ | |
5208 | Force_txflow_en | \ | |
5209 | Cxpl_dbg_sel | \ | |
5210 | ASF | \ | |
5211 | PktCntrDisable | \ | |
5212 | Mac_dbgo_sel) | |
5213 | ||
beb1fe18 | 5214 | static void rtl_hw_start_8168bb(struct rtl8169_private *tp) |
219a1e9d | 5215 | { |
beb1fe18 HW |
5216 | void __iomem *ioaddr = tp->mmio_addr; |
5217 | struct pci_dev *pdev = tp->pci_dev; | |
5218 | ||
b726e493 FR |
5219 | RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); |
5220 | ||
5221 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); | |
5222 | ||
faf1e785 | 5223 | if (tp->dev->mtu <= ETH_DATA_LEN) { |
5224 | rtl_tx_performance_tweak(pdev, (0x5 << MAX_READ_REQUEST_SHIFT) | | |
5225 | PCI_EXP_DEVCTL_NOSNOOP_EN); | |
5226 | } | |
219a1e9d FR |
5227 | } |
5228 | ||
beb1fe18 | 5229 | static void rtl_hw_start_8168bef(struct rtl8169_private *tp) |
219a1e9d | 5230 | { |
beb1fe18 HW |
5231 | void __iomem *ioaddr = tp->mmio_addr; |
5232 | ||
5233 | rtl_hw_start_8168bb(tp); | |
b726e493 | 5234 | |
f0298f81 | 5235 | RTL_W8(MaxTxPacketSize, TxPacketMax); |
b726e493 FR |
5236 | |
5237 | RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0)); | |
219a1e9d FR |
5238 | } |
5239 | ||
beb1fe18 | 5240 | static void __rtl_hw_start_8168cp(struct rtl8169_private *tp) |
219a1e9d | 5241 | { |
beb1fe18 HW |
5242 | void __iomem *ioaddr = tp->mmio_addr; |
5243 | struct pci_dev *pdev = tp->pci_dev; | |
5244 | ||
b726e493 FR |
5245 | RTL_W8(Config1, RTL_R8(Config1) | Speed_down); |
5246 | ||
5247 | RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); | |
5248 | ||
faf1e785 | 5249 | if (tp->dev->mtu <= ETH_DATA_LEN) |
5250 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
b726e493 FR |
5251 | |
5252 | rtl_disable_clock_request(pdev); | |
5253 | ||
5254 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); | |
219a1e9d FR |
5255 | } |
5256 | ||
beb1fe18 | 5257 | static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp) |
219a1e9d | 5258 | { |
350f7596 | 5259 | static const struct ephy_info e_info_8168cp[] = { |
b726e493 FR |
5260 | { 0x01, 0, 0x0001 }, |
5261 | { 0x02, 0x0800, 0x1000 }, | |
5262 | { 0x03, 0, 0x0042 }, | |
5263 | { 0x06, 0x0080, 0x0000 }, | |
5264 | { 0x07, 0, 0x2000 } | |
5265 | }; | |
5266 | ||
beb1fe18 | 5267 | rtl_csi_access_enable_2(tp); |
b726e493 | 5268 | |
fdf6fc06 | 5269 | rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp)); |
b726e493 | 5270 | |
beb1fe18 | 5271 | __rtl_hw_start_8168cp(tp); |
219a1e9d FR |
5272 | } |
5273 | ||
beb1fe18 | 5274 | static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp) |
ef3386f0 | 5275 | { |
beb1fe18 HW |
5276 | void __iomem *ioaddr = tp->mmio_addr; |
5277 | struct pci_dev *pdev = tp->pci_dev; | |
5278 | ||
5279 | rtl_csi_access_enable_2(tp); | |
ef3386f0 FR |
5280 | |
5281 | RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); | |
5282 | ||
faf1e785 | 5283 | if (tp->dev->mtu <= ETH_DATA_LEN) |
5284 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
ef3386f0 FR |
5285 | |
5286 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); | |
5287 | } | |
5288 | ||
beb1fe18 | 5289 | static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp) |
7f3e3d3a | 5290 | { |
beb1fe18 HW |
5291 | void __iomem *ioaddr = tp->mmio_addr; |
5292 | struct pci_dev *pdev = tp->pci_dev; | |
5293 | ||
5294 | rtl_csi_access_enable_2(tp); | |
7f3e3d3a FR |
5295 | |
5296 | RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); | |
5297 | ||
5298 | /* Magic. */ | |
5299 | RTL_W8(DBG_REG, 0x20); | |
5300 | ||
f0298f81 | 5301 | RTL_W8(MaxTxPacketSize, TxPacketMax); |
7f3e3d3a | 5302 | |
faf1e785 | 5303 | if (tp->dev->mtu <= ETH_DATA_LEN) |
5304 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
7f3e3d3a FR |
5305 | |
5306 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); | |
5307 | } | |
5308 | ||
beb1fe18 | 5309 | static void rtl_hw_start_8168c_1(struct rtl8169_private *tp) |
219a1e9d | 5310 | { |
beb1fe18 | 5311 | void __iomem *ioaddr = tp->mmio_addr; |
350f7596 | 5312 | static const struct ephy_info e_info_8168c_1[] = { |
b726e493 FR |
5313 | { 0x02, 0x0800, 0x1000 }, |
5314 | { 0x03, 0, 0x0002 }, | |
5315 | { 0x06, 0x0080, 0x0000 } | |
5316 | }; | |
5317 | ||
beb1fe18 | 5318 | rtl_csi_access_enable_2(tp); |
b726e493 FR |
5319 | |
5320 | RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); | |
5321 | ||
fdf6fc06 | 5322 | rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1)); |
b726e493 | 5323 | |
beb1fe18 | 5324 | __rtl_hw_start_8168cp(tp); |
219a1e9d FR |
5325 | } |
5326 | ||
beb1fe18 | 5327 | static void rtl_hw_start_8168c_2(struct rtl8169_private *tp) |
219a1e9d | 5328 | { |
350f7596 | 5329 | static const struct ephy_info e_info_8168c_2[] = { |
b726e493 FR |
5330 | { 0x01, 0, 0x0001 }, |
5331 | { 0x03, 0x0400, 0x0220 } | |
5332 | }; | |
5333 | ||
beb1fe18 | 5334 | rtl_csi_access_enable_2(tp); |
b726e493 | 5335 | |
fdf6fc06 | 5336 | rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2)); |
b726e493 | 5337 | |
beb1fe18 | 5338 | __rtl_hw_start_8168cp(tp); |
219a1e9d FR |
5339 | } |
5340 | ||
beb1fe18 | 5341 | static void rtl_hw_start_8168c_3(struct rtl8169_private *tp) |
197ff761 | 5342 | { |
beb1fe18 | 5343 | rtl_hw_start_8168c_2(tp); |
197ff761 FR |
5344 | } |
5345 | ||
beb1fe18 | 5346 | static void rtl_hw_start_8168c_4(struct rtl8169_private *tp) |
6fb07058 | 5347 | { |
beb1fe18 | 5348 | rtl_csi_access_enable_2(tp); |
6fb07058 | 5349 | |
beb1fe18 | 5350 | __rtl_hw_start_8168cp(tp); |
6fb07058 FR |
5351 | } |
5352 | ||
beb1fe18 | 5353 | static void rtl_hw_start_8168d(struct rtl8169_private *tp) |
5b538df9 | 5354 | { |
beb1fe18 HW |
5355 | void __iomem *ioaddr = tp->mmio_addr; |
5356 | struct pci_dev *pdev = tp->pci_dev; | |
5357 | ||
5358 | rtl_csi_access_enable_2(tp); | |
5b538df9 FR |
5359 | |
5360 | rtl_disable_clock_request(pdev); | |
5361 | ||
f0298f81 | 5362 | RTL_W8(MaxTxPacketSize, TxPacketMax); |
5b538df9 | 5363 | |
faf1e785 | 5364 | if (tp->dev->mtu <= ETH_DATA_LEN) |
5365 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
5b538df9 FR |
5366 | |
5367 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); | |
5368 | } | |
5369 | ||
beb1fe18 | 5370 | static void rtl_hw_start_8168dp(struct rtl8169_private *tp) |
4804b3b3 | 5371 | { |
beb1fe18 HW |
5372 | void __iomem *ioaddr = tp->mmio_addr; |
5373 | struct pci_dev *pdev = tp->pci_dev; | |
5374 | ||
5375 | rtl_csi_access_enable_1(tp); | |
4804b3b3 | 5376 | |
faf1e785 | 5377 | if (tp->dev->mtu <= ETH_DATA_LEN) |
5378 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
4804b3b3 | 5379 | |
5380 | RTL_W8(MaxTxPacketSize, TxPacketMax); | |
5381 | ||
5382 | rtl_disable_clock_request(pdev); | |
5383 | } | |
5384 | ||
beb1fe18 | 5385 | static void rtl_hw_start_8168d_4(struct rtl8169_private *tp) |
e6de30d6 | 5386 | { |
beb1fe18 HW |
5387 | void __iomem *ioaddr = tp->mmio_addr; |
5388 | struct pci_dev *pdev = tp->pci_dev; | |
e6de30d6 | 5389 | static const struct ephy_info e_info_8168d_4[] = { |
5390 | { 0x0b, ~0, 0x48 }, | |
5391 | { 0x19, 0x20, 0x50 }, | |
5392 | { 0x0c, ~0, 0x20 } | |
5393 | }; | |
5394 | int i; | |
5395 | ||
beb1fe18 | 5396 | rtl_csi_access_enable_1(tp); |
e6de30d6 | 5397 | |
5398 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
5399 | ||
5400 | RTL_W8(MaxTxPacketSize, TxPacketMax); | |
5401 | ||
5402 | for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) { | |
5403 | const struct ephy_info *e = e_info_8168d_4 + i; | |
5404 | u16 w; | |
5405 | ||
fdf6fc06 FR |
5406 | w = rtl_ephy_read(tp, e->offset); |
5407 | rtl_ephy_write(tp, 0x03, (w & e->mask) | e->bits); | |
e6de30d6 | 5408 | } |
5409 | ||
5410 | rtl_enable_clock_request(pdev); | |
5411 | } | |
5412 | ||
beb1fe18 | 5413 | static void rtl_hw_start_8168e_1(struct rtl8169_private *tp) |
01dc7fec | 5414 | { |
beb1fe18 HW |
5415 | void __iomem *ioaddr = tp->mmio_addr; |
5416 | struct pci_dev *pdev = tp->pci_dev; | |
70090424 | 5417 | static const struct ephy_info e_info_8168e_1[] = { |
01dc7fec | 5418 | { 0x00, 0x0200, 0x0100 }, |
5419 | { 0x00, 0x0000, 0x0004 }, | |
5420 | { 0x06, 0x0002, 0x0001 }, | |
5421 | { 0x06, 0x0000, 0x0030 }, | |
5422 | { 0x07, 0x0000, 0x2000 }, | |
5423 | { 0x00, 0x0000, 0x0020 }, | |
5424 | { 0x03, 0x5800, 0x2000 }, | |
5425 | { 0x03, 0x0000, 0x0001 }, | |
5426 | { 0x01, 0x0800, 0x1000 }, | |
5427 | { 0x07, 0x0000, 0x4000 }, | |
5428 | { 0x1e, 0x0000, 0x2000 }, | |
5429 | { 0x19, 0xffff, 0xfe6c }, | |
5430 | { 0x0a, 0x0000, 0x0040 } | |
5431 | }; | |
5432 | ||
beb1fe18 | 5433 | rtl_csi_access_enable_2(tp); |
01dc7fec | 5434 | |
fdf6fc06 | 5435 | rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1)); |
01dc7fec | 5436 | |
faf1e785 | 5437 | if (tp->dev->mtu <= ETH_DATA_LEN) |
5438 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
01dc7fec | 5439 | |
5440 | RTL_W8(MaxTxPacketSize, TxPacketMax); | |
5441 | ||
5442 | rtl_disable_clock_request(pdev); | |
5443 | ||
5444 | /* Reset tx FIFO pointer */ | |
cecb5fd7 FR |
5445 | RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST); |
5446 | RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST); | |
01dc7fec | 5447 | |
cecb5fd7 | 5448 | RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en); |
01dc7fec | 5449 | } |
5450 | ||
beb1fe18 | 5451 | static void rtl_hw_start_8168e_2(struct rtl8169_private *tp) |
70090424 | 5452 | { |
beb1fe18 HW |
5453 | void __iomem *ioaddr = tp->mmio_addr; |
5454 | struct pci_dev *pdev = tp->pci_dev; | |
70090424 HW |
5455 | static const struct ephy_info e_info_8168e_2[] = { |
5456 | { 0x09, 0x0000, 0x0080 }, | |
5457 | { 0x19, 0x0000, 0x0224 } | |
5458 | }; | |
5459 | ||
beb1fe18 | 5460 | rtl_csi_access_enable_1(tp); |
70090424 | 5461 | |
fdf6fc06 | 5462 | rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2)); |
70090424 | 5463 | |
faf1e785 | 5464 | if (tp->dev->mtu <= ETH_DATA_LEN) |
5465 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
70090424 | 5466 | |
fdf6fc06 FR |
5467 | rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); |
5468 | rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); | |
5469 | rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC); | |
5470 | rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC); | |
5471 | rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC); | |
5472 | rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC); | |
5473 | rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC); | |
5474 | rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC); | |
70090424 | 5475 | |
3090bd9a | 5476 | RTL_W8(MaxTxPacketSize, EarlySize); |
70090424 | 5477 | |
4521e1a9 FR |
5478 | rtl_disable_clock_request(pdev); |
5479 | ||
70090424 HW |
5480 | RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO); |
5481 | RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB); | |
5482 | ||
5483 | /* Adjust EEE LED frequency */ | |
5484 | RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07); | |
5485 | ||
5486 | RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN); | |
5487 | RTL_W32(MISC, RTL_R32(MISC) | PWM_EN); | |
4521e1a9 | 5488 | RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en); |
70090424 HW |
5489 | } |
5490 | ||
5f886e08 | 5491 | static void rtl_hw_start_8168f(struct rtl8169_private *tp) |
c2218925 | 5492 | { |
beb1fe18 HW |
5493 | void __iomem *ioaddr = tp->mmio_addr; |
5494 | struct pci_dev *pdev = tp->pci_dev; | |
c2218925 | 5495 | |
5f886e08 | 5496 | rtl_csi_access_enable_2(tp); |
c2218925 HW |
5497 | |
5498 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
5499 | ||
fdf6fc06 FR |
5500 | rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); |
5501 | rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); | |
5502 | rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC); | |
5503 | rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC); | |
5504 | rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC); | |
5505 | rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC); | |
5506 | rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC); | |
5507 | rtl_w1w0_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC); | |
5508 | rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC); | |
5509 | rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC); | |
c2218925 HW |
5510 | |
5511 | RTL_W8(MaxTxPacketSize, EarlySize); | |
5512 | ||
4521e1a9 FR |
5513 | rtl_disable_clock_request(pdev); |
5514 | ||
c2218925 HW |
5515 | RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO); |
5516 | RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB); | |
c2218925 | 5517 | RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN); |
4521e1a9 FR |
5518 | RTL_W32(MISC, RTL_R32(MISC) | PWM_EN); |
5519 | RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en); | |
c2218925 HW |
5520 | } |
5521 | ||
5f886e08 HW |
5522 | static void rtl_hw_start_8168f_1(struct rtl8169_private *tp) |
5523 | { | |
5524 | void __iomem *ioaddr = tp->mmio_addr; | |
5525 | static const struct ephy_info e_info_8168f_1[] = { | |
5526 | { 0x06, 0x00c0, 0x0020 }, | |
5527 | { 0x08, 0x0001, 0x0002 }, | |
5528 | { 0x09, 0x0000, 0x0080 }, | |
5529 | { 0x19, 0x0000, 0x0224 } | |
5530 | }; | |
5531 | ||
5532 | rtl_hw_start_8168f(tp); | |
5533 | ||
fdf6fc06 | 5534 | rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1)); |
5f886e08 | 5535 | |
fdf6fc06 | 5536 | rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC); |
5f886e08 HW |
5537 | |
5538 | /* Adjust EEE LED frequency */ | |
5539 | RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07); | |
5540 | } | |
5541 | ||
b3d7b2f2 HW |
5542 | static void rtl_hw_start_8411(struct rtl8169_private *tp) |
5543 | { | |
b3d7b2f2 HW |
5544 | static const struct ephy_info e_info_8168f_1[] = { |
5545 | { 0x06, 0x00c0, 0x0020 }, | |
5546 | { 0x0f, 0xffff, 0x5200 }, | |
5547 | { 0x1e, 0x0000, 0x4000 }, | |
5548 | { 0x19, 0x0000, 0x0224 } | |
5549 | }; | |
5550 | ||
5551 | rtl_hw_start_8168f(tp); | |
b51ecea8 | 5552 | rtl_pcie_state_l2l3_enable(tp, false); |
b3d7b2f2 | 5553 | |
fdf6fc06 | 5554 | rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1)); |
b3d7b2f2 | 5555 | |
fdf6fc06 | 5556 | rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC); |
b3d7b2f2 HW |
5557 | } |
5558 | ||
c558386b HW |
5559 | static void rtl_hw_start_8168g_1(struct rtl8169_private *tp) |
5560 | { | |
5561 | void __iomem *ioaddr = tp->mmio_addr; | |
5562 | struct pci_dev *pdev = tp->pci_dev; | |
5563 | ||
beb330a4 | 5564 | RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO); |
5565 | ||
c558386b HW |
5566 | rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC); |
5567 | rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC); | |
5568 | rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC); | |
5569 | rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC); | |
5570 | ||
5571 | rtl_csi_access_enable_1(tp); | |
5572 | ||
5573 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
5574 | ||
5575 | rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC); | |
5576 | rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC); | |
beb330a4 | 5577 | rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC); |
c558386b HW |
5578 | |
5579 | RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); | |
4521e1a9 | 5580 | RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN); |
c558386b HW |
5581 | RTL_W8(MaxTxPacketSize, EarlySize); |
5582 | ||
5583 | rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); | |
5584 | rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); | |
5585 | ||
5586 | /* Adjust EEE LED frequency */ | |
5587 | RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07); | |
5588 | ||
beb330a4 | 5589 | rtl_w1w0_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC); |
5590 | rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC); | |
b51ecea8 | 5591 | |
5592 | rtl_pcie_state_l2l3_enable(tp, false); | |
c558386b HW |
5593 | } |
5594 | ||
57538c4a | 5595 | static void rtl_hw_start_8168g_2(struct rtl8169_private *tp) |
5596 | { | |
5597 | void __iomem *ioaddr = tp->mmio_addr; | |
5598 | static const struct ephy_info e_info_8168g_2[] = { | |
5599 | { 0x00, 0x0000, 0x0008 }, | |
5600 | { 0x0c, 0x3df0, 0x0200 }, | |
5601 | { 0x19, 0xffff, 0xfc00 }, | |
5602 | { 0x1e, 0xffff, 0x20eb } | |
5603 | }; | |
5604 | ||
5605 | rtl_hw_start_8168g_1(tp); | |
5606 | ||
5607 | /* disable aspm and clock request before access ephy */ | |
5608 | RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn); | |
5609 | RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en); | |
5610 | rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2)); | |
5611 | } | |
5612 | ||
45dd95c4 | 5613 | static void rtl_hw_start_8411_2(struct rtl8169_private *tp) |
5614 | { | |
5615 | void __iomem *ioaddr = tp->mmio_addr; | |
5616 | static const struct ephy_info e_info_8411_2[] = { | |
5617 | { 0x00, 0x0000, 0x0008 }, | |
5618 | { 0x0c, 0x3df0, 0x0200 }, | |
5619 | { 0x0f, 0xffff, 0x5200 }, | |
5620 | { 0x19, 0x0020, 0x0000 }, | |
5621 | { 0x1e, 0x0000, 0x2000 } | |
5622 | }; | |
5623 | ||
5624 | rtl_hw_start_8168g_1(tp); | |
5625 | ||
5626 | /* disable aspm and clock request before access ephy */ | |
5627 | RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn); | |
5628 | RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en); | |
5629 | rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2)); | |
5630 | } | |
5631 | ||
6e1d0b89 CHL |
5632 | static void rtl_hw_start_8168h_1(struct rtl8169_private *tp) |
5633 | { | |
5634 | void __iomem *ioaddr = tp->mmio_addr; | |
5635 | struct pci_dev *pdev = tp->pci_dev; | |
5636 | u16 rg_saw_cnt; | |
5637 | u32 data; | |
5638 | static const struct ephy_info e_info_8168h_1[] = { | |
5639 | { 0x1e, 0x0800, 0x0001 }, | |
5640 | { 0x1d, 0x0000, 0x0800 }, | |
5641 | { 0x05, 0xffff, 0x2089 }, | |
5642 | { 0x06, 0xffff, 0x5881 }, | |
5643 | { 0x04, 0xffff, 0x154a }, | |
5644 | { 0x01, 0xffff, 0x068b } | |
5645 | }; | |
5646 | ||
5647 | /* disable aspm and clock request before access ephy */ | |
5648 | RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn); | |
5649 | RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en); | |
5650 | rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1)); | |
5651 | ||
5652 | RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO); | |
5653 | ||
5654 | rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC); | |
5655 | rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC); | |
5656 | rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC); | |
5657 | rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC); | |
5658 | ||
5659 | rtl_csi_access_enable_1(tp); | |
5660 | ||
5661 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
5662 | ||
5663 | rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC); | |
5664 | rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC); | |
5665 | ||
5666 | rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC); | |
5667 | ||
5668 | rtl_w1w0_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC); | |
5669 | ||
5670 | rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC); | |
5671 | ||
5672 | RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); | |
5673 | RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN); | |
5674 | RTL_W8(MaxTxPacketSize, EarlySize); | |
5675 | ||
5676 | rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); | |
5677 | rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); | |
5678 | ||
5679 | /* Adjust EEE LED frequency */ | |
5680 | RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07); | |
5681 | ||
5682 | RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN); | |
5683 | RTL_W8(DLLPR, RTL_R8(MISC_1) & ~PFM_D3COLD_EN); | |
5684 | ||
5685 | RTL_W8(DLLPR, RTL_R8(DLLPR) & ~TX_10M_PS_EN); | |
5686 | ||
5687 | rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC); | |
5688 | ||
5689 | rtl_pcie_state_l2l3_enable(tp, false); | |
5690 | ||
5691 | rtl_writephy(tp, 0x1f, 0x0c42); | |
5692 | rg_saw_cnt = rtl_readphy(tp, 0x13); | |
5693 | rtl_writephy(tp, 0x1f, 0x0000); | |
5694 | if (rg_saw_cnt > 0) { | |
5695 | u16 sw_cnt_1ms_ini; | |
5696 | ||
5697 | sw_cnt_1ms_ini = 16000000/rg_saw_cnt; | |
5698 | sw_cnt_1ms_ini &= 0x0fff; | |
5699 | data = r8168_mac_ocp_read(tp, 0xd412); | |
5700 | data &= 0x0fff; | |
5701 | data |= sw_cnt_1ms_ini; | |
5702 | r8168_mac_ocp_write(tp, 0xd412, data); | |
5703 | } | |
5704 | ||
5705 | data = r8168_mac_ocp_read(tp, 0xe056); | |
5706 | data &= 0xf0; | |
5707 | data |= 0x07; | |
5708 | r8168_mac_ocp_write(tp, 0xe056, data); | |
5709 | ||
5710 | data = r8168_mac_ocp_read(tp, 0xe052); | |
5711 | data &= 0x8008; | |
5712 | data |= 0x6000; | |
5713 | r8168_mac_ocp_write(tp, 0xe052, data); | |
5714 | ||
5715 | data = r8168_mac_ocp_read(tp, 0xe0d6); | |
5716 | data &= 0x01ff; | |
5717 | data |= 0x017f; | |
5718 | r8168_mac_ocp_write(tp, 0xe0d6, data); | |
5719 | ||
5720 | data = r8168_mac_ocp_read(tp, 0xd420); | |
5721 | data &= 0x0fff; | |
5722 | data |= 0x047f; | |
5723 | r8168_mac_ocp_write(tp, 0xd420, data); | |
5724 | ||
5725 | r8168_mac_ocp_write(tp, 0xe63e, 0x0001); | |
5726 | r8168_mac_ocp_write(tp, 0xe63e, 0x0000); | |
5727 | r8168_mac_ocp_write(tp, 0xc094, 0x0000); | |
5728 | r8168_mac_ocp_write(tp, 0xc09e, 0x0000); | |
5729 | } | |
5730 | ||
07ce4064 FR |
5731 | static void rtl_hw_start_8168(struct net_device *dev) |
5732 | { | |
2dd99530 FR |
5733 | struct rtl8169_private *tp = netdev_priv(dev); |
5734 | void __iomem *ioaddr = tp->mmio_addr; | |
5735 | ||
5736 | RTL_W8(Cfg9346, Cfg9346_Unlock); | |
5737 | ||
f0298f81 | 5738 | RTL_W8(MaxTxPacketSize, TxPacketMax); |
2dd99530 | 5739 | |
6f0333b8 | 5740 | rtl_set_rx_max_size(ioaddr, rx_buf_sz); |
2dd99530 | 5741 | |
0e485150 | 5742 | tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1; |
2dd99530 FR |
5743 | |
5744 | RTL_W16(CPlusCmd, tp->cp_cmd); | |
5745 | ||
0e485150 | 5746 | RTL_W16(IntrMitigate, 0x5151); |
2dd99530 | 5747 | |
0e485150 | 5748 | /* Work around for RxFIFO overflow. */ |
811fd301 | 5749 | if (tp->mac_version == RTL_GIGA_MAC_VER_11) { |
da78dbff FR |
5750 | tp->event_slow |= RxFIFOOver | PCSTimeout; |
5751 | tp->event_slow &= ~RxOverflow; | |
0e485150 FR |
5752 | } |
5753 | ||
5754 | rtl_set_rx_tx_desc_registers(tp, ioaddr); | |
2dd99530 | 5755 | |
1a964649 | 5756 | rtl_set_rx_tx_config_registers(tp); |
2dd99530 FR |
5757 | |
5758 | RTL_R8(IntrMask); | |
5759 | ||
219a1e9d FR |
5760 | switch (tp->mac_version) { |
5761 | case RTL_GIGA_MAC_VER_11: | |
beb1fe18 | 5762 | rtl_hw_start_8168bb(tp); |
4804b3b3 | 5763 | break; |
219a1e9d FR |
5764 | |
5765 | case RTL_GIGA_MAC_VER_12: | |
5766 | case RTL_GIGA_MAC_VER_17: | |
beb1fe18 | 5767 | rtl_hw_start_8168bef(tp); |
4804b3b3 | 5768 | break; |
219a1e9d FR |
5769 | |
5770 | case RTL_GIGA_MAC_VER_18: | |
beb1fe18 | 5771 | rtl_hw_start_8168cp_1(tp); |
4804b3b3 | 5772 | break; |
219a1e9d FR |
5773 | |
5774 | case RTL_GIGA_MAC_VER_19: | |
beb1fe18 | 5775 | rtl_hw_start_8168c_1(tp); |
4804b3b3 | 5776 | break; |
219a1e9d FR |
5777 | |
5778 | case RTL_GIGA_MAC_VER_20: | |
beb1fe18 | 5779 | rtl_hw_start_8168c_2(tp); |
4804b3b3 | 5780 | break; |
219a1e9d | 5781 | |
197ff761 | 5782 | case RTL_GIGA_MAC_VER_21: |
beb1fe18 | 5783 | rtl_hw_start_8168c_3(tp); |
4804b3b3 | 5784 | break; |
197ff761 | 5785 | |
6fb07058 | 5786 | case RTL_GIGA_MAC_VER_22: |
beb1fe18 | 5787 | rtl_hw_start_8168c_4(tp); |
4804b3b3 | 5788 | break; |
6fb07058 | 5789 | |
ef3386f0 | 5790 | case RTL_GIGA_MAC_VER_23: |
beb1fe18 | 5791 | rtl_hw_start_8168cp_2(tp); |
4804b3b3 | 5792 | break; |
ef3386f0 | 5793 | |
7f3e3d3a | 5794 | case RTL_GIGA_MAC_VER_24: |
beb1fe18 | 5795 | rtl_hw_start_8168cp_3(tp); |
4804b3b3 | 5796 | break; |
7f3e3d3a | 5797 | |
5b538df9 | 5798 | case RTL_GIGA_MAC_VER_25: |
daf9df6d | 5799 | case RTL_GIGA_MAC_VER_26: |
5800 | case RTL_GIGA_MAC_VER_27: | |
beb1fe18 | 5801 | rtl_hw_start_8168d(tp); |
4804b3b3 | 5802 | break; |
5b538df9 | 5803 | |
e6de30d6 | 5804 | case RTL_GIGA_MAC_VER_28: |
beb1fe18 | 5805 | rtl_hw_start_8168d_4(tp); |
4804b3b3 | 5806 | break; |
cecb5fd7 | 5807 | |
4804b3b3 | 5808 | case RTL_GIGA_MAC_VER_31: |
beb1fe18 | 5809 | rtl_hw_start_8168dp(tp); |
4804b3b3 | 5810 | break; |
5811 | ||
01dc7fec | 5812 | case RTL_GIGA_MAC_VER_32: |
5813 | case RTL_GIGA_MAC_VER_33: | |
beb1fe18 | 5814 | rtl_hw_start_8168e_1(tp); |
70090424 HW |
5815 | break; |
5816 | case RTL_GIGA_MAC_VER_34: | |
beb1fe18 | 5817 | rtl_hw_start_8168e_2(tp); |
01dc7fec | 5818 | break; |
e6de30d6 | 5819 | |
c2218925 HW |
5820 | case RTL_GIGA_MAC_VER_35: |
5821 | case RTL_GIGA_MAC_VER_36: | |
beb1fe18 | 5822 | rtl_hw_start_8168f_1(tp); |
c2218925 HW |
5823 | break; |
5824 | ||
b3d7b2f2 HW |
5825 | case RTL_GIGA_MAC_VER_38: |
5826 | rtl_hw_start_8411(tp); | |
5827 | break; | |
5828 | ||
c558386b HW |
5829 | case RTL_GIGA_MAC_VER_40: |
5830 | case RTL_GIGA_MAC_VER_41: | |
5831 | rtl_hw_start_8168g_1(tp); | |
5832 | break; | |
57538c4a | 5833 | case RTL_GIGA_MAC_VER_42: |
5834 | rtl_hw_start_8168g_2(tp); | |
5835 | break; | |
c558386b | 5836 | |
45dd95c4 | 5837 | case RTL_GIGA_MAC_VER_44: |
5838 | rtl_hw_start_8411_2(tp); | |
5839 | break; | |
5840 | ||
6e1d0b89 CHL |
5841 | case RTL_GIGA_MAC_VER_45: |
5842 | case RTL_GIGA_MAC_VER_46: | |
5843 | rtl_hw_start_8168h_1(tp); | |
5844 | break; | |
5845 | ||
219a1e9d FR |
5846 | default: |
5847 | printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n", | |
5848 | dev->name, tp->mac_version); | |
4804b3b3 | 5849 | break; |
219a1e9d | 5850 | } |
2dd99530 | 5851 | |
1a964649 | 5852 | RTL_W8(Cfg9346, Cfg9346_Lock); |
5853 | ||
0e485150 FR |
5854 | RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
5855 | ||
1a964649 | 5856 | rtl_set_rx_mode(dev); |
b8363901 | 5857 | |
2dd99530 | 5858 | RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); |
07ce4064 | 5859 | } |
1da177e4 | 5860 | |
2857ffb7 FR |
5861 | #define R810X_CPCMD_QUIRK_MASK (\ |
5862 | EnableBist | \ | |
5863 | Mac_dbgo_oe | \ | |
5864 | Force_half_dup | \ | |
5edcc537 | 5865 | Force_rxflow_en | \ |
2857ffb7 FR |
5866 | Force_txflow_en | \ |
5867 | Cxpl_dbg_sel | \ | |
5868 | ASF | \ | |
5869 | PktCntrDisable | \ | |
d24e9aaf | 5870 | Mac_dbgo_sel) |
2857ffb7 | 5871 | |
beb1fe18 | 5872 | static void rtl_hw_start_8102e_1(struct rtl8169_private *tp) |
2857ffb7 | 5873 | { |
beb1fe18 HW |
5874 | void __iomem *ioaddr = tp->mmio_addr; |
5875 | struct pci_dev *pdev = tp->pci_dev; | |
350f7596 | 5876 | static const struct ephy_info e_info_8102e_1[] = { |
2857ffb7 FR |
5877 | { 0x01, 0, 0x6e65 }, |
5878 | { 0x02, 0, 0x091f }, | |
5879 | { 0x03, 0, 0xc2f9 }, | |
5880 | { 0x06, 0, 0xafb5 }, | |
5881 | { 0x07, 0, 0x0e00 }, | |
5882 | { 0x19, 0, 0xec80 }, | |
5883 | { 0x01, 0, 0x2e65 }, | |
5884 | { 0x01, 0, 0x6e65 } | |
5885 | }; | |
5886 | u8 cfg1; | |
5887 | ||
beb1fe18 | 5888 | rtl_csi_access_enable_2(tp); |
2857ffb7 FR |
5889 | |
5890 | RTL_W8(DBG_REG, FIX_NAK_1); | |
5891 | ||
5892 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
5893 | ||
5894 | RTL_W8(Config1, | |
5895 | LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); | |
5896 | RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); | |
5897 | ||
5898 | cfg1 = RTL_R8(Config1); | |
5899 | if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) | |
5900 | RTL_W8(Config1, cfg1 & ~LEDS0); | |
5901 | ||
fdf6fc06 | 5902 | rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1)); |
2857ffb7 FR |
5903 | } |
5904 | ||
beb1fe18 | 5905 | static void rtl_hw_start_8102e_2(struct rtl8169_private *tp) |
2857ffb7 | 5906 | { |
beb1fe18 HW |
5907 | void __iomem *ioaddr = tp->mmio_addr; |
5908 | struct pci_dev *pdev = tp->pci_dev; | |
5909 | ||
5910 | rtl_csi_access_enable_2(tp); | |
2857ffb7 FR |
5911 | |
5912 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
5913 | ||
5914 | RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable); | |
5915 | RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); | |
2857ffb7 FR |
5916 | } |
5917 | ||
beb1fe18 | 5918 | static void rtl_hw_start_8102e_3(struct rtl8169_private *tp) |
2857ffb7 | 5919 | { |
beb1fe18 | 5920 | rtl_hw_start_8102e_2(tp); |
2857ffb7 | 5921 | |
fdf6fc06 | 5922 | rtl_ephy_write(tp, 0x03, 0xc2f9); |
2857ffb7 FR |
5923 | } |
5924 | ||
beb1fe18 | 5925 | static void rtl_hw_start_8105e_1(struct rtl8169_private *tp) |
5a5e4443 | 5926 | { |
beb1fe18 | 5927 | void __iomem *ioaddr = tp->mmio_addr; |
5a5e4443 HW |
5928 | static const struct ephy_info e_info_8105e_1[] = { |
5929 | { 0x07, 0, 0x4000 }, | |
5930 | { 0x19, 0, 0x0200 }, | |
5931 | { 0x19, 0, 0x0020 }, | |
5932 | { 0x1e, 0, 0x2000 }, | |
5933 | { 0x03, 0, 0x0001 }, | |
5934 | { 0x19, 0, 0x0100 }, | |
5935 | { 0x19, 0, 0x0004 }, | |
5936 | { 0x0a, 0, 0x0020 } | |
5937 | }; | |
5938 | ||
cecb5fd7 | 5939 | /* Force LAN exit from ASPM if Rx/Tx are not idle */ |
5a5e4443 HW |
5940 | RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800); |
5941 | ||
cecb5fd7 | 5942 | /* Disable Early Tally Counter */ |
5a5e4443 HW |
5943 | RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000); |
5944 | ||
5945 | RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET); | |
4f6b00e5 | 5946 | RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN); |
5a5e4443 | 5947 | |
fdf6fc06 | 5948 | rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1)); |
b51ecea8 | 5949 | |
5950 | rtl_pcie_state_l2l3_enable(tp, false); | |
5a5e4443 HW |
5951 | } |
5952 | ||
beb1fe18 | 5953 | static void rtl_hw_start_8105e_2(struct rtl8169_private *tp) |
5a5e4443 | 5954 | { |
beb1fe18 | 5955 | rtl_hw_start_8105e_1(tp); |
fdf6fc06 | 5956 | rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000); |
5a5e4443 HW |
5957 | } |
5958 | ||
7e18dca1 HW |
5959 | static void rtl_hw_start_8402(struct rtl8169_private *tp) |
5960 | { | |
5961 | void __iomem *ioaddr = tp->mmio_addr; | |
5962 | static const struct ephy_info e_info_8402[] = { | |
5963 | { 0x19, 0xffff, 0xff64 }, | |
5964 | { 0x1e, 0, 0x4000 } | |
5965 | }; | |
5966 | ||
5967 | rtl_csi_access_enable_2(tp); | |
5968 | ||
5969 | /* Force LAN exit from ASPM if Rx/Tx are not idle */ | |
5970 | RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800); | |
5971 | ||
5972 | RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO); | |
5973 | RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB); | |
5974 | ||
fdf6fc06 | 5975 | rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402)); |
7e18dca1 HW |
5976 | |
5977 | rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
5978 | ||
fdf6fc06 FR |
5979 | rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC); |
5980 | rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC); | |
5981 | rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC); | |
5982 | rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC); | |
5983 | rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); | |
5984 | rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); | |
5985 | rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC); | |
b51ecea8 | 5986 | |
5987 | rtl_pcie_state_l2l3_enable(tp, false); | |
7e18dca1 HW |
5988 | } |
5989 | ||
5598bfe5 HW |
5990 | static void rtl_hw_start_8106(struct rtl8169_private *tp) |
5991 | { | |
5992 | void __iomem *ioaddr = tp->mmio_addr; | |
5993 | ||
5994 | /* Force LAN exit from ASPM if Rx/Tx are not idle */ | |
5995 | RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800); | |
5996 | ||
4521e1a9 | 5997 | RTL_W32(MISC, (RTL_R32(MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN); |
5598bfe5 HW |
5998 | RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET); |
5999 | RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN); | |
b51ecea8 | 6000 | |
6001 | rtl_pcie_state_l2l3_enable(tp, false); | |
5598bfe5 HW |
6002 | } |
6003 | ||
07ce4064 FR |
6004 | static void rtl_hw_start_8101(struct net_device *dev) |
6005 | { | |
cdf1a608 FR |
6006 | struct rtl8169_private *tp = netdev_priv(dev); |
6007 | void __iomem *ioaddr = tp->mmio_addr; | |
6008 | struct pci_dev *pdev = tp->pci_dev; | |
6009 | ||
da78dbff FR |
6010 | if (tp->mac_version >= RTL_GIGA_MAC_VER_30) |
6011 | tp->event_slow &= ~RxFIFOOver; | |
811fd301 | 6012 | |
cecb5fd7 | 6013 | if (tp->mac_version == RTL_GIGA_MAC_VER_13 || |
7d7903b2 | 6014 | tp->mac_version == RTL_GIGA_MAC_VER_16) |
8200bc72 BH |
6015 | pcie_capability_set_word(pdev, PCI_EXP_DEVCTL, |
6016 | PCI_EXP_DEVCTL_NOSNOOP_EN); | |
cdf1a608 | 6017 | |
d24e9aaf HW |
6018 | RTL_W8(Cfg9346, Cfg9346_Unlock); |
6019 | ||
1a964649 | 6020 | RTL_W8(MaxTxPacketSize, TxPacketMax); |
6021 | ||
6022 | rtl_set_rx_max_size(ioaddr, rx_buf_sz); | |
6023 | ||
6024 | tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK; | |
6025 | RTL_W16(CPlusCmd, tp->cp_cmd); | |
6026 | ||
6027 | rtl_set_rx_tx_desc_registers(tp, ioaddr); | |
6028 | ||
6029 | rtl_set_rx_tx_config_registers(tp); | |
6030 | ||
2857ffb7 FR |
6031 | switch (tp->mac_version) { |
6032 | case RTL_GIGA_MAC_VER_07: | |
beb1fe18 | 6033 | rtl_hw_start_8102e_1(tp); |
2857ffb7 FR |
6034 | break; |
6035 | ||
6036 | case RTL_GIGA_MAC_VER_08: | |
beb1fe18 | 6037 | rtl_hw_start_8102e_3(tp); |
2857ffb7 FR |
6038 | break; |
6039 | ||
6040 | case RTL_GIGA_MAC_VER_09: | |
beb1fe18 | 6041 | rtl_hw_start_8102e_2(tp); |
2857ffb7 | 6042 | break; |
5a5e4443 HW |
6043 | |
6044 | case RTL_GIGA_MAC_VER_29: | |
beb1fe18 | 6045 | rtl_hw_start_8105e_1(tp); |
5a5e4443 HW |
6046 | break; |
6047 | case RTL_GIGA_MAC_VER_30: | |
beb1fe18 | 6048 | rtl_hw_start_8105e_2(tp); |
5a5e4443 | 6049 | break; |
7e18dca1 HW |
6050 | |
6051 | case RTL_GIGA_MAC_VER_37: | |
6052 | rtl_hw_start_8402(tp); | |
6053 | break; | |
5598bfe5 HW |
6054 | |
6055 | case RTL_GIGA_MAC_VER_39: | |
6056 | rtl_hw_start_8106(tp); | |
6057 | break; | |
58152cd4 | 6058 | case RTL_GIGA_MAC_VER_43: |
6059 | rtl_hw_start_8168g_2(tp); | |
6060 | break; | |
6e1d0b89 CHL |
6061 | case RTL_GIGA_MAC_VER_47: |
6062 | case RTL_GIGA_MAC_VER_48: | |
6063 | rtl_hw_start_8168h_1(tp); | |
6064 | break; | |
cdf1a608 FR |
6065 | } |
6066 | ||
d24e9aaf | 6067 | RTL_W8(Cfg9346, Cfg9346_Lock); |
cdf1a608 | 6068 | |
cdf1a608 FR |
6069 | RTL_W16(IntrMitigate, 0x0000); |
6070 | ||
cdf1a608 | 6071 | RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
cdf1a608 | 6072 | |
cdf1a608 FR |
6073 | rtl_set_rx_mode(dev); |
6074 | ||
1a964649 | 6075 | RTL_R8(IntrMask); |
6076 | ||
cdf1a608 | 6077 | RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000); |
1da177e4 LT |
6078 | } |
6079 | ||
6080 | static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) | |
6081 | { | |
d58d46b5 FR |
6082 | struct rtl8169_private *tp = netdev_priv(dev); |
6083 | ||
6084 | if (new_mtu < ETH_ZLEN || | |
6085 | new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max) | |
1da177e4 LT |
6086 | return -EINVAL; |
6087 | ||
d58d46b5 FR |
6088 | if (new_mtu > ETH_DATA_LEN) |
6089 | rtl_hw_jumbo_enable(tp); | |
6090 | else | |
6091 | rtl_hw_jumbo_disable(tp); | |
6092 | ||
1da177e4 | 6093 | dev->mtu = new_mtu; |
350fb32a MM |
6094 | netdev_update_features(dev); |
6095 | ||
323bb685 | 6096 | return 0; |
1da177e4 LT |
6097 | } |
6098 | ||
6099 | static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc) | |
6100 | { | |
95e0918d | 6101 | desc->addr = cpu_to_le64(0x0badbadbadbadbadull); |
1da177e4 LT |
6102 | desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask); |
6103 | } | |
6104 | ||
6f0333b8 ED |
6105 | static void rtl8169_free_rx_databuff(struct rtl8169_private *tp, |
6106 | void **data_buff, struct RxDesc *desc) | |
1da177e4 | 6107 | { |
48addcc9 | 6108 | dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz, |
231aee63 | 6109 | DMA_FROM_DEVICE); |
48addcc9 | 6110 | |
6f0333b8 ED |
6111 | kfree(*data_buff); |
6112 | *data_buff = NULL; | |
1da177e4 LT |
6113 | rtl8169_make_unusable_by_asic(desc); |
6114 | } | |
6115 | ||
6116 | static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz) | |
6117 | { | |
6118 | u32 eor = le32_to_cpu(desc->opts1) & RingEnd; | |
6119 | ||
6120 | desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz); | |
6121 | } | |
6122 | ||
6123 | static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping, | |
6124 | u32 rx_buf_sz) | |
6125 | { | |
6126 | desc->addr = cpu_to_le64(mapping); | |
6127 | wmb(); | |
6128 | rtl8169_mark_to_asic(desc, rx_buf_sz); | |
6129 | } | |
6130 | ||
6f0333b8 ED |
6131 | static inline void *rtl8169_align(void *data) |
6132 | { | |
6133 | return (void *)ALIGN((long)data, 16); | |
6134 | } | |
6135 | ||
0ecbe1ca SG |
6136 | static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp, |
6137 | struct RxDesc *desc) | |
1da177e4 | 6138 | { |
6f0333b8 | 6139 | void *data; |
1da177e4 | 6140 | dma_addr_t mapping; |
48addcc9 | 6141 | struct device *d = &tp->pci_dev->dev; |
0ecbe1ca | 6142 | struct net_device *dev = tp->dev; |
6f0333b8 | 6143 | int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1; |
1da177e4 | 6144 | |
6f0333b8 ED |
6145 | data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node); |
6146 | if (!data) | |
6147 | return NULL; | |
e9f63f30 | 6148 | |
6f0333b8 ED |
6149 | if (rtl8169_align(data) != data) { |
6150 | kfree(data); | |
6151 | data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node); | |
6152 | if (!data) | |
6153 | return NULL; | |
6154 | } | |
3eafe507 | 6155 | |
48addcc9 | 6156 | mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz, |
231aee63 | 6157 | DMA_FROM_DEVICE); |
d827d86b SG |
6158 | if (unlikely(dma_mapping_error(d, mapping))) { |
6159 | if (net_ratelimit()) | |
6160 | netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n"); | |
3eafe507 | 6161 | goto err_out; |
d827d86b | 6162 | } |
1da177e4 LT |
6163 | |
6164 | rtl8169_map_to_asic(desc, mapping, rx_buf_sz); | |
6f0333b8 | 6165 | return data; |
3eafe507 SG |
6166 | |
6167 | err_out: | |
6168 | kfree(data); | |
6169 | return NULL; | |
1da177e4 LT |
6170 | } |
6171 | ||
6172 | static void rtl8169_rx_clear(struct rtl8169_private *tp) | |
6173 | { | |
07d3f51f | 6174 | unsigned int i; |
1da177e4 LT |
6175 | |
6176 | for (i = 0; i < NUM_RX_DESC; i++) { | |
6f0333b8 ED |
6177 | if (tp->Rx_databuff[i]) { |
6178 | rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i, | |
1da177e4 LT |
6179 | tp->RxDescArray + i); |
6180 | } | |
6181 | } | |
6182 | } | |
6183 | ||
0ecbe1ca | 6184 | static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc) |
1da177e4 | 6185 | { |
0ecbe1ca SG |
6186 | desc->opts1 |= cpu_to_le32(RingEnd); |
6187 | } | |
5b0384f4 | 6188 | |
0ecbe1ca SG |
6189 | static int rtl8169_rx_fill(struct rtl8169_private *tp) |
6190 | { | |
6191 | unsigned int i; | |
1da177e4 | 6192 | |
0ecbe1ca SG |
6193 | for (i = 0; i < NUM_RX_DESC; i++) { |
6194 | void *data; | |
4ae47c2d | 6195 | |
6f0333b8 | 6196 | if (tp->Rx_databuff[i]) |
1da177e4 | 6197 | continue; |
bcf0bf90 | 6198 | |
0ecbe1ca | 6199 | data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i); |
6f0333b8 ED |
6200 | if (!data) { |
6201 | rtl8169_make_unusable_by_asic(tp->RxDescArray + i); | |
0ecbe1ca | 6202 | goto err_out; |
6f0333b8 ED |
6203 | } |
6204 | tp->Rx_databuff[i] = data; | |
1da177e4 | 6205 | } |
1da177e4 | 6206 | |
0ecbe1ca SG |
6207 | rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1); |
6208 | return 0; | |
6209 | ||
6210 | err_out: | |
6211 | rtl8169_rx_clear(tp); | |
6212 | return -ENOMEM; | |
1da177e4 LT |
6213 | } |
6214 | ||
1da177e4 LT |
6215 | static int rtl8169_init_ring(struct net_device *dev) |
6216 | { | |
6217 | struct rtl8169_private *tp = netdev_priv(dev); | |
6218 | ||
6219 | rtl8169_init_ring_indexes(tp); | |
6220 | ||
6221 | memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info)); | |
6f0333b8 | 6222 | memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *)); |
1da177e4 | 6223 | |
0ecbe1ca | 6224 | return rtl8169_rx_fill(tp); |
1da177e4 LT |
6225 | } |
6226 | ||
48addcc9 | 6227 | static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb, |
1da177e4 LT |
6228 | struct TxDesc *desc) |
6229 | { | |
6230 | unsigned int len = tx_skb->len; | |
6231 | ||
48addcc9 SG |
6232 | dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE); |
6233 | ||
1da177e4 LT |
6234 | desc->opts1 = 0x00; |
6235 | desc->opts2 = 0x00; | |
6236 | desc->addr = 0x00; | |
6237 | tx_skb->len = 0; | |
6238 | } | |
6239 | ||
3eafe507 SG |
6240 | static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start, |
6241 | unsigned int n) | |
1da177e4 LT |
6242 | { |
6243 | unsigned int i; | |
6244 | ||
3eafe507 SG |
6245 | for (i = 0; i < n; i++) { |
6246 | unsigned int entry = (start + i) % NUM_TX_DESC; | |
1da177e4 LT |
6247 | struct ring_info *tx_skb = tp->tx_skb + entry; |
6248 | unsigned int len = tx_skb->len; | |
6249 | ||
6250 | if (len) { | |
6251 | struct sk_buff *skb = tx_skb->skb; | |
6252 | ||
48addcc9 | 6253 | rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb, |
1da177e4 LT |
6254 | tp->TxDescArray + entry); |
6255 | if (skb) { | |
cac4b22f | 6256 | tp->dev->stats.tx_dropped++; |
989c9ba1 | 6257 | dev_kfree_skb_any(skb); |
1da177e4 LT |
6258 | tx_skb->skb = NULL; |
6259 | } | |
1da177e4 LT |
6260 | } |
6261 | } | |
3eafe507 SG |
6262 | } |
6263 | ||
6264 | static void rtl8169_tx_clear(struct rtl8169_private *tp) | |
6265 | { | |
6266 | rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC); | |
1da177e4 LT |
6267 | tp->cur_tx = tp->dirty_tx = 0; |
6268 | } | |
6269 | ||
4422bcd4 | 6270 | static void rtl_reset_work(struct rtl8169_private *tp) |
1da177e4 | 6271 | { |
c4028958 | 6272 | struct net_device *dev = tp->dev; |
56de414c | 6273 | int i; |
1da177e4 | 6274 | |
da78dbff FR |
6275 | napi_disable(&tp->napi); |
6276 | netif_stop_queue(dev); | |
6277 | synchronize_sched(); | |
1da177e4 | 6278 | |
c7c2c39b | 6279 | rtl8169_hw_reset(tp); |
6280 | ||
56de414c FR |
6281 | for (i = 0; i < NUM_RX_DESC; i++) |
6282 | rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz); | |
6283 | ||
1da177e4 | 6284 | rtl8169_tx_clear(tp); |
c7c2c39b | 6285 | rtl8169_init_ring_indexes(tp); |
1da177e4 | 6286 | |
da78dbff | 6287 | napi_enable(&tp->napi); |
56de414c FR |
6288 | rtl_hw_start(dev); |
6289 | netif_wake_queue(dev); | |
6290 | rtl8169_check_link_status(dev, tp, tp->mmio_addr); | |
1da177e4 LT |
6291 | } |
6292 | ||
6293 | static void rtl8169_tx_timeout(struct net_device *dev) | |
6294 | { | |
da78dbff FR |
6295 | struct rtl8169_private *tp = netdev_priv(dev); |
6296 | ||
6297 | rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); | |
1da177e4 LT |
6298 | } |
6299 | ||
6300 | static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, | |
2b7b4318 | 6301 | u32 *opts) |
1da177e4 LT |
6302 | { |
6303 | struct skb_shared_info *info = skb_shinfo(skb); | |
6304 | unsigned int cur_frag, entry; | |
6e1d0b89 | 6305 | struct TxDesc *uninitialized_var(txd); |
48addcc9 | 6306 | struct device *d = &tp->pci_dev->dev; |
1da177e4 LT |
6307 | |
6308 | entry = tp->cur_tx; | |
6309 | for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { | |
9e903e08 | 6310 | const skb_frag_t *frag = info->frags + cur_frag; |
1da177e4 LT |
6311 | dma_addr_t mapping; |
6312 | u32 status, len; | |
6313 | void *addr; | |
6314 | ||
6315 | entry = (entry + 1) % NUM_TX_DESC; | |
6316 | ||
6317 | txd = tp->TxDescArray + entry; | |
9e903e08 | 6318 | len = skb_frag_size(frag); |
929f6189 | 6319 | addr = skb_frag_address(frag); |
48addcc9 | 6320 | mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE); |
d827d86b SG |
6321 | if (unlikely(dma_mapping_error(d, mapping))) { |
6322 | if (net_ratelimit()) | |
6323 | netif_err(tp, drv, tp->dev, | |
6324 | "Failed to map TX fragments DMA!\n"); | |
3eafe507 | 6325 | goto err_out; |
d827d86b | 6326 | } |
1da177e4 | 6327 | |
cecb5fd7 | 6328 | /* Anti gcc 2.95.3 bugware (sic) */ |
2b7b4318 FR |
6329 | status = opts[0] | len | |
6330 | (RingEnd * !((entry + 1) % NUM_TX_DESC)); | |
1da177e4 LT |
6331 | |
6332 | txd->opts1 = cpu_to_le32(status); | |
2b7b4318 | 6333 | txd->opts2 = cpu_to_le32(opts[1]); |
1da177e4 LT |
6334 | txd->addr = cpu_to_le64(mapping); |
6335 | ||
6336 | tp->tx_skb[entry].len = len; | |
6337 | } | |
6338 | ||
6339 | if (cur_frag) { | |
6340 | tp->tx_skb[entry].skb = skb; | |
6341 | txd->opts1 |= cpu_to_le32(LastFrag); | |
6342 | } | |
6343 | ||
6344 | return cur_frag; | |
3eafe507 SG |
6345 | |
6346 | err_out: | |
6347 | rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag); | |
6348 | return -EIO; | |
1da177e4 LT |
6349 | } |
6350 | ||
b423e9ae | 6351 | static bool rtl_skb_pad(struct sk_buff *skb) |
6352 | { | |
6353 | if (skb_padto(skb, ETH_ZLEN)) | |
6354 | return false; | |
6355 | skb_put(skb, ETH_ZLEN - skb->len); | |
6356 | return true; | |
6357 | } | |
6358 | ||
6359 | static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb) | |
6360 | { | |
6361 | return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34; | |
6362 | } | |
6363 | ||
e974604b | 6364 | static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, |
6365 | struct net_device *dev); | |
6366 | /* r8169_csum_workaround() | |
6367 | * The hw limites the value the transport offset. When the offset is out of the | |
6368 | * range, calculate the checksum by sw. | |
6369 | */ | |
6370 | static void r8169_csum_workaround(struct rtl8169_private *tp, | |
6371 | struct sk_buff *skb) | |
6372 | { | |
6373 | if (skb_shinfo(skb)->gso_size) { | |
6374 | netdev_features_t features = tp->dev->features; | |
6375 | struct sk_buff *segs, *nskb; | |
6376 | ||
6377 | features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6); | |
6378 | segs = skb_gso_segment(skb, features); | |
6379 | if (IS_ERR(segs) || !segs) | |
6380 | goto drop; | |
6381 | ||
6382 | do { | |
6383 | nskb = segs; | |
6384 | segs = segs->next; | |
6385 | nskb->next = NULL; | |
6386 | rtl8169_start_xmit(nskb, tp->dev); | |
6387 | } while (segs); | |
6388 | ||
6389 | dev_kfree_skb(skb); | |
6390 | } else if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
6391 | if (skb_checksum_help(skb) < 0) | |
6392 | goto drop; | |
6393 | ||
6394 | rtl8169_start_xmit(skb, tp->dev); | |
6395 | } else { | |
6396 | struct net_device_stats *stats; | |
6397 | ||
6398 | drop: | |
6399 | stats = &tp->dev->stats; | |
6400 | stats->tx_dropped++; | |
6401 | dev_kfree_skb(skb); | |
6402 | } | |
6403 | } | |
6404 | ||
6405 | /* msdn_giant_send_check() | |
6406 | * According to the document of microsoft, the TCP Pseudo Header excludes the | |
6407 | * packet length for IPv6 TCP large packets. | |
6408 | */ | |
6409 | static int msdn_giant_send_check(struct sk_buff *skb) | |
6410 | { | |
6411 | const struct ipv6hdr *ipv6h; | |
6412 | struct tcphdr *th; | |
6413 | int ret; | |
6414 | ||
6415 | ret = skb_cow_head(skb, 0); | |
6416 | if (ret) | |
6417 | return ret; | |
6418 | ||
6419 | ipv6h = ipv6_hdr(skb); | |
6420 | th = tcp_hdr(skb); | |
6421 | ||
6422 | th->check = 0; | |
6423 | th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0); | |
6424 | ||
6425 | return ret; | |
6426 | } | |
6427 | ||
6428 | static inline __be16 get_protocol(struct sk_buff *skb) | |
6429 | { | |
6430 | __be16 protocol; | |
6431 | ||
6432 | if (skb->protocol == htons(ETH_P_8021Q)) | |
6433 | protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto; | |
6434 | else | |
6435 | protocol = skb->protocol; | |
6436 | ||
6437 | return protocol; | |
6438 | } | |
6439 | ||
5888d3fc | 6440 | static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp, |
6441 | struct sk_buff *skb, u32 *opts) | |
1da177e4 | 6442 | { |
350fb32a MM |
6443 | u32 mss = skb_shinfo(skb)->gso_size; |
6444 | ||
2b7b4318 FR |
6445 | if (mss) { |
6446 | opts[0] |= TD_LSO; | |
5888d3fc | 6447 | opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT; |
6448 | } else if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
6449 | const struct iphdr *ip = ip_hdr(skb); | |
6450 | ||
6451 | if (ip->protocol == IPPROTO_TCP) | |
6452 | opts[0] |= TD0_IP_CS | TD0_TCP_CS; | |
6453 | else if (ip->protocol == IPPROTO_UDP) | |
6454 | opts[0] |= TD0_IP_CS | TD0_UDP_CS; | |
6455 | else | |
6456 | WARN_ON_ONCE(1); | |
6457 | } | |
6458 | ||
6459 | return true; | |
6460 | } | |
6461 | ||
6462 | static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp, | |
6463 | struct sk_buff *skb, u32 *opts) | |
6464 | { | |
bdfa4ed6 | 6465 | u32 transport_offset = (u32)skb_transport_offset(skb); |
5888d3fc | 6466 | u32 mss = skb_shinfo(skb)->gso_size; |
6467 | ||
6468 | if (mss) { | |
e974604b | 6469 | if (transport_offset > GTTCPHO_MAX) { |
6470 | netif_warn(tp, tx_err, tp->dev, | |
6471 | "Invalid transport offset 0x%x for TSO\n", | |
6472 | transport_offset); | |
6473 | return false; | |
6474 | } | |
6475 | ||
6476 | switch (get_protocol(skb)) { | |
6477 | case htons(ETH_P_IP): | |
6478 | opts[0] |= TD1_GTSENV4; | |
6479 | break; | |
6480 | ||
6481 | case htons(ETH_P_IPV6): | |
6482 | if (msdn_giant_send_check(skb)) | |
6483 | return false; | |
6484 | ||
6485 | opts[0] |= TD1_GTSENV6; | |
6486 | break; | |
6487 | ||
6488 | default: | |
6489 | WARN_ON_ONCE(1); | |
6490 | break; | |
6491 | } | |
6492 | ||
bdfa4ed6 | 6493 | opts[0] |= transport_offset << GTTCPHO_SHIFT; |
5888d3fc | 6494 | opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT; |
2b7b4318 | 6495 | } else if (skb->ip_summed == CHECKSUM_PARTIAL) { |
e974604b | 6496 | u8 ip_protocol; |
1da177e4 | 6497 | |
b423e9ae | 6498 | if (unlikely(rtl_test_hw_pad_bug(tp, skb))) |
6499 | return skb_checksum_help(skb) == 0 && rtl_skb_pad(skb); | |
6500 | ||
e974604b | 6501 | if (transport_offset > TCPHO_MAX) { |
6502 | netif_warn(tp, tx_err, tp->dev, | |
6503 | "Invalid transport offset 0x%x\n", | |
6504 | transport_offset); | |
6505 | return false; | |
6506 | } | |
6507 | ||
6508 | switch (get_protocol(skb)) { | |
6509 | case htons(ETH_P_IP): | |
6510 | opts[1] |= TD1_IPv4_CS; | |
6511 | ip_protocol = ip_hdr(skb)->protocol; | |
6512 | break; | |
6513 | ||
6514 | case htons(ETH_P_IPV6): | |
6515 | opts[1] |= TD1_IPv6_CS; | |
6516 | ip_protocol = ipv6_hdr(skb)->nexthdr; | |
6517 | break; | |
6518 | ||
6519 | default: | |
6520 | ip_protocol = IPPROTO_RAW; | |
6521 | break; | |
6522 | } | |
6523 | ||
6524 | if (ip_protocol == IPPROTO_TCP) | |
6525 | opts[1] |= TD1_TCP_CS; | |
6526 | else if (ip_protocol == IPPROTO_UDP) | |
6527 | opts[1] |= TD1_UDP_CS; | |
2b7b4318 FR |
6528 | else |
6529 | WARN_ON_ONCE(1); | |
e974604b | 6530 | |
6531 | opts[1] |= transport_offset << TCPHO_SHIFT; | |
b423e9ae | 6532 | } else { |
6533 | if (unlikely(rtl_test_hw_pad_bug(tp, skb))) | |
6534 | return rtl_skb_pad(skb); | |
1da177e4 | 6535 | } |
5888d3fc | 6536 | |
b423e9ae | 6537 | return true; |
1da177e4 LT |
6538 | } |
6539 | ||
61357325 SH |
6540 | static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, |
6541 | struct net_device *dev) | |
1da177e4 LT |
6542 | { |
6543 | struct rtl8169_private *tp = netdev_priv(dev); | |
3eafe507 | 6544 | unsigned int entry = tp->cur_tx % NUM_TX_DESC; |
1da177e4 LT |
6545 | struct TxDesc *txd = tp->TxDescArray + entry; |
6546 | void __iomem *ioaddr = tp->mmio_addr; | |
48addcc9 | 6547 | struct device *d = &tp->pci_dev->dev; |
1da177e4 LT |
6548 | dma_addr_t mapping; |
6549 | u32 status, len; | |
2b7b4318 | 6550 | u32 opts[2]; |
3eafe507 | 6551 | int frags; |
5b0384f4 | 6552 | |
477206a0 | 6553 | if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) { |
bf82c189 | 6554 | netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n"); |
3eafe507 | 6555 | goto err_stop_0; |
1da177e4 LT |
6556 | } |
6557 | ||
6558 | if (unlikely(le32_to_cpu(txd->opts1) & DescOwn)) | |
3eafe507 SG |
6559 | goto err_stop_0; |
6560 | ||
b423e9ae | 6561 | opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb)); |
6562 | opts[0] = DescOwn; | |
6563 | ||
e974604b | 6564 | if (!tp->tso_csum(tp, skb, opts)) { |
6565 | r8169_csum_workaround(tp, skb); | |
6566 | return NETDEV_TX_OK; | |
6567 | } | |
b423e9ae | 6568 | |
3eafe507 | 6569 | len = skb_headlen(skb); |
48addcc9 | 6570 | mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE); |
d827d86b SG |
6571 | if (unlikely(dma_mapping_error(d, mapping))) { |
6572 | if (net_ratelimit()) | |
6573 | netif_err(tp, drv, dev, "Failed to map TX DMA!\n"); | |
3eafe507 | 6574 | goto err_dma_0; |
d827d86b | 6575 | } |
3eafe507 SG |
6576 | |
6577 | tp->tx_skb[entry].len = len; | |
6578 | txd->addr = cpu_to_le64(mapping); | |
1da177e4 | 6579 | |
2b7b4318 | 6580 | frags = rtl8169_xmit_frags(tp, skb, opts); |
3eafe507 SG |
6581 | if (frags < 0) |
6582 | goto err_dma_1; | |
6583 | else if (frags) | |
2b7b4318 | 6584 | opts[0] |= FirstFrag; |
3eafe507 | 6585 | else { |
2b7b4318 | 6586 | opts[0] |= FirstFrag | LastFrag; |
1da177e4 LT |
6587 | tp->tx_skb[entry].skb = skb; |
6588 | } | |
6589 | ||
2b7b4318 FR |
6590 | txd->opts2 = cpu_to_le32(opts[1]); |
6591 | ||
5047fb5d RC |
6592 | skb_tx_timestamp(skb); |
6593 | ||
1da177e4 LT |
6594 | wmb(); |
6595 | ||
cecb5fd7 | 6596 | /* Anti gcc 2.95.3 bugware (sic) */ |
2b7b4318 | 6597 | status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC)); |
1da177e4 LT |
6598 | txd->opts1 = cpu_to_le32(status); |
6599 | ||
1da177e4 LT |
6600 | tp->cur_tx += frags + 1; |
6601 | ||
4c020a96 | 6602 | wmb(); |
1da177e4 | 6603 | |
cecb5fd7 | 6604 | RTL_W8(TxPoll, NPQ); |
1da177e4 | 6605 | |
da78dbff FR |
6606 | mmiowb(); |
6607 | ||
477206a0 | 6608 | if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) { |
ae1f23fb FR |
6609 | /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must |
6610 | * not miss a ring update when it notices a stopped queue. | |
6611 | */ | |
6612 | smp_wmb(); | |
1da177e4 | 6613 | netif_stop_queue(dev); |
ae1f23fb FR |
6614 | /* Sync with rtl_tx: |
6615 | * - publish queue status and cur_tx ring index (write barrier) | |
6616 | * - refresh dirty_tx ring index (read barrier). | |
6617 | * May the current thread have a pessimistic view of the ring | |
6618 | * status and forget to wake up queue, a racing rtl_tx thread | |
6619 | * can't. | |
6620 | */ | |
1e874e04 | 6621 | smp_mb(); |
477206a0 | 6622 | if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) |
1da177e4 LT |
6623 | netif_wake_queue(dev); |
6624 | } | |
6625 | ||
61357325 | 6626 | return NETDEV_TX_OK; |
1da177e4 | 6627 | |
3eafe507 | 6628 | err_dma_1: |
48addcc9 | 6629 | rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd); |
3eafe507 | 6630 | err_dma_0: |
989c9ba1 | 6631 | dev_kfree_skb_any(skb); |
3eafe507 SG |
6632 | dev->stats.tx_dropped++; |
6633 | return NETDEV_TX_OK; | |
6634 | ||
6635 | err_stop_0: | |
1da177e4 | 6636 | netif_stop_queue(dev); |
cebf8cc7 | 6637 | dev->stats.tx_dropped++; |
61357325 | 6638 | return NETDEV_TX_BUSY; |
1da177e4 LT |
6639 | } |
6640 | ||
6641 | static void rtl8169_pcierr_interrupt(struct net_device *dev) | |
6642 | { | |
6643 | struct rtl8169_private *tp = netdev_priv(dev); | |
6644 | struct pci_dev *pdev = tp->pci_dev; | |
1da177e4 LT |
6645 | u16 pci_status, pci_cmd; |
6646 | ||
6647 | pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); | |
6648 | pci_read_config_word(pdev, PCI_STATUS, &pci_status); | |
6649 | ||
bf82c189 JP |
6650 | netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n", |
6651 | pci_cmd, pci_status); | |
1da177e4 LT |
6652 | |
6653 | /* | |
6654 | * The recovery sequence below admits a very elaborated explanation: | |
6655 | * - it seems to work; | |
d03902b8 FR |
6656 | * - I did not see what else could be done; |
6657 | * - it makes iop3xx happy. | |
1da177e4 LT |
6658 | * |
6659 | * Feel free to adjust to your needs. | |
6660 | */ | |
a27993f3 | 6661 | if (pdev->broken_parity_status) |
d03902b8 FR |
6662 | pci_cmd &= ~PCI_COMMAND_PARITY; |
6663 | else | |
6664 | pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY; | |
6665 | ||
6666 | pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); | |
1da177e4 LT |
6667 | |
6668 | pci_write_config_word(pdev, PCI_STATUS, | |
6669 | pci_status & (PCI_STATUS_DETECTED_PARITY | | |
6670 | PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT | | |
6671 | PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT)); | |
6672 | ||
6673 | /* The infamous DAC f*ckup only happens at boot time */ | |
9fba0812 | 6674 | if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) { |
e6de30d6 | 6675 | void __iomem *ioaddr = tp->mmio_addr; |
6676 | ||
bf82c189 | 6677 | netif_info(tp, intr, dev, "disabling PCI DAC\n"); |
1da177e4 LT |
6678 | tp->cp_cmd &= ~PCIDAC; |
6679 | RTL_W16(CPlusCmd, tp->cp_cmd); | |
6680 | dev->features &= ~NETIF_F_HIGHDMA; | |
1da177e4 LT |
6681 | } |
6682 | ||
e6de30d6 | 6683 | rtl8169_hw_reset(tp); |
d03902b8 | 6684 | |
98ddf986 | 6685 | rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); |
1da177e4 LT |
6686 | } |
6687 | ||
da78dbff | 6688 | static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp) |
1da177e4 LT |
6689 | { |
6690 | unsigned int dirty_tx, tx_left; | |
6691 | ||
1da177e4 LT |
6692 | dirty_tx = tp->dirty_tx; |
6693 | smp_rmb(); | |
6694 | tx_left = tp->cur_tx - dirty_tx; | |
6695 | ||
6696 | while (tx_left > 0) { | |
6697 | unsigned int entry = dirty_tx % NUM_TX_DESC; | |
6698 | struct ring_info *tx_skb = tp->tx_skb + entry; | |
1da177e4 LT |
6699 | u32 status; |
6700 | ||
6701 | rmb(); | |
6702 | status = le32_to_cpu(tp->TxDescArray[entry].opts1); | |
6703 | if (status & DescOwn) | |
6704 | break; | |
6705 | ||
48addcc9 SG |
6706 | rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb, |
6707 | tp->TxDescArray + entry); | |
1da177e4 | 6708 | if (status & LastFrag) { |
17bcb684 FR |
6709 | u64_stats_update_begin(&tp->tx_stats.syncp); |
6710 | tp->tx_stats.packets++; | |
6711 | tp->tx_stats.bytes += tx_skb->skb->len; | |
6712 | u64_stats_update_end(&tp->tx_stats.syncp); | |
989c9ba1 | 6713 | dev_kfree_skb_any(tx_skb->skb); |
1da177e4 LT |
6714 | tx_skb->skb = NULL; |
6715 | } | |
6716 | dirty_tx++; | |
6717 | tx_left--; | |
6718 | } | |
6719 | ||
6720 | if (tp->dirty_tx != dirty_tx) { | |
6721 | tp->dirty_tx = dirty_tx; | |
ae1f23fb FR |
6722 | /* Sync with rtl8169_start_xmit: |
6723 | * - publish dirty_tx ring index (write barrier) | |
6724 | * - refresh cur_tx ring index and queue status (read barrier) | |
6725 | * May the current thread miss the stopped queue condition, | |
6726 | * a racing xmit thread can only have a right view of the | |
6727 | * ring status. | |
6728 | */ | |
1e874e04 | 6729 | smp_mb(); |
1da177e4 | 6730 | if (netif_queue_stopped(dev) && |
477206a0 | 6731 | TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) { |
1da177e4 LT |
6732 | netif_wake_queue(dev); |
6733 | } | |
d78ae2dc FR |
6734 | /* |
6735 | * 8168 hack: TxPoll requests are lost when the Tx packets are | |
6736 | * too close. Let's kick an extra TxPoll request when a burst | |
6737 | * of start_xmit activity is detected (if it is not detected, | |
6738 | * it is slow enough). -- FR | |
6739 | */ | |
da78dbff FR |
6740 | if (tp->cur_tx != dirty_tx) { |
6741 | void __iomem *ioaddr = tp->mmio_addr; | |
6742 | ||
d78ae2dc | 6743 | RTL_W8(TxPoll, NPQ); |
da78dbff | 6744 | } |
1da177e4 LT |
6745 | } |
6746 | } | |
6747 | ||
126fa4b9 FR |
6748 | static inline int rtl8169_fragmented_frame(u32 status) |
6749 | { | |
6750 | return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); | |
6751 | } | |
6752 | ||
adea1ac7 | 6753 | static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1) |
1da177e4 | 6754 | { |
1da177e4 LT |
6755 | u32 status = opts1 & RxProtoMask; |
6756 | ||
6757 | if (((status == RxProtoTCP) && !(opts1 & TCPFail)) || | |
d5d3ebe3 | 6758 | ((status == RxProtoUDP) && !(opts1 & UDPFail))) |
1da177e4 LT |
6759 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
6760 | else | |
bc8acf2c | 6761 | skb_checksum_none_assert(skb); |
1da177e4 LT |
6762 | } |
6763 | ||
6f0333b8 ED |
6764 | static struct sk_buff *rtl8169_try_rx_copy(void *data, |
6765 | struct rtl8169_private *tp, | |
6766 | int pkt_size, | |
6767 | dma_addr_t addr) | |
1da177e4 | 6768 | { |
b449655f | 6769 | struct sk_buff *skb; |
48addcc9 | 6770 | struct device *d = &tp->pci_dev->dev; |
b449655f | 6771 | |
6f0333b8 | 6772 | data = rtl8169_align(data); |
48addcc9 | 6773 | dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE); |
6f0333b8 ED |
6774 | prefetch(data); |
6775 | skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size); | |
6776 | if (skb) | |
6777 | memcpy(skb->data, data, pkt_size); | |
48addcc9 SG |
6778 | dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE); |
6779 | ||
6f0333b8 | 6780 | return skb; |
1da177e4 LT |
6781 | } |
6782 | ||
da78dbff | 6783 | static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget) |
1da177e4 LT |
6784 | { |
6785 | unsigned int cur_rx, rx_left; | |
6f0333b8 | 6786 | unsigned int count; |
1da177e4 | 6787 | |
1da177e4 | 6788 | cur_rx = tp->cur_rx; |
1da177e4 | 6789 | |
9fba0812 | 6790 | for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) { |
1da177e4 | 6791 | unsigned int entry = cur_rx % NUM_RX_DESC; |
126fa4b9 | 6792 | struct RxDesc *desc = tp->RxDescArray + entry; |
1da177e4 LT |
6793 | u32 status; |
6794 | ||
6795 | rmb(); | |
e03f33af | 6796 | status = le32_to_cpu(desc->opts1) & tp->opts1_mask; |
1da177e4 LT |
6797 | |
6798 | if (status & DescOwn) | |
6799 | break; | |
4dcb7d33 | 6800 | if (unlikely(status & RxRES)) { |
bf82c189 JP |
6801 | netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n", |
6802 | status); | |
cebf8cc7 | 6803 | dev->stats.rx_errors++; |
1da177e4 | 6804 | if (status & (RxRWT | RxRUNT)) |
cebf8cc7 | 6805 | dev->stats.rx_length_errors++; |
1da177e4 | 6806 | if (status & RxCRC) |
cebf8cc7 | 6807 | dev->stats.rx_crc_errors++; |
9dccf611 | 6808 | if (status & RxFOVF) { |
da78dbff | 6809 | rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); |
cebf8cc7 | 6810 | dev->stats.rx_fifo_errors++; |
9dccf611 | 6811 | } |
6bbe021d BG |
6812 | if ((status & (RxRUNT | RxCRC)) && |
6813 | !(status & (RxRWT | RxFOVF)) && | |
6814 | (dev->features & NETIF_F_RXALL)) | |
6815 | goto process_pkt; | |
1da177e4 | 6816 | } else { |
6f0333b8 | 6817 | struct sk_buff *skb; |
6bbe021d BG |
6818 | dma_addr_t addr; |
6819 | int pkt_size; | |
6820 | ||
6821 | process_pkt: | |
6822 | addr = le64_to_cpu(desc->addr); | |
79d0c1d2 BG |
6823 | if (likely(!(dev->features & NETIF_F_RXFCS))) |
6824 | pkt_size = (status & 0x00003fff) - 4; | |
6825 | else | |
6826 | pkt_size = status & 0x00003fff; | |
1da177e4 | 6827 | |
126fa4b9 FR |
6828 | /* |
6829 | * The driver does not support incoming fragmented | |
6830 | * frames. They are seen as a symptom of over-mtu | |
6831 | * sized frames. | |
6832 | */ | |
6833 | if (unlikely(rtl8169_fragmented_frame(status))) { | |
cebf8cc7 FR |
6834 | dev->stats.rx_dropped++; |
6835 | dev->stats.rx_length_errors++; | |
ce11ff5e | 6836 | goto release_descriptor; |
126fa4b9 FR |
6837 | } |
6838 | ||
6f0333b8 ED |
6839 | skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry], |
6840 | tp, pkt_size, addr); | |
6f0333b8 ED |
6841 | if (!skb) { |
6842 | dev->stats.rx_dropped++; | |
ce11ff5e | 6843 | goto release_descriptor; |
1da177e4 LT |
6844 | } |
6845 | ||
adea1ac7 | 6846 | rtl8169_rx_csum(skb, status); |
1da177e4 LT |
6847 | skb_put(skb, pkt_size); |
6848 | skb->protocol = eth_type_trans(skb, dev); | |
6849 | ||
7a8fc77b FR |
6850 | rtl8169_rx_vlan_tag(desc, skb); |
6851 | ||
56de414c | 6852 | napi_gro_receive(&tp->napi, skb); |
1da177e4 | 6853 | |
8027aa24 JW |
6854 | u64_stats_update_begin(&tp->rx_stats.syncp); |
6855 | tp->rx_stats.packets++; | |
6856 | tp->rx_stats.bytes += pkt_size; | |
6857 | u64_stats_update_end(&tp->rx_stats.syncp); | |
1da177e4 | 6858 | } |
ce11ff5e | 6859 | release_descriptor: |
6860 | desc->opts2 = 0; | |
6861 | wmb(); | |
6862 | rtl8169_mark_to_asic(desc, rx_buf_sz); | |
1da177e4 LT |
6863 | } |
6864 | ||
6865 | count = cur_rx - tp->cur_rx; | |
6866 | tp->cur_rx = cur_rx; | |
6867 | ||
1da177e4 LT |
6868 | return count; |
6869 | } | |
6870 | ||
07d3f51f | 6871 | static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) |
1da177e4 | 6872 | { |
07d3f51f | 6873 | struct net_device *dev = dev_instance; |
1da177e4 | 6874 | struct rtl8169_private *tp = netdev_priv(dev); |
1da177e4 | 6875 | int handled = 0; |
9085cdfa | 6876 | u16 status; |
1da177e4 | 6877 | |
9085cdfa | 6878 | status = rtl_get_events(tp); |
da78dbff FR |
6879 | if (status && status != 0xffff) { |
6880 | status &= RTL_EVENT_NAPI | tp->event_slow; | |
6881 | if (status) { | |
6882 | handled = 1; | |
1da177e4 | 6883 | |
da78dbff FR |
6884 | rtl_irq_disable(tp); |
6885 | napi_schedule(&tp->napi); | |
f11a377b | 6886 | } |
da78dbff FR |
6887 | } |
6888 | return IRQ_RETVAL(handled); | |
6889 | } | |
1da177e4 | 6890 | |
da78dbff FR |
6891 | /* |
6892 | * Workqueue context. | |
6893 | */ | |
6894 | static void rtl_slow_event_work(struct rtl8169_private *tp) | |
6895 | { | |
6896 | struct net_device *dev = tp->dev; | |
6897 | u16 status; | |
6898 | ||
6899 | status = rtl_get_events(tp) & tp->event_slow; | |
6900 | rtl_ack_events(tp, status); | |
1da177e4 | 6901 | |
da78dbff FR |
6902 | if (unlikely(status & RxFIFOOver)) { |
6903 | switch (tp->mac_version) { | |
6904 | /* Work around for rx fifo overflow */ | |
6905 | case RTL_GIGA_MAC_VER_11: | |
6906 | netif_stop_queue(dev); | |
934714d0 FR |
6907 | /* XXX - Hack alert. See rtl_task(). */ |
6908 | set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags); | |
da78dbff | 6909 | default: |
f11a377b DD |
6910 | break; |
6911 | } | |
da78dbff | 6912 | } |
1da177e4 | 6913 | |
da78dbff FR |
6914 | if (unlikely(status & SYSErr)) |
6915 | rtl8169_pcierr_interrupt(dev); | |
0e485150 | 6916 | |
da78dbff FR |
6917 | if (status & LinkChg) |
6918 | __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true); | |
1da177e4 | 6919 | |
7dbb4918 | 6920 | rtl_irq_enable_all(tp); |
1da177e4 LT |
6921 | } |
6922 | ||
4422bcd4 FR |
6923 | static void rtl_task(struct work_struct *work) |
6924 | { | |
da78dbff FR |
6925 | static const struct { |
6926 | int bitnr; | |
6927 | void (*action)(struct rtl8169_private *); | |
6928 | } rtl_work[] = { | |
934714d0 | 6929 | /* XXX - keep rtl_slow_event_work() as first element. */ |
da78dbff FR |
6930 | { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work }, |
6931 | { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work }, | |
6932 | { RTL_FLAG_TASK_PHY_PENDING, rtl_phy_work } | |
6933 | }; | |
4422bcd4 FR |
6934 | struct rtl8169_private *tp = |
6935 | container_of(work, struct rtl8169_private, wk.work); | |
da78dbff FR |
6936 | struct net_device *dev = tp->dev; |
6937 | int i; | |
6938 | ||
6939 | rtl_lock_work(tp); | |
6940 | ||
6c4a70c5 FR |
6941 | if (!netif_running(dev) || |
6942 | !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags)) | |
da78dbff FR |
6943 | goto out_unlock; |
6944 | ||
6945 | for (i = 0; i < ARRAY_SIZE(rtl_work); i++) { | |
6946 | bool pending; | |
6947 | ||
da78dbff | 6948 | pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags); |
da78dbff FR |
6949 | if (pending) |
6950 | rtl_work[i].action(tp); | |
6951 | } | |
4422bcd4 | 6952 | |
da78dbff FR |
6953 | out_unlock: |
6954 | rtl_unlock_work(tp); | |
4422bcd4 FR |
6955 | } |
6956 | ||
bea3348e | 6957 | static int rtl8169_poll(struct napi_struct *napi, int budget) |
1da177e4 | 6958 | { |
bea3348e SH |
6959 | struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); |
6960 | struct net_device *dev = tp->dev; | |
da78dbff FR |
6961 | u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow; |
6962 | int work_done= 0; | |
6963 | u16 status; | |
6964 | ||
6965 | status = rtl_get_events(tp); | |
6966 | rtl_ack_events(tp, status & ~tp->event_slow); | |
6967 | ||
6968 | if (status & RTL_EVENT_NAPI_RX) | |
6969 | work_done = rtl_rx(dev, tp, (u32) budget); | |
6970 | ||
6971 | if (status & RTL_EVENT_NAPI_TX) | |
6972 | rtl_tx(dev, tp); | |
1da177e4 | 6973 | |
da78dbff FR |
6974 | if (status & tp->event_slow) { |
6975 | enable_mask &= ~tp->event_slow; | |
6976 | ||
6977 | rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING); | |
6978 | } | |
1da177e4 | 6979 | |
bea3348e | 6980 | if (work_done < budget) { |
288379f0 | 6981 | napi_complete(napi); |
f11a377b | 6982 | |
da78dbff FR |
6983 | rtl_irq_enable(tp, enable_mask); |
6984 | mmiowb(); | |
1da177e4 LT |
6985 | } |
6986 | ||
bea3348e | 6987 | return work_done; |
1da177e4 | 6988 | } |
1da177e4 | 6989 | |
523a6094 FR |
6990 | static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr) |
6991 | { | |
6992 | struct rtl8169_private *tp = netdev_priv(dev); | |
6993 | ||
6994 | if (tp->mac_version > RTL_GIGA_MAC_VER_06) | |
6995 | return; | |
6996 | ||
6997 | dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff); | |
6998 | RTL_W32(RxMissed, 0); | |
6999 | } | |
7000 | ||
1da177e4 LT |
7001 | static void rtl8169_down(struct net_device *dev) |
7002 | { | |
7003 | struct rtl8169_private *tp = netdev_priv(dev); | |
7004 | void __iomem *ioaddr = tp->mmio_addr; | |
1da177e4 | 7005 | |
4876cc1e | 7006 | del_timer_sync(&tp->timer); |
1da177e4 | 7007 | |
93dd79e8 | 7008 | napi_disable(&tp->napi); |
da78dbff | 7009 | netif_stop_queue(dev); |
1da177e4 | 7010 | |
92fc43b4 | 7011 | rtl8169_hw_reset(tp); |
323bb685 SG |
7012 | /* |
7013 | * At this point device interrupts can not be enabled in any function, | |
209e5ac8 FR |
7014 | * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task) |
7015 | * and napi is disabled (rtl8169_poll). | |
323bb685 | 7016 | */ |
523a6094 | 7017 | rtl8169_rx_missed(dev, ioaddr); |
1da177e4 | 7018 | |
1da177e4 | 7019 | /* Give a racing hard_start_xmit a few cycles to complete. */ |
da78dbff | 7020 | synchronize_sched(); |
1da177e4 | 7021 | |
1da177e4 LT |
7022 | rtl8169_tx_clear(tp); |
7023 | ||
7024 | rtl8169_rx_clear(tp); | |
065c27c1 | 7025 | |
7026 | rtl_pll_power_down(tp); | |
1da177e4 LT |
7027 | } |
7028 | ||
7029 | static int rtl8169_close(struct net_device *dev) | |
7030 | { | |
7031 | struct rtl8169_private *tp = netdev_priv(dev); | |
7032 | struct pci_dev *pdev = tp->pci_dev; | |
7033 | ||
e1759441 RW |
7034 | pm_runtime_get_sync(&pdev->dev); |
7035 | ||
cecb5fd7 | 7036 | /* Update counters before going down */ |
355423d0 IV |
7037 | rtl8169_update_counters(dev); |
7038 | ||
da78dbff | 7039 | rtl_lock_work(tp); |
6c4a70c5 | 7040 | clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); |
da78dbff | 7041 | |
1da177e4 | 7042 | rtl8169_down(dev); |
da78dbff | 7043 | rtl_unlock_work(tp); |
1da177e4 | 7044 | |
4ea72445 L |
7045 | cancel_work_sync(&tp->wk.work); |
7046 | ||
92a7c4e7 | 7047 | free_irq(pdev->irq, dev); |
1da177e4 | 7048 | |
82553bb6 SG |
7049 | dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, |
7050 | tp->RxPhyAddr); | |
7051 | dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, | |
7052 | tp->TxPhyAddr); | |
1da177e4 LT |
7053 | tp->TxDescArray = NULL; |
7054 | tp->RxDescArray = NULL; | |
7055 | ||
e1759441 RW |
7056 | pm_runtime_put_sync(&pdev->dev); |
7057 | ||
1da177e4 LT |
7058 | return 0; |
7059 | } | |
7060 | ||
dc1c00ce FR |
7061 | #ifdef CONFIG_NET_POLL_CONTROLLER |
7062 | static void rtl8169_netpoll(struct net_device *dev) | |
7063 | { | |
7064 | struct rtl8169_private *tp = netdev_priv(dev); | |
7065 | ||
7066 | rtl8169_interrupt(tp->pci_dev->irq, dev); | |
7067 | } | |
7068 | #endif | |
7069 | ||
df43ac78 FR |
7070 | static int rtl_open(struct net_device *dev) |
7071 | { | |
7072 | struct rtl8169_private *tp = netdev_priv(dev); | |
7073 | void __iomem *ioaddr = tp->mmio_addr; | |
7074 | struct pci_dev *pdev = tp->pci_dev; | |
7075 | int retval = -ENOMEM; | |
7076 | ||
7077 | pm_runtime_get_sync(&pdev->dev); | |
7078 | ||
7079 | /* | |
e75d6606 | 7080 | * Rx and Tx descriptors needs 256 bytes alignment. |
df43ac78 FR |
7081 | * dma_alloc_coherent provides more. |
7082 | */ | |
7083 | tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES, | |
7084 | &tp->TxPhyAddr, GFP_KERNEL); | |
7085 | if (!tp->TxDescArray) | |
7086 | goto err_pm_runtime_put; | |
7087 | ||
7088 | tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES, | |
7089 | &tp->RxPhyAddr, GFP_KERNEL); | |
7090 | if (!tp->RxDescArray) | |
7091 | goto err_free_tx_0; | |
7092 | ||
7093 | retval = rtl8169_init_ring(dev); | |
7094 | if (retval < 0) | |
7095 | goto err_free_rx_1; | |
7096 | ||
7097 | INIT_WORK(&tp->wk.work, rtl_task); | |
7098 | ||
7099 | smp_mb(); | |
7100 | ||
7101 | rtl_request_firmware(tp); | |
7102 | ||
92a7c4e7 | 7103 | retval = request_irq(pdev->irq, rtl8169_interrupt, |
df43ac78 FR |
7104 | (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED, |
7105 | dev->name, dev); | |
7106 | if (retval < 0) | |
7107 | goto err_release_fw_2; | |
7108 | ||
7109 | rtl_lock_work(tp); | |
7110 | ||
7111 | set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); | |
7112 | ||
7113 | napi_enable(&tp->napi); | |
7114 | ||
7115 | rtl8169_init_phy(dev, tp); | |
7116 | ||
7117 | __rtl8169_set_features(dev, dev->features); | |
7118 | ||
7119 | rtl_pll_power_up(tp); | |
7120 | ||
7121 | rtl_hw_start(dev); | |
7122 | ||
7123 | netif_start_queue(dev); | |
7124 | ||
7125 | rtl_unlock_work(tp); | |
7126 | ||
7127 | tp->saved_wolopts = 0; | |
7128 | pm_runtime_put_noidle(&pdev->dev); | |
7129 | ||
7130 | rtl8169_check_link_status(dev, tp, ioaddr); | |
7131 | out: | |
7132 | return retval; | |
7133 | ||
7134 | err_release_fw_2: | |
7135 | rtl_release_firmware(tp); | |
7136 | rtl8169_rx_clear(tp); | |
7137 | err_free_rx_1: | |
7138 | dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, | |
7139 | tp->RxPhyAddr); | |
7140 | tp->RxDescArray = NULL; | |
7141 | err_free_tx_0: | |
7142 | dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, | |
7143 | tp->TxPhyAddr); | |
7144 | tp->TxDescArray = NULL; | |
7145 | err_pm_runtime_put: | |
7146 | pm_runtime_put_noidle(&pdev->dev); | |
7147 | goto out; | |
7148 | } | |
7149 | ||
8027aa24 JW |
7150 | static struct rtnl_link_stats64 * |
7151 | rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) | |
1da177e4 LT |
7152 | { |
7153 | struct rtl8169_private *tp = netdev_priv(dev); | |
7154 | void __iomem *ioaddr = tp->mmio_addr; | |
8027aa24 | 7155 | unsigned int start; |
1da177e4 | 7156 | |
da78dbff | 7157 | if (netif_running(dev)) |
523a6094 | 7158 | rtl8169_rx_missed(dev, ioaddr); |
5b0384f4 | 7159 | |
8027aa24 | 7160 | do { |
57a7744e | 7161 | start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp); |
8027aa24 JW |
7162 | stats->rx_packets = tp->rx_stats.packets; |
7163 | stats->rx_bytes = tp->rx_stats.bytes; | |
57a7744e | 7164 | } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start)); |
8027aa24 JW |
7165 | |
7166 | ||
7167 | do { | |
57a7744e | 7168 | start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp); |
8027aa24 JW |
7169 | stats->tx_packets = tp->tx_stats.packets; |
7170 | stats->tx_bytes = tp->tx_stats.bytes; | |
57a7744e | 7171 | } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start)); |
8027aa24 JW |
7172 | |
7173 | stats->rx_dropped = dev->stats.rx_dropped; | |
7174 | stats->tx_dropped = dev->stats.tx_dropped; | |
7175 | stats->rx_length_errors = dev->stats.rx_length_errors; | |
7176 | stats->rx_errors = dev->stats.rx_errors; | |
7177 | stats->rx_crc_errors = dev->stats.rx_crc_errors; | |
7178 | stats->rx_fifo_errors = dev->stats.rx_fifo_errors; | |
7179 | stats->rx_missed_errors = dev->stats.rx_missed_errors; | |
7180 | ||
7181 | return stats; | |
1da177e4 LT |
7182 | } |
7183 | ||
861ab440 | 7184 | static void rtl8169_net_suspend(struct net_device *dev) |
5d06a99f | 7185 | { |
065c27c1 | 7186 | struct rtl8169_private *tp = netdev_priv(dev); |
7187 | ||
5d06a99f | 7188 | if (!netif_running(dev)) |
861ab440 | 7189 | return; |
5d06a99f FR |
7190 | |
7191 | netif_device_detach(dev); | |
7192 | netif_stop_queue(dev); | |
da78dbff FR |
7193 | |
7194 | rtl_lock_work(tp); | |
7195 | napi_disable(&tp->napi); | |
6c4a70c5 | 7196 | clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); |
da78dbff FR |
7197 | rtl_unlock_work(tp); |
7198 | ||
7199 | rtl_pll_power_down(tp); | |
861ab440 RW |
7200 | } |
7201 | ||
7202 | #ifdef CONFIG_PM | |
7203 | ||
7204 | static int rtl8169_suspend(struct device *device) | |
7205 | { | |
7206 | struct pci_dev *pdev = to_pci_dev(device); | |
7207 | struct net_device *dev = pci_get_drvdata(pdev); | |
5d06a99f | 7208 | |
861ab440 | 7209 | rtl8169_net_suspend(dev); |
1371fa6d | 7210 | |
5d06a99f FR |
7211 | return 0; |
7212 | } | |
7213 | ||
e1759441 RW |
7214 | static void __rtl8169_resume(struct net_device *dev) |
7215 | { | |
065c27c1 | 7216 | struct rtl8169_private *tp = netdev_priv(dev); |
7217 | ||
e1759441 | 7218 | netif_device_attach(dev); |
065c27c1 | 7219 | |
7220 | rtl_pll_power_up(tp); | |
7221 | ||
cff4c162 AS |
7222 | rtl_lock_work(tp); |
7223 | napi_enable(&tp->napi); | |
6c4a70c5 | 7224 | set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); |
cff4c162 | 7225 | rtl_unlock_work(tp); |
da78dbff | 7226 | |
98ddf986 | 7227 | rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); |
e1759441 RW |
7228 | } |
7229 | ||
861ab440 | 7230 | static int rtl8169_resume(struct device *device) |
5d06a99f | 7231 | { |
861ab440 | 7232 | struct pci_dev *pdev = to_pci_dev(device); |
5d06a99f | 7233 | struct net_device *dev = pci_get_drvdata(pdev); |
fccec10b SG |
7234 | struct rtl8169_private *tp = netdev_priv(dev); |
7235 | ||
7236 | rtl8169_init_phy(dev, tp); | |
5d06a99f | 7237 | |
e1759441 RW |
7238 | if (netif_running(dev)) |
7239 | __rtl8169_resume(dev); | |
5d06a99f | 7240 | |
e1759441 RW |
7241 | return 0; |
7242 | } | |
7243 | ||
7244 | static int rtl8169_runtime_suspend(struct device *device) | |
7245 | { | |
7246 | struct pci_dev *pdev = to_pci_dev(device); | |
7247 | struct net_device *dev = pci_get_drvdata(pdev); | |
7248 | struct rtl8169_private *tp = netdev_priv(dev); | |
7249 | ||
7250 | if (!tp->TxDescArray) | |
7251 | return 0; | |
7252 | ||
da78dbff | 7253 | rtl_lock_work(tp); |
e1759441 RW |
7254 | tp->saved_wolopts = __rtl8169_get_wol(tp); |
7255 | __rtl8169_set_wol(tp, WAKE_ANY); | |
da78dbff | 7256 | rtl_unlock_work(tp); |
e1759441 RW |
7257 | |
7258 | rtl8169_net_suspend(dev); | |
7259 | ||
7260 | return 0; | |
7261 | } | |
7262 | ||
7263 | static int rtl8169_runtime_resume(struct device *device) | |
7264 | { | |
7265 | struct pci_dev *pdev = to_pci_dev(device); | |
7266 | struct net_device *dev = pci_get_drvdata(pdev); | |
7267 | struct rtl8169_private *tp = netdev_priv(dev); | |
7268 | ||
7269 | if (!tp->TxDescArray) | |
7270 | return 0; | |
7271 | ||
da78dbff | 7272 | rtl_lock_work(tp); |
e1759441 RW |
7273 | __rtl8169_set_wol(tp, tp->saved_wolopts); |
7274 | tp->saved_wolopts = 0; | |
da78dbff | 7275 | rtl_unlock_work(tp); |
e1759441 | 7276 | |
fccec10b SG |
7277 | rtl8169_init_phy(dev, tp); |
7278 | ||
e1759441 | 7279 | __rtl8169_resume(dev); |
5d06a99f | 7280 | |
5d06a99f FR |
7281 | return 0; |
7282 | } | |
7283 | ||
e1759441 RW |
7284 | static int rtl8169_runtime_idle(struct device *device) |
7285 | { | |
7286 | struct pci_dev *pdev = to_pci_dev(device); | |
7287 | struct net_device *dev = pci_get_drvdata(pdev); | |
7288 | struct rtl8169_private *tp = netdev_priv(dev); | |
7289 | ||
e4fbce74 | 7290 | return tp->TxDescArray ? -EBUSY : 0; |
e1759441 RW |
7291 | } |
7292 | ||
47145210 | 7293 | static const struct dev_pm_ops rtl8169_pm_ops = { |
cecb5fd7 FR |
7294 | .suspend = rtl8169_suspend, |
7295 | .resume = rtl8169_resume, | |
7296 | .freeze = rtl8169_suspend, | |
7297 | .thaw = rtl8169_resume, | |
7298 | .poweroff = rtl8169_suspend, | |
7299 | .restore = rtl8169_resume, | |
7300 | .runtime_suspend = rtl8169_runtime_suspend, | |
7301 | .runtime_resume = rtl8169_runtime_resume, | |
7302 | .runtime_idle = rtl8169_runtime_idle, | |
861ab440 RW |
7303 | }; |
7304 | ||
7305 | #define RTL8169_PM_OPS (&rtl8169_pm_ops) | |
7306 | ||
7307 | #else /* !CONFIG_PM */ | |
7308 | ||
7309 | #define RTL8169_PM_OPS NULL | |
7310 | ||
7311 | #endif /* !CONFIG_PM */ | |
7312 | ||
649b3b8c | 7313 | static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp) |
7314 | { | |
7315 | void __iomem *ioaddr = tp->mmio_addr; | |
7316 | ||
7317 | /* WoL fails with 8168b when the receiver is disabled. */ | |
7318 | switch (tp->mac_version) { | |
7319 | case RTL_GIGA_MAC_VER_11: | |
7320 | case RTL_GIGA_MAC_VER_12: | |
7321 | case RTL_GIGA_MAC_VER_17: | |
7322 | pci_clear_master(tp->pci_dev); | |
7323 | ||
7324 | RTL_W8(ChipCmd, CmdRxEnb); | |
7325 | /* PCI commit */ | |
7326 | RTL_R8(ChipCmd); | |
7327 | break; | |
7328 | default: | |
7329 | break; | |
7330 | } | |
7331 | } | |
7332 | ||
1765f95d FR |
7333 | static void rtl_shutdown(struct pci_dev *pdev) |
7334 | { | |
861ab440 | 7335 | struct net_device *dev = pci_get_drvdata(pdev); |
4bb3f522 | 7336 | struct rtl8169_private *tp = netdev_priv(dev); |
2a15cd2f | 7337 | struct device *d = &pdev->dev; |
7338 | ||
7339 | pm_runtime_get_sync(d); | |
861ab440 RW |
7340 | |
7341 | rtl8169_net_suspend(dev); | |
1765f95d | 7342 | |
cecb5fd7 | 7343 | /* Restore original MAC address */ |
cc098dc7 IV |
7344 | rtl_rar_set(tp, dev->perm_addr); |
7345 | ||
92fc43b4 | 7346 | rtl8169_hw_reset(tp); |
4bb3f522 | 7347 | |
861ab440 | 7348 | if (system_state == SYSTEM_POWER_OFF) { |
649b3b8c | 7349 | if (__rtl8169_get_wol(tp) & WAKE_ANY) { |
7350 | rtl_wol_suspend_quirk(tp); | |
7351 | rtl_wol_shutdown_quirk(tp); | |
ca52efd5 | 7352 | } |
7353 | ||
861ab440 RW |
7354 | pci_wake_from_d3(pdev, true); |
7355 | pci_set_power_state(pdev, PCI_D3hot); | |
7356 | } | |
2a15cd2f | 7357 | |
7358 | pm_runtime_put_noidle(d); | |
861ab440 | 7359 | } |
5d06a99f | 7360 | |
baf63293 | 7361 | static void rtl_remove_one(struct pci_dev *pdev) |
e27566ed FR |
7362 | { |
7363 | struct net_device *dev = pci_get_drvdata(pdev); | |
7364 | struct rtl8169_private *tp = netdev_priv(dev); | |
7365 | ||
7366 | if (tp->mac_version == RTL_GIGA_MAC_VER_27 || | |
7367 | tp->mac_version == RTL_GIGA_MAC_VER_28 || | |
7368 | tp->mac_version == RTL_GIGA_MAC_VER_31) { | |
7369 | rtl8168_driver_stop(tp); | |
7370 | } | |
7371 | ||
ad1be8d3 DN |
7372 | netif_napi_del(&tp->napi); |
7373 | ||
e27566ed FR |
7374 | unregister_netdev(dev); |
7375 | ||
7376 | rtl_release_firmware(tp); | |
7377 | ||
7378 | if (pci_dev_run_wake(pdev)) | |
7379 | pm_runtime_get_noresume(&pdev->dev); | |
7380 | ||
7381 | /* restore original MAC address */ | |
7382 | rtl_rar_set(tp, dev->perm_addr); | |
7383 | ||
7384 | rtl_disable_msi(pdev, tp); | |
7385 | rtl8169_release_board(pdev, dev, tp->mmio_addr); | |
e27566ed FR |
7386 | } |
7387 | ||
fa9c385e | 7388 | static const struct net_device_ops rtl_netdev_ops = { |
df43ac78 | 7389 | .ndo_open = rtl_open, |
fa9c385e FR |
7390 | .ndo_stop = rtl8169_close, |
7391 | .ndo_get_stats64 = rtl8169_get_stats64, | |
7392 | .ndo_start_xmit = rtl8169_start_xmit, | |
7393 | .ndo_tx_timeout = rtl8169_tx_timeout, | |
7394 | .ndo_validate_addr = eth_validate_addr, | |
7395 | .ndo_change_mtu = rtl8169_change_mtu, | |
7396 | .ndo_fix_features = rtl8169_fix_features, | |
7397 | .ndo_set_features = rtl8169_set_features, | |
7398 | .ndo_set_mac_address = rtl_set_mac_address, | |
7399 | .ndo_do_ioctl = rtl8169_ioctl, | |
7400 | .ndo_set_rx_mode = rtl_set_rx_mode, | |
7401 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
7402 | .ndo_poll_controller = rtl8169_netpoll, | |
7403 | #endif | |
7404 | ||
7405 | }; | |
7406 | ||
31fa8b18 FR |
7407 | static const struct rtl_cfg_info { |
7408 | void (*hw_start)(struct net_device *); | |
7409 | unsigned int region; | |
7410 | unsigned int align; | |
7411 | u16 event_slow; | |
7412 | unsigned features; | |
7413 | u8 default_ver; | |
7414 | } rtl_cfg_infos [] = { | |
7415 | [RTL_CFG_0] = { | |
7416 | .hw_start = rtl_hw_start_8169, | |
7417 | .region = 1, | |
7418 | .align = 0, | |
7419 | .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver, | |
7420 | .features = RTL_FEATURE_GMII, | |
7421 | .default_ver = RTL_GIGA_MAC_VER_01, | |
7422 | }, | |
7423 | [RTL_CFG_1] = { | |
7424 | .hw_start = rtl_hw_start_8168, | |
7425 | .region = 2, | |
7426 | .align = 8, | |
7427 | .event_slow = SYSErr | LinkChg | RxOverflow, | |
7428 | .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI, | |
7429 | .default_ver = RTL_GIGA_MAC_VER_11, | |
7430 | }, | |
7431 | [RTL_CFG_2] = { | |
7432 | .hw_start = rtl_hw_start_8101, | |
7433 | .region = 2, | |
7434 | .align = 8, | |
7435 | .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver | | |
7436 | PCSTimeout, | |
7437 | .features = RTL_FEATURE_MSI, | |
7438 | .default_ver = RTL_GIGA_MAC_VER_13, | |
7439 | } | |
7440 | }; | |
7441 | ||
7442 | /* Cfg9346_Unlock assumed. */ | |
7443 | static unsigned rtl_try_msi(struct rtl8169_private *tp, | |
7444 | const struct rtl_cfg_info *cfg) | |
7445 | { | |
7446 | void __iomem *ioaddr = tp->mmio_addr; | |
7447 | unsigned msi = 0; | |
7448 | u8 cfg2; | |
7449 | ||
7450 | cfg2 = RTL_R8(Config2) & ~MSIEnable; | |
7451 | if (cfg->features & RTL_FEATURE_MSI) { | |
7452 | if (pci_enable_msi(tp->pci_dev)) { | |
7453 | netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n"); | |
7454 | } else { | |
7455 | cfg2 |= MSIEnable; | |
7456 | msi = RTL_FEATURE_MSI; | |
7457 | } | |
7458 | } | |
7459 | if (tp->mac_version <= RTL_GIGA_MAC_VER_06) | |
7460 | RTL_W8(Config2, cfg2); | |
7461 | return msi; | |
7462 | } | |
7463 | ||
c558386b HW |
7464 | DECLARE_RTL_COND(rtl_link_list_ready_cond) |
7465 | { | |
7466 | void __iomem *ioaddr = tp->mmio_addr; | |
7467 | ||
7468 | return RTL_R8(MCU) & LINK_LIST_RDY; | |
7469 | } | |
7470 | ||
7471 | DECLARE_RTL_COND(rtl_rxtx_empty_cond) | |
7472 | { | |
7473 | void __iomem *ioaddr = tp->mmio_addr; | |
7474 | ||
7475 | return (RTL_R8(MCU) & RXTX_EMPTY) == RXTX_EMPTY; | |
7476 | } | |
7477 | ||
baf63293 | 7478 | static void rtl_hw_init_8168g(struct rtl8169_private *tp) |
c558386b HW |
7479 | { |
7480 | void __iomem *ioaddr = tp->mmio_addr; | |
7481 | u32 data; | |
7482 | ||
7483 | tp->ocp_base = OCP_STD_PHY_BASE; | |
7484 | ||
7485 | RTL_W32(MISC, RTL_R32(MISC) | RXDV_GATED_EN); | |
7486 | ||
7487 | if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42)) | |
7488 | return; | |
7489 | ||
7490 | if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42)) | |
7491 | return; | |
7492 | ||
7493 | RTL_W8(ChipCmd, RTL_R8(ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); | |
7494 | msleep(1); | |
7495 | RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB); | |
7496 | ||
5f8bcce9 | 7497 | data = r8168_mac_ocp_read(tp, 0xe8de); |
c558386b HW |
7498 | data &= ~(1 << 14); |
7499 | r8168_mac_ocp_write(tp, 0xe8de, data); | |
7500 | ||
7501 | if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42)) | |
7502 | return; | |
7503 | ||
5f8bcce9 | 7504 | data = r8168_mac_ocp_read(tp, 0xe8de); |
c558386b HW |
7505 | data |= (1 << 15); |
7506 | r8168_mac_ocp_write(tp, 0xe8de, data); | |
7507 | ||
7508 | if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42)) | |
7509 | return; | |
7510 | } | |
7511 | ||
baf63293 | 7512 | static void rtl_hw_initialize(struct rtl8169_private *tp) |
c558386b HW |
7513 | { |
7514 | switch (tp->mac_version) { | |
7515 | case RTL_GIGA_MAC_VER_40: | |
7516 | case RTL_GIGA_MAC_VER_41: | |
57538c4a | 7517 | case RTL_GIGA_MAC_VER_42: |
58152cd4 | 7518 | case RTL_GIGA_MAC_VER_43: |
45dd95c4 | 7519 | case RTL_GIGA_MAC_VER_44: |
6e1d0b89 CHL |
7520 | case RTL_GIGA_MAC_VER_45: |
7521 | case RTL_GIGA_MAC_VER_46: | |
7522 | case RTL_GIGA_MAC_VER_47: | |
7523 | case RTL_GIGA_MAC_VER_48: | |
c558386b HW |
7524 | rtl_hw_init_8168g(tp); |
7525 | break; | |
7526 | ||
7527 | default: | |
7528 | break; | |
7529 | } | |
7530 | } | |
7531 | ||
baf63293 | 7532 | static int |
3b6cf25d FR |
7533 | rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
7534 | { | |
7535 | const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data; | |
7536 | const unsigned int region = cfg->region; | |
7537 | struct rtl8169_private *tp; | |
7538 | struct mii_if_info *mii; | |
7539 | struct net_device *dev; | |
7540 | void __iomem *ioaddr; | |
7541 | int chipset, i; | |
7542 | int rc; | |
7543 | ||
7544 | if (netif_msg_drv(&debug)) { | |
7545 | printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n", | |
7546 | MODULENAME, RTL8169_VERSION); | |
7547 | } | |
7548 | ||
7549 | dev = alloc_etherdev(sizeof (*tp)); | |
7550 | if (!dev) { | |
7551 | rc = -ENOMEM; | |
7552 | goto out; | |
7553 | } | |
7554 | ||
7555 | SET_NETDEV_DEV(dev, &pdev->dev); | |
fa9c385e | 7556 | dev->netdev_ops = &rtl_netdev_ops; |
3b6cf25d FR |
7557 | tp = netdev_priv(dev); |
7558 | tp->dev = dev; | |
7559 | tp->pci_dev = pdev; | |
7560 | tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT); | |
7561 | ||
7562 | mii = &tp->mii; | |
7563 | mii->dev = dev; | |
7564 | mii->mdio_read = rtl_mdio_read; | |
7565 | mii->mdio_write = rtl_mdio_write; | |
7566 | mii->phy_id_mask = 0x1f; | |
7567 | mii->reg_num_mask = 0x1f; | |
7568 | mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII); | |
7569 | ||
7570 | /* disable ASPM completely as that cause random device stop working | |
7571 | * problems as well as full system hangs for some PCIe devices users */ | |
7572 | pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 | | |
7573 | PCIE_LINK_STATE_CLKPM); | |
7574 | ||
7575 | /* enable device (incl. PCI PM wakeup and hotplug setup) */ | |
7576 | rc = pci_enable_device(pdev); | |
7577 | if (rc < 0) { | |
7578 | netif_err(tp, probe, dev, "enable failure\n"); | |
7579 | goto err_out_free_dev_1; | |
7580 | } | |
7581 | ||
7582 | if (pci_set_mwi(pdev) < 0) | |
7583 | netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n"); | |
7584 | ||
7585 | /* make sure PCI base addr 1 is MMIO */ | |
7586 | if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) { | |
7587 | netif_err(tp, probe, dev, | |
7588 | "region #%d not an MMIO resource, aborting\n", | |
7589 | region); | |
7590 | rc = -ENODEV; | |
7591 | goto err_out_mwi_2; | |
7592 | } | |
7593 | ||
7594 | /* check for weird/broken PCI region reporting */ | |
7595 | if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) { | |
7596 | netif_err(tp, probe, dev, | |
7597 | "Invalid PCI region size(s), aborting\n"); | |
7598 | rc = -ENODEV; | |
7599 | goto err_out_mwi_2; | |
7600 | } | |
7601 | ||
7602 | rc = pci_request_regions(pdev, MODULENAME); | |
7603 | if (rc < 0) { | |
7604 | netif_err(tp, probe, dev, "could not request regions\n"); | |
7605 | goto err_out_mwi_2; | |
7606 | } | |
7607 | ||
7608 | tp->cp_cmd = RxChkSum; | |
7609 | ||
7610 | if ((sizeof(dma_addr_t) > 4) && | |
7611 | !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) { | |
7612 | tp->cp_cmd |= PCIDAC; | |
7613 | dev->features |= NETIF_F_HIGHDMA; | |
7614 | } else { | |
7615 | rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); | |
7616 | if (rc < 0) { | |
7617 | netif_err(tp, probe, dev, "DMA configuration failed\n"); | |
7618 | goto err_out_free_res_3; | |
7619 | } | |
7620 | } | |
7621 | ||
7622 | /* ioremap MMIO region */ | |
7623 | ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE); | |
7624 | if (!ioaddr) { | |
7625 | netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n"); | |
7626 | rc = -EIO; | |
7627 | goto err_out_free_res_3; | |
7628 | } | |
7629 | tp->mmio_addr = ioaddr; | |
7630 | ||
7631 | if (!pci_is_pcie(pdev)) | |
7632 | netif_info(tp, probe, dev, "not PCI Express\n"); | |
7633 | ||
7634 | /* Identify chip attached to board */ | |
7635 | rtl8169_get_mac_version(tp, dev, cfg->default_ver); | |
7636 | ||
7637 | rtl_init_rxcfg(tp); | |
7638 | ||
7639 | rtl_irq_disable(tp); | |
7640 | ||
c558386b HW |
7641 | rtl_hw_initialize(tp); |
7642 | ||
3b6cf25d FR |
7643 | rtl_hw_reset(tp); |
7644 | ||
7645 | rtl_ack_events(tp, 0xffff); | |
7646 | ||
7647 | pci_set_master(pdev); | |
7648 | ||
7649 | /* | |
7650 | * Pretend we are using VLANs; This bypasses a nasty bug where | |
7651 | * Interrupts stop flowing on high load on 8110SCd controllers. | |
7652 | */ | |
7653 | if (tp->mac_version == RTL_GIGA_MAC_VER_05) | |
7654 | tp->cp_cmd |= RxVlan; | |
7655 | ||
7656 | rtl_init_mdio_ops(tp); | |
7657 | rtl_init_pll_power_ops(tp); | |
7658 | rtl_init_jumbo_ops(tp); | |
beb1fe18 | 7659 | rtl_init_csi_ops(tp); |
3b6cf25d FR |
7660 | |
7661 | rtl8169_print_mac_version(tp); | |
7662 | ||
7663 | chipset = tp->mac_version; | |
7664 | tp->txd_version = rtl_chip_infos[chipset].txd_version; | |
7665 | ||
7666 | RTL_W8(Cfg9346, Cfg9346_Unlock); | |
7667 | RTL_W8(Config1, RTL_R8(Config1) | PMEnable); | |
8f9d5138 | 7668 | RTL_W8(Config5, RTL_R8(Config5) & (BWF | MWF | UWF | LanWake | PMEStatus)); |
6e1d0b89 CHL |
7669 | switch (tp->mac_version) { |
7670 | case RTL_GIGA_MAC_VER_45: | |
7671 | case RTL_GIGA_MAC_VER_46: | |
7672 | if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2) | |
7673 | tp->features |= RTL_FEATURE_WOL; | |
7674 | if ((RTL_R8(Config3) & LinkUp) != 0) | |
7675 | tp->features |= RTL_FEATURE_WOL; | |
7676 | break; | |
7677 | default: | |
7678 | if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0) | |
7679 | tp->features |= RTL_FEATURE_WOL; | |
7680 | break; | |
7681 | } | |
3b6cf25d FR |
7682 | if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0) |
7683 | tp->features |= RTL_FEATURE_WOL; | |
7684 | tp->features |= rtl_try_msi(tp, cfg); | |
7685 | RTL_W8(Cfg9346, Cfg9346_Lock); | |
7686 | ||
7687 | if (rtl_tbi_enabled(tp)) { | |
7688 | tp->set_speed = rtl8169_set_speed_tbi; | |
7689 | tp->get_settings = rtl8169_gset_tbi; | |
7690 | tp->phy_reset_enable = rtl8169_tbi_reset_enable; | |
7691 | tp->phy_reset_pending = rtl8169_tbi_reset_pending; | |
7692 | tp->link_ok = rtl8169_tbi_link_ok; | |
7693 | tp->do_ioctl = rtl_tbi_ioctl; | |
7694 | } else { | |
7695 | tp->set_speed = rtl8169_set_speed_xmii; | |
7696 | tp->get_settings = rtl8169_gset_xmii; | |
7697 | tp->phy_reset_enable = rtl8169_xmii_reset_enable; | |
7698 | tp->phy_reset_pending = rtl8169_xmii_reset_pending; | |
7699 | tp->link_ok = rtl8169_xmii_link_ok; | |
7700 | tp->do_ioctl = rtl_xmii_ioctl; | |
7701 | } | |
7702 | ||
7703 | mutex_init(&tp->wk.mutex); | |
340fea3d KM |
7704 | u64_stats_init(&tp->rx_stats.syncp); |
7705 | u64_stats_init(&tp->tx_stats.syncp); | |
3b6cf25d FR |
7706 | |
7707 | /* Get MAC address */ | |
6e1d0b89 CHL |
7708 | if (tp->mac_version == RTL_GIGA_MAC_VER_45 || |
7709 | tp->mac_version == RTL_GIGA_MAC_VER_46 || | |
7710 | tp->mac_version == RTL_GIGA_MAC_VER_47 || | |
7711 | tp->mac_version == RTL_GIGA_MAC_VER_48) { | |
7712 | u16 mac_addr[3]; | |
7713 | ||
7714 | *(u32 *)&mac_addr[0] = rtl_eri_read(tp, 0xE0, ERIAR_EXGMAC); | |
7715 | *(u16 *)&mac_addr[2] = rtl_eri_read(tp, 0xE4, ERIAR_EXGMAC); | |
7716 | ||
7717 | if (is_valid_ether_addr((u8 *)mac_addr)) | |
7718 | rtl_rar_set(tp, (u8 *)mac_addr); | |
7719 | } | |
3b6cf25d FR |
7720 | for (i = 0; i < ETH_ALEN; i++) |
7721 | dev->dev_addr[i] = RTL_R8(MAC0 + i); | |
3b6cf25d | 7722 | |
7ad24ea4 | 7723 | dev->ethtool_ops = &rtl8169_ethtool_ops; |
3b6cf25d | 7724 | dev->watchdog_timeo = RTL8169_TX_TIMEOUT; |
3b6cf25d FR |
7725 | |
7726 | netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT); | |
7727 | ||
7728 | /* don't enable SG, IP_CSUM and TSO by default - it might not work | |
7729 | * properly for all devices */ | |
7730 | dev->features |= NETIF_F_RXCSUM | | |
f646968f | 7731 | NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; |
3b6cf25d FR |
7732 | |
7733 | dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | | |
f646968f PM |
7734 | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX | |
7735 | NETIF_F_HW_VLAN_CTAG_RX; | |
3b6cf25d FR |
7736 | dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | |
7737 | NETIF_F_HIGHDMA; | |
7738 | ||
7739 | if (tp->mac_version == RTL_GIGA_MAC_VER_05) | |
7740 | /* 8110SCd requires hardware Rx VLAN - disallow toggling */ | |
f646968f | 7741 | dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX; |
3b6cf25d | 7742 | |
5888d3fc | 7743 | if (tp->txd_version == RTL_TD_0) |
7744 | tp->tso_csum = rtl8169_tso_csum_v1; | |
e974604b | 7745 | else if (tp->txd_version == RTL_TD_1) { |
5888d3fc | 7746 | tp->tso_csum = rtl8169_tso_csum_v2; |
e974604b | 7747 | dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6; |
7748 | } else | |
5888d3fc | 7749 | WARN_ON_ONCE(1); |
7750 | ||
3b6cf25d FR |
7751 | dev->hw_features |= NETIF_F_RXALL; |
7752 | dev->hw_features |= NETIF_F_RXFCS; | |
7753 | ||
7754 | tp->hw_start = cfg->hw_start; | |
7755 | tp->event_slow = cfg->event_slow; | |
7756 | ||
7757 | tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ? | |
7758 | ~(RxBOVF | RxFOVF) : ~0; | |
7759 | ||
7760 | init_timer(&tp->timer); | |
7761 | tp->timer.data = (unsigned long) dev; | |
7762 | tp->timer.function = rtl8169_phy_timer; | |
7763 | ||
7764 | tp->rtl_fw = RTL_FIRMWARE_UNKNOWN; | |
7765 | ||
7766 | rc = register_netdev(dev); | |
7767 | if (rc < 0) | |
7768 | goto err_out_msi_4; | |
7769 | ||
7770 | pci_set_drvdata(pdev, dev); | |
7771 | ||
92a7c4e7 FR |
7772 | netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n", |
7773 | rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr, | |
7774 | (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq); | |
3b6cf25d FR |
7775 | if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) { |
7776 | netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, " | |
7777 | "tx checksumming: %s]\n", | |
7778 | rtl_chip_infos[chipset].jumbo_max, | |
7779 | rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko"); | |
7780 | } | |
7781 | ||
7782 | if (tp->mac_version == RTL_GIGA_MAC_VER_27 || | |
7783 | tp->mac_version == RTL_GIGA_MAC_VER_28 || | |
7784 | tp->mac_version == RTL_GIGA_MAC_VER_31) { | |
7785 | rtl8168_driver_start(tp); | |
7786 | } | |
7787 | ||
7788 | device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL); | |
7789 | ||
7790 | if (pci_dev_run_wake(pdev)) | |
7791 | pm_runtime_put_noidle(&pdev->dev); | |
7792 | ||
7793 | netif_carrier_off(dev); | |
7794 | ||
7795 | out: | |
7796 | return rc; | |
7797 | ||
7798 | err_out_msi_4: | |
ad1be8d3 | 7799 | netif_napi_del(&tp->napi); |
3b6cf25d FR |
7800 | rtl_disable_msi(pdev, tp); |
7801 | iounmap(ioaddr); | |
7802 | err_out_free_res_3: | |
7803 | pci_release_regions(pdev); | |
7804 | err_out_mwi_2: | |
7805 | pci_clear_mwi(pdev); | |
7806 | pci_disable_device(pdev); | |
7807 | err_out_free_dev_1: | |
7808 | free_netdev(dev); | |
7809 | goto out; | |
7810 | } | |
7811 | ||
1da177e4 LT |
7812 | static struct pci_driver rtl8169_pci_driver = { |
7813 | .name = MODULENAME, | |
7814 | .id_table = rtl8169_pci_tbl, | |
3b6cf25d | 7815 | .probe = rtl_init_one, |
baf63293 | 7816 | .remove = rtl_remove_one, |
1765f95d | 7817 | .shutdown = rtl_shutdown, |
861ab440 | 7818 | .driver.pm = RTL8169_PM_OPS, |
1da177e4 LT |
7819 | }; |
7820 | ||
3eeb7da9 | 7821 | module_pci_driver(rtl8169_pci_driver); |