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r8169: factor out IntrMask writes.
[mirror_ubuntu-zesty-kernel.git] / drivers / net / ethernet / realtek / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
a6b7a407 25#include <linux/interrupt.h>
1da177e4 26#include <linux/dma-mapping.h>
e1759441 27#include <linux/pm_runtime.h>
bca03d5f 28#include <linux/firmware.h>
ba04c7c9 29#include <linux/pci-aspm.h>
70c71606 30#include <linux/prefetch.h>
1da177e4 31
99f252b0 32#include <asm/system.h>
1da177e4
LT		 33#include <asm/io.h>
34#include <asm/irq.h>
35
865c652d 36#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 37#define MODULENAME "r8169"
38#define PFX MODULENAME ": "
39
bca03d5f 40#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
41#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
01dc7fec 42#define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
43#define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
70090424 44#define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
c2218925
HW		 45#define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
46#define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
5a5e4443 47#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
bca03d5f 48
1da177e4
LT		 49#ifdef RTL8169_DEBUG
50#define assert(expr) \
5b0384f4
FR		 51 if (!(expr)) { \
52 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
b39d66a8 53 #expr,__FILE__,__func__,__LINE__); \
5b0384f4 54 }
06fa7358
JP		 55#define dprintk(fmt, args...) \
56 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 57#else
58#define assert(expr) do {} while (0)
59#define dprintk(fmt, args...) do {} while (0)
60#endif /* RTL8169_DEBUG */
61
b57b7e5a 62#define R8169_MSG_DEFAULT \
f0e837d9 63 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 64
1da177e4
LT		 65#define TX_BUFFS_AVAIL(tp) \
66 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
67
1da177e4
LT		 68/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
69 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 70static const int multicast_filter_limit = 32;
1da177e4 71
9c14ceaf 72#define MAX_READ_REQUEST_SHIFT 12
1da177e4 73#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
1da177e4
LT		 74#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
75#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
76
77#define R8169_REGS_SIZE 256
78#define R8169_NAPI_WEIGHT 64
79#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
80#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
81#define RX_BUF_SIZE 1536 /* Rx Buffer size */
82#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
83#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
84
85#define RTL8169_TX_TIMEOUT (6*HZ)
86#define RTL8169_PHY_TIMEOUT (10*HZ)
87
ea8dbdd1 88#define RTL_EEPROM_SIG cpu_to_le32(0x8129)
89#define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
e1564ec9
FR		 90#define RTL_EEPROM_SIG_ADDR 0x0000
91
1da177e4
LT		 92/* write/read MMIO register */
93#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
94#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
95#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
96#define RTL_R8(reg) readb (ioaddr + (reg))
97#define RTL_R16(reg) readw (ioaddr + (reg))
06f555f3 98#define RTL_R32(reg) readl (ioaddr + (reg))
1da177e4
LT		 99
100enum mac_version {
85bffe6c
FR		 101 RTL_GIGA_MAC_VER_01 = 0,
102 RTL_GIGA_MAC_VER_02,
103 RTL_GIGA_MAC_VER_03,
104 RTL_GIGA_MAC_VER_04,
105 RTL_GIGA_MAC_VER_05,
106 RTL_GIGA_MAC_VER_06,
107 RTL_GIGA_MAC_VER_07,
108 RTL_GIGA_MAC_VER_08,
109 RTL_GIGA_MAC_VER_09,
110 RTL_GIGA_MAC_VER_10,
111 RTL_GIGA_MAC_VER_11,
112 RTL_GIGA_MAC_VER_12,
113 RTL_GIGA_MAC_VER_13,
114 RTL_GIGA_MAC_VER_14,
115 RTL_GIGA_MAC_VER_15,
116 RTL_GIGA_MAC_VER_16,
117 RTL_GIGA_MAC_VER_17,
118 RTL_GIGA_MAC_VER_18,
119 RTL_GIGA_MAC_VER_19,
120 RTL_GIGA_MAC_VER_20,
121 RTL_GIGA_MAC_VER_21,
122 RTL_GIGA_MAC_VER_22,
123 RTL_GIGA_MAC_VER_23,
124 RTL_GIGA_MAC_VER_24,
125 RTL_GIGA_MAC_VER_25,
126 RTL_GIGA_MAC_VER_26,
127 RTL_GIGA_MAC_VER_27,
128 RTL_GIGA_MAC_VER_28,
129 RTL_GIGA_MAC_VER_29,
130 RTL_GIGA_MAC_VER_30,
131 RTL_GIGA_MAC_VER_31,
132 RTL_GIGA_MAC_VER_32,
133 RTL_GIGA_MAC_VER_33,
70090424 134 RTL_GIGA_MAC_VER_34,
c2218925
HW		 135 RTL_GIGA_MAC_VER_35,
136 RTL_GIGA_MAC_VER_36,
85bffe6c 137 RTL_GIGA_MAC_NONE = 0xff,
1da177e4
LT		 138};
139
2b7b4318
FR		 140enum rtl_tx_desc_version {
141 RTL_TD_0 = 0,
142 RTL_TD_1 = 1,
143};
144
d58d46b5
FR		 145#define JUMBO_1K ETH_DATA_LEN
146#define JUMBO_4K (4*1024 - ETH_HLEN - 2)
147#define JUMBO_6K (6*1024 - ETH_HLEN - 2)
148#define JUMBO_7K (7*1024 - ETH_HLEN - 2)
149#define JUMBO_9K (9*1024 - ETH_HLEN - 2)
150
151#define _R(NAME,TD,FW,SZ,B) { \
152 .name = NAME, \
153 .txd_version = TD, \
154 .fw_name = FW, \
155 .jumbo_max = SZ, \
156 .jumbo_tx_csum = B \
157}
1da177e4 158
3c6bee1d 159static const struct {
1da177e4 160 const char *name;
2b7b4318 161 enum rtl_tx_desc_version txd_version;
953a12cc 162 const char *fw_name;
d58d46b5
FR		 163 u16 jumbo_max;
164 bool jumbo_tx_csum;
85bffe6c
FR		 165} rtl_chip_infos[] = {
166 /* PCI devices. */
167 [RTL_GIGA_MAC_VER_01] =
d58d46b5 168 _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 169 [RTL_GIGA_MAC_VER_02] =
d58d46b5 170 _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 171 [RTL_GIGA_MAC_VER_03] =
d58d46b5 172 _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 173 [RTL_GIGA_MAC_VER_04] =
d58d46b5 174 _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 175 [RTL_GIGA_MAC_VER_05] =
d58d46b5 176 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 177 [RTL_GIGA_MAC_VER_06] =
d58d46b5 178 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c
FR		 179 /* PCI-E devices. */
180 [RTL_GIGA_MAC_VER_07] =
d58d46b5 181 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 182 [RTL_GIGA_MAC_VER_08] =
d58d46b5 183 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 184 [RTL_GIGA_MAC_VER_09] =
d58d46b5 185 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 186 [RTL_GIGA_MAC_VER_10] =
d58d46b5 187 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 188 [RTL_GIGA_MAC_VER_11] =
d58d46b5 189 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
85bffe6c 190 [RTL_GIGA_MAC_VER_12] =
d58d46b5 191 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
85bffe6c 192 [RTL_GIGA_MAC_VER_13] =
d58d46b5 193 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 194 [RTL_GIGA_MAC_VER_14] =
d58d46b5 195 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 196 [RTL_GIGA_MAC_VER_15] =
d58d46b5 197 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 198 [RTL_GIGA_MAC_VER_16] =
d58d46b5 199 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 200 [RTL_GIGA_MAC_VER_17] =
d58d46b5 201 _R("RTL8168b/8111b", RTL_TD_1, NULL, JUMBO_4K, false),
85bffe6c 202 [RTL_GIGA_MAC_VER_18] =
d58d46b5 203 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 204 [RTL_GIGA_MAC_VER_19] =
d58d46b5 205 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 206 [RTL_GIGA_MAC_VER_20] =
d58d46b5 207 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 208 [RTL_GIGA_MAC_VER_21] =
d58d46b5 209 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 210 [RTL_GIGA_MAC_VER_22] =
d58d46b5 211 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 212 [RTL_GIGA_MAC_VER_23] =
d58d46b5 213 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 214 [RTL_GIGA_MAC_VER_24] =
d58d46b5 215 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 216 [RTL_GIGA_MAC_VER_25] =
d58d46b5
FR		 217 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1,
218 JUMBO_9K, false),
85bffe6c 219 [RTL_GIGA_MAC_VER_26] =
d58d46b5
FR		 220 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2,
221 JUMBO_9K, false),
85bffe6c 222 [RTL_GIGA_MAC_VER_27] =
d58d46b5 223 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 224 [RTL_GIGA_MAC_VER_28] =
d58d46b5 225 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 226 [RTL_GIGA_MAC_VER_29] =
d58d46b5
FR		 227 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
228 JUMBO_1K, true),
85bffe6c 229 [RTL_GIGA_MAC_VER_30] =
d58d46b5
FR		 230 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
231 JUMBO_1K, true),
85bffe6c 232 [RTL_GIGA_MAC_VER_31] =
d58d46b5 233 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 234 [RTL_GIGA_MAC_VER_32] =
d58d46b5
FR		 235 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1,
236 JUMBO_9K, false),
85bffe6c 237 [RTL_GIGA_MAC_VER_33] =
d58d46b5
FR		 238 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2,
239 JUMBO_9K, false),
70090424 240 [RTL_GIGA_MAC_VER_34] =
d58d46b5
FR		 241 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
242 JUMBO_9K, false),
c2218925 243 [RTL_GIGA_MAC_VER_35] =
d58d46b5
FR		 244 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1,
245 JUMBO_9K, false),
c2218925 246 [RTL_GIGA_MAC_VER_36] =
d58d46b5
FR		 247 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2,
248 JUMBO_9K, false),
953a12cc 249};
85bffe6c 250#undef _R
953a12cc 251
bcf0bf90
FR		 252enum cfg_version {
253 RTL_CFG_0 = 0x00,
254 RTL_CFG_1,
255 RTL_CFG_2
256};
257
07ce4064
FR		 258static void rtl_hw_start_8169(struct net_device *);
259static void rtl_hw_start_8168(struct net_device *);
260static void rtl_hw_start_8101(struct net_device *);
261
a3aa1884 262static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
bcf0bf90 263 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 264 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 265 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 266 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90
FR		 267 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
268 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
93a3aa25 269 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
bc1660b5 270 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 271 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
272 { PCI_VENDOR_ID_LINKSYS, 0x1032,
273 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 274 { 0x0001, 0x8168,
275 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 276 {0,},
277};
278
279MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
280
6f0333b8 281static int rx_buf_sz = 16383;
4300e8c7 282static int use_dac;
b57b7e5a
SH		 283static struct {
284 u32 msg_enable;
285} debug = { -1 };
1da177e4 286
07d3f51f
FR		 287enum rtl_registers {
288 MAC0 = 0, /* Ethernet hardware address. */
773d2021 289 MAC4 = 4,
07d3f51f
FR		 290 MAR0 = 8, /* Multicast filter. */
291 CounterAddrLow = 0x10,
292 CounterAddrHigh = 0x14,
293 TxDescStartAddrLow = 0x20,
294 TxDescStartAddrHigh = 0x24,
295 TxHDescStartAddrLow = 0x28,
296 TxHDescStartAddrHigh = 0x2c,
297 FLASH = 0x30,
298 ERSR = 0x36,
299 ChipCmd = 0x37,
300 TxPoll = 0x38,
301 IntrMask = 0x3c,
302 IntrStatus = 0x3e,
4f6b00e5 303
07d3f51f 304 TxConfig = 0x40,
4f6b00e5
HW		 305#define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
306#define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
2b7b4318 307
4f6b00e5
HW		 308 RxConfig = 0x44,
309#define RX128_INT_EN (1 << 15) /* 8111c and later */
310#define RX_MULTI_EN (1 << 14) /* 8111c only */
311#define RXCFG_FIFO_SHIFT 13
312 /* No threshold before first PCI xfer */
313#define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
314#define RXCFG_DMA_SHIFT 8
315 /* Unlimited maximum PCI burst. */
316#define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
2b7b4318 317
07d3f51f
FR		 318 RxMissed = 0x4c,
319 Cfg9346 = 0x50,
320 Config0 = 0x51,
321 Config1 = 0x52,
322 Config2 = 0x53,
323 Config3 = 0x54,
324 Config4 = 0x55,
325 Config5 = 0x56,
326 MultiIntr = 0x5c,
327 PHYAR = 0x60,
07d3f51f
FR		 328 PHYstatus = 0x6c,
329 RxMaxSize = 0xda,
330 CPlusCmd = 0xe0,
331 IntrMitigate = 0xe2,
332 RxDescAddrLow = 0xe4,
333 RxDescAddrHigh = 0xe8,
f0298f81 334 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
335
336#define NoEarlyTx 0x3f /* Max value : no early transmit. */
337
338 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
339
340#define TxPacketMax (8064 >> 7)
3090bd9a 341#define EarlySize 0x27
f0298f81 342
07d3f51f
FR		 343 FuncEvent = 0xf0,
344 FuncEventMask = 0xf4,
345 FuncPresetState = 0xf8,
346 FuncForceEvent = 0xfc,
1da177e4
LT		 347};
348
f162a5d1
FR		 349enum rtl8110_registers {
350 TBICSR = 0x64,
351 TBI_ANAR = 0x68,
352 TBI_LPAR = 0x6a,
353};
354
355enum rtl8168_8101_registers {
356 CSIDR = 0x64,
357 CSIAR = 0x68,
358#define CSIAR_FLAG 0x80000000
359#define CSIAR_WRITE_CMD 0x80000000
360#define CSIAR_BYTE_ENABLE 0x0f
361#define CSIAR_BYTE_ENABLE_SHIFT 12
362#define CSIAR_ADDR_MASK 0x0fff
065c27c1 363 PMCH = 0x6f,
f162a5d1
FR		 364 EPHYAR = 0x80,
365#define EPHYAR_FLAG 0x80000000
366#define EPHYAR_WRITE_CMD 0x80000000
367#define EPHYAR_REG_MASK 0x1f
368#define EPHYAR_REG_SHIFT 16
369#define EPHYAR_DATA_MASK 0xffff
5a5e4443 370 DLLPR = 0xd0,
4f6b00e5 371#define PFM_EN (1 << 6)
f162a5d1
FR		 372 DBG_REG = 0xd1,
373#define FIX_NAK_1 (1 << 4)
374#define FIX_NAK_2 (1 << 3)
5a5e4443
HW		 375 TWSI = 0xd2,
376 MCU = 0xd3,
4f6b00e5 377#define NOW_IS_OOB (1 << 7)
5a5e4443
HW		 378#define EN_NDP (1 << 3)
379#define EN_OOB_RESET (1 << 2)
daf9df6d 380 EFUSEAR = 0xdc,
381#define EFUSEAR_FLAG 0x80000000
382#define EFUSEAR_WRITE_CMD 0x80000000
383#define EFUSEAR_READ_CMD 0x00000000
384#define EFUSEAR_REG_MASK 0x03ff
385#define EFUSEAR_REG_SHIFT 8
386#define EFUSEAR_DATA_MASK 0xff
f162a5d1
FR		 387};
388
c0e45c1c 389enum rtl8168_registers {
4f6b00e5
HW		 390 LED_FREQ = 0x1a,
391 EEE_LED = 0x1b,
b646d900 392 ERIDR = 0x70,
393 ERIAR = 0x74,
394#define ERIAR_FLAG 0x80000000
395#define ERIAR_WRITE_CMD 0x80000000
396#define ERIAR_READ_CMD 0x00000000
397#define ERIAR_ADDR_BYTE_ALIGN 4
b646d900 398#define ERIAR_TYPE_SHIFT 16
4f6b00e5
HW		 399#define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
400#define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
401#define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
402#define ERIAR_MASK_SHIFT 12
403#define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
404#define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
405#define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
c0e45c1c 406 EPHY_RXER_NUM = 0x7c,
407 OCPDR = 0xb0, /* OCP GPHY access */
408#define OCPDR_WRITE_CMD 0x80000000
409#define OCPDR_READ_CMD 0x00000000
410#define OCPDR_REG_MASK 0x7f
411#define OCPDR_GPHY_REG_SHIFT 16
412#define OCPDR_DATA_MASK 0xffff
413 OCPAR = 0xb4,
414#define OCPAR_FLAG 0x80000000
415#define OCPAR_GPHY_WRITE_CMD 0x8000f060
416#define OCPAR_GPHY_READ_CMD 0x0000f060
01dc7fec 417 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
418 MISC = 0xf0, /* 8168e only. */
cecb5fd7 419#define TXPLA_RST (1 << 29)
4f6b00e5 420#define PWM_EN (1 << 22)
c0e45c1c 421};
422
07d3f51f 423enum rtl_register_content {
1da177e4 424 /* InterruptStatusBits */
07d3f51f
FR		 425 SYSErr = 0x8000,
426 PCSTimeout = 0x4000,
427 SWInt = 0x0100,
428 TxDescUnavail = 0x0080,
429 RxFIFOOver = 0x0040,
430 LinkChg = 0x0020,
431 RxOverflow = 0x0010,
432 TxErr = 0x0008,
433 TxOK = 0x0004,
434 RxErr = 0x0002,
435 RxOK = 0x0001,
1da177e4
LT		 436
437 /* RxStatusDesc */
e03f33af 438 RxBOVF = (1 << 24),
9dccf611
FR		 439 RxFOVF = (1 << 23),
440 RxRWT = (1 << 22),
441 RxRES = (1 << 21),
442 RxRUNT = (1 << 20),
443 RxCRC = (1 << 19),
1da177e4
LT		 444
445 /* ChipCmdBits */
4f6b00e5 446 StopReq = 0x80,
07d3f51f
FR		 447 CmdReset = 0x10,
448 CmdRxEnb = 0x08,
449 CmdTxEnb = 0x04,
450 RxBufEmpty = 0x01,
1da177e4 451
275391a4
FR		 452 /* TXPoll register p.5 */
453 HPQ = 0x80, /* Poll cmd on the high prio queue */
454 NPQ = 0x40, /* Poll cmd on the low prio queue */
455 FSWInt = 0x01, /* Forced software interrupt */
456
1da177e4 457 /* Cfg9346Bits */
07d3f51f
FR		 458 Cfg9346_Lock = 0x00,
459 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 460
461 /* rx_mode_bits */
07d3f51f
FR		 462 AcceptErr = 0x20,
463 AcceptRunt = 0x10,
464 AcceptBroadcast = 0x08,
465 AcceptMulticast = 0x04,
466 AcceptMyPhys = 0x02,
467 AcceptAllPhys = 0x01,
1687b566 468#define RX_CONFIG_ACCEPT_MASK 0x3f
1da177e4 469
1da177e4
LT		 470 /* TxConfigBits */
471 TxInterFrameGapShift = 24,
472 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
473
5d06a99f 474 /* Config1 register p.24 */
f162a5d1
FR		 475 LEDS1 = (1 << 7),
476 LEDS0 = (1 << 6),
f162a5d1
FR		 477 Speed_down = (1 << 4),
478 MEMMAP = (1 << 3),
479 IOMAP = (1 << 2),
480 VPD = (1 << 1),
5d06a99f
FR		 481 PMEnable = (1 << 0), /* Power Management Enable */
482
6dccd16b 483 /* Config2 register p. 25 */
2ca6cf06 484 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
6dccd16b
FR		 485 PCI_Clock_66MHz = 0x01,
486 PCI_Clock_33MHz = 0x00,
487
61a4dcc2
FR		 488 /* Config3 register p.25 */
489 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
490 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
d58d46b5 491 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
f162a5d1 492 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 493
d58d46b5
FR		 494 /* Config4 register */
495 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
496
5d06a99f 497 /* Config5 register p.27 */
61a4dcc2
FR		 498 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
499 MWF = (1 << 5), /* Accept Multicast wakeup frame */
500 UWF = (1 << 4), /* Accept Unicast wakeup frame */
cecb5fd7 501 Spi_en = (1 << 3),
61a4dcc2 502 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 503 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
504
1da177e4
LT		 505 /* TBICSR p.28 */
506 TBIReset = 0x80000000,
507 TBILoopback = 0x40000000,
508 TBINwEnable = 0x20000000,
509 TBINwRestart = 0x10000000,
510 TBILinkOk = 0x02000000,
511 TBINwComplete = 0x01000000,
512
513 /* CPlusCmd p.31 */
f162a5d1
FR		 514 EnableBist = (1 << 15), // 8168 8101
515 Mac_dbgo_oe = (1 << 14), // 8168 8101
516 Normal_mode = (1 << 13), // unused
517 Force_half_dup = (1 << 12), // 8168 8101
518 Force_rxflow_en = (1 << 11), // 8168 8101
519 Force_txflow_en = (1 << 10), // 8168 8101
520 Cxpl_dbg_sel = (1 << 9), // 8168 8101
521 ASF = (1 << 8), // 8168 8101
522 PktCntrDisable = (1 << 7), // 8168 8101
523 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 524 RxVlan = (1 << 6),
525 RxChkSum = (1 << 5),
526 PCIDAC = (1 << 4),
527 PCIMulRW = (1 << 3),
0e485150
FR		 528 INTT_0 = 0x0000, // 8168
529 INTT_1 = 0x0001, // 8168
530 INTT_2 = 0x0002, // 8168
531 INTT_3 = 0x0003, // 8168
1da177e4
LT		 532
533 /* rtl8169_PHYstatus */
07d3f51f
FR		 534 TBI_Enable = 0x80,
535 TxFlowCtrl = 0x40,
536 RxFlowCtrl = 0x20,
537 _1000bpsF = 0x10,
538 _100bps = 0x08,
539 _10bps = 0x04,
540 LinkStatus = 0x02,
541 FullDup = 0x01,
1da177e4 542
1da177e4 543 /* _TBICSRBit */
07d3f51f 544 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 545
546 /* DumpCounterCommand */
07d3f51f 547 CounterDump = 0x8,
1da177e4
LT		 548};
549
2b7b4318
FR		 550enum rtl_desc_bit {
551 /* First doubleword. */
1da177e4
LT		 552 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
553 RingEnd = (1 << 30), /* End of descriptor ring */
554 FirstFrag = (1 << 29), /* First segment of a packet */
555 LastFrag = (1 << 28), /* Final segment of a packet */
2b7b4318
FR		 556};
557
558/* Generic case. */
559enum rtl_tx_desc_bit {
560 /* First doubleword. */
561 TD_LSO = (1 << 27), /* Large Send Offload */
562#define TD_MSS_MAX 0x07ffu /* MSS value */
1da177e4 563
2b7b4318
FR		 564 /* Second doubleword. */
565 TxVlanTag = (1 << 17), /* Add VLAN tag */
566};
567
568/* 8169, 8168b and 810x except 8102e. */
569enum rtl_tx_desc_bit_0 {
570 /* First doubleword. */
571#define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
572 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
573 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
574 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
575};
576
577/* 8102e, 8168c and beyond. */
578enum rtl_tx_desc_bit_1 {
579 /* Second doubleword. */
580#define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
581 TD1_IP_CS = (1 << 29), /* Calculate IP checksum */
582 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
583 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
584};
1da177e4 585
2b7b4318
FR		 586static const struct rtl_tx_desc_info {
587 struct {
588 u32 udp;
589 u32 tcp;
590 } checksum;
591 u16 mss_shift;
592 u16 opts_offset;
593} tx_desc_info [] = {
594 [RTL_TD_0] = {
595 .checksum = {
596 .udp = TD0_IP_CS | TD0_UDP_CS,
597 .tcp = TD0_IP_CS | TD0_TCP_CS
598 },
599 .mss_shift = TD0_MSS_SHIFT,
600 .opts_offset = 0
601 },
602 [RTL_TD_1] = {
603 .checksum = {
604 .udp = TD1_IP_CS | TD1_UDP_CS,
605 .tcp = TD1_IP_CS | TD1_TCP_CS
606 },
607 .mss_shift = TD1_MSS_SHIFT,
608 .opts_offset = 1
609 }
610};
611
612enum rtl_rx_desc_bit {
1da177e4
LT		 613 /* Rx private */
614 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
615 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
616
617#define RxProtoUDP (PID1)
618#define RxProtoTCP (PID0)
619#define RxProtoIP (PID1 | PID0)
620#define RxProtoMask RxProtoIP
621
622 IPFail = (1 << 16), /* IP checksum failed */
623 UDPFail = (1 << 15), /* UDP/IP checksum failed */
624 TCPFail = (1 << 14), /* TCP/IP checksum failed */
625 RxVlanTag = (1 << 16), /* VLAN tag available */
626};
627
628#define RsvdMask 0x3fffc000
629
630struct TxDesc {
6cccd6e7
REB		 631 __le32 opts1;
632 __le32 opts2;
633 __le64 addr;
1da177e4
LT		 634};
635
636struct RxDesc {
6cccd6e7
REB		 637 __le32 opts1;
638 __le32 opts2;
639 __le64 addr;
1da177e4
LT		 640};
641
642struct ring_info {
643 struct sk_buff *skb;
644 u32 len;
645 u8 __pad[sizeof(void *) - sizeof(u32)];
646};
647
f23e7fda 648enum features {
ccdffb9a
FR		 649 RTL_FEATURE_WOL = (1 << 0),
650 RTL_FEATURE_MSI = (1 << 1),
651 RTL_FEATURE_GMII = (1 << 2),
f23e7fda
FR		 652};
653
355423d0
IV		 654struct rtl8169_counters {
655 __le64 tx_packets;
656 __le64 rx_packets;
657 __le64 tx_errors;
658 __le32 rx_errors;
659 __le16 rx_missed;
660 __le16 align_errors;
661 __le32 tx_one_collision;
662 __le32 tx_multi_collision;
663 __le64 rx_unicast;
664 __le64 rx_broadcast;
665 __le32 rx_multicast;
666 __le16 tx_aborted;
667 __le16 tx_underun;
668};
669
1da177e4
LT		 670struct rtl8169_private {
671 void __iomem *mmio_addr; /* memory map physical address */
cecb5fd7 672 struct pci_dev *pci_dev;
c4028958 673 struct net_device *dev;
bea3348e 674 struct napi_struct napi;
cecb5fd7 675 spinlock_t lock;
b57b7e5a 676 u32 msg_enable;
2b7b4318
FR		 677 u16 txd_version;
678 u16 mac_version;
1da177e4
LT		 679 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
680 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
681 u32 dirty_rx;
682 u32 dirty_tx;
683 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
684 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
685 dma_addr_t TxPhyAddr;
686 dma_addr_t RxPhyAddr;
6f0333b8 687 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
1da177e4 688 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
1da177e4
LT		 689 struct timer_list timer;
690 u16 cp_cmd;
0e485150
FR		 691 u16 intr_event;
692 u16 napi_event;
1da177e4 693 u16 intr_mask;
c0e45c1c 694
695 struct mdio_ops {
696 void (*write)(void __iomem *, int, int);
697 int (*read)(void __iomem *, int);
698 } mdio_ops;
699
065c27c1 700 struct pll_power_ops {
701 void (*down)(struct rtl8169_private *);
702 void (*up)(struct rtl8169_private *);
703 } pll_power_ops;
704
d58d46b5
FR		 705 struct jumbo_ops {
706 void (*enable)(struct rtl8169_private *);
707 void (*disable)(struct rtl8169_private *);
708 } jumbo_ops;
709
54405cde 710 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
ccdffb9a 711 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
4da19633 712 void (*phy_reset_enable)(struct rtl8169_private *tp);
07ce4064 713 void (*hw_start)(struct net_device *);
4da19633 714 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
1da177e4 715 unsigned int (*link_ok)(void __iomem *);
8b4ab28d 716 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
4422bcd4
FR		 717
718 struct {
719 struct work_struct work;
720 } wk;
721
f23e7fda 722 unsigned features;
ccdffb9a
FR		 723
724 struct mii_if_info mii;
355423d0 725 struct rtl8169_counters counters;
e1759441 726 u32 saved_wolopts;
e03f33af 727 u32 opts1_mask;
f1e02ed1 728
b6ffd97f
FR		 729 struct rtl_fw {
730 const struct firmware *fw;
1c361efb
FR		 731
732#define RTL_VER_SIZE 32
733
734 char version[RTL_VER_SIZE];
735
736 struct rtl_fw_phy_action {
737 __le32 *code;
738 size_t size;
739 } phy_action;
b6ffd97f 740 } *rtl_fw;
497888cf 741#define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
1da177e4
LT		 742};
743
979b6c13 744MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 745MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 746module_param(use_dac, int, 0);
4300e8c7 747MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 748module_param_named(debug, debug.msg_enable, int, 0);
749MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 750MODULE_LICENSE("GPL");
751MODULE_VERSION(RTL8169_VERSION);
bca03d5f 752MODULE_FIRMWARE(FIRMWARE_8168D_1);
753MODULE_FIRMWARE(FIRMWARE_8168D_2);
01dc7fec 754MODULE_FIRMWARE(FIRMWARE_8168E_1);
755MODULE_FIRMWARE(FIRMWARE_8168E_2);
bbb8af75 756MODULE_FIRMWARE(FIRMWARE_8168E_3);
5a5e4443 757MODULE_FIRMWARE(FIRMWARE_8105E_1);
c2218925
HW		 758MODULE_FIRMWARE(FIRMWARE_8168F_1);
759MODULE_FIRMWARE(FIRMWARE_8168F_2);
1da177e4
LT		 760
761static int rtl8169_open(struct net_device *dev);
61357325
SH		 762static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
763 struct net_device *dev);
7d12e780 764static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
1da177e4 765static int rtl8169_init_ring(struct net_device *dev);
07ce4064 766static void rtl_hw_start(struct net_device *dev);
1da177e4 767static int rtl8169_close(struct net_device *dev);
07ce4064 768static void rtl_set_rx_mode(struct net_device *dev);
1da177e4 769static void rtl8169_tx_timeout(struct net_device *dev);
4dcb7d33 770static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
1da177e4 771static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
bea3348e 772 void __iomem *, u32 budget);
4dcb7d33 773static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
1da177e4 774static void rtl8169_down(struct net_device *dev);
99f252b0 775static void rtl8169_rx_clear(struct rtl8169_private *tp);
bea3348e 776static int rtl8169_poll(struct napi_struct *napi, int budget);
1da177e4 777
d58d46b5
FR		 778static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
779{
780 int cap = pci_pcie_cap(pdev);
781
782 if (cap) {
783 u16 ctl;
784
785 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
786 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
787 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
788 }
789}
790
b646d900 791static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
792{
793 void __iomem *ioaddr = tp->mmio_addr;
794 int i;
795
796 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
797 for (i = 0; i < 20; i++) {
798 udelay(100);
799 if (RTL_R32(OCPAR) & OCPAR_FLAG)
800 break;
801 }
802 return RTL_R32(OCPDR);
803}
804
805static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
806{
807 void __iomem *ioaddr = tp->mmio_addr;
808 int i;
809
810 RTL_W32(OCPDR, data);
811 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
812 for (i = 0; i < 20; i++) {
813 udelay(100);
814 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
815 break;
816 }
817}
818
fac5b3ca 819static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
b646d900 820{
fac5b3ca 821 void __iomem *ioaddr = tp->mmio_addr;
b646d900 822 int i;
823
824 RTL_W8(ERIDR, cmd);
825 RTL_W32(ERIAR, 0x800010e8);
826 msleep(2);
827 for (i = 0; i < 5; i++) {
828 udelay(100);
1e4e82ba 829 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
b646d900 830 break;
831 }
832
fac5b3ca 833 ocp_write(tp, 0x1, 0x30, 0x00000001);
b646d900 834}
835
836#define OOB_CMD_RESET 0x00
837#define OOB_CMD_DRIVER_START 0x05
838#define OOB_CMD_DRIVER_STOP 0x06
839
cecb5fd7
FR		 840static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
841{
842 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
843}
844
b646d900 845static void rtl8168_driver_start(struct rtl8169_private *tp)
846{
cecb5fd7 847 u16 reg;
b646d900 848 int i;
849
850 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
851
cecb5fd7 852 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 853
b646d900 854 for (i = 0; i < 10; i++) {
855 msleep(10);
4804b3b3 856 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
b646d900 857 break;
858 }
859}
860
861static void rtl8168_driver_stop(struct rtl8169_private *tp)
862{
cecb5fd7 863 u16 reg;
b646d900 864 int i;
865
866 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
867
cecb5fd7 868 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 869
b646d900 870 for (i = 0; i < 10; i++) {
871 msleep(10);
4804b3b3 872 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
b646d900 873 break;
874 }
875}
876
4804b3b3 877static int r8168dp_check_dash(struct rtl8169_private *tp)
878{
cecb5fd7 879 u16 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 880
cecb5fd7 881 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
4804b3b3 882}
b646d900 883
4da19633 884static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1da177e4
LT		 885{
886 int i;
887
a6baf3af 888 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
1da177e4 889
2371408c 890 for (i = 20; i > 0; i--) {
07d3f51f
FR		 891 /*
892 * Check if the RTL8169 has completed writing to the specified
893 * MII register.
894 */
5b0384f4 895 if (!(RTL_R32(PHYAR) & 0x80000000))
1da177e4 896 break;
2371408c 897 udelay(25);
1da177e4 898 }
024a07ba 899 /*
81a95f04
TT		 900 * According to hardware specs a 20us delay is required after write
901 * complete indication, but before sending next command.
024a07ba 902 */
81a95f04 903 udelay(20);
1da177e4
LT		 904}
905
4da19633 906static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
1da177e4
LT		 907{
908 int i, value = -1;
909
a6baf3af 910 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
1da177e4 911
2371408c 912 for (i = 20; i > 0; i--) {
07d3f51f
FR		 913 /*
914 * Check if the RTL8169 has completed retrieving data from
915 * the specified MII register.
916 */
1da177e4 917 if (RTL_R32(PHYAR) & 0x80000000) {
a6baf3af 918 value = RTL_R32(PHYAR) & 0xffff;
1da177e4
LT		 919 break;
920 }
2371408c 921 udelay(25);
1da177e4 922 }
81a95f04
TT		 923 /*
924 * According to hardware specs a 20us delay is required after read
925 * complete indication, but before sending next command.
926 */
927 udelay(20);
928
1da177e4
LT		 929 return value;
930}
931
c0e45c1c 932static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
933{
934 int i;
935
936 RTL_W32(OCPDR, data |
937 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
938 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
939 RTL_W32(EPHY_RXER_NUM, 0);
940
941 for (i = 0; i < 100; i++) {
942 mdelay(1);
943 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
944 break;
945 }
946}
947
948static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
949{
950 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
951 (value & OCPDR_DATA_MASK));
952}
953
954static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
955{
956 int i;
957
958 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
959
960 mdelay(1);
961 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
962 RTL_W32(EPHY_RXER_NUM, 0);
963
964 for (i = 0; i < 100; i++) {
965 mdelay(1);
966 if (RTL_R32(OCPAR) & OCPAR_FLAG)
967 break;
968 }
969
970 return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
971}
972
e6de30d6 973#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
974
975static void r8168dp_2_mdio_start(void __iomem *ioaddr)
976{
977 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
978}
979
980static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
981{
982 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
983}
984
985static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
986{
987 r8168dp_2_mdio_start(ioaddr);
988
989 r8169_mdio_write(ioaddr, reg_addr, value);
990
991 r8168dp_2_mdio_stop(ioaddr);
992}
993
994static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
995{
996 int value;
997
998 r8168dp_2_mdio_start(ioaddr);
999
1000 value = r8169_mdio_read(ioaddr, reg_addr);
1001
1002 r8168dp_2_mdio_stop(ioaddr);
1003
1004 return value;
1005}
1006
4da19633 1007static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
dacf8154 1008{
c0e45c1c 1009 tp->mdio_ops.write(tp->mmio_addr, location, val);
dacf8154
FR		 1010}
1011
4da19633 1012static int rtl_readphy(struct rtl8169_private *tp, int location)
1013{
c0e45c1c 1014 return tp->mdio_ops.read(tp->mmio_addr, location);
4da19633 1015}
1016
1017static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1018{
1019 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1020}
1021
1022static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
daf9df6d 1023{
1024 int val;
1025
4da19633 1026 val = rtl_readphy(tp, reg_addr);
1027 rtl_writephy(tp, reg_addr, (val | p) & ~m);
daf9df6d 1028}
1029
ccdffb9a
FR		 1030static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1031 int val)
1032{
1033 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1034
4da19633 1035 rtl_writephy(tp, location, val);
ccdffb9a
FR		 1036}
1037
1038static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1039{
1040 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1041
4da19633 1042 return rtl_readphy(tp, location);
ccdffb9a
FR		 1043}
1044
dacf8154
FR		 1045static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
1046{
1047 unsigned int i;
1048
1049 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1050 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1051
1052 for (i = 0; i < 100; i++) {
1053 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
1054 break;
1055 udelay(10);
1056 }
1057}
1058
1059static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
1060{
1061 u16 value = 0xffff;
1062 unsigned int i;
1063
1064 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1065
1066 for (i = 0; i < 100; i++) {
1067 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
1068 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
1069 break;
1070 }
1071 udelay(10);
1072 }
1073
1074 return value;
1075}
1076
1077static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
1078{
1079 unsigned int i;
1080
1081 RTL_W32(CSIDR, value);
1082 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
1083 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1084
1085 for (i = 0; i < 100; i++) {
1086 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
1087 break;
1088 udelay(10);
1089 }
1090}
1091
1092static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
1093{
1094 u32 value = ~0x00;
1095 unsigned int i;
1096
1097 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
1098 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1099
1100 for (i = 0; i < 100; i++) {
1101 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
1102 value = RTL_R32(CSIDR);
1103 break;
1104 }
1105 udelay(10);
1106 }
1107
1108 return value;
1109}
1110
133ac40a
HW		 1111static
1112void rtl_eri_write(void __iomem *ioaddr, int addr, u32 mask, u32 val, int type)
1113{
1114 unsigned int i;
1115
1116 BUG_ON((addr & 3) || (mask == 0));
1117 RTL_W32(ERIDR, val);
1118 RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1119
1120 for (i = 0; i < 100; i++) {
1121 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
1122 break;
1123 udelay(100);
1124 }
1125}
1126
1127static u32 rtl_eri_read(void __iomem *ioaddr, int addr, int type)
1128{
1129 u32 value = ~0x00;
1130 unsigned int i;
1131
1132 RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1133
1134 for (i = 0; i < 100; i++) {
1135 if (RTL_R32(ERIAR) & ERIAR_FLAG) {
1136 value = RTL_R32(ERIDR);
1137 break;
1138 }
1139 udelay(100);
1140 }
1141
1142 return value;
1143}
1144
1145static void
1146rtl_w1w0_eri(void __iomem *ioaddr, int addr, u32 mask, u32 p, u32 m, int type)
1147{
1148 u32 val;
1149
1150 val = rtl_eri_read(ioaddr, addr, type);
1151 rtl_eri_write(ioaddr, addr, mask, (val & ~m) | p, type);
1152}
1153
c28aa385 1154struct exgmac_reg {
1155 u16 addr;
1156 u16 mask;
1157 u32 val;
1158};
1159
1160static void rtl_write_exgmac_batch(void __iomem *ioaddr,
1161 const struct exgmac_reg *r, int len)
1162{
1163 while (len-- > 0) {
1164 rtl_eri_write(ioaddr, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1165 r++;
1166 }
1167}
1168
daf9df6d 1169static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
1170{
1171 u8 value = 0xff;
1172 unsigned int i;
1173
1174 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1175
1176 for (i = 0; i < 300; i++) {
1177 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
1178 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
1179 break;
1180 }
1181 udelay(100);
1182 }
1183
1184 return value;
1185}
1186
3e990ff5
FR		 1187static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1188{
1189 void __iomem *ioaddr = tp->mmio_addr;
1190
1191 RTL_W16(IntrMask, bits);
1192}
1193
811fd301 1194static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1da177e4 1195{
811fd301 1196 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 1197
811fd301 1198 RTL_W16(IntrMask, 0x0000);
1199 RTL_W16(IntrStatus, tp->intr_event);
1200 RTL_R8(ChipCmd);
1da177e4
LT		 1201}
1202
4da19633 1203static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1da177e4 1204{
4da19633 1205 void __iomem *ioaddr = tp->mmio_addr;
1206
1da177e4
LT		 1207 return RTL_R32(TBICSR) & TBIReset;
1208}
1209
4da19633 1210static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1da177e4 1211{
4da19633 1212 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 1213}
1214
1215static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1216{
1217 return RTL_R32(TBICSR) & TBILinkOk;
1218}
1219
1220static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1221{
1222 return RTL_R8(PHYstatus) & LinkStatus;
1223}
1224
4da19633 1225static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1da177e4 1226{
4da19633 1227 void __iomem *ioaddr = tp->mmio_addr;
1228
1da177e4
LT		 1229 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1230}
1231
4da19633 1232static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1da177e4
LT		 1233{
1234 unsigned int val;
1235
4da19633 1236 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1237 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1da177e4
LT		 1238}
1239
70090424
HW		 1240static void rtl_link_chg_patch(struct rtl8169_private *tp)
1241{
1242 void __iomem *ioaddr = tp->mmio_addr;
1243 struct net_device *dev = tp->dev;
1244
1245 if (!netif_running(dev))
1246 return;
1247
1248 if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
1249 if (RTL_R8(PHYstatus) & _1000bpsF) {
1250 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1251 0x00000011, ERIAR_EXGMAC);
1252 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1253 0x00000005, ERIAR_EXGMAC);
1254 } else if (RTL_R8(PHYstatus) & _100bps) {
1255 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1256 0x0000001f, ERIAR_EXGMAC);
1257 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1258 0x00000005, ERIAR_EXGMAC);
1259 } else {
1260 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1261 0x0000001f, ERIAR_EXGMAC);
1262 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1263 0x0000003f, ERIAR_EXGMAC);
1264 }
1265 /* Reset packet filter */
1266 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1267 ERIAR_EXGMAC);
1268 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1269 ERIAR_EXGMAC);
c2218925
HW		 1270 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1271 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1272 if (RTL_R8(PHYstatus) & _1000bpsF) {
1273 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1274 0x00000011, ERIAR_EXGMAC);
1275 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1276 0x00000005, ERIAR_EXGMAC);
1277 } else {
1278 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1279 0x0000001f, ERIAR_EXGMAC);
1280 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1281 0x0000003f, ERIAR_EXGMAC);
1282 }
70090424
HW		 1283 }
1284}
1285
e4fbce74 1286static void __rtl8169_check_link_status(struct net_device *dev,
cecb5fd7
FR		 1287 struct rtl8169_private *tp,
1288 void __iomem *ioaddr, bool pm)
1da177e4
LT		 1289{
1290 unsigned long flags;
1291
1292 spin_lock_irqsave(&tp->lock, flags);
1293 if (tp->link_ok(ioaddr)) {
70090424 1294 rtl_link_chg_patch(tp);
e1759441 1295 /* This is to cancel a scheduled suspend if there's one. */
e4fbce74
RW		 1296 if (pm)
1297 pm_request_resume(&tp->pci_dev->dev);
1da177e4 1298 netif_carrier_on(dev);
1519e57f
FR		 1299 if (net_ratelimit())
1300 netif_info(tp, ifup, dev, "link up\n");
b57b7e5a 1301 } else {
1da177e4 1302 netif_carrier_off(dev);
bf82c189 1303 netif_info(tp, ifdown, dev, "link down\n");
e4fbce74 1304 if (pm)
10953db8 1305 pm_schedule_suspend(&tp->pci_dev->dev, 5000);
b57b7e5a 1306 }
1da177e4
LT		 1307 spin_unlock_irqrestore(&tp->lock, flags);
1308}
1309
e4fbce74
RW		 1310static void rtl8169_check_link_status(struct net_device *dev,
1311 struct rtl8169_private *tp,
1312 void __iomem *ioaddr)
1313{
1314 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1315}
1316
e1759441
RW		 1317#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1318
1319static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
61a4dcc2 1320{
61a4dcc2
FR		 1321 void __iomem *ioaddr = tp->mmio_addr;
1322 u8 options;
e1759441 1323 u32 wolopts = 0;
61a4dcc2
FR		 1324
1325 options = RTL_R8(Config1);
1326 if (!(options & PMEnable))
e1759441 1327 return 0;
61a4dcc2
FR		 1328
1329 options = RTL_R8(Config3);
1330 if (options & LinkUp)
e1759441 1331 wolopts |= WAKE_PHY;
61a4dcc2 1332 if (options & MagicPacket)
e1759441 1333 wolopts |= WAKE_MAGIC;
61a4dcc2
FR		 1334
1335 options = RTL_R8(Config5);
1336 if (options & UWF)
e1759441 1337 wolopts |= WAKE_UCAST;
61a4dcc2 1338 if (options & BWF)
e1759441 1339 wolopts |= WAKE_BCAST;
61a4dcc2 1340 if (options & MWF)
e1759441 1341 wolopts |= WAKE_MCAST;
61a4dcc2 1342
e1759441 1343 return wolopts;
61a4dcc2
FR		 1344}
1345
e1759441 1346static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
61a4dcc2
FR		 1347{
1348 struct rtl8169_private *tp = netdev_priv(dev);
e1759441
RW		 1349
1350 spin_lock_irq(&tp->lock);
1351
1352 wol->supported = WAKE_ANY;
1353 wol->wolopts = __rtl8169_get_wol(tp);
1354
1355 spin_unlock_irq(&tp->lock);
1356}
1357
1358static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1359{
61a4dcc2 1360 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1361 unsigned int i;
350f7596 1362 static const struct {
61a4dcc2
FR		 1363 u32 opt;
1364 u16 reg;
1365 u8 mask;
1366 } cfg[] = {
1367 { WAKE_ANY, Config1, PMEnable },
1368 { WAKE_PHY, Config3, LinkUp },
1369 { WAKE_MAGIC, Config3, MagicPacket },
1370 { WAKE_UCAST, Config5, UWF },
1371 { WAKE_BCAST, Config5, BWF },
1372 { WAKE_MCAST, Config5, MWF },
1373 { WAKE_ANY, Config5, LanWake }
1374 };
1375
61a4dcc2
FR		 1376 RTL_W8(Cfg9346, Cfg9346_Unlock);
1377
1378 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1379 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
e1759441 1380 if (wolopts & cfg[i].opt)
61a4dcc2
FR		 1381 options |= cfg[i].mask;
1382 RTL_W8(cfg[i].reg, options);
1383 }
1384
1385 RTL_W8(Cfg9346, Cfg9346_Lock);
e1759441
RW		 1386}
1387
1388static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1389{
1390 struct rtl8169_private *tp = netdev_priv(dev);
1391
1392 spin_lock_irq(&tp->lock);
61a4dcc2 1393
f23e7fda
FR		 1394 if (wol->wolopts)
1395 tp->features |= RTL_FEATURE_WOL;
1396 else
1397 tp->features &= ~RTL_FEATURE_WOL;
e1759441 1398 __rtl8169_set_wol(tp, wol->wolopts);
61a4dcc2
FR		 1399 spin_unlock_irq(&tp->lock);
1400
ea80907f 1401 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1402
61a4dcc2
FR		 1403 return 0;
1404}
1405
31bd204f
FR		 1406static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1407{
85bffe6c 1408 return rtl_chip_infos[tp->mac_version].fw_name;
31bd204f
FR		 1409}
1410
1da177e4
LT		 1411static void rtl8169_get_drvinfo(struct net_device *dev,
1412 struct ethtool_drvinfo *info)
1413{
1414 struct rtl8169_private *tp = netdev_priv(dev);
b6ffd97f 1415 struct rtl_fw *rtl_fw = tp->rtl_fw;
1da177e4 1416
68aad78c
RJ		 1417 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1418 strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1419 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1c361efb 1420 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
8ac72d16
RJ		 1421 if (!IS_ERR_OR_NULL(rtl_fw))
1422 strlcpy(info->fw_version, rtl_fw->version,
1423 sizeof(info->fw_version));
1da177e4
LT		 1424}
1425
1426static int rtl8169_get_regs_len(struct net_device *dev)
1427{
1428 return R8169_REGS_SIZE;
1429}
1430
1431static int rtl8169_set_speed_tbi(struct net_device *dev,
54405cde 1432 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1da177e4
LT		 1433{
1434 struct rtl8169_private *tp = netdev_priv(dev);
1435 void __iomem *ioaddr = tp->mmio_addr;
1436 int ret = 0;
1437 u32 reg;
1438
1439 reg = RTL_R32(TBICSR);
1440 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1441 (duplex == DUPLEX_FULL)) {
1442 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1443 } else if (autoneg == AUTONEG_ENABLE)
1444 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1445 else {
bf82c189
JP		 1446 netif_warn(tp, link, dev,
1447 "incorrect speed setting refused in TBI mode\n");
1da177e4
LT		 1448 ret = -EOPNOTSUPP;
1449 }
1450
1451 return ret;
1452}
1453
1454static int rtl8169_set_speed_xmii(struct net_device *dev,
54405cde 1455 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1da177e4
LT		 1456{
1457 struct rtl8169_private *tp = netdev_priv(dev);
3577aa1b 1458 int giga_ctrl, bmcr;
54405cde 1459 int rc = -EINVAL;
1da177e4 1460
716b50a3 1461 rtl_writephy(tp, 0x1f, 0x0000);
1da177e4
LT		 1462
1463 if (autoneg == AUTONEG_ENABLE) {
3577aa1b 1464 int auto_nego;
1465
4da19633 1466 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
54405cde
ON		 1467 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1468 ADVERTISE_100HALF | ADVERTISE_100FULL);
1469
1470 if (adv & ADVERTISED_10baseT_Half)
1471 auto_nego |= ADVERTISE_10HALF;
1472 if (adv & ADVERTISED_10baseT_Full)
1473 auto_nego |= ADVERTISE_10FULL;
1474 if (adv & ADVERTISED_100baseT_Half)
1475 auto_nego |= ADVERTISE_100HALF;
1476 if (adv & ADVERTISED_100baseT_Full)
1477 auto_nego |= ADVERTISE_100FULL;
1478
3577aa1b 1479 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1da177e4 1480
4da19633 1481 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
3577aa1b 1482 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
bcf0bf90 1483
3577aa1b 1484 /* The 8100e/8101e/8102e do Fast Ethernet only. */
826e6cbd 1485 if (tp->mii.supports_gmii) {
54405cde
ON		 1486 if (adv & ADVERTISED_1000baseT_Half)
1487 giga_ctrl |= ADVERTISE_1000HALF;
1488 if (adv & ADVERTISED_1000baseT_Full)
1489 giga_ctrl |= ADVERTISE_1000FULL;
1490 } else if (adv & (ADVERTISED_1000baseT_Half |
1491 ADVERTISED_1000baseT_Full)) {
bf82c189
JP		 1492 netif_info(tp, link, dev,
1493 "PHY does not support 1000Mbps\n");
54405cde 1494 goto out;
bcf0bf90 1495 }
1da177e4 1496
3577aa1b 1497 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1498
4da19633 1499 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1500 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
3577aa1b 1501 } else {
1502 giga_ctrl = 0;
1503
1504 if (speed == SPEED_10)
1505 bmcr = 0;
1506 else if (speed == SPEED_100)
1507 bmcr = BMCR_SPEED100;
1508 else
54405cde 1509 goto out;
3577aa1b 1510
1511 if (duplex == DUPLEX_FULL)
1512 bmcr |= BMCR_FULLDPLX;
2584fbc3
RS		 1513 }
1514
4da19633 1515 rtl_writephy(tp, MII_BMCR, bmcr);
3577aa1b 1516
cecb5fd7
FR		 1517 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1518 tp->mac_version == RTL_GIGA_MAC_VER_03) {
3577aa1b 1519 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
4da19633 1520 rtl_writephy(tp, 0x17, 0x2138);
1521 rtl_writephy(tp, 0x0e, 0x0260);
3577aa1b 1522 } else {
4da19633 1523 rtl_writephy(tp, 0x17, 0x2108);
1524 rtl_writephy(tp, 0x0e, 0x0000);
3577aa1b 1525 }
1526 }
1527
54405cde
ON		 1528 rc = 0;
1529out:
1530 return rc;
1da177e4
LT		 1531}
1532
1533static int rtl8169_set_speed(struct net_device *dev,
54405cde 1534 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1da177e4
LT		 1535{
1536 struct rtl8169_private *tp = netdev_priv(dev);
1537 int ret;
1538
54405cde 1539 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
4876cc1e
FR		 1540 if (ret < 0)
1541 goto out;
1da177e4 1542
4876cc1e
FR		 1543 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1544 (advertising & ADVERTISED_1000baseT_Full)) {
1da177e4 1545 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
4876cc1e
FR		 1546 }
1547out:
1da177e4
LT		 1548 return ret;
1549}
1550
1551static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1552{
1553 struct rtl8169_private *tp = netdev_priv(dev);
1554 unsigned long flags;
1555 int ret;
1556
4876cc1e
FR		 1557 del_timer_sync(&tp->timer);
1558
1da177e4 1559 spin_lock_irqsave(&tp->lock, flags);
cecb5fd7 1560 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
25db0338 1561 cmd->duplex, cmd->advertising);
1da177e4 1562 spin_unlock_irqrestore(&tp->lock, flags);
5b0384f4 1563
1da177e4
LT		 1564 return ret;
1565}
1566
c8f44aff
MM		 1567static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1568 netdev_features_t features)
1da177e4 1569{
d58d46b5
FR		 1570 struct rtl8169_private *tp = netdev_priv(dev);
1571
2b7b4318 1572 if (dev->mtu > TD_MSS_MAX)
350fb32a 1573 features &= ~NETIF_F_ALL_TSO;
1da177e4 1574
d58d46b5
FR		 1575 if (dev->mtu > JUMBO_1K &&
1576 !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1577 features &= ~NETIF_F_IP_CSUM;
1578
350fb32a 1579 return features;
1da177e4
LT		 1580}
1581
c8f44aff
MM		 1582static int rtl8169_set_features(struct net_device *dev,
1583 netdev_features_t features)
1da177e4
LT		 1584{
1585 struct rtl8169_private *tp = netdev_priv(dev);
1586 void __iomem *ioaddr = tp->mmio_addr;
1587 unsigned long flags;
1588
1589 spin_lock_irqsave(&tp->lock, flags);
1590
350fb32a 1591 if (features & NETIF_F_RXCSUM)
1da177e4
LT		 1592 tp->cp_cmd |= RxChkSum;
1593 else
1594 tp->cp_cmd &= ~RxChkSum;
1595
350fb32a
MM		 1596 if (dev->features & NETIF_F_HW_VLAN_RX)
1597 tp->cp_cmd |= RxVlan;
1598 else
1599 tp->cp_cmd &= ~RxVlan;
1600
1da177e4
LT		 1601 RTL_W16(CPlusCmd, tp->cp_cmd);
1602 RTL_R16(CPlusCmd);
1603
1604 spin_unlock_irqrestore(&tp->lock, flags);
1605
1606 return 0;
1607}
1608
1da177e4
LT		 1609static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1610 struct sk_buff *skb)
1611{
eab6d18d 1612 return (vlan_tx_tag_present(skb)) ?
1da177e4
LT		 1613 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1614}
1615
7a8fc77b 1616static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1da177e4
LT		 1617{
1618 u32 opts2 = le32_to_cpu(desc->opts2);
1da177e4 1619
7a8fc77b
FR		 1620 if (opts2 & RxVlanTag)
1621 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
2edae08e 1622
1da177e4 1623 desc->opts2 = 0;
1da177e4
LT		 1624}
1625
ccdffb9a 1626static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1627{
1628 struct rtl8169_private *tp = netdev_priv(dev);
1629 void __iomem *ioaddr = tp->mmio_addr;
1630 u32 status;
1631
1632 cmd->supported =
1633 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1634 cmd->port = PORT_FIBRE;
1635 cmd->transceiver = XCVR_INTERNAL;
1636
1637 status = RTL_R32(TBICSR);
1638 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1639 cmd->autoneg = !!(status & TBINwEnable);
1640
70739497 1641 ethtool_cmd_speed_set(cmd, SPEED_1000);
1da177e4 1642 cmd->duplex = DUPLEX_FULL; /* Always set */
ccdffb9a
FR		 1643
1644 return 0;
1da177e4
LT		 1645}
1646
ccdffb9a 1647static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1648{
1649 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a
FR		 1650
1651 return mii_ethtool_gset(&tp->mii, cmd);
1da177e4
LT		 1652}
1653
1654static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1655{
1656 struct rtl8169_private *tp = netdev_priv(dev);
1657 unsigned long flags;
ccdffb9a 1658 int rc;
1da177e4
LT		 1659
1660 spin_lock_irqsave(&tp->lock, flags);
1661
ccdffb9a 1662 rc = tp->get_settings(dev, cmd);
1da177e4
LT		 1663
1664 spin_unlock_irqrestore(&tp->lock, flags);
ccdffb9a 1665 return rc;
1da177e4
LT		 1666}
1667
1668static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1669 void *p)
1670{
5b0384f4
FR		 1671 struct rtl8169_private *tp = netdev_priv(dev);
1672 unsigned long flags;
1da177e4 1673
5b0384f4
FR		 1674 if (regs->len > R8169_REGS_SIZE)
1675 regs->len = R8169_REGS_SIZE;
1da177e4 1676
5b0384f4
FR		 1677 spin_lock_irqsave(&tp->lock, flags);
1678 memcpy_fromio(p, tp->mmio_addr, regs->len);
1679 spin_unlock_irqrestore(&tp->lock, flags);
1da177e4
LT		 1680}
1681
b57b7e5a
SH		 1682static u32 rtl8169_get_msglevel(struct net_device *dev)
1683{
1684 struct rtl8169_private *tp = netdev_priv(dev);
1685
1686 return tp->msg_enable;
1687}
1688
1689static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1690{
1691 struct rtl8169_private *tp = netdev_priv(dev);
1692
1693 tp->msg_enable = value;
1694}
1695
d4a3a0fc
SH		 1696static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1697 "tx_packets",
1698 "rx_packets",
1699 "tx_errors",
1700 "rx_errors",
1701 "rx_missed",
1702 "align_errors",
1703 "tx_single_collisions",
1704 "tx_multi_collisions",
1705 "unicast",
1706 "broadcast",
1707 "multicast",
1708 "tx_aborted",
1709 "tx_underrun",
1710};
1711
b9f2c044 1712static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1713{
b9f2c044
JG		 1714 switch (sset) {
1715 case ETH_SS_STATS:
1716 return ARRAY_SIZE(rtl8169_gstrings);
1717 default:
1718 return -EOPNOTSUPP;
1719 }
d4a3a0fc
SH		 1720}
1721
355423d0 1722static void rtl8169_update_counters(struct net_device *dev)
d4a3a0fc
SH		 1723{
1724 struct rtl8169_private *tp = netdev_priv(dev);
1725 void __iomem *ioaddr = tp->mmio_addr;
cecb5fd7 1726 struct device *d = &tp->pci_dev->dev;
d4a3a0fc
SH		 1727 struct rtl8169_counters *counters;
1728 dma_addr_t paddr;
1729 u32 cmd;
355423d0 1730 int wait = 1000;
d4a3a0fc 1731
355423d0
IV		 1732 /*
1733 * Some chips are unable to dump tally counters when the receiver
1734 * is disabled.
1735 */
1736 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1737 return;
d4a3a0fc 1738
48addcc9 1739 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
d4a3a0fc
SH		 1740 if (!counters)
1741 return;
1742
1743 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
284901a9 1744 cmd = (u64)paddr & DMA_BIT_MASK(32);
d4a3a0fc
SH		 1745 RTL_W32(CounterAddrLow, cmd);
1746 RTL_W32(CounterAddrLow, cmd | CounterDump);
1747
355423d0
IV		 1748 while (wait--) {
1749 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
355423d0 1750 memcpy(&tp->counters, counters, sizeof(*counters));
d4a3a0fc 1751 break;
355423d0
IV		 1752 }
1753 udelay(10);
d4a3a0fc
SH		 1754 }
1755
1756 RTL_W32(CounterAddrLow, 0);
1757 RTL_W32(CounterAddrHigh, 0);
1758
48addcc9 1759 dma_free_coherent(d, sizeof(*counters), counters, paddr);
d4a3a0fc
SH		 1760}
1761
355423d0
IV		 1762static void rtl8169_get_ethtool_stats(struct net_device *dev,
1763 struct ethtool_stats *stats, u64 *data)
1764{
1765 struct rtl8169_private *tp = netdev_priv(dev);
1766
1767 ASSERT_RTNL();
1768
1769 rtl8169_update_counters(dev);
1770
1771 data[0] = le64_to_cpu(tp->counters.tx_packets);
1772 data[1] = le64_to_cpu(tp->counters.rx_packets);
1773 data[2] = le64_to_cpu(tp->counters.tx_errors);
1774 data[3] = le32_to_cpu(tp->counters.rx_errors);
1775 data[4] = le16_to_cpu(tp->counters.rx_missed);
1776 data[5] = le16_to_cpu(tp->counters.align_errors);
1777 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1778 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1779 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1780 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1781 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1782 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1783 data[12] = le16_to_cpu(tp->counters.tx_underun);
1784}
1785
d4a3a0fc
SH		 1786static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1787{
1788 switch(stringset) {
1789 case ETH_SS_STATS:
1790 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1791 break;
1792 }
1793}
1794
7282d491 1795static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 1796 .get_drvinfo = rtl8169_get_drvinfo,
1797 .get_regs_len = rtl8169_get_regs_len,
1798 .get_link = ethtool_op_get_link,
1799 .get_settings = rtl8169_get_settings,
1800 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 1801 .get_msglevel = rtl8169_get_msglevel,
1802 .set_msglevel = rtl8169_set_msglevel,
1da177e4 1803 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1804 .get_wol = rtl8169_get_wol,
1805 .set_wol = rtl8169_set_wol,
d4a3a0fc 1806 .get_strings = rtl8169_get_strings,
b9f2c044 1807 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 1808 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1da177e4
LT		 1809};
1810
07d3f51f 1811static void rtl8169_get_mac_version(struct rtl8169_private *tp,
5d320a20 1812 struct net_device *dev, u8 default_version)
1da177e4 1813{
5d320a20 1814 void __iomem *ioaddr = tp->mmio_addr;
0e485150
FR		 1815 /*
1816 * The driver currently handles the 8168Bf and the 8168Be identically
1817 * but they can be identified more specifically through the test below
1818 * if needed:
1819 *
1820 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 1821 *
1822 * Same thing for the 8101Eb and the 8101Ec:
1823 *
1824 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 1825 */
3744100e 1826 static const struct rtl_mac_info {
1da177e4 1827 u32 mask;
e3cf0cc0 1828 u32 val;
1da177e4
LT		 1829 int mac_version;
1830 } mac_info[] = {
c2218925
HW		 1831 /* 8168F family. */
1832 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
1833 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
1834
01dc7fec 1835 /* 8168E family. */
70090424 1836 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
01dc7fec 1837 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
1838 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
1839 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
1840
5b538df9 1841 /* 8168D family. */
daf9df6d 1842 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1843 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
daf9df6d 1844 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
5b538df9 1845
e6de30d6 1846 /* 8168DP family. */
1847 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1848 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
4804b3b3 1849 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
e6de30d6 1850
ef808d50 1851 /* 8168C family. */
17c99297 1852 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
ef3386f0 1853 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 1854 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 1855 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 1856 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1857 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 1858 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
6fb07058 1859 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
ef808d50 1860 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 1861
1862 /* 8168B family. */
1863 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1864 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1865 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1866 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1867
1868 /* 8101 family. */
36a0e6c2 1869 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
5a5e4443
HW		 1870 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
1871 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
1872 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2857ffb7
FR		 1873 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1874 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1875 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1876 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1877 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1878 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 1879 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 1880 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 1881 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 1882 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1883 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 1884 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1885 /* FIXME: where did these entries come from ? -- FR */
1886 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1887 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1888
1889 /* 8110 family. */
1890 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1891 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1892 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1893 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1894 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1895 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1896
f21b75e9
JD		 1897 /* Catch-all */
1898 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
3744100e
FR		 1899 };
1900 const struct rtl_mac_info *p = mac_info;
1da177e4
LT		 1901 u32 reg;
1902
e3cf0cc0
FR		 1903 reg = RTL_R32(TxConfig);
1904 while ((reg & p->mask) != p->val)
1da177e4
LT		 1905 p++;
1906 tp->mac_version = p->mac_version;
5d320a20
FR		 1907
1908 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
1909 netif_notice(tp, probe, dev,
1910 "unknown MAC, using family default\n");
1911 tp->mac_version = default_version;
1912 }
1da177e4
LT		 1913}
1914
1915static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1916{
bcf0bf90 1917 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 1918}
1919
867763c1
FR		 1920struct phy_reg {
1921 u16 reg;
1922 u16 val;
1923};
1924
4da19633 1925static void rtl_writephy_batch(struct rtl8169_private *tp,
1926 const struct phy_reg *regs, int len)
867763c1
FR		 1927{
1928 while (len-- > 0) {
4da19633 1929 rtl_writephy(tp, regs->reg, regs->val);
867763c1
FR		 1930 regs++;
1931 }
1932}
1933
bca03d5f 1934#define PHY_READ 0x00000000
1935#define PHY_DATA_OR 0x10000000
1936#define PHY_DATA_AND 0x20000000
1937#define PHY_BJMPN 0x30000000
1938#define PHY_READ_EFUSE 0x40000000
1939#define PHY_READ_MAC_BYTE 0x50000000
1940#define PHY_WRITE_MAC_BYTE 0x60000000
1941#define PHY_CLEAR_READCOUNT 0x70000000
1942#define PHY_WRITE 0x80000000
1943#define PHY_READCOUNT_EQ_SKIP 0x90000000
1944#define PHY_COMP_EQ_SKIPN 0xa0000000
1945#define PHY_COMP_NEQ_SKIPN 0xb0000000
1946#define PHY_WRITE_PREVIOUS 0xc0000000
1947#define PHY_SKIPN 0xd0000000
1948#define PHY_DELAY_MS 0xe0000000
1949#define PHY_WRITE_ERI_WORD 0xf0000000
1950
960aee6c
HW		 1951struct fw_info {
1952 u32 magic;
1953 char version[RTL_VER_SIZE];
1954 __le32 fw_start;
1955 __le32 fw_len;
1956 u8 chksum;
1957} __packed;
1958
1c361efb
FR		 1959#define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
1960
1961static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
bca03d5f 1962{
b6ffd97f 1963 const struct firmware *fw = rtl_fw->fw;
960aee6c 1964 struct fw_info *fw_info = (struct fw_info *)fw->data;
1c361efb
FR		 1965 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
1966 char *version = rtl_fw->version;
1967 bool rc = false;
1968
1969 if (fw->size < FW_OPCODE_SIZE)
1970 goto out;
960aee6c
HW		 1971
1972 if (!fw_info->magic) {
1973 size_t i, size, start;
1974 u8 checksum = 0;
1975
1976 if (fw->size < sizeof(*fw_info))
1977 goto out;
1978
1979 for (i = 0; i < fw->size; i++)
1980 checksum += fw->data[i];
1981 if (checksum != 0)
1982 goto out;
1983
1984 start = le32_to_cpu(fw_info->fw_start);
1985 if (start > fw->size)
1986 goto out;
1987
1988 size = le32_to_cpu(fw_info->fw_len);
1989 if (size > (fw->size - start) / FW_OPCODE_SIZE)
1990 goto out;
1991
1992 memcpy(version, fw_info->version, RTL_VER_SIZE);
1993
1994 pa->code = (__le32 *)(fw->data + start);
1995 pa->size = size;
1996 } else {
1c361efb
FR		 1997 if (fw->size % FW_OPCODE_SIZE)
1998 goto out;
1999
2000 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2001
2002 pa->code = (__le32 *)fw->data;
2003 pa->size = fw->size / FW_OPCODE_SIZE;
2004 }
2005 version[RTL_VER_SIZE - 1] = 0;
2006
2007 rc = true;
2008out:
2009 return rc;
2010}
2011
fd112f2e
FR		 2012static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2013 struct rtl_fw_phy_action *pa)
1c361efb 2014{
fd112f2e 2015 bool rc = false;
1c361efb 2016 size_t index;
bca03d5f 2017
1c361efb
FR		 2018 for (index = 0; index < pa->size; index++) {
2019 u32 action = le32_to_cpu(pa->code[index]);
42b82dc1 2020 u32 regno = (action & 0x0fff0000) >> 16;
bca03d5f 2021
42b82dc1 2022 switch(action & 0xf0000000) {
2023 case PHY_READ:
2024 case PHY_DATA_OR:
2025 case PHY_DATA_AND:
2026 case PHY_READ_EFUSE:
2027 case PHY_CLEAR_READCOUNT:
2028 case PHY_WRITE:
2029 case PHY_WRITE_PREVIOUS:
2030 case PHY_DELAY_MS:
2031 break;
2032
2033 case PHY_BJMPN:
2034 if (regno > index) {
fd112f2e 2035 netif_err(tp, ifup, tp->dev,
cecb5fd7 2036 "Out of range of firmware\n");
fd112f2e 2037 goto out;
42b82dc1 2038 }
2039 break;
2040 case PHY_READCOUNT_EQ_SKIP:
1c361efb 2041 if (index + 2 >= pa->size) {
fd112f2e 2042 netif_err(tp, ifup, tp->dev,
cecb5fd7 2043 "Out of range of firmware\n");
fd112f2e 2044 goto out;
42b82dc1 2045 }
2046 break;
2047 case PHY_COMP_EQ_SKIPN:
2048 case PHY_COMP_NEQ_SKIPN:
2049 case PHY_SKIPN:
1c361efb 2050 if (index + 1 + regno >= pa->size) {
fd112f2e 2051 netif_err(tp, ifup, tp->dev,
cecb5fd7 2052 "Out of range of firmware\n");
fd112f2e 2053 goto out;
42b82dc1 2054 }
bca03d5f 2055 break;
2056
42b82dc1 2057 case PHY_READ_MAC_BYTE:
2058 case PHY_WRITE_MAC_BYTE:
2059 case PHY_WRITE_ERI_WORD:
2060 default:
fd112f2e 2061 netif_err(tp, ifup, tp->dev,
42b82dc1 2062 "Invalid action 0x%08x\n", action);
fd112f2e 2063 goto out;
bca03d5f 2064 }
2065 }
fd112f2e
FR		 2066 rc = true;
2067out:
2068 return rc;
2069}
bca03d5f 2070
fd112f2e
FR		 2071static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2072{
2073 struct net_device *dev = tp->dev;
2074 int rc = -EINVAL;
2075
2076 if (!rtl_fw_format_ok(tp, rtl_fw)) {
2077 netif_err(tp, ifup, dev, "invalid firwmare\n");
2078 goto out;
2079 }
2080
2081 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2082 rc = 0;
2083out:
2084 return rc;
2085}
2086
2087static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2088{
2089 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2090 u32 predata, count;
2091 size_t index;
2092
2093 predata = count = 0;
42b82dc1 2094
1c361efb
FR		 2095 for (index = 0; index < pa->size; ) {
2096 u32 action = le32_to_cpu(pa->code[index]);
bca03d5f 2097 u32 data = action & 0x0000ffff;
42b82dc1 2098 u32 regno = (action & 0x0fff0000) >> 16;
2099
2100 if (!action)
2101 break;
bca03d5f 2102
2103 switch(action & 0xf0000000) {
42b82dc1 2104 case PHY_READ:
2105 predata = rtl_readphy(tp, regno);
2106 count++;
2107 index++;
2108 break;
2109 case PHY_DATA_OR:
2110 predata |= data;
2111 index++;
2112 break;
2113 case PHY_DATA_AND:
2114 predata &= data;
2115 index++;
2116 break;
2117 case PHY_BJMPN:
2118 index -= regno;
2119 break;
2120 case PHY_READ_EFUSE:
2121 predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
2122 index++;
2123 break;
2124 case PHY_CLEAR_READCOUNT:
2125 count = 0;
2126 index++;
2127 break;
bca03d5f 2128 case PHY_WRITE:
42b82dc1 2129 rtl_writephy(tp, regno, data);
2130 index++;
2131 break;
2132 case PHY_READCOUNT_EQ_SKIP:
cecb5fd7 2133 index += (count == data) ? 2 : 1;
bca03d5f 2134 break;
42b82dc1 2135 case PHY_COMP_EQ_SKIPN:
2136 if (predata == data)
2137 index += regno;
2138 index++;
2139 break;
2140 case PHY_COMP_NEQ_SKIPN:
2141 if (predata != data)
2142 index += regno;
2143 index++;
2144 break;
2145 case PHY_WRITE_PREVIOUS:
2146 rtl_writephy(tp, regno, predata);
2147 index++;
2148 break;
2149 case PHY_SKIPN:
2150 index += regno + 1;
2151 break;
2152 case PHY_DELAY_MS:
2153 mdelay(data);
2154 index++;
2155 break;
2156
2157 case PHY_READ_MAC_BYTE:
2158 case PHY_WRITE_MAC_BYTE:
2159 case PHY_WRITE_ERI_WORD:
bca03d5f 2160 default:
2161 BUG();
2162 }
2163 }
2164}
2165
f1e02ed1 2166static void rtl_release_firmware(struct rtl8169_private *tp)
2167{
b6ffd97f
FR		 2168 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2169 release_firmware(tp->rtl_fw->fw);
2170 kfree(tp->rtl_fw);
2171 }
2172 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
f1e02ed1 2173}
2174
953a12cc 2175static void rtl_apply_firmware(struct rtl8169_private *tp)
f1e02ed1 2176{
b6ffd97f 2177 struct rtl_fw *rtl_fw = tp->rtl_fw;
f1e02ed1 2178
2179 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
b6ffd97f
FR		 2180 if (!IS_ERR_OR_NULL(rtl_fw))
2181 rtl_phy_write_fw(tp, rtl_fw);
953a12cc
FR		 2182}
2183
2184static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2185{
2186 if (rtl_readphy(tp, reg) != val)
2187 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2188 else
2189 rtl_apply_firmware(tp);
f1e02ed1 2190}
2191
4da19633 2192static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1da177e4 2193{
350f7596 2194 static const struct phy_reg phy_reg_init[] = {
0b9b571d 2195 { 0x1f, 0x0001 },
2196 { 0x06, 0x006e },
2197 { 0x08, 0x0708 },
2198 { 0x15, 0x4000 },
2199 { 0x18, 0x65c7 },
1da177e4 2200
0b9b571d 2201 { 0x1f, 0x0001 },
2202 { 0x03, 0x00a1 },
2203 { 0x02, 0x0008 },
2204 { 0x01, 0x0120 },
2205 { 0x00, 0x1000 },
2206 { 0x04, 0x0800 },
2207 { 0x04, 0x0000 },
1da177e4 2208
0b9b571d 2209 { 0x03, 0xff41 },
2210 { 0x02, 0xdf60 },
2211 { 0x01, 0x0140 },
2212 { 0x00, 0x0077 },
2213 { 0x04, 0x7800 },
2214 { 0x04, 0x7000 },
2215
2216 { 0x03, 0x802f },
2217 { 0x02, 0x4f02 },
2218 { 0x01, 0x0409 },
2219 { 0x00, 0xf0f9 },
2220 { 0x04, 0x9800 },
2221 { 0x04, 0x9000 },
2222
2223 { 0x03, 0xdf01 },
2224 { 0x02, 0xdf20 },
2225 { 0x01, 0xff95 },
2226 { 0x00, 0xba00 },
2227 { 0x04, 0xa800 },
2228 { 0x04, 0xa000 },
2229
2230 { 0x03, 0xff41 },
2231 { 0x02, 0xdf20 },
2232 { 0x01, 0x0140 },
2233 { 0x00, 0x00bb },
2234 { 0x04, 0xb800 },
2235 { 0x04, 0xb000 },
2236
2237 { 0x03, 0xdf41 },
2238 { 0x02, 0xdc60 },
2239 { 0x01, 0x6340 },
2240 { 0x00, 0x007d },
2241 { 0x04, 0xd800 },
2242 { 0x04, 0xd000 },
2243
2244 { 0x03, 0xdf01 },
2245 { 0x02, 0xdf20 },
2246 { 0x01, 0x100a },
2247 { 0x00, 0xa0ff },
2248 { 0x04, 0xf800 },
2249 { 0x04, 0xf000 },
2250
2251 { 0x1f, 0x0000 },
2252 { 0x0b, 0x0000 },
2253 { 0x00, 0x9200 }
2254 };
1da177e4 2255
4da19633 2256 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1da177e4
LT		 2257}
2258
4da19633 2259static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
5615d9f1 2260{
350f7596 2261 static const struct phy_reg phy_reg_init[] = {
a441d7b6
FR		 2262 { 0x1f, 0x0002 },
2263 { 0x01, 0x90d0 },
2264 { 0x1f, 0x0000 }
2265 };
2266
4da19633 2267 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 2268}
2269
4da19633 2270static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2e955856 2271{
2272 struct pci_dev *pdev = tp->pci_dev;
2e955856 2273
ccbae55e
SS		 2274 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2275 (pdev->subsystem_device != 0xe000))
2e955856 2276 return;
2277
4da19633 2278 rtl_writephy(tp, 0x1f, 0x0001);
2279 rtl_writephy(tp, 0x10, 0xf01b);
2280 rtl_writephy(tp, 0x1f, 0x0000);
2e955856 2281}
2282
4da19633 2283static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2e955856 2284{
350f7596 2285 static const struct phy_reg phy_reg_init[] = {
2e955856 2286 { 0x1f, 0x0001 },
2287 { 0x04, 0x0000 },
2288 { 0x03, 0x00a1 },
2289 { 0x02, 0x0008 },
2290 { 0x01, 0x0120 },
2291 { 0x00, 0x1000 },
2292 { 0x04, 0x0800 },
2293 { 0x04, 0x9000 },
2294 { 0x03, 0x802f },
2295 { 0x02, 0x4f02 },
2296 { 0x01, 0x0409 },
2297 { 0x00, 0xf099 },
2298 { 0x04, 0x9800 },
2299 { 0x04, 0xa000 },
2300 { 0x03, 0xdf01 },
2301 { 0x02, 0xdf20 },
2302 { 0x01, 0xff95 },
2303 { 0x00, 0xba00 },
2304 { 0x04, 0xa800 },
2305 { 0x04, 0xf000 },
2306 { 0x03, 0xdf01 },
2307 { 0x02, 0xdf20 },
2308 { 0x01, 0x101a },
2309 { 0x00, 0xa0ff },
2310 { 0x04, 0xf800 },
2311 { 0x04, 0x0000 },
2312 { 0x1f, 0x0000 },
2313
2314 { 0x1f, 0x0001 },
2315 { 0x10, 0xf41b },
2316 { 0x14, 0xfb54 },
2317 { 0x18, 0xf5c7 },
2318 { 0x1f, 0x0000 },
2319
2320 { 0x1f, 0x0001 },
2321 { 0x17, 0x0cc0 },
2322 { 0x1f, 0x0000 }
2323 };
2324
4da19633 2325 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2e955856 2326
4da19633 2327 rtl8169scd_hw_phy_config_quirk(tp);
2e955856 2328}
2329
4da19633 2330static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
8c7006aa 2331{
350f7596 2332 static const struct phy_reg phy_reg_init[] = {
8c7006aa 2333 { 0x1f, 0x0001 },
2334 { 0x04, 0x0000 },
2335 { 0x03, 0x00a1 },
2336 { 0x02, 0x0008 },
2337 { 0x01, 0x0120 },
2338 { 0x00, 0x1000 },
2339 { 0x04, 0x0800 },
2340 { 0x04, 0x9000 },
2341 { 0x03, 0x802f },
2342 { 0x02, 0x4f02 },
2343 { 0x01, 0x0409 },
2344 { 0x00, 0xf099 },
2345 { 0x04, 0x9800 },
2346 { 0x04, 0xa000 },
2347 { 0x03, 0xdf01 },
2348 { 0x02, 0xdf20 },
2349 { 0x01, 0xff95 },
2350 { 0x00, 0xba00 },
2351 { 0x04, 0xa800 },
2352 { 0x04, 0xf000 },
2353 { 0x03, 0xdf01 },
2354 { 0x02, 0xdf20 },
2355 { 0x01, 0x101a },
2356 { 0x00, 0xa0ff },
2357 { 0x04, 0xf800 },
2358 { 0x04, 0x0000 },
2359 { 0x1f, 0x0000 },
2360
2361 { 0x1f, 0x0001 },
2362 { 0x0b, 0x8480 },
2363 { 0x1f, 0x0000 },
2364
2365 { 0x1f, 0x0001 },
2366 { 0x18, 0x67c7 },
2367 { 0x04, 0x2000 },
2368 { 0x03, 0x002f },
2369 { 0x02, 0x4360 },
2370 { 0x01, 0x0109 },
2371 { 0x00, 0x3022 },
2372 { 0x04, 0x2800 },
2373 { 0x1f, 0x0000 },
2374
2375 { 0x1f, 0x0001 },
2376 { 0x17, 0x0cc0 },
2377 { 0x1f, 0x0000 }
2378 };
2379
4da19633 2380 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
8c7006aa 2381}
2382
4da19633 2383static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
236b8082 2384{
350f7596 2385 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2386 { 0x10, 0xf41b },
2387 { 0x1f, 0x0000 }
2388 };
2389
4da19633 2390 rtl_writephy(tp, 0x1f, 0x0001);
2391 rtl_patchphy(tp, 0x16, 1 << 0);
236b8082 2392
4da19633 2393 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2394}
2395
4da19633 2396static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
236b8082 2397{
350f7596 2398 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2399 { 0x1f, 0x0001 },
2400 { 0x10, 0xf41b },
2401 { 0x1f, 0x0000 }
2402 };
2403
4da19633 2404 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2405}
2406
4da19633 2407static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2408{
350f7596 2409 static const struct phy_reg phy_reg_init[] = {
867763c1
FR		 2410 { 0x1f, 0x0000 },
2411 { 0x1d, 0x0f00 },
2412 { 0x1f, 0x0002 },
2413 { 0x0c, 0x1ec8 },
2414 { 0x1f, 0x0000 }
2415 };
2416
4da19633 2417 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
867763c1
FR		 2418}
2419
4da19633 2420static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
ef3386f0 2421{
350f7596 2422 static const struct phy_reg phy_reg_init[] = {
ef3386f0
FR		 2423 { 0x1f, 0x0001 },
2424 { 0x1d, 0x3d98 },
2425 { 0x1f, 0x0000 }
2426 };
2427
4da19633 2428 rtl_writephy(tp, 0x1f, 0x0000);
2429 rtl_patchphy(tp, 0x14, 1 << 5);
2430 rtl_patchphy(tp, 0x0d, 1 << 5);
ef3386f0 2431
4da19633 2432 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
ef3386f0
FR		 2433}
2434
4da19633 2435static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2436{
350f7596 2437 static const struct phy_reg phy_reg_init[] = {
a3f80671
FR		 2438 { 0x1f, 0x0001 },
2439 { 0x12, 0x2300 },
867763c1
FR		 2440 { 0x1f, 0x0002 },
2441 { 0x00, 0x88d4 },
2442 { 0x01, 0x82b1 },
2443 { 0x03, 0x7002 },
2444 { 0x08, 0x9e30 },
2445 { 0x09, 0x01f0 },
2446 { 0x0a, 0x5500 },
2447 { 0x0c, 0x00c8 },
2448 { 0x1f, 0x0003 },
2449 { 0x12, 0xc096 },
2450 { 0x16, 0x000a },
f50d4275
FR		 2451 { 0x1f, 0x0000 },
2452 { 0x1f, 0x0000 },
2453 { 0x09, 0x2000 },
2454 { 0x09, 0x0000 }
867763c1
FR		 2455 };
2456
4da19633 2457 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2458
4da19633 2459 rtl_patchphy(tp, 0x14, 1 << 5);
2460 rtl_patchphy(tp, 0x0d, 1 << 5);
2461 rtl_writephy(tp, 0x1f, 0x0000);
867763c1
FR		 2462}
2463
4da19633 2464static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
7da97ec9 2465{
350f7596 2466 static const struct phy_reg phy_reg_init[] = {
f50d4275 2467 { 0x1f, 0x0001 },
7da97ec9 2468 { 0x12, 0x2300 },
f50d4275
FR		 2469 { 0x03, 0x802f },
2470 { 0x02, 0x4f02 },
2471 { 0x01, 0x0409 },
2472 { 0x00, 0xf099 },
2473 { 0x04, 0x9800 },
2474 { 0x04, 0x9000 },
2475 { 0x1d, 0x3d98 },
7da97ec9
FR		 2476 { 0x1f, 0x0002 },
2477 { 0x0c, 0x7eb8 },
f50d4275
FR		 2478 { 0x06, 0x0761 },
2479 { 0x1f, 0x0003 },
2480 { 0x16, 0x0f0a },
7da97ec9
FR		 2481 { 0x1f, 0x0000 }
2482 };
2483
4da19633 2484 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2485
4da19633 2486 rtl_patchphy(tp, 0x16, 1 << 0);
2487 rtl_patchphy(tp, 0x14, 1 << 5);
2488 rtl_patchphy(tp, 0x0d, 1 << 5);
2489 rtl_writephy(tp, 0x1f, 0x0000);
7da97ec9
FR		 2490}
2491
4da19633 2492static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
197ff761 2493{
350f7596 2494 static const struct phy_reg phy_reg_init[] = {
197ff761
FR		 2495 { 0x1f, 0x0001 },
2496 { 0x12, 0x2300 },
2497 { 0x1d, 0x3d98 },
2498 { 0x1f, 0x0002 },
2499 { 0x0c, 0x7eb8 },
2500 { 0x06, 0x5461 },
2501 { 0x1f, 0x0003 },
2502 { 0x16, 0x0f0a },
2503 { 0x1f, 0x0000 }
2504 };
2505
4da19633 2506 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
197ff761 2507
4da19633 2508 rtl_patchphy(tp, 0x16, 1 << 0);
2509 rtl_patchphy(tp, 0x14, 1 << 5);
2510 rtl_patchphy(tp, 0x0d, 1 << 5);
2511 rtl_writephy(tp, 0x1f, 0x0000);
197ff761
FR		 2512}
2513
4da19633 2514static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
6fb07058 2515{
4da19633 2516 rtl8168c_3_hw_phy_config(tp);
6fb07058
FR		 2517}
2518
bca03d5f 2519static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
5b538df9 2520{
350f7596 2521 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2522 /* Channel Estimation */
5b538df9 2523 { 0x1f, 0x0001 },
daf9df6d 2524 { 0x06, 0x4064 },
2525 { 0x07, 0x2863 },
2526 { 0x08, 0x059c },
2527 { 0x09, 0x26b4 },
2528 { 0x0a, 0x6a19 },
2529 { 0x0b, 0xdcc8 },
2530 { 0x10, 0xf06d },
2531 { 0x14, 0x7f68 },
2532 { 0x18, 0x7fd9 },
2533 { 0x1c, 0xf0ff },
2534 { 0x1d, 0x3d9c },
5b538df9 2535 { 0x1f, 0x0003 },
daf9df6d 2536 { 0x12, 0xf49f },
2537 { 0x13, 0x070b },
2538 { 0x1a, 0x05ad },
bca03d5f 2539 { 0x14, 0x94c0 },
2540
2541 /*
2542 * Tx Error Issue
cecb5fd7 2543 * Enhance line driver power
bca03d5f 2544 */
5b538df9 2545 { 0x1f, 0x0002 },
daf9df6d 2546 { 0x06, 0x5561 },
2547 { 0x1f, 0x0005 },
2548 { 0x05, 0x8332 },
bca03d5f 2549 { 0x06, 0x5561 },
2550
2551 /*
2552 * Can not link to 1Gbps with bad cable
2553 * Decrease SNR threshold form 21.07dB to 19.04dB
2554 */
2555 { 0x1f, 0x0001 },
2556 { 0x17, 0x0cc0 },
daf9df6d 2557
5b538df9 2558 { 0x1f, 0x0000 },
bca03d5f 2559 { 0x0d, 0xf880 }
daf9df6d 2560 };
bca03d5f 2561 void __iomem *ioaddr = tp->mmio_addr;
daf9df6d 2562
4da19633 2563 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
daf9df6d 2564
bca03d5f 2565 /*
2566 * Rx Error Issue
2567 * Fine Tune Switching regulator parameter
2568 */
4da19633 2569 rtl_writephy(tp, 0x1f, 0x0002);
2570 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2571 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
daf9df6d 2572
daf9df6d 2573 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
350f7596 2574 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2575 { 0x1f, 0x0002 },
2576 { 0x05, 0x669a },
2577 { 0x1f, 0x0005 },
2578 { 0x05, 0x8330 },
2579 { 0x06, 0x669a },
2580 { 0x1f, 0x0002 }
2581 };
2582 int val;
2583
4da19633 2584 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2585
4da19633 2586 val = rtl_readphy(tp, 0x0d);
daf9df6d 2587
2588 if ((val & 0x00ff) != 0x006c) {
350f7596 2589 static const u32 set[] = {
daf9df6d 2590 0x0065, 0x0066, 0x0067, 0x0068,
2591 0x0069, 0x006a, 0x006b, 0x006c
2592 };
2593 int i;
2594
4da19633 2595 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2596
2597 val &= 0xff00;
2598 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2599 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2600 }
2601 } else {
350f7596 2602 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2603 { 0x1f, 0x0002 },
2604 { 0x05, 0x6662 },
2605 { 0x1f, 0x0005 },
2606 { 0x05, 0x8330 },
2607 { 0x06, 0x6662 }
2608 };
2609
4da19633 2610 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2611 }
2612
bca03d5f 2613 /* RSET couple improve */
4da19633 2614 rtl_writephy(tp, 0x1f, 0x0002);
2615 rtl_patchphy(tp, 0x0d, 0x0300);
2616 rtl_patchphy(tp, 0x0f, 0x0010);
daf9df6d 2617
bca03d5f 2618 /* Fine tune PLL performance */
4da19633 2619 rtl_writephy(tp, 0x1f, 0x0002);
2620 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2621 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2622
4da19633 2623 rtl_writephy(tp, 0x1f, 0x0005);
2624 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2625
2626 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
bca03d5f 2627
4da19633 2628 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2629}
2630
bca03d5f 2631static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2632{
350f7596 2633 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2634 /* Channel Estimation */
daf9df6d 2635 { 0x1f, 0x0001 },
2636 { 0x06, 0x4064 },
2637 { 0x07, 0x2863 },
2638 { 0x08, 0x059c },
2639 { 0x09, 0x26b4 },
2640 { 0x0a, 0x6a19 },
2641 { 0x0b, 0xdcc8 },
2642 { 0x10, 0xf06d },
2643 { 0x14, 0x7f68 },
2644 { 0x18, 0x7fd9 },
2645 { 0x1c, 0xf0ff },
2646 { 0x1d, 0x3d9c },
2647 { 0x1f, 0x0003 },
2648 { 0x12, 0xf49f },
2649 { 0x13, 0x070b },
2650 { 0x1a, 0x05ad },
2651 { 0x14, 0x94c0 },
2652
bca03d5f 2653 /*
2654 * Tx Error Issue
cecb5fd7 2655 * Enhance line driver power
bca03d5f 2656 */
daf9df6d 2657 { 0x1f, 0x0002 },
2658 { 0x06, 0x5561 },
2659 { 0x1f, 0x0005 },
2660 { 0x05, 0x8332 },
bca03d5f 2661 { 0x06, 0x5561 },
2662
2663 /*
2664 * Can not link to 1Gbps with bad cable
2665 * Decrease SNR threshold form 21.07dB to 19.04dB
2666 */
2667 { 0x1f, 0x0001 },
2668 { 0x17, 0x0cc0 },
daf9df6d 2669
2670 { 0x1f, 0x0000 },
bca03d5f 2671 { 0x0d, 0xf880 }
5b538df9 2672 };
bca03d5f 2673 void __iomem *ioaddr = tp->mmio_addr;
5b538df9 2674
4da19633 2675 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
5b538df9 2676
daf9df6d 2677 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
350f7596 2678 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2679 { 0x1f, 0x0002 },
2680 { 0x05, 0x669a },
5b538df9 2681 { 0x1f, 0x0005 },
daf9df6d 2682 { 0x05, 0x8330 },
2683 { 0x06, 0x669a },
2684
2685 { 0x1f, 0x0002 }
2686 };
2687 int val;
2688
4da19633 2689 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2690
4da19633 2691 val = rtl_readphy(tp, 0x0d);
daf9df6d 2692 if ((val & 0x00ff) != 0x006c) {
b6bc7650 2693 static const u32 set[] = {
daf9df6d 2694 0x0065, 0x0066, 0x0067, 0x0068,
2695 0x0069, 0x006a, 0x006b, 0x006c
2696 };
2697 int i;
2698
4da19633 2699 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2700
2701 val &= 0xff00;
2702 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2703 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2704 }
2705 } else {
350f7596 2706 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2707 { 0x1f, 0x0002 },
2708 { 0x05, 0x2642 },
5b538df9 2709 { 0x1f, 0x0005 },
daf9df6d 2710 { 0x05, 0x8330 },
2711 { 0x06, 0x2642 }
5b538df9
FR		 2712 };
2713
4da19633 2714 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2715 }
2716
bca03d5f 2717 /* Fine tune PLL performance */
4da19633 2718 rtl_writephy(tp, 0x1f, 0x0002);
2719 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2720 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2721
bca03d5f 2722 /* Switching regulator Slew rate */
4da19633 2723 rtl_writephy(tp, 0x1f, 0x0002);
2724 rtl_patchphy(tp, 0x0f, 0x0017);
daf9df6d 2725
4da19633 2726 rtl_writephy(tp, 0x1f, 0x0005);
2727 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2728
2729 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
bca03d5f 2730
4da19633 2731 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2732}
2733
4da19633 2734static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2735{
350f7596 2736 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2737 { 0x1f, 0x0002 },
2738 { 0x10, 0x0008 },
2739 { 0x0d, 0x006c },
2740
2741 { 0x1f, 0x0000 },
2742 { 0x0d, 0xf880 },
2743
2744 { 0x1f, 0x0001 },
2745 { 0x17, 0x0cc0 },
2746
2747 { 0x1f, 0x0001 },
2748 { 0x0b, 0xa4d8 },
2749 { 0x09, 0x281c },
2750 { 0x07, 0x2883 },
2751 { 0x0a, 0x6b35 },
2752 { 0x1d, 0x3da4 },
2753 { 0x1c, 0xeffd },
2754 { 0x14, 0x7f52 },
2755 { 0x18, 0x7fc6 },
2756 { 0x08, 0x0601 },
2757 { 0x06, 0x4063 },
2758 { 0x10, 0xf074 },
2759 { 0x1f, 0x0003 },
2760 { 0x13, 0x0789 },
2761 { 0x12, 0xf4bd },
2762 { 0x1a, 0x04fd },
2763 { 0x14, 0x84b0 },
2764 { 0x1f, 0x0000 },
2765 { 0x00, 0x9200 },
2766
2767 { 0x1f, 0x0005 },
2768 { 0x01, 0x0340 },
2769 { 0x1f, 0x0001 },
2770 { 0x04, 0x4000 },
2771 { 0x03, 0x1d21 },
2772 { 0x02, 0x0c32 },
2773 { 0x01, 0x0200 },
2774 { 0x00, 0x5554 },
2775 { 0x04, 0x4800 },
2776 { 0x04, 0x4000 },
2777 { 0x04, 0xf000 },
2778 { 0x03, 0xdf01 },
2779 { 0x02, 0xdf20 },
2780 { 0x01, 0x101a },
2781 { 0x00, 0xa0ff },
2782 { 0x04, 0xf800 },
2783 { 0x04, 0xf000 },
2784 { 0x1f, 0x0000 },
2785
2786 { 0x1f, 0x0007 },
2787 { 0x1e, 0x0023 },
2788 { 0x16, 0x0000 },
2789 { 0x1f, 0x0000 }
2790 };
2791
4da19633 2792 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2793}
2794
e6de30d6 2795static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2796{
2797 static const struct phy_reg phy_reg_init[] = {
2798 { 0x1f, 0x0001 },
2799 { 0x17, 0x0cc0 },
2800
2801 { 0x1f, 0x0007 },
2802 { 0x1e, 0x002d },
2803 { 0x18, 0x0040 },
2804 { 0x1f, 0x0000 }
2805 };
2806
2807 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2808 rtl_patchphy(tp, 0x0d, 1 << 5);
2809}
2810
70090424 2811static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
01dc7fec 2812{
2813 static const struct phy_reg phy_reg_init[] = {
2814 /* Enable Delay cap */
2815 { 0x1f, 0x0005 },
2816 { 0x05, 0x8b80 },
2817 { 0x06, 0xc896 },
2818 { 0x1f, 0x0000 },
2819
2820 /* Channel estimation fine tune */
2821 { 0x1f, 0x0001 },
2822 { 0x0b, 0x6c20 },
2823 { 0x07, 0x2872 },
2824 { 0x1c, 0xefff },
2825 { 0x1f, 0x0003 },
2826 { 0x14, 0x6420 },
2827 { 0x1f, 0x0000 },
2828
2829 /* Update PFM & 10M TX idle timer */
2830 { 0x1f, 0x0007 },
2831 { 0x1e, 0x002f },
2832 { 0x15, 0x1919 },
2833 { 0x1f, 0x0000 },
2834
2835 { 0x1f, 0x0007 },
2836 { 0x1e, 0x00ac },
2837 { 0x18, 0x0006 },
2838 { 0x1f, 0x0000 }
2839 };
2840
15ecd039
FR		 2841 rtl_apply_firmware(tp);
2842
01dc7fec 2843 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2844
2845 /* DCO enable for 10M IDLE Power */
2846 rtl_writephy(tp, 0x1f, 0x0007);
2847 rtl_writephy(tp, 0x1e, 0x0023);
2848 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2849 rtl_writephy(tp, 0x1f, 0x0000);
2850
2851 /* For impedance matching */
2852 rtl_writephy(tp, 0x1f, 0x0002);
2853 rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
cecb5fd7 2854 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 2855
2856 /* PHY auto speed down */
2857 rtl_writephy(tp, 0x1f, 0x0007);
2858 rtl_writephy(tp, 0x1e, 0x002d);
2859 rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2860 rtl_writephy(tp, 0x1f, 0x0000);
2861 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2862
2863 rtl_writephy(tp, 0x1f, 0x0005);
2864 rtl_writephy(tp, 0x05, 0x8b86);
2865 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2866 rtl_writephy(tp, 0x1f, 0x0000);
2867
2868 rtl_writephy(tp, 0x1f, 0x0005);
2869 rtl_writephy(tp, 0x05, 0x8b85);
2870 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2871 rtl_writephy(tp, 0x1f, 0x0007);
2872 rtl_writephy(tp, 0x1e, 0x0020);
2873 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2874 rtl_writephy(tp, 0x1f, 0x0006);
2875 rtl_writephy(tp, 0x00, 0x5a00);
2876 rtl_writephy(tp, 0x1f, 0x0000);
2877 rtl_writephy(tp, 0x0d, 0x0007);
2878 rtl_writephy(tp, 0x0e, 0x003c);
2879 rtl_writephy(tp, 0x0d, 0x4007);
2880 rtl_writephy(tp, 0x0e, 0x0000);
2881 rtl_writephy(tp, 0x0d, 0x0000);
2882}
2883
70090424
HW		 2884static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
2885{
2886 static const struct phy_reg phy_reg_init[] = {
2887 /* Enable Delay cap */
2888 { 0x1f, 0x0004 },
2889 { 0x1f, 0x0007 },
2890 { 0x1e, 0x00ac },
2891 { 0x18, 0x0006 },
2892 { 0x1f, 0x0002 },
2893 { 0x1f, 0x0000 },
2894 { 0x1f, 0x0000 },
2895
2896 /* Channel estimation fine tune */
2897 { 0x1f, 0x0003 },
2898 { 0x09, 0xa20f },
2899 { 0x1f, 0x0000 },
2900 { 0x1f, 0x0000 },
2901
2902 /* Green Setting */
2903 { 0x1f, 0x0005 },
2904 { 0x05, 0x8b5b },
2905 { 0x06, 0x9222 },
2906 { 0x05, 0x8b6d },
2907 { 0x06, 0x8000 },
2908 { 0x05, 0x8b76 },
2909 { 0x06, 0x8000 },
2910 { 0x1f, 0x0000 }
2911 };
2912
2913 rtl_apply_firmware(tp);
2914
2915 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2916
2917 /* For 4-corner performance improve */
2918 rtl_writephy(tp, 0x1f, 0x0005);
2919 rtl_writephy(tp, 0x05, 0x8b80);
2920 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2921 rtl_writephy(tp, 0x1f, 0x0000);
2922
2923 /* PHY auto speed down */
2924 rtl_writephy(tp, 0x1f, 0x0004);
2925 rtl_writephy(tp, 0x1f, 0x0007);
2926 rtl_writephy(tp, 0x1e, 0x002d);
2927 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
2928 rtl_writephy(tp, 0x1f, 0x0002);
2929 rtl_writephy(tp, 0x1f, 0x0000);
2930 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2931
2932 /* improve 10M EEE waveform */
2933 rtl_writephy(tp, 0x1f, 0x0005);
2934 rtl_writephy(tp, 0x05, 0x8b86);
2935 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2936 rtl_writephy(tp, 0x1f, 0x0000);
2937
2938 /* Improve 2-pair detection performance */
2939 rtl_writephy(tp, 0x1f, 0x0005);
2940 rtl_writephy(tp, 0x05, 0x8b85);
2941 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
2942 rtl_writephy(tp, 0x1f, 0x0000);
2943
2944 /* EEE setting */
2945 rtl_w1w0_eri(tp->mmio_addr, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003,
2946 ERIAR_EXGMAC);
2947 rtl_writephy(tp, 0x1f, 0x0005);
2948 rtl_writephy(tp, 0x05, 0x8b85);
2949 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2950 rtl_writephy(tp, 0x1f, 0x0004);
2951 rtl_writephy(tp, 0x1f, 0x0007);
2952 rtl_writephy(tp, 0x1e, 0x0020);
1b23a3e3 2953 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
70090424
HW		 2954 rtl_writephy(tp, 0x1f, 0x0002);
2955 rtl_writephy(tp, 0x1f, 0x0000);
2956 rtl_writephy(tp, 0x0d, 0x0007);
2957 rtl_writephy(tp, 0x0e, 0x003c);
2958 rtl_writephy(tp, 0x0d, 0x4007);
2959 rtl_writephy(tp, 0x0e, 0x0000);
2960 rtl_writephy(tp, 0x0d, 0x0000);
2961
2962 /* Green feature */
2963 rtl_writephy(tp, 0x1f, 0x0003);
2964 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
2965 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
2966 rtl_writephy(tp, 0x1f, 0x0000);
2967}
2968
c2218925
HW		 2969static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
2970{
2971 static const struct phy_reg phy_reg_init[] = {
2972 /* Channel estimation fine tune */
2973 { 0x1f, 0x0003 },
2974 { 0x09, 0xa20f },
2975 { 0x1f, 0x0000 },
2976
2977 /* Modify green table for giga & fnet */
2978 { 0x1f, 0x0005 },
2979 { 0x05, 0x8b55 },
2980 { 0x06, 0x0000 },
2981 { 0x05, 0x8b5e },
2982 { 0x06, 0x0000 },
2983 { 0x05, 0x8b67 },
2984 { 0x06, 0x0000 },
2985 { 0x05, 0x8b70 },
2986 { 0x06, 0x0000 },
2987 { 0x1f, 0x0000 },
2988 { 0x1f, 0x0007 },
2989 { 0x1e, 0x0078 },
2990 { 0x17, 0x0000 },
2991 { 0x19, 0x00fb },
2992 { 0x1f, 0x0000 },
2993
2994 /* Modify green table for 10M */
2995 { 0x1f, 0x0005 },
2996 { 0x05, 0x8b79 },
2997 { 0x06, 0xaa00 },
2998 { 0x1f, 0x0000 },
2999
3000 /* Disable hiimpedance detection (RTCT) */
3001 { 0x1f, 0x0003 },
3002 { 0x01, 0x328a },
3003 { 0x1f, 0x0000 }
3004 };
3005
3006 rtl_apply_firmware(tp);
3007
3008 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3009
3010 /* For 4-corner performance improve */
3011 rtl_writephy(tp, 0x1f, 0x0005);
3012 rtl_writephy(tp, 0x05, 0x8b80);
3013 rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3014 rtl_writephy(tp, 0x1f, 0x0000);
3015
3016 /* PHY auto speed down */
3017 rtl_writephy(tp, 0x1f, 0x0007);
3018 rtl_writephy(tp, 0x1e, 0x002d);
3019 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3020 rtl_writephy(tp, 0x1f, 0x0000);
3021 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3022
3023 /* Improve 10M EEE waveform */
3024 rtl_writephy(tp, 0x1f, 0x0005);
3025 rtl_writephy(tp, 0x05, 0x8b86);
3026 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3027 rtl_writephy(tp, 0x1f, 0x0000);
3028
3029 /* Improve 2-pair detection performance */
3030 rtl_writephy(tp, 0x1f, 0x0005);
3031 rtl_writephy(tp, 0x05, 0x8b85);
3032 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3033 rtl_writephy(tp, 0x1f, 0x0000);
3034}
3035
3036static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3037{
3038 rtl_apply_firmware(tp);
3039
3040 /* For 4-corner performance improve */
3041 rtl_writephy(tp, 0x1f, 0x0005);
3042 rtl_writephy(tp, 0x05, 0x8b80);
3043 rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3044 rtl_writephy(tp, 0x1f, 0x0000);
3045
3046 /* PHY auto speed down */
3047 rtl_writephy(tp, 0x1f, 0x0007);
3048 rtl_writephy(tp, 0x1e, 0x002d);
3049 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3050 rtl_writephy(tp, 0x1f, 0x0000);
3051 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3052
3053 /* Improve 10M EEE waveform */
3054 rtl_writephy(tp, 0x1f, 0x0005);
3055 rtl_writephy(tp, 0x05, 0x8b86);
3056 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3057 rtl_writephy(tp, 0x1f, 0x0000);
3058}
3059
4da19633 3060static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2857ffb7 3061{
350f7596 3062 static const struct phy_reg phy_reg_init[] = {
2857ffb7
FR		 3063 { 0x1f, 0x0003 },
3064 { 0x08, 0x441d },
3065 { 0x01, 0x9100 },
3066 { 0x1f, 0x0000 }
3067 };
3068
4da19633 3069 rtl_writephy(tp, 0x1f, 0x0000);
3070 rtl_patchphy(tp, 0x11, 1 << 12);
3071 rtl_patchphy(tp, 0x19, 1 << 13);
3072 rtl_patchphy(tp, 0x10, 1 << 15);
2857ffb7 3073
4da19633 3074 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2857ffb7
FR		 3075}
3076
5a5e4443
HW		 3077static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3078{
3079 static const struct phy_reg phy_reg_init[] = {
3080 { 0x1f, 0x0005 },
3081 { 0x1a, 0x0000 },
3082 { 0x1f, 0x0000 },
3083
3084 { 0x1f, 0x0004 },
3085 { 0x1c, 0x0000 },
3086 { 0x1f, 0x0000 },
3087
3088 { 0x1f, 0x0001 },
3089 { 0x15, 0x7701 },
3090 { 0x1f, 0x0000 }
3091 };
3092
3093 /* Disable ALDPS before ram code */
3094 rtl_writephy(tp, 0x1f, 0x0000);
3095 rtl_writephy(tp, 0x18, 0x0310);
3096 msleep(100);
3097
953a12cc 3098 rtl_apply_firmware(tp);
5a5e4443
HW		 3099
3100 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3101}
3102
5615d9f1
FR		 3103static void rtl_hw_phy_config(struct net_device *dev)
3104{
3105 struct rtl8169_private *tp = netdev_priv(dev);
5615d9f1
FR		 3106
3107 rtl8169_print_mac_version(tp);
3108
3109 switch (tp->mac_version) {
3110 case RTL_GIGA_MAC_VER_01:
3111 break;
3112 case RTL_GIGA_MAC_VER_02:
3113 case RTL_GIGA_MAC_VER_03:
4da19633 3114 rtl8169s_hw_phy_config(tp);
5615d9f1
FR		 3115 break;
3116 case RTL_GIGA_MAC_VER_04:
4da19633 3117 rtl8169sb_hw_phy_config(tp);
5615d9f1 3118 break;
2e955856 3119 case RTL_GIGA_MAC_VER_05:
4da19633 3120 rtl8169scd_hw_phy_config(tp);
2e955856 3121 break;
8c7006aa 3122 case RTL_GIGA_MAC_VER_06:
4da19633 3123 rtl8169sce_hw_phy_config(tp);
8c7006aa 3124 break;
2857ffb7
FR		 3125 case RTL_GIGA_MAC_VER_07:
3126 case RTL_GIGA_MAC_VER_08:
3127 case RTL_GIGA_MAC_VER_09:
4da19633 3128 rtl8102e_hw_phy_config(tp);
2857ffb7 3129 break;
236b8082 3130 case RTL_GIGA_MAC_VER_11:
4da19633 3131 rtl8168bb_hw_phy_config(tp);
236b8082
FR		 3132 break;
3133 case RTL_GIGA_MAC_VER_12:
4da19633 3134 rtl8168bef_hw_phy_config(tp);
236b8082
FR		 3135 break;
3136 case RTL_GIGA_MAC_VER_17:
4da19633 3137 rtl8168bef_hw_phy_config(tp);
236b8082 3138 break;
867763c1 3139 case RTL_GIGA_MAC_VER_18:
4da19633 3140 rtl8168cp_1_hw_phy_config(tp);
867763c1
FR		 3141 break;
3142 case RTL_GIGA_MAC_VER_19:
4da19633 3143 rtl8168c_1_hw_phy_config(tp);
867763c1 3144 break;
7da97ec9 3145 case RTL_GIGA_MAC_VER_20:
4da19633 3146 rtl8168c_2_hw_phy_config(tp);
7da97ec9 3147 break;
197ff761 3148 case RTL_GIGA_MAC_VER_21:
4da19633 3149 rtl8168c_3_hw_phy_config(tp);
197ff761 3150 break;
6fb07058 3151 case RTL_GIGA_MAC_VER_22:
4da19633 3152 rtl8168c_4_hw_phy_config(tp);
6fb07058 3153 break;
ef3386f0 3154 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 3155 case RTL_GIGA_MAC_VER_24:
4da19633 3156 rtl8168cp_2_hw_phy_config(tp);
ef3386f0 3157 break;
5b538df9 3158 case RTL_GIGA_MAC_VER_25:
bca03d5f 3159 rtl8168d_1_hw_phy_config(tp);
daf9df6d 3160 break;
3161 case RTL_GIGA_MAC_VER_26:
bca03d5f 3162 rtl8168d_2_hw_phy_config(tp);
daf9df6d 3163 break;
3164 case RTL_GIGA_MAC_VER_27:
4da19633 3165 rtl8168d_3_hw_phy_config(tp);
5b538df9 3166 break;
e6de30d6 3167 case RTL_GIGA_MAC_VER_28:
3168 rtl8168d_4_hw_phy_config(tp);
3169 break;
5a5e4443
HW		 3170 case RTL_GIGA_MAC_VER_29:
3171 case RTL_GIGA_MAC_VER_30:
3172 rtl8105e_hw_phy_config(tp);
3173 break;
cecb5fd7
FR		 3174 case RTL_GIGA_MAC_VER_31:
3175 /* None. */
3176 break;
01dc7fec 3177 case RTL_GIGA_MAC_VER_32:
01dc7fec 3178 case RTL_GIGA_MAC_VER_33:
70090424
HW		 3179 rtl8168e_1_hw_phy_config(tp);
3180 break;
3181 case RTL_GIGA_MAC_VER_34:
3182 rtl8168e_2_hw_phy_config(tp);
01dc7fec 3183 break;
c2218925
HW		 3184 case RTL_GIGA_MAC_VER_35:
3185 rtl8168f_1_hw_phy_config(tp);
3186 break;
3187 case RTL_GIGA_MAC_VER_36:
3188 rtl8168f_2_hw_phy_config(tp);
3189 break;
ef3386f0 3190
5615d9f1
FR		 3191 default:
3192 break;
3193 }
3194}
3195
1da177e4
LT		 3196static void rtl8169_phy_timer(unsigned long __opaque)
3197{
3198 struct net_device *dev = (struct net_device *)__opaque;
3199 struct rtl8169_private *tp = netdev_priv(dev);
3200 struct timer_list *timer = &tp->timer;
3201 void __iomem *ioaddr = tp->mmio_addr;
3202 unsigned long timeout = RTL8169_PHY_TIMEOUT;
3203
bcf0bf90 3204 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 3205
1da177e4
LT		 3206 spin_lock_irq(&tp->lock);
3207
4da19633 3208 if (tp->phy_reset_pending(tp)) {
5b0384f4 3209 /*
1da177e4
LT		 3210 * A busy loop could burn quite a few cycles on nowadays CPU.
3211 * Let's delay the execution of the timer for a few ticks.
3212 */
3213 timeout = HZ/10;
3214 goto out_mod_timer;
3215 }
3216
3217 if (tp->link_ok(ioaddr))
3218 goto out_unlock;
3219
bf82c189 3220 netif_warn(tp, link, dev, "PHY reset until link up\n");
1da177e4 3221
4da19633 3222 tp->phy_reset_enable(tp);
1da177e4
LT		 3223
3224out_mod_timer:
3225 mod_timer(timer, jiffies + timeout);
3226out_unlock:
3227 spin_unlock_irq(&tp->lock);
3228}
3229
1da177e4
LT		 3230#ifdef CONFIG_NET_POLL_CONTROLLER
3231/*
3232 * Polling 'interrupt' - used by things like netconsole to send skbs
3233 * without having to re-enable interrupts. It's not called while
3234 * the interrupt routine is executing.
3235 */
3236static void rtl8169_netpoll(struct net_device *dev)
3237{
3238 struct rtl8169_private *tp = netdev_priv(dev);
3239 struct pci_dev *pdev = tp->pci_dev;
3240
3241 disable_irq(pdev->irq);
7d12e780 3242 rtl8169_interrupt(pdev->irq, dev);
1da177e4
LT		 3243 enable_irq(pdev->irq);
3244}
3245#endif
3246
3247static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3248 void __iomem *ioaddr)
3249{
3250 iounmap(ioaddr);
3251 pci_release_regions(pdev);
87aeec76 3252 pci_clear_mwi(pdev);
1da177e4
LT		 3253 pci_disable_device(pdev);
3254 free_netdev(dev);
3255}
3256
bf793295
FR		 3257static void rtl8169_phy_reset(struct net_device *dev,
3258 struct rtl8169_private *tp)
3259{
07d3f51f 3260 unsigned int i;
bf793295 3261
4da19633 3262 tp->phy_reset_enable(tp);
bf793295 3263 for (i = 0; i < 100; i++) {
4da19633 3264 if (!tp->phy_reset_pending(tp))
bf793295
FR		 3265 return;
3266 msleep(1);
3267 }
bf82c189 3268 netif_err(tp, link, dev, "PHY reset failed\n");
bf793295
FR		 3269}
3270
2544bfc0
FR		 3271static bool rtl_tbi_enabled(struct rtl8169_private *tp)
3272{
3273 void __iomem *ioaddr = tp->mmio_addr;
3274
3275 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
3276 (RTL_R8(PHYstatus) & TBI_Enable);
3277}
3278
4ff96fa6
FR		 3279static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3280{
3281 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 3282
5615d9f1 3283 rtl_hw_phy_config(dev);
4ff96fa6 3284
77332894
MS		 3285 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3286 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3287 RTL_W8(0x82, 0x01);
3288 }
4ff96fa6 3289
6dccd16b
FR		 3290 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3291
3292 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3293 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 3294
bcf0bf90 3295 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 3296 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3297 RTL_W8(0x82, 0x01);
3298 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4da19633 3299 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4ff96fa6
FR		 3300 }
3301
bf793295
FR		 3302 rtl8169_phy_reset(dev, tp);
3303
54405cde 3304 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
cecb5fd7
FR		 3305 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3306 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3307 (tp->mii.supports_gmii ?
3308 ADVERTISED_1000baseT_Half |
3309 ADVERTISED_1000baseT_Full : 0));
4ff96fa6 3310
2544bfc0 3311 if (rtl_tbi_enabled(tp))
bf82c189 3312 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4ff96fa6
FR		 3313}
3314
773d2021
FR		 3315static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3316{
3317 void __iomem *ioaddr = tp->mmio_addr;
3318 u32 high;
3319 u32 low;
3320
3321 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
3322 high = addr[4] | (addr[5] << 8);
3323
3324 spin_lock_irq(&tp->lock);
3325
3326 RTL_W8(Cfg9346, Cfg9346_Unlock);
908ba2bf 3327
773d2021 3328 RTL_W32(MAC4, high);
908ba2bf 3329 RTL_R32(MAC4);
3330
78f1cd02 3331 RTL_W32(MAC0, low);
908ba2bf 3332 RTL_R32(MAC0);
3333
c28aa385 3334 if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
3335 const struct exgmac_reg e[] = {
3336 { .addr = 0xe0, ERIAR_MASK_1111, .val = low },
3337 { .addr = 0xe4, ERIAR_MASK_1111, .val = high },
3338 { .addr = 0xf0, ERIAR_MASK_1111, .val = low << 16 },
3339 { .addr = 0xf4, ERIAR_MASK_1111, .val = high << 16 |
3340 low >> 16 },
3341 };
3342
3343 rtl_write_exgmac_batch(ioaddr, e, ARRAY_SIZE(e));
3344 }
3345
773d2021
FR		 3346 RTL_W8(Cfg9346, Cfg9346_Lock);
3347
3348 spin_unlock_irq(&tp->lock);
3349}
3350
3351static int rtl_set_mac_address(struct net_device *dev, void *p)
3352{
3353 struct rtl8169_private *tp = netdev_priv(dev);
3354 struct sockaddr *addr = p;
3355
3356 if (!is_valid_ether_addr(addr->sa_data))
3357 return -EADDRNOTAVAIL;
3358
3359 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3360
3361 rtl_rar_set(tp, dev->dev_addr);
3362
3363 return 0;
3364}
3365
5f787a1a
FR		 3366static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3367{
3368 struct rtl8169_private *tp = netdev_priv(dev);
3369 struct mii_ioctl_data *data = if_mii(ifr);
3370
8b4ab28d
FR		 3371 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
3372}
5f787a1a 3373
cecb5fd7
FR		 3374static int rtl_xmii_ioctl(struct rtl8169_private *tp,
3375 struct mii_ioctl_data *data, int cmd)
8b4ab28d 3376{
5f787a1a
FR		 3377 switch (cmd) {
3378 case SIOCGMIIPHY:
3379 data->phy_id = 32; /* Internal PHY */
3380 return 0;
3381
3382 case SIOCGMIIREG:
4da19633 3383 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
5f787a1a
FR		 3384 return 0;
3385
3386 case SIOCSMIIREG:
4da19633 3387 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
5f787a1a
FR		 3388 return 0;
3389 }
3390 return -EOPNOTSUPP;
3391}
3392
8b4ab28d
FR		 3393static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3394{
3395 return -EOPNOTSUPP;
3396}
3397
0e485150
FR		 3398static const struct rtl_cfg_info {
3399 void (*hw_start)(struct net_device *);
3400 unsigned int region;
3401 unsigned int align;
3402 u16 intr_event;
3403 u16 napi_event;
ccdffb9a 3404 unsigned features;
f21b75e9 3405 u8 default_ver;
0e485150
FR		 3406} rtl_cfg_infos [] = {
3407 [RTL_CFG_0] = {
3408 .hw_start = rtl_hw_start_8169,
3409 .region = 1,
e9f63f30 3410 .align = 0,
0e485150
FR		 3411 .intr_event = SYSErr | LinkChg | RxOverflow |
3412 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 3413 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 3414 .features = RTL_FEATURE_GMII,
3415 .default_ver = RTL_GIGA_MAC_VER_01,
0e485150
FR		 3416 },
3417 [RTL_CFG_1] = {
3418 .hw_start = rtl_hw_start_8168,
3419 .region = 2,
3420 .align = 8,
53f57357 3421 .intr_event = SYSErr | LinkChg | RxOverflow |
0e485150 3422 TxErr | TxOK | RxOK | RxErr,
fbac58fc 3423 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 3424 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
3425 .default_ver = RTL_GIGA_MAC_VER_11,
0e485150
FR		 3426 },
3427 [RTL_CFG_2] = {
3428 .hw_start = rtl_hw_start_8101,
3429 .region = 2,
3430 .align = 8,
3431 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
3432 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 3433 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 3434 .features = RTL_FEATURE_MSI,
3435 .default_ver = RTL_GIGA_MAC_VER_13,
0e485150
FR		 3436 }
3437};
3438
fbac58fc 3439/* Cfg9346_Unlock assumed. */
2ca6cf06 3440static unsigned rtl_try_msi(struct rtl8169_private *tp,
fbac58fc
FR		 3441 const struct rtl_cfg_info *cfg)
3442{
2ca6cf06 3443 void __iomem *ioaddr = tp->mmio_addr;
fbac58fc
FR		 3444 unsigned msi = 0;
3445 u8 cfg2;
3446
3447 cfg2 = RTL_R8(Config2) & ~MSIEnable;
ccdffb9a 3448 if (cfg->features & RTL_FEATURE_MSI) {
2ca6cf06 3449 if (pci_enable_msi(tp->pci_dev)) {
3450 netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
fbac58fc
FR		 3451 } else {
3452 cfg2 |= MSIEnable;
3453 msi = RTL_FEATURE_MSI;
3454 }
3455 }
2ca6cf06 3456 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3457 RTL_W8(Config2, cfg2);
fbac58fc
FR		 3458 return msi;
3459}
3460
3461static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3462{
3463 if (tp->features & RTL_FEATURE_MSI) {
3464 pci_disable_msi(pdev);
3465 tp->features &= ~RTL_FEATURE_MSI;
3466 }
3467}
3468
8b4ab28d
FR		 3469static const struct net_device_ops rtl8169_netdev_ops = {
3470 .ndo_open = rtl8169_open,
3471 .ndo_stop = rtl8169_close,
3472 .ndo_get_stats = rtl8169_get_stats,
00829823 3473 .ndo_start_xmit = rtl8169_start_xmit,
8b4ab28d
FR		 3474 .ndo_tx_timeout = rtl8169_tx_timeout,
3475 .ndo_validate_addr = eth_validate_addr,
3476 .ndo_change_mtu = rtl8169_change_mtu,
350fb32a
MM		 3477 .ndo_fix_features = rtl8169_fix_features,
3478 .ndo_set_features = rtl8169_set_features,
8b4ab28d
FR		 3479 .ndo_set_mac_address = rtl_set_mac_address,
3480 .ndo_do_ioctl = rtl8169_ioctl,
afc4b13d 3481 .ndo_set_rx_mode = rtl_set_rx_mode,
8b4ab28d
FR		 3482#ifdef CONFIG_NET_POLL_CONTROLLER
3483 .ndo_poll_controller = rtl8169_netpoll,
3484#endif
3485
3486};
3487
c0e45c1c 3488static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
3489{
3490 struct mdio_ops *ops = &tp->mdio_ops;
3491
3492 switch (tp->mac_version) {
3493 case RTL_GIGA_MAC_VER_27:
3494 ops->write = r8168dp_1_mdio_write;
3495 ops->read = r8168dp_1_mdio_read;
3496 break;
e6de30d6 3497 case RTL_GIGA_MAC_VER_28:
4804b3b3 3498 case RTL_GIGA_MAC_VER_31:
e6de30d6 3499 ops->write = r8168dp_2_mdio_write;
3500 ops->read = r8168dp_2_mdio_read;
3501 break;
c0e45c1c 3502 default:
3503 ops->write = r8169_mdio_write;
3504 ops->read = r8169_mdio_read;
3505 break;
3506 }
3507}
3508
649b3b8c 3509static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3510{
3511 void __iomem *ioaddr = tp->mmio_addr;
3512
3513 switch (tp->mac_version) {
3514 case RTL_GIGA_MAC_VER_29:
3515 case RTL_GIGA_MAC_VER_30:
3516 case RTL_GIGA_MAC_VER_32:
3517 case RTL_GIGA_MAC_VER_33:
3518 case RTL_GIGA_MAC_VER_34:
3519 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3520 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3521 break;
3522 default:
3523 break;
3524 }
3525}
3526
3527static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
3528{
3529 if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
3530 return false;
3531
3532 rtl_writephy(tp, 0x1f, 0x0000);
3533 rtl_writephy(tp, MII_BMCR, 0x0000);
3534
3535 rtl_wol_suspend_quirk(tp);
3536
3537 return true;
3538}
3539
065c27c1 3540static void r810x_phy_power_down(struct rtl8169_private *tp)
3541{
3542 rtl_writephy(tp, 0x1f, 0x0000);
3543 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3544}
3545
3546static void r810x_phy_power_up(struct rtl8169_private *tp)
3547{
3548 rtl_writephy(tp, 0x1f, 0x0000);
3549 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3550}
3551
3552static void r810x_pll_power_down(struct rtl8169_private *tp)
3553{
649b3b8c 3554 if (rtl_wol_pll_power_down(tp))
065c27c1 3555 return;
065c27c1 3556
3557 r810x_phy_power_down(tp);
3558}
3559
3560static void r810x_pll_power_up(struct rtl8169_private *tp)
3561{
3562 r810x_phy_power_up(tp);
3563}
3564
3565static void r8168_phy_power_up(struct rtl8169_private *tp)
3566{
3567 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3568 switch (tp->mac_version) {
3569 case RTL_GIGA_MAC_VER_11:
3570 case RTL_GIGA_MAC_VER_12:
3571 case RTL_GIGA_MAC_VER_17:
3572 case RTL_GIGA_MAC_VER_18:
3573 case RTL_GIGA_MAC_VER_19:
3574 case RTL_GIGA_MAC_VER_20:
3575 case RTL_GIGA_MAC_VER_21:
3576 case RTL_GIGA_MAC_VER_22:
3577 case RTL_GIGA_MAC_VER_23:
3578 case RTL_GIGA_MAC_VER_24:
3579 case RTL_GIGA_MAC_VER_25:
3580 case RTL_GIGA_MAC_VER_26:
3581 case RTL_GIGA_MAC_VER_27:
3582 case RTL_GIGA_MAC_VER_28:
3583 case RTL_GIGA_MAC_VER_31:
3584 rtl_writephy(tp, 0x0e, 0x0000);
3585 break;
3586 default:
3587 break;
3588 }
065c27c1 3589 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3590}
3591
3592static void r8168_phy_power_down(struct rtl8169_private *tp)
3593{
3594 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3595 switch (tp->mac_version) {
3596 case RTL_GIGA_MAC_VER_32:
3597 case RTL_GIGA_MAC_VER_33:
3598 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3599 break;
3600
3601 case RTL_GIGA_MAC_VER_11:
3602 case RTL_GIGA_MAC_VER_12:
3603 case RTL_GIGA_MAC_VER_17:
3604 case RTL_GIGA_MAC_VER_18:
3605 case RTL_GIGA_MAC_VER_19:
3606 case RTL_GIGA_MAC_VER_20:
3607 case RTL_GIGA_MAC_VER_21:
3608 case RTL_GIGA_MAC_VER_22:
3609 case RTL_GIGA_MAC_VER_23:
3610 case RTL_GIGA_MAC_VER_24:
3611 case RTL_GIGA_MAC_VER_25:
3612 case RTL_GIGA_MAC_VER_26:
3613 case RTL_GIGA_MAC_VER_27:
3614 case RTL_GIGA_MAC_VER_28:
3615 case RTL_GIGA_MAC_VER_31:
3616 rtl_writephy(tp, 0x0e, 0x0200);
3617 default:
3618 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3619 break;
3620 }
065c27c1 3621}
3622
3623static void r8168_pll_power_down(struct rtl8169_private *tp)
3624{
3625 void __iomem *ioaddr = tp->mmio_addr;
3626
cecb5fd7
FR		 3627 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3628 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3629 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
4804b3b3 3630 r8168dp_check_dash(tp)) {
065c27c1 3631 return;
5d2e1957 3632 }
065c27c1 3633
cecb5fd7
FR		 3634 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3635 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
065c27c1 3636 (RTL_R16(CPlusCmd) & ASF)) {
3637 return;
3638 }
3639
01dc7fec 3640 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3641 tp->mac_version == RTL_GIGA_MAC_VER_33)
3642 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3643
649b3b8c 3644 if (rtl_wol_pll_power_down(tp))
065c27c1 3645 return;
065c27c1 3646
3647 r8168_phy_power_down(tp);
3648
3649 switch (tp->mac_version) {
3650 case RTL_GIGA_MAC_VER_25:
3651 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 3652 case RTL_GIGA_MAC_VER_27:
3653 case RTL_GIGA_MAC_VER_28:
4804b3b3 3654 case RTL_GIGA_MAC_VER_31:
01dc7fec 3655 case RTL_GIGA_MAC_VER_32:
3656 case RTL_GIGA_MAC_VER_33:
065c27c1 3657 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3658 break;
3659 }
3660}
3661
3662static void r8168_pll_power_up(struct rtl8169_private *tp)
3663{
3664 void __iomem *ioaddr = tp->mmio_addr;
3665
cecb5fd7
FR		 3666 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3667 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3668 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
4804b3b3 3669 r8168dp_check_dash(tp)) {
065c27c1 3670 return;
5d2e1957 3671 }
065c27c1 3672
3673 switch (tp->mac_version) {
3674 case RTL_GIGA_MAC_VER_25:
3675 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 3676 case RTL_GIGA_MAC_VER_27:
3677 case RTL_GIGA_MAC_VER_28:
4804b3b3 3678 case RTL_GIGA_MAC_VER_31:
01dc7fec 3679 case RTL_GIGA_MAC_VER_32:
3680 case RTL_GIGA_MAC_VER_33:
065c27c1 3681 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3682 break;
3683 }
3684
3685 r8168_phy_power_up(tp);
3686}
3687
d58d46b5
FR		 3688static void rtl_generic_op(struct rtl8169_private *tp,
3689 void (*op)(struct rtl8169_private *))
065c27c1 3690{
3691 if (op)
3692 op(tp);
3693}
3694
3695static void rtl_pll_power_down(struct rtl8169_private *tp)
3696{
d58d46b5 3697 rtl_generic_op(tp, tp->pll_power_ops.down);
065c27c1 3698}
3699
3700static void rtl_pll_power_up(struct rtl8169_private *tp)
3701{
d58d46b5 3702 rtl_generic_op(tp, tp->pll_power_ops.up);
065c27c1 3703}
3704
3705static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3706{
3707 struct pll_power_ops *ops = &tp->pll_power_ops;
3708
3709 switch (tp->mac_version) {
3710 case RTL_GIGA_MAC_VER_07:
3711 case RTL_GIGA_MAC_VER_08:
3712 case RTL_GIGA_MAC_VER_09:
3713 case RTL_GIGA_MAC_VER_10:
3714 case RTL_GIGA_MAC_VER_16:
5a5e4443
HW		 3715 case RTL_GIGA_MAC_VER_29:
3716 case RTL_GIGA_MAC_VER_30:
065c27c1 3717 ops->down = r810x_pll_power_down;
3718 ops->up = r810x_pll_power_up;
3719 break;
3720
3721 case RTL_GIGA_MAC_VER_11:
3722 case RTL_GIGA_MAC_VER_12:
3723 case RTL_GIGA_MAC_VER_17:
3724 case RTL_GIGA_MAC_VER_18:
3725 case RTL_GIGA_MAC_VER_19:
3726 case RTL_GIGA_MAC_VER_20:
3727 case RTL_GIGA_MAC_VER_21:
3728 case RTL_GIGA_MAC_VER_22:
3729 case RTL_GIGA_MAC_VER_23:
3730 case RTL_GIGA_MAC_VER_24:
3731 case RTL_GIGA_MAC_VER_25:
3732 case RTL_GIGA_MAC_VER_26:
3733 case RTL_GIGA_MAC_VER_27:
e6de30d6 3734 case RTL_GIGA_MAC_VER_28:
4804b3b3 3735 case RTL_GIGA_MAC_VER_31:
01dc7fec 3736 case RTL_GIGA_MAC_VER_32:
3737 case RTL_GIGA_MAC_VER_33:
70090424 3738 case RTL_GIGA_MAC_VER_34:
c2218925
HW		 3739 case RTL_GIGA_MAC_VER_35:
3740 case RTL_GIGA_MAC_VER_36:
065c27c1 3741 ops->down = r8168_pll_power_down;
3742 ops->up = r8168_pll_power_up;
3743 break;
3744
3745 default:
3746 ops->down = NULL;
3747 ops->up = NULL;
3748 break;
3749 }
3750}
3751
e542a226
HW		 3752static void rtl_init_rxcfg(struct rtl8169_private *tp)
3753{
3754 void __iomem *ioaddr = tp->mmio_addr;
3755
3756 switch (tp->mac_version) {
3757 case RTL_GIGA_MAC_VER_01:
3758 case RTL_GIGA_MAC_VER_02:
3759 case RTL_GIGA_MAC_VER_03:
3760 case RTL_GIGA_MAC_VER_04:
3761 case RTL_GIGA_MAC_VER_05:
3762 case RTL_GIGA_MAC_VER_06:
3763 case RTL_GIGA_MAC_VER_10:
3764 case RTL_GIGA_MAC_VER_11:
3765 case RTL_GIGA_MAC_VER_12:
3766 case RTL_GIGA_MAC_VER_13:
3767 case RTL_GIGA_MAC_VER_14:
3768 case RTL_GIGA_MAC_VER_15:
3769 case RTL_GIGA_MAC_VER_16:
3770 case RTL_GIGA_MAC_VER_17:
3771 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
3772 break;
3773 case RTL_GIGA_MAC_VER_18:
3774 case RTL_GIGA_MAC_VER_19:
3775 case RTL_GIGA_MAC_VER_20:
3776 case RTL_GIGA_MAC_VER_21:
3777 case RTL_GIGA_MAC_VER_22:
3778 case RTL_GIGA_MAC_VER_23:
3779 case RTL_GIGA_MAC_VER_24:
3780 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
3781 break;
3782 default:
3783 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
3784 break;
3785 }
3786}
3787
92fc43b4
HW		 3788static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3789{
3790 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
3791}
3792
d58d46b5
FR		 3793static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
3794{
3795 rtl_generic_op(tp, tp->jumbo_ops.enable);
3796}
3797
3798static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
3799{
3800 rtl_generic_op(tp, tp->jumbo_ops.disable);
3801}
3802
3803static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
3804{
3805 void __iomem *ioaddr = tp->mmio_addr;
3806
3807 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3808 RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
3809 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
3810}
3811
3812static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
3813{
3814 void __iomem *ioaddr = tp->mmio_addr;
3815
3816 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3817 RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
3818 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
3819}
3820
3821static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
3822{
3823 void __iomem *ioaddr = tp->mmio_addr;
3824
3825 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3826}
3827
3828static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
3829{
3830 void __iomem *ioaddr = tp->mmio_addr;
3831
3832 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3833}
3834
3835static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
3836{
3837 void __iomem *ioaddr = tp->mmio_addr;
d58d46b5
FR		 3838
3839 RTL_W8(MaxTxPacketSize, 0x3f);
3840 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3841 RTL_W8(Config4, RTL_R8(Config4) | 0x01);
4512ff9f 3842 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
d58d46b5
FR		 3843}
3844
3845static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
3846{
3847 void __iomem *ioaddr = tp->mmio_addr;
d58d46b5
FR		 3848
3849 RTL_W8(MaxTxPacketSize, 0x0c);
3850 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3851 RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
4512ff9f 3852 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
d58d46b5
FR		 3853}
3854
3855static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
3856{
3857 rtl_tx_performance_tweak(tp->pci_dev,
3858 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3859}
3860
3861static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
3862{
3863 rtl_tx_performance_tweak(tp->pci_dev,
3864 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3865}
3866
3867static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
3868{
3869 void __iomem *ioaddr = tp->mmio_addr;
3870
3871 r8168b_0_hw_jumbo_enable(tp);
3872
3873 RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
3874}
3875
3876static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
3877{
3878 void __iomem *ioaddr = tp->mmio_addr;
3879
3880 r8168b_0_hw_jumbo_disable(tp);
3881
3882 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
3883}
3884
3885static void __devinit rtl_init_jumbo_ops(struct rtl8169_private *tp)
3886{
3887 struct jumbo_ops *ops = &tp->jumbo_ops;
3888
3889 switch (tp->mac_version) {
3890 case RTL_GIGA_MAC_VER_11:
3891 ops->disable = r8168b_0_hw_jumbo_disable;
3892 ops->enable = r8168b_0_hw_jumbo_enable;
3893 break;
3894 case RTL_GIGA_MAC_VER_12:
3895 case RTL_GIGA_MAC_VER_17:
3896 ops->disable = r8168b_1_hw_jumbo_disable;
3897 ops->enable = r8168b_1_hw_jumbo_enable;
3898 break;
3899 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
3900 case RTL_GIGA_MAC_VER_19:
3901 case RTL_GIGA_MAC_VER_20:
3902 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
3903 case RTL_GIGA_MAC_VER_22:
3904 case RTL_GIGA_MAC_VER_23:
3905 case RTL_GIGA_MAC_VER_24:
3906 case RTL_GIGA_MAC_VER_25:
3907 case RTL_GIGA_MAC_VER_26:
3908 ops->disable = r8168c_hw_jumbo_disable;
3909 ops->enable = r8168c_hw_jumbo_enable;
3910 break;
3911 case RTL_GIGA_MAC_VER_27:
3912 case RTL_GIGA_MAC_VER_28:
3913 ops->disable = r8168dp_hw_jumbo_disable;
3914 ops->enable = r8168dp_hw_jumbo_enable;
3915 break;
3916 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
3917 case RTL_GIGA_MAC_VER_32:
3918 case RTL_GIGA_MAC_VER_33:
3919 case RTL_GIGA_MAC_VER_34:
3920 ops->disable = r8168e_hw_jumbo_disable;
3921 ops->enable = r8168e_hw_jumbo_enable;
3922 break;
3923
3924 /*
3925 * No action needed for jumbo frames with 8169.
3926 * No jumbo for 810x at all.
3927 */
3928 default:
3929 ops->disable = NULL;
3930 ops->enable = NULL;
3931 break;
3932 }
3933}
3934
6f43adc8
FR		 3935static void rtl_hw_reset(struct rtl8169_private *tp)
3936{
3937 void __iomem *ioaddr = tp->mmio_addr;
3938 int i;
3939
3940 /* Soft reset the chip. */
3941 RTL_W8(ChipCmd, CmdReset);
3942
3943 /* Check that the chip has finished the reset. */
3944 for (i = 0; i < 100; i++) {
3945 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3946 break;
92fc43b4 3947 udelay(100);
6f43adc8
FR		 3948 }
3949}
3950
1da177e4 3951static int __devinit
4ff96fa6 3952rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 3953{
0e485150
FR		 3954 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
3955 const unsigned int region = cfg->region;
1da177e4 3956 struct rtl8169_private *tp;
ccdffb9a 3957 struct mii_if_info *mii;
4ff96fa6
FR		 3958 struct net_device *dev;
3959 void __iomem *ioaddr;
2b7b4318 3960 int chipset, i;
07d3f51f 3961 int rc;
1da177e4 3962
4ff96fa6
FR		 3963 if (netif_msg_drv(&debug)) {
3964 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
3965 MODULENAME, RTL8169_VERSION);
3966 }
1da177e4 3967
1da177e4 3968 dev = alloc_etherdev(sizeof (*tp));
4ff96fa6 3969 if (!dev) {
b57b7e5a 3970 if (netif_msg_drv(&debug))
9b91cf9d 3971 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
4ff96fa6
FR		 3972 rc = -ENOMEM;
3973 goto out;
1da177e4
LT		 3974 }
3975
1da177e4 3976 SET_NETDEV_DEV(dev, &pdev->dev);
8b4ab28d 3977 dev->netdev_ops = &rtl8169_netdev_ops;
1da177e4 3978 tp = netdev_priv(dev);
c4028958 3979 tp->dev = dev;
21e197f2 3980 tp->pci_dev = pdev;
b57b7e5a 3981 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1da177e4 3982
ccdffb9a
FR		 3983 mii = &tp->mii;
3984 mii->dev = dev;
3985 mii->mdio_read = rtl_mdio_read;
3986 mii->mdio_write = rtl_mdio_write;
3987 mii->phy_id_mask = 0x1f;
3988 mii->reg_num_mask = 0x1f;
3989 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3990
ba04c7c9
SG		 3991 /* disable ASPM completely as that cause random device stop working
3992 * problems as well as full system hangs for some PCIe devices users */
3993 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3994 PCIE_LINK_STATE_CLKPM);
3995
1da177e4
LT		 3996 /* enable device (incl. PCI PM wakeup and hotplug setup) */
3997 rc = pci_enable_device(pdev);
b57b7e5a 3998 if (rc < 0) {
bf82c189 3999 netif_err(tp, probe, dev, "enable failure\n");
4ff96fa6 4000 goto err_out_free_dev_1;
1da177e4
LT		 4001 }
4002
87aeec76 4003 if (pci_set_mwi(pdev) < 0)
4004 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
1da177e4 4005
1da177e4 4006 /* make sure PCI base addr 1 is MMIO */
bcf0bf90 4007 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
bf82c189
JP		 4008 netif_err(tp, probe, dev,
4009 "region #%d not an MMIO resource, aborting\n",
4010 region);
1da177e4 4011 rc = -ENODEV;
87aeec76 4012 goto err_out_mwi_2;
1da177e4 4013 }
4ff96fa6 4014
1da177e4 4015 /* check for weird/broken PCI region reporting */
bcf0bf90 4016 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
bf82c189
JP		 4017 netif_err(tp, probe, dev,
4018 "Invalid PCI region size(s), aborting\n");
1da177e4 4019 rc = -ENODEV;
87aeec76 4020 goto err_out_mwi_2;
1da177e4
LT		 4021 }
4022
4023 rc = pci_request_regions(pdev, MODULENAME);
b57b7e5a 4024 if (rc < 0) {
bf82c189 4025 netif_err(tp, probe, dev, "could not request regions\n");
87aeec76 4026 goto err_out_mwi_2;
1da177e4
LT		 4027 }
4028
d24e9aaf 4029 tp->cp_cmd = RxChkSum;
1da177e4
LT		 4030
4031 if ((sizeof(dma_addr_t) > 4) &&
4300e8c7 4032 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
1da177e4
LT		 4033 tp->cp_cmd |= PCIDAC;
4034 dev->features |= NETIF_F_HIGHDMA;
4035 } else {
284901a9 4036 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 4037 if (rc < 0) {
bf82c189 4038 netif_err(tp, probe, dev, "DMA configuration failed\n");
87aeec76 4039 goto err_out_free_res_3;
1da177e4
LT		 4040 }
4041 }
4042
1da177e4 4043 /* ioremap MMIO region */
bcf0bf90 4044 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4ff96fa6 4045 if (!ioaddr) {
bf82c189 4046 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
1da177e4 4047 rc = -EIO;
87aeec76 4048 goto err_out_free_res_3;
1da177e4 4049 }
6f43adc8 4050 tp->mmio_addr = ioaddr;
1da177e4 4051
e44daade
JM		 4052 if (!pci_is_pcie(pdev))
4053 netif_info(tp, probe, dev, "not PCI Express\n");
4300e8c7 4054
e542a226
HW		 4055 /* Identify chip attached to board */
4056 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
4057
4058 rtl_init_rxcfg(tp);
4059
d78ad8cb 4060 RTL_W16(IntrMask, 0x0000);
1da177e4 4061
6f43adc8 4062 rtl_hw_reset(tp);
1da177e4 4063
d78ad8cb
KW		 4064 RTL_W16(IntrStatus, 0xffff);
4065
ca52efd5 4066 pci_set_master(pdev);
4067
7a8fc77b
FR		 4068 /*
4069 * Pretend we are using VLANs; This bypasses a nasty bug where
4070 * Interrupts stop flowing on high load on 8110SCd controllers.
4071 */
4072 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4073 tp->cp_cmd |= RxVlan;
4074
c0e45c1c 4075 rtl_init_mdio_ops(tp);
065c27c1 4076 rtl_init_pll_power_ops(tp);
d58d46b5 4077 rtl_init_jumbo_ops(tp);
c0e45c1c 4078
1da177e4 4079 rtl8169_print_mac_version(tp);
1da177e4 4080
85bffe6c
FR		 4081 chipset = tp->mac_version;
4082 tp->txd_version = rtl_chip_infos[chipset].txd_version;
1da177e4 4083
5d06a99f
FR		 4084 RTL_W8(Cfg9346, Cfg9346_Unlock);
4085 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
4086 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
20037fa4
BP		 4087 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
4088 tp->features |= RTL_FEATURE_WOL;
4089 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
4090 tp->features |= RTL_FEATURE_WOL;
2ca6cf06 4091 tp->features |= rtl_try_msi(tp, cfg);
5d06a99f
FR		 4092 RTL_W8(Cfg9346, Cfg9346_Lock);
4093
2544bfc0 4094 if (rtl_tbi_enabled(tp)) {
1da177e4
LT		 4095 tp->set_speed = rtl8169_set_speed_tbi;
4096 tp->get_settings = rtl8169_gset_tbi;
4097 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
4098 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
4099 tp->link_ok = rtl8169_tbi_link_ok;
8b4ab28d 4100 tp->do_ioctl = rtl_tbi_ioctl;
1da177e4
LT		 4101 } else {
4102 tp->set_speed = rtl8169_set_speed_xmii;
4103 tp->get_settings = rtl8169_gset_xmii;
4104 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
4105 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
4106 tp->link_ok = rtl8169_xmii_link_ok;
8b4ab28d 4107 tp->do_ioctl = rtl_xmii_ioctl;
1da177e4
LT		 4108 }
4109
df58ef51
FR		 4110 spin_lock_init(&tp->lock);
4111
7bf6bf48 4112 /* Get MAC address */
6a3c910c 4113 for (i = 0; i < ETH_ALEN; i++)
1da177e4 4114 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6d6525b7 4115 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4 4116
1da177e4 4117 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1da177e4
LT		 4118 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
4119 dev->irq = pdev->irq;
4120 dev->base_addr = (unsigned long) ioaddr;
1da177e4 4121
bea3348e 4122 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
1da177e4 4123
350fb32a
MM		 4124 /* don't enable SG, IP_CSUM and TSO by default - it might not work
4125 * properly for all devices */
4126 dev->features |= NETIF_F_RXCSUM |
4127 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4128
4129 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
4130 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4131 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
4132 NETIF_F_HIGHDMA;
4133
4134 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4135 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
4136 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
1da177e4
LT		 4137
4138 tp->intr_mask = 0xffff;
0e485150
FR		 4139 tp->hw_start = cfg->hw_start;
4140 tp->intr_event = cfg->intr_event;
4141 tp->napi_event = cfg->napi_event;
1da177e4 4142
e03f33af
FR		 4143 tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
4144 ~(RxBOVF | RxFOVF) : ~0;
4145
2efa53f3
FR		 4146 init_timer(&tp->timer);
4147 tp->timer.data = (unsigned long) dev;
4148 tp->timer.function = rtl8169_phy_timer;
4149
b6ffd97f 4150 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
953a12cc 4151
1da177e4 4152 rc = register_netdev(dev);
4ff96fa6 4153 if (rc < 0)
87aeec76 4154 goto err_out_msi_4;
1da177e4
LT		 4155
4156 pci_set_drvdata(pdev, dev);
4157
bf82c189 4158 netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
85bffe6c 4159 rtl_chip_infos[chipset].name, dev->base_addr, dev->dev_addr,
bf82c189 4160 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
d58d46b5
FR		 4161 if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
4162 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
4163 "tx checksumming: %s]\n",
4164 rtl_chip_infos[chipset].jumbo_max,
4165 rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
4166 }
1da177e4 4167
cecb5fd7
FR		 4168 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4169 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4170 tp->mac_version == RTL_GIGA_MAC_VER_31) {
b646d900 4171 rtl8168_driver_start(tp);
e6de30d6 4172 }
b646d900 4173
8b76ab39 4174 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
1da177e4 4175
f3ec4f87
AS		 4176 if (pci_dev_run_wake(pdev))
4177 pm_runtime_put_noidle(&pdev->dev);
e1759441 4178
0d672e9f
IV		 4179 netif_carrier_off(dev);
4180
4ff96fa6
FR		 4181out:
4182 return rc;
1da177e4 4183
87aeec76 4184err_out_msi_4:
fbac58fc 4185 rtl_disable_msi(pdev, tp);
4ff96fa6 4186 iounmap(ioaddr);
87aeec76 4187err_out_free_res_3:
4ff96fa6 4188 pci_release_regions(pdev);
87aeec76 4189err_out_mwi_2:
4ff96fa6 4190 pci_clear_mwi(pdev);
4ff96fa6
FR		 4191 pci_disable_device(pdev);
4192err_out_free_dev_1:
4193 free_netdev(dev);
4194 goto out;
1da177e4
LT		 4195}
4196
07d3f51f 4197static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1da177e4
LT		 4198{
4199 struct net_device *dev = pci_get_drvdata(pdev);
4200 struct rtl8169_private *tp = netdev_priv(dev);
4201
cecb5fd7
FR		 4202 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4203 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4204 tp->mac_version == RTL_GIGA_MAC_VER_31) {
b646d900 4205 rtl8168_driver_stop(tp);
e6de30d6 4206 }
b646d900 4207
4422bcd4 4208 cancel_work_sync(&tp->wk.work);
eb2a021c 4209
1da177e4 4210 unregister_netdev(dev);
cc098dc7 4211
953a12cc
FR		 4212 rtl_release_firmware(tp);
4213
f3ec4f87
AS		 4214 if (pci_dev_run_wake(pdev))
4215 pm_runtime_get_noresume(&pdev->dev);
e1759441 4216
cc098dc7
IV		 4217 /* restore original MAC address */
4218 rtl_rar_set(tp, dev->perm_addr);
4219
fbac58fc 4220 rtl_disable_msi(pdev, tp);
1da177e4
LT		 4221 rtl8169_release_board(pdev, dev, tp->mmio_addr);
4222 pci_set_drvdata(pdev, NULL);
4223}
4224
b6ffd97f 4225static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
953a12cc 4226{
b6ffd97f
FR		 4227 struct rtl_fw *rtl_fw;
4228 const char *name;
4229 int rc = -ENOMEM;
953a12cc 4230
b6ffd97f
FR		 4231 name = rtl_lookup_firmware_name(tp);
4232 if (!name)
4233 goto out_no_firmware;
953a12cc 4234
b6ffd97f
FR		 4235 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4236 if (!rtl_fw)
4237 goto err_warn;
31bd204f 4238
b6ffd97f
FR		 4239 rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
4240 if (rc < 0)
4241 goto err_free;
4242
fd112f2e
FR		 4243 rc = rtl_check_firmware(tp, rtl_fw);
4244 if (rc < 0)
4245 goto err_release_firmware;
4246
b6ffd97f
FR		 4247 tp->rtl_fw = rtl_fw;
4248out:
4249 return;
4250
fd112f2e
FR		 4251err_release_firmware:
4252 release_firmware(rtl_fw->fw);
b6ffd97f
FR		 4253err_free:
4254 kfree(rtl_fw);
4255err_warn:
4256 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4257 name, rc);
4258out_no_firmware:
4259 tp->rtl_fw = NULL;
4260 goto out;
4261}
4262
4263static void rtl_request_firmware(struct rtl8169_private *tp)
4264{
4265 if (IS_ERR(tp->rtl_fw))
4266 rtl_request_uncached_firmware(tp);
953a12cc
FR		 4267}
4268
4422bcd4
FR		 4269static void rtl_task(struct work_struct *);
4270
1da177e4
LT		 4271static int rtl8169_open(struct net_device *dev)
4272{
4273 struct rtl8169_private *tp = netdev_priv(dev);
eee3a96c 4274 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 4275 struct pci_dev *pdev = tp->pci_dev;
99f252b0 4276 int retval = -ENOMEM;
1da177e4 4277
e1759441 4278 pm_runtime_get_sync(&pdev->dev);
1da177e4 4279
1da177e4
LT		 4280 /*
4281 * Rx and Tx desscriptors needs 256 bytes alignment.
82553bb6 4282 * dma_alloc_coherent provides more.
1da177e4 4283 */
82553bb6
SG		 4284 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
4285 &tp->TxPhyAddr, GFP_KERNEL);
1da177e4 4286 if (!tp->TxDescArray)
e1759441 4287 goto err_pm_runtime_put;
1da177e4 4288
82553bb6
SG		 4289 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
4290 &tp->RxPhyAddr, GFP_KERNEL);
1da177e4 4291 if (!tp->RxDescArray)
99f252b0 4292 goto err_free_tx_0;
1da177e4
LT		 4293
4294 retval = rtl8169_init_ring(dev);
4295 if (retval < 0)
99f252b0 4296 goto err_free_rx_1;
1da177e4 4297
4422bcd4 4298 INIT_WORK(&tp->wk.work, rtl_task);
1da177e4 4299
99f252b0
FR		 4300 smp_mb();
4301
953a12cc
FR		 4302 rtl_request_firmware(tp);
4303
fbac58fc
FR		 4304 retval = request_irq(dev->irq, rtl8169_interrupt,
4305 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
99f252b0
FR		 4306 dev->name, dev);
4307 if (retval < 0)
953a12cc 4308 goto err_release_fw_2;
99f252b0 4309
bea3348e 4310 napi_enable(&tp->napi);
bea3348e 4311
eee3a96c 4312 rtl8169_init_phy(dev, tp);
4313
350fb32a 4314 rtl8169_set_features(dev, dev->features);
eee3a96c 4315
065c27c1 4316 rtl_pll_power_up(tp);
4317
07ce4064 4318 rtl_hw_start(dev);
1da177e4 4319
e1759441
RW		 4320 tp->saved_wolopts = 0;
4321 pm_runtime_put_noidle(&pdev->dev);
4322
eee3a96c 4323 rtl8169_check_link_status(dev, tp, ioaddr);
1da177e4
LT		 4324out:
4325 return retval;
4326
953a12cc
FR		 4327err_release_fw_2:
4328 rtl_release_firmware(tp);
99f252b0
FR		 4329 rtl8169_rx_clear(tp);
4330err_free_rx_1:
82553bb6
SG		 4331 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4332 tp->RxPhyAddr);
e1759441 4333 tp->RxDescArray = NULL;
99f252b0 4334err_free_tx_0:
82553bb6
SG		 4335 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4336 tp->TxPhyAddr);
e1759441
RW		 4337 tp->TxDescArray = NULL;
4338err_pm_runtime_put:
4339 pm_runtime_put_noidle(&pdev->dev);
1da177e4
LT		 4340 goto out;
4341}
4342
92fc43b4
HW		 4343static void rtl_rx_close(struct rtl8169_private *tp)
4344{
4345 void __iomem *ioaddr = tp->mmio_addr;
92fc43b4 4346
1687b566 4347 RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
92fc43b4
HW		 4348}
4349
e6de30d6 4350static void rtl8169_hw_reset(struct rtl8169_private *tp)
1da177e4 4351{
e6de30d6 4352 void __iomem *ioaddr = tp->mmio_addr;
4353
1da177e4 4354 /* Disable interrupts */
811fd301 4355 rtl8169_irq_mask_and_ack(tp);
1da177e4 4356
92fc43b4
HW		 4357 rtl_rx_close(tp);
4358
5d2e1957 4359 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4804b3b3 4360 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4361 tp->mac_version == RTL_GIGA_MAC_VER_31) {
e6de30d6 4362 while (RTL_R8(TxPoll) & NPQ)
4363 udelay(20);
c2218925
HW		 4364 } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
4365 tp->mac_version == RTL_GIGA_MAC_VER_35 ||
4366 tp->mac_version == RTL_GIGA_MAC_VER_36) {
c2b0c1e7 4367 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
70090424
HW		 4368 while (!(RTL_R32(TxConfig) & TXCFG_EMPTY))
4369 udelay(100);
92fc43b4
HW		 4370 } else {
4371 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4372 udelay(100);
e6de30d6 4373 }
4374
92fc43b4 4375 rtl_hw_reset(tp);
1da177e4
LT		 4376}
4377
7f796d83 4378static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 4379{
4380 void __iomem *ioaddr = tp->mmio_addr;
9cb427b6
FR		 4381
4382 /* Set DMA burst size and Interframe Gap Time */
4383 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4384 (InterFrameGap << TxInterFrameGapShift));
4385}
4386
07ce4064 4387static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 4388{
4389 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 4390
07ce4064
FR		 4391 tp->hw_start(dev);
4392
3e990ff5
FR		 4393 rtl_irq_enable(tp, tp->intr_event);
4394
07ce4064
FR		 4395 netif_start_queue(dev);
4396}
4397
7f796d83
FR		 4398static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
4399 void __iomem *ioaddr)
4400{
4401 /*
4402 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4403 * register to be written before TxDescAddrLow to work.
4404 * Switching from MMIO to I/O access fixes the issue as well.
4405 */
4406 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
284901a9 4407 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
7f796d83 4408 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
284901a9 4409 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 4410}
4411
4412static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4413{
4414 u16 cmd;
4415
4416 cmd = RTL_R16(CPlusCmd);
4417 RTL_W16(CPlusCmd, cmd);
4418 return cmd;
4419}
4420
fdd7b4c3 4421static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
7f796d83
FR		 4422{
4423 /* Low hurts. Let's disable the filtering. */
207d6e87 4424 RTL_W16(RxMaxSize, rx_buf_sz + 1);
7f796d83
FR		 4425}
4426
6dccd16b
FR		 4427static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4428{
3744100e 4429 static const struct rtl_cfg2_info {
6dccd16b
FR		 4430 u32 mac_version;
4431 u32 clk;
4432 u32 val;
4433 } cfg2_info [] = {
4434 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4435 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4436 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4437 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3744100e
FR		 4438 };
4439 const struct rtl_cfg2_info *p = cfg2_info;
6dccd16b
FR		 4440 unsigned int i;
4441 u32 clk;
4442
4443 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 4444 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 4445 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4446 RTL_W32(0x7c, p->val);
4447 break;
4448 }
4449 }
4450}
4451
07ce4064
FR		 4452static void rtl_hw_start_8169(struct net_device *dev)
4453{
4454 struct rtl8169_private *tp = netdev_priv(dev);
4455 void __iomem *ioaddr = tp->mmio_addr;
4456 struct pci_dev *pdev = tp->pci_dev;
07ce4064 4457
9cb427b6
FR		 4458 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4459 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4460 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4461 }
4462
1da177e4 4463 RTL_W8(Cfg9346, Cfg9346_Unlock);
cecb5fd7
FR		 4464 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4465 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4466 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4467 tp->mac_version == RTL_GIGA_MAC_VER_04)
9cb427b6
FR		 4468 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4469
e542a226
HW		 4470 rtl_init_rxcfg(tp);
4471
f0298f81 4472 RTL_W8(EarlyTxThres, NoEarlyTx);
1da177e4 4473
6f0333b8 4474 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
1da177e4 4475
cecb5fd7
FR		 4476 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4477 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4478 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4479 tp->mac_version == RTL_GIGA_MAC_VER_04)
c946b304 4480 rtl_set_rx_tx_config_registers(tp);
1da177e4 4481
7f796d83 4482 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 4483
cecb5fd7
FR		 4484 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4485 tp->mac_version == RTL_GIGA_MAC_VER_03) {
06fa7358 4486 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1da177e4 4487 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 4488 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 4489 }
4490
bcf0bf90
FR		 4491 RTL_W16(CPlusCmd, tp->cp_cmd);
4492
6dccd16b
FR		 4493 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4494
1da177e4
LT		 4495 /*
4496 * Undocumented corner. Supposedly:
4497 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4498 */
4499 RTL_W16(IntrMitigate, 0x0000);
4500
7f796d83 4501 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 4502
cecb5fd7
FR		 4503 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4504 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4505 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
4506 tp->mac_version != RTL_GIGA_MAC_VER_04) {
c946b304
FR		 4507 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4508 rtl_set_rx_tx_config_registers(tp);
4509 }
4510
1da177e4 4511 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 4512
4513 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4514 RTL_R8(IntrMask);
1da177e4
LT		 4515
4516 RTL_W32(RxMissed, 0);
4517
07ce4064 4518 rtl_set_rx_mode(dev);
1da177e4
LT		 4519
4520 /* no early-rx interrupts */
4521 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
07ce4064 4522}
1da177e4 4523
650e8d5d 4524static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
dacf8154
FR		 4525{
4526 u32 csi;
4527
4528 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
650e8d5d 4529 rtl_csi_write(ioaddr, 0x070c, csi | bits);
4530}
4531
e6de30d6 4532static void rtl_csi_access_enable_1(void __iomem *ioaddr)
4533{
4534 rtl_csi_access_enable(ioaddr, 0x17000000);
4535}
4536
650e8d5d 4537static void rtl_csi_access_enable_2(void __iomem *ioaddr)
4538{
4539 rtl_csi_access_enable(ioaddr, 0x27000000);
dacf8154
FR		 4540}
4541
4542struct ephy_info {
4543 unsigned int offset;
4544 u16 mask;
4545 u16 bits;
4546};
4547
350f7596 4548static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
dacf8154
FR		 4549{
4550 u16 w;
4551
4552 while (len-- > 0) {
4553 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
4554 rtl_ephy_write(ioaddr, e->offset, w);
4555 e++;
4556 }
4557}
4558
b726e493
FR		 4559static void rtl_disable_clock_request(struct pci_dev *pdev)
4560{
e44daade 4561 int cap = pci_pcie_cap(pdev);
b726e493
FR		 4562
4563 if (cap) {
4564 u16 ctl;
4565
4566 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4567 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
4568 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4569 }
4570}
4571
e6de30d6 4572static void rtl_enable_clock_request(struct pci_dev *pdev)
4573{
e44daade 4574 int cap = pci_pcie_cap(pdev);
e6de30d6 4575
4576 if (cap) {
4577 u16 ctl;
4578
4579 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4580 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
4581 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4582 }
4583}
4584
b726e493
FR		 4585#define R8168_CPCMD_QUIRK_MASK (\
4586 EnableBist | \
4587 Mac_dbgo_oe | \
4588 Force_half_dup | \
4589 Force_rxflow_en | \
4590 Force_txflow_en | \
4591 Cxpl_dbg_sel | \
4592 ASF | \
4593 PktCntrDisable | \
4594 Mac_dbgo_sel)
4595
219a1e9d
FR		 4596static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
4597{
b726e493
FR		 4598 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4599
4600 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4601
2e68ae44
FR		 4602 rtl_tx_performance_tweak(pdev,
4603 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
219a1e9d
FR		 4604}
4605
4606static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
4607{
4608 rtl_hw_start_8168bb(ioaddr, pdev);
b726e493 4609
f0298f81 4610 RTL_W8(MaxTxPacketSize, TxPacketMax);
b726e493
FR		 4611
4612 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
219a1e9d
FR		 4613}
4614
4615static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
4616{
b726e493
FR		 4617 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4618
4619 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4620
219a1e9d 4621 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
b726e493
FR		 4622
4623 rtl_disable_clock_request(pdev);
4624
4625 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
219a1e9d
FR		 4626}
4627
ef3386f0 4628static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
219a1e9d 4629{
350f7596 4630 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 4631 { 0x01, 0, 0x0001 },
4632 { 0x02, 0x0800, 0x1000 },
4633 { 0x03, 0, 0x0042 },
4634 { 0x06, 0x0080, 0x0000 },
4635 { 0x07, 0, 0x2000 }
4636 };
4637
650e8d5d 4638 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 4639
4640 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4641
219a1e9d
FR		 4642 __rtl_hw_start_8168cp(ioaddr, pdev);
4643}
4644
ef3386f0
FR		 4645static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
4646{
650e8d5d 4647 rtl_csi_access_enable_2(ioaddr);
ef3386f0
FR		 4648
4649 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4650
4651 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4652
4653 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4654}
4655
7f3e3d3a
FR		 4656static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
4657{
650e8d5d 4658 rtl_csi_access_enable_2(ioaddr);
7f3e3d3a
FR		 4659
4660 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4661
4662 /* Magic. */
4663 RTL_W8(DBG_REG, 0x20);
4664
f0298f81 4665 RTL_W8(MaxTxPacketSize, TxPacketMax);
7f3e3d3a
FR		 4666
4667 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4668
4669 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4670}
4671
219a1e9d
FR		 4672static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
4673{
350f7596 4674 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 4675 { 0x02, 0x0800, 0x1000 },
4676 { 0x03, 0, 0x0002 },
4677 { 0x06, 0x0080, 0x0000 }
4678 };
4679
650e8d5d 4680 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 4681
4682 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4683
4684 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4685
219a1e9d
FR		 4686 __rtl_hw_start_8168cp(ioaddr, pdev);
4687}
4688
4689static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
4690{
350f7596 4691 static const struct ephy_info e_info_8168c_2[] = {
b726e493
FR		 4692 { 0x01, 0, 0x0001 },
4693 { 0x03, 0x0400, 0x0220 }
4694 };
4695
650e8d5d 4696 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 4697
4698 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4699
219a1e9d
FR		 4700 __rtl_hw_start_8168cp(ioaddr, pdev);
4701}
4702
197ff761
FR		 4703static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
4704{
4705 rtl_hw_start_8168c_2(ioaddr, pdev);
4706}
4707
6fb07058
FR		 4708static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
4709{
650e8d5d 4710 rtl_csi_access_enable_2(ioaddr);
6fb07058
FR		 4711
4712 __rtl_hw_start_8168cp(ioaddr, pdev);
4713}
4714
5b538df9
FR		 4715static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
4716{
650e8d5d 4717 rtl_csi_access_enable_2(ioaddr);
5b538df9
FR		 4718
4719 rtl_disable_clock_request(pdev);
4720
f0298f81 4721 RTL_W8(MaxTxPacketSize, TxPacketMax);
5b538df9
FR		 4722
4723 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4724
4725 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4726}
4727
4804b3b3 4728static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev)
4729{
4730 rtl_csi_access_enable_1(ioaddr);
4731
4732 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4733
4734 RTL_W8(MaxTxPacketSize, TxPacketMax);
4735
4736 rtl_disable_clock_request(pdev);
4737}
4738
e6de30d6 4739static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
4740{
4741 static const struct ephy_info e_info_8168d_4[] = {
4742 { 0x0b, ~0, 0x48 },
4743 { 0x19, 0x20, 0x50 },
4744 { 0x0c, ~0, 0x20 }
4745 };
4746 int i;
4747
4748 rtl_csi_access_enable_1(ioaddr);
4749
4750 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4751
4752 RTL_W8(MaxTxPacketSize, TxPacketMax);
4753
4754 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4755 const struct ephy_info *e = e_info_8168d_4 + i;
4756 u16 w;
4757
4758 w = rtl_ephy_read(ioaddr, e->offset);
4759 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
4760 }
4761
4762 rtl_enable_clock_request(pdev);
4763}
4764
70090424 4765static void rtl_hw_start_8168e_1(void __iomem *ioaddr, struct pci_dev *pdev)
01dc7fec 4766{
70090424 4767 static const struct ephy_info e_info_8168e_1[] = {
01dc7fec 4768 { 0x00, 0x0200, 0x0100 },
4769 { 0x00, 0x0000, 0x0004 },
4770 { 0x06, 0x0002, 0x0001 },
4771 { 0x06, 0x0000, 0x0030 },
4772 { 0x07, 0x0000, 0x2000 },
4773 { 0x00, 0x0000, 0x0020 },
4774 { 0x03, 0x5800, 0x2000 },
4775 { 0x03, 0x0000, 0x0001 },
4776 { 0x01, 0x0800, 0x1000 },
4777 { 0x07, 0x0000, 0x4000 },
4778 { 0x1e, 0x0000, 0x2000 },
4779 { 0x19, 0xffff, 0xfe6c },
4780 { 0x0a, 0x0000, 0x0040 }
4781 };
4782
4783 rtl_csi_access_enable_2(ioaddr);
4784
70090424 4785 rtl_ephy_init(ioaddr, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
01dc7fec 4786
4787 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4788
4789 RTL_W8(MaxTxPacketSize, TxPacketMax);
4790
4791 rtl_disable_clock_request(pdev);
4792
4793 /* Reset tx FIFO pointer */
cecb5fd7
FR		 4794 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
4795 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
01dc7fec 4796
cecb5fd7 4797 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
01dc7fec 4798}
4799
70090424
HW		 4800static void rtl_hw_start_8168e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4801{
4802 static const struct ephy_info e_info_8168e_2[] = {
4803 { 0x09, 0x0000, 0x0080 },
4804 { 0x19, 0x0000, 0x0224 }
4805 };
4806
4807 rtl_csi_access_enable_1(ioaddr);
4808
4809 rtl_ephy_init(ioaddr, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
4810
4811 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4812
4813 rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4814 rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4815 rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4816 rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4817 rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4818 rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
4819 rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4820 rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4821 ERIAR_EXGMAC);
4822
3090bd9a 4823 RTL_W8(MaxTxPacketSize, EarlySize);
70090424
HW		 4824
4825 rtl_disable_clock_request(pdev);
4826
4827 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4828 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4829
4830 /* Adjust EEE LED frequency */
4831 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4832
4833 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4834 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4835 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4836}
4837
c2218925
HW		 4838static void rtl_hw_start_8168f_1(void __iomem *ioaddr, struct pci_dev *pdev)
4839{
4840 static const struct ephy_info e_info_8168f_1[] = {
4841 { 0x06, 0x00c0, 0x0020 },
4842 { 0x08, 0x0001, 0x0002 },
4843 { 0x09, 0x0000, 0x0080 },
4844 { 0x19, 0x0000, 0x0224 }
4845 };
4846
4847 rtl_csi_access_enable_1(ioaddr);
4848
4849 rtl_ephy_init(ioaddr, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
4850
4851 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4852
4853 rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4854 rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4855 rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4856 rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4857 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
4858 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
4859 rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4860 rtl_w1w0_eri(ioaddr, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4861 rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4862 rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
4863 rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4864 ERIAR_EXGMAC);
4865
4866 RTL_W8(MaxTxPacketSize, EarlySize);
4867
4868 rtl_disable_clock_request(pdev);
4869
4870 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4871 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4872
4873 /* Adjust EEE LED frequency */
4874 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4875
4876 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4877 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4878 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4879}
4880
07ce4064
FR		 4881static void rtl_hw_start_8168(struct net_device *dev)
4882{
2dd99530
FR		 4883 struct rtl8169_private *tp = netdev_priv(dev);
4884 void __iomem *ioaddr = tp->mmio_addr;
0e485150 4885 struct pci_dev *pdev = tp->pci_dev;
2dd99530
FR		 4886
4887 RTL_W8(Cfg9346, Cfg9346_Unlock);
4888
f0298f81 4889 RTL_W8(MaxTxPacketSize, TxPacketMax);
2dd99530 4890
6f0333b8 4891 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
2dd99530 4892
0e485150 4893 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 4894
4895 RTL_W16(CPlusCmd, tp->cp_cmd);
4896
0e485150 4897 RTL_W16(IntrMitigate, 0x5151);
2dd99530 4898
0e485150 4899 /* Work around for RxFIFO overflow. */
811fd301 4900 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
0e485150
FR		 4901 tp->intr_event |= RxFIFOOver | PCSTimeout;
4902 tp->intr_event &= ~RxOverflow;
4903 }
4904
4905 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530 4906
b8363901
FR		 4907 rtl_set_rx_mode(dev);
4908
4909 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4910 (InterFrameGap << TxInterFrameGapShift));
2dd99530
FR		 4911
4912 RTL_R8(IntrMask);
4913
219a1e9d
FR		 4914 switch (tp->mac_version) {
4915 case RTL_GIGA_MAC_VER_11:
4916 rtl_hw_start_8168bb(ioaddr, pdev);
4804b3b3 4917 break;
219a1e9d
FR		 4918
4919 case RTL_GIGA_MAC_VER_12:
4920 case RTL_GIGA_MAC_VER_17:
4921 rtl_hw_start_8168bef(ioaddr, pdev);
4804b3b3 4922 break;
219a1e9d
FR		 4923
4924 case RTL_GIGA_MAC_VER_18:
ef3386f0 4925 rtl_hw_start_8168cp_1(ioaddr, pdev);
4804b3b3 4926 break;
219a1e9d
FR		 4927
4928 case RTL_GIGA_MAC_VER_19:
4929 rtl_hw_start_8168c_1(ioaddr, pdev);
4804b3b3 4930 break;
219a1e9d
FR		 4931
4932 case RTL_GIGA_MAC_VER_20:
4933 rtl_hw_start_8168c_2(ioaddr, pdev);
4804b3b3 4934 break;
219a1e9d 4935
197ff761
FR		 4936 case RTL_GIGA_MAC_VER_21:
4937 rtl_hw_start_8168c_3(ioaddr, pdev);
4804b3b3 4938 break;
197ff761 4939
6fb07058
FR		 4940 case RTL_GIGA_MAC_VER_22:
4941 rtl_hw_start_8168c_4(ioaddr, pdev);
4804b3b3 4942 break;
6fb07058 4943
ef3386f0
FR		 4944 case RTL_GIGA_MAC_VER_23:
4945 rtl_hw_start_8168cp_2(ioaddr, pdev);
4804b3b3 4946 break;
ef3386f0 4947
7f3e3d3a
FR		 4948 case RTL_GIGA_MAC_VER_24:
4949 rtl_hw_start_8168cp_3(ioaddr, pdev);
4804b3b3 4950 break;
7f3e3d3a 4951
5b538df9 4952 case RTL_GIGA_MAC_VER_25:
daf9df6d 4953 case RTL_GIGA_MAC_VER_26:
4954 case RTL_GIGA_MAC_VER_27:
5b538df9 4955 rtl_hw_start_8168d(ioaddr, pdev);
4804b3b3 4956 break;
5b538df9 4957
e6de30d6 4958 case RTL_GIGA_MAC_VER_28:
4959 rtl_hw_start_8168d_4(ioaddr, pdev);
4804b3b3 4960 break;
cecb5fd7 4961
4804b3b3 4962 case RTL_GIGA_MAC_VER_31:
4963 rtl_hw_start_8168dp(ioaddr, pdev);
4964 break;
4965
01dc7fec 4966 case RTL_GIGA_MAC_VER_32:
4967 case RTL_GIGA_MAC_VER_33:
70090424
HW		 4968 rtl_hw_start_8168e_1(ioaddr, pdev);
4969 break;
4970 case RTL_GIGA_MAC_VER_34:
4971 rtl_hw_start_8168e_2(ioaddr, pdev);
01dc7fec 4972 break;
e6de30d6 4973
c2218925
HW		 4974 case RTL_GIGA_MAC_VER_35:
4975 case RTL_GIGA_MAC_VER_36:
4976 rtl_hw_start_8168f_1(ioaddr, pdev);
4977 break;
4978
219a1e9d
FR		 4979 default:
4980 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
4981 dev->name, tp->mac_version);
4804b3b3 4982 break;
219a1e9d 4983 }
2dd99530 4984
0e485150
FR		 4985 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4986
b8363901
FR		 4987 RTL_W8(Cfg9346, Cfg9346_Lock);
4988
2dd99530 4989 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
07ce4064 4990}
1da177e4 4991
2857ffb7
FR		 4992#define R810X_CPCMD_QUIRK_MASK (\
4993 EnableBist | \
4994 Mac_dbgo_oe | \
4995 Force_half_dup | \
5edcc537 4996 Force_rxflow_en | \
2857ffb7
FR		 4997 Force_txflow_en | \
4998 Cxpl_dbg_sel | \
4999 ASF | \
5000 PktCntrDisable | \
d24e9aaf 5001 Mac_dbgo_sel)
2857ffb7
FR		 5002
5003static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
5004{
350f7596 5005 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 5006 { 0x01, 0, 0x6e65 },
5007 { 0x02, 0, 0x091f },
5008 { 0x03, 0, 0xc2f9 },
5009 { 0x06, 0, 0xafb5 },
5010 { 0x07, 0, 0x0e00 },
5011 { 0x19, 0, 0xec80 },
5012 { 0x01, 0, 0x2e65 },
5013 { 0x01, 0, 0x6e65 }
5014 };
5015 u8 cfg1;
5016
650e8d5d 5017 rtl_csi_access_enable_2(ioaddr);
2857ffb7
FR		 5018
5019 RTL_W8(DBG_REG, FIX_NAK_1);
5020
5021 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5022
5023 RTL_W8(Config1,
5024 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5025 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5026
5027 cfg1 = RTL_R8(Config1);
5028 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5029 RTL_W8(Config1, cfg1 & ~LEDS0);
5030
2857ffb7
FR		 5031 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
5032}
5033
5034static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
5035{
650e8d5d 5036 rtl_csi_access_enable_2(ioaddr);
2857ffb7
FR		 5037
5038 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5039
5040 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
5041 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2857ffb7
FR		 5042}
5043
5044static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
5045{
5046 rtl_hw_start_8102e_2(ioaddr, pdev);
5047
5048 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
5049}
5050
5a5e4443
HW		 5051static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
5052{
5053 static const struct ephy_info e_info_8105e_1[] = {
5054 { 0x07, 0, 0x4000 },
5055 { 0x19, 0, 0x0200 },
5056 { 0x19, 0, 0x0020 },
5057 { 0x1e, 0, 0x2000 },
5058 { 0x03, 0, 0x0001 },
5059 { 0x19, 0, 0x0100 },
5060 { 0x19, 0, 0x0004 },
5061 { 0x0a, 0, 0x0020 }
5062 };
5063
cecb5fd7 5064 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5a5e4443
HW		 5065 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5066
cecb5fd7 5067 /* Disable Early Tally Counter */
5a5e4443
HW		 5068 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
5069
5070 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4f6b00e5 5071 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5a5e4443
HW		 5072
5073 rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
5074}
5075
5076static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
5077{
5078 rtl_hw_start_8105e_1(ioaddr, pdev);
5079 rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
5080}
5081
07ce4064
FR		 5082static void rtl_hw_start_8101(struct net_device *dev)
5083{
cdf1a608
FR		 5084 struct rtl8169_private *tp = netdev_priv(dev);
5085 void __iomem *ioaddr = tp->mmio_addr;
5086 struct pci_dev *pdev = tp->pci_dev;
5087
811fd301 5088 if (tp->mac_version >= RTL_GIGA_MAC_VER_30) {
5089 tp->intr_event &= ~RxFIFOOver;
5090 tp->napi_event &= ~RxFIFOOver;
5091 }
5092
cecb5fd7
FR		 5093 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5094 tp->mac_version == RTL_GIGA_MAC_VER_16) {
e44daade 5095 int cap = pci_pcie_cap(pdev);
9c14ceaf
FR		 5096
5097 if (cap) {
5098 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
5099 PCI_EXP_DEVCTL_NOSNOOP_EN);
5100 }
cdf1a608
FR		 5101 }
5102
d24e9aaf
HW		 5103 RTL_W8(Cfg9346, Cfg9346_Unlock);
5104
2857ffb7
FR		 5105 switch (tp->mac_version) {
5106 case RTL_GIGA_MAC_VER_07:
5107 rtl_hw_start_8102e_1(ioaddr, pdev);
5108 break;
5109
5110 case RTL_GIGA_MAC_VER_08:
5111 rtl_hw_start_8102e_3(ioaddr, pdev);
5112 break;
5113
5114 case RTL_GIGA_MAC_VER_09:
5115 rtl_hw_start_8102e_2(ioaddr, pdev);
5116 break;
5a5e4443
HW		 5117
5118 case RTL_GIGA_MAC_VER_29:
5119 rtl_hw_start_8105e_1(ioaddr, pdev);
5120 break;
5121 case RTL_GIGA_MAC_VER_30:
5122 rtl_hw_start_8105e_2(ioaddr, pdev);
5123 break;
cdf1a608
FR		 5124 }
5125
d24e9aaf 5126 RTL_W8(Cfg9346, Cfg9346_Lock);
cdf1a608 5127
f0298f81 5128 RTL_W8(MaxTxPacketSize, TxPacketMax);
cdf1a608 5129
6f0333b8 5130 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
cdf1a608 5131
d24e9aaf 5132 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
cdf1a608
FR		 5133 RTL_W16(CPlusCmd, tp->cp_cmd);
5134
5135 RTL_W16(IntrMitigate, 0x0000);
5136
5137 rtl_set_rx_tx_desc_registers(tp, ioaddr);
5138
5139 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5140 rtl_set_rx_tx_config_registers(tp);
5141
cdf1a608
FR		 5142 RTL_R8(IntrMask);
5143
cdf1a608
FR		 5144 rtl_set_rx_mode(dev);
5145
5146 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
1da177e4
LT		 5147}
5148
5149static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5150{
d58d46b5
FR		 5151 struct rtl8169_private *tp = netdev_priv(dev);
5152
5153 if (new_mtu < ETH_ZLEN ||
5154 new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
1da177e4
LT		 5155 return -EINVAL;
5156
d58d46b5
FR		 5157 if (new_mtu > ETH_DATA_LEN)
5158 rtl_hw_jumbo_enable(tp);
5159 else
5160 rtl_hw_jumbo_disable(tp);
5161
1da177e4 5162 dev->mtu = new_mtu;
350fb32a
MM		 5163 netdev_update_features(dev);
5164
323bb685 5165 return 0;
1da177e4
LT		 5166}
5167
5168static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5169{
95e0918d 5170 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 5171 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5172}
5173
6f0333b8
ED		 5174static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5175 void **data_buff, struct RxDesc *desc)
1da177e4 5176{
48addcc9 5177 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
231aee63 5178 DMA_FROM_DEVICE);
48addcc9 5179
6f0333b8
ED		 5180 kfree(*data_buff);
5181 *data_buff = NULL;
1da177e4
LT		 5182 rtl8169_make_unusable_by_asic(desc);
5183}
5184
5185static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
5186{
5187 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5188
5189 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
5190}
5191
5192static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
5193 u32 rx_buf_sz)
5194{
5195 desc->addr = cpu_to_le64(mapping);
5196 wmb();
5197 rtl8169_mark_to_asic(desc, rx_buf_sz);
5198}
5199
6f0333b8
ED		 5200static inline void *rtl8169_align(void *data)
5201{
5202 return (void *)ALIGN((long)data, 16);
5203}
5204
0ecbe1ca
SG		 5205static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5206 struct RxDesc *desc)
1da177e4 5207{
6f0333b8 5208 void *data;
1da177e4 5209 dma_addr_t mapping;
48addcc9 5210 struct device *d = &tp->pci_dev->dev;
0ecbe1ca 5211 struct net_device *dev = tp->dev;
6f0333b8 5212 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
1da177e4 5213
6f0333b8
ED		 5214 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
5215 if (!data)
5216 return NULL;
e9f63f30 5217
6f0333b8
ED		 5218 if (rtl8169_align(data) != data) {
5219 kfree(data);
5220 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
5221 if (!data)
5222 return NULL;
5223 }
3eafe507 5224
48addcc9 5225 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
231aee63 5226 DMA_FROM_DEVICE);
d827d86b
SG		 5227 if (unlikely(dma_mapping_error(d, mapping))) {
5228 if (net_ratelimit())
5229 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
3eafe507 5230 goto err_out;
d827d86b 5231 }
1da177e4
LT		 5232
5233 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6f0333b8 5234 return data;
3eafe507
SG		 5235
5236err_out:
5237 kfree(data);
5238 return NULL;
1da177e4
LT		 5239}
5240
5241static void rtl8169_rx_clear(struct rtl8169_private *tp)
5242{
07d3f51f 5243 unsigned int i;
1da177e4
LT		 5244
5245 for (i = 0; i < NUM_RX_DESC; i++) {
6f0333b8
ED		 5246 if (tp->Rx_databuff[i]) {
5247 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
1da177e4
LT		 5248 tp->RxDescArray + i);
5249 }
5250 }
5251}
5252
0ecbe1ca 5253static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1da177e4 5254{
0ecbe1ca
SG		 5255 desc->opts1 |= cpu_to_le32(RingEnd);
5256}
5b0384f4 5257
0ecbe1ca
SG		 5258static int rtl8169_rx_fill(struct rtl8169_private *tp)
5259{
5260 unsigned int i;
1da177e4 5261
0ecbe1ca
SG		 5262 for (i = 0; i < NUM_RX_DESC; i++) {
5263 void *data;
4ae47c2d 5264
6f0333b8 5265 if (tp->Rx_databuff[i])
1da177e4 5266 continue;
bcf0bf90 5267
0ecbe1ca 5268 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6f0333b8
ED		 5269 if (!data) {
5270 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
0ecbe1ca 5271 goto err_out;
6f0333b8
ED		 5272 }
5273 tp->Rx_databuff[i] = data;
1da177e4 5274 }
1da177e4 5275
0ecbe1ca
SG		 5276 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5277 return 0;
5278
5279err_out:
5280 rtl8169_rx_clear(tp);
5281 return -ENOMEM;
1da177e4
LT		 5282}
5283
1da177e4
LT		 5284static int rtl8169_init_ring(struct net_device *dev)
5285{
5286 struct rtl8169_private *tp = netdev_priv(dev);
5287
5288 rtl8169_init_ring_indexes(tp);
5289
5290 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
6f0333b8 5291 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
1da177e4 5292
0ecbe1ca 5293 return rtl8169_rx_fill(tp);
1da177e4
LT		 5294}
5295
48addcc9 5296static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
1da177e4
LT		 5297 struct TxDesc *desc)
5298{
5299 unsigned int len = tx_skb->len;
5300
48addcc9
SG		 5301 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5302
1da177e4
LT		 5303 desc->opts1 = 0x00;
5304 desc->opts2 = 0x00;
5305 desc->addr = 0x00;
5306 tx_skb->len = 0;
5307}
5308
3eafe507
SG		 5309static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5310 unsigned int n)
1da177e4
LT		 5311{
5312 unsigned int i;
5313
3eafe507
SG		 5314 for (i = 0; i < n; i++) {
5315 unsigned int entry = (start + i) % NUM_TX_DESC;
1da177e4
LT		 5316 struct ring_info *tx_skb = tp->tx_skb + entry;
5317 unsigned int len = tx_skb->len;
5318
5319 if (len) {
5320 struct sk_buff *skb = tx_skb->skb;
5321
48addcc9 5322 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
1da177e4
LT		 5323 tp->TxDescArray + entry);
5324 if (skb) {
cac4b22f 5325 tp->dev->stats.tx_dropped++;
1da177e4
LT		 5326 dev_kfree_skb(skb);
5327 tx_skb->skb = NULL;
5328 }
1da177e4
LT		 5329 }
5330 }
3eafe507
SG		 5331}
5332
5333static void rtl8169_tx_clear(struct rtl8169_private *tp)
5334{
5335 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
1da177e4
LT		 5336 tp->cur_tx = tp->dirty_tx = 0;
5337}
5338
4422bcd4 5339static void rtl8169_schedule_work(struct net_device *dev)
1da177e4
LT		 5340{
5341 struct rtl8169_private *tp = netdev_priv(dev);
5342
4422bcd4 5343 schedule_work(&tp->wk.work);
1da177e4
LT		 5344}
5345
5346static void rtl8169_wait_for_quiescence(struct net_device *dev)
5347{
5348 struct rtl8169_private *tp = netdev_priv(dev);
5349 void __iomem *ioaddr = tp->mmio_addr;
5350
5351 synchronize_irq(dev->irq);
5352
5353 /* Wait for any pending NAPI task to complete */
bea3348e 5354 napi_disable(&tp->napi);
1da177e4 5355
811fd301 5356 rtl8169_irq_mask_and_ack(tp);
1da177e4 5357
d1d08d12
DM		 5358 tp->intr_mask = 0xffff;
5359 RTL_W16(IntrMask, tp->intr_event);
bea3348e 5360 napi_enable(&tp->napi);
1da177e4
LT		 5361}
5362
4422bcd4 5363static void rtl_reset_work(struct rtl8169_private *tp)
1da177e4 5364{
c4028958 5365 struct net_device *dev = tp->dev;
56de414c 5366 int i;
1da177e4 5367
eb2a021c
FR		 5368 rtnl_lock();
5369
1da177e4 5370 if (!netif_running(dev))
eb2a021c 5371 goto out_unlock;
1da177e4 5372
c7c2c39b 5373 rtl8169_hw_reset(tp);
5374
1da177e4
LT		 5375 rtl8169_wait_for_quiescence(dev);
5376
56de414c
FR		 5377 for (i = 0; i < NUM_RX_DESC; i++)
5378 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
5379
1da177e4 5380 rtl8169_tx_clear(tp);
c7c2c39b 5381 rtl8169_init_ring_indexes(tp);
1da177e4 5382
56de414c
FR		 5383 rtl_hw_start(dev);
5384 netif_wake_queue(dev);
5385 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
eb2a021c
FR		 5386
5387out_unlock:
5388 rtnl_unlock();
1da177e4
LT		 5389}
5390
5391static void rtl8169_tx_timeout(struct net_device *dev)
5392{
4422bcd4 5393 rtl8169_schedule_work(dev);
1da177e4
LT		 5394}
5395
5396static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2b7b4318 5397 u32 *opts)
1da177e4
LT		 5398{
5399 struct skb_shared_info *info = skb_shinfo(skb);
5400 unsigned int cur_frag, entry;
a6343afb 5401 struct TxDesc * uninitialized_var(txd);
48addcc9 5402 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 5403
5404 entry = tp->cur_tx;
5405 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
9e903e08 5406 const skb_frag_t *frag = info->frags + cur_frag;
1da177e4
LT		 5407 dma_addr_t mapping;
5408 u32 status, len;
5409 void *addr;
5410
5411 entry = (entry + 1) % NUM_TX_DESC;
5412
5413 txd = tp->TxDescArray + entry;
9e903e08 5414 len = skb_frag_size(frag);
929f6189 5415 addr = skb_frag_address(frag);
48addcc9 5416 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
d827d86b
SG		 5417 if (unlikely(dma_mapping_error(d, mapping))) {
5418 if (net_ratelimit())
5419 netif_err(tp, drv, tp->dev,
5420 "Failed to map TX fragments DMA!\n");
3eafe507 5421 goto err_out;
d827d86b 5422 }
1da177e4 5423
cecb5fd7 5424 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318
FR		 5425 status = opts[0] | len |
5426 (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 5427
5428 txd->opts1 = cpu_to_le32(status);
2b7b4318 5429 txd->opts2 = cpu_to_le32(opts[1]);
1da177e4
LT		 5430 txd->addr = cpu_to_le64(mapping);
5431
5432 tp->tx_skb[entry].len = len;
5433 }
5434
5435 if (cur_frag) {
5436 tp->tx_skb[entry].skb = skb;
5437 txd->opts1 |= cpu_to_le32(LastFrag);
5438 }
5439
5440 return cur_frag;
3eafe507
SG		 5441
5442err_out:
5443 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5444 return -EIO;
1da177e4
LT		 5445}
5446
2b7b4318
FR		 5447static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
5448 struct sk_buff *skb, u32 *opts)
1da177e4 5449{
2b7b4318 5450 const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
350fb32a 5451 u32 mss = skb_shinfo(skb)->gso_size;
2b7b4318 5452 int offset = info->opts_offset;
350fb32a 5453
2b7b4318
FR		 5454 if (mss) {
5455 opts[0] |= TD_LSO;
5456 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
5457 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 5458 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 5459
5460 if (ip->protocol == IPPROTO_TCP)
2b7b4318 5461 opts[offset] |= info->checksum.tcp;
1da177e4 5462 else if (ip->protocol == IPPROTO_UDP)
2b7b4318
FR		 5463 opts[offset] |= info->checksum.udp;
5464 else
5465 WARN_ON_ONCE(1);
1da177e4 5466 }
1da177e4
LT		 5467}
5468
61357325
SH		 5469static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5470 struct net_device *dev)
1da177e4
LT		 5471{
5472 struct rtl8169_private *tp = netdev_priv(dev);
3eafe507 5473 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
1da177e4
LT		 5474 struct TxDesc *txd = tp->TxDescArray + entry;
5475 void __iomem *ioaddr = tp->mmio_addr;
48addcc9 5476 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 5477 dma_addr_t mapping;
5478 u32 status, len;
2b7b4318 5479 u32 opts[2];
3eafe507 5480 int frags;
5b0384f4 5481
1da177e4 5482 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
bf82c189 5483 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
3eafe507 5484 goto err_stop_0;
1da177e4
LT		 5485 }
5486
5487 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3eafe507
SG		 5488 goto err_stop_0;
5489
5490 len = skb_headlen(skb);
48addcc9 5491 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
d827d86b
SG		 5492 if (unlikely(dma_mapping_error(d, mapping))) {
5493 if (net_ratelimit())
5494 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
3eafe507 5495 goto err_dma_0;
d827d86b 5496 }
3eafe507
SG		 5497
5498 tp->tx_skb[entry].len = len;
5499 txd->addr = cpu_to_le64(mapping);
1da177e4 5500
2b7b4318
FR		 5501 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
5502 opts[0] = DescOwn;
1da177e4 5503
2b7b4318
FR		 5504 rtl8169_tso_csum(tp, skb, opts);
5505
5506 frags = rtl8169_xmit_frags(tp, skb, opts);
3eafe507
SG		 5507 if (frags < 0)
5508 goto err_dma_1;
5509 else if (frags)
2b7b4318 5510 opts[0] |= FirstFrag;
3eafe507 5511 else {
2b7b4318 5512 opts[0] |= FirstFrag | LastFrag;
1da177e4
LT		 5513 tp->tx_skb[entry].skb = skb;
5514 }
5515
2b7b4318
FR		 5516 txd->opts2 = cpu_to_le32(opts[1]);
5517
1da177e4
LT		 5518 wmb();
5519
cecb5fd7 5520 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318 5521 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 5522 txd->opts1 = cpu_to_le32(status);
5523
1da177e4
LT		 5524 tp->cur_tx += frags + 1;
5525
4c020a96 5526 wmb();
1da177e4 5527
cecb5fd7 5528 RTL_W8(TxPoll, NPQ);
1da177e4
LT		 5529
5530 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
5531 netif_stop_queue(dev);
5532 smp_rmb();
5533 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
5534 netif_wake_queue(dev);
5535 }
5536
61357325 5537 return NETDEV_TX_OK;
1da177e4 5538
3eafe507 5539err_dma_1:
48addcc9 5540 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
3eafe507
SG		 5541err_dma_0:
5542 dev_kfree_skb(skb);
5543 dev->stats.tx_dropped++;
5544 return NETDEV_TX_OK;
5545
5546err_stop_0:
1da177e4 5547 netif_stop_queue(dev);
cebf8cc7 5548 dev->stats.tx_dropped++;
61357325 5549 return NETDEV_TX_BUSY;
1da177e4
LT		 5550}
5551
5552static void rtl8169_pcierr_interrupt(struct net_device *dev)
5553{
5554 struct rtl8169_private *tp = netdev_priv(dev);
5555 struct pci_dev *pdev = tp->pci_dev;
1da177e4
LT		 5556 u16 pci_status, pci_cmd;
5557
5558 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5559 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5560
bf82c189
JP		 5561 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5562 pci_cmd, pci_status);
1da177e4
LT		 5563
5564 /*
5565 * The recovery sequence below admits a very elaborated explanation:
5566 * - it seems to work;
d03902b8
FR		 5567 * - I did not see what else could be done;
5568 * - it makes iop3xx happy.
1da177e4
LT		 5569 *
5570 * Feel free to adjust to your needs.
5571 */
a27993f3 5572 if (pdev->broken_parity_status)
d03902b8
FR		 5573 pci_cmd &= ~PCI_COMMAND_PARITY;
5574 else
5575 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5576
5577 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 5578
5579 pci_write_config_word(pdev, PCI_STATUS,
5580 pci_status & (PCI_STATUS_DETECTED_PARITY |
5581 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5582 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5583
5584 /* The infamous DAC f*ckup only happens at boot time */
5585 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
e6de30d6 5586 void __iomem *ioaddr = tp->mmio_addr;
5587
bf82c189 5588 netif_info(tp, intr, dev, "disabling PCI DAC\n");
1da177e4
LT		 5589 tp->cp_cmd &= ~PCIDAC;
5590 RTL_W16(CPlusCmd, tp->cp_cmd);
5591 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 5592 }
5593
e6de30d6 5594 rtl8169_hw_reset(tp);
d03902b8 5595
4422bcd4 5596 rtl8169_schedule_work(dev);
1da177e4
LT		 5597}
5598
07d3f51f
FR		 5599static void rtl8169_tx_interrupt(struct net_device *dev,
5600 struct rtl8169_private *tp,
5601 void __iomem *ioaddr)
1da177e4
LT		 5602{
5603 unsigned int dirty_tx, tx_left;
5604
1da177e4
LT		 5605 dirty_tx = tp->dirty_tx;
5606 smp_rmb();
5607 tx_left = tp->cur_tx - dirty_tx;
5608
5609 while (tx_left > 0) {
5610 unsigned int entry = dirty_tx % NUM_TX_DESC;
5611 struct ring_info *tx_skb = tp->tx_skb + entry;
1da177e4
LT		 5612 u32 status;
5613
5614 rmb();
5615 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5616 if (status & DescOwn)
5617 break;
5618
48addcc9
SG		 5619 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5620 tp->TxDescArray + entry);
1da177e4 5621 if (status & LastFrag) {
cac4b22f
SG		 5622 dev->stats.tx_packets++;
5623 dev->stats.tx_bytes += tx_skb->skb->len;
87433bfc 5624 dev_kfree_skb(tx_skb->skb);
1da177e4
LT		 5625 tx_skb->skb = NULL;
5626 }
5627 dirty_tx++;
5628 tx_left--;
5629 }
5630
5631 if (tp->dirty_tx != dirty_tx) {
5632 tp->dirty_tx = dirty_tx;
5633 smp_wmb();
5634 if (netif_queue_stopped(dev) &&
5635 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
5636 netif_wake_queue(dev);
5637 }
d78ae2dc
FR		 5638 /*
5639 * 8168 hack: TxPoll requests are lost when the Tx packets are
5640 * too close. Let's kick an extra TxPoll request when a burst
5641 * of start_xmit activity is detected (if it is not detected,
5642 * it is slow enough). -- FR
5643 */
5644 smp_rmb();
5645 if (tp->cur_tx != dirty_tx)
5646 RTL_W8(TxPoll, NPQ);
1da177e4
LT		 5647 }
5648}
5649
126fa4b9
FR		 5650static inline int rtl8169_fragmented_frame(u32 status)
5651{
5652 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
5653}
5654
adea1ac7 5655static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
1da177e4 5656{
1da177e4
LT		 5657 u32 status = opts1 & RxProtoMask;
5658
5659 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
d5d3ebe3 5660 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
1da177e4
LT		 5661 skb->ip_summed = CHECKSUM_UNNECESSARY;
5662 else
bc8acf2c 5663 skb_checksum_none_assert(skb);
1da177e4
LT		 5664}
5665
6f0333b8
ED		 5666static struct sk_buff *rtl8169_try_rx_copy(void *data,
5667 struct rtl8169_private *tp,
5668 int pkt_size,
5669 dma_addr_t addr)
1da177e4 5670{
b449655f 5671 struct sk_buff *skb;
48addcc9 5672 struct device *d = &tp->pci_dev->dev;
b449655f 5673
6f0333b8 5674 data = rtl8169_align(data);
48addcc9 5675 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6f0333b8
ED		 5676 prefetch(data);
5677 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
5678 if (skb)
5679 memcpy(skb->data, data, pkt_size);
48addcc9
SG		 5680 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
5681
6f0333b8 5682 return skb;
1da177e4
LT		 5683}
5684
07d3f51f
FR		 5685static int rtl8169_rx_interrupt(struct net_device *dev,
5686 struct rtl8169_private *tp,
bea3348e 5687 void __iomem *ioaddr, u32 budget)
1da177e4
LT		 5688{
5689 unsigned int cur_rx, rx_left;
6f0333b8 5690 unsigned int count;
1da177e4 5691
1da177e4
LT		 5692 cur_rx = tp->cur_rx;
5693 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
865c652d 5694 rx_left = min(rx_left, budget);
1da177e4 5695
4dcb7d33 5696 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 5697 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 5698 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 5699 u32 status;
5700
5701 rmb();
e03f33af 5702 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
1da177e4
LT		 5703
5704 if (status & DescOwn)
5705 break;
4dcb7d33 5706 if (unlikely(status & RxRES)) {
bf82c189
JP		 5707 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
5708 status);
cebf8cc7 5709 dev->stats.rx_errors++;
1da177e4 5710 if (status & (RxRWT | RxRUNT))
cebf8cc7 5711 dev->stats.rx_length_errors++;
1da177e4 5712 if (status & RxCRC)
cebf8cc7 5713 dev->stats.rx_crc_errors++;
9dccf611 5714 if (status & RxFOVF) {
4422bcd4 5715 rtl8169_schedule_work(dev);
cebf8cc7 5716 dev->stats.rx_fifo_errors++;
9dccf611 5717 }
6f0333b8 5718 rtl8169_mark_to_asic(desc, rx_buf_sz);
1da177e4 5719 } else {
6f0333b8 5720 struct sk_buff *skb;
b449655f 5721 dma_addr_t addr = le64_to_cpu(desc->addr);
deb9d93c 5722 int pkt_size = (status & 0x00003fff) - 4;
1da177e4 5723
126fa4b9
FR		 5724 /*
5725 * The driver does not support incoming fragmented
5726 * frames. They are seen as a symptom of over-mtu
5727 * sized frames.
5728 */
5729 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 5730 dev->stats.rx_dropped++;
5731 dev->stats.rx_length_errors++;
6f0333b8 5732 rtl8169_mark_to_asic(desc, rx_buf_sz);
4dcb7d33 5733 continue;
126fa4b9
FR		 5734 }
5735
6f0333b8
ED		 5736 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
5737 tp, pkt_size, addr);
5738 rtl8169_mark_to_asic(desc, rx_buf_sz);
5739 if (!skb) {
5740 dev->stats.rx_dropped++;
5741 continue;
1da177e4
LT		 5742 }
5743
adea1ac7 5744 rtl8169_rx_csum(skb, status);
1da177e4
LT		 5745 skb_put(skb, pkt_size);
5746 skb->protocol = eth_type_trans(skb, dev);
5747
7a8fc77b
FR		 5748 rtl8169_rx_vlan_tag(desc, skb);
5749
56de414c 5750 napi_gro_receive(&tp->napi, skb);
1da177e4 5751
cebf8cc7
FR		 5752 dev->stats.rx_bytes += pkt_size;
5753 dev->stats.rx_packets++;
1da177e4 5754 }
6dccd16b
FR		 5755
5756 /* Work around for AMD plateform. */
95e0918d 5757 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
6dccd16b
FR		 5758 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
5759 desc->opts2 = 0;
5760 cur_rx++;
5761 }
1da177e4
LT		 5762 }
5763
5764 count = cur_rx - tp->cur_rx;
5765 tp->cur_rx = cur_rx;
5766
6f0333b8 5767 tp->dirty_rx += count;
1da177e4
LT		 5768
5769 return count;
5770}
5771
07d3f51f 5772static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 5773{
07d3f51f 5774 struct net_device *dev = dev_instance;
1da177e4 5775 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 5776 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 5777 int handled = 0;
865c652d 5778 int status;
1da177e4 5779
f11a377b
DD		 5780 /* loop handling interrupts until we have no new ones or
5781 * we hit a invalid/hotplug case.
5782 */
865c652d 5783 status = RTL_R16(IntrStatus);
f11a377b 5784 while (status && status != 0xffff) {
811fd301 5785 status &= tp->intr_event;
5786 if (!status)
5787 break;
5788
f11a377b 5789 handled = 1;
1da177e4 5790
f11a377b
DD		 5791 /* Handle all of the error cases first. These will reset
5792 * the chip, so just exit the loop.
5793 */
5794 if (unlikely(!netif_running(dev))) {
92fc43b4 5795 rtl8169_hw_reset(tp);
f11a377b
DD		 5796 break;
5797 }
1da177e4 5798
1519e57f
FR		 5799 if (unlikely(status & RxFIFOOver)) {
5800 switch (tp->mac_version) {
5801 /* Work around for rx fifo overflow */
5802 case RTL_GIGA_MAC_VER_11:
1519e57f
FR		 5803 netif_stop_queue(dev);
5804 rtl8169_tx_timeout(dev);
5805 goto done;
1519e57f
FR		 5806 default:
5807 break;
5808 }
f11a377b 5809 }
1da177e4 5810
f11a377b
DD		 5811 if (unlikely(status & SYSErr)) {
5812 rtl8169_pcierr_interrupt(dev);
5813 break;
5814 }
1da177e4 5815
f11a377b 5816 if (status & LinkChg)
e4fbce74 5817 __rtl8169_check_link_status(dev, tp, ioaddr, true);
0e485150 5818
f11a377b
DD		 5819 /* We need to see the lastest version of tp->intr_mask to
5820 * avoid ignoring an MSI interrupt and having to wait for
5821 * another event which may never come.
5822 */
5823 smp_rmb();
5824 if (status & tp->intr_mask & tp->napi_event) {
5825 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
5826 tp->intr_mask = ~tp->napi_event;
5827
5828 if (likely(napi_schedule_prep(&tp->napi)))
5829 __napi_schedule(&tp->napi);
bf82c189
JP		 5830 else
5831 netif_info(tp, intr, dev,
5832 "interrupt %04x in poll\n", status);
f11a377b 5833 }
1da177e4 5834
f11a377b
DD		 5835 /* We only get a new MSI interrupt when all active irq
5836 * sources on the chip have been acknowledged. So, ack
5837 * everything we've seen and check if new sources have become
5838 * active to avoid blocking all interrupts from the chip.
5839 */
5840 RTL_W16(IntrStatus,
5841 (status & RxFIFOOver) ? (status | RxOverflow) : status);
5842 status = RTL_R16(IntrStatus);
865c652d 5843 }
1519e57f 5844done:
1da177e4
LT		 5845 return IRQ_RETVAL(handled);
5846}
5847
4422bcd4
FR		 5848static void rtl_task(struct work_struct *work)
5849{
5850 struct rtl8169_private *tp =
5851 container_of(work, struct rtl8169_private, wk.work);
5852
5853 rtl_reset_work(tp);
5854}
5855
bea3348e 5856static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 5857{
bea3348e
SH		 5858 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5859 struct net_device *dev = tp->dev;
1da177e4 5860 void __iomem *ioaddr = tp->mmio_addr;
bea3348e 5861 int work_done;
1da177e4 5862
bea3348e 5863 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
1da177e4
LT		 5864 rtl8169_tx_interrupt(dev, tp, ioaddr);
5865
bea3348e 5866 if (work_done < budget) {
288379f0 5867 napi_complete(napi);
f11a377b
DD		 5868
5869 /* We need for force the visibility of tp->intr_mask
5870 * for other CPUs, as we can loose an MSI interrupt
5871 * and potentially wait for a retransmit timeout if we don't.
5872 * The posted write to IntrMask is safe, as it will
5873 * eventually make it to the chip and we won't loose anything
5874 * until it does.
1da177e4 5875 */
f11a377b 5876 tp->intr_mask = 0xffff;
4c020a96 5877 wmb();
0e485150 5878 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 5879 }
5880
bea3348e 5881 return work_done;
1da177e4 5882}
1da177e4 5883
523a6094
FR		 5884static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
5885{
5886 struct rtl8169_private *tp = netdev_priv(dev);
5887
5888 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5889 return;
5890
5891 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
5892 RTL_W32(RxMissed, 0);
5893}
5894
1da177e4
LT		 5895static void rtl8169_down(struct net_device *dev)
5896{
5897 struct rtl8169_private *tp = netdev_priv(dev);
5898 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 5899
4876cc1e 5900 del_timer_sync(&tp->timer);
1da177e4
LT		 5901
5902 netif_stop_queue(dev);
5903
93dd79e8 5904 napi_disable(&tp->napi);
93dd79e8 5905
1da177e4
LT		 5906 spin_lock_irq(&tp->lock);
5907
92fc43b4 5908 rtl8169_hw_reset(tp);
323bb685
SG		 5909 /*
5910 * At this point device interrupts can not be enabled in any function,
209e5ac8
FR		 5911 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
5912 * and napi is disabled (rtl8169_poll).
323bb685 5913 */
523a6094 5914 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 5915
5916 spin_unlock_irq(&tp->lock);
5917
5918 synchronize_irq(dev->irq);
5919
1da177e4 5920 /* Give a racing hard_start_xmit a few cycles to complete. */
fbd568a3 5921 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
1da177e4 5922
1da177e4
LT		 5923 rtl8169_tx_clear(tp);
5924
5925 rtl8169_rx_clear(tp);
065c27c1 5926
5927 rtl_pll_power_down(tp);
1da177e4
LT		 5928}
5929
5930static int rtl8169_close(struct net_device *dev)
5931{
5932 struct rtl8169_private *tp = netdev_priv(dev);
5933 struct pci_dev *pdev = tp->pci_dev;
5934
e1759441
RW		 5935 pm_runtime_get_sync(&pdev->dev);
5936
cecb5fd7 5937 /* Update counters before going down */
355423d0
IV		 5938 rtl8169_update_counters(dev);
5939
1da177e4
LT		 5940 rtl8169_down(dev);
5941
5942 free_irq(dev->irq, dev);
5943
82553bb6
SG		 5944 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5945 tp->RxPhyAddr);
5946 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5947 tp->TxPhyAddr);
1da177e4
LT		 5948 tp->TxDescArray = NULL;
5949 tp->RxDescArray = NULL;
5950
e1759441
RW		 5951 pm_runtime_put_sync(&pdev->dev);
5952
1da177e4
LT		 5953 return 0;
5954}
5955
07ce4064 5956static void rtl_set_rx_mode(struct net_device *dev)
1da177e4
LT		 5957{
5958 struct rtl8169_private *tp = netdev_priv(dev);
5959 void __iomem *ioaddr = tp->mmio_addr;
5960 unsigned long flags;
5961 u32 mc_filter[2]; /* Multicast hash filter */
07d3f51f 5962 int rx_mode;
1da177e4
LT		 5963 u32 tmp = 0;
5964
5965 if (dev->flags & IFF_PROMISC) {
5966 /* Unconditionally log net taps. */
bf82c189 5967 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
1da177e4
LT		 5968 rx_mode =
5969 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5970 AcceptAllPhys;
5971 mc_filter[1] = mc_filter[0] = 0xffffffff;
4cd24eaf 5972 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
8e95a202 5973 (dev->flags & IFF_ALLMULTI)) {
1da177e4
LT		 5974 /* Too many to filter perfectly -- accept all multicasts. */
5975 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5976 mc_filter[1] = mc_filter[0] = 0xffffffff;
5977 } else {
22bedad3 5978 struct netdev_hw_addr *ha;
07d3f51f 5979
1da177e4
LT		 5980 rx_mode = AcceptBroadcast | AcceptMyPhys;
5981 mc_filter[1] = mc_filter[0] = 0;
22bedad3
JP		 5982 netdev_for_each_mc_addr(ha, dev) {
5983 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
1da177e4
LT		 5984 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5985 rx_mode |= AcceptMulticast;
5986 }
5987 }
5988
5989 spin_lock_irqsave(&tp->lock, flags);
5990
1687b566 5991 tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
1da177e4 5992
f887cce8 5993 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
1087f4f4
FR		 5994 u32 data = mc_filter[0];
5995
5996 mc_filter[0] = swab32(mc_filter[1]);
5997 mc_filter[1] = swab32(data);
bcf0bf90
FR		 5998 }
5999
1da177e4 6000 RTL_W32(MAR0 + 4, mc_filter[1]);
78f1cd02 6001 RTL_W32(MAR0 + 0, mc_filter[0]);
1da177e4 6002
57a9f236
FR		 6003 RTL_W32(RxConfig, tmp);
6004
1da177e4
LT		 6005 spin_unlock_irqrestore(&tp->lock, flags);
6006}
6007
6008/**
6009 * rtl8169_get_stats - Get rtl8169 read/write statistics
6010 * @dev: The Ethernet Device to get statistics for
6011 *
6012 * Get TX/RX statistics for rtl8169
6013 */
6014static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
6015{
6016 struct rtl8169_private *tp = netdev_priv(dev);
6017 void __iomem *ioaddr = tp->mmio_addr;
6018 unsigned long flags;
6019
6020 if (netif_running(dev)) {
6021 spin_lock_irqsave(&tp->lock, flags);
523a6094 6022 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 6023 spin_unlock_irqrestore(&tp->lock, flags);
6024 }
5b0384f4 6025
cebf8cc7 6026 return &dev->stats;
1da177e4
LT		 6027}
6028
861ab440 6029static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 6030{
065c27c1 6031 struct rtl8169_private *tp = netdev_priv(dev);
6032
5d06a99f 6033 if (!netif_running(dev))
861ab440 6034 return;
5d06a99f 6035
065c27c1 6036 rtl_pll_power_down(tp);
6037
5d06a99f
FR		 6038 netif_device_detach(dev);
6039 netif_stop_queue(dev);
861ab440
RW		 6040}
6041
6042#ifdef CONFIG_PM
6043
6044static int rtl8169_suspend(struct device *device)
6045{
6046 struct pci_dev *pdev = to_pci_dev(device);
6047 struct net_device *dev = pci_get_drvdata(pdev);
5d06a99f 6048
861ab440 6049 rtl8169_net_suspend(dev);
1371fa6d 6050
5d06a99f
FR		 6051 return 0;
6052}
6053
e1759441
RW		 6054static void __rtl8169_resume(struct net_device *dev)
6055{
065c27c1 6056 struct rtl8169_private *tp = netdev_priv(dev);
6057
e1759441 6058 netif_device_attach(dev);
065c27c1 6059
6060 rtl_pll_power_up(tp);
6061
4422bcd4 6062 rtl8169_schedule_work(dev);
e1759441
RW		 6063}
6064
861ab440 6065static int rtl8169_resume(struct device *device)
5d06a99f 6066{
861ab440 6067 struct pci_dev *pdev = to_pci_dev(device);
5d06a99f 6068 struct net_device *dev = pci_get_drvdata(pdev);
fccec10b
SG		 6069 struct rtl8169_private *tp = netdev_priv(dev);
6070
6071 rtl8169_init_phy(dev, tp);
5d06a99f 6072
e1759441
RW		 6073 if (netif_running(dev))
6074 __rtl8169_resume(dev);
5d06a99f 6075
e1759441
RW		 6076 return 0;
6077}
6078
6079static int rtl8169_runtime_suspend(struct device *device)
6080{
6081 struct pci_dev *pdev = to_pci_dev(device);
6082 struct net_device *dev = pci_get_drvdata(pdev);
6083 struct rtl8169_private *tp = netdev_priv(dev);
6084
6085 if (!tp->TxDescArray)
6086 return 0;
6087
6088 spin_lock_irq(&tp->lock);
6089 tp->saved_wolopts = __rtl8169_get_wol(tp);
6090 __rtl8169_set_wol(tp, WAKE_ANY);
6091 spin_unlock_irq(&tp->lock);
6092
6093 rtl8169_net_suspend(dev);
6094
6095 return 0;
6096}
6097
6098static int rtl8169_runtime_resume(struct device *device)
6099{
6100 struct pci_dev *pdev = to_pci_dev(device);
6101 struct net_device *dev = pci_get_drvdata(pdev);
6102 struct rtl8169_private *tp = netdev_priv(dev);
6103
6104 if (!tp->TxDescArray)
6105 return 0;
6106
6107 spin_lock_irq(&tp->lock);
6108 __rtl8169_set_wol(tp, tp->saved_wolopts);
6109 tp->saved_wolopts = 0;
6110 spin_unlock_irq(&tp->lock);
6111
fccec10b
SG		 6112 rtl8169_init_phy(dev, tp);
6113
e1759441 6114 __rtl8169_resume(dev);
5d06a99f 6115
5d06a99f
FR		 6116 return 0;
6117}
6118
e1759441
RW		 6119static int rtl8169_runtime_idle(struct device *device)
6120{
6121 struct pci_dev *pdev = to_pci_dev(device);
6122 struct net_device *dev = pci_get_drvdata(pdev);
6123 struct rtl8169_private *tp = netdev_priv(dev);
6124
e4fbce74 6125 return tp->TxDescArray ? -EBUSY : 0;
e1759441
RW		 6126}
6127
47145210 6128static const struct dev_pm_ops rtl8169_pm_ops = {
cecb5fd7
FR		 6129 .suspend = rtl8169_suspend,
6130 .resume = rtl8169_resume,
6131 .freeze = rtl8169_suspend,
6132 .thaw = rtl8169_resume,
6133 .poweroff = rtl8169_suspend,
6134 .restore = rtl8169_resume,
6135 .runtime_suspend = rtl8169_runtime_suspend,
6136 .runtime_resume = rtl8169_runtime_resume,
6137 .runtime_idle = rtl8169_runtime_idle,
861ab440
RW		 6138};
6139
6140#define RTL8169_PM_OPS (&rtl8169_pm_ops)
6141
6142#else /* !CONFIG_PM */
6143
6144#define RTL8169_PM_OPS NULL
6145
6146#endif /* !CONFIG_PM */
6147
649b3b8c 6148static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6149{
6150 void __iomem *ioaddr = tp->mmio_addr;
6151
6152 /* WoL fails with 8168b when the receiver is disabled. */
6153 switch (tp->mac_version) {
6154 case RTL_GIGA_MAC_VER_11:
6155 case RTL_GIGA_MAC_VER_12:
6156 case RTL_GIGA_MAC_VER_17:
6157 pci_clear_master(tp->pci_dev);
6158
6159 RTL_W8(ChipCmd, CmdRxEnb);
6160 /* PCI commit */
6161 RTL_R8(ChipCmd);
6162 break;
6163 default:
6164 break;
6165 }
6166}
6167
1765f95d
FR		 6168static void rtl_shutdown(struct pci_dev *pdev)
6169{
861ab440 6170 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 6171 struct rtl8169_private *tp = netdev_priv(dev);
861ab440
RW		 6172
6173 rtl8169_net_suspend(dev);
1765f95d 6174
cecb5fd7 6175 /* Restore original MAC address */
cc098dc7
IV		 6176 rtl_rar_set(tp, dev->perm_addr);
6177
4bb3f522 6178 spin_lock_irq(&tp->lock);
6179
92fc43b4 6180 rtl8169_hw_reset(tp);
4bb3f522 6181
6182 spin_unlock_irq(&tp->lock);
6183
861ab440 6184 if (system_state == SYSTEM_POWER_OFF) {
649b3b8c 6185 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
6186 rtl_wol_suspend_quirk(tp);
6187 rtl_wol_shutdown_quirk(tp);
ca52efd5 6188 }
6189
861ab440
RW		 6190 pci_wake_from_d3(pdev, true);
6191 pci_set_power_state(pdev, PCI_D3hot);
6192 }
6193}
5d06a99f 6194
1da177e4
LT		 6195static struct pci_driver rtl8169_pci_driver = {
6196 .name = MODULENAME,
6197 .id_table = rtl8169_pci_tbl,
6198 .probe = rtl8169_init_one,
6199 .remove = __devexit_p(rtl8169_remove_one),
1765f95d 6200 .shutdown = rtl_shutdown,
861ab440 6201 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 6202};
6203
07d3f51f 6204static int __init rtl8169_init_module(void)
1da177e4 6205{
29917620 6206 return pci_register_driver(&rtl8169_pci_driver);
1da177e4
LT		 6207}
6208
07d3f51f 6209static void __exit rtl8169_cleanup_module(void)
1da177e4
LT		 6210{
6211 pci_unregister_driver(&rtl8169_pci_driver);
6212}
6213
6214module_init(rtl8169_init_module);
6215module_exit(rtl8169_cleanup_module);
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