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[mirror_ubuntu-focal-kernel.git] / drivers / net / ethernet / realtek / r8169.c
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1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
a6b7a407 25#include <linux/interrupt.h>
1da177e4 26#include <linux/dma-mapping.h>
e1759441 27#include <linux/pm_runtime.h>
bca03d5f 28#include <linux/firmware.h>
ba04c7c9 29#include <linux/pci-aspm.h>
70c71606 30#include <linux/prefetch.h>
1da177e4
LT		 31
32#include <asm/io.h>
33#include <asm/irq.h>
34
865c652d 35#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 36#define MODULENAME "r8169"
37#define PFX MODULENAME ": "
38
bca03d5f 39#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
40#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
01dc7fec 41#define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
42#define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
70090424 43#define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
c2218925
HW		 44#define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
45#define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
5a5e4443 46#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
7e18dca1 47#define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
b3d7b2f2 48#define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
5598bfe5 49#define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
c558386b 50#define FIRMWARE_8168G_1 "rtl_nic/rtl8168g-1.fw"
bca03d5f 51
1da177e4
LT		 52#ifdef RTL8169_DEBUG
53#define assert(expr) \
5b0384f4
FR		 54 if (!(expr)) { \
55 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
b39d66a8 56 #expr,__FILE__,__func__,__LINE__); \
5b0384f4 57 }
06fa7358
JP		 58#define dprintk(fmt, args...) \
59 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 60#else
61#define assert(expr) do {} while (0)
62#define dprintk(fmt, args...) do {} while (0)
63#endif /* RTL8169_DEBUG */
64
b57b7e5a 65#define R8169_MSG_DEFAULT \
f0e837d9 66 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 67
477206a0
JD		 68#define TX_SLOTS_AVAIL(tp) \
69 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
70
71/* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
72#define TX_FRAGS_READY_FOR(tp,nr_frags) \
73 (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
1da177e4 74
1da177e4
LT		 75/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
76 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 77static const int multicast_filter_limit = 32;
1da177e4 78
9c14ceaf 79#define MAX_READ_REQUEST_SHIFT 12
aee77e4a 80#define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
1da177e4
LT		 81#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
82
83#define R8169_REGS_SIZE 256
84#define R8169_NAPI_WEIGHT 64
85#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
86#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
1da177e4
LT		 87#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
88#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
89
90#define RTL8169_TX_TIMEOUT (6*HZ)
91#define RTL8169_PHY_TIMEOUT (10*HZ)
92
93/* write/read MMIO register */
94#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
95#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
96#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
97#define RTL_R8(reg) readb (ioaddr + (reg))
98#define RTL_R16(reg) readw (ioaddr + (reg))
06f555f3 99#define RTL_R32(reg) readl (ioaddr + (reg))
1da177e4
LT		 100
101enum mac_version {
85bffe6c
FR		 102 RTL_GIGA_MAC_VER_01 = 0,
103 RTL_GIGA_MAC_VER_02,
104 RTL_GIGA_MAC_VER_03,
105 RTL_GIGA_MAC_VER_04,
106 RTL_GIGA_MAC_VER_05,
107 RTL_GIGA_MAC_VER_06,
108 RTL_GIGA_MAC_VER_07,
109 RTL_GIGA_MAC_VER_08,
110 RTL_GIGA_MAC_VER_09,
111 RTL_GIGA_MAC_VER_10,
112 RTL_GIGA_MAC_VER_11,
113 RTL_GIGA_MAC_VER_12,
114 RTL_GIGA_MAC_VER_13,
115 RTL_GIGA_MAC_VER_14,
116 RTL_GIGA_MAC_VER_15,
117 RTL_GIGA_MAC_VER_16,
118 RTL_GIGA_MAC_VER_17,
119 RTL_GIGA_MAC_VER_18,
120 RTL_GIGA_MAC_VER_19,
121 RTL_GIGA_MAC_VER_20,
122 RTL_GIGA_MAC_VER_21,
123 RTL_GIGA_MAC_VER_22,
124 RTL_GIGA_MAC_VER_23,
125 RTL_GIGA_MAC_VER_24,
126 RTL_GIGA_MAC_VER_25,
127 RTL_GIGA_MAC_VER_26,
128 RTL_GIGA_MAC_VER_27,
129 RTL_GIGA_MAC_VER_28,
130 RTL_GIGA_MAC_VER_29,
131 RTL_GIGA_MAC_VER_30,
132 RTL_GIGA_MAC_VER_31,
133 RTL_GIGA_MAC_VER_32,
134 RTL_GIGA_MAC_VER_33,
70090424 135 RTL_GIGA_MAC_VER_34,
c2218925
HW		 136 RTL_GIGA_MAC_VER_35,
137 RTL_GIGA_MAC_VER_36,
7e18dca1 138 RTL_GIGA_MAC_VER_37,
b3d7b2f2 139 RTL_GIGA_MAC_VER_38,
5598bfe5 140 RTL_GIGA_MAC_VER_39,
c558386b
HW		 141 RTL_GIGA_MAC_VER_40,
142 RTL_GIGA_MAC_VER_41,
85bffe6c 143 RTL_GIGA_MAC_NONE = 0xff,
1da177e4
LT		 144};
145
2b7b4318
FR		 146enum rtl_tx_desc_version {
147 RTL_TD_0 = 0,
148 RTL_TD_1 = 1,
149};
150
d58d46b5
FR		 151#define JUMBO_1K ETH_DATA_LEN
152#define JUMBO_4K (4*1024 - ETH_HLEN - 2)
153#define JUMBO_6K (6*1024 - ETH_HLEN - 2)
154#define JUMBO_7K (7*1024 - ETH_HLEN - 2)
155#define JUMBO_9K (9*1024 - ETH_HLEN - 2)
156
157#define _R(NAME,TD,FW,SZ,B) { \
158 .name = NAME, \
159 .txd_version = TD, \
160 .fw_name = FW, \
161 .jumbo_max = SZ, \
162 .jumbo_tx_csum = B \
163}
1da177e4 164
3c6bee1d 165static const struct {
1da177e4 166 const char *name;
2b7b4318 167 enum rtl_tx_desc_version txd_version;
953a12cc 168 const char *fw_name;
d58d46b5
FR		 169 u16 jumbo_max;
170 bool jumbo_tx_csum;
85bffe6c
FR		 171} rtl_chip_infos[] = {
172 /* PCI devices. */
173 [RTL_GIGA_MAC_VER_01] =
d58d46b5 174 _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 175 [RTL_GIGA_MAC_VER_02] =
d58d46b5 176 _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 177 [RTL_GIGA_MAC_VER_03] =
d58d46b5 178 _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 179 [RTL_GIGA_MAC_VER_04] =
d58d46b5 180 _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 181 [RTL_GIGA_MAC_VER_05] =
d58d46b5 182 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 183 [RTL_GIGA_MAC_VER_06] =
d58d46b5 184 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c
FR		 185 /* PCI-E devices. */
186 [RTL_GIGA_MAC_VER_07] =
d58d46b5 187 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 188 [RTL_GIGA_MAC_VER_08] =
d58d46b5 189 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 190 [RTL_GIGA_MAC_VER_09] =
d58d46b5 191 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 192 [RTL_GIGA_MAC_VER_10] =
d58d46b5 193 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 194 [RTL_GIGA_MAC_VER_11] =
d58d46b5 195 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
85bffe6c 196 [RTL_GIGA_MAC_VER_12] =
d58d46b5 197 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
85bffe6c 198 [RTL_GIGA_MAC_VER_13] =
d58d46b5 199 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 200 [RTL_GIGA_MAC_VER_14] =
d58d46b5 201 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 202 [RTL_GIGA_MAC_VER_15] =
d58d46b5 203 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 204 [RTL_GIGA_MAC_VER_16] =
d58d46b5 205 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 206 [RTL_GIGA_MAC_VER_17] =
d58d46b5 207 _R("RTL8168b/8111b", RTL_TD_1, NULL, JUMBO_4K, false),
85bffe6c 208 [RTL_GIGA_MAC_VER_18] =
d58d46b5 209 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 210 [RTL_GIGA_MAC_VER_19] =
d58d46b5 211 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 212 [RTL_GIGA_MAC_VER_20] =
d58d46b5 213 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 214 [RTL_GIGA_MAC_VER_21] =
d58d46b5 215 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 216 [RTL_GIGA_MAC_VER_22] =
d58d46b5 217 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 218 [RTL_GIGA_MAC_VER_23] =
d58d46b5 219 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 220 [RTL_GIGA_MAC_VER_24] =
d58d46b5 221 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 222 [RTL_GIGA_MAC_VER_25] =
d58d46b5
FR		 223 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1,
224 JUMBO_9K, false),
85bffe6c 225 [RTL_GIGA_MAC_VER_26] =
d58d46b5
FR		 226 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2,
227 JUMBO_9K, false),
85bffe6c 228 [RTL_GIGA_MAC_VER_27] =
d58d46b5 229 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 230 [RTL_GIGA_MAC_VER_28] =
d58d46b5 231 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 232 [RTL_GIGA_MAC_VER_29] =
d58d46b5
FR		 233 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
234 JUMBO_1K, true),
85bffe6c 235 [RTL_GIGA_MAC_VER_30] =
d58d46b5
FR		 236 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
237 JUMBO_1K, true),
85bffe6c 238 [RTL_GIGA_MAC_VER_31] =
d58d46b5 239 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 240 [RTL_GIGA_MAC_VER_32] =
d58d46b5
FR		 241 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1,
242 JUMBO_9K, false),
85bffe6c 243 [RTL_GIGA_MAC_VER_33] =
d58d46b5
FR		 244 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2,
245 JUMBO_9K, false),
70090424 246 [RTL_GIGA_MAC_VER_34] =
d58d46b5
FR		 247 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
248 JUMBO_9K, false),
c2218925 249 [RTL_GIGA_MAC_VER_35] =
d58d46b5
FR		 250 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1,
251 JUMBO_9K, false),
c2218925 252 [RTL_GIGA_MAC_VER_36] =
d58d46b5
FR		 253 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2,
254 JUMBO_9K, false),
7e18dca1
HW		 255 [RTL_GIGA_MAC_VER_37] =
256 _R("RTL8402", RTL_TD_1, FIRMWARE_8402_1,
257 JUMBO_1K, true),
b3d7b2f2
HW		 258 [RTL_GIGA_MAC_VER_38] =
259 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_1,
260 JUMBO_9K, false),
5598bfe5
HW		 261 [RTL_GIGA_MAC_VER_39] =
262 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_1,
263 JUMBO_1K, true),
c558386b
HW		 264 [RTL_GIGA_MAC_VER_40] =
265 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_1,
266 JUMBO_9K, false),
267 [RTL_GIGA_MAC_VER_41] =
268 _R("RTL8168g/8111g", RTL_TD_1, NULL, JUMBO_9K, false),
953a12cc 269};
85bffe6c 270#undef _R
953a12cc 271
bcf0bf90
FR		 272enum cfg_version {
273 RTL_CFG_0 = 0x00,
274 RTL_CFG_1,
275 RTL_CFG_2
276};
277
a3aa1884 278static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
bcf0bf90 279 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 280 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 281 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 282 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90 283 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
2a35cfa5
FR		 284 { PCI_VENDOR_ID_DLINK, 0x4300,
285 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
bcf0bf90 286 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
93a3aa25 287 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
bc1660b5 288 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 289 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
290 { PCI_VENDOR_ID_LINKSYS, 0x1032,
291 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 292 { 0x0001, 0x8168,
293 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 294 {0,},
295};
296
297MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
298
6f0333b8 299static int rx_buf_sz = 16383;
4300e8c7 300static int use_dac;
b57b7e5a
SH		 301static struct {
302 u32 msg_enable;
303} debug = { -1 };
1da177e4 304
07d3f51f
FR		 305enum rtl_registers {
306 MAC0 = 0, /* Ethernet hardware address. */
773d2021 307 MAC4 = 4,
07d3f51f
FR		 308 MAR0 = 8, /* Multicast filter. */
309 CounterAddrLow = 0x10,
310 CounterAddrHigh = 0x14,
311 TxDescStartAddrLow = 0x20,
312 TxDescStartAddrHigh = 0x24,
313 TxHDescStartAddrLow = 0x28,
314 TxHDescStartAddrHigh = 0x2c,
315 FLASH = 0x30,
316 ERSR = 0x36,
317 ChipCmd = 0x37,
318 TxPoll = 0x38,
319 IntrMask = 0x3c,
320 IntrStatus = 0x3e,
4f6b00e5 321
07d3f51f 322 TxConfig = 0x40,
4f6b00e5
HW		 323#define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
324#define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
2b7b4318 325
4f6b00e5
HW		 326 RxConfig = 0x44,
327#define RX128_INT_EN (1 << 15) /* 8111c and later */
328#define RX_MULTI_EN (1 << 14) /* 8111c only */
329#define RXCFG_FIFO_SHIFT 13
330 /* No threshold before first PCI xfer */
331#define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
332#define RXCFG_DMA_SHIFT 8
333 /* Unlimited maximum PCI burst. */
334#define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
2b7b4318 335
07d3f51f
FR		 336 RxMissed = 0x4c,
337 Cfg9346 = 0x50,
338 Config0 = 0x51,
339 Config1 = 0x52,
340 Config2 = 0x53,
d387b427
FR		 341#define PME_SIGNAL (1 << 5) /* 8168c and later */
342
07d3f51f
FR		 343 Config3 = 0x54,
344 Config4 = 0x55,
345 Config5 = 0x56,
346 MultiIntr = 0x5c,
347 PHYAR = 0x60,
07d3f51f
FR		 348 PHYstatus = 0x6c,
349 RxMaxSize = 0xda,
350 CPlusCmd = 0xe0,
351 IntrMitigate = 0xe2,
352 RxDescAddrLow = 0xe4,
353 RxDescAddrHigh = 0xe8,
f0298f81 354 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
355
356#define NoEarlyTx 0x3f /* Max value : no early transmit. */
357
358 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
359
360#define TxPacketMax (8064 >> 7)
3090bd9a 361#define EarlySize 0x27
f0298f81 362
07d3f51f
FR		 363 FuncEvent = 0xf0,
364 FuncEventMask = 0xf4,
365 FuncPresetState = 0xf8,
366 FuncForceEvent = 0xfc,
1da177e4
LT		 367};
368
f162a5d1
FR		 369enum rtl8110_registers {
370 TBICSR = 0x64,
371 TBI_ANAR = 0x68,
372 TBI_LPAR = 0x6a,
373};
374
375enum rtl8168_8101_registers {
376 CSIDR = 0x64,
377 CSIAR = 0x68,
378#define CSIAR_FLAG 0x80000000
379#define CSIAR_WRITE_CMD 0x80000000
380#define CSIAR_BYTE_ENABLE 0x0f
381#define CSIAR_BYTE_ENABLE_SHIFT 12
382#define CSIAR_ADDR_MASK 0x0fff
7e18dca1
HW		 383#define CSIAR_FUNC_CARD 0x00000000
384#define CSIAR_FUNC_SDIO 0x00010000
385#define CSIAR_FUNC_NIC 0x00020000
065c27c1 386 PMCH = 0x6f,
f162a5d1
FR		 387 EPHYAR = 0x80,
388#define EPHYAR_FLAG 0x80000000
389#define EPHYAR_WRITE_CMD 0x80000000
390#define EPHYAR_REG_MASK 0x1f
391#define EPHYAR_REG_SHIFT 16
392#define EPHYAR_DATA_MASK 0xffff
5a5e4443 393 DLLPR = 0xd0,
4f6b00e5 394#define PFM_EN (1 << 6)
f162a5d1
FR		 395 DBG_REG = 0xd1,
396#define FIX_NAK_1 (1 << 4)
397#define FIX_NAK_2 (1 << 3)
5a5e4443
HW		 398 TWSI = 0xd2,
399 MCU = 0xd3,
4f6b00e5 400#define NOW_IS_OOB (1 << 7)
c558386b
HW		 401#define TX_EMPTY (1 << 5)
402#define RX_EMPTY (1 << 4)
403#define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
5a5e4443
HW		 404#define EN_NDP (1 << 3)
405#define EN_OOB_RESET (1 << 2)
c558386b 406#define LINK_LIST_RDY (1 << 1)
daf9df6d 407 EFUSEAR = 0xdc,
408#define EFUSEAR_FLAG 0x80000000
409#define EFUSEAR_WRITE_CMD 0x80000000
410#define EFUSEAR_READ_CMD 0x00000000
411#define EFUSEAR_REG_MASK 0x03ff
412#define EFUSEAR_REG_SHIFT 8
413#define EFUSEAR_DATA_MASK 0xff
f162a5d1
FR		 414};
415
c0e45c1c 416enum rtl8168_registers {
4f6b00e5
HW		 417 LED_FREQ = 0x1a,
418 EEE_LED = 0x1b,
b646d900 419 ERIDR = 0x70,
420 ERIAR = 0x74,
421#define ERIAR_FLAG 0x80000000
422#define ERIAR_WRITE_CMD 0x80000000
423#define ERIAR_READ_CMD 0x00000000
424#define ERIAR_ADDR_BYTE_ALIGN 4
b646d900 425#define ERIAR_TYPE_SHIFT 16
4f6b00e5
HW		 426#define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
427#define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
428#define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
429#define ERIAR_MASK_SHIFT 12
430#define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
431#define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
c558386b 432#define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
4f6b00e5 433#define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
c0e45c1c 434 EPHY_RXER_NUM = 0x7c,
435 OCPDR = 0xb0, /* OCP GPHY access */
436#define OCPDR_WRITE_CMD 0x80000000
437#define OCPDR_READ_CMD 0x00000000
438#define OCPDR_REG_MASK 0x7f
439#define OCPDR_GPHY_REG_SHIFT 16
440#define OCPDR_DATA_MASK 0xffff
441 OCPAR = 0xb4,
442#define OCPAR_FLAG 0x80000000
443#define OCPAR_GPHY_WRITE_CMD 0x8000f060
444#define OCPAR_GPHY_READ_CMD 0x0000f060
c558386b 445 GPHY_OCP = 0xb8,
01dc7fec 446 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
447 MISC = 0xf0, /* 8168e only. */
cecb5fd7 448#define TXPLA_RST (1 << 29)
5598bfe5 449#define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
4f6b00e5 450#define PWM_EN (1 << 22)
c558386b 451#define RXDV_GATED_EN (1 << 19)
5598bfe5 452#define EARLY_TALLY_EN (1 << 16)
d64ec841 453#define FORCE_CLK (1 << 15) /* force clock request */
c0e45c1c 454};
455
07d3f51f 456enum rtl_register_content {
1da177e4 457 /* InterruptStatusBits */
07d3f51f
FR		 458 SYSErr = 0x8000,
459 PCSTimeout = 0x4000,
460 SWInt = 0x0100,
461 TxDescUnavail = 0x0080,
462 RxFIFOOver = 0x0040,
463 LinkChg = 0x0020,
464 RxOverflow = 0x0010,
465 TxErr = 0x0008,
466 TxOK = 0x0004,
467 RxErr = 0x0002,
468 RxOK = 0x0001,
1da177e4
LT		 469
470 /* RxStatusDesc */
e03f33af 471 RxBOVF = (1 << 24),
9dccf611
FR		 472 RxFOVF = (1 << 23),
473 RxRWT = (1 << 22),
474 RxRES = (1 << 21),
475 RxRUNT = (1 << 20),
476 RxCRC = (1 << 19),
1da177e4
LT		 477
478 /* ChipCmdBits */
4f6b00e5 479 StopReq = 0x80,
07d3f51f
FR		 480 CmdReset = 0x10,
481 CmdRxEnb = 0x08,
482 CmdTxEnb = 0x04,
483 RxBufEmpty = 0x01,
1da177e4 484
275391a4
FR		 485 /* TXPoll register p.5 */
486 HPQ = 0x80, /* Poll cmd on the high prio queue */
487 NPQ = 0x40, /* Poll cmd on the low prio queue */
488 FSWInt = 0x01, /* Forced software interrupt */
489
1da177e4 490 /* Cfg9346Bits */
07d3f51f
FR		 491 Cfg9346_Lock = 0x00,
492 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 493
494 /* rx_mode_bits */
07d3f51f
FR		 495 AcceptErr = 0x20,
496 AcceptRunt = 0x10,
497 AcceptBroadcast = 0x08,
498 AcceptMulticast = 0x04,
499 AcceptMyPhys = 0x02,
500 AcceptAllPhys = 0x01,
1687b566 501#define RX_CONFIG_ACCEPT_MASK 0x3f
1da177e4 502
1da177e4
LT		 503 /* TxConfigBits */
504 TxInterFrameGapShift = 24,
505 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
506
5d06a99f 507 /* Config1 register p.24 */
f162a5d1
FR		 508 LEDS1 = (1 << 7),
509 LEDS0 = (1 << 6),
f162a5d1
FR		 510 Speed_down = (1 << 4),
511 MEMMAP = (1 << 3),
512 IOMAP = (1 << 2),
513 VPD = (1 << 1),
5d06a99f
FR		 514 PMEnable = (1 << 0), /* Power Management Enable */
515
6dccd16b 516 /* Config2 register p. 25 */
d64ec841 517 ClkReqEn = (1 << 7), /* Clock Request Enable */
2ca6cf06 518 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
6dccd16b
FR		 519 PCI_Clock_66MHz = 0x01,
520 PCI_Clock_33MHz = 0x00,
521
61a4dcc2
FR		 522 /* Config3 register p.25 */
523 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
524 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
d58d46b5 525 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
f162a5d1 526 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 527
d58d46b5
FR		 528 /* Config4 register */
529 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
530
5d06a99f 531 /* Config5 register p.27 */
61a4dcc2
FR		 532 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
533 MWF = (1 << 5), /* Accept Multicast wakeup frame */
534 UWF = (1 << 4), /* Accept Unicast wakeup frame */
cecb5fd7 535 Spi_en = (1 << 3),
61a4dcc2 536 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f 537 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
d64ec841 538 ASPM_en = (1 << 0), /* ASPM enable */
5d06a99f 539
1da177e4
LT		 540 /* TBICSR p.28 */
541 TBIReset = 0x80000000,
542 TBILoopback = 0x40000000,
543 TBINwEnable = 0x20000000,
544 TBINwRestart = 0x10000000,
545 TBILinkOk = 0x02000000,
546 TBINwComplete = 0x01000000,
547
548 /* CPlusCmd p.31 */
f162a5d1
FR		 549 EnableBist = (1 << 15), // 8168 8101
550 Mac_dbgo_oe = (1 << 14), // 8168 8101
551 Normal_mode = (1 << 13), // unused
552 Force_half_dup = (1 << 12), // 8168 8101
553 Force_rxflow_en = (1 << 11), // 8168 8101
554 Force_txflow_en = (1 << 10), // 8168 8101
555 Cxpl_dbg_sel = (1 << 9), // 8168 8101
556 ASF = (1 << 8), // 8168 8101
557 PktCntrDisable = (1 << 7), // 8168 8101
558 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 559 RxVlan = (1 << 6),
560 RxChkSum = (1 << 5),
561 PCIDAC = (1 << 4),
562 PCIMulRW = (1 << 3),
0e485150
FR		 563 INTT_0 = 0x0000, // 8168
564 INTT_1 = 0x0001, // 8168
565 INTT_2 = 0x0002, // 8168
566 INTT_3 = 0x0003, // 8168
1da177e4
LT		 567
568 /* rtl8169_PHYstatus */
07d3f51f
FR		 569 TBI_Enable = 0x80,
570 TxFlowCtrl = 0x40,
571 RxFlowCtrl = 0x20,
572 _1000bpsF = 0x10,
573 _100bps = 0x08,
574 _10bps = 0x04,
575 LinkStatus = 0x02,
576 FullDup = 0x01,
1da177e4 577
1da177e4 578 /* _TBICSRBit */
07d3f51f 579 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 580
581 /* DumpCounterCommand */
07d3f51f 582 CounterDump = 0x8,
1da177e4
LT		 583};
584
2b7b4318
FR		 585enum rtl_desc_bit {
586 /* First doubleword. */
1da177e4
LT		 587 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
588 RingEnd = (1 << 30), /* End of descriptor ring */
589 FirstFrag = (1 << 29), /* First segment of a packet */
590 LastFrag = (1 << 28), /* Final segment of a packet */
2b7b4318
FR		 591};
592
593/* Generic case. */
594enum rtl_tx_desc_bit {
595 /* First doubleword. */
596 TD_LSO = (1 << 27), /* Large Send Offload */
597#define TD_MSS_MAX 0x07ffu /* MSS value */
1da177e4 598
2b7b4318
FR		 599 /* Second doubleword. */
600 TxVlanTag = (1 << 17), /* Add VLAN tag */
601};
602
603/* 8169, 8168b and 810x except 8102e. */
604enum rtl_tx_desc_bit_0 {
605 /* First doubleword. */
606#define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
607 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
608 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
609 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
610};
611
612/* 8102e, 8168c and beyond. */
613enum rtl_tx_desc_bit_1 {
614 /* Second doubleword. */
615#define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
616 TD1_IP_CS = (1 << 29), /* Calculate IP checksum */
617 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
618 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
619};
1da177e4 620
2b7b4318
FR		 621static const struct rtl_tx_desc_info {
622 struct {
623 u32 udp;
624 u32 tcp;
625 } checksum;
626 u16 mss_shift;
627 u16 opts_offset;
628} tx_desc_info [] = {
629 [RTL_TD_0] = {
630 .checksum = {
631 .udp = TD0_IP_CS | TD0_UDP_CS,
632 .tcp = TD0_IP_CS | TD0_TCP_CS
633 },
634 .mss_shift = TD0_MSS_SHIFT,
635 .opts_offset = 0
636 },
637 [RTL_TD_1] = {
638 .checksum = {
639 .udp = TD1_IP_CS | TD1_UDP_CS,
640 .tcp = TD1_IP_CS | TD1_TCP_CS
641 },
642 .mss_shift = TD1_MSS_SHIFT,
643 .opts_offset = 1
644 }
645};
646
647enum rtl_rx_desc_bit {
1da177e4
LT		 648 /* Rx private */
649 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
650 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
651
652#define RxProtoUDP (PID1)
653#define RxProtoTCP (PID0)
654#define RxProtoIP (PID1 | PID0)
655#define RxProtoMask RxProtoIP
656
657 IPFail = (1 << 16), /* IP checksum failed */
658 UDPFail = (1 << 15), /* UDP/IP checksum failed */
659 TCPFail = (1 << 14), /* TCP/IP checksum failed */
660 RxVlanTag = (1 << 16), /* VLAN tag available */
661};
662
663#define RsvdMask 0x3fffc000
664
665struct TxDesc {
6cccd6e7
REB		 666 __le32 opts1;
667 __le32 opts2;
668 __le64 addr;
1da177e4
LT		 669};
670
671struct RxDesc {
6cccd6e7
REB		 672 __le32 opts1;
673 __le32 opts2;
674 __le64 addr;
1da177e4
LT		 675};
676
677struct ring_info {
678 struct sk_buff *skb;
679 u32 len;
680 u8 __pad[sizeof(void *) - sizeof(u32)];
681};
682
f23e7fda 683enum features {
ccdffb9a
FR		 684 RTL_FEATURE_WOL = (1 << 0),
685 RTL_FEATURE_MSI = (1 << 1),
686 RTL_FEATURE_GMII = (1 << 2),
e0c07557 687 RTL_FEATURE_FW_LOADED = (1 << 3),
f23e7fda
FR		 688};
689
355423d0
IV		 690struct rtl8169_counters {
691 __le64 tx_packets;
692 __le64 rx_packets;
693 __le64 tx_errors;
694 __le32 rx_errors;
695 __le16 rx_missed;
696 __le16 align_errors;
697 __le32 tx_one_collision;
698 __le32 tx_multi_collision;
699 __le64 rx_unicast;
700 __le64 rx_broadcast;
701 __le32 rx_multicast;
702 __le16 tx_aborted;
703 __le16 tx_underun;
704};
705
da78dbff 706enum rtl_flag {
6c4a70c5 707 RTL_FLAG_TASK_ENABLED,
da78dbff
FR		 708 RTL_FLAG_TASK_SLOW_PENDING,
709 RTL_FLAG_TASK_RESET_PENDING,
710 RTL_FLAG_TASK_PHY_PENDING,
711 RTL_FLAG_MAX
712};
713
8027aa24
JW		 714struct rtl8169_stats {
715 u64 packets;
716 u64 bytes;
717 struct u64_stats_sync syncp;
718};
719
1da177e4
LT		 720struct rtl8169_private {
721 void __iomem *mmio_addr; /* memory map physical address */
cecb5fd7 722 struct pci_dev *pci_dev;
c4028958 723 struct net_device *dev;
bea3348e 724 struct napi_struct napi;
b57b7e5a 725 u32 msg_enable;
2b7b4318
FR		 726 u16 txd_version;
727 u16 mac_version;
1da177e4
LT		 728 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
729 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
730 u32 dirty_rx;
731 u32 dirty_tx;
8027aa24
JW		 732 struct rtl8169_stats rx_stats;
733 struct rtl8169_stats tx_stats;
1da177e4
LT		 734 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
735 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
736 dma_addr_t TxPhyAddr;
737 dma_addr_t RxPhyAddr;
6f0333b8 738 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
1da177e4 739 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
1da177e4
LT		 740 struct timer_list timer;
741 u16 cp_cmd;
da78dbff
FR		 742
743 u16 event_slow;
c0e45c1c 744
745 struct mdio_ops {
24192210
FR		 746 void (*write)(struct rtl8169_private *, int, int);
747 int (*read)(struct rtl8169_private *, int);
c0e45c1c 748 } mdio_ops;
749
065c27c1 750 struct pll_power_ops {
751 void (*down)(struct rtl8169_private *);
752 void (*up)(struct rtl8169_private *);
753 } pll_power_ops;
754
d58d46b5
FR		 755 struct jumbo_ops {
756 void (*enable)(struct rtl8169_private *);
757 void (*disable)(struct rtl8169_private *);
758 } jumbo_ops;
759
beb1fe18 760 struct csi_ops {
52989f0e
FR		 761 void (*write)(struct rtl8169_private *, int, int);
762 u32 (*read)(struct rtl8169_private *, int);
beb1fe18
HW		 763 } csi_ops;
764
54405cde 765 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
ccdffb9a 766 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
4da19633 767 void (*phy_reset_enable)(struct rtl8169_private *tp);
07ce4064 768 void (*hw_start)(struct net_device *);
4da19633 769 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
1da177e4 770 unsigned int (*link_ok)(void __iomem *);
8b4ab28d 771 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
4422bcd4
FR		 772
773 struct {
da78dbff
FR		 774 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
775 struct mutex mutex;
4422bcd4
FR		 776 struct work_struct work;
777 } wk;
778
f23e7fda 779 unsigned features;
ccdffb9a
FR		 780
781 struct mii_if_info mii;
355423d0 782 struct rtl8169_counters counters;
e1759441 783 u32 saved_wolopts;
e03f33af 784 u32 opts1_mask;
f1e02ed1 785
b6ffd97f
FR		 786 struct rtl_fw {
787 const struct firmware *fw;
1c361efb
FR		 788
789#define RTL_VER_SIZE 32
790
791 char version[RTL_VER_SIZE];
792
793 struct rtl_fw_phy_action {
794 __le32 *code;
795 size_t size;
796 } phy_action;
b6ffd97f 797 } *rtl_fw;
497888cf 798#define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
c558386b
HW		 799
800 u32 ocp_base;
1da177e4
LT		 801};
802
979b6c13 803MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 804MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 805module_param(use_dac, int, 0);
4300e8c7 806MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 807module_param_named(debug, debug.msg_enable, int, 0);
808MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 809MODULE_LICENSE("GPL");
810MODULE_VERSION(RTL8169_VERSION);
bca03d5f 811MODULE_FIRMWARE(FIRMWARE_8168D_1);
812MODULE_FIRMWARE(FIRMWARE_8168D_2);
01dc7fec 813MODULE_FIRMWARE(FIRMWARE_8168E_1);
814MODULE_FIRMWARE(FIRMWARE_8168E_2);
bbb8af75 815MODULE_FIRMWARE(FIRMWARE_8168E_3);
5a5e4443 816MODULE_FIRMWARE(FIRMWARE_8105E_1);
c2218925
HW		 817MODULE_FIRMWARE(FIRMWARE_8168F_1);
818MODULE_FIRMWARE(FIRMWARE_8168F_2);
7e18dca1 819MODULE_FIRMWARE(FIRMWARE_8402_1);
b3d7b2f2 820MODULE_FIRMWARE(FIRMWARE_8411_1);
5598bfe5 821MODULE_FIRMWARE(FIRMWARE_8106E_1);
c558386b 822MODULE_FIRMWARE(FIRMWARE_8168G_1);
1da177e4 823
da78dbff
FR		 824static void rtl_lock_work(struct rtl8169_private *tp)
825{
826 mutex_lock(&tp->wk.mutex);
827}
828
829static void rtl_unlock_work(struct rtl8169_private *tp)
830{
831 mutex_unlock(&tp->wk.mutex);
832}
833
d58d46b5
FR		 834static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
835{
7d7903b2
JL		 836 pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
837 PCI_EXP_DEVCTL_READRQ, force);
d58d46b5
FR		 838}
839
ffc46952
FR		 840struct rtl_cond {
841 bool (*check)(struct rtl8169_private *);
842 const char *msg;
843};
844
845static void rtl_udelay(unsigned int d)
846{
847 udelay(d);
848}
849
850static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
851 void (*delay)(unsigned int), unsigned int d, int n,
852 bool high)
853{
854 int i;
855
856 for (i = 0; i < n; i++) {
857 delay(d);
858 if (c->check(tp) == high)
859 return true;
860 }
82e316ef
FR		 861 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
862 c->msg, !high, n, d);
ffc46952
FR		 863 return false;
864}
865
866static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
867 const struct rtl_cond *c,
868 unsigned int d, int n)
869{
870 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
871}
872
873static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
874 const struct rtl_cond *c,
875 unsigned int d, int n)
876{
877 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
878}
879
880static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
881 const struct rtl_cond *c,
882 unsigned int d, int n)
883{
884 return rtl_loop_wait(tp, c, msleep, d, n, true);
885}
886
887static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
888 const struct rtl_cond *c,
889 unsigned int d, int n)
890{
891 return rtl_loop_wait(tp, c, msleep, d, n, false);
892}
893
894#define DECLARE_RTL_COND(name) \
895static bool name ## _check(struct rtl8169_private *); \
896 \
897static const struct rtl_cond name = { \
898 .check = name ## _check, \
899 .msg = #name \
900}; \
901 \
902static bool name ## _check(struct rtl8169_private *tp)
903
904DECLARE_RTL_COND(rtl_ocpar_cond)
905{
906 void __iomem *ioaddr = tp->mmio_addr;
907
908 return RTL_R32(OCPAR) & OCPAR_FLAG;
909}
910
b646d900 911static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
912{
913 void __iomem *ioaddr = tp->mmio_addr;
b646d900 914
915 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
ffc46952
FR		 916
917 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
918 RTL_R32(OCPDR) : ~0;
b646d900 919}
920
921static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
922{
923 void __iomem *ioaddr = tp->mmio_addr;
b646d900 924
925 RTL_W32(OCPDR, data);
926 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
ffc46952
FR		 927
928 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
929}
930
931DECLARE_RTL_COND(rtl_eriar_cond)
932{
933 void __iomem *ioaddr = tp->mmio_addr;
934
935 return RTL_R32(ERIAR) & ERIAR_FLAG;
b646d900 936}
937
fac5b3ca 938static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
b646d900 939{
fac5b3ca 940 void __iomem *ioaddr = tp->mmio_addr;
b646d900 941
942 RTL_W8(ERIDR, cmd);
943 RTL_W32(ERIAR, 0x800010e8);
944 msleep(2);
ffc46952
FR		 945
946 if (!rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 5))
947 return;
b646d900 948
fac5b3ca 949 ocp_write(tp, 0x1, 0x30, 0x00000001);
b646d900 950}
951
952#define OOB_CMD_RESET 0x00
953#define OOB_CMD_DRIVER_START 0x05
954#define OOB_CMD_DRIVER_STOP 0x06
955
cecb5fd7
FR		 956static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
957{
958 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
959}
960
ffc46952 961DECLARE_RTL_COND(rtl_ocp_read_cond)
b646d900 962{
cecb5fd7 963 u16 reg;
b646d900 964
cecb5fd7 965 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 966
ffc46952 967 return ocp_read(tp, 0x0f, reg) & 0x00000800;
b646d900 968}
969
ffc46952 970static void rtl8168_driver_start(struct rtl8169_private *tp)
b646d900 971{
ffc46952 972 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
b646d900 973
ffc46952
FR		 974 rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
975}
b646d900 976
ffc46952
FR		 977static void rtl8168_driver_stop(struct rtl8169_private *tp)
978{
979 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
4804b3b3 980
ffc46952 981 rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
b646d900 982}
983
4804b3b3 984static int r8168dp_check_dash(struct rtl8169_private *tp)
985{
cecb5fd7 986 u16 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 987
cecb5fd7 988 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
4804b3b3 989}
b646d900 990
c558386b
HW		 991static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
992{
993 if (reg & 0xffff0001) {
994 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
995 return true;
996 }
997 return false;
998}
999
1000DECLARE_RTL_COND(rtl_ocp_gphy_cond)
1001{
1002 void __iomem *ioaddr = tp->mmio_addr;
1003
1004 return RTL_R32(GPHY_OCP) & OCPAR_FLAG;
1005}
1006
1007static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1008{
1009 void __iomem *ioaddr = tp->mmio_addr;
1010
1011 if (rtl_ocp_reg_failure(tp, reg))
1012 return;
1013
1014 RTL_W32(GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
1015
1016 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
1017}
1018
1019static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
1020{
1021 void __iomem *ioaddr = tp->mmio_addr;
1022
1023 if (rtl_ocp_reg_failure(tp, reg))
1024 return 0;
1025
1026 RTL_W32(GPHY_OCP, reg << 15);
1027
1028 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
1029 (RTL_R32(GPHY_OCP) & 0xffff) : ~0;
1030}
1031
1032static void rtl_w1w0_phy_ocp(struct rtl8169_private *tp, int reg, int p, int m)
1033{
1034 int val;
1035
1036 val = r8168_phy_ocp_read(tp, reg);
1037 r8168_phy_ocp_write(tp, reg, (val | p) & ~m);
1038}
1039
c558386b
HW		 1040static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1041{
1042 void __iomem *ioaddr = tp->mmio_addr;
1043
1044 if (rtl_ocp_reg_failure(tp, reg))
1045 return;
1046
1047 RTL_W32(OCPDR, OCPAR_FLAG | (reg << 15) | data);
c558386b
HW		 1048}
1049
1050static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1051{
1052 void __iomem *ioaddr = tp->mmio_addr;
1053
1054 if (rtl_ocp_reg_failure(tp, reg))
1055 return 0;
1056
1057 RTL_W32(OCPDR, reg << 15);
1058
3a83ad12 1059 return RTL_R32(OCPDR);
c558386b
HW		 1060}
1061
1062#define OCP_STD_PHY_BASE 0xa400
1063
1064static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
1065{
1066 if (reg == 0x1f) {
1067 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
1068 return;
1069 }
1070
1071 if (tp->ocp_base != OCP_STD_PHY_BASE)
1072 reg -= 0x10;
1073
1074 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
1075}
1076
1077static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1078{
1079 if (tp->ocp_base != OCP_STD_PHY_BASE)
1080 reg -= 0x10;
1081
1082 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
1083}
1084
ffc46952
FR		 1085DECLARE_RTL_COND(rtl_phyar_cond)
1086{
1087 void __iomem *ioaddr = tp->mmio_addr;
1088
1089 return RTL_R32(PHYAR) & 0x80000000;
1090}
1091
24192210 1092static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1da177e4 1093{
24192210 1094 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 1095
24192210 1096 RTL_W32(PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1da177e4 1097
ffc46952 1098 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
024a07ba 1099 /*
81a95f04
TT		 1100 * According to hardware specs a 20us delay is required after write
1101 * complete indication, but before sending next command.
024a07ba 1102 */
81a95f04 1103 udelay(20);
1da177e4
LT		 1104}
1105
24192210 1106static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1da177e4 1107{
24192210 1108 void __iomem *ioaddr = tp->mmio_addr;
ffc46952 1109 int value;
1da177e4 1110
24192210 1111 RTL_W32(PHYAR, 0x0 | (reg & 0x1f) << 16);
1da177e4 1112
ffc46952
FR		 1113 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1114 RTL_R32(PHYAR) & 0xffff : ~0;
1115
81a95f04
TT		 1116 /*
1117 * According to hardware specs a 20us delay is required after read
1118 * complete indication, but before sending next command.
1119 */
1120 udelay(20);
1121
1da177e4
LT		 1122 return value;
1123}
1124
24192210 1125static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
c0e45c1c 1126{
24192210 1127 void __iomem *ioaddr = tp->mmio_addr;
c0e45c1c 1128
24192210 1129 RTL_W32(OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
c0e45c1c 1130 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
1131 RTL_W32(EPHY_RXER_NUM, 0);
1132
ffc46952 1133 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
c0e45c1c 1134}
1135
24192210 1136static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
c0e45c1c 1137{
24192210
FR		 1138 r8168dp_1_mdio_access(tp, reg,
1139 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
c0e45c1c 1140}
1141
24192210 1142static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
c0e45c1c 1143{
24192210 1144 void __iomem *ioaddr = tp->mmio_addr;
c0e45c1c 1145
24192210 1146 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
c0e45c1c 1147
1148 mdelay(1);
1149 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
1150 RTL_W32(EPHY_RXER_NUM, 0);
1151
ffc46952
FR		 1152 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1153 RTL_R32(OCPDR) & OCPDR_DATA_MASK : ~0;
c0e45c1c 1154}
1155
e6de30d6 1156#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1157
1158static void r8168dp_2_mdio_start(void __iomem *ioaddr)
1159{
1160 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1161}
1162
1163static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
1164{
1165 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1166}
1167
24192210 1168static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
e6de30d6 1169{
24192210
FR		 1170 void __iomem *ioaddr = tp->mmio_addr;
1171
e6de30d6 1172 r8168dp_2_mdio_start(ioaddr);
1173
24192210 1174 r8169_mdio_write(tp, reg, value);
e6de30d6 1175
1176 r8168dp_2_mdio_stop(ioaddr);
1177}
1178
24192210 1179static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
e6de30d6 1180{
24192210 1181 void __iomem *ioaddr = tp->mmio_addr;
e6de30d6 1182 int value;
1183
1184 r8168dp_2_mdio_start(ioaddr);
1185
24192210 1186 value = r8169_mdio_read(tp, reg);
e6de30d6 1187
1188 r8168dp_2_mdio_stop(ioaddr);
1189
1190 return value;
1191}
1192
4da19633 1193static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
dacf8154 1194{
24192210 1195 tp->mdio_ops.write(tp, location, val);
dacf8154
FR		 1196}
1197
4da19633 1198static int rtl_readphy(struct rtl8169_private *tp, int location)
1199{
24192210 1200 return tp->mdio_ops.read(tp, location);
4da19633 1201}
1202
1203static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1204{
1205 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1206}
1207
1208static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
daf9df6d 1209{
1210 int val;
1211
4da19633 1212 val = rtl_readphy(tp, reg_addr);
1213 rtl_writephy(tp, reg_addr, (val | p) & ~m);
daf9df6d 1214}
1215
ccdffb9a
FR		 1216static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1217 int val)
1218{
1219 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1220
4da19633 1221 rtl_writephy(tp, location, val);
ccdffb9a
FR		 1222}
1223
1224static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1225{
1226 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1227
4da19633 1228 return rtl_readphy(tp, location);
ccdffb9a
FR		 1229}
1230
ffc46952
FR		 1231DECLARE_RTL_COND(rtl_ephyar_cond)
1232{
1233 void __iomem *ioaddr = tp->mmio_addr;
1234
1235 return RTL_R32(EPHYAR) & EPHYAR_FLAG;
1236}
1237
fdf6fc06 1238static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
dacf8154 1239{
fdf6fc06 1240 void __iomem *ioaddr = tp->mmio_addr;
dacf8154
FR		 1241
1242 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1243 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1244
ffc46952
FR		 1245 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1246
1247 udelay(10);
dacf8154
FR		 1248}
1249
fdf6fc06 1250static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
dacf8154 1251{
fdf6fc06 1252 void __iomem *ioaddr = tp->mmio_addr;
dacf8154
FR		 1253
1254 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1255
ffc46952
FR		 1256 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1257 RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0;
dacf8154
FR		 1258}
1259
fdf6fc06
FR		 1260static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1261 u32 val, int type)
133ac40a 1262{
fdf6fc06 1263 void __iomem *ioaddr = tp->mmio_addr;
133ac40a
HW		 1264
1265 BUG_ON((addr & 3) || (mask == 0));
1266 RTL_W32(ERIDR, val);
1267 RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1268
ffc46952 1269 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
133ac40a
HW		 1270}
1271
fdf6fc06 1272static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
133ac40a 1273{
fdf6fc06 1274 void __iomem *ioaddr = tp->mmio_addr;
133ac40a
HW		 1275
1276 RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1277
ffc46952
FR		 1278 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1279 RTL_R32(ERIDR) : ~0;
133ac40a
HW		 1280}
1281
fdf6fc06
FR		 1282static void rtl_w1w0_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1283 u32 m, int type)
133ac40a
HW		 1284{
1285 u32 val;
1286
fdf6fc06
FR		 1287 val = rtl_eri_read(tp, addr, type);
1288 rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
133ac40a
HW		 1289}
1290
c28aa385 1291struct exgmac_reg {
1292 u16 addr;
1293 u16 mask;
1294 u32 val;
1295};
1296
fdf6fc06 1297static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
c28aa385 1298 const struct exgmac_reg *r, int len)
1299{
1300 while (len-- > 0) {
fdf6fc06 1301 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
c28aa385 1302 r++;
1303 }
1304}
1305
ffc46952
FR		 1306DECLARE_RTL_COND(rtl_efusear_cond)
1307{
1308 void __iomem *ioaddr = tp->mmio_addr;
1309
1310 return RTL_R32(EFUSEAR) & EFUSEAR_FLAG;
1311}
1312
fdf6fc06 1313static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
daf9df6d 1314{
fdf6fc06 1315 void __iomem *ioaddr = tp->mmio_addr;
daf9df6d 1316
1317 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1318
ffc46952
FR		 1319 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1320 RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
daf9df6d 1321}
1322
9085cdfa
FR		 1323static u16 rtl_get_events(struct rtl8169_private *tp)
1324{
1325 void __iomem *ioaddr = tp->mmio_addr;
1326
1327 return RTL_R16(IntrStatus);
1328}
1329
1330static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1331{
1332 void __iomem *ioaddr = tp->mmio_addr;
1333
1334 RTL_W16(IntrStatus, bits);
1335 mmiowb();
1336}
1337
1338static void rtl_irq_disable(struct rtl8169_private *tp)
1339{
1340 void __iomem *ioaddr = tp->mmio_addr;
1341
1342 RTL_W16(IntrMask, 0);
1343 mmiowb();
1344}
1345
3e990ff5
FR		 1346static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1347{
1348 void __iomem *ioaddr = tp->mmio_addr;
1349
1350 RTL_W16(IntrMask, bits);
1351}
1352
da78dbff
FR		 1353#define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1354#define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1355#define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1356
1357static void rtl_irq_enable_all(struct rtl8169_private *tp)
1358{
1359 rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1360}
1361
811fd301 1362static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1da177e4 1363{
811fd301 1364 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 1365
9085cdfa 1366 rtl_irq_disable(tp);
da78dbff 1367 rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
811fd301 1368 RTL_R8(ChipCmd);
1da177e4
LT		 1369}
1370
4da19633 1371static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1da177e4 1372{
4da19633 1373 void __iomem *ioaddr = tp->mmio_addr;
1374
1da177e4
LT		 1375 return RTL_R32(TBICSR) & TBIReset;
1376}
1377
4da19633 1378static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1da177e4 1379{
4da19633 1380 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 1381}
1382
1383static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1384{
1385 return RTL_R32(TBICSR) & TBILinkOk;
1386}
1387
1388static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1389{
1390 return RTL_R8(PHYstatus) & LinkStatus;
1391}
1392
4da19633 1393static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1da177e4 1394{
4da19633 1395 void __iomem *ioaddr = tp->mmio_addr;
1396
1da177e4
LT		 1397 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1398}
1399
4da19633 1400static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1da177e4
LT		 1401{
1402 unsigned int val;
1403
4da19633 1404 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1405 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1da177e4
LT		 1406}
1407
70090424
HW		 1408static void rtl_link_chg_patch(struct rtl8169_private *tp)
1409{
1410 void __iomem *ioaddr = tp->mmio_addr;
1411 struct net_device *dev = tp->dev;
1412
1413 if (!netif_running(dev))
1414 return;
1415
b3d7b2f2
HW		 1416 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1417 tp->mac_version == RTL_GIGA_MAC_VER_38) {
70090424 1418 if (RTL_R8(PHYstatus) & _1000bpsF) {
fdf6fc06
FR		 1419 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1420 ERIAR_EXGMAC);
1421 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1422 ERIAR_EXGMAC);
70090424 1423 } else if (RTL_R8(PHYstatus) & _100bps) {
fdf6fc06
FR		 1424 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1425 ERIAR_EXGMAC);
1426 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1427 ERIAR_EXGMAC);
70090424 1428 } else {
fdf6fc06
FR		 1429 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1430 ERIAR_EXGMAC);
1431 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1432 ERIAR_EXGMAC);
70090424
HW		 1433 }
1434 /* Reset packet filter */
fdf6fc06 1435 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
70090424 1436 ERIAR_EXGMAC);
fdf6fc06 1437 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
70090424 1438 ERIAR_EXGMAC);
c2218925
HW		 1439 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1440 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1441 if (RTL_R8(PHYstatus) & _1000bpsF) {
fdf6fc06
FR		 1442 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1443 ERIAR_EXGMAC);
1444 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1445 ERIAR_EXGMAC);
c2218925 1446 } else {
fdf6fc06
FR		 1447 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1448 ERIAR_EXGMAC);
1449 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1450 ERIAR_EXGMAC);
c2218925 1451 }
7e18dca1
HW		 1452 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1453 if (RTL_R8(PHYstatus) & _10bps) {
fdf6fc06
FR		 1454 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1455 ERIAR_EXGMAC);
1456 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1457 ERIAR_EXGMAC);
7e18dca1 1458 } else {
fdf6fc06
FR		 1459 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1460 ERIAR_EXGMAC);
7e18dca1 1461 }
70090424
HW		 1462 }
1463}
1464
e4fbce74 1465static void __rtl8169_check_link_status(struct net_device *dev,
cecb5fd7
FR		 1466 struct rtl8169_private *tp,
1467 void __iomem *ioaddr, bool pm)
1da177e4 1468{
1da177e4 1469 if (tp->link_ok(ioaddr)) {
70090424 1470 rtl_link_chg_patch(tp);
e1759441 1471 /* This is to cancel a scheduled suspend if there's one. */
e4fbce74
RW		 1472 if (pm)
1473 pm_request_resume(&tp->pci_dev->dev);
1da177e4 1474 netif_carrier_on(dev);
1519e57f
FR		 1475 if (net_ratelimit())
1476 netif_info(tp, ifup, dev, "link up\n");
b57b7e5a 1477 } else {
1da177e4 1478 netif_carrier_off(dev);
bf82c189 1479 netif_info(tp, ifdown, dev, "link down\n");
e4fbce74 1480 if (pm)
10953db8 1481 pm_schedule_suspend(&tp->pci_dev->dev, 5000);
b57b7e5a 1482 }
1da177e4
LT		 1483}
1484
e4fbce74
RW		 1485static void rtl8169_check_link_status(struct net_device *dev,
1486 struct rtl8169_private *tp,
1487 void __iomem *ioaddr)
1488{
1489 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1490}
1491
e1759441
RW		 1492#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1493
1494static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
61a4dcc2 1495{
61a4dcc2
FR		 1496 void __iomem *ioaddr = tp->mmio_addr;
1497 u8 options;
e1759441 1498 u32 wolopts = 0;
61a4dcc2
FR		 1499
1500 options = RTL_R8(Config1);
1501 if (!(options & PMEnable))
e1759441 1502 return 0;
61a4dcc2
FR		 1503
1504 options = RTL_R8(Config3);
1505 if (options & LinkUp)
e1759441 1506 wolopts |= WAKE_PHY;
61a4dcc2 1507 if (options & MagicPacket)
e1759441 1508 wolopts |= WAKE_MAGIC;
61a4dcc2
FR		 1509
1510 options = RTL_R8(Config5);
1511 if (options & UWF)
e1759441 1512 wolopts |= WAKE_UCAST;
61a4dcc2 1513 if (options & BWF)
e1759441 1514 wolopts |= WAKE_BCAST;
61a4dcc2 1515 if (options & MWF)
e1759441 1516 wolopts |= WAKE_MCAST;
61a4dcc2 1517
e1759441 1518 return wolopts;
61a4dcc2
FR		 1519}
1520
e1759441 1521static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
61a4dcc2
FR		 1522{
1523 struct rtl8169_private *tp = netdev_priv(dev);
e1759441 1524
da78dbff 1525 rtl_lock_work(tp);
e1759441
RW		 1526
1527 wol->supported = WAKE_ANY;
1528 wol->wolopts = __rtl8169_get_wol(tp);
1529
da78dbff 1530 rtl_unlock_work(tp);
e1759441
RW		 1531}
1532
1533static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1534{
61a4dcc2 1535 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1536 unsigned int i;
350f7596 1537 static const struct {
61a4dcc2
FR		 1538 u32 opt;
1539 u16 reg;
1540 u8 mask;
1541 } cfg[] = {
61a4dcc2
FR		 1542 { WAKE_PHY, Config3, LinkUp },
1543 { WAKE_MAGIC, Config3, MagicPacket },
1544 { WAKE_UCAST, Config5, UWF },
1545 { WAKE_BCAST, Config5, BWF },
1546 { WAKE_MCAST, Config5, MWF },
1547 { WAKE_ANY, Config5, LanWake }
1548 };
851e6022 1549 u8 options;
61a4dcc2 1550
61a4dcc2
FR		 1551 RTL_W8(Cfg9346, Cfg9346_Unlock);
1552
1553 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
851e6022 1554 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
e1759441 1555 if (wolopts & cfg[i].opt)
61a4dcc2
FR		 1556 options |= cfg[i].mask;
1557 RTL_W8(cfg[i].reg, options);
1558 }
1559
851e6022
FR		 1560 switch (tp->mac_version) {
1561 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1562 options = RTL_R8(Config1) & ~PMEnable;
1563 if (wolopts)
1564 options |= PMEnable;
1565 RTL_W8(Config1, options);
1566 break;
1567 default:
d387b427
FR		 1568 options = RTL_R8(Config2) & ~PME_SIGNAL;
1569 if (wolopts)
1570 options |= PME_SIGNAL;
1571 RTL_W8(Config2, options);
851e6022
FR		 1572 break;
1573 }
1574
61a4dcc2 1575 RTL_W8(Cfg9346, Cfg9346_Lock);
e1759441
RW		 1576}
1577
1578static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1579{
1580 struct rtl8169_private *tp = netdev_priv(dev);
1581
da78dbff 1582 rtl_lock_work(tp);
61a4dcc2 1583
f23e7fda
FR		 1584 if (wol->wolopts)
1585 tp->features |= RTL_FEATURE_WOL;
1586 else
1587 tp->features &= ~RTL_FEATURE_WOL;
e1759441 1588 __rtl8169_set_wol(tp, wol->wolopts);
da78dbff
FR		 1589
1590 rtl_unlock_work(tp);
61a4dcc2 1591
ea80907f 1592 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1593
61a4dcc2
FR		 1594 return 0;
1595}
1596
31bd204f
FR		 1597static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1598{
85bffe6c 1599 return rtl_chip_infos[tp->mac_version].fw_name;
31bd204f
FR		 1600}
1601
1da177e4
LT		 1602static void rtl8169_get_drvinfo(struct net_device *dev,
1603 struct ethtool_drvinfo *info)
1604{
1605 struct rtl8169_private *tp = netdev_priv(dev);
b6ffd97f 1606 struct rtl_fw *rtl_fw = tp->rtl_fw;
1da177e4 1607
68aad78c
RJ		 1608 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1609 strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1610 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1c361efb 1611 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
8ac72d16
RJ		 1612 if (!IS_ERR_OR_NULL(rtl_fw))
1613 strlcpy(info->fw_version, rtl_fw->version,
1614 sizeof(info->fw_version));
1da177e4
LT		 1615}
1616
1617static int rtl8169_get_regs_len(struct net_device *dev)
1618{
1619 return R8169_REGS_SIZE;
1620}
1621
1622static int rtl8169_set_speed_tbi(struct net_device *dev,
54405cde 1623 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1da177e4
LT		 1624{
1625 struct rtl8169_private *tp = netdev_priv(dev);
1626 void __iomem *ioaddr = tp->mmio_addr;
1627 int ret = 0;
1628 u32 reg;
1629
1630 reg = RTL_R32(TBICSR);
1631 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1632 (duplex == DUPLEX_FULL)) {
1633 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1634 } else if (autoneg == AUTONEG_ENABLE)
1635 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1636 else {
bf82c189
JP		 1637 netif_warn(tp, link, dev,
1638 "incorrect speed setting refused in TBI mode\n");
1da177e4
LT		 1639 ret = -EOPNOTSUPP;
1640 }
1641
1642 return ret;
1643}
1644
1645static int rtl8169_set_speed_xmii(struct net_device *dev,
54405cde 1646 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1da177e4
LT		 1647{
1648 struct rtl8169_private *tp = netdev_priv(dev);
3577aa1b 1649 int giga_ctrl, bmcr;
54405cde 1650 int rc = -EINVAL;
1da177e4 1651
716b50a3 1652 rtl_writephy(tp, 0x1f, 0x0000);
1da177e4
LT		 1653
1654 if (autoneg == AUTONEG_ENABLE) {
3577aa1b 1655 int auto_nego;
1656
4da19633 1657 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
54405cde
ON		 1658 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1659 ADVERTISE_100HALF | ADVERTISE_100FULL);
1660
1661 if (adv & ADVERTISED_10baseT_Half)
1662 auto_nego |= ADVERTISE_10HALF;
1663 if (adv & ADVERTISED_10baseT_Full)
1664 auto_nego |= ADVERTISE_10FULL;
1665 if (adv & ADVERTISED_100baseT_Half)
1666 auto_nego |= ADVERTISE_100HALF;
1667 if (adv & ADVERTISED_100baseT_Full)
1668 auto_nego |= ADVERTISE_100FULL;
1669
3577aa1b 1670 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1da177e4 1671
4da19633 1672 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
3577aa1b 1673 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
bcf0bf90 1674
3577aa1b 1675 /* The 8100e/8101e/8102e do Fast Ethernet only. */
826e6cbd 1676 if (tp->mii.supports_gmii) {
54405cde
ON		 1677 if (adv & ADVERTISED_1000baseT_Half)
1678 giga_ctrl |= ADVERTISE_1000HALF;
1679 if (adv & ADVERTISED_1000baseT_Full)
1680 giga_ctrl |= ADVERTISE_1000FULL;
1681 } else if (adv & (ADVERTISED_1000baseT_Half |
1682 ADVERTISED_1000baseT_Full)) {
bf82c189
JP		 1683 netif_info(tp, link, dev,
1684 "PHY does not support 1000Mbps\n");
54405cde 1685 goto out;
bcf0bf90 1686 }
1da177e4 1687
3577aa1b 1688 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1689
4da19633 1690 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1691 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
3577aa1b 1692 } else {
1693 giga_ctrl = 0;
1694
1695 if (speed == SPEED_10)
1696 bmcr = 0;
1697 else if (speed == SPEED_100)
1698 bmcr = BMCR_SPEED100;
1699 else
54405cde 1700 goto out;
3577aa1b 1701
1702 if (duplex == DUPLEX_FULL)
1703 bmcr |= BMCR_FULLDPLX;
2584fbc3
RS		 1704 }
1705
4da19633 1706 rtl_writephy(tp, MII_BMCR, bmcr);
3577aa1b 1707
cecb5fd7
FR		 1708 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1709 tp->mac_version == RTL_GIGA_MAC_VER_03) {
3577aa1b 1710 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
4da19633 1711 rtl_writephy(tp, 0x17, 0x2138);
1712 rtl_writephy(tp, 0x0e, 0x0260);
3577aa1b 1713 } else {
4da19633 1714 rtl_writephy(tp, 0x17, 0x2108);
1715 rtl_writephy(tp, 0x0e, 0x0000);
3577aa1b 1716 }
1717 }
1718
54405cde
ON		 1719 rc = 0;
1720out:
1721 return rc;
1da177e4
LT		 1722}
1723
1724static int rtl8169_set_speed(struct net_device *dev,
54405cde 1725 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1da177e4
LT		 1726{
1727 struct rtl8169_private *tp = netdev_priv(dev);
1728 int ret;
1729
54405cde 1730 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
4876cc1e
FR		 1731 if (ret < 0)
1732 goto out;
1da177e4 1733
4876cc1e
FR		 1734 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1735 (advertising & ADVERTISED_1000baseT_Full)) {
1da177e4 1736 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
4876cc1e
FR		 1737 }
1738out:
1da177e4
LT		 1739 return ret;
1740}
1741
1742static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1743{
1744 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4
LT		 1745 int ret;
1746
4876cc1e
FR		 1747 del_timer_sync(&tp->timer);
1748
da78dbff 1749 rtl_lock_work(tp);
cecb5fd7 1750 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
25db0338 1751 cmd->duplex, cmd->advertising);
da78dbff 1752 rtl_unlock_work(tp);
5b0384f4 1753
1da177e4
LT		 1754 return ret;
1755}
1756
c8f44aff
MM		 1757static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1758 netdev_features_t features)
1da177e4 1759{
d58d46b5
FR		 1760 struct rtl8169_private *tp = netdev_priv(dev);
1761
2b7b4318 1762 if (dev->mtu > TD_MSS_MAX)
350fb32a 1763 features &= ~NETIF_F_ALL_TSO;
1da177e4 1764
d58d46b5
FR		 1765 if (dev->mtu > JUMBO_1K &&
1766 !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1767 features &= ~NETIF_F_IP_CSUM;
1768
350fb32a 1769 return features;
1da177e4
LT		 1770}
1771
da78dbff
FR		 1772static void __rtl8169_set_features(struct net_device *dev,
1773 netdev_features_t features)
1da177e4
LT		 1774{
1775 struct rtl8169_private *tp = netdev_priv(dev);
6bbe021d 1776 netdev_features_t changed = features ^ dev->features;
da78dbff 1777 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 1778
6bbe021d
BG		 1779 if (!(changed & (NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)))
1780 return;
1da177e4 1781
6bbe021d
BG		 1782 if (changed & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)) {
1783 if (features & NETIF_F_RXCSUM)
1784 tp->cp_cmd |= RxChkSum;
1785 else
1786 tp->cp_cmd &= ~RxChkSum;
350fb32a 1787
6bbe021d
BG		 1788 if (dev->features & NETIF_F_HW_VLAN_RX)
1789 tp->cp_cmd |= RxVlan;
1790 else
1791 tp->cp_cmd &= ~RxVlan;
1792
1793 RTL_W16(CPlusCmd, tp->cp_cmd);
1794 RTL_R16(CPlusCmd);
1795 }
1796 if (changed & NETIF_F_RXALL) {
1797 int tmp = (RTL_R32(RxConfig) & ~(AcceptErr | AcceptRunt));
1798 if (features & NETIF_F_RXALL)
1799 tmp |= (AcceptErr | AcceptRunt);
1800 RTL_W32(RxConfig, tmp);
1801 }
da78dbff 1802}
1da177e4 1803
da78dbff
FR		 1804static int rtl8169_set_features(struct net_device *dev,
1805 netdev_features_t features)
1806{
1807 struct rtl8169_private *tp = netdev_priv(dev);
1808
1809 rtl_lock_work(tp);
1810 __rtl8169_set_features(dev, features);
1811 rtl_unlock_work(tp);
1da177e4
LT		 1812
1813 return 0;
1814}
1815
da78dbff 1816
810f4893 1817static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1da177e4 1818{
eab6d18d 1819 return (vlan_tx_tag_present(skb)) ?
1da177e4
LT		 1820 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1821}
1822
7a8fc77b 1823static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1da177e4
LT		 1824{
1825 u32 opts2 = le32_to_cpu(desc->opts2);
1da177e4 1826
7a8fc77b
FR		 1827 if (opts2 & RxVlanTag)
1828 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
2edae08e 1829
1da177e4 1830 desc->opts2 = 0;
1da177e4
LT		 1831}
1832
ccdffb9a 1833static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1834{
1835 struct rtl8169_private *tp = netdev_priv(dev);
1836 void __iomem *ioaddr = tp->mmio_addr;
1837 u32 status;
1838
1839 cmd->supported =
1840 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1841 cmd->port = PORT_FIBRE;
1842 cmd->transceiver = XCVR_INTERNAL;
1843
1844 status = RTL_R32(TBICSR);
1845 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1846 cmd->autoneg = !!(status & TBINwEnable);
1847
70739497 1848 ethtool_cmd_speed_set(cmd, SPEED_1000);
1da177e4 1849 cmd->duplex = DUPLEX_FULL; /* Always set */
ccdffb9a
FR		 1850
1851 return 0;
1da177e4
LT		 1852}
1853
ccdffb9a 1854static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1855{
1856 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a
FR		 1857
1858 return mii_ethtool_gset(&tp->mii, cmd);
1da177e4
LT		 1859}
1860
1861static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1862{
1863 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1864 int rc;
1da177e4 1865
da78dbff 1866 rtl_lock_work(tp);
ccdffb9a 1867 rc = tp->get_settings(dev, cmd);
da78dbff 1868 rtl_unlock_work(tp);
1da177e4 1869
ccdffb9a 1870 return rc;
1da177e4
LT		 1871}
1872
1873static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1874 void *p)
1875{
5b0384f4 1876 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 1877
5b0384f4
FR		 1878 if (regs->len > R8169_REGS_SIZE)
1879 regs->len = R8169_REGS_SIZE;
1da177e4 1880
da78dbff 1881 rtl_lock_work(tp);
5b0384f4 1882 memcpy_fromio(p, tp->mmio_addr, regs->len);
da78dbff 1883 rtl_unlock_work(tp);
1da177e4
LT		 1884}
1885
b57b7e5a
SH		 1886static u32 rtl8169_get_msglevel(struct net_device *dev)
1887{
1888 struct rtl8169_private *tp = netdev_priv(dev);
1889
1890 return tp->msg_enable;
1891}
1892
1893static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1894{
1895 struct rtl8169_private *tp = netdev_priv(dev);
1896
1897 tp->msg_enable = value;
1898}
1899
d4a3a0fc
SH		 1900static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1901 "tx_packets",
1902 "rx_packets",
1903 "tx_errors",
1904 "rx_errors",
1905 "rx_missed",
1906 "align_errors",
1907 "tx_single_collisions",
1908 "tx_multi_collisions",
1909 "unicast",
1910 "broadcast",
1911 "multicast",
1912 "tx_aborted",
1913 "tx_underrun",
1914};
1915
b9f2c044 1916static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1917{
b9f2c044
JG		 1918 switch (sset) {
1919 case ETH_SS_STATS:
1920 return ARRAY_SIZE(rtl8169_gstrings);
1921 default:
1922 return -EOPNOTSUPP;
1923 }
d4a3a0fc
SH		 1924}
1925
ffc46952
FR		 1926DECLARE_RTL_COND(rtl_counters_cond)
1927{
1928 void __iomem *ioaddr = tp->mmio_addr;
1929
1930 return RTL_R32(CounterAddrLow) & CounterDump;
1931}
1932
355423d0 1933static void rtl8169_update_counters(struct net_device *dev)
d4a3a0fc
SH		 1934{
1935 struct rtl8169_private *tp = netdev_priv(dev);
1936 void __iomem *ioaddr = tp->mmio_addr;
cecb5fd7 1937 struct device *d = &tp->pci_dev->dev;
d4a3a0fc
SH		 1938 struct rtl8169_counters *counters;
1939 dma_addr_t paddr;
1940 u32 cmd;
1941
355423d0
IV		 1942 /*
1943 * Some chips are unable to dump tally counters when the receiver
1944 * is disabled.
1945 */
1946 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1947 return;
d4a3a0fc 1948
48addcc9 1949 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
d4a3a0fc
SH		 1950 if (!counters)
1951 return;
1952
1953 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
284901a9 1954 cmd = (u64)paddr & DMA_BIT_MASK(32);
d4a3a0fc
SH		 1955 RTL_W32(CounterAddrLow, cmd);
1956 RTL_W32(CounterAddrLow, cmd | CounterDump);
1957
ffc46952
FR		 1958 if (rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000))
1959 memcpy(&tp->counters, counters, sizeof(*counters));
d4a3a0fc
SH		 1960
1961 RTL_W32(CounterAddrLow, 0);
1962 RTL_W32(CounterAddrHigh, 0);
1963
48addcc9 1964 dma_free_coherent(d, sizeof(*counters), counters, paddr);
d4a3a0fc
SH		 1965}
1966
355423d0
IV		 1967static void rtl8169_get_ethtool_stats(struct net_device *dev,
1968 struct ethtool_stats *stats, u64 *data)
1969{
1970 struct rtl8169_private *tp = netdev_priv(dev);
1971
1972 ASSERT_RTNL();
1973
1974 rtl8169_update_counters(dev);
1975
1976 data[0] = le64_to_cpu(tp->counters.tx_packets);
1977 data[1] = le64_to_cpu(tp->counters.rx_packets);
1978 data[2] = le64_to_cpu(tp->counters.tx_errors);
1979 data[3] = le32_to_cpu(tp->counters.rx_errors);
1980 data[4] = le16_to_cpu(tp->counters.rx_missed);
1981 data[5] = le16_to_cpu(tp->counters.align_errors);
1982 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1983 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1984 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1985 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1986 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1987 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1988 data[12] = le16_to_cpu(tp->counters.tx_underun);
1989}
1990
d4a3a0fc
SH		 1991static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1992{
1993 switch(stringset) {
1994 case ETH_SS_STATS:
1995 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1996 break;
1997 }
1998}
1999
7282d491 2000static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 2001 .get_drvinfo = rtl8169_get_drvinfo,
2002 .get_regs_len = rtl8169_get_regs_len,
2003 .get_link = ethtool_op_get_link,
2004 .get_settings = rtl8169_get_settings,
2005 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 2006 .get_msglevel = rtl8169_get_msglevel,
2007 .set_msglevel = rtl8169_set_msglevel,
1da177e4 2008 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 2009 .get_wol = rtl8169_get_wol,
2010 .set_wol = rtl8169_set_wol,
d4a3a0fc 2011 .get_strings = rtl8169_get_strings,
b9f2c044 2012 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 2013 .get_ethtool_stats = rtl8169_get_ethtool_stats,
e1593bb1 2014 .get_ts_info = ethtool_op_get_ts_info,
1da177e4
LT		 2015};
2016
07d3f51f 2017static void rtl8169_get_mac_version(struct rtl8169_private *tp,
5d320a20 2018 struct net_device *dev, u8 default_version)
1da177e4 2019{
5d320a20 2020 void __iomem *ioaddr = tp->mmio_addr;
0e485150
FR		 2021 /*
2022 * The driver currently handles the 8168Bf and the 8168Be identically
2023 * but they can be identified more specifically through the test below
2024 * if needed:
2025 *
2026 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 2027 *
2028 * Same thing for the 8101Eb and the 8101Ec:
2029 *
2030 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 2031 */
3744100e 2032 static const struct rtl_mac_info {
1da177e4 2033 u32 mask;
e3cf0cc0 2034 u32 val;
1da177e4
LT		 2035 int mac_version;
2036 } mac_info[] = {
c558386b
HW		 2037 /* 8168G family. */
2038 { 0x7cf00000, 0x4c100000, RTL_GIGA_MAC_VER_41 },
2039 { 0x7cf00000, 0x4c000000, RTL_GIGA_MAC_VER_40 },
2040
c2218925 2041 /* 8168F family. */
b3d7b2f2 2042 { 0x7c800000, 0x48800000, RTL_GIGA_MAC_VER_38 },
c2218925
HW		 2043 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
2044 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
2045
01dc7fec 2046 /* 8168E family. */
70090424 2047 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
01dc7fec 2048 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
2049 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
2050 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
2051
5b538df9 2052 /* 8168D family. */
daf9df6d 2053 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
2054 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
daf9df6d 2055 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
5b538df9 2056
e6de30d6 2057 /* 8168DP family. */
2058 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
2059 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
4804b3b3 2060 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
e6de30d6 2061
ef808d50 2062 /* 8168C family. */
17c99297 2063 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
ef3386f0 2064 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 2065 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 2066 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 2067 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
2068 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 2069 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
6fb07058 2070 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
ef808d50 2071 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 2072
2073 /* 8168B family. */
2074 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
2075 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
2076 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
2077 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
2078
2079 /* 8101 family. */
5598bfe5
HW		 2080 { 0x7cf00000, 0x44900000, RTL_GIGA_MAC_VER_39 },
2081 { 0x7c800000, 0x44800000, RTL_GIGA_MAC_VER_39 },
7e18dca1 2082 { 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37 },
36a0e6c2 2083 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
5a5e4443
HW		 2084 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
2085 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
2086 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2857ffb7
FR		 2087 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
2088 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
2089 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
2090 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
2091 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
2092 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 2093 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 2094 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 2095 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 2096 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
2097 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 2098 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
2099 /* FIXME: where did these entries come from ? -- FR */
2100 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
2101 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
2102
2103 /* 8110 family. */
2104 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
2105 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
2106 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
2107 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
2108 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
2109 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
2110
f21b75e9
JD		 2111 /* Catch-all */
2112 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
3744100e
FR		 2113 };
2114 const struct rtl_mac_info *p = mac_info;
1da177e4
LT		 2115 u32 reg;
2116
e3cf0cc0
FR		 2117 reg = RTL_R32(TxConfig);
2118 while ((reg & p->mask) != p->val)
1da177e4
LT		 2119 p++;
2120 tp->mac_version = p->mac_version;
5d320a20
FR		 2121
2122 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2123 netif_notice(tp, probe, dev,
2124 "unknown MAC, using family default\n");
2125 tp->mac_version = default_version;
2126 }
1da177e4
LT		 2127}
2128
2129static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2130{
bcf0bf90 2131 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 2132}
2133
867763c1
FR		 2134struct phy_reg {
2135 u16 reg;
2136 u16 val;
2137};
2138
4da19633 2139static void rtl_writephy_batch(struct rtl8169_private *tp,
2140 const struct phy_reg *regs, int len)
867763c1
FR		 2141{
2142 while (len-- > 0) {
4da19633 2143 rtl_writephy(tp, regs->reg, regs->val);
867763c1
FR		 2144 regs++;
2145 }
2146}
2147
bca03d5f 2148#define PHY_READ 0x00000000
2149#define PHY_DATA_OR 0x10000000
2150#define PHY_DATA_AND 0x20000000
2151#define PHY_BJMPN 0x30000000
2152#define PHY_READ_EFUSE 0x40000000
2153#define PHY_READ_MAC_BYTE 0x50000000
2154#define PHY_WRITE_MAC_BYTE 0x60000000
2155#define PHY_CLEAR_READCOUNT 0x70000000
2156#define PHY_WRITE 0x80000000
2157#define PHY_READCOUNT_EQ_SKIP 0x90000000
2158#define PHY_COMP_EQ_SKIPN 0xa0000000
2159#define PHY_COMP_NEQ_SKIPN 0xb0000000
2160#define PHY_WRITE_PREVIOUS 0xc0000000
2161#define PHY_SKIPN 0xd0000000
2162#define PHY_DELAY_MS 0xe0000000
2163#define PHY_WRITE_ERI_WORD 0xf0000000
2164
960aee6c
HW		 2165struct fw_info {
2166 u32 magic;
2167 char version[RTL_VER_SIZE];
2168 __le32 fw_start;
2169 __le32 fw_len;
2170 u8 chksum;
2171} __packed;
2172
1c361efb
FR		 2173#define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2174
2175static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
bca03d5f 2176{
b6ffd97f 2177 const struct firmware *fw = rtl_fw->fw;
960aee6c 2178 struct fw_info *fw_info = (struct fw_info *)fw->data;
1c361efb
FR		 2179 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2180 char *version = rtl_fw->version;
2181 bool rc = false;
2182
2183 if (fw->size < FW_OPCODE_SIZE)
2184 goto out;
960aee6c
HW		 2185
2186 if (!fw_info->magic) {
2187 size_t i, size, start;
2188 u8 checksum = 0;
2189
2190 if (fw->size < sizeof(*fw_info))
2191 goto out;
2192
2193 for (i = 0; i < fw->size; i++)
2194 checksum += fw->data[i];
2195 if (checksum != 0)
2196 goto out;
2197
2198 start = le32_to_cpu(fw_info->fw_start);
2199 if (start > fw->size)
2200 goto out;
2201
2202 size = le32_to_cpu(fw_info->fw_len);
2203 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2204 goto out;
2205
2206 memcpy(version, fw_info->version, RTL_VER_SIZE);
2207
2208 pa->code = (__le32 *)(fw->data + start);
2209 pa->size = size;
2210 } else {
1c361efb
FR		 2211 if (fw->size % FW_OPCODE_SIZE)
2212 goto out;
2213
2214 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2215
2216 pa->code = (__le32 *)fw->data;
2217 pa->size = fw->size / FW_OPCODE_SIZE;
2218 }
2219 version[RTL_VER_SIZE - 1] = 0;
2220
2221 rc = true;
2222out:
2223 return rc;
2224}
2225
fd112f2e
FR		 2226static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2227 struct rtl_fw_phy_action *pa)
1c361efb 2228{
fd112f2e 2229 bool rc = false;
1c361efb 2230 size_t index;
bca03d5f 2231
1c361efb
FR		 2232 for (index = 0; index < pa->size; index++) {
2233 u32 action = le32_to_cpu(pa->code[index]);
42b82dc1 2234 u32 regno = (action & 0x0fff0000) >> 16;
bca03d5f 2235
42b82dc1 2236 switch(action & 0xf0000000) {
2237 case PHY_READ:
2238 case PHY_DATA_OR:
2239 case PHY_DATA_AND:
2240 case PHY_READ_EFUSE:
2241 case PHY_CLEAR_READCOUNT:
2242 case PHY_WRITE:
2243 case PHY_WRITE_PREVIOUS:
2244 case PHY_DELAY_MS:
2245 break;
2246
2247 case PHY_BJMPN:
2248 if (regno > index) {
fd112f2e 2249 netif_err(tp, ifup, tp->dev,
cecb5fd7 2250 "Out of range of firmware\n");
fd112f2e 2251 goto out;
42b82dc1 2252 }
2253 break;
2254 case PHY_READCOUNT_EQ_SKIP:
1c361efb 2255 if (index + 2 >= pa->size) {
fd112f2e 2256 netif_err(tp, ifup, tp->dev,
cecb5fd7 2257 "Out of range of firmware\n");
fd112f2e 2258 goto out;
42b82dc1 2259 }
2260 break;
2261 case PHY_COMP_EQ_SKIPN:
2262 case PHY_COMP_NEQ_SKIPN:
2263 case PHY_SKIPN:
1c361efb 2264 if (index + 1 + regno >= pa->size) {
fd112f2e 2265 netif_err(tp, ifup, tp->dev,
cecb5fd7 2266 "Out of range of firmware\n");
fd112f2e 2267 goto out;
42b82dc1 2268 }
bca03d5f 2269 break;
2270
42b82dc1 2271 case PHY_READ_MAC_BYTE:
2272 case PHY_WRITE_MAC_BYTE:
2273 case PHY_WRITE_ERI_WORD:
2274 default:
fd112f2e 2275 netif_err(tp, ifup, tp->dev,
42b82dc1 2276 "Invalid action 0x%08x\n", action);
fd112f2e 2277 goto out;
bca03d5f 2278 }
2279 }
fd112f2e
FR		 2280 rc = true;
2281out:
2282 return rc;
2283}
bca03d5f 2284
fd112f2e
FR		 2285static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2286{
2287 struct net_device *dev = tp->dev;
2288 int rc = -EINVAL;
2289
2290 if (!rtl_fw_format_ok(tp, rtl_fw)) {
2291 netif_err(tp, ifup, dev, "invalid firwmare\n");
2292 goto out;
2293 }
2294
2295 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2296 rc = 0;
2297out:
2298 return rc;
2299}
2300
2301static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2302{
2303 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2304 u32 predata, count;
2305 size_t index;
2306
2307 predata = count = 0;
42b82dc1 2308
1c361efb
FR		 2309 for (index = 0; index < pa->size; ) {
2310 u32 action = le32_to_cpu(pa->code[index]);
bca03d5f 2311 u32 data = action & 0x0000ffff;
42b82dc1 2312 u32 regno = (action & 0x0fff0000) >> 16;
2313
2314 if (!action)
2315 break;
bca03d5f 2316
2317 switch(action & 0xf0000000) {
42b82dc1 2318 case PHY_READ:
2319 predata = rtl_readphy(tp, regno);
2320 count++;
2321 index++;
2322 break;
2323 case PHY_DATA_OR:
2324 predata |= data;
2325 index++;
2326 break;
2327 case PHY_DATA_AND:
2328 predata &= data;
2329 index++;
2330 break;
2331 case PHY_BJMPN:
2332 index -= regno;
2333 break;
2334 case PHY_READ_EFUSE:
fdf6fc06 2335 predata = rtl8168d_efuse_read(tp, regno);
42b82dc1 2336 index++;
2337 break;
2338 case PHY_CLEAR_READCOUNT:
2339 count = 0;
2340 index++;
2341 break;
bca03d5f 2342 case PHY_WRITE:
42b82dc1 2343 rtl_writephy(tp, regno, data);
2344 index++;
2345 break;
2346 case PHY_READCOUNT_EQ_SKIP:
cecb5fd7 2347 index += (count == data) ? 2 : 1;
bca03d5f 2348 break;
42b82dc1 2349 case PHY_COMP_EQ_SKIPN:
2350 if (predata == data)
2351 index += regno;
2352 index++;
2353 break;
2354 case PHY_COMP_NEQ_SKIPN:
2355 if (predata != data)
2356 index += regno;
2357 index++;
2358 break;
2359 case PHY_WRITE_PREVIOUS:
2360 rtl_writephy(tp, regno, predata);
2361 index++;
2362 break;
2363 case PHY_SKIPN:
2364 index += regno + 1;
2365 break;
2366 case PHY_DELAY_MS:
2367 mdelay(data);
2368 index++;
2369 break;
2370
2371 case PHY_READ_MAC_BYTE:
2372 case PHY_WRITE_MAC_BYTE:
2373 case PHY_WRITE_ERI_WORD:
bca03d5f 2374 default:
2375 BUG();
2376 }
2377 }
2378}
2379
f1e02ed1 2380static void rtl_release_firmware(struct rtl8169_private *tp)
2381{
b6ffd97f
FR		 2382 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2383 release_firmware(tp->rtl_fw->fw);
2384 kfree(tp->rtl_fw);
2385 }
2386 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
f1e02ed1 2387}
2388
953a12cc 2389static void rtl_apply_firmware(struct rtl8169_private *tp)
f1e02ed1 2390{
b6ffd97f 2391 struct rtl_fw *rtl_fw = tp->rtl_fw;
f1e02ed1 2392
2393 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
e0c07557 2394 if (!IS_ERR_OR_NULL(rtl_fw)) {
b6ffd97f 2395 rtl_phy_write_fw(tp, rtl_fw);
e0c07557 2396 tp->features |= RTL_FEATURE_FW_LOADED;
2397 }
953a12cc
FR		 2398}
2399
2400static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2401{
2402 if (rtl_readphy(tp, reg) != val)
2403 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2404 else
2405 rtl_apply_firmware(tp);
f1e02ed1 2406}
2407
e0c07557 2408static void r810x_aldps_disable(struct rtl8169_private *tp)
2409{
2410 rtl_writephy(tp, 0x1f, 0x0000);
2411 rtl_writephy(tp, 0x18, 0x0310);
2412 msleep(100);
2413}
2414
2415static void r810x_aldps_enable(struct rtl8169_private *tp)
2416{
2417 if (!(tp->features & RTL_FEATURE_FW_LOADED))
2418 return;
2419
2420 rtl_writephy(tp, 0x1f, 0x0000);
2421 rtl_writephy(tp, 0x18, 0x8310);
2422}
2423
2424static void r8168_aldps_enable_1(struct rtl8169_private *tp)
2425{
2426 if (!(tp->features & RTL_FEATURE_FW_LOADED))
2427 return;
2428
2429 rtl_writephy(tp, 0x1f, 0x0000);
2430 rtl_w1w0_phy(tp, 0x15, 0x1000, 0x0000);
2431}
2432
4da19633 2433static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1da177e4 2434{
350f7596 2435 static const struct phy_reg phy_reg_init[] = {
0b9b571d 2436 { 0x1f, 0x0001 },
2437 { 0x06, 0x006e },
2438 { 0x08, 0x0708 },
2439 { 0x15, 0x4000 },
2440 { 0x18, 0x65c7 },
1da177e4 2441
0b9b571d 2442 { 0x1f, 0x0001 },
2443 { 0x03, 0x00a1 },
2444 { 0x02, 0x0008 },
2445 { 0x01, 0x0120 },
2446 { 0x00, 0x1000 },
2447 { 0x04, 0x0800 },
2448 { 0x04, 0x0000 },
1da177e4 2449
0b9b571d 2450 { 0x03, 0xff41 },
2451 { 0x02, 0xdf60 },
2452 { 0x01, 0x0140 },
2453 { 0x00, 0x0077 },
2454 { 0x04, 0x7800 },
2455 { 0x04, 0x7000 },
2456
2457 { 0x03, 0x802f },
2458 { 0x02, 0x4f02 },
2459 { 0x01, 0x0409 },
2460 { 0x00, 0xf0f9 },
2461 { 0x04, 0x9800 },
2462 { 0x04, 0x9000 },
2463
2464 { 0x03, 0xdf01 },
2465 { 0x02, 0xdf20 },
2466 { 0x01, 0xff95 },
2467 { 0x00, 0xba00 },
2468 { 0x04, 0xa800 },
2469 { 0x04, 0xa000 },
2470
2471 { 0x03, 0xff41 },
2472 { 0x02, 0xdf20 },
2473 { 0x01, 0x0140 },
2474 { 0x00, 0x00bb },
2475 { 0x04, 0xb800 },
2476 { 0x04, 0xb000 },
2477
2478 { 0x03, 0xdf41 },
2479 { 0x02, 0xdc60 },
2480 { 0x01, 0x6340 },
2481 { 0x00, 0x007d },
2482 { 0x04, 0xd800 },
2483 { 0x04, 0xd000 },
2484
2485 { 0x03, 0xdf01 },
2486 { 0x02, 0xdf20 },
2487 { 0x01, 0x100a },
2488 { 0x00, 0xa0ff },
2489 { 0x04, 0xf800 },
2490 { 0x04, 0xf000 },
2491
2492 { 0x1f, 0x0000 },
2493 { 0x0b, 0x0000 },
2494 { 0x00, 0x9200 }
2495 };
1da177e4 2496
4da19633 2497 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1da177e4
LT		 2498}
2499
4da19633 2500static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
5615d9f1 2501{
350f7596 2502 static const struct phy_reg phy_reg_init[] = {
a441d7b6
FR		 2503 { 0x1f, 0x0002 },
2504 { 0x01, 0x90d0 },
2505 { 0x1f, 0x0000 }
2506 };
2507
4da19633 2508 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 2509}
2510
4da19633 2511static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2e955856 2512{
2513 struct pci_dev *pdev = tp->pci_dev;
2e955856 2514
ccbae55e
SS		 2515 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2516 (pdev->subsystem_device != 0xe000))
2e955856 2517 return;
2518
4da19633 2519 rtl_writephy(tp, 0x1f, 0x0001);
2520 rtl_writephy(tp, 0x10, 0xf01b);
2521 rtl_writephy(tp, 0x1f, 0x0000);
2e955856 2522}
2523
4da19633 2524static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2e955856 2525{
350f7596 2526 static const struct phy_reg phy_reg_init[] = {
2e955856 2527 { 0x1f, 0x0001 },
2528 { 0x04, 0x0000 },
2529 { 0x03, 0x00a1 },
2530 { 0x02, 0x0008 },
2531 { 0x01, 0x0120 },
2532 { 0x00, 0x1000 },
2533 { 0x04, 0x0800 },
2534 { 0x04, 0x9000 },
2535 { 0x03, 0x802f },
2536 { 0x02, 0x4f02 },
2537 { 0x01, 0x0409 },
2538 { 0x00, 0xf099 },
2539 { 0x04, 0x9800 },
2540 { 0x04, 0xa000 },
2541 { 0x03, 0xdf01 },
2542 { 0x02, 0xdf20 },
2543 { 0x01, 0xff95 },
2544 { 0x00, 0xba00 },
2545 { 0x04, 0xa800 },
2546 { 0x04, 0xf000 },
2547 { 0x03, 0xdf01 },
2548 { 0x02, 0xdf20 },
2549 { 0x01, 0x101a },
2550 { 0x00, 0xa0ff },
2551 { 0x04, 0xf800 },
2552 { 0x04, 0x0000 },
2553 { 0x1f, 0x0000 },
2554
2555 { 0x1f, 0x0001 },
2556 { 0x10, 0xf41b },
2557 { 0x14, 0xfb54 },
2558 { 0x18, 0xf5c7 },
2559 { 0x1f, 0x0000 },
2560
2561 { 0x1f, 0x0001 },
2562 { 0x17, 0x0cc0 },
2563 { 0x1f, 0x0000 }
2564 };
2565
4da19633 2566 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2e955856 2567
4da19633 2568 rtl8169scd_hw_phy_config_quirk(tp);
2e955856 2569}
2570
4da19633 2571static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
8c7006aa 2572{
350f7596 2573 static const struct phy_reg phy_reg_init[] = {
8c7006aa 2574 { 0x1f, 0x0001 },
2575 { 0x04, 0x0000 },
2576 { 0x03, 0x00a1 },
2577 { 0x02, 0x0008 },
2578 { 0x01, 0x0120 },
2579 { 0x00, 0x1000 },
2580 { 0x04, 0x0800 },
2581 { 0x04, 0x9000 },
2582 { 0x03, 0x802f },
2583 { 0x02, 0x4f02 },
2584 { 0x01, 0x0409 },
2585 { 0x00, 0xf099 },
2586 { 0x04, 0x9800 },
2587 { 0x04, 0xa000 },
2588 { 0x03, 0xdf01 },
2589 { 0x02, 0xdf20 },
2590 { 0x01, 0xff95 },
2591 { 0x00, 0xba00 },
2592 { 0x04, 0xa800 },
2593 { 0x04, 0xf000 },
2594 { 0x03, 0xdf01 },
2595 { 0x02, 0xdf20 },
2596 { 0x01, 0x101a },
2597 { 0x00, 0xa0ff },
2598 { 0x04, 0xf800 },
2599 { 0x04, 0x0000 },
2600 { 0x1f, 0x0000 },
2601
2602 { 0x1f, 0x0001 },
2603 { 0x0b, 0x8480 },
2604 { 0x1f, 0x0000 },
2605
2606 { 0x1f, 0x0001 },
2607 { 0x18, 0x67c7 },
2608 { 0x04, 0x2000 },
2609 { 0x03, 0x002f },
2610 { 0x02, 0x4360 },
2611 { 0x01, 0x0109 },
2612 { 0x00, 0x3022 },
2613 { 0x04, 0x2800 },
2614 { 0x1f, 0x0000 },
2615
2616 { 0x1f, 0x0001 },
2617 { 0x17, 0x0cc0 },
2618 { 0x1f, 0x0000 }
2619 };
2620
4da19633 2621 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
8c7006aa 2622}
2623
4da19633 2624static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
236b8082 2625{
350f7596 2626 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2627 { 0x10, 0xf41b },
2628 { 0x1f, 0x0000 }
2629 };
2630
4da19633 2631 rtl_writephy(tp, 0x1f, 0x0001);
2632 rtl_patchphy(tp, 0x16, 1 << 0);
236b8082 2633
4da19633 2634 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2635}
2636
4da19633 2637static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
236b8082 2638{
350f7596 2639 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2640 { 0x1f, 0x0001 },
2641 { 0x10, 0xf41b },
2642 { 0x1f, 0x0000 }
2643 };
2644
4da19633 2645 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2646}
2647
4da19633 2648static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2649{
350f7596 2650 static const struct phy_reg phy_reg_init[] = {
867763c1
FR		 2651 { 0x1f, 0x0000 },
2652 { 0x1d, 0x0f00 },
2653 { 0x1f, 0x0002 },
2654 { 0x0c, 0x1ec8 },
2655 { 0x1f, 0x0000 }
2656 };
2657
4da19633 2658 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
867763c1
FR		 2659}
2660
4da19633 2661static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
ef3386f0 2662{
350f7596 2663 static const struct phy_reg phy_reg_init[] = {
ef3386f0
FR		 2664 { 0x1f, 0x0001 },
2665 { 0x1d, 0x3d98 },
2666 { 0x1f, 0x0000 }
2667 };
2668
4da19633 2669 rtl_writephy(tp, 0x1f, 0x0000);
2670 rtl_patchphy(tp, 0x14, 1 << 5);
2671 rtl_patchphy(tp, 0x0d, 1 << 5);
ef3386f0 2672
4da19633 2673 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
ef3386f0
FR		 2674}
2675
4da19633 2676static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2677{
350f7596 2678 static const struct phy_reg phy_reg_init[] = {
a3f80671
FR		 2679 { 0x1f, 0x0001 },
2680 { 0x12, 0x2300 },
867763c1
FR		 2681 { 0x1f, 0x0002 },
2682 { 0x00, 0x88d4 },
2683 { 0x01, 0x82b1 },
2684 { 0x03, 0x7002 },
2685 { 0x08, 0x9e30 },
2686 { 0x09, 0x01f0 },
2687 { 0x0a, 0x5500 },
2688 { 0x0c, 0x00c8 },
2689 { 0x1f, 0x0003 },
2690 { 0x12, 0xc096 },
2691 { 0x16, 0x000a },
f50d4275
FR		 2692 { 0x1f, 0x0000 },
2693 { 0x1f, 0x0000 },
2694 { 0x09, 0x2000 },
2695 { 0x09, 0x0000 }
867763c1
FR		 2696 };
2697
4da19633 2698 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2699
4da19633 2700 rtl_patchphy(tp, 0x14, 1 << 5);
2701 rtl_patchphy(tp, 0x0d, 1 << 5);
2702 rtl_writephy(tp, 0x1f, 0x0000);
867763c1
FR		 2703}
2704
4da19633 2705static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
7da97ec9 2706{
350f7596 2707 static const struct phy_reg phy_reg_init[] = {
f50d4275 2708 { 0x1f, 0x0001 },
7da97ec9 2709 { 0x12, 0x2300 },
f50d4275
FR		 2710 { 0x03, 0x802f },
2711 { 0x02, 0x4f02 },
2712 { 0x01, 0x0409 },
2713 { 0x00, 0xf099 },
2714 { 0x04, 0x9800 },
2715 { 0x04, 0x9000 },
2716 { 0x1d, 0x3d98 },
7da97ec9
FR		 2717 { 0x1f, 0x0002 },
2718 { 0x0c, 0x7eb8 },
f50d4275
FR		 2719 { 0x06, 0x0761 },
2720 { 0x1f, 0x0003 },
2721 { 0x16, 0x0f0a },
7da97ec9
FR		 2722 { 0x1f, 0x0000 }
2723 };
2724
4da19633 2725 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2726
4da19633 2727 rtl_patchphy(tp, 0x16, 1 << 0);
2728 rtl_patchphy(tp, 0x14, 1 << 5);
2729 rtl_patchphy(tp, 0x0d, 1 << 5);
2730 rtl_writephy(tp, 0x1f, 0x0000);
7da97ec9
FR		 2731}
2732
4da19633 2733static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
197ff761 2734{
350f7596 2735 static const struct phy_reg phy_reg_init[] = {
197ff761
FR		 2736 { 0x1f, 0x0001 },
2737 { 0x12, 0x2300 },
2738 { 0x1d, 0x3d98 },
2739 { 0x1f, 0x0002 },
2740 { 0x0c, 0x7eb8 },
2741 { 0x06, 0x5461 },
2742 { 0x1f, 0x0003 },
2743 { 0x16, 0x0f0a },
2744 { 0x1f, 0x0000 }
2745 };
2746
4da19633 2747 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
197ff761 2748
4da19633 2749 rtl_patchphy(tp, 0x16, 1 << 0);
2750 rtl_patchphy(tp, 0x14, 1 << 5);
2751 rtl_patchphy(tp, 0x0d, 1 << 5);
2752 rtl_writephy(tp, 0x1f, 0x0000);
197ff761
FR		 2753}
2754
4da19633 2755static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
6fb07058 2756{
4da19633 2757 rtl8168c_3_hw_phy_config(tp);
6fb07058
FR		 2758}
2759
bca03d5f 2760static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
5b538df9 2761{
350f7596 2762 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2763 /* Channel Estimation */
5b538df9 2764 { 0x1f, 0x0001 },
daf9df6d 2765 { 0x06, 0x4064 },
2766 { 0x07, 0x2863 },
2767 { 0x08, 0x059c },
2768 { 0x09, 0x26b4 },
2769 { 0x0a, 0x6a19 },
2770 { 0x0b, 0xdcc8 },
2771 { 0x10, 0xf06d },
2772 { 0x14, 0x7f68 },
2773 { 0x18, 0x7fd9 },
2774 { 0x1c, 0xf0ff },
2775 { 0x1d, 0x3d9c },
5b538df9 2776 { 0x1f, 0x0003 },
daf9df6d 2777 { 0x12, 0xf49f },
2778 { 0x13, 0x070b },
2779 { 0x1a, 0x05ad },
bca03d5f 2780 { 0x14, 0x94c0 },
2781
2782 /*
2783 * Tx Error Issue
cecb5fd7 2784 * Enhance line driver power
bca03d5f 2785 */
5b538df9 2786 { 0x1f, 0x0002 },
daf9df6d 2787 { 0x06, 0x5561 },
2788 { 0x1f, 0x0005 },
2789 { 0x05, 0x8332 },
bca03d5f 2790 { 0x06, 0x5561 },
2791
2792 /*
2793 * Can not link to 1Gbps with bad cable
2794 * Decrease SNR threshold form 21.07dB to 19.04dB
2795 */
2796 { 0x1f, 0x0001 },
2797 { 0x17, 0x0cc0 },
daf9df6d 2798
5b538df9 2799 { 0x1f, 0x0000 },
bca03d5f 2800 { 0x0d, 0xf880 }
daf9df6d 2801 };
2802
4da19633 2803 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
daf9df6d 2804
bca03d5f 2805 /*
2806 * Rx Error Issue
2807 * Fine Tune Switching regulator parameter
2808 */
4da19633 2809 rtl_writephy(tp, 0x1f, 0x0002);
2810 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2811 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
daf9df6d 2812
fdf6fc06 2813 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
350f7596 2814 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2815 { 0x1f, 0x0002 },
2816 { 0x05, 0x669a },
2817 { 0x1f, 0x0005 },
2818 { 0x05, 0x8330 },
2819 { 0x06, 0x669a },
2820 { 0x1f, 0x0002 }
2821 };
2822 int val;
2823
4da19633 2824 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2825
4da19633 2826 val = rtl_readphy(tp, 0x0d);
daf9df6d 2827
2828 if ((val & 0x00ff) != 0x006c) {
350f7596 2829 static const u32 set[] = {
daf9df6d 2830 0x0065, 0x0066, 0x0067, 0x0068,
2831 0x0069, 0x006a, 0x006b, 0x006c
2832 };
2833 int i;
2834
4da19633 2835 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2836
2837 val &= 0xff00;
2838 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2839 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2840 }
2841 } else {
350f7596 2842 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2843 { 0x1f, 0x0002 },
2844 { 0x05, 0x6662 },
2845 { 0x1f, 0x0005 },
2846 { 0x05, 0x8330 },
2847 { 0x06, 0x6662 }
2848 };
2849
4da19633 2850 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2851 }
2852
bca03d5f 2853 /* RSET couple improve */
4da19633 2854 rtl_writephy(tp, 0x1f, 0x0002);
2855 rtl_patchphy(tp, 0x0d, 0x0300);
2856 rtl_patchphy(tp, 0x0f, 0x0010);
daf9df6d 2857
bca03d5f 2858 /* Fine tune PLL performance */
4da19633 2859 rtl_writephy(tp, 0x1f, 0x0002);
2860 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2861 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2862
4da19633 2863 rtl_writephy(tp, 0x1f, 0x0005);
2864 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2865
2866 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
bca03d5f 2867
4da19633 2868 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2869}
2870
bca03d5f 2871static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2872{
350f7596 2873 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2874 /* Channel Estimation */
daf9df6d 2875 { 0x1f, 0x0001 },
2876 { 0x06, 0x4064 },
2877 { 0x07, 0x2863 },
2878 { 0x08, 0x059c },
2879 { 0x09, 0x26b4 },
2880 { 0x0a, 0x6a19 },
2881 { 0x0b, 0xdcc8 },
2882 { 0x10, 0xf06d },
2883 { 0x14, 0x7f68 },
2884 { 0x18, 0x7fd9 },
2885 { 0x1c, 0xf0ff },
2886 { 0x1d, 0x3d9c },
2887 { 0x1f, 0x0003 },
2888 { 0x12, 0xf49f },
2889 { 0x13, 0x070b },
2890 { 0x1a, 0x05ad },
2891 { 0x14, 0x94c0 },
2892
bca03d5f 2893 /*
2894 * Tx Error Issue
cecb5fd7 2895 * Enhance line driver power
bca03d5f 2896 */
daf9df6d 2897 { 0x1f, 0x0002 },
2898 { 0x06, 0x5561 },
2899 { 0x1f, 0x0005 },
2900 { 0x05, 0x8332 },
bca03d5f 2901 { 0x06, 0x5561 },
2902
2903 /*
2904 * Can not link to 1Gbps with bad cable
2905 * Decrease SNR threshold form 21.07dB to 19.04dB
2906 */
2907 { 0x1f, 0x0001 },
2908 { 0x17, 0x0cc0 },
daf9df6d 2909
2910 { 0x1f, 0x0000 },
bca03d5f 2911 { 0x0d, 0xf880 }
5b538df9
FR		 2912 };
2913
4da19633 2914 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
5b538df9 2915
fdf6fc06 2916 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
350f7596 2917 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2918 { 0x1f, 0x0002 },
2919 { 0x05, 0x669a },
5b538df9 2920 { 0x1f, 0x0005 },
daf9df6d 2921 { 0x05, 0x8330 },
2922 { 0x06, 0x669a },
2923
2924 { 0x1f, 0x0002 }
2925 };
2926 int val;
2927
4da19633 2928 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2929
4da19633 2930 val = rtl_readphy(tp, 0x0d);
daf9df6d 2931 if ((val & 0x00ff) != 0x006c) {
b6bc7650 2932 static const u32 set[] = {
daf9df6d 2933 0x0065, 0x0066, 0x0067, 0x0068,
2934 0x0069, 0x006a, 0x006b, 0x006c
2935 };
2936 int i;
2937
4da19633 2938 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2939
2940 val &= 0xff00;
2941 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2942 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2943 }
2944 } else {
350f7596 2945 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2946 { 0x1f, 0x0002 },
2947 { 0x05, 0x2642 },
5b538df9 2948 { 0x1f, 0x0005 },
daf9df6d 2949 { 0x05, 0x8330 },
2950 { 0x06, 0x2642 }
5b538df9
FR		 2951 };
2952
4da19633 2953 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2954 }
2955
bca03d5f 2956 /* Fine tune PLL performance */
4da19633 2957 rtl_writephy(tp, 0x1f, 0x0002);
2958 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2959 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2960
bca03d5f 2961 /* Switching regulator Slew rate */
4da19633 2962 rtl_writephy(tp, 0x1f, 0x0002);
2963 rtl_patchphy(tp, 0x0f, 0x0017);
daf9df6d 2964
4da19633 2965 rtl_writephy(tp, 0x1f, 0x0005);
2966 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2967
2968 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
bca03d5f 2969
4da19633 2970 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2971}
2972
4da19633 2973static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2974{
350f7596 2975 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2976 { 0x1f, 0x0002 },
2977 { 0x10, 0x0008 },
2978 { 0x0d, 0x006c },
2979
2980 { 0x1f, 0x0000 },
2981 { 0x0d, 0xf880 },
2982
2983 { 0x1f, 0x0001 },
2984 { 0x17, 0x0cc0 },
2985
2986 { 0x1f, 0x0001 },
2987 { 0x0b, 0xa4d8 },
2988 { 0x09, 0x281c },
2989 { 0x07, 0x2883 },
2990 { 0x0a, 0x6b35 },
2991 { 0x1d, 0x3da4 },
2992 { 0x1c, 0xeffd },
2993 { 0x14, 0x7f52 },
2994 { 0x18, 0x7fc6 },
2995 { 0x08, 0x0601 },
2996 { 0x06, 0x4063 },
2997 { 0x10, 0xf074 },
2998 { 0x1f, 0x0003 },
2999 { 0x13, 0x0789 },
3000 { 0x12, 0xf4bd },
3001 { 0x1a, 0x04fd },
3002 { 0x14, 0x84b0 },
3003 { 0x1f, 0x0000 },
3004 { 0x00, 0x9200 },
3005
3006 { 0x1f, 0x0005 },
3007 { 0x01, 0x0340 },
3008 { 0x1f, 0x0001 },
3009 { 0x04, 0x4000 },
3010 { 0x03, 0x1d21 },
3011 { 0x02, 0x0c32 },
3012 { 0x01, 0x0200 },
3013 { 0x00, 0x5554 },
3014 { 0x04, 0x4800 },
3015 { 0x04, 0x4000 },
3016 { 0x04, 0xf000 },
3017 { 0x03, 0xdf01 },
3018 { 0x02, 0xdf20 },
3019 { 0x01, 0x101a },
3020 { 0x00, 0xa0ff },
3021 { 0x04, 0xf800 },
3022 { 0x04, 0xf000 },
3023 { 0x1f, 0x0000 },
3024
3025 { 0x1f, 0x0007 },
3026 { 0x1e, 0x0023 },
3027 { 0x16, 0x0000 },
3028 { 0x1f, 0x0000 }
3029 };
3030
4da19633 3031 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 3032}
3033
e6de30d6 3034static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3035{
3036 static const struct phy_reg phy_reg_init[] = {
3037 { 0x1f, 0x0001 },
3038 { 0x17, 0x0cc0 },
3039
3040 { 0x1f, 0x0007 },
3041 { 0x1e, 0x002d },
3042 { 0x18, 0x0040 },
3043 { 0x1f, 0x0000 }
3044 };
3045
3046 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3047 rtl_patchphy(tp, 0x0d, 1 << 5);
3048}
3049
70090424 3050static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
01dc7fec 3051{
3052 static const struct phy_reg phy_reg_init[] = {
3053 /* Enable Delay cap */
3054 { 0x1f, 0x0005 },
3055 { 0x05, 0x8b80 },
3056 { 0x06, 0xc896 },
3057 { 0x1f, 0x0000 },
3058
3059 /* Channel estimation fine tune */
3060 { 0x1f, 0x0001 },
3061 { 0x0b, 0x6c20 },
3062 { 0x07, 0x2872 },
3063 { 0x1c, 0xefff },
3064 { 0x1f, 0x0003 },
3065 { 0x14, 0x6420 },
3066 { 0x1f, 0x0000 },
3067
3068 /* Update PFM & 10M TX idle timer */
3069 { 0x1f, 0x0007 },
3070 { 0x1e, 0x002f },
3071 { 0x15, 0x1919 },
3072 { 0x1f, 0x0000 },
3073
3074 { 0x1f, 0x0007 },
3075 { 0x1e, 0x00ac },
3076 { 0x18, 0x0006 },
3077 { 0x1f, 0x0000 }
3078 };
3079
15ecd039
FR		 3080 rtl_apply_firmware(tp);
3081
01dc7fec 3082 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3083
3084 /* DCO enable for 10M IDLE Power */
3085 rtl_writephy(tp, 0x1f, 0x0007);
3086 rtl_writephy(tp, 0x1e, 0x0023);
3087 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
3088 rtl_writephy(tp, 0x1f, 0x0000);
3089
3090 /* For impedance matching */
3091 rtl_writephy(tp, 0x1f, 0x0002);
3092 rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
cecb5fd7 3093 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3094
3095 /* PHY auto speed down */
3096 rtl_writephy(tp, 0x1f, 0x0007);
3097 rtl_writephy(tp, 0x1e, 0x002d);
3098 rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
3099 rtl_writephy(tp, 0x1f, 0x0000);
3100 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3101
3102 rtl_writephy(tp, 0x1f, 0x0005);
3103 rtl_writephy(tp, 0x05, 0x8b86);
3104 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3105 rtl_writephy(tp, 0x1f, 0x0000);
3106
3107 rtl_writephy(tp, 0x1f, 0x0005);
3108 rtl_writephy(tp, 0x05, 0x8b85);
3109 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3110 rtl_writephy(tp, 0x1f, 0x0007);
3111 rtl_writephy(tp, 0x1e, 0x0020);
3112 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
3113 rtl_writephy(tp, 0x1f, 0x0006);
3114 rtl_writephy(tp, 0x00, 0x5a00);
3115 rtl_writephy(tp, 0x1f, 0x0000);
3116 rtl_writephy(tp, 0x0d, 0x0007);
3117 rtl_writephy(tp, 0x0e, 0x003c);
3118 rtl_writephy(tp, 0x0d, 0x4007);
3119 rtl_writephy(tp, 0x0e, 0x0000);
3120 rtl_writephy(tp, 0x0d, 0x0000);
3121}
3122
9ecb9aab 3123static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3124{
3125 const u16 w[] = {
3126 addr[0] | (addr[1] << 8),
3127 addr[2] | (addr[3] << 8),
3128 addr[4] | (addr[5] << 8)
3129 };
3130 const struct exgmac_reg e[] = {
3131 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3132 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3133 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3134 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3135 };
3136
3137 rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3138}
3139
70090424
HW		 3140static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3141{
3142 static const struct phy_reg phy_reg_init[] = {
3143 /* Enable Delay cap */
3144 { 0x1f, 0x0004 },
3145 { 0x1f, 0x0007 },
3146 { 0x1e, 0x00ac },
3147 { 0x18, 0x0006 },
3148 { 0x1f, 0x0002 },
3149 { 0x1f, 0x0000 },
3150 { 0x1f, 0x0000 },
3151
3152 /* Channel estimation fine tune */
3153 { 0x1f, 0x0003 },
3154 { 0x09, 0xa20f },
3155 { 0x1f, 0x0000 },
3156 { 0x1f, 0x0000 },
3157
3158 /* Green Setting */
3159 { 0x1f, 0x0005 },
3160 { 0x05, 0x8b5b },
3161 { 0x06, 0x9222 },
3162 { 0x05, 0x8b6d },
3163 { 0x06, 0x8000 },
3164 { 0x05, 0x8b76 },
3165 { 0x06, 0x8000 },
3166 { 0x1f, 0x0000 }
3167 };
3168
3169 rtl_apply_firmware(tp);
3170
3171 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3172
3173 /* For 4-corner performance improve */
3174 rtl_writephy(tp, 0x1f, 0x0005);
3175 rtl_writephy(tp, 0x05, 0x8b80);
3176 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
3177 rtl_writephy(tp, 0x1f, 0x0000);
3178
3179 /* PHY auto speed down */
3180 rtl_writephy(tp, 0x1f, 0x0004);
3181 rtl_writephy(tp, 0x1f, 0x0007);
3182 rtl_writephy(tp, 0x1e, 0x002d);
3183 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3184 rtl_writephy(tp, 0x1f, 0x0002);
3185 rtl_writephy(tp, 0x1f, 0x0000);
3186 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3187
3188 /* improve 10M EEE waveform */
3189 rtl_writephy(tp, 0x1f, 0x0005);
3190 rtl_writephy(tp, 0x05, 0x8b86);
3191 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3192 rtl_writephy(tp, 0x1f, 0x0000);
3193
3194 /* Improve 2-pair detection performance */
3195 rtl_writephy(tp, 0x1f, 0x0005);
3196 rtl_writephy(tp, 0x05, 0x8b85);
3197 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3198 rtl_writephy(tp, 0x1f, 0x0000);
3199
3200 /* EEE setting */
fdf6fc06 3201 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, ERIAR_EXGMAC);
70090424
HW		 3202 rtl_writephy(tp, 0x1f, 0x0005);
3203 rtl_writephy(tp, 0x05, 0x8b85);
3204 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3205 rtl_writephy(tp, 0x1f, 0x0004);
3206 rtl_writephy(tp, 0x1f, 0x0007);
3207 rtl_writephy(tp, 0x1e, 0x0020);
1b23a3e3 3208 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
70090424
HW		 3209 rtl_writephy(tp, 0x1f, 0x0002);
3210 rtl_writephy(tp, 0x1f, 0x0000);
3211 rtl_writephy(tp, 0x0d, 0x0007);
3212 rtl_writephy(tp, 0x0e, 0x003c);
3213 rtl_writephy(tp, 0x0d, 0x4007);
3214 rtl_writephy(tp, 0x0e, 0x0000);
3215 rtl_writephy(tp, 0x0d, 0x0000);
3216
3217 /* Green feature */
3218 rtl_writephy(tp, 0x1f, 0x0003);
3219 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3220 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3221 rtl_writephy(tp, 0x1f, 0x0000);
e0c07557 3222
3223 r8168_aldps_enable_1(tp);
9ecb9aab 3224
3225 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3226 rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
70090424
HW		 3227}
3228
5f886e08
HW		 3229static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3230{
3231 /* For 4-corner performance improve */
3232 rtl_writephy(tp, 0x1f, 0x0005);
3233 rtl_writephy(tp, 0x05, 0x8b80);
3234 rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3235 rtl_writephy(tp, 0x1f, 0x0000);
3236
3237 /* PHY auto speed down */
3238 rtl_writephy(tp, 0x1f, 0x0007);
3239 rtl_writephy(tp, 0x1e, 0x002d);
3240 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3241 rtl_writephy(tp, 0x1f, 0x0000);
3242 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3243
3244 /* Improve 10M EEE waveform */
3245 rtl_writephy(tp, 0x1f, 0x0005);
3246 rtl_writephy(tp, 0x05, 0x8b86);
3247 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3248 rtl_writephy(tp, 0x1f, 0x0000);
3249}
3250
c2218925
HW		 3251static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3252{
3253 static const struct phy_reg phy_reg_init[] = {
3254 /* Channel estimation fine tune */
3255 { 0x1f, 0x0003 },
3256 { 0x09, 0xa20f },
3257 { 0x1f, 0x0000 },
3258
3259 /* Modify green table for giga & fnet */
3260 { 0x1f, 0x0005 },
3261 { 0x05, 0x8b55 },
3262 { 0x06, 0x0000 },
3263 { 0x05, 0x8b5e },
3264 { 0x06, 0x0000 },
3265 { 0x05, 0x8b67 },
3266 { 0x06, 0x0000 },
3267 { 0x05, 0x8b70 },
3268 { 0x06, 0x0000 },
3269 { 0x1f, 0x0000 },
3270 { 0x1f, 0x0007 },
3271 { 0x1e, 0x0078 },
3272 { 0x17, 0x0000 },
3273 { 0x19, 0x00fb },
3274 { 0x1f, 0x0000 },
3275
3276 /* Modify green table for 10M */
3277 { 0x1f, 0x0005 },
3278 { 0x05, 0x8b79 },
3279 { 0x06, 0xaa00 },
3280 { 0x1f, 0x0000 },
3281
3282 /* Disable hiimpedance detection (RTCT) */
3283 { 0x1f, 0x0003 },
3284 { 0x01, 0x328a },
3285 { 0x1f, 0x0000 }
3286 };
3287
3288 rtl_apply_firmware(tp);
3289
3290 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3291
5f886e08 3292 rtl8168f_hw_phy_config(tp);
c2218925
HW		 3293
3294 /* Improve 2-pair detection performance */
3295 rtl_writephy(tp, 0x1f, 0x0005);
3296 rtl_writephy(tp, 0x05, 0x8b85);
3297 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3298 rtl_writephy(tp, 0x1f, 0x0000);
e0c07557 3299
3300 r8168_aldps_enable_1(tp);
c2218925
HW		 3301}
3302
3303static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3304{
3305 rtl_apply_firmware(tp);
3306
5f886e08 3307 rtl8168f_hw_phy_config(tp);
e0c07557 3308
3309 r8168_aldps_enable_1(tp);
c2218925
HW		 3310}
3311
b3d7b2f2
HW		 3312static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3313{
b3d7b2f2
HW		 3314 static const struct phy_reg phy_reg_init[] = {
3315 /* Channel estimation fine tune */
3316 { 0x1f, 0x0003 },
3317 { 0x09, 0xa20f },
3318 { 0x1f, 0x0000 },
3319
3320 /* Modify green table for giga & fnet */
3321 { 0x1f, 0x0005 },
3322 { 0x05, 0x8b55 },
3323 { 0x06, 0x0000 },
3324 { 0x05, 0x8b5e },
3325 { 0x06, 0x0000 },
3326 { 0x05, 0x8b67 },
3327 { 0x06, 0x0000 },
3328 { 0x05, 0x8b70 },
3329 { 0x06, 0x0000 },
3330 { 0x1f, 0x0000 },
3331 { 0x1f, 0x0007 },
3332 { 0x1e, 0x0078 },
3333 { 0x17, 0x0000 },
3334 { 0x19, 0x00aa },
3335 { 0x1f, 0x0000 },
3336
3337 /* Modify green table for 10M */
3338 { 0x1f, 0x0005 },
3339 { 0x05, 0x8b79 },
3340 { 0x06, 0xaa00 },
3341 { 0x1f, 0x0000 },
3342
3343 /* Disable hiimpedance detection (RTCT) */
3344 { 0x1f, 0x0003 },
3345 { 0x01, 0x328a },
3346 { 0x1f, 0x0000 }
3347 };
3348
3349
3350 rtl_apply_firmware(tp);
3351
3352 rtl8168f_hw_phy_config(tp);
3353
3354 /* Improve 2-pair detection performance */
3355 rtl_writephy(tp, 0x1f, 0x0005);
3356 rtl_writephy(tp, 0x05, 0x8b85);
3357 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3358 rtl_writephy(tp, 0x1f, 0x0000);
3359
3360 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3361
3362 /* Modify green table for giga */
3363 rtl_writephy(tp, 0x1f, 0x0005);
3364 rtl_writephy(tp, 0x05, 0x8b54);
3365 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
3366 rtl_writephy(tp, 0x05, 0x8b5d);
3367 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
3368 rtl_writephy(tp, 0x05, 0x8a7c);
3369 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3370 rtl_writephy(tp, 0x05, 0x8a7f);
3371 rtl_w1w0_phy(tp, 0x06, 0x0100, 0x0000);
3372 rtl_writephy(tp, 0x05, 0x8a82);
3373 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3374 rtl_writephy(tp, 0x05, 0x8a85);
3375 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3376 rtl_writephy(tp, 0x05, 0x8a88);
3377 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3378 rtl_writephy(tp, 0x1f, 0x0000);
3379
3380 /* uc same-seed solution */
3381 rtl_writephy(tp, 0x1f, 0x0005);
3382 rtl_writephy(tp, 0x05, 0x8b85);
3383 rtl_w1w0_phy(tp, 0x06, 0x8000, 0x0000);
3384 rtl_writephy(tp, 0x1f, 0x0000);
3385
3386 /* eee setting */
fdf6fc06 3387 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
b3d7b2f2
HW		 3388 rtl_writephy(tp, 0x1f, 0x0005);
3389 rtl_writephy(tp, 0x05, 0x8b85);
3390 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3391 rtl_writephy(tp, 0x1f, 0x0004);
3392 rtl_writephy(tp, 0x1f, 0x0007);
3393 rtl_writephy(tp, 0x1e, 0x0020);
3394 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
3395 rtl_writephy(tp, 0x1f, 0x0000);
3396 rtl_writephy(tp, 0x0d, 0x0007);
3397 rtl_writephy(tp, 0x0e, 0x003c);
3398 rtl_writephy(tp, 0x0d, 0x4007);
3399 rtl_writephy(tp, 0x0e, 0x0000);
3400 rtl_writephy(tp, 0x0d, 0x0000);
3401
3402 /* Green feature */
3403 rtl_writephy(tp, 0x1f, 0x0003);
3404 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3405 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3406 rtl_writephy(tp, 0x1f, 0x0000);
e0c07557 3407
3408 r8168_aldps_enable_1(tp);
b3d7b2f2
HW		 3409}
3410
c558386b
HW		 3411static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3412{
3413 static const u16 mac_ocp_patch[] = {
3414 0xe008, 0xe01b, 0xe01d, 0xe01f,
3415 0xe021, 0xe023, 0xe025, 0xe027,
3416 0x49d2, 0xf10d, 0x766c, 0x49e2,
3417 0xf00a, 0x1ec0, 0x8ee1, 0xc60a,
3418
3419 0x77c0, 0x4870, 0x9fc0, 0x1ea0,
3420 0xc707, 0x8ee1, 0x9d6c, 0xc603,
3421 0xbe00, 0xb416, 0x0076, 0xe86c,
3422 0xc602, 0xbe00, 0x0000, 0xc602,
3423
3424 0xbe00, 0x0000, 0xc602, 0xbe00,
3425 0x0000, 0xc602, 0xbe00, 0x0000,
3426 0xc602, 0xbe00, 0x0000, 0xc602,
3427 0xbe00, 0x0000, 0xc602, 0xbe00,
3428
3429 0x0000, 0x0000, 0x0000, 0x0000
3430 };
3431 u32 i;
3432
3433 /* Patch code for GPHY reset */
3434 for (i = 0; i < ARRAY_SIZE(mac_ocp_patch); i++)
3435 r8168_mac_ocp_write(tp, 0xf800 + 2*i, mac_ocp_patch[i]);
3436 r8168_mac_ocp_write(tp, 0xfc26, 0x8000);
3437 r8168_mac_ocp_write(tp, 0xfc28, 0x0075);
3438
3439 rtl_apply_firmware(tp);
3440
3441 if (r8168_phy_ocp_read(tp, 0xa460) & 0x0100)
3442 rtl_w1w0_phy_ocp(tp, 0xbcc4, 0x0000, 0x8000);
3443 else
3444 rtl_w1w0_phy_ocp(tp, 0xbcc4, 0x8000, 0x0000);
3445
3446 if (r8168_phy_ocp_read(tp, 0xa466) & 0x0100)
3447 rtl_w1w0_phy_ocp(tp, 0xc41a, 0x0002, 0x0000);
3448 else
3449 rtl_w1w0_phy_ocp(tp, 0xbcc4, 0x0000, 0x0002);
3450
3451 rtl_w1w0_phy_ocp(tp, 0xa442, 0x000c, 0x0000);
3452 rtl_w1w0_phy_ocp(tp, 0xa4b2, 0x0004, 0x0000);
3453
3454 r8168_phy_ocp_write(tp, 0xa436, 0x8012);
3455 rtl_w1w0_phy_ocp(tp, 0xa438, 0x8000, 0x0000);
3456
3457 rtl_w1w0_phy_ocp(tp, 0xc422, 0x4000, 0x2000);
3458}
3459
4da19633 3460static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2857ffb7 3461{
350f7596 3462 static const struct phy_reg phy_reg_init[] = {
2857ffb7
FR		 3463 { 0x1f, 0x0003 },
3464 { 0x08, 0x441d },
3465 { 0x01, 0x9100 },
3466 { 0x1f, 0x0000 }
3467 };
3468
4da19633 3469 rtl_writephy(tp, 0x1f, 0x0000);
3470 rtl_patchphy(tp, 0x11, 1 << 12);
3471 rtl_patchphy(tp, 0x19, 1 << 13);
3472 rtl_patchphy(tp, 0x10, 1 << 15);
2857ffb7 3473
4da19633 3474 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2857ffb7
FR		 3475}
3476
5a5e4443
HW		 3477static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3478{
3479 static const struct phy_reg phy_reg_init[] = {
3480 { 0x1f, 0x0005 },
3481 { 0x1a, 0x0000 },
3482 { 0x1f, 0x0000 },
3483
3484 { 0x1f, 0x0004 },
3485 { 0x1c, 0x0000 },
3486 { 0x1f, 0x0000 },
3487
3488 { 0x1f, 0x0001 },
3489 { 0x15, 0x7701 },
3490 { 0x1f, 0x0000 }
3491 };
3492
3493 /* Disable ALDPS before ram code */
e0c07557 3494 r810x_aldps_disable(tp);
5a5e4443 3495
953a12cc 3496 rtl_apply_firmware(tp);
5a5e4443
HW		 3497
3498 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
e0c07557 3499
3500 r810x_aldps_enable(tp);
5a5e4443
HW		 3501}
3502
7e18dca1
HW		 3503static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3504{
7e18dca1 3505 /* Disable ALDPS before setting firmware */
e0c07557 3506 r810x_aldps_disable(tp);
7e18dca1
HW		 3507
3508 rtl_apply_firmware(tp);
3509
3510 /* EEE setting */
fdf6fc06 3511 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
7e18dca1
HW		 3512 rtl_writephy(tp, 0x1f, 0x0004);
3513 rtl_writephy(tp, 0x10, 0x401f);
3514 rtl_writephy(tp, 0x19, 0x7030);
3515 rtl_writephy(tp, 0x1f, 0x0000);
e0c07557 3516
3517 r810x_aldps_enable(tp);
7e18dca1
HW		 3518}
3519
5598bfe5
HW		 3520static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3521{
5598bfe5
HW		 3522 static const struct phy_reg phy_reg_init[] = {
3523 { 0x1f, 0x0004 },
3524 { 0x10, 0xc07f },
3525 { 0x19, 0x7030 },
3526 { 0x1f, 0x0000 }
3527 };
3528
3529 /* Disable ALDPS before ram code */
e0c07557 3530 r810x_aldps_disable(tp);
5598bfe5
HW		 3531
3532 rtl_apply_firmware(tp);
3533
fdf6fc06 3534 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5598bfe5
HW		 3535 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3536
fdf6fc06 3537 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
e0c07557 3538
3539 r810x_aldps_enable(tp);
5598bfe5
HW		 3540}
3541
5615d9f1
FR		 3542static void rtl_hw_phy_config(struct net_device *dev)
3543{
3544 struct rtl8169_private *tp = netdev_priv(dev);
5615d9f1
FR		 3545
3546 rtl8169_print_mac_version(tp);
3547
3548 switch (tp->mac_version) {
3549 case RTL_GIGA_MAC_VER_01:
3550 break;
3551 case RTL_GIGA_MAC_VER_02:
3552 case RTL_GIGA_MAC_VER_03:
4da19633 3553 rtl8169s_hw_phy_config(tp);
5615d9f1
FR		 3554 break;
3555 case RTL_GIGA_MAC_VER_04:
4da19633 3556 rtl8169sb_hw_phy_config(tp);
5615d9f1 3557 break;
2e955856 3558 case RTL_GIGA_MAC_VER_05:
4da19633 3559 rtl8169scd_hw_phy_config(tp);
2e955856 3560 break;
8c7006aa 3561 case RTL_GIGA_MAC_VER_06:
4da19633 3562 rtl8169sce_hw_phy_config(tp);
8c7006aa 3563 break;
2857ffb7
FR		 3564 case RTL_GIGA_MAC_VER_07:
3565 case RTL_GIGA_MAC_VER_08:
3566 case RTL_GIGA_MAC_VER_09:
4da19633 3567 rtl8102e_hw_phy_config(tp);
2857ffb7 3568 break;
236b8082 3569 case RTL_GIGA_MAC_VER_11:
4da19633 3570 rtl8168bb_hw_phy_config(tp);
236b8082
FR		 3571 break;
3572 case RTL_GIGA_MAC_VER_12:
4da19633 3573 rtl8168bef_hw_phy_config(tp);
236b8082
FR		 3574 break;
3575 case RTL_GIGA_MAC_VER_17:
4da19633 3576 rtl8168bef_hw_phy_config(tp);
236b8082 3577 break;
867763c1 3578 case RTL_GIGA_MAC_VER_18:
4da19633 3579 rtl8168cp_1_hw_phy_config(tp);
867763c1
FR		 3580 break;
3581 case RTL_GIGA_MAC_VER_19:
4da19633 3582 rtl8168c_1_hw_phy_config(tp);
867763c1 3583 break;
7da97ec9 3584 case RTL_GIGA_MAC_VER_20:
4da19633 3585 rtl8168c_2_hw_phy_config(tp);
7da97ec9 3586 break;
197ff761 3587 case RTL_GIGA_MAC_VER_21:
4da19633 3588 rtl8168c_3_hw_phy_config(tp);
197ff761 3589 break;
6fb07058 3590 case RTL_GIGA_MAC_VER_22:
4da19633 3591 rtl8168c_4_hw_phy_config(tp);
6fb07058 3592 break;
ef3386f0 3593 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 3594 case RTL_GIGA_MAC_VER_24:
4da19633 3595 rtl8168cp_2_hw_phy_config(tp);
ef3386f0 3596 break;
5b538df9 3597 case RTL_GIGA_MAC_VER_25:
bca03d5f 3598 rtl8168d_1_hw_phy_config(tp);
daf9df6d 3599 break;
3600 case RTL_GIGA_MAC_VER_26:
bca03d5f 3601 rtl8168d_2_hw_phy_config(tp);
daf9df6d 3602 break;
3603 case RTL_GIGA_MAC_VER_27:
4da19633 3604 rtl8168d_3_hw_phy_config(tp);
5b538df9 3605 break;
e6de30d6 3606 case RTL_GIGA_MAC_VER_28:
3607 rtl8168d_4_hw_phy_config(tp);
3608 break;
5a5e4443
HW		 3609 case RTL_GIGA_MAC_VER_29:
3610 case RTL_GIGA_MAC_VER_30:
3611 rtl8105e_hw_phy_config(tp);
3612 break;
cecb5fd7
FR		 3613 case RTL_GIGA_MAC_VER_31:
3614 /* None. */
3615 break;
01dc7fec 3616 case RTL_GIGA_MAC_VER_32:
01dc7fec 3617 case RTL_GIGA_MAC_VER_33:
70090424
HW		 3618 rtl8168e_1_hw_phy_config(tp);
3619 break;
3620 case RTL_GIGA_MAC_VER_34:
3621 rtl8168e_2_hw_phy_config(tp);
01dc7fec 3622 break;
c2218925
HW		 3623 case RTL_GIGA_MAC_VER_35:
3624 rtl8168f_1_hw_phy_config(tp);
3625 break;
3626 case RTL_GIGA_MAC_VER_36:
3627 rtl8168f_2_hw_phy_config(tp);
3628 break;
ef3386f0 3629
7e18dca1
HW		 3630 case RTL_GIGA_MAC_VER_37:
3631 rtl8402_hw_phy_config(tp);
3632 break;
3633
b3d7b2f2
HW		 3634 case RTL_GIGA_MAC_VER_38:
3635 rtl8411_hw_phy_config(tp);
3636 break;
3637
5598bfe5
HW		 3638 case RTL_GIGA_MAC_VER_39:
3639 rtl8106e_hw_phy_config(tp);
3640 break;
3641
c558386b
HW		 3642 case RTL_GIGA_MAC_VER_40:
3643 rtl8168g_1_hw_phy_config(tp);
3644 break;
3645
3646 case RTL_GIGA_MAC_VER_41:
5615d9f1
FR		 3647 default:
3648 break;
3649 }
3650}
3651
da78dbff 3652static void rtl_phy_work(struct rtl8169_private *tp)
1da177e4 3653{
1da177e4
LT		 3654 struct timer_list *timer = &tp->timer;
3655 void __iomem *ioaddr = tp->mmio_addr;
3656 unsigned long timeout = RTL8169_PHY_TIMEOUT;
3657
bcf0bf90 3658 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 3659
4da19633 3660 if (tp->phy_reset_pending(tp)) {
5b0384f4 3661 /*
1da177e4
LT		 3662 * A busy loop could burn quite a few cycles on nowadays CPU.
3663 * Let's delay the execution of the timer for a few ticks.
3664 */
3665 timeout = HZ/10;
3666 goto out_mod_timer;
3667 }
3668
3669 if (tp->link_ok(ioaddr))
da78dbff 3670 return;
1da177e4 3671
da78dbff 3672 netif_warn(tp, link, tp->dev, "PHY reset until link up\n");
1da177e4 3673
4da19633 3674 tp->phy_reset_enable(tp);
1da177e4
LT		 3675
3676out_mod_timer:
3677 mod_timer(timer, jiffies + timeout);
da78dbff
FR		 3678}
3679
3680static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3681{
da78dbff
FR		 3682 if (!test_and_set_bit(flag, tp->wk.flags))
3683 schedule_work(&tp->wk.work);
da78dbff
FR		 3684}
3685
3686static void rtl8169_phy_timer(unsigned long __opaque)
3687{
3688 struct net_device *dev = (struct net_device *)__opaque;
3689 struct rtl8169_private *tp = netdev_priv(dev);
3690
98ddf986 3691 rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
1da177e4
LT		 3692}
3693
1da177e4
LT		 3694static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3695 void __iomem *ioaddr)
3696{
3697 iounmap(ioaddr);
3698 pci_release_regions(pdev);
87aeec76 3699 pci_clear_mwi(pdev);
1da177e4
LT		 3700 pci_disable_device(pdev);
3701 free_netdev(dev);
3702}
3703
ffc46952
FR		 3704DECLARE_RTL_COND(rtl_phy_reset_cond)
3705{
3706 return tp->phy_reset_pending(tp);
3707}
3708
bf793295
FR		 3709static void rtl8169_phy_reset(struct net_device *dev,
3710 struct rtl8169_private *tp)
3711{
4da19633 3712 tp->phy_reset_enable(tp);
ffc46952 3713 rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100);
bf793295
FR		 3714}
3715
2544bfc0
FR		 3716static bool rtl_tbi_enabled(struct rtl8169_private *tp)
3717{
3718 void __iomem *ioaddr = tp->mmio_addr;
3719
3720 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
3721 (RTL_R8(PHYstatus) & TBI_Enable);
3722}
3723
4ff96fa6
FR		 3724static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3725{
3726 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 3727
5615d9f1 3728 rtl_hw_phy_config(dev);
4ff96fa6 3729
77332894
MS		 3730 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3731 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3732 RTL_W8(0x82, 0x01);
3733 }
4ff96fa6 3734
6dccd16b
FR		 3735 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3736
3737 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3738 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 3739
bcf0bf90 3740 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 3741 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3742 RTL_W8(0x82, 0x01);
3743 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4da19633 3744 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4ff96fa6
FR		 3745 }
3746
bf793295
FR		 3747 rtl8169_phy_reset(dev, tp);
3748
54405cde 3749 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
cecb5fd7
FR		 3750 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3751 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3752 (tp->mii.supports_gmii ?
3753 ADVERTISED_1000baseT_Half |
3754 ADVERTISED_1000baseT_Full : 0));
4ff96fa6 3755
2544bfc0 3756 if (rtl_tbi_enabled(tp))
bf82c189 3757 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4ff96fa6
FR		 3758}
3759
773d2021
FR		 3760static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3761{
3762 void __iomem *ioaddr = tp->mmio_addr;
773d2021 3763
da78dbff 3764 rtl_lock_work(tp);
773d2021
FR		 3765
3766 RTL_W8(Cfg9346, Cfg9346_Unlock);
908ba2bf 3767
9ecb9aab 3768 RTL_W32(MAC4, addr[4] | addr[5] << 8);
908ba2bf 3769 RTL_R32(MAC4);
3770
9ecb9aab 3771 RTL_W32(MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
908ba2bf 3772 RTL_R32(MAC0);
3773
9ecb9aab 3774 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
3775 rtl_rar_exgmac_set(tp, addr);
c28aa385 3776
773d2021
FR		 3777 RTL_W8(Cfg9346, Cfg9346_Lock);
3778
da78dbff 3779 rtl_unlock_work(tp);
773d2021
FR		 3780}
3781
3782static int rtl_set_mac_address(struct net_device *dev, void *p)
3783{
3784 struct rtl8169_private *tp = netdev_priv(dev);
3785 struct sockaddr *addr = p;
3786
3787 if (!is_valid_ether_addr(addr->sa_data))
3788 return -EADDRNOTAVAIL;
3789
3790 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3791
3792 rtl_rar_set(tp, dev->dev_addr);
3793
3794 return 0;
3795}
3796
5f787a1a
FR		 3797static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3798{
3799 struct rtl8169_private *tp = netdev_priv(dev);
3800 struct mii_ioctl_data *data = if_mii(ifr);
3801
8b4ab28d
FR		 3802 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
3803}
5f787a1a 3804
cecb5fd7
FR		 3805static int rtl_xmii_ioctl(struct rtl8169_private *tp,
3806 struct mii_ioctl_data *data, int cmd)
8b4ab28d 3807{
5f787a1a
FR		 3808 switch (cmd) {
3809 case SIOCGMIIPHY:
3810 data->phy_id = 32; /* Internal PHY */
3811 return 0;
3812
3813 case SIOCGMIIREG:
4da19633 3814 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
5f787a1a
FR		 3815 return 0;
3816
3817 case SIOCSMIIREG:
4da19633 3818 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
5f787a1a
FR		 3819 return 0;
3820 }
3821 return -EOPNOTSUPP;
3822}
3823
8b4ab28d
FR		 3824static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3825{
3826 return -EOPNOTSUPP;
3827}
3828
fbac58fc
FR		 3829static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3830{
3831 if (tp->features & RTL_FEATURE_MSI) {
3832 pci_disable_msi(pdev);
3833 tp->features &= ~RTL_FEATURE_MSI;
3834 }
3835}
3836
baf63293 3837static void rtl_init_mdio_ops(struct rtl8169_private *tp)
c0e45c1c 3838{
3839 struct mdio_ops *ops = &tp->mdio_ops;
3840
3841 switch (tp->mac_version) {
3842 case RTL_GIGA_MAC_VER_27:
3843 ops->write = r8168dp_1_mdio_write;
3844 ops->read = r8168dp_1_mdio_read;
3845 break;
e6de30d6 3846 case RTL_GIGA_MAC_VER_28:
4804b3b3 3847 case RTL_GIGA_MAC_VER_31:
e6de30d6 3848 ops->write = r8168dp_2_mdio_write;
3849 ops->read = r8168dp_2_mdio_read;
3850 break;
c558386b
HW		 3851 case RTL_GIGA_MAC_VER_40:
3852 case RTL_GIGA_MAC_VER_41:
3853 ops->write = r8168g_mdio_write;
3854 ops->read = r8168g_mdio_read;
3855 break;
c0e45c1c 3856 default:
3857 ops->write = r8169_mdio_write;
3858 ops->read = r8169_mdio_read;
3859 break;
3860 }
3861}
3862
649b3b8c 3863static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3864{
3865 void __iomem *ioaddr = tp->mmio_addr;
3866
3867 switch (tp->mac_version) {
b00e69de
CB		 3868 case RTL_GIGA_MAC_VER_25:
3869 case RTL_GIGA_MAC_VER_26:
649b3b8c 3870 case RTL_GIGA_MAC_VER_29:
3871 case RTL_GIGA_MAC_VER_30:
3872 case RTL_GIGA_MAC_VER_32:
3873 case RTL_GIGA_MAC_VER_33:
3874 case RTL_GIGA_MAC_VER_34:
7e18dca1 3875 case RTL_GIGA_MAC_VER_37:
b3d7b2f2 3876 case RTL_GIGA_MAC_VER_38:
5598bfe5 3877 case RTL_GIGA_MAC_VER_39:
c558386b
HW		 3878 case RTL_GIGA_MAC_VER_40:
3879 case RTL_GIGA_MAC_VER_41:
649b3b8c 3880 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3881 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3882 break;
3883 default:
3884 break;
3885 }
3886}
3887
3888static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
3889{
3890 if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
3891 return false;
3892
3893 rtl_writephy(tp, 0x1f, 0x0000);
3894 rtl_writephy(tp, MII_BMCR, 0x0000);
3895
3896 rtl_wol_suspend_quirk(tp);
3897
3898 return true;
3899}
3900
065c27c1 3901static void r810x_phy_power_down(struct rtl8169_private *tp)
3902{
3903 rtl_writephy(tp, 0x1f, 0x0000);
3904 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3905}
3906
3907static void r810x_phy_power_up(struct rtl8169_private *tp)
3908{
3909 rtl_writephy(tp, 0x1f, 0x0000);
3910 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3911}
3912
3913static void r810x_pll_power_down(struct rtl8169_private *tp)
3914{
0004299a
HW		 3915 void __iomem *ioaddr = tp->mmio_addr;
3916
649b3b8c 3917 if (rtl_wol_pll_power_down(tp))
065c27c1 3918 return;
065c27c1 3919
3920 r810x_phy_power_down(tp);
0004299a
HW		 3921
3922 switch (tp->mac_version) {
3923 case RTL_GIGA_MAC_VER_07:
3924 case RTL_GIGA_MAC_VER_08:
3925 case RTL_GIGA_MAC_VER_09:
3926 case RTL_GIGA_MAC_VER_10:
3927 case RTL_GIGA_MAC_VER_13:
3928 case RTL_GIGA_MAC_VER_16:
3929 break;
3930 default:
3931 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3932 break;
3933 }
065c27c1 3934}
3935
3936static void r810x_pll_power_up(struct rtl8169_private *tp)
3937{
0004299a
HW		 3938 void __iomem *ioaddr = tp->mmio_addr;
3939
065c27c1 3940 r810x_phy_power_up(tp);
0004299a
HW		 3941
3942 switch (tp->mac_version) {
3943 case RTL_GIGA_MAC_VER_07:
3944 case RTL_GIGA_MAC_VER_08:
3945 case RTL_GIGA_MAC_VER_09:
3946 case RTL_GIGA_MAC_VER_10:
3947 case RTL_GIGA_MAC_VER_13:
3948 case RTL_GIGA_MAC_VER_16:
3949 break;
3950 default:
3951 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3952 break;
3953 }
065c27c1 3954}
3955
3956static void r8168_phy_power_up(struct rtl8169_private *tp)
3957{
3958 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3959 switch (tp->mac_version) {
3960 case RTL_GIGA_MAC_VER_11:
3961 case RTL_GIGA_MAC_VER_12:
3962 case RTL_GIGA_MAC_VER_17:
3963 case RTL_GIGA_MAC_VER_18:
3964 case RTL_GIGA_MAC_VER_19:
3965 case RTL_GIGA_MAC_VER_20:
3966 case RTL_GIGA_MAC_VER_21:
3967 case RTL_GIGA_MAC_VER_22:
3968 case RTL_GIGA_MAC_VER_23:
3969 case RTL_GIGA_MAC_VER_24:
3970 case RTL_GIGA_MAC_VER_25:
3971 case RTL_GIGA_MAC_VER_26:
3972 case RTL_GIGA_MAC_VER_27:
3973 case RTL_GIGA_MAC_VER_28:
3974 case RTL_GIGA_MAC_VER_31:
3975 rtl_writephy(tp, 0x0e, 0x0000);
3976 break;
3977 default:
3978 break;
3979 }
065c27c1 3980 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3981}
3982
3983static void r8168_phy_power_down(struct rtl8169_private *tp)
3984{
3985 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3986 switch (tp->mac_version) {
3987 case RTL_GIGA_MAC_VER_32:
3988 case RTL_GIGA_MAC_VER_33:
3989 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3990 break;
3991
3992 case RTL_GIGA_MAC_VER_11:
3993 case RTL_GIGA_MAC_VER_12:
3994 case RTL_GIGA_MAC_VER_17:
3995 case RTL_GIGA_MAC_VER_18:
3996 case RTL_GIGA_MAC_VER_19:
3997 case RTL_GIGA_MAC_VER_20:
3998 case RTL_GIGA_MAC_VER_21:
3999 case RTL_GIGA_MAC_VER_22:
4000 case RTL_GIGA_MAC_VER_23:
4001 case RTL_GIGA_MAC_VER_24:
4002 case RTL_GIGA_MAC_VER_25:
4003 case RTL_GIGA_MAC_VER_26:
4004 case RTL_GIGA_MAC_VER_27:
4005 case RTL_GIGA_MAC_VER_28:
4006 case RTL_GIGA_MAC_VER_31:
4007 rtl_writephy(tp, 0x0e, 0x0200);
4008 default:
4009 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4010 break;
4011 }
065c27c1 4012}
4013
4014static void r8168_pll_power_down(struct rtl8169_private *tp)
4015{
4016 void __iomem *ioaddr = tp->mmio_addr;
4017
cecb5fd7
FR		 4018 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4019 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4020 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
4804b3b3 4021 r8168dp_check_dash(tp)) {
065c27c1 4022 return;
5d2e1957 4023 }
065c27c1 4024
cecb5fd7
FR		 4025 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
4026 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
065c27c1 4027 (RTL_R16(CPlusCmd) & ASF)) {
4028 return;
4029 }
4030
01dc7fec 4031 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4032 tp->mac_version == RTL_GIGA_MAC_VER_33)
fdf6fc06 4033 rtl_ephy_write(tp, 0x19, 0xff64);
01dc7fec 4034
649b3b8c 4035 if (rtl_wol_pll_power_down(tp))
065c27c1 4036 return;
065c27c1 4037
4038 r8168_phy_power_down(tp);
4039
4040 switch (tp->mac_version) {
4041 case RTL_GIGA_MAC_VER_25:
4042 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 4043 case RTL_GIGA_MAC_VER_27:
4044 case RTL_GIGA_MAC_VER_28:
4804b3b3 4045 case RTL_GIGA_MAC_VER_31:
01dc7fec 4046 case RTL_GIGA_MAC_VER_32:
4047 case RTL_GIGA_MAC_VER_33:
065c27c1 4048 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4049 break;
4050 }
4051}
4052
4053static void r8168_pll_power_up(struct rtl8169_private *tp)
4054{
4055 void __iomem *ioaddr = tp->mmio_addr;
4056
065c27c1 4057 switch (tp->mac_version) {
4058 case RTL_GIGA_MAC_VER_25:
4059 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 4060 case RTL_GIGA_MAC_VER_27:
4061 case RTL_GIGA_MAC_VER_28:
4804b3b3 4062 case RTL_GIGA_MAC_VER_31:
01dc7fec 4063 case RTL_GIGA_MAC_VER_32:
4064 case RTL_GIGA_MAC_VER_33:
065c27c1 4065 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4066 break;
4067 }
4068
4069 r8168_phy_power_up(tp);
4070}
4071
d58d46b5
FR		 4072static void rtl_generic_op(struct rtl8169_private *tp,
4073 void (*op)(struct rtl8169_private *))
065c27c1 4074{
4075 if (op)
4076 op(tp);
4077}
4078
4079static void rtl_pll_power_down(struct rtl8169_private *tp)
4080{
d58d46b5 4081 rtl_generic_op(tp, tp->pll_power_ops.down);
065c27c1 4082}
4083
4084static void rtl_pll_power_up(struct rtl8169_private *tp)
4085{
d58d46b5 4086 rtl_generic_op(tp, tp->pll_power_ops.up);
065c27c1 4087}
4088
baf63293 4089static void rtl_init_pll_power_ops(struct rtl8169_private *tp)
065c27c1 4090{
4091 struct pll_power_ops *ops = &tp->pll_power_ops;
4092
4093 switch (tp->mac_version) {
4094 case RTL_GIGA_MAC_VER_07:
4095 case RTL_GIGA_MAC_VER_08:
4096 case RTL_GIGA_MAC_VER_09:
4097 case RTL_GIGA_MAC_VER_10:
4098 case RTL_GIGA_MAC_VER_16:
5a5e4443
HW		 4099 case RTL_GIGA_MAC_VER_29:
4100 case RTL_GIGA_MAC_VER_30:
7e18dca1 4101 case RTL_GIGA_MAC_VER_37:
5598bfe5 4102 case RTL_GIGA_MAC_VER_39:
065c27c1 4103 ops->down = r810x_pll_power_down;
4104 ops->up = r810x_pll_power_up;
4105 break;
4106
4107 case RTL_GIGA_MAC_VER_11:
4108 case RTL_GIGA_MAC_VER_12:
4109 case RTL_GIGA_MAC_VER_17:
4110 case RTL_GIGA_MAC_VER_18:
4111 case RTL_GIGA_MAC_VER_19:
4112 case RTL_GIGA_MAC_VER_20:
4113 case RTL_GIGA_MAC_VER_21:
4114 case RTL_GIGA_MAC_VER_22:
4115 case RTL_GIGA_MAC_VER_23:
4116 case RTL_GIGA_MAC_VER_24:
4117 case RTL_GIGA_MAC_VER_25:
4118 case RTL_GIGA_MAC_VER_26:
4119 case RTL_GIGA_MAC_VER_27:
e6de30d6 4120 case RTL_GIGA_MAC_VER_28:
4804b3b3 4121 case RTL_GIGA_MAC_VER_31:
01dc7fec 4122 case RTL_GIGA_MAC_VER_32:
4123 case RTL_GIGA_MAC_VER_33:
70090424 4124 case RTL_GIGA_MAC_VER_34:
c2218925
HW		 4125 case RTL_GIGA_MAC_VER_35:
4126 case RTL_GIGA_MAC_VER_36:
b3d7b2f2 4127 case RTL_GIGA_MAC_VER_38:
c558386b
HW		 4128 case RTL_GIGA_MAC_VER_40:
4129 case RTL_GIGA_MAC_VER_41:
065c27c1 4130 ops->down = r8168_pll_power_down;
4131 ops->up = r8168_pll_power_up;
4132 break;
4133
4134 default:
4135 ops->down = NULL;
4136 ops->up = NULL;
4137 break;
4138 }
4139}
4140
e542a226
HW		 4141static void rtl_init_rxcfg(struct rtl8169_private *tp)
4142{
4143 void __iomem *ioaddr = tp->mmio_addr;
4144
4145 switch (tp->mac_version) {
4146 case RTL_GIGA_MAC_VER_01:
4147 case RTL_GIGA_MAC_VER_02:
4148 case RTL_GIGA_MAC_VER_03:
4149 case RTL_GIGA_MAC_VER_04:
4150 case RTL_GIGA_MAC_VER_05:
4151 case RTL_GIGA_MAC_VER_06:
4152 case RTL_GIGA_MAC_VER_10:
4153 case RTL_GIGA_MAC_VER_11:
4154 case RTL_GIGA_MAC_VER_12:
4155 case RTL_GIGA_MAC_VER_13:
4156 case RTL_GIGA_MAC_VER_14:
4157 case RTL_GIGA_MAC_VER_15:
4158 case RTL_GIGA_MAC_VER_16:
4159 case RTL_GIGA_MAC_VER_17:
4160 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4161 break;
4162 case RTL_GIGA_MAC_VER_18:
4163 case RTL_GIGA_MAC_VER_19:
4164 case RTL_GIGA_MAC_VER_20:
4165 case RTL_GIGA_MAC_VER_21:
4166 case RTL_GIGA_MAC_VER_22:
4167 case RTL_GIGA_MAC_VER_23:
4168 case RTL_GIGA_MAC_VER_24:
eb2dc35d 4169 case RTL_GIGA_MAC_VER_34:
e542a226
HW		 4170 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4171 break;
4172 default:
4173 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
4174 break;
4175 }
4176}
4177
92fc43b4
HW		 4178static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4179{
4180 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
4181}
4182
d58d46b5
FR		 4183static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4184{
9c5028e9 4185 void __iomem *ioaddr = tp->mmio_addr;
4186
4187 RTL_W8(Cfg9346, Cfg9346_Unlock);
d58d46b5 4188 rtl_generic_op(tp, tp->jumbo_ops.enable);
9c5028e9 4189 RTL_W8(Cfg9346, Cfg9346_Lock);
d58d46b5
FR		 4190}
4191
4192static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4193{
9c5028e9 4194 void __iomem *ioaddr = tp->mmio_addr;
4195
4196 RTL_W8(Cfg9346, Cfg9346_Unlock);
d58d46b5 4197 rtl_generic_op(tp, tp->jumbo_ops.disable);
9c5028e9 4198 RTL_W8(Cfg9346, Cfg9346_Lock);
d58d46b5
FR		 4199}
4200
4201static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4202{
4203 void __iomem *ioaddr = tp->mmio_addr;
4204
4205 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4206 RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
4207 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
4208}
4209
4210static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4211{
4212 void __iomem *ioaddr = tp->mmio_addr;
4213
4214 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4215 RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
4216 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
4217}
4218
4219static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4220{
4221 void __iomem *ioaddr = tp->mmio_addr;
4222
4223 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4224}
4225
4226static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4227{
4228 void __iomem *ioaddr = tp->mmio_addr;
4229
4230 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4231}
4232
4233static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4234{
4235 void __iomem *ioaddr = tp->mmio_addr;
d58d46b5
FR		 4236
4237 RTL_W8(MaxTxPacketSize, 0x3f);
4238 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4239 RTL_W8(Config4, RTL_R8(Config4) | 0x01);
4512ff9f 4240 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
d58d46b5
FR		 4241}
4242
4243static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4244{
4245 void __iomem *ioaddr = tp->mmio_addr;
d58d46b5
FR		 4246
4247 RTL_W8(MaxTxPacketSize, 0x0c);
4248 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4249 RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
4512ff9f 4250 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
d58d46b5
FR		 4251}
4252
4253static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4254{
4255 rtl_tx_performance_tweak(tp->pci_dev,
4256 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4257}
4258
4259static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4260{
4261 rtl_tx_performance_tweak(tp->pci_dev,
4262 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4263}
4264
4265static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4266{
4267 void __iomem *ioaddr = tp->mmio_addr;
4268
4269 r8168b_0_hw_jumbo_enable(tp);
4270
4271 RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
4272}
4273
4274static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4275{
4276 void __iomem *ioaddr = tp->mmio_addr;
4277
4278 r8168b_0_hw_jumbo_disable(tp);
4279
4280 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4281}
4282
baf63293 4283static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
d58d46b5
FR		 4284{
4285 struct jumbo_ops *ops = &tp->jumbo_ops;
4286
4287 switch (tp->mac_version) {
4288 case RTL_GIGA_MAC_VER_11:
4289 ops->disable = r8168b_0_hw_jumbo_disable;
4290 ops->enable = r8168b_0_hw_jumbo_enable;
4291 break;
4292 case RTL_GIGA_MAC_VER_12:
4293 case RTL_GIGA_MAC_VER_17:
4294 ops->disable = r8168b_1_hw_jumbo_disable;
4295 ops->enable = r8168b_1_hw_jumbo_enable;
4296 break;
4297 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
4298 case RTL_GIGA_MAC_VER_19:
4299 case RTL_GIGA_MAC_VER_20:
4300 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
4301 case RTL_GIGA_MAC_VER_22:
4302 case RTL_GIGA_MAC_VER_23:
4303 case RTL_GIGA_MAC_VER_24:
4304 case RTL_GIGA_MAC_VER_25:
4305 case RTL_GIGA_MAC_VER_26:
4306 ops->disable = r8168c_hw_jumbo_disable;
4307 ops->enable = r8168c_hw_jumbo_enable;
4308 break;
4309 case RTL_GIGA_MAC_VER_27:
4310 case RTL_GIGA_MAC_VER_28:
4311 ops->disable = r8168dp_hw_jumbo_disable;
4312 ops->enable = r8168dp_hw_jumbo_enable;
4313 break;
4314 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
4315 case RTL_GIGA_MAC_VER_32:
4316 case RTL_GIGA_MAC_VER_33:
4317 case RTL_GIGA_MAC_VER_34:
4318 ops->disable = r8168e_hw_jumbo_disable;
4319 ops->enable = r8168e_hw_jumbo_enable;
4320 break;
4321
4322 /*
4323 * No action needed for jumbo frames with 8169.
4324 * No jumbo for 810x at all.
4325 */
c558386b
HW		 4326 case RTL_GIGA_MAC_VER_40:
4327 case RTL_GIGA_MAC_VER_41:
d58d46b5
FR		 4328 default:
4329 ops->disable = NULL;
4330 ops->enable = NULL;
4331 break;
4332 }
4333}
4334
ffc46952
FR		 4335DECLARE_RTL_COND(rtl_chipcmd_cond)
4336{
4337 void __iomem *ioaddr = tp->mmio_addr;
4338
4339 return RTL_R8(ChipCmd) & CmdReset;
4340}
4341
6f43adc8
FR		 4342static void rtl_hw_reset(struct rtl8169_private *tp)
4343{
4344 void __iomem *ioaddr = tp->mmio_addr;
6f43adc8 4345
6f43adc8
FR		 4346 RTL_W8(ChipCmd, CmdReset);
4347
ffc46952 4348 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
6f43adc8
FR		 4349}
4350
b6ffd97f 4351static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
953a12cc 4352{
b6ffd97f
FR		 4353 struct rtl_fw *rtl_fw;
4354 const char *name;
4355 int rc = -ENOMEM;
953a12cc 4356
b6ffd97f
FR		 4357 name = rtl_lookup_firmware_name(tp);
4358 if (!name)
4359 goto out_no_firmware;
953a12cc 4360
b6ffd97f
FR		 4361 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4362 if (!rtl_fw)
4363 goto err_warn;
31bd204f 4364
b6ffd97f
FR		 4365 rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
4366 if (rc < 0)
4367 goto err_free;
4368
fd112f2e
FR		 4369 rc = rtl_check_firmware(tp, rtl_fw);
4370 if (rc < 0)
4371 goto err_release_firmware;
4372
b6ffd97f
FR		 4373 tp->rtl_fw = rtl_fw;
4374out:
4375 return;
4376
fd112f2e
FR		 4377err_release_firmware:
4378 release_firmware(rtl_fw->fw);
b6ffd97f
FR		 4379err_free:
4380 kfree(rtl_fw);
4381err_warn:
4382 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4383 name, rc);
4384out_no_firmware:
4385 tp->rtl_fw = NULL;
4386 goto out;
4387}
4388
4389static void rtl_request_firmware(struct rtl8169_private *tp)
4390{
4391 if (IS_ERR(tp->rtl_fw))
4392 rtl_request_uncached_firmware(tp);
953a12cc
FR		 4393}
4394
92fc43b4
HW		 4395static void rtl_rx_close(struct rtl8169_private *tp)
4396{
4397 void __iomem *ioaddr = tp->mmio_addr;
92fc43b4 4398
1687b566 4399 RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
92fc43b4
HW		 4400}
4401
ffc46952
FR		 4402DECLARE_RTL_COND(rtl_npq_cond)
4403{
4404 void __iomem *ioaddr = tp->mmio_addr;
4405
4406 return RTL_R8(TxPoll) & NPQ;
4407}
4408
4409DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4410{
4411 void __iomem *ioaddr = tp->mmio_addr;
4412
4413 return RTL_R32(TxConfig) & TXCFG_EMPTY;
4414}
4415
e6de30d6 4416static void rtl8169_hw_reset(struct rtl8169_private *tp)
1da177e4 4417{
e6de30d6 4418 void __iomem *ioaddr = tp->mmio_addr;
4419
1da177e4 4420 /* Disable interrupts */
811fd301 4421 rtl8169_irq_mask_and_ack(tp);
1da177e4 4422
92fc43b4
HW		 4423 rtl_rx_close(tp);
4424
5d2e1957 4425 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4804b3b3 4426 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4427 tp->mac_version == RTL_GIGA_MAC_VER_31) {
ffc46952 4428 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
c2218925
HW		 4429 } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
4430 tp->mac_version == RTL_GIGA_MAC_VER_35 ||
7e18dca1 4431 tp->mac_version == RTL_GIGA_MAC_VER_36 ||
b3d7b2f2 4432 tp->mac_version == RTL_GIGA_MAC_VER_37 ||
c558386b
HW		 4433 tp->mac_version == RTL_GIGA_MAC_VER_40 ||
4434 tp->mac_version == RTL_GIGA_MAC_VER_41 ||
b3d7b2f2 4435 tp->mac_version == RTL_GIGA_MAC_VER_38) {
c2b0c1e7 4436 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
ffc46952 4437 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
92fc43b4
HW		 4438 } else {
4439 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4440 udelay(100);
e6de30d6 4441 }
4442
92fc43b4 4443 rtl_hw_reset(tp);
1da177e4
LT		 4444}
4445
7f796d83 4446static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 4447{
4448 void __iomem *ioaddr = tp->mmio_addr;
9cb427b6
FR		 4449
4450 /* Set DMA burst size and Interframe Gap Time */
4451 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4452 (InterFrameGap << TxInterFrameGapShift));
4453}
4454
07ce4064 4455static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 4456{
4457 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 4458
07ce4064
FR		 4459 tp->hw_start(dev);
4460
da78dbff 4461 rtl_irq_enable_all(tp);
07ce4064
FR		 4462}
4463
7f796d83
FR		 4464static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
4465 void __iomem *ioaddr)
4466{
4467 /*
4468 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4469 * register to be written before TxDescAddrLow to work.
4470 * Switching from MMIO to I/O access fixes the issue as well.
4471 */
4472 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
284901a9 4473 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
7f796d83 4474 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
284901a9 4475 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 4476}
4477
4478static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4479{
4480 u16 cmd;
4481
4482 cmd = RTL_R16(CPlusCmd);
4483 RTL_W16(CPlusCmd, cmd);
4484 return cmd;
4485}
4486
fdd7b4c3 4487static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
7f796d83
FR		 4488{
4489 /* Low hurts. Let's disable the filtering. */
207d6e87 4490 RTL_W16(RxMaxSize, rx_buf_sz + 1);
7f796d83
FR		 4491}
4492
6dccd16b
FR		 4493static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4494{
3744100e 4495 static const struct rtl_cfg2_info {
6dccd16b
FR		 4496 u32 mac_version;
4497 u32 clk;
4498 u32 val;
4499 } cfg2_info [] = {
4500 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4501 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4502 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4503 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3744100e
FR		 4504 };
4505 const struct rtl_cfg2_info *p = cfg2_info;
6dccd16b
FR		 4506 unsigned int i;
4507 u32 clk;
4508
4509 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 4510 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 4511 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4512 RTL_W32(0x7c, p->val);
4513 break;
4514 }
4515 }
4516}
4517
e6b763ea
FR		 4518static void rtl_set_rx_mode(struct net_device *dev)
4519{
4520 struct rtl8169_private *tp = netdev_priv(dev);
4521 void __iomem *ioaddr = tp->mmio_addr;
4522 u32 mc_filter[2]; /* Multicast hash filter */
4523 int rx_mode;
4524 u32 tmp = 0;
4525
4526 if (dev->flags & IFF_PROMISC) {
4527 /* Unconditionally log net taps. */
4528 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4529 rx_mode =
4530 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4531 AcceptAllPhys;
4532 mc_filter[1] = mc_filter[0] = 0xffffffff;
4533 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4534 (dev->flags & IFF_ALLMULTI)) {
4535 /* Too many to filter perfectly -- accept all multicasts. */
4536 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4537 mc_filter[1] = mc_filter[0] = 0xffffffff;
4538 } else {
4539 struct netdev_hw_addr *ha;
4540
4541 rx_mode = AcceptBroadcast | AcceptMyPhys;
4542 mc_filter[1] = mc_filter[0] = 0;
4543 netdev_for_each_mc_addr(ha, dev) {
4544 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4545 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4546 rx_mode |= AcceptMulticast;
4547 }
4548 }
4549
4550 if (dev->features & NETIF_F_RXALL)
4551 rx_mode |= (AcceptErr | AcceptRunt);
4552
4553 tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4554
4555 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4556 u32 data = mc_filter[0];
4557
4558 mc_filter[0] = swab32(mc_filter[1]);
4559 mc_filter[1] = swab32(data);
4560 }
4561
0481776b
NW		 4562 if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4563 mc_filter[1] = mc_filter[0] = 0xffffffff;
4564
e6b763ea
FR		 4565 RTL_W32(MAR0 + 4, mc_filter[1]);
4566 RTL_W32(MAR0 + 0, mc_filter[0]);
4567
4568 RTL_W32(RxConfig, tmp);
4569}
4570
07ce4064
FR		 4571static void rtl_hw_start_8169(struct net_device *dev)
4572{
4573 struct rtl8169_private *tp = netdev_priv(dev);
4574 void __iomem *ioaddr = tp->mmio_addr;
4575 struct pci_dev *pdev = tp->pci_dev;
07ce4064 4576
9cb427b6
FR		 4577 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4578 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4579 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4580 }
4581
1da177e4 4582 RTL_W8(Cfg9346, Cfg9346_Unlock);
cecb5fd7
FR		 4583 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4584 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4585 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4586 tp->mac_version == RTL_GIGA_MAC_VER_04)
9cb427b6
FR		 4587 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4588
e542a226
HW		 4589 rtl_init_rxcfg(tp);
4590
f0298f81 4591 RTL_W8(EarlyTxThres, NoEarlyTx);
1da177e4 4592
6f0333b8 4593 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
1da177e4 4594
cecb5fd7
FR		 4595 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4596 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4597 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4598 tp->mac_version == RTL_GIGA_MAC_VER_04)
c946b304 4599 rtl_set_rx_tx_config_registers(tp);
1da177e4 4600
7f796d83 4601 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 4602
cecb5fd7
FR		 4603 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4604 tp->mac_version == RTL_GIGA_MAC_VER_03) {
06fa7358 4605 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1da177e4 4606 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 4607 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 4608 }
4609
bcf0bf90
FR		 4610 RTL_W16(CPlusCmd, tp->cp_cmd);
4611
6dccd16b
FR		 4612 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4613
1da177e4
LT		 4614 /*
4615 * Undocumented corner. Supposedly:
4616 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4617 */
4618 RTL_W16(IntrMitigate, 0x0000);
4619
7f796d83 4620 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 4621
cecb5fd7
FR		 4622 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4623 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4624 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
4625 tp->mac_version != RTL_GIGA_MAC_VER_04) {
c946b304
FR		 4626 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4627 rtl_set_rx_tx_config_registers(tp);
4628 }
4629
1da177e4 4630 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 4631
4632 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4633 RTL_R8(IntrMask);
1da177e4
LT		 4634
4635 RTL_W32(RxMissed, 0);
4636
07ce4064 4637 rtl_set_rx_mode(dev);
1da177e4
LT		 4638
4639 /* no early-rx interrupts */
4640 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
07ce4064 4641}
1da177e4 4642
beb1fe18
HW		 4643static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4644{
4645 if (tp->csi_ops.write)
52989f0e 4646 tp->csi_ops.write(tp, addr, value);
beb1fe18
HW		 4647}
4648
4649static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4650{
52989f0e 4651 return tp->csi_ops.read ? tp->csi_ops.read(tp, addr) : ~0;
beb1fe18
HW		 4652}
4653
4654static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits)
dacf8154
FR		 4655{
4656 u32 csi;
4657
beb1fe18
HW		 4658 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4659 rtl_csi_write(tp, 0x070c, csi | bits);
4660}
4661
4662static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
4663{
4664 rtl_csi_access_enable(tp, 0x17000000);
650e8d5d 4665}
4666
beb1fe18 4667static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
e6de30d6 4668{
beb1fe18 4669 rtl_csi_access_enable(tp, 0x27000000);
e6de30d6 4670}
4671
ffc46952
FR		 4672DECLARE_RTL_COND(rtl_csiar_cond)
4673{
4674 void __iomem *ioaddr = tp->mmio_addr;
4675
4676 return RTL_R32(CSIAR) & CSIAR_FLAG;
4677}
4678
52989f0e 4679static void r8169_csi_write(struct rtl8169_private *tp, int addr, int value)
650e8d5d 4680{
52989f0e 4681 void __iomem *ioaddr = tp->mmio_addr;
beb1fe18
HW		 4682
4683 RTL_W32(CSIDR, value);
4684 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4685 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4686
ffc46952 4687 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
beb1fe18
HW		 4688}
4689
52989f0e 4690static u32 r8169_csi_read(struct rtl8169_private *tp, int addr)
beb1fe18 4691{
52989f0e 4692 void __iomem *ioaddr = tp->mmio_addr;
beb1fe18
HW		 4693
4694 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
4695 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4696
ffc46952
FR		 4697 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4698 RTL_R32(CSIDR) : ~0;
beb1fe18
HW		 4699}
4700
52989f0e 4701static void r8402_csi_write(struct rtl8169_private *tp, int addr, int value)
7e18dca1 4702{
52989f0e 4703 void __iomem *ioaddr = tp->mmio_addr;
7e18dca1
HW		 4704
4705 RTL_W32(CSIDR, value);
4706 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4707 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
4708 CSIAR_FUNC_NIC);
4709
ffc46952 4710 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
7e18dca1
HW		 4711}
4712
52989f0e 4713static u32 r8402_csi_read(struct rtl8169_private *tp, int addr)
7e18dca1 4714{
52989f0e 4715 void __iomem *ioaddr = tp->mmio_addr;
7e18dca1
HW		 4716
4717 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
4718 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4719
ffc46952
FR		 4720 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4721 RTL_R32(CSIDR) : ~0;
7e18dca1
HW		 4722}
4723
baf63293 4724static void rtl_init_csi_ops(struct rtl8169_private *tp)
beb1fe18
HW		 4725{
4726 struct csi_ops *ops = &tp->csi_ops;
4727
4728 switch (tp->mac_version) {
4729 case RTL_GIGA_MAC_VER_01:
4730 case RTL_GIGA_MAC_VER_02:
4731 case RTL_GIGA_MAC_VER_03:
4732 case RTL_GIGA_MAC_VER_04:
4733 case RTL_GIGA_MAC_VER_05:
4734 case RTL_GIGA_MAC_VER_06:
4735 case RTL_GIGA_MAC_VER_10:
4736 case RTL_GIGA_MAC_VER_11:
4737 case RTL_GIGA_MAC_VER_12:
4738 case RTL_GIGA_MAC_VER_13:
4739 case RTL_GIGA_MAC_VER_14:
4740 case RTL_GIGA_MAC_VER_15:
4741 case RTL_GIGA_MAC_VER_16:
4742 case RTL_GIGA_MAC_VER_17:
4743 ops->write = NULL;
4744 ops->read = NULL;
4745 break;
4746
7e18dca1 4747 case RTL_GIGA_MAC_VER_37:
b3d7b2f2 4748 case RTL_GIGA_MAC_VER_38:
7e18dca1
HW		 4749 ops->write = r8402_csi_write;
4750 ops->read = r8402_csi_read;
4751 break;
4752
beb1fe18
HW		 4753 default:
4754 ops->write = r8169_csi_write;
4755 ops->read = r8169_csi_read;
4756 break;
4757 }
dacf8154
FR		 4758}
4759
4760struct ephy_info {
4761 unsigned int offset;
4762 u16 mask;
4763 u16 bits;
4764};
4765
fdf6fc06
FR		 4766static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
4767 int len)
dacf8154
FR		 4768{
4769 u16 w;
4770
4771 while (len-- > 0) {
fdf6fc06
FR		 4772 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4773 rtl_ephy_write(tp, e->offset, w);
dacf8154
FR		 4774 e++;
4775 }
4776}
4777
b726e493
FR		 4778static void rtl_disable_clock_request(struct pci_dev *pdev)
4779{
7d7903b2
JL		 4780 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
4781 PCI_EXP_LNKCTL_CLKREQ_EN);
b726e493
FR		 4782}
4783
e6de30d6 4784static void rtl_enable_clock_request(struct pci_dev *pdev)
4785{
7d7903b2
JL		 4786 pcie_capability_set_word(pdev, PCI_EXP_LNKCTL,
4787 PCI_EXP_LNKCTL_CLKREQ_EN);
e6de30d6 4788}
4789
b726e493
FR		 4790#define R8168_CPCMD_QUIRK_MASK (\
4791 EnableBist | \
4792 Mac_dbgo_oe | \
4793 Force_half_dup | \
4794 Force_rxflow_en | \
4795 Force_txflow_en | \
4796 Cxpl_dbg_sel | \
4797 ASF | \
4798 PktCntrDisable | \
4799 Mac_dbgo_sel)
4800
beb1fe18 4801static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
219a1e9d 4802{
beb1fe18
HW		 4803 void __iomem *ioaddr = tp->mmio_addr;
4804 struct pci_dev *pdev = tp->pci_dev;
4805
b726e493
FR		 4806 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4807
4808 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4809
2e68ae44
FR		 4810 rtl_tx_performance_tweak(pdev,
4811 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
219a1e9d
FR		 4812}
4813
beb1fe18 4814static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
219a1e9d 4815{
beb1fe18
HW		 4816 void __iomem *ioaddr = tp->mmio_addr;
4817
4818 rtl_hw_start_8168bb(tp);
b726e493 4819
f0298f81 4820 RTL_W8(MaxTxPacketSize, TxPacketMax);
b726e493
FR		 4821
4822 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
219a1e9d
FR		 4823}
4824
beb1fe18 4825static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
219a1e9d 4826{
beb1fe18
HW		 4827 void __iomem *ioaddr = tp->mmio_addr;
4828 struct pci_dev *pdev = tp->pci_dev;
4829
b726e493
FR		 4830 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4831
4832 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4833
219a1e9d 4834 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
b726e493
FR		 4835
4836 rtl_disable_clock_request(pdev);
4837
4838 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
219a1e9d
FR		 4839}
4840
beb1fe18 4841static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
219a1e9d 4842{
350f7596 4843 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 4844 { 0x01, 0, 0x0001 },
4845 { 0x02, 0x0800, 0x1000 },
4846 { 0x03, 0, 0x0042 },
4847 { 0x06, 0x0080, 0x0000 },
4848 { 0x07, 0, 0x2000 }
4849 };
4850
beb1fe18 4851 rtl_csi_access_enable_2(tp);
b726e493 4852
fdf6fc06 4853 rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
b726e493 4854
beb1fe18 4855 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 4856}
4857
beb1fe18 4858static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
ef3386f0 4859{
beb1fe18
HW		 4860 void __iomem *ioaddr = tp->mmio_addr;
4861 struct pci_dev *pdev = tp->pci_dev;
4862
4863 rtl_csi_access_enable_2(tp);
ef3386f0
FR		 4864
4865 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4866
4867 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4868
4869 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4870}
4871
beb1fe18 4872static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
7f3e3d3a 4873{
beb1fe18
HW		 4874 void __iomem *ioaddr = tp->mmio_addr;
4875 struct pci_dev *pdev = tp->pci_dev;
4876
4877 rtl_csi_access_enable_2(tp);
7f3e3d3a
FR		 4878
4879 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4880
4881 /* Magic. */
4882 RTL_W8(DBG_REG, 0x20);
4883
f0298f81 4884 RTL_W8(MaxTxPacketSize, TxPacketMax);
7f3e3d3a
FR		 4885
4886 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4887
4888 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4889}
4890
beb1fe18 4891static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
219a1e9d 4892{
beb1fe18 4893 void __iomem *ioaddr = tp->mmio_addr;
350f7596 4894 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 4895 { 0x02, 0x0800, 0x1000 },
4896 { 0x03, 0, 0x0002 },
4897 { 0x06, 0x0080, 0x0000 }
4898 };
4899
beb1fe18 4900 rtl_csi_access_enable_2(tp);
b726e493
FR		 4901
4902 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4903
fdf6fc06 4904 rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
b726e493 4905
beb1fe18 4906 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 4907}
4908
beb1fe18 4909static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
219a1e9d 4910{
350f7596 4911 static const struct ephy_info e_info_8168c_2[] = {
b726e493
FR		 4912 { 0x01, 0, 0x0001 },
4913 { 0x03, 0x0400, 0x0220 }
4914 };
4915
beb1fe18 4916 rtl_csi_access_enable_2(tp);
b726e493 4917
fdf6fc06 4918 rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
b726e493 4919
beb1fe18 4920 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 4921}
4922
beb1fe18 4923static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
197ff761 4924{
beb1fe18 4925 rtl_hw_start_8168c_2(tp);
197ff761
FR		 4926}
4927
beb1fe18 4928static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
6fb07058 4929{
beb1fe18 4930 rtl_csi_access_enable_2(tp);
6fb07058 4931
beb1fe18 4932 __rtl_hw_start_8168cp(tp);
6fb07058
FR		 4933}
4934
beb1fe18 4935static void rtl_hw_start_8168d(struct rtl8169_private *tp)
5b538df9 4936{
beb1fe18
HW		 4937 void __iomem *ioaddr = tp->mmio_addr;
4938 struct pci_dev *pdev = tp->pci_dev;
4939
4940 rtl_csi_access_enable_2(tp);
5b538df9
FR		 4941
4942 rtl_disable_clock_request(pdev);
4943
f0298f81 4944 RTL_W8(MaxTxPacketSize, TxPacketMax);
5b538df9
FR		 4945
4946 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4947
4948 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4949}
4950
beb1fe18 4951static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4804b3b3 4952{
beb1fe18
HW		 4953 void __iomem *ioaddr = tp->mmio_addr;
4954 struct pci_dev *pdev = tp->pci_dev;
4955
4956 rtl_csi_access_enable_1(tp);
4804b3b3 4957
4958 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4959
4960 RTL_W8(MaxTxPacketSize, TxPacketMax);
4961
4962 rtl_disable_clock_request(pdev);
4963}
4964
beb1fe18 4965static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
e6de30d6 4966{
beb1fe18
HW		 4967 void __iomem *ioaddr = tp->mmio_addr;
4968 struct pci_dev *pdev = tp->pci_dev;
e6de30d6 4969 static const struct ephy_info e_info_8168d_4[] = {
4970 { 0x0b, ~0, 0x48 },
4971 { 0x19, 0x20, 0x50 },
4972 { 0x0c, ~0, 0x20 }
4973 };
4974 int i;
4975
beb1fe18 4976 rtl_csi_access_enable_1(tp);
e6de30d6 4977
4978 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4979
4980 RTL_W8(MaxTxPacketSize, TxPacketMax);
4981
4982 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4983 const struct ephy_info *e = e_info_8168d_4 + i;
4984 u16 w;
4985
fdf6fc06
FR		 4986 w = rtl_ephy_read(tp, e->offset);
4987 rtl_ephy_write(tp, 0x03, (w & e->mask) | e->bits);
e6de30d6 4988 }
4989
4990 rtl_enable_clock_request(pdev);
4991}
4992
beb1fe18 4993static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
01dc7fec 4994{
beb1fe18
HW		 4995 void __iomem *ioaddr = tp->mmio_addr;
4996 struct pci_dev *pdev = tp->pci_dev;
70090424 4997 static const struct ephy_info e_info_8168e_1[] = {
01dc7fec 4998 { 0x00, 0x0200, 0x0100 },
4999 { 0x00, 0x0000, 0x0004 },
5000 { 0x06, 0x0002, 0x0001 },
5001 { 0x06, 0x0000, 0x0030 },
5002 { 0x07, 0x0000, 0x2000 },
5003 { 0x00, 0x0000, 0x0020 },
5004 { 0x03, 0x5800, 0x2000 },
5005 { 0x03, 0x0000, 0x0001 },
5006 { 0x01, 0x0800, 0x1000 },
5007 { 0x07, 0x0000, 0x4000 },
5008 { 0x1e, 0x0000, 0x2000 },
5009 { 0x19, 0xffff, 0xfe6c },
5010 { 0x0a, 0x0000, 0x0040 }
5011 };
5012
beb1fe18 5013 rtl_csi_access_enable_2(tp);
01dc7fec 5014
fdf6fc06 5015 rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
01dc7fec 5016
5017 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5018
5019 RTL_W8(MaxTxPacketSize, TxPacketMax);
5020
5021 rtl_disable_clock_request(pdev);
5022
5023 /* Reset tx FIFO pointer */
cecb5fd7
FR		 5024 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
5025 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
01dc7fec 5026
cecb5fd7 5027 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
01dc7fec 5028}
5029
beb1fe18 5030static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
70090424 5031{
beb1fe18
HW		 5032 void __iomem *ioaddr = tp->mmio_addr;
5033 struct pci_dev *pdev = tp->pci_dev;
70090424
HW		 5034 static const struct ephy_info e_info_8168e_2[] = {
5035 { 0x09, 0x0000, 0x0080 },
5036 { 0x19, 0x0000, 0x0224 }
5037 };
5038
beb1fe18 5039 rtl_csi_access_enable_1(tp);
70090424 5040
fdf6fc06 5041 rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
70090424
HW		 5042
5043 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5044
fdf6fc06
FR		 5045 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5046 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5047 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5048 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5049 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5050 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
5051 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5052 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
70090424 5053
3090bd9a 5054 RTL_W8(MaxTxPacketSize, EarlySize);
70090424 5055
70090424
HW		 5056 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5057 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5058
5059 /* Adjust EEE LED frequency */
5060 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5061
5062 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5063 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
d64ec841 5064 RTL_W8(Config5, (RTL_R8(Config5) & ~Spi_en) | ASPM_en);
5065 RTL_W8(Config2, RTL_R8(Config2) | ClkReqEn);
70090424
HW		 5066}
5067
5f886e08 5068static void rtl_hw_start_8168f(struct rtl8169_private *tp)
c2218925 5069{
beb1fe18
HW		 5070 void __iomem *ioaddr = tp->mmio_addr;
5071 struct pci_dev *pdev = tp->pci_dev;
c2218925 5072
5f886e08 5073 rtl_csi_access_enable_2(tp);
c2218925
HW		 5074
5075 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5076
fdf6fc06
FR		 5077 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5078 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5079 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5080 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5081 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5082 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5083 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5084 rtl_w1w0_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5085 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5086 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
c2218925
HW		 5087
5088 RTL_W8(MaxTxPacketSize, EarlySize);
5089
c2218925
HW		 5090 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5091 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
c2218925 5092 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
d64ec841 5093 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN | FORCE_CLK);
5094 RTL_W8(Config5, (RTL_R8(Config5) & ~Spi_en) | ASPM_en);
5095 RTL_W8(Config2, RTL_R8(Config2) | ClkReqEn);
c2218925
HW		 5096}
5097
5f886e08
HW		 5098static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5099{
5100 void __iomem *ioaddr = tp->mmio_addr;
5101 static const struct ephy_info e_info_8168f_1[] = {
5102 { 0x06, 0x00c0, 0x0020 },
5103 { 0x08, 0x0001, 0x0002 },
5104 { 0x09, 0x0000, 0x0080 },
5105 { 0x19, 0x0000, 0x0224 }
5106 };
5107
5108 rtl_hw_start_8168f(tp);
5109
fdf6fc06 5110 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5f886e08 5111
fdf6fc06 5112 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5f886e08
HW		 5113
5114 /* Adjust EEE LED frequency */
5115 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5116}
5117
b3d7b2f2
HW		 5118static void rtl_hw_start_8411(struct rtl8169_private *tp)
5119{
b3d7b2f2
HW		 5120 static const struct ephy_info e_info_8168f_1[] = {
5121 { 0x06, 0x00c0, 0x0020 },
5122 { 0x0f, 0xffff, 0x5200 },
5123 { 0x1e, 0x0000, 0x4000 },
5124 { 0x19, 0x0000, 0x0224 }
5125 };
5126
5127 rtl_hw_start_8168f(tp);
5128
fdf6fc06 5129 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
b3d7b2f2 5130
fdf6fc06 5131 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
b3d7b2f2
HW		 5132}
5133
c558386b
HW		 5134static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5135{
5136 void __iomem *ioaddr = tp->mmio_addr;
5137 struct pci_dev *pdev = tp->pci_dev;
5138
5139 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
5140 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5141 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5142 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5143
5144 rtl_csi_access_enable_1(tp);
5145
5146 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5147
5148 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5149 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5150
5151 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
d64ec841 5152 RTL_W32(MISC, (RTL_R32(MISC) | FORCE_CLK) & ~RXDV_GATED_EN);
c558386b 5153 RTL_W8(MaxTxPacketSize, EarlySize);
d64ec841 5154 RTL_W8(Config5, RTL_R8(Config5) | ASPM_en);
5155 RTL_W8(Config2, RTL_R8(Config2) | ClkReqEn);
c558386b
HW		 5156
5157 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5158 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5159
5160 /* Adjust EEE LED frequency */
5161 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5162
5163 rtl_w1w0_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x02, ERIAR_EXGMAC);
5164}
5165
07ce4064
FR		 5166static void rtl_hw_start_8168(struct net_device *dev)
5167{
2dd99530
FR		 5168 struct rtl8169_private *tp = netdev_priv(dev);
5169 void __iomem *ioaddr = tp->mmio_addr;
5170
5171 RTL_W8(Cfg9346, Cfg9346_Unlock);
5172
f0298f81 5173 RTL_W8(MaxTxPacketSize, TxPacketMax);
2dd99530 5174
6f0333b8 5175 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
2dd99530 5176
0e485150 5177 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 5178
5179 RTL_W16(CPlusCmd, tp->cp_cmd);
5180
0e485150 5181 RTL_W16(IntrMitigate, 0x5151);
2dd99530 5182
0e485150 5183 /* Work around for RxFIFO overflow. */
811fd301 5184 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
da78dbff
FR		 5185 tp->event_slow |= RxFIFOOver | PCSTimeout;
5186 tp->event_slow &= ~RxOverflow;
0e485150
FR		 5187 }
5188
5189 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530 5190
b8363901
FR		 5191 rtl_set_rx_mode(dev);
5192
5193 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
5194 (InterFrameGap << TxInterFrameGapShift));
2dd99530
FR		 5195
5196 RTL_R8(IntrMask);
5197
219a1e9d
FR		 5198 switch (tp->mac_version) {
5199 case RTL_GIGA_MAC_VER_11:
beb1fe18 5200 rtl_hw_start_8168bb(tp);
4804b3b3 5201 break;
219a1e9d
FR		 5202
5203 case RTL_GIGA_MAC_VER_12:
5204 case RTL_GIGA_MAC_VER_17:
beb1fe18 5205 rtl_hw_start_8168bef(tp);
4804b3b3 5206 break;
219a1e9d
FR		 5207
5208 case RTL_GIGA_MAC_VER_18:
beb1fe18 5209 rtl_hw_start_8168cp_1(tp);
4804b3b3 5210 break;
219a1e9d
FR		 5211
5212 case RTL_GIGA_MAC_VER_19:
beb1fe18 5213 rtl_hw_start_8168c_1(tp);
4804b3b3 5214 break;
219a1e9d
FR		 5215
5216 case RTL_GIGA_MAC_VER_20:
beb1fe18 5217 rtl_hw_start_8168c_2(tp);
4804b3b3 5218 break;
219a1e9d 5219
197ff761 5220 case RTL_GIGA_MAC_VER_21:
beb1fe18 5221 rtl_hw_start_8168c_3(tp);
4804b3b3 5222 break;
197ff761 5223
6fb07058 5224 case RTL_GIGA_MAC_VER_22:
beb1fe18 5225 rtl_hw_start_8168c_4(tp);
4804b3b3 5226 break;
6fb07058 5227
ef3386f0 5228 case RTL_GIGA_MAC_VER_23:
beb1fe18 5229 rtl_hw_start_8168cp_2(tp);
4804b3b3 5230 break;
ef3386f0 5231
7f3e3d3a 5232 case RTL_GIGA_MAC_VER_24:
beb1fe18 5233 rtl_hw_start_8168cp_3(tp);
4804b3b3 5234 break;
7f3e3d3a 5235
5b538df9 5236 case RTL_GIGA_MAC_VER_25:
daf9df6d 5237 case RTL_GIGA_MAC_VER_26:
5238 case RTL_GIGA_MAC_VER_27:
beb1fe18 5239 rtl_hw_start_8168d(tp);
4804b3b3 5240 break;
5b538df9 5241
e6de30d6 5242 case RTL_GIGA_MAC_VER_28:
beb1fe18 5243 rtl_hw_start_8168d_4(tp);
4804b3b3 5244 break;
cecb5fd7 5245
4804b3b3 5246 case RTL_GIGA_MAC_VER_31:
beb1fe18 5247 rtl_hw_start_8168dp(tp);
4804b3b3 5248 break;
5249
01dc7fec 5250 case RTL_GIGA_MAC_VER_32:
5251 case RTL_GIGA_MAC_VER_33:
beb1fe18 5252 rtl_hw_start_8168e_1(tp);
70090424
HW		 5253 break;
5254 case RTL_GIGA_MAC_VER_34:
beb1fe18 5255 rtl_hw_start_8168e_2(tp);
01dc7fec 5256 break;
e6de30d6 5257
c2218925
HW		 5258 case RTL_GIGA_MAC_VER_35:
5259 case RTL_GIGA_MAC_VER_36:
beb1fe18 5260 rtl_hw_start_8168f_1(tp);
c2218925
HW		 5261 break;
5262
b3d7b2f2
HW		 5263 case RTL_GIGA_MAC_VER_38:
5264 rtl_hw_start_8411(tp);
5265 break;
5266
c558386b
HW		 5267 case RTL_GIGA_MAC_VER_40:
5268 case RTL_GIGA_MAC_VER_41:
5269 rtl_hw_start_8168g_1(tp);
5270 break;
5271
219a1e9d
FR		 5272 default:
5273 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
5274 dev->name, tp->mac_version);
4804b3b3 5275 break;
219a1e9d 5276 }
2dd99530 5277
0e485150
FR		 5278 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5279
b8363901
FR		 5280 RTL_W8(Cfg9346, Cfg9346_Lock);
5281
2dd99530 5282 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
07ce4064 5283}
1da177e4 5284
2857ffb7
FR		 5285#define R810X_CPCMD_QUIRK_MASK (\
5286 EnableBist | \
5287 Mac_dbgo_oe | \
5288 Force_half_dup | \
5edcc537 5289 Force_rxflow_en | \
2857ffb7
FR		 5290 Force_txflow_en | \
5291 Cxpl_dbg_sel | \
5292 ASF | \
5293 PktCntrDisable | \
d24e9aaf 5294 Mac_dbgo_sel)
2857ffb7 5295
beb1fe18 5296static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
2857ffb7 5297{
beb1fe18
HW		 5298 void __iomem *ioaddr = tp->mmio_addr;
5299 struct pci_dev *pdev = tp->pci_dev;
350f7596 5300 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 5301 { 0x01, 0, 0x6e65 },
5302 { 0x02, 0, 0x091f },
5303 { 0x03, 0, 0xc2f9 },
5304 { 0x06, 0, 0xafb5 },
5305 { 0x07, 0, 0x0e00 },
5306 { 0x19, 0, 0xec80 },
5307 { 0x01, 0, 0x2e65 },
5308 { 0x01, 0, 0x6e65 }
5309 };
5310 u8 cfg1;
5311
beb1fe18 5312 rtl_csi_access_enable_2(tp);
2857ffb7
FR		 5313
5314 RTL_W8(DBG_REG, FIX_NAK_1);
5315
5316 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5317
5318 RTL_W8(Config1,
5319 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5320 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5321
5322 cfg1 = RTL_R8(Config1);
5323 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5324 RTL_W8(Config1, cfg1 & ~LEDS0);
5325
fdf6fc06 5326 rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
2857ffb7
FR		 5327}
5328
beb1fe18 5329static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
2857ffb7 5330{
beb1fe18
HW		 5331 void __iomem *ioaddr = tp->mmio_addr;
5332 struct pci_dev *pdev = tp->pci_dev;
5333
5334 rtl_csi_access_enable_2(tp);
2857ffb7
FR		 5335
5336 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5337
5338 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
5339 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2857ffb7
FR		 5340}
5341
beb1fe18 5342static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
2857ffb7 5343{
beb1fe18 5344 rtl_hw_start_8102e_2(tp);
2857ffb7 5345
fdf6fc06 5346 rtl_ephy_write(tp, 0x03, 0xc2f9);
2857ffb7
FR		 5347}
5348
beb1fe18 5349static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5a5e4443 5350{
beb1fe18 5351 void __iomem *ioaddr = tp->mmio_addr;
5a5e4443
HW		 5352 static const struct ephy_info e_info_8105e_1[] = {
5353 { 0x07, 0, 0x4000 },
5354 { 0x19, 0, 0x0200 },
5355 { 0x19, 0, 0x0020 },
5356 { 0x1e, 0, 0x2000 },
5357 { 0x03, 0, 0x0001 },
5358 { 0x19, 0, 0x0100 },
5359 { 0x19, 0, 0x0004 },
5360 { 0x0a, 0, 0x0020 }
5361 };
5362
cecb5fd7 5363 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5a5e4443
HW		 5364 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5365
cecb5fd7 5366 /* Disable Early Tally Counter */
5a5e4443
HW		 5367 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
5368
5369 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4f6b00e5 5370 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
d64ec841 5371 RTL_W8(Config5, RTL_R8(Config5) | ASPM_en);
5372 RTL_W8(Config2, RTL_R8(Config2) | ClkReqEn);
5373 RTL_W32(MISC, RTL_R32(MISC) | FORCE_CLK);
5a5e4443 5374
fdf6fc06 5375 rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
5a5e4443
HW		 5376}
5377
beb1fe18 5378static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5a5e4443 5379{
beb1fe18 5380 rtl_hw_start_8105e_1(tp);
fdf6fc06 5381 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5a5e4443
HW		 5382}
5383
7e18dca1
HW		 5384static void rtl_hw_start_8402(struct rtl8169_private *tp)
5385{
5386 void __iomem *ioaddr = tp->mmio_addr;
5387 static const struct ephy_info e_info_8402[] = {
5388 { 0x19, 0xffff, 0xff64 },
5389 { 0x1e, 0, 0x4000 }
5390 };
5391
5392 rtl_csi_access_enable_2(tp);
5393
5394 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5395 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5396
5397 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5398 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
d64ec841 5399 RTL_W8(Config5, RTL_R8(Config5) | ASPM_en);
5400 RTL_W8(Config2, RTL_R8(Config2) | ClkReqEn);
5401 RTL_W32(MISC, RTL_R32(MISC) | FORCE_CLK);
7e18dca1 5402
fdf6fc06 5403 rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
7e18dca1
HW		 5404
5405 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
5406
fdf6fc06
FR		 5407 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
5408 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
5409 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5410 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5411 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5412 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5413 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
7e18dca1
HW		 5414}
5415
5598bfe5
HW		 5416static void rtl_hw_start_8106(struct rtl8169_private *tp)
5417{
5418 void __iomem *ioaddr = tp->mmio_addr;
5419
5420 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5421 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5422
d64ec841 5423 RTL_W32(MISC,
5424 (RTL_R32(MISC) | DISABLE_LAN_EN | FORCE_CLK) & ~EARLY_TALLY_EN);
5425 RTL_W8(Config5, RTL_R8(Config5) | ASPM_en);
5426 RTL_W8(Config2, RTL_R8(Config2) | ClkReqEn);
5598bfe5
HW		 5427 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
5428 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
5429}
5430
07ce4064
FR		 5431static void rtl_hw_start_8101(struct net_device *dev)
5432{
cdf1a608
FR		 5433 struct rtl8169_private *tp = netdev_priv(dev);
5434 void __iomem *ioaddr = tp->mmio_addr;
5435 struct pci_dev *pdev = tp->pci_dev;
5436
da78dbff
FR		 5437 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5438 tp->event_slow &= ~RxFIFOOver;
811fd301 5439
cecb5fd7 5440 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
7d7903b2 5441 tp->mac_version == RTL_GIGA_MAC_VER_16)
8200bc72
BH		 5442 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL,
5443 PCI_EXP_DEVCTL_NOSNOOP_EN);
cdf1a608 5444
d24e9aaf
HW		 5445 RTL_W8(Cfg9346, Cfg9346_Unlock);
5446
2857ffb7
FR		 5447 switch (tp->mac_version) {
5448 case RTL_GIGA_MAC_VER_07:
beb1fe18 5449 rtl_hw_start_8102e_1(tp);
2857ffb7
FR		 5450 break;
5451
5452 case RTL_GIGA_MAC_VER_08:
beb1fe18 5453 rtl_hw_start_8102e_3(tp);
2857ffb7
FR		 5454 break;
5455
5456 case RTL_GIGA_MAC_VER_09:
beb1fe18 5457 rtl_hw_start_8102e_2(tp);
2857ffb7 5458 break;
5a5e4443
HW		 5459
5460 case RTL_GIGA_MAC_VER_29:
beb1fe18 5461 rtl_hw_start_8105e_1(tp);
5a5e4443
HW		 5462 break;
5463 case RTL_GIGA_MAC_VER_30:
beb1fe18 5464 rtl_hw_start_8105e_2(tp);
5a5e4443 5465 break;
7e18dca1
HW		 5466
5467 case RTL_GIGA_MAC_VER_37:
5468 rtl_hw_start_8402(tp);
5469 break;
5598bfe5
HW		 5470
5471 case RTL_GIGA_MAC_VER_39:
5472 rtl_hw_start_8106(tp);
5473 break;
cdf1a608
FR		 5474 }
5475
d24e9aaf 5476 RTL_W8(Cfg9346, Cfg9346_Lock);
cdf1a608 5477
f0298f81 5478 RTL_W8(MaxTxPacketSize, TxPacketMax);
cdf1a608 5479
6f0333b8 5480 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
cdf1a608 5481
d24e9aaf 5482 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
cdf1a608
FR		 5483 RTL_W16(CPlusCmd, tp->cp_cmd);
5484
5485 RTL_W16(IntrMitigate, 0x0000);
5486
5487 rtl_set_rx_tx_desc_registers(tp, ioaddr);
5488
5489 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5490 rtl_set_rx_tx_config_registers(tp);
5491
cdf1a608
FR		 5492 RTL_R8(IntrMask);
5493
cdf1a608
FR		 5494 rtl_set_rx_mode(dev);
5495
5496 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
1da177e4
LT		 5497}
5498
5499static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5500{
d58d46b5
FR		 5501 struct rtl8169_private *tp = netdev_priv(dev);
5502
5503 if (new_mtu < ETH_ZLEN ||
5504 new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
1da177e4
LT		 5505 return -EINVAL;
5506
d58d46b5
FR		 5507 if (new_mtu > ETH_DATA_LEN)
5508 rtl_hw_jumbo_enable(tp);
5509 else
5510 rtl_hw_jumbo_disable(tp);
5511
1da177e4 5512 dev->mtu = new_mtu;
350fb32a
MM		 5513 netdev_update_features(dev);
5514
323bb685 5515 return 0;
1da177e4
LT		 5516}
5517
5518static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5519{
95e0918d 5520 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 5521 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5522}
5523
6f0333b8
ED		 5524static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5525 void **data_buff, struct RxDesc *desc)
1da177e4 5526{
48addcc9 5527 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
231aee63 5528 DMA_FROM_DEVICE);
48addcc9 5529
6f0333b8
ED		 5530 kfree(*data_buff);
5531 *data_buff = NULL;
1da177e4
LT		 5532 rtl8169_make_unusable_by_asic(desc);
5533}
5534
5535static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
5536{
5537 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5538
5539 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
5540}
5541
5542static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
5543 u32 rx_buf_sz)
5544{
5545 desc->addr = cpu_to_le64(mapping);
5546 wmb();
5547 rtl8169_mark_to_asic(desc, rx_buf_sz);
5548}
5549
6f0333b8
ED		 5550static inline void *rtl8169_align(void *data)
5551{
5552 return (void *)ALIGN((long)data, 16);
5553}
5554
0ecbe1ca
SG		 5555static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5556 struct RxDesc *desc)
1da177e4 5557{
6f0333b8 5558 void *data;
1da177e4 5559 dma_addr_t mapping;
48addcc9 5560 struct device *d = &tp->pci_dev->dev;
0ecbe1ca 5561 struct net_device *dev = tp->dev;
6f0333b8 5562 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
1da177e4 5563
6f0333b8
ED		 5564 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
5565 if (!data)
5566 return NULL;
e9f63f30 5567
6f0333b8
ED		 5568 if (rtl8169_align(data) != data) {
5569 kfree(data);
5570 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
5571 if (!data)
5572 return NULL;
5573 }
3eafe507 5574
48addcc9 5575 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
231aee63 5576 DMA_FROM_DEVICE);
d827d86b
SG		 5577 if (unlikely(dma_mapping_error(d, mapping))) {
5578 if (net_ratelimit())
5579 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
3eafe507 5580 goto err_out;
d827d86b 5581 }
1da177e4
LT		 5582
5583 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6f0333b8 5584 return data;
3eafe507
SG		 5585
5586err_out:
5587 kfree(data);
5588 return NULL;
1da177e4
LT		 5589}
5590
5591static void rtl8169_rx_clear(struct rtl8169_private *tp)
5592{
07d3f51f 5593 unsigned int i;
1da177e4
LT		 5594
5595 for (i = 0; i < NUM_RX_DESC; i++) {
6f0333b8
ED		 5596 if (tp->Rx_databuff[i]) {
5597 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
1da177e4
LT		 5598 tp->RxDescArray + i);
5599 }
5600 }
5601}
5602
0ecbe1ca 5603static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1da177e4 5604{
0ecbe1ca
SG		 5605 desc->opts1 |= cpu_to_le32(RingEnd);
5606}
5b0384f4 5607
0ecbe1ca
SG		 5608static int rtl8169_rx_fill(struct rtl8169_private *tp)
5609{
5610 unsigned int i;
1da177e4 5611
0ecbe1ca
SG		 5612 for (i = 0; i < NUM_RX_DESC; i++) {
5613 void *data;
4ae47c2d 5614
6f0333b8 5615 if (tp->Rx_databuff[i])
1da177e4 5616 continue;
bcf0bf90 5617
0ecbe1ca 5618 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6f0333b8
ED		 5619 if (!data) {
5620 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
0ecbe1ca 5621 goto err_out;
6f0333b8
ED		 5622 }
5623 tp->Rx_databuff[i] = data;
1da177e4 5624 }
1da177e4 5625
0ecbe1ca
SG		 5626 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5627 return 0;
5628
5629err_out:
5630 rtl8169_rx_clear(tp);
5631 return -ENOMEM;
1da177e4
LT		 5632}
5633
1da177e4
LT		 5634static int rtl8169_init_ring(struct net_device *dev)
5635{
5636 struct rtl8169_private *tp = netdev_priv(dev);
5637
5638 rtl8169_init_ring_indexes(tp);
5639
5640 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
6f0333b8 5641 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
1da177e4 5642
0ecbe1ca 5643 return rtl8169_rx_fill(tp);
1da177e4
LT		 5644}
5645
48addcc9 5646static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
1da177e4
LT		 5647 struct TxDesc *desc)
5648{
5649 unsigned int len = tx_skb->len;
5650
48addcc9
SG		 5651 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5652
1da177e4
LT		 5653 desc->opts1 = 0x00;
5654 desc->opts2 = 0x00;
5655 desc->addr = 0x00;
5656 tx_skb->len = 0;
5657}
5658
3eafe507
SG		 5659static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5660 unsigned int n)
1da177e4
LT		 5661{
5662 unsigned int i;
5663
3eafe507
SG		 5664 for (i = 0; i < n; i++) {
5665 unsigned int entry = (start + i) % NUM_TX_DESC;
1da177e4
LT		 5666 struct ring_info *tx_skb = tp->tx_skb + entry;
5667 unsigned int len = tx_skb->len;
5668
5669 if (len) {
5670 struct sk_buff *skb = tx_skb->skb;
5671
48addcc9 5672 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
1da177e4
LT		 5673 tp->TxDescArray + entry);
5674 if (skb) {
cac4b22f 5675 tp->dev->stats.tx_dropped++;
1da177e4
LT		 5676 dev_kfree_skb(skb);
5677 tx_skb->skb = NULL;
5678 }
1da177e4
LT		 5679 }
5680 }
3eafe507
SG		 5681}
5682
5683static void rtl8169_tx_clear(struct rtl8169_private *tp)
5684{
5685 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
1da177e4
LT		 5686 tp->cur_tx = tp->dirty_tx = 0;
5687}
5688
4422bcd4 5689static void rtl_reset_work(struct rtl8169_private *tp)
1da177e4 5690{
c4028958 5691 struct net_device *dev = tp->dev;
56de414c 5692 int i;
1da177e4 5693
da78dbff
FR		 5694 napi_disable(&tp->napi);
5695 netif_stop_queue(dev);
5696 synchronize_sched();
1da177e4 5697
c7c2c39b 5698 rtl8169_hw_reset(tp);
5699
56de414c
FR		 5700 for (i = 0; i < NUM_RX_DESC; i++)
5701 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
5702
1da177e4 5703 rtl8169_tx_clear(tp);
c7c2c39b 5704 rtl8169_init_ring_indexes(tp);
1da177e4 5705
da78dbff 5706 napi_enable(&tp->napi);
56de414c
FR		 5707 rtl_hw_start(dev);
5708 netif_wake_queue(dev);
5709 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1da177e4
LT		 5710}
5711
5712static void rtl8169_tx_timeout(struct net_device *dev)
5713{
da78dbff
FR		 5714 struct rtl8169_private *tp = netdev_priv(dev);
5715
5716 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 5717}
5718
5719static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2b7b4318 5720 u32 *opts)
1da177e4
LT		 5721{
5722 struct skb_shared_info *info = skb_shinfo(skb);
5723 unsigned int cur_frag, entry;
a6343afb 5724 struct TxDesc * uninitialized_var(txd);
48addcc9 5725 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 5726
5727 entry = tp->cur_tx;
5728 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
9e903e08 5729 const skb_frag_t *frag = info->frags + cur_frag;
1da177e4
LT		 5730 dma_addr_t mapping;
5731 u32 status, len;
5732 void *addr;
5733
5734 entry = (entry + 1) % NUM_TX_DESC;
5735
5736 txd = tp->TxDescArray + entry;
9e903e08 5737 len = skb_frag_size(frag);
929f6189 5738 addr = skb_frag_address(frag);
48addcc9 5739 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
d827d86b
SG		 5740 if (unlikely(dma_mapping_error(d, mapping))) {
5741 if (net_ratelimit())
5742 netif_err(tp, drv, tp->dev,
5743 "Failed to map TX fragments DMA!\n");
3eafe507 5744 goto err_out;
d827d86b 5745 }
1da177e4 5746
cecb5fd7 5747 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318
FR		 5748 status = opts[0] | len |
5749 (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 5750
5751 txd->opts1 = cpu_to_le32(status);
2b7b4318 5752 txd->opts2 = cpu_to_le32(opts[1]);
1da177e4
LT		 5753 txd->addr = cpu_to_le64(mapping);
5754
5755 tp->tx_skb[entry].len = len;
5756 }
5757
5758 if (cur_frag) {
5759 tp->tx_skb[entry].skb = skb;
5760 txd->opts1 |= cpu_to_le32(LastFrag);
5761 }
5762
5763 return cur_frag;
3eafe507
SG		 5764
5765err_out:
5766 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5767 return -EIO;
1da177e4
LT		 5768}
5769
2b7b4318
FR		 5770static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
5771 struct sk_buff *skb, u32 *opts)
1da177e4 5772{
2b7b4318 5773 const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
350fb32a 5774 u32 mss = skb_shinfo(skb)->gso_size;
2b7b4318 5775 int offset = info->opts_offset;
350fb32a 5776
2b7b4318
FR		 5777 if (mss) {
5778 opts[0] |= TD_LSO;
5779 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
5780 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 5781 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 5782
5783 if (ip->protocol == IPPROTO_TCP)
2b7b4318 5784 opts[offset] |= info->checksum.tcp;
1da177e4 5785 else if (ip->protocol == IPPROTO_UDP)
2b7b4318
FR		 5786 opts[offset] |= info->checksum.udp;
5787 else
5788 WARN_ON_ONCE(1);
1da177e4 5789 }
1da177e4
LT		 5790}
5791
61357325
SH		 5792static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5793 struct net_device *dev)
1da177e4
LT		 5794{
5795 struct rtl8169_private *tp = netdev_priv(dev);
3eafe507 5796 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
1da177e4
LT		 5797 struct TxDesc *txd = tp->TxDescArray + entry;
5798 void __iomem *ioaddr = tp->mmio_addr;
48addcc9 5799 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 5800 dma_addr_t mapping;
5801 u32 status, len;
2b7b4318 5802 u32 opts[2];
3eafe507 5803 int frags;
5b0384f4 5804
477206a0 5805 if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
bf82c189 5806 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
3eafe507 5807 goto err_stop_0;
1da177e4
LT		 5808 }
5809
5810 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3eafe507
SG		 5811 goto err_stop_0;
5812
5813 len = skb_headlen(skb);
48addcc9 5814 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
d827d86b
SG		 5815 if (unlikely(dma_mapping_error(d, mapping))) {
5816 if (net_ratelimit())
5817 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
3eafe507 5818 goto err_dma_0;
d827d86b 5819 }
3eafe507
SG		 5820
5821 tp->tx_skb[entry].len = len;
5822 txd->addr = cpu_to_le64(mapping);
1da177e4 5823
810f4893 5824 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
2b7b4318 5825 opts[0] = DescOwn;
1da177e4 5826
2b7b4318
FR		 5827 rtl8169_tso_csum(tp, skb, opts);
5828
5829 frags = rtl8169_xmit_frags(tp, skb, opts);
3eafe507
SG		 5830 if (frags < 0)
5831 goto err_dma_1;
5832 else if (frags)
2b7b4318 5833 opts[0] |= FirstFrag;
3eafe507 5834 else {
2b7b4318 5835 opts[0] |= FirstFrag | LastFrag;
1da177e4
LT		 5836 tp->tx_skb[entry].skb = skb;
5837 }
5838
2b7b4318
FR		 5839 txd->opts2 = cpu_to_le32(opts[1]);
5840
5047fb5d
RC		 5841 skb_tx_timestamp(skb);
5842
1da177e4
LT		 5843 wmb();
5844
cecb5fd7 5845 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318 5846 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 5847 txd->opts1 = cpu_to_le32(status);
5848
1da177e4
LT		 5849 tp->cur_tx += frags + 1;
5850
4c020a96 5851 wmb();
1da177e4 5852
cecb5fd7 5853 RTL_W8(TxPoll, NPQ);
1da177e4 5854
da78dbff
FR		 5855 mmiowb();
5856
477206a0 5857 if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
ae1f23fb
FR		 5858 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
5859 * not miss a ring update when it notices a stopped queue.
5860 */
5861 smp_wmb();
1da177e4 5862 netif_stop_queue(dev);
ae1f23fb
FR		 5863 /* Sync with rtl_tx:
5864 * - publish queue status and cur_tx ring index (write barrier)
5865 * - refresh dirty_tx ring index (read barrier).
5866 * May the current thread have a pessimistic view of the ring
5867 * status and forget to wake up queue, a racing rtl_tx thread
5868 * can't.
5869 */
1e874e04 5870 smp_mb();
477206a0 5871 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
1da177e4
LT		 5872 netif_wake_queue(dev);
5873 }
5874
61357325 5875 return NETDEV_TX_OK;
1da177e4 5876
3eafe507 5877err_dma_1:
48addcc9 5878 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
3eafe507
SG		 5879err_dma_0:
5880 dev_kfree_skb(skb);
5881 dev->stats.tx_dropped++;
5882 return NETDEV_TX_OK;
5883
5884err_stop_0:
1da177e4 5885 netif_stop_queue(dev);
cebf8cc7 5886 dev->stats.tx_dropped++;
61357325 5887 return NETDEV_TX_BUSY;
1da177e4
LT		 5888}
5889
5890static void rtl8169_pcierr_interrupt(struct net_device *dev)
5891{
5892 struct rtl8169_private *tp = netdev_priv(dev);
5893 struct pci_dev *pdev = tp->pci_dev;
1da177e4
LT		 5894 u16 pci_status, pci_cmd;
5895
5896 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5897 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5898
bf82c189
JP		 5899 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5900 pci_cmd, pci_status);
1da177e4
LT		 5901
5902 /*
5903 * The recovery sequence below admits a very elaborated explanation:
5904 * - it seems to work;
d03902b8
FR		 5905 * - I did not see what else could be done;
5906 * - it makes iop3xx happy.
1da177e4
LT		 5907 *
5908 * Feel free to adjust to your needs.
5909 */
a27993f3 5910 if (pdev->broken_parity_status)
d03902b8
FR		 5911 pci_cmd &= ~PCI_COMMAND_PARITY;
5912 else
5913 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5914
5915 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 5916
5917 pci_write_config_word(pdev, PCI_STATUS,
5918 pci_status & (PCI_STATUS_DETECTED_PARITY |
5919 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5920 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5921
5922 /* The infamous DAC f*ckup only happens at boot time */
5923 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
e6de30d6 5924 void __iomem *ioaddr = tp->mmio_addr;
5925
bf82c189 5926 netif_info(tp, intr, dev, "disabling PCI DAC\n");
1da177e4
LT		 5927 tp->cp_cmd &= ~PCIDAC;
5928 RTL_W16(CPlusCmd, tp->cp_cmd);
5929 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 5930 }
5931
e6de30d6 5932 rtl8169_hw_reset(tp);
d03902b8 5933
98ddf986 5934 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 5935}
5936
da78dbff 5937static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
1da177e4
LT		 5938{
5939 unsigned int dirty_tx, tx_left;
5940
1da177e4
LT		 5941 dirty_tx = tp->dirty_tx;
5942 smp_rmb();
5943 tx_left = tp->cur_tx - dirty_tx;
5944
5945 while (tx_left > 0) {
5946 unsigned int entry = dirty_tx % NUM_TX_DESC;
5947 struct ring_info *tx_skb = tp->tx_skb + entry;
1da177e4
LT		 5948 u32 status;
5949
5950 rmb();
5951 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5952 if (status & DescOwn)
5953 break;
5954
48addcc9
SG		 5955 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5956 tp->TxDescArray + entry);
1da177e4 5957 if (status & LastFrag) {
17bcb684
FR		 5958 u64_stats_update_begin(&tp->tx_stats.syncp);
5959 tp->tx_stats.packets++;
5960 tp->tx_stats.bytes += tx_skb->skb->len;
5961 u64_stats_update_end(&tp->tx_stats.syncp);
5962 dev_kfree_skb(tx_skb->skb);
1da177e4
LT		 5963 tx_skb->skb = NULL;
5964 }
5965 dirty_tx++;
5966 tx_left--;
5967 }
5968
5969 if (tp->dirty_tx != dirty_tx) {
5970 tp->dirty_tx = dirty_tx;
ae1f23fb
FR		 5971 /* Sync with rtl8169_start_xmit:
5972 * - publish dirty_tx ring index (write barrier)
5973 * - refresh cur_tx ring index and queue status (read barrier)
5974 * May the current thread miss the stopped queue condition,
5975 * a racing xmit thread can only have a right view of the
5976 * ring status.
5977 */
1e874e04 5978 smp_mb();
1da177e4 5979 if (netif_queue_stopped(dev) &&
477206a0 5980 TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
1da177e4
LT		 5981 netif_wake_queue(dev);
5982 }
d78ae2dc
FR		 5983 /*
5984 * 8168 hack: TxPoll requests are lost when the Tx packets are
5985 * too close. Let's kick an extra TxPoll request when a burst
5986 * of start_xmit activity is detected (if it is not detected,
5987 * it is slow enough). -- FR
5988 */
da78dbff
FR		 5989 if (tp->cur_tx != dirty_tx) {
5990 void __iomem *ioaddr = tp->mmio_addr;
5991
d78ae2dc 5992 RTL_W8(TxPoll, NPQ);
da78dbff 5993 }
1da177e4
LT		 5994 }
5995}
5996
126fa4b9
FR		 5997static inline int rtl8169_fragmented_frame(u32 status)
5998{
5999 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
6000}
6001
adea1ac7 6002static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
1da177e4 6003{
1da177e4
LT		 6004 u32 status = opts1 & RxProtoMask;
6005
6006 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
d5d3ebe3 6007 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
1da177e4
LT		 6008 skb->ip_summed = CHECKSUM_UNNECESSARY;
6009 else
bc8acf2c 6010 skb_checksum_none_assert(skb);
1da177e4
LT		 6011}
6012
6f0333b8
ED		 6013static struct sk_buff *rtl8169_try_rx_copy(void *data,
6014 struct rtl8169_private *tp,
6015 int pkt_size,
6016 dma_addr_t addr)
1da177e4 6017{
b449655f 6018 struct sk_buff *skb;
48addcc9 6019 struct device *d = &tp->pci_dev->dev;
b449655f 6020
6f0333b8 6021 data = rtl8169_align(data);
48addcc9 6022 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6f0333b8
ED		 6023 prefetch(data);
6024 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
6025 if (skb)
6026 memcpy(skb->data, data, pkt_size);
48addcc9
SG		 6027 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
6028
6f0333b8 6029 return skb;
1da177e4
LT		 6030}
6031
da78dbff 6032static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
1da177e4
LT		 6033{
6034 unsigned int cur_rx, rx_left;
6f0333b8 6035 unsigned int count;
1da177e4 6036
1da177e4
LT		 6037 cur_rx = tp->cur_rx;
6038 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
865c652d 6039 rx_left = min(rx_left, budget);
1da177e4 6040
4dcb7d33 6041 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 6042 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 6043 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 6044 u32 status;
6045
6046 rmb();
e03f33af 6047 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
1da177e4
LT		 6048
6049 if (status & DescOwn)
6050 break;
4dcb7d33 6051 if (unlikely(status & RxRES)) {
bf82c189
JP		 6052 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6053 status);
cebf8cc7 6054 dev->stats.rx_errors++;
1da177e4 6055 if (status & (RxRWT | RxRUNT))
cebf8cc7 6056 dev->stats.rx_length_errors++;
1da177e4 6057 if (status & RxCRC)
cebf8cc7 6058 dev->stats.rx_crc_errors++;
9dccf611 6059 if (status & RxFOVF) {
da78dbff 6060 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
cebf8cc7 6061 dev->stats.rx_fifo_errors++;
9dccf611 6062 }
6bbe021d
BG		 6063 if ((status & (RxRUNT | RxCRC)) &&
6064 !(status & (RxRWT | RxFOVF)) &&
6065 (dev->features & NETIF_F_RXALL))
6066 goto process_pkt;
6067
6f0333b8 6068 rtl8169_mark_to_asic(desc, rx_buf_sz);
1da177e4 6069 } else {
6f0333b8 6070 struct sk_buff *skb;
6bbe021d
BG		 6071 dma_addr_t addr;
6072 int pkt_size;
6073
6074process_pkt:
6075 addr = le64_to_cpu(desc->addr);
79d0c1d2
BG		 6076 if (likely(!(dev->features & NETIF_F_RXFCS)))
6077 pkt_size = (status & 0x00003fff) - 4;
6078 else
6079 pkt_size = status & 0x00003fff;
1da177e4 6080
126fa4b9
FR		 6081 /*
6082 * The driver does not support incoming fragmented
6083 * frames. They are seen as a symptom of over-mtu
6084 * sized frames.
6085 */
6086 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 6087 dev->stats.rx_dropped++;
6088 dev->stats.rx_length_errors++;
6f0333b8 6089 rtl8169_mark_to_asic(desc, rx_buf_sz);
4dcb7d33 6090 continue;
126fa4b9
FR		 6091 }
6092
6f0333b8
ED		 6093 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6094 tp, pkt_size, addr);
6095 rtl8169_mark_to_asic(desc, rx_buf_sz);
6096 if (!skb) {
6097 dev->stats.rx_dropped++;
6098 continue;
1da177e4
LT		 6099 }
6100
adea1ac7 6101 rtl8169_rx_csum(skb, status);
1da177e4
LT		 6102 skb_put(skb, pkt_size);
6103 skb->protocol = eth_type_trans(skb, dev);
6104
7a8fc77b
FR		 6105 rtl8169_rx_vlan_tag(desc, skb);
6106
56de414c 6107 napi_gro_receive(&tp->napi, skb);
1da177e4 6108
8027aa24
JW		 6109 u64_stats_update_begin(&tp->rx_stats.syncp);
6110 tp->rx_stats.packets++;
6111 tp->rx_stats.bytes += pkt_size;
6112 u64_stats_update_end(&tp->rx_stats.syncp);
1da177e4 6113 }
1da177e4
LT		 6114 }
6115
6116 count = cur_rx - tp->cur_rx;
6117 tp->cur_rx = cur_rx;
6118
6f0333b8 6119 tp->dirty_rx += count;
1da177e4
LT		 6120
6121 return count;
6122}
6123
07d3f51f 6124static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 6125{
07d3f51f 6126 struct net_device *dev = dev_instance;
1da177e4 6127 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 6128 int handled = 0;
9085cdfa 6129 u16 status;
1da177e4 6130
9085cdfa 6131 status = rtl_get_events(tp);
da78dbff
FR		 6132 if (status && status != 0xffff) {
6133 status &= RTL_EVENT_NAPI | tp->event_slow;
6134 if (status) {
6135 handled = 1;
1da177e4 6136
da78dbff
FR		 6137 rtl_irq_disable(tp);
6138 napi_schedule(&tp->napi);
f11a377b 6139 }
da78dbff
FR		 6140 }
6141 return IRQ_RETVAL(handled);
6142}
1da177e4 6143
da78dbff
FR		 6144/*
6145 * Workqueue context.
6146 */
6147static void rtl_slow_event_work(struct rtl8169_private *tp)
6148{
6149 struct net_device *dev = tp->dev;
6150 u16 status;
6151
6152 status = rtl_get_events(tp) & tp->event_slow;
6153 rtl_ack_events(tp, status);
1da177e4 6154
da78dbff
FR		 6155 if (unlikely(status & RxFIFOOver)) {
6156 switch (tp->mac_version) {
6157 /* Work around for rx fifo overflow */
6158 case RTL_GIGA_MAC_VER_11:
6159 netif_stop_queue(dev);
934714d0
FR		 6160 /* XXX - Hack alert. See rtl_task(). */
6161 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
da78dbff 6162 default:
f11a377b
DD		 6163 break;
6164 }
da78dbff 6165 }
1da177e4 6166
da78dbff
FR		 6167 if (unlikely(status & SYSErr))
6168 rtl8169_pcierr_interrupt(dev);
0e485150 6169
da78dbff
FR		 6170 if (status & LinkChg)
6171 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
1da177e4 6172
7dbb4918 6173 rtl_irq_enable_all(tp);
1da177e4
LT		 6174}
6175
4422bcd4
FR		 6176static void rtl_task(struct work_struct *work)
6177{
da78dbff
FR		 6178 static const struct {
6179 int bitnr;
6180 void (*action)(struct rtl8169_private *);
6181 } rtl_work[] = {
934714d0 6182 /* XXX - keep rtl_slow_event_work() as first element. */
da78dbff
FR		 6183 { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work },
6184 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
6185 { RTL_FLAG_TASK_PHY_PENDING, rtl_phy_work }
6186 };
4422bcd4
FR		 6187 struct rtl8169_private *tp =
6188 container_of(work, struct rtl8169_private, wk.work);
da78dbff
FR		 6189 struct net_device *dev = tp->dev;
6190 int i;
6191
6192 rtl_lock_work(tp);
6193
6c4a70c5
FR		 6194 if (!netif_running(dev) ||
6195 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
da78dbff
FR		 6196 goto out_unlock;
6197
6198 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6199 bool pending;
6200
da78dbff 6201 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
da78dbff
FR		 6202 if (pending)
6203 rtl_work[i].action(tp);
6204 }
4422bcd4 6205
da78dbff
FR		 6206out_unlock:
6207 rtl_unlock_work(tp);
4422bcd4
FR		 6208}
6209
bea3348e 6210static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 6211{
bea3348e
SH		 6212 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6213 struct net_device *dev = tp->dev;
da78dbff
FR		 6214 u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
6215 int work_done= 0;
6216 u16 status;
6217
6218 status = rtl_get_events(tp);
6219 rtl_ack_events(tp, status & ~tp->event_slow);
6220
6221 if (status & RTL_EVENT_NAPI_RX)
6222 work_done = rtl_rx(dev, tp, (u32) budget);
6223
6224 if (status & RTL_EVENT_NAPI_TX)
6225 rtl_tx(dev, tp);
1da177e4 6226
da78dbff
FR		 6227 if (status & tp->event_slow) {
6228 enable_mask &= ~tp->event_slow;
6229
6230 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
6231 }
1da177e4 6232
bea3348e 6233 if (work_done < budget) {
288379f0 6234 napi_complete(napi);
f11a377b 6235
da78dbff
FR		 6236 rtl_irq_enable(tp, enable_mask);
6237 mmiowb();
1da177e4
LT		 6238 }
6239
bea3348e 6240 return work_done;
1da177e4 6241}
1da177e4 6242
523a6094
FR		 6243static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
6244{
6245 struct rtl8169_private *tp = netdev_priv(dev);
6246
6247 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6248 return;
6249
6250 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
6251 RTL_W32(RxMissed, 0);
6252}
6253
1da177e4
LT		 6254static void rtl8169_down(struct net_device *dev)
6255{
6256 struct rtl8169_private *tp = netdev_priv(dev);
6257 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 6258
4876cc1e 6259 del_timer_sync(&tp->timer);
1da177e4 6260
93dd79e8 6261 napi_disable(&tp->napi);
da78dbff 6262 netif_stop_queue(dev);
1da177e4 6263
92fc43b4 6264 rtl8169_hw_reset(tp);
323bb685
SG		 6265 /*
6266 * At this point device interrupts can not be enabled in any function,
209e5ac8
FR		 6267 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6268 * and napi is disabled (rtl8169_poll).
323bb685 6269 */
523a6094 6270 rtl8169_rx_missed(dev, ioaddr);
1da177e4 6271
1da177e4 6272 /* Give a racing hard_start_xmit a few cycles to complete. */
da78dbff 6273 synchronize_sched();
1da177e4 6274
1da177e4
LT		 6275 rtl8169_tx_clear(tp);
6276
6277 rtl8169_rx_clear(tp);
065c27c1 6278
6279 rtl_pll_power_down(tp);
1da177e4
LT		 6280}
6281
6282static int rtl8169_close(struct net_device *dev)
6283{
6284 struct rtl8169_private *tp = netdev_priv(dev);
6285 struct pci_dev *pdev = tp->pci_dev;
6286
e1759441
RW		 6287 pm_runtime_get_sync(&pdev->dev);
6288
cecb5fd7 6289 /* Update counters before going down */
355423d0
IV		 6290 rtl8169_update_counters(dev);
6291
da78dbff 6292 rtl_lock_work(tp);
6c4a70c5 6293 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
da78dbff 6294
1da177e4 6295 rtl8169_down(dev);
da78dbff 6296 rtl_unlock_work(tp);
1da177e4 6297
92a7c4e7 6298 free_irq(pdev->irq, dev);
1da177e4 6299
82553bb6
SG		 6300 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6301 tp->RxPhyAddr);
6302 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6303 tp->TxPhyAddr);
1da177e4
LT		 6304 tp->TxDescArray = NULL;
6305 tp->RxDescArray = NULL;
6306
e1759441
RW		 6307 pm_runtime_put_sync(&pdev->dev);
6308
1da177e4
LT		 6309 return 0;
6310}
6311
dc1c00ce
FR		 6312#ifdef CONFIG_NET_POLL_CONTROLLER
6313static void rtl8169_netpoll(struct net_device *dev)
6314{
6315 struct rtl8169_private *tp = netdev_priv(dev);
6316
6317 rtl8169_interrupt(tp->pci_dev->irq, dev);
6318}
6319#endif
6320
df43ac78
FR		 6321static int rtl_open(struct net_device *dev)
6322{
6323 struct rtl8169_private *tp = netdev_priv(dev);
6324 void __iomem *ioaddr = tp->mmio_addr;
6325 struct pci_dev *pdev = tp->pci_dev;
6326 int retval = -ENOMEM;
6327
6328 pm_runtime_get_sync(&pdev->dev);
6329
6330 /*
e75d6606 6331 * Rx and Tx descriptors needs 256 bytes alignment.
df43ac78
FR		 6332 * dma_alloc_coherent provides more.
6333 */
6334 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6335 &tp->TxPhyAddr, GFP_KERNEL);
6336 if (!tp->TxDescArray)
6337 goto err_pm_runtime_put;
6338
6339 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6340 &tp->RxPhyAddr, GFP_KERNEL);
6341 if (!tp->RxDescArray)
6342 goto err_free_tx_0;
6343
6344 retval = rtl8169_init_ring(dev);
6345 if (retval < 0)
6346 goto err_free_rx_1;
6347
6348 INIT_WORK(&tp->wk.work, rtl_task);
6349
6350 smp_mb();
6351
6352 rtl_request_firmware(tp);
6353
92a7c4e7 6354 retval = request_irq(pdev->irq, rtl8169_interrupt,
df43ac78
FR		 6355 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
6356 dev->name, dev);
6357 if (retval < 0)
6358 goto err_release_fw_2;
6359
6360 rtl_lock_work(tp);
6361
6362 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6363
6364 napi_enable(&tp->napi);
6365
6366 rtl8169_init_phy(dev, tp);
6367
6368 __rtl8169_set_features(dev, dev->features);
6369
6370 rtl_pll_power_up(tp);
6371
6372 rtl_hw_start(dev);
6373
6374 netif_start_queue(dev);
6375
6376 rtl_unlock_work(tp);
6377
6378 tp->saved_wolopts = 0;
6379 pm_runtime_put_noidle(&pdev->dev);
6380
6381 rtl8169_check_link_status(dev, tp, ioaddr);
6382out:
6383 return retval;
6384
6385err_release_fw_2:
6386 rtl_release_firmware(tp);
6387 rtl8169_rx_clear(tp);
6388err_free_rx_1:
6389 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6390 tp->RxPhyAddr);
6391 tp->RxDescArray = NULL;
6392err_free_tx_0:
6393 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6394 tp->TxPhyAddr);
6395 tp->TxDescArray = NULL;
6396err_pm_runtime_put:
6397 pm_runtime_put_noidle(&pdev->dev);
6398 goto out;
6399}
6400
8027aa24
JW		 6401static struct rtnl_link_stats64 *
6402rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
1da177e4
LT		 6403{
6404 struct rtl8169_private *tp = netdev_priv(dev);
6405 void __iomem *ioaddr = tp->mmio_addr;
8027aa24 6406 unsigned int start;
1da177e4 6407
da78dbff 6408 if (netif_running(dev))
523a6094 6409 rtl8169_rx_missed(dev, ioaddr);
5b0384f4 6410
8027aa24
JW		 6411 do {
6412 start = u64_stats_fetch_begin_bh(&tp->rx_stats.syncp);
6413 stats->rx_packets = tp->rx_stats.packets;
6414 stats->rx_bytes = tp->rx_stats.bytes;
6415 } while (u64_stats_fetch_retry_bh(&tp->rx_stats.syncp, start));
6416
6417
6418 do {
6419 start = u64_stats_fetch_begin_bh(&tp->tx_stats.syncp);
6420 stats->tx_packets = tp->tx_stats.packets;
6421 stats->tx_bytes = tp->tx_stats.bytes;
6422 } while (u64_stats_fetch_retry_bh(&tp->tx_stats.syncp, start));
6423
6424 stats->rx_dropped = dev->stats.rx_dropped;
6425 stats->tx_dropped = dev->stats.tx_dropped;
6426 stats->rx_length_errors = dev->stats.rx_length_errors;
6427 stats->rx_errors = dev->stats.rx_errors;
6428 stats->rx_crc_errors = dev->stats.rx_crc_errors;
6429 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
6430 stats->rx_missed_errors = dev->stats.rx_missed_errors;
6431
6432 return stats;
1da177e4
LT		 6433}
6434
861ab440 6435static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 6436{
065c27c1 6437 struct rtl8169_private *tp = netdev_priv(dev);
6438
5d06a99f 6439 if (!netif_running(dev))
861ab440 6440 return;
5d06a99f
FR		 6441
6442 netif_device_detach(dev);
6443 netif_stop_queue(dev);
da78dbff
FR		 6444
6445 rtl_lock_work(tp);
6446 napi_disable(&tp->napi);
6c4a70c5 6447 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
da78dbff
FR		 6448 rtl_unlock_work(tp);
6449
6450 rtl_pll_power_down(tp);
861ab440
RW		 6451}
6452
6453#ifdef CONFIG_PM
6454
6455static int rtl8169_suspend(struct device *device)
6456{
6457 struct pci_dev *pdev = to_pci_dev(device);
6458 struct net_device *dev = pci_get_drvdata(pdev);
5d06a99f 6459
861ab440 6460 rtl8169_net_suspend(dev);
1371fa6d 6461
5d06a99f
FR		 6462 return 0;
6463}
6464
e1759441
RW		 6465static void __rtl8169_resume(struct net_device *dev)
6466{
065c27c1 6467 struct rtl8169_private *tp = netdev_priv(dev);
6468
e1759441 6469 netif_device_attach(dev);
065c27c1 6470
6471 rtl_pll_power_up(tp);
6472
cff4c162
AS		 6473 rtl_lock_work(tp);
6474 napi_enable(&tp->napi);
6c4a70c5 6475 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
cff4c162 6476 rtl_unlock_work(tp);
da78dbff 6477
98ddf986 6478 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
e1759441
RW		 6479}
6480
861ab440 6481static int rtl8169_resume(struct device *device)
5d06a99f 6482{
861ab440 6483 struct pci_dev *pdev = to_pci_dev(device);
5d06a99f 6484 struct net_device *dev = pci_get_drvdata(pdev);
fccec10b
SG		 6485 struct rtl8169_private *tp = netdev_priv(dev);
6486
6487 rtl8169_init_phy(dev, tp);
5d06a99f 6488
e1759441
RW		 6489 if (netif_running(dev))
6490 __rtl8169_resume(dev);
5d06a99f 6491
e1759441
RW		 6492 return 0;
6493}
6494
6495static int rtl8169_runtime_suspend(struct device *device)
6496{
6497 struct pci_dev *pdev = to_pci_dev(device);
6498 struct net_device *dev = pci_get_drvdata(pdev);
6499 struct rtl8169_private *tp = netdev_priv(dev);
6500
6501 if (!tp->TxDescArray)
6502 return 0;
6503
da78dbff 6504 rtl_lock_work(tp);
e1759441
RW		 6505 tp->saved_wolopts = __rtl8169_get_wol(tp);
6506 __rtl8169_set_wol(tp, WAKE_ANY);
da78dbff 6507 rtl_unlock_work(tp);
e1759441
RW		 6508
6509 rtl8169_net_suspend(dev);
6510
6511 return 0;
6512}
6513
6514static int rtl8169_runtime_resume(struct device *device)
6515{
6516 struct pci_dev *pdev = to_pci_dev(device);
6517 struct net_device *dev = pci_get_drvdata(pdev);
6518 struct rtl8169_private *tp = netdev_priv(dev);
6519
6520 if (!tp->TxDescArray)
6521 return 0;
6522
da78dbff 6523 rtl_lock_work(tp);
e1759441
RW		 6524 __rtl8169_set_wol(tp, tp->saved_wolopts);
6525 tp->saved_wolopts = 0;
da78dbff 6526 rtl_unlock_work(tp);
e1759441 6527
fccec10b
SG		 6528 rtl8169_init_phy(dev, tp);
6529
e1759441 6530 __rtl8169_resume(dev);
5d06a99f 6531
5d06a99f
FR		 6532 return 0;
6533}
6534
e1759441
RW		 6535static int rtl8169_runtime_idle(struct device *device)
6536{
6537 struct pci_dev *pdev = to_pci_dev(device);
6538 struct net_device *dev = pci_get_drvdata(pdev);
6539 struct rtl8169_private *tp = netdev_priv(dev);
6540
e4fbce74 6541 return tp->TxDescArray ? -EBUSY : 0;
e1759441
RW		 6542}
6543
47145210 6544static const struct dev_pm_ops rtl8169_pm_ops = {
cecb5fd7
FR		 6545 .suspend = rtl8169_suspend,
6546 .resume = rtl8169_resume,
6547 .freeze = rtl8169_suspend,
6548 .thaw = rtl8169_resume,
6549 .poweroff = rtl8169_suspend,
6550 .restore = rtl8169_resume,
6551 .runtime_suspend = rtl8169_runtime_suspend,
6552 .runtime_resume = rtl8169_runtime_resume,
6553 .runtime_idle = rtl8169_runtime_idle,
861ab440
RW		 6554};
6555
6556#define RTL8169_PM_OPS (&rtl8169_pm_ops)
6557
6558#else /* !CONFIG_PM */
6559
6560#define RTL8169_PM_OPS NULL
6561
6562#endif /* !CONFIG_PM */
6563
649b3b8c 6564static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6565{
6566 void __iomem *ioaddr = tp->mmio_addr;
6567
6568 /* WoL fails with 8168b when the receiver is disabled. */
6569 switch (tp->mac_version) {
6570 case RTL_GIGA_MAC_VER_11:
6571 case RTL_GIGA_MAC_VER_12:
6572 case RTL_GIGA_MAC_VER_17:
6573 pci_clear_master(tp->pci_dev);
6574
6575 RTL_W8(ChipCmd, CmdRxEnb);
6576 /* PCI commit */
6577 RTL_R8(ChipCmd);
6578 break;
6579 default:
6580 break;
6581 }
6582}
6583
1765f95d
FR		 6584static void rtl_shutdown(struct pci_dev *pdev)
6585{
861ab440 6586 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 6587 struct rtl8169_private *tp = netdev_priv(dev);
2a15cd2f 6588 struct device *d = &pdev->dev;
6589
6590 pm_runtime_get_sync(d);
861ab440
RW		 6591
6592 rtl8169_net_suspend(dev);
1765f95d 6593
cecb5fd7 6594 /* Restore original MAC address */
cc098dc7
IV		 6595 rtl_rar_set(tp, dev->perm_addr);
6596
92fc43b4 6597 rtl8169_hw_reset(tp);
4bb3f522 6598
861ab440 6599 if (system_state == SYSTEM_POWER_OFF) {
649b3b8c 6600 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
6601 rtl_wol_suspend_quirk(tp);
6602 rtl_wol_shutdown_quirk(tp);
ca52efd5 6603 }
6604
861ab440
RW		 6605 pci_wake_from_d3(pdev, true);
6606 pci_set_power_state(pdev, PCI_D3hot);
6607 }
2a15cd2f 6608
6609 pm_runtime_put_noidle(d);
861ab440 6610}
5d06a99f 6611
baf63293 6612static void rtl_remove_one(struct pci_dev *pdev)
e27566ed
FR		 6613{
6614 struct net_device *dev = pci_get_drvdata(pdev);
6615 struct rtl8169_private *tp = netdev_priv(dev);
6616
6617 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
6618 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
6619 tp->mac_version == RTL_GIGA_MAC_VER_31) {
6620 rtl8168_driver_stop(tp);
6621 }
6622
6623 cancel_work_sync(&tp->wk.work);
6624
ad1be8d3
DN		 6625 netif_napi_del(&tp->napi);
6626
e27566ed
FR		 6627 unregister_netdev(dev);
6628
6629 rtl_release_firmware(tp);
6630
6631 if (pci_dev_run_wake(pdev))
6632 pm_runtime_get_noresume(&pdev->dev);
6633
6634 /* restore original MAC address */
6635 rtl_rar_set(tp, dev->perm_addr);
6636
6637 rtl_disable_msi(pdev, tp);
6638 rtl8169_release_board(pdev, dev, tp->mmio_addr);
6639 pci_set_drvdata(pdev, NULL);
6640}
6641
fa9c385e 6642static const struct net_device_ops rtl_netdev_ops = {
df43ac78 6643 .ndo_open = rtl_open,
fa9c385e
FR		 6644 .ndo_stop = rtl8169_close,
6645 .ndo_get_stats64 = rtl8169_get_stats64,
6646 .ndo_start_xmit = rtl8169_start_xmit,
6647 .ndo_tx_timeout = rtl8169_tx_timeout,
6648 .ndo_validate_addr = eth_validate_addr,
6649 .ndo_change_mtu = rtl8169_change_mtu,
6650 .ndo_fix_features = rtl8169_fix_features,
6651 .ndo_set_features = rtl8169_set_features,
6652 .ndo_set_mac_address = rtl_set_mac_address,
6653 .ndo_do_ioctl = rtl8169_ioctl,
6654 .ndo_set_rx_mode = rtl_set_rx_mode,
6655#ifdef CONFIG_NET_POLL_CONTROLLER
6656 .ndo_poll_controller = rtl8169_netpoll,
6657#endif
6658
6659};
6660
31fa8b18
FR		 6661static const struct rtl_cfg_info {
6662 void (*hw_start)(struct net_device *);
6663 unsigned int region;
6664 unsigned int align;
6665 u16 event_slow;
6666 unsigned features;
6667 u8 default_ver;
6668} rtl_cfg_infos [] = {
6669 [RTL_CFG_0] = {
6670 .hw_start = rtl_hw_start_8169,
6671 .region = 1,
6672 .align = 0,
6673 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
6674 .features = RTL_FEATURE_GMII,
6675 .default_ver = RTL_GIGA_MAC_VER_01,
6676 },
6677 [RTL_CFG_1] = {
6678 .hw_start = rtl_hw_start_8168,
6679 .region = 2,
6680 .align = 8,
6681 .event_slow = SYSErr | LinkChg | RxOverflow,
6682 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
6683 .default_ver = RTL_GIGA_MAC_VER_11,
6684 },
6685 [RTL_CFG_2] = {
6686 .hw_start = rtl_hw_start_8101,
6687 .region = 2,
6688 .align = 8,
6689 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
6690 PCSTimeout,
6691 .features = RTL_FEATURE_MSI,
6692 .default_ver = RTL_GIGA_MAC_VER_13,
6693 }
6694};
6695
6696/* Cfg9346_Unlock assumed. */
6697static unsigned rtl_try_msi(struct rtl8169_private *tp,
6698 const struct rtl_cfg_info *cfg)
6699{
6700 void __iomem *ioaddr = tp->mmio_addr;
6701 unsigned msi = 0;
6702 u8 cfg2;
6703
6704 cfg2 = RTL_R8(Config2) & ~MSIEnable;
6705 if (cfg->features & RTL_FEATURE_MSI) {
6706 if (pci_enable_msi(tp->pci_dev)) {
6707 netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
6708 } else {
6709 cfg2 |= MSIEnable;
6710 msi = RTL_FEATURE_MSI;
6711 }
6712 }
6713 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
6714 RTL_W8(Config2, cfg2);
6715 return msi;
6716}
6717
c558386b
HW		 6718DECLARE_RTL_COND(rtl_link_list_ready_cond)
6719{
6720 void __iomem *ioaddr = tp->mmio_addr;
6721
6722 return RTL_R8(MCU) & LINK_LIST_RDY;
6723}
6724
6725DECLARE_RTL_COND(rtl_rxtx_empty_cond)
6726{
6727 void __iomem *ioaddr = tp->mmio_addr;
6728
6729 return (RTL_R8(MCU) & RXTX_EMPTY) == RXTX_EMPTY;
6730}
6731
baf63293 6732static void rtl_hw_init_8168g(struct rtl8169_private *tp)
c558386b
HW		 6733{
6734 void __iomem *ioaddr = tp->mmio_addr;
6735 u32 data;
6736
6737 tp->ocp_base = OCP_STD_PHY_BASE;
6738
6739 RTL_W32(MISC, RTL_R32(MISC) | RXDV_GATED_EN);
6740
6741 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
6742 return;
6743
6744 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
6745 return;
6746
6747 RTL_W8(ChipCmd, RTL_R8(ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
6748 msleep(1);
6749 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
6750
5f8bcce9 6751 data = r8168_mac_ocp_read(tp, 0xe8de);
c558386b
HW		 6752 data &= ~(1 << 14);
6753 r8168_mac_ocp_write(tp, 0xe8de, data);
6754
6755 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6756 return;
6757
5f8bcce9 6758 data = r8168_mac_ocp_read(tp, 0xe8de);
c558386b
HW		 6759 data |= (1 << 15);
6760 r8168_mac_ocp_write(tp, 0xe8de, data);
6761
6762 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6763 return;
6764}
6765
baf63293 6766static void rtl_hw_initialize(struct rtl8169_private *tp)
c558386b
HW		 6767{
6768 switch (tp->mac_version) {
6769 case RTL_GIGA_MAC_VER_40:
6770 case RTL_GIGA_MAC_VER_41:
6771 rtl_hw_init_8168g(tp);
6772 break;
6773
6774 default:
6775 break;
6776 }
6777}
6778
baf63293 6779static int
3b6cf25d
FR		 6780rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6781{
6782 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
6783 const unsigned int region = cfg->region;
6784 struct rtl8169_private *tp;
6785 struct mii_if_info *mii;
6786 struct net_device *dev;
6787 void __iomem *ioaddr;
6788 int chipset, i;
6789 int rc;
6790
6791 if (netif_msg_drv(&debug)) {
6792 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
6793 MODULENAME, RTL8169_VERSION);
6794 }
6795
6796 dev = alloc_etherdev(sizeof (*tp));
6797 if (!dev) {
6798 rc = -ENOMEM;
6799 goto out;
6800 }
6801
6802 SET_NETDEV_DEV(dev, &pdev->dev);
fa9c385e 6803 dev->netdev_ops = &rtl_netdev_ops;
3b6cf25d
FR		 6804 tp = netdev_priv(dev);
6805 tp->dev = dev;
6806 tp->pci_dev = pdev;
6807 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
6808
6809 mii = &tp->mii;
6810 mii->dev = dev;
6811 mii->mdio_read = rtl_mdio_read;
6812 mii->mdio_write = rtl_mdio_write;
6813 mii->phy_id_mask = 0x1f;
6814 mii->reg_num_mask = 0x1f;
6815 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
6816
6817 /* disable ASPM completely as that cause random device stop working
6818 * problems as well as full system hangs for some PCIe devices users */
6819 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
6820 PCIE_LINK_STATE_CLKPM);
6821
6822 /* enable device (incl. PCI PM wakeup and hotplug setup) */
6823 rc = pci_enable_device(pdev);
6824 if (rc < 0) {
6825 netif_err(tp, probe, dev, "enable failure\n");
6826 goto err_out_free_dev_1;
6827 }
6828
6829 if (pci_set_mwi(pdev) < 0)
6830 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
6831
6832 /* make sure PCI base addr 1 is MMIO */
6833 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
6834 netif_err(tp, probe, dev,
6835 "region #%d not an MMIO resource, aborting\n",
6836 region);
6837 rc = -ENODEV;
6838 goto err_out_mwi_2;
6839 }
6840
6841 /* check for weird/broken PCI region reporting */
6842 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
6843 netif_err(tp, probe, dev,
6844 "Invalid PCI region size(s), aborting\n");
6845 rc = -ENODEV;
6846 goto err_out_mwi_2;
6847 }
6848
6849 rc = pci_request_regions(pdev, MODULENAME);
6850 if (rc < 0) {
6851 netif_err(tp, probe, dev, "could not request regions\n");
6852 goto err_out_mwi_2;
6853 }
6854
6855 tp->cp_cmd = RxChkSum;
6856
6857 if ((sizeof(dma_addr_t) > 4) &&
6858 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
6859 tp->cp_cmd |= PCIDAC;
6860 dev->features |= NETIF_F_HIGHDMA;
6861 } else {
6862 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6863 if (rc < 0) {
6864 netif_err(tp, probe, dev, "DMA configuration failed\n");
6865 goto err_out_free_res_3;
6866 }
6867 }
6868
6869 /* ioremap MMIO region */
6870 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
6871 if (!ioaddr) {
6872 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
6873 rc = -EIO;
6874 goto err_out_free_res_3;
6875 }
6876 tp->mmio_addr = ioaddr;
6877
6878 if (!pci_is_pcie(pdev))
6879 netif_info(tp, probe, dev, "not PCI Express\n");
6880
6881 /* Identify chip attached to board */
6882 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
6883
6884 rtl_init_rxcfg(tp);
6885
6886 rtl_irq_disable(tp);
6887
c558386b
HW		 6888 rtl_hw_initialize(tp);
6889
3b6cf25d
FR		 6890 rtl_hw_reset(tp);
6891
6892 rtl_ack_events(tp, 0xffff);
6893
6894 pci_set_master(pdev);
6895
6896 /*
6897 * Pretend we are using VLANs; This bypasses a nasty bug where
6898 * Interrupts stop flowing on high load on 8110SCd controllers.
6899 */
6900 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6901 tp->cp_cmd |= RxVlan;
6902
6903 rtl_init_mdio_ops(tp);
6904 rtl_init_pll_power_ops(tp);
6905 rtl_init_jumbo_ops(tp);
beb1fe18 6906 rtl_init_csi_ops(tp);
3b6cf25d
FR		 6907
6908 rtl8169_print_mac_version(tp);
6909
6910 chipset = tp->mac_version;
6911 tp->txd_version = rtl_chip_infos[chipset].txd_version;
6912
6913 RTL_W8(Cfg9346, Cfg9346_Unlock);
6914 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
6915 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
6916 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
6917 tp->features |= RTL_FEATURE_WOL;
6918 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
6919 tp->features |= RTL_FEATURE_WOL;
6920 tp->features |= rtl_try_msi(tp, cfg);
6921 RTL_W8(Cfg9346, Cfg9346_Lock);
6922
6923 if (rtl_tbi_enabled(tp)) {
6924 tp->set_speed = rtl8169_set_speed_tbi;
6925 tp->get_settings = rtl8169_gset_tbi;
6926 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
6927 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
6928 tp->link_ok = rtl8169_tbi_link_ok;
6929 tp->do_ioctl = rtl_tbi_ioctl;
6930 } else {
6931 tp->set_speed = rtl8169_set_speed_xmii;
6932 tp->get_settings = rtl8169_gset_xmii;
6933 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
6934 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
6935 tp->link_ok = rtl8169_xmii_link_ok;
6936 tp->do_ioctl = rtl_xmii_ioctl;
6937 }
6938
6939 mutex_init(&tp->wk.mutex);
6940
6941 /* Get MAC address */
6942 for (i = 0; i < ETH_ALEN; i++)
6943 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6944 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
6945
6946 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
6947 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3b6cf25d
FR		 6948
6949 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
6950
6951 /* don't enable SG, IP_CSUM and TSO by default - it might not work
6952 * properly for all devices */
6953 dev->features |= NETIF_F_RXCSUM |
6954 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6955
6956 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6957 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6958 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6959 NETIF_F_HIGHDMA;
6960
6961 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6962 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
6963 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
6964
6965 dev->hw_features |= NETIF_F_RXALL;
6966 dev->hw_features |= NETIF_F_RXFCS;
6967
6968 tp->hw_start = cfg->hw_start;
6969 tp->event_slow = cfg->event_slow;
6970
6971 tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
6972 ~(RxBOVF | RxFOVF) : ~0;
6973
6974 init_timer(&tp->timer);
6975 tp->timer.data = (unsigned long) dev;
6976 tp->timer.function = rtl8169_phy_timer;
6977
6978 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
6979
6980 rc = register_netdev(dev);
6981 if (rc < 0)
6982 goto err_out_msi_4;
6983
6984 pci_set_drvdata(pdev, dev);
6985
92a7c4e7
FR		 6986 netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
6987 rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
6988 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
3b6cf25d
FR		 6989 if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
6990 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
6991 "tx checksumming: %s]\n",
6992 rtl_chip_infos[chipset].jumbo_max,
6993 rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
6994 }
6995
6996 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
6997 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
6998 tp->mac_version == RTL_GIGA_MAC_VER_31) {
6999 rtl8168_driver_start(tp);
7000 }
7001
7002 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
7003
7004 if (pci_dev_run_wake(pdev))
7005 pm_runtime_put_noidle(&pdev->dev);
7006
7007 netif_carrier_off(dev);
7008
7009out:
7010 return rc;
7011
7012err_out_msi_4:
ad1be8d3 7013 netif_napi_del(&tp->napi);
3b6cf25d
FR		 7014 rtl_disable_msi(pdev, tp);
7015 iounmap(ioaddr);
7016err_out_free_res_3:
7017 pci_release_regions(pdev);
7018err_out_mwi_2:
7019 pci_clear_mwi(pdev);
7020 pci_disable_device(pdev);
7021err_out_free_dev_1:
7022 free_netdev(dev);
7023 goto out;
7024}
7025
1da177e4
LT		 7026static struct pci_driver rtl8169_pci_driver = {
7027 .name = MODULENAME,
7028 .id_table = rtl8169_pci_tbl,
3b6cf25d 7029 .probe = rtl_init_one,
baf63293 7030 .remove = rtl_remove_one,
1765f95d 7031 .shutdown = rtl_shutdown,
861ab440 7032 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 7033};
7034
3eeb7da9 7035module_pci_driver(rtl8169_pci_driver);
Ubuntu Focal Linux kernel mirror