]> git.proxmox.com Git - mirror_ubuntu-focal-kernel.git/blame - drivers/net/ethernet/realtek/r8169.c
projects / mirror_ubuntu-focal-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
r8169: add a new chip for RTL8111G
[mirror_ubuntu-focal-kernel.git] / drivers / net / ethernet / realtek / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
a6b7a407 25#include <linux/interrupt.h>
1da177e4 26#include <linux/dma-mapping.h>
e1759441 27#include <linux/pm_runtime.h>
bca03d5f 28#include <linux/firmware.h>
ba04c7c9 29#include <linux/pci-aspm.h>
70c71606 30#include <linux/prefetch.h>
1da177e4
LT		 31
32#include <asm/io.h>
33#include <asm/irq.h>
34
865c652d 35#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 36#define MODULENAME "r8169"
37#define PFX MODULENAME ": "
38
bca03d5f 39#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
40#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
01dc7fec 41#define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
42#define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
70090424 43#define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
c2218925
HW		 44#define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
45#define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
5a5e4443 46#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
7e18dca1 47#define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
b3d7b2f2 48#define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
5598bfe5 49#define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
beb330a4 50#define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
57538c4a 51#define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
bca03d5f 52
1da177e4
LT		 53#ifdef RTL8169_DEBUG
54#define assert(expr) \
5b0384f4
FR		 55 if (!(expr)) { \
56 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
b39d66a8 57 #expr,__FILE__,__func__,__LINE__); \
5b0384f4 58 }
06fa7358
JP		 59#define dprintk(fmt, args...) \
60 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 61#else
62#define assert(expr) do {} while (0)
63#define dprintk(fmt, args...) do {} while (0)
64#endif /* RTL8169_DEBUG */
65
b57b7e5a 66#define R8169_MSG_DEFAULT \
f0e837d9 67 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 68
477206a0
JD		 69#define TX_SLOTS_AVAIL(tp) \
70 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
71
72/* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
73#define TX_FRAGS_READY_FOR(tp,nr_frags) \
74 (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
1da177e4 75
1da177e4
LT		 76/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
77 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 78static const int multicast_filter_limit = 32;
1da177e4 79
9c14ceaf 80#define MAX_READ_REQUEST_SHIFT 12
aee77e4a 81#define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
1da177e4
LT		 82#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
83
84#define R8169_REGS_SIZE 256
85#define R8169_NAPI_WEIGHT 64
86#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
9fba0812 87#define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
1da177e4
LT		 88#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
89#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
90
91#define RTL8169_TX_TIMEOUT (6*HZ)
92#define RTL8169_PHY_TIMEOUT (10*HZ)
93
94/* write/read MMIO register */
95#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
96#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
97#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
98#define RTL_R8(reg) readb (ioaddr + (reg))
99#define RTL_R16(reg) readw (ioaddr + (reg))
06f555f3 100#define RTL_R32(reg) readl (ioaddr + (reg))
1da177e4
LT		 101
102enum mac_version {
85bffe6c
FR		 103 RTL_GIGA_MAC_VER_01 = 0,
104 RTL_GIGA_MAC_VER_02,
105 RTL_GIGA_MAC_VER_03,
106 RTL_GIGA_MAC_VER_04,
107 RTL_GIGA_MAC_VER_05,
108 RTL_GIGA_MAC_VER_06,
109 RTL_GIGA_MAC_VER_07,
110 RTL_GIGA_MAC_VER_08,
111 RTL_GIGA_MAC_VER_09,
112 RTL_GIGA_MAC_VER_10,
113 RTL_GIGA_MAC_VER_11,
114 RTL_GIGA_MAC_VER_12,
115 RTL_GIGA_MAC_VER_13,
116 RTL_GIGA_MAC_VER_14,
117 RTL_GIGA_MAC_VER_15,
118 RTL_GIGA_MAC_VER_16,
119 RTL_GIGA_MAC_VER_17,
120 RTL_GIGA_MAC_VER_18,
121 RTL_GIGA_MAC_VER_19,
122 RTL_GIGA_MAC_VER_20,
123 RTL_GIGA_MAC_VER_21,
124 RTL_GIGA_MAC_VER_22,
125 RTL_GIGA_MAC_VER_23,
126 RTL_GIGA_MAC_VER_24,
127 RTL_GIGA_MAC_VER_25,
128 RTL_GIGA_MAC_VER_26,
129 RTL_GIGA_MAC_VER_27,
130 RTL_GIGA_MAC_VER_28,
131 RTL_GIGA_MAC_VER_29,
132 RTL_GIGA_MAC_VER_30,
133 RTL_GIGA_MAC_VER_31,
134 RTL_GIGA_MAC_VER_32,
135 RTL_GIGA_MAC_VER_33,
70090424 136 RTL_GIGA_MAC_VER_34,
c2218925
HW		 137 RTL_GIGA_MAC_VER_35,
138 RTL_GIGA_MAC_VER_36,
7e18dca1 139 RTL_GIGA_MAC_VER_37,
b3d7b2f2 140 RTL_GIGA_MAC_VER_38,
5598bfe5 141 RTL_GIGA_MAC_VER_39,
c558386b
HW		 142 RTL_GIGA_MAC_VER_40,
143 RTL_GIGA_MAC_VER_41,
57538c4a 144 RTL_GIGA_MAC_VER_42,
85bffe6c 145 RTL_GIGA_MAC_NONE = 0xff,
1da177e4
LT		 146};
147
2b7b4318
FR		 148enum rtl_tx_desc_version {
149 RTL_TD_0 = 0,
150 RTL_TD_1 = 1,
151};
152
d58d46b5
FR		 153#define JUMBO_1K ETH_DATA_LEN
154#define JUMBO_4K (4*1024 - ETH_HLEN - 2)
155#define JUMBO_6K (6*1024 - ETH_HLEN - 2)
156#define JUMBO_7K (7*1024 - ETH_HLEN - 2)
157#define JUMBO_9K (9*1024 - ETH_HLEN - 2)
158
159#define _R(NAME,TD,FW,SZ,B) { \
160 .name = NAME, \
161 .txd_version = TD, \
162 .fw_name = FW, \
163 .jumbo_max = SZ, \
164 .jumbo_tx_csum = B \
165}
1da177e4 166
3c6bee1d 167static const struct {
1da177e4 168 const char *name;
2b7b4318 169 enum rtl_tx_desc_version txd_version;
953a12cc 170 const char *fw_name;
d58d46b5
FR		 171 u16 jumbo_max;
172 bool jumbo_tx_csum;
85bffe6c
FR		 173} rtl_chip_infos[] = {
174 /* PCI devices. */
175 [RTL_GIGA_MAC_VER_01] =
d58d46b5 176 _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 177 [RTL_GIGA_MAC_VER_02] =
d58d46b5 178 _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 179 [RTL_GIGA_MAC_VER_03] =
d58d46b5 180 _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 181 [RTL_GIGA_MAC_VER_04] =
d58d46b5 182 _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 183 [RTL_GIGA_MAC_VER_05] =
d58d46b5 184 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 185 [RTL_GIGA_MAC_VER_06] =
d58d46b5 186 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c
FR		 187 /* PCI-E devices. */
188 [RTL_GIGA_MAC_VER_07] =
d58d46b5 189 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 190 [RTL_GIGA_MAC_VER_08] =
d58d46b5 191 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 192 [RTL_GIGA_MAC_VER_09] =
d58d46b5 193 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 194 [RTL_GIGA_MAC_VER_10] =
d58d46b5 195 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 196 [RTL_GIGA_MAC_VER_11] =
d58d46b5 197 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
85bffe6c 198 [RTL_GIGA_MAC_VER_12] =
d58d46b5 199 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
85bffe6c 200 [RTL_GIGA_MAC_VER_13] =
d58d46b5 201 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 202 [RTL_GIGA_MAC_VER_14] =
d58d46b5 203 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 204 [RTL_GIGA_MAC_VER_15] =
d58d46b5 205 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 206 [RTL_GIGA_MAC_VER_16] =
d58d46b5 207 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 208 [RTL_GIGA_MAC_VER_17] =
d58d46b5 209 _R("RTL8168b/8111b", RTL_TD_1, NULL, JUMBO_4K, false),
85bffe6c 210 [RTL_GIGA_MAC_VER_18] =
d58d46b5 211 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 212 [RTL_GIGA_MAC_VER_19] =
d58d46b5 213 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 214 [RTL_GIGA_MAC_VER_20] =
d58d46b5 215 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 216 [RTL_GIGA_MAC_VER_21] =
d58d46b5 217 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 218 [RTL_GIGA_MAC_VER_22] =
d58d46b5 219 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 220 [RTL_GIGA_MAC_VER_23] =
d58d46b5 221 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 222 [RTL_GIGA_MAC_VER_24] =
d58d46b5 223 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 224 [RTL_GIGA_MAC_VER_25] =
d58d46b5
FR		 225 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1,
226 JUMBO_9K, false),
85bffe6c 227 [RTL_GIGA_MAC_VER_26] =
d58d46b5
FR		 228 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2,
229 JUMBO_9K, false),
85bffe6c 230 [RTL_GIGA_MAC_VER_27] =
d58d46b5 231 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 232 [RTL_GIGA_MAC_VER_28] =
d58d46b5 233 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 234 [RTL_GIGA_MAC_VER_29] =
d58d46b5
FR		 235 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
236 JUMBO_1K, true),
85bffe6c 237 [RTL_GIGA_MAC_VER_30] =
d58d46b5
FR		 238 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
239 JUMBO_1K, true),
85bffe6c 240 [RTL_GIGA_MAC_VER_31] =
d58d46b5 241 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 242 [RTL_GIGA_MAC_VER_32] =
d58d46b5
FR		 243 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1,
244 JUMBO_9K, false),
85bffe6c 245 [RTL_GIGA_MAC_VER_33] =
d58d46b5
FR		 246 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2,
247 JUMBO_9K, false),
70090424 248 [RTL_GIGA_MAC_VER_34] =
d58d46b5
FR		 249 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
250 JUMBO_9K, false),
c2218925 251 [RTL_GIGA_MAC_VER_35] =
d58d46b5
FR		 252 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1,
253 JUMBO_9K, false),
c2218925 254 [RTL_GIGA_MAC_VER_36] =
d58d46b5
FR		 255 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2,
256 JUMBO_9K, false),
7e18dca1
HW		 257 [RTL_GIGA_MAC_VER_37] =
258 _R("RTL8402", RTL_TD_1, FIRMWARE_8402_1,
259 JUMBO_1K, true),
b3d7b2f2
HW		 260 [RTL_GIGA_MAC_VER_38] =
261 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_1,
262 JUMBO_9K, false),
5598bfe5
HW		 263 [RTL_GIGA_MAC_VER_39] =
264 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_1,
265 JUMBO_1K, true),
c558386b 266 [RTL_GIGA_MAC_VER_40] =
beb330a4 267 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_2,
c558386b
HW		 268 JUMBO_9K, false),
269 [RTL_GIGA_MAC_VER_41] =
270 _R("RTL8168g/8111g", RTL_TD_1, NULL, JUMBO_9K, false),
57538c4a 271 [RTL_GIGA_MAC_VER_42] =
272 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_3,
273 JUMBO_9K, false),
953a12cc 274};
85bffe6c 275#undef _R
953a12cc 276
bcf0bf90
FR		 277enum cfg_version {
278 RTL_CFG_0 = 0x00,
279 RTL_CFG_1,
280 RTL_CFG_2
281};
282
a3aa1884 283static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
bcf0bf90 284 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 285 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 286 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 287 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90 288 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
2a35cfa5
FR		 289 { PCI_VENDOR_ID_DLINK, 0x4300,
290 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
bcf0bf90 291 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
93a3aa25 292 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
bc1660b5 293 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 294 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
295 { PCI_VENDOR_ID_LINKSYS, 0x1032,
296 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 297 { 0x0001, 0x8168,
298 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 299 {0,},
300};
301
302MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
303
6f0333b8 304static int rx_buf_sz = 16383;
4300e8c7 305static int use_dac;
b57b7e5a
SH		 306static struct {
307 u32 msg_enable;
308} debug = { -1 };
1da177e4 309
07d3f51f
FR		 310enum rtl_registers {
311 MAC0 = 0, /* Ethernet hardware address. */
773d2021 312 MAC4 = 4,
07d3f51f
FR		 313 MAR0 = 8, /* Multicast filter. */
314 CounterAddrLow = 0x10,
315 CounterAddrHigh = 0x14,
316 TxDescStartAddrLow = 0x20,
317 TxDescStartAddrHigh = 0x24,
318 TxHDescStartAddrLow = 0x28,
319 TxHDescStartAddrHigh = 0x2c,
320 FLASH = 0x30,
321 ERSR = 0x36,
322 ChipCmd = 0x37,
323 TxPoll = 0x38,
324 IntrMask = 0x3c,
325 IntrStatus = 0x3e,
4f6b00e5 326
07d3f51f 327 TxConfig = 0x40,
4f6b00e5
HW		 328#define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
329#define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
2b7b4318 330
4f6b00e5
HW		 331 RxConfig = 0x44,
332#define RX128_INT_EN (1 << 15) /* 8111c and later */
333#define RX_MULTI_EN (1 << 14) /* 8111c only */
334#define RXCFG_FIFO_SHIFT 13
335 /* No threshold before first PCI xfer */
336#define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
beb330a4 337#define RX_EARLY_OFF (1 << 11)
4f6b00e5
HW		 338#define RXCFG_DMA_SHIFT 8
339 /* Unlimited maximum PCI burst. */
340#define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
2b7b4318 341
07d3f51f
FR		 342 RxMissed = 0x4c,
343 Cfg9346 = 0x50,
344 Config0 = 0x51,
345 Config1 = 0x52,
346 Config2 = 0x53,
d387b427
FR		 347#define PME_SIGNAL (1 << 5) /* 8168c and later */
348
07d3f51f
FR		 349 Config3 = 0x54,
350 Config4 = 0x55,
351 Config5 = 0x56,
352 MultiIntr = 0x5c,
353 PHYAR = 0x60,
07d3f51f
FR		 354 PHYstatus = 0x6c,
355 RxMaxSize = 0xda,
356 CPlusCmd = 0xe0,
357 IntrMitigate = 0xe2,
358 RxDescAddrLow = 0xe4,
359 RxDescAddrHigh = 0xe8,
f0298f81 360 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
361
362#define NoEarlyTx 0x3f /* Max value : no early transmit. */
363
364 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
365
366#define TxPacketMax (8064 >> 7)
3090bd9a 367#define EarlySize 0x27
f0298f81 368
07d3f51f
FR		 369 FuncEvent = 0xf0,
370 FuncEventMask = 0xf4,
371 FuncPresetState = 0xf8,
372 FuncForceEvent = 0xfc,
1da177e4
LT		 373};
374
f162a5d1
FR		 375enum rtl8110_registers {
376 TBICSR = 0x64,
377 TBI_ANAR = 0x68,
378 TBI_LPAR = 0x6a,
379};
380
381enum rtl8168_8101_registers {
382 CSIDR = 0x64,
383 CSIAR = 0x68,
384#define CSIAR_FLAG 0x80000000
385#define CSIAR_WRITE_CMD 0x80000000
386#define CSIAR_BYTE_ENABLE 0x0f
387#define CSIAR_BYTE_ENABLE_SHIFT 12
388#define CSIAR_ADDR_MASK 0x0fff
7e18dca1
HW		 389#define CSIAR_FUNC_CARD 0x00000000
390#define CSIAR_FUNC_SDIO 0x00010000
391#define CSIAR_FUNC_NIC 0x00020000
065c27c1 392 PMCH = 0x6f,
f162a5d1
FR		 393 EPHYAR = 0x80,
394#define EPHYAR_FLAG 0x80000000
395#define EPHYAR_WRITE_CMD 0x80000000
396#define EPHYAR_REG_MASK 0x1f
397#define EPHYAR_REG_SHIFT 16
398#define EPHYAR_DATA_MASK 0xffff
5a5e4443 399 DLLPR = 0xd0,
4f6b00e5 400#define PFM_EN (1 << 6)
f162a5d1
FR		 401 DBG_REG = 0xd1,
402#define FIX_NAK_1 (1 << 4)
403#define FIX_NAK_2 (1 << 3)
5a5e4443
HW		 404 TWSI = 0xd2,
405 MCU = 0xd3,
4f6b00e5 406#define NOW_IS_OOB (1 << 7)
c558386b
HW		 407#define TX_EMPTY (1 << 5)
408#define RX_EMPTY (1 << 4)
409#define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
5a5e4443
HW		 410#define EN_NDP (1 << 3)
411#define EN_OOB_RESET (1 << 2)
c558386b 412#define LINK_LIST_RDY (1 << 1)
daf9df6d 413 EFUSEAR = 0xdc,
414#define EFUSEAR_FLAG 0x80000000
415#define EFUSEAR_WRITE_CMD 0x80000000
416#define EFUSEAR_READ_CMD 0x00000000
417#define EFUSEAR_REG_MASK 0x03ff
418#define EFUSEAR_REG_SHIFT 8
419#define EFUSEAR_DATA_MASK 0xff
f162a5d1
FR		 420};
421
c0e45c1c 422enum rtl8168_registers {
4f6b00e5
HW		 423 LED_FREQ = 0x1a,
424 EEE_LED = 0x1b,
b646d900 425 ERIDR = 0x70,
426 ERIAR = 0x74,
427#define ERIAR_FLAG 0x80000000
428#define ERIAR_WRITE_CMD 0x80000000
429#define ERIAR_READ_CMD 0x00000000
430#define ERIAR_ADDR_BYTE_ALIGN 4
b646d900 431#define ERIAR_TYPE_SHIFT 16
4f6b00e5
HW		 432#define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
433#define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
434#define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
435#define ERIAR_MASK_SHIFT 12
436#define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
437#define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
c558386b 438#define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
4f6b00e5 439#define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
c0e45c1c 440 EPHY_RXER_NUM = 0x7c,
441 OCPDR = 0xb0, /* OCP GPHY access */
442#define OCPDR_WRITE_CMD 0x80000000
443#define OCPDR_READ_CMD 0x00000000
444#define OCPDR_REG_MASK 0x7f
445#define OCPDR_GPHY_REG_SHIFT 16
446#define OCPDR_DATA_MASK 0xffff
447 OCPAR = 0xb4,
448#define OCPAR_FLAG 0x80000000
449#define OCPAR_GPHY_WRITE_CMD 0x8000f060
450#define OCPAR_GPHY_READ_CMD 0x0000f060
c558386b 451 GPHY_OCP = 0xb8,
01dc7fec 452 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
453 MISC = 0xf0, /* 8168e only. */
cecb5fd7 454#define TXPLA_RST (1 << 29)
5598bfe5 455#define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
4f6b00e5 456#define PWM_EN (1 << 22)
c558386b 457#define RXDV_GATED_EN (1 << 19)
5598bfe5 458#define EARLY_TALLY_EN (1 << 16)
c0e45c1c 459};
460
07d3f51f 461enum rtl_register_content {
1da177e4 462 /* InterruptStatusBits */
07d3f51f
FR		 463 SYSErr = 0x8000,
464 PCSTimeout = 0x4000,
465 SWInt = 0x0100,
466 TxDescUnavail = 0x0080,
467 RxFIFOOver = 0x0040,
468 LinkChg = 0x0020,
469 RxOverflow = 0x0010,
470 TxErr = 0x0008,
471 TxOK = 0x0004,
472 RxErr = 0x0002,
473 RxOK = 0x0001,
1da177e4
LT		 474
475 /* RxStatusDesc */
e03f33af 476 RxBOVF = (1 << 24),
9dccf611
FR		 477 RxFOVF = (1 << 23),
478 RxRWT = (1 << 22),
479 RxRES = (1 << 21),
480 RxRUNT = (1 << 20),
481 RxCRC = (1 << 19),
1da177e4
LT		 482
483 /* ChipCmdBits */
4f6b00e5 484 StopReq = 0x80,
07d3f51f
FR		 485 CmdReset = 0x10,
486 CmdRxEnb = 0x08,
487 CmdTxEnb = 0x04,
488 RxBufEmpty = 0x01,
1da177e4 489
275391a4
FR		 490 /* TXPoll register p.5 */
491 HPQ = 0x80, /* Poll cmd on the high prio queue */
492 NPQ = 0x40, /* Poll cmd on the low prio queue */
493 FSWInt = 0x01, /* Forced software interrupt */
494
1da177e4 495 /* Cfg9346Bits */
07d3f51f
FR		 496 Cfg9346_Lock = 0x00,
497 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 498
499 /* rx_mode_bits */
07d3f51f
FR		 500 AcceptErr = 0x20,
501 AcceptRunt = 0x10,
502 AcceptBroadcast = 0x08,
503 AcceptMulticast = 0x04,
504 AcceptMyPhys = 0x02,
505 AcceptAllPhys = 0x01,
1687b566 506#define RX_CONFIG_ACCEPT_MASK 0x3f
1da177e4 507
1da177e4
LT		 508 /* TxConfigBits */
509 TxInterFrameGapShift = 24,
510 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
511
5d06a99f 512 /* Config1 register p.24 */
f162a5d1
FR		 513 LEDS1 = (1 << 7),
514 LEDS0 = (1 << 6),
f162a5d1
FR		 515 Speed_down = (1 << 4),
516 MEMMAP = (1 << 3),
517 IOMAP = (1 << 2),
518 VPD = (1 << 1),
5d06a99f
FR		 519 PMEnable = (1 << 0), /* Power Management Enable */
520
6dccd16b 521 /* Config2 register p. 25 */
57538c4a 522 ClkReqEn = (1 << 7), /* Clock Request Enable */
2ca6cf06 523 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
6dccd16b
FR		 524 PCI_Clock_66MHz = 0x01,
525 PCI_Clock_33MHz = 0x00,
526
61a4dcc2
FR		 527 /* Config3 register p.25 */
528 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
529 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
d58d46b5 530 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
f162a5d1 531 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 532
d58d46b5
FR		 533 /* Config4 register */
534 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
535
5d06a99f 536 /* Config5 register p.27 */
61a4dcc2
FR		 537 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
538 MWF = (1 << 5), /* Accept Multicast wakeup frame */
539 UWF = (1 << 4), /* Accept Unicast wakeup frame */
cecb5fd7 540 Spi_en = (1 << 3),
61a4dcc2 541 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f 542 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
57538c4a 543 ASPM_en = (1 << 0), /* ASPM enable */
5d06a99f 544
1da177e4
LT		 545 /* TBICSR p.28 */
546 TBIReset = 0x80000000,
547 TBILoopback = 0x40000000,
548 TBINwEnable = 0x20000000,
549 TBINwRestart = 0x10000000,
550 TBILinkOk = 0x02000000,
551 TBINwComplete = 0x01000000,
552
553 /* CPlusCmd p.31 */
f162a5d1
FR		 554 EnableBist = (1 << 15), // 8168 8101
555 Mac_dbgo_oe = (1 << 14), // 8168 8101
556 Normal_mode = (1 << 13), // unused
557 Force_half_dup = (1 << 12), // 8168 8101
558 Force_rxflow_en = (1 << 11), // 8168 8101
559 Force_txflow_en = (1 << 10), // 8168 8101
560 Cxpl_dbg_sel = (1 << 9), // 8168 8101
561 ASF = (1 << 8), // 8168 8101
562 PktCntrDisable = (1 << 7), // 8168 8101
563 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 564 RxVlan = (1 << 6),
565 RxChkSum = (1 << 5),
566 PCIDAC = (1 << 4),
567 PCIMulRW = (1 << 3),
0e485150
FR		 568 INTT_0 = 0x0000, // 8168
569 INTT_1 = 0x0001, // 8168
570 INTT_2 = 0x0002, // 8168
571 INTT_3 = 0x0003, // 8168
1da177e4
LT		 572
573 /* rtl8169_PHYstatus */
07d3f51f
FR		 574 TBI_Enable = 0x80,
575 TxFlowCtrl = 0x40,
576 RxFlowCtrl = 0x20,
577 _1000bpsF = 0x10,
578 _100bps = 0x08,
579 _10bps = 0x04,
580 LinkStatus = 0x02,
581 FullDup = 0x01,
1da177e4 582
1da177e4 583 /* _TBICSRBit */
07d3f51f 584 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 585
586 /* DumpCounterCommand */
07d3f51f 587 CounterDump = 0x8,
1da177e4
LT		 588};
589
2b7b4318
FR		 590enum rtl_desc_bit {
591 /* First doubleword. */
1da177e4
LT		 592 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
593 RingEnd = (1 << 30), /* End of descriptor ring */
594 FirstFrag = (1 << 29), /* First segment of a packet */
595 LastFrag = (1 << 28), /* Final segment of a packet */
2b7b4318
FR		 596};
597
598/* Generic case. */
599enum rtl_tx_desc_bit {
600 /* First doubleword. */
601 TD_LSO = (1 << 27), /* Large Send Offload */
602#define TD_MSS_MAX 0x07ffu /* MSS value */
1da177e4 603
2b7b4318
FR		 604 /* Second doubleword. */
605 TxVlanTag = (1 << 17), /* Add VLAN tag */
606};
607
608/* 8169, 8168b and 810x except 8102e. */
609enum rtl_tx_desc_bit_0 {
610 /* First doubleword. */
611#define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
612 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
613 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
614 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
615};
616
617/* 8102e, 8168c and beyond. */
618enum rtl_tx_desc_bit_1 {
619 /* Second doubleword. */
620#define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
621 TD1_IP_CS = (1 << 29), /* Calculate IP checksum */
622 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
623 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
624};
1da177e4 625
2b7b4318
FR		 626static const struct rtl_tx_desc_info {
627 struct {
628 u32 udp;
629 u32 tcp;
630 } checksum;
631 u16 mss_shift;
632 u16 opts_offset;
633} tx_desc_info [] = {
634 [RTL_TD_0] = {
635 .checksum = {
636 .udp = TD0_IP_CS | TD0_UDP_CS,
637 .tcp = TD0_IP_CS | TD0_TCP_CS
638 },
639 .mss_shift = TD0_MSS_SHIFT,
640 .opts_offset = 0
641 },
642 [RTL_TD_1] = {
643 .checksum = {
644 .udp = TD1_IP_CS | TD1_UDP_CS,
645 .tcp = TD1_IP_CS | TD1_TCP_CS
646 },
647 .mss_shift = TD1_MSS_SHIFT,
648 .opts_offset = 1
649 }
650};
651
652enum rtl_rx_desc_bit {
1da177e4
LT		 653 /* Rx private */
654 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
655 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
656
657#define RxProtoUDP (PID1)
658#define RxProtoTCP (PID0)
659#define RxProtoIP (PID1 | PID0)
660#define RxProtoMask RxProtoIP
661
662 IPFail = (1 << 16), /* IP checksum failed */
663 UDPFail = (1 << 15), /* UDP/IP checksum failed */
664 TCPFail = (1 << 14), /* TCP/IP checksum failed */
665 RxVlanTag = (1 << 16), /* VLAN tag available */
666};
667
668#define RsvdMask 0x3fffc000
669
670struct TxDesc {
6cccd6e7
REB		 671 __le32 opts1;
672 __le32 opts2;
673 __le64 addr;
1da177e4
LT		 674};
675
676struct RxDesc {
6cccd6e7
REB		 677 __le32 opts1;
678 __le32 opts2;
679 __le64 addr;
1da177e4
LT		 680};
681
682struct ring_info {
683 struct sk_buff *skb;
684 u32 len;
685 u8 __pad[sizeof(void *) - sizeof(u32)];
686};
687
f23e7fda 688enum features {
ccdffb9a
FR		 689 RTL_FEATURE_WOL = (1 << 0),
690 RTL_FEATURE_MSI = (1 << 1),
691 RTL_FEATURE_GMII = (1 << 2),
f23e7fda
FR		 692};
693
355423d0
IV		 694struct rtl8169_counters {
695 __le64 tx_packets;
696 __le64 rx_packets;
697 __le64 tx_errors;
698 __le32 rx_errors;
699 __le16 rx_missed;
700 __le16 align_errors;
701 __le32 tx_one_collision;
702 __le32 tx_multi_collision;
703 __le64 rx_unicast;
704 __le64 rx_broadcast;
705 __le32 rx_multicast;
706 __le16 tx_aborted;
707 __le16 tx_underun;
708};
709
da78dbff 710enum rtl_flag {
6c4a70c5 711 RTL_FLAG_TASK_ENABLED,
da78dbff
FR		 712 RTL_FLAG_TASK_SLOW_PENDING,
713 RTL_FLAG_TASK_RESET_PENDING,
714 RTL_FLAG_TASK_PHY_PENDING,
715 RTL_FLAG_MAX
716};
717
8027aa24
JW		 718struct rtl8169_stats {
719 u64 packets;
720 u64 bytes;
721 struct u64_stats_sync syncp;
722};
723
1da177e4
LT		 724struct rtl8169_private {
725 void __iomem *mmio_addr; /* memory map physical address */
cecb5fd7 726 struct pci_dev *pci_dev;
c4028958 727 struct net_device *dev;
bea3348e 728 struct napi_struct napi;
b57b7e5a 729 u32 msg_enable;
2b7b4318
FR		 730 u16 txd_version;
731 u16 mac_version;
1da177e4
LT		 732 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
733 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
1da177e4 734 u32 dirty_tx;
8027aa24
JW		 735 struct rtl8169_stats rx_stats;
736 struct rtl8169_stats tx_stats;
1da177e4
LT		 737 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
738 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
739 dma_addr_t TxPhyAddr;
740 dma_addr_t RxPhyAddr;
6f0333b8 741 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
1da177e4 742 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
1da177e4
LT		 743 struct timer_list timer;
744 u16 cp_cmd;
da78dbff
FR		 745
746 u16 event_slow;
c0e45c1c 747
748 struct mdio_ops {
24192210
FR		 749 void (*write)(struct rtl8169_private *, int, int);
750 int (*read)(struct rtl8169_private *, int);
c0e45c1c 751 } mdio_ops;
752
065c27c1 753 struct pll_power_ops {
754 void (*down)(struct rtl8169_private *);
755 void (*up)(struct rtl8169_private *);
756 } pll_power_ops;
757
d58d46b5
FR		 758 struct jumbo_ops {
759 void (*enable)(struct rtl8169_private *);
760 void (*disable)(struct rtl8169_private *);
761 } jumbo_ops;
762
beb1fe18 763 struct csi_ops {
52989f0e
FR		 764 void (*write)(struct rtl8169_private *, int, int);
765 u32 (*read)(struct rtl8169_private *, int);
beb1fe18
HW		 766 } csi_ops;
767
54405cde 768 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
ccdffb9a 769 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
4da19633 770 void (*phy_reset_enable)(struct rtl8169_private *tp);
07ce4064 771 void (*hw_start)(struct net_device *);
4da19633 772 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
1da177e4 773 unsigned int (*link_ok)(void __iomem *);
8b4ab28d 774 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
4422bcd4
FR		 775
776 struct {
da78dbff
FR		 777 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
778 struct mutex mutex;
4422bcd4
FR		 779 struct work_struct work;
780 } wk;
781
f23e7fda 782 unsigned features;
ccdffb9a
FR		 783
784 struct mii_if_info mii;
355423d0 785 struct rtl8169_counters counters;
e1759441 786 u32 saved_wolopts;
e03f33af 787 u32 opts1_mask;
f1e02ed1 788
b6ffd97f
FR		 789 struct rtl_fw {
790 const struct firmware *fw;
1c361efb
FR		 791
792#define RTL_VER_SIZE 32
793
794 char version[RTL_VER_SIZE];
795
796 struct rtl_fw_phy_action {
797 __le32 *code;
798 size_t size;
799 } phy_action;
b6ffd97f 800 } *rtl_fw;
497888cf 801#define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
c558386b
HW		 802
803 u32 ocp_base;
1da177e4
LT		 804};
805
979b6c13 806MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 807MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 808module_param(use_dac, int, 0);
4300e8c7 809MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 810module_param_named(debug, debug.msg_enable, int, 0);
811MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 812MODULE_LICENSE("GPL");
813MODULE_VERSION(RTL8169_VERSION);
bca03d5f 814MODULE_FIRMWARE(FIRMWARE_8168D_1);
815MODULE_FIRMWARE(FIRMWARE_8168D_2);
01dc7fec 816MODULE_FIRMWARE(FIRMWARE_8168E_1);
817MODULE_FIRMWARE(FIRMWARE_8168E_2);
bbb8af75 818MODULE_FIRMWARE(FIRMWARE_8168E_3);
5a5e4443 819MODULE_FIRMWARE(FIRMWARE_8105E_1);
c2218925
HW		 820MODULE_FIRMWARE(FIRMWARE_8168F_1);
821MODULE_FIRMWARE(FIRMWARE_8168F_2);
7e18dca1 822MODULE_FIRMWARE(FIRMWARE_8402_1);
b3d7b2f2 823MODULE_FIRMWARE(FIRMWARE_8411_1);
5598bfe5 824MODULE_FIRMWARE(FIRMWARE_8106E_1);
beb330a4 825MODULE_FIRMWARE(FIRMWARE_8168G_2);
57538c4a 826MODULE_FIRMWARE(FIRMWARE_8168G_3);
1da177e4 827
da78dbff
FR		 828static void rtl_lock_work(struct rtl8169_private *tp)
829{
830 mutex_lock(&tp->wk.mutex);
831}
832
833static void rtl_unlock_work(struct rtl8169_private *tp)
834{
835 mutex_unlock(&tp->wk.mutex);
836}
837
d58d46b5
FR		 838static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
839{
7d7903b2
JL		 840 pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
841 PCI_EXP_DEVCTL_READRQ, force);
d58d46b5
FR		 842}
843
ffc46952
FR		 844struct rtl_cond {
845 bool (*check)(struct rtl8169_private *);
846 const char *msg;
847};
848
849static void rtl_udelay(unsigned int d)
850{
851 udelay(d);
852}
853
854static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
855 void (*delay)(unsigned int), unsigned int d, int n,
856 bool high)
857{
858 int i;
859
860 for (i = 0; i < n; i++) {
861 delay(d);
862 if (c->check(tp) == high)
863 return true;
864 }
82e316ef
FR		 865 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
866 c->msg, !high, n, d);
ffc46952
FR		 867 return false;
868}
869
870static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
871 const struct rtl_cond *c,
872 unsigned int d, int n)
873{
874 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
875}
876
877static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
878 const struct rtl_cond *c,
879 unsigned int d, int n)
880{
881 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
882}
883
884static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
885 const struct rtl_cond *c,
886 unsigned int d, int n)
887{
888 return rtl_loop_wait(tp, c, msleep, d, n, true);
889}
890
891static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
892 const struct rtl_cond *c,
893 unsigned int d, int n)
894{
895 return rtl_loop_wait(tp, c, msleep, d, n, false);
896}
897
898#define DECLARE_RTL_COND(name) \
899static bool name ## _check(struct rtl8169_private *); \
900 \
901static const struct rtl_cond name = { \
902 .check = name ## _check, \
903 .msg = #name \
904}; \
905 \
906static bool name ## _check(struct rtl8169_private *tp)
907
908DECLARE_RTL_COND(rtl_ocpar_cond)
909{
910 void __iomem *ioaddr = tp->mmio_addr;
911
912 return RTL_R32(OCPAR) & OCPAR_FLAG;
913}
914
b646d900 915static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
916{
917 void __iomem *ioaddr = tp->mmio_addr;
b646d900 918
919 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
ffc46952
FR		 920
921 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
922 RTL_R32(OCPDR) : ~0;
b646d900 923}
924
925static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
926{
927 void __iomem *ioaddr = tp->mmio_addr;
b646d900 928
929 RTL_W32(OCPDR, data);
930 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
ffc46952
FR		 931
932 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
933}
934
935DECLARE_RTL_COND(rtl_eriar_cond)
936{
937 void __iomem *ioaddr = tp->mmio_addr;
938
939 return RTL_R32(ERIAR) & ERIAR_FLAG;
b646d900 940}
941
fac5b3ca 942static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
b646d900 943{
fac5b3ca 944 void __iomem *ioaddr = tp->mmio_addr;
b646d900 945
946 RTL_W8(ERIDR, cmd);
947 RTL_W32(ERIAR, 0x800010e8);
948 msleep(2);
ffc46952
FR		 949
950 if (!rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 5))
951 return;
b646d900 952
fac5b3ca 953 ocp_write(tp, 0x1, 0x30, 0x00000001);
b646d900 954}
955
956#define OOB_CMD_RESET 0x00
957#define OOB_CMD_DRIVER_START 0x05
958#define OOB_CMD_DRIVER_STOP 0x06
959
cecb5fd7
FR		 960static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
961{
962 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
963}
964
ffc46952 965DECLARE_RTL_COND(rtl_ocp_read_cond)
b646d900 966{
cecb5fd7 967 u16 reg;
b646d900 968
cecb5fd7 969 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 970
ffc46952 971 return ocp_read(tp, 0x0f, reg) & 0x00000800;
b646d900 972}
973
ffc46952 974static void rtl8168_driver_start(struct rtl8169_private *tp)
b646d900 975{
ffc46952 976 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
b646d900 977
ffc46952
FR		 978 rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
979}
b646d900 980
ffc46952
FR		 981static void rtl8168_driver_stop(struct rtl8169_private *tp)
982{
983 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
4804b3b3 984
ffc46952 985 rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
b646d900 986}
987
4804b3b3 988static int r8168dp_check_dash(struct rtl8169_private *tp)
989{
cecb5fd7 990 u16 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 991
cecb5fd7 992 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
4804b3b3 993}
b646d900 994
c558386b
HW		 995static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
996{
997 if (reg & 0xffff0001) {
998 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
999 return true;
1000 }
1001 return false;
1002}
1003
1004DECLARE_RTL_COND(rtl_ocp_gphy_cond)
1005{
1006 void __iomem *ioaddr = tp->mmio_addr;
1007
1008 return RTL_R32(GPHY_OCP) & OCPAR_FLAG;
1009}
1010
1011static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1012{
1013 void __iomem *ioaddr = tp->mmio_addr;
1014
1015 if (rtl_ocp_reg_failure(tp, reg))
1016 return;
1017
1018 RTL_W32(GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
1019
1020 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
1021}
1022
1023static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
1024{
1025 void __iomem *ioaddr = tp->mmio_addr;
1026
1027 if (rtl_ocp_reg_failure(tp, reg))
1028 return 0;
1029
1030 RTL_W32(GPHY_OCP, reg << 15);
1031
1032 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
1033 (RTL_R32(GPHY_OCP) & 0xffff) : ~0;
1034}
1035
c558386b
HW		 1036static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1037{
1038 void __iomem *ioaddr = tp->mmio_addr;
1039
1040 if (rtl_ocp_reg_failure(tp, reg))
1041 return;
1042
1043 RTL_W32(OCPDR, OCPAR_FLAG | (reg << 15) | data);
c558386b
HW		 1044}
1045
1046static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1047{
1048 void __iomem *ioaddr = tp->mmio_addr;
1049
1050 if (rtl_ocp_reg_failure(tp, reg))
1051 return 0;
1052
1053 RTL_W32(OCPDR, reg << 15);
1054
3a83ad12 1055 return RTL_R32(OCPDR);
c558386b
HW		 1056}
1057
1058#define OCP_STD_PHY_BASE 0xa400
1059
1060static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
1061{
1062 if (reg == 0x1f) {
1063 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
1064 return;
1065 }
1066
1067 if (tp->ocp_base != OCP_STD_PHY_BASE)
1068 reg -= 0x10;
1069
1070 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
1071}
1072
1073static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1074{
1075 if (tp->ocp_base != OCP_STD_PHY_BASE)
1076 reg -= 0x10;
1077
1078 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
1079}
1080
eee3786f 1081static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
1082{
1083 if (reg == 0x1f) {
1084 tp->ocp_base = value << 4;
1085 return;
1086 }
1087
1088 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
1089}
1090
1091static int mac_mcu_read(struct rtl8169_private *tp, int reg)
1092{
1093 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
1094}
1095
ffc46952
FR		 1096DECLARE_RTL_COND(rtl_phyar_cond)
1097{
1098 void __iomem *ioaddr = tp->mmio_addr;
1099
1100 return RTL_R32(PHYAR) & 0x80000000;
1101}
1102
24192210 1103static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1da177e4 1104{
24192210 1105 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 1106
24192210 1107 RTL_W32(PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1da177e4 1108
ffc46952 1109 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
024a07ba 1110 /*
81a95f04
TT		 1111 * According to hardware specs a 20us delay is required after write
1112 * complete indication, but before sending next command.
024a07ba 1113 */
81a95f04 1114 udelay(20);
1da177e4
LT		 1115}
1116
24192210 1117static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1da177e4 1118{
24192210 1119 void __iomem *ioaddr = tp->mmio_addr;
ffc46952 1120 int value;
1da177e4 1121
24192210 1122 RTL_W32(PHYAR, 0x0 | (reg & 0x1f) << 16);
1da177e4 1123
ffc46952
FR		 1124 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1125 RTL_R32(PHYAR) & 0xffff : ~0;
1126
81a95f04
TT		 1127 /*
1128 * According to hardware specs a 20us delay is required after read
1129 * complete indication, but before sending next command.
1130 */
1131 udelay(20);
1132
1da177e4
LT		 1133 return value;
1134}
1135
24192210 1136static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
c0e45c1c 1137{
24192210 1138 void __iomem *ioaddr = tp->mmio_addr;
c0e45c1c 1139
24192210 1140 RTL_W32(OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
c0e45c1c 1141 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
1142 RTL_W32(EPHY_RXER_NUM, 0);
1143
ffc46952 1144 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
c0e45c1c 1145}
1146
24192210 1147static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
c0e45c1c 1148{
24192210
FR		 1149 r8168dp_1_mdio_access(tp, reg,
1150 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
c0e45c1c 1151}
1152
24192210 1153static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
c0e45c1c 1154{
24192210 1155 void __iomem *ioaddr = tp->mmio_addr;
c0e45c1c 1156
24192210 1157 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
c0e45c1c 1158
1159 mdelay(1);
1160 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
1161 RTL_W32(EPHY_RXER_NUM, 0);
1162
ffc46952
FR		 1163 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1164 RTL_R32(OCPDR) & OCPDR_DATA_MASK : ~0;
c0e45c1c 1165}
1166
e6de30d6 1167#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1168
1169static void r8168dp_2_mdio_start(void __iomem *ioaddr)
1170{
1171 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1172}
1173
1174static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
1175{
1176 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1177}
1178
24192210 1179static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
e6de30d6 1180{
24192210
FR		 1181 void __iomem *ioaddr = tp->mmio_addr;
1182
e6de30d6 1183 r8168dp_2_mdio_start(ioaddr);
1184
24192210 1185 r8169_mdio_write(tp, reg, value);
e6de30d6 1186
1187 r8168dp_2_mdio_stop(ioaddr);
1188}
1189
24192210 1190static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
e6de30d6 1191{
24192210 1192 void __iomem *ioaddr = tp->mmio_addr;
e6de30d6 1193 int value;
1194
1195 r8168dp_2_mdio_start(ioaddr);
1196
24192210 1197 value = r8169_mdio_read(tp, reg);
e6de30d6 1198
1199 r8168dp_2_mdio_stop(ioaddr);
1200
1201 return value;
1202}
1203
4da19633 1204static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
dacf8154 1205{
24192210 1206 tp->mdio_ops.write(tp, location, val);
dacf8154
FR		 1207}
1208
4da19633 1209static int rtl_readphy(struct rtl8169_private *tp, int location)
1210{
24192210 1211 return tp->mdio_ops.read(tp, location);
4da19633 1212}
1213
1214static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1215{
1216 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1217}
1218
1219static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
daf9df6d 1220{
1221 int val;
1222
4da19633 1223 val = rtl_readphy(tp, reg_addr);
1224 rtl_writephy(tp, reg_addr, (val | p) & ~m);
daf9df6d 1225}
1226
ccdffb9a
FR		 1227static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1228 int val)
1229{
1230 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1231
4da19633 1232 rtl_writephy(tp, location, val);
ccdffb9a
FR		 1233}
1234
1235static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1236{
1237 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1238
4da19633 1239 return rtl_readphy(tp, location);
ccdffb9a
FR		 1240}
1241
ffc46952
FR		 1242DECLARE_RTL_COND(rtl_ephyar_cond)
1243{
1244 void __iomem *ioaddr = tp->mmio_addr;
1245
1246 return RTL_R32(EPHYAR) & EPHYAR_FLAG;
1247}
1248
fdf6fc06 1249static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
dacf8154 1250{
fdf6fc06 1251 void __iomem *ioaddr = tp->mmio_addr;
dacf8154
FR		 1252
1253 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1254 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1255
ffc46952
FR		 1256 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1257
1258 udelay(10);
dacf8154
FR		 1259}
1260
fdf6fc06 1261static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
dacf8154 1262{
fdf6fc06 1263 void __iomem *ioaddr = tp->mmio_addr;
dacf8154
FR		 1264
1265 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1266
ffc46952
FR		 1267 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1268 RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0;
dacf8154
FR		 1269}
1270
fdf6fc06
FR		 1271static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1272 u32 val, int type)
133ac40a 1273{
fdf6fc06 1274 void __iomem *ioaddr = tp->mmio_addr;
133ac40a
HW		 1275
1276 BUG_ON((addr & 3) || (mask == 0));
1277 RTL_W32(ERIDR, val);
1278 RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1279
ffc46952 1280 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
133ac40a
HW		 1281}
1282
fdf6fc06 1283static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
133ac40a 1284{
fdf6fc06 1285 void __iomem *ioaddr = tp->mmio_addr;
133ac40a
HW		 1286
1287 RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1288
ffc46952
FR		 1289 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1290 RTL_R32(ERIDR) : ~0;
133ac40a
HW		 1291}
1292
fdf6fc06
FR		 1293static void rtl_w1w0_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1294 u32 m, int type)
133ac40a
HW		 1295{
1296 u32 val;
1297
fdf6fc06
FR		 1298 val = rtl_eri_read(tp, addr, type);
1299 rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
133ac40a
HW		 1300}
1301
c28aa385 1302struct exgmac_reg {
1303 u16 addr;
1304 u16 mask;
1305 u32 val;
1306};
1307
fdf6fc06 1308static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
c28aa385 1309 const struct exgmac_reg *r, int len)
1310{
1311 while (len-- > 0) {
fdf6fc06 1312 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
c28aa385 1313 r++;
1314 }
1315}
1316
ffc46952
FR		 1317DECLARE_RTL_COND(rtl_efusear_cond)
1318{
1319 void __iomem *ioaddr = tp->mmio_addr;
1320
1321 return RTL_R32(EFUSEAR) & EFUSEAR_FLAG;
1322}
1323
fdf6fc06 1324static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
daf9df6d 1325{
fdf6fc06 1326 void __iomem *ioaddr = tp->mmio_addr;
daf9df6d 1327
1328 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1329
ffc46952
FR		 1330 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1331 RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
daf9df6d 1332}
1333
9085cdfa
FR		 1334static u16 rtl_get_events(struct rtl8169_private *tp)
1335{
1336 void __iomem *ioaddr = tp->mmio_addr;
1337
1338 return RTL_R16(IntrStatus);
1339}
1340
1341static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1342{
1343 void __iomem *ioaddr = tp->mmio_addr;
1344
1345 RTL_W16(IntrStatus, bits);
1346 mmiowb();
1347}
1348
1349static void rtl_irq_disable(struct rtl8169_private *tp)
1350{
1351 void __iomem *ioaddr = tp->mmio_addr;
1352
1353 RTL_W16(IntrMask, 0);
1354 mmiowb();
1355}
1356
3e990ff5
FR		 1357static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1358{
1359 void __iomem *ioaddr = tp->mmio_addr;
1360
1361 RTL_W16(IntrMask, bits);
1362}
1363
da78dbff
FR		 1364#define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1365#define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1366#define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1367
1368static void rtl_irq_enable_all(struct rtl8169_private *tp)
1369{
1370 rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1371}
1372
811fd301 1373static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1da177e4 1374{
811fd301 1375 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 1376
9085cdfa 1377 rtl_irq_disable(tp);
da78dbff 1378 rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
811fd301 1379 RTL_R8(ChipCmd);
1da177e4
LT		 1380}
1381
4da19633 1382static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1da177e4 1383{
4da19633 1384 void __iomem *ioaddr = tp->mmio_addr;
1385
1da177e4
LT		 1386 return RTL_R32(TBICSR) & TBIReset;
1387}
1388
4da19633 1389static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1da177e4 1390{
4da19633 1391 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 1392}
1393
1394static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1395{
1396 return RTL_R32(TBICSR) & TBILinkOk;
1397}
1398
1399static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1400{
1401 return RTL_R8(PHYstatus) & LinkStatus;
1402}
1403
4da19633 1404static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1da177e4 1405{
4da19633 1406 void __iomem *ioaddr = tp->mmio_addr;
1407
1da177e4
LT		 1408 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1409}
1410
4da19633 1411static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1da177e4
LT		 1412{
1413 unsigned int val;
1414
4da19633 1415 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1416 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1da177e4
LT		 1417}
1418
70090424
HW		 1419static void rtl_link_chg_patch(struct rtl8169_private *tp)
1420{
1421 void __iomem *ioaddr = tp->mmio_addr;
1422 struct net_device *dev = tp->dev;
1423
1424 if (!netif_running(dev))
1425 return;
1426
b3d7b2f2
HW		 1427 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1428 tp->mac_version == RTL_GIGA_MAC_VER_38) {
70090424 1429 if (RTL_R8(PHYstatus) & _1000bpsF) {
fdf6fc06
FR		 1430 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1431 ERIAR_EXGMAC);
1432 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1433 ERIAR_EXGMAC);
70090424 1434 } else if (RTL_R8(PHYstatus) & _100bps) {
fdf6fc06
FR		 1435 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1436 ERIAR_EXGMAC);
1437 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1438 ERIAR_EXGMAC);
70090424 1439 } else {
fdf6fc06
FR		 1440 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1441 ERIAR_EXGMAC);
1442 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1443 ERIAR_EXGMAC);
70090424
HW		 1444 }
1445 /* Reset packet filter */
fdf6fc06 1446 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
70090424 1447 ERIAR_EXGMAC);
fdf6fc06 1448 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
70090424 1449 ERIAR_EXGMAC);
c2218925
HW		 1450 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1451 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1452 if (RTL_R8(PHYstatus) & _1000bpsF) {
fdf6fc06
FR		 1453 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1454 ERIAR_EXGMAC);
1455 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1456 ERIAR_EXGMAC);
c2218925 1457 } else {
fdf6fc06
FR		 1458 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1459 ERIAR_EXGMAC);
1460 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1461 ERIAR_EXGMAC);
c2218925 1462 }
7e18dca1
HW		 1463 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1464 if (RTL_R8(PHYstatus) & _10bps) {
fdf6fc06
FR		 1465 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1466 ERIAR_EXGMAC);
1467 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1468 ERIAR_EXGMAC);
7e18dca1 1469 } else {
fdf6fc06
FR		 1470 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1471 ERIAR_EXGMAC);
7e18dca1 1472 }
70090424
HW		 1473 }
1474}
1475
e4fbce74 1476static void __rtl8169_check_link_status(struct net_device *dev,
cecb5fd7
FR		 1477 struct rtl8169_private *tp,
1478 void __iomem *ioaddr, bool pm)
1da177e4 1479{
1da177e4 1480 if (tp->link_ok(ioaddr)) {
70090424 1481 rtl_link_chg_patch(tp);
e1759441 1482 /* This is to cancel a scheduled suspend if there's one. */
e4fbce74
RW		 1483 if (pm)
1484 pm_request_resume(&tp->pci_dev->dev);
1da177e4 1485 netif_carrier_on(dev);
1519e57f
FR		 1486 if (net_ratelimit())
1487 netif_info(tp, ifup, dev, "link up\n");
b57b7e5a 1488 } else {
1da177e4 1489 netif_carrier_off(dev);
bf82c189 1490 netif_info(tp, ifdown, dev, "link down\n");
e4fbce74 1491 if (pm)
10953db8 1492 pm_schedule_suspend(&tp->pci_dev->dev, 5000);
b57b7e5a 1493 }
1da177e4
LT		 1494}
1495
e4fbce74
RW		 1496static void rtl8169_check_link_status(struct net_device *dev,
1497 struct rtl8169_private *tp,
1498 void __iomem *ioaddr)
1499{
1500 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1501}
1502
e1759441
RW		 1503#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1504
1505static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
61a4dcc2 1506{
61a4dcc2
FR		 1507 void __iomem *ioaddr = tp->mmio_addr;
1508 u8 options;
e1759441 1509 u32 wolopts = 0;
61a4dcc2
FR		 1510
1511 options = RTL_R8(Config1);
1512 if (!(options & PMEnable))
e1759441 1513 return 0;
61a4dcc2
FR		 1514
1515 options = RTL_R8(Config3);
1516 if (options & LinkUp)
e1759441 1517 wolopts |= WAKE_PHY;
61a4dcc2 1518 if (options & MagicPacket)
e1759441 1519 wolopts |= WAKE_MAGIC;
61a4dcc2
FR		 1520
1521 options = RTL_R8(Config5);
1522 if (options & UWF)
e1759441 1523 wolopts |= WAKE_UCAST;
61a4dcc2 1524 if (options & BWF)
e1759441 1525 wolopts |= WAKE_BCAST;
61a4dcc2 1526 if (options & MWF)
e1759441 1527 wolopts |= WAKE_MCAST;
61a4dcc2 1528
e1759441 1529 return wolopts;
61a4dcc2
FR		 1530}
1531
e1759441 1532static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
61a4dcc2
FR		 1533{
1534 struct rtl8169_private *tp = netdev_priv(dev);
e1759441 1535
da78dbff 1536 rtl_lock_work(tp);
e1759441
RW		 1537
1538 wol->supported = WAKE_ANY;
1539 wol->wolopts = __rtl8169_get_wol(tp);
1540
da78dbff 1541 rtl_unlock_work(tp);
e1759441
RW		 1542}
1543
1544static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1545{
61a4dcc2 1546 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1547 unsigned int i;
350f7596 1548 static const struct {
61a4dcc2
FR		 1549 u32 opt;
1550 u16 reg;
1551 u8 mask;
1552 } cfg[] = {
61a4dcc2
FR		 1553 { WAKE_PHY, Config3, LinkUp },
1554 { WAKE_MAGIC, Config3, MagicPacket },
1555 { WAKE_UCAST, Config5, UWF },
1556 { WAKE_BCAST, Config5, BWF },
1557 { WAKE_MCAST, Config5, MWF },
1558 { WAKE_ANY, Config5, LanWake }
1559 };
851e6022 1560 u8 options;
61a4dcc2 1561
61a4dcc2
FR		 1562 RTL_W8(Cfg9346, Cfg9346_Unlock);
1563
1564 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
851e6022 1565 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
e1759441 1566 if (wolopts & cfg[i].opt)
61a4dcc2
FR		 1567 options |= cfg[i].mask;
1568 RTL_W8(cfg[i].reg, options);
1569 }
1570
851e6022
FR		 1571 switch (tp->mac_version) {
1572 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1573 options = RTL_R8(Config1) & ~PMEnable;
1574 if (wolopts)
1575 options |= PMEnable;
1576 RTL_W8(Config1, options);
1577 break;
1578 default:
d387b427
FR		 1579 options = RTL_R8(Config2) & ~PME_SIGNAL;
1580 if (wolopts)
1581 options |= PME_SIGNAL;
1582 RTL_W8(Config2, options);
851e6022
FR		 1583 break;
1584 }
1585
61a4dcc2 1586 RTL_W8(Cfg9346, Cfg9346_Lock);
e1759441
RW		 1587}
1588
1589static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1590{
1591 struct rtl8169_private *tp = netdev_priv(dev);
1592
da78dbff 1593 rtl_lock_work(tp);
61a4dcc2 1594
f23e7fda
FR		 1595 if (wol->wolopts)
1596 tp->features |= RTL_FEATURE_WOL;
1597 else
1598 tp->features &= ~RTL_FEATURE_WOL;
e1759441 1599 __rtl8169_set_wol(tp, wol->wolopts);
da78dbff
FR		 1600
1601 rtl_unlock_work(tp);
61a4dcc2 1602
ea80907f 1603 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1604
61a4dcc2
FR		 1605 return 0;
1606}
1607
31bd204f
FR		 1608static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1609{
85bffe6c 1610 return rtl_chip_infos[tp->mac_version].fw_name;
31bd204f
FR		 1611}
1612
1da177e4
LT		 1613static void rtl8169_get_drvinfo(struct net_device *dev,
1614 struct ethtool_drvinfo *info)
1615{
1616 struct rtl8169_private *tp = netdev_priv(dev);
b6ffd97f 1617 struct rtl_fw *rtl_fw = tp->rtl_fw;
1da177e4 1618
68aad78c
RJ		 1619 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1620 strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1621 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1c361efb 1622 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
8ac72d16
RJ		 1623 if (!IS_ERR_OR_NULL(rtl_fw))
1624 strlcpy(info->fw_version, rtl_fw->version,
1625 sizeof(info->fw_version));
1da177e4
LT		 1626}
1627
1628static int rtl8169_get_regs_len(struct net_device *dev)
1629{
1630 return R8169_REGS_SIZE;
1631}
1632
1633static int rtl8169_set_speed_tbi(struct net_device *dev,
54405cde 1634 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1da177e4
LT		 1635{
1636 struct rtl8169_private *tp = netdev_priv(dev);
1637 void __iomem *ioaddr = tp->mmio_addr;
1638 int ret = 0;
1639 u32 reg;
1640
1641 reg = RTL_R32(TBICSR);
1642 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1643 (duplex == DUPLEX_FULL)) {
1644 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1645 } else if (autoneg == AUTONEG_ENABLE)
1646 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1647 else {
bf82c189
JP		 1648 netif_warn(tp, link, dev,
1649 "incorrect speed setting refused in TBI mode\n");
1da177e4
LT		 1650 ret = -EOPNOTSUPP;
1651 }
1652
1653 return ret;
1654}
1655
1656static int rtl8169_set_speed_xmii(struct net_device *dev,
54405cde 1657 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1da177e4
LT		 1658{
1659 struct rtl8169_private *tp = netdev_priv(dev);
3577aa1b 1660 int giga_ctrl, bmcr;
54405cde 1661 int rc = -EINVAL;
1da177e4 1662
716b50a3 1663 rtl_writephy(tp, 0x1f, 0x0000);
1da177e4
LT		 1664
1665 if (autoneg == AUTONEG_ENABLE) {
3577aa1b 1666 int auto_nego;
1667
4da19633 1668 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
54405cde
ON		 1669 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1670 ADVERTISE_100HALF | ADVERTISE_100FULL);
1671
1672 if (adv & ADVERTISED_10baseT_Half)
1673 auto_nego |= ADVERTISE_10HALF;
1674 if (adv & ADVERTISED_10baseT_Full)
1675 auto_nego |= ADVERTISE_10FULL;
1676 if (adv & ADVERTISED_100baseT_Half)
1677 auto_nego |= ADVERTISE_100HALF;
1678 if (adv & ADVERTISED_100baseT_Full)
1679 auto_nego |= ADVERTISE_100FULL;
1680
3577aa1b 1681 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1da177e4 1682
4da19633 1683 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
3577aa1b 1684 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
bcf0bf90 1685
3577aa1b 1686 /* The 8100e/8101e/8102e do Fast Ethernet only. */
826e6cbd 1687 if (tp->mii.supports_gmii) {
54405cde
ON		 1688 if (adv & ADVERTISED_1000baseT_Half)
1689 giga_ctrl |= ADVERTISE_1000HALF;
1690 if (adv & ADVERTISED_1000baseT_Full)
1691 giga_ctrl |= ADVERTISE_1000FULL;
1692 } else if (adv & (ADVERTISED_1000baseT_Half |
1693 ADVERTISED_1000baseT_Full)) {
bf82c189
JP		 1694 netif_info(tp, link, dev,
1695 "PHY does not support 1000Mbps\n");
54405cde 1696 goto out;
bcf0bf90 1697 }
1da177e4 1698
3577aa1b 1699 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1700
4da19633 1701 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1702 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
3577aa1b 1703 } else {
1704 giga_ctrl = 0;
1705
1706 if (speed == SPEED_10)
1707 bmcr = 0;
1708 else if (speed == SPEED_100)
1709 bmcr = BMCR_SPEED100;
1710 else
54405cde 1711 goto out;
3577aa1b 1712
1713 if (duplex == DUPLEX_FULL)
1714 bmcr |= BMCR_FULLDPLX;
2584fbc3
RS		 1715 }
1716
4da19633 1717 rtl_writephy(tp, MII_BMCR, bmcr);
3577aa1b 1718
cecb5fd7
FR		 1719 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1720 tp->mac_version == RTL_GIGA_MAC_VER_03) {
3577aa1b 1721 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
4da19633 1722 rtl_writephy(tp, 0x17, 0x2138);
1723 rtl_writephy(tp, 0x0e, 0x0260);
3577aa1b 1724 } else {
4da19633 1725 rtl_writephy(tp, 0x17, 0x2108);
1726 rtl_writephy(tp, 0x0e, 0x0000);
3577aa1b 1727 }
1728 }
1729
54405cde
ON		 1730 rc = 0;
1731out:
1732 return rc;
1da177e4
LT		 1733}
1734
1735static int rtl8169_set_speed(struct net_device *dev,
54405cde 1736 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1da177e4
LT		 1737{
1738 struct rtl8169_private *tp = netdev_priv(dev);
1739 int ret;
1740
54405cde 1741 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
4876cc1e
FR		 1742 if (ret < 0)
1743 goto out;
1da177e4 1744
4876cc1e
FR		 1745 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1746 (advertising & ADVERTISED_1000baseT_Full)) {
1da177e4 1747 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
4876cc1e
FR		 1748 }
1749out:
1da177e4
LT		 1750 return ret;
1751}
1752
1753static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1754{
1755 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4
LT		 1756 int ret;
1757
4876cc1e
FR		 1758 del_timer_sync(&tp->timer);
1759
da78dbff 1760 rtl_lock_work(tp);
cecb5fd7 1761 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
25db0338 1762 cmd->duplex, cmd->advertising);
da78dbff 1763 rtl_unlock_work(tp);
5b0384f4 1764
1da177e4
LT		 1765 return ret;
1766}
1767
c8f44aff
MM		 1768static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1769 netdev_features_t features)
1da177e4 1770{
d58d46b5
FR		 1771 struct rtl8169_private *tp = netdev_priv(dev);
1772
2b7b4318 1773 if (dev->mtu > TD_MSS_MAX)
350fb32a 1774 features &= ~NETIF_F_ALL_TSO;
1da177e4 1775
d58d46b5
FR		 1776 if (dev->mtu > JUMBO_1K &&
1777 !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1778 features &= ~NETIF_F_IP_CSUM;
1779
350fb32a 1780 return features;
1da177e4
LT		 1781}
1782
da78dbff
FR		 1783static void __rtl8169_set_features(struct net_device *dev,
1784 netdev_features_t features)
1da177e4
LT		 1785{
1786 struct rtl8169_private *tp = netdev_priv(dev);
6bbe021d 1787 netdev_features_t changed = features ^ dev->features;
da78dbff 1788 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 1789
6bbe021d
BG		 1790 if (!(changed & (NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)))
1791 return;
1da177e4 1792
6bbe021d
BG		 1793 if (changed & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)) {
1794 if (features & NETIF_F_RXCSUM)
1795 tp->cp_cmd |= RxChkSum;
1796 else
1797 tp->cp_cmd &= ~RxChkSum;
350fb32a 1798
6bbe021d
BG		 1799 if (dev->features & NETIF_F_HW_VLAN_RX)
1800 tp->cp_cmd |= RxVlan;
1801 else
1802 tp->cp_cmd &= ~RxVlan;
1803
1804 RTL_W16(CPlusCmd, tp->cp_cmd);
1805 RTL_R16(CPlusCmd);
1806 }
1807 if (changed & NETIF_F_RXALL) {
1808 int tmp = (RTL_R32(RxConfig) & ~(AcceptErr | AcceptRunt));
1809 if (features & NETIF_F_RXALL)
1810 tmp |= (AcceptErr | AcceptRunt);
1811 RTL_W32(RxConfig, tmp);
1812 }
da78dbff 1813}
1da177e4 1814
da78dbff
FR		 1815static int rtl8169_set_features(struct net_device *dev,
1816 netdev_features_t features)
1817{
1818 struct rtl8169_private *tp = netdev_priv(dev);
1819
1820 rtl_lock_work(tp);
1821 __rtl8169_set_features(dev, features);
1822 rtl_unlock_work(tp);
1da177e4
LT		 1823
1824 return 0;
1825}
1826
da78dbff 1827
810f4893 1828static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1da177e4 1829{
eab6d18d 1830 return (vlan_tx_tag_present(skb)) ?
1da177e4
LT		 1831 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1832}
1833
7a8fc77b 1834static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1da177e4
LT		 1835{
1836 u32 opts2 = le32_to_cpu(desc->opts2);
1da177e4 1837
7a8fc77b
FR		 1838 if (opts2 & RxVlanTag)
1839 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
1da177e4
LT		 1840}
1841
ccdffb9a 1842static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1843{
1844 struct rtl8169_private *tp = netdev_priv(dev);
1845 void __iomem *ioaddr = tp->mmio_addr;
1846 u32 status;
1847
1848 cmd->supported =
1849 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1850 cmd->port = PORT_FIBRE;
1851 cmd->transceiver = XCVR_INTERNAL;
1852
1853 status = RTL_R32(TBICSR);
1854 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1855 cmd->autoneg = !!(status & TBINwEnable);
1856
70739497 1857 ethtool_cmd_speed_set(cmd, SPEED_1000);
1da177e4 1858 cmd->duplex = DUPLEX_FULL; /* Always set */
ccdffb9a
FR		 1859
1860 return 0;
1da177e4
LT		 1861}
1862
ccdffb9a 1863static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1864{
1865 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a
FR		 1866
1867 return mii_ethtool_gset(&tp->mii, cmd);
1da177e4
LT		 1868}
1869
1870static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1871{
1872 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1873 int rc;
1da177e4 1874
da78dbff 1875 rtl_lock_work(tp);
ccdffb9a 1876 rc = tp->get_settings(dev, cmd);
da78dbff 1877 rtl_unlock_work(tp);
1da177e4 1878
ccdffb9a 1879 return rc;
1da177e4
LT		 1880}
1881
1882static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1883 void *p)
1884{
5b0384f4 1885 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 1886
5b0384f4
FR		 1887 if (regs->len > R8169_REGS_SIZE)
1888 regs->len = R8169_REGS_SIZE;
1da177e4 1889
da78dbff 1890 rtl_lock_work(tp);
5b0384f4 1891 memcpy_fromio(p, tp->mmio_addr, regs->len);
da78dbff 1892 rtl_unlock_work(tp);
1da177e4
LT		 1893}
1894
b57b7e5a
SH		 1895static u32 rtl8169_get_msglevel(struct net_device *dev)
1896{
1897 struct rtl8169_private *tp = netdev_priv(dev);
1898
1899 return tp->msg_enable;
1900}
1901
1902static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1903{
1904 struct rtl8169_private *tp = netdev_priv(dev);
1905
1906 tp->msg_enable = value;
1907}
1908
d4a3a0fc
SH		 1909static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1910 "tx_packets",
1911 "rx_packets",
1912 "tx_errors",
1913 "rx_errors",
1914 "rx_missed",
1915 "align_errors",
1916 "tx_single_collisions",
1917 "tx_multi_collisions",
1918 "unicast",
1919 "broadcast",
1920 "multicast",
1921 "tx_aborted",
1922 "tx_underrun",
1923};
1924
b9f2c044 1925static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1926{
b9f2c044
JG		 1927 switch (sset) {
1928 case ETH_SS_STATS:
1929 return ARRAY_SIZE(rtl8169_gstrings);
1930 default:
1931 return -EOPNOTSUPP;
1932 }
d4a3a0fc
SH		 1933}
1934
ffc46952
FR		 1935DECLARE_RTL_COND(rtl_counters_cond)
1936{
1937 void __iomem *ioaddr = tp->mmio_addr;
1938
1939 return RTL_R32(CounterAddrLow) & CounterDump;
1940}
1941
355423d0 1942static void rtl8169_update_counters(struct net_device *dev)
d4a3a0fc
SH		 1943{
1944 struct rtl8169_private *tp = netdev_priv(dev);
1945 void __iomem *ioaddr = tp->mmio_addr;
cecb5fd7 1946 struct device *d = &tp->pci_dev->dev;
d4a3a0fc
SH		 1947 struct rtl8169_counters *counters;
1948 dma_addr_t paddr;
1949 u32 cmd;
1950
355423d0
IV		 1951 /*
1952 * Some chips are unable to dump tally counters when the receiver
1953 * is disabled.
1954 */
1955 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1956 return;
d4a3a0fc 1957
48addcc9 1958 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
d4a3a0fc
SH		 1959 if (!counters)
1960 return;
1961
1962 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
284901a9 1963 cmd = (u64)paddr & DMA_BIT_MASK(32);
d4a3a0fc
SH		 1964 RTL_W32(CounterAddrLow, cmd);
1965 RTL_W32(CounterAddrLow, cmd | CounterDump);
1966
ffc46952
FR		 1967 if (rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000))
1968 memcpy(&tp->counters, counters, sizeof(*counters));
d4a3a0fc
SH		 1969
1970 RTL_W32(CounterAddrLow, 0);
1971 RTL_W32(CounterAddrHigh, 0);
1972
48addcc9 1973 dma_free_coherent(d, sizeof(*counters), counters, paddr);
d4a3a0fc
SH		 1974}
1975
355423d0
IV		 1976static void rtl8169_get_ethtool_stats(struct net_device *dev,
1977 struct ethtool_stats *stats, u64 *data)
1978{
1979 struct rtl8169_private *tp = netdev_priv(dev);
1980
1981 ASSERT_RTNL();
1982
1983 rtl8169_update_counters(dev);
1984
1985 data[0] = le64_to_cpu(tp->counters.tx_packets);
1986 data[1] = le64_to_cpu(tp->counters.rx_packets);
1987 data[2] = le64_to_cpu(tp->counters.tx_errors);
1988 data[3] = le32_to_cpu(tp->counters.rx_errors);
1989 data[4] = le16_to_cpu(tp->counters.rx_missed);
1990 data[5] = le16_to_cpu(tp->counters.align_errors);
1991 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1992 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1993 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1994 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1995 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1996 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1997 data[12] = le16_to_cpu(tp->counters.tx_underun);
1998}
1999
d4a3a0fc
SH		 2000static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2001{
2002 switch(stringset) {
2003 case ETH_SS_STATS:
2004 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
2005 break;
2006 }
2007}
2008
7282d491 2009static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 2010 .get_drvinfo = rtl8169_get_drvinfo,
2011 .get_regs_len = rtl8169_get_regs_len,
2012 .get_link = ethtool_op_get_link,
2013 .get_settings = rtl8169_get_settings,
2014 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 2015 .get_msglevel = rtl8169_get_msglevel,
2016 .set_msglevel = rtl8169_set_msglevel,
1da177e4 2017 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 2018 .get_wol = rtl8169_get_wol,
2019 .set_wol = rtl8169_set_wol,
d4a3a0fc 2020 .get_strings = rtl8169_get_strings,
b9f2c044 2021 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 2022 .get_ethtool_stats = rtl8169_get_ethtool_stats,
e1593bb1 2023 .get_ts_info = ethtool_op_get_ts_info,
1da177e4
LT		 2024};
2025
07d3f51f 2026static void rtl8169_get_mac_version(struct rtl8169_private *tp,
5d320a20 2027 struct net_device *dev, u8 default_version)
1da177e4 2028{
5d320a20 2029 void __iomem *ioaddr = tp->mmio_addr;
0e485150
FR		 2030 /*
2031 * The driver currently handles the 8168Bf and the 8168Be identically
2032 * but they can be identified more specifically through the test below
2033 * if needed:
2034 *
2035 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 2036 *
2037 * Same thing for the 8101Eb and the 8101Ec:
2038 *
2039 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 2040 */
3744100e 2041 static const struct rtl_mac_info {
1da177e4 2042 u32 mask;
e3cf0cc0 2043 u32 val;
1da177e4
LT		 2044 int mac_version;
2045 } mac_info[] = {
c558386b 2046 /* 8168G family. */
57538c4a 2047 { 0x7cf00000, 0x50900000, RTL_GIGA_MAC_VER_42 },
c558386b
HW		 2048 { 0x7cf00000, 0x4c100000, RTL_GIGA_MAC_VER_41 },
2049 { 0x7cf00000, 0x4c000000, RTL_GIGA_MAC_VER_40 },
2050
c2218925 2051 /* 8168F family. */
b3d7b2f2 2052 { 0x7c800000, 0x48800000, RTL_GIGA_MAC_VER_38 },
c2218925
HW		 2053 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
2054 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
2055
01dc7fec 2056 /* 8168E family. */
70090424 2057 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
01dc7fec 2058 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
2059 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
2060 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
2061
5b538df9 2062 /* 8168D family. */
daf9df6d 2063 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
2064 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
daf9df6d 2065 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
5b538df9 2066
e6de30d6 2067 /* 8168DP family. */
2068 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
2069 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
4804b3b3 2070 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
e6de30d6 2071
ef808d50 2072 /* 8168C family. */
17c99297 2073 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
ef3386f0 2074 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 2075 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 2076 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 2077 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
2078 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 2079 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
6fb07058 2080 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
ef808d50 2081 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 2082
2083 /* 8168B family. */
2084 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
2085 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
2086 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
2087 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
2088
2089 /* 8101 family. */
5598bfe5
HW		 2090 { 0x7cf00000, 0x44900000, RTL_GIGA_MAC_VER_39 },
2091 { 0x7c800000, 0x44800000, RTL_GIGA_MAC_VER_39 },
7e18dca1 2092 { 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37 },
36a0e6c2 2093 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
5a5e4443
HW		 2094 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
2095 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
2096 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2857ffb7
FR		 2097 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
2098 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
2099 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
2100 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
2101 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
2102 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 2103 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 2104 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 2105 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 2106 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
2107 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 2108 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
2109 /* FIXME: where did these entries come from ? -- FR */
2110 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
2111 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
2112
2113 /* 8110 family. */
2114 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
2115 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
2116 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
2117 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
2118 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
2119 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
2120
f21b75e9
JD		 2121 /* Catch-all */
2122 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
3744100e
FR		 2123 };
2124 const struct rtl_mac_info *p = mac_info;
1da177e4
LT		 2125 u32 reg;
2126
e3cf0cc0
FR		 2127 reg = RTL_R32(TxConfig);
2128 while ((reg & p->mask) != p->val)
1da177e4
LT		 2129 p++;
2130 tp->mac_version = p->mac_version;
5d320a20
FR		 2131
2132 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2133 netif_notice(tp, probe, dev,
2134 "unknown MAC, using family default\n");
2135 tp->mac_version = default_version;
2136 }
1da177e4
LT		 2137}
2138
2139static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2140{
bcf0bf90 2141 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 2142}
2143
867763c1
FR		 2144struct phy_reg {
2145 u16 reg;
2146 u16 val;
2147};
2148
4da19633 2149static void rtl_writephy_batch(struct rtl8169_private *tp,
2150 const struct phy_reg *regs, int len)
867763c1
FR		 2151{
2152 while (len-- > 0) {
4da19633 2153 rtl_writephy(tp, regs->reg, regs->val);
867763c1
FR		 2154 regs++;
2155 }
2156}
2157
bca03d5f 2158#define PHY_READ 0x00000000
2159#define PHY_DATA_OR 0x10000000
2160#define PHY_DATA_AND 0x20000000
2161#define PHY_BJMPN 0x30000000
eee3786f 2162#define PHY_MDIO_CHG 0x40000000
bca03d5f 2163#define PHY_CLEAR_READCOUNT 0x70000000
2164#define PHY_WRITE 0x80000000
2165#define PHY_READCOUNT_EQ_SKIP 0x90000000
2166#define PHY_COMP_EQ_SKIPN 0xa0000000
2167#define PHY_COMP_NEQ_SKIPN 0xb0000000
2168#define PHY_WRITE_PREVIOUS 0xc0000000
2169#define PHY_SKIPN 0xd0000000
2170#define PHY_DELAY_MS 0xe0000000
bca03d5f 2171
960aee6c
HW		 2172struct fw_info {
2173 u32 magic;
2174 char version[RTL_VER_SIZE];
2175 __le32 fw_start;
2176 __le32 fw_len;
2177 u8 chksum;
2178} __packed;
2179
1c361efb
FR		 2180#define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2181
2182static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
bca03d5f 2183{
b6ffd97f 2184 const struct firmware *fw = rtl_fw->fw;
960aee6c 2185 struct fw_info *fw_info = (struct fw_info *)fw->data;
1c361efb
FR		 2186 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2187 char *version = rtl_fw->version;
2188 bool rc = false;
2189
2190 if (fw->size < FW_OPCODE_SIZE)
2191 goto out;
960aee6c
HW		 2192
2193 if (!fw_info->magic) {
2194 size_t i, size, start;
2195 u8 checksum = 0;
2196
2197 if (fw->size < sizeof(*fw_info))
2198 goto out;
2199
2200 for (i = 0; i < fw->size; i++)
2201 checksum += fw->data[i];
2202 if (checksum != 0)
2203 goto out;
2204
2205 start = le32_to_cpu(fw_info->fw_start);
2206 if (start > fw->size)
2207 goto out;
2208
2209 size = le32_to_cpu(fw_info->fw_len);
2210 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2211 goto out;
2212
2213 memcpy(version, fw_info->version, RTL_VER_SIZE);
2214
2215 pa->code = (__le32 *)(fw->data + start);
2216 pa->size = size;
2217 } else {
1c361efb
FR		 2218 if (fw->size % FW_OPCODE_SIZE)
2219 goto out;
2220
2221 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2222
2223 pa->code = (__le32 *)fw->data;
2224 pa->size = fw->size / FW_OPCODE_SIZE;
2225 }
2226 version[RTL_VER_SIZE - 1] = 0;
2227
2228 rc = true;
2229out:
2230 return rc;
2231}
2232
fd112f2e
FR		 2233static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2234 struct rtl_fw_phy_action *pa)
1c361efb 2235{
fd112f2e 2236 bool rc = false;
1c361efb 2237 size_t index;
bca03d5f 2238
1c361efb
FR		 2239 for (index = 0; index < pa->size; index++) {
2240 u32 action = le32_to_cpu(pa->code[index]);
42b82dc1 2241 u32 regno = (action & 0x0fff0000) >> 16;
bca03d5f 2242
42b82dc1 2243 switch(action & 0xf0000000) {
2244 case PHY_READ:
2245 case PHY_DATA_OR:
2246 case PHY_DATA_AND:
eee3786f 2247 case PHY_MDIO_CHG:
42b82dc1 2248 case PHY_CLEAR_READCOUNT:
2249 case PHY_WRITE:
2250 case PHY_WRITE_PREVIOUS:
2251 case PHY_DELAY_MS:
2252 break;
2253
2254 case PHY_BJMPN:
2255 if (regno > index) {
fd112f2e 2256 netif_err(tp, ifup, tp->dev,
cecb5fd7 2257 "Out of range of firmware\n");
fd112f2e 2258 goto out;
42b82dc1 2259 }
2260 break;
2261 case PHY_READCOUNT_EQ_SKIP:
1c361efb 2262 if (index + 2 >= pa->size) {
fd112f2e 2263 netif_err(tp, ifup, tp->dev,
cecb5fd7 2264 "Out of range of firmware\n");
fd112f2e 2265 goto out;
42b82dc1 2266 }
2267 break;
2268 case PHY_COMP_EQ_SKIPN:
2269 case PHY_COMP_NEQ_SKIPN:
2270 case PHY_SKIPN:
1c361efb 2271 if (index + 1 + regno >= pa->size) {
fd112f2e 2272 netif_err(tp, ifup, tp->dev,
cecb5fd7 2273 "Out of range of firmware\n");
fd112f2e 2274 goto out;
42b82dc1 2275 }
bca03d5f 2276 break;
2277
42b82dc1 2278 default:
fd112f2e 2279 netif_err(tp, ifup, tp->dev,
42b82dc1 2280 "Invalid action 0x%08x\n", action);
fd112f2e 2281 goto out;
bca03d5f 2282 }
2283 }
fd112f2e
FR		 2284 rc = true;
2285out:
2286 return rc;
2287}
bca03d5f 2288
fd112f2e
FR		 2289static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2290{
2291 struct net_device *dev = tp->dev;
2292 int rc = -EINVAL;
2293
2294 if (!rtl_fw_format_ok(tp, rtl_fw)) {
2295 netif_err(tp, ifup, dev, "invalid firwmare\n");
2296 goto out;
2297 }
2298
2299 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2300 rc = 0;
2301out:
2302 return rc;
2303}
2304
2305static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2306{
2307 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
eee3786f 2308 struct mdio_ops org, *ops = &tp->mdio_ops;
fd112f2e
FR		 2309 u32 predata, count;
2310 size_t index;
2311
2312 predata = count = 0;
eee3786f 2313 org.write = ops->write;
2314 org.read = ops->read;
42b82dc1 2315
1c361efb
FR		 2316 for (index = 0; index < pa->size; ) {
2317 u32 action = le32_to_cpu(pa->code[index]);
bca03d5f 2318 u32 data = action & 0x0000ffff;
42b82dc1 2319 u32 regno = (action & 0x0fff0000) >> 16;
2320
2321 if (!action)
2322 break;
bca03d5f 2323
2324 switch(action & 0xf0000000) {
42b82dc1 2325 case PHY_READ:
2326 predata = rtl_readphy(tp, regno);
2327 count++;
2328 index++;
2329 break;
2330 case PHY_DATA_OR:
2331 predata |= data;
2332 index++;
2333 break;
2334 case PHY_DATA_AND:
2335 predata &= data;
2336 index++;
2337 break;
2338 case PHY_BJMPN:
2339 index -= regno;
2340 break;
eee3786f 2341 case PHY_MDIO_CHG:
2342 if (data == 0) {
2343 ops->write = org.write;
2344 ops->read = org.read;
2345 } else if (data == 1) {
2346 ops->write = mac_mcu_write;
2347 ops->read = mac_mcu_read;
2348 }
2349
42b82dc1 2350 index++;
2351 break;
2352 case PHY_CLEAR_READCOUNT:
2353 count = 0;
2354 index++;
2355 break;
bca03d5f 2356 case PHY_WRITE:
42b82dc1 2357 rtl_writephy(tp, regno, data);
2358 index++;
2359 break;
2360 case PHY_READCOUNT_EQ_SKIP:
cecb5fd7 2361 index += (count == data) ? 2 : 1;
bca03d5f 2362 break;
42b82dc1 2363 case PHY_COMP_EQ_SKIPN:
2364 if (predata == data)
2365 index += regno;
2366 index++;
2367 break;
2368 case PHY_COMP_NEQ_SKIPN:
2369 if (predata != data)
2370 index += regno;
2371 index++;
2372 break;
2373 case PHY_WRITE_PREVIOUS:
2374 rtl_writephy(tp, regno, predata);
2375 index++;
2376 break;
2377 case PHY_SKIPN:
2378 index += regno + 1;
2379 break;
2380 case PHY_DELAY_MS:
2381 mdelay(data);
2382 index++;
2383 break;
2384
bca03d5f 2385 default:
2386 BUG();
2387 }
2388 }
eee3786f 2389
2390 ops->write = org.write;
2391 ops->read = org.read;
bca03d5f 2392}
2393
f1e02ed1 2394static void rtl_release_firmware(struct rtl8169_private *tp)
2395{
b6ffd97f
FR		 2396 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2397 release_firmware(tp->rtl_fw->fw);
2398 kfree(tp->rtl_fw);
2399 }
2400 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
f1e02ed1 2401}
2402
953a12cc 2403static void rtl_apply_firmware(struct rtl8169_private *tp)
f1e02ed1 2404{
b6ffd97f 2405 struct rtl_fw *rtl_fw = tp->rtl_fw;
f1e02ed1 2406
2407 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
eef63cc1 2408 if (!IS_ERR_OR_NULL(rtl_fw))
b6ffd97f 2409 rtl_phy_write_fw(tp, rtl_fw);
953a12cc
FR		 2410}
2411
2412static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2413{
2414 if (rtl_readphy(tp, reg) != val)
2415 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2416 else
2417 rtl_apply_firmware(tp);
f1e02ed1 2418}
2419
4da19633 2420static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1da177e4 2421{
350f7596 2422 static const struct phy_reg phy_reg_init[] = {
0b9b571d 2423 { 0x1f, 0x0001 },
2424 { 0x06, 0x006e },
2425 { 0x08, 0x0708 },
2426 { 0x15, 0x4000 },
2427 { 0x18, 0x65c7 },
1da177e4 2428
0b9b571d 2429 { 0x1f, 0x0001 },
2430 { 0x03, 0x00a1 },
2431 { 0x02, 0x0008 },
2432 { 0x01, 0x0120 },
2433 { 0x00, 0x1000 },
2434 { 0x04, 0x0800 },
2435 { 0x04, 0x0000 },
1da177e4 2436
0b9b571d 2437 { 0x03, 0xff41 },
2438 { 0x02, 0xdf60 },
2439 { 0x01, 0x0140 },
2440 { 0x00, 0x0077 },
2441 { 0x04, 0x7800 },
2442 { 0x04, 0x7000 },
2443
2444 { 0x03, 0x802f },
2445 { 0x02, 0x4f02 },
2446 { 0x01, 0x0409 },
2447 { 0x00, 0xf0f9 },
2448 { 0x04, 0x9800 },
2449 { 0x04, 0x9000 },
2450
2451 { 0x03, 0xdf01 },
2452 { 0x02, 0xdf20 },
2453 { 0x01, 0xff95 },
2454 { 0x00, 0xba00 },
2455 { 0x04, 0xa800 },
2456 { 0x04, 0xa000 },
2457
2458 { 0x03, 0xff41 },
2459 { 0x02, 0xdf20 },
2460 { 0x01, 0x0140 },
2461 { 0x00, 0x00bb },
2462 { 0x04, 0xb800 },
2463 { 0x04, 0xb000 },
2464
2465 { 0x03, 0xdf41 },
2466 { 0x02, 0xdc60 },
2467 { 0x01, 0x6340 },
2468 { 0x00, 0x007d },
2469 { 0x04, 0xd800 },
2470 { 0x04, 0xd000 },
2471
2472 { 0x03, 0xdf01 },
2473 { 0x02, 0xdf20 },
2474 { 0x01, 0x100a },
2475 { 0x00, 0xa0ff },
2476 { 0x04, 0xf800 },
2477 { 0x04, 0xf000 },
2478
2479 { 0x1f, 0x0000 },
2480 { 0x0b, 0x0000 },
2481 { 0x00, 0x9200 }
2482 };
1da177e4 2483
4da19633 2484 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1da177e4
LT		 2485}
2486
4da19633 2487static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
5615d9f1 2488{
350f7596 2489 static const struct phy_reg phy_reg_init[] = {
a441d7b6
FR		 2490 { 0x1f, 0x0002 },
2491 { 0x01, 0x90d0 },
2492 { 0x1f, 0x0000 }
2493 };
2494
4da19633 2495 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 2496}
2497
4da19633 2498static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2e955856 2499{
2500 struct pci_dev *pdev = tp->pci_dev;
2e955856 2501
ccbae55e
SS		 2502 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2503 (pdev->subsystem_device != 0xe000))
2e955856 2504 return;
2505
4da19633 2506 rtl_writephy(tp, 0x1f, 0x0001);
2507 rtl_writephy(tp, 0x10, 0xf01b);
2508 rtl_writephy(tp, 0x1f, 0x0000);
2e955856 2509}
2510
4da19633 2511static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2e955856 2512{
350f7596 2513 static const struct phy_reg phy_reg_init[] = {
2e955856 2514 { 0x1f, 0x0001 },
2515 { 0x04, 0x0000 },
2516 { 0x03, 0x00a1 },
2517 { 0x02, 0x0008 },
2518 { 0x01, 0x0120 },
2519 { 0x00, 0x1000 },
2520 { 0x04, 0x0800 },
2521 { 0x04, 0x9000 },
2522 { 0x03, 0x802f },
2523 { 0x02, 0x4f02 },
2524 { 0x01, 0x0409 },
2525 { 0x00, 0xf099 },
2526 { 0x04, 0x9800 },
2527 { 0x04, 0xa000 },
2528 { 0x03, 0xdf01 },
2529 { 0x02, 0xdf20 },
2530 { 0x01, 0xff95 },
2531 { 0x00, 0xba00 },
2532 { 0x04, 0xa800 },
2533 { 0x04, 0xf000 },
2534 { 0x03, 0xdf01 },
2535 { 0x02, 0xdf20 },
2536 { 0x01, 0x101a },
2537 { 0x00, 0xa0ff },
2538 { 0x04, 0xf800 },
2539 { 0x04, 0x0000 },
2540 { 0x1f, 0x0000 },
2541
2542 { 0x1f, 0x0001 },
2543 { 0x10, 0xf41b },
2544 { 0x14, 0xfb54 },
2545 { 0x18, 0xf5c7 },
2546 { 0x1f, 0x0000 },
2547
2548 { 0x1f, 0x0001 },
2549 { 0x17, 0x0cc0 },
2550 { 0x1f, 0x0000 }
2551 };
2552
4da19633 2553 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2e955856 2554
4da19633 2555 rtl8169scd_hw_phy_config_quirk(tp);
2e955856 2556}
2557
4da19633 2558static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
8c7006aa 2559{
350f7596 2560 static const struct phy_reg phy_reg_init[] = {
8c7006aa 2561 { 0x1f, 0x0001 },
2562 { 0x04, 0x0000 },
2563 { 0x03, 0x00a1 },
2564 { 0x02, 0x0008 },
2565 { 0x01, 0x0120 },
2566 { 0x00, 0x1000 },
2567 { 0x04, 0x0800 },
2568 { 0x04, 0x9000 },
2569 { 0x03, 0x802f },
2570 { 0x02, 0x4f02 },
2571 { 0x01, 0x0409 },
2572 { 0x00, 0xf099 },
2573 { 0x04, 0x9800 },
2574 { 0x04, 0xa000 },
2575 { 0x03, 0xdf01 },
2576 { 0x02, 0xdf20 },
2577 { 0x01, 0xff95 },
2578 { 0x00, 0xba00 },
2579 { 0x04, 0xa800 },
2580 { 0x04, 0xf000 },
2581 { 0x03, 0xdf01 },
2582 { 0x02, 0xdf20 },
2583 { 0x01, 0x101a },
2584 { 0x00, 0xa0ff },
2585 { 0x04, 0xf800 },
2586 { 0x04, 0x0000 },
2587 { 0x1f, 0x0000 },
2588
2589 { 0x1f, 0x0001 },
2590 { 0x0b, 0x8480 },
2591 { 0x1f, 0x0000 },
2592
2593 { 0x1f, 0x0001 },
2594 { 0x18, 0x67c7 },
2595 { 0x04, 0x2000 },
2596 { 0x03, 0x002f },
2597 { 0x02, 0x4360 },
2598 { 0x01, 0x0109 },
2599 { 0x00, 0x3022 },
2600 { 0x04, 0x2800 },
2601 { 0x1f, 0x0000 },
2602
2603 { 0x1f, 0x0001 },
2604 { 0x17, 0x0cc0 },
2605 { 0x1f, 0x0000 }
2606 };
2607
4da19633 2608 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
8c7006aa 2609}
2610
4da19633 2611static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
236b8082 2612{
350f7596 2613 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2614 { 0x10, 0xf41b },
2615 { 0x1f, 0x0000 }
2616 };
2617
4da19633 2618 rtl_writephy(tp, 0x1f, 0x0001);
2619 rtl_patchphy(tp, 0x16, 1 << 0);
236b8082 2620
4da19633 2621 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2622}
2623
4da19633 2624static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
236b8082 2625{
350f7596 2626 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2627 { 0x1f, 0x0001 },
2628 { 0x10, 0xf41b },
2629 { 0x1f, 0x0000 }
2630 };
2631
4da19633 2632 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2633}
2634
4da19633 2635static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2636{
350f7596 2637 static const struct phy_reg phy_reg_init[] = {
867763c1
FR		 2638 { 0x1f, 0x0000 },
2639 { 0x1d, 0x0f00 },
2640 { 0x1f, 0x0002 },
2641 { 0x0c, 0x1ec8 },
2642 { 0x1f, 0x0000 }
2643 };
2644
4da19633 2645 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
867763c1
FR		 2646}
2647
4da19633 2648static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
ef3386f0 2649{
350f7596 2650 static const struct phy_reg phy_reg_init[] = {
ef3386f0
FR		 2651 { 0x1f, 0x0001 },
2652 { 0x1d, 0x3d98 },
2653 { 0x1f, 0x0000 }
2654 };
2655
4da19633 2656 rtl_writephy(tp, 0x1f, 0x0000);
2657 rtl_patchphy(tp, 0x14, 1 << 5);
2658 rtl_patchphy(tp, 0x0d, 1 << 5);
ef3386f0 2659
4da19633 2660 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
ef3386f0
FR		 2661}
2662
4da19633 2663static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2664{
350f7596 2665 static const struct phy_reg phy_reg_init[] = {
a3f80671
FR		 2666 { 0x1f, 0x0001 },
2667 { 0x12, 0x2300 },
867763c1
FR		 2668 { 0x1f, 0x0002 },
2669 { 0x00, 0x88d4 },
2670 { 0x01, 0x82b1 },
2671 { 0x03, 0x7002 },
2672 { 0x08, 0x9e30 },
2673 { 0x09, 0x01f0 },
2674 { 0x0a, 0x5500 },
2675 { 0x0c, 0x00c8 },
2676 { 0x1f, 0x0003 },
2677 { 0x12, 0xc096 },
2678 { 0x16, 0x000a },
f50d4275
FR		 2679 { 0x1f, 0x0000 },
2680 { 0x1f, 0x0000 },
2681 { 0x09, 0x2000 },
2682 { 0x09, 0x0000 }
867763c1
FR		 2683 };
2684
4da19633 2685 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2686
4da19633 2687 rtl_patchphy(tp, 0x14, 1 << 5);
2688 rtl_patchphy(tp, 0x0d, 1 << 5);
2689 rtl_writephy(tp, 0x1f, 0x0000);
867763c1
FR		 2690}
2691
4da19633 2692static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
7da97ec9 2693{
350f7596 2694 static const struct phy_reg phy_reg_init[] = {
f50d4275 2695 { 0x1f, 0x0001 },
7da97ec9 2696 { 0x12, 0x2300 },
f50d4275
FR		 2697 { 0x03, 0x802f },
2698 { 0x02, 0x4f02 },
2699 { 0x01, 0x0409 },
2700 { 0x00, 0xf099 },
2701 { 0x04, 0x9800 },
2702 { 0x04, 0x9000 },
2703 { 0x1d, 0x3d98 },
7da97ec9
FR		 2704 { 0x1f, 0x0002 },
2705 { 0x0c, 0x7eb8 },
f50d4275
FR		 2706 { 0x06, 0x0761 },
2707 { 0x1f, 0x0003 },
2708 { 0x16, 0x0f0a },
7da97ec9
FR		 2709 { 0x1f, 0x0000 }
2710 };
2711
4da19633 2712 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2713
4da19633 2714 rtl_patchphy(tp, 0x16, 1 << 0);
2715 rtl_patchphy(tp, 0x14, 1 << 5);
2716 rtl_patchphy(tp, 0x0d, 1 << 5);
2717 rtl_writephy(tp, 0x1f, 0x0000);
7da97ec9
FR		 2718}
2719
4da19633 2720static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
197ff761 2721{
350f7596 2722 static const struct phy_reg phy_reg_init[] = {
197ff761
FR		 2723 { 0x1f, 0x0001 },
2724 { 0x12, 0x2300 },
2725 { 0x1d, 0x3d98 },
2726 { 0x1f, 0x0002 },
2727 { 0x0c, 0x7eb8 },
2728 { 0x06, 0x5461 },
2729 { 0x1f, 0x0003 },
2730 { 0x16, 0x0f0a },
2731 { 0x1f, 0x0000 }
2732 };
2733
4da19633 2734 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
197ff761 2735
4da19633 2736 rtl_patchphy(tp, 0x16, 1 << 0);
2737 rtl_patchphy(tp, 0x14, 1 << 5);
2738 rtl_patchphy(tp, 0x0d, 1 << 5);
2739 rtl_writephy(tp, 0x1f, 0x0000);
197ff761
FR		 2740}
2741
4da19633 2742static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
6fb07058 2743{
4da19633 2744 rtl8168c_3_hw_phy_config(tp);
6fb07058
FR		 2745}
2746
bca03d5f 2747static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
5b538df9 2748{
350f7596 2749 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2750 /* Channel Estimation */
5b538df9 2751 { 0x1f, 0x0001 },
daf9df6d 2752 { 0x06, 0x4064 },
2753 { 0x07, 0x2863 },
2754 { 0x08, 0x059c },
2755 { 0x09, 0x26b4 },
2756 { 0x0a, 0x6a19 },
2757 { 0x0b, 0xdcc8 },
2758 { 0x10, 0xf06d },
2759 { 0x14, 0x7f68 },
2760 { 0x18, 0x7fd9 },
2761 { 0x1c, 0xf0ff },
2762 { 0x1d, 0x3d9c },
5b538df9 2763 { 0x1f, 0x0003 },
daf9df6d 2764 { 0x12, 0xf49f },
2765 { 0x13, 0x070b },
2766 { 0x1a, 0x05ad },
bca03d5f 2767 { 0x14, 0x94c0 },
2768
2769 /*
2770 * Tx Error Issue
cecb5fd7 2771 * Enhance line driver power
bca03d5f 2772 */
5b538df9 2773 { 0x1f, 0x0002 },
daf9df6d 2774 { 0x06, 0x5561 },
2775 { 0x1f, 0x0005 },
2776 { 0x05, 0x8332 },
bca03d5f 2777 { 0x06, 0x5561 },
2778
2779 /*
2780 * Can not link to 1Gbps with bad cable
2781 * Decrease SNR threshold form 21.07dB to 19.04dB
2782 */
2783 { 0x1f, 0x0001 },
2784 { 0x17, 0x0cc0 },
daf9df6d 2785
5b538df9 2786 { 0x1f, 0x0000 },
bca03d5f 2787 { 0x0d, 0xf880 }
daf9df6d 2788 };
2789
4da19633 2790 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
daf9df6d 2791
bca03d5f 2792 /*
2793 * Rx Error Issue
2794 * Fine Tune Switching regulator parameter
2795 */
4da19633 2796 rtl_writephy(tp, 0x1f, 0x0002);
2797 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2798 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
daf9df6d 2799
fdf6fc06 2800 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
350f7596 2801 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2802 { 0x1f, 0x0002 },
2803 { 0x05, 0x669a },
2804 { 0x1f, 0x0005 },
2805 { 0x05, 0x8330 },
2806 { 0x06, 0x669a },
2807 { 0x1f, 0x0002 }
2808 };
2809 int val;
2810
4da19633 2811 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2812
4da19633 2813 val = rtl_readphy(tp, 0x0d);
daf9df6d 2814
2815 if ((val & 0x00ff) != 0x006c) {
350f7596 2816 static const u32 set[] = {
daf9df6d 2817 0x0065, 0x0066, 0x0067, 0x0068,
2818 0x0069, 0x006a, 0x006b, 0x006c
2819 };
2820 int i;
2821
4da19633 2822 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2823
2824 val &= 0xff00;
2825 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2826 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2827 }
2828 } else {
350f7596 2829 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2830 { 0x1f, 0x0002 },
2831 { 0x05, 0x6662 },
2832 { 0x1f, 0x0005 },
2833 { 0x05, 0x8330 },
2834 { 0x06, 0x6662 }
2835 };
2836
4da19633 2837 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2838 }
2839
bca03d5f 2840 /* RSET couple improve */
4da19633 2841 rtl_writephy(tp, 0x1f, 0x0002);
2842 rtl_patchphy(tp, 0x0d, 0x0300);
2843 rtl_patchphy(tp, 0x0f, 0x0010);
daf9df6d 2844
bca03d5f 2845 /* Fine tune PLL performance */
4da19633 2846 rtl_writephy(tp, 0x1f, 0x0002);
2847 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2848 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2849
4da19633 2850 rtl_writephy(tp, 0x1f, 0x0005);
2851 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2852
2853 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
bca03d5f 2854
4da19633 2855 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2856}
2857
bca03d5f 2858static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2859{
350f7596 2860 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2861 /* Channel Estimation */
daf9df6d 2862 { 0x1f, 0x0001 },
2863 { 0x06, 0x4064 },
2864 { 0x07, 0x2863 },
2865 { 0x08, 0x059c },
2866 { 0x09, 0x26b4 },
2867 { 0x0a, 0x6a19 },
2868 { 0x0b, 0xdcc8 },
2869 { 0x10, 0xf06d },
2870 { 0x14, 0x7f68 },
2871 { 0x18, 0x7fd9 },
2872 { 0x1c, 0xf0ff },
2873 { 0x1d, 0x3d9c },
2874 { 0x1f, 0x0003 },
2875 { 0x12, 0xf49f },
2876 { 0x13, 0x070b },
2877 { 0x1a, 0x05ad },
2878 { 0x14, 0x94c0 },
2879
bca03d5f 2880 /*
2881 * Tx Error Issue
cecb5fd7 2882 * Enhance line driver power
bca03d5f 2883 */
daf9df6d 2884 { 0x1f, 0x0002 },
2885 { 0x06, 0x5561 },
2886 { 0x1f, 0x0005 },
2887 { 0x05, 0x8332 },
bca03d5f 2888 { 0x06, 0x5561 },
2889
2890 /*
2891 * Can not link to 1Gbps with bad cable
2892 * Decrease SNR threshold form 21.07dB to 19.04dB
2893 */
2894 { 0x1f, 0x0001 },
2895 { 0x17, 0x0cc0 },
daf9df6d 2896
2897 { 0x1f, 0x0000 },
bca03d5f 2898 { 0x0d, 0xf880 }
5b538df9
FR		 2899 };
2900
4da19633 2901 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
5b538df9 2902
fdf6fc06 2903 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
350f7596 2904 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2905 { 0x1f, 0x0002 },
2906 { 0x05, 0x669a },
5b538df9 2907 { 0x1f, 0x0005 },
daf9df6d 2908 { 0x05, 0x8330 },
2909 { 0x06, 0x669a },
2910
2911 { 0x1f, 0x0002 }
2912 };
2913 int val;
2914
4da19633 2915 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2916
4da19633 2917 val = rtl_readphy(tp, 0x0d);
daf9df6d 2918 if ((val & 0x00ff) != 0x006c) {
b6bc7650 2919 static const u32 set[] = {
daf9df6d 2920 0x0065, 0x0066, 0x0067, 0x0068,
2921 0x0069, 0x006a, 0x006b, 0x006c
2922 };
2923 int i;
2924
4da19633 2925 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2926
2927 val &= 0xff00;
2928 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2929 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2930 }
2931 } else {
350f7596 2932 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2933 { 0x1f, 0x0002 },
2934 { 0x05, 0x2642 },
5b538df9 2935 { 0x1f, 0x0005 },
daf9df6d 2936 { 0x05, 0x8330 },
2937 { 0x06, 0x2642 }
5b538df9
FR		 2938 };
2939
4da19633 2940 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2941 }
2942
bca03d5f 2943 /* Fine tune PLL performance */
4da19633 2944 rtl_writephy(tp, 0x1f, 0x0002);
2945 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2946 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2947
bca03d5f 2948 /* Switching regulator Slew rate */
4da19633 2949 rtl_writephy(tp, 0x1f, 0x0002);
2950 rtl_patchphy(tp, 0x0f, 0x0017);
daf9df6d 2951
4da19633 2952 rtl_writephy(tp, 0x1f, 0x0005);
2953 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2954
2955 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
bca03d5f 2956
4da19633 2957 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2958}
2959
4da19633 2960static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2961{
350f7596 2962 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2963 { 0x1f, 0x0002 },
2964 { 0x10, 0x0008 },
2965 { 0x0d, 0x006c },
2966
2967 { 0x1f, 0x0000 },
2968 { 0x0d, 0xf880 },
2969
2970 { 0x1f, 0x0001 },
2971 { 0x17, 0x0cc0 },
2972
2973 { 0x1f, 0x0001 },
2974 { 0x0b, 0xa4d8 },
2975 { 0x09, 0x281c },
2976 { 0x07, 0x2883 },
2977 { 0x0a, 0x6b35 },
2978 { 0x1d, 0x3da4 },
2979 { 0x1c, 0xeffd },
2980 { 0x14, 0x7f52 },
2981 { 0x18, 0x7fc6 },
2982 { 0x08, 0x0601 },
2983 { 0x06, 0x4063 },
2984 { 0x10, 0xf074 },
2985 { 0x1f, 0x0003 },
2986 { 0x13, 0x0789 },
2987 { 0x12, 0xf4bd },
2988 { 0x1a, 0x04fd },
2989 { 0x14, 0x84b0 },
2990 { 0x1f, 0x0000 },
2991 { 0x00, 0x9200 },
2992
2993 { 0x1f, 0x0005 },
2994 { 0x01, 0x0340 },
2995 { 0x1f, 0x0001 },
2996 { 0x04, 0x4000 },
2997 { 0x03, 0x1d21 },
2998 { 0x02, 0x0c32 },
2999 { 0x01, 0x0200 },
3000 { 0x00, 0x5554 },
3001 { 0x04, 0x4800 },
3002 { 0x04, 0x4000 },
3003 { 0x04, 0xf000 },
3004 { 0x03, 0xdf01 },
3005 { 0x02, 0xdf20 },
3006 { 0x01, 0x101a },
3007 { 0x00, 0xa0ff },
3008 { 0x04, 0xf800 },
3009 { 0x04, 0xf000 },
3010 { 0x1f, 0x0000 },
3011
3012 { 0x1f, 0x0007 },
3013 { 0x1e, 0x0023 },
3014 { 0x16, 0x0000 },
3015 { 0x1f, 0x0000 }
3016 };
3017
4da19633 3018 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 3019}
3020
e6de30d6 3021static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3022{
3023 static const struct phy_reg phy_reg_init[] = {
3024 { 0x1f, 0x0001 },
3025 { 0x17, 0x0cc0 },
3026
3027 { 0x1f, 0x0007 },
3028 { 0x1e, 0x002d },
3029 { 0x18, 0x0040 },
3030 { 0x1f, 0x0000 }
3031 };
3032
3033 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3034 rtl_patchphy(tp, 0x0d, 1 << 5);
3035}
3036
70090424 3037static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
01dc7fec 3038{
3039 static const struct phy_reg phy_reg_init[] = {
3040 /* Enable Delay cap */
3041 { 0x1f, 0x0005 },
3042 { 0x05, 0x8b80 },
3043 { 0x06, 0xc896 },
3044 { 0x1f, 0x0000 },
3045
3046 /* Channel estimation fine tune */
3047 { 0x1f, 0x0001 },
3048 { 0x0b, 0x6c20 },
3049 { 0x07, 0x2872 },
3050 { 0x1c, 0xefff },
3051 { 0x1f, 0x0003 },
3052 { 0x14, 0x6420 },
3053 { 0x1f, 0x0000 },
3054
3055 /* Update PFM & 10M TX idle timer */
3056 { 0x1f, 0x0007 },
3057 { 0x1e, 0x002f },
3058 { 0x15, 0x1919 },
3059 { 0x1f, 0x0000 },
3060
3061 { 0x1f, 0x0007 },
3062 { 0x1e, 0x00ac },
3063 { 0x18, 0x0006 },
3064 { 0x1f, 0x0000 }
3065 };
3066
15ecd039
FR		 3067 rtl_apply_firmware(tp);
3068
01dc7fec 3069 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3070
3071 /* DCO enable for 10M IDLE Power */
3072 rtl_writephy(tp, 0x1f, 0x0007);
3073 rtl_writephy(tp, 0x1e, 0x0023);
3074 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
3075 rtl_writephy(tp, 0x1f, 0x0000);
3076
3077 /* For impedance matching */
3078 rtl_writephy(tp, 0x1f, 0x0002);
3079 rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
cecb5fd7 3080 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3081
3082 /* PHY auto speed down */
3083 rtl_writephy(tp, 0x1f, 0x0007);
3084 rtl_writephy(tp, 0x1e, 0x002d);
3085 rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
3086 rtl_writephy(tp, 0x1f, 0x0000);
3087 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3088
3089 rtl_writephy(tp, 0x1f, 0x0005);
3090 rtl_writephy(tp, 0x05, 0x8b86);
3091 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3092 rtl_writephy(tp, 0x1f, 0x0000);
3093
3094 rtl_writephy(tp, 0x1f, 0x0005);
3095 rtl_writephy(tp, 0x05, 0x8b85);
3096 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3097 rtl_writephy(tp, 0x1f, 0x0007);
3098 rtl_writephy(tp, 0x1e, 0x0020);
3099 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
3100 rtl_writephy(tp, 0x1f, 0x0006);
3101 rtl_writephy(tp, 0x00, 0x5a00);
3102 rtl_writephy(tp, 0x1f, 0x0000);
3103 rtl_writephy(tp, 0x0d, 0x0007);
3104 rtl_writephy(tp, 0x0e, 0x003c);
3105 rtl_writephy(tp, 0x0d, 0x4007);
3106 rtl_writephy(tp, 0x0e, 0x0000);
3107 rtl_writephy(tp, 0x0d, 0x0000);
3108}
3109
9ecb9aab 3110static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3111{
3112 const u16 w[] = {
3113 addr[0] | (addr[1] << 8),
3114 addr[2] | (addr[3] << 8),
3115 addr[4] | (addr[5] << 8)
3116 };
3117 const struct exgmac_reg e[] = {
3118 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3119 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3120 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3121 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3122 };
3123
3124 rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3125}
3126
70090424
HW		 3127static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3128{
3129 static const struct phy_reg phy_reg_init[] = {
3130 /* Enable Delay cap */
3131 { 0x1f, 0x0004 },
3132 { 0x1f, 0x0007 },
3133 { 0x1e, 0x00ac },
3134 { 0x18, 0x0006 },
3135 { 0x1f, 0x0002 },
3136 { 0x1f, 0x0000 },
3137 { 0x1f, 0x0000 },
3138
3139 /* Channel estimation fine tune */
3140 { 0x1f, 0x0003 },
3141 { 0x09, 0xa20f },
3142 { 0x1f, 0x0000 },
3143 { 0x1f, 0x0000 },
3144
3145 /* Green Setting */
3146 { 0x1f, 0x0005 },
3147 { 0x05, 0x8b5b },
3148 { 0x06, 0x9222 },
3149 { 0x05, 0x8b6d },
3150 { 0x06, 0x8000 },
3151 { 0x05, 0x8b76 },
3152 { 0x06, 0x8000 },
3153 { 0x1f, 0x0000 }
3154 };
3155
3156 rtl_apply_firmware(tp);
3157
3158 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3159
3160 /* For 4-corner performance improve */
3161 rtl_writephy(tp, 0x1f, 0x0005);
3162 rtl_writephy(tp, 0x05, 0x8b80);
3163 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
3164 rtl_writephy(tp, 0x1f, 0x0000);
3165
3166 /* PHY auto speed down */
3167 rtl_writephy(tp, 0x1f, 0x0004);
3168 rtl_writephy(tp, 0x1f, 0x0007);
3169 rtl_writephy(tp, 0x1e, 0x002d);
3170 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3171 rtl_writephy(tp, 0x1f, 0x0002);
3172 rtl_writephy(tp, 0x1f, 0x0000);
3173 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3174
3175 /* improve 10M EEE waveform */
3176 rtl_writephy(tp, 0x1f, 0x0005);
3177 rtl_writephy(tp, 0x05, 0x8b86);
3178 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3179 rtl_writephy(tp, 0x1f, 0x0000);
3180
3181 /* Improve 2-pair detection performance */
3182 rtl_writephy(tp, 0x1f, 0x0005);
3183 rtl_writephy(tp, 0x05, 0x8b85);
3184 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3185 rtl_writephy(tp, 0x1f, 0x0000);
3186
3187 /* EEE setting */
fdf6fc06 3188 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, ERIAR_EXGMAC);
70090424
HW		 3189 rtl_writephy(tp, 0x1f, 0x0005);
3190 rtl_writephy(tp, 0x05, 0x8b85);
3191 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3192 rtl_writephy(tp, 0x1f, 0x0004);
3193 rtl_writephy(tp, 0x1f, 0x0007);
3194 rtl_writephy(tp, 0x1e, 0x0020);
1b23a3e3 3195 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
70090424
HW		 3196 rtl_writephy(tp, 0x1f, 0x0002);
3197 rtl_writephy(tp, 0x1f, 0x0000);
3198 rtl_writephy(tp, 0x0d, 0x0007);
3199 rtl_writephy(tp, 0x0e, 0x003c);
3200 rtl_writephy(tp, 0x0d, 0x4007);
3201 rtl_writephy(tp, 0x0e, 0x0000);
3202 rtl_writephy(tp, 0x0d, 0x0000);
3203
3204 /* Green feature */
3205 rtl_writephy(tp, 0x1f, 0x0003);
3206 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3207 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3208 rtl_writephy(tp, 0x1f, 0x0000);
e0c07557 3209
9ecb9aab 3210 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3211 rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
70090424
HW		 3212}
3213
5f886e08
HW		 3214static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3215{
3216 /* For 4-corner performance improve */
3217 rtl_writephy(tp, 0x1f, 0x0005);
3218 rtl_writephy(tp, 0x05, 0x8b80);
3219 rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3220 rtl_writephy(tp, 0x1f, 0x0000);
3221
3222 /* PHY auto speed down */
3223 rtl_writephy(tp, 0x1f, 0x0007);
3224 rtl_writephy(tp, 0x1e, 0x002d);
3225 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3226 rtl_writephy(tp, 0x1f, 0x0000);
3227 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3228
3229 /* Improve 10M EEE waveform */
3230 rtl_writephy(tp, 0x1f, 0x0005);
3231 rtl_writephy(tp, 0x05, 0x8b86);
3232 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3233 rtl_writephy(tp, 0x1f, 0x0000);
3234}
3235
c2218925
HW		 3236static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3237{
3238 static const struct phy_reg phy_reg_init[] = {
3239 /* Channel estimation fine tune */
3240 { 0x1f, 0x0003 },
3241 { 0x09, 0xa20f },
3242 { 0x1f, 0x0000 },
3243
3244 /* Modify green table for giga & fnet */
3245 { 0x1f, 0x0005 },
3246 { 0x05, 0x8b55 },
3247 { 0x06, 0x0000 },
3248 { 0x05, 0x8b5e },
3249 { 0x06, 0x0000 },
3250 { 0x05, 0x8b67 },
3251 { 0x06, 0x0000 },
3252 { 0x05, 0x8b70 },
3253 { 0x06, 0x0000 },
3254 { 0x1f, 0x0000 },
3255 { 0x1f, 0x0007 },
3256 { 0x1e, 0x0078 },
3257 { 0x17, 0x0000 },
3258 { 0x19, 0x00fb },
3259 { 0x1f, 0x0000 },
3260
3261 /* Modify green table for 10M */
3262 { 0x1f, 0x0005 },
3263 { 0x05, 0x8b79 },
3264 { 0x06, 0xaa00 },
3265 { 0x1f, 0x0000 },
3266
3267 /* Disable hiimpedance detection (RTCT) */
3268 { 0x1f, 0x0003 },
3269 { 0x01, 0x328a },
3270 { 0x1f, 0x0000 }
3271 };
3272
3273 rtl_apply_firmware(tp);
3274
3275 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3276
5f886e08 3277 rtl8168f_hw_phy_config(tp);
c2218925
HW		 3278
3279 /* Improve 2-pair detection performance */
3280 rtl_writephy(tp, 0x1f, 0x0005);
3281 rtl_writephy(tp, 0x05, 0x8b85);
3282 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3283 rtl_writephy(tp, 0x1f, 0x0000);
3284}
3285
3286static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3287{
3288 rtl_apply_firmware(tp);
3289
5f886e08 3290 rtl8168f_hw_phy_config(tp);
c2218925
HW		 3291}
3292
b3d7b2f2
HW		 3293static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3294{
b3d7b2f2
HW		 3295 static const struct phy_reg phy_reg_init[] = {
3296 /* Channel estimation fine tune */
3297 { 0x1f, 0x0003 },
3298 { 0x09, 0xa20f },
3299 { 0x1f, 0x0000 },
3300
3301 /* Modify green table for giga & fnet */
3302 { 0x1f, 0x0005 },
3303 { 0x05, 0x8b55 },
3304 { 0x06, 0x0000 },
3305 { 0x05, 0x8b5e },
3306 { 0x06, 0x0000 },
3307 { 0x05, 0x8b67 },
3308 { 0x06, 0x0000 },
3309 { 0x05, 0x8b70 },
3310 { 0x06, 0x0000 },
3311 { 0x1f, 0x0000 },
3312 { 0x1f, 0x0007 },
3313 { 0x1e, 0x0078 },
3314 { 0x17, 0x0000 },
3315 { 0x19, 0x00aa },
3316 { 0x1f, 0x0000 },
3317
3318 /* Modify green table for 10M */
3319 { 0x1f, 0x0005 },
3320 { 0x05, 0x8b79 },
3321 { 0x06, 0xaa00 },
3322 { 0x1f, 0x0000 },
3323
3324 /* Disable hiimpedance detection (RTCT) */
3325 { 0x1f, 0x0003 },
3326 { 0x01, 0x328a },
3327 { 0x1f, 0x0000 }
3328 };
3329
3330
3331 rtl_apply_firmware(tp);
3332
3333 rtl8168f_hw_phy_config(tp);
3334
3335 /* Improve 2-pair detection performance */
3336 rtl_writephy(tp, 0x1f, 0x0005);
3337 rtl_writephy(tp, 0x05, 0x8b85);
3338 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3339 rtl_writephy(tp, 0x1f, 0x0000);
3340
3341 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3342
3343 /* Modify green table for giga */
3344 rtl_writephy(tp, 0x1f, 0x0005);
3345 rtl_writephy(tp, 0x05, 0x8b54);
3346 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
3347 rtl_writephy(tp, 0x05, 0x8b5d);
3348 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
3349 rtl_writephy(tp, 0x05, 0x8a7c);
3350 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3351 rtl_writephy(tp, 0x05, 0x8a7f);
3352 rtl_w1w0_phy(tp, 0x06, 0x0100, 0x0000);
3353 rtl_writephy(tp, 0x05, 0x8a82);
3354 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3355 rtl_writephy(tp, 0x05, 0x8a85);
3356 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3357 rtl_writephy(tp, 0x05, 0x8a88);
3358 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3359 rtl_writephy(tp, 0x1f, 0x0000);
3360
3361 /* uc same-seed solution */
3362 rtl_writephy(tp, 0x1f, 0x0005);
3363 rtl_writephy(tp, 0x05, 0x8b85);
3364 rtl_w1w0_phy(tp, 0x06, 0x8000, 0x0000);
3365 rtl_writephy(tp, 0x1f, 0x0000);
3366
3367 /* eee setting */
fdf6fc06 3368 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
b3d7b2f2
HW		 3369 rtl_writephy(tp, 0x1f, 0x0005);
3370 rtl_writephy(tp, 0x05, 0x8b85);
3371 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3372 rtl_writephy(tp, 0x1f, 0x0004);
3373 rtl_writephy(tp, 0x1f, 0x0007);
3374 rtl_writephy(tp, 0x1e, 0x0020);
3375 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
3376 rtl_writephy(tp, 0x1f, 0x0000);
3377 rtl_writephy(tp, 0x0d, 0x0007);
3378 rtl_writephy(tp, 0x0e, 0x003c);
3379 rtl_writephy(tp, 0x0d, 0x4007);
3380 rtl_writephy(tp, 0x0e, 0x0000);
3381 rtl_writephy(tp, 0x0d, 0x0000);
3382
3383 /* Green feature */
3384 rtl_writephy(tp, 0x1f, 0x0003);
3385 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3386 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3387 rtl_writephy(tp, 0x1f, 0x0000);
3388}
3389
c558386b
HW		 3390static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3391{
c558386b
HW		 3392 rtl_apply_firmware(tp);
3393
41f44d13 3394 rtl_writephy(tp, 0x1f, 0x0a46);
3395 if (rtl_readphy(tp, 0x10) & 0x0100) {
3396 rtl_writephy(tp, 0x1f, 0x0bcc);
3397 rtl_w1w0_phy(tp, 0x12, 0x0000, 0x8000);
3398 } else {
3399 rtl_writephy(tp, 0x1f, 0x0bcc);
3400 rtl_w1w0_phy(tp, 0x12, 0x8000, 0x0000);
3401 }
c558386b 3402
41f44d13 3403 rtl_writephy(tp, 0x1f, 0x0a46);
3404 if (rtl_readphy(tp, 0x13) & 0x0100) {
3405 rtl_writephy(tp, 0x1f, 0x0c41);
3406 rtl_w1w0_phy(tp, 0x15, 0x0002, 0x0000);
3407 } else {
fe7524c0 3408 rtl_writephy(tp, 0x1f, 0x0c41);
3409 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0002);
41f44d13 3410 }
c558386b 3411
41f44d13 3412 /* Enable PHY auto speed down */
3413 rtl_writephy(tp, 0x1f, 0x0a44);
3414 rtl_w1w0_phy(tp, 0x11, 0x000c, 0x0000);
c558386b 3415
fe7524c0 3416 rtl_writephy(tp, 0x1f, 0x0bcc);
3417 rtl_w1w0_phy(tp, 0x14, 0x0100, 0x0000);
3418 rtl_writephy(tp, 0x1f, 0x0a44);
3419 rtl_w1w0_phy(tp, 0x11, 0x00c0, 0x0000);
3420 rtl_writephy(tp, 0x1f, 0x0a43);
3421 rtl_writephy(tp, 0x13, 0x8084);
3422 rtl_w1w0_phy(tp, 0x14, 0x0000, 0x6000);
3423 rtl_w1w0_phy(tp, 0x10, 0x1003, 0x0000);
3424
41f44d13 3425 /* EEE auto-fallback function */
3426 rtl_writephy(tp, 0x1f, 0x0a4b);
3427 rtl_w1w0_phy(tp, 0x11, 0x0004, 0x0000);
c558386b 3428
41f44d13 3429 /* Enable UC LPF tune function */
3430 rtl_writephy(tp, 0x1f, 0x0a43);
3431 rtl_writephy(tp, 0x13, 0x8012);
3432 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3433
3434 rtl_writephy(tp, 0x1f, 0x0c42);
3435 rtl_w1w0_phy(tp, 0x11, 0x4000, 0x2000);
3436
fe7524c0 3437 /* Improve SWR Efficiency */
3438 rtl_writephy(tp, 0x1f, 0x0bcd);
3439 rtl_writephy(tp, 0x14, 0x5065);
3440 rtl_writephy(tp, 0x14, 0xd065);
3441 rtl_writephy(tp, 0x1f, 0x0bc8);
3442 rtl_writephy(tp, 0x11, 0x5655);
3443 rtl_writephy(tp, 0x1f, 0x0bcd);
3444 rtl_writephy(tp, 0x14, 0x1065);
3445 rtl_writephy(tp, 0x14, 0x9065);
3446 rtl_writephy(tp, 0x14, 0x1065);
3447
41f44d13 3448 rtl_writephy(tp, 0x1f, 0x0000);
c558386b
HW		 3449}
3450
57538c4a 3451static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3452{
3453 rtl_apply_firmware(tp);
3454}
3455
4da19633 3456static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2857ffb7 3457{
350f7596 3458 static const struct phy_reg phy_reg_init[] = {
2857ffb7
FR		 3459 { 0x1f, 0x0003 },
3460 { 0x08, 0x441d },
3461 { 0x01, 0x9100 },
3462 { 0x1f, 0x0000 }
3463 };
3464
4da19633 3465 rtl_writephy(tp, 0x1f, 0x0000);
3466 rtl_patchphy(tp, 0x11, 1 << 12);
3467 rtl_patchphy(tp, 0x19, 1 << 13);
3468 rtl_patchphy(tp, 0x10, 1 << 15);
2857ffb7 3469
4da19633 3470 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2857ffb7
FR		 3471}
3472
5a5e4443
HW		 3473static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3474{
3475 static const struct phy_reg phy_reg_init[] = {
3476 { 0x1f, 0x0005 },
3477 { 0x1a, 0x0000 },
3478 { 0x1f, 0x0000 },
3479
3480 { 0x1f, 0x0004 },
3481 { 0x1c, 0x0000 },
3482 { 0x1f, 0x0000 },
3483
3484 { 0x1f, 0x0001 },
3485 { 0x15, 0x7701 },
3486 { 0x1f, 0x0000 }
3487 };
3488
3489 /* Disable ALDPS before ram code */
eef63cc1
FR		 3490 rtl_writephy(tp, 0x1f, 0x0000);
3491 rtl_writephy(tp, 0x18, 0x0310);
3492 msleep(100);
5a5e4443 3493
953a12cc 3494 rtl_apply_firmware(tp);
5a5e4443
HW		 3495
3496 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3497}
3498
7e18dca1
HW		 3499static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3500{
7e18dca1 3501 /* Disable ALDPS before setting firmware */
eef63cc1
FR		 3502 rtl_writephy(tp, 0x1f, 0x0000);
3503 rtl_writephy(tp, 0x18, 0x0310);
3504 msleep(20);
7e18dca1
HW		 3505
3506 rtl_apply_firmware(tp);
3507
3508 /* EEE setting */
fdf6fc06 3509 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
7e18dca1
HW		 3510 rtl_writephy(tp, 0x1f, 0x0004);
3511 rtl_writephy(tp, 0x10, 0x401f);
3512 rtl_writephy(tp, 0x19, 0x7030);
3513 rtl_writephy(tp, 0x1f, 0x0000);
3514}
3515
5598bfe5
HW		 3516static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3517{
5598bfe5
HW		 3518 static const struct phy_reg phy_reg_init[] = {
3519 { 0x1f, 0x0004 },
3520 { 0x10, 0xc07f },
3521 { 0x19, 0x7030 },
3522 { 0x1f, 0x0000 }
3523 };
3524
3525 /* Disable ALDPS before ram code */
eef63cc1
FR		 3526 rtl_writephy(tp, 0x1f, 0x0000);
3527 rtl_writephy(tp, 0x18, 0x0310);
3528 msleep(100);
5598bfe5
HW		 3529
3530 rtl_apply_firmware(tp);
3531
fdf6fc06 3532 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5598bfe5
HW		 3533 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3534
fdf6fc06 3535 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5598bfe5
HW		 3536}
3537
5615d9f1
FR		 3538static void rtl_hw_phy_config(struct net_device *dev)
3539{
3540 struct rtl8169_private *tp = netdev_priv(dev);
5615d9f1
FR		 3541
3542 rtl8169_print_mac_version(tp);
3543
3544 switch (tp->mac_version) {
3545 case RTL_GIGA_MAC_VER_01:
3546 break;
3547 case RTL_GIGA_MAC_VER_02:
3548 case RTL_GIGA_MAC_VER_03:
4da19633 3549 rtl8169s_hw_phy_config(tp);
5615d9f1
FR		 3550 break;
3551 case RTL_GIGA_MAC_VER_04:
4da19633 3552 rtl8169sb_hw_phy_config(tp);
5615d9f1 3553 break;
2e955856 3554 case RTL_GIGA_MAC_VER_05:
4da19633 3555 rtl8169scd_hw_phy_config(tp);
2e955856 3556 break;
8c7006aa 3557 case RTL_GIGA_MAC_VER_06:
4da19633 3558 rtl8169sce_hw_phy_config(tp);
8c7006aa 3559 break;
2857ffb7
FR		 3560 case RTL_GIGA_MAC_VER_07:
3561 case RTL_GIGA_MAC_VER_08:
3562 case RTL_GIGA_MAC_VER_09:
4da19633 3563 rtl8102e_hw_phy_config(tp);
2857ffb7 3564 break;
236b8082 3565 case RTL_GIGA_MAC_VER_11:
4da19633 3566 rtl8168bb_hw_phy_config(tp);
236b8082
FR		 3567 break;
3568 case RTL_GIGA_MAC_VER_12:
4da19633 3569 rtl8168bef_hw_phy_config(tp);
236b8082
FR		 3570 break;
3571 case RTL_GIGA_MAC_VER_17:
4da19633 3572 rtl8168bef_hw_phy_config(tp);
236b8082 3573 break;
867763c1 3574 case RTL_GIGA_MAC_VER_18:
4da19633 3575 rtl8168cp_1_hw_phy_config(tp);
867763c1
FR		 3576 break;
3577 case RTL_GIGA_MAC_VER_19:
4da19633 3578 rtl8168c_1_hw_phy_config(tp);
867763c1 3579 break;
7da97ec9 3580 case RTL_GIGA_MAC_VER_20:
4da19633 3581 rtl8168c_2_hw_phy_config(tp);
7da97ec9 3582 break;
197ff761 3583 case RTL_GIGA_MAC_VER_21:
4da19633 3584 rtl8168c_3_hw_phy_config(tp);
197ff761 3585 break;
6fb07058 3586 case RTL_GIGA_MAC_VER_22:
4da19633 3587 rtl8168c_4_hw_phy_config(tp);
6fb07058 3588 break;
ef3386f0 3589 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 3590 case RTL_GIGA_MAC_VER_24:
4da19633 3591 rtl8168cp_2_hw_phy_config(tp);
ef3386f0 3592 break;
5b538df9 3593 case RTL_GIGA_MAC_VER_25:
bca03d5f 3594 rtl8168d_1_hw_phy_config(tp);
daf9df6d 3595 break;
3596 case RTL_GIGA_MAC_VER_26:
bca03d5f 3597 rtl8168d_2_hw_phy_config(tp);
daf9df6d 3598 break;
3599 case RTL_GIGA_MAC_VER_27:
4da19633 3600 rtl8168d_3_hw_phy_config(tp);
5b538df9 3601 break;
e6de30d6 3602 case RTL_GIGA_MAC_VER_28:
3603 rtl8168d_4_hw_phy_config(tp);
3604 break;
5a5e4443
HW		 3605 case RTL_GIGA_MAC_VER_29:
3606 case RTL_GIGA_MAC_VER_30:
3607 rtl8105e_hw_phy_config(tp);
3608 break;
cecb5fd7
FR		 3609 case RTL_GIGA_MAC_VER_31:
3610 /* None. */
3611 break;
01dc7fec 3612 case RTL_GIGA_MAC_VER_32:
01dc7fec 3613 case RTL_GIGA_MAC_VER_33:
70090424
HW		 3614 rtl8168e_1_hw_phy_config(tp);
3615 break;
3616 case RTL_GIGA_MAC_VER_34:
3617 rtl8168e_2_hw_phy_config(tp);
01dc7fec 3618 break;
c2218925
HW		 3619 case RTL_GIGA_MAC_VER_35:
3620 rtl8168f_1_hw_phy_config(tp);
3621 break;
3622 case RTL_GIGA_MAC_VER_36:
3623 rtl8168f_2_hw_phy_config(tp);
3624 break;
ef3386f0 3625
7e18dca1
HW		 3626 case RTL_GIGA_MAC_VER_37:
3627 rtl8402_hw_phy_config(tp);
3628 break;
3629
b3d7b2f2
HW		 3630 case RTL_GIGA_MAC_VER_38:
3631 rtl8411_hw_phy_config(tp);
3632 break;
3633
5598bfe5
HW		 3634 case RTL_GIGA_MAC_VER_39:
3635 rtl8106e_hw_phy_config(tp);
3636 break;
3637
c558386b
HW		 3638 case RTL_GIGA_MAC_VER_40:
3639 rtl8168g_1_hw_phy_config(tp);
3640 break;
57538c4a 3641 case RTL_GIGA_MAC_VER_42:
3642 rtl8168g_2_hw_phy_config(tp);
3643 break;
c558386b
HW		 3644
3645 case RTL_GIGA_MAC_VER_41:
5615d9f1
FR		 3646 default:
3647 break;
3648 }
3649}
3650
da78dbff 3651static void rtl_phy_work(struct rtl8169_private *tp)
1da177e4 3652{
1da177e4
LT		 3653 struct timer_list *timer = &tp->timer;
3654 void __iomem *ioaddr = tp->mmio_addr;
3655 unsigned long timeout = RTL8169_PHY_TIMEOUT;
3656
bcf0bf90 3657 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 3658
4da19633 3659 if (tp->phy_reset_pending(tp)) {
5b0384f4 3660 /*
1da177e4
LT		 3661 * A busy loop could burn quite a few cycles on nowadays CPU.
3662 * Let's delay the execution of the timer for a few ticks.
3663 */
3664 timeout = HZ/10;
3665 goto out_mod_timer;
3666 }
3667
3668 if (tp->link_ok(ioaddr))
da78dbff 3669 return;
1da177e4 3670
da78dbff 3671 netif_warn(tp, link, tp->dev, "PHY reset until link up\n");
1da177e4 3672
4da19633 3673 tp->phy_reset_enable(tp);
1da177e4
LT		 3674
3675out_mod_timer:
3676 mod_timer(timer, jiffies + timeout);
da78dbff
FR		 3677}
3678
3679static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3680{
da78dbff
FR		 3681 if (!test_and_set_bit(flag, tp->wk.flags))
3682 schedule_work(&tp->wk.work);
da78dbff
FR		 3683}
3684
3685static void rtl8169_phy_timer(unsigned long __opaque)
3686{
3687 struct net_device *dev = (struct net_device *)__opaque;
3688 struct rtl8169_private *tp = netdev_priv(dev);
3689
98ddf986 3690 rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
1da177e4
LT		 3691}
3692
1da177e4
LT		 3693static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3694 void __iomem *ioaddr)
3695{
3696 iounmap(ioaddr);
3697 pci_release_regions(pdev);
87aeec76 3698 pci_clear_mwi(pdev);
1da177e4
LT		 3699 pci_disable_device(pdev);
3700 free_netdev(dev);
3701}
3702
ffc46952
FR		 3703DECLARE_RTL_COND(rtl_phy_reset_cond)
3704{
3705 return tp->phy_reset_pending(tp);
3706}
3707
bf793295
FR		 3708static void rtl8169_phy_reset(struct net_device *dev,
3709 struct rtl8169_private *tp)
3710{
4da19633 3711 tp->phy_reset_enable(tp);
ffc46952 3712 rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100);
bf793295
FR		 3713}
3714
2544bfc0
FR		 3715static bool rtl_tbi_enabled(struct rtl8169_private *tp)
3716{
3717 void __iomem *ioaddr = tp->mmio_addr;
3718
3719 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
3720 (RTL_R8(PHYstatus) & TBI_Enable);
3721}
3722
4ff96fa6
FR		 3723static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3724{
3725 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 3726
5615d9f1 3727 rtl_hw_phy_config(dev);
4ff96fa6 3728
77332894
MS		 3729 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3730 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3731 RTL_W8(0x82, 0x01);
3732 }
4ff96fa6 3733
6dccd16b
FR		 3734 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3735
3736 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3737 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 3738
bcf0bf90 3739 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 3740 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3741 RTL_W8(0x82, 0x01);
3742 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4da19633 3743 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4ff96fa6
FR		 3744 }
3745
bf793295
FR		 3746 rtl8169_phy_reset(dev, tp);
3747
54405cde 3748 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
cecb5fd7
FR		 3749 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3750 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3751 (tp->mii.supports_gmii ?
3752 ADVERTISED_1000baseT_Half |
3753 ADVERTISED_1000baseT_Full : 0));
4ff96fa6 3754
2544bfc0 3755 if (rtl_tbi_enabled(tp))
bf82c189 3756 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4ff96fa6
FR		 3757}
3758
773d2021
FR		 3759static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3760{
3761 void __iomem *ioaddr = tp->mmio_addr;
773d2021 3762
da78dbff 3763 rtl_lock_work(tp);
773d2021
FR		 3764
3765 RTL_W8(Cfg9346, Cfg9346_Unlock);
908ba2bf 3766
9ecb9aab 3767 RTL_W32(MAC4, addr[4] | addr[5] << 8);
908ba2bf 3768 RTL_R32(MAC4);
3769
9ecb9aab 3770 RTL_W32(MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
908ba2bf 3771 RTL_R32(MAC0);
3772
9ecb9aab 3773 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
3774 rtl_rar_exgmac_set(tp, addr);
c28aa385 3775
773d2021
FR		 3776 RTL_W8(Cfg9346, Cfg9346_Lock);
3777
da78dbff 3778 rtl_unlock_work(tp);
773d2021
FR		 3779}
3780
3781static int rtl_set_mac_address(struct net_device *dev, void *p)
3782{
3783 struct rtl8169_private *tp = netdev_priv(dev);
3784 struct sockaddr *addr = p;
3785
3786 if (!is_valid_ether_addr(addr->sa_data))
3787 return -EADDRNOTAVAIL;
3788
3789 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3790
3791 rtl_rar_set(tp, dev->dev_addr);
3792
3793 return 0;
3794}
3795
5f787a1a
FR		 3796static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3797{
3798 struct rtl8169_private *tp = netdev_priv(dev);
3799 struct mii_ioctl_data *data = if_mii(ifr);
3800
8b4ab28d
FR		 3801 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
3802}
5f787a1a 3803
cecb5fd7
FR		 3804static int rtl_xmii_ioctl(struct rtl8169_private *tp,
3805 struct mii_ioctl_data *data, int cmd)
8b4ab28d 3806{
5f787a1a
FR		 3807 switch (cmd) {
3808 case SIOCGMIIPHY:
3809 data->phy_id = 32; /* Internal PHY */
3810 return 0;
3811
3812 case SIOCGMIIREG:
4da19633 3813 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
5f787a1a
FR		 3814 return 0;
3815
3816 case SIOCSMIIREG:
4da19633 3817 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
5f787a1a
FR		 3818 return 0;
3819 }
3820 return -EOPNOTSUPP;
3821}
3822
8b4ab28d
FR		 3823static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3824{
3825 return -EOPNOTSUPP;
3826}
3827
fbac58fc
FR		 3828static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3829{
3830 if (tp->features & RTL_FEATURE_MSI) {
3831 pci_disable_msi(pdev);
3832 tp->features &= ~RTL_FEATURE_MSI;
3833 }
3834}
3835
baf63293 3836static void rtl_init_mdio_ops(struct rtl8169_private *tp)
c0e45c1c 3837{
3838 struct mdio_ops *ops = &tp->mdio_ops;
3839
3840 switch (tp->mac_version) {
3841 case RTL_GIGA_MAC_VER_27:
3842 ops->write = r8168dp_1_mdio_write;
3843 ops->read = r8168dp_1_mdio_read;
3844 break;
e6de30d6 3845 case RTL_GIGA_MAC_VER_28:
4804b3b3 3846 case RTL_GIGA_MAC_VER_31:
e6de30d6 3847 ops->write = r8168dp_2_mdio_write;
3848 ops->read = r8168dp_2_mdio_read;
3849 break;
c558386b
HW		 3850 case RTL_GIGA_MAC_VER_40:
3851 case RTL_GIGA_MAC_VER_41:
57538c4a 3852 case RTL_GIGA_MAC_VER_42:
c558386b
HW		 3853 ops->write = r8168g_mdio_write;
3854 ops->read = r8168g_mdio_read;
3855 break;
c0e45c1c 3856 default:
3857 ops->write = r8169_mdio_write;
3858 ops->read = r8169_mdio_read;
3859 break;
3860 }
3861}
3862
649b3b8c 3863static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3864{
3865 void __iomem *ioaddr = tp->mmio_addr;
3866
3867 switch (tp->mac_version) {
b00e69de
CB		 3868 case RTL_GIGA_MAC_VER_25:
3869 case RTL_GIGA_MAC_VER_26:
649b3b8c 3870 case RTL_GIGA_MAC_VER_29:
3871 case RTL_GIGA_MAC_VER_30:
3872 case RTL_GIGA_MAC_VER_32:
3873 case RTL_GIGA_MAC_VER_33:
3874 case RTL_GIGA_MAC_VER_34:
7e18dca1 3875 case RTL_GIGA_MAC_VER_37:
b3d7b2f2 3876 case RTL_GIGA_MAC_VER_38:
5598bfe5 3877 case RTL_GIGA_MAC_VER_39:
c558386b
HW		 3878 case RTL_GIGA_MAC_VER_40:
3879 case RTL_GIGA_MAC_VER_41:
57538c4a 3880 case RTL_GIGA_MAC_VER_42:
649b3b8c 3881 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3882 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3883 break;
3884 default:
3885 break;
3886 }
3887}
3888
3889static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
3890{
3891 if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
3892 return false;
3893
3894 rtl_writephy(tp, 0x1f, 0x0000);
3895 rtl_writephy(tp, MII_BMCR, 0x0000);
3896
3897 rtl_wol_suspend_quirk(tp);
3898
3899 return true;
3900}
3901
065c27c1 3902static void r810x_phy_power_down(struct rtl8169_private *tp)
3903{
3904 rtl_writephy(tp, 0x1f, 0x0000);
3905 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3906}
3907
3908static void r810x_phy_power_up(struct rtl8169_private *tp)
3909{
3910 rtl_writephy(tp, 0x1f, 0x0000);
3911 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3912}
3913
3914static void r810x_pll_power_down(struct rtl8169_private *tp)
3915{
0004299a
HW		 3916 void __iomem *ioaddr = tp->mmio_addr;
3917
649b3b8c 3918 if (rtl_wol_pll_power_down(tp))
065c27c1 3919 return;
065c27c1 3920
3921 r810x_phy_power_down(tp);
0004299a
HW		 3922
3923 switch (tp->mac_version) {
3924 case RTL_GIGA_MAC_VER_07:
3925 case RTL_GIGA_MAC_VER_08:
3926 case RTL_GIGA_MAC_VER_09:
3927 case RTL_GIGA_MAC_VER_10:
3928 case RTL_GIGA_MAC_VER_13:
3929 case RTL_GIGA_MAC_VER_16:
3930 break;
3931 default:
3932 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3933 break;
3934 }
065c27c1 3935}
3936
3937static void r810x_pll_power_up(struct rtl8169_private *tp)
3938{
0004299a
HW		 3939 void __iomem *ioaddr = tp->mmio_addr;
3940
065c27c1 3941 r810x_phy_power_up(tp);
0004299a
HW		 3942
3943 switch (tp->mac_version) {
3944 case RTL_GIGA_MAC_VER_07:
3945 case RTL_GIGA_MAC_VER_08:
3946 case RTL_GIGA_MAC_VER_09:
3947 case RTL_GIGA_MAC_VER_10:
3948 case RTL_GIGA_MAC_VER_13:
3949 case RTL_GIGA_MAC_VER_16:
3950 break;
3951 default:
3952 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3953 break;
3954 }
065c27c1 3955}
3956
3957static void r8168_phy_power_up(struct rtl8169_private *tp)
3958{
3959 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3960 switch (tp->mac_version) {
3961 case RTL_GIGA_MAC_VER_11:
3962 case RTL_GIGA_MAC_VER_12:
3963 case RTL_GIGA_MAC_VER_17:
3964 case RTL_GIGA_MAC_VER_18:
3965 case RTL_GIGA_MAC_VER_19:
3966 case RTL_GIGA_MAC_VER_20:
3967 case RTL_GIGA_MAC_VER_21:
3968 case RTL_GIGA_MAC_VER_22:
3969 case RTL_GIGA_MAC_VER_23:
3970 case RTL_GIGA_MAC_VER_24:
3971 case RTL_GIGA_MAC_VER_25:
3972 case RTL_GIGA_MAC_VER_26:
3973 case RTL_GIGA_MAC_VER_27:
3974 case RTL_GIGA_MAC_VER_28:
3975 case RTL_GIGA_MAC_VER_31:
3976 rtl_writephy(tp, 0x0e, 0x0000);
3977 break;
3978 default:
3979 break;
3980 }
065c27c1 3981 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3982}
3983
3984static void r8168_phy_power_down(struct rtl8169_private *tp)
3985{
3986 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3987 switch (tp->mac_version) {
3988 case RTL_GIGA_MAC_VER_32:
3989 case RTL_GIGA_MAC_VER_33:
beb330a4 3990 case RTL_GIGA_MAC_VER_40:
3991 case RTL_GIGA_MAC_VER_41:
01dc7fec 3992 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3993 break;
3994
3995 case RTL_GIGA_MAC_VER_11:
3996 case RTL_GIGA_MAC_VER_12:
3997 case RTL_GIGA_MAC_VER_17:
3998 case RTL_GIGA_MAC_VER_18:
3999 case RTL_GIGA_MAC_VER_19:
4000 case RTL_GIGA_MAC_VER_20:
4001 case RTL_GIGA_MAC_VER_21:
4002 case RTL_GIGA_MAC_VER_22:
4003 case RTL_GIGA_MAC_VER_23:
4004 case RTL_GIGA_MAC_VER_24:
4005 case RTL_GIGA_MAC_VER_25:
4006 case RTL_GIGA_MAC_VER_26:
4007 case RTL_GIGA_MAC_VER_27:
4008 case RTL_GIGA_MAC_VER_28:
4009 case RTL_GIGA_MAC_VER_31:
4010 rtl_writephy(tp, 0x0e, 0x0200);
4011 default:
4012 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4013 break;
4014 }
065c27c1 4015}
4016
4017static void r8168_pll_power_down(struct rtl8169_private *tp)
4018{
4019 void __iomem *ioaddr = tp->mmio_addr;
4020
cecb5fd7
FR		 4021 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4022 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4023 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
4804b3b3 4024 r8168dp_check_dash(tp)) {
065c27c1 4025 return;
5d2e1957 4026 }
065c27c1 4027
cecb5fd7
FR		 4028 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
4029 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
065c27c1 4030 (RTL_R16(CPlusCmd) & ASF)) {
4031 return;
4032 }
4033
01dc7fec 4034 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4035 tp->mac_version == RTL_GIGA_MAC_VER_33)
fdf6fc06 4036 rtl_ephy_write(tp, 0x19, 0xff64);
01dc7fec 4037
649b3b8c 4038 if (rtl_wol_pll_power_down(tp))
065c27c1 4039 return;
065c27c1 4040
4041 r8168_phy_power_down(tp);
4042
4043 switch (tp->mac_version) {
4044 case RTL_GIGA_MAC_VER_25:
4045 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 4046 case RTL_GIGA_MAC_VER_27:
4047 case RTL_GIGA_MAC_VER_28:
4804b3b3 4048 case RTL_GIGA_MAC_VER_31:
01dc7fec 4049 case RTL_GIGA_MAC_VER_32:
4050 case RTL_GIGA_MAC_VER_33:
065c27c1 4051 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4052 break;
beb330a4 4053 case RTL_GIGA_MAC_VER_40:
4054 case RTL_GIGA_MAC_VER_41:
4055 rtl_w1w0_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
4056 0xfc000000, ERIAR_EXGMAC);
4057 break;
065c27c1 4058 }
4059}
4060
4061static void r8168_pll_power_up(struct rtl8169_private *tp)
4062{
4063 void __iomem *ioaddr = tp->mmio_addr;
4064
065c27c1 4065 switch (tp->mac_version) {
4066 case RTL_GIGA_MAC_VER_25:
4067 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 4068 case RTL_GIGA_MAC_VER_27:
4069 case RTL_GIGA_MAC_VER_28:
4804b3b3 4070 case RTL_GIGA_MAC_VER_31:
01dc7fec 4071 case RTL_GIGA_MAC_VER_32:
4072 case RTL_GIGA_MAC_VER_33:
065c27c1 4073 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4074 break;
beb330a4 4075 case RTL_GIGA_MAC_VER_40:
4076 case RTL_GIGA_MAC_VER_41:
4077 rtl_w1w0_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
4078 0x00000000, ERIAR_EXGMAC);
4079 break;
065c27c1 4080 }
4081
4082 r8168_phy_power_up(tp);
4083}
4084
d58d46b5
FR		 4085static void rtl_generic_op(struct rtl8169_private *tp,
4086 void (*op)(struct rtl8169_private *))
065c27c1 4087{
4088 if (op)
4089 op(tp);
4090}
4091
4092static void rtl_pll_power_down(struct rtl8169_private *tp)
4093{
d58d46b5 4094 rtl_generic_op(tp, tp->pll_power_ops.down);
065c27c1 4095}
4096
4097static void rtl_pll_power_up(struct rtl8169_private *tp)
4098{
d58d46b5 4099 rtl_generic_op(tp, tp->pll_power_ops.up);
065c27c1 4100}
4101
baf63293 4102static void rtl_init_pll_power_ops(struct rtl8169_private *tp)
065c27c1 4103{
4104 struct pll_power_ops *ops = &tp->pll_power_ops;
4105
4106 switch (tp->mac_version) {
4107 case RTL_GIGA_MAC_VER_07:
4108 case RTL_GIGA_MAC_VER_08:
4109 case RTL_GIGA_MAC_VER_09:
4110 case RTL_GIGA_MAC_VER_10:
4111 case RTL_GIGA_MAC_VER_16:
5a5e4443
HW		 4112 case RTL_GIGA_MAC_VER_29:
4113 case RTL_GIGA_MAC_VER_30:
7e18dca1 4114 case RTL_GIGA_MAC_VER_37:
5598bfe5 4115 case RTL_GIGA_MAC_VER_39:
065c27c1 4116 ops->down = r810x_pll_power_down;
4117 ops->up = r810x_pll_power_up;
4118 break;
4119
4120 case RTL_GIGA_MAC_VER_11:
4121 case RTL_GIGA_MAC_VER_12:
4122 case RTL_GIGA_MAC_VER_17:
4123 case RTL_GIGA_MAC_VER_18:
4124 case RTL_GIGA_MAC_VER_19:
4125 case RTL_GIGA_MAC_VER_20:
4126 case RTL_GIGA_MAC_VER_21:
4127 case RTL_GIGA_MAC_VER_22:
4128 case RTL_GIGA_MAC_VER_23:
4129 case RTL_GIGA_MAC_VER_24:
4130 case RTL_GIGA_MAC_VER_25:
4131 case RTL_GIGA_MAC_VER_26:
4132 case RTL_GIGA_MAC_VER_27:
e6de30d6 4133 case RTL_GIGA_MAC_VER_28:
4804b3b3 4134 case RTL_GIGA_MAC_VER_31:
01dc7fec 4135 case RTL_GIGA_MAC_VER_32:
4136 case RTL_GIGA_MAC_VER_33:
70090424 4137 case RTL_GIGA_MAC_VER_34:
c2218925
HW		 4138 case RTL_GIGA_MAC_VER_35:
4139 case RTL_GIGA_MAC_VER_36:
b3d7b2f2 4140 case RTL_GIGA_MAC_VER_38:
c558386b
HW		 4141 case RTL_GIGA_MAC_VER_40:
4142 case RTL_GIGA_MAC_VER_41:
57538c4a 4143 case RTL_GIGA_MAC_VER_42:
065c27c1 4144 ops->down = r8168_pll_power_down;
4145 ops->up = r8168_pll_power_up;
4146 break;
4147
4148 default:
4149 ops->down = NULL;
4150 ops->up = NULL;
4151 break;
4152 }
4153}
4154
e542a226
HW		 4155static void rtl_init_rxcfg(struct rtl8169_private *tp)
4156{
4157 void __iomem *ioaddr = tp->mmio_addr;
4158
4159 switch (tp->mac_version) {
4160 case RTL_GIGA_MAC_VER_01:
4161 case RTL_GIGA_MAC_VER_02:
4162 case RTL_GIGA_MAC_VER_03:
4163 case RTL_GIGA_MAC_VER_04:
4164 case RTL_GIGA_MAC_VER_05:
4165 case RTL_GIGA_MAC_VER_06:
4166 case RTL_GIGA_MAC_VER_10:
4167 case RTL_GIGA_MAC_VER_11:
4168 case RTL_GIGA_MAC_VER_12:
4169 case RTL_GIGA_MAC_VER_13:
4170 case RTL_GIGA_MAC_VER_14:
4171 case RTL_GIGA_MAC_VER_15:
4172 case RTL_GIGA_MAC_VER_16:
4173 case RTL_GIGA_MAC_VER_17:
4174 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4175 break;
4176 case RTL_GIGA_MAC_VER_18:
4177 case RTL_GIGA_MAC_VER_19:
4178 case RTL_GIGA_MAC_VER_20:
4179 case RTL_GIGA_MAC_VER_21:
4180 case RTL_GIGA_MAC_VER_22:
4181 case RTL_GIGA_MAC_VER_23:
4182 case RTL_GIGA_MAC_VER_24:
eb2dc35d 4183 case RTL_GIGA_MAC_VER_34:
e542a226
HW		 4184 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4185 break;
beb330a4 4186 case RTL_GIGA_MAC_VER_40:
4187 case RTL_GIGA_MAC_VER_41:
57538c4a 4188 case RTL_GIGA_MAC_VER_42:
beb330a4 4189 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST | RX_EARLY_OFF);
4190 break;
e542a226
HW		 4191 default:
4192 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
4193 break;
4194 }
4195}
4196
92fc43b4
HW		 4197static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4198{
9fba0812 4199 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
92fc43b4
HW		 4200}
4201
d58d46b5
FR		 4202static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4203{
9c5028e9 4204 void __iomem *ioaddr = tp->mmio_addr;
4205
4206 RTL_W8(Cfg9346, Cfg9346_Unlock);
d58d46b5 4207 rtl_generic_op(tp, tp->jumbo_ops.enable);
9c5028e9 4208 RTL_W8(Cfg9346, Cfg9346_Lock);
d58d46b5
FR		 4209}
4210
4211static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4212{
9c5028e9 4213 void __iomem *ioaddr = tp->mmio_addr;
4214
4215 RTL_W8(Cfg9346, Cfg9346_Unlock);
d58d46b5 4216 rtl_generic_op(tp, tp->jumbo_ops.disable);
9c5028e9 4217 RTL_W8(Cfg9346, Cfg9346_Lock);
d58d46b5
FR		 4218}
4219
4220static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4221{
4222 void __iomem *ioaddr = tp->mmio_addr;
4223
4224 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4225 RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
4226 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
4227}
4228
4229static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4230{
4231 void __iomem *ioaddr = tp->mmio_addr;
4232
4233 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4234 RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
4235 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
4236}
4237
4238static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4239{
4240 void __iomem *ioaddr = tp->mmio_addr;
4241
4242 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4243}
4244
4245static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4246{
4247 void __iomem *ioaddr = tp->mmio_addr;
4248
4249 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4250}
4251
4252static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4253{
4254 void __iomem *ioaddr = tp->mmio_addr;
d58d46b5
FR		 4255
4256 RTL_W8(MaxTxPacketSize, 0x3f);
4257 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4258 RTL_W8(Config4, RTL_R8(Config4) | 0x01);
4512ff9f 4259 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
d58d46b5
FR		 4260}
4261
4262static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4263{
4264 void __iomem *ioaddr = tp->mmio_addr;
d58d46b5
FR		 4265
4266 RTL_W8(MaxTxPacketSize, 0x0c);
4267 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4268 RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
4512ff9f 4269 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
d58d46b5
FR		 4270}
4271
4272static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4273{
4274 rtl_tx_performance_tweak(tp->pci_dev,
4275 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4276}
4277
4278static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4279{
4280 rtl_tx_performance_tweak(tp->pci_dev,
4281 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4282}
4283
4284static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4285{
4286 void __iomem *ioaddr = tp->mmio_addr;
4287
4288 r8168b_0_hw_jumbo_enable(tp);
4289
4290 RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
4291}
4292
4293static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4294{
4295 void __iomem *ioaddr = tp->mmio_addr;
4296
4297 r8168b_0_hw_jumbo_disable(tp);
4298
4299 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4300}
4301
baf63293 4302static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
d58d46b5
FR		 4303{
4304 struct jumbo_ops *ops = &tp->jumbo_ops;
4305
4306 switch (tp->mac_version) {
4307 case RTL_GIGA_MAC_VER_11:
4308 ops->disable = r8168b_0_hw_jumbo_disable;
4309 ops->enable = r8168b_0_hw_jumbo_enable;
4310 break;
4311 case RTL_GIGA_MAC_VER_12:
4312 case RTL_GIGA_MAC_VER_17:
4313 ops->disable = r8168b_1_hw_jumbo_disable;
4314 ops->enable = r8168b_1_hw_jumbo_enable;
4315 break;
4316 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
4317 case RTL_GIGA_MAC_VER_19:
4318 case RTL_GIGA_MAC_VER_20:
4319 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
4320 case RTL_GIGA_MAC_VER_22:
4321 case RTL_GIGA_MAC_VER_23:
4322 case RTL_GIGA_MAC_VER_24:
4323 case RTL_GIGA_MAC_VER_25:
4324 case RTL_GIGA_MAC_VER_26:
4325 ops->disable = r8168c_hw_jumbo_disable;
4326 ops->enable = r8168c_hw_jumbo_enable;
4327 break;
4328 case RTL_GIGA_MAC_VER_27:
4329 case RTL_GIGA_MAC_VER_28:
4330 ops->disable = r8168dp_hw_jumbo_disable;
4331 ops->enable = r8168dp_hw_jumbo_enable;
4332 break;
4333 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
4334 case RTL_GIGA_MAC_VER_32:
4335 case RTL_GIGA_MAC_VER_33:
4336 case RTL_GIGA_MAC_VER_34:
4337 ops->disable = r8168e_hw_jumbo_disable;
4338 ops->enable = r8168e_hw_jumbo_enable;
4339 break;
4340
4341 /*
4342 * No action needed for jumbo frames with 8169.
4343 * No jumbo for 810x at all.
4344 */
c558386b
HW		 4345 case RTL_GIGA_MAC_VER_40:
4346 case RTL_GIGA_MAC_VER_41:
57538c4a 4347 case RTL_GIGA_MAC_VER_42:
d58d46b5
FR		 4348 default:
4349 ops->disable = NULL;
4350 ops->enable = NULL;
4351 break;
4352 }
4353}
4354
ffc46952
FR		 4355DECLARE_RTL_COND(rtl_chipcmd_cond)
4356{
4357 void __iomem *ioaddr = tp->mmio_addr;
4358
4359 return RTL_R8(ChipCmd) & CmdReset;
4360}
4361
6f43adc8
FR		 4362static void rtl_hw_reset(struct rtl8169_private *tp)
4363{
4364 void __iomem *ioaddr = tp->mmio_addr;
6f43adc8 4365
6f43adc8
FR		 4366 RTL_W8(ChipCmd, CmdReset);
4367
ffc46952 4368 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
6f43adc8
FR		 4369}
4370
b6ffd97f 4371static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
953a12cc 4372{
b6ffd97f
FR		 4373 struct rtl_fw *rtl_fw;
4374 const char *name;
4375 int rc = -ENOMEM;
953a12cc 4376
b6ffd97f
FR		 4377 name = rtl_lookup_firmware_name(tp);
4378 if (!name)
4379 goto out_no_firmware;
953a12cc 4380
b6ffd97f
FR		 4381 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4382 if (!rtl_fw)
4383 goto err_warn;
31bd204f 4384
b6ffd97f
FR		 4385 rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
4386 if (rc < 0)
4387 goto err_free;
4388
fd112f2e
FR		 4389 rc = rtl_check_firmware(tp, rtl_fw);
4390 if (rc < 0)
4391 goto err_release_firmware;
4392
b6ffd97f
FR		 4393 tp->rtl_fw = rtl_fw;
4394out:
4395 return;
4396
fd112f2e
FR		 4397err_release_firmware:
4398 release_firmware(rtl_fw->fw);
b6ffd97f
FR		 4399err_free:
4400 kfree(rtl_fw);
4401err_warn:
4402 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4403 name, rc);
4404out_no_firmware:
4405 tp->rtl_fw = NULL;
4406 goto out;
4407}
4408
4409static void rtl_request_firmware(struct rtl8169_private *tp)
4410{
4411 if (IS_ERR(tp->rtl_fw))
4412 rtl_request_uncached_firmware(tp);
953a12cc
FR		 4413}
4414
92fc43b4
HW		 4415static void rtl_rx_close(struct rtl8169_private *tp)
4416{
4417 void __iomem *ioaddr = tp->mmio_addr;
92fc43b4 4418
1687b566 4419 RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
92fc43b4
HW		 4420}
4421
ffc46952
FR		 4422DECLARE_RTL_COND(rtl_npq_cond)
4423{
4424 void __iomem *ioaddr = tp->mmio_addr;
4425
4426 return RTL_R8(TxPoll) & NPQ;
4427}
4428
4429DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4430{
4431 void __iomem *ioaddr = tp->mmio_addr;
4432
4433 return RTL_R32(TxConfig) & TXCFG_EMPTY;
4434}
4435
e6de30d6 4436static void rtl8169_hw_reset(struct rtl8169_private *tp)
1da177e4 4437{
e6de30d6 4438 void __iomem *ioaddr = tp->mmio_addr;
4439
1da177e4 4440 /* Disable interrupts */
811fd301 4441 rtl8169_irq_mask_and_ack(tp);
1da177e4 4442
92fc43b4
HW		 4443 rtl_rx_close(tp);
4444
5d2e1957 4445 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4804b3b3 4446 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4447 tp->mac_version == RTL_GIGA_MAC_VER_31) {
ffc46952 4448 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
c2218925
HW		 4449 } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
4450 tp->mac_version == RTL_GIGA_MAC_VER_35 ||
7e18dca1 4451 tp->mac_version == RTL_GIGA_MAC_VER_36 ||
b3d7b2f2 4452 tp->mac_version == RTL_GIGA_MAC_VER_37 ||
c558386b
HW		 4453 tp->mac_version == RTL_GIGA_MAC_VER_40 ||
4454 tp->mac_version == RTL_GIGA_MAC_VER_41 ||
57538c4a 4455 tp->mac_version == RTL_GIGA_MAC_VER_42 ||
b3d7b2f2 4456 tp->mac_version == RTL_GIGA_MAC_VER_38) {
c2b0c1e7 4457 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
ffc46952 4458 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
92fc43b4
HW		 4459 } else {
4460 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4461 udelay(100);
e6de30d6 4462 }
4463
92fc43b4 4464 rtl_hw_reset(tp);
1da177e4
LT		 4465}
4466
7f796d83 4467static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 4468{
4469 void __iomem *ioaddr = tp->mmio_addr;
9cb427b6
FR		 4470
4471 /* Set DMA burst size and Interframe Gap Time */
4472 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4473 (InterFrameGap << TxInterFrameGapShift));
4474}
4475
07ce4064 4476static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 4477{
4478 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 4479
07ce4064
FR		 4480 tp->hw_start(dev);
4481
da78dbff 4482 rtl_irq_enable_all(tp);
07ce4064
FR		 4483}
4484
7f796d83
FR		 4485static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
4486 void __iomem *ioaddr)
4487{
4488 /*
4489 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4490 * register to be written before TxDescAddrLow to work.
4491 * Switching from MMIO to I/O access fixes the issue as well.
4492 */
4493 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
284901a9 4494 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
7f796d83 4495 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
284901a9 4496 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 4497}
4498
4499static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4500{
4501 u16 cmd;
4502
4503 cmd = RTL_R16(CPlusCmd);
4504 RTL_W16(CPlusCmd, cmd);
4505 return cmd;
4506}
4507
fdd7b4c3 4508static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
7f796d83
FR		 4509{
4510 /* Low hurts. Let's disable the filtering. */
207d6e87 4511 RTL_W16(RxMaxSize, rx_buf_sz + 1);
7f796d83
FR		 4512}
4513
6dccd16b
FR		 4514static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4515{
3744100e 4516 static const struct rtl_cfg2_info {
6dccd16b
FR		 4517 u32 mac_version;
4518 u32 clk;
4519 u32 val;
4520 } cfg2_info [] = {
4521 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4522 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4523 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4524 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3744100e
FR		 4525 };
4526 const struct rtl_cfg2_info *p = cfg2_info;
6dccd16b
FR		 4527 unsigned int i;
4528 u32 clk;
4529
4530 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 4531 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 4532 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4533 RTL_W32(0x7c, p->val);
4534 break;
4535 }
4536 }
4537}
4538
e6b763ea
FR		 4539static void rtl_set_rx_mode(struct net_device *dev)
4540{
4541 struct rtl8169_private *tp = netdev_priv(dev);
4542 void __iomem *ioaddr = tp->mmio_addr;
4543 u32 mc_filter[2]; /* Multicast hash filter */
4544 int rx_mode;
4545 u32 tmp = 0;
4546
4547 if (dev->flags & IFF_PROMISC) {
4548 /* Unconditionally log net taps. */
4549 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4550 rx_mode =
4551 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4552 AcceptAllPhys;
4553 mc_filter[1] = mc_filter[0] = 0xffffffff;
4554 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4555 (dev->flags & IFF_ALLMULTI)) {
4556 /* Too many to filter perfectly -- accept all multicasts. */
4557 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4558 mc_filter[1] = mc_filter[0] = 0xffffffff;
4559 } else {
4560 struct netdev_hw_addr *ha;
4561
4562 rx_mode = AcceptBroadcast | AcceptMyPhys;
4563 mc_filter[1] = mc_filter[0] = 0;
4564 netdev_for_each_mc_addr(ha, dev) {
4565 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4566 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4567 rx_mode |= AcceptMulticast;
4568 }
4569 }
4570
4571 if (dev->features & NETIF_F_RXALL)
4572 rx_mode |= (AcceptErr | AcceptRunt);
4573
4574 tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4575
4576 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4577 u32 data = mc_filter[0];
4578
4579 mc_filter[0] = swab32(mc_filter[1]);
4580 mc_filter[1] = swab32(data);
4581 }
4582
0481776b
NW		 4583 if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4584 mc_filter[1] = mc_filter[0] = 0xffffffff;
4585
e6b763ea
FR		 4586 RTL_W32(MAR0 + 4, mc_filter[1]);
4587 RTL_W32(MAR0 + 0, mc_filter[0]);
4588
4589 RTL_W32(RxConfig, tmp);
4590}
4591
07ce4064
FR		 4592static void rtl_hw_start_8169(struct net_device *dev)
4593{
4594 struct rtl8169_private *tp = netdev_priv(dev);
4595 void __iomem *ioaddr = tp->mmio_addr;
4596 struct pci_dev *pdev = tp->pci_dev;
07ce4064 4597
9cb427b6
FR		 4598 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4599 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4600 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4601 }
4602
1da177e4 4603 RTL_W8(Cfg9346, Cfg9346_Unlock);
cecb5fd7
FR		 4604 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4605 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4606 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4607 tp->mac_version == RTL_GIGA_MAC_VER_04)
9cb427b6
FR		 4608 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4609
e542a226
HW		 4610 rtl_init_rxcfg(tp);
4611
f0298f81 4612 RTL_W8(EarlyTxThres, NoEarlyTx);
1da177e4 4613
6f0333b8 4614 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
1da177e4 4615
cecb5fd7
FR		 4616 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4617 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4618 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4619 tp->mac_version == RTL_GIGA_MAC_VER_04)
c946b304 4620 rtl_set_rx_tx_config_registers(tp);
1da177e4 4621
7f796d83 4622 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 4623
cecb5fd7
FR		 4624 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4625 tp->mac_version == RTL_GIGA_MAC_VER_03) {
06fa7358 4626 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1da177e4 4627 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 4628 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 4629 }
4630
bcf0bf90
FR		 4631 RTL_W16(CPlusCmd, tp->cp_cmd);
4632
6dccd16b
FR		 4633 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4634
1da177e4
LT		 4635 /*
4636 * Undocumented corner. Supposedly:
4637 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4638 */
4639 RTL_W16(IntrMitigate, 0x0000);
4640
7f796d83 4641 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 4642
cecb5fd7
FR		 4643 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4644 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4645 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
4646 tp->mac_version != RTL_GIGA_MAC_VER_04) {
c946b304
FR		 4647 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4648 rtl_set_rx_tx_config_registers(tp);
4649 }
4650
1da177e4 4651 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 4652
4653 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4654 RTL_R8(IntrMask);
1da177e4
LT		 4655
4656 RTL_W32(RxMissed, 0);
4657
07ce4064 4658 rtl_set_rx_mode(dev);
1da177e4
LT		 4659
4660 /* no early-rx interrupts */
4661 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
07ce4064 4662}
1da177e4 4663
beb1fe18
HW		 4664static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4665{
4666 if (tp->csi_ops.write)
52989f0e 4667 tp->csi_ops.write(tp, addr, value);
beb1fe18
HW		 4668}
4669
4670static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4671{
52989f0e 4672 return tp->csi_ops.read ? tp->csi_ops.read(tp, addr) : ~0;
beb1fe18
HW		 4673}
4674
4675static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits)
dacf8154
FR		 4676{
4677 u32 csi;
4678
beb1fe18
HW		 4679 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4680 rtl_csi_write(tp, 0x070c, csi | bits);
4681}
4682
4683static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
4684{
4685 rtl_csi_access_enable(tp, 0x17000000);
650e8d5d 4686}
4687
beb1fe18 4688static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
e6de30d6 4689{
beb1fe18 4690 rtl_csi_access_enable(tp, 0x27000000);
e6de30d6 4691}
4692
ffc46952
FR		 4693DECLARE_RTL_COND(rtl_csiar_cond)
4694{
4695 void __iomem *ioaddr = tp->mmio_addr;
4696
4697 return RTL_R32(CSIAR) & CSIAR_FLAG;
4698}
4699
52989f0e 4700static void r8169_csi_write(struct rtl8169_private *tp, int addr, int value)
650e8d5d 4701{
52989f0e 4702 void __iomem *ioaddr = tp->mmio_addr;
beb1fe18
HW		 4703
4704 RTL_W32(CSIDR, value);
4705 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4706 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4707
ffc46952 4708 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
beb1fe18
HW		 4709}
4710
52989f0e 4711static u32 r8169_csi_read(struct rtl8169_private *tp, int addr)
beb1fe18 4712{
52989f0e 4713 void __iomem *ioaddr = tp->mmio_addr;
beb1fe18
HW		 4714
4715 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
4716 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4717
ffc46952
FR		 4718 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4719 RTL_R32(CSIDR) : ~0;
beb1fe18
HW		 4720}
4721
52989f0e 4722static void r8402_csi_write(struct rtl8169_private *tp, int addr, int value)
7e18dca1 4723{
52989f0e 4724 void __iomem *ioaddr = tp->mmio_addr;
7e18dca1
HW		 4725
4726 RTL_W32(CSIDR, value);
4727 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4728 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
4729 CSIAR_FUNC_NIC);
4730
ffc46952 4731 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
7e18dca1
HW		 4732}
4733
52989f0e 4734static u32 r8402_csi_read(struct rtl8169_private *tp, int addr)
7e18dca1 4735{
52989f0e 4736 void __iomem *ioaddr = tp->mmio_addr;
7e18dca1
HW		 4737
4738 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
4739 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4740
ffc46952
FR		 4741 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4742 RTL_R32(CSIDR) : ~0;
7e18dca1
HW		 4743}
4744
baf63293 4745static void rtl_init_csi_ops(struct rtl8169_private *tp)
beb1fe18
HW		 4746{
4747 struct csi_ops *ops = &tp->csi_ops;
4748
4749 switch (tp->mac_version) {
4750 case RTL_GIGA_MAC_VER_01:
4751 case RTL_GIGA_MAC_VER_02:
4752 case RTL_GIGA_MAC_VER_03:
4753 case RTL_GIGA_MAC_VER_04:
4754 case RTL_GIGA_MAC_VER_05:
4755 case RTL_GIGA_MAC_VER_06:
4756 case RTL_GIGA_MAC_VER_10:
4757 case RTL_GIGA_MAC_VER_11:
4758 case RTL_GIGA_MAC_VER_12:
4759 case RTL_GIGA_MAC_VER_13:
4760 case RTL_GIGA_MAC_VER_14:
4761 case RTL_GIGA_MAC_VER_15:
4762 case RTL_GIGA_MAC_VER_16:
4763 case RTL_GIGA_MAC_VER_17:
4764 ops->write = NULL;
4765 ops->read = NULL;
4766 break;
4767
7e18dca1 4768 case RTL_GIGA_MAC_VER_37:
b3d7b2f2 4769 case RTL_GIGA_MAC_VER_38:
7e18dca1
HW		 4770 ops->write = r8402_csi_write;
4771 ops->read = r8402_csi_read;
4772 break;
4773
beb1fe18
HW		 4774 default:
4775 ops->write = r8169_csi_write;
4776 ops->read = r8169_csi_read;
4777 break;
4778 }
dacf8154
FR		 4779}
4780
4781struct ephy_info {
4782 unsigned int offset;
4783 u16 mask;
4784 u16 bits;
4785};
4786
fdf6fc06
FR		 4787static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
4788 int len)
dacf8154
FR		 4789{
4790 u16 w;
4791
4792 while (len-- > 0) {
fdf6fc06
FR		 4793 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4794 rtl_ephy_write(tp, e->offset, w);
dacf8154
FR		 4795 e++;
4796 }
4797}
4798
b726e493
FR		 4799static void rtl_disable_clock_request(struct pci_dev *pdev)
4800{
7d7903b2
JL		 4801 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
4802 PCI_EXP_LNKCTL_CLKREQ_EN);
b726e493
FR		 4803}
4804
e6de30d6 4805static void rtl_enable_clock_request(struct pci_dev *pdev)
4806{
7d7903b2
JL		 4807 pcie_capability_set_word(pdev, PCI_EXP_LNKCTL,
4808 PCI_EXP_LNKCTL_CLKREQ_EN);
e6de30d6 4809}
4810
b726e493
FR		 4811#define R8168_CPCMD_QUIRK_MASK (\
4812 EnableBist | \
4813 Mac_dbgo_oe | \
4814 Force_half_dup | \
4815 Force_rxflow_en | \
4816 Force_txflow_en | \
4817 Cxpl_dbg_sel | \
4818 ASF | \
4819 PktCntrDisable | \
4820 Mac_dbgo_sel)
4821
beb1fe18 4822static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
219a1e9d 4823{
beb1fe18
HW		 4824 void __iomem *ioaddr = tp->mmio_addr;
4825 struct pci_dev *pdev = tp->pci_dev;
4826
b726e493
FR		 4827 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4828
4829 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4830
faf1e785 4831 if (tp->dev->mtu <= ETH_DATA_LEN) {
4832 rtl_tx_performance_tweak(pdev, (0x5 << MAX_READ_REQUEST_SHIFT) |
4833 PCI_EXP_DEVCTL_NOSNOOP_EN);
4834 }
219a1e9d
FR		 4835}
4836
beb1fe18 4837static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
219a1e9d 4838{
beb1fe18
HW		 4839 void __iomem *ioaddr = tp->mmio_addr;
4840
4841 rtl_hw_start_8168bb(tp);
b726e493 4842
f0298f81 4843 RTL_W8(MaxTxPacketSize, TxPacketMax);
b726e493
FR		 4844
4845 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
219a1e9d
FR		 4846}
4847
beb1fe18 4848static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
219a1e9d 4849{
beb1fe18
HW		 4850 void __iomem *ioaddr = tp->mmio_addr;
4851 struct pci_dev *pdev = tp->pci_dev;
4852
b726e493
FR		 4853 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4854
4855 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4856
faf1e785 4857 if (tp->dev->mtu <= ETH_DATA_LEN)
4858 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
b726e493
FR		 4859
4860 rtl_disable_clock_request(pdev);
4861
4862 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
219a1e9d
FR		 4863}
4864
beb1fe18 4865static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
219a1e9d 4866{
350f7596 4867 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 4868 { 0x01, 0, 0x0001 },
4869 { 0x02, 0x0800, 0x1000 },
4870 { 0x03, 0, 0x0042 },
4871 { 0x06, 0x0080, 0x0000 },
4872 { 0x07, 0, 0x2000 }
4873 };
4874
beb1fe18 4875 rtl_csi_access_enable_2(tp);
b726e493 4876
fdf6fc06 4877 rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
b726e493 4878
beb1fe18 4879 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 4880}
4881
beb1fe18 4882static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
ef3386f0 4883{
beb1fe18
HW		 4884 void __iomem *ioaddr = tp->mmio_addr;
4885 struct pci_dev *pdev = tp->pci_dev;
4886
4887 rtl_csi_access_enable_2(tp);
ef3386f0
FR		 4888
4889 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4890
faf1e785 4891 if (tp->dev->mtu <= ETH_DATA_LEN)
4892 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
ef3386f0
FR		 4893
4894 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4895}
4896
beb1fe18 4897static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
7f3e3d3a 4898{
beb1fe18
HW		 4899 void __iomem *ioaddr = tp->mmio_addr;
4900 struct pci_dev *pdev = tp->pci_dev;
4901
4902 rtl_csi_access_enable_2(tp);
7f3e3d3a
FR		 4903
4904 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4905
4906 /* Magic. */
4907 RTL_W8(DBG_REG, 0x20);
4908
f0298f81 4909 RTL_W8(MaxTxPacketSize, TxPacketMax);
7f3e3d3a 4910
faf1e785 4911 if (tp->dev->mtu <= ETH_DATA_LEN)
4912 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
7f3e3d3a
FR		 4913
4914 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4915}
4916
beb1fe18 4917static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
219a1e9d 4918{
beb1fe18 4919 void __iomem *ioaddr = tp->mmio_addr;
350f7596 4920 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 4921 { 0x02, 0x0800, 0x1000 },
4922 { 0x03, 0, 0x0002 },
4923 { 0x06, 0x0080, 0x0000 }
4924 };
4925
beb1fe18 4926 rtl_csi_access_enable_2(tp);
b726e493
FR		 4927
4928 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4929
fdf6fc06 4930 rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
b726e493 4931
beb1fe18 4932 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 4933}
4934
beb1fe18 4935static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
219a1e9d 4936{
350f7596 4937 static const struct ephy_info e_info_8168c_2[] = {
b726e493
FR		 4938 { 0x01, 0, 0x0001 },
4939 { 0x03, 0x0400, 0x0220 }
4940 };
4941
beb1fe18 4942 rtl_csi_access_enable_2(tp);
b726e493 4943
fdf6fc06 4944 rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
b726e493 4945
beb1fe18 4946 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 4947}
4948
beb1fe18 4949static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
197ff761 4950{
beb1fe18 4951 rtl_hw_start_8168c_2(tp);
197ff761
FR		 4952}
4953
beb1fe18 4954static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
6fb07058 4955{
beb1fe18 4956 rtl_csi_access_enable_2(tp);
6fb07058 4957
beb1fe18 4958 __rtl_hw_start_8168cp(tp);
6fb07058
FR		 4959}
4960
beb1fe18 4961static void rtl_hw_start_8168d(struct rtl8169_private *tp)
5b538df9 4962{
beb1fe18
HW		 4963 void __iomem *ioaddr = tp->mmio_addr;
4964 struct pci_dev *pdev = tp->pci_dev;
4965
4966 rtl_csi_access_enable_2(tp);
5b538df9
FR		 4967
4968 rtl_disable_clock_request(pdev);
4969
f0298f81 4970 RTL_W8(MaxTxPacketSize, TxPacketMax);
5b538df9 4971
faf1e785 4972 if (tp->dev->mtu <= ETH_DATA_LEN)
4973 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5b538df9
FR		 4974
4975 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4976}
4977
beb1fe18 4978static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4804b3b3 4979{
beb1fe18
HW		 4980 void __iomem *ioaddr = tp->mmio_addr;
4981 struct pci_dev *pdev = tp->pci_dev;
4982
4983 rtl_csi_access_enable_1(tp);
4804b3b3 4984
faf1e785 4985 if (tp->dev->mtu <= ETH_DATA_LEN)
4986 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4804b3b3 4987
4988 RTL_W8(MaxTxPacketSize, TxPacketMax);
4989
4990 rtl_disable_clock_request(pdev);
4991}
4992
beb1fe18 4993static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
e6de30d6 4994{
beb1fe18
HW		 4995 void __iomem *ioaddr = tp->mmio_addr;
4996 struct pci_dev *pdev = tp->pci_dev;
e6de30d6 4997 static const struct ephy_info e_info_8168d_4[] = {
4998 { 0x0b, ~0, 0x48 },
4999 { 0x19, 0x20, 0x50 },
5000 { 0x0c, ~0, 0x20 }
5001 };
5002 int i;
5003
beb1fe18 5004 rtl_csi_access_enable_1(tp);
e6de30d6 5005
5006 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5007
5008 RTL_W8(MaxTxPacketSize, TxPacketMax);
5009
5010 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
5011 const struct ephy_info *e = e_info_8168d_4 + i;
5012 u16 w;
5013
fdf6fc06
FR		 5014 w = rtl_ephy_read(tp, e->offset);
5015 rtl_ephy_write(tp, 0x03, (w & e->mask) | e->bits);
e6de30d6 5016 }
5017
5018 rtl_enable_clock_request(pdev);
5019}
5020
beb1fe18 5021static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
01dc7fec 5022{
beb1fe18
HW		 5023 void __iomem *ioaddr = tp->mmio_addr;
5024 struct pci_dev *pdev = tp->pci_dev;
70090424 5025 static const struct ephy_info e_info_8168e_1[] = {
01dc7fec 5026 { 0x00, 0x0200, 0x0100 },
5027 { 0x00, 0x0000, 0x0004 },
5028 { 0x06, 0x0002, 0x0001 },
5029 { 0x06, 0x0000, 0x0030 },
5030 { 0x07, 0x0000, 0x2000 },
5031 { 0x00, 0x0000, 0x0020 },
5032 { 0x03, 0x5800, 0x2000 },
5033 { 0x03, 0x0000, 0x0001 },
5034 { 0x01, 0x0800, 0x1000 },
5035 { 0x07, 0x0000, 0x4000 },
5036 { 0x1e, 0x0000, 0x2000 },
5037 { 0x19, 0xffff, 0xfe6c },
5038 { 0x0a, 0x0000, 0x0040 }
5039 };
5040
beb1fe18 5041 rtl_csi_access_enable_2(tp);
01dc7fec 5042
fdf6fc06 5043 rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
01dc7fec 5044
faf1e785 5045 if (tp->dev->mtu <= ETH_DATA_LEN)
5046 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
01dc7fec 5047
5048 RTL_W8(MaxTxPacketSize, TxPacketMax);
5049
5050 rtl_disable_clock_request(pdev);
5051
5052 /* Reset tx FIFO pointer */
cecb5fd7
FR		 5053 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
5054 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
01dc7fec 5055
cecb5fd7 5056 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
01dc7fec 5057}
5058
beb1fe18 5059static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
70090424 5060{
beb1fe18
HW		 5061 void __iomem *ioaddr = tp->mmio_addr;
5062 struct pci_dev *pdev = tp->pci_dev;
70090424
HW		 5063 static const struct ephy_info e_info_8168e_2[] = {
5064 { 0x09, 0x0000, 0x0080 },
5065 { 0x19, 0x0000, 0x0224 }
5066 };
5067
beb1fe18 5068 rtl_csi_access_enable_1(tp);
70090424 5069
fdf6fc06 5070 rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
70090424 5071
faf1e785 5072 if (tp->dev->mtu <= ETH_DATA_LEN)
5073 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
70090424 5074
fdf6fc06
FR		 5075 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5076 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5077 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5078 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5079 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5080 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
5081 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5082 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
70090424 5083
3090bd9a 5084 RTL_W8(MaxTxPacketSize, EarlySize);
70090424 5085
4521e1a9
FR		 5086 rtl_disable_clock_request(pdev);
5087
70090424
HW		 5088 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5089 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5090
5091 /* Adjust EEE LED frequency */
5092 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5093
5094 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5095 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4521e1a9 5096 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
70090424
HW		 5097}
5098
5f886e08 5099static void rtl_hw_start_8168f(struct rtl8169_private *tp)
c2218925 5100{
beb1fe18
HW		 5101 void __iomem *ioaddr = tp->mmio_addr;
5102 struct pci_dev *pdev = tp->pci_dev;
c2218925 5103
5f886e08 5104 rtl_csi_access_enable_2(tp);
c2218925
HW		 5105
5106 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5107
fdf6fc06
FR		 5108 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5109 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5110 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5111 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5112 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5113 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5114 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5115 rtl_w1w0_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5116 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5117 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
c2218925
HW		 5118
5119 RTL_W8(MaxTxPacketSize, EarlySize);
5120
4521e1a9
FR		 5121 rtl_disable_clock_request(pdev);
5122
c2218925
HW		 5123 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5124 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
c2218925 5125 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4521e1a9
FR		 5126 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5127 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
c2218925
HW		 5128}
5129
5f886e08
HW		 5130static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5131{
5132 void __iomem *ioaddr = tp->mmio_addr;
5133 static const struct ephy_info e_info_8168f_1[] = {
5134 { 0x06, 0x00c0, 0x0020 },
5135 { 0x08, 0x0001, 0x0002 },
5136 { 0x09, 0x0000, 0x0080 },
5137 { 0x19, 0x0000, 0x0224 }
5138 };
5139
5140 rtl_hw_start_8168f(tp);
5141
fdf6fc06 5142 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5f886e08 5143
fdf6fc06 5144 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5f886e08
HW		 5145
5146 /* Adjust EEE LED frequency */
5147 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5148}
5149
b3d7b2f2
HW		 5150static void rtl_hw_start_8411(struct rtl8169_private *tp)
5151{
b3d7b2f2
HW		 5152 static const struct ephy_info e_info_8168f_1[] = {
5153 { 0x06, 0x00c0, 0x0020 },
5154 { 0x0f, 0xffff, 0x5200 },
5155 { 0x1e, 0x0000, 0x4000 },
5156 { 0x19, 0x0000, 0x0224 }
5157 };
5158
5159 rtl_hw_start_8168f(tp);
5160
fdf6fc06 5161 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
b3d7b2f2 5162
fdf6fc06 5163 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
b3d7b2f2
HW		 5164}
5165
c558386b
HW		 5166static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5167{
5168 void __iomem *ioaddr = tp->mmio_addr;
5169 struct pci_dev *pdev = tp->pci_dev;
5170
beb330a4 5171 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5172
c558386b
HW		 5173 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
5174 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5175 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5176 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5177
5178 rtl_csi_access_enable_1(tp);
5179
5180 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5181
5182 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5183 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
beb330a4 5184 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
c558386b
HW		 5185
5186 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4521e1a9 5187 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
c558386b
HW		 5188 RTL_W8(MaxTxPacketSize, EarlySize);
5189
5190 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5191 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5192
5193 /* Adjust EEE LED frequency */
5194 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5195
beb330a4 5196 rtl_w1w0_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5197 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
c558386b
HW		 5198}
5199
57538c4a 5200static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
5201{
5202 void __iomem *ioaddr = tp->mmio_addr;
5203 static const struct ephy_info e_info_8168g_2[] = {
5204 { 0x00, 0x0000, 0x0008 },
5205 { 0x0c, 0x3df0, 0x0200 },
5206 { 0x19, 0xffff, 0xfc00 },
5207 { 0x1e, 0xffff, 0x20eb }
5208 };
5209
5210 rtl_hw_start_8168g_1(tp);
5211
5212 /* disable aspm and clock request before access ephy */
5213 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
5214 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
5215 rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
5216}
5217
07ce4064
FR		 5218static void rtl_hw_start_8168(struct net_device *dev)
5219{
2dd99530
FR		 5220 struct rtl8169_private *tp = netdev_priv(dev);
5221 void __iomem *ioaddr = tp->mmio_addr;
5222
5223 RTL_W8(Cfg9346, Cfg9346_Unlock);
5224
f0298f81 5225 RTL_W8(MaxTxPacketSize, TxPacketMax);
2dd99530 5226
6f0333b8 5227 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
2dd99530 5228
0e485150 5229 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 5230
5231 RTL_W16(CPlusCmd, tp->cp_cmd);
5232
0e485150 5233 RTL_W16(IntrMitigate, 0x5151);
2dd99530 5234
0e485150 5235 /* Work around for RxFIFO overflow. */
811fd301 5236 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
da78dbff
FR		 5237 tp->event_slow |= RxFIFOOver | PCSTimeout;
5238 tp->event_slow &= ~RxOverflow;
0e485150
FR		 5239 }
5240
5241 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530 5242
b8363901
FR		 5243 rtl_set_rx_mode(dev);
5244
5245 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
5246 (InterFrameGap << TxInterFrameGapShift));
2dd99530
FR		 5247
5248 RTL_R8(IntrMask);
5249
219a1e9d
FR		 5250 switch (tp->mac_version) {
5251 case RTL_GIGA_MAC_VER_11:
beb1fe18 5252 rtl_hw_start_8168bb(tp);
4804b3b3 5253 break;
219a1e9d
FR		 5254
5255 case RTL_GIGA_MAC_VER_12:
5256 case RTL_GIGA_MAC_VER_17:
beb1fe18 5257 rtl_hw_start_8168bef(tp);
4804b3b3 5258 break;
219a1e9d
FR		 5259
5260 case RTL_GIGA_MAC_VER_18:
beb1fe18 5261 rtl_hw_start_8168cp_1(tp);
4804b3b3 5262 break;
219a1e9d
FR		 5263
5264 case RTL_GIGA_MAC_VER_19:
beb1fe18 5265 rtl_hw_start_8168c_1(tp);
4804b3b3 5266 break;
219a1e9d
FR		 5267
5268 case RTL_GIGA_MAC_VER_20:
beb1fe18 5269 rtl_hw_start_8168c_2(tp);
4804b3b3 5270 break;
219a1e9d 5271
197ff761 5272 case RTL_GIGA_MAC_VER_21:
beb1fe18 5273 rtl_hw_start_8168c_3(tp);
4804b3b3 5274 break;
197ff761 5275
6fb07058 5276 case RTL_GIGA_MAC_VER_22:
beb1fe18 5277 rtl_hw_start_8168c_4(tp);
4804b3b3 5278 break;
6fb07058 5279
ef3386f0 5280 case RTL_GIGA_MAC_VER_23:
beb1fe18 5281 rtl_hw_start_8168cp_2(tp);
4804b3b3 5282 break;
ef3386f0 5283
7f3e3d3a 5284 case RTL_GIGA_MAC_VER_24:
beb1fe18 5285 rtl_hw_start_8168cp_3(tp);
4804b3b3 5286 break;
7f3e3d3a 5287
5b538df9 5288 case RTL_GIGA_MAC_VER_25:
daf9df6d 5289 case RTL_GIGA_MAC_VER_26:
5290 case RTL_GIGA_MAC_VER_27:
beb1fe18 5291 rtl_hw_start_8168d(tp);
4804b3b3 5292 break;
5b538df9 5293
e6de30d6 5294 case RTL_GIGA_MAC_VER_28:
beb1fe18 5295 rtl_hw_start_8168d_4(tp);
4804b3b3 5296 break;
cecb5fd7 5297
4804b3b3 5298 case RTL_GIGA_MAC_VER_31:
beb1fe18 5299 rtl_hw_start_8168dp(tp);
4804b3b3 5300 break;
5301
01dc7fec 5302 case RTL_GIGA_MAC_VER_32:
5303 case RTL_GIGA_MAC_VER_33:
beb1fe18 5304 rtl_hw_start_8168e_1(tp);
70090424
HW		 5305 break;
5306 case RTL_GIGA_MAC_VER_34:
beb1fe18 5307 rtl_hw_start_8168e_2(tp);
01dc7fec 5308 break;
e6de30d6 5309
c2218925
HW		 5310 case RTL_GIGA_MAC_VER_35:
5311 case RTL_GIGA_MAC_VER_36:
beb1fe18 5312 rtl_hw_start_8168f_1(tp);
c2218925
HW		 5313 break;
5314
b3d7b2f2
HW		 5315 case RTL_GIGA_MAC_VER_38:
5316 rtl_hw_start_8411(tp);
5317 break;
5318
c558386b
HW		 5319 case RTL_GIGA_MAC_VER_40:
5320 case RTL_GIGA_MAC_VER_41:
5321 rtl_hw_start_8168g_1(tp);
5322 break;
57538c4a 5323 case RTL_GIGA_MAC_VER_42:
5324 rtl_hw_start_8168g_2(tp);
5325 break;
c558386b 5326
219a1e9d
FR		 5327 default:
5328 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
5329 dev->name, tp->mac_version);
4804b3b3 5330 break;
219a1e9d 5331 }
2dd99530 5332
0e485150
FR		 5333 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5334
b8363901
FR		 5335 RTL_W8(Cfg9346, Cfg9346_Lock);
5336
2dd99530 5337 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
07ce4064 5338}
1da177e4 5339
2857ffb7
FR		 5340#define R810X_CPCMD_QUIRK_MASK (\
5341 EnableBist | \
5342 Mac_dbgo_oe | \
5343 Force_half_dup | \
5edcc537 5344 Force_rxflow_en | \
2857ffb7
FR		 5345 Force_txflow_en | \
5346 Cxpl_dbg_sel | \
5347 ASF | \
5348 PktCntrDisable | \
d24e9aaf 5349 Mac_dbgo_sel)
2857ffb7 5350
beb1fe18 5351static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
2857ffb7 5352{
beb1fe18
HW		 5353 void __iomem *ioaddr = tp->mmio_addr;
5354 struct pci_dev *pdev = tp->pci_dev;
350f7596 5355 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 5356 { 0x01, 0, 0x6e65 },
5357 { 0x02, 0, 0x091f },
5358 { 0x03, 0, 0xc2f9 },
5359 { 0x06, 0, 0xafb5 },
5360 { 0x07, 0, 0x0e00 },
5361 { 0x19, 0, 0xec80 },
5362 { 0x01, 0, 0x2e65 },
5363 { 0x01, 0, 0x6e65 }
5364 };
5365 u8 cfg1;
5366
beb1fe18 5367 rtl_csi_access_enable_2(tp);
2857ffb7
FR		 5368
5369 RTL_W8(DBG_REG, FIX_NAK_1);
5370
5371 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5372
5373 RTL_W8(Config1,
5374 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5375 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5376
5377 cfg1 = RTL_R8(Config1);
5378 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5379 RTL_W8(Config1, cfg1 & ~LEDS0);
5380
fdf6fc06 5381 rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
2857ffb7
FR		 5382}
5383
beb1fe18 5384static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
2857ffb7 5385{
beb1fe18
HW		 5386 void __iomem *ioaddr = tp->mmio_addr;
5387 struct pci_dev *pdev = tp->pci_dev;
5388
5389 rtl_csi_access_enable_2(tp);
2857ffb7
FR		 5390
5391 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5392
5393 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
5394 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2857ffb7
FR		 5395}
5396
beb1fe18 5397static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
2857ffb7 5398{
beb1fe18 5399 rtl_hw_start_8102e_2(tp);
2857ffb7 5400
fdf6fc06 5401 rtl_ephy_write(tp, 0x03, 0xc2f9);
2857ffb7
FR		 5402}
5403
beb1fe18 5404static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5a5e4443 5405{
beb1fe18 5406 void __iomem *ioaddr = tp->mmio_addr;
5a5e4443
HW		 5407 static const struct ephy_info e_info_8105e_1[] = {
5408 { 0x07, 0, 0x4000 },
5409 { 0x19, 0, 0x0200 },
5410 { 0x19, 0, 0x0020 },
5411 { 0x1e, 0, 0x2000 },
5412 { 0x03, 0, 0x0001 },
5413 { 0x19, 0, 0x0100 },
5414 { 0x19, 0, 0x0004 },
5415 { 0x0a, 0, 0x0020 }
5416 };
5417
cecb5fd7 5418 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5a5e4443
HW		 5419 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5420
cecb5fd7 5421 /* Disable Early Tally Counter */
5a5e4443
HW		 5422 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
5423
5424 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4f6b00e5 5425 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5a5e4443 5426
fdf6fc06 5427 rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
5a5e4443
HW		 5428}
5429
beb1fe18 5430static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5a5e4443 5431{
beb1fe18 5432 rtl_hw_start_8105e_1(tp);
fdf6fc06 5433 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5a5e4443
HW		 5434}
5435
7e18dca1
HW		 5436static void rtl_hw_start_8402(struct rtl8169_private *tp)
5437{
5438 void __iomem *ioaddr = tp->mmio_addr;
5439 static const struct ephy_info e_info_8402[] = {
5440 { 0x19, 0xffff, 0xff64 },
5441 { 0x1e, 0, 0x4000 }
5442 };
5443
5444 rtl_csi_access_enable_2(tp);
5445
5446 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5447 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5448
5449 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5450 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5451
fdf6fc06 5452 rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
7e18dca1
HW		 5453
5454 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
5455
fdf6fc06
FR		 5456 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
5457 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
5458 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5459 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5460 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5461 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5462 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
7e18dca1
HW		 5463}
5464
5598bfe5
HW		 5465static void rtl_hw_start_8106(struct rtl8169_private *tp)
5466{
5467 void __iomem *ioaddr = tp->mmio_addr;
5468
5469 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5470 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5471
4521e1a9 5472 RTL_W32(MISC, (RTL_R32(MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5598bfe5
HW		 5473 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
5474 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
5475}
5476
07ce4064
FR		 5477static void rtl_hw_start_8101(struct net_device *dev)
5478{
cdf1a608
FR		 5479 struct rtl8169_private *tp = netdev_priv(dev);
5480 void __iomem *ioaddr = tp->mmio_addr;
5481 struct pci_dev *pdev = tp->pci_dev;
5482
da78dbff
FR		 5483 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5484 tp->event_slow &= ~RxFIFOOver;
811fd301 5485
cecb5fd7 5486 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
7d7903b2 5487 tp->mac_version == RTL_GIGA_MAC_VER_16)
8200bc72
BH		 5488 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL,
5489 PCI_EXP_DEVCTL_NOSNOOP_EN);
cdf1a608 5490
d24e9aaf
HW		 5491 RTL_W8(Cfg9346, Cfg9346_Unlock);
5492
2857ffb7
FR		 5493 switch (tp->mac_version) {
5494 case RTL_GIGA_MAC_VER_07:
beb1fe18 5495 rtl_hw_start_8102e_1(tp);
2857ffb7
FR		 5496 break;
5497
5498 case RTL_GIGA_MAC_VER_08:
beb1fe18 5499 rtl_hw_start_8102e_3(tp);
2857ffb7
FR		 5500 break;
5501
5502 case RTL_GIGA_MAC_VER_09:
beb1fe18 5503 rtl_hw_start_8102e_2(tp);
2857ffb7 5504 break;
5a5e4443
HW		 5505
5506 case RTL_GIGA_MAC_VER_29:
beb1fe18 5507 rtl_hw_start_8105e_1(tp);
5a5e4443
HW		 5508 break;
5509 case RTL_GIGA_MAC_VER_30:
beb1fe18 5510 rtl_hw_start_8105e_2(tp);
5a5e4443 5511 break;
7e18dca1
HW		 5512
5513 case RTL_GIGA_MAC_VER_37:
5514 rtl_hw_start_8402(tp);
5515 break;
5598bfe5
HW		 5516
5517 case RTL_GIGA_MAC_VER_39:
5518 rtl_hw_start_8106(tp);
5519 break;
cdf1a608
FR		 5520 }
5521
d24e9aaf 5522 RTL_W8(Cfg9346, Cfg9346_Lock);
cdf1a608 5523
f0298f81 5524 RTL_W8(MaxTxPacketSize, TxPacketMax);
cdf1a608 5525
6f0333b8 5526 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
cdf1a608 5527
d24e9aaf 5528 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
cdf1a608
FR		 5529 RTL_W16(CPlusCmd, tp->cp_cmd);
5530
5531 RTL_W16(IntrMitigate, 0x0000);
5532
5533 rtl_set_rx_tx_desc_registers(tp, ioaddr);
5534
5535 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5536 rtl_set_rx_tx_config_registers(tp);
5537
cdf1a608
FR		 5538 RTL_R8(IntrMask);
5539
cdf1a608
FR		 5540 rtl_set_rx_mode(dev);
5541
5542 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
1da177e4
LT		 5543}
5544
5545static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5546{
d58d46b5
FR		 5547 struct rtl8169_private *tp = netdev_priv(dev);
5548
5549 if (new_mtu < ETH_ZLEN ||
5550 new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
1da177e4
LT		 5551 return -EINVAL;
5552
d58d46b5
FR		 5553 if (new_mtu > ETH_DATA_LEN)
5554 rtl_hw_jumbo_enable(tp);
5555 else
5556 rtl_hw_jumbo_disable(tp);
5557
1da177e4 5558 dev->mtu = new_mtu;
350fb32a
MM		 5559 netdev_update_features(dev);
5560
323bb685 5561 return 0;
1da177e4
LT		 5562}
5563
5564static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5565{
95e0918d 5566 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 5567 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5568}
5569
6f0333b8
ED		 5570static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5571 void **data_buff, struct RxDesc *desc)
1da177e4 5572{
48addcc9 5573 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
231aee63 5574 DMA_FROM_DEVICE);
48addcc9 5575
6f0333b8
ED		 5576 kfree(*data_buff);
5577 *data_buff = NULL;
1da177e4
LT		 5578 rtl8169_make_unusable_by_asic(desc);
5579}
5580
5581static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
5582{
5583 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5584
5585 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
5586}
5587
5588static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
5589 u32 rx_buf_sz)
5590{
5591 desc->addr = cpu_to_le64(mapping);
5592 wmb();
5593 rtl8169_mark_to_asic(desc, rx_buf_sz);
5594}
5595
6f0333b8
ED		 5596static inline void *rtl8169_align(void *data)
5597{
5598 return (void *)ALIGN((long)data, 16);
5599}
5600
0ecbe1ca
SG		 5601static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5602 struct RxDesc *desc)
1da177e4 5603{
6f0333b8 5604 void *data;
1da177e4 5605 dma_addr_t mapping;
48addcc9 5606 struct device *d = &tp->pci_dev->dev;
0ecbe1ca 5607 struct net_device *dev = tp->dev;
6f0333b8 5608 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
1da177e4 5609
6f0333b8
ED		 5610 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
5611 if (!data)
5612 return NULL;
e9f63f30 5613
6f0333b8
ED		 5614 if (rtl8169_align(data) != data) {
5615 kfree(data);
5616 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
5617 if (!data)
5618 return NULL;
5619 }
3eafe507 5620
48addcc9 5621 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
231aee63 5622 DMA_FROM_DEVICE);
d827d86b
SG		 5623 if (unlikely(dma_mapping_error(d, mapping))) {
5624 if (net_ratelimit())
5625 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
3eafe507 5626 goto err_out;
d827d86b 5627 }
1da177e4
LT		 5628
5629 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6f0333b8 5630 return data;
3eafe507
SG		 5631
5632err_out:
5633 kfree(data);
5634 return NULL;
1da177e4
LT		 5635}
5636
5637static void rtl8169_rx_clear(struct rtl8169_private *tp)
5638{
07d3f51f 5639 unsigned int i;
1da177e4
LT		 5640
5641 for (i = 0; i < NUM_RX_DESC; i++) {
6f0333b8
ED		 5642 if (tp->Rx_databuff[i]) {
5643 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
1da177e4
LT		 5644 tp->RxDescArray + i);
5645 }
5646 }
5647}
5648
0ecbe1ca 5649static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1da177e4 5650{
0ecbe1ca
SG		 5651 desc->opts1 |= cpu_to_le32(RingEnd);
5652}
5b0384f4 5653
0ecbe1ca
SG		 5654static int rtl8169_rx_fill(struct rtl8169_private *tp)
5655{
5656 unsigned int i;
1da177e4 5657
0ecbe1ca
SG		 5658 for (i = 0; i < NUM_RX_DESC; i++) {
5659 void *data;
4ae47c2d 5660
6f0333b8 5661 if (tp->Rx_databuff[i])
1da177e4 5662 continue;
bcf0bf90 5663
0ecbe1ca 5664 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6f0333b8
ED		 5665 if (!data) {
5666 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
0ecbe1ca 5667 goto err_out;
6f0333b8
ED		 5668 }
5669 tp->Rx_databuff[i] = data;
1da177e4 5670 }
1da177e4 5671
0ecbe1ca
SG		 5672 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5673 return 0;
5674
5675err_out:
5676 rtl8169_rx_clear(tp);
5677 return -ENOMEM;
1da177e4
LT		 5678}
5679
1da177e4
LT		 5680static int rtl8169_init_ring(struct net_device *dev)
5681{
5682 struct rtl8169_private *tp = netdev_priv(dev);
5683
5684 rtl8169_init_ring_indexes(tp);
5685
5686 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
6f0333b8 5687 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
1da177e4 5688
0ecbe1ca 5689 return rtl8169_rx_fill(tp);
1da177e4
LT		 5690}
5691
48addcc9 5692static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
1da177e4
LT		 5693 struct TxDesc *desc)
5694{
5695 unsigned int len = tx_skb->len;
5696
48addcc9
SG		 5697 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5698
1da177e4
LT		 5699 desc->opts1 = 0x00;
5700 desc->opts2 = 0x00;
5701 desc->addr = 0x00;
5702 tx_skb->len = 0;
5703}
5704
3eafe507
SG		 5705static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5706 unsigned int n)
1da177e4
LT		 5707{
5708 unsigned int i;
5709
3eafe507
SG		 5710 for (i = 0; i < n; i++) {
5711 unsigned int entry = (start + i) % NUM_TX_DESC;
1da177e4
LT		 5712 struct ring_info *tx_skb = tp->tx_skb + entry;
5713 unsigned int len = tx_skb->len;
5714
5715 if (len) {
5716 struct sk_buff *skb = tx_skb->skb;
5717
48addcc9 5718 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
1da177e4
LT		 5719 tp->TxDescArray + entry);
5720 if (skb) {
cac4b22f 5721 tp->dev->stats.tx_dropped++;
1da177e4
LT		 5722 dev_kfree_skb(skb);
5723 tx_skb->skb = NULL;
5724 }
1da177e4
LT		 5725 }
5726 }
3eafe507
SG		 5727}
5728
5729static void rtl8169_tx_clear(struct rtl8169_private *tp)
5730{
5731 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
1da177e4
LT		 5732 tp->cur_tx = tp->dirty_tx = 0;
5733}
5734
4422bcd4 5735static void rtl_reset_work(struct rtl8169_private *tp)
1da177e4 5736{
c4028958 5737 struct net_device *dev = tp->dev;
56de414c 5738 int i;
1da177e4 5739
da78dbff
FR		 5740 napi_disable(&tp->napi);
5741 netif_stop_queue(dev);
5742 synchronize_sched();
1da177e4 5743
c7c2c39b 5744 rtl8169_hw_reset(tp);
5745
56de414c
FR		 5746 for (i = 0; i < NUM_RX_DESC; i++)
5747 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
5748
1da177e4 5749 rtl8169_tx_clear(tp);
c7c2c39b 5750 rtl8169_init_ring_indexes(tp);
1da177e4 5751
da78dbff 5752 napi_enable(&tp->napi);
56de414c
FR		 5753 rtl_hw_start(dev);
5754 netif_wake_queue(dev);
5755 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1da177e4
LT		 5756}
5757
5758static void rtl8169_tx_timeout(struct net_device *dev)
5759{
da78dbff
FR		 5760 struct rtl8169_private *tp = netdev_priv(dev);
5761
5762 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 5763}
5764
5765static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2b7b4318 5766 u32 *opts)
1da177e4
LT		 5767{
5768 struct skb_shared_info *info = skb_shinfo(skb);
5769 unsigned int cur_frag, entry;
a6343afb 5770 struct TxDesc * uninitialized_var(txd);
48addcc9 5771 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 5772
5773 entry = tp->cur_tx;
5774 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
9e903e08 5775 const skb_frag_t *frag = info->frags + cur_frag;
1da177e4
LT		 5776 dma_addr_t mapping;
5777 u32 status, len;
5778 void *addr;
5779
5780 entry = (entry + 1) % NUM_TX_DESC;
5781
5782 txd = tp->TxDescArray + entry;
9e903e08 5783 len = skb_frag_size(frag);
929f6189 5784 addr = skb_frag_address(frag);
48addcc9 5785 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
d827d86b
SG		 5786 if (unlikely(dma_mapping_error(d, mapping))) {
5787 if (net_ratelimit())
5788 netif_err(tp, drv, tp->dev,
5789 "Failed to map TX fragments DMA!\n");
3eafe507 5790 goto err_out;
d827d86b 5791 }
1da177e4 5792
cecb5fd7 5793 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318
FR		 5794 status = opts[0] | len |
5795 (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 5796
5797 txd->opts1 = cpu_to_le32(status);
2b7b4318 5798 txd->opts2 = cpu_to_le32(opts[1]);
1da177e4
LT		 5799 txd->addr = cpu_to_le64(mapping);
5800
5801 tp->tx_skb[entry].len = len;
5802 }
5803
5804 if (cur_frag) {
5805 tp->tx_skb[entry].skb = skb;
5806 txd->opts1 |= cpu_to_le32(LastFrag);
5807 }
5808
5809 return cur_frag;
3eafe507
SG		 5810
5811err_out:
5812 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5813 return -EIO;
1da177e4
LT		 5814}
5815
2b7b4318
FR		 5816static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
5817 struct sk_buff *skb, u32 *opts)
1da177e4 5818{
2b7b4318 5819 const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
350fb32a 5820 u32 mss = skb_shinfo(skb)->gso_size;
2b7b4318 5821 int offset = info->opts_offset;
350fb32a 5822
2b7b4318
FR		 5823 if (mss) {
5824 opts[0] |= TD_LSO;
5825 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
5826 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 5827 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 5828
5829 if (ip->protocol == IPPROTO_TCP)
2b7b4318 5830 opts[offset] |= info->checksum.tcp;
1da177e4 5831 else if (ip->protocol == IPPROTO_UDP)
2b7b4318
FR		 5832 opts[offset] |= info->checksum.udp;
5833 else
5834 WARN_ON_ONCE(1);
1da177e4 5835 }
1da177e4
LT		 5836}
5837
61357325
SH		 5838static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5839 struct net_device *dev)
1da177e4
LT		 5840{
5841 struct rtl8169_private *tp = netdev_priv(dev);
3eafe507 5842 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
1da177e4
LT		 5843 struct TxDesc *txd = tp->TxDescArray + entry;
5844 void __iomem *ioaddr = tp->mmio_addr;
48addcc9 5845 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 5846 dma_addr_t mapping;
5847 u32 status, len;
2b7b4318 5848 u32 opts[2];
3eafe507 5849 int frags;
5b0384f4 5850
477206a0 5851 if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
bf82c189 5852 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
3eafe507 5853 goto err_stop_0;
1da177e4
LT		 5854 }
5855
5856 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3eafe507
SG		 5857 goto err_stop_0;
5858
5859 len = skb_headlen(skb);
48addcc9 5860 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
d827d86b
SG		 5861 if (unlikely(dma_mapping_error(d, mapping))) {
5862 if (net_ratelimit())
5863 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
3eafe507 5864 goto err_dma_0;
d827d86b 5865 }
3eafe507
SG		 5866
5867 tp->tx_skb[entry].len = len;
5868 txd->addr = cpu_to_le64(mapping);
1da177e4 5869
810f4893 5870 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
2b7b4318 5871 opts[0] = DescOwn;
1da177e4 5872
2b7b4318
FR		 5873 rtl8169_tso_csum(tp, skb, opts);
5874
5875 frags = rtl8169_xmit_frags(tp, skb, opts);
3eafe507
SG		 5876 if (frags < 0)
5877 goto err_dma_1;
5878 else if (frags)
2b7b4318 5879 opts[0] |= FirstFrag;
3eafe507 5880 else {
2b7b4318 5881 opts[0] |= FirstFrag | LastFrag;
1da177e4
LT		 5882 tp->tx_skb[entry].skb = skb;
5883 }
5884
2b7b4318
FR		 5885 txd->opts2 = cpu_to_le32(opts[1]);
5886
5047fb5d
RC		 5887 skb_tx_timestamp(skb);
5888
1da177e4
LT		 5889 wmb();
5890
cecb5fd7 5891 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318 5892 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 5893 txd->opts1 = cpu_to_le32(status);
5894
1da177e4
LT		 5895 tp->cur_tx += frags + 1;
5896
4c020a96 5897 wmb();
1da177e4 5898
cecb5fd7 5899 RTL_W8(TxPoll, NPQ);
1da177e4 5900
da78dbff
FR		 5901 mmiowb();
5902
477206a0 5903 if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
ae1f23fb
FR		 5904 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
5905 * not miss a ring update when it notices a stopped queue.
5906 */
5907 smp_wmb();
1da177e4 5908 netif_stop_queue(dev);
ae1f23fb
FR		 5909 /* Sync with rtl_tx:
5910 * - publish queue status and cur_tx ring index (write barrier)
5911 * - refresh dirty_tx ring index (read barrier).
5912 * May the current thread have a pessimistic view of the ring
5913 * status and forget to wake up queue, a racing rtl_tx thread
5914 * can't.
5915 */
1e874e04 5916 smp_mb();
477206a0 5917 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
1da177e4
LT		 5918 netif_wake_queue(dev);
5919 }
5920
61357325 5921 return NETDEV_TX_OK;
1da177e4 5922
3eafe507 5923err_dma_1:
48addcc9 5924 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
3eafe507
SG		 5925err_dma_0:
5926 dev_kfree_skb(skb);
5927 dev->stats.tx_dropped++;
5928 return NETDEV_TX_OK;
5929
5930err_stop_0:
1da177e4 5931 netif_stop_queue(dev);
cebf8cc7 5932 dev->stats.tx_dropped++;
61357325 5933 return NETDEV_TX_BUSY;
1da177e4
LT		 5934}
5935
5936static void rtl8169_pcierr_interrupt(struct net_device *dev)
5937{
5938 struct rtl8169_private *tp = netdev_priv(dev);
5939 struct pci_dev *pdev = tp->pci_dev;
1da177e4
LT		 5940 u16 pci_status, pci_cmd;
5941
5942 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5943 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5944
bf82c189
JP		 5945 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5946 pci_cmd, pci_status);
1da177e4
LT		 5947
5948 /*
5949 * The recovery sequence below admits a very elaborated explanation:
5950 * - it seems to work;
d03902b8
FR		 5951 * - I did not see what else could be done;
5952 * - it makes iop3xx happy.
1da177e4
LT		 5953 *
5954 * Feel free to adjust to your needs.
5955 */
a27993f3 5956 if (pdev->broken_parity_status)
d03902b8
FR		 5957 pci_cmd &= ~PCI_COMMAND_PARITY;
5958 else
5959 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5960
5961 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 5962
5963 pci_write_config_word(pdev, PCI_STATUS,
5964 pci_status & (PCI_STATUS_DETECTED_PARITY |
5965 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5966 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5967
5968 /* The infamous DAC f*ckup only happens at boot time */
9fba0812 5969 if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
e6de30d6 5970 void __iomem *ioaddr = tp->mmio_addr;
5971
bf82c189 5972 netif_info(tp, intr, dev, "disabling PCI DAC\n");
1da177e4
LT		 5973 tp->cp_cmd &= ~PCIDAC;
5974 RTL_W16(CPlusCmd, tp->cp_cmd);
5975 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 5976 }
5977
e6de30d6 5978 rtl8169_hw_reset(tp);
d03902b8 5979
98ddf986 5980 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 5981}
5982
da78dbff 5983static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
1da177e4
LT		 5984{
5985 unsigned int dirty_tx, tx_left;
5986
1da177e4
LT		 5987 dirty_tx = tp->dirty_tx;
5988 smp_rmb();
5989 tx_left = tp->cur_tx - dirty_tx;
5990
5991 while (tx_left > 0) {
5992 unsigned int entry = dirty_tx % NUM_TX_DESC;
5993 struct ring_info *tx_skb = tp->tx_skb + entry;
1da177e4
LT		 5994 u32 status;
5995
5996 rmb();
5997 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5998 if (status & DescOwn)
5999 break;
6000
48addcc9
SG		 6001 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
6002 tp->TxDescArray + entry);
1da177e4 6003 if (status & LastFrag) {
17bcb684
FR		 6004 u64_stats_update_begin(&tp->tx_stats.syncp);
6005 tp->tx_stats.packets++;
6006 tp->tx_stats.bytes += tx_skb->skb->len;
6007 u64_stats_update_end(&tp->tx_stats.syncp);
6008 dev_kfree_skb(tx_skb->skb);
1da177e4
LT		 6009 tx_skb->skb = NULL;
6010 }
6011 dirty_tx++;
6012 tx_left--;
6013 }
6014
6015 if (tp->dirty_tx != dirty_tx) {
6016 tp->dirty_tx = dirty_tx;
ae1f23fb
FR		 6017 /* Sync with rtl8169_start_xmit:
6018 * - publish dirty_tx ring index (write barrier)
6019 * - refresh cur_tx ring index and queue status (read barrier)
6020 * May the current thread miss the stopped queue condition,
6021 * a racing xmit thread can only have a right view of the
6022 * ring status.
6023 */
1e874e04 6024 smp_mb();
1da177e4 6025 if (netif_queue_stopped(dev) &&
477206a0 6026 TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
1da177e4
LT		 6027 netif_wake_queue(dev);
6028 }
d78ae2dc
FR		 6029 /*
6030 * 8168 hack: TxPoll requests are lost when the Tx packets are
6031 * too close. Let's kick an extra TxPoll request when a burst
6032 * of start_xmit activity is detected (if it is not detected,
6033 * it is slow enough). -- FR
6034 */
da78dbff
FR		 6035 if (tp->cur_tx != dirty_tx) {
6036 void __iomem *ioaddr = tp->mmio_addr;
6037
d78ae2dc 6038 RTL_W8(TxPoll, NPQ);
da78dbff 6039 }
1da177e4
LT		 6040 }
6041}
6042
126fa4b9
FR		 6043static inline int rtl8169_fragmented_frame(u32 status)
6044{
6045 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
6046}
6047
adea1ac7 6048static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
1da177e4 6049{
1da177e4
LT		 6050 u32 status = opts1 & RxProtoMask;
6051
6052 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
d5d3ebe3 6053 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
1da177e4
LT		 6054 skb->ip_summed = CHECKSUM_UNNECESSARY;
6055 else
bc8acf2c 6056 skb_checksum_none_assert(skb);
1da177e4
LT		 6057}
6058
6f0333b8
ED		 6059static struct sk_buff *rtl8169_try_rx_copy(void *data,
6060 struct rtl8169_private *tp,
6061 int pkt_size,
6062 dma_addr_t addr)
1da177e4 6063{
b449655f 6064 struct sk_buff *skb;
48addcc9 6065 struct device *d = &tp->pci_dev->dev;
b449655f 6066
6f0333b8 6067 data = rtl8169_align(data);
48addcc9 6068 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6f0333b8
ED		 6069 prefetch(data);
6070 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
6071 if (skb)
6072 memcpy(skb->data, data, pkt_size);
48addcc9
SG		 6073 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
6074
6f0333b8 6075 return skb;
1da177e4
LT		 6076}
6077
da78dbff 6078static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
1da177e4
LT		 6079{
6080 unsigned int cur_rx, rx_left;
6f0333b8 6081 unsigned int count;
1da177e4 6082
1da177e4 6083 cur_rx = tp->cur_rx;
1da177e4 6084
9fba0812 6085 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
1da177e4 6086 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 6087 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 6088 u32 status;
6089
6090 rmb();
e03f33af 6091 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
1da177e4
LT		 6092
6093 if (status & DescOwn)
6094 break;
4dcb7d33 6095 if (unlikely(status & RxRES)) {
bf82c189
JP		 6096 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6097 status);
cebf8cc7 6098 dev->stats.rx_errors++;
1da177e4 6099 if (status & (RxRWT | RxRUNT))
cebf8cc7 6100 dev->stats.rx_length_errors++;
1da177e4 6101 if (status & RxCRC)
cebf8cc7 6102 dev->stats.rx_crc_errors++;
9dccf611 6103 if (status & RxFOVF) {
da78dbff 6104 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
cebf8cc7 6105 dev->stats.rx_fifo_errors++;
9dccf611 6106 }
6bbe021d
BG		 6107 if ((status & (RxRUNT | RxCRC)) &&
6108 !(status & (RxRWT | RxFOVF)) &&
6109 (dev->features & NETIF_F_RXALL))
6110 goto process_pkt;
1da177e4 6111 } else {
6f0333b8 6112 struct sk_buff *skb;
6bbe021d
BG		 6113 dma_addr_t addr;
6114 int pkt_size;
6115
6116process_pkt:
6117 addr = le64_to_cpu(desc->addr);
79d0c1d2
BG		 6118 if (likely(!(dev->features & NETIF_F_RXFCS)))
6119 pkt_size = (status & 0x00003fff) - 4;
6120 else
6121 pkt_size = status & 0x00003fff;
1da177e4 6122
126fa4b9
FR		 6123 /*
6124 * The driver does not support incoming fragmented
6125 * frames. They are seen as a symptom of over-mtu
6126 * sized frames.
6127 */
6128 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 6129 dev->stats.rx_dropped++;
6130 dev->stats.rx_length_errors++;
ce11ff5e 6131 goto release_descriptor;
126fa4b9
FR		 6132 }
6133
6f0333b8
ED		 6134 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6135 tp, pkt_size, addr);
6f0333b8
ED		 6136 if (!skb) {
6137 dev->stats.rx_dropped++;
ce11ff5e 6138 goto release_descriptor;
1da177e4
LT		 6139 }
6140
adea1ac7 6141 rtl8169_rx_csum(skb, status);
1da177e4
LT		 6142 skb_put(skb, pkt_size);
6143 skb->protocol = eth_type_trans(skb, dev);
6144
7a8fc77b
FR		 6145 rtl8169_rx_vlan_tag(desc, skb);
6146
56de414c 6147 napi_gro_receive(&tp->napi, skb);
1da177e4 6148
8027aa24
JW		 6149 u64_stats_update_begin(&tp->rx_stats.syncp);
6150 tp->rx_stats.packets++;
6151 tp->rx_stats.bytes += pkt_size;
6152 u64_stats_update_end(&tp->rx_stats.syncp);
1da177e4 6153 }
ce11ff5e 6154release_descriptor:
6155 desc->opts2 = 0;
6156 wmb();
6157 rtl8169_mark_to_asic(desc, rx_buf_sz);
1da177e4
LT		 6158 }
6159
6160 count = cur_rx - tp->cur_rx;
6161 tp->cur_rx = cur_rx;
6162
1da177e4
LT		 6163 return count;
6164}
6165
07d3f51f 6166static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 6167{
07d3f51f 6168 struct net_device *dev = dev_instance;
1da177e4 6169 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 6170 int handled = 0;
9085cdfa 6171 u16 status;
1da177e4 6172
9085cdfa 6173 status = rtl_get_events(tp);
da78dbff
FR		 6174 if (status && status != 0xffff) {
6175 status &= RTL_EVENT_NAPI | tp->event_slow;
6176 if (status) {
6177 handled = 1;
1da177e4 6178
da78dbff
FR		 6179 rtl_irq_disable(tp);
6180 napi_schedule(&tp->napi);
f11a377b 6181 }
da78dbff
FR		 6182 }
6183 return IRQ_RETVAL(handled);
6184}
1da177e4 6185
da78dbff
FR		 6186/*
6187 * Workqueue context.
6188 */
6189static void rtl_slow_event_work(struct rtl8169_private *tp)
6190{
6191 struct net_device *dev = tp->dev;
6192 u16 status;
6193
6194 status = rtl_get_events(tp) & tp->event_slow;
6195 rtl_ack_events(tp, status);
1da177e4 6196
da78dbff
FR		 6197 if (unlikely(status & RxFIFOOver)) {
6198 switch (tp->mac_version) {
6199 /* Work around for rx fifo overflow */
6200 case RTL_GIGA_MAC_VER_11:
6201 netif_stop_queue(dev);
934714d0
FR		 6202 /* XXX - Hack alert. See rtl_task(). */
6203 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
da78dbff 6204 default:
f11a377b
DD		 6205 break;
6206 }
da78dbff 6207 }
1da177e4 6208
da78dbff
FR		 6209 if (unlikely(status & SYSErr))
6210 rtl8169_pcierr_interrupt(dev);
0e485150 6211
da78dbff
FR		 6212 if (status & LinkChg)
6213 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
1da177e4 6214
7dbb4918 6215 rtl_irq_enable_all(tp);
1da177e4
LT		 6216}
6217
4422bcd4
FR		 6218static void rtl_task(struct work_struct *work)
6219{
da78dbff
FR		 6220 static const struct {
6221 int bitnr;
6222 void (*action)(struct rtl8169_private *);
6223 } rtl_work[] = {
934714d0 6224 /* XXX - keep rtl_slow_event_work() as first element. */
da78dbff
FR		 6225 { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work },
6226 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
6227 { RTL_FLAG_TASK_PHY_PENDING, rtl_phy_work }
6228 };
4422bcd4
FR		 6229 struct rtl8169_private *tp =
6230 container_of(work, struct rtl8169_private, wk.work);
da78dbff
FR		 6231 struct net_device *dev = tp->dev;
6232 int i;
6233
6234 rtl_lock_work(tp);
6235
6c4a70c5
FR		 6236 if (!netif_running(dev) ||
6237 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
da78dbff
FR		 6238 goto out_unlock;
6239
6240 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6241 bool pending;
6242
da78dbff 6243 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
da78dbff
FR		 6244 if (pending)
6245 rtl_work[i].action(tp);
6246 }
4422bcd4 6247
da78dbff
FR		 6248out_unlock:
6249 rtl_unlock_work(tp);
4422bcd4
FR		 6250}
6251
bea3348e 6252static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 6253{
bea3348e
SH		 6254 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6255 struct net_device *dev = tp->dev;
da78dbff
FR		 6256 u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
6257 int work_done= 0;
6258 u16 status;
6259
6260 status = rtl_get_events(tp);
6261 rtl_ack_events(tp, status & ~tp->event_slow);
6262
6263 if (status & RTL_EVENT_NAPI_RX)
6264 work_done = rtl_rx(dev, tp, (u32) budget);
6265
6266 if (status & RTL_EVENT_NAPI_TX)
6267 rtl_tx(dev, tp);
1da177e4 6268
da78dbff
FR		 6269 if (status & tp->event_slow) {
6270 enable_mask &= ~tp->event_slow;
6271
6272 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
6273 }
1da177e4 6274
bea3348e 6275 if (work_done < budget) {
288379f0 6276 napi_complete(napi);
f11a377b 6277
da78dbff
FR		 6278 rtl_irq_enable(tp, enable_mask);
6279 mmiowb();
1da177e4
LT		 6280 }
6281
bea3348e 6282 return work_done;
1da177e4 6283}
1da177e4 6284
523a6094
FR		 6285static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
6286{
6287 struct rtl8169_private *tp = netdev_priv(dev);
6288
6289 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6290 return;
6291
6292 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
6293 RTL_W32(RxMissed, 0);
6294}
6295
1da177e4
LT		 6296static void rtl8169_down(struct net_device *dev)
6297{
6298 struct rtl8169_private *tp = netdev_priv(dev);
6299 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 6300
4876cc1e 6301 del_timer_sync(&tp->timer);
1da177e4 6302
93dd79e8 6303 napi_disable(&tp->napi);
da78dbff 6304 netif_stop_queue(dev);
1da177e4 6305
92fc43b4 6306 rtl8169_hw_reset(tp);
323bb685
SG		 6307 /*
6308 * At this point device interrupts can not be enabled in any function,
209e5ac8
FR		 6309 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6310 * and napi is disabled (rtl8169_poll).
323bb685 6311 */
523a6094 6312 rtl8169_rx_missed(dev, ioaddr);
1da177e4 6313
1da177e4 6314 /* Give a racing hard_start_xmit a few cycles to complete. */
da78dbff 6315 synchronize_sched();
1da177e4 6316
1da177e4
LT		 6317 rtl8169_tx_clear(tp);
6318
6319 rtl8169_rx_clear(tp);
065c27c1 6320
6321 rtl_pll_power_down(tp);
1da177e4
LT		 6322}
6323
6324static int rtl8169_close(struct net_device *dev)
6325{
6326 struct rtl8169_private *tp = netdev_priv(dev);
6327 struct pci_dev *pdev = tp->pci_dev;
6328
e1759441
RW		 6329 pm_runtime_get_sync(&pdev->dev);
6330
cecb5fd7 6331 /* Update counters before going down */
355423d0
IV		 6332 rtl8169_update_counters(dev);
6333
da78dbff 6334 rtl_lock_work(tp);
6c4a70c5 6335 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
da78dbff 6336
1da177e4 6337 rtl8169_down(dev);
da78dbff 6338 rtl_unlock_work(tp);
1da177e4 6339
92a7c4e7 6340 free_irq(pdev->irq, dev);
1da177e4 6341
82553bb6
SG		 6342 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6343 tp->RxPhyAddr);
6344 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6345 tp->TxPhyAddr);
1da177e4
LT		 6346 tp->TxDescArray = NULL;
6347 tp->RxDescArray = NULL;
6348
e1759441
RW		 6349 pm_runtime_put_sync(&pdev->dev);
6350
1da177e4
LT		 6351 return 0;
6352}
6353
dc1c00ce
FR		 6354#ifdef CONFIG_NET_POLL_CONTROLLER
6355static void rtl8169_netpoll(struct net_device *dev)
6356{
6357 struct rtl8169_private *tp = netdev_priv(dev);
6358
6359 rtl8169_interrupt(tp->pci_dev->irq, dev);
6360}
6361#endif
6362
df43ac78
FR		 6363static int rtl_open(struct net_device *dev)
6364{
6365 struct rtl8169_private *tp = netdev_priv(dev);
6366 void __iomem *ioaddr = tp->mmio_addr;
6367 struct pci_dev *pdev = tp->pci_dev;
6368 int retval = -ENOMEM;
6369
6370 pm_runtime_get_sync(&pdev->dev);
6371
6372 /*
e75d6606 6373 * Rx and Tx descriptors needs 256 bytes alignment.
df43ac78
FR		 6374 * dma_alloc_coherent provides more.
6375 */
6376 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6377 &tp->TxPhyAddr, GFP_KERNEL);
6378 if (!tp->TxDescArray)
6379 goto err_pm_runtime_put;
6380
6381 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6382 &tp->RxPhyAddr, GFP_KERNEL);
6383 if (!tp->RxDescArray)
6384 goto err_free_tx_0;
6385
6386 retval = rtl8169_init_ring(dev);
6387 if (retval < 0)
6388 goto err_free_rx_1;
6389
6390 INIT_WORK(&tp->wk.work, rtl_task);
6391
6392 smp_mb();
6393
6394 rtl_request_firmware(tp);
6395
92a7c4e7 6396 retval = request_irq(pdev->irq, rtl8169_interrupt,
df43ac78
FR		 6397 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
6398 dev->name, dev);
6399 if (retval < 0)
6400 goto err_release_fw_2;
6401
6402 rtl_lock_work(tp);
6403
6404 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6405
6406 napi_enable(&tp->napi);
6407
6408 rtl8169_init_phy(dev, tp);
6409
6410 __rtl8169_set_features(dev, dev->features);
6411
6412 rtl_pll_power_up(tp);
6413
6414 rtl_hw_start(dev);
6415
6416 netif_start_queue(dev);
6417
6418 rtl_unlock_work(tp);
6419
6420 tp->saved_wolopts = 0;
6421 pm_runtime_put_noidle(&pdev->dev);
6422
6423 rtl8169_check_link_status(dev, tp, ioaddr);
6424out:
6425 return retval;
6426
6427err_release_fw_2:
6428 rtl_release_firmware(tp);
6429 rtl8169_rx_clear(tp);
6430err_free_rx_1:
6431 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6432 tp->RxPhyAddr);
6433 tp->RxDescArray = NULL;
6434err_free_tx_0:
6435 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6436 tp->TxPhyAddr);
6437 tp->TxDescArray = NULL;
6438err_pm_runtime_put:
6439 pm_runtime_put_noidle(&pdev->dev);
6440 goto out;
6441}
6442
8027aa24
JW		 6443static struct rtnl_link_stats64 *
6444rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
1da177e4
LT		 6445{
6446 struct rtl8169_private *tp = netdev_priv(dev);
6447 void __iomem *ioaddr = tp->mmio_addr;
8027aa24 6448 unsigned int start;
1da177e4 6449
da78dbff 6450 if (netif_running(dev))
523a6094 6451 rtl8169_rx_missed(dev, ioaddr);
5b0384f4 6452
8027aa24
JW		 6453 do {
6454 start = u64_stats_fetch_begin_bh(&tp->rx_stats.syncp);
6455 stats->rx_packets = tp->rx_stats.packets;
6456 stats->rx_bytes = tp->rx_stats.bytes;
6457 } while (u64_stats_fetch_retry_bh(&tp->rx_stats.syncp, start));
6458
6459
6460 do {
6461 start = u64_stats_fetch_begin_bh(&tp->tx_stats.syncp);
6462 stats->tx_packets = tp->tx_stats.packets;
6463 stats->tx_bytes = tp->tx_stats.bytes;
6464 } while (u64_stats_fetch_retry_bh(&tp->tx_stats.syncp, start));
6465
6466 stats->rx_dropped = dev->stats.rx_dropped;
6467 stats->tx_dropped = dev->stats.tx_dropped;
6468 stats->rx_length_errors = dev->stats.rx_length_errors;
6469 stats->rx_errors = dev->stats.rx_errors;
6470 stats->rx_crc_errors = dev->stats.rx_crc_errors;
6471 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
6472 stats->rx_missed_errors = dev->stats.rx_missed_errors;
6473
6474 return stats;
1da177e4
LT		 6475}
6476
861ab440 6477static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 6478{
065c27c1 6479 struct rtl8169_private *tp = netdev_priv(dev);
6480
5d06a99f 6481 if (!netif_running(dev))
861ab440 6482 return;
5d06a99f
FR		 6483
6484 netif_device_detach(dev);
6485 netif_stop_queue(dev);
da78dbff
FR		 6486
6487 rtl_lock_work(tp);
6488 napi_disable(&tp->napi);
6c4a70c5 6489 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
da78dbff
FR		 6490 rtl_unlock_work(tp);
6491
6492 rtl_pll_power_down(tp);
861ab440
RW		 6493}
6494
6495#ifdef CONFIG_PM
6496
6497static int rtl8169_suspend(struct device *device)
6498{
6499 struct pci_dev *pdev = to_pci_dev(device);
6500 struct net_device *dev = pci_get_drvdata(pdev);
5d06a99f 6501
861ab440 6502 rtl8169_net_suspend(dev);
1371fa6d 6503
5d06a99f
FR		 6504 return 0;
6505}
6506
e1759441
RW		 6507static void __rtl8169_resume(struct net_device *dev)
6508{
065c27c1 6509 struct rtl8169_private *tp = netdev_priv(dev);
6510
e1759441 6511 netif_device_attach(dev);
065c27c1 6512
6513 rtl_pll_power_up(tp);
6514
cff4c162
AS		 6515 rtl_lock_work(tp);
6516 napi_enable(&tp->napi);
6c4a70c5 6517 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
cff4c162 6518 rtl_unlock_work(tp);
da78dbff 6519
98ddf986 6520 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
e1759441
RW		 6521}
6522
861ab440 6523static int rtl8169_resume(struct device *device)
5d06a99f 6524{
861ab440 6525 struct pci_dev *pdev = to_pci_dev(device);
5d06a99f 6526 struct net_device *dev = pci_get_drvdata(pdev);
fccec10b
SG		 6527 struct rtl8169_private *tp = netdev_priv(dev);
6528
6529 rtl8169_init_phy(dev, tp);
5d06a99f 6530
e1759441
RW		 6531 if (netif_running(dev))
6532 __rtl8169_resume(dev);
5d06a99f 6533
e1759441
RW		 6534 return 0;
6535}
6536
6537static int rtl8169_runtime_suspend(struct device *device)
6538{
6539 struct pci_dev *pdev = to_pci_dev(device);
6540 struct net_device *dev = pci_get_drvdata(pdev);
6541 struct rtl8169_private *tp = netdev_priv(dev);
6542
6543 if (!tp->TxDescArray)
6544 return 0;
6545
da78dbff 6546 rtl_lock_work(tp);
e1759441
RW		 6547 tp->saved_wolopts = __rtl8169_get_wol(tp);
6548 __rtl8169_set_wol(tp, WAKE_ANY);
da78dbff 6549 rtl_unlock_work(tp);
e1759441
RW		 6550
6551 rtl8169_net_suspend(dev);
6552
6553 return 0;
6554}
6555
6556static int rtl8169_runtime_resume(struct device *device)
6557{
6558 struct pci_dev *pdev = to_pci_dev(device);
6559 struct net_device *dev = pci_get_drvdata(pdev);
6560 struct rtl8169_private *tp = netdev_priv(dev);
6561
6562 if (!tp->TxDescArray)
6563 return 0;
6564
da78dbff 6565 rtl_lock_work(tp);
e1759441
RW		 6566 __rtl8169_set_wol(tp, tp->saved_wolopts);
6567 tp->saved_wolopts = 0;
da78dbff 6568 rtl_unlock_work(tp);
e1759441 6569
fccec10b
SG		 6570 rtl8169_init_phy(dev, tp);
6571
e1759441 6572 __rtl8169_resume(dev);
5d06a99f 6573
5d06a99f
FR		 6574 return 0;
6575}
6576
e1759441
RW		 6577static int rtl8169_runtime_idle(struct device *device)
6578{
6579 struct pci_dev *pdev = to_pci_dev(device);
6580 struct net_device *dev = pci_get_drvdata(pdev);
6581 struct rtl8169_private *tp = netdev_priv(dev);
6582
e4fbce74 6583 return tp->TxDescArray ? -EBUSY : 0;
e1759441
RW		 6584}
6585
47145210 6586static const struct dev_pm_ops rtl8169_pm_ops = {
cecb5fd7
FR		 6587 .suspend = rtl8169_suspend,
6588 .resume = rtl8169_resume,
6589 .freeze = rtl8169_suspend,
6590 .thaw = rtl8169_resume,
6591 .poweroff = rtl8169_suspend,
6592 .restore = rtl8169_resume,
6593 .runtime_suspend = rtl8169_runtime_suspend,
6594 .runtime_resume = rtl8169_runtime_resume,
6595 .runtime_idle = rtl8169_runtime_idle,
861ab440
RW		 6596};
6597
6598#define RTL8169_PM_OPS (&rtl8169_pm_ops)
6599
6600#else /* !CONFIG_PM */
6601
6602#define RTL8169_PM_OPS NULL
6603
6604#endif /* !CONFIG_PM */
6605
649b3b8c 6606static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6607{
6608 void __iomem *ioaddr = tp->mmio_addr;
6609
6610 /* WoL fails with 8168b when the receiver is disabled. */
6611 switch (tp->mac_version) {
6612 case RTL_GIGA_MAC_VER_11:
6613 case RTL_GIGA_MAC_VER_12:
6614 case RTL_GIGA_MAC_VER_17:
6615 pci_clear_master(tp->pci_dev);
6616
6617 RTL_W8(ChipCmd, CmdRxEnb);
6618 /* PCI commit */
6619 RTL_R8(ChipCmd);
6620 break;
6621 default:
6622 break;
6623 }
6624}
6625
1765f95d
FR		 6626static void rtl_shutdown(struct pci_dev *pdev)
6627{
861ab440 6628 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 6629 struct rtl8169_private *tp = netdev_priv(dev);
2a15cd2f 6630 struct device *d = &pdev->dev;
6631
6632 pm_runtime_get_sync(d);
861ab440
RW		 6633
6634 rtl8169_net_suspend(dev);
1765f95d 6635
cecb5fd7 6636 /* Restore original MAC address */
cc098dc7
IV		 6637 rtl_rar_set(tp, dev->perm_addr);
6638
92fc43b4 6639 rtl8169_hw_reset(tp);
4bb3f522 6640
861ab440 6641 if (system_state == SYSTEM_POWER_OFF) {
649b3b8c 6642 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
6643 rtl_wol_suspend_quirk(tp);
6644 rtl_wol_shutdown_quirk(tp);
ca52efd5 6645 }
6646
861ab440
RW		 6647 pci_wake_from_d3(pdev, true);
6648 pci_set_power_state(pdev, PCI_D3hot);
6649 }
2a15cd2f 6650
6651 pm_runtime_put_noidle(d);
861ab440 6652}
5d06a99f 6653
baf63293 6654static void rtl_remove_one(struct pci_dev *pdev)
e27566ed
FR		 6655{
6656 struct net_device *dev = pci_get_drvdata(pdev);
6657 struct rtl8169_private *tp = netdev_priv(dev);
6658
6659 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
6660 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
6661 tp->mac_version == RTL_GIGA_MAC_VER_31) {
6662 rtl8168_driver_stop(tp);
6663 }
6664
6665 cancel_work_sync(&tp->wk.work);
6666
ad1be8d3
DN		 6667 netif_napi_del(&tp->napi);
6668
e27566ed
FR		 6669 unregister_netdev(dev);
6670
6671 rtl_release_firmware(tp);
6672
6673 if (pci_dev_run_wake(pdev))
6674 pm_runtime_get_noresume(&pdev->dev);
6675
6676 /* restore original MAC address */
6677 rtl_rar_set(tp, dev->perm_addr);
6678
6679 rtl_disable_msi(pdev, tp);
6680 rtl8169_release_board(pdev, dev, tp->mmio_addr);
6681 pci_set_drvdata(pdev, NULL);
6682}
6683
fa9c385e 6684static const struct net_device_ops rtl_netdev_ops = {
df43ac78 6685 .ndo_open = rtl_open,
fa9c385e
FR		 6686 .ndo_stop = rtl8169_close,
6687 .ndo_get_stats64 = rtl8169_get_stats64,
6688 .ndo_start_xmit = rtl8169_start_xmit,
6689 .ndo_tx_timeout = rtl8169_tx_timeout,
6690 .ndo_validate_addr = eth_validate_addr,
6691 .ndo_change_mtu = rtl8169_change_mtu,
6692 .ndo_fix_features = rtl8169_fix_features,
6693 .ndo_set_features = rtl8169_set_features,
6694 .ndo_set_mac_address = rtl_set_mac_address,
6695 .ndo_do_ioctl = rtl8169_ioctl,
6696 .ndo_set_rx_mode = rtl_set_rx_mode,
6697#ifdef CONFIG_NET_POLL_CONTROLLER
6698 .ndo_poll_controller = rtl8169_netpoll,
6699#endif
6700
6701};
6702
31fa8b18
FR		 6703static const struct rtl_cfg_info {
6704 void (*hw_start)(struct net_device *);
6705 unsigned int region;
6706 unsigned int align;
6707 u16 event_slow;
6708 unsigned features;
6709 u8 default_ver;
6710} rtl_cfg_infos [] = {
6711 [RTL_CFG_0] = {
6712 .hw_start = rtl_hw_start_8169,
6713 .region = 1,
6714 .align = 0,
6715 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
6716 .features = RTL_FEATURE_GMII,
6717 .default_ver = RTL_GIGA_MAC_VER_01,
6718 },
6719 [RTL_CFG_1] = {
6720 .hw_start = rtl_hw_start_8168,
6721 .region = 2,
6722 .align = 8,
6723 .event_slow = SYSErr | LinkChg | RxOverflow,
6724 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
6725 .default_ver = RTL_GIGA_MAC_VER_11,
6726 },
6727 [RTL_CFG_2] = {
6728 .hw_start = rtl_hw_start_8101,
6729 .region = 2,
6730 .align = 8,
6731 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
6732 PCSTimeout,
6733 .features = RTL_FEATURE_MSI,
6734 .default_ver = RTL_GIGA_MAC_VER_13,
6735 }
6736};
6737
6738/* Cfg9346_Unlock assumed. */
6739static unsigned rtl_try_msi(struct rtl8169_private *tp,
6740 const struct rtl_cfg_info *cfg)
6741{
6742 void __iomem *ioaddr = tp->mmio_addr;
6743 unsigned msi = 0;
6744 u8 cfg2;
6745
6746 cfg2 = RTL_R8(Config2) & ~MSIEnable;
6747 if (cfg->features & RTL_FEATURE_MSI) {
6748 if (pci_enable_msi(tp->pci_dev)) {
6749 netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
6750 } else {
6751 cfg2 |= MSIEnable;
6752 msi = RTL_FEATURE_MSI;
6753 }
6754 }
6755 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
6756 RTL_W8(Config2, cfg2);
6757 return msi;
6758}
6759
c558386b
HW		 6760DECLARE_RTL_COND(rtl_link_list_ready_cond)
6761{
6762 void __iomem *ioaddr = tp->mmio_addr;
6763
6764 return RTL_R8(MCU) & LINK_LIST_RDY;
6765}
6766
6767DECLARE_RTL_COND(rtl_rxtx_empty_cond)
6768{
6769 void __iomem *ioaddr = tp->mmio_addr;
6770
6771 return (RTL_R8(MCU) & RXTX_EMPTY) == RXTX_EMPTY;
6772}
6773
baf63293 6774static void rtl_hw_init_8168g(struct rtl8169_private *tp)
c558386b
HW		 6775{
6776 void __iomem *ioaddr = tp->mmio_addr;
6777 u32 data;
6778
6779 tp->ocp_base = OCP_STD_PHY_BASE;
6780
6781 RTL_W32(MISC, RTL_R32(MISC) | RXDV_GATED_EN);
6782
6783 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
6784 return;
6785
6786 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
6787 return;
6788
6789 RTL_W8(ChipCmd, RTL_R8(ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
6790 msleep(1);
6791 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
6792
5f8bcce9 6793 data = r8168_mac_ocp_read(tp, 0xe8de);
c558386b
HW		 6794 data &= ~(1 << 14);
6795 r8168_mac_ocp_write(tp, 0xe8de, data);
6796
6797 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6798 return;
6799
5f8bcce9 6800 data = r8168_mac_ocp_read(tp, 0xe8de);
c558386b
HW		 6801 data |= (1 << 15);
6802 r8168_mac_ocp_write(tp, 0xe8de, data);
6803
6804 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6805 return;
6806}
6807
baf63293 6808static void rtl_hw_initialize(struct rtl8169_private *tp)
c558386b
HW		 6809{
6810 switch (tp->mac_version) {
6811 case RTL_GIGA_MAC_VER_40:
6812 case RTL_GIGA_MAC_VER_41:
57538c4a 6813 case RTL_GIGA_MAC_VER_42:
c558386b
HW		 6814 rtl_hw_init_8168g(tp);
6815 break;
6816
6817 default:
6818 break;
6819 }
6820}
6821
baf63293 6822static int
3b6cf25d
FR		 6823rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6824{
6825 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
6826 const unsigned int region = cfg->region;
6827 struct rtl8169_private *tp;
6828 struct mii_if_info *mii;
6829 struct net_device *dev;
6830 void __iomem *ioaddr;
6831 int chipset, i;
6832 int rc;
6833
6834 if (netif_msg_drv(&debug)) {
6835 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
6836 MODULENAME, RTL8169_VERSION);
6837 }
6838
6839 dev = alloc_etherdev(sizeof (*tp));
6840 if (!dev) {
6841 rc = -ENOMEM;
6842 goto out;
6843 }
6844
6845 SET_NETDEV_DEV(dev, &pdev->dev);
fa9c385e 6846 dev->netdev_ops = &rtl_netdev_ops;
3b6cf25d
FR		 6847 tp = netdev_priv(dev);
6848 tp->dev = dev;
6849 tp->pci_dev = pdev;
6850 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
6851
6852 mii = &tp->mii;
6853 mii->dev = dev;
6854 mii->mdio_read = rtl_mdio_read;
6855 mii->mdio_write = rtl_mdio_write;
6856 mii->phy_id_mask = 0x1f;
6857 mii->reg_num_mask = 0x1f;
6858 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
6859
6860 /* disable ASPM completely as that cause random device stop working
6861 * problems as well as full system hangs for some PCIe devices users */
6862 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
6863 PCIE_LINK_STATE_CLKPM);
6864
6865 /* enable device (incl. PCI PM wakeup and hotplug setup) */
6866 rc = pci_enable_device(pdev);
6867 if (rc < 0) {
6868 netif_err(tp, probe, dev, "enable failure\n");
6869 goto err_out_free_dev_1;
6870 }
6871
6872 if (pci_set_mwi(pdev) < 0)
6873 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
6874
6875 /* make sure PCI base addr 1 is MMIO */
6876 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
6877 netif_err(tp, probe, dev,
6878 "region #%d not an MMIO resource, aborting\n",
6879 region);
6880 rc = -ENODEV;
6881 goto err_out_mwi_2;
6882 }
6883
6884 /* check for weird/broken PCI region reporting */
6885 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
6886 netif_err(tp, probe, dev,
6887 "Invalid PCI region size(s), aborting\n");
6888 rc = -ENODEV;
6889 goto err_out_mwi_2;
6890 }
6891
6892 rc = pci_request_regions(pdev, MODULENAME);
6893 if (rc < 0) {
6894 netif_err(tp, probe, dev, "could not request regions\n");
6895 goto err_out_mwi_2;
6896 }
6897
6898 tp->cp_cmd = RxChkSum;
6899
6900 if ((sizeof(dma_addr_t) > 4) &&
6901 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
6902 tp->cp_cmd |= PCIDAC;
6903 dev->features |= NETIF_F_HIGHDMA;
6904 } else {
6905 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6906 if (rc < 0) {
6907 netif_err(tp, probe, dev, "DMA configuration failed\n");
6908 goto err_out_free_res_3;
6909 }
6910 }
6911
6912 /* ioremap MMIO region */
6913 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
6914 if (!ioaddr) {
6915 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
6916 rc = -EIO;
6917 goto err_out_free_res_3;
6918 }
6919 tp->mmio_addr = ioaddr;
6920
6921 if (!pci_is_pcie(pdev))
6922 netif_info(tp, probe, dev, "not PCI Express\n");
6923
6924 /* Identify chip attached to board */
6925 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
6926
6927 rtl_init_rxcfg(tp);
6928
6929 rtl_irq_disable(tp);
6930
c558386b
HW		 6931 rtl_hw_initialize(tp);
6932
3b6cf25d
FR		 6933 rtl_hw_reset(tp);
6934
6935 rtl_ack_events(tp, 0xffff);
6936
6937 pci_set_master(pdev);
6938
6939 /*
6940 * Pretend we are using VLANs; This bypasses a nasty bug where
6941 * Interrupts stop flowing on high load on 8110SCd controllers.
6942 */
6943 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6944 tp->cp_cmd |= RxVlan;
6945
6946 rtl_init_mdio_ops(tp);
6947 rtl_init_pll_power_ops(tp);
6948 rtl_init_jumbo_ops(tp);
beb1fe18 6949 rtl_init_csi_ops(tp);
3b6cf25d
FR		 6950
6951 rtl8169_print_mac_version(tp);
6952
6953 chipset = tp->mac_version;
6954 tp->txd_version = rtl_chip_infos[chipset].txd_version;
6955
6956 RTL_W8(Cfg9346, Cfg9346_Unlock);
6957 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
6958 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
6959 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
6960 tp->features |= RTL_FEATURE_WOL;
6961 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
6962 tp->features |= RTL_FEATURE_WOL;
6963 tp->features |= rtl_try_msi(tp, cfg);
6964 RTL_W8(Cfg9346, Cfg9346_Lock);
6965
6966 if (rtl_tbi_enabled(tp)) {
6967 tp->set_speed = rtl8169_set_speed_tbi;
6968 tp->get_settings = rtl8169_gset_tbi;
6969 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
6970 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
6971 tp->link_ok = rtl8169_tbi_link_ok;
6972 tp->do_ioctl = rtl_tbi_ioctl;
6973 } else {
6974 tp->set_speed = rtl8169_set_speed_xmii;
6975 tp->get_settings = rtl8169_gset_xmii;
6976 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
6977 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
6978 tp->link_ok = rtl8169_xmii_link_ok;
6979 tp->do_ioctl = rtl_xmii_ioctl;
6980 }
6981
6982 mutex_init(&tp->wk.mutex);
6983
6984 /* Get MAC address */
6985 for (i = 0; i < ETH_ALEN; i++)
6986 dev->dev_addr[i] = RTL_R8(MAC0 + i);
3b6cf25d
FR		 6987
6988 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
6989 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3b6cf25d
FR		 6990
6991 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
6992
6993 /* don't enable SG, IP_CSUM and TSO by default - it might not work
6994 * properly for all devices */
6995 dev->features |= NETIF_F_RXCSUM |
6996 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6997
6998 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6999 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
7000 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7001 NETIF_F_HIGHDMA;
7002
7003 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
7004 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
7005 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
7006
7007 dev->hw_features |= NETIF_F_RXALL;
7008 dev->hw_features |= NETIF_F_RXFCS;
7009
7010 tp->hw_start = cfg->hw_start;
7011 tp->event_slow = cfg->event_slow;
7012
7013 tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
7014 ~(RxBOVF | RxFOVF) : ~0;
7015
7016 init_timer(&tp->timer);
7017 tp->timer.data = (unsigned long) dev;
7018 tp->timer.function = rtl8169_phy_timer;
7019
7020 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
7021
7022 rc = register_netdev(dev);
7023 if (rc < 0)
7024 goto err_out_msi_4;
7025
7026 pci_set_drvdata(pdev, dev);
7027
92a7c4e7
FR		 7028 netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
7029 rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
7030 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
3b6cf25d
FR		 7031 if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
7032 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
7033 "tx checksumming: %s]\n",
7034 rtl_chip_infos[chipset].jumbo_max,
7035 rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
7036 }
7037
7038 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
7039 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
7040 tp->mac_version == RTL_GIGA_MAC_VER_31) {
7041 rtl8168_driver_start(tp);
7042 }
7043
7044 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
7045
7046 if (pci_dev_run_wake(pdev))
7047 pm_runtime_put_noidle(&pdev->dev);
7048
7049 netif_carrier_off(dev);
7050
7051out:
7052 return rc;
7053
7054err_out_msi_4:
ad1be8d3 7055 netif_napi_del(&tp->napi);
3b6cf25d
FR		 7056 rtl_disable_msi(pdev, tp);
7057 iounmap(ioaddr);
7058err_out_free_res_3:
7059 pci_release_regions(pdev);
7060err_out_mwi_2:
7061 pci_clear_mwi(pdev);
7062 pci_disable_device(pdev);
7063err_out_free_dev_1:
7064 free_netdev(dev);
7065 goto out;
7066}
7067
1da177e4
LT		 7068static struct pci_driver rtl8169_pci_driver = {
7069 .name = MODULENAME,
7070 .id_table = rtl8169_pci_tbl,
3b6cf25d 7071 .probe = rtl_init_one,
baf63293 7072 .remove = rtl_remove_one,
1765f95d 7073 .shutdown = rtl_shutdown,
861ab440 7074 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 7075};
7076
3eeb7da9 7077module_pci_driver(rtl8169_pci_driver);
Ubuntu Focal Linux kernel mirror