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sunvnet: fix potential NULL pointer dereference
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / realtek / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
a6b7a407 24#include <linux/interrupt.h>
1da177e4 25#include <linux/dma-mapping.h>
e1759441 26#include <linux/pm_runtime.h>
bca03d5f 27#include <linux/firmware.h>
ba04c7c9 28#include <linux/pci-aspm.h>
70c71606 29#include <linux/prefetch.h>
e974604b 30#include <linux/ipv6.h>
31#include <net/ip6_checksum.h>
1da177e4
LT		 32
33#include <asm/io.h>
34#include <asm/irq.h>
35
865c652d 36#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 37#define MODULENAME "r8169"
38#define PFX MODULENAME ": "
39
bca03d5f 40#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
41#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
01dc7fec 42#define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
43#define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
70090424 44#define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
c2218925
HW		 45#define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
46#define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
5a5e4443 47#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
7e18dca1 48#define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
b3d7b2f2 49#define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
45dd95c4 50#define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
5598bfe5 51#define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
58152cd4 52#define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
beb330a4 53#define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
57538c4a 54#define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
6e1d0b89
CHL		 55#define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw"
56#define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
57#define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw"
58#define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
bca03d5f 59
1da177e4
LT		 60#ifdef RTL8169_DEBUG
61#define assert(expr) \
5b0384f4
FR		 62 if (!(expr)) { \
63 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
b39d66a8 64 #expr,__FILE__,__func__,__LINE__); \
5b0384f4 65 }
06fa7358
JP		 66#define dprintk(fmt, args...) \
67 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 68#else
69#define assert(expr) do {} while (0)
70#define dprintk(fmt, args...) do {} while (0)
71#endif /* RTL8169_DEBUG */
72
b57b7e5a 73#define R8169_MSG_DEFAULT \
f0e837d9 74 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 75
477206a0
JD		 76#define TX_SLOTS_AVAIL(tp) \
77 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
78
79/* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
80#define TX_FRAGS_READY_FOR(tp,nr_frags) \
81 (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
1da177e4 82
1da177e4
LT		 83/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
84 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 85static const int multicast_filter_limit = 32;
1da177e4 86
9c14ceaf 87#define MAX_READ_REQUEST_SHIFT 12
aee77e4a 88#define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
1da177e4
LT		 89#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
90
91#define R8169_REGS_SIZE 256
92#define R8169_NAPI_WEIGHT 64
93#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
9fba0812 94#define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
1da177e4
LT		 95#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
96#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
97
98#define RTL8169_TX_TIMEOUT (6*HZ)
99#define RTL8169_PHY_TIMEOUT (10*HZ)
100
101/* write/read MMIO register */
102#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
103#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
104#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
105#define RTL_R8(reg) readb (ioaddr + (reg))
106#define RTL_R16(reg) readw (ioaddr + (reg))
06f555f3 107#define RTL_R32(reg) readl (ioaddr + (reg))
1da177e4
LT		 108
109enum mac_version {
85bffe6c
FR		 110 RTL_GIGA_MAC_VER_01 = 0,
111 RTL_GIGA_MAC_VER_02,
112 RTL_GIGA_MAC_VER_03,
113 RTL_GIGA_MAC_VER_04,
114 RTL_GIGA_MAC_VER_05,
115 RTL_GIGA_MAC_VER_06,
116 RTL_GIGA_MAC_VER_07,
117 RTL_GIGA_MAC_VER_08,
118 RTL_GIGA_MAC_VER_09,
119 RTL_GIGA_MAC_VER_10,
120 RTL_GIGA_MAC_VER_11,
121 RTL_GIGA_MAC_VER_12,
122 RTL_GIGA_MAC_VER_13,
123 RTL_GIGA_MAC_VER_14,
124 RTL_GIGA_MAC_VER_15,
125 RTL_GIGA_MAC_VER_16,
126 RTL_GIGA_MAC_VER_17,
127 RTL_GIGA_MAC_VER_18,
128 RTL_GIGA_MAC_VER_19,
129 RTL_GIGA_MAC_VER_20,
130 RTL_GIGA_MAC_VER_21,
131 RTL_GIGA_MAC_VER_22,
132 RTL_GIGA_MAC_VER_23,
133 RTL_GIGA_MAC_VER_24,
134 RTL_GIGA_MAC_VER_25,
135 RTL_GIGA_MAC_VER_26,
136 RTL_GIGA_MAC_VER_27,
137 RTL_GIGA_MAC_VER_28,
138 RTL_GIGA_MAC_VER_29,
139 RTL_GIGA_MAC_VER_30,
140 RTL_GIGA_MAC_VER_31,
141 RTL_GIGA_MAC_VER_32,
142 RTL_GIGA_MAC_VER_33,
70090424 143 RTL_GIGA_MAC_VER_34,
c2218925
HW		 144 RTL_GIGA_MAC_VER_35,
145 RTL_GIGA_MAC_VER_36,
7e18dca1 146 RTL_GIGA_MAC_VER_37,
b3d7b2f2 147 RTL_GIGA_MAC_VER_38,
5598bfe5 148 RTL_GIGA_MAC_VER_39,
c558386b
HW		 149 RTL_GIGA_MAC_VER_40,
150 RTL_GIGA_MAC_VER_41,
57538c4a 151 RTL_GIGA_MAC_VER_42,
58152cd4 152 RTL_GIGA_MAC_VER_43,
45dd95c4 153 RTL_GIGA_MAC_VER_44,
6e1d0b89
CHL		 154 RTL_GIGA_MAC_VER_45,
155 RTL_GIGA_MAC_VER_46,
156 RTL_GIGA_MAC_VER_47,
157 RTL_GIGA_MAC_VER_48,
85bffe6c 158 RTL_GIGA_MAC_NONE = 0xff,
1da177e4
LT		 159};
160
2b7b4318
FR		 161enum rtl_tx_desc_version {
162 RTL_TD_0 = 0,
163 RTL_TD_1 = 1,
164};
165
d58d46b5
FR		 166#define JUMBO_1K ETH_DATA_LEN
167#define JUMBO_4K (4*1024 - ETH_HLEN - 2)
168#define JUMBO_6K (6*1024 - ETH_HLEN - 2)
169#define JUMBO_7K (7*1024 - ETH_HLEN - 2)
170#define JUMBO_9K (9*1024 - ETH_HLEN - 2)
171
172#define _R(NAME,TD,FW,SZ,B) { \
173 .name = NAME, \
174 .txd_version = TD, \
175 .fw_name = FW, \
176 .jumbo_max = SZ, \
177 .jumbo_tx_csum = B \
178}
1da177e4 179
3c6bee1d 180static const struct {
1da177e4 181 const char *name;
2b7b4318 182 enum rtl_tx_desc_version txd_version;
953a12cc 183 const char *fw_name;
d58d46b5
FR		 184 u16 jumbo_max;
185 bool jumbo_tx_csum;
85bffe6c
FR		 186} rtl_chip_infos[] = {
187 /* PCI devices. */
188 [RTL_GIGA_MAC_VER_01] =
d58d46b5 189 _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 190 [RTL_GIGA_MAC_VER_02] =
d58d46b5 191 _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 192 [RTL_GIGA_MAC_VER_03] =
d58d46b5 193 _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 194 [RTL_GIGA_MAC_VER_04] =
d58d46b5 195 _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 196 [RTL_GIGA_MAC_VER_05] =
d58d46b5 197 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 198 [RTL_GIGA_MAC_VER_06] =
d58d46b5 199 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c
FR		 200 /* PCI-E devices. */
201 [RTL_GIGA_MAC_VER_07] =
d58d46b5 202 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 203 [RTL_GIGA_MAC_VER_08] =
d58d46b5 204 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 205 [RTL_GIGA_MAC_VER_09] =
d58d46b5 206 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 207 [RTL_GIGA_MAC_VER_10] =
d58d46b5 208 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 209 [RTL_GIGA_MAC_VER_11] =
d58d46b5 210 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
85bffe6c 211 [RTL_GIGA_MAC_VER_12] =
d58d46b5 212 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
85bffe6c 213 [RTL_GIGA_MAC_VER_13] =
d58d46b5 214 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 215 [RTL_GIGA_MAC_VER_14] =
d58d46b5 216 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 217 [RTL_GIGA_MAC_VER_15] =
d58d46b5 218 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 219 [RTL_GIGA_MAC_VER_16] =
d58d46b5 220 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 221 [RTL_GIGA_MAC_VER_17] =
f75761b6 222 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
85bffe6c 223 [RTL_GIGA_MAC_VER_18] =
d58d46b5 224 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 225 [RTL_GIGA_MAC_VER_19] =
d58d46b5 226 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 227 [RTL_GIGA_MAC_VER_20] =
d58d46b5 228 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 229 [RTL_GIGA_MAC_VER_21] =
d58d46b5 230 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 231 [RTL_GIGA_MAC_VER_22] =
d58d46b5 232 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 233 [RTL_GIGA_MAC_VER_23] =
d58d46b5 234 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 235 [RTL_GIGA_MAC_VER_24] =
d58d46b5 236 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 237 [RTL_GIGA_MAC_VER_25] =
d58d46b5
FR		 238 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1,
239 JUMBO_9K, false),
85bffe6c 240 [RTL_GIGA_MAC_VER_26] =
d58d46b5
FR		 241 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2,
242 JUMBO_9K, false),
85bffe6c 243 [RTL_GIGA_MAC_VER_27] =
d58d46b5 244 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 245 [RTL_GIGA_MAC_VER_28] =
d58d46b5 246 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 247 [RTL_GIGA_MAC_VER_29] =
d58d46b5
FR		 248 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
249 JUMBO_1K, true),
85bffe6c 250 [RTL_GIGA_MAC_VER_30] =
d58d46b5
FR		 251 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
252 JUMBO_1K, true),
85bffe6c 253 [RTL_GIGA_MAC_VER_31] =
d58d46b5 254 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 255 [RTL_GIGA_MAC_VER_32] =
d58d46b5
FR		 256 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1,
257 JUMBO_9K, false),
85bffe6c 258 [RTL_GIGA_MAC_VER_33] =
d58d46b5
FR		 259 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2,
260 JUMBO_9K, false),
70090424 261 [RTL_GIGA_MAC_VER_34] =
d58d46b5
FR		 262 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
263 JUMBO_9K, false),
c2218925 264 [RTL_GIGA_MAC_VER_35] =
d58d46b5
FR		 265 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1,
266 JUMBO_9K, false),
c2218925 267 [RTL_GIGA_MAC_VER_36] =
d58d46b5
FR		 268 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2,
269 JUMBO_9K, false),
7e18dca1
HW		 270 [RTL_GIGA_MAC_VER_37] =
271 _R("RTL8402", RTL_TD_1, FIRMWARE_8402_1,
272 JUMBO_1K, true),
b3d7b2f2
HW		 273 [RTL_GIGA_MAC_VER_38] =
274 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_1,
275 JUMBO_9K, false),
5598bfe5
HW		 276 [RTL_GIGA_MAC_VER_39] =
277 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_1,
278 JUMBO_1K, true),
c558386b 279 [RTL_GIGA_MAC_VER_40] =
beb330a4 280 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_2,
c558386b
HW		 281 JUMBO_9K, false),
282 [RTL_GIGA_MAC_VER_41] =
283 _R("RTL8168g/8111g", RTL_TD_1, NULL, JUMBO_9K, false),
57538c4a 284 [RTL_GIGA_MAC_VER_42] =
285 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_3,
286 JUMBO_9K, false),
58152cd4 287 [RTL_GIGA_MAC_VER_43] =
288 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_2,
289 JUMBO_1K, true),
45dd95c4 290 [RTL_GIGA_MAC_VER_44] =
291 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_2,
292 JUMBO_9K, false),
6e1d0b89
CHL		 293 [RTL_GIGA_MAC_VER_45] =
294 _R("RTL8168h/8111h", RTL_TD_1, FIRMWARE_8168H_1,
295 JUMBO_9K, false),
296 [RTL_GIGA_MAC_VER_46] =
297 _R("RTL8168h/8111h", RTL_TD_1, FIRMWARE_8168H_2,
298 JUMBO_9K, false),
299 [RTL_GIGA_MAC_VER_47] =
300 _R("RTL8107e", RTL_TD_1, FIRMWARE_8107E_1,
301 JUMBO_1K, false),
302 [RTL_GIGA_MAC_VER_48] =
303 _R("RTL8107e", RTL_TD_1, FIRMWARE_8107E_2,
304 JUMBO_1K, false),
953a12cc 305};
85bffe6c 306#undef _R
953a12cc 307
bcf0bf90
FR		 308enum cfg_version {
309 RTL_CFG_0 = 0x00,
310 RTL_CFG_1,
311 RTL_CFG_2
312};
313
9baa3c34 314static const struct pci_device_id rtl8169_pci_tbl[] = {
bcf0bf90 315 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 316 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 317 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 318 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90 319 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
2a35cfa5
FR		 320 { PCI_VENDOR_ID_DLINK, 0x4300,
321 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
bcf0bf90 322 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
93a3aa25 323 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
bc1660b5 324 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 325 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
326 { PCI_VENDOR_ID_LINKSYS, 0x1032,
327 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 328 { 0x0001, 0x8168,
329 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 330 {0,},
331};
332
333MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
334
6f0333b8 335static int rx_buf_sz = 16383;
4300e8c7 336static int use_dac;
b57b7e5a
SH		 337static struct {
338 u32 msg_enable;
339} debug = { -1 };
1da177e4 340
07d3f51f
FR		 341enum rtl_registers {
342 MAC0 = 0, /* Ethernet hardware address. */
773d2021 343 MAC4 = 4,
07d3f51f
FR		 344 MAR0 = 8, /* Multicast filter. */
345 CounterAddrLow = 0x10,
346 CounterAddrHigh = 0x14,
347 TxDescStartAddrLow = 0x20,
348 TxDescStartAddrHigh = 0x24,
349 TxHDescStartAddrLow = 0x28,
350 TxHDescStartAddrHigh = 0x2c,
351 FLASH = 0x30,
352 ERSR = 0x36,
353 ChipCmd = 0x37,
354 TxPoll = 0x38,
355 IntrMask = 0x3c,
356 IntrStatus = 0x3e,
4f6b00e5 357
07d3f51f 358 TxConfig = 0x40,
4f6b00e5
HW		 359#define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
360#define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
2b7b4318 361
4f6b00e5
HW		 362 RxConfig = 0x44,
363#define RX128_INT_EN (1 << 15) /* 8111c and later */
364#define RX_MULTI_EN (1 << 14) /* 8111c only */
365#define RXCFG_FIFO_SHIFT 13
366 /* No threshold before first PCI xfer */
367#define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
beb330a4 368#define RX_EARLY_OFF (1 << 11)
4f6b00e5
HW		 369#define RXCFG_DMA_SHIFT 8
370 /* Unlimited maximum PCI burst. */
371#define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
2b7b4318 372
07d3f51f
FR		 373 RxMissed = 0x4c,
374 Cfg9346 = 0x50,
375 Config0 = 0x51,
376 Config1 = 0x52,
377 Config2 = 0x53,
d387b427
FR		 378#define PME_SIGNAL (1 << 5) /* 8168c and later */
379
07d3f51f
FR		 380 Config3 = 0x54,
381 Config4 = 0x55,
382 Config5 = 0x56,
383 MultiIntr = 0x5c,
384 PHYAR = 0x60,
07d3f51f
FR		 385 PHYstatus = 0x6c,
386 RxMaxSize = 0xda,
387 CPlusCmd = 0xe0,
388 IntrMitigate = 0xe2,
389 RxDescAddrLow = 0xe4,
390 RxDescAddrHigh = 0xe8,
f0298f81 391 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
392
393#define NoEarlyTx 0x3f /* Max value : no early transmit. */
394
395 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
396
397#define TxPacketMax (8064 >> 7)
3090bd9a 398#define EarlySize 0x27
f0298f81 399
07d3f51f
FR		 400 FuncEvent = 0xf0,
401 FuncEventMask = 0xf4,
402 FuncPresetState = 0xf8,
403 FuncForceEvent = 0xfc,
1da177e4
LT		 404};
405
f162a5d1
FR		 406enum rtl8110_registers {
407 TBICSR = 0x64,
408 TBI_ANAR = 0x68,
409 TBI_LPAR = 0x6a,
410};
411
412enum rtl8168_8101_registers {
413 CSIDR = 0x64,
414 CSIAR = 0x68,
415#define CSIAR_FLAG 0x80000000
416#define CSIAR_WRITE_CMD 0x80000000
417#define CSIAR_BYTE_ENABLE 0x0f
418#define CSIAR_BYTE_ENABLE_SHIFT 12
419#define CSIAR_ADDR_MASK 0x0fff
7e18dca1
HW		 420#define CSIAR_FUNC_CARD 0x00000000
421#define CSIAR_FUNC_SDIO 0x00010000
422#define CSIAR_FUNC_NIC 0x00020000
45dd95c4 423#define CSIAR_FUNC_NIC2 0x00010000
065c27c1 424 PMCH = 0x6f,
f162a5d1
FR		 425 EPHYAR = 0x80,
426#define EPHYAR_FLAG 0x80000000
427#define EPHYAR_WRITE_CMD 0x80000000
428#define EPHYAR_REG_MASK 0x1f
429#define EPHYAR_REG_SHIFT 16
430#define EPHYAR_DATA_MASK 0xffff
5a5e4443 431 DLLPR = 0xd0,
4f6b00e5 432#define PFM_EN (1 << 6)
6e1d0b89 433#define TX_10M_PS_EN (1 << 7)
f162a5d1
FR		 434 DBG_REG = 0xd1,
435#define FIX_NAK_1 (1 << 4)
436#define FIX_NAK_2 (1 << 3)
5a5e4443
HW		 437 TWSI = 0xd2,
438 MCU = 0xd3,
4f6b00e5 439#define NOW_IS_OOB (1 << 7)
c558386b
HW		 440#define TX_EMPTY (1 << 5)
441#define RX_EMPTY (1 << 4)
442#define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
5a5e4443
HW		 443#define EN_NDP (1 << 3)
444#define EN_OOB_RESET (1 << 2)
c558386b 445#define LINK_LIST_RDY (1 << 1)
daf9df6d 446 EFUSEAR = 0xdc,
447#define EFUSEAR_FLAG 0x80000000
448#define EFUSEAR_WRITE_CMD 0x80000000
449#define EFUSEAR_READ_CMD 0x00000000
450#define EFUSEAR_REG_MASK 0x03ff
451#define EFUSEAR_REG_SHIFT 8
452#define EFUSEAR_DATA_MASK 0xff
6e1d0b89
CHL		 453 MISC_1 = 0xf2,
454#define PFM_D3COLD_EN (1 << 6)
f162a5d1
FR		 455};
456
c0e45c1c 457enum rtl8168_registers {
4f6b00e5
HW		 458 LED_FREQ = 0x1a,
459 EEE_LED = 0x1b,
b646d900 460 ERIDR = 0x70,
461 ERIAR = 0x74,
462#define ERIAR_FLAG 0x80000000
463#define ERIAR_WRITE_CMD 0x80000000
464#define ERIAR_READ_CMD 0x00000000
465#define ERIAR_ADDR_BYTE_ALIGN 4
b646d900 466#define ERIAR_TYPE_SHIFT 16
4f6b00e5
HW		 467#define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
468#define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
469#define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
470#define ERIAR_MASK_SHIFT 12
471#define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
472#define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
6e1d0b89 473#define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
c558386b 474#define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
4f6b00e5 475#define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
c0e45c1c 476 EPHY_RXER_NUM = 0x7c,
477 OCPDR = 0xb0, /* OCP GPHY access */
478#define OCPDR_WRITE_CMD 0x80000000
479#define OCPDR_READ_CMD 0x00000000
480#define OCPDR_REG_MASK 0x7f
481#define OCPDR_GPHY_REG_SHIFT 16
482#define OCPDR_DATA_MASK 0xffff
483 OCPAR = 0xb4,
484#define OCPAR_FLAG 0x80000000
485#define OCPAR_GPHY_WRITE_CMD 0x8000f060
486#define OCPAR_GPHY_READ_CMD 0x0000f060
c558386b 487 GPHY_OCP = 0xb8,
01dc7fec 488 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
489 MISC = 0xf0, /* 8168e only. */
cecb5fd7 490#define TXPLA_RST (1 << 29)
5598bfe5 491#define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
4f6b00e5 492#define PWM_EN (1 << 22)
c558386b 493#define RXDV_GATED_EN (1 << 19)
5598bfe5 494#define EARLY_TALLY_EN (1 << 16)
c0e45c1c 495};
496
07d3f51f 497enum rtl_register_content {
1da177e4 498 /* InterruptStatusBits */
07d3f51f
FR		 499 SYSErr = 0x8000,
500 PCSTimeout = 0x4000,
501 SWInt = 0x0100,
502 TxDescUnavail = 0x0080,
503 RxFIFOOver = 0x0040,
504 LinkChg = 0x0020,
505 RxOverflow = 0x0010,
506 TxErr = 0x0008,
507 TxOK = 0x0004,
508 RxErr = 0x0002,
509 RxOK = 0x0001,
1da177e4
LT		 510
511 /* RxStatusDesc */
e03f33af 512 RxBOVF = (1 << 24),
9dccf611
FR		 513 RxFOVF = (1 << 23),
514 RxRWT = (1 << 22),
515 RxRES = (1 << 21),
516 RxRUNT = (1 << 20),
517 RxCRC = (1 << 19),
1da177e4
LT		 518
519 /* ChipCmdBits */
4f6b00e5 520 StopReq = 0x80,
07d3f51f
FR		 521 CmdReset = 0x10,
522 CmdRxEnb = 0x08,
523 CmdTxEnb = 0x04,
524 RxBufEmpty = 0x01,
1da177e4 525
275391a4
FR		 526 /* TXPoll register p.5 */
527 HPQ = 0x80, /* Poll cmd on the high prio queue */
528 NPQ = 0x40, /* Poll cmd on the low prio queue */
529 FSWInt = 0x01, /* Forced software interrupt */
530
1da177e4 531 /* Cfg9346Bits */
07d3f51f
FR		 532 Cfg9346_Lock = 0x00,
533 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 534
535 /* rx_mode_bits */
07d3f51f
FR		 536 AcceptErr = 0x20,
537 AcceptRunt = 0x10,
538 AcceptBroadcast = 0x08,
539 AcceptMulticast = 0x04,
540 AcceptMyPhys = 0x02,
541 AcceptAllPhys = 0x01,
1687b566 542#define RX_CONFIG_ACCEPT_MASK 0x3f
1da177e4 543
1da177e4
LT		 544 /* TxConfigBits */
545 TxInterFrameGapShift = 24,
546 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
547
5d06a99f 548 /* Config1 register p.24 */
f162a5d1
FR		 549 LEDS1 = (1 << 7),
550 LEDS0 = (1 << 6),
f162a5d1
FR		 551 Speed_down = (1 << 4),
552 MEMMAP = (1 << 3),
553 IOMAP = (1 << 2),
554 VPD = (1 << 1),
5d06a99f
FR		 555 PMEnable = (1 << 0), /* Power Management Enable */
556
6dccd16b 557 /* Config2 register p. 25 */
57538c4a 558 ClkReqEn = (1 << 7), /* Clock Request Enable */
2ca6cf06 559 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
6dccd16b
FR		 560 PCI_Clock_66MHz = 0x01,
561 PCI_Clock_33MHz = 0x00,
562
61a4dcc2
FR		 563 /* Config3 register p.25 */
564 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
565 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
d58d46b5 566 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
b51ecea8 567 Rdy_to_L23 = (1 << 1), /* L23 Enable */
f162a5d1 568 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 569
d58d46b5
FR		 570 /* Config4 register */
571 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
572
5d06a99f 573 /* Config5 register p.27 */
61a4dcc2
FR		 574 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
575 MWF = (1 << 5), /* Accept Multicast wakeup frame */
576 UWF = (1 << 4), /* Accept Unicast wakeup frame */
cecb5fd7 577 Spi_en = (1 << 3),
61a4dcc2 578 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f 579 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
57538c4a 580 ASPM_en = (1 << 0), /* ASPM enable */
5d06a99f 581
1da177e4
LT		 582 /* TBICSR p.28 */
583 TBIReset = 0x80000000,
584 TBILoopback = 0x40000000,
585 TBINwEnable = 0x20000000,
586 TBINwRestart = 0x10000000,
587 TBILinkOk = 0x02000000,
588 TBINwComplete = 0x01000000,
589
590 /* CPlusCmd p.31 */
f162a5d1
FR		 591 EnableBist = (1 << 15), // 8168 8101
592 Mac_dbgo_oe = (1 << 14), // 8168 8101
593 Normal_mode = (1 << 13), // unused
594 Force_half_dup = (1 << 12), // 8168 8101
595 Force_rxflow_en = (1 << 11), // 8168 8101
596 Force_txflow_en = (1 << 10), // 8168 8101
597 Cxpl_dbg_sel = (1 << 9), // 8168 8101
598 ASF = (1 << 8), // 8168 8101
599 PktCntrDisable = (1 << 7), // 8168 8101
600 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 601 RxVlan = (1 << 6),
602 RxChkSum = (1 << 5),
603 PCIDAC = (1 << 4),
604 PCIMulRW = (1 << 3),
0e485150
FR		 605 INTT_0 = 0x0000, // 8168
606 INTT_1 = 0x0001, // 8168
607 INTT_2 = 0x0002, // 8168
608 INTT_3 = 0x0003, // 8168
1da177e4
LT		 609
610 /* rtl8169_PHYstatus */
07d3f51f
FR		 611 TBI_Enable = 0x80,
612 TxFlowCtrl = 0x40,
613 RxFlowCtrl = 0x20,
614 _1000bpsF = 0x10,
615 _100bps = 0x08,
616 _10bps = 0x04,
617 LinkStatus = 0x02,
618 FullDup = 0x01,
1da177e4 619
1da177e4 620 /* _TBICSRBit */
07d3f51f 621 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 622
623 /* DumpCounterCommand */
07d3f51f 624 CounterDump = 0x8,
6e1d0b89
CHL		 625
626 /* magic enable v2 */
627 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */
1da177e4
LT		 628};
629
2b7b4318
FR		 630enum rtl_desc_bit {
631 /* First doubleword. */
1da177e4
LT		 632 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
633 RingEnd = (1 << 30), /* End of descriptor ring */
634 FirstFrag = (1 << 29), /* First segment of a packet */
635 LastFrag = (1 << 28), /* Final segment of a packet */
2b7b4318
FR		 636};
637
638/* Generic case. */
639enum rtl_tx_desc_bit {
640 /* First doubleword. */
641 TD_LSO = (1 << 27), /* Large Send Offload */
642#define TD_MSS_MAX 0x07ffu /* MSS value */
1da177e4 643
2b7b4318
FR		 644 /* Second doubleword. */
645 TxVlanTag = (1 << 17), /* Add VLAN tag */
646};
647
648/* 8169, 8168b and 810x except 8102e. */
649enum rtl_tx_desc_bit_0 {
650 /* First doubleword. */
651#define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
652 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
653 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
654 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
655};
656
657/* 8102e, 8168c and beyond. */
658enum rtl_tx_desc_bit_1 {
bdfa4ed6 659 /* First doubleword. */
660 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */
e974604b 661 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */
bdfa4ed6 662#define GTTCPHO_SHIFT 18
e974604b 663#define GTTCPHO_MAX 0x7fU
bdfa4ed6 664
2b7b4318 665 /* Second doubleword. */
e974604b 666#define TCPHO_SHIFT 18
667#define TCPHO_MAX 0x3ffU
2b7b4318 668#define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
e974604b 669 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */
670 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */
2b7b4318
FR		 671 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
672 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
673};
1da177e4 674
2b7b4318 675enum rtl_rx_desc_bit {
1da177e4
LT		 676 /* Rx private */
677 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
678 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
679
680#define RxProtoUDP (PID1)
681#define RxProtoTCP (PID0)
682#define RxProtoIP (PID1 | PID0)
683#define RxProtoMask RxProtoIP
684
685 IPFail = (1 << 16), /* IP checksum failed */
686 UDPFail = (1 << 15), /* UDP/IP checksum failed */
687 TCPFail = (1 << 14), /* TCP/IP checksum failed */
688 RxVlanTag = (1 << 16), /* VLAN tag available */
689};
690
691#define RsvdMask 0x3fffc000
692
693struct TxDesc {
6cccd6e7
REB		 694 __le32 opts1;
695 __le32 opts2;
696 __le64 addr;
1da177e4
LT		 697};
698
699struct RxDesc {
6cccd6e7
REB		 700 __le32 opts1;
701 __le32 opts2;
702 __le64 addr;
1da177e4
LT		 703};
704
705struct ring_info {
706 struct sk_buff *skb;
707 u32 len;
708 u8 __pad[sizeof(void *) - sizeof(u32)];
709};
710
f23e7fda 711enum features {
ccdffb9a
FR		 712 RTL_FEATURE_WOL = (1 << 0),
713 RTL_FEATURE_MSI = (1 << 1),
714 RTL_FEATURE_GMII = (1 << 2),
f23e7fda
FR		 715};
716
355423d0
IV		 717struct rtl8169_counters {
718 __le64 tx_packets;
719 __le64 rx_packets;
720 __le64 tx_errors;
721 __le32 rx_errors;
722 __le16 rx_missed;
723 __le16 align_errors;
724 __le32 tx_one_collision;
725 __le32 tx_multi_collision;
726 __le64 rx_unicast;
727 __le64 rx_broadcast;
728 __le32 rx_multicast;
729 __le16 tx_aborted;
730 __le16 tx_underun;
731};
732
da78dbff 733enum rtl_flag {
6c4a70c5 734 RTL_FLAG_TASK_ENABLED,
da78dbff
FR		 735 RTL_FLAG_TASK_SLOW_PENDING,
736 RTL_FLAG_TASK_RESET_PENDING,
737 RTL_FLAG_TASK_PHY_PENDING,
738 RTL_FLAG_MAX
739};
740
8027aa24
JW		 741struct rtl8169_stats {
742 u64 packets;
743 u64 bytes;
744 struct u64_stats_sync syncp;
745};
746
1da177e4
LT		 747struct rtl8169_private {
748 void __iomem *mmio_addr; /* memory map physical address */
cecb5fd7 749 struct pci_dev *pci_dev;
c4028958 750 struct net_device *dev;
bea3348e 751 struct napi_struct napi;
b57b7e5a 752 u32 msg_enable;
2b7b4318
FR		 753 u16 txd_version;
754 u16 mac_version;
1da177e4
LT		 755 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
756 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
1da177e4 757 u32 dirty_tx;
8027aa24
JW		 758 struct rtl8169_stats rx_stats;
759 struct rtl8169_stats tx_stats;
1da177e4
LT		 760 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
761 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
762 dma_addr_t TxPhyAddr;
763 dma_addr_t RxPhyAddr;
6f0333b8 764 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
1da177e4 765 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
1da177e4
LT		 766 struct timer_list timer;
767 u16 cp_cmd;
da78dbff
FR		 768
769 u16 event_slow;
c0e45c1c 770
771 struct mdio_ops {
24192210
FR		 772 void (*write)(struct rtl8169_private *, int, int);
773 int (*read)(struct rtl8169_private *, int);
c0e45c1c 774 } mdio_ops;
775
065c27c1 776 struct pll_power_ops {
777 void (*down)(struct rtl8169_private *);
778 void (*up)(struct rtl8169_private *);
779 } pll_power_ops;
780
d58d46b5
FR		 781 struct jumbo_ops {
782 void (*enable)(struct rtl8169_private *);
783 void (*disable)(struct rtl8169_private *);
784 } jumbo_ops;
785
beb1fe18 786 struct csi_ops {
52989f0e
FR		 787 void (*write)(struct rtl8169_private *, int, int);
788 u32 (*read)(struct rtl8169_private *, int);
beb1fe18
HW		 789 } csi_ops;
790
54405cde 791 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
ccdffb9a 792 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
4da19633 793 void (*phy_reset_enable)(struct rtl8169_private *tp);
07ce4064 794 void (*hw_start)(struct net_device *);
4da19633 795 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
1da177e4 796 unsigned int (*link_ok)(void __iomem *);
8b4ab28d 797 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
5888d3fc 798 bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
4422bcd4
FR		 799
800 struct {
da78dbff
FR		 801 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
802 struct mutex mutex;
4422bcd4
FR		 803 struct work_struct work;
804 } wk;
805
f23e7fda 806 unsigned features;
ccdffb9a
FR		 807
808 struct mii_if_info mii;
355423d0 809 struct rtl8169_counters counters;
e1759441 810 u32 saved_wolopts;
e03f33af 811 u32 opts1_mask;
f1e02ed1 812
b6ffd97f
FR		 813 struct rtl_fw {
814 const struct firmware *fw;
1c361efb
FR		 815
816#define RTL_VER_SIZE 32
817
818 char version[RTL_VER_SIZE];
819
820 struct rtl_fw_phy_action {
821 __le32 *code;
822 size_t size;
823 } phy_action;
b6ffd97f 824 } *rtl_fw;
497888cf 825#define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
c558386b
HW		 826
827 u32 ocp_base;
1da177e4
LT		 828};
829
979b6c13 830MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 831MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 832module_param(use_dac, int, 0);
4300e8c7 833MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 834module_param_named(debug, debug.msg_enable, int, 0);
835MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 836MODULE_LICENSE("GPL");
837MODULE_VERSION(RTL8169_VERSION);
bca03d5f 838MODULE_FIRMWARE(FIRMWARE_8168D_1);
839MODULE_FIRMWARE(FIRMWARE_8168D_2);
01dc7fec 840MODULE_FIRMWARE(FIRMWARE_8168E_1);
841MODULE_FIRMWARE(FIRMWARE_8168E_2);
bbb8af75 842MODULE_FIRMWARE(FIRMWARE_8168E_3);
5a5e4443 843MODULE_FIRMWARE(FIRMWARE_8105E_1);
c2218925
HW		 844MODULE_FIRMWARE(FIRMWARE_8168F_1);
845MODULE_FIRMWARE(FIRMWARE_8168F_2);
7e18dca1 846MODULE_FIRMWARE(FIRMWARE_8402_1);
b3d7b2f2 847MODULE_FIRMWARE(FIRMWARE_8411_1);
45dd95c4 848MODULE_FIRMWARE(FIRMWARE_8411_2);
5598bfe5 849MODULE_FIRMWARE(FIRMWARE_8106E_1);
58152cd4 850MODULE_FIRMWARE(FIRMWARE_8106E_2);
beb330a4 851MODULE_FIRMWARE(FIRMWARE_8168G_2);
57538c4a 852MODULE_FIRMWARE(FIRMWARE_8168G_3);
6e1d0b89
CHL		 853MODULE_FIRMWARE(FIRMWARE_8168H_1);
854MODULE_FIRMWARE(FIRMWARE_8168H_2);
a3bf5c42
FR		 855MODULE_FIRMWARE(FIRMWARE_8107E_1);
856MODULE_FIRMWARE(FIRMWARE_8107E_2);
1da177e4 857
da78dbff
FR		 858static void rtl_lock_work(struct rtl8169_private *tp)
859{
860 mutex_lock(&tp->wk.mutex);
861}
862
863static void rtl_unlock_work(struct rtl8169_private *tp)
864{
865 mutex_unlock(&tp->wk.mutex);
866}
867
d58d46b5
FR		 868static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
869{
7d7903b2
JL		 870 pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
871 PCI_EXP_DEVCTL_READRQ, force);
d58d46b5
FR		 872}
873
ffc46952
FR		 874struct rtl_cond {
875 bool (*check)(struct rtl8169_private *);
876 const char *msg;
877};
878
879static void rtl_udelay(unsigned int d)
880{
881 udelay(d);
882}
883
884static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
885 void (*delay)(unsigned int), unsigned int d, int n,
886 bool high)
887{
888 int i;
889
890 for (i = 0; i < n; i++) {
891 delay(d);
892 if (c->check(tp) == high)
893 return true;
894 }
82e316ef
FR		 895 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
896 c->msg, !high, n, d);
ffc46952
FR		 897 return false;
898}
899
900static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
901 const struct rtl_cond *c,
902 unsigned int d, int n)
903{
904 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
905}
906
907static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
908 const struct rtl_cond *c,
909 unsigned int d, int n)
910{
911 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
912}
913
914static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
915 const struct rtl_cond *c,
916 unsigned int d, int n)
917{
918 return rtl_loop_wait(tp, c, msleep, d, n, true);
919}
920
921static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
922 const struct rtl_cond *c,
923 unsigned int d, int n)
924{
925 return rtl_loop_wait(tp, c, msleep, d, n, false);
926}
927
928#define DECLARE_RTL_COND(name) \
929static bool name ## _check(struct rtl8169_private *); \
930 \
931static const struct rtl_cond name = { \
932 .check = name ## _check, \
933 .msg = #name \
934}; \
935 \
936static bool name ## _check(struct rtl8169_private *tp)
937
938DECLARE_RTL_COND(rtl_ocpar_cond)
939{
940 void __iomem *ioaddr = tp->mmio_addr;
941
942 return RTL_R32(OCPAR) & OCPAR_FLAG;
943}
944
b646d900 945static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
946{
947 void __iomem *ioaddr = tp->mmio_addr;
b646d900 948
949 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
ffc46952
FR		 950
951 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
952 RTL_R32(OCPDR) : ~0;
b646d900 953}
954
955static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
956{
957 void __iomem *ioaddr = tp->mmio_addr;
b646d900 958
959 RTL_W32(OCPDR, data);
960 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
ffc46952
FR		 961
962 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
963}
964
965DECLARE_RTL_COND(rtl_eriar_cond)
966{
967 void __iomem *ioaddr = tp->mmio_addr;
968
969 return RTL_R32(ERIAR) & ERIAR_FLAG;
b646d900 970}
971
fac5b3ca 972static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
b646d900 973{
fac5b3ca 974 void __iomem *ioaddr = tp->mmio_addr;
b646d900 975
976 RTL_W8(ERIDR, cmd);
977 RTL_W32(ERIAR, 0x800010e8);
978 msleep(2);
ffc46952
FR		 979
980 if (!rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 5))
981 return;
b646d900 982
fac5b3ca 983 ocp_write(tp, 0x1, 0x30, 0x00000001);
b646d900 984}
985
986#define OOB_CMD_RESET 0x00
987#define OOB_CMD_DRIVER_START 0x05
988#define OOB_CMD_DRIVER_STOP 0x06
989
cecb5fd7
FR		 990static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
991{
992 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
993}
994
ffc46952 995DECLARE_RTL_COND(rtl_ocp_read_cond)
b646d900 996{
cecb5fd7 997 u16 reg;
b646d900 998
cecb5fd7 999 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 1000
ffc46952 1001 return ocp_read(tp, 0x0f, reg) & 0x00000800;
b646d900 1002}
1003
ffc46952 1004static void rtl8168_driver_start(struct rtl8169_private *tp)
b646d900 1005{
ffc46952 1006 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
b646d900 1007
ffc46952
FR		 1008 rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
1009}
b646d900 1010
ffc46952
FR		 1011static void rtl8168_driver_stop(struct rtl8169_private *tp)
1012{
1013 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
4804b3b3 1014
ffc46952 1015 rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
b646d900 1016}
1017
4804b3b3 1018static int r8168dp_check_dash(struct rtl8169_private *tp)
1019{
cecb5fd7 1020 u16 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 1021
cecb5fd7 1022 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
4804b3b3 1023}
b646d900 1024
c558386b
HW		 1025static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
1026{
1027 if (reg & 0xffff0001) {
1028 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
1029 return true;
1030 }
1031 return false;
1032}
1033
1034DECLARE_RTL_COND(rtl_ocp_gphy_cond)
1035{
1036 void __iomem *ioaddr = tp->mmio_addr;
1037
1038 return RTL_R32(GPHY_OCP) & OCPAR_FLAG;
1039}
1040
1041static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1042{
1043 void __iomem *ioaddr = tp->mmio_addr;
1044
1045 if (rtl_ocp_reg_failure(tp, reg))
1046 return;
1047
1048 RTL_W32(GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
1049
1050 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
1051}
1052
1053static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
1054{
1055 void __iomem *ioaddr = tp->mmio_addr;
1056
1057 if (rtl_ocp_reg_failure(tp, reg))
1058 return 0;
1059
1060 RTL_W32(GPHY_OCP, reg << 15);
1061
1062 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
1063 (RTL_R32(GPHY_OCP) & 0xffff) : ~0;
1064}
1065
c558386b
HW		 1066static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1067{
1068 void __iomem *ioaddr = tp->mmio_addr;
1069
1070 if (rtl_ocp_reg_failure(tp, reg))
1071 return;
1072
1073 RTL_W32(OCPDR, OCPAR_FLAG | (reg << 15) | data);
c558386b
HW		 1074}
1075
1076static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1077{
1078 void __iomem *ioaddr = tp->mmio_addr;
1079
1080 if (rtl_ocp_reg_failure(tp, reg))
1081 return 0;
1082
1083 RTL_W32(OCPDR, reg << 15);
1084
3a83ad12 1085 return RTL_R32(OCPDR);
c558386b
HW		 1086}
1087
1088#define OCP_STD_PHY_BASE 0xa400
1089
1090static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
1091{
1092 if (reg == 0x1f) {
1093 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
1094 return;
1095 }
1096
1097 if (tp->ocp_base != OCP_STD_PHY_BASE)
1098 reg -= 0x10;
1099
1100 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
1101}
1102
1103static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1104{
1105 if (tp->ocp_base != OCP_STD_PHY_BASE)
1106 reg -= 0x10;
1107
1108 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
1109}
1110
eee3786f 1111static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
1112{
1113 if (reg == 0x1f) {
1114 tp->ocp_base = value << 4;
1115 return;
1116 }
1117
1118 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
1119}
1120
1121static int mac_mcu_read(struct rtl8169_private *tp, int reg)
1122{
1123 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
1124}
1125
ffc46952
FR		 1126DECLARE_RTL_COND(rtl_phyar_cond)
1127{
1128 void __iomem *ioaddr = tp->mmio_addr;
1129
1130 return RTL_R32(PHYAR) & 0x80000000;
1131}
1132
24192210 1133static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1da177e4 1134{
24192210 1135 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 1136
24192210 1137 RTL_W32(PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1da177e4 1138
ffc46952 1139 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
024a07ba 1140 /*
81a95f04
TT		 1141 * According to hardware specs a 20us delay is required after write
1142 * complete indication, but before sending next command.
024a07ba 1143 */
81a95f04 1144 udelay(20);
1da177e4
LT		 1145}
1146
24192210 1147static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1da177e4 1148{
24192210 1149 void __iomem *ioaddr = tp->mmio_addr;
ffc46952 1150 int value;
1da177e4 1151
24192210 1152 RTL_W32(PHYAR, 0x0 | (reg & 0x1f) << 16);
1da177e4 1153
ffc46952
FR		 1154 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1155 RTL_R32(PHYAR) & 0xffff : ~0;
1156
81a95f04
TT		 1157 /*
1158 * According to hardware specs a 20us delay is required after read
1159 * complete indication, but before sending next command.
1160 */
1161 udelay(20);
1162
1da177e4
LT		 1163 return value;
1164}
1165
24192210 1166static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
c0e45c1c 1167{
24192210 1168 void __iomem *ioaddr = tp->mmio_addr;
c0e45c1c 1169
24192210 1170 RTL_W32(OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
c0e45c1c 1171 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
1172 RTL_W32(EPHY_RXER_NUM, 0);
1173
ffc46952 1174 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
c0e45c1c 1175}
1176
24192210 1177static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
c0e45c1c 1178{
24192210
FR		 1179 r8168dp_1_mdio_access(tp, reg,
1180 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
c0e45c1c 1181}
1182
24192210 1183static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
c0e45c1c 1184{
24192210 1185 void __iomem *ioaddr = tp->mmio_addr;
c0e45c1c 1186
24192210 1187 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
c0e45c1c 1188
1189 mdelay(1);
1190 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
1191 RTL_W32(EPHY_RXER_NUM, 0);
1192
ffc46952
FR		 1193 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1194 RTL_R32(OCPDR) & OCPDR_DATA_MASK : ~0;
c0e45c1c 1195}
1196
e6de30d6 1197#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1198
1199static void r8168dp_2_mdio_start(void __iomem *ioaddr)
1200{
1201 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1202}
1203
1204static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
1205{
1206 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1207}
1208
24192210 1209static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
e6de30d6 1210{
24192210
FR		 1211 void __iomem *ioaddr = tp->mmio_addr;
1212
e6de30d6 1213 r8168dp_2_mdio_start(ioaddr);
1214
24192210 1215 r8169_mdio_write(tp, reg, value);
e6de30d6 1216
1217 r8168dp_2_mdio_stop(ioaddr);
1218}
1219
24192210 1220static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
e6de30d6 1221{
24192210 1222 void __iomem *ioaddr = tp->mmio_addr;
e6de30d6 1223 int value;
1224
1225 r8168dp_2_mdio_start(ioaddr);
1226
24192210 1227 value = r8169_mdio_read(tp, reg);
e6de30d6 1228
1229 r8168dp_2_mdio_stop(ioaddr);
1230
1231 return value;
1232}
1233
4da19633 1234static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
dacf8154 1235{
24192210 1236 tp->mdio_ops.write(tp, location, val);
dacf8154
FR		 1237}
1238
4da19633 1239static int rtl_readphy(struct rtl8169_private *tp, int location)
1240{
24192210 1241 return tp->mdio_ops.read(tp, location);
4da19633 1242}
1243
1244static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1245{
1246 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1247}
1248
1249static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
daf9df6d 1250{
1251 int val;
1252
4da19633 1253 val = rtl_readphy(tp, reg_addr);
1254 rtl_writephy(tp, reg_addr, (val | p) & ~m);
daf9df6d 1255}
1256
ccdffb9a
FR		 1257static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1258 int val)
1259{
1260 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1261
4da19633 1262 rtl_writephy(tp, location, val);
ccdffb9a
FR		 1263}
1264
1265static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1266{
1267 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1268
4da19633 1269 return rtl_readphy(tp, location);
ccdffb9a
FR		 1270}
1271
ffc46952
FR		 1272DECLARE_RTL_COND(rtl_ephyar_cond)
1273{
1274 void __iomem *ioaddr = tp->mmio_addr;
1275
1276 return RTL_R32(EPHYAR) & EPHYAR_FLAG;
1277}
1278
fdf6fc06 1279static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
dacf8154 1280{
fdf6fc06 1281 void __iomem *ioaddr = tp->mmio_addr;
dacf8154
FR		 1282
1283 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1284 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1285
ffc46952
FR		 1286 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1287
1288 udelay(10);
dacf8154
FR		 1289}
1290
fdf6fc06 1291static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
dacf8154 1292{
fdf6fc06 1293 void __iomem *ioaddr = tp->mmio_addr;
dacf8154
FR		 1294
1295 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1296
ffc46952
FR		 1297 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1298 RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0;
dacf8154
FR		 1299}
1300
fdf6fc06
FR		 1301static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1302 u32 val, int type)
133ac40a 1303{
fdf6fc06 1304 void __iomem *ioaddr = tp->mmio_addr;
133ac40a
HW		 1305
1306 BUG_ON((addr & 3) || (mask == 0));
1307 RTL_W32(ERIDR, val);
1308 RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1309
ffc46952 1310 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
133ac40a
HW		 1311}
1312
fdf6fc06 1313static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
133ac40a 1314{
fdf6fc06 1315 void __iomem *ioaddr = tp->mmio_addr;
133ac40a
HW		 1316
1317 RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1318
ffc46952
FR		 1319 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1320 RTL_R32(ERIDR) : ~0;
133ac40a
HW		 1321}
1322
fdf6fc06
FR		 1323static void rtl_w1w0_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1324 u32 m, int type)
133ac40a
HW		 1325{
1326 u32 val;
1327
fdf6fc06
FR		 1328 val = rtl_eri_read(tp, addr, type);
1329 rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
133ac40a
HW		 1330}
1331
c28aa385 1332struct exgmac_reg {
1333 u16 addr;
1334 u16 mask;
1335 u32 val;
1336};
1337
fdf6fc06 1338static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
c28aa385 1339 const struct exgmac_reg *r, int len)
1340{
1341 while (len-- > 0) {
fdf6fc06 1342 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
c28aa385 1343 r++;
1344 }
1345}
1346
ffc46952
FR		 1347DECLARE_RTL_COND(rtl_efusear_cond)
1348{
1349 void __iomem *ioaddr = tp->mmio_addr;
1350
1351 return RTL_R32(EFUSEAR) & EFUSEAR_FLAG;
1352}
1353
fdf6fc06 1354static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
daf9df6d 1355{
fdf6fc06 1356 void __iomem *ioaddr = tp->mmio_addr;
daf9df6d 1357
1358 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1359
ffc46952
FR		 1360 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1361 RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
daf9df6d 1362}
1363
9085cdfa
FR		 1364static u16 rtl_get_events(struct rtl8169_private *tp)
1365{
1366 void __iomem *ioaddr = tp->mmio_addr;
1367
1368 return RTL_R16(IntrStatus);
1369}
1370
1371static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1372{
1373 void __iomem *ioaddr = tp->mmio_addr;
1374
1375 RTL_W16(IntrStatus, bits);
1376 mmiowb();
1377}
1378
1379static void rtl_irq_disable(struct rtl8169_private *tp)
1380{
1381 void __iomem *ioaddr = tp->mmio_addr;
1382
1383 RTL_W16(IntrMask, 0);
1384 mmiowb();
1385}
1386
3e990ff5
FR		 1387static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1388{
1389 void __iomem *ioaddr = tp->mmio_addr;
1390
1391 RTL_W16(IntrMask, bits);
1392}
1393
da78dbff
FR		 1394#define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1395#define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1396#define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1397
1398static void rtl_irq_enable_all(struct rtl8169_private *tp)
1399{
1400 rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1401}
1402
811fd301 1403static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1da177e4 1404{
811fd301 1405 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 1406
9085cdfa 1407 rtl_irq_disable(tp);
da78dbff 1408 rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
811fd301 1409 RTL_R8(ChipCmd);
1da177e4
LT		 1410}
1411
4da19633 1412static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1da177e4 1413{
4da19633 1414 void __iomem *ioaddr = tp->mmio_addr;
1415
1da177e4
LT		 1416 return RTL_R32(TBICSR) & TBIReset;
1417}
1418
4da19633 1419static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1da177e4 1420{
4da19633 1421 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 1422}
1423
1424static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1425{
1426 return RTL_R32(TBICSR) & TBILinkOk;
1427}
1428
1429static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1430{
1431 return RTL_R8(PHYstatus) & LinkStatus;
1432}
1433
4da19633 1434static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1da177e4 1435{
4da19633 1436 void __iomem *ioaddr = tp->mmio_addr;
1437
1da177e4
LT		 1438 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1439}
1440
4da19633 1441static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1da177e4
LT		 1442{
1443 unsigned int val;
1444
4da19633 1445 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1446 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1da177e4
LT		 1447}
1448
70090424
HW		 1449static void rtl_link_chg_patch(struct rtl8169_private *tp)
1450{
1451 void __iomem *ioaddr = tp->mmio_addr;
1452 struct net_device *dev = tp->dev;
1453
1454 if (!netif_running(dev))
1455 return;
1456
b3d7b2f2
HW		 1457 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1458 tp->mac_version == RTL_GIGA_MAC_VER_38) {
70090424 1459 if (RTL_R8(PHYstatus) & _1000bpsF) {
fdf6fc06
FR		 1460 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1461 ERIAR_EXGMAC);
1462 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1463 ERIAR_EXGMAC);
70090424 1464 } else if (RTL_R8(PHYstatus) & _100bps) {
fdf6fc06
FR		 1465 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1466 ERIAR_EXGMAC);
1467 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1468 ERIAR_EXGMAC);
70090424 1469 } else {
fdf6fc06
FR		 1470 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1471 ERIAR_EXGMAC);
1472 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1473 ERIAR_EXGMAC);
70090424
HW		 1474 }
1475 /* Reset packet filter */
fdf6fc06 1476 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
70090424 1477 ERIAR_EXGMAC);
fdf6fc06 1478 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
70090424 1479 ERIAR_EXGMAC);
c2218925
HW		 1480 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1481 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1482 if (RTL_R8(PHYstatus) & _1000bpsF) {
fdf6fc06
FR		 1483 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1484 ERIAR_EXGMAC);
1485 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1486 ERIAR_EXGMAC);
c2218925 1487 } else {
fdf6fc06
FR		 1488 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1489 ERIAR_EXGMAC);
1490 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1491 ERIAR_EXGMAC);
c2218925 1492 }
7e18dca1
HW		 1493 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1494 if (RTL_R8(PHYstatus) & _10bps) {
fdf6fc06
FR		 1495 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1496 ERIAR_EXGMAC);
1497 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1498 ERIAR_EXGMAC);
7e18dca1 1499 } else {
fdf6fc06
FR		 1500 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1501 ERIAR_EXGMAC);
7e18dca1 1502 }
70090424
HW		 1503 }
1504}
1505
e4fbce74 1506static void __rtl8169_check_link_status(struct net_device *dev,
cecb5fd7
FR		 1507 struct rtl8169_private *tp,
1508 void __iomem *ioaddr, bool pm)
1da177e4 1509{
1da177e4 1510 if (tp->link_ok(ioaddr)) {
70090424 1511 rtl_link_chg_patch(tp);
e1759441 1512 /* This is to cancel a scheduled suspend if there's one. */
e4fbce74
RW		 1513 if (pm)
1514 pm_request_resume(&tp->pci_dev->dev);
1da177e4 1515 netif_carrier_on(dev);
1519e57f
FR		 1516 if (net_ratelimit())
1517 netif_info(tp, ifup, dev, "link up\n");
b57b7e5a 1518 } else {
1da177e4 1519 netif_carrier_off(dev);
bf82c189 1520 netif_info(tp, ifdown, dev, "link down\n");
e4fbce74 1521 if (pm)
10953db8 1522 pm_schedule_suspend(&tp->pci_dev->dev, 5000);
b57b7e5a 1523 }
1da177e4
LT		 1524}
1525
e4fbce74
RW		 1526static void rtl8169_check_link_status(struct net_device *dev,
1527 struct rtl8169_private *tp,
1528 void __iomem *ioaddr)
1529{
1530 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1531}
1532
e1759441
RW		 1533#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1534
1535static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
61a4dcc2 1536{
61a4dcc2
FR		 1537 void __iomem *ioaddr = tp->mmio_addr;
1538 u8 options;
e1759441 1539 u32 wolopts = 0;
61a4dcc2
FR		 1540
1541 options = RTL_R8(Config1);
1542 if (!(options & PMEnable))
e1759441 1543 return 0;
61a4dcc2
FR		 1544
1545 options = RTL_R8(Config3);
1546 if (options & LinkUp)
e1759441 1547 wolopts |= WAKE_PHY;
6e1d0b89
CHL		 1548 switch (tp->mac_version) {
1549 case RTL_GIGA_MAC_VER_45:
1550 case RTL_GIGA_MAC_VER_46:
1551 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
1552 wolopts |= WAKE_MAGIC;
1553 break;
1554 default:
1555 if (options & MagicPacket)
1556 wolopts |= WAKE_MAGIC;
1557 break;
1558 }
61a4dcc2
FR		 1559
1560 options = RTL_R8(Config5);
1561 if (options & UWF)
e1759441 1562 wolopts |= WAKE_UCAST;
61a4dcc2 1563 if (options & BWF)
e1759441 1564 wolopts |= WAKE_BCAST;
61a4dcc2 1565 if (options & MWF)
e1759441 1566 wolopts |= WAKE_MCAST;
61a4dcc2 1567
e1759441 1568 return wolopts;
61a4dcc2
FR		 1569}
1570
e1759441 1571static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
61a4dcc2
FR		 1572{
1573 struct rtl8169_private *tp = netdev_priv(dev);
e1759441 1574
da78dbff 1575 rtl_lock_work(tp);
e1759441
RW		 1576
1577 wol->supported = WAKE_ANY;
1578 wol->wolopts = __rtl8169_get_wol(tp);
1579
da78dbff 1580 rtl_unlock_work(tp);
e1759441
RW		 1581}
1582
1583static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1584{
61a4dcc2 1585 void __iomem *ioaddr = tp->mmio_addr;
6e1d0b89 1586 unsigned int i, tmp;
350f7596 1587 static const struct {
61a4dcc2
FR		 1588 u32 opt;
1589 u16 reg;
1590 u8 mask;
1591 } cfg[] = {
61a4dcc2 1592 { WAKE_PHY, Config3, LinkUp },
61a4dcc2
FR		 1593 { WAKE_UCAST, Config5, UWF },
1594 { WAKE_BCAST, Config5, BWF },
1595 { WAKE_MCAST, Config5, MWF },
6e1d0b89
CHL		 1596 { WAKE_ANY, Config5, LanWake },
1597 { WAKE_MAGIC, Config3, MagicPacket }
61a4dcc2 1598 };
851e6022 1599 u8 options;
61a4dcc2 1600
61a4dcc2
FR		 1601 RTL_W8(Cfg9346, Cfg9346_Unlock);
1602
6e1d0b89
CHL		 1603 switch (tp->mac_version) {
1604 case RTL_GIGA_MAC_VER_45:
1605 case RTL_GIGA_MAC_VER_46:
1606 tmp = ARRAY_SIZE(cfg) - 1;
1607 if (wolopts & WAKE_MAGIC)
1608 rtl_w1w0_eri(tp,
1609 0x0dc,
1610 ERIAR_MASK_0100,
1611 MagicPacket_v2,
1612 0x0000,
1613 ERIAR_EXGMAC);
1614 else
1615 rtl_w1w0_eri(tp,
1616 0x0dc,
1617 ERIAR_MASK_0100,
1618 0x0000,
1619 MagicPacket_v2,
1620 ERIAR_EXGMAC);
1621 break;
1622 default:
1623 tmp = ARRAY_SIZE(cfg);
1624 break;
1625 }
1626
1627 for (i = 0; i < tmp; i++) {
851e6022 1628 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
e1759441 1629 if (wolopts & cfg[i].opt)
61a4dcc2
FR		 1630 options |= cfg[i].mask;
1631 RTL_W8(cfg[i].reg, options);
1632 }
1633
851e6022
FR		 1634 switch (tp->mac_version) {
1635 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1636 options = RTL_R8(Config1) & ~PMEnable;
1637 if (wolopts)
1638 options |= PMEnable;
1639 RTL_W8(Config1, options);
1640 break;
1641 default:
d387b427
FR		 1642 options = RTL_R8(Config2) & ~PME_SIGNAL;
1643 if (wolopts)
1644 options |= PME_SIGNAL;
1645 RTL_W8(Config2, options);
851e6022
FR		 1646 break;
1647 }
1648
61a4dcc2 1649 RTL_W8(Cfg9346, Cfg9346_Lock);
e1759441
RW		 1650}
1651
1652static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1653{
1654 struct rtl8169_private *tp = netdev_priv(dev);
1655
da78dbff 1656 rtl_lock_work(tp);
61a4dcc2 1657
f23e7fda
FR		 1658 if (wol->wolopts)
1659 tp->features |= RTL_FEATURE_WOL;
1660 else
1661 tp->features &= ~RTL_FEATURE_WOL;
e1759441 1662 __rtl8169_set_wol(tp, wol->wolopts);
da78dbff
FR		 1663
1664 rtl_unlock_work(tp);
61a4dcc2 1665
ea80907f 1666 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1667
61a4dcc2
FR		 1668 return 0;
1669}
1670
31bd204f
FR		 1671static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1672{
85bffe6c 1673 return rtl_chip_infos[tp->mac_version].fw_name;
31bd204f
FR		 1674}
1675
1da177e4
LT		 1676static void rtl8169_get_drvinfo(struct net_device *dev,
1677 struct ethtool_drvinfo *info)
1678{
1679 struct rtl8169_private *tp = netdev_priv(dev);
b6ffd97f 1680 struct rtl_fw *rtl_fw = tp->rtl_fw;
1da177e4 1681
68aad78c
RJ		 1682 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1683 strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1684 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1c361efb 1685 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
8ac72d16
RJ		 1686 if (!IS_ERR_OR_NULL(rtl_fw))
1687 strlcpy(info->fw_version, rtl_fw->version,
1688 sizeof(info->fw_version));
1da177e4
LT		 1689}
1690
1691static int rtl8169_get_regs_len(struct net_device *dev)
1692{
1693 return R8169_REGS_SIZE;
1694}
1695
1696static int rtl8169_set_speed_tbi(struct net_device *dev,
54405cde 1697 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1da177e4
LT		 1698{
1699 struct rtl8169_private *tp = netdev_priv(dev);
1700 void __iomem *ioaddr = tp->mmio_addr;
1701 int ret = 0;
1702 u32 reg;
1703
1704 reg = RTL_R32(TBICSR);
1705 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1706 (duplex == DUPLEX_FULL)) {
1707 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1708 } else if (autoneg == AUTONEG_ENABLE)
1709 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1710 else {
bf82c189
JP		 1711 netif_warn(tp, link, dev,
1712 "incorrect speed setting refused in TBI mode\n");
1da177e4
LT		 1713 ret = -EOPNOTSUPP;
1714 }
1715
1716 return ret;
1717}
1718
1719static int rtl8169_set_speed_xmii(struct net_device *dev,
54405cde 1720 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1da177e4
LT		 1721{
1722 struct rtl8169_private *tp = netdev_priv(dev);
3577aa1b 1723 int giga_ctrl, bmcr;
54405cde 1724 int rc = -EINVAL;
1da177e4 1725
716b50a3 1726 rtl_writephy(tp, 0x1f, 0x0000);
1da177e4
LT		 1727
1728 if (autoneg == AUTONEG_ENABLE) {
3577aa1b 1729 int auto_nego;
1730
4da19633 1731 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
54405cde
ON		 1732 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1733 ADVERTISE_100HALF | ADVERTISE_100FULL);
1734
1735 if (adv & ADVERTISED_10baseT_Half)
1736 auto_nego |= ADVERTISE_10HALF;
1737 if (adv & ADVERTISED_10baseT_Full)
1738 auto_nego |= ADVERTISE_10FULL;
1739 if (adv & ADVERTISED_100baseT_Half)
1740 auto_nego |= ADVERTISE_100HALF;
1741 if (adv & ADVERTISED_100baseT_Full)
1742 auto_nego |= ADVERTISE_100FULL;
1743
3577aa1b 1744 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1da177e4 1745
4da19633 1746 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
3577aa1b 1747 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
bcf0bf90 1748
3577aa1b 1749 /* The 8100e/8101e/8102e do Fast Ethernet only. */
826e6cbd 1750 if (tp->mii.supports_gmii) {
54405cde
ON		 1751 if (adv & ADVERTISED_1000baseT_Half)
1752 giga_ctrl |= ADVERTISE_1000HALF;
1753 if (adv & ADVERTISED_1000baseT_Full)
1754 giga_ctrl |= ADVERTISE_1000FULL;
1755 } else if (adv & (ADVERTISED_1000baseT_Half |
1756 ADVERTISED_1000baseT_Full)) {
bf82c189
JP		 1757 netif_info(tp, link, dev,
1758 "PHY does not support 1000Mbps\n");
54405cde 1759 goto out;
bcf0bf90 1760 }
1da177e4 1761
3577aa1b 1762 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1763
4da19633 1764 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1765 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
3577aa1b 1766 } else {
1767 giga_ctrl = 0;
1768
1769 if (speed == SPEED_10)
1770 bmcr = 0;
1771 else if (speed == SPEED_100)
1772 bmcr = BMCR_SPEED100;
1773 else
54405cde 1774 goto out;
3577aa1b 1775
1776 if (duplex == DUPLEX_FULL)
1777 bmcr |= BMCR_FULLDPLX;
2584fbc3
RS		 1778 }
1779
4da19633 1780 rtl_writephy(tp, MII_BMCR, bmcr);
3577aa1b 1781
cecb5fd7
FR		 1782 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1783 tp->mac_version == RTL_GIGA_MAC_VER_03) {
3577aa1b 1784 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
4da19633 1785 rtl_writephy(tp, 0x17, 0x2138);
1786 rtl_writephy(tp, 0x0e, 0x0260);
3577aa1b 1787 } else {
4da19633 1788 rtl_writephy(tp, 0x17, 0x2108);
1789 rtl_writephy(tp, 0x0e, 0x0000);
3577aa1b 1790 }
1791 }
1792
54405cde
ON		 1793 rc = 0;
1794out:
1795 return rc;
1da177e4
LT		 1796}
1797
1798static int rtl8169_set_speed(struct net_device *dev,
54405cde 1799 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1da177e4
LT		 1800{
1801 struct rtl8169_private *tp = netdev_priv(dev);
1802 int ret;
1803
54405cde 1804 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
4876cc1e
FR		 1805 if (ret < 0)
1806 goto out;
1da177e4 1807
4876cc1e
FR		 1808 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1809 (advertising & ADVERTISED_1000baseT_Full)) {
1da177e4 1810 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
4876cc1e
FR		 1811 }
1812out:
1da177e4
LT		 1813 return ret;
1814}
1815
1816static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1817{
1818 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4
LT		 1819 int ret;
1820
4876cc1e
FR		 1821 del_timer_sync(&tp->timer);
1822
da78dbff 1823 rtl_lock_work(tp);
cecb5fd7 1824 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
25db0338 1825 cmd->duplex, cmd->advertising);
da78dbff 1826 rtl_unlock_work(tp);
5b0384f4 1827
1da177e4
LT		 1828 return ret;
1829}
1830
c8f44aff
MM		 1831static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1832 netdev_features_t features)
1da177e4 1833{
d58d46b5
FR		 1834 struct rtl8169_private *tp = netdev_priv(dev);
1835
2b7b4318 1836 if (dev->mtu > TD_MSS_MAX)
350fb32a 1837 features &= ~NETIF_F_ALL_TSO;
1da177e4 1838
d58d46b5
FR		 1839 if (dev->mtu > JUMBO_1K &&
1840 !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1841 features &= ~NETIF_F_IP_CSUM;
1842
350fb32a 1843 return features;
1da177e4
LT		 1844}
1845
da78dbff
FR		 1846static void __rtl8169_set_features(struct net_device *dev,
1847 netdev_features_t features)
1da177e4
LT		 1848{
1849 struct rtl8169_private *tp = netdev_priv(dev);
da78dbff 1850 void __iomem *ioaddr = tp->mmio_addr;
929a031d 1851 u32 rx_config;
1da177e4 1852
929a031d 1853 rx_config = RTL_R32(RxConfig);
1854 if (features & NETIF_F_RXALL)
1855 rx_config |= (AcceptErr | AcceptRunt);
1856 else
1857 rx_config &= ~(AcceptErr | AcceptRunt);
1da177e4 1858
929a031d 1859 RTL_W32(RxConfig, rx_config);
350fb32a 1860
929a031d 1861 if (features & NETIF_F_RXCSUM)
1862 tp->cp_cmd |= RxChkSum;
1863 else
1864 tp->cp_cmd &= ~RxChkSum;
6bbe021d 1865
929a031d 1866 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1867 tp->cp_cmd |= RxVlan;
1868 else
1869 tp->cp_cmd &= ~RxVlan;
1870
1871 tp->cp_cmd |= RTL_R16(CPlusCmd) & ~(RxVlan | RxChkSum);
1872
1873 RTL_W16(CPlusCmd, tp->cp_cmd);
1874 RTL_R16(CPlusCmd);
da78dbff 1875}
1da177e4 1876
da78dbff
FR		 1877static int rtl8169_set_features(struct net_device *dev,
1878 netdev_features_t features)
1879{
1880 struct rtl8169_private *tp = netdev_priv(dev);
1881
929a031d 1882 features &= NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX;
1883
da78dbff 1884 rtl_lock_work(tp);
85911d71 1885 if (features ^ dev->features)
929a031d 1886 __rtl8169_set_features(dev, features);
da78dbff 1887 rtl_unlock_work(tp);
1da177e4
LT		 1888
1889 return 0;
1890}
1891
da78dbff 1892
810f4893 1893static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1da177e4 1894{
eab6d18d 1895 return (vlan_tx_tag_present(skb)) ?
1da177e4
LT		 1896 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1897}
1898
7a8fc77b 1899static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1da177e4
LT		 1900{
1901 u32 opts2 = le32_to_cpu(desc->opts2);
1da177e4 1902
7a8fc77b 1903 if (opts2 & RxVlanTag)
86a9bad3 1904 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1da177e4
LT		 1905}
1906
ccdffb9a 1907static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1908{
1909 struct rtl8169_private *tp = netdev_priv(dev);
1910 void __iomem *ioaddr = tp->mmio_addr;
1911 u32 status;
1912
1913 cmd->supported =
1914 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1915 cmd->port = PORT_FIBRE;
1916 cmd->transceiver = XCVR_INTERNAL;
1917
1918 status = RTL_R32(TBICSR);
1919 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1920 cmd->autoneg = !!(status & TBINwEnable);
1921
70739497 1922 ethtool_cmd_speed_set(cmd, SPEED_1000);
1da177e4 1923 cmd->duplex = DUPLEX_FULL; /* Always set */
ccdffb9a
FR		 1924
1925 return 0;
1da177e4
LT		 1926}
1927
ccdffb9a 1928static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1929{
1930 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a
FR		 1931
1932 return mii_ethtool_gset(&tp->mii, cmd);
1da177e4
LT		 1933}
1934
1935static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1936{
1937 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1938 int rc;
1da177e4 1939
da78dbff 1940 rtl_lock_work(tp);
ccdffb9a 1941 rc = tp->get_settings(dev, cmd);
da78dbff 1942 rtl_unlock_work(tp);
1da177e4 1943
ccdffb9a 1944 return rc;
1da177e4
LT		 1945}
1946
1947static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1948 void *p)
1949{
5b0384f4 1950 struct rtl8169_private *tp = netdev_priv(dev);
15edae91
PW		 1951 u32 __iomem *data = tp->mmio_addr;
1952 u32 *dw = p;
1953 int i;
1da177e4 1954
da78dbff 1955 rtl_lock_work(tp);
15edae91
PW		 1956 for (i = 0; i < R8169_REGS_SIZE; i += 4)
1957 memcpy_fromio(dw++, data++, 4);
da78dbff 1958 rtl_unlock_work(tp);
1da177e4
LT		 1959}
1960
b57b7e5a
SH		 1961static u32 rtl8169_get_msglevel(struct net_device *dev)
1962{
1963 struct rtl8169_private *tp = netdev_priv(dev);
1964
1965 return tp->msg_enable;
1966}
1967
1968static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1969{
1970 struct rtl8169_private *tp = netdev_priv(dev);
1971
1972 tp->msg_enable = value;
1973}
1974
d4a3a0fc
SH		 1975static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1976 "tx_packets",
1977 "rx_packets",
1978 "tx_errors",
1979 "rx_errors",
1980 "rx_missed",
1981 "align_errors",
1982 "tx_single_collisions",
1983 "tx_multi_collisions",
1984 "unicast",
1985 "broadcast",
1986 "multicast",
1987 "tx_aborted",
1988 "tx_underrun",
1989};
1990
b9f2c044 1991static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1992{
b9f2c044
JG		 1993 switch (sset) {
1994 case ETH_SS_STATS:
1995 return ARRAY_SIZE(rtl8169_gstrings);
1996 default:
1997 return -EOPNOTSUPP;
1998 }
d4a3a0fc
SH		 1999}
2000
ffc46952
FR		 2001DECLARE_RTL_COND(rtl_counters_cond)
2002{
2003 void __iomem *ioaddr = tp->mmio_addr;
2004
2005 return RTL_R32(CounterAddrLow) & CounterDump;
2006}
2007
355423d0 2008static void rtl8169_update_counters(struct net_device *dev)
d4a3a0fc
SH		 2009{
2010 struct rtl8169_private *tp = netdev_priv(dev);
2011 void __iomem *ioaddr = tp->mmio_addr;
cecb5fd7 2012 struct device *d = &tp->pci_dev->dev;
d4a3a0fc
SH		 2013 struct rtl8169_counters *counters;
2014 dma_addr_t paddr;
2015 u32 cmd;
2016
355423d0
IV		 2017 /*
2018 * Some chips are unable to dump tally counters when the receiver
2019 * is disabled.
2020 */
2021 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
2022 return;
d4a3a0fc 2023
48addcc9 2024 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
d4a3a0fc
SH		 2025 if (!counters)
2026 return;
2027
2028 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
284901a9 2029 cmd = (u64)paddr & DMA_BIT_MASK(32);
d4a3a0fc
SH		 2030 RTL_W32(CounterAddrLow, cmd);
2031 RTL_W32(CounterAddrLow, cmd | CounterDump);
2032
ffc46952
FR		 2033 if (rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000))
2034 memcpy(&tp->counters, counters, sizeof(*counters));
d4a3a0fc
SH		 2035
2036 RTL_W32(CounterAddrLow, 0);
2037 RTL_W32(CounterAddrHigh, 0);
2038
48addcc9 2039 dma_free_coherent(d, sizeof(*counters), counters, paddr);
d4a3a0fc
SH		 2040}
2041
355423d0
IV		 2042static void rtl8169_get_ethtool_stats(struct net_device *dev,
2043 struct ethtool_stats *stats, u64 *data)
2044{
2045 struct rtl8169_private *tp = netdev_priv(dev);
2046
2047 ASSERT_RTNL();
2048
2049 rtl8169_update_counters(dev);
2050
2051 data[0] = le64_to_cpu(tp->counters.tx_packets);
2052 data[1] = le64_to_cpu(tp->counters.rx_packets);
2053 data[2] = le64_to_cpu(tp->counters.tx_errors);
2054 data[3] = le32_to_cpu(tp->counters.rx_errors);
2055 data[4] = le16_to_cpu(tp->counters.rx_missed);
2056 data[5] = le16_to_cpu(tp->counters.align_errors);
2057 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
2058 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
2059 data[8] = le64_to_cpu(tp->counters.rx_unicast);
2060 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
2061 data[10] = le32_to_cpu(tp->counters.rx_multicast);
2062 data[11] = le16_to_cpu(tp->counters.tx_aborted);
2063 data[12] = le16_to_cpu(tp->counters.tx_underun);
2064}
2065
d4a3a0fc
SH		 2066static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2067{
2068 switch(stringset) {
2069 case ETH_SS_STATS:
2070 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
2071 break;
2072 }
2073}
2074
7282d491 2075static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 2076 .get_drvinfo = rtl8169_get_drvinfo,
2077 .get_regs_len = rtl8169_get_regs_len,
2078 .get_link = ethtool_op_get_link,
2079 .get_settings = rtl8169_get_settings,
2080 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 2081 .get_msglevel = rtl8169_get_msglevel,
2082 .set_msglevel = rtl8169_set_msglevel,
1da177e4 2083 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 2084 .get_wol = rtl8169_get_wol,
2085 .set_wol = rtl8169_set_wol,
d4a3a0fc 2086 .get_strings = rtl8169_get_strings,
b9f2c044 2087 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 2088 .get_ethtool_stats = rtl8169_get_ethtool_stats,
e1593bb1 2089 .get_ts_info = ethtool_op_get_ts_info,
1da177e4
LT		 2090};
2091
07d3f51f 2092static void rtl8169_get_mac_version(struct rtl8169_private *tp,
5d320a20 2093 struct net_device *dev, u8 default_version)
1da177e4 2094{
5d320a20 2095 void __iomem *ioaddr = tp->mmio_addr;
0e485150
FR		 2096 /*
2097 * The driver currently handles the 8168Bf and the 8168Be identically
2098 * but they can be identified more specifically through the test below
2099 * if needed:
2100 *
2101 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 2102 *
2103 * Same thing for the 8101Eb and the 8101Ec:
2104 *
2105 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 2106 */
3744100e 2107 static const struct rtl_mac_info {
1da177e4 2108 u32 mask;
e3cf0cc0 2109 u32 val;
1da177e4
LT		 2110 int mac_version;
2111 } mac_info[] = {
6e1d0b89
CHL		 2112 /* 8168H family. */
2113 { 0x7cf00000, 0x54100000, RTL_GIGA_MAC_VER_46 },
2114 { 0x7cf00000, 0x54000000, RTL_GIGA_MAC_VER_45 },
2115
c558386b 2116 /* 8168G family. */
45dd95c4 2117 { 0x7cf00000, 0x5c800000, RTL_GIGA_MAC_VER_44 },
57538c4a 2118 { 0x7cf00000, 0x50900000, RTL_GIGA_MAC_VER_42 },
c558386b
HW		 2119 { 0x7cf00000, 0x4c100000, RTL_GIGA_MAC_VER_41 },
2120 { 0x7cf00000, 0x4c000000, RTL_GIGA_MAC_VER_40 },
2121
c2218925 2122 /* 8168F family. */
b3d7b2f2 2123 { 0x7c800000, 0x48800000, RTL_GIGA_MAC_VER_38 },
c2218925
HW		 2124 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
2125 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
2126
01dc7fec 2127 /* 8168E family. */
70090424 2128 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
01dc7fec 2129 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
2130 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
2131 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
2132
5b538df9 2133 /* 8168D family. */
daf9df6d 2134 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
2135 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
daf9df6d 2136 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
5b538df9 2137
e6de30d6 2138 /* 8168DP family. */
2139 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
2140 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
4804b3b3 2141 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
e6de30d6 2142
ef808d50 2143 /* 8168C family. */
17c99297 2144 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
ef3386f0 2145 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 2146 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 2147 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 2148 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
2149 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 2150 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
6fb07058 2151 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
ef808d50 2152 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 2153
2154 /* 8168B family. */
2155 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
2156 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
2157 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
2158 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
2159
2160 /* 8101 family. */
5598bfe5
HW		 2161 { 0x7cf00000, 0x44900000, RTL_GIGA_MAC_VER_39 },
2162 { 0x7c800000, 0x44800000, RTL_GIGA_MAC_VER_39 },
7e18dca1 2163 { 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37 },
36a0e6c2 2164 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
5a5e4443
HW		 2165 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
2166 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
2167 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2857ffb7
FR		 2168 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
2169 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
2170 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
2171 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
2172 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
2173 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 2174 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 2175 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 2176 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 2177 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
2178 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 2179 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
2180 /* FIXME: where did these entries come from ? -- FR */
2181 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
2182 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
2183
2184 /* 8110 family. */
2185 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
2186 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
2187 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
2188 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
2189 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
2190 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
2191
f21b75e9
JD		 2192 /* Catch-all */
2193 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
3744100e
FR		 2194 };
2195 const struct rtl_mac_info *p = mac_info;
1da177e4
LT		 2196 u32 reg;
2197
e3cf0cc0
FR		 2198 reg = RTL_R32(TxConfig);
2199 while ((reg & p->mask) != p->val)
1da177e4
LT		 2200 p++;
2201 tp->mac_version = p->mac_version;
5d320a20
FR		 2202
2203 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2204 netif_notice(tp, probe, dev,
2205 "unknown MAC, using family default\n");
2206 tp->mac_version = default_version;
58152cd4 2207 } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
2208 tp->mac_version = tp->mii.supports_gmii ?
2209 RTL_GIGA_MAC_VER_42 :
2210 RTL_GIGA_MAC_VER_43;
6e1d0b89
CHL		 2211 } else if (tp->mac_version == RTL_GIGA_MAC_VER_45) {
2212 tp->mac_version = tp->mii.supports_gmii ?
2213 RTL_GIGA_MAC_VER_45 :
2214 RTL_GIGA_MAC_VER_47;
2215 } else if (tp->mac_version == RTL_GIGA_MAC_VER_46) {
2216 tp->mac_version = tp->mii.supports_gmii ?
2217 RTL_GIGA_MAC_VER_46 :
2218 RTL_GIGA_MAC_VER_48;
5d320a20 2219 }
1da177e4
LT		 2220}
2221
2222static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2223{
bcf0bf90 2224 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 2225}
2226
867763c1
FR		 2227struct phy_reg {
2228 u16 reg;
2229 u16 val;
2230};
2231
4da19633 2232static void rtl_writephy_batch(struct rtl8169_private *tp,
2233 const struct phy_reg *regs, int len)
867763c1
FR		 2234{
2235 while (len-- > 0) {
4da19633 2236 rtl_writephy(tp, regs->reg, regs->val);
867763c1
FR		 2237 regs++;
2238 }
2239}
2240
bca03d5f 2241#define PHY_READ 0x00000000
2242#define PHY_DATA_OR 0x10000000
2243#define PHY_DATA_AND 0x20000000
2244#define PHY_BJMPN 0x30000000
eee3786f 2245#define PHY_MDIO_CHG 0x40000000
bca03d5f 2246#define PHY_CLEAR_READCOUNT 0x70000000
2247#define PHY_WRITE 0x80000000
2248#define PHY_READCOUNT_EQ_SKIP 0x90000000
2249#define PHY_COMP_EQ_SKIPN 0xa0000000
2250#define PHY_COMP_NEQ_SKIPN 0xb0000000
2251#define PHY_WRITE_PREVIOUS 0xc0000000
2252#define PHY_SKIPN 0xd0000000
2253#define PHY_DELAY_MS 0xe0000000
bca03d5f 2254
960aee6c
HW		 2255struct fw_info {
2256 u32 magic;
2257 char version[RTL_VER_SIZE];
2258 __le32 fw_start;
2259 __le32 fw_len;
2260 u8 chksum;
2261} __packed;
2262
1c361efb
FR		 2263#define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2264
2265static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
bca03d5f 2266{
b6ffd97f 2267 const struct firmware *fw = rtl_fw->fw;
960aee6c 2268 struct fw_info *fw_info = (struct fw_info *)fw->data;
1c361efb
FR		 2269 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2270 char *version = rtl_fw->version;
2271 bool rc = false;
2272
2273 if (fw->size < FW_OPCODE_SIZE)
2274 goto out;
960aee6c
HW		 2275
2276 if (!fw_info->magic) {
2277 size_t i, size, start;
2278 u8 checksum = 0;
2279
2280 if (fw->size < sizeof(*fw_info))
2281 goto out;
2282
2283 for (i = 0; i < fw->size; i++)
2284 checksum += fw->data[i];
2285 if (checksum != 0)
2286 goto out;
2287
2288 start = le32_to_cpu(fw_info->fw_start);
2289 if (start > fw->size)
2290 goto out;
2291
2292 size = le32_to_cpu(fw_info->fw_len);
2293 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2294 goto out;
2295
2296 memcpy(version, fw_info->version, RTL_VER_SIZE);
2297
2298 pa->code = (__le32 *)(fw->data + start);
2299 pa->size = size;
2300 } else {
1c361efb
FR		 2301 if (fw->size % FW_OPCODE_SIZE)
2302 goto out;
2303
2304 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2305
2306 pa->code = (__le32 *)fw->data;
2307 pa->size = fw->size / FW_OPCODE_SIZE;
2308 }
2309 version[RTL_VER_SIZE - 1] = 0;
2310
2311 rc = true;
2312out:
2313 return rc;
2314}
2315
fd112f2e
FR		 2316static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2317 struct rtl_fw_phy_action *pa)
1c361efb 2318{
fd112f2e 2319 bool rc = false;
1c361efb 2320 size_t index;
bca03d5f 2321
1c361efb
FR		 2322 for (index = 0; index < pa->size; index++) {
2323 u32 action = le32_to_cpu(pa->code[index]);
42b82dc1 2324 u32 regno = (action & 0x0fff0000) >> 16;
bca03d5f 2325
42b82dc1 2326 switch(action & 0xf0000000) {
2327 case PHY_READ:
2328 case PHY_DATA_OR:
2329 case PHY_DATA_AND:
eee3786f 2330 case PHY_MDIO_CHG:
42b82dc1 2331 case PHY_CLEAR_READCOUNT:
2332 case PHY_WRITE:
2333 case PHY_WRITE_PREVIOUS:
2334 case PHY_DELAY_MS:
2335 break;
2336
2337 case PHY_BJMPN:
2338 if (regno > index) {
fd112f2e 2339 netif_err(tp, ifup, tp->dev,
cecb5fd7 2340 "Out of range of firmware\n");
fd112f2e 2341 goto out;
42b82dc1 2342 }
2343 break;
2344 case PHY_READCOUNT_EQ_SKIP:
1c361efb 2345 if (index + 2 >= pa->size) {
fd112f2e 2346 netif_err(tp, ifup, tp->dev,
cecb5fd7 2347 "Out of range of firmware\n");
fd112f2e 2348 goto out;
42b82dc1 2349 }
2350 break;
2351 case PHY_COMP_EQ_SKIPN:
2352 case PHY_COMP_NEQ_SKIPN:
2353 case PHY_SKIPN:
1c361efb 2354 if (index + 1 + regno >= pa->size) {
fd112f2e 2355 netif_err(tp, ifup, tp->dev,
cecb5fd7 2356 "Out of range of firmware\n");
fd112f2e 2357 goto out;
42b82dc1 2358 }
bca03d5f 2359 break;
2360
42b82dc1 2361 default:
fd112f2e 2362 netif_err(tp, ifup, tp->dev,
42b82dc1 2363 "Invalid action 0x%08x\n", action);
fd112f2e 2364 goto out;
bca03d5f 2365 }
2366 }
fd112f2e
FR		 2367 rc = true;
2368out:
2369 return rc;
2370}
bca03d5f 2371
fd112f2e
FR		 2372static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2373{
2374 struct net_device *dev = tp->dev;
2375 int rc = -EINVAL;
2376
2377 if (!rtl_fw_format_ok(tp, rtl_fw)) {
2378 netif_err(tp, ifup, dev, "invalid firwmare\n");
2379 goto out;
2380 }
2381
2382 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2383 rc = 0;
2384out:
2385 return rc;
2386}
2387
2388static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2389{
2390 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
eee3786f 2391 struct mdio_ops org, *ops = &tp->mdio_ops;
fd112f2e
FR		 2392 u32 predata, count;
2393 size_t index;
2394
2395 predata = count = 0;
eee3786f 2396 org.write = ops->write;
2397 org.read = ops->read;
42b82dc1 2398
1c361efb
FR		 2399 for (index = 0; index < pa->size; ) {
2400 u32 action = le32_to_cpu(pa->code[index]);
bca03d5f 2401 u32 data = action & 0x0000ffff;
42b82dc1 2402 u32 regno = (action & 0x0fff0000) >> 16;
2403
2404 if (!action)
2405 break;
bca03d5f 2406
2407 switch(action & 0xf0000000) {
42b82dc1 2408 case PHY_READ:
2409 predata = rtl_readphy(tp, regno);
2410 count++;
2411 index++;
2412 break;
2413 case PHY_DATA_OR:
2414 predata |= data;
2415 index++;
2416 break;
2417 case PHY_DATA_AND:
2418 predata &= data;
2419 index++;
2420 break;
2421 case PHY_BJMPN:
2422 index -= regno;
2423 break;
eee3786f 2424 case PHY_MDIO_CHG:
2425 if (data == 0) {
2426 ops->write = org.write;
2427 ops->read = org.read;
2428 } else if (data == 1) {
2429 ops->write = mac_mcu_write;
2430 ops->read = mac_mcu_read;
2431 }
2432
42b82dc1 2433 index++;
2434 break;
2435 case PHY_CLEAR_READCOUNT:
2436 count = 0;
2437 index++;
2438 break;
bca03d5f 2439 case PHY_WRITE:
42b82dc1 2440 rtl_writephy(tp, regno, data);
2441 index++;
2442 break;
2443 case PHY_READCOUNT_EQ_SKIP:
cecb5fd7 2444 index += (count == data) ? 2 : 1;
bca03d5f 2445 break;
42b82dc1 2446 case PHY_COMP_EQ_SKIPN:
2447 if (predata == data)
2448 index += regno;
2449 index++;
2450 break;
2451 case PHY_COMP_NEQ_SKIPN:
2452 if (predata != data)
2453 index += regno;
2454 index++;
2455 break;
2456 case PHY_WRITE_PREVIOUS:
2457 rtl_writephy(tp, regno, predata);
2458 index++;
2459 break;
2460 case PHY_SKIPN:
2461 index += regno + 1;
2462 break;
2463 case PHY_DELAY_MS:
2464 mdelay(data);
2465 index++;
2466 break;
2467
bca03d5f 2468 default:
2469 BUG();
2470 }
2471 }
eee3786f 2472
2473 ops->write = org.write;
2474 ops->read = org.read;
bca03d5f 2475}
2476
f1e02ed1 2477static void rtl_release_firmware(struct rtl8169_private *tp)
2478{
b6ffd97f
FR		 2479 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2480 release_firmware(tp->rtl_fw->fw);
2481 kfree(tp->rtl_fw);
2482 }
2483 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
f1e02ed1 2484}
2485
953a12cc 2486static void rtl_apply_firmware(struct rtl8169_private *tp)
f1e02ed1 2487{
b6ffd97f 2488 struct rtl_fw *rtl_fw = tp->rtl_fw;
f1e02ed1 2489
2490 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
eef63cc1 2491 if (!IS_ERR_OR_NULL(rtl_fw))
b6ffd97f 2492 rtl_phy_write_fw(tp, rtl_fw);
953a12cc
FR		 2493}
2494
2495static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2496{
2497 if (rtl_readphy(tp, reg) != val)
2498 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2499 else
2500 rtl_apply_firmware(tp);
f1e02ed1 2501}
2502
4da19633 2503static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1da177e4 2504{
350f7596 2505 static const struct phy_reg phy_reg_init[] = {
0b9b571d 2506 { 0x1f, 0x0001 },
2507 { 0x06, 0x006e },
2508 { 0x08, 0x0708 },
2509 { 0x15, 0x4000 },
2510 { 0x18, 0x65c7 },
1da177e4 2511
0b9b571d 2512 { 0x1f, 0x0001 },
2513 { 0x03, 0x00a1 },
2514 { 0x02, 0x0008 },
2515 { 0x01, 0x0120 },
2516 { 0x00, 0x1000 },
2517 { 0x04, 0x0800 },
2518 { 0x04, 0x0000 },
1da177e4 2519
0b9b571d 2520 { 0x03, 0xff41 },
2521 { 0x02, 0xdf60 },
2522 { 0x01, 0x0140 },
2523 { 0x00, 0x0077 },
2524 { 0x04, 0x7800 },
2525 { 0x04, 0x7000 },
2526
2527 { 0x03, 0x802f },
2528 { 0x02, 0x4f02 },
2529 { 0x01, 0x0409 },
2530 { 0x00, 0xf0f9 },
2531 { 0x04, 0x9800 },
2532 { 0x04, 0x9000 },
2533
2534 { 0x03, 0xdf01 },
2535 { 0x02, 0xdf20 },
2536 { 0x01, 0xff95 },
2537 { 0x00, 0xba00 },
2538 { 0x04, 0xa800 },
2539 { 0x04, 0xa000 },
2540
2541 { 0x03, 0xff41 },
2542 { 0x02, 0xdf20 },
2543 { 0x01, 0x0140 },
2544 { 0x00, 0x00bb },
2545 { 0x04, 0xb800 },
2546 { 0x04, 0xb000 },
2547
2548 { 0x03, 0xdf41 },
2549 { 0x02, 0xdc60 },
2550 { 0x01, 0x6340 },
2551 { 0x00, 0x007d },
2552 { 0x04, 0xd800 },
2553 { 0x04, 0xd000 },
2554
2555 { 0x03, 0xdf01 },
2556 { 0x02, 0xdf20 },
2557 { 0x01, 0x100a },
2558 { 0x00, 0xa0ff },
2559 { 0x04, 0xf800 },
2560 { 0x04, 0xf000 },
2561
2562 { 0x1f, 0x0000 },
2563 { 0x0b, 0x0000 },
2564 { 0x00, 0x9200 }
2565 };
1da177e4 2566
4da19633 2567 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1da177e4
LT		 2568}
2569
4da19633 2570static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
5615d9f1 2571{
350f7596 2572 static const struct phy_reg phy_reg_init[] = {
a441d7b6
FR		 2573 { 0x1f, 0x0002 },
2574 { 0x01, 0x90d0 },
2575 { 0x1f, 0x0000 }
2576 };
2577
4da19633 2578 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 2579}
2580
4da19633 2581static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2e955856 2582{
2583 struct pci_dev *pdev = tp->pci_dev;
2e955856 2584
ccbae55e
SS		 2585 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2586 (pdev->subsystem_device != 0xe000))
2e955856 2587 return;
2588
4da19633 2589 rtl_writephy(tp, 0x1f, 0x0001);
2590 rtl_writephy(tp, 0x10, 0xf01b);
2591 rtl_writephy(tp, 0x1f, 0x0000);
2e955856 2592}
2593
4da19633 2594static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2e955856 2595{
350f7596 2596 static const struct phy_reg phy_reg_init[] = {
2e955856 2597 { 0x1f, 0x0001 },
2598 { 0x04, 0x0000 },
2599 { 0x03, 0x00a1 },
2600 { 0x02, 0x0008 },
2601 { 0x01, 0x0120 },
2602 { 0x00, 0x1000 },
2603 { 0x04, 0x0800 },
2604 { 0x04, 0x9000 },
2605 { 0x03, 0x802f },
2606 { 0x02, 0x4f02 },
2607 { 0x01, 0x0409 },
2608 { 0x00, 0xf099 },
2609 { 0x04, 0x9800 },
2610 { 0x04, 0xa000 },
2611 { 0x03, 0xdf01 },
2612 { 0x02, 0xdf20 },
2613 { 0x01, 0xff95 },
2614 { 0x00, 0xba00 },
2615 { 0x04, 0xa800 },
2616 { 0x04, 0xf000 },
2617 { 0x03, 0xdf01 },
2618 { 0x02, 0xdf20 },
2619 { 0x01, 0x101a },
2620 { 0x00, 0xa0ff },
2621 { 0x04, 0xf800 },
2622 { 0x04, 0x0000 },
2623 { 0x1f, 0x0000 },
2624
2625 { 0x1f, 0x0001 },
2626 { 0x10, 0xf41b },
2627 { 0x14, 0xfb54 },
2628 { 0x18, 0xf5c7 },
2629 { 0x1f, 0x0000 },
2630
2631 { 0x1f, 0x0001 },
2632 { 0x17, 0x0cc0 },
2633 { 0x1f, 0x0000 }
2634 };
2635
4da19633 2636 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2e955856 2637
4da19633 2638 rtl8169scd_hw_phy_config_quirk(tp);
2e955856 2639}
2640
4da19633 2641static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
8c7006aa 2642{
350f7596 2643 static const struct phy_reg phy_reg_init[] = {
8c7006aa 2644 { 0x1f, 0x0001 },
2645 { 0x04, 0x0000 },
2646 { 0x03, 0x00a1 },
2647 { 0x02, 0x0008 },
2648 { 0x01, 0x0120 },
2649 { 0x00, 0x1000 },
2650 { 0x04, 0x0800 },
2651 { 0x04, 0x9000 },
2652 { 0x03, 0x802f },
2653 { 0x02, 0x4f02 },
2654 { 0x01, 0x0409 },
2655 { 0x00, 0xf099 },
2656 { 0x04, 0x9800 },
2657 { 0x04, 0xa000 },
2658 { 0x03, 0xdf01 },
2659 { 0x02, 0xdf20 },
2660 { 0x01, 0xff95 },
2661 { 0x00, 0xba00 },
2662 { 0x04, 0xa800 },
2663 { 0x04, 0xf000 },
2664 { 0x03, 0xdf01 },
2665 { 0x02, 0xdf20 },
2666 { 0x01, 0x101a },
2667 { 0x00, 0xa0ff },
2668 { 0x04, 0xf800 },
2669 { 0x04, 0x0000 },
2670 { 0x1f, 0x0000 },
2671
2672 { 0x1f, 0x0001 },
2673 { 0x0b, 0x8480 },
2674 { 0x1f, 0x0000 },
2675
2676 { 0x1f, 0x0001 },
2677 { 0x18, 0x67c7 },
2678 { 0x04, 0x2000 },
2679 { 0x03, 0x002f },
2680 { 0x02, 0x4360 },
2681 { 0x01, 0x0109 },
2682 { 0x00, 0x3022 },
2683 { 0x04, 0x2800 },
2684 { 0x1f, 0x0000 },
2685
2686 { 0x1f, 0x0001 },
2687 { 0x17, 0x0cc0 },
2688 { 0x1f, 0x0000 }
2689 };
2690
4da19633 2691 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
8c7006aa 2692}
2693
4da19633 2694static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
236b8082 2695{
350f7596 2696 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2697 { 0x10, 0xf41b },
2698 { 0x1f, 0x0000 }
2699 };
2700
4da19633 2701 rtl_writephy(tp, 0x1f, 0x0001);
2702 rtl_patchphy(tp, 0x16, 1 << 0);
236b8082 2703
4da19633 2704 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2705}
2706
4da19633 2707static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
236b8082 2708{
350f7596 2709 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2710 { 0x1f, 0x0001 },
2711 { 0x10, 0xf41b },
2712 { 0x1f, 0x0000 }
2713 };
2714
4da19633 2715 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2716}
2717
4da19633 2718static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2719{
350f7596 2720 static const struct phy_reg phy_reg_init[] = {
867763c1
FR		 2721 { 0x1f, 0x0000 },
2722 { 0x1d, 0x0f00 },
2723 { 0x1f, 0x0002 },
2724 { 0x0c, 0x1ec8 },
2725 { 0x1f, 0x0000 }
2726 };
2727
4da19633 2728 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
867763c1
FR		 2729}
2730
4da19633 2731static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
ef3386f0 2732{
350f7596 2733 static const struct phy_reg phy_reg_init[] = {
ef3386f0
FR		 2734 { 0x1f, 0x0001 },
2735 { 0x1d, 0x3d98 },
2736 { 0x1f, 0x0000 }
2737 };
2738
4da19633 2739 rtl_writephy(tp, 0x1f, 0x0000);
2740 rtl_patchphy(tp, 0x14, 1 << 5);
2741 rtl_patchphy(tp, 0x0d, 1 << 5);
ef3386f0 2742
4da19633 2743 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
ef3386f0
FR		 2744}
2745
4da19633 2746static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2747{
350f7596 2748 static const struct phy_reg phy_reg_init[] = {
a3f80671
FR		 2749 { 0x1f, 0x0001 },
2750 { 0x12, 0x2300 },
867763c1
FR		 2751 { 0x1f, 0x0002 },
2752 { 0x00, 0x88d4 },
2753 { 0x01, 0x82b1 },
2754 { 0x03, 0x7002 },
2755 { 0x08, 0x9e30 },
2756 { 0x09, 0x01f0 },
2757 { 0x0a, 0x5500 },
2758 { 0x0c, 0x00c8 },
2759 { 0x1f, 0x0003 },
2760 { 0x12, 0xc096 },
2761 { 0x16, 0x000a },
f50d4275
FR		 2762 { 0x1f, 0x0000 },
2763 { 0x1f, 0x0000 },
2764 { 0x09, 0x2000 },
2765 { 0x09, 0x0000 }
867763c1
FR		 2766 };
2767
4da19633 2768 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2769
4da19633 2770 rtl_patchphy(tp, 0x14, 1 << 5);
2771 rtl_patchphy(tp, 0x0d, 1 << 5);
2772 rtl_writephy(tp, 0x1f, 0x0000);
867763c1
FR		 2773}
2774
4da19633 2775static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
7da97ec9 2776{
350f7596 2777 static const struct phy_reg phy_reg_init[] = {
f50d4275 2778 { 0x1f, 0x0001 },
7da97ec9 2779 { 0x12, 0x2300 },
f50d4275
FR		 2780 { 0x03, 0x802f },
2781 { 0x02, 0x4f02 },
2782 { 0x01, 0x0409 },
2783 { 0x00, 0xf099 },
2784 { 0x04, 0x9800 },
2785 { 0x04, 0x9000 },
2786 { 0x1d, 0x3d98 },
7da97ec9
FR		 2787 { 0x1f, 0x0002 },
2788 { 0x0c, 0x7eb8 },
f50d4275
FR		 2789 { 0x06, 0x0761 },
2790 { 0x1f, 0x0003 },
2791 { 0x16, 0x0f0a },
7da97ec9
FR		 2792 { 0x1f, 0x0000 }
2793 };
2794
4da19633 2795 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2796
4da19633 2797 rtl_patchphy(tp, 0x16, 1 << 0);
2798 rtl_patchphy(tp, 0x14, 1 << 5);
2799 rtl_patchphy(tp, 0x0d, 1 << 5);
2800 rtl_writephy(tp, 0x1f, 0x0000);
7da97ec9
FR		 2801}
2802
4da19633 2803static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
197ff761 2804{
350f7596 2805 static const struct phy_reg phy_reg_init[] = {
197ff761
FR		 2806 { 0x1f, 0x0001 },
2807 { 0x12, 0x2300 },
2808 { 0x1d, 0x3d98 },
2809 { 0x1f, 0x0002 },
2810 { 0x0c, 0x7eb8 },
2811 { 0x06, 0x5461 },
2812 { 0x1f, 0x0003 },
2813 { 0x16, 0x0f0a },
2814 { 0x1f, 0x0000 }
2815 };
2816
4da19633 2817 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
197ff761 2818
4da19633 2819 rtl_patchphy(tp, 0x16, 1 << 0);
2820 rtl_patchphy(tp, 0x14, 1 << 5);
2821 rtl_patchphy(tp, 0x0d, 1 << 5);
2822 rtl_writephy(tp, 0x1f, 0x0000);
197ff761
FR		 2823}
2824
4da19633 2825static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
6fb07058 2826{
4da19633 2827 rtl8168c_3_hw_phy_config(tp);
6fb07058
FR		 2828}
2829
bca03d5f 2830static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
5b538df9 2831{
350f7596 2832 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2833 /* Channel Estimation */
5b538df9 2834 { 0x1f, 0x0001 },
daf9df6d 2835 { 0x06, 0x4064 },
2836 { 0x07, 0x2863 },
2837 { 0x08, 0x059c },
2838 { 0x09, 0x26b4 },
2839 { 0x0a, 0x6a19 },
2840 { 0x0b, 0xdcc8 },
2841 { 0x10, 0xf06d },
2842 { 0x14, 0x7f68 },
2843 { 0x18, 0x7fd9 },
2844 { 0x1c, 0xf0ff },
2845 { 0x1d, 0x3d9c },
5b538df9 2846 { 0x1f, 0x0003 },
daf9df6d 2847 { 0x12, 0xf49f },
2848 { 0x13, 0x070b },
2849 { 0x1a, 0x05ad },
bca03d5f 2850 { 0x14, 0x94c0 },
2851
2852 /*
2853 * Tx Error Issue
cecb5fd7 2854 * Enhance line driver power
bca03d5f 2855 */
5b538df9 2856 { 0x1f, 0x0002 },
daf9df6d 2857 { 0x06, 0x5561 },
2858 { 0x1f, 0x0005 },
2859 { 0x05, 0x8332 },
bca03d5f 2860 { 0x06, 0x5561 },
2861
2862 /*
2863 * Can not link to 1Gbps with bad cable
2864 * Decrease SNR threshold form 21.07dB to 19.04dB
2865 */
2866 { 0x1f, 0x0001 },
2867 { 0x17, 0x0cc0 },
daf9df6d 2868
5b538df9 2869 { 0x1f, 0x0000 },
bca03d5f 2870 { 0x0d, 0xf880 }
daf9df6d 2871 };
2872
4da19633 2873 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
daf9df6d 2874
bca03d5f 2875 /*
2876 * Rx Error Issue
2877 * Fine Tune Switching regulator parameter
2878 */
4da19633 2879 rtl_writephy(tp, 0x1f, 0x0002);
2880 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2881 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
daf9df6d 2882
fdf6fc06 2883 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
350f7596 2884 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2885 { 0x1f, 0x0002 },
2886 { 0x05, 0x669a },
2887 { 0x1f, 0x0005 },
2888 { 0x05, 0x8330 },
2889 { 0x06, 0x669a },
2890 { 0x1f, 0x0002 }
2891 };
2892 int val;
2893
4da19633 2894 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2895
4da19633 2896 val = rtl_readphy(tp, 0x0d);
daf9df6d 2897
2898 if ((val & 0x00ff) != 0x006c) {
350f7596 2899 static const u32 set[] = {
daf9df6d 2900 0x0065, 0x0066, 0x0067, 0x0068,
2901 0x0069, 0x006a, 0x006b, 0x006c
2902 };
2903 int i;
2904
4da19633 2905 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2906
2907 val &= 0xff00;
2908 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2909 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2910 }
2911 } else {
350f7596 2912 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2913 { 0x1f, 0x0002 },
2914 { 0x05, 0x6662 },
2915 { 0x1f, 0x0005 },
2916 { 0x05, 0x8330 },
2917 { 0x06, 0x6662 }
2918 };
2919
4da19633 2920 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2921 }
2922
bca03d5f 2923 /* RSET couple improve */
4da19633 2924 rtl_writephy(tp, 0x1f, 0x0002);
2925 rtl_patchphy(tp, 0x0d, 0x0300);
2926 rtl_patchphy(tp, 0x0f, 0x0010);
daf9df6d 2927
bca03d5f 2928 /* Fine tune PLL performance */
4da19633 2929 rtl_writephy(tp, 0x1f, 0x0002);
2930 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2931 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2932
4da19633 2933 rtl_writephy(tp, 0x1f, 0x0005);
2934 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2935
2936 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
bca03d5f 2937
4da19633 2938 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2939}
2940
bca03d5f 2941static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2942{
350f7596 2943 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2944 /* Channel Estimation */
daf9df6d 2945 { 0x1f, 0x0001 },
2946 { 0x06, 0x4064 },
2947 { 0x07, 0x2863 },
2948 { 0x08, 0x059c },
2949 { 0x09, 0x26b4 },
2950 { 0x0a, 0x6a19 },
2951 { 0x0b, 0xdcc8 },
2952 { 0x10, 0xf06d },
2953 { 0x14, 0x7f68 },
2954 { 0x18, 0x7fd9 },
2955 { 0x1c, 0xf0ff },
2956 { 0x1d, 0x3d9c },
2957 { 0x1f, 0x0003 },
2958 { 0x12, 0xf49f },
2959 { 0x13, 0x070b },
2960 { 0x1a, 0x05ad },
2961 { 0x14, 0x94c0 },
2962
bca03d5f 2963 /*
2964 * Tx Error Issue
cecb5fd7 2965 * Enhance line driver power
bca03d5f 2966 */
daf9df6d 2967 { 0x1f, 0x0002 },
2968 { 0x06, 0x5561 },
2969 { 0x1f, 0x0005 },
2970 { 0x05, 0x8332 },
bca03d5f 2971 { 0x06, 0x5561 },
2972
2973 /*
2974 * Can not link to 1Gbps with bad cable
2975 * Decrease SNR threshold form 21.07dB to 19.04dB
2976 */
2977 { 0x1f, 0x0001 },
2978 { 0x17, 0x0cc0 },
daf9df6d 2979
2980 { 0x1f, 0x0000 },
bca03d5f 2981 { 0x0d, 0xf880 }
5b538df9
FR		 2982 };
2983
4da19633 2984 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
5b538df9 2985
fdf6fc06 2986 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
350f7596 2987 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2988 { 0x1f, 0x0002 },
2989 { 0x05, 0x669a },
5b538df9 2990 { 0x1f, 0x0005 },
daf9df6d 2991 { 0x05, 0x8330 },
2992 { 0x06, 0x669a },
2993
2994 { 0x1f, 0x0002 }
2995 };
2996 int val;
2997
4da19633 2998 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2999
4da19633 3000 val = rtl_readphy(tp, 0x0d);
daf9df6d 3001 if ((val & 0x00ff) != 0x006c) {
b6bc7650 3002 static const u32 set[] = {
daf9df6d 3003 0x0065, 0x0066, 0x0067, 0x0068,
3004 0x0069, 0x006a, 0x006b, 0x006c
3005 };
3006 int i;
3007
4da19633 3008 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 3009
3010 val &= 0xff00;
3011 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 3012 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 3013 }
3014 } else {
350f7596 3015 static const struct phy_reg phy_reg_init[] = {
daf9df6d 3016 { 0x1f, 0x0002 },
3017 { 0x05, 0x2642 },
5b538df9 3018 { 0x1f, 0x0005 },
daf9df6d 3019 { 0x05, 0x8330 },
3020 { 0x06, 0x2642 }
5b538df9
FR		 3021 };
3022
4da19633 3023 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 3024 }
3025
bca03d5f 3026 /* Fine tune PLL performance */
4da19633 3027 rtl_writephy(tp, 0x1f, 0x0002);
3028 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
3029 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 3030
bca03d5f 3031 /* Switching regulator Slew rate */
4da19633 3032 rtl_writephy(tp, 0x1f, 0x0002);
3033 rtl_patchphy(tp, 0x0f, 0x0017);
daf9df6d 3034
4da19633 3035 rtl_writephy(tp, 0x1f, 0x0005);
3036 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 3037
3038 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
bca03d5f 3039
4da19633 3040 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 3041}
3042
4da19633 3043static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 3044{
350f7596 3045 static const struct phy_reg phy_reg_init[] = {
daf9df6d 3046 { 0x1f, 0x0002 },
3047 { 0x10, 0x0008 },
3048 { 0x0d, 0x006c },
3049
3050 { 0x1f, 0x0000 },
3051 { 0x0d, 0xf880 },
3052
3053 { 0x1f, 0x0001 },
3054 { 0x17, 0x0cc0 },
3055
3056 { 0x1f, 0x0001 },
3057 { 0x0b, 0xa4d8 },
3058 { 0x09, 0x281c },
3059 { 0x07, 0x2883 },
3060 { 0x0a, 0x6b35 },
3061 { 0x1d, 0x3da4 },
3062 { 0x1c, 0xeffd },
3063 { 0x14, 0x7f52 },
3064 { 0x18, 0x7fc6 },
3065 { 0x08, 0x0601 },
3066 { 0x06, 0x4063 },
3067 { 0x10, 0xf074 },
3068 { 0x1f, 0x0003 },
3069 { 0x13, 0x0789 },
3070 { 0x12, 0xf4bd },
3071 { 0x1a, 0x04fd },
3072 { 0x14, 0x84b0 },
3073 { 0x1f, 0x0000 },
3074 { 0x00, 0x9200 },
3075
3076 { 0x1f, 0x0005 },
3077 { 0x01, 0x0340 },
3078 { 0x1f, 0x0001 },
3079 { 0x04, 0x4000 },
3080 { 0x03, 0x1d21 },
3081 { 0x02, 0x0c32 },
3082 { 0x01, 0x0200 },
3083 { 0x00, 0x5554 },
3084 { 0x04, 0x4800 },
3085 { 0x04, 0x4000 },
3086 { 0x04, 0xf000 },
3087 { 0x03, 0xdf01 },
3088 { 0x02, 0xdf20 },
3089 { 0x01, 0x101a },
3090 { 0x00, 0xa0ff },
3091 { 0x04, 0xf800 },
3092 { 0x04, 0xf000 },
3093 { 0x1f, 0x0000 },
3094
3095 { 0x1f, 0x0007 },
3096 { 0x1e, 0x0023 },
3097 { 0x16, 0x0000 },
3098 { 0x1f, 0x0000 }
3099 };
3100
4da19633 3101 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 3102}
3103
e6de30d6 3104static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3105{
3106 static const struct phy_reg phy_reg_init[] = {
3107 { 0x1f, 0x0001 },
3108 { 0x17, 0x0cc0 },
3109
3110 { 0x1f, 0x0007 },
3111 { 0x1e, 0x002d },
3112 { 0x18, 0x0040 },
3113 { 0x1f, 0x0000 }
3114 };
3115
3116 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3117 rtl_patchphy(tp, 0x0d, 1 << 5);
3118}
3119
70090424 3120static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
01dc7fec 3121{
3122 static const struct phy_reg phy_reg_init[] = {
3123 /* Enable Delay cap */
3124 { 0x1f, 0x0005 },
3125 { 0x05, 0x8b80 },
3126 { 0x06, 0xc896 },
3127 { 0x1f, 0x0000 },
3128
3129 /* Channel estimation fine tune */
3130 { 0x1f, 0x0001 },
3131 { 0x0b, 0x6c20 },
3132 { 0x07, 0x2872 },
3133 { 0x1c, 0xefff },
3134 { 0x1f, 0x0003 },
3135 { 0x14, 0x6420 },
3136 { 0x1f, 0x0000 },
3137
3138 /* Update PFM & 10M TX idle timer */
3139 { 0x1f, 0x0007 },
3140 { 0x1e, 0x002f },
3141 { 0x15, 0x1919 },
3142 { 0x1f, 0x0000 },
3143
3144 { 0x1f, 0x0007 },
3145 { 0x1e, 0x00ac },
3146 { 0x18, 0x0006 },
3147 { 0x1f, 0x0000 }
3148 };
3149
15ecd039
FR		 3150 rtl_apply_firmware(tp);
3151
01dc7fec 3152 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3153
3154 /* DCO enable for 10M IDLE Power */
3155 rtl_writephy(tp, 0x1f, 0x0007);
3156 rtl_writephy(tp, 0x1e, 0x0023);
3157 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
3158 rtl_writephy(tp, 0x1f, 0x0000);
3159
3160 /* For impedance matching */
3161 rtl_writephy(tp, 0x1f, 0x0002);
3162 rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
cecb5fd7 3163 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3164
3165 /* PHY auto speed down */
3166 rtl_writephy(tp, 0x1f, 0x0007);
3167 rtl_writephy(tp, 0x1e, 0x002d);
3168 rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
3169 rtl_writephy(tp, 0x1f, 0x0000);
3170 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3171
3172 rtl_writephy(tp, 0x1f, 0x0005);
3173 rtl_writephy(tp, 0x05, 0x8b86);
3174 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3175 rtl_writephy(tp, 0x1f, 0x0000);
3176
3177 rtl_writephy(tp, 0x1f, 0x0005);
3178 rtl_writephy(tp, 0x05, 0x8b85);
3179 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3180 rtl_writephy(tp, 0x1f, 0x0007);
3181 rtl_writephy(tp, 0x1e, 0x0020);
3182 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
3183 rtl_writephy(tp, 0x1f, 0x0006);
3184 rtl_writephy(tp, 0x00, 0x5a00);
3185 rtl_writephy(tp, 0x1f, 0x0000);
3186 rtl_writephy(tp, 0x0d, 0x0007);
3187 rtl_writephy(tp, 0x0e, 0x003c);
3188 rtl_writephy(tp, 0x0d, 0x4007);
3189 rtl_writephy(tp, 0x0e, 0x0000);
3190 rtl_writephy(tp, 0x0d, 0x0000);
3191}
3192
9ecb9aab 3193static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3194{
3195 const u16 w[] = {
3196 addr[0] | (addr[1] << 8),
3197 addr[2] | (addr[3] << 8),
3198 addr[4] | (addr[5] << 8)
3199 };
3200 const struct exgmac_reg e[] = {
3201 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3202 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3203 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3204 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3205 };
3206
3207 rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3208}
3209
70090424
HW		 3210static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3211{
3212 static const struct phy_reg phy_reg_init[] = {
3213 /* Enable Delay cap */
3214 { 0x1f, 0x0004 },
3215 { 0x1f, 0x0007 },
3216 { 0x1e, 0x00ac },
3217 { 0x18, 0x0006 },
3218 { 0x1f, 0x0002 },
3219 { 0x1f, 0x0000 },
3220 { 0x1f, 0x0000 },
3221
3222 /* Channel estimation fine tune */
3223 { 0x1f, 0x0003 },
3224 { 0x09, 0xa20f },
3225 { 0x1f, 0x0000 },
3226 { 0x1f, 0x0000 },
3227
3228 /* Green Setting */
3229 { 0x1f, 0x0005 },
3230 { 0x05, 0x8b5b },
3231 { 0x06, 0x9222 },
3232 { 0x05, 0x8b6d },
3233 { 0x06, 0x8000 },
3234 { 0x05, 0x8b76 },
3235 { 0x06, 0x8000 },
3236 { 0x1f, 0x0000 }
3237 };
3238
3239 rtl_apply_firmware(tp);
3240
3241 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3242
3243 /* For 4-corner performance improve */
3244 rtl_writephy(tp, 0x1f, 0x0005);
3245 rtl_writephy(tp, 0x05, 0x8b80);
3246 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
3247 rtl_writephy(tp, 0x1f, 0x0000);
3248
3249 /* PHY auto speed down */
3250 rtl_writephy(tp, 0x1f, 0x0004);
3251 rtl_writephy(tp, 0x1f, 0x0007);
3252 rtl_writephy(tp, 0x1e, 0x002d);
3253 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3254 rtl_writephy(tp, 0x1f, 0x0002);
3255 rtl_writephy(tp, 0x1f, 0x0000);
3256 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3257
3258 /* improve 10M EEE waveform */
3259 rtl_writephy(tp, 0x1f, 0x0005);
3260 rtl_writephy(tp, 0x05, 0x8b86);
3261 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3262 rtl_writephy(tp, 0x1f, 0x0000);
3263
3264 /* Improve 2-pair detection performance */
3265 rtl_writephy(tp, 0x1f, 0x0005);
3266 rtl_writephy(tp, 0x05, 0x8b85);
3267 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3268 rtl_writephy(tp, 0x1f, 0x0000);
3269
3270 /* EEE setting */
fdf6fc06 3271 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, ERIAR_EXGMAC);
70090424
HW		 3272 rtl_writephy(tp, 0x1f, 0x0005);
3273 rtl_writephy(tp, 0x05, 0x8b85);
3274 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3275 rtl_writephy(tp, 0x1f, 0x0004);
3276 rtl_writephy(tp, 0x1f, 0x0007);
3277 rtl_writephy(tp, 0x1e, 0x0020);
1b23a3e3 3278 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
70090424
HW		 3279 rtl_writephy(tp, 0x1f, 0x0002);
3280 rtl_writephy(tp, 0x1f, 0x0000);
3281 rtl_writephy(tp, 0x0d, 0x0007);
3282 rtl_writephy(tp, 0x0e, 0x003c);
3283 rtl_writephy(tp, 0x0d, 0x4007);
3284 rtl_writephy(tp, 0x0e, 0x0000);
3285 rtl_writephy(tp, 0x0d, 0x0000);
3286
3287 /* Green feature */
3288 rtl_writephy(tp, 0x1f, 0x0003);
3289 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3290 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3291 rtl_writephy(tp, 0x1f, 0x0000);
e0c07557 3292
9ecb9aab 3293 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3294 rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
70090424
HW		 3295}
3296
5f886e08
HW		 3297static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3298{
3299 /* For 4-corner performance improve */
3300 rtl_writephy(tp, 0x1f, 0x0005);
3301 rtl_writephy(tp, 0x05, 0x8b80);
3302 rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3303 rtl_writephy(tp, 0x1f, 0x0000);
3304
3305 /* PHY auto speed down */
3306 rtl_writephy(tp, 0x1f, 0x0007);
3307 rtl_writephy(tp, 0x1e, 0x002d);
3308 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3309 rtl_writephy(tp, 0x1f, 0x0000);
3310 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3311
3312 /* Improve 10M EEE waveform */
3313 rtl_writephy(tp, 0x1f, 0x0005);
3314 rtl_writephy(tp, 0x05, 0x8b86);
3315 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3316 rtl_writephy(tp, 0x1f, 0x0000);
3317}
3318
c2218925
HW		 3319static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3320{
3321 static const struct phy_reg phy_reg_init[] = {
3322 /* Channel estimation fine tune */
3323 { 0x1f, 0x0003 },
3324 { 0x09, 0xa20f },
3325 { 0x1f, 0x0000 },
3326
3327 /* Modify green table for giga & fnet */
3328 { 0x1f, 0x0005 },
3329 { 0x05, 0x8b55 },
3330 { 0x06, 0x0000 },
3331 { 0x05, 0x8b5e },
3332 { 0x06, 0x0000 },
3333 { 0x05, 0x8b67 },
3334 { 0x06, 0x0000 },
3335 { 0x05, 0x8b70 },
3336 { 0x06, 0x0000 },
3337 { 0x1f, 0x0000 },
3338 { 0x1f, 0x0007 },
3339 { 0x1e, 0x0078 },
3340 { 0x17, 0x0000 },
3341 { 0x19, 0x00fb },
3342 { 0x1f, 0x0000 },
3343
3344 /* Modify green table for 10M */
3345 { 0x1f, 0x0005 },
3346 { 0x05, 0x8b79 },
3347 { 0x06, 0xaa00 },
3348 { 0x1f, 0x0000 },
3349
3350 /* Disable hiimpedance detection (RTCT) */
3351 { 0x1f, 0x0003 },
3352 { 0x01, 0x328a },
3353 { 0x1f, 0x0000 }
3354 };
3355
3356 rtl_apply_firmware(tp);
3357
3358 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3359
5f886e08 3360 rtl8168f_hw_phy_config(tp);
c2218925
HW		 3361
3362 /* Improve 2-pair detection performance */
3363 rtl_writephy(tp, 0x1f, 0x0005);
3364 rtl_writephy(tp, 0x05, 0x8b85);
3365 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3366 rtl_writephy(tp, 0x1f, 0x0000);
3367}
3368
3369static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3370{
3371 rtl_apply_firmware(tp);
3372
5f886e08 3373 rtl8168f_hw_phy_config(tp);
c2218925
HW		 3374}
3375
b3d7b2f2
HW		 3376static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3377{
b3d7b2f2
HW		 3378 static const struct phy_reg phy_reg_init[] = {
3379 /* Channel estimation fine tune */
3380 { 0x1f, 0x0003 },
3381 { 0x09, 0xa20f },
3382 { 0x1f, 0x0000 },
3383
3384 /* Modify green table for giga & fnet */
3385 { 0x1f, 0x0005 },
3386 { 0x05, 0x8b55 },
3387 { 0x06, 0x0000 },
3388 { 0x05, 0x8b5e },
3389 { 0x06, 0x0000 },
3390 { 0x05, 0x8b67 },
3391 { 0x06, 0x0000 },
3392 { 0x05, 0x8b70 },
3393 { 0x06, 0x0000 },
3394 { 0x1f, 0x0000 },
3395 { 0x1f, 0x0007 },
3396 { 0x1e, 0x0078 },
3397 { 0x17, 0x0000 },
3398 { 0x19, 0x00aa },
3399 { 0x1f, 0x0000 },
3400
3401 /* Modify green table for 10M */
3402 { 0x1f, 0x0005 },
3403 { 0x05, 0x8b79 },
3404 { 0x06, 0xaa00 },
3405 { 0x1f, 0x0000 },
3406
3407 /* Disable hiimpedance detection (RTCT) */
3408 { 0x1f, 0x0003 },
3409 { 0x01, 0x328a },
3410 { 0x1f, 0x0000 }
3411 };
3412
3413
3414 rtl_apply_firmware(tp);
3415
3416 rtl8168f_hw_phy_config(tp);
3417
3418 /* Improve 2-pair detection performance */
3419 rtl_writephy(tp, 0x1f, 0x0005);
3420 rtl_writephy(tp, 0x05, 0x8b85);
3421 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3422 rtl_writephy(tp, 0x1f, 0x0000);
3423
3424 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3425
3426 /* Modify green table for giga */
3427 rtl_writephy(tp, 0x1f, 0x0005);
3428 rtl_writephy(tp, 0x05, 0x8b54);
3429 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
3430 rtl_writephy(tp, 0x05, 0x8b5d);
3431 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
3432 rtl_writephy(tp, 0x05, 0x8a7c);
3433 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3434 rtl_writephy(tp, 0x05, 0x8a7f);
3435 rtl_w1w0_phy(tp, 0x06, 0x0100, 0x0000);
3436 rtl_writephy(tp, 0x05, 0x8a82);
3437 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3438 rtl_writephy(tp, 0x05, 0x8a85);
3439 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3440 rtl_writephy(tp, 0x05, 0x8a88);
3441 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3442 rtl_writephy(tp, 0x1f, 0x0000);
3443
3444 /* uc same-seed solution */
3445 rtl_writephy(tp, 0x1f, 0x0005);
3446 rtl_writephy(tp, 0x05, 0x8b85);
3447 rtl_w1w0_phy(tp, 0x06, 0x8000, 0x0000);
3448 rtl_writephy(tp, 0x1f, 0x0000);
3449
3450 /* eee setting */
fdf6fc06 3451 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
b3d7b2f2
HW		 3452 rtl_writephy(tp, 0x1f, 0x0005);
3453 rtl_writephy(tp, 0x05, 0x8b85);
3454 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3455 rtl_writephy(tp, 0x1f, 0x0004);
3456 rtl_writephy(tp, 0x1f, 0x0007);
3457 rtl_writephy(tp, 0x1e, 0x0020);
3458 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
3459 rtl_writephy(tp, 0x1f, 0x0000);
3460 rtl_writephy(tp, 0x0d, 0x0007);
3461 rtl_writephy(tp, 0x0e, 0x003c);
3462 rtl_writephy(tp, 0x0d, 0x4007);
3463 rtl_writephy(tp, 0x0e, 0x0000);
3464 rtl_writephy(tp, 0x0d, 0x0000);
3465
3466 /* Green feature */
3467 rtl_writephy(tp, 0x1f, 0x0003);
3468 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3469 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3470 rtl_writephy(tp, 0x1f, 0x0000);
3471}
3472
c558386b
HW		 3473static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3474{
c558386b
HW		 3475 rtl_apply_firmware(tp);
3476
41f44d13 3477 rtl_writephy(tp, 0x1f, 0x0a46);
3478 if (rtl_readphy(tp, 0x10) & 0x0100) {
3479 rtl_writephy(tp, 0x1f, 0x0bcc);
3480 rtl_w1w0_phy(tp, 0x12, 0x0000, 0x8000);
3481 } else {
3482 rtl_writephy(tp, 0x1f, 0x0bcc);
3483 rtl_w1w0_phy(tp, 0x12, 0x8000, 0x0000);
3484 }
c558386b 3485
41f44d13 3486 rtl_writephy(tp, 0x1f, 0x0a46);
3487 if (rtl_readphy(tp, 0x13) & 0x0100) {
3488 rtl_writephy(tp, 0x1f, 0x0c41);
3489 rtl_w1w0_phy(tp, 0x15, 0x0002, 0x0000);
3490 } else {
fe7524c0 3491 rtl_writephy(tp, 0x1f, 0x0c41);
3492 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0002);
41f44d13 3493 }
c558386b 3494
41f44d13 3495 /* Enable PHY auto speed down */
3496 rtl_writephy(tp, 0x1f, 0x0a44);
3497 rtl_w1w0_phy(tp, 0x11, 0x000c, 0x0000);
c558386b 3498
fe7524c0 3499 rtl_writephy(tp, 0x1f, 0x0bcc);
3500 rtl_w1w0_phy(tp, 0x14, 0x0100, 0x0000);
3501 rtl_writephy(tp, 0x1f, 0x0a44);
3502 rtl_w1w0_phy(tp, 0x11, 0x00c0, 0x0000);
3503 rtl_writephy(tp, 0x1f, 0x0a43);
3504 rtl_writephy(tp, 0x13, 0x8084);
3505 rtl_w1w0_phy(tp, 0x14, 0x0000, 0x6000);
3506 rtl_w1w0_phy(tp, 0x10, 0x1003, 0x0000);
3507
41f44d13 3508 /* EEE auto-fallback function */
3509 rtl_writephy(tp, 0x1f, 0x0a4b);
3510 rtl_w1w0_phy(tp, 0x11, 0x0004, 0x0000);
c558386b 3511
41f44d13 3512 /* Enable UC LPF tune function */
3513 rtl_writephy(tp, 0x1f, 0x0a43);
3514 rtl_writephy(tp, 0x13, 0x8012);
3515 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3516
3517 rtl_writephy(tp, 0x1f, 0x0c42);
3518 rtl_w1w0_phy(tp, 0x11, 0x4000, 0x2000);
3519
fe7524c0 3520 /* Improve SWR Efficiency */
3521 rtl_writephy(tp, 0x1f, 0x0bcd);
3522 rtl_writephy(tp, 0x14, 0x5065);
3523 rtl_writephy(tp, 0x14, 0xd065);
3524 rtl_writephy(tp, 0x1f, 0x0bc8);
3525 rtl_writephy(tp, 0x11, 0x5655);
3526 rtl_writephy(tp, 0x1f, 0x0bcd);
3527 rtl_writephy(tp, 0x14, 0x1065);
3528 rtl_writephy(tp, 0x14, 0x9065);
3529 rtl_writephy(tp, 0x14, 0x1065);
3530
1bac1072
DC		 3531 /* Check ALDPS bit, disable it if enabled */
3532 rtl_writephy(tp, 0x1f, 0x0a43);
3533 if (rtl_readphy(tp, 0x10) & 0x0004)
3534 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0004);
3535
41f44d13 3536 rtl_writephy(tp, 0x1f, 0x0000);
c558386b
HW		 3537}
3538
57538c4a 3539static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3540{
3541 rtl_apply_firmware(tp);
3542}
3543
6e1d0b89
CHL		 3544static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3545{
3546 u16 dout_tapbin;
3547 u32 data;
3548
3549 rtl_apply_firmware(tp);
3550
3551 /* CHN EST parameters adjust - giga master */
3552 rtl_writephy(tp, 0x1f, 0x0a43);
3553 rtl_writephy(tp, 0x13, 0x809b);
3554 rtl_w1w0_phy(tp, 0x14, 0x8000, 0xf800);
3555 rtl_writephy(tp, 0x13, 0x80a2);
3556 rtl_w1w0_phy(tp, 0x14, 0x8000, 0xff00);
3557 rtl_writephy(tp, 0x13, 0x80a4);
3558 rtl_w1w0_phy(tp, 0x14, 0x8500, 0xff00);
3559 rtl_writephy(tp, 0x13, 0x809c);
3560 rtl_w1w0_phy(tp, 0x14, 0xbd00, 0xff00);
3561 rtl_writephy(tp, 0x1f, 0x0000);
3562
3563 /* CHN EST parameters adjust - giga slave */
3564 rtl_writephy(tp, 0x1f, 0x0a43);
3565 rtl_writephy(tp, 0x13, 0x80ad);
3566 rtl_w1w0_phy(tp, 0x14, 0x7000, 0xf800);
3567 rtl_writephy(tp, 0x13, 0x80b4);
3568 rtl_w1w0_phy(tp, 0x14, 0x5000, 0xff00);
3569 rtl_writephy(tp, 0x13, 0x80ac);
3570 rtl_w1w0_phy(tp, 0x14, 0x4000, 0xff00);
3571 rtl_writephy(tp, 0x1f, 0x0000);
3572
3573 /* CHN EST parameters adjust - fnet */
3574 rtl_writephy(tp, 0x1f, 0x0a43);
3575 rtl_writephy(tp, 0x13, 0x808e);
3576 rtl_w1w0_phy(tp, 0x14, 0x1200, 0xff00);
3577 rtl_writephy(tp, 0x13, 0x8090);
3578 rtl_w1w0_phy(tp, 0x14, 0xe500, 0xff00);
3579 rtl_writephy(tp, 0x13, 0x8092);
3580 rtl_w1w0_phy(tp, 0x14, 0x9f00, 0xff00);
3581 rtl_writephy(tp, 0x1f, 0x0000);
3582
3583 /* enable R-tune & PGA-retune function */
3584 dout_tapbin = 0;
3585 rtl_writephy(tp, 0x1f, 0x0a46);
3586 data = rtl_readphy(tp, 0x13);
3587 data &= 3;
3588 data <<= 2;
3589 dout_tapbin |= data;
3590 data = rtl_readphy(tp, 0x12);
3591 data &= 0xc000;
3592 data >>= 14;
3593 dout_tapbin |= data;
3594 dout_tapbin = ~(dout_tapbin^0x08);
3595 dout_tapbin <<= 12;
3596 dout_tapbin &= 0xf000;
3597 rtl_writephy(tp, 0x1f, 0x0a43);
3598 rtl_writephy(tp, 0x13, 0x827a);
3599 rtl_w1w0_phy(tp, 0x14, dout_tapbin, 0xf000);
3600 rtl_writephy(tp, 0x13, 0x827b);
3601 rtl_w1w0_phy(tp, 0x14, dout_tapbin, 0xf000);
3602 rtl_writephy(tp, 0x13, 0x827c);
3603 rtl_w1w0_phy(tp, 0x14, dout_tapbin, 0xf000);
3604 rtl_writephy(tp, 0x13, 0x827d);
3605 rtl_w1w0_phy(tp, 0x14, dout_tapbin, 0xf000);
3606
3607 rtl_writephy(tp, 0x1f, 0x0a43);
3608 rtl_writephy(tp, 0x13, 0x0811);
3609 rtl_w1w0_phy(tp, 0x14, 0x0800, 0x0000);
3610 rtl_writephy(tp, 0x1f, 0x0a42);
3611 rtl_w1w0_phy(tp, 0x16, 0x0002, 0x0000);
3612 rtl_writephy(tp, 0x1f, 0x0000);
3613
3614 /* enable GPHY 10M */
3615 rtl_writephy(tp, 0x1f, 0x0a44);
3616 rtl_w1w0_phy(tp, 0x11, 0x0800, 0x0000);
3617 rtl_writephy(tp, 0x1f, 0x0000);
3618
3619 /* SAR ADC performance */
3620 rtl_writephy(tp, 0x1f, 0x0bca);
3621 rtl_w1w0_phy(tp, 0x17, 0x4000, 0x3000);
3622 rtl_writephy(tp, 0x1f, 0x0000);
3623
3624 rtl_writephy(tp, 0x1f, 0x0a43);
3625 rtl_writephy(tp, 0x13, 0x803f);
3626 rtl_w1w0_phy(tp, 0x14, 0x0000, 0x3000);
3627 rtl_writephy(tp, 0x13, 0x8047);
3628 rtl_w1w0_phy(tp, 0x14, 0x0000, 0x3000);
3629 rtl_writephy(tp, 0x13, 0x804f);
3630 rtl_w1w0_phy(tp, 0x14, 0x0000, 0x3000);
3631 rtl_writephy(tp, 0x13, 0x8057);
3632 rtl_w1w0_phy(tp, 0x14, 0x0000, 0x3000);
3633 rtl_writephy(tp, 0x13, 0x805f);
3634 rtl_w1w0_phy(tp, 0x14, 0x0000, 0x3000);
3635 rtl_writephy(tp, 0x13, 0x8067);
3636 rtl_w1w0_phy(tp, 0x14, 0x0000, 0x3000);
3637 rtl_writephy(tp, 0x13, 0x806f);
3638 rtl_w1w0_phy(tp, 0x14, 0x0000, 0x3000);
3639 rtl_writephy(tp, 0x1f, 0x0000);
3640
3641 /* disable phy pfm mode */
3642 rtl_writephy(tp, 0x1f, 0x0a44);
3643 rtl_w1w0_phy(tp, 0x14, 0x0000, 0x0080);
3644 rtl_writephy(tp, 0x1f, 0x0000);
3645
3646 /* Check ALDPS bit, disable it if enabled */
3647 rtl_writephy(tp, 0x1f, 0x0a43);
3648 if (rtl_readphy(tp, 0x10) & 0x0004)
3649 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0004);
3650
3651 rtl_writephy(tp, 0x1f, 0x0000);
3652}
3653
3654static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3655{
3656 u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3657 u16 rlen;
3658 u32 data;
3659
3660 rtl_apply_firmware(tp);
3661
3662 /* CHIN EST parameter update */
3663 rtl_writephy(tp, 0x1f, 0x0a43);
3664 rtl_writephy(tp, 0x13, 0x808a);
3665 rtl_w1w0_phy(tp, 0x14, 0x000a, 0x003f);
3666 rtl_writephy(tp, 0x1f, 0x0000);
3667
3668 /* enable R-tune & PGA-retune function */
3669 rtl_writephy(tp, 0x1f, 0x0a43);
3670 rtl_writephy(tp, 0x13, 0x0811);
3671 rtl_w1w0_phy(tp, 0x14, 0x0800, 0x0000);
3672 rtl_writephy(tp, 0x1f, 0x0a42);
3673 rtl_w1w0_phy(tp, 0x16, 0x0002, 0x0000);
3674 rtl_writephy(tp, 0x1f, 0x0000);
3675
3676 /* enable GPHY 10M */
3677 rtl_writephy(tp, 0x1f, 0x0a44);
3678 rtl_w1w0_phy(tp, 0x11, 0x0800, 0x0000);
3679 rtl_writephy(tp, 0x1f, 0x0000);
3680
3681 r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3682 data = r8168_mac_ocp_read(tp, 0xdd02);
3683 ioffset_p3 = ((data & 0x80)>>7);
3684 ioffset_p3 <<= 3;
3685
3686 data = r8168_mac_ocp_read(tp, 0xdd00);
3687 ioffset_p3 |= ((data & (0xe000))>>13);
3688 ioffset_p2 = ((data & (0x1e00))>>9);
3689 ioffset_p1 = ((data & (0x01e0))>>5);
3690 ioffset_p0 = ((data & 0x0010)>>4);
3691 ioffset_p0 <<= 3;
3692 ioffset_p0 |= (data & (0x07));
3693 data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3694
3695 if ((ioffset_p3 != 0x0F) || (ioffset_p2 != 0x0F) ||
3696 (ioffset_p1 != 0x0F) || (ioffset_p0 == 0x0F)) {
3697 rtl_writephy(tp, 0x1f, 0x0bcf);
3698 rtl_writephy(tp, 0x16, data);
3699 rtl_writephy(tp, 0x1f, 0x0000);
3700 }
3701
3702 /* Modify rlen (TX LPF corner frequency) level */
3703 rtl_writephy(tp, 0x1f, 0x0bcd);
3704 data = rtl_readphy(tp, 0x16);
3705 data &= 0x000f;
3706 rlen = 0;
3707 if (data > 3)
3708 rlen = data - 3;
3709 data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3710 rtl_writephy(tp, 0x17, data);
3711 rtl_writephy(tp, 0x1f, 0x0bcd);
3712 rtl_writephy(tp, 0x1f, 0x0000);
3713
3714 /* disable phy pfm mode */
3715 rtl_writephy(tp, 0x1f, 0x0a44);
3716 rtl_w1w0_phy(tp, 0x14, 0x0000, 0x0080);
3717 rtl_writephy(tp, 0x1f, 0x0000);
3718
3719 /* Check ALDPS bit, disable it if enabled */
3720 rtl_writephy(tp, 0x1f, 0x0a43);
3721 if (rtl_readphy(tp, 0x10) & 0x0004)
3722 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0004);
3723
3724 rtl_writephy(tp, 0x1f, 0x0000);
3725}
3726
4da19633 3727static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2857ffb7 3728{
350f7596 3729 static const struct phy_reg phy_reg_init[] = {
2857ffb7
FR		 3730 { 0x1f, 0x0003 },
3731 { 0x08, 0x441d },
3732 { 0x01, 0x9100 },
3733 { 0x1f, 0x0000 }
3734 };
3735
4da19633 3736 rtl_writephy(tp, 0x1f, 0x0000);
3737 rtl_patchphy(tp, 0x11, 1 << 12);
3738 rtl_patchphy(tp, 0x19, 1 << 13);
3739 rtl_patchphy(tp, 0x10, 1 << 15);
2857ffb7 3740
4da19633 3741 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2857ffb7
FR		 3742}
3743
5a5e4443
HW		 3744static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3745{
3746 static const struct phy_reg phy_reg_init[] = {
3747 { 0x1f, 0x0005 },
3748 { 0x1a, 0x0000 },
3749 { 0x1f, 0x0000 },
3750
3751 { 0x1f, 0x0004 },
3752 { 0x1c, 0x0000 },
3753 { 0x1f, 0x0000 },
3754
3755 { 0x1f, 0x0001 },
3756 { 0x15, 0x7701 },
3757 { 0x1f, 0x0000 }
3758 };
3759
3760 /* Disable ALDPS before ram code */
eef63cc1
FR		 3761 rtl_writephy(tp, 0x1f, 0x0000);
3762 rtl_writephy(tp, 0x18, 0x0310);
3763 msleep(100);
5a5e4443 3764
953a12cc 3765 rtl_apply_firmware(tp);
5a5e4443
HW		 3766
3767 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3768}
3769
7e18dca1
HW		 3770static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3771{
7e18dca1 3772 /* Disable ALDPS before setting firmware */
eef63cc1
FR		 3773 rtl_writephy(tp, 0x1f, 0x0000);
3774 rtl_writephy(tp, 0x18, 0x0310);
3775 msleep(20);
7e18dca1
HW		 3776
3777 rtl_apply_firmware(tp);
3778
3779 /* EEE setting */
fdf6fc06 3780 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
7e18dca1
HW		 3781 rtl_writephy(tp, 0x1f, 0x0004);
3782 rtl_writephy(tp, 0x10, 0x401f);
3783 rtl_writephy(tp, 0x19, 0x7030);
3784 rtl_writephy(tp, 0x1f, 0x0000);
3785}
3786
5598bfe5
HW		 3787static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3788{
5598bfe5
HW		 3789 static const struct phy_reg phy_reg_init[] = {
3790 { 0x1f, 0x0004 },
3791 { 0x10, 0xc07f },
3792 { 0x19, 0x7030 },
3793 { 0x1f, 0x0000 }
3794 };
3795
3796 /* Disable ALDPS before ram code */
eef63cc1
FR		 3797 rtl_writephy(tp, 0x1f, 0x0000);
3798 rtl_writephy(tp, 0x18, 0x0310);
3799 msleep(100);
5598bfe5
HW		 3800
3801 rtl_apply_firmware(tp);
3802
fdf6fc06 3803 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5598bfe5
HW		 3804 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3805
fdf6fc06 3806 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5598bfe5
HW		 3807}
3808
5615d9f1
FR		 3809static void rtl_hw_phy_config(struct net_device *dev)
3810{
3811 struct rtl8169_private *tp = netdev_priv(dev);
5615d9f1
FR		 3812
3813 rtl8169_print_mac_version(tp);
3814
3815 switch (tp->mac_version) {
3816 case RTL_GIGA_MAC_VER_01:
3817 break;
3818 case RTL_GIGA_MAC_VER_02:
3819 case RTL_GIGA_MAC_VER_03:
4da19633 3820 rtl8169s_hw_phy_config(tp);
5615d9f1
FR		 3821 break;
3822 case RTL_GIGA_MAC_VER_04:
4da19633 3823 rtl8169sb_hw_phy_config(tp);
5615d9f1 3824 break;
2e955856 3825 case RTL_GIGA_MAC_VER_05:
4da19633 3826 rtl8169scd_hw_phy_config(tp);
2e955856 3827 break;
8c7006aa 3828 case RTL_GIGA_MAC_VER_06:
4da19633 3829 rtl8169sce_hw_phy_config(tp);
8c7006aa 3830 break;
2857ffb7
FR		 3831 case RTL_GIGA_MAC_VER_07:
3832 case RTL_GIGA_MAC_VER_08:
3833 case RTL_GIGA_MAC_VER_09:
4da19633 3834 rtl8102e_hw_phy_config(tp);
2857ffb7 3835 break;
236b8082 3836 case RTL_GIGA_MAC_VER_11:
4da19633 3837 rtl8168bb_hw_phy_config(tp);
236b8082
FR		 3838 break;
3839 case RTL_GIGA_MAC_VER_12:
4da19633 3840 rtl8168bef_hw_phy_config(tp);
236b8082
FR		 3841 break;
3842 case RTL_GIGA_MAC_VER_17:
4da19633 3843 rtl8168bef_hw_phy_config(tp);
236b8082 3844 break;
867763c1 3845 case RTL_GIGA_MAC_VER_18:
4da19633 3846 rtl8168cp_1_hw_phy_config(tp);
867763c1
FR		 3847 break;
3848 case RTL_GIGA_MAC_VER_19:
4da19633 3849 rtl8168c_1_hw_phy_config(tp);
867763c1 3850 break;
7da97ec9 3851 case RTL_GIGA_MAC_VER_20:
4da19633 3852 rtl8168c_2_hw_phy_config(tp);
7da97ec9 3853 break;
197ff761 3854 case RTL_GIGA_MAC_VER_21:
4da19633 3855 rtl8168c_3_hw_phy_config(tp);
197ff761 3856 break;
6fb07058 3857 case RTL_GIGA_MAC_VER_22:
4da19633 3858 rtl8168c_4_hw_phy_config(tp);
6fb07058 3859 break;
ef3386f0 3860 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 3861 case RTL_GIGA_MAC_VER_24:
4da19633 3862 rtl8168cp_2_hw_phy_config(tp);
ef3386f0 3863 break;
5b538df9 3864 case RTL_GIGA_MAC_VER_25:
bca03d5f 3865 rtl8168d_1_hw_phy_config(tp);
daf9df6d 3866 break;
3867 case RTL_GIGA_MAC_VER_26:
bca03d5f 3868 rtl8168d_2_hw_phy_config(tp);
daf9df6d 3869 break;
3870 case RTL_GIGA_MAC_VER_27:
4da19633 3871 rtl8168d_3_hw_phy_config(tp);
5b538df9 3872 break;
e6de30d6 3873 case RTL_GIGA_MAC_VER_28:
3874 rtl8168d_4_hw_phy_config(tp);
3875 break;
5a5e4443
HW		 3876 case RTL_GIGA_MAC_VER_29:
3877 case RTL_GIGA_MAC_VER_30:
3878 rtl8105e_hw_phy_config(tp);
3879 break;
cecb5fd7
FR		 3880 case RTL_GIGA_MAC_VER_31:
3881 /* None. */
3882 break;
01dc7fec 3883 case RTL_GIGA_MAC_VER_32:
01dc7fec 3884 case RTL_GIGA_MAC_VER_33:
70090424
HW		 3885 rtl8168e_1_hw_phy_config(tp);
3886 break;
3887 case RTL_GIGA_MAC_VER_34:
3888 rtl8168e_2_hw_phy_config(tp);
01dc7fec 3889 break;
c2218925
HW		 3890 case RTL_GIGA_MAC_VER_35:
3891 rtl8168f_1_hw_phy_config(tp);
3892 break;
3893 case RTL_GIGA_MAC_VER_36:
3894 rtl8168f_2_hw_phy_config(tp);
3895 break;
ef3386f0 3896
7e18dca1
HW		 3897 case RTL_GIGA_MAC_VER_37:
3898 rtl8402_hw_phy_config(tp);
3899 break;
3900
b3d7b2f2
HW		 3901 case RTL_GIGA_MAC_VER_38:
3902 rtl8411_hw_phy_config(tp);
3903 break;
3904
5598bfe5
HW		 3905 case RTL_GIGA_MAC_VER_39:
3906 rtl8106e_hw_phy_config(tp);
3907 break;
3908
c558386b
HW		 3909 case RTL_GIGA_MAC_VER_40:
3910 rtl8168g_1_hw_phy_config(tp);
3911 break;
57538c4a 3912 case RTL_GIGA_MAC_VER_42:
58152cd4 3913 case RTL_GIGA_MAC_VER_43:
45dd95c4 3914 case RTL_GIGA_MAC_VER_44:
57538c4a 3915 rtl8168g_2_hw_phy_config(tp);
3916 break;
6e1d0b89
CHL		 3917 case RTL_GIGA_MAC_VER_45:
3918 case RTL_GIGA_MAC_VER_47:
3919 rtl8168h_1_hw_phy_config(tp);
3920 break;
3921 case RTL_GIGA_MAC_VER_46:
3922 case RTL_GIGA_MAC_VER_48:
3923 rtl8168h_2_hw_phy_config(tp);
3924 break;
c558386b
HW		 3925
3926 case RTL_GIGA_MAC_VER_41:
5615d9f1
FR		 3927 default:
3928 break;
3929 }
3930}
3931
da78dbff 3932static void rtl_phy_work(struct rtl8169_private *tp)
1da177e4 3933{
1da177e4
LT		 3934 struct timer_list *timer = &tp->timer;
3935 void __iomem *ioaddr = tp->mmio_addr;
3936 unsigned long timeout = RTL8169_PHY_TIMEOUT;
3937
bcf0bf90 3938 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 3939
4da19633 3940 if (tp->phy_reset_pending(tp)) {
5b0384f4 3941 /*
1da177e4
LT		 3942 * A busy loop could burn quite a few cycles on nowadays CPU.
3943 * Let's delay the execution of the timer for a few ticks.
3944 */
3945 timeout = HZ/10;
3946 goto out_mod_timer;
3947 }
3948
3949 if (tp->link_ok(ioaddr))
da78dbff 3950 return;
1da177e4 3951
9bb8eeb5 3952 netif_dbg(tp, link, tp->dev, "PHY reset until link up\n");
1da177e4 3953
4da19633 3954 tp->phy_reset_enable(tp);
1da177e4
LT		 3955
3956out_mod_timer:
3957 mod_timer(timer, jiffies + timeout);
da78dbff
FR		 3958}
3959
3960static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3961{
da78dbff
FR		 3962 if (!test_and_set_bit(flag, tp->wk.flags))
3963 schedule_work(&tp->wk.work);
da78dbff
FR		 3964}
3965
3966static void rtl8169_phy_timer(unsigned long __opaque)
3967{
3968 struct net_device *dev = (struct net_device *)__opaque;
3969 struct rtl8169_private *tp = netdev_priv(dev);
3970
98ddf986 3971 rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
1da177e4
LT		 3972}
3973
1da177e4
LT		 3974static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3975 void __iomem *ioaddr)
3976{
3977 iounmap(ioaddr);
3978 pci_release_regions(pdev);
87aeec76 3979 pci_clear_mwi(pdev);
1da177e4
LT		 3980 pci_disable_device(pdev);
3981 free_netdev(dev);
3982}
3983
ffc46952
FR		 3984DECLARE_RTL_COND(rtl_phy_reset_cond)
3985{
3986 return tp->phy_reset_pending(tp);
3987}
3988
bf793295
FR		 3989static void rtl8169_phy_reset(struct net_device *dev,
3990 struct rtl8169_private *tp)
3991{
4da19633 3992 tp->phy_reset_enable(tp);
ffc46952 3993 rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100);
bf793295
FR		 3994}
3995
2544bfc0
FR		 3996static bool rtl_tbi_enabled(struct rtl8169_private *tp)
3997{
3998 void __iomem *ioaddr = tp->mmio_addr;
3999
4000 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
4001 (RTL_R8(PHYstatus) & TBI_Enable);
4002}
4003
4ff96fa6
FR		 4004static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
4005{
4006 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 4007
5615d9f1 4008 rtl_hw_phy_config(dev);
4ff96fa6 4009
77332894
MS		 4010 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
4011 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4012 RTL_W8(0x82, 0x01);
4013 }
4ff96fa6 4014
6dccd16b
FR		 4015 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
4016
4017 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
4018 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 4019
bcf0bf90 4020 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 4021 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4022 RTL_W8(0x82, 0x01);
4023 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4da19633 4024 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4ff96fa6
FR		 4025 }
4026
bf793295
FR		 4027 rtl8169_phy_reset(dev, tp);
4028
54405cde 4029 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
cecb5fd7
FR		 4030 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4031 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4032 (tp->mii.supports_gmii ?
4033 ADVERTISED_1000baseT_Half |
4034 ADVERTISED_1000baseT_Full : 0));
4ff96fa6 4035
2544bfc0 4036 if (rtl_tbi_enabled(tp))
bf82c189 4037 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4ff96fa6
FR		 4038}
4039
773d2021
FR		 4040static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4041{
4042 void __iomem *ioaddr = tp->mmio_addr;
773d2021 4043
da78dbff 4044 rtl_lock_work(tp);
773d2021
FR		 4045
4046 RTL_W8(Cfg9346, Cfg9346_Unlock);
908ba2bf 4047
9ecb9aab 4048 RTL_W32(MAC4, addr[4] | addr[5] << 8);
908ba2bf 4049 RTL_R32(MAC4);
4050
9ecb9aab 4051 RTL_W32(MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
908ba2bf 4052 RTL_R32(MAC0);
4053
9ecb9aab 4054 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4055 rtl_rar_exgmac_set(tp, addr);
c28aa385 4056
773d2021
FR		 4057 RTL_W8(Cfg9346, Cfg9346_Lock);
4058
da78dbff 4059 rtl_unlock_work(tp);
773d2021
FR		 4060}
4061
4062static int rtl_set_mac_address(struct net_device *dev, void *p)
4063{
4064 struct rtl8169_private *tp = netdev_priv(dev);
4065 struct sockaddr *addr = p;
4066
4067 if (!is_valid_ether_addr(addr->sa_data))
4068 return -EADDRNOTAVAIL;
4069
4070 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
4071
4072 rtl_rar_set(tp, dev->dev_addr);
4073
4074 return 0;
4075}
4076
5f787a1a
FR		 4077static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4078{
4079 struct rtl8169_private *tp = netdev_priv(dev);
4080 struct mii_ioctl_data *data = if_mii(ifr);
4081
8b4ab28d
FR		 4082 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
4083}
5f787a1a 4084
cecb5fd7
FR		 4085static int rtl_xmii_ioctl(struct rtl8169_private *tp,
4086 struct mii_ioctl_data *data, int cmd)
8b4ab28d 4087{
5f787a1a
FR		 4088 switch (cmd) {
4089 case SIOCGMIIPHY:
4090 data->phy_id = 32; /* Internal PHY */
4091 return 0;
4092
4093 case SIOCGMIIREG:
4da19633 4094 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
5f787a1a
FR		 4095 return 0;
4096
4097 case SIOCSMIIREG:
4da19633 4098 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
5f787a1a
FR		 4099 return 0;
4100 }
4101 return -EOPNOTSUPP;
4102}
4103
8b4ab28d
FR		 4104static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
4105{
4106 return -EOPNOTSUPP;
4107}
4108
fbac58fc
FR		 4109static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
4110{
4111 if (tp->features & RTL_FEATURE_MSI) {
4112 pci_disable_msi(pdev);
4113 tp->features &= ~RTL_FEATURE_MSI;
4114 }
4115}
4116
baf63293 4117static void rtl_init_mdio_ops(struct rtl8169_private *tp)
c0e45c1c 4118{
4119 struct mdio_ops *ops = &tp->mdio_ops;
4120
4121 switch (tp->mac_version) {
4122 case RTL_GIGA_MAC_VER_27:
4123 ops->write = r8168dp_1_mdio_write;
4124 ops->read = r8168dp_1_mdio_read;
4125 break;
e6de30d6 4126 case RTL_GIGA_MAC_VER_28:
4804b3b3 4127 case RTL_GIGA_MAC_VER_31:
e6de30d6 4128 ops->write = r8168dp_2_mdio_write;
4129 ops->read = r8168dp_2_mdio_read;
4130 break;
c558386b
HW		 4131 case RTL_GIGA_MAC_VER_40:
4132 case RTL_GIGA_MAC_VER_41:
57538c4a 4133 case RTL_GIGA_MAC_VER_42:
58152cd4 4134 case RTL_GIGA_MAC_VER_43:
45dd95c4 4135 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4136 case RTL_GIGA_MAC_VER_45:
4137 case RTL_GIGA_MAC_VER_46:
4138 case RTL_GIGA_MAC_VER_47:
4139 case RTL_GIGA_MAC_VER_48:
c558386b
HW		 4140 ops->write = r8168g_mdio_write;
4141 ops->read = r8168g_mdio_read;
4142 break;
c0e45c1c 4143 default:
4144 ops->write = r8169_mdio_write;
4145 ops->read = r8169_mdio_read;
4146 break;
4147 }
4148}
4149
e2409d83 4150static void rtl_speed_down(struct rtl8169_private *tp)
4151{
4152 u32 adv;
4153 int lpa;
4154
4155 rtl_writephy(tp, 0x1f, 0x0000);
4156 lpa = rtl_readphy(tp, MII_LPA);
4157
4158 if (lpa & (LPA_10HALF | LPA_10FULL))
4159 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
4160 else if (lpa & (LPA_100HALF | LPA_100FULL))
4161 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4162 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4163 else
4164 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4165 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4166 (tp->mii.supports_gmii ?
4167 ADVERTISED_1000baseT_Half |
4168 ADVERTISED_1000baseT_Full : 0);
4169
4170 rtl8169_set_speed(tp->dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
4171 adv);
4172}
4173
649b3b8c 4174static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4175{
4176 void __iomem *ioaddr = tp->mmio_addr;
4177
4178 switch (tp->mac_version) {
b00e69de
CB		 4179 case RTL_GIGA_MAC_VER_25:
4180 case RTL_GIGA_MAC_VER_26:
649b3b8c 4181 case RTL_GIGA_MAC_VER_29:
4182 case RTL_GIGA_MAC_VER_30:
4183 case RTL_GIGA_MAC_VER_32:
4184 case RTL_GIGA_MAC_VER_33:
4185 case RTL_GIGA_MAC_VER_34:
7e18dca1 4186 case RTL_GIGA_MAC_VER_37:
b3d7b2f2 4187 case RTL_GIGA_MAC_VER_38:
5598bfe5 4188 case RTL_GIGA_MAC_VER_39:
c558386b
HW		 4189 case RTL_GIGA_MAC_VER_40:
4190 case RTL_GIGA_MAC_VER_41:
57538c4a 4191 case RTL_GIGA_MAC_VER_42:
58152cd4 4192 case RTL_GIGA_MAC_VER_43:
45dd95c4 4193 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4194 case RTL_GIGA_MAC_VER_45:
4195 case RTL_GIGA_MAC_VER_46:
4196 case RTL_GIGA_MAC_VER_47:
4197 case RTL_GIGA_MAC_VER_48:
649b3b8c 4198 RTL_W32(RxConfig, RTL_R32(RxConfig) |
4199 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4200 break;
4201 default:
4202 break;
4203 }
4204}
4205
4206static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
4207{
4208 if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
4209 return false;
4210
e2409d83 4211 rtl_speed_down(tp);
649b3b8c 4212 rtl_wol_suspend_quirk(tp);
4213
4214 return true;
4215}
4216
065c27c1 4217static void r810x_phy_power_down(struct rtl8169_private *tp)
4218{
4219 rtl_writephy(tp, 0x1f, 0x0000);
4220 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4221}
4222
4223static void r810x_phy_power_up(struct rtl8169_private *tp)
4224{
4225 rtl_writephy(tp, 0x1f, 0x0000);
4226 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4227}
4228
4229static void r810x_pll_power_down(struct rtl8169_private *tp)
4230{
0004299a
HW		 4231 void __iomem *ioaddr = tp->mmio_addr;
4232
649b3b8c 4233 if (rtl_wol_pll_power_down(tp))
065c27c1 4234 return;
065c27c1 4235
4236 r810x_phy_power_down(tp);
0004299a
HW		 4237
4238 switch (tp->mac_version) {
4239 case RTL_GIGA_MAC_VER_07:
4240 case RTL_GIGA_MAC_VER_08:
4241 case RTL_GIGA_MAC_VER_09:
4242 case RTL_GIGA_MAC_VER_10:
4243 case RTL_GIGA_MAC_VER_13:
4244 case RTL_GIGA_MAC_VER_16:
4245 break;
4246 default:
4247 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4248 break;
4249 }
065c27c1 4250}
4251
4252static void r810x_pll_power_up(struct rtl8169_private *tp)
4253{
0004299a
HW		 4254 void __iomem *ioaddr = tp->mmio_addr;
4255
065c27c1 4256 r810x_phy_power_up(tp);
0004299a
HW		 4257
4258 switch (tp->mac_version) {
4259 case RTL_GIGA_MAC_VER_07:
4260 case RTL_GIGA_MAC_VER_08:
4261 case RTL_GIGA_MAC_VER_09:
4262 case RTL_GIGA_MAC_VER_10:
4263 case RTL_GIGA_MAC_VER_13:
4264 case RTL_GIGA_MAC_VER_16:
4265 break;
6e1d0b89
CHL		 4266 case RTL_GIGA_MAC_VER_47:
4267 case RTL_GIGA_MAC_VER_48:
4268 RTL_W8(PMCH, RTL_R8(PMCH) | 0xC0);
4269 break;
0004299a
HW		 4270 default:
4271 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4272 break;
4273 }
065c27c1 4274}
4275
4276static void r8168_phy_power_up(struct rtl8169_private *tp)
4277{
4278 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 4279 switch (tp->mac_version) {
4280 case RTL_GIGA_MAC_VER_11:
4281 case RTL_GIGA_MAC_VER_12:
4282 case RTL_GIGA_MAC_VER_17:
4283 case RTL_GIGA_MAC_VER_18:
4284 case RTL_GIGA_MAC_VER_19:
4285 case RTL_GIGA_MAC_VER_20:
4286 case RTL_GIGA_MAC_VER_21:
4287 case RTL_GIGA_MAC_VER_22:
4288 case RTL_GIGA_MAC_VER_23:
4289 case RTL_GIGA_MAC_VER_24:
4290 case RTL_GIGA_MAC_VER_25:
4291 case RTL_GIGA_MAC_VER_26:
4292 case RTL_GIGA_MAC_VER_27:
4293 case RTL_GIGA_MAC_VER_28:
4294 case RTL_GIGA_MAC_VER_31:
4295 rtl_writephy(tp, 0x0e, 0x0000);
4296 break;
4297 default:
4298 break;
4299 }
065c27c1 4300 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4301}
4302
4303static void r8168_phy_power_down(struct rtl8169_private *tp)
4304{
4305 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 4306 switch (tp->mac_version) {
4307 case RTL_GIGA_MAC_VER_32:
4308 case RTL_GIGA_MAC_VER_33:
beb330a4 4309 case RTL_GIGA_MAC_VER_40:
4310 case RTL_GIGA_MAC_VER_41:
01dc7fec 4311 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
4312 break;
4313
4314 case RTL_GIGA_MAC_VER_11:
4315 case RTL_GIGA_MAC_VER_12:
4316 case RTL_GIGA_MAC_VER_17:
4317 case RTL_GIGA_MAC_VER_18:
4318 case RTL_GIGA_MAC_VER_19:
4319 case RTL_GIGA_MAC_VER_20:
4320 case RTL_GIGA_MAC_VER_21:
4321 case RTL_GIGA_MAC_VER_22:
4322 case RTL_GIGA_MAC_VER_23:
4323 case RTL_GIGA_MAC_VER_24:
4324 case RTL_GIGA_MAC_VER_25:
4325 case RTL_GIGA_MAC_VER_26:
4326 case RTL_GIGA_MAC_VER_27:
4327 case RTL_GIGA_MAC_VER_28:
4328 case RTL_GIGA_MAC_VER_31:
4329 rtl_writephy(tp, 0x0e, 0x0200);
4330 default:
4331 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4332 break;
4333 }
065c27c1 4334}
4335
4336static void r8168_pll_power_down(struct rtl8169_private *tp)
4337{
4338 void __iomem *ioaddr = tp->mmio_addr;
4339
cecb5fd7
FR		 4340 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4341 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4342 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
4804b3b3 4343 r8168dp_check_dash(tp)) {
065c27c1 4344 return;
5d2e1957 4345 }
065c27c1 4346
cecb5fd7
FR		 4347 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
4348 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
065c27c1 4349 (RTL_R16(CPlusCmd) & ASF)) {
4350 return;
4351 }
4352
01dc7fec 4353 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4354 tp->mac_version == RTL_GIGA_MAC_VER_33)
fdf6fc06 4355 rtl_ephy_write(tp, 0x19, 0xff64);
01dc7fec 4356
649b3b8c 4357 if (rtl_wol_pll_power_down(tp))
065c27c1 4358 return;
065c27c1 4359
4360 r8168_phy_power_down(tp);
4361
4362 switch (tp->mac_version) {
4363 case RTL_GIGA_MAC_VER_25:
4364 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 4365 case RTL_GIGA_MAC_VER_27:
4366 case RTL_GIGA_MAC_VER_28:
4804b3b3 4367 case RTL_GIGA_MAC_VER_31:
01dc7fec 4368 case RTL_GIGA_MAC_VER_32:
4369 case RTL_GIGA_MAC_VER_33:
6e1d0b89
CHL		 4370 case RTL_GIGA_MAC_VER_45:
4371 case RTL_GIGA_MAC_VER_46:
065c27c1 4372 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4373 break;
beb330a4 4374 case RTL_GIGA_MAC_VER_40:
4375 case RTL_GIGA_MAC_VER_41:
4376 rtl_w1w0_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
4377 0xfc000000, ERIAR_EXGMAC);
4378 break;
065c27c1 4379 }
4380}
4381
4382static void r8168_pll_power_up(struct rtl8169_private *tp)
4383{
4384 void __iomem *ioaddr = tp->mmio_addr;
4385
065c27c1 4386 switch (tp->mac_version) {
4387 case RTL_GIGA_MAC_VER_25:
4388 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 4389 case RTL_GIGA_MAC_VER_27:
4390 case RTL_GIGA_MAC_VER_28:
4804b3b3 4391 case RTL_GIGA_MAC_VER_31:
01dc7fec 4392 case RTL_GIGA_MAC_VER_32:
4393 case RTL_GIGA_MAC_VER_33:
065c27c1 4394 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4395 break;
6e1d0b89
CHL		 4396 case RTL_GIGA_MAC_VER_45:
4397 case RTL_GIGA_MAC_VER_46:
4398 RTL_W8(PMCH, RTL_R8(PMCH) | 0xC0);
4399 break;
beb330a4 4400 case RTL_GIGA_MAC_VER_40:
4401 case RTL_GIGA_MAC_VER_41:
4402 rtl_w1w0_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
4403 0x00000000, ERIAR_EXGMAC);
4404 break;
065c27c1 4405 }
4406
4407 r8168_phy_power_up(tp);
4408}
4409
d58d46b5
FR		 4410static void rtl_generic_op(struct rtl8169_private *tp,
4411 void (*op)(struct rtl8169_private *))
065c27c1 4412{
4413 if (op)
4414 op(tp);
4415}
4416
4417static void rtl_pll_power_down(struct rtl8169_private *tp)
4418{
d58d46b5 4419 rtl_generic_op(tp, tp->pll_power_ops.down);
065c27c1 4420}
4421
4422static void rtl_pll_power_up(struct rtl8169_private *tp)
4423{
d58d46b5 4424 rtl_generic_op(tp, tp->pll_power_ops.up);
065c27c1 4425}
4426
baf63293 4427static void rtl_init_pll_power_ops(struct rtl8169_private *tp)
065c27c1 4428{
4429 struct pll_power_ops *ops = &tp->pll_power_ops;
4430
4431 switch (tp->mac_version) {
4432 case RTL_GIGA_MAC_VER_07:
4433 case RTL_GIGA_MAC_VER_08:
4434 case RTL_GIGA_MAC_VER_09:
4435 case RTL_GIGA_MAC_VER_10:
4436 case RTL_GIGA_MAC_VER_16:
5a5e4443
HW		 4437 case RTL_GIGA_MAC_VER_29:
4438 case RTL_GIGA_MAC_VER_30:
7e18dca1 4439 case RTL_GIGA_MAC_VER_37:
5598bfe5 4440 case RTL_GIGA_MAC_VER_39:
58152cd4 4441 case RTL_GIGA_MAC_VER_43:
6e1d0b89
CHL		 4442 case RTL_GIGA_MAC_VER_47:
4443 case RTL_GIGA_MAC_VER_48:
065c27c1 4444 ops->down = r810x_pll_power_down;
4445 ops->up = r810x_pll_power_up;
4446 break;
4447
4448 case RTL_GIGA_MAC_VER_11:
4449 case RTL_GIGA_MAC_VER_12:
4450 case RTL_GIGA_MAC_VER_17:
4451 case RTL_GIGA_MAC_VER_18:
4452 case RTL_GIGA_MAC_VER_19:
4453 case RTL_GIGA_MAC_VER_20:
4454 case RTL_GIGA_MAC_VER_21:
4455 case RTL_GIGA_MAC_VER_22:
4456 case RTL_GIGA_MAC_VER_23:
4457 case RTL_GIGA_MAC_VER_24:
4458 case RTL_GIGA_MAC_VER_25:
4459 case RTL_GIGA_MAC_VER_26:
4460 case RTL_GIGA_MAC_VER_27:
e6de30d6 4461 case RTL_GIGA_MAC_VER_28:
4804b3b3 4462 case RTL_GIGA_MAC_VER_31:
01dc7fec 4463 case RTL_GIGA_MAC_VER_32:
4464 case RTL_GIGA_MAC_VER_33:
70090424 4465 case RTL_GIGA_MAC_VER_34:
c2218925
HW		 4466 case RTL_GIGA_MAC_VER_35:
4467 case RTL_GIGA_MAC_VER_36:
b3d7b2f2 4468 case RTL_GIGA_MAC_VER_38:
c558386b
HW		 4469 case RTL_GIGA_MAC_VER_40:
4470 case RTL_GIGA_MAC_VER_41:
57538c4a 4471 case RTL_GIGA_MAC_VER_42:
45dd95c4 4472 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4473 case RTL_GIGA_MAC_VER_45:
4474 case RTL_GIGA_MAC_VER_46:
065c27c1 4475 ops->down = r8168_pll_power_down;
4476 ops->up = r8168_pll_power_up;
4477 break;
4478
4479 default:
4480 ops->down = NULL;
4481 ops->up = NULL;
4482 break;
4483 }
4484}
4485
e542a226
HW		 4486static void rtl_init_rxcfg(struct rtl8169_private *tp)
4487{
4488 void __iomem *ioaddr = tp->mmio_addr;
4489
4490 switch (tp->mac_version) {
4491 case RTL_GIGA_MAC_VER_01:
4492 case RTL_GIGA_MAC_VER_02:
4493 case RTL_GIGA_MAC_VER_03:
4494 case RTL_GIGA_MAC_VER_04:
4495 case RTL_GIGA_MAC_VER_05:
4496 case RTL_GIGA_MAC_VER_06:
4497 case RTL_GIGA_MAC_VER_10:
4498 case RTL_GIGA_MAC_VER_11:
4499 case RTL_GIGA_MAC_VER_12:
4500 case RTL_GIGA_MAC_VER_13:
4501 case RTL_GIGA_MAC_VER_14:
4502 case RTL_GIGA_MAC_VER_15:
4503 case RTL_GIGA_MAC_VER_16:
4504 case RTL_GIGA_MAC_VER_17:
4505 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4506 break;
4507 case RTL_GIGA_MAC_VER_18:
4508 case RTL_GIGA_MAC_VER_19:
4509 case RTL_GIGA_MAC_VER_20:
4510 case RTL_GIGA_MAC_VER_21:
4511 case RTL_GIGA_MAC_VER_22:
4512 case RTL_GIGA_MAC_VER_23:
4513 case RTL_GIGA_MAC_VER_24:
eb2dc35d 4514 case RTL_GIGA_MAC_VER_34:
3ced8c95 4515 case RTL_GIGA_MAC_VER_35:
e542a226
HW		 4516 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4517 break;
beb330a4 4518 case RTL_GIGA_MAC_VER_40:
7a9810e7
MD		 4519 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
4520 break;
beb330a4 4521 case RTL_GIGA_MAC_VER_41:
57538c4a 4522 case RTL_GIGA_MAC_VER_42:
58152cd4 4523 case RTL_GIGA_MAC_VER_43:
45dd95c4 4524 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4525 case RTL_GIGA_MAC_VER_45:
4526 case RTL_GIGA_MAC_VER_46:
4527 case RTL_GIGA_MAC_VER_47:
4528 case RTL_GIGA_MAC_VER_48:
beb330a4 4529 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST | RX_EARLY_OFF);
4530 break;
e542a226
HW		 4531 default:
4532 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
4533 break;
4534 }
4535}
4536
92fc43b4
HW		 4537static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4538{
9fba0812 4539 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
92fc43b4
HW		 4540}
4541
d58d46b5
FR		 4542static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4543{
9c5028e9 4544 void __iomem *ioaddr = tp->mmio_addr;
4545
4546 RTL_W8(Cfg9346, Cfg9346_Unlock);
d58d46b5 4547 rtl_generic_op(tp, tp->jumbo_ops.enable);
9c5028e9 4548 RTL_W8(Cfg9346, Cfg9346_Lock);
d58d46b5
FR		 4549}
4550
4551static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4552{
9c5028e9 4553 void __iomem *ioaddr = tp->mmio_addr;
4554
4555 RTL_W8(Cfg9346, Cfg9346_Unlock);
d58d46b5 4556 rtl_generic_op(tp, tp->jumbo_ops.disable);
9c5028e9 4557 RTL_W8(Cfg9346, Cfg9346_Lock);
d58d46b5
FR		 4558}
4559
4560static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4561{
4562 void __iomem *ioaddr = tp->mmio_addr;
4563
4564 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4565 RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
4566 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
4567}
4568
4569static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4570{
4571 void __iomem *ioaddr = tp->mmio_addr;
4572
4573 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4574 RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
4575 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
4576}
4577
4578static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4579{
4580 void __iomem *ioaddr = tp->mmio_addr;
4581
4582 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4583}
4584
4585static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4586{
4587 void __iomem *ioaddr = tp->mmio_addr;
4588
4589 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4590}
4591
4592static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4593{
4594 void __iomem *ioaddr = tp->mmio_addr;
d58d46b5
FR		 4595
4596 RTL_W8(MaxTxPacketSize, 0x3f);
4597 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4598 RTL_W8(Config4, RTL_R8(Config4) | 0x01);
4512ff9f 4599 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
d58d46b5
FR		 4600}
4601
4602static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4603{
4604 void __iomem *ioaddr = tp->mmio_addr;
d58d46b5
FR		 4605
4606 RTL_W8(MaxTxPacketSize, 0x0c);
4607 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4608 RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
4512ff9f 4609 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
d58d46b5
FR		 4610}
4611
4612static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4613{
4614 rtl_tx_performance_tweak(tp->pci_dev,
4615 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4616}
4617
4618static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4619{
4620 rtl_tx_performance_tweak(tp->pci_dev,
4621 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4622}
4623
4624static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4625{
4626 void __iomem *ioaddr = tp->mmio_addr;
4627
4628 r8168b_0_hw_jumbo_enable(tp);
4629
4630 RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
4631}
4632
4633static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4634{
4635 void __iomem *ioaddr = tp->mmio_addr;
4636
4637 r8168b_0_hw_jumbo_disable(tp);
4638
4639 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4640}
4641
baf63293 4642static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
d58d46b5
FR		 4643{
4644 struct jumbo_ops *ops = &tp->jumbo_ops;
4645
4646 switch (tp->mac_version) {
4647 case RTL_GIGA_MAC_VER_11:
4648 ops->disable = r8168b_0_hw_jumbo_disable;
4649 ops->enable = r8168b_0_hw_jumbo_enable;
4650 break;
4651 case RTL_GIGA_MAC_VER_12:
4652 case RTL_GIGA_MAC_VER_17:
4653 ops->disable = r8168b_1_hw_jumbo_disable;
4654 ops->enable = r8168b_1_hw_jumbo_enable;
4655 break;
4656 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
4657 case RTL_GIGA_MAC_VER_19:
4658 case RTL_GIGA_MAC_VER_20:
4659 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
4660 case RTL_GIGA_MAC_VER_22:
4661 case RTL_GIGA_MAC_VER_23:
4662 case RTL_GIGA_MAC_VER_24:
4663 case RTL_GIGA_MAC_VER_25:
4664 case RTL_GIGA_MAC_VER_26:
4665 ops->disable = r8168c_hw_jumbo_disable;
4666 ops->enable = r8168c_hw_jumbo_enable;
4667 break;
4668 case RTL_GIGA_MAC_VER_27:
4669 case RTL_GIGA_MAC_VER_28:
4670 ops->disable = r8168dp_hw_jumbo_disable;
4671 ops->enable = r8168dp_hw_jumbo_enable;
4672 break;
4673 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
4674 case RTL_GIGA_MAC_VER_32:
4675 case RTL_GIGA_MAC_VER_33:
4676 case RTL_GIGA_MAC_VER_34:
4677 ops->disable = r8168e_hw_jumbo_disable;
4678 ops->enable = r8168e_hw_jumbo_enable;
4679 break;
4680
4681 /*
4682 * No action needed for jumbo frames with 8169.
4683 * No jumbo for 810x at all.
4684 */
c558386b
HW		 4685 case RTL_GIGA_MAC_VER_40:
4686 case RTL_GIGA_MAC_VER_41:
57538c4a 4687 case RTL_GIGA_MAC_VER_42:
58152cd4 4688 case RTL_GIGA_MAC_VER_43:
45dd95c4 4689 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4690 case RTL_GIGA_MAC_VER_45:
4691 case RTL_GIGA_MAC_VER_46:
4692 case RTL_GIGA_MAC_VER_47:
4693 case RTL_GIGA_MAC_VER_48:
d58d46b5
FR		 4694 default:
4695 ops->disable = NULL;
4696 ops->enable = NULL;
4697 break;
4698 }
4699}
4700
ffc46952
FR		 4701DECLARE_RTL_COND(rtl_chipcmd_cond)
4702{
4703 void __iomem *ioaddr = tp->mmio_addr;
4704
4705 return RTL_R8(ChipCmd) & CmdReset;
4706}
4707
6f43adc8
FR		 4708static void rtl_hw_reset(struct rtl8169_private *tp)
4709{
4710 void __iomem *ioaddr = tp->mmio_addr;
6f43adc8 4711
6f43adc8
FR		 4712 RTL_W8(ChipCmd, CmdReset);
4713
ffc46952 4714 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
6f43adc8
FR		 4715}
4716
b6ffd97f 4717static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
953a12cc 4718{
b6ffd97f
FR		 4719 struct rtl_fw *rtl_fw;
4720 const char *name;
4721 int rc = -ENOMEM;
953a12cc 4722
b6ffd97f
FR		 4723 name = rtl_lookup_firmware_name(tp);
4724 if (!name)
4725 goto out_no_firmware;
953a12cc 4726
b6ffd97f
FR		 4727 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4728 if (!rtl_fw)
4729 goto err_warn;
31bd204f 4730
b6ffd97f
FR		 4731 rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
4732 if (rc < 0)
4733 goto err_free;
4734
fd112f2e
FR		 4735 rc = rtl_check_firmware(tp, rtl_fw);
4736 if (rc < 0)
4737 goto err_release_firmware;
4738
b6ffd97f
FR		 4739 tp->rtl_fw = rtl_fw;
4740out:
4741 return;
4742
fd112f2e
FR		 4743err_release_firmware:
4744 release_firmware(rtl_fw->fw);
b6ffd97f
FR		 4745err_free:
4746 kfree(rtl_fw);
4747err_warn:
4748 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4749 name, rc);
4750out_no_firmware:
4751 tp->rtl_fw = NULL;
4752 goto out;
4753}
4754
4755static void rtl_request_firmware(struct rtl8169_private *tp)
4756{
4757 if (IS_ERR(tp->rtl_fw))
4758 rtl_request_uncached_firmware(tp);
953a12cc
FR		 4759}
4760
92fc43b4
HW		 4761static void rtl_rx_close(struct rtl8169_private *tp)
4762{
4763 void __iomem *ioaddr = tp->mmio_addr;
92fc43b4 4764
1687b566 4765 RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
92fc43b4
HW		 4766}
4767
ffc46952
FR		 4768DECLARE_RTL_COND(rtl_npq_cond)
4769{
4770 void __iomem *ioaddr = tp->mmio_addr;
4771
4772 return RTL_R8(TxPoll) & NPQ;
4773}
4774
4775DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4776{
4777 void __iomem *ioaddr = tp->mmio_addr;
4778
4779 return RTL_R32(TxConfig) & TXCFG_EMPTY;
4780}
4781
e6de30d6 4782static void rtl8169_hw_reset(struct rtl8169_private *tp)
1da177e4 4783{
e6de30d6 4784 void __iomem *ioaddr = tp->mmio_addr;
4785
1da177e4 4786 /* Disable interrupts */
811fd301 4787 rtl8169_irq_mask_and_ack(tp);
1da177e4 4788
92fc43b4
HW		 4789 rtl_rx_close(tp);
4790
5d2e1957 4791 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4804b3b3 4792 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4793 tp->mac_version == RTL_GIGA_MAC_VER_31) {
ffc46952 4794 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
c2218925 4795 } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
6e1d0b89
CHL		 4796 tp->mac_version == RTL_GIGA_MAC_VER_35 ||
4797 tp->mac_version == RTL_GIGA_MAC_VER_36 ||
4798 tp->mac_version == RTL_GIGA_MAC_VER_37 ||
4799 tp->mac_version == RTL_GIGA_MAC_VER_38 ||
4800 tp->mac_version == RTL_GIGA_MAC_VER_40 ||
4801 tp->mac_version == RTL_GIGA_MAC_VER_41 ||
4802 tp->mac_version == RTL_GIGA_MAC_VER_42 ||
4803 tp->mac_version == RTL_GIGA_MAC_VER_43 ||
4804 tp->mac_version == RTL_GIGA_MAC_VER_44 ||
4805 tp->mac_version == RTL_GIGA_MAC_VER_45 ||
4806 tp->mac_version == RTL_GIGA_MAC_VER_46 ||
4807 tp->mac_version == RTL_GIGA_MAC_VER_47 ||
4808 tp->mac_version == RTL_GIGA_MAC_VER_48) {
c2b0c1e7 4809 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
ffc46952 4810 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
92fc43b4
HW		 4811 } else {
4812 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4813 udelay(100);
e6de30d6 4814 }
4815
92fc43b4 4816 rtl_hw_reset(tp);
1da177e4
LT		 4817}
4818
7f796d83 4819static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 4820{
4821 void __iomem *ioaddr = tp->mmio_addr;
9cb427b6
FR		 4822
4823 /* Set DMA burst size and Interframe Gap Time */
4824 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4825 (InterFrameGap << TxInterFrameGapShift));
4826}
4827
07ce4064 4828static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 4829{
4830 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 4831
07ce4064
FR		 4832 tp->hw_start(dev);
4833
da78dbff 4834 rtl_irq_enable_all(tp);
07ce4064
FR		 4835}
4836
7f796d83
FR		 4837static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
4838 void __iomem *ioaddr)
4839{
4840 /*
4841 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4842 * register to be written before TxDescAddrLow to work.
4843 * Switching from MMIO to I/O access fixes the issue as well.
4844 */
4845 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
284901a9 4846 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
7f796d83 4847 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
284901a9 4848 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 4849}
4850
4851static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4852{
4853 u16 cmd;
4854
4855 cmd = RTL_R16(CPlusCmd);
4856 RTL_W16(CPlusCmd, cmd);
4857 return cmd;
4858}
4859
fdd7b4c3 4860static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
7f796d83
FR		 4861{
4862 /* Low hurts. Let's disable the filtering. */
207d6e87 4863 RTL_W16(RxMaxSize, rx_buf_sz + 1);
7f796d83
FR		 4864}
4865
6dccd16b
FR		 4866static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4867{
3744100e 4868 static const struct rtl_cfg2_info {
6dccd16b
FR		 4869 u32 mac_version;
4870 u32 clk;
4871 u32 val;
4872 } cfg2_info [] = {
4873 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4874 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4875 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4876 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3744100e
FR		 4877 };
4878 const struct rtl_cfg2_info *p = cfg2_info;
6dccd16b
FR		 4879 unsigned int i;
4880 u32 clk;
4881
4882 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 4883 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 4884 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4885 RTL_W32(0x7c, p->val);
4886 break;
4887 }
4888 }
4889}
4890
e6b763ea
FR		 4891static void rtl_set_rx_mode(struct net_device *dev)
4892{
4893 struct rtl8169_private *tp = netdev_priv(dev);
4894 void __iomem *ioaddr = tp->mmio_addr;
4895 u32 mc_filter[2]; /* Multicast hash filter */
4896 int rx_mode;
4897 u32 tmp = 0;
4898
4899 if (dev->flags & IFF_PROMISC) {
4900 /* Unconditionally log net taps. */
4901 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4902 rx_mode =
4903 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4904 AcceptAllPhys;
4905 mc_filter[1] = mc_filter[0] = 0xffffffff;
4906 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4907 (dev->flags & IFF_ALLMULTI)) {
4908 /* Too many to filter perfectly -- accept all multicasts. */
4909 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4910 mc_filter[1] = mc_filter[0] = 0xffffffff;
4911 } else {
4912 struct netdev_hw_addr *ha;
4913
4914 rx_mode = AcceptBroadcast | AcceptMyPhys;
4915 mc_filter[1] = mc_filter[0] = 0;
4916 netdev_for_each_mc_addr(ha, dev) {
4917 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4918 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4919 rx_mode |= AcceptMulticast;
4920 }
4921 }
4922
4923 if (dev->features & NETIF_F_RXALL)
4924 rx_mode |= (AcceptErr | AcceptRunt);
4925
4926 tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4927
4928 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4929 u32 data = mc_filter[0];
4930
4931 mc_filter[0] = swab32(mc_filter[1]);
4932 mc_filter[1] = swab32(data);
4933 }
4934
0481776b
NW		 4935 if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4936 mc_filter[1] = mc_filter[0] = 0xffffffff;
4937
e6b763ea
FR		 4938 RTL_W32(MAR0 + 4, mc_filter[1]);
4939 RTL_W32(MAR0 + 0, mc_filter[0]);
4940
4941 RTL_W32(RxConfig, tmp);
4942}
4943
07ce4064
FR		 4944static void rtl_hw_start_8169(struct net_device *dev)
4945{
4946 struct rtl8169_private *tp = netdev_priv(dev);
4947 void __iomem *ioaddr = tp->mmio_addr;
4948 struct pci_dev *pdev = tp->pci_dev;
07ce4064 4949
9cb427b6
FR		 4950 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4951 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4952 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4953 }
4954
1da177e4 4955 RTL_W8(Cfg9346, Cfg9346_Unlock);
cecb5fd7
FR		 4956 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4957 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4958 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4959 tp->mac_version == RTL_GIGA_MAC_VER_04)
9cb427b6
FR		 4960 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4961
e542a226
HW		 4962 rtl_init_rxcfg(tp);
4963
f0298f81 4964 RTL_W8(EarlyTxThres, NoEarlyTx);
1da177e4 4965
6f0333b8 4966 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
1da177e4 4967
cecb5fd7
FR		 4968 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4969 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4970 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4971 tp->mac_version == RTL_GIGA_MAC_VER_04)
c946b304 4972 rtl_set_rx_tx_config_registers(tp);
1da177e4 4973
7f796d83 4974 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 4975
cecb5fd7
FR		 4976 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4977 tp->mac_version == RTL_GIGA_MAC_VER_03) {
06fa7358 4978 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1da177e4 4979 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 4980 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 4981 }
4982
bcf0bf90
FR		 4983 RTL_W16(CPlusCmd, tp->cp_cmd);
4984
6dccd16b
FR		 4985 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4986
1da177e4
LT		 4987 /*
4988 * Undocumented corner. Supposedly:
4989 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4990 */
4991 RTL_W16(IntrMitigate, 0x0000);
4992
7f796d83 4993 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 4994
cecb5fd7
FR		 4995 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4996 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4997 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
4998 tp->mac_version != RTL_GIGA_MAC_VER_04) {
c946b304
FR		 4999 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5000 rtl_set_rx_tx_config_registers(tp);
5001 }
5002
1da177e4 5003 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 5004
5005 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
5006 RTL_R8(IntrMask);
1da177e4
LT		 5007
5008 RTL_W32(RxMissed, 0);
5009
07ce4064 5010 rtl_set_rx_mode(dev);
1da177e4
LT		 5011
5012 /* no early-rx interrupts */
5013 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
07ce4064 5014}
1da177e4 5015
beb1fe18
HW		 5016static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
5017{
5018 if (tp->csi_ops.write)
52989f0e 5019 tp->csi_ops.write(tp, addr, value);
beb1fe18
HW		 5020}
5021
5022static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
5023{
52989f0e 5024 return tp->csi_ops.read ? tp->csi_ops.read(tp, addr) : ~0;
beb1fe18
HW		 5025}
5026
5027static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits)
dacf8154
FR		 5028{
5029 u32 csi;
5030
beb1fe18
HW		 5031 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
5032 rtl_csi_write(tp, 0x070c, csi | bits);
5033}
5034
5035static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
5036{
5037 rtl_csi_access_enable(tp, 0x17000000);
650e8d5d 5038}
5039
beb1fe18 5040static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
e6de30d6 5041{
beb1fe18 5042 rtl_csi_access_enable(tp, 0x27000000);
e6de30d6 5043}
5044
ffc46952
FR		 5045DECLARE_RTL_COND(rtl_csiar_cond)
5046{
5047 void __iomem *ioaddr = tp->mmio_addr;
5048
5049 return RTL_R32(CSIAR) & CSIAR_FLAG;
5050}
5051
52989f0e 5052static void r8169_csi_write(struct rtl8169_private *tp, int addr, int value)
650e8d5d 5053{
52989f0e 5054 void __iomem *ioaddr = tp->mmio_addr;
beb1fe18
HW		 5055
5056 RTL_W32(CSIDR, value);
5057 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5058 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5059
ffc46952 5060 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
beb1fe18
HW		 5061}
5062
52989f0e 5063static u32 r8169_csi_read(struct rtl8169_private *tp, int addr)
beb1fe18 5064{
52989f0e 5065 void __iomem *ioaddr = tp->mmio_addr;
beb1fe18
HW		 5066
5067 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
5068 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5069
ffc46952
FR		 5070 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5071 RTL_R32(CSIDR) : ~0;
beb1fe18
HW		 5072}
5073
52989f0e 5074static void r8402_csi_write(struct rtl8169_private *tp, int addr, int value)
7e18dca1 5075{
52989f0e 5076 void __iomem *ioaddr = tp->mmio_addr;
7e18dca1
HW		 5077
5078 RTL_W32(CSIDR, value);
5079 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5080 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
5081 CSIAR_FUNC_NIC);
5082
ffc46952 5083 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
7e18dca1
HW		 5084}
5085
52989f0e 5086static u32 r8402_csi_read(struct rtl8169_private *tp, int addr)
7e18dca1 5087{
52989f0e 5088 void __iomem *ioaddr = tp->mmio_addr;
7e18dca1
HW		 5089
5090 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
5091 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5092
ffc46952
FR		 5093 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5094 RTL_R32(CSIDR) : ~0;
7e18dca1
HW		 5095}
5096
45dd95c4 5097static void r8411_csi_write(struct rtl8169_private *tp, int addr, int value)
5098{
5099 void __iomem *ioaddr = tp->mmio_addr;
5100
5101 RTL_W32(CSIDR, value);
5102 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5103 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
5104 CSIAR_FUNC_NIC2);
5105
5106 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5107}
5108
5109static u32 r8411_csi_read(struct rtl8169_private *tp, int addr)
5110{
5111 void __iomem *ioaddr = tp->mmio_addr;
5112
5113 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC2 |
5114 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5115
5116 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5117 RTL_R32(CSIDR) : ~0;
5118}
5119
baf63293 5120static void rtl_init_csi_ops(struct rtl8169_private *tp)
beb1fe18
HW		 5121{
5122 struct csi_ops *ops = &tp->csi_ops;
5123
5124 switch (tp->mac_version) {
5125 case RTL_GIGA_MAC_VER_01:
5126 case RTL_GIGA_MAC_VER_02:
5127 case RTL_GIGA_MAC_VER_03:
5128 case RTL_GIGA_MAC_VER_04:
5129 case RTL_GIGA_MAC_VER_05:
5130 case RTL_GIGA_MAC_VER_06:
5131 case RTL_GIGA_MAC_VER_10:
5132 case RTL_GIGA_MAC_VER_11:
5133 case RTL_GIGA_MAC_VER_12:
5134 case RTL_GIGA_MAC_VER_13:
5135 case RTL_GIGA_MAC_VER_14:
5136 case RTL_GIGA_MAC_VER_15:
5137 case RTL_GIGA_MAC_VER_16:
5138 case RTL_GIGA_MAC_VER_17:
5139 ops->write = NULL;
5140 ops->read = NULL;
5141 break;
5142
7e18dca1 5143 case RTL_GIGA_MAC_VER_37:
b3d7b2f2 5144 case RTL_GIGA_MAC_VER_38:
7e18dca1
HW		 5145 ops->write = r8402_csi_write;
5146 ops->read = r8402_csi_read;
5147 break;
5148
45dd95c4 5149 case RTL_GIGA_MAC_VER_44:
5150 ops->write = r8411_csi_write;
5151 ops->read = r8411_csi_read;
5152 break;
5153
beb1fe18
HW		 5154 default:
5155 ops->write = r8169_csi_write;
5156 ops->read = r8169_csi_read;
5157 break;
5158 }
dacf8154
FR		 5159}
5160
5161struct ephy_info {
5162 unsigned int offset;
5163 u16 mask;
5164 u16 bits;
5165};
5166
fdf6fc06
FR		 5167static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
5168 int len)
dacf8154
FR		 5169{
5170 u16 w;
5171
5172 while (len-- > 0) {
fdf6fc06
FR		 5173 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
5174 rtl_ephy_write(tp, e->offset, w);
dacf8154
FR		 5175 e++;
5176 }
5177}
5178
b726e493
FR		 5179static void rtl_disable_clock_request(struct pci_dev *pdev)
5180{
7d7903b2
JL		 5181 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
5182 PCI_EXP_LNKCTL_CLKREQ_EN);
b726e493
FR		 5183}
5184
e6de30d6 5185static void rtl_enable_clock_request(struct pci_dev *pdev)
5186{
7d7903b2
JL		 5187 pcie_capability_set_word(pdev, PCI_EXP_LNKCTL,
5188 PCI_EXP_LNKCTL_CLKREQ_EN);
e6de30d6 5189}
5190
b51ecea8 5191static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable)
5192{
5193 void __iomem *ioaddr = tp->mmio_addr;
5194 u8 data;
5195
5196 data = RTL_R8(Config3);
5197
5198 if (enable)
5199 data |= Rdy_to_L23;
5200 else
5201 data &= ~Rdy_to_L23;
5202
5203 RTL_W8(Config3, data);
5204}
5205
b726e493
FR		 5206#define R8168_CPCMD_QUIRK_MASK (\
5207 EnableBist | \
5208 Mac_dbgo_oe | \
5209 Force_half_dup | \
5210 Force_rxflow_en | \
5211 Force_txflow_en | \
5212 Cxpl_dbg_sel | \
5213 ASF | \
5214 PktCntrDisable | \
5215 Mac_dbgo_sel)
5216
beb1fe18 5217static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
219a1e9d 5218{
beb1fe18
HW		 5219 void __iomem *ioaddr = tp->mmio_addr;
5220 struct pci_dev *pdev = tp->pci_dev;
5221
b726e493
FR		 5222 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5223
5224 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5225
faf1e785 5226 if (tp->dev->mtu <= ETH_DATA_LEN) {
5227 rtl_tx_performance_tweak(pdev, (0x5 << MAX_READ_REQUEST_SHIFT) |
5228 PCI_EXP_DEVCTL_NOSNOOP_EN);
5229 }
219a1e9d
FR		 5230}
5231
beb1fe18 5232static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
219a1e9d 5233{
beb1fe18
HW		 5234 void __iomem *ioaddr = tp->mmio_addr;
5235
5236 rtl_hw_start_8168bb(tp);
b726e493 5237
f0298f81 5238 RTL_W8(MaxTxPacketSize, TxPacketMax);
b726e493
FR		 5239
5240 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
219a1e9d
FR		 5241}
5242
beb1fe18 5243static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
219a1e9d 5244{
beb1fe18
HW		 5245 void __iomem *ioaddr = tp->mmio_addr;
5246 struct pci_dev *pdev = tp->pci_dev;
5247
b726e493
FR		 5248 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
5249
5250 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5251
faf1e785 5252 if (tp->dev->mtu <= ETH_DATA_LEN)
5253 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
b726e493
FR		 5254
5255 rtl_disable_clock_request(pdev);
5256
5257 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
219a1e9d
FR		 5258}
5259
beb1fe18 5260static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
219a1e9d 5261{
350f7596 5262 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 5263 { 0x01, 0, 0x0001 },
5264 { 0x02, 0x0800, 0x1000 },
5265 { 0x03, 0, 0x0042 },
5266 { 0x06, 0x0080, 0x0000 },
5267 { 0x07, 0, 0x2000 }
5268 };
5269
beb1fe18 5270 rtl_csi_access_enable_2(tp);
b726e493 5271
fdf6fc06 5272 rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
b726e493 5273
beb1fe18 5274 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 5275}
5276
beb1fe18 5277static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
ef3386f0 5278{
beb1fe18
HW		 5279 void __iomem *ioaddr = tp->mmio_addr;
5280 struct pci_dev *pdev = tp->pci_dev;
5281
5282 rtl_csi_access_enable_2(tp);
ef3386f0
FR		 5283
5284 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5285
faf1e785 5286 if (tp->dev->mtu <= ETH_DATA_LEN)
5287 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
ef3386f0
FR		 5288
5289 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5290}
5291
beb1fe18 5292static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
7f3e3d3a 5293{
beb1fe18
HW		 5294 void __iomem *ioaddr = tp->mmio_addr;
5295 struct pci_dev *pdev = tp->pci_dev;
5296
5297 rtl_csi_access_enable_2(tp);
7f3e3d3a
FR		 5298
5299 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5300
5301 /* Magic. */
5302 RTL_W8(DBG_REG, 0x20);
5303
f0298f81 5304 RTL_W8(MaxTxPacketSize, TxPacketMax);
7f3e3d3a 5305
faf1e785 5306 if (tp->dev->mtu <= ETH_DATA_LEN)
5307 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
7f3e3d3a
FR		 5308
5309 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5310}
5311
beb1fe18 5312static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
219a1e9d 5313{
beb1fe18 5314 void __iomem *ioaddr = tp->mmio_addr;
350f7596 5315 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 5316 { 0x02, 0x0800, 0x1000 },
5317 { 0x03, 0, 0x0002 },
5318 { 0x06, 0x0080, 0x0000 }
5319 };
5320
beb1fe18 5321 rtl_csi_access_enable_2(tp);
b726e493
FR		 5322
5323 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
5324
fdf6fc06 5325 rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
b726e493 5326
beb1fe18 5327 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 5328}
5329
beb1fe18 5330static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
219a1e9d 5331{
350f7596 5332 static const struct ephy_info e_info_8168c_2[] = {
b726e493
FR		 5333 { 0x01, 0, 0x0001 },
5334 { 0x03, 0x0400, 0x0220 }
5335 };
5336
beb1fe18 5337 rtl_csi_access_enable_2(tp);
b726e493 5338
fdf6fc06 5339 rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
b726e493 5340
beb1fe18 5341 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 5342}
5343
beb1fe18 5344static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
197ff761 5345{
beb1fe18 5346 rtl_hw_start_8168c_2(tp);
197ff761
FR		 5347}
5348
beb1fe18 5349static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
6fb07058 5350{
beb1fe18 5351 rtl_csi_access_enable_2(tp);
6fb07058 5352
beb1fe18 5353 __rtl_hw_start_8168cp(tp);
6fb07058
FR		 5354}
5355
beb1fe18 5356static void rtl_hw_start_8168d(struct rtl8169_private *tp)
5b538df9 5357{
beb1fe18
HW		 5358 void __iomem *ioaddr = tp->mmio_addr;
5359 struct pci_dev *pdev = tp->pci_dev;
5360
5361 rtl_csi_access_enable_2(tp);
5b538df9
FR		 5362
5363 rtl_disable_clock_request(pdev);
5364
f0298f81 5365 RTL_W8(MaxTxPacketSize, TxPacketMax);
5b538df9 5366
faf1e785 5367 if (tp->dev->mtu <= ETH_DATA_LEN)
5368 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5b538df9
FR		 5369
5370 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5371}
5372
beb1fe18 5373static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4804b3b3 5374{
beb1fe18
HW		 5375 void __iomem *ioaddr = tp->mmio_addr;
5376 struct pci_dev *pdev = tp->pci_dev;
5377
5378 rtl_csi_access_enable_1(tp);
4804b3b3 5379
faf1e785 5380 if (tp->dev->mtu <= ETH_DATA_LEN)
5381 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4804b3b3 5382
5383 RTL_W8(MaxTxPacketSize, TxPacketMax);
5384
5385 rtl_disable_clock_request(pdev);
5386}
5387
beb1fe18 5388static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
e6de30d6 5389{
beb1fe18
HW		 5390 void __iomem *ioaddr = tp->mmio_addr;
5391 struct pci_dev *pdev = tp->pci_dev;
e6de30d6 5392 static const struct ephy_info e_info_8168d_4[] = {
5393 { 0x0b, ~0, 0x48 },
5394 { 0x19, 0x20, 0x50 },
5395 { 0x0c, ~0, 0x20 }
5396 };
5397 int i;
5398
beb1fe18 5399 rtl_csi_access_enable_1(tp);
e6de30d6 5400
5401 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5402
5403 RTL_W8(MaxTxPacketSize, TxPacketMax);
5404
5405 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
5406 const struct ephy_info *e = e_info_8168d_4 + i;
5407 u16 w;
5408
fdf6fc06
FR		 5409 w = rtl_ephy_read(tp, e->offset);
5410 rtl_ephy_write(tp, 0x03, (w & e->mask) | e->bits);
e6de30d6 5411 }
5412
5413 rtl_enable_clock_request(pdev);
5414}
5415
beb1fe18 5416static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
01dc7fec 5417{
beb1fe18
HW		 5418 void __iomem *ioaddr = tp->mmio_addr;
5419 struct pci_dev *pdev = tp->pci_dev;
70090424 5420 static const struct ephy_info e_info_8168e_1[] = {
01dc7fec 5421 { 0x00, 0x0200, 0x0100 },
5422 { 0x00, 0x0000, 0x0004 },
5423 { 0x06, 0x0002, 0x0001 },
5424 { 0x06, 0x0000, 0x0030 },
5425 { 0x07, 0x0000, 0x2000 },
5426 { 0x00, 0x0000, 0x0020 },
5427 { 0x03, 0x5800, 0x2000 },
5428 { 0x03, 0x0000, 0x0001 },
5429 { 0x01, 0x0800, 0x1000 },
5430 { 0x07, 0x0000, 0x4000 },
5431 { 0x1e, 0x0000, 0x2000 },
5432 { 0x19, 0xffff, 0xfe6c },
5433 { 0x0a, 0x0000, 0x0040 }
5434 };
5435
beb1fe18 5436 rtl_csi_access_enable_2(tp);
01dc7fec 5437
fdf6fc06 5438 rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
01dc7fec 5439
faf1e785 5440 if (tp->dev->mtu <= ETH_DATA_LEN)
5441 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
01dc7fec 5442
5443 RTL_W8(MaxTxPacketSize, TxPacketMax);
5444
5445 rtl_disable_clock_request(pdev);
5446
5447 /* Reset tx FIFO pointer */
cecb5fd7
FR		 5448 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
5449 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
01dc7fec 5450
cecb5fd7 5451 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
01dc7fec 5452}
5453
beb1fe18 5454static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
70090424 5455{
beb1fe18
HW		 5456 void __iomem *ioaddr = tp->mmio_addr;
5457 struct pci_dev *pdev = tp->pci_dev;
70090424
HW		 5458 static const struct ephy_info e_info_8168e_2[] = {
5459 { 0x09, 0x0000, 0x0080 },
5460 { 0x19, 0x0000, 0x0224 }
5461 };
5462
beb1fe18 5463 rtl_csi_access_enable_1(tp);
70090424 5464
fdf6fc06 5465 rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
70090424 5466
faf1e785 5467 if (tp->dev->mtu <= ETH_DATA_LEN)
5468 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
70090424 5469
fdf6fc06
FR		 5470 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5471 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5472 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5473 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5474 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5475 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
5476 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5477 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
70090424 5478
3090bd9a 5479 RTL_W8(MaxTxPacketSize, EarlySize);
70090424 5480
4521e1a9
FR		 5481 rtl_disable_clock_request(pdev);
5482
70090424
HW		 5483 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5484 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5485
5486 /* Adjust EEE LED frequency */
5487 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5488
5489 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5490 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4521e1a9 5491 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
70090424
HW		 5492}
5493
5f886e08 5494static void rtl_hw_start_8168f(struct rtl8169_private *tp)
c2218925 5495{
beb1fe18
HW		 5496 void __iomem *ioaddr = tp->mmio_addr;
5497 struct pci_dev *pdev = tp->pci_dev;
c2218925 5498
5f886e08 5499 rtl_csi_access_enable_2(tp);
c2218925
HW		 5500
5501 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5502
fdf6fc06
FR		 5503 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5504 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5505 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5506 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5507 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5508 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5509 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5510 rtl_w1w0_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5511 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5512 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
c2218925
HW		 5513
5514 RTL_W8(MaxTxPacketSize, EarlySize);
5515
4521e1a9
FR		 5516 rtl_disable_clock_request(pdev);
5517
c2218925
HW		 5518 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5519 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
c2218925 5520 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4521e1a9
FR		 5521 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5522 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
c2218925
HW		 5523}
5524
5f886e08
HW		 5525static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5526{
5527 void __iomem *ioaddr = tp->mmio_addr;
5528 static const struct ephy_info e_info_8168f_1[] = {
5529 { 0x06, 0x00c0, 0x0020 },
5530 { 0x08, 0x0001, 0x0002 },
5531 { 0x09, 0x0000, 0x0080 },
5532 { 0x19, 0x0000, 0x0224 }
5533 };
5534
5535 rtl_hw_start_8168f(tp);
5536
fdf6fc06 5537 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5f886e08 5538
fdf6fc06 5539 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5f886e08
HW		 5540
5541 /* Adjust EEE LED frequency */
5542 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5543}
5544
b3d7b2f2
HW		 5545static void rtl_hw_start_8411(struct rtl8169_private *tp)
5546{
b3d7b2f2
HW		 5547 static const struct ephy_info e_info_8168f_1[] = {
5548 { 0x06, 0x00c0, 0x0020 },
5549 { 0x0f, 0xffff, 0x5200 },
5550 { 0x1e, 0x0000, 0x4000 },
5551 { 0x19, 0x0000, 0x0224 }
5552 };
5553
5554 rtl_hw_start_8168f(tp);
b51ecea8 5555 rtl_pcie_state_l2l3_enable(tp, false);
b3d7b2f2 5556
fdf6fc06 5557 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
b3d7b2f2 5558
fdf6fc06 5559 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
b3d7b2f2
HW		 5560}
5561
c558386b
HW		 5562static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5563{
5564 void __iomem *ioaddr = tp->mmio_addr;
5565 struct pci_dev *pdev = tp->pci_dev;
5566
beb330a4 5567 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5568
c558386b
HW		 5569 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
5570 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5571 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5572 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5573
5574 rtl_csi_access_enable_1(tp);
5575
5576 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5577
5578 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5579 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
beb330a4 5580 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
c558386b
HW		 5581
5582 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4521e1a9 5583 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
c558386b
HW		 5584 RTL_W8(MaxTxPacketSize, EarlySize);
5585
5586 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5587 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5588
5589 /* Adjust EEE LED frequency */
5590 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5591
beb330a4 5592 rtl_w1w0_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5593 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
b51ecea8 5594
5595 rtl_pcie_state_l2l3_enable(tp, false);
c558386b
HW		 5596}
5597
57538c4a 5598static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
5599{
5600 void __iomem *ioaddr = tp->mmio_addr;
5601 static const struct ephy_info e_info_8168g_2[] = {
5602 { 0x00, 0x0000, 0x0008 },
5603 { 0x0c, 0x3df0, 0x0200 },
5604 { 0x19, 0xffff, 0xfc00 },
5605 { 0x1e, 0xffff, 0x20eb }
5606 };
5607
5608 rtl_hw_start_8168g_1(tp);
5609
5610 /* disable aspm and clock request before access ephy */
5611 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
5612 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
5613 rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
5614}
5615
45dd95c4 5616static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
5617{
5618 void __iomem *ioaddr = tp->mmio_addr;
5619 static const struct ephy_info e_info_8411_2[] = {
5620 { 0x00, 0x0000, 0x0008 },
5621 { 0x0c, 0x3df0, 0x0200 },
5622 { 0x0f, 0xffff, 0x5200 },
5623 { 0x19, 0x0020, 0x0000 },
5624 { 0x1e, 0x0000, 0x2000 }
5625 };
5626
5627 rtl_hw_start_8168g_1(tp);
5628
5629 /* disable aspm and clock request before access ephy */
5630 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
5631 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
5632 rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
5633}
5634
6e1d0b89
CHL		 5635static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
5636{
5637 void __iomem *ioaddr = tp->mmio_addr;
5638 struct pci_dev *pdev = tp->pci_dev;
5639 u16 rg_saw_cnt;
5640 u32 data;
5641 static const struct ephy_info e_info_8168h_1[] = {
5642 { 0x1e, 0x0800, 0x0001 },
5643 { 0x1d, 0x0000, 0x0800 },
5644 { 0x05, 0xffff, 0x2089 },
5645 { 0x06, 0xffff, 0x5881 },
5646 { 0x04, 0xffff, 0x154a },
5647 { 0x01, 0xffff, 0x068b }
5648 };
5649
5650 /* disable aspm and clock request before access ephy */
5651 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
5652 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
5653 rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));
5654
5655 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5656
5657 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
5658 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5659 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5660 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5661
5662 rtl_csi_access_enable_1(tp);
5663
5664 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5665
5666 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5667 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5668
5669 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);
5670
5671 rtl_w1w0_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);
5672
5673 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
5674
5675 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5676 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
5677 RTL_W8(MaxTxPacketSize, EarlySize);
5678
5679 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5680 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5681
5682 /* Adjust EEE LED frequency */
5683 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5684
5685 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
5686 RTL_W8(DLLPR, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
5687
5688 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~TX_10M_PS_EN);
5689
5690 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
5691
5692 rtl_pcie_state_l2l3_enable(tp, false);
5693
5694 rtl_writephy(tp, 0x1f, 0x0c42);
5695 rg_saw_cnt = rtl_readphy(tp, 0x13);
5696 rtl_writephy(tp, 0x1f, 0x0000);
5697 if (rg_saw_cnt > 0) {
5698 u16 sw_cnt_1ms_ini;
5699
5700 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
5701 sw_cnt_1ms_ini &= 0x0fff;
5702 data = r8168_mac_ocp_read(tp, 0xd412);
5703 data &= 0x0fff;
5704 data |= sw_cnt_1ms_ini;
5705 r8168_mac_ocp_write(tp, 0xd412, data);
5706 }
5707
5708 data = r8168_mac_ocp_read(tp, 0xe056);
5709 data &= 0xf0;
5710 data |= 0x07;
5711 r8168_mac_ocp_write(tp, 0xe056, data);
5712
5713 data = r8168_mac_ocp_read(tp, 0xe052);
5714 data &= 0x8008;
5715 data |= 0x6000;
5716 r8168_mac_ocp_write(tp, 0xe052, data);
5717
5718 data = r8168_mac_ocp_read(tp, 0xe0d6);
5719 data &= 0x01ff;
5720 data |= 0x017f;
5721 r8168_mac_ocp_write(tp, 0xe0d6, data);
5722
5723 data = r8168_mac_ocp_read(tp, 0xd420);
5724 data &= 0x0fff;
5725 data |= 0x047f;
5726 r8168_mac_ocp_write(tp, 0xd420, data);
5727
5728 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
5729 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
5730 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
5731 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
5732}
5733
07ce4064
FR		 5734static void rtl_hw_start_8168(struct net_device *dev)
5735{
2dd99530
FR		 5736 struct rtl8169_private *tp = netdev_priv(dev);
5737 void __iomem *ioaddr = tp->mmio_addr;
5738
5739 RTL_W8(Cfg9346, Cfg9346_Unlock);
5740
f0298f81 5741 RTL_W8(MaxTxPacketSize, TxPacketMax);
2dd99530 5742
6f0333b8 5743 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
2dd99530 5744
0e485150 5745 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 5746
5747 RTL_W16(CPlusCmd, tp->cp_cmd);
5748
0e485150 5749 RTL_W16(IntrMitigate, 0x5151);
2dd99530 5750
0e485150 5751 /* Work around for RxFIFO overflow. */
811fd301 5752 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
da78dbff
FR		 5753 tp->event_slow |= RxFIFOOver | PCSTimeout;
5754 tp->event_slow &= ~RxOverflow;
0e485150
FR		 5755 }
5756
5757 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530 5758
1a964649 5759 rtl_set_rx_tx_config_registers(tp);
2dd99530
FR		 5760
5761 RTL_R8(IntrMask);
5762
219a1e9d
FR		 5763 switch (tp->mac_version) {
5764 case RTL_GIGA_MAC_VER_11:
beb1fe18 5765 rtl_hw_start_8168bb(tp);
4804b3b3 5766 break;
219a1e9d
FR		 5767
5768 case RTL_GIGA_MAC_VER_12:
5769 case RTL_GIGA_MAC_VER_17:
beb1fe18 5770 rtl_hw_start_8168bef(tp);
4804b3b3 5771 break;
219a1e9d
FR		 5772
5773 case RTL_GIGA_MAC_VER_18:
beb1fe18 5774 rtl_hw_start_8168cp_1(tp);
4804b3b3 5775 break;
219a1e9d
FR		 5776
5777 case RTL_GIGA_MAC_VER_19:
beb1fe18 5778 rtl_hw_start_8168c_1(tp);
4804b3b3 5779 break;
219a1e9d
FR		 5780
5781 case RTL_GIGA_MAC_VER_20:
beb1fe18 5782 rtl_hw_start_8168c_2(tp);
4804b3b3 5783 break;
219a1e9d 5784
197ff761 5785 case RTL_GIGA_MAC_VER_21:
beb1fe18 5786 rtl_hw_start_8168c_3(tp);
4804b3b3 5787 break;
197ff761 5788
6fb07058 5789 case RTL_GIGA_MAC_VER_22:
beb1fe18 5790 rtl_hw_start_8168c_4(tp);
4804b3b3 5791 break;
6fb07058 5792
ef3386f0 5793 case RTL_GIGA_MAC_VER_23:
beb1fe18 5794 rtl_hw_start_8168cp_2(tp);
4804b3b3 5795 break;
ef3386f0 5796
7f3e3d3a 5797 case RTL_GIGA_MAC_VER_24:
beb1fe18 5798 rtl_hw_start_8168cp_3(tp);
4804b3b3 5799 break;
7f3e3d3a 5800
5b538df9 5801 case RTL_GIGA_MAC_VER_25:
daf9df6d 5802 case RTL_GIGA_MAC_VER_26:
5803 case RTL_GIGA_MAC_VER_27:
beb1fe18 5804 rtl_hw_start_8168d(tp);
4804b3b3 5805 break;
5b538df9 5806
e6de30d6 5807 case RTL_GIGA_MAC_VER_28:
beb1fe18 5808 rtl_hw_start_8168d_4(tp);
4804b3b3 5809 break;
cecb5fd7 5810
4804b3b3 5811 case RTL_GIGA_MAC_VER_31:
beb1fe18 5812 rtl_hw_start_8168dp(tp);
4804b3b3 5813 break;
5814
01dc7fec 5815 case RTL_GIGA_MAC_VER_32:
5816 case RTL_GIGA_MAC_VER_33:
beb1fe18 5817 rtl_hw_start_8168e_1(tp);
70090424
HW		 5818 break;
5819 case RTL_GIGA_MAC_VER_34:
beb1fe18 5820 rtl_hw_start_8168e_2(tp);
01dc7fec 5821 break;
e6de30d6 5822
c2218925
HW		 5823 case RTL_GIGA_MAC_VER_35:
5824 case RTL_GIGA_MAC_VER_36:
beb1fe18 5825 rtl_hw_start_8168f_1(tp);
c2218925
HW		 5826 break;
5827
b3d7b2f2
HW		 5828 case RTL_GIGA_MAC_VER_38:
5829 rtl_hw_start_8411(tp);
5830 break;
5831
c558386b
HW		 5832 case RTL_GIGA_MAC_VER_40:
5833 case RTL_GIGA_MAC_VER_41:
5834 rtl_hw_start_8168g_1(tp);
5835 break;
57538c4a 5836 case RTL_GIGA_MAC_VER_42:
5837 rtl_hw_start_8168g_2(tp);
5838 break;
c558386b 5839
45dd95c4 5840 case RTL_GIGA_MAC_VER_44:
5841 rtl_hw_start_8411_2(tp);
5842 break;
5843
6e1d0b89
CHL		 5844 case RTL_GIGA_MAC_VER_45:
5845 case RTL_GIGA_MAC_VER_46:
5846 rtl_hw_start_8168h_1(tp);
5847 break;
5848
219a1e9d
FR		 5849 default:
5850 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
5851 dev->name, tp->mac_version);
4804b3b3 5852 break;
219a1e9d 5853 }
2dd99530 5854
1a964649 5855 RTL_W8(Cfg9346, Cfg9346_Lock);
5856
0e485150
FR		 5857 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5858
1a964649 5859 rtl_set_rx_mode(dev);
b8363901 5860
2dd99530 5861 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
07ce4064 5862}
1da177e4 5863
2857ffb7
FR		 5864#define R810X_CPCMD_QUIRK_MASK (\
5865 EnableBist | \
5866 Mac_dbgo_oe | \
5867 Force_half_dup | \
5edcc537 5868 Force_rxflow_en | \
2857ffb7
FR		 5869 Force_txflow_en | \
5870 Cxpl_dbg_sel | \
5871 ASF | \
5872 PktCntrDisable | \
d24e9aaf 5873 Mac_dbgo_sel)
2857ffb7 5874
beb1fe18 5875static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
2857ffb7 5876{
beb1fe18
HW		 5877 void __iomem *ioaddr = tp->mmio_addr;
5878 struct pci_dev *pdev = tp->pci_dev;
350f7596 5879 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 5880 { 0x01, 0, 0x6e65 },
5881 { 0x02, 0, 0x091f },
5882 { 0x03, 0, 0xc2f9 },
5883 { 0x06, 0, 0xafb5 },
5884 { 0x07, 0, 0x0e00 },
5885 { 0x19, 0, 0xec80 },
5886 { 0x01, 0, 0x2e65 },
5887 { 0x01, 0, 0x6e65 }
5888 };
5889 u8 cfg1;
5890
beb1fe18 5891 rtl_csi_access_enable_2(tp);
2857ffb7
FR		 5892
5893 RTL_W8(DBG_REG, FIX_NAK_1);
5894
5895 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5896
5897 RTL_W8(Config1,
5898 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5899 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5900
5901 cfg1 = RTL_R8(Config1);
5902 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5903 RTL_W8(Config1, cfg1 & ~LEDS0);
5904
fdf6fc06 5905 rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
2857ffb7
FR		 5906}
5907
beb1fe18 5908static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
2857ffb7 5909{
beb1fe18
HW		 5910 void __iomem *ioaddr = tp->mmio_addr;
5911 struct pci_dev *pdev = tp->pci_dev;
5912
5913 rtl_csi_access_enable_2(tp);
2857ffb7
FR		 5914
5915 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5916
5917 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
5918 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2857ffb7
FR		 5919}
5920
beb1fe18 5921static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
2857ffb7 5922{
beb1fe18 5923 rtl_hw_start_8102e_2(tp);
2857ffb7 5924
fdf6fc06 5925 rtl_ephy_write(tp, 0x03, 0xc2f9);
2857ffb7
FR		 5926}
5927
beb1fe18 5928static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5a5e4443 5929{
beb1fe18 5930 void __iomem *ioaddr = tp->mmio_addr;
5a5e4443
HW		 5931 static const struct ephy_info e_info_8105e_1[] = {
5932 { 0x07, 0, 0x4000 },
5933 { 0x19, 0, 0x0200 },
5934 { 0x19, 0, 0x0020 },
5935 { 0x1e, 0, 0x2000 },
5936 { 0x03, 0, 0x0001 },
5937 { 0x19, 0, 0x0100 },
5938 { 0x19, 0, 0x0004 },
5939 { 0x0a, 0, 0x0020 }
5940 };
5941
cecb5fd7 5942 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5a5e4443
HW		 5943 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5944
cecb5fd7 5945 /* Disable Early Tally Counter */
5a5e4443
HW		 5946 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
5947
5948 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4f6b00e5 5949 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5a5e4443 5950
fdf6fc06 5951 rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
b51ecea8 5952
5953 rtl_pcie_state_l2l3_enable(tp, false);
5a5e4443
HW		 5954}
5955
beb1fe18 5956static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5a5e4443 5957{
beb1fe18 5958 rtl_hw_start_8105e_1(tp);
fdf6fc06 5959 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5a5e4443
HW		 5960}
5961
7e18dca1
HW		 5962static void rtl_hw_start_8402(struct rtl8169_private *tp)
5963{
5964 void __iomem *ioaddr = tp->mmio_addr;
5965 static const struct ephy_info e_info_8402[] = {
5966 { 0x19, 0xffff, 0xff64 },
5967 { 0x1e, 0, 0x4000 }
5968 };
5969
5970 rtl_csi_access_enable_2(tp);
5971
5972 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5973 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5974
5975 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5976 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5977
fdf6fc06 5978 rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
7e18dca1
HW		 5979
5980 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
5981
fdf6fc06
FR		 5982 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
5983 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
5984 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5985 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5986 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5987 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5988 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
b51ecea8 5989
5990 rtl_pcie_state_l2l3_enable(tp, false);
7e18dca1
HW		 5991}
5992
5598bfe5
HW		 5993static void rtl_hw_start_8106(struct rtl8169_private *tp)
5994{
5995 void __iomem *ioaddr = tp->mmio_addr;
5996
5997 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5998 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5999
4521e1a9 6000 RTL_W32(MISC, (RTL_R32(MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5598bfe5
HW		 6001 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
6002 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
b51ecea8 6003
6004 rtl_pcie_state_l2l3_enable(tp, false);
5598bfe5
HW		 6005}
6006
07ce4064
FR		 6007static void rtl_hw_start_8101(struct net_device *dev)
6008{
cdf1a608
FR		 6009 struct rtl8169_private *tp = netdev_priv(dev);
6010 void __iomem *ioaddr = tp->mmio_addr;
6011 struct pci_dev *pdev = tp->pci_dev;
6012
da78dbff
FR		 6013 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
6014 tp->event_slow &= ~RxFIFOOver;
811fd301 6015
cecb5fd7 6016 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
7d7903b2 6017 tp->mac_version == RTL_GIGA_MAC_VER_16)
8200bc72
BH		 6018 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL,
6019 PCI_EXP_DEVCTL_NOSNOOP_EN);
cdf1a608 6020
d24e9aaf
HW		 6021 RTL_W8(Cfg9346, Cfg9346_Unlock);
6022
1a964649 6023 RTL_W8(MaxTxPacketSize, TxPacketMax);
6024
6025 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
6026
6027 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
6028 RTL_W16(CPlusCmd, tp->cp_cmd);
6029
6030 rtl_set_rx_tx_desc_registers(tp, ioaddr);
6031
6032 rtl_set_rx_tx_config_registers(tp);
6033
2857ffb7
FR		 6034 switch (tp->mac_version) {
6035 case RTL_GIGA_MAC_VER_07:
beb1fe18 6036 rtl_hw_start_8102e_1(tp);
2857ffb7
FR		 6037 break;
6038
6039 case RTL_GIGA_MAC_VER_08:
beb1fe18 6040 rtl_hw_start_8102e_3(tp);
2857ffb7
FR		 6041 break;
6042
6043 case RTL_GIGA_MAC_VER_09:
beb1fe18 6044 rtl_hw_start_8102e_2(tp);
2857ffb7 6045 break;
5a5e4443
HW		 6046
6047 case RTL_GIGA_MAC_VER_29:
beb1fe18 6048 rtl_hw_start_8105e_1(tp);
5a5e4443
HW		 6049 break;
6050 case RTL_GIGA_MAC_VER_30:
beb1fe18 6051 rtl_hw_start_8105e_2(tp);
5a5e4443 6052 break;
7e18dca1
HW		 6053
6054 case RTL_GIGA_MAC_VER_37:
6055 rtl_hw_start_8402(tp);
6056 break;
5598bfe5
HW		 6057
6058 case RTL_GIGA_MAC_VER_39:
6059 rtl_hw_start_8106(tp);
6060 break;
58152cd4 6061 case RTL_GIGA_MAC_VER_43:
6062 rtl_hw_start_8168g_2(tp);
6063 break;
6e1d0b89
CHL		 6064 case RTL_GIGA_MAC_VER_47:
6065 case RTL_GIGA_MAC_VER_48:
6066 rtl_hw_start_8168h_1(tp);
6067 break;
cdf1a608
FR		 6068 }
6069
d24e9aaf 6070 RTL_W8(Cfg9346, Cfg9346_Lock);
cdf1a608 6071
cdf1a608
FR		 6072 RTL_W16(IntrMitigate, 0x0000);
6073
cdf1a608 6074 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
cdf1a608 6075
cdf1a608
FR		 6076 rtl_set_rx_mode(dev);
6077
1a964649 6078 RTL_R8(IntrMask);
6079
cdf1a608 6080 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
1da177e4
LT		 6081}
6082
6083static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
6084{
d58d46b5
FR		 6085 struct rtl8169_private *tp = netdev_priv(dev);
6086
6087 if (new_mtu < ETH_ZLEN ||
6088 new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
1da177e4
LT		 6089 return -EINVAL;
6090
d58d46b5
FR		 6091 if (new_mtu > ETH_DATA_LEN)
6092 rtl_hw_jumbo_enable(tp);
6093 else
6094 rtl_hw_jumbo_disable(tp);
6095
1da177e4 6096 dev->mtu = new_mtu;
350fb32a
MM		 6097 netdev_update_features(dev);
6098
323bb685 6099 return 0;
1da177e4
LT		 6100}
6101
6102static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
6103{
95e0918d 6104 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 6105 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
6106}
6107
6f0333b8
ED		 6108static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
6109 void **data_buff, struct RxDesc *desc)
1da177e4 6110{
48addcc9 6111 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
231aee63 6112 DMA_FROM_DEVICE);
48addcc9 6113
6f0333b8
ED		 6114 kfree(*data_buff);
6115 *data_buff = NULL;
1da177e4
LT		 6116 rtl8169_make_unusable_by_asic(desc);
6117}
6118
6119static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
6120{
6121 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
6122
6123 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
6124}
6125
6126static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
6127 u32 rx_buf_sz)
6128{
6129 desc->addr = cpu_to_le64(mapping);
6130 wmb();
6131 rtl8169_mark_to_asic(desc, rx_buf_sz);
6132}
6133
6f0333b8
ED		 6134static inline void *rtl8169_align(void *data)
6135{
6136 return (void *)ALIGN((long)data, 16);
6137}
6138
0ecbe1ca
SG		 6139static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
6140 struct RxDesc *desc)
1da177e4 6141{
6f0333b8 6142 void *data;
1da177e4 6143 dma_addr_t mapping;
48addcc9 6144 struct device *d = &tp->pci_dev->dev;
0ecbe1ca 6145 struct net_device *dev = tp->dev;
6f0333b8 6146 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
1da177e4 6147
6f0333b8
ED		 6148 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
6149 if (!data)
6150 return NULL;
e9f63f30 6151
6f0333b8
ED		 6152 if (rtl8169_align(data) != data) {
6153 kfree(data);
6154 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
6155 if (!data)
6156 return NULL;
6157 }
3eafe507 6158
48addcc9 6159 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
231aee63 6160 DMA_FROM_DEVICE);
d827d86b
SG		 6161 if (unlikely(dma_mapping_error(d, mapping))) {
6162 if (net_ratelimit())
6163 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
3eafe507 6164 goto err_out;
d827d86b 6165 }
1da177e4
LT		 6166
6167 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6f0333b8 6168 return data;
3eafe507
SG		 6169
6170err_out:
6171 kfree(data);
6172 return NULL;
1da177e4
LT		 6173}
6174
6175static void rtl8169_rx_clear(struct rtl8169_private *tp)
6176{
07d3f51f 6177 unsigned int i;
1da177e4
LT		 6178
6179 for (i = 0; i < NUM_RX_DESC; i++) {
6f0333b8
ED		 6180 if (tp->Rx_databuff[i]) {
6181 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
1da177e4
LT		 6182 tp->RxDescArray + i);
6183 }
6184 }
6185}
6186
0ecbe1ca 6187static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1da177e4 6188{
0ecbe1ca
SG		 6189 desc->opts1 |= cpu_to_le32(RingEnd);
6190}
5b0384f4 6191
0ecbe1ca
SG		 6192static int rtl8169_rx_fill(struct rtl8169_private *tp)
6193{
6194 unsigned int i;
1da177e4 6195
0ecbe1ca
SG		 6196 for (i = 0; i < NUM_RX_DESC; i++) {
6197 void *data;
4ae47c2d 6198
6f0333b8 6199 if (tp->Rx_databuff[i])
1da177e4 6200 continue;
bcf0bf90 6201
0ecbe1ca 6202 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6f0333b8
ED		 6203 if (!data) {
6204 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
0ecbe1ca 6205 goto err_out;
6f0333b8
ED		 6206 }
6207 tp->Rx_databuff[i] = data;
1da177e4 6208 }
1da177e4 6209
0ecbe1ca
SG		 6210 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
6211 return 0;
6212
6213err_out:
6214 rtl8169_rx_clear(tp);
6215 return -ENOMEM;
1da177e4
LT		 6216}
6217
1da177e4
LT		 6218static int rtl8169_init_ring(struct net_device *dev)
6219{
6220 struct rtl8169_private *tp = netdev_priv(dev);
6221
6222 rtl8169_init_ring_indexes(tp);
6223
6224 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
6f0333b8 6225 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
1da177e4 6226
0ecbe1ca 6227 return rtl8169_rx_fill(tp);
1da177e4
LT		 6228}
6229
48addcc9 6230static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
1da177e4
LT		 6231 struct TxDesc *desc)
6232{
6233 unsigned int len = tx_skb->len;
6234
48addcc9
SG		 6235 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
6236
1da177e4
LT		 6237 desc->opts1 = 0x00;
6238 desc->opts2 = 0x00;
6239 desc->addr = 0x00;
6240 tx_skb->len = 0;
6241}
6242
3eafe507
SG		 6243static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
6244 unsigned int n)
1da177e4
LT		 6245{
6246 unsigned int i;
6247
3eafe507
SG		 6248 for (i = 0; i < n; i++) {
6249 unsigned int entry = (start + i) % NUM_TX_DESC;
1da177e4
LT		 6250 struct ring_info *tx_skb = tp->tx_skb + entry;
6251 unsigned int len = tx_skb->len;
6252
6253 if (len) {
6254 struct sk_buff *skb = tx_skb->skb;
6255
48addcc9 6256 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
1da177e4
LT		 6257 tp->TxDescArray + entry);
6258 if (skb) {
cac4b22f 6259 tp->dev->stats.tx_dropped++;
989c9ba1 6260 dev_kfree_skb_any(skb);
1da177e4
LT		 6261 tx_skb->skb = NULL;
6262 }
1da177e4
LT		 6263 }
6264 }
3eafe507
SG		 6265}
6266
6267static void rtl8169_tx_clear(struct rtl8169_private *tp)
6268{
6269 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
1da177e4
LT		 6270 tp->cur_tx = tp->dirty_tx = 0;
6271}
6272
4422bcd4 6273static void rtl_reset_work(struct rtl8169_private *tp)
1da177e4 6274{
c4028958 6275 struct net_device *dev = tp->dev;
56de414c 6276 int i;
1da177e4 6277
da78dbff
FR		 6278 napi_disable(&tp->napi);
6279 netif_stop_queue(dev);
6280 synchronize_sched();
1da177e4 6281
c7c2c39b 6282 rtl8169_hw_reset(tp);
6283
56de414c
FR		 6284 for (i = 0; i < NUM_RX_DESC; i++)
6285 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
6286
1da177e4 6287 rtl8169_tx_clear(tp);
c7c2c39b 6288 rtl8169_init_ring_indexes(tp);
1da177e4 6289
da78dbff 6290 napi_enable(&tp->napi);
56de414c
FR		 6291 rtl_hw_start(dev);
6292 netif_wake_queue(dev);
6293 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1da177e4
LT		 6294}
6295
6296static void rtl8169_tx_timeout(struct net_device *dev)
6297{
da78dbff
FR		 6298 struct rtl8169_private *tp = netdev_priv(dev);
6299
6300 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 6301}
6302
6303static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2b7b4318 6304 u32 *opts)
1da177e4
LT		 6305{
6306 struct skb_shared_info *info = skb_shinfo(skb);
6307 unsigned int cur_frag, entry;
6e1d0b89 6308 struct TxDesc *uninitialized_var(txd);
48addcc9 6309 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 6310
6311 entry = tp->cur_tx;
6312 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
9e903e08 6313 const skb_frag_t *frag = info->frags + cur_frag;
1da177e4
LT		 6314 dma_addr_t mapping;
6315 u32 status, len;
6316 void *addr;
6317
6318 entry = (entry + 1) % NUM_TX_DESC;
6319
6320 txd = tp->TxDescArray + entry;
9e903e08 6321 len = skb_frag_size(frag);
929f6189 6322 addr = skb_frag_address(frag);
48addcc9 6323 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
d827d86b
SG		 6324 if (unlikely(dma_mapping_error(d, mapping))) {
6325 if (net_ratelimit())
6326 netif_err(tp, drv, tp->dev,
6327 "Failed to map TX fragments DMA!\n");
3eafe507 6328 goto err_out;
d827d86b 6329 }
1da177e4 6330
cecb5fd7 6331 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318
FR		 6332 status = opts[0] | len |
6333 (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 6334
6335 txd->opts1 = cpu_to_le32(status);
2b7b4318 6336 txd->opts2 = cpu_to_le32(opts[1]);
1da177e4
LT		 6337 txd->addr = cpu_to_le64(mapping);
6338
6339 tp->tx_skb[entry].len = len;
6340 }
6341
6342 if (cur_frag) {
6343 tp->tx_skb[entry].skb = skb;
6344 txd->opts1 |= cpu_to_le32(LastFrag);
6345 }
6346
6347 return cur_frag;
3eafe507
SG		 6348
6349err_out:
6350 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
6351 return -EIO;
1da177e4
LT		 6352}
6353
b423e9ae 6354static bool rtl_skb_pad(struct sk_buff *skb)
6355{
6356 if (skb_padto(skb, ETH_ZLEN))
6357 return false;
6358 skb_put(skb, ETH_ZLEN - skb->len);
6359 return true;
6360}
6361
6362static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
6363{
6364 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
6365}
6366
e974604b 6367static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6368 struct net_device *dev);
6369/* r8169_csum_workaround()
6370 * The hw limites the value the transport offset. When the offset is out of the
6371 * range, calculate the checksum by sw.
6372 */
6373static void r8169_csum_workaround(struct rtl8169_private *tp,
6374 struct sk_buff *skb)
6375{
6376 if (skb_shinfo(skb)->gso_size) {
6377 netdev_features_t features = tp->dev->features;
6378 struct sk_buff *segs, *nskb;
6379
6380 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
6381 segs = skb_gso_segment(skb, features);
6382 if (IS_ERR(segs) || !segs)
6383 goto drop;
6384
6385 do {
6386 nskb = segs;
6387 segs = segs->next;
6388 nskb->next = NULL;
6389 rtl8169_start_xmit(nskb, tp->dev);
6390 } while (segs);
6391
6392 dev_kfree_skb(skb);
6393 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6394 if (skb_checksum_help(skb) < 0)
6395 goto drop;
6396
6397 rtl8169_start_xmit(skb, tp->dev);
6398 } else {
6399 struct net_device_stats *stats;
6400
6401drop:
6402 stats = &tp->dev->stats;
6403 stats->tx_dropped++;
6404 dev_kfree_skb(skb);
6405 }
6406}
6407
6408/* msdn_giant_send_check()
6409 * According to the document of microsoft, the TCP Pseudo Header excludes the
6410 * packet length for IPv6 TCP large packets.
6411 */
6412static int msdn_giant_send_check(struct sk_buff *skb)
6413{
6414 const struct ipv6hdr *ipv6h;
6415 struct tcphdr *th;
6416 int ret;
6417
6418 ret = skb_cow_head(skb, 0);
6419 if (ret)
6420 return ret;
6421
6422 ipv6h = ipv6_hdr(skb);
6423 th = tcp_hdr(skb);
6424
6425 th->check = 0;
6426 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
6427
6428 return ret;
6429}
6430
6431static inline __be16 get_protocol(struct sk_buff *skb)
6432{
6433 __be16 protocol;
6434
6435 if (skb->protocol == htons(ETH_P_8021Q))
6436 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
6437 else
6438 protocol = skb->protocol;
6439
6440 return protocol;
6441}
6442
5888d3fc 6443static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
6444 struct sk_buff *skb, u32 *opts)
1da177e4 6445{
350fb32a
MM		 6446 u32 mss = skb_shinfo(skb)->gso_size;
6447
2b7b4318
FR		 6448 if (mss) {
6449 opts[0] |= TD_LSO;
5888d3fc 6450 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
6451 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6452 const struct iphdr *ip = ip_hdr(skb);
6453
6454 if (ip->protocol == IPPROTO_TCP)
6455 opts[0] |= TD0_IP_CS | TD0_TCP_CS;
6456 else if (ip->protocol == IPPROTO_UDP)
6457 opts[0] |= TD0_IP_CS | TD0_UDP_CS;
6458 else
6459 WARN_ON_ONCE(1);
6460 }
6461
6462 return true;
6463}
6464
6465static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
6466 struct sk_buff *skb, u32 *opts)
6467{
bdfa4ed6 6468 u32 transport_offset = (u32)skb_transport_offset(skb);
5888d3fc 6469 u32 mss = skb_shinfo(skb)->gso_size;
6470
6471 if (mss) {
e974604b 6472 if (transport_offset > GTTCPHO_MAX) {
6473 netif_warn(tp, tx_err, tp->dev,
6474 "Invalid transport offset 0x%x for TSO\n",
6475 transport_offset);
6476 return false;
6477 }
6478
6479 switch (get_protocol(skb)) {
6480 case htons(ETH_P_IP):
6481 opts[0] |= TD1_GTSENV4;
6482 break;
6483
6484 case htons(ETH_P_IPV6):
6485 if (msdn_giant_send_check(skb))
6486 return false;
6487
6488 opts[0] |= TD1_GTSENV6;
6489 break;
6490
6491 default:
6492 WARN_ON_ONCE(1);
6493 break;
6494 }
6495
bdfa4ed6 6496 opts[0] |= transport_offset << GTTCPHO_SHIFT;
5888d3fc 6497 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
2b7b4318 6498 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
e974604b 6499 u8 ip_protocol;
1da177e4 6500
b423e9ae 6501 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
6502 return skb_checksum_help(skb) == 0 && rtl_skb_pad(skb);
6503
e974604b 6504 if (transport_offset > TCPHO_MAX) {
6505 netif_warn(tp, tx_err, tp->dev,
6506 "Invalid transport offset 0x%x\n",
6507 transport_offset);
6508 return false;
6509 }
6510
6511 switch (get_protocol(skb)) {
6512 case htons(ETH_P_IP):
6513 opts[1] |= TD1_IPv4_CS;
6514 ip_protocol = ip_hdr(skb)->protocol;
6515 break;
6516
6517 case htons(ETH_P_IPV6):
6518 opts[1] |= TD1_IPv6_CS;
6519 ip_protocol = ipv6_hdr(skb)->nexthdr;
6520 break;
6521
6522 default:
6523 ip_protocol = IPPROTO_RAW;
6524 break;
6525 }
6526
6527 if (ip_protocol == IPPROTO_TCP)
6528 opts[1] |= TD1_TCP_CS;
6529 else if (ip_protocol == IPPROTO_UDP)
6530 opts[1] |= TD1_UDP_CS;
2b7b4318
FR		 6531 else
6532 WARN_ON_ONCE(1);
e974604b 6533
6534 opts[1] |= transport_offset << TCPHO_SHIFT;
b423e9ae 6535 } else {
6536 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
6537 return rtl_skb_pad(skb);
1da177e4 6538 }
5888d3fc 6539
b423e9ae 6540 return true;
1da177e4
LT		 6541}
6542
61357325
SH		 6543static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6544 struct net_device *dev)
1da177e4
LT		 6545{
6546 struct rtl8169_private *tp = netdev_priv(dev);
3eafe507 6547 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
1da177e4
LT		 6548 struct TxDesc *txd = tp->TxDescArray + entry;
6549 void __iomem *ioaddr = tp->mmio_addr;
48addcc9 6550 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 6551 dma_addr_t mapping;
6552 u32 status, len;
2b7b4318 6553 u32 opts[2];
3eafe507 6554 int frags;
5b0384f4 6555
477206a0 6556 if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
bf82c189 6557 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
3eafe507 6558 goto err_stop_0;
1da177e4
LT		 6559 }
6560
6561 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3eafe507
SG		 6562 goto err_stop_0;
6563
b423e9ae 6564 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
6565 opts[0] = DescOwn;
6566
e974604b 6567 if (!tp->tso_csum(tp, skb, opts)) {
6568 r8169_csum_workaround(tp, skb);
6569 return NETDEV_TX_OK;
6570 }
b423e9ae 6571
3eafe507 6572 len = skb_headlen(skb);
48addcc9 6573 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
d827d86b
SG		 6574 if (unlikely(dma_mapping_error(d, mapping))) {
6575 if (net_ratelimit())
6576 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
3eafe507 6577 goto err_dma_0;
d827d86b 6578 }
3eafe507
SG		 6579
6580 tp->tx_skb[entry].len = len;
6581 txd->addr = cpu_to_le64(mapping);
1da177e4 6582
2b7b4318 6583 frags = rtl8169_xmit_frags(tp, skb, opts);
3eafe507
SG		 6584 if (frags < 0)
6585 goto err_dma_1;
6586 else if (frags)
2b7b4318 6587 opts[0] |= FirstFrag;
3eafe507 6588 else {
2b7b4318 6589 opts[0] |= FirstFrag | LastFrag;
1da177e4
LT		 6590 tp->tx_skb[entry].skb = skb;
6591 }
6592
2b7b4318
FR		 6593 txd->opts2 = cpu_to_le32(opts[1]);
6594
5047fb5d
RC		 6595 skb_tx_timestamp(skb);
6596
1da177e4
LT		 6597 wmb();
6598
cecb5fd7 6599 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318 6600 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 6601 txd->opts1 = cpu_to_le32(status);
6602
1da177e4
LT		 6603 tp->cur_tx += frags + 1;
6604
4c020a96 6605 wmb();
1da177e4 6606
cecb5fd7 6607 RTL_W8(TxPoll, NPQ);
1da177e4 6608
da78dbff
FR		 6609 mmiowb();
6610
477206a0 6611 if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
ae1f23fb
FR		 6612 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
6613 * not miss a ring update when it notices a stopped queue.
6614 */
6615 smp_wmb();
1da177e4 6616 netif_stop_queue(dev);
ae1f23fb
FR		 6617 /* Sync with rtl_tx:
6618 * - publish queue status and cur_tx ring index (write barrier)
6619 * - refresh dirty_tx ring index (read barrier).
6620 * May the current thread have a pessimistic view of the ring
6621 * status and forget to wake up queue, a racing rtl_tx thread
6622 * can't.
6623 */
1e874e04 6624 smp_mb();
477206a0 6625 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
1da177e4
LT		 6626 netif_wake_queue(dev);
6627 }
6628
61357325 6629 return NETDEV_TX_OK;
1da177e4 6630
3eafe507 6631err_dma_1:
48addcc9 6632 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
3eafe507 6633err_dma_0:
989c9ba1 6634 dev_kfree_skb_any(skb);
3eafe507
SG		 6635 dev->stats.tx_dropped++;
6636 return NETDEV_TX_OK;
6637
6638err_stop_0:
1da177e4 6639 netif_stop_queue(dev);
cebf8cc7 6640 dev->stats.tx_dropped++;
61357325 6641 return NETDEV_TX_BUSY;
1da177e4
LT		 6642}
6643
6644static void rtl8169_pcierr_interrupt(struct net_device *dev)
6645{
6646 struct rtl8169_private *tp = netdev_priv(dev);
6647 struct pci_dev *pdev = tp->pci_dev;
1da177e4
LT		 6648 u16 pci_status, pci_cmd;
6649
6650 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
6651 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
6652
bf82c189
JP		 6653 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
6654 pci_cmd, pci_status);
1da177e4
LT		 6655
6656 /*
6657 * The recovery sequence below admits a very elaborated explanation:
6658 * - it seems to work;
d03902b8
FR		 6659 * - I did not see what else could be done;
6660 * - it makes iop3xx happy.
1da177e4
LT		 6661 *
6662 * Feel free to adjust to your needs.
6663 */
a27993f3 6664 if (pdev->broken_parity_status)
d03902b8
FR		 6665 pci_cmd &= ~PCI_COMMAND_PARITY;
6666 else
6667 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
6668
6669 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 6670
6671 pci_write_config_word(pdev, PCI_STATUS,
6672 pci_status & (PCI_STATUS_DETECTED_PARITY |
6673 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
6674 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
6675
6676 /* The infamous DAC f*ckup only happens at boot time */
9fba0812 6677 if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
e6de30d6 6678 void __iomem *ioaddr = tp->mmio_addr;
6679
bf82c189 6680 netif_info(tp, intr, dev, "disabling PCI DAC\n");
1da177e4
LT		 6681 tp->cp_cmd &= ~PCIDAC;
6682 RTL_W16(CPlusCmd, tp->cp_cmd);
6683 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 6684 }
6685
e6de30d6 6686 rtl8169_hw_reset(tp);
d03902b8 6687
98ddf986 6688 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 6689}
6690
da78dbff 6691static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
1da177e4
LT		 6692{
6693 unsigned int dirty_tx, tx_left;
6694
1da177e4
LT		 6695 dirty_tx = tp->dirty_tx;
6696 smp_rmb();
6697 tx_left = tp->cur_tx - dirty_tx;
6698
6699 while (tx_left > 0) {
6700 unsigned int entry = dirty_tx % NUM_TX_DESC;
6701 struct ring_info *tx_skb = tp->tx_skb + entry;
1da177e4
LT		 6702 u32 status;
6703
6704 rmb();
6705 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
6706 if (status & DescOwn)
6707 break;
6708
48addcc9
SG		 6709 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
6710 tp->TxDescArray + entry);
1da177e4 6711 if (status & LastFrag) {
17bcb684
FR		 6712 u64_stats_update_begin(&tp->tx_stats.syncp);
6713 tp->tx_stats.packets++;
6714 tp->tx_stats.bytes += tx_skb->skb->len;
6715 u64_stats_update_end(&tp->tx_stats.syncp);
989c9ba1 6716 dev_kfree_skb_any(tx_skb->skb);
1da177e4
LT		 6717 tx_skb->skb = NULL;
6718 }
6719 dirty_tx++;
6720 tx_left--;
6721 }
6722
6723 if (tp->dirty_tx != dirty_tx) {
6724 tp->dirty_tx = dirty_tx;
ae1f23fb
FR		 6725 /* Sync with rtl8169_start_xmit:
6726 * - publish dirty_tx ring index (write barrier)
6727 * - refresh cur_tx ring index and queue status (read barrier)
6728 * May the current thread miss the stopped queue condition,
6729 * a racing xmit thread can only have a right view of the
6730 * ring status.
6731 */
1e874e04 6732 smp_mb();
1da177e4 6733 if (netif_queue_stopped(dev) &&
477206a0 6734 TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
1da177e4
LT		 6735 netif_wake_queue(dev);
6736 }
d78ae2dc
FR		 6737 /*
6738 * 8168 hack: TxPoll requests are lost when the Tx packets are
6739 * too close. Let's kick an extra TxPoll request when a burst
6740 * of start_xmit activity is detected (if it is not detected,
6741 * it is slow enough). -- FR
6742 */
da78dbff
FR		 6743 if (tp->cur_tx != dirty_tx) {
6744 void __iomem *ioaddr = tp->mmio_addr;
6745
d78ae2dc 6746 RTL_W8(TxPoll, NPQ);
da78dbff 6747 }
1da177e4
LT		 6748 }
6749}
6750
126fa4b9
FR		 6751static inline int rtl8169_fragmented_frame(u32 status)
6752{
6753 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
6754}
6755
adea1ac7 6756static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
1da177e4 6757{
1da177e4
LT		 6758 u32 status = opts1 & RxProtoMask;
6759
6760 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
d5d3ebe3 6761 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
1da177e4
LT		 6762 skb->ip_summed = CHECKSUM_UNNECESSARY;
6763 else
bc8acf2c 6764 skb_checksum_none_assert(skb);
1da177e4
LT		 6765}
6766
6f0333b8
ED		 6767static struct sk_buff *rtl8169_try_rx_copy(void *data,
6768 struct rtl8169_private *tp,
6769 int pkt_size,
6770 dma_addr_t addr)
1da177e4 6771{
b449655f 6772 struct sk_buff *skb;
48addcc9 6773 struct device *d = &tp->pci_dev->dev;
b449655f 6774
6f0333b8 6775 data = rtl8169_align(data);
48addcc9 6776 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6f0333b8
ED		 6777 prefetch(data);
6778 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
6779 if (skb)
6780 memcpy(skb->data, data, pkt_size);
48addcc9
SG		 6781 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
6782
6f0333b8 6783 return skb;
1da177e4
LT		 6784}
6785
da78dbff 6786static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
1da177e4
LT		 6787{
6788 unsigned int cur_rx, rx_left;
6f0333b8 6789 unsigned int count;
1da177e4 6790
1da177e4 6791 cur_rx = tp->cur_rx;
1da177e4 6792
9fba0812 6793 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
1da177e4 6794 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 6795 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 6796 u32 status;
6797
6798 rmb();
e03f33af 6799 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
1da177e4
LT		 6800
6801 if (status & DescOwn)
6802 break;
4dcb7d33 6803 if (unlikely(status & RxRES)) {
bf82c189
JP		 6804 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6805 status);
cebf8cc7 6806 dev->stats.rx_errors++;
1da177e4 6807 if (status & (RxRWT | RxRUNT))
cebf8cc7 6808 dev->stats.rx_length_errors++;
1da177e4 6809 if (status & RxCRC)
cebf8cc7 6810 dev->stats.rx_crc_errors++;
9dccf611 6811 if (status & RxFOVF) {
da78dbff 6812 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
cebf8cc7 6813 dev->stats.rx_fifo_errors++;
9dccf611 6814 }
6bbe021d
BG		 6815 if ((status & (RxRUNT | RxCRC)) &&
6816 !(status & (RxRWT | RxFOVF)) &&
6817 (dev->features & NETIF_F_RXALL))
6818 goto process_pkt;
1da177e4 6819 } else {
6f0333b8 6820 struct sk_buff *skb;
6bbe021d
BG		 6821 dma_addr_t addr;
6822 int pkt_size;
6823
6824process_pkt:
6825 addr = le64_to_cpu(desc->addr);
79d0c1d2
BG		 6826 if (likely(!(dev->features & NETIF_F_RXFCS)))
6827 pkt_size = (status & 0x00003fff) - 4;
6828 else
6829 pkt_size = status & 0x00003fff;
1da177e4 6830
126fa4b9
FR		 6831 /*
6832 * The driver does not support incoming fragmented
6833 * frames. They are seen as a symptom of over-mtu
6834 * sized frames.
6835 */
6836 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 6837 dev->stats.rx_dropped++;
6838 dev->stats.rx_length_errors++;
ce11ff5e 6839 goto release_descriptor;
126fa4b9
FR		 6840 }
6841
6f0333b8
ED		 6842 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6843 tp, pkt_size, addr);
6f0333b8
ED		 6844 if (!skb) {
6845 dev->stats.rx_dropped++;
ce11ff5e 6846 goto release_descriptor;
1da177e4
LT		 6847 }
6848
adea1ac7 6849 rtl8169_rx_csum(skb, status);
1da177e4
LT		 6850 skb_put(skb, pkt_size);
6851 skb->protocol = eth_type_trans(skb, dev);
6852
7a8fc77b
FR		 6853 rtl8169_rx_vlan_tag(desc, skb);
6854
56de414c 6855 napi_gro_receive(&tp->napi, skb);
1da177e4 6856
8027aa24
JW		 6857 u64_stats_update_begin(&tp->rx_stats.syncp);
6858 tp->rx_stats.packets++;
6859 tp->rx_stats.bytes += pkt_size;
6860 u64_stats_update_end(&tp->rx_stats.syncp);
1da177e4 6861 }
ce11ff5e 6862release_descriptor:
6863 desc->opts2 = 0;
6864 wmb();
6865 rtl8169_mark_to_asic(desc, rx_buf_sz);
1da177e4
LT		 6866 }
6867
6868 count = cur_rx - tp->cur_rx;
6869 tp->cur_rx = cur_rx;
6870
1da177e4
LT		 6871 return count;
6872}
6873
07d3f51f 6874static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 6875{
07d3f51f 6876 struct net_device *dev = dev_instance;
1da177e4 6877 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 6878 int handled = 0;
9085cdfa 6879 u16 status;
1da177e4 6880
9085cdfa 6881 status = rtl_get_events(tp);
da78dbff
FR		 6882 if (status && status != 0xffff) {
6883 status &= RTL_EVENT_NAPI | tp->event_slow;
6884 if (status) {
6885 handled = 1;
1da177e4 6886
da78dbff
FR		 6887 rtl_irq_disable(tp);
6888 napi_schedule(&tp->napi);
f11a377b 6889 }
da78dbff
FR		 6890 }
6891 return IRQ_RETVAL(handled);
6892}
1da177e4 6893
da78dbff
FR		 6894/*
6895 * Workqueue context.
6896 */
6897static void rtl_slow_event_work(struct rtl8169_private *tp)
6898{
6899 struct net_device *dev = tp->dev;
6900 u16 status;
6901
6902 status = rtl_get_events(tp) & tp->event_slow;
6903 rtl_ack_events(tp, status);
1da177e4 6904
da78dbff
FR		 6905 if (unlikely(status & RxFIFOOver)) {
6906 switch (tp->mac_version) {
6907 /* Work around for rx fifo overflow */
6908 case RTL_GIGA_MAC_VER_11:
6909 netif_stop_queue(dev);
934714d0
FR		 6910 /* XXX - Hack alert. See rtl_task(). */
6911 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
da78dbff 6912 default:
f11a377b
DD		 6913 break;
6914 }
da78dbff 6915 }
1da177e4 6916
da78dbff
FR		 6917 if (unlikely(status & SYSErr))
6918 rtl8169_pcierr_interrupt(dev);
0e485150 6919
da78dbff
FR		 6920 if (status & LinkChg)
6921 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
1da177e4 6922
7dbb4918 6923 rtl_irq_enable_all(tp);
1da177e4
LT		 6924}
6925
4422bcd4
FR		 6926static void rtl_task(struct work_struct *work)
6927{
da78dbff
FR		 6928 static const struct {
6929 int bitnr;
6930 void (*action)(struct rtl8169_private *);
6931 } rtl_work[] = {
934714d0 6932 /* XXX - keep rtl_slow_event_work() as first element. */
da78dbff
FR		 6933 { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work },
6934 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
6935 { RTL_FLAG_TASK_PHY_PENDING, rtl_phy_work }
6936 };
4422bcd4
FR		 6937 struct rtl8169_private *tp =
6938 container_of(work, struct rtl8169_private, wk.work);
da78dbff
FR		 6939 struct net_device *dev = tp->dev;
6940 int i;
6941
6942 rtl_lock_work(tp);
6943
6c4a70c5
FR		 6944 if (!netif_running(dev) ||
6945 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
da78dbff
FR		 6946 goto out_unlock;
6947
6948 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6949 bool pending;
6950
da78dbff 6951 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
da78dbff
FR		 6952 if (pending)
6953 rtl_work[i].action(tp);
6954 }
4422bcd4 6955
da78dbff
FR		 6956out_unlock:
6957 rtl_unlock_work(tp);
4422bcd4
FR		 6958}
6959
bea3348e 6960static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 6961{
bea3348e
SH		 6962 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6963 struct net_device *dev = tp->dev;
da78dbff
FR		 6964 u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
6965 int work_done= 0;
6966 u16 status;
6967
6968 status = rtl_get_events(tp);
6969 rtl_ack_events(tp, status & ~tp->event_slow);
6970
6971 if (status & RTL_EVENT_NAPI_RX)
6972 work_done = rtl_rx(dev, tp, (u32) budget);
6973
6974 if (status & RTL_EVENT_NAPI_TX)
6975 rtl_tx(dev, tp);
1da177e4 6976
da78dbff
FR		 6977 if (status & tp->event_slow) {
6978 enable_mask &= ~tp->event_slow;
6979
6980 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
6981 }
1da177e4 6982
bea3348e 6983 if (work_done < budget) {
288379f0 6984 napi_complete(napi);
f11a377b 6985
da78dbff
FR		 6986 rtl_irq_enable(tp, enable_mask);
6987 mmiowb();
1da177e4
LT		 6988 }
6989
bea3348e 6990 return work_done;
1da177e4 6991}
1da177e4 6992
523a6094
FR		 6993static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
6994{
6995 struct rtl8169_private *tp = netdev_priv(dev);
6996
6997 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6998 return;
6999
7000 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
7001 RTL_W32(RxMissed, 0);
7002}
7003
1da177e4
LT		 7004static void rtl8169_down(struct net_device *dev)
7005{
7006 struct rtl8169_private *tp = netdev_priv(dev);
7007 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 7008
4876cc1e 7009 del_timer_sync(&tp->timer);
1da177e4 7010
93dd79e8 7011 napi_disable(&tp->napi);
da78dbff 7012 netif_stop_queue(dev);
1da177e4 7013
92fc43b4 7014 rtl8169_hw_reset(tp);
323bb685
SG		 7015 /*
7016 * At this point device interrupts can not be enabled in any function,
209e5ac8
FR		 7017 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
7018 * and napi is disabled (rtl8169_poll).
323bb685 7019 */
523a6094 7020 rtl8169_rx_missed(dev, ioaddr);
1da177e4 7021
1da177e4 7022 /* Give a racing hard_start_xmit a few cycles to complete. */
da78dbff 7023 synchronize_sched();
1da177e4 7024
1da177e4
LT		 7025 rtl8169_tx_clear(tp);
7026
7027 rtl8169_rx_clear(tp);
065c27c1 7028
7029 rtl_pll_power_down(tp);
1da177e4
LT		 7030}
7031
7032static int rtl8169_close(struct net_device *dev)
7033{
7034 struct rtl8169_private *tp = netdev_priv(dev);
7035 struct pci_dev *pdev = tp->pci_dev;
7036
e1759441
RW		 7037 pm_runtime_get_sync(&pdev->dev);
7038
cecb5fd7 7039 /* Update counters before going down */
355423d0
IV		 7040 rtl8169_update_counters(dev);
7041
da78dbff 7042 rtl_lock_work(tp);
6c4a70c5 7043 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
da78dbff 7044
1da177e4 7045 rtl8169_down(dev);
da78dbff 7046 rtl_unlock_work(tp);
1da177e4 7047
4ea72445
L		 7048 cancel_work_sync(&tp->wk.work);
7049
92a7c4e7 7050 free_irq(pdev->irq, dev);
1da177e4 7051
82553bb6
SG		 7052 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7053 tp->RxPhyAddr);
7054 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7055 tp->TxPhyAddr);
1da177e4
LT		 7056 tp->TxDescArray = NULL;
7057 tp->RxDescArray = NULL;
7058
e1759441
RW		 7059 pm_runtime_put_sync(&pdev->dev);
7060
1da177e4
LT		 7061 return 0;
7062}
7063
dc1c00ce
FR		 7064#ifdef CONFIG_NET_POLL_CONTROLLER
7065static void rtl8169_netpoll(struct net_device *dev)
7066{
7067 struct rtl8169_private *tp = netdev_priv(dev);
7068
7069 rtl8169_interrupt(tp->pci_dev->irq, dev);
7070}
7071#endif
7072
df43ac78
FR		 7073static int rtl_open(struct net_device *dev)
7074{
7075 struct rtl8169_private *tp = netdev_priv(dev);
7076 void __iomem *ioaddr = tp->mmio_addr;
7077 struct pci_dev *pdev = tp->pci_dev;
7078 int retval = -ENOMEM;
7079
7080 pm_runtime_get_sync(&pdev->dev);
7081
7082 /*
e75d6606 7083 * Rx and Tx descriptors needs 256 bytes alignment.
df43ac78
FR		 7084 * dma_alloc_coherent provides more.
7085 */
7086 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
7087 &tp->TxPhyAddr, GFP_KERNEL);
7088 if (!tp->TxDescArray)
7089 goto err_pm_runtime_put;
7090
7091 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
7092 &tp->RxPhyAddr, GFP_KERNEL);
7093 if (!tp->RxDescArray)
7094 goto err_free_tx_0;
7095
7096 retval = rtl8169_init_ring(dev);
7097 if (retval < 0)
7098 goto err_free_rx_1;
7099
7100 INIT_WORK(&tp->wk.work, rtl_task);
7101
7102 smp_mb();
7103
7104 rtl_request_firmware(tp);
7105
92a7c4e7 7106 retval = request_irq(pdev->irq, rtl8169_interrupt,
df43ac78
FR		 7107 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
7108 dev->name, dev);
7109 if (retval < 0)
7110 goto err_release_fw_2;
7111
7112 rtl_lock_work(tp);
7113
7114 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7115
7116 napi_enable(&tp->napi);
7117
7118 rtl8169_init_phy(dev, tp);
7119
7120 __rtl8169_set_features(dev, dev->features);
7121
7122 rtl_pll_power_up(tp);
7123
7124 rtl_hw_start(dev);
7125
7126 netif_start_queue(dev);
7127
7128 rtl_unlock_work(tp);
7129
7130 tp->saved_wolopts = 0;
7131 pm_runtime_put_noidle(&pdev->dev);
7132
7133 rtl8169_check_link_status(dev, tp, ioaddr);
7134out:
7135 return retval;
7136
7137err_release_fw_2:
7138 rtl_release_firmware(tp);
7139 rtl8169_rx_clear(tp);
7140err_free_rx_1:
7141 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7142 tp->RxPhyAddr);
7143 tp->RxDescArray = NULL;
7144err_free_tx_0:
7145 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7146 tp->TxPhyAddr);
7147 tp->TxDescArray = NULL;
7148err_pm_runtime_put:
7149 pm_runtime_put_noidle(&pdev->dev);
7150 goto out;
7151}
7152
8027aa24
JW		 7153static struct rtnl_link_stats64 *
7154rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
1da177e4
LT		 7155{
7156 struct rtl8169_private *tp = netdev_priv(dev);
7157 void __iomem *ioaddr = tp->mmio_addr;
8027aa24 7158 unsigned int start;
1da177e4 7159
da78dbff 7160 if (netif_running(dev))
523a6094 7161 rtl8169_rx_missed(dev, ioaddr);
5b0384f4 7162
8027aa24 7163 do {
57a7744e 7164 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
8027aa24
JW		 7165 stats->rx_packets = tp->rx_stats.packets;
7166 stats->rx_bytes = tp->rx_stats.bytes;
57a7744e 7167 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
8027aa24
JW		 7168
7169
7170 do {
57a7744e 7171 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
8027aa24
JW		 7172 stats->tx_packets = tp->tx_stats.packets;
7173 stats->tx_bytes = tp->tx_stats.bytes;
57a7744e 7174 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
8027aa24
JW		 7175
7176 stats->rx_dropped = dev->stats.rx_dropped;
7177 stats->tx_dropped = dev->stats.tx_dropped;
7178 stats->rx_length_errors = dev->stats.rx_length_errors;
7179 stats->rx_errors = dev->stats.rx_errors;
7180 stats->rx_crc_errors = dev->stats.rx_crc_errors;
7181 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
7182 stats->rx_missed_errors = dev->stats.rx_missed_errors;
7183
7184 return stats;
1da177e4
LT		 7185}
7186
861ab440 7187static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 7188{
065c27c1 7189 struct rtl8169_private *tp = netdev_priv(dev);
7190
5d06a99f 7191 if (!netif_running(dev))
861ab440 7192 return;
5d06a99f
FR		 7193
7194 netif_device_detach(dev);
7195 netif_stop_queue(dev);
da78dbff
FR		 7196
7197 rtl_lock_work(tp);
7198 napi_disable(&tp->napi);
6c4a70c5 7199 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
da78dbff
FR		 7200 rtl_unlock_work(tp);
7201
7202 rtl_pll_power_down(tp);
861ab440
RW		 7203}
7204
7205#ifdef CONFIG_PM
7206
7207static int rtl8169_suspend(struct device *device)
7208{
7209 struct pci_dev *pdev = to_pci_dev(device);
7210 struct net_device *dev = pci_get_drvdata(pdev);
5d06a99f 7211
861ab440 7212 rtl8169_net_suspend(dev);
1371fa6d 7213
5d06a99f
FR		 7214 return 0;
7215}
7216
e1759441
RW		 7217static void __rtl8169_resume(struct net_device *dev)
7218{
065c27c1 7219 struct rtl8169_private *tp = netdev_priv(dev);
7220
e1759441 7221 netif_device_attach(dev);
065c27c1 7222
7223 rtl_pll_power_up(tp);
7224
cff4c162
AS		 7225 rtl_lock_work(tp);
7226 napi_enable(&tp->napi);
6c4a70c5 7227 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
cff4c162 7228 rtl_unlock_work(tp);
da78dbff 7229
98ddf986 7230 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
e1759441
RW		 7231}
7232
861ab440 7233static int rtl8169_resume(struct device *device)
5d06a99f 7234{
861ab440 7235 struct pci_dev *pdev = to_pci_dev(device);
5d06a99f 7236 struct net_device *dev = pci_get_drvdata(pdev);
fccec10b
SG		 7237 struct rtl8169_private *tp = netdev_priv(dev);
7238
7239 rtl8169_init_phy(dev, tp);
5d06a99f 7240
e1759441
RW		 7241 if (netif_running(dev))
7242 __rtl8169_resume(dev);
5d06a99f 7243
e1759441
RW		 7244 return 0;
7245}
7246
7247static int rtl8169_runtime_suspend(struct device *device)
7248{
7249 struct pci_dev *pdev = to_pci_dev(device);
7250 struct net_device *dev = pci_get_drvdata(pdev);
7251 struct rtl8169_private *tp = netdev_priv(dev);
7252
7253 if (!tp->TxDescArray)
7254 return 0;
7255
da78dbff 7256 rtl_lock_work(tp);
e1759441
RW		 7257 tp->saved_wolopts = __rtl8169_get_wol(tp);
7258 __rtl8169_set_wol(tp, WAKE_ANY);
da78dbff 7259 rtl_unlock_work(tp);
e1759441
RW		 7260
7261 rtl8169_net_suspend(dev);
7262
7263 return 0;
7264}
7265
7266static int rtl8169_runtime_resume(struct device *device)
7267{
7268 struct pci_dev *pdev = to_pci_dev(device);
7269 struct net_device *dev = pci_get_drvdata(pdev);
7270 struct rtl8169_private *tp = netdev_priv(dev);
7271
7272 if (!tp->TxDescArray)
7273 return 0;
7274
da78dbff 7275 rtl_lock_work(tp);
e1759441
RW		 7276 __rtl8169_set_wol(tp, tp->saved_wolopts);
7277 tp->saved_wolopts = 0;
da78dbff 7278 rtl_unlock_work(tp);
e1759441 7279
fccec10b
SG		 7280 rtl8169_init_phy(dev, tp);
7281
e1759441 7282 __rtl8169_resume(dev);
5d06a99f 7283
5d06a99f
FR		 7284 return 0;
7285}
7286
e1759441
RW		 7287static int rtl8169_runtime_idle(struct device *device)
7288{
7289 struct pci_dev *pdev = to_pci_dev(device);
7290 struct net_device *dev = pci_get_drvdata(pdev);
7291 struct rtl8169_private *tp = netdev_priv(dev);
7292
e4fbce74 7293 return tp->TxDescArray ? -EBUSY : 0;
e1759441
RW		 7294}
7295
47145210 7296static const struct dev_pm_ops rtl8169_pm_ops = {
cecb5fd7
FR		 7297 .suspend = rtl8169_suspend,
7298 .resume = rtl8169_resume,
7299 .freeze = rtl8169_suspend,
7300 .thaw = rtl8169_resume,
7301 .poweroff = rtl8169_suspend,
7302 .restore = rtl8169_resume,
7303 .runtime_suspend = rtl8169_runtime_suspend,
7304 .runtime_resume = rtl8169_runtime_resume,
7305 .runtime_idle = rtl8169_runtime_idle,
861ab440
RW		 7306};
7307
7308#define RTL8169_PM_OPS (&rtl8169_pm_ops)
7309
7310#else /* !CONFIG_PM */
7311
7312#define RTL8169_PM_OPS NULL
7313
7314#endif /* !CONFIG_PM */
7315
649b3b8c 7316static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
7317{
7318 void __iomem *ioaddr = tp->mmio_addr;
7319
7320 /* WoL fails with 8168b when the receiver is disabled. */
7321 switch (tp->mac_version) {
7322 case RTL_GIGA_MAC_VER_11:
7323 case RTL_GIGA_MAC_VER_12:
7324 case RTL_GIGA_MAC_VER_17:
7325 pci_clear_master(tp->pci_dev);
7326
7327 RTL_W8(ChipCmd, CmdRxEnb);
7328 /* PCI commit */
7329 RTL_R8(ChipCmd);
7330 break;
7331 default:
7332 break;
7333 }
7334}
7335
1765f95d
FR		 7336static void rtl_shutdown(struct pci_dev *pdev)
7337{
861ab440 7338 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 7339 struct rtl8169_private *tp = netdev_priv(dev);
2a15cd2f 7340 struct device *d = &pdev->dev;
7341
7342 pm_runtime_get_sync(d);
861ab440
RW		 7343
7344 rtl8169_net_suspend(dev);
1765f95d 7345
cecb5fd7 7346 /* Restore original MAC address */
cc098dc7
IV		 7347 rtl_rar_set(tp, dev->perm_addr);
7348
92fc43b4 7349 rtl8169_hw_reset(tp);
4bb3f522 7350
861ab440 7351 if (system_state == SYSTEM_POWER_OFF) {
649b3b8c 7352 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
7353 rtl_wol_suspend_quirk(tp);
7354 rtl_wol_shutdown_quirk(tp);
ca52efd5 7355 }
7356
861ab440
RW		 7357 pci_wake_from_d3(pdev, true);
7358 pci_set_power_state(pdev, PCI_D3hot);
7359 }
2a15cd2f 7360
7361 pm_runtime_put_noidle(d);
861ab440 7362}
5d06a99f 7363
baf63293 7364static void rtl_remove_one(struct pci_dev *pdev)
e27566ed
FR		 7365{
7366 struct net_device *dev = pci_get_drvdata(pdev);
7367 struct rtl8169_private *tp = netdev_priv(dev);
7368
7369 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
7370 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
7371 tp->mac_version == RTL_GIGA_MAC_VER_31) {
7372 rtl8168_driver_stop(tp);
7373 }
7374
ad1be8d3
DN		 7375 netif_napi_del(&tp->napi);
7376
e27566ed
FR		 7377 unregister_netdev(dev);
7378
7379 rtl_release_firmware(tp);
7380
7381 if (pci_dev_run_wake(pdev))
7382 pm_runtime_get_noresume(&pdev->dev);
7383
7384 /* restore original MAC address */
7385 rtl_rar_set(tp, dev->perm_addr);
7386
7387 rtl_disable_msi(pdev, tp);
7388 rtl8169_release_board(pdev, dev, tp->mmio_addr);
e27566ed
FR		 7389}
7390
fa9c385e 7391static const struct net_device_ops rtl_netdev_ops = {
df43ac78 7392 .ndo_open = rtl_open,
fa9c385e
FR		 7393 .ndo_stop = rtl8169_close,
7394 .ndo_get_stats64 = rtl8169_get_stats64,
7395 .ndo_start_xmit = rtl8169_start_xmit,
7396 .ndo_tx_timeout = rtl8169_tx_timeout,
7397 .ndo_validate_addr = eth_validate_addr,
7398 .ndo_change_mtu = rtl8169_change_mtu,
7399 .ndo_fix_features = rtl8169_fix_features,
7400 .ndo_set_features = rtl8169_set_features,
7401 .ndo_set_mac_address = rtl_set_mac_address,
7402 .ndo_do_ioctl = rtl8169_ioctl,
7403 .ndo_set_rx_mode = rtl_set_rx_mode,
7404#ifdef CONFIG_NET_POLL_CONTROLLER
7405 .ndo_poll_controller = rtl8169_netpoll,
7406#endif
7407
7408};
7409
31fa8b18
FR		 7410static const struct rtl_cfg_info {
7411 void (*hw_start)(struct net_device *);
7412 unsigned int region;
7413 unsigned int align;
7414 u16 event_slow;
7415 unsigned features;
7416 u8 default_ver;
7417} rtl_cfg_infos [] = {
7418 [RTL_CFG_0] = {
7419 .hw_start = rtl_hw_start_8169,
7420 .region = 1,
7421 .align = 0,
7422 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
7423 .features = RTL_FEATURE_GMII,
7424 .default_ver = RTL_GIGA_MAC_VER_01,
7425 },
7426 [RTL_CFG_1] = {
7427 .hw_start = rtl_hw_start_8168,
7428 .region = 2,
7429 .align = 8,
7430 .event_slow = SYSErr | LinkChg | RxOverflow,
7431 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
7432 .default_ver = RTL_GIGA_MAC_VER_11,
7433 },
7434 [RTL_CFG_2] = {
7435 .hw_start = rtl_hw_start_8101,
7436 .region = 2,
7437 .align = 8,
7438 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
7439 PCSTimeout,
7440 .features = RTL_FEATURE_MSI,
7441 .default_ver = RTL_GIGA_MAC_VER_13,
7442 }
7443};
7444
7445/* Cfg9346_Unlock assumed. */
7446static unsigned rtl_try_msi(struct rtl8169_private *tp,
7447 const struct rtl_cfg_info *cfg)
7448{
7449 void __iomem *ioaddr = tp->mmio_addr;
7450 unsigned msi = 0;
7451 u8 cfg2;
7452
7453 cfg2 = RTL_R8(Config2) & ~MSIEnable;
7454 if (cfg->features & RTL_FEATURE_MSI) {
7455 if (pci_enable_msi(tp->pci_dev)) {
7456 netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
7457 } else {
7458 cfg2 |= MSIEnable;
7459 msi = RTL_FEATURE_MSI;
7460 }
7461 }
7462 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
7463 RTL_W8(Config2, cfg2);
7464 return msi;
7465}
7466
c558386b
HW		 7467DECLARE_RTL_COND(rtl_link_list_ready_cond)
7468{
7469 void __iomem *ioaddr = tp->mmio_addr;
7470
7471 return RTL_R8(MCU) & LINK_LIST_RDY;
7472}
7473
7474DECLARE_RTL_COND(rtl_rxtx_empty_cond)
7475{
7476 void __iomem *ioaddr = tp->mmio_addr;
7477
7478 return (RTL_R8(MCU) & RXTX_EMPTY) == RXTX_EMPTY;
7479}
7480
baf63293 7481static void rtl_hw_init_8168g(struct rtl8169_private *tp)
c558386b
HW		 7482{
7483 void __iomem *ioaddr = tp->mmio_addr;
7484 u32 data;
7485
7486 tp->ocp_base = OCP_STD_PHY_BASE;
7487
7488 RTL_W32(MISC, RTL_R32(MISC) | RXDV_GATED_EN);
7489
7490 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
7491 return;
7492
7493 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
7494 return;
7495
7496 RTL_W8(ChipCmd, RTL_R8(ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
7497 msleep(1);
7498 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
7499
5f8bcce9 7500 data = r8168_mac_ocp_read(tp, 0xe8de);
c558386b
HW		 7501 data &= ~(1 << 14);
7502 r8168_mac_ocp_write(tp, 0xe8de, data);
7503
7504 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7505 return;
7506
5f8bcce9 7507 data = r8168_mac_ocp_read(tp, 0xe8de);
c558386b
HW		 7508 data |= (1 << 15);
7509 r8168_mac_ocp_write(tp, 0xe8de, data);
7510
7511 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7512 return;
7513}
7514
baf63293 7515static void rtl_hw_initialize(struct rtl8169_private *tp)
c558386b
HW		 7516{
7517 switch (tp->mac_version) {
7518 case RTL_GIGA_MAC_VER_40:
7519 case RTL_GIGA_MAC_VER_41:
57538c4a 7520 case RTL_GIGA_MAC_VER_42:
58152cd4 7521 case RTL_GIGA_MAC_VER_43:
45dd95c4 7522 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 7523 case RTL_GIGA_MAC_VER_45:
7524 case RTL_GIGA_MAC_VER_46:
7525 case RTL_GIGA_MAC_VER_47:
7526 case RTL_GIGA_MAC_VER_48:
c558386b
HW		 7527 rtl_hw_init_8168g(tp);
7528 break;
7529
7530 default:
7531 break;
7532 }
7533}
7534
929a031d 7535static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3b6cf25d
FR		 7536{
7537 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
7538 const unsigned int region = cfg->region;
7539 struct rtl8169_private *tp;
7540 struct mii_if_info *mii;
7541 struct net_device *dev;
7542 void __iomem *ioaddr;
7543 int chipset, i;
7544 int rc;
7545
7546 if (netif_msg_drv(&debug)) {
7547 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
7548 MODULENAME, RTL8169_VERSION);
7549 }
7550
7551 dev = alloc_etherdev(sizeof (*tp));
7552 if (!dev) {
7553 rc = -ENOMEM;
7554 goto out;
7555 }
7556
7557 SET_NETDEV_DEV(dev, &pdev->dev);
fa9c385e 7558 dev->netdev_ops = &rtl_netdev_ops;
3b6cf25d
FR		 7559 tp = netdev_priv(dev);
7560 tp->dev = dev;
7561 tp->pci_dev = pdev;
7562 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
7563
7564 mii = &tp->mii;
7565 mii->dev = dev;
7566 mii->mdio_read = rtl_mdio_read;
7567 mii->mdio_write = rtl_mdio_write;
7568 mii->phy_id_mask = 0x1f;
7569 mii->reg_num_mask = 0x1f;
7570 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
7571
7572 /* disable ASPM completely as that cause random device stop working
7573 * problems as well as full system hangs for some PCIe devices users */
7574 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
7575 PCIE_LINK_STATE_CLKPM);
7576
7577 /* enable device (incl. PCI PM wakeup and hotplug setup) */
7578 rc = pci_enable_device(pdev);
7579 if (rc < 0) {
7580 netif_err(tp, probe, dev, "enable failure\n");
7581 goto err_out_free_dev_1;
7582 }
7583
7584 if (pci_set_mwi(pdev) < 0)
7585 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
7586
7587 /* make sure PCI base addr 1 is MMIO */
7588 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
7589 netif_err(tp, probe, dev,
7590 "region #%d not an MMIO resource, aborting\n",
7591 region);
7592 rc = -ENODEV;
7593 goto err_out_mwi_2;
7594 }
7595
7596 /* check for weird/broken PCI region reporting */
7597 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
7598 netif_err(tp, probe, dev,
7599 "Invalid PCI region size(s), aborting\n");
7600 rc = -ENODEV;
7601 goto err_out_mwi_2;
7602 }
7603
7604 rc = pci_request_regions(pdev, MODULENAME);
7605 if (rc < 0) {
7606 netif_err(tp, probe, dev, "could not request regions\n");
7607 goto err_out_mwi_2;
7608 }
7609
929a031d 7610 tp->cp_cmd = 0;
3b6cf25d
FR		 7611
7612 if ((sizeof(dma_addr_t) > 4) &&
7613 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
7614 tp->cp_cmd |= PCIDAC;
7615 dev->features |= NETIF_F_HIGHDMA;
7616 } else {
7617 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
7618 if (rc < 0) {
7619 netif_err(tp, probe, dev, "DMA configuration failed\n");
7620 goto err_out_free_res_3;
7621 }
7622 }
7623
7624 /* ioremap MMIO region */
7625 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
7626 if (!ioaddr) {
7627 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
7628 rc = -EIO;
7629 goto err_out_free_res_3;
7630 }
7631 tp->mmio_addr = ioaddr;
7632
7633 if (!pci_is_pcie(pdev))
7634 netif_info(tp, probe, dev, "not PCI Express\n");
7635
7636 /* Identify chip attached to board */
7637 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
7638
7639 rtl_init_rxcfg(tp);
7640
7641 rtl_irq_disable(tp);
7642
c558386b
HW		 7643 rtl_hw_initialize(tp);
7644
3b6cf25d
FR		 7645 rtl_hw_reset(tp);
7646
7647 rtl_ack_events(tp, 0xffff);
7648
7649 pci_set_master(pdev);
7650
3b6cf25d
FR		 7651 rtl_init_mdio_ops(tp);
7652 rtl_init_pll_power_ops(tp);
7653 rtl_init_jumbo_ops(tp);
beb1fe18 7654 rtl_init_csi_ops(tp);
3b6cf25d
FR		 7655
7656 rtl8169_print_mac_version(tp);
7657
7658 chipset = tp->mac_version;
7659 tp->txd_version = rtl_chip_infos[chipset].txd_version;
7660
7661 RTL_W8(Cfg9346, Cfg9346_Unlock);
7662 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
8f9d5138 7663 RTL_W8(Config5, RTL_R8(Config5) & (BWF | MWF | UWF | LanWake | PMEStatus));
6e1d0b89
CHL		 7664 switch (tp->mac_version) {
7665 case RTL_GIGA_MAC_VER_45:
7666 case RTL_GIGA_MAC_VER_46:
7667 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
7668 tp->features |= RTL_FEATURE_WOL;
7669 if ((RTL_R8(Config3) & LinkUp) != 0)
7670 tp->features |= RTL_FEATURE_WOL;
7671 break;
7672 default:
7673 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
7674 tp->features |= RTL_FEATURE_WOL;
7675 break;
7676 }
3b6cf25d
FR		 7677 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
7678 tp->features |= RTL_FEATURE_WOL;
7679 tp->features |= rtl_try_msi(tp, cfg);
7680 RTL_W8(Cfg9346, Cfg9346_Lock);
7681
7682 if (rtl_tbi_enabled(tp)) {
7683 tp->set_speed = rtl8169_set_speed_tbi;
7684 tp->get_settings = rtl8169_gset_tbi;
7685 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
7686 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
7687 tp->link_ok = rtl8169_tbi_link_ok;
7688 tp->do_ioctl = rtl_tbi_ioctl;
7689 } else {
7690 tp->set_speed = rtl8169_set_speed_xmii;
7691 tp->get_settings = rtl8169_gset_xmii;
7692 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
7693 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
7694 tp->link_ok = rtl8169_xmii_link_ok;
7695 tp->do_ioctl = rtl_xmii_ioctl;
7696 }
7697
7698 mutex_init(&tp->wk.mutex);
340fea3d
KM		 7699 u64_stats_init(&tp->rx_stats.syncp);
7700 u64_stats_init(&tp->tx_stats.syncp);
3b6cf25d
FR		 7701
7702 /* Get MAC address */
6e1d0b89
CHL		 7703 if (tp->mac_version == RTL_GIGA_MAC_VER_45 ||
7704 tp->mac_version == RTL_GIGA_MAC_VER_46 ||
7705 tp->mac_version == RTL_GIGA_MAC_VER_47 ||
7706 tp->mac_version == RTL_GIGA_MAC_VER_48) {
7707 u16 mac_addr[3];
7708
7709 *(u32 *)&mac_addr[0] = rtl_eri_read(tp, 0xE0, ERIAR_EXGMAC);
7710 *(u16 *)&mac_addr[2] = rtl_eri_read(tp, 0xE4, ERIAR_EXGMAC);
7711
7712 if (is_valid_ether_addr((u8 *)mac_addr))
7713 rtl_rar_set(tp, (u8 *)mac_addr);
7714 }
3b6cf25d
FR		 7715 for (i = 0; i < ETH_ALEN; i++)
7716 dev->dev_addr[i] = RTL_R8(MAC0 + i);
3b6cf25d 7717
7ad24ea4 7718 dev->ethtool_ops = &rtl8169_ethtool_ops;
3b6cf25d 7719 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3b6cf25d
FR		 7720
7721 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
7722
7723 /* don't enable SG, IP_CSUM and TSO by default - it might not work
7724 * properly for all devices */
7725 dev->features |= NETIF_F_RXCSUM |
f646968f 7726 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d
FR		 7727
7728 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
f646968f
PM		 7729 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
7730 NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d
FR		 7731 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7732 NETIF_F_HIGHDMA;
7733
929a031d 7734 tp->cp_cmd |= RxChkSum | RxVlan;
7735
7736 /*
7737 * Pretend we are using VLANs; This bypasses a nasty bug where
7738 * Interrupts stop flowing on high load on 8110SCd controllers.
7739 */
3b6cf25d 7740 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
929a031d 7741 /* Disallow toggling */
f646968f 7742 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d 7743
5888d3fc 7744 if (tp->txd_version == RTL_TD_0)
7745 tp->tso_csum = rtl8169_tso_csum_v1;
e974604b 7746 else if (tp->txd_version == RTL_TD_1) {
5888d3fc 7747 tp->tso_csum = rtl8169_tso_csum_v2;
e974604b 7748 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
7749 } else
5888d3fc 7750 WARN_ON_ONCE(1);
7751
3b6cf25d
FR		 7752 dev->hw_features |= NETIF_F_RXALL;
7753 dev->hw_features |= NETIF_F_RXFCS;
7754
7755 tp->hw_start = cfg->hw_start;
7756 tp->event_slow = cfg->event_slow;
7757
7758 tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
7759 ~(RxBOVF | RxFOVF) : ~0;
7760
7761 init_timer(&tp->timer);
7762 tp->timer.data = (unsigned long) dev;
7763 tp->timer.function = rtl8169_phy_timer;
7764
7765 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
7766
7767 rc = register_netdev(dev);
7768 if (rc < 0)
7769 goto err_out_msi_4;
7770
7771 pci_set_drvdata(pdev, dev);
7772
92a7c4e7
FR		 7773 netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
7774 rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
7775 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
3b6cf25d
FR		 7776 if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
7777 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
7778 "tx checksumming: %s]\n",
7779 rtl_chip_infos[chipset].jumbo_max,
7780 rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
7781 }
7782
7783 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
7784 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
7785 tp->mac_version == RTL_GIGA_MAC_VER_31) {
7786 rtl8168_driver_start(tp);
7787 }
7788
7789 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
7790
7791 if (pci_dev_run_wake(pdev))
7792 pm_runtime_put_noidle(&pdev->dev);
7793
7794 netif_carrier_off(dev);
7795
7796out:
7797 return rc;
7798
7799err_out_msi_4:
ad1be8d3 7800 netif_napi_del(&tp->napi);
3b6cf25d
FR		 7801 rtl_disable_msi(pdev, tp);
7802 iounmap(ioaddr);
7803err_out_free_res_3:
7804 pci_release_regions(pdev);
7805err_out_mwi_2:
7806 pci_clear_mwi(pdev);
7807 pci_disable_device(pdev);
7808err_out_free_dev_1:
7809 free_netdev(dev);
7810 goto out;
7811}
7812
1da177e4
LT		 7813static struct pci_driver rtl8169_pci_driver = {
7814 .name = MODULENAME,
7815 .id_table = rtl8169_pci_tbl,
3b6cf25d 7816 .probe = rtl_init_one,
baf63293 7817 .remove = rtl_remove_one,
1765f95d 7818 .shutdown = rtl_shutdown,
861ab440 7819 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 7820};
7821
3eeb7da9 7822module_pci_driver(rtl8169_pci_driver);
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