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r8169: remove unused macros.
[mirror_ubuntu-focal-kernel.git] / drivers / net / ethernet / realtek / r8169.c
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1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
a6b7a407 25#include <linux/interrupt.h>
1da177e4 26#include <linux/dma-mapping.h>
e1759441 27#include <linux/pm_runtime.h>
bca03d5f 28#include <linux/firmware.h>
ba04c7c9 29#include <linux/pci-aspm.h>
70c71606 30#include <linux/prefetch.h>
1da177e4
LT		 31
32#include <asm/io.h>
33#include <asm/irq.h>
34
865c652d 35#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 36#define MODULENAME "r8169"
37#define PFX MODULENAME ": "
38
bca03d5f 39#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
40#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
01dc7fec 41#define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
42#define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
70090424 43#define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
c2218925
HW		 44#define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
45#define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
5a5e4443 46#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
7e18dca1 47#define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
b3d7b2f2 48#define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
5598bfe5 49#define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
c558386b 50#define FIRMWARE_8168G_1 "rtl_nic/rtl8168g-1.fw"
bca03d5f 51
1da177e4
LT		 52#ifdef RTL8169_DEBUG
53#define assert(expr) \
5b0384f4
FR		 54 if (!(expr)) { \
55 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
b39d66a8 56 #expr,__FILE__,__func__,__LINE__); \
5b0384f4 57 }
06fa7358
JP		 58#define dprintk(fmt, args...) \
59 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 60#else
61#define assert(expr) do {} while (0)
62#define dprintk(fmt, args...) do {} while (0)
63#endif /* RTL8169_DEBUG */
64
b57b7e5a 65#define R8169_MSG_DEFAULT \
f0e837d9 66 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 67
477206a0
JD		 68#define TX_SLOTS_AVAIL(tp) \
69 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
70
71/* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
72#define TX_FRAGS_READY_FOR(tp,nr_frags) \
73 (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
1da177e4 74
1da177e4
LT		 75/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
76 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 77static const int multicast_filter_limit = 32;
1da177e4 78
9c14ceaf 79#define MAX_READ_REQUEST_SHIFT 12
aee77e4a 80#define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
1da177e4
LT		 81#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
82
83#define R8169_REGS_SIZE 256
84#define R8169_NAPI_WEIGHT 64
85#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
86#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
1da177e4
LT		 87#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
88#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
89
90#define RTL8169_TX_TIMEOUT (6*HZ)
91#define RTL8169_PHY_TIMEOUT (10*HZ)
92
93/* write/read MMIO register */
94#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
95#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
96#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
97#define RTL_R8(reg) readb (ioaddr + (reg))
98#define RTL_R16(reg) readw (ioaddr + (reg))
06f555f3 99#define RTL_R32(reg) readl (ioaddr + (reg))
1da177e4
LT		 100
101enum mac_version {
85bffe6c
FR		 102 RTL_GIGA_MAC_VER_01 = 0,
103 RTL_GIGA_MAC_VER_02,
104 RTL_GIGA_MAC_VER_03,
105 RTL_GIGA_MAC_VER_04,
106 RTL_GIGA_MAC_VER_05,
107 RTL_GIGA_MAC_VER_06,
108 RTL_GIGA_MAC_VER_07,
109 RTL_GIGA_MAC_VER_08,
110 RTL_GIGA_MAC_VER_09,
111 RTL_GIGA_MAC_VER_10,
112 RTL_GIGA_MAC_VER_11,
113 RTL_GIGA_MAC_VER_12,
114 RTL_GIGA_MAC_VER_13,
115 RTL_GIGA_MAC_VER_14,
116 RTL_GIGA_MAC_VER_15,
117 RTL_GIGA_MAC_VER_16,
118 RTL_GIGA_MAC_VER_17,
119 RTL_GIGA_MAC_VER_18,
120 RTL_GIGA_MAC_VER_19,
121 RTL_GIGA_MAC_VER_20,
122 RTL_GIGA_MAC_VER_21,
123 RTL_GIGA_MAC_VER_22,
124 RTL_GIGA_MAC_VER_23,
125 RTL_GIGA_MAC_VER_24,
126 RTL_GIGA_MAC_VER_25,
127 RTL_GIGA_MAC_VER_26,
128 RTL_GIGA_MAC_VER_27,
129 RTL_GIGA_MAC_VER_28,
130 RTL_GIGA_MAC_VER_29,
131 RTL_GIGA_MAC_VER_30,
132 RTL_GIGA_MAC_VER_31,
133 RTL_GIGA_MAC_VER_32,
134 RTL_GIGA_MAC_VER_33,
70090424 135 RTL_GIGA_MAC_VER_34,
c2218925
HW		 136 RTL_GIGA_MAC_VER_35,
137 RTL_GIGA_MAC_VER_36,
7e18dca1 138 RTL_GIGA_MAC_VER_37,
b3d7b2f2 139 RTL_GIGA_MAC_VER_38,
5598bfe5 140 RTL_GIGA_MAC_VER_39,
c558386b
HW		 141 RTL_GIGA_MAC_VER_40,
142 RTL_GIGA_MAC_VER_41,
85bffe6c 143 RTL_GIGA_MAC_NONE = 0xff,
1da177e4
LT		 144};
145
2b7b4318
FR		 146enum rtl_tx_desc_version {
147 RTL_TD_0 = 0,
148 RTL_TD_1 = 1,
149};
150
d58d46b5
FR		 151#define JUMBO_1K ETH_DATA_LEN
152#define JUMBO_4K (4*1024 - ETH_HLEN - 2)
153#define JUMBO_6K (6*1024 - ETH_HLEN - 2)
154#define JUMBO_7K (7*1024 - ETH_HLEN - 2)
155#define JUMBO_9K (9*1024 - ETH_HLEN - 2)
156
157#define _R(NAME,TD,FW,SZ,B) { \
158 .name = NAME, \
159 .txd_version = TD, \
160 .fw_name = FW, \
161 .jumbo_max = SZ, \
162 .jumbo_tx_csum = B \
163}
1da177e4 164
3c6bee1d 165static const struct {
1da177e4 166 const char *name;
2b7b4318 167 enum rtl_tx_desc_version txd_version;
953a12cc 168 const char *fw_name;
d58d46b5
FR		 169 u16 jumbo_max;
170 bool jumbo_tx_csum;
85bffe6c
FR		 171} rtl_chip_infos[] = {
172 /* PCI devices. */
173 [RTL_GIGA_MAC_VER_01] =
d58d46b5 174 _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 175 [RTL_GIGA_MAC_VER_02] =
d58d46b5 176 _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 177 [RTL_GIGA_MAC_VER_03] =
d58d46b5 178 _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 179 [RTL_GIGA_MAC_VER_04] =
d58d46b5 180 _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 181 [RTL_GIGA_MAC_VER_05] =
d58d46b5 182 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 183 [RTL_GIGA_MAC_VER_06] =
d58d46b5 184 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c
FR		 185 /* PCI-E devices. */
186 [RTL_GIGA_MAC_VER_07] =
d58d46b5 187 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 188 [RTL_GIGA_MAC_VER_08] =
d58d46b5 189 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 190 [RTL_GIGA_MAC_VER_09] =
d58d46b5 191 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 192 [RTL_GIGA_MAC_VER_10] =
d58d46b5 193 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 194 [RTL_GIGA_MAC_VER_11] =
d58d46b5 195 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
85bffe6c 196 [RTL_GIGA_MAC_VER_12] =
d58d46b5 197 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
85bffe6c 198 [RTL_GIGA_MAC_VER_13] =
d58d46b5 199 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 200 [RTL_GIGA_MAC_VER_14] =
d58d46b5 201 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 202 [RTL_GIGA_MAC_VER_15] =
d58d46b5 203 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 204 [RTL_GIGA_MAC_VER_16] =
d58d46b5 205 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 206 [RTL_GIGA_MAC_VER_17] =
d58d46b5 207 _R("RTL8168b/8111b", RTL_TD_1, NULL, JUMBO_4K, false),
85bffe6c 208 [RTL_GIGA_MAC_VER_18] =
d58d46b5 209 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 210 [RTL_GIGA_MAC_VER_19] =
d58d46b5 211 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 212 [RTL_GIGA_MAC_VER_20] =
d58d46b5 213 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 214 [RTL_GIGA_MAC_VER_21] =
d58d46b5 215 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 216 [RTL_GIGA_MAC_VER_22] =
d58d46b5 217 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 218 [RTL_GIGA_MAC_VER_23] =
d58d46b5 219 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 220 [RTL_GIGA_MAC_VER_24] =
d58d46b5 221 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 222 [RTL_GIGA_MAC_VER_25] =
d58d46b5
FR		 223 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1,
224 JUMBO_9K, false),
85bffe6c 225 [RTL_GIGA_MAC_VER_26] =
d58d46b5
FR		 226 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2,
227 JUMBO_9K, false),
85bffe6c 228 [RTL_GIGA_MAC_VER_27] =
d58d46b5 229 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 230 [RTL_GIGA_MAC_VER_28] =
d58d46b5 231 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 232 [RTL_GIGA_MAC_VER_29] =
d58d46b5
FR		 233 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
234 JUMBO_1K, true),
85bffe6c 235 [RTL_GIGA_MAC_VER_30] =
d58d46b5
FR		 236 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
237 JUMBO_1K, true),
85bffe6c 238 [RTL_GIGA_MAC_VER_31] =
d58d46b5 239 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 240 [RTL_GIGA_MAC_VER_32] =
d58d46b5
FR		 241 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1,
242 JUMBO_9K, false),
85bffe6c 243 [RTL_GIGA_MAC_VER_33] =
d58d46b5
FR		 244 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2,
245 JUMBO_9K, false),
70090424 246 [RTL_GIGA_MAC_VER_34] =
d58d46b5
FR		 247 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
248 JUMBO_9K, false),
c2218925 249 [RTL_GIGA_MAC_VER_35] =
d58d46b5
FR		 250 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1,
251 JUMBO_9K, false),
c2218925 252 [RTL_GIGA_MAC_VER_36] =
d58d46b5
FR		 253 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2,
254 JUMBO_9K, false),
7e18dca1
HW		 255 [RTL_GIGA_MAC_VER_37] =
256 _R("RTL8402", RTL_TD_1, FIRMWARE_8402_1,
257 JUMBO_1K, true),
b3d7b2f2
HW		 258 [RTL_GIGA_MAC_VER_38] =
259 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_1,
260 JUMBO_9K, false),
5598bfe5
HW		 261 [RTL_GIGA_MAC_VER_39] =
262 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_1,
263 JUMBO_1K, true),
c558386b
HW		 264 [RTL_GIGA_MAC_VER_40] =
265 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_1,
266 JUMBO_9K, false),
267 [RTL_GIGA_MAC_VER_41] =
268 _R("RTL8168g/8111g", RTL_TD_1, NULL, JUMBO_9K, false),
953a12cc 269};
85bffe6c 270#undef _R
953a12cc 271
bcf0bf90
FR		 272enum cfg_version {
273 RTL_CFG_0 = 0x00,
274 RTL_CFG_1,
275 RTL_CFG_2
276};
277
a3aa1884 278static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
bcf0bf90 279 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 280 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 281 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 282 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90 283 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
2a35cfa5
FR		 284 { PCI_VENDOR_ID_DLINK, 0x4300,
285 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
bcf0bf90 286 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
93a3aa25 287 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
bc1660b5 288 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 289 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
290 { PCI_VENDOR_ID_LINKSYS, 0x1032,
291 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 292 { 0x0001, 0x8168,
293 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 294 {0,},
295};
296
297MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
298
6f0333b8 299static int rx_buf_sz = 16383;
4300e8c7 300static int use_dac;
b57b7e5a
SH		 301static struct {
302 u32 msg_enable;
303} debug = { -1 };
1da177e4 304
07d3f51f
FR		 305enum rtl_registers {
306 MAC0 = 0, /* Ethernet hardware address. */
773d2021 307 MAC4 = 4,
07d3f51f
FR		 308 MAR0 = 8, /* Multicast filter. */
309 CounterAddrLow = 0x10,
310 CounterAddrHigh = 0x14,
311 TxDescStartAddrLow = 0x20,
312 TxDescStartAddrHigh = 0x24,
313 TxHDescStartAddrLow = 0x28,
314 TxHDescStartAddrHigh = 0x2c,
315 FLASH = 0x30,
316 ERSR = 0x36,
317 ChipCmd = 0x37,
318 TxPoll = 0x38,
319 IntrMask = 0x3c,
320 IntrStatus = 0x3e,
4f6b00e5 321
07d3f51f 322 TxConfig = 0x40,
4f6b00e5
HW		 323#define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
324#define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
2b7b4318 325
4f6b00e5
HW		 326 RxConfig = 0x44,
327#define RX128_INT_EN (1 << 15) /* 8111c and later */
328#define RX_MULTI_EN (1 << 14) /* 8111c only */
329#define RXCFG_FIFO_SHIFT 13
330 /* No threshold before first PCI xfer */
331#define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
332#define RXCFG_DMA_SHIFT 8
333 /* Unlimited maximum PCI burst. */
334#define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
2b7b4318 335
07d3f51f
FR		 336 RxMissed = 0x4c,
337 Cfg9346 = 0x50,
338 Config0 = 0x51,
339 Config1 = 0x52,
340 Config2 = 0x53,
d387b427
FR		 341#define PME_SIGNAL (1 << 5) /* 8168c and later */
342
07d3f51f
FR		 343 Config3 = 0x54,
344 Config4 = 0x55,
345 Config5 = 0x56,
346 MultiIntr = 0x5c,
347 PHYAR = 0x60,
07d3f51f
FR		 348 PHYstatus = 0x6c,
349 RxMaxSize = 0xda,
350 CPlusCmd = 0xe0,
351 IntrMitigate = 0xe2,
352 RxDescAddrLow = 0xe4,
353 RxDescAddrHigh = 0xe8,
f0298f81 354 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
355
356#define NoEarlyTx 0x3f /* Max value : no early transmit. */
357
358 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
359
360#define TxPacketMax (8064 >> 7)
3090bd9a 361#define EarlySize 0x27
f0298f81 362
07d3f51f
FR		 363 FuncEvent = 0xf0,
364 FuncEventMask = 0xf4,
365 FuncPresetState = 0xf8,
366 FuncForceEvent = 0xfc,
1da177e4
LT		 367};
368
f162a5d1
FR		 369enum rtl8110_registers {
370 TBICSR = 0x64,
371 TBI_ANAR = 0x68,
372 TBI_LPAR = 0x6a,
373};
374
375enum rtl8168_8101_registers {
376 CSIDR = 0x64,
377 CSIAR = 0x68,
378#define CSIAR_FLAG 0x80000000
379#define CSIAR_WRITE_CMD 0x80000000
380#define CSIAR_BYTE_ENABLE 0x0f
381#define CSIAR_BYTE_ENABLE_SHIFT 12
382#define CSIAR_ADDR_MASK 0x0fff
7e18dca1
HW		 383#define CSIAR_FUNC_CARD 0x00000000
384#define CSIAR_FUNC_SDIO 0x00010000
385#define CSIAR_FUNC_NIC 0x00020000
065c27c1 386 PMCH = 0x6f,
f162a5d1
FR		 387 EPHYAR = 0x80,
388#define EPHYAR_FLAG 0x80000000
389#define EPHYAR_WRITE_CMD 0x80000000
390#define EPHYAR_REG_MASK 0x1f
391#define EPHYAR_REG_SHIFT 16
392#define EPHYAR_DATA_MASK 0xffff
5a5e4443 393 DLLPR = 0xd0,
4f6b00e5 394#define PFM_EN (1 << 6)
f162a5d1
FR		 395 DBG_REG = 0xd1,
396#define FIX_NAK_1 (1 << 4)
397#define FIX_NAK_2 (1 << 3)
5a5e4443
HW		 398 TWSI = 0xd2,
399 MCU = 0xd3,
4f6b00e5 400#define NOW_IS_OOB (1 << 7)
c558386b
HW		 401#define TX_EMPTY (1 << 5)
402#define RX_EMPTY (1 << 4)
403#define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
5a5e4443
HW		 404#define EN_NDP (1 << 3)
405#define EN_OOB_RESET (1 << 2)
c558386b 406#define LINK_LIST_RDY (1 << 1)
daf9df6d 407 EFUSEAR = 0xdc,
408#define EFUSEAR_FLAG 0x80000000
409#define EFUSEAR_WRITE_CMD 0x80000000
410#define EFUSEAR_READ_CMD 0x00000000
411#define EFUSEAR_REG_MASK 0x03ff
412#define EFUSEAR_REG_SHIFT 8
413#define EFUSEAR_DATA_MASK 0xff
f162a5d1
FR		 414};
415
c0e45c1c 416enum rtl8168_registers {
4f6b00e5
HW		 417 LED_FREQ = 0x1a,
418 EEE_LED = 0x1b,
b646d900 419 ERIDR = 0x70,
420 ERIAR = 0x74,
421#define ERIAR_FLAG 0x80000000
422#define ERIAR_WRITE_CMD 0x80000000
423#define ERIAR_READ_CMD 0x00000000
424#define ERIAR_ADDR_BYTE_ALIGN 4
b646d900 425#define ERIAR_TYPE_SHIFT 16
4f6b00e5
HW		 426#define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
427#define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
428#define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
429#define ERIAR_MASK_SHIFT 12
430#define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
431#define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
c558386b 432#define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
4f6b00e5 433#define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
c0e45c1c 434 EPHY_RXER_NUM = 0x7c,
435 OCPDR = 0xb0, /* OCP GPHY access */
436#define OCPDR_WRITE_CMD 0x80000000
437#define OCPDR_READ_CMD 0x00000000
438#define OCPDR_REG_MASK 0x7f
439#define OCPDR_GPHY_REG_SHIFT 16
440#define OCPDR_DATA_MASK 0xffff
441 OCPAR = 0xb4,
442#define OCPAR_FLAG 0x80000000
443#define OCPAR_GPHY_WRITE_CMD 0x8000f060
444#define OCPAR_GPHY_READ_CMD 0x0000f060
c558386b 445 GPHY_OCP = 0xb8,
01dc7fec 446 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
447 MISC = 0xf0, /* 8168e only. */
cecb5fd7 448#define TXPLA_RST (1 << 29)
5598bfe5 449#define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
4f6b00e5 450#define PWM_EN (1 << 22)
c558386b 451#define RXDV_GATED_EN (1 << 19)
5598bfe5 452#define EARLY_TALLY_EN (1 << 16)
d64ec841 453#define FORCE_CLK (1 << 15) /* force clock request */
c0e45c1c 454};
455
07d3f51f 456enum rtl_register_content {
1da177e4 457 /* InterruptStatusBits */
07d3f51f
FR		 458 SYSErr = 0x8000,
459 PCSTimeout = 0x4000,
460 SWInt = 0x0100,
461 TxDescUnavail = 0x0080,
462 RxFIFOOver = 0x0040,
463 LinkChg = 0x0020,
464 RxOverflow = 0x0010,
465 TxErr = 0x0008,
466 TxOK = 0x0004,
467 RxErr = 0x0002,
468 RxOK = 0x0001,
1da177e4
LT		 469
470 /* RxStatusDesc */
e03f33af 471 RxBOVF = (1 << 24),
9dccf611
FR		 472 RxFOVF = (1 << 23),
473 RxRWT = (1 << 22),
474 RxRES = (1 << 21),
475 RxRUNT = (1 << 20),
476 RxCRC = (1 << 19),
1da177e4
LT		 477
478 /* ChipCmdBits */
4f6b00e5 479 StopReq = 0x80,
07d3f51f
FR		 480 CmdReset = 0x10,
481 CmdRxEnb = 0x08,
482 CmdTxEnb = 0x04,
483 RxBufEmpty = 0x01,
1da177e4 484
275391a4
FR		 485 /* TXPoll register p.5 */
486 HPQ = 0x80, /* Poll cmd on the high prio queue */
487 NPQ = 0x40, /* Poll cmd on the low prio queue */
488 FSWInt = 0x01, /* Forced software interrupt */
489
1da177e4 490 /* Cfg9346Bits */
07d3f51f
FR		 491 Cfg9346_Lock = 0x00,
492 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 493
494 /* rx_mode_bits */
07d3f51f
FR		 495 AcceptErr = 0x20,
496 AcceptRunt = 0x10,
497 AcceptBroadcast = 0x08,
498 AcceptMulticast = 0x04,
499 AcceptMyPhys = 0x02,
500 AcceptAllPhys = 0x01,
1687b566 501#define RX_CONFIG_ACCEPT_MASK 0x3f
1da177e4 502
1da177e4
LT		 503 /* TxConfigBits */
504 TxInterFrameGapShift = 24,
505 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
506
5d06a99f 507 /* Config1 register p.24 */
f162a5d1
FR		 508 LEDS1 = (1 << 7),
509 LEDS0 = (1 << 6),
f162a5d1
FR		 510 Speed_down = (1 << 4),
511 MEMMAP = (1 << 3),
512 IOMAP = (1 << 2),
513 VPD = (1 << 1),
5d06a99f
FR		 514 PMEnable = (1 << 0), /* Power Management Enable */
515
6dccd16b 516 /* Config2 register p. 25 */
d64ec841 517 ClkReqEn = (1 << 7), /* Clock Request Enable */
2ca6cf06 518 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
6dccd16b
FR		 519 PCI_Clock_66MHz = 0x01,
520 PCI_Clock_33MHz = 0x00,
521
61a4dcc2
FR		 522 /* Config3 register p.25 */
523 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
524 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
d58d46b5 525 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
f162a5d1 526 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 527
d58d46b5
FR		 528 /* Config4 register */
529 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
530
5d06a99f 531 /* Config5 register p.27 */
61a4dcc2
FR		 532 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
533 MWF = (1 << 5), /* Accept Multicast wakeup frame */
534 UWF = (1 << 4), /* Accept Unicast wakeup frame */
cecb5fd7 535 Spi_en = (1 << 3),
61a4dcc2 536 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f 537 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
d64ec841 538 ASPM_en = (1 << 0), /* ASPM enable */
5d06a99f 539
1da177e4
LT		 540 /* TBICSR p.28 */
541 TBIReset = 0x80000000,
542 TBILoopback = 0x40000000,
543 TBINwEnable = 0x20000000,
544 TBINwRestart = 0x10000000,
545 TBILinkOk = 0x02000000,
546 TBINwComplete = 0x01000000,
547
548 /* CPlusCmd p.31 */
f162a5d1
FR		 549 EnableBist = (1 << 15), // 8168 8101
550 Mac_dbgo_oe = (1 << 14), // 8168 8101
551 Normal_mode = (1 << 13), // unused
552 Force_half_dup = (1 << 12), // 8168 8101
553 Force_rxflow_en = (1 << 11), // 8168 8101
554 Force_txflow_en = (1 << 10), // 8168 8101
555 Cxpl_dbg_sel = (1 << 9), // 8168 8101
556 ASF = (1 << 8), // 8168 8101
557 PktCntrDisable = (1 << 7), // 8168 8101
558 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 559 RxVlan = (1 << 6),
560 RxChkSum = (1 << 5),
561 PCIDAC = (1 << 4),
562 PCIMulRW = (1 << 3),
0e485150
FR		 563 INTT_0 = 0x0000, // 8168
564 INTT_1 = 0x0001, // 8168
565 INTT_2 = 0x0002, // 8168
566 INTT_3 = 0x0003, // 8168
1da177e4
LT		 567
568 /* rtl8169_PHYstatus */
07d3f51f
FR		 569 TBI_Enable = 0x80,
570 TxFlowCtrl = 0x40,
571 RxFlowCtrl = 0x20,
572 _1000bpsF = 0x10,
573 _100bps = 0x08,
574 _10bps = 0x04,
575 LinkStatus = 0x02,
576 FullDup = 0x01,
1da177e4 577
1da177e4 578 /* _TBICSRBit */
07d3f51f 579 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 580
581 /* DumpCounterCommand */
07d3f51f 582 CounterDump = 0x8,
1da177e4
LT		 583};
584
2b7b4318
FR		 585enum rtl_desc_bit {
586 /* First doubleword. */
1da177e4
LT		 587 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
588 RingEnd = (1 << 30), /* End of descriptor ring */
589 FirstFrag = (1 << 29), /* First segment of a packet */
590 LastFrag = (1 << 28), /* Final segment of a packet */
2b7b4318
FR		 591};
592
593/* Generic case. */
594enum rtl_tx_desc_bit {
595 /* First doubleword. */
596 TD_LSO = (1 << 27), /* Large Send Offload */
597#define TD_MSS_MAX 0x07ffu /* MSS value */
1da177e4 598
2b7b4318
FR		 599 /* Second doubleword. */
600 TxVlanTag = (1 << 17), /* Add VLAN tag */
601};
602
603/* 8169, 8168b and 810x except 8102e. */
604enum rtl_tx_desc_bit_0 {
605 /* First doubleword. */
606#define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
607 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
608 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
609 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
610};
611
612/* 8102e, 8168c and beyond. */
613enum rtl_tx_desc_bit_1 {
614 /* Second doubleword. */
615#define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
616 TD1_IP_CS = (1 << 29), /* Calculate IP checksum */
617 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
618 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
619};
1da177e4 620
2b7b4318
FR		 621static const struct rtl_tx_desc_info {
622 struct {
623 u32 udp;
624 u32 tcp;
625 } checksum;
626 u16 mss_shift;
627 u16 opts_offset;
628} tx_desc_info [] = {
629 [RTL_TD_0] = {
630 .checksum = {
631 .udp = TD0_IP_CS | TD0_UDP_CS,
632 .tcp = TD0_IP_CS | TD0_TCP_CS
633 },
634 .mss_shift = TD0_MSS_SHIFT,
635 .opts_offset = 0
636 },
637 [RTL_TD_1] = {
638 .checksum = {
639 .udp = TD1_IP_CS | TD1_UDP_CS,
640 .tcp = TD1_IP_CS | TD1_TCP_CS
641 },
642 .mss_shift = TD1_MSS_SHIFT,
643 .opts_offset = 1
644 }
645};
646
647enum rtl_rx_desc_bit {
1da177e4
LT		 648 /* Rx private */
649 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
650 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
651
652#define RxProtoUDP (PID1)
653#define RxProtoTCP (PID0)
654#define RxProtoIP (PID1 | PID0)
655#define RxProtoMask RxProtoIP
656
657 IPFail = (1 << 16), /* IP checksum failed */
658 UDPFail = (1 << 15), /* UDP/IP checksum failed */
659 TCPFail = (1 << 14), /* TCP/IP checksum failed */
660 RxVlanTag = (1 << 16), /* VLAN tag available */
661};
662
663#define RsvdMask 0x3fffc000
664
665struct TxDesc {
6cccd6e7
REB		 666 __le32 opts1;
667 __le32 opts2;
668 __le64 addr;
1da177e4
LT		 669};
670
671struct RxDesc {
6cccd6e7
REB		 672 __le32 opts1;
673 __le32 opts2;
674 __le64 addr;
1da177e4
LT		 675};
676
677struct ring_info {
678 struct sk_buff *skb;
679 u32 len;
680 u8 __pad[sizeof(void *) - sizeof(u32)];
681};
682
f23e7fda 683enum features {
ccdffb9a
FR		 684 RTL_FEATURE_WOL = (1 << 0),
685 RTL_FEATURE_MSI = (1 << 1),
686 RTL_FEATURE_GMII = (1 << 2),
e0c07557 687 RTL_FEATURE_FW_LOADED = (1 << 3),
f23e7fda
FR		 688};
689
355423d0
IV		 690struct rtl8169_counters {
691 __le64 tx_packets;
692 __le64 rx_packets;
693 __le64 tx_errors;
694 __le32 rx_errors;
695 __le16 rx_missed;
696 __le16 align_errors;
697 __le32 tx_one_collision;
698 __le32 tx_multi_collision;
699 __le64 rx_unicast;
700 __le64 rx_broadcast;
701 __le32 rx_multicast;
702 __le16 tx_aborted;
703 __le16 tx_underun;
704};
705
da78dbff 706enum rtl_flag {
6c4a70c5 707 RTL_FLAG_TASK_ENABLED,
da78dbff
FR		 708 RTL_FLAG_TASK_SLOW_PENDING,
709 RTL_FLAG_TASK_RESET_PENDING,
710 RTL_FLAG_TASK_PHY_PENDING,
711 RTL_FLAG_MAX
712};
713
8027aa24
JW		 714struct rtl8169_stats {
715 u64 packets;
716 u64 bytes;
717 struct u64_stats_sync syncp;
718};
719
1da177e4
LT		 720struct rtl8169_private {
721 void __iomem *mmio_addr; /* memory map physical address */
cecb5fd7 722 struct pci_dev *pci_dev;
c4028958 723 struct net_device *dev;
bea3348e 724 struct napi_struct napi;
b57b7e5a 725 u32 msg_enable;
2b7b4318
FR		 726 u16 txd_version;
727 u16 mac_version;
1da177e4
LT		 728 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
729 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
730 u32 dirty_rx;
731 u32 dirty_tx;
8027aa24
JW		 732 struct rtl8169_stats rx_stats;
733 struct rtl8169_stats tx_stats;
1da177e4
LT		 734 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
735 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
736 dma_addr_t TxPhyAddr;
737 dma_addr_t RxPhyAddr;
6f0333b8 738 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
1da177e4 739 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
1da177e4
LT		 740 struct timer_list timer;
741 u16 cp_cmd;
da78dbff
FR		 742
743 u16 event_slow;
c0e45c1c 744
745 struct mdio_ops {
24192210
FR		 746 void (*write)(struct rtl8169_private *, int, int);
747 int (*read)(struct rtl8169_private *, int);
c0e45c1c 748 } mdio_ops;
749
065c27c1 750 struct pll_power_ops {
751 void (*down)(struct rtl8169_private *);
752 void (*up)(struct rtl8169_private *);
753 } pll_power_ops;
754
d58d46b5
FR		 755 struct jumbo_ops {
756 void (*enable)(struct rtl8169_private *);
757 void (*disable)(struct rtl8169_private *);
758 } jumbo_ops;
759
beb1fe18 760 struct csi_ops {
52989f0e
FR		 761 void (*write)(struct rtl8169_private *, int, int);
762 u32 (*read)(struct rtl8169_private *, int);
beb1fe18
HW		 763 } csi_ops;
764
54405cde 765 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
ccdffb9a 766 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
4da19633 767 void (*phy_reset_enable)(struct rtl8169_private *tp);
07ce4064 768 void (*hw_start)(struct net_device *);
4da19633 769 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
1da177e4 770 unsigned int (*link_ok)(void __iomem *);
8b4ab28d 771 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
4422bcd4
FR		 772
773 struct {
da78dbff
FR		 774 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
775 struct mutex mutex;
4422bcd4
FR		 776 struct work_struct work;
777 } wk;
778
f23e7fda 779 unsigned features;
ccdffb9a
FR		 780
781 struct mii_if_info mii;
355423d0 782 struct rtl8169_counters counters;
e1759441 783 u32 saved_wolopts;
e03f33af 784 u32 opts1_mask;
f1e02ed1 785
b6ffd97f
FR		 786 struct rtl_fw {
787 const struct firmware *fw;
1c361efb
FR		 788
789#define RTL_VER_SIZE 32
790
791 char version[RTL_VER_SIZE];
792
793 struct rtl_fw_phy_action {
794 __le32 *code;
795 size_t size;
796 } phy_action;
b6ffd97f 797 } *rtl_fw;
497888cf 798#define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
c558386b
HW		 799
800 u32 ocp_base;
1da177e4
LT		 801};
802
979b6c13 803MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 804MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 805module_param(use_dac, int, 0);
4300e8c7 806MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 807module_param_named(debug, debug.msg_enable, int, 0);
808MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 809MODULE_LICENSE("GPL");
810MODULE_VERSION(RTL8169_VERSION);
bca03d5f 811MODULE_FIRMWARE(FIRMWARE_8168D_1);
812MODULE_FIRMWARE(FIRMWARE_8168D_2);
01dc7fec 813MODULE_FIRMWARE(FIRMWARE_8168E_1);
814MODULE_FIRMWARE(FIRMWARE_8168E_2);
bbb8af75 815MODULE_FIRMWARE(FIRMWARE_8168E_3);
5a5e4443 816MODULE_FIRMWARE(FIRMWARE_8105E_1);
c2218925
HW		 817MODULE_FIRMWARE(FIRMWARE_8168F_1);
818MODULE_FIRMWARE(FIRMWARE_8168F_2);
7e18dca1 819MODULE_FIRMWARE(FIRMWARE_8402_1);
b3d7b2f2 820MODULE_FIRMWARE(FIRMWARE_8411_1);
5598bfe5 821MODULE_FIRMWARE(FIRMWARE_8106E_1);
c558386b 822MODULE_FIRMWARE(FIRMWARE_8168G_1);
1da177e4 823
da78dbff
FR		 824static void rtl_lock_work(struct rtl8169_private *tp)
825{
826 mutex_lock(&tp->wk.mutex);
827}
828
829static void rtl_unlock_work(struct rtl8169_private *tp)
830{
831 mutex_unlock(&tp->wk.mutex);
832}
833
d58d46b5
FR		 834static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
835{
7d7903b2
JL		 836 pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
837 PCI_EXP_DEVCTL_READRQ, force);
d58d46b5
FR		 838}
839
ffc46952
FR		 840struct rtl_cond {
841 bool (*check)(struct rtl8169_private *);
842 const char *msg;
843};
844
845static void rtl_udelay(unsigned int d)
846{
847 udelay(d);
848}
849
850static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
851 void (*delay)(unsigned int), unsigned int d, int n,
852 bool high)
853{
854 int i;
855
856 for (i = 0; i < n; i++) {
857 delay(d);
858 if (c->check(tp) == high)
859 return true;
860 }
82e316ef
FR		 861 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
862 c->msg, !high, n, d);
ffc46952
FR		 863 return false;
864}
865
866static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
867 const struct rtl_cond *c,
868 unsigned int d, int n)
869{
870 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
871}
872
873static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
874 const struct rtl_cond *c,
875 unsigned int d, int n)
876{
877 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
878}
879
880static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
881 const struct rtl_cond *c,
882 unsigned int d, int n)
883{
884 return rtl_loop_wait(tp, c, msleep, d, n, true);
885}
886
887static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
888 const struct rtl_cond *c,
889 unsigned int d, int n)
890{
891 return rtl_loop_wait(tp, c, msleep, d, n, false);
892}
893
894#define DECLARE_RTL_COND(name) \
895static bool name ## _check(struct rtl8169_private *); \
896 \
897static const struct rtl_cond name = { \
898 .check = name ## _check, \
899 .msg = #name \
900}; \
901 \
902static bool name ## _check(struct rtl8169_private *tp)
903
904DECLARE_RTL_COND(rtl_ocpar_cond)
905{
906 void __iomem *ioaddr = tp->mmio_addr;
907
908 return RTL_R32(OCPAR) & OCPAR_FLAG;
909}
910
b646d900 911static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
912{
913 void __iomem *ioaddr = tp->mmio_addr;
b646d900 914
915 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
ffc46952
FR		 916
917 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
918 RTL_R32(OCPDR) : ~0;
b646d900 919}
920
921static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
922{
923 void __iomem *ioaddr = tp->mmio_addr;
b646d900 924
925 RTL_W32(OCPDR, data);
926 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
ffc46952
FR		 927
928 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
929}
930
931DECLARE_RTL_COND(rtl_eriar_cond)
932{
933 void __iomem *ioaddr = tp->mmio_addr;
934
935 return RTL_R32(ERIAR) & ERIAR_FLAG;
b646d900 936}
937
fac5b3ca 938static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
b646d900 939{
fac5b3ca 940 void __iomem *ioaddr = tp->mmio_addr;
b646d900 941
942 RTL_W8(ERIDR, cmd);
943 RTL_W32(ERIAR, 0x800010e8);
944 msleep(2);
ffc46952
FR		 945
946 if (!rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 5))
947 return;
b646d900 948
fac5b3ca 949 ocp_write(tp, 0x1, 0x30, 0x00000001);
b646d900 950}
951
952#define OOB_CMD_RESET 0x00
953#define OOB_CMD_DRIVER_START 0x05
954#define OOB_CMD_DRIVER_STOP 0x06
955
cecb5fd7
FR		 956static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
957{
958 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
959}
960
ffc46952 961DECLARE_RTL_COND(rtl_ocp_read_cond)
b646d900 962{
cecb5fd7 963 u16 reg;
b646d900 964
cecb5fd7 965 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 966
ffc46952 967 return ocp_read(tp, 0x0f, reg) & 0x00000800;
b646d900 968}
969
ffc46952 970static void rtl8168_driver_start(struct rtl8169_private *tp)
b646d900 971{
ffc46952 972 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
b646d900 973
ffc46952
FR		 974 rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
975}
b646d900 976
ffc46952
FR		 977static void rtl8168_driver_stop(struct rtl8169_private *tp)
978{
979 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
4804b3b3 980
ffc46952 981 rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
b646d900 982}
983
4804b3b3 984static int r8168dp_check_dash(struct rtl8169_private *tp)
985{
cecb5fd7 986 u16 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 987
cecb5fd7 988 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
4804b3b3 989}
b646d900 990
c558386b
HW		 991static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
992{
993 if (reg & 0xffff0001) {
994 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
995 return true;
996 }
997 return false;
998}
999
1000DECLARE_RTL_COND(rtl_ocp_gphy_cond)
1001{
1002 void __iomem *ioaddr = tp->mmio_addr;
1003
1004 return RTL_R32(GPHY_OCP) & OCPAR_FLAG;
1005}
1006
1007static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1008{
1009 void __iomem *ioaddr = tp->mmio_addr;
1010
1011 if (rtl_ocp_reg_failure(tp, reg))
1012 return;
1013
1014 RTL_W32(GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
1015
1016 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
1017}
1018
1019static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
1020{
1021 void __iomem *ioaddr = tp->mmio_addr;
1022
1023 if (rtl_ocp_reg_failure(tp, reg))
1024 return 0;
1025
1026 RTL_W32(GPHY_OCP, reg << 15);
1027
1028 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
1029 (RTL_R32(GPHY_OCP) & 0xffff) : ~0;
1030}
1031
1032static void rtl_w1w0_phy_ocp(struct rtl8169_private *tp, int reg, int p, int m)
1033{
1034 int val;
1035
1036 val = r8168_phy_ocp_read(tp, reg);
1037 r8168_phy_ocp_write(tp, reg, (val | p) & ~m);
1038}
1039
c558386b
HW		 1040static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1041{
1042 void __iomem *ioaddr = tp->mmio_addr;
1043
1044 if (rtl_ocp_reg_failure(tp, reg))
1045 return;
1046
1047 RTL_W32(OCPDR, OCPAR_FLAG | (reg << 15) | data);
c558386b
HW		 1048}
1049
1050static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1051{
1052 void __iomem *ioaddr = tp->mmio_addr;
1053
1054 if (rtl_ocp_reg_failure(tp, reg))
1055 return 0;
1056
1057 RTL_W32(OCPDR, reg << 15);
1058
3a83ad12 1059 return RTL_R32(OCPDR);
c558386b
HW		 1060}
1061
1062#define OCP_STD_PHY_BASE 0xa400
1063
1064static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
1065{
1066 if (reg == 0x1f) {
1067 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
1068 return;
1069 }
1070
1071 if (tp->ocp_base != OCP_STD_PHY_BASE)
1072 reg -= 0x10;
1073
1074 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
1075}
1076
1077static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1078{
1079 if (tp->ocp_base != OCP_STD_PHY_BASE)
1080 reg -= 0x10;
1081
1082 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
1083}
1084
ffc46952
FR		 1085DECLARE_RTL_COND(rtl_phyar_cond)
1086{
1087 void __iomem *ioaddr = tp->mmio_addr;
1088
1089 return RTL_R32(PHYAR) & 0x80000000;
1090}
1091
24192210 1092static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1da177e4 1093{
24192210 1094 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 1095
24192210 1096 RTL_W32(PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1da177e4 1097
ffc46952 1098 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
024a07ba 1099 /*
81a95f04
TT		 1100 * According to hardware specs a 20us delay is required after write
1101 * complete indication, but before sending next command.
024a07ba 1102 */
81a95f04 1103 udelay(20);
1da177e4
LT		 1104}
1105
24192210 1106static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1da177e4 1107{
24192210 1108 void __iomem *ioaddr = tp->mmio_addr;
ffc46952 1109 int value;
1da177e4 1110
24192210 1111 RTL_W32(PHYAR, 0x0 | (reg & 0x1f) << 16);
1da177e4 1112
ffc46952
FR		 1113 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1114 RTL_R32(PHYAR) & 0xffff : ~0;
1115
81a95f04
TT		 1116 /*
1117 * According to hardware specs a 20us delay is required after read
1118 * complete indication, but before sending next command.
1119 */
1120 udelay(20);
1121
1da177e4
LT		 1122 return value;
1123}
1124
24192210 1125static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
c0e45c1c 1126{
24192210 1127 void __iomem *ioaddr = tp->mmio_addr;
c0e45c1c 1128
24192210 1129 RTL_W32(OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
c0e45c1c 1130 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
1131 RTL_W32(EPHY_RXER_NUM, 0);
1132
ffc46952 1133 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
c0e45c1c 1134}
1135
24192210 1136static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
c0e45c1c 1137{
24192210
FR		 1138 r8168dp_1_mdio_access(tp, reg,
1139 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
c0e45c1c 1140}
1141
24192210 1142static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
c0e45c1c 1143{
24192210 1144 void __iomem *ioaddr = tp->mmio_addr;
c0e45c1c 1145
24192210 1146 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
c0e45c1c 1147
1148 mdelay(1);
1149 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
1150 RTL_W32(EPHY_RXER_NUM, 0);
1151
ffc46952
FR		 1152 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1153 RTL_R32(OCPDR) & OCPDR_DATA_MASK : ~0;
c0e45c1c 1154}
1155
e6de30d6 1156#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1157
1158static void r8168dp_2_mdio_start(void __iomem *ioaddr)
1159{
1160 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1161}
1162
1163static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
1164{
1165 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1166}
1167
24192210 1168static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
e6de30d6 1169{
24192210
FR		 1170 void __iomem *ioaddr = tp->mmio_addr;
1171
e6de30d6 1172 r8168dp_2_mdio_start(ioaddr);
1173
24192210 1174 r8169_mdio_write(tp, reg, value);
e6de30d6 1175
1176 r8168dp_2_mdio_stop(ioaddr);
1177}
1178
24192210 1179static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
e6de30d6 1180{
24192210 1181 void __iomem *ioaddr = tp->mmio_addr;
e6de30d6 1182 int value;
1183
1184 r8168dp_2_mdio_start(ioaddr);
1185
24192210 1186 value = r8169_mdio_read(tp, reg);
e6de30d6 1187
1188 r8168dp_2_mdio_stop(ioaddr);
1189
1190 return value;
1191}
1192
4da19633 1193static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
dacf8154 1194{
24192210 1195 tp->mdio_ops.write(tp, location, val);
dacf8154
FR		 1196}
1197
4da19633 1198static int rtl_readphy(struct rtl8169_private *tp, int location)
1199{
24192210 1200 return tp->mdio_ops.read(tp, location);
4da19633 1201}
1202
1203static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1204{
1205 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1206}
1207
1208static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
daf9df6d 1209{
1210 int val;
1211
4da19633 1212 val = rtl_readphy(tp, reg_addr);
1213 rtl_writephy(tp, reg_addr, (val | p) & ~m);
daf9df6d 1214}
1215
ccdffb9a
FR		 1216static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1217 int val)
1218{
1219 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1220
4da19633 1221 rtl_writephy(tp, location, val);
ccdffb9a
FR		 1222}
1223
1224static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1225{
1226 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1227
4da19633 1228 return rtl_readphy(tp, location);
ccdffb9a
FR		 1229}
1230
ffc46952
FR		 1231DECLARE_RTL_COND(rtl_ephyar_cond)
1232{
1233 void __iomem *ioaddr = tp->mmio_addr;
1234
1235 return RTL_R32(EPHYAR) & EPHYAR_FLAG;
1236}
1237
fdf6fc06 1238static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
dacf8154 1239{
fdf6fc06 1240 void __iomem *ioaddr = tp->mmio_addr;
dacf8154
FR		 1241
1242 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1243 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1244
ffc46952
FR		 1245 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1246
1247 udelay(10);
dacf8154
FR		 1248}
1249
fdf6fc06 1250static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
dacf8154 1251{
fdf6fc06 1252 void __iomem *ioaddr = tp->mmio_addr;
dacf8154
FR		 1253
1254 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1255
ffc46952
FR		 1256 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1257 RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0;
dacf8154
FR		 1258}
1259
fdf6fc06
FR		 1260static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1261 u32 val, int type)
133ac40a 1262{
fdf6fc06 1263 void __iomem *ioaddr = tp->mmio_addr;
133ac40a
HW		 1264
1265 BUG_ON((addr & 3) || (mask == 0));
1266 RTL_W32(ERIDR, val);
1267 RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1268
ffc46952 1269 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
133ac40a
HW		 1270}
1271
fdf6fc06 1272static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
133ac40a 1273{
fdf6fc06 1274 void __iomem *ioaddr = tp->mmio_addr;
133ac40a
HW		 1275
1276 RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1277
ffc46952
FR		 1278 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1279 RTL_R32(ERIDR) : ~0;
133ac40a
HW		 1280}
1281
fdf6fc06
FR		 1282static void rtl_w1w0_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1283 u32 m, int type)
133ac40a
HW		 1284{
1285 u32 val;
1286
fdf6fc06
FR		 1287 val = rtl_eri_read(tp, addr, type);
1288 rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
133ac40a
HW		 1289}
1290
c28aa385 1291struct exgmac_reg {
1292 u16 addr;
1293 u16 mask;
1294 u32 val;
1295};
1296
fdf6fc06 1297static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
c28aa385 1298 const struct exgmac_reg *r, int len)
1299{
1300 while (len-- > 0) {
fdf6fc06 1301 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
c28aa385 1302 r++;
1303 }
1304}
1305
ffc46952
FR		 1306DECLARE_RTL_COND(rtl_efusear_cond)
1307{
1308 void __iomem *ioaddr = tp->mmio_addr;
1309
1310 return RTL_R32(EFUSEAR) & EFUSEAR_FLAG;
1311}
1312
fdf6fc06 1313static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
daf9df6d 1314{
fdf6fc06 1315 void __iomem *ioaddr = tp->mmio_addr;
daf9df6d 1316
1317 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1318
ffc46952
FR		 1319 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1320 RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
daf9df6d 1321}
1322
9085cdfa
FR		 1323static u16 rtl_get_events(struct rtl8169_private *tp)
1324{
1325 void __iomem *ioaddr = tp->mmio_addr;
1326
1327 return RTL_R16(IntrStatus);
1328}
1329
1330static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1331{
1332 void __iomem *ioaddr = tp->mmio_addr;
1333
1334 RTL_W16(IntrStatus, bits);
1335 mmiowb();
1336}
1337
1338static void rtl_irq_disable(struct rtl8169_private *tp)
1339{
1340 void __iomem *ioaddr = tp->mmio_addr;
1341
1342 RTL_W16(IntrMask, 0);
1343 mmiowb();
1344}
1345
3e990ff5
FR		 1346static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1347{
1348 void __iomem *ioaddr = tp->mmio_addr;
1349
1350 RTL_W16(IntrMask, bits);
1351}
1352
da78dbff
FR		 1353#define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1354#define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1355#define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1356
1357static void rtl_irq_enable_all(struct rtl8169_private *tp)
1358{
1359 rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1360}
1361
811fd301 1362static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1da177e4 1363{
811fd301 1364 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 1365
9085cdfa 1366 rtl_irq_disable(tp);
da78dbff 1367 rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
811fd301 1368 RTL_R8(ChipCmd);
1da177e4
LT		 1369}
1370
4da19633 1371static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1da177e4 1372{
4da19633 1373 void __iomem *ioaddr = tp->mmio_addr;
1374
1da177e4
LT		 1375 return RTL_R32(TBICSR) & TBIReset;
1376}
1377
4da19633 1378static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1da177e4 1379{
4da19633 1380 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 1381}
1382
1383static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1384{
1385 return RTL_R32(TBICSR) & TBILinkOk;
1386}
1387
1388static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1389{
1390 return RTL_R8(PHYstatus) & LinkStatus;
1391}
1392
4da19633 1393static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1da177e4 1394{
4da19633 1395 void __iomem *ioaddr = tp->mmio_addr;
1396
1da177e4
LT		 1397 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1398}
1399
4da19633 1400static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1da177e4
LT		 1401{
1402 unsigned int val;
1403
4da19633 1404 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1405 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1da177e4
LT		 1406}
1407
70090424
HW		 1408static void rtl_link_chg_patch(struct rtl8169_private *tp)
1409{
1410 void __iomem *ioaddr = tp->mmio_addr;
1411 struct net_device *dev = tp->dev;
1412
1413 if (!netif_running(dev))
1414 return;
1415
b3d7b2f2
HW		 1416 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1417 tp->mac_version == RTL_GIGA_MAC_VER_38) {
70090424 1418 if (RTL_R8(PHYstatus) & _1000bpsF) {
fdf6fc06
FR		 1419 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1420 ERIAR_EXGMAC);
1421 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1422 ERIAR_EXGMAC);
70090424 1423 } else if (RTL_R8(PHYstatus) & _100bps) {
fdf6fc06
FR		 1424 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1425 ERIAR_EXGMAC);
1426 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1427 ERIAR_EXGMAC);
70090424 1428 } else {
fdf6fc06
FR		 1429 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1430 ERIAR_EXGMAC);
1431 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1432 ERIAR_EXGMAC);
70090424
HW		 1433 }
1434 /* Reset packet filter */
fdf6fc06 1435 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
70090424 1436 ERIAR_EXGMAC);
fdf6fc06 1437 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
70090424 1438 ERIAR_EXGMAC);
c2218925
HW		 1439 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1440 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1441 if (RTL_R8(PHYstatus) & _1000bpsF) {
fdf6fc06
FR		 1442 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1443 ERIAR_EXGMAC);
1444 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1445 ERIAR_EXGMAC);
c2218925 1446 } else {
fdf6fc06
FR		 1447 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1448 ERIAR_EXGMAC);
1449 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1450 ERIAR_EXGMAC);
c2218925 1451 }
7e18dca1
HW		 1452 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1453 if (RTL_R8(PHYstatus) & _10bps) {
fdf6fc06
FR		 1454 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1455 ERIAR_EXGMAC);
1456 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1457 ERIAR_EXGMAC);
7e18dca1 1458 } else {
fdf6fc06
FR		 1459 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1460 ERIAR_EXGMAC);
7e18dca1 1461 }
70090424
HW		 1462 }
1463}
1464
e4fbce74 1465static void __rtl8169_check_link_status(struct net_device *dev,
cecb5fd7
FR		 1466 struct rtl8169_private *tp,
1467 void __iomem *ioaddr, bool pm)
1da177e4 1468{
1da177e4 1469 if (tp->link_ok(ioaddr)) {
70090424 1470 rtl_link_chg_patch(tp);
e1759441 1471 /* This is to cancel a scheduled suspend if there's one. */
e4fbce74
RW		 1472 if (pm)
1473 pm_request_resume(&tp->pci_dev->dev);
1da177e4 1474 netif_carrier_on(dev);
1519e57f
FR		 1475 if (net_ratelimit())
1476 netif_info(tp, ifup, dev, "link up\n");
b57b7e5a 1477 } else {
1da177e4 1478 netif_carrier_off(dev);
bf82c189 1479 netif_info(tp, ifdown, dev, "link down\n");
e4fbce74 1480 if (pm)
10953db8 1481 pm_schedule_suspend(&tp->pci_dev->dev, 5000);
b57b7e5a 1482 }
1da177e4
LT		 1483}
1484
e4fbce74
RW		 1485static void rtl8169_check_link_status(struct net_device *dev,
1486 struct rtl8169_private *tp,
1487 void __iomem *ioaddr)
1488{
1489 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1490}
1491
e1759441
RW		 1492#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1493
1494static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
61a4dcc2 1495{
61a4dcc2
FR		 1496 void __iomem *ioaddr = tp->mmio_addr;
1497 u8 options;
e1759441 1498 u32 wolopts = 0;
61a4dcc2
FR		 1499
1500 options = RTL_R8(Config1);
1501 if (!(options & PMEnable))
e1759441 1502 return 0;
61a4dcc2
FR		 1503
1504 options = RTL_R8(Config3);
1505 if (options & LinkUp)
e1759441 1506 wolopts |= WAKE_PHY;
61a4dcc2 1507 if (options & MagicPacket)
e1759441 1508 wolopts |= WAKE_MAGIC;
61a4dcc2
FR		 1509
1510 options = RTL_R8(Config5);
1511 if (options & UWF)
e1759441 1512 wolopts |= WAKE_UCAST;
61a4dcc2 1513 if (options & BWF)
e1759441 1514 wolopts |= WAKE_BCAST;
61a4dcc2 1515 if (options & MWF)
e1759441 1516 wolopts |= WAKE_MCAST;
61a4dcc2 1517
e1759441 1518 return wolopts;
61a4dcc2
FR		 1519}
1520
e1759441 1521static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
61a4dcc2
FR		 1522{
1523 struct rtl8169_private *tp = netdev_priv(dev);
e1759441 1524
da78dbff 1525 rtl_lock_work(tp);
e1759441
RW		 1526
1527 wol->supported = WAKE_ANY;
1528 wol->wolopts = __rtl8169_get_wol(tp);
1529
da78dbff 1530 rtl_unlock_work(tp);
e1759441
RW		 1531}
1532
1533static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1534{
61a4dcc2 1535 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1536 unsigned int i;
350f7596 1537 static const struct {
61a4dcc2
FR		 1538 u32 opt;
1539 u16 reg;
1540 u8 mask;
1541 } cfg[] = {
61a4dcc2
FR		 1542 { WAKE_PHY, Config3, LinkUp },
1543 { WAKE_MAGIC, Config3, MagicPacket },
1544 { WAKE_UCAST, Config5, UWF },
1545 { WAKE_BCAST, Config5, BWF },
1546 { WAKE_MCAST, Config5, MWF },
1547 { WAKE_ANY, Config5, LanWake }
1548 };
851e6022 1549 u8 options;
61a4dcc2 1550
61a4dcc2
FR		 1551 RTL_W8(Cfg9346, Cfg9346_Unlock);
1552
1553 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
851e6022 1554 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
e1759441 1555 if (wolopts & cfg[i].opt)
61a4dcc2
FR		 1556 options |= cfg[i].mask;
1557 RTL_W8(cfg[i].reg, options);
1558 }
1559
851e6022
FR		 1560 switch (tp->mac_version) {
1561 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1562 options = RTL_R8(Config1) & ~PMEnable;
1563 if (wolopts)
1564 options |= PMEnable;
1565 RTL_W8(Config1, options);
1566 break;
1567 default:
d387b427
FR		 1568 options = RTL_R8(Config2) & ~PME_SIGNAL;
1569 if (wolopts)
1570 options |= PME_SIGNAL;
1571 RTL_W8(Config2, options);
851e6022
FR		 1572 break;
1573 }
1574
61a4dcc2 1575 RTL_W8(Cfg9346, Cfg9346_Lock);
e1759441
RW		 1576}
1577
1578static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1579{
1580 struct rtl8169_private *tp = netdev_priv(dev);
1581
da78dbff 1582 rtl_lock_work(tp);
61a4dcc2 1583
f23e7fda
FR		 1584 if (wol->wolopts)
1585 tp->features |= RTL_FEATURE_WOL;
1586 else
1587 tp->features &= ~RTL_FEATURE_WOL;
e1759441 1588 __rtl8169_set_wol(tp, wol->wolopts);
da78dbff
FR		 1589
1590 rtl_unlock_work(tp);
61a4dcc2 1591
ea80907f 1592 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1593
61a4dcc2
FR		 1594 return 0;
1595}
1596
31bd204f
FR		 1597static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1598{
85bffe6c 1599 return rtl_chip_infos[tp->mac_version].fw_name;
31bd204f
FR		 1600}
1601
1da177e4
LT		 1602static void rtl8169_get_drvinfo(struct net_device *dev,
1603 struct ethtool_drvinfo *info)
1604{
1605 struct rtl8169_private *tp = netdev_priv(dev);
b6ffd97f 1606 struct rtl_fw *rtl_fw = tp->rtl_fw;
1da177e4 1607
68aad78c
RJ		 1608 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1609 strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1610 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1c361efb 1611 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
8ac72d16
RJ		 1612 if (!IS_ERR_OR_NULL(rtl_fw))
1613 strlcpy(info->fw_version, rtl_fw->version,
1614 sizeof(info->fw_version));
1da177e4
LT		 1615}
1616
1617static int rtl8169_get_regs_len(struct net_device *dev)
1618{
1619 return R8169_REGS_SIZE;
1620}
1621
1622static int rtl8169_set_speed_tbi(struct net_device *dev,
54405cde 1623 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1da177e4
LT		 1624{
1625 struct rtl8169_private *tp = netdev_priv(dev);
1626 void __iomem *ioaddr = tp->mmio_addr;
1627 int ret = 0;
1628 u32 reg;
1629
1630 reg = RTL_R32(TBICSR);
1631 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1632 (duplex == DUPLEX_FULL)) {
1633 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1634 } else if (autoneg == AUTONEG_ENABLE)
1635 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1636 else {
bf82c189
JP		 1637 netif_warn(tp, link, dev,
1638 "incorrect speed setting refused in TBI mode\n");
1da177e4
LT		 1639 ret = -EOPNOTSUPP;
1640 }
1641
1642 return ret;
1643}
1644
1645static int rtl8169_set_speed_xmii(struct net_device *dev,
54405cde 1646 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1da177e4
LT		 1647{
1648 struct rtl8169_private *tp = netdev_priv(dev);
3577aa1b 1649 int giga_ctrl, bmcr;
54405cde 1650 int rc = -EINVAL;
1da177e4 1651
716b50a3 1652 rtl_writephy(tp, 0x1f, 0x0000);
1da177e4
LT		 1653
1654 if (autoneg == AUTONEG_ENABLE) {
3577aa1b 1655 int auto_nego;
1656
4da19633 1657 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
54405cde
ON		 1658 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1659 ADVERTISE_100HALF | ADVERTISE_100FULL);
1660
1661 if (adv & ADVERTISED_10baseT_Half)
1662 auto_nego |= ADVERTISE_10HALF;
1663 if (adv & ADVERTISED_10baseT_Full)
1664 auto_nego |= ADVERTISE_10FULL;
1665 if (adv & ADVERTISED_100baseT_Half)
1666 auto_nego |= ADVERTISE_100HALF;
1667 if (adv & ADVERTISED_100baseT_Full)
1668 auto_nego |= ADVERTISE_100FULL;
1669
3577aa1b 1670 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1da177e4 1671
4da19633 1672 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
3577aa1b 1673 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
bcf0bf90 1674
3577aa1b 1675 /* The 8100e/8101e/8102e do Fast Ethernet only. */
826e6cbd 1676 if (tp->mii.supports_gmii) {
54405cde
ON		 1677 if (adv & ADVERTISED_1000baseT_Half)
1678 giga_ctrl |= ADVERTISE_1000HALF;
1679 if (adv & ADVERTISED_1000baseT_Full)
1680 giga_ctrl |= ADVERTISE_1000FULL;
1681 } else if (adv & (ADVERTISED_1000baseT_Half |
1682 ADVERTISED_1000baseT_Full)) {
bf82c189
JP		 1683 netif_info(tp, link, dev,
1684 "PHY does not support 1000Mbps\n");
54405cde 1685 goto out;
bcf0bf90 1686 }
1da177e4 1687
3577aa1b 1688 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1689
4da19633 1690 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1691 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
3577aa1b 1692 } else {
1693 giga_ctrl = 0;
1694
1695 if (speed == SPEED_10)
1696 bmcr = 0;
1697 else if (speed == SPEED_100)
1698 bmcr = BMCR_SPEED100;
1699 else
54405cde 1700 goto out;
3577aa1b 1701
1702 if (duplex == DUPLEX_FULL)
1703 bmcr |= BMCR_FULLDPLX;
2584fbc3
RS		 1704 }
1705
4da19633 1706 rtl_writephy(tp, MII_BMCR, bmcr);
3577aa1b 1707
cecb5fd7
FR		 1708 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1709 tp->mac_version == RTL_GIGA_MAC_VER_03) {
3577aa1b 1710 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
4da19633 1711 rtl_writephy(tp, 0x17, 0x2138);
1712 rtl_writephy(tp, 0x0e, 0x0260);
3577aa1b 1713 } else {
4da19633 1714 rtl_writephy(tp, 0x17, 0x2108);
1715 rtl_writephy(tp, 0x0e, 0x0000);
3577aa1b 1716 }
1717 }
1718
54405cde
ON		 1719 rc = 0;
1720out:
1721 return rc;
1da177e4
LT		 1722}
1723
1724static int rtl8169_set_speed(struct net_device *dev,
54405cde 1725 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1da177e4
LT		 1726{
1727 struct rtl8169_private *tp = netdev_priv(dev);
1728 int ret;
1729
54405cde 1730 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
4876cc1e
FR		 1731 if (ret < 0)
1732 goto out;
1da177e4 1733
4876cc1e
FR		 1734 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1735 (advertising & ADVERTISED_1000baseT_Full)) {
1da177e4 1736 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
4876cc1e
FR		 1737 }
1738out:
1da177e4
LT		 1739 return ret;
1740}
1741
1742static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1743{
1744 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4
LT		 1745 int ret;
1746
4876cc1e
FR		 1747 del_timer_sync(&tp->timer);
1748
da78dbff 1749 rtl_lock_work(tp);
cecb5fd7 1750 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
25db0338 1751 cmd->duplex, cmd->advertising);
da78dbff 1752 rtl_unlock_work(tp);
5b0384f4 1753
1da177e4
LT		 1754 return ret;
1755}
1756
c8f44aff
MM		 1757static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1758 netdev_features_t features)
1da177e4 1759{
d58d46b5
FR		 1760 struct rtl8169_private *tp = netdev_priv(dev);
1761
2b7b4318 1762 if (dev->mtu > TD_MSS_MAX)
350fb32a 1763 features &= ~NETIF_F_ALL_TSO;
1da177e4 1764
d58d46b5
FR		 1765 if (dev->mtu > JUMBO_1K &&
1766 !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1767 features &= ~NETIF_F_IP_CSUM;
1768
350fb32a 1769 return features;
1da177e4
LT		 1770}
1771
da78dbff
FR		 1772static void __rtl8169_set_features(struct net_device *dev,
1773 netdev_features_t features)
1da177e4
LT		 1774{
1775 struct rtl8169_private *tp = netdev_priv(dev);
6bbe021d 1776 netdev_features_t changed = features ^ dev->features;
da78dbff 1777 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 1778
6bbe021d
BG		 1779 if (!(changed & (NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)))
1780 return;
1da177e4 1781
6bbe021d
BG		 1782 if (changed & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)) {
1783 if (features & NETIF_F_RXCSUM)
1784 tp->cp_cmd |= RxChkSum;
1785 else
1786 tp->cp_cmd &= ~RxChkSum;
350fb32a 1787
6bbe021d
BG		 1788 if (dev->features & NETIF_F_HW_VLAN_RX)
1789 tp->cp_cmd |= RxVlan;
1790 else
1791 tp->cp_cmd &= ~RxVlan;
1792
1793 RTL_W16(CPlusCmd, tp->cp_cmd);
1794 RTL_R16(CPlusCmd);
1795 }
1796 if (changed & NETIF_F_RXALL) {
1797 int tmp = (RTL_R32(RxConfig) & ~(AcceptErr | AcceptRunt));
1798 if (features & NETIF_F_RXALL)
1799 tmp |= (AcceptErr | AcceptRunt);
1800 RTL_W32(RxConfig, tmp);
1801 }
da78dbff 1802}
1da177e4 1803
da78dbff
FR		 1804static int rtl8169_set_features(struct net_device *dev,
1805 netdev_features_t features)
1806{
1807 struct rtl8169_private *tp = netdev_priv(dev);
1808
1809 rtl_lock_work(tp);
1810 __rtl8169_set_features(dev, features);
1811 rtl_unlock_work(tp);
1da177e4
LT		 1812
1813 return 0;
1814}
1815
da78dbff 1816
1da177e4
LT		 1817static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1818 struct sk_buff *skb)
1819{
eab6d18d 1820 return (vlan_tx_tag_present(skb)) ?
1da177e4
LT		 1821 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1822}
1823
7a8fc77b 1824static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1da177e4
LT		 1825{
1826 u32 opts2 = le32_to_cpu(desc->opts2);
1da177e4 1827
7a8fc77b
FR		 1828 if (opts2 & RxVlanTag)
1829 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
2edae08e 1830
1da177e4 1831 desc->opts2 = 0;
1da177e4
LT		 1832}
1833
ccdffb9a 1834static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1835{
1836 struct rtl8169_private *tp = netdev_priv(dev);
1837 void __iomem *ioaddr = tp->mmio_addr;
1838 u32 status;
1839
1840 cmd->supported =
1841 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1842 cmd->port = PORT_FIBRE;
1843 cmd->transceiver = XCVR_INTERNAL;
1844
1845 status = RTL_R32(TBICSR);
1846 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1847 cmd->autoneg = !!(status & TBINwEnable);
1848
70739497 1849 ethtool_cmd_speed_set(cmd, SPEED_1000);
1da177e4 1850 cmd->duplex = DUPLEX_FULL; /* Always set */
ccdffb9a
FR		 1851
1852 return 0;
1da177e4
LT		 1853}
1854
ccdffb9a 1855static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1856{
1857 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a
FR		 1858
1859 return mii_ethtool_gset(&tp->mii, cmd);
1da177e4
LT		 1860}
1861
1862static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1863{
1864 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1865 int rc;
1da177e4 1866
da78dbff 1867 rtl_lock_work(tp);
ccdffb9a 1868 rc = tp->get_settings(dev, cmd);
da78dbff 1869 rtl_unlock_work(tp);
1da177e4 1870
ccdffb9a 1871 return rc;
1da177e4
LT		 1872}
1873
1874static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1875 void *p)
1876{
5b0384f4 1877 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 1878
5b0384f4
FR		 1879 if (regs->len > R8169_REGS_SIZE)
1880 regs->len = R8169_REGS_SIZE;
1da177e4 1881
da78dbff 1882 rtl_lock_work(tp);
5b0384f4 1883 memcpy_fromio(p, tp->mmio_addr, regs->len);
da78dbff 1884 rtl_unlock_work(tp);
1da177e4
LT		 1885}
1886
b57b7e5a
SH		 1887static u32 rtl8169_get_msglevel(struct net_device *dev)
1888{
1889 struct rtl8169_private *tp = netdev_priv(dev);
1890
1891 return tp->msg_enable;
1892}
1893
1894static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1895{
1896 struct rtl8169_private *tp = netdev_priv(dev);
1897
1898 tp->msg_enable = value;
1899}
1900
d4a3a0fc
SH		 1901static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1902 "tx_packets",
1903 "rx_packets",
1904 "tx_errors",
1905 "rx_errors",
1906 "rx_missed",
1907 "align_errors",
1908 "tx_single_collisions",
1909 "tx_multi_collisions",
1910 "unicast",
1911 "broadcast",
1912 "multicast",
1913 "tx_aborted",
1914 "tx_underrun",
1915};
1916
b9f2c044 1917static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1918{
b9f2c044
JG		 1919 switch (sset) {
1920 case ETH_SS_STATS:
1921 return ARRAY_SIZE(rtl8169_gstrings);
1922 default:
1923 return -EOPNOTSUPP;
1924 }
d4a3a0fc
SH		 1925}
1926
ffc46952
FR		 1927DECLARE_RTL_COND(rtl_counters_cond)
1928{
1929 void __iomem *ioaddr = tp->mmio_addr;
1930
1931 return RTL_R32(CounterAddrLow) & CounterDump;
1932}
1933
355423d0 1934static void rtl8169_update_counters(struct net_device *dev)
d4a3a0fc
SH		 1935{
1936 struct rtl8169_private *tp = netdev_priv(dev);
1937 void __iomem *ioaddr = tp->mmio_addr;
cecb5fd7 1938 struct device *d = &tp->pci_dev->dev;
d4a3a0fc
SH		 1939 struct rtl8169_counters *counters;
1940 dma_addr_t paddr;
1941 u32 cmd;
1942
355423d0
IV		 1943 /*
1944 * Some chips are unable to dump tally counters when the receiver
1945 * is disabled.
1946 */
1947 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1948 return;
d4a3a0fc 1949
48addcc9 1950 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
d4a3a0fc
SH		 1951 if (!counters)
1952 return;
1953
1954 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
284901a9 1955 cmd = (u64)paddr & DMA_BIT_MASK(32);
d4a3a0fc
SH		 1956 RTL_W32(CounterAddrLow, cmd);
1957 RTL_W32(CounterAddrLow, cmd | CounterDump);
1958
ffc46952
FR		 1959 if (rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000))
1960 memcpy(&tp->counters, counters, sizeof(*counters));
d4a3a0fc
SH		 1961
1962 RTL_W32(CounterAddrLow, 0);
1963 RTL_W32(CounterAddrHigh, 0);
1964
48addcc9 1965 dma_free_coherent(d, sizeof(*counters), counters, paddr);
d4a3a0fc
SH		 1966}
1967
355423d0
IV		 1968static void rtl8169_get_ethtool_stats(struct net_device *dev,
1969 struct ethtool_stats *stats, u64 *data)
1970{
1971 struct rtl8169_private *tp = netdev_priv(dev);
1972
1973 ASSERT_RTNL();
1974
1975 rtl8169_update_counters(dev);
1976
1977 data[0] = le64_to_cpu(tp->counters.tx_packets);
1978 data[1] = le64_to_cpu(tp->counters.rx_packets);
1979 data[2] = le64_to_cpu(tp->counters.tx_errors);
1980 data[3] = le32_to_cpu(tp->counters.rx_errors);
1981 data[4] = le16_to_cpu(tp->counters.rx_missed);
1982 data[5] = le16_to_cpu(tp->counters.align_errors);
1983 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1984 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1985 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1986 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1987 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1988 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1989 data[12] = le16_to_cpu(tp->counters.tx_underun);
1990}
1991
d4a3a0fc
SH		 1992static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1993{
1994 switch(stringset) {
1995 case ETH_SS_STATS:
1996 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1997 break;
1998 }
1999}
2000
7282d491 2001static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 2002 .get_drvinfo = rtl8169_get_drvinfo,
2003 .get_regs_len = rtl8169_get_regs_len,
2004 .get_link = ethtool_op_get_link,
2005 .get_settings = rtl8169_get_settings,
2006 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 2007 .get_msglevel = rtl8169_get_msglevel,
2008 .set_msglevel = rtl8169_set_msglevel,
1da177e4 2009 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 2010 .get_wol = rtl8169_get_wol,
2011 .set_wol = rtl8169_set_wol,
d4a3a0fc 2012 .get_strings = rtl8169_get_strings,
b9f2c044 2013 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 2014 .get_ethtool_stats = rtl8169_get_ethtool_stats,
e1593bb1 2015 .get_ts_info = ethtool_op_get_ts_info,
1da177e4
LT		 2016};
2017
07d3f51f 2018static void rtl8169_get_mac_version(struct rtl8169_private *tp,
5d320a20 2019 struct net_device *dev, u8 default_version)
1da177e4 2020{
5d320a20 2021 void __iomem *ioaddr = tp->mmio_addr;
0e485150
FR		 2022 /*
2023 * The driver currently handles the 8168Bf and the 8168Be identically
2024 * but they can be identified more specifically through the test below
2025 * if needed:
2026 *
2027 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 2028 *
2029 * Same thing for the 8101Eb and the 8101Ec:
2030 *
2031 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 2032 */
3744100e 2033 static const struct rtl_mac_info {
1da177e4 2034 u32 mask;
e3cf0cc0 2035 u32 val;
1da177e4
LT		 2036 int mac_version;
2037 } mac_info[] = {
c558386b
HW		 2038 /* 8168G family. */
2039 { 0x7cf00000, 0x4c100000, RTL_GIGA_MAC_VER_41 },
2040 { 0x7cf00000, 0x4c000000, RTL_GIGA_MAC_VER_40 },
2041
c2218925 2042 /* 8168F family. */
b3d7b2f2 2043 { 0x7c800000, 0x48800000, RTL_GIGA_MAC_VER_38 },
c2218925
HW		 2044 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
2045 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
2046
01dc7fec 2047 /* 8168E family. */
70090424 2048 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
01dc7fec 2049 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
2050 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
2051 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
2052
5b538df9 2053 /* 8168D family. */
daf9df6d 2054 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
2055 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
daf9df6d 2056 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
5b538df9 2057
e6de30d6 2058 /* 8168DP family. */
2059 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
2060 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
4804b3b3 2061 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
e6de30d6 2062
ef808d50 2063 /* 8168C family. */
17c99297 2064 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
ef3386f0 2065 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 2066 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 2067 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 2068 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
2069 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 2070 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
6fb07058 2071 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
ef808d50 2072 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 2073
2074 /* 8168B family. */
2075 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
2076 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
2077 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
2078 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
2079
2080 /* 8101 family. */
5598bfe5
HW		 2081 { 0x7cf00000, 0x44900000, RTL_GIGA_MAC_VER_39 },
2082 { 0x7c800000, 0x44800000, RTL_GIGA_MAC_VER_39 },
7e18dca1 2083 { 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37 },
36a0e6c2 2084 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
5a5e4443
HW		 2085 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
2086 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
2087 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2857ffb7
FR		 2088 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
2089 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
2090 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
2091 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
2092 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
2093 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 2094 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 2095 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 2096 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 2097 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
2098 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 2099 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
2100 /* FIXME: where did these entries come from ? -- FR */
2101 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
2102 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
2103
2104 /* 8110 family. */
2105 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
2106 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
2107 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
2108 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
2109 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
2110 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
2111
f21b75e9
JD		 2112 /* Catch-all */
2113 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
3744100e
FR		 2114 };
2115 const struct rtl_mac_info *p = mac_info;
1da177e4
LT		 2116 u32 reg;
2117
e3cf0cc0
FR		 2118 reg = RTL_R32(TxConfig);
2119 while ((reg & p->mask) != p->val)
1da177e4
LT		 2120 p++;
2121 tp->mac_version = p->mac_version;
5d320a20
FR		 2122
2123 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2124 netif_notice(tp, probe, dev,
2125 "unknown MAC, using family default\n");
2126 tp->mac_version = default_version;
2127 }
1da177e4
LT		 2128}
2129
2130static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2131{
bcf0bf90 2132 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 2133}
2134
867763c1
FR		 2135struct phy_reg {
2136 u16 reg;
2137 u16 val;
2138};
2139
4da19633 2140static void rtl_writephy_batch(struct rtl8169_private *tp,
2141 const struct phy_reg *regs, int len)
867763c1
FR		 2142{
2143 while (len-- > 0) {
4da19633 2144 rtl_writephy(tp, regs->reg, regs->val);
867763c1
FR		 2145 regs++;
2146 }
2147}
2148
bca03d5f 2149#define PHY_READ 0x00000000
2150#define PHY_DATA_OR 0x10000000
2151#define PHY_DATA_AND 0x20000000
2152#define PHY_BJMPN 0x30000000
2153#define PHY_READ_EFUSE 0x40000000
2154#define PHY_READ_MAC_BYTE 0x50000000
2155#define PHY_WRITE_MAC_BYTE 0x60000000
2156#define PHY_CLEAR_READCOUNT 0x70000000
2157#define PHY_WRITE 0x80000000
2158#define PHY_READCOUNT_EQ_SKIP 0x90000000
2159#define PHY_COMP_EQ_SKIPN 0xa0000000
2160#define PHY_COMP_NEQ_SKIPN 0xb0000000
2161#define PHY_WRITE_PREVIOUS 0xc0000000
2162#define PHY_SKIPN 0xd0000000
2163#define PHY_DELAY_MS 0xe0000000
2164#define PHY_WRITE_ERI_WORD 0xf0000000
2165
960aee6c
HW		 2166struct fw_info {
2167 u32 magic;
2168 char version[RTL_VER_SIZE];
2169 __le32 fw_start;
2170 __le32 fw_len;
2171 u8 chksum;
2172} __packed;
2173
1c361efb
FR		 2174#define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2175
2176static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
bca03d5f 2177{
b6ffd97f 2178 const struct firmware *fw = rtl_fw->fw;
960aee6c 2179 struct fw_info *fw_info = (struct fw_info *)fw->data;
1c361efb
FR		 2180 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2181 char *version = rtl_fw->version;
2182 bool rc = false;
2183
2184 if (fw->size < FW_OPCODE_SIZE)
2185 goto out;
960aee6c
HW		 2186
2187 if (!fw_info->magic) {
2188 size_t i, size, start;
2189 u8 checksum = 0;
2190
2191 if (fw->size < sizeof(*fw_info))
2192 goto out;
2193
2194 for (i = 0; i < fw->size; i++)
2195 checksum += fw->data[i];
2196 if (checksum != 0)
2197 goto out;
2198
2199 start = le32_to_cpu(fw_info->fw_start);
2200 if (start > fw->size)
2201 goto out;
2202
2203 size = le32_to_cpu(fw_info->fw_len);
2204 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2205 goto out;
2206
2207 memcpy(version, fw_info->version, RTL_VER_SIZE);
2208
2209 pa->code = (__le32 *)(fw->data + start);
2210 pa->size = size;
2211 } else {
1c361efb
FR		 2212 if (fw->size % FW_OPCODE_SIZE)
2213 goto out;
2214
2215 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2216
2217 pa->code = (__le32 *)fw->data;
2218 pa->size = fw->size / FW_OPCODE_SIZE;
2219 }
2220 version[RTL_VER_SIZE - 1] = 0;
2221
2222 rc = true;
2223out:
2224 return rc;
2225}
2226
fd112f2e
FR		 2227static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2228 struct rtl_fw_phy_action *pa)
1c361efb 2229{
fd112f2e 2230 bool rc = false;
1c361efb 2231 size_t index;
bca03d5f 2232
1c361efb
FR		 2233 for (index = 0; index < pa->size; index++) {
2234 u32 action = le32_to_cpu(pa->code[index]);
42b82dc1 2235 u32 regno = (action & 0x0fff0000) >> 16;
bca03d5f 2236
42b82dc1 2237 switch(action & 0xf0000000) {
2238 case PHY_READ:
2239 case PHY_DATA_OR:
2240 case PHY_DATA_AND:
2241 case PHY_READ_EFUSE:
2242 case PHY_CLEAR_READCOUNT:
2243 case PHY_WRITE:
2244 case PHY_WRITE_PREVIOUS:
2245 case PHY_DELAY_MS:
2246 break;
2247
2248 case PHY_BJMPN:
2249 if (regno > index) {
fd112f2e 2250 netif_err(tp, ifup, tp->dev,
cecb5fd7 2251 "Out of range of firmware\n");
fd112f2e 2252 goto out;
42b82dc1 2253 }
2254 break;
2255 case PHY_READCOUNT_EQ_SKIP:
1c361efb 2256 if (index + 2 >= pa->size) {
fd112f2e 2257 netif_err(tp, ifup, tp->dev,
cecb5fd7 2258 "Out of range of firmware\n");
fd112f2e 2259 goto out;
42b82dc1 2260 }
2261 break;
2262 case PHY_COMP_EQ_SKIPN:
2263 case PHY_COMP_NEQ_SKIPN:
2264 case PHY_SKIPN:
1c361efb 2265 if (index + 1 + regno >= pa->size) {
fd112f2e 2266 netif_err(tp, ifup, tp->dev,
cecb5fd7 2267 "Out of range of firmware\n");
fd112f2e 2268 goto out;
42b82dc1 2269 }
bca03d5f 2270 break;
2271
42b82dc1 2272 case PHY_READ_MAC_BYTE:
2273 case PHY_WRITE_MAC_BYTE:
2274 case PHY_WRITE_ERI_WORD:
2275 default:
fd112f2e 2276 netif_err(tp, ifup, tp->dev,
42b82dc1 2277 "Invalid action 0x%08x\n", action);
fd112f2e 2278 goto out;
bca03d5f 2279 }
2280 }
fd112f2e
FR		 2281 rc = true;
2282out:
2283 return rc;
2284}
bca03d5f 2285
fd112f2e
FR		 2286static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2287{
2288 struct net_device *dev = tp->dev;
2289 int rc = -EINVAL;
2290
2291 if (!rtl_fw_format_ok(tp, rtl_fw)) {
2292 netif_err(tp, ifup, dev, "invalid firwmare\n");
2293 goto out;
2294 }
2295
2296 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2297 rc = 0;
2298out:
2299 return rc;
2300}
2301
2302static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2303{
2304 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2305 u32 predata, count;
2306 size_t index;
2307
2308 predata = count = 0;
42b82dc1 2309
1c361efb
FR		 2310 for (index = 0; index < pa->size; ) {
2311 u32 action = le32_to_cpu(pa->code[index]);
bca03d5f 2312 u32 data = action & 0x0000ffff;
42b82dc1 2313 u32 regno = (action & 0x0fff0000) >> 16;
2314
2315 if (!action)
2316 break;
bca03d5f 2317
2318 switch(action & 0xf0000000) {
42b82dc1 2319 case PHY_READ:
2320 predata = rtl_readphy(tp, regno);
2321 count++;
2322 index++;
2323 break;
2324 case PHY_DATA_OR:
2325 predata |= data;
2326 index++;
2327 break;
2328 case PHY_DATA_AND:
2329 predata &= data;
2330 index++;
2331 break;
2332 case PHY_BJMPN:
2333 index -= regno;
2334 break;
2335 case PHY_READ_EFUSE:
fdf6fc06 2336 predata = rtl8168d_efuse_read(tp, regno);
42b82dc1 2337 index++;
2338 break;
2339 case PHY_CLEAR_READCOUNT:
2340 count = 0;
2341 index++;
2342 break;
bca03d5f 2343 case PHY_WRITE:
42b82dc1 2344 rtl_writephy(tp, regno, data);
2345 index++;
2346 break;
2347 case PHY_READCOUNT_EQ_SKIP:
cecb5fd7 2348 index += (count == data) ? 2 : 1;
bca03d5f 2349 break;
42b82dc1 2350 case PHY_COMP_EQ_SKIPN:
2351 if (predata == data)
2352 index += regno;
2353 index++;
2354 break;
2355 case PHY_COMP_NEQ_SKIPN:
2356 if (predata != data)
2357 index += regno;
2358 index++;
2359 break;
2360 case PHY_WRITE_PREVIOUS:
2361 rtl_writephy(tp, regno, predata);
2362 index++;
2363 break;
2364 case PHY_SKIPN:
2365 index += regno + 1;
2366 break;
2367 case PHY_DELAY_MS:
2368 mdelay(data);
2369 index++;
2370 break;
2371
2372 case PHY_READ_MAC_BYTE:
2373 case PHY_WRITE_MAC_BYTE:
2374 case PHY_WRITE_ERI_WORD:
bca03d5f 2375 default:
2376 BUG();
2377 }
2378 }
2379}
2380
f1e02ed1 2381static void rtl_release_firmware(struct rtl8169_private *tp)
2382{
b6ffd97f
FR		 2383 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2384 release_firmware(tp->rtl_fw->fw);
2385 kfree(tp->rtl_fw);
2386 }
2387 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
f1e02ed1 2388}
2389
953a12cc 2390static void rtl_apply_firmware(struct rtl8169_private *tp)
f1e02ed1 2391{
b6ffd97f 2392 struct rtl_fw *rtl_fw = tp->rtl_fw;
f1e02ed1 2393
2394 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
e0c07557 2395 if (!IS_ERR_OR_NULL(rtl_fw)) {
b6ffd97f 2396 rtl_phy_write_fw(tp, rtl_fw);
e0c07557 2397 tp->features |= RTL_FEATURE_FW_LOADED;
2398 }
953a12cc
FR		 2399}
2400
2401static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2402{
2403 if (rtl_readphy(tp, reg) != val)
2404 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2405 else
2406 rtl_apply_firmware(tp);
f1e02ed1 2407}
2408
e0c07557 2409static void r810x_aldps_disable(struct rtl8169_private *tp)
2410{
2411 rtl_writephy(tp, 0x1f, 0x0000);
2412 rtl_writephy(tp, 0x18, 0x0310);
2413 msleep(100);
2414}
2415
2416static void r810x_aldps_enable(struct rtl8169_private *tp)
2417{
2418 if (!(tp->features & RTL_FEATURE_FW_LOADED))
2419 return;
2420
2421 rtl_writephy(tp, 0x1f, 0x0000);
2422 rtl_writephy(tp, 0x18, 0x8310);
2423}
2424
2425static void r8168_aldps_enable_1(struct rtl8169_private *tp)
2426{
2427 if (!(tp->features & RTL_FEATURE_FW_LOADED))
2428 return;
2429
2430 rtl_writephy(tp, 0x1f, 0x0000);
2431 rtl_w1w0_phy(tp, 0x15, 0x1000, 0x0000);
2432}
2433
4da19633 2434static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1da177e4 2435{
350f7596 2436 static const struct phy_reg phy_reg_init[] = {
0b9b571d 2437 { 0x1f, 0x0001 },
2438 { 0x06, 0x006e },
2439 { 0x08, 0x0708 },
2440 { 0x15, 0x4000 },
2441 { 0x18, 0x65c7 },
1da177e4 2442
0b9b571d 2443 { 0x1f, 0x0001 },
2444 { 0x03, 0x00a1 },
2445 { 0x02, 0x0008 },
2446 { 0x01, 0x0120 },
2447 { 0x00, 0x1000 },
2448 { 0x04, 0x0800 },
2449 { 0x04, 0x0000 },
1da177e4 2450
0b9b571d 2451 { 0x03, 0xff41 },
2452 { 0x02, 0xdf60 },
2453 { 0x01, 0x0140 },
2454 { 0x00, 0x0077 },
2455 { 0x04, 0x7800 },
2456 { 0x04, 0x7000 },
2457
2458 { 0x03, 0x802f },
2459 { 0x02, 0x4f02 },
2460 { 0x01, 0x0409 },
2461 { 0x00, 0xf0f9 },
2462 { 0x04, 0x9800 },
2463 { 0x04, 0x9000 },
2464
2465 { 0x03, 0xdf01 },
2466 { 0x02, 0xdf20 },
2467 { 0x01, 0xff95 },
2468 { 0x00, 0xba00 },
2469 { 0x04, 0xa800 },
2470 { 0x04, 0xa000 },
2471
2472 { 0x03, 0xff41 },
2473 { 0x02, 0xdf20 },
2474 { 0x01, 0x0140 },
2475 { 0x00, 0x00bb },
2476 { 0x04, 0xb800 },
2477 { 0x04, 0xb000 },
2478
2479 { 0x03, 0xdf41 },
2480 { 0x02, 0xdc60 },
2481 { 0x01, 0x6340 },
2482 { 0x00, 0x007d },
2483 { 0x04, 0xd800 },
2484 { 0x04, 0xd000 },
2485
2486 { 0x03, 0xdf01 },
2487 { 0x02, 0xdf20 },
2488 { 0x01, 0x100a },
2489 { 0x00, 0xa0ff },
2490 { 0x04, 0xf800 },
2491 { 0x04, 0xf000 },
2492
2493 { 0x1f, 0x0000 },
2494 { 0x0b, 0x0000 },
2495 { 0x00, 0x9200 }
2496 };
1da177e4 2497
4da19633 2498 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1da177e4
LT		 2499}
2500
4da19633 2501static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
5615d9f1 2502{
350f7596 2503 static const struct phy_reg phy_reg_init[] = {
a441d7b6
FR		 2504 { 0x1f, 0x0002 },
2505 { 0x01, 0x90d0 },
2506 { 0x1f, 0x0000 }
2507 };
2508
4da19633 2509 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 2510}
2511
4da19633 2512static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2e955856 2513{
2514 struct pci_dev *pdev = tp->pci_dev;
2e955856 2515
ccbae55e
SS		 2516 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2517 (pdev->subsystem_device != 0xe000))
2e955856 2518 return;
2519
4da19633 2520 rtl_writephy(tp, 0x1f, 0x0001);
2521 rtl_writephy(tp, 0x10, 0xf01b);
2522 rtl_writephy(tp, 0x1f, 0x0000);
2e955856 2523}
2524
4da19633 2525static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2e955856 2526{
350f7596 2527 static const struct phy_reg phy_reg_init[] = {
2e955856 2528 { 0x1f, 0x0001 },
2529 { 0x04, 0x0000 },
2530 { 0x03, 0x00a1 },
2531 { 0x02, 0x0008 },
2532 { 0x01, 0x0120 },
2533 { 0x00, 0x1000 },
2534 { 0x04, 0x0800 },
2535 { 0x04, 0x9000 },
2536 { 0x03, 0x802f },
2537 { 0x02, 0x4f02 },
2538 { 0x01, 0x0409 },
2539 { 0x00, 0xf099 },
2540 { 0x04, 0x9800 },
2541 { 0x04, 0xa000 },
2542 { 0x03, 0xdf01 },
2543 { 0x02, 0xdf20 },
2544 { 0x01, 0xff95 },
2545 { 0x00, 0xba00 },
2546 { 0x04, 0xa800 },
2547 { 0x04, 0xf000 },
2548 { 0x03, 0xdf01 },
2549 { 0x02, 0xdf20 },
2550 { 0x01, 0x101a },
2551 { 0x00, 0xa0ff },
2552 { 0x04, 0xf800 },
2553 { 0x04, 0x0000 },
2554 { 0x1f, 0x0000 },
2555
2556 { 0x1f, 0x0001 },
2557 { 0x10, 0xf41b },
2558 { 0x14, 0xfb54 },
2559 { 0x18, 0xf5c7 },
2560 { 0x1f, 0x0000 },
2561
2562 { 0x1f, 0x0001 },
2563 { 0x17, 0x0cc0 },
2564 { 0x1f, 0x0000 }
2565 };
2566
4da19633 2567 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2e955856 2568
4da19633 2569 rtl8169scd_hw_phy_config_quirk(tp);
2e955856 2570}
2571
4da19633 2572static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
8c7006aa 2573{
350f7596 2574 static const struct phy_reg phy_reg_init[] = {
8c7006aa 2575 { 0x1f, 0x0001 },
2576 { 0x04, 0x0000 },
2577 { 0x03, 0x00a1 },
2578 { 0x02, 0x0008 },
2579 { 0x01, 0x0120 },
2580 { 0x00, 0x1000 },
2581 { 0x04, 0x0800 },
2582 { 0x04, 0x9000 },
2583 { 0x03, 0x802f },
2584 { 0x02, 0x4f02 },
2585 { 0x01, 0x0409 },
2586 { 0x00, 0xf099 },
2587 { 0x04, 0x9800 },
2588 { 0x04, 0xa000 },
2589 { 0x03, 0xdf01 },
2590 { 0x02, 0xdf20 },
2591 { 0x01, 0xff95 },
2592 { 0x00, 0xba00 },
2593 { 0x04, 0xa800 },
2594 { 0x04, 0xf000 },
2595 { 0x03, 0xdf01 },
2596 { 0x02, 0xdf20 },
2597 { 0x01, 0x101a },
2598 { 0x00, 0xa0ff },
2599 { 0x04, 0xf800 },
2600 { 0x04, 0x0000 },
2601 { 0x1f, 0x0000 },
2602
2603 { 0x1f, 0x0001 },
2604 { 0x0b, 0x8480 },
2605 { 0x1f, 0x0000 },
2606
2607 { 0x1f, 0x0001 },
2608 { 0x18, 0x67c7 },
2609 { 0x04, 0x2000 },
2610 { 0x03, 0x002f },
2611 { 0x02, 0x4360 },
2612 { 0x01, 0x0109 },
2613 { 0x00, 0x3022 },
2614 { 0x04, 0x2800 },
2615 { 0x1f, 0x0000 },
2616
2617 { 0x1f, 0x0001 },
2618 { 0x17, 0x0cc0 },
2619 { 0x1f, 0x0000 }
2620 };
2621
4da19633 2622 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
8c7006aa 2623}
2624
4da19633 2625static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
236b8082 2626{
350f7596 2627 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2628 { 0x10, 0xf41b },
2629 { 0x1f, 0x0000 }
2630 };
2631
4da19633 2632 rtl_writephy(tp, 0x1f, 0x0001);
2633 rtl_patchphy(tp, 0x16, 1 << 0);
236b8082 2634
4da19633 2635 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2636}
2637
4da19633 2638static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
236b8082 2639{
350f7596 2640 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2641 { 0x1f, 0x0001 },
2642 { 0x10, 0xf41b },
2643 { 0x1f, 0x0000 }
2644 };
2645
4da19633 2646 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2647}
2648
4da19633 2649static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2650{
350f7596 2651 static const struct phy_reg phy_reg_init[] = {
867763c1
FR		 2652 { 0x1f, 0x0000 },
2653 { 0x1d, 0x0f00 },
2654 { 0x1f, 0x0002 },
2655 { 0x0c, 0x1ec8 },
2656 { 0x1f, 0x0000 }
2657 };
2658
4da19633 2659 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
867763c1
FR		 2660}
2661
4da19633 2662static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
ef3386f0 2663{
350f7596 2664 static const struct phy_reg phy_reg_init[] = {
ef3386f0
FR		 2665 { 0x1f, 0x0001 },
2666 { 0x1d, 0x3d98 },
2667 { 0x1f, 0x0000 }
2668 };
2669
4da19633 2670 rtl_writephy(tp, 0x1f, 0x0000);
2671 rtl_patchphy(tp, 0x14, 1 << 5);
2672 rtl_patchphy(tp, 0x0d, 1 << 5);
ef3386f0 2673
4da19633 2674 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
ef3386f0
FR		 2675}
2676
4da19633 2677static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2678{
350f7596 2679 static const struct phy_reg phy_reg_init[] = {
a3f80671
FR		 2680 { 0x1f, 0x0001 },
2681 { 0x12, 0x2300 },
867763c1
FR		 2682 { 0x1f, 0x0002 },
2683 { 0x00, 0x88d4 },
2684 { 0x01, 0x82b1 },
2685 { 0x03, 0x7002 },
2686 { 0x08, 0x9e30 },
2687 { 0x09, 0x01f0 },
2688 { 0x0a, 0x5500 },
2689 { 0x0c, 0x00c8 },
2690 { 0x1f, 0x0003 },
2691 { 0x12, 0xc096 },
2692 { 0x16, 0x000a },
f50d4275
FR		 2693 { 0x1f, 0x0000 },
2694 { 0x1f, 0x0000 },
2695 { 0x09, 0x2000 },
2696 { 0x09, 0x0000 }
867763c1
FR		 2697 };
2698
4da19633 2699 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2700
4da19633 2701 rtl_patchphy(tp, 0x14, 1 << 5);
2702 rtl_patchphy(tp, 0x0d, 1 << 5);
2703 rtl_writephy(tp, 0x1f, 0x0000);
867763c1
FR		 2704}
2705
4da19633 2706static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
7da97ec9 2707{
350f7596 2708 static const struct phy_reg phy_reg_init[] = {
f50d4275 2709 { 0x1f, 0x0001 },
7da97ec9 2710 { 0x12, 0x2300 },
f50d4275
FR		 2711 { 0x03, 0x802f },
2712 { 0x02, 0x4f02 },
2713 { 0x01, 0x0409 },
2714 { 0x00, 0xf099 },
2715 { 0x04, 0x9800 },
2716 { 0x04, 0x9000 },
2717 { 0x1d, 0x3d98 },
7da97ec9
FR		 2718 { 0x1f, 0x0002 },
2719 { 0x0c, 0x7eb8 },
f50d4275
FR		 2720 { 0x06, 0x0761 },
2721 { 0x1f, 0x0003 },
2722 { 0x16, 0x0f0a },
7da97ec9
FR		 2723 { 0x1f, 0x0000 }
2724 };
2725
4da19633 2726 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2727
4da19633 2728 rtl_patchphy(tp, 0x16, 1 << 0);
2729 rtl_patchphy(tp, 0x14, 1 << 5);
2730 rtl_patchphy(tp, 0x0d, 1 << 5);
2731 rtl_writephy(tp, 0x1f, 0x0000);
7da97ec9
FR		 2732}
2733
4da19633 2734static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
197ff761 2735{
350f7596 2736 static const struct phy_reg phy_reg_init[] = {
197ff761
FR		 2737 { 0x1f, 0x0001 },
2738 { 0x12, 0x2300 },
2739 { 0x1d, 0x3d98 },
2740 { 0x1f, 0x0002 },
2741 { 0x0c, 0x7eb8 },
2742 { 0x06, 0x5461 },
2743 { 0x1f, 0x0003 },
2744 { 0x16, 0x0f0a },
2745 { 0x1f, 0x0000 }
2746 };
2747
4da19633 2748 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
197ff761 2749
4da19633 2750 rtl_patchphy(tp, 0x16, 1 << 0);
2751 rtl_patchphy(tp, 0x14, 1 << 5);
2752 rtl_patchphy(tp, 0x0d, 1 << 5);
2753 rtl_writephy(tp, 0x1f, 0x0000);
197ff761
FR		 2754}
2755
4da19633 2756static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
6fb07058 2757{
4da19633 2758 rtl8168c_3_hw_phy_config(tp);
6fb07058
FR		 2759}
2760
bca03d5f 2761static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
5b538df9 2762{
350f7596 2763 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2764 /* Channel Estimation */
5b538df9 2765 { 0x1f, 0x0001 },
daf9df6d 2766 { 0x06, 0x4064 },
2767 { 0x07, 0x2863 },
2768 { 0x08, 0x059c },
2769 { 0x09, 0x26b4 },
2770 { 0x0a, 0x6a19 },
2771 { 0x0b, 0xdcc8 },
2772 { 0x10, 0xf06d },
2773 { 0x14, 0x7f68 },
2774 { 0x18, 0x7fd9 },
2775 { 0x1c, 0xf0ff },
2776 { 0x1d, 0x3d9c },
5b538df9 2777 { 0x1f, 0x0003 },
daf9df6d 2778 { 0x12, 0xf49f },
2779 { 0x13, 0x070b },
2780 { 0x1a, 0x05ad },
bca03d5f 2781 { 0x14, 0x94c0 },
2782
2783 /*
2784 * Tx Error Issue
cecb5fd7 2785 * Enhance line driver power
bca03d5f 2786 */
5b538df9 2787 { 0x1f, 0x0002 },
daf9df6d 2788 { 0x06, 0x5561 },
2789 { 0x1f, 0x0005 },
2790 { 0x05, 0x8332 },
bca03d5f 2791 { 0x06, 0x5561 },
2792
2793 /*
2794 * Can not link to 1Gbps with bad cable
2795 * Decrease SNR threshold form 21.07dB to 19.04dB
2796 */
2797 { 0x1f, 0x0001 },
2798 { 0x17, 0x0cc0 },
daf9df6d 2799
5b538df9 2800 { 0x1f, 0x0000 },
bca03d5f 2801 { 0x0d, 0xf880 }
daf9df6d 2802 };
2803
4da19633 2804 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
daf9df6d 2805
bca03d5f 2806 /*
2807 * Rx Error Issue
2808 * Fine Tune Switching regulator parameter
2809 */
4da19633 2810 rtl_writephy(tp, 0x1f, 0x0002);
2811 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2812 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
daf9df6d 2813
fdf6fc06 2814 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
350f7596 2815 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2816 { 0x1f, 0x0002 },
2817 { 0x05, 0x669a },
2818 { 0x1f, 0x0005 },
2819 { 0x05, 0x8330 },
2820 { 0x06, 0x669a },
2821 { 0x1f, 0x0002 }
2822 };
2823 int val;
2824
4da19633 2825 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2826
4da19633 2827 val = rtl_readphy(tp, 0x0d);
daf9df6d 2828
2829 if ((val & 0x00ff) != 0x006c) {
350f7596 2830 static const u32 set[] = {
daf9df6d 2831 0x0065, 0x0066, 0x0067, 0x0068,
2832 0x0069, 0x006a, 0x006b, 0x006c
2833 };
2834 int i;
2835
4da19633 2836 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2837
2838 val &= 0xff00;
2839 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2840 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2841 }
2842 } else {
350f7596 2843 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2844 { 0x1f, 0x0002 },
2845 { 0x05, 0x6662 },
2846 { 0x1f, 0x0005 },
2847 { 0x05, 0x8330 },
2848 { 0x06, 0x6662 }
2849 };
2850
4da19633 2851 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2852 }
2853
bca03d5f 2854 /* RSET couple improve */
4da19633 2855 rtl_writephy(tp, 0x1f, 0x0002);
2856 rtl_patchphy(tp, 0x0d, 0x0300);
2857 rtl_patchphy(tp, 0x0f, 0x0010);
daf9df6d 2858
bca03d5f 2859 /* Fine tune PLL performance */
4da19633 2860 rtl_writephy(tp, 0x1f, 0x0002);
2861 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2862 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2863
4da19633 2864 rtl_writephy(tp, 0x1f, 0x0005);
2865 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2866
2867 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
bca03d5f 2868
4da19633 2869 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2870}
2871
bca03d5f 2872static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2873{
350f7596 2874 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2875 /* Channel Estimation */
daf9df6d 2876 { 0x1f, 0x0001 },
2877 { 0x06, 0x4064 },
2878 { 0x07, 0x2863 },
2879 { 0x08, 0x059c },
2880 { 0x09, 0x26b4 },
2881 { 0x0a, 0x6a19 },
2882 { 0x0b, 0xdcc8 },
2883 { 0x10, 0xf06d },
2884 { 0x14, 0x7f68 },
2885 { 0x18, 0x7fd9 },
2886 { 0x1c, 0xf0ff },
2887 { 0x1d, 0x3d9c },
2888 { 0x1f, 0x0003 },
2889 { 0x12, 0xf49f },
2890 { 0x13, 0x070b },
2891 { 0x1a, 0x05ad },
2892 { 0x14, 0x94c0 },
2893
bca03d5f 2894 /*
2895 * Tx Error Issue
cecb5fd7 2896 * Enhance line driver power
bca03d5f 2897 */
daf9df6d 2898 { 0x1f, 0x0002 },
2899 { 0x06, 0x5561 },
2900 { 0x1f, 0x0005 },
2901 { 0x05, 0x8332 },
bca03d5f 2902 { 0x06, 0x5561 },
2903
2904 /*
2905 * Can not link to 1Gbps with bad cable
2906 * Decrease SNR threshold form 21.07dB to 19.04dB
2907 */
2908 { 0x1f, 0x0001 },
2909 { 0x17, 0x0cc0 },
daf9df6d 2910
2911 { 0x1f, 0x0000 },
bca03d5f 2912 { 0x0d, 0xf880 }
5b538df9
FR		 2913 };
2914
4da19633 2915 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
5b538df9 2916
fdf6fc06 2917 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
350f7596 2918 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2919 { 0x1f, 0x0002 },
2920 { 0x05, 0x669a },
5b538df9 2921 { 0x1f, 0x0005 },
daf9df6d 2922 { 0x05, 0x8330 },
2923 { 0x06, 0x669a },
2924
2925 { 0x1f, 0x0002 }
2926 };
2927 int val;
2928
4da19633 2929 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2930
4da19633 2931 val = rtl_readphy(tp, 0x0d);
daf9df6d 2932 if ((val & 0x00ff) != 0x006c) {
b6bc7650 2933 static const u32 set[] = {
daf9df6d 2934 0x0065, 0x0066, 0x0067, 0x0068,
2935 0x0069, 0x006a, 0x006b, 0x006c
2936 };
2937 int i;
2938
4da19633 2939 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2940
2941 val &= 0xff00;
2942 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2943 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2944 }
2945 } else {
350f7596 2946 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2947 { 0x1f, 0x0002 },
2948 { 0x05, 0x2642 },
5b538df9 2949 { 0x1f, 0x0005 },
daf9df6d 2950 { 0x05, 0x8330 },
2951 { 0x06, 0x2642 }
5b538df9
FR		 2952 };
2953
4da19633 2954 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2955 }
2956
bca03d5f 2957 /* Fine tune PLL performance */
4da19633 2958 rtl_writephy(tp, 0x1f, 0x0002);
2959 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2960 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2961
bca03d5f 2962 /* Switching regulator Slew rate */
4da19633 2963 rtl_writephy(tp, 0x1f, 0x0002);
2964 rtl_patchphy(tp, 0x0f, 0x0017);
daf9df6d 2965
4da19633 2966 rtl_writephy(tp, 0x1f, 0x0005);
2967 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2968
2969 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
bca03d5f 2970
4da19633 2971 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2972}
2973
4da19633 2974static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2975{
350f7596 2976 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2977 { 0x1f, 0x0002 },
2978 { 0x10, 0x0008 },
2979 { 0x0d, 0x006c },
2980
2981 { 0x1f, 0x0000 },
2982 { 0x0d, 0xf880 },
2983
2984 { 0x1f, 0x0001 },
2985 { 0x17, 0x0cc0 },
2986
2987 { 0x1f, 0x0001 },
2988 { 0x0b, 0xa4d8 },
2989 { 0x09, 0x281c },
2990 { 0x07, 0x2883 },
2991 { 0x0a, 0x6b35 },
2992 { 0x1d, 0x3da4 },
2993 { 0x1c, 0xeffd },
2994 { 0x14, 0x7f52 },
2995 { 0x18, 0x7fc6 },
2996 { 0x08, 0x0601 },
2997 { 0x06, 0x4063 },
2998 { 0x10, 0xf074 },
2999 { 0x1f, 0x0003 },
3000 { 0x13, 0x0789 },
3001 { 0x12, 0xf4bd },
3002 { 0x1a, 0x04fd },
3003 { 0x14, 0x84b0 },
3004 { 0x1f, 0x0000 },
3005 { 0x00, 0x9200 },
3006
3007 { 0x1f, 0x0005 },
3008 { 0x01, 0x0340 },
3009 { 0x1f, 0x0001 },
3010 { 0x04, 0x4000 },
3011 { 0x03, 0x1d21 },
3012 { 0x02, 0x0c32 },
3013 { 0x01, 0x0200 },
3014 { 0x00, 0x5554 },
3015 { 0x04, 0x4800 },
3016 { 0x04, 0x4000 },
3017 { 0x04, 0xf000 },
3018 { 0x03, 0xdf01 },
3019 { 0x02, 0xdf20 },
3020 { 0x01, 0x101a },
3021 { 0x00, 0xa0ff },
3022 { 0x04, 0xf800 },
3023 { 0x04, 0xf000 },
3024 { 0x1f, 0x0000 },
3025
3026 { 0x1f, 0x0007 },
3027 { 0x1e, 0x0023 },
3028 { 0x16, 0x0000 },
3029 { 0x1f, 0x0000 }
3030 };
3031
4da19633 3032 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 3033}
3034
e6de30d6 3035static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3036{
3037 static const struct phy_reg phy_reg_init[] = {
3038 { 0x1f, 0x0001 },
3039 { 0x17, 0x0cc0 },
3040
3041 { 0x1f, 0x0007 },
3042 { 0x1e, 0x002d },
3043 { 0x18, 0x0040 },
3044 { 0x1f, 0x0000 }
3045 };
3046
3047 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3048 rtl_patchphy(tp, 0x0d, 1 << 5);
3049}
3050
70090424 3051static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
01dc7fec 3052{
3053 static const struct phy_reg phy_reg_init[] = {
3054 /* Enable Delay cap */
3055 { 0x1f, 0x0005 },
3056 { 0x05, 0x8b80 },
3057 { 0x06, 0xc896 },
3058 { 0x1f, 0x0000 },
3059
3060 /* Channel estimation fine tune */
3061 { 0x1f, 0x0001 },
3062 { 0x0b, 0x6c20 },
3063 { 0x07, 0x2872 },
3064 { 0x1c, 0xefff },
3065 { 0x1f, 0x0003 },
3066 { 0x14, 0x6420 },
3067 { 0x1f, 0x0000 },
3068
3069 /* Update PFM & 10M TX idle timer */
3070 { 0x1f, 0x0007 },
3071 { 0x1e, 0x002f },
3072 { 0x15, 0x1919 },
3073 { 0x1f, 0x0000 },
3074
3075 { 0x1f, 0x0007 },
3076 { 0x1e, 0x00ac },
3077 { 0x18, 0x0006 },
3078 { 0x1f, 0x0000 }
3079 };
3080
15ecd039
FR		 3081 rtl_apply_firmware(tp);
3082
01dc7fec 3083 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3084
3085 /* DCO enable for 10M IDLE Power */
3086 rtl_writephy(tp, 0x1f, 0x0007);
3087 rtl_writephy(tp, 0x1e, 0x0023);
3088 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
3089 rtl_writephy(tp, 0x1f, 0x0000);
3090
3091 /* For impedance matching */
3092 rtl_writephy(tp, 0x1f, 0x0002);
3093 rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
cecb5fd7 3094 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3095
3096 /* PHY auto speed down */
3097 rtl_writephy(tp, 0x1f, 0x0007);
3098 rtl_writephy(tp, 0x1e, 0x002d);
3099 rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
3100 rtl_writephy(tp, 0x1f, 0x0000);
3101 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3102
3103 rtl_writephy(tp, 0x1f, 0x0005);
3104 rtl_writephy(tp, 0x05, 0x8b86);
3105 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3106 rtl_writephy(tp, 0x1f, 0x0000);
3107
3108 rtl_writephy(tp, 0x1f, 0x0005);
3109 rtl_writephy(tp, 0x05, 0x8b85);
3110 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3111 rtl_writephy(tp, 0x1f, 0x0007);
3112 rtl_writephy(tp, 0x1e, 0x0020);
3113 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
3114 rtl_writephy(tp, 0x1f, 0x0006);
3115 rtl_writephy(tp, 0x00, 0x5a00);
3116 rtl_writephy(tp, 0x1f, 0x0000);
3117 rtl_writephy(tp, 0x0d, 0x0007);
3118 rtl_writephy(tp, 0x0e, 0x003c);
3119 rtl_writephy(tp, 0x0d, 0x4007);
3120 rtl_writephy(tp, 0x0e, 0x0000);
3121 rtl_writephy(tp, 0x0d, 0x0000);
3122}
3123
70090424
HW		 3124static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3125{
3126 static const struct phy_reg phy_reg_init[] = {
3127 /* Enable Delay cap */
3128 { 0x1f, 0x0004 },
3129 { 0x1f, 0x0007 },
3130 { 0x1e, 0x00ac },
3131 { 0x18, 0x0006 },
3132 { 0x1f, 0x0002 },
3133 { 0x1f, 0x0000 },
3134 { 0x1f, 0x0000 },
3135
3136 /* Channel estimation fine tune */
3137 { 0x1f, 0x0003 },
3138 { 0x09, 0xa20f },
3139 { 0x1f, 0x0000 },
3140 { 0x1f, 0x0000 },
3141
3142 /* Green Setting */
3143 { 0x1f, 0x0005 },
3144 { 0x05, 0x8b5b },
3145 { 0x06, 0x9222 },
3146 { 0x05, 0x8b6d },
3147 { 0x06, 0x8000 },
3148 { 0x05, 0x8b76 },
3149 { 0x06, 0x8000 },
3150 { 0x1f, 0x0000 }
3151 };
3152
3153 rtl_apply_firmware(tp);
3154
3155 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3156
3157 /* For 4-corner performance improve */
3158 rtl_writephy(tp, 0x1f, 0x0005);
3159 rtl_writephy(tp, 0x05, 0x8b80);
3160 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
3161 rtl_writephy(tp, 0x1f, 0x0000);
3162
3163 /* PHY auto speed down */
3164 rtl_writephy(tp, 0x1f, 0x0004);
3165 rtl_writephy(tp, 0x1f, 0x0007);
3166 rtl_writephy(tp, 0x1e, 0x002d);
3167 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3168 rtl_writephy(tp, 0x1f, 0x0002);
3169 rtl_writephy(tp, 0x1f, 0x0000);
3170 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3171
3172 /* improve 10M EEE waveform */
3173 rtl_writephy(tp, 0x1f, 0x0005);
3174 rtl_writephy(tp, 0x05, 0x8b86);
3175 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3176 rtl_writephy(tp, 0x1f, 0x0000);
3177
3178 /* Improve 2-pair detection performance */
3179 rtl_writephy(tp, 0x1f, 0x0005);
3180 rtl_writephy(tp, 0x05, 0x8b85);
3181 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3182 rtl_writephy(tp, 0x1f, 0x0000);
3183
3184 /* EEE setting */
fdf6fc06 3185 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, ERIAR_EXGMAC);
70090424
HW		 3186 rtl_writephy(tp, 0x1f, 0x0005);
3187 rtl_writephy(tp, 0x05, 0x8b85);
3188 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3189 rtl_writephy(tp, 0x1f, 0x0004);
3190 rtl_writephy(tp, 0x1f, 0x0007);
3191 rtl_writephy(tp, 0x1e, 0x0020);
1b23a3e3 3192 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
70090424
HW		 3193 rtl_writephy(tp, 0x1f, 0x0002);
3194 rtl_writephy(tp, 0x1f, 0x0000);
3195 rtl_writephy(tp, 0x0d, 0x0007);
3196 rtl_writephy(tp, 0x0e, 0x003c);
3197 rtl_writephy(tp, 0x0d, 0x4007);
3198 rtl_writephy(tp, 0x0e, 0x0000);
3199 rtl_writephy(tp, 0x0d, 0x0000);
3200
3201 /* Green feature */
3202 rtl_writephy(tp, 0x1f, 0x0003);
3203 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3204 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3205 rtl_writephy(tp, 0x1f, 0x0000);
e0c07557 3206
3207 r8168_aldps_enable_1(tp);
70090424
HW		 3208}
3209
5f886e08
HW		 3210static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3211{
3212 /* For 4-corner performance improve */
3213 rtl_writephy(tp, 0x1f, 0x0005);
3214 rtl_writephy(tp, 0x05, 0x8b80);
3215 rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3216 rtl_writephy(tp, 0x1f, 0x0000);
3217
3218 /* PHY auto speed down */
3219 rtl_writephy(tp, 0x1f, 0x0007);
3220 rtl_writephy(tp, 0x1e, 0x002d);
3221 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3222 rtl_writephy(tp, 0x1f, 0x0000);
3223 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3224
3225 /* Improve 10M EEE waveform */
3226 rtl_writephy(tp, 0x1f, 0x0005);
3227 rtl_writephy(tp, 0x05, 0x8b86);
3228 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3229 rtl_writephy(tp, 0x1f, 0x0000);
3230}
3231
c2218925
HW		 3232static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3233{
3234 static const struct phy_reg phy_reg_init[] = {
3235 /* Channel estimation fine tune */
3236 { 0x1f, 0x0003 },
3237 { 0x09, 0xa20f },
3238 { 0x1f, 0x0000 },
3239
3240 /* Modify green table for giga & fnet */
3241 { 0x1f, 0x0005 },
3242 { 0x05, 0x8b55 },
3243 { 0x06, 0x0000 },
3244 { 0x05, 0x8b5e },
3245 { 0x06, 0x0000 },
3246 { 0x05, 0x8b67 },
3247 { 0x06, 0x0000 },
3248 { 0x05, 0x8b70 },
3249 { 0x06, 0x0000 },
3250 { 0x1f, 0x0000 },
3251 { 0x1f, 0x0007 },
3252 { 0x1e, 0x0078 },
3253 { 0x17, 0x0000 },
3254 { 0x19, 0x00fb },
3255 { 0x1f, 0x0000 },
3256
3257 /* Modify green table for 10M */
3258 { 0x1f, 0x0005 },
3259 { 0x05, 0x8b79 },
3260 { 0x06, 0xaa00 },
3261 { 0x1f, 0x0000 },
3262
3263 /* Disable hiimpedance detection (RTCT) */
3264 { 0x1f, 0x0003 },
3265 { 0x01, 0x328a },
3266 { 0x1f, 0x0000 }
3267 };
3268
3269 rtl_apply_firmware(tp);
3270
3271 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3272
5f886e08 3273 rtl8168f_hw_phy_config(tp);
c2218925
HW		 3274
3275 /* Improve 2-pair detection performance */
3276 rtl_writephy(tp, 0x1f, 0x0005);
3277 rtl_writephy(tp, 0x05, 0x8b85);
3278 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3279 rtl_writephy(tp, 0x1f, 0x0000);
e0c07557 3280
3281 r8168_aldps_enable_1(tp);
c2218925
HW		 3282}
3283
3284static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3285{
3286 rtl_apply_firmware(tp);
3287
5f886e08 3288 rtl8168f_hw_phy_config(tp);
e0c07557 3289
3290 r8168_aldps_enable_1(tp);
c2218925
HW		 3291}
3292
b3d7b2f2
HW		 3293static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3294{
b3d7b2f2
HW		 3295 static const struct phy_reg phy_reg_init[] = {
3296 /* Channel estimation fine tune */
3297 { 0x1f, 0x0003 },
3298 { 0x09, 0xa20f },
3299 { 0x1f, 0x0000 },
3300
3301 /* Modify green table for giga & fnet */
3302 { 0x1f, 0x0005 },
3303 { 0x05, 0x8b55 },
3304 { 0x06, 0x0000 },
3305 { 0x05, 0x8b5e },
3306 { 0x06, 0x0000 },
3307 { 0x05, 0x8b67 },
3308 { 0x06, 0x0000 },
3309 { 0x05, 0x8b70 },
3310 { 0x06, 0x0000 },
3311 { 0x1f, 0x0000 },
3312 { 0x1f, 0x0007 },
3313 { 0x1e, 0x0078 },
3314 { 0x17, 0x0000 },
3315 { 0x19, 0x00aa },
3316 { 0x1f, 0x0000 },
3317
3318 /* Modify green table for 10M */
3319 { 0x1f, 0x0005 },
3320 { 0x05, 0x8b79 },
3321 { 0x06, 0xaa00 },
3322 { 0x1f, 0x0000 },
3323
3324 /* Disable hiimpedance detection (RTCT) */
3325 { 0x1f, 0x0003 },
3326 { 0x01, 0x328a },
3327 { 0x1f, 0x0000 }
3328 };
3329
3330
3331 rtl_apply_firmware(tp);
3332
3333 rtl8168f_hw_phy_config(tp);
3334
3335 /* Improve 2-pair detection performance */
3336 rtl_writephy(tp, 0x1f, 0x0005);
3337 rtl_writephy(tp, 0x05, 0x8b85);
3338 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3339 rtl_writephy(tp, 0x1f, 0x0000);
3340
3341 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3342
3343 /* Modify green table for giga */
3344 rtl_writephy(tp, 0x1f, 0x0005);
3345 rtl_writephy(tp, 0x05, 0x8b54);
3346 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
3347 rtl_writephy(tp, 0x05, 0x8b5d);
3348 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
3349 rtl_writephy(tp, 0x05, 0x8a7c);
3350 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3351 rtl_writephy(tp, 0x05, 0x8a7f);
3352 rtl_w1w0_phy(tp, 0x06, 0x0100, 0x0000);
3353 rtl_writephy(tp, 0x05, 0x8a82);
3354 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3355 rtl_writephy(tp, 0x05, 0x8a85);
3356 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3357 rtl_writephy(tp, 0x05, 0x8a88);
3358 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3359 rtl_writephy(tp, 0x1f, 0x0000);
3360
3361 /* uc same-seed solution */
3362 rtl_writephy(tp, 0x1f, 0x0005);
3363 rtl_writephy(tp, 0x05, 0x8b85);
3364 rtl_w1w0_phy(tp, 0x06, 0x8000, 0x0000);
3365 rtl_writephy(tp, 0x1f, 0x0000);
3366
3367 /* eee setting */
fdf6fc06 3368 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
b3d7b2f2
HW		 3369 rtl_writephy(tp, 0x1f, 0x0005);
3370 rtl_writephy(tp, 0x05, 0x8b85);
3371 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3372 rtl_writephy(tp, 0x1f, 0x0004);
3373 rtl_writephy(tp, 0x1f, 0x0007);
3374 rtl_writephy(tp, 0x1e, 0x0020);
3375 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
3376 rtl_writephy(tp, 0x1f, 0x0000);
3377 rtl_writephy(tp, 0x0d, 0x0007);
3378 rtl_writephy(tp, 0x0e, 0x003c);
3379 rtl_writephy(tp, 0x0d, 0x4007);
3380 rtl_writephy(tp, 0x0e, 0x0000);
3381 rtl_writephy(tp, 0x0d, 0x0000);
3382
3383 /* Green feature */
3384 rtl_writephy(tp, 0x1f, 0x0003);
3385 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3386 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3387 rtl_writephy(tp, 0x1f, 0x0000);
e0c07557 3388
3389 r8168_aldps_enable_1(tp);
b3d7b2f2
HW		 3390}
3391
c558386b
HW		 3392static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3393{
3394 static const u16 mac_ocp_patch[] = {
3395 0xe008, 0xe01b, 0xe01d, 0xe01f,
3396 0xe021, 0xe023, 0xe025, 0xe027,
3397 0x49d2, 0xf10d, 0x766c, 0x49e2,
3398 0xf00a, 0x1ec0, 0x8ee1, 0xc60a,
3399
3400 0x77c0, 0x4870, 0x9fc0, 0x1ea0,
3401 0xc707, 0x8ee1, 0x9d6c, 0xc603,
3402 0xbe00, 0xb416, 0x0076, 0xe86c,
3403 0xc602, 0xbe00, 0x0000, 0xc602,
3404
3405 0xbe00, 0x0000, 0xc602, 0xbe00,
3406 0x0000, 0xc602, 0xbe00, 0x0000,
3407 0xc602, 0xbe00, 0x0000, 0xc602,
3408 0xbe00, 0x0000, 0xc602, 0xbe00,
3409
3410 0x0000, 0x0000, 0x0000, 0x0000
3411 };
3412 u32 i;
3413
3414 /* Patch code for GPHY reset */
3415 for (i = 0; i < ARRAY_SIZE(mac_ocp_patch); i++)
3416 r8168_mac_ocp_write(tp, 0xf800 + 2*i, mac_ocp_patch[i]);
3417 r8168_mac_ocp_write(tp, 0xfc26, 0x8000);
3418 r8168_mac_ocp_write(tp, 0xfc28, 0x0075);
3419
3420 rtl_apply_firmware(tp);
3421
3422 if (r8168_phy_ocp_read(tp, 0xa460) & 0x0100)
3423 rtl_w1w0_phy_ocp(tp, 0xbcc4, 0x0000, 0x8000);
3424 else
3425 rtl_w1w0_phy_ocp(tp, 0xbcc4, 0x8000, 0x0000);
3426
3427 if (r8168_phy_ocp_read(tp, 0xa466) & 0x0100)
3428 rtl_w1w0_phy_ocp(tp, 0xc41a, 0x0002, 0x0000);
3429 else
3430 rtl_w1w0_phy_ocp(tp, 0xbcc4, 0x0000, 0x0002);
3431
3432 rtl_w1w0_phy_ocp(tp, 0xa442, 0x000c, 0x0000);
3433 rtl_w1w0_phy_ocp(tp, 0xa4b2, 0x0004, 0x0000);
3434
3435 r8168_phy_ocp_write(tp, 0xa436, 0x8012);
3436 rtl_w1w0_phy_ocp(tp, 0xa438, 0x8000, 0x0000);
3437
3438 rtl_w1w0_phy_ocp(tp, 0xc422, 0x4000, 0x2000);
3439}
3440
4da19633 3441static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2857ffb7 3442{
350f7596 3443 static const struct phy_reg phy_reg_init[] = {
2857ffb7
FR		 3444 { 0x1f, 0x0003 },
3445 { 0x08, 0x441d },
3446 { 0x01, 0x9100 },
3447 { 0x1f, 0x0000 }
3448 };
3449
4da19633 3450 rtl_writephy(tp, 0x1f, 0x0000);
3451 rtl_patchphy(tp, 0x11, 1 << 12);
3452 rtl_patchphy(tp, 0x19, 1 << 13);
3453 rtl_patchphy(tp, 0x10, 1 << 15);
2857ffb7 3454
4da19633 3455 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2857ffb7
FR		 3456}
3457
5a5e4443
HW		 3458static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3459{
3460 static const struct phy_reg phy_reg_init[] = {
3461 { 0x1f, 0x0005 },
3462 { 0x1a, 0x0000 },
3463 { 0x1f, 0x0000 },
3464
3465 { 0x1f, 0x0004 },
3466 { 0x1c, 0x0000 },
3467 { 0x1f, 0x0000 },
3468
3469 { 0x1f, 0x0001 },
3470 { 0x15, 0x7701 },
3471 { 0x1f, 0x0000 }
3472 };
3473
3474 /* Disable ALDPS before ram code */
e0c07557 3475 r810x_aldps_disable(tp);
5a5e4443 3476
953a12cc 3477 rtl_apply_firmware(tp);
5a5e4443
HW		 3478
3479 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
e0c07557 3480
3481 r810x_aldps_enable(tp);
5a5e4443
HW		 3482}
3483
7e18dca1
HW		 3484static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3485{
7e18dca1 3486 /* Disable ALDPS before setting firmware */
e0c07557 3487 r810x_aldps_disable(tp);
7e18dca1
HW		 3488
3489 rtl_apply_firmware(tp);
3490
3491 /* EEE setting */
fdf6fc06 3492 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
7e18dca1
HW		 3493 rtl_writephy(tp, 0x1f, 0x0004);
3494 rtl_writephy(tp, 0x10, 0x401f);
3495 rtl_writephy(tp, 0x19, 0x7030);
3496 rtl_writephy(tp, 0x1f, 0x0000);
e0c07557 3497
3498 r810x_aldps_enable(tp);
7e18dca1
HW		 3499}
3500
5598bfe5
HW		 3501static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3502{
5598bfe5
HW		 3503 static const struct phy_reg phy_reg_init[] = {
3504 { 0x1f, 0x0004 },
3505 { 0x10, 0xc07f },
3506 { 0x19, 0x7030 },
3507 { 0x1f, 0x0000 }
3508 };
3509
3510 /* Disable ALDPS before ram code */
e0c07557 3511 r810x_aldps_disable(tp);
5598bfe5
HW		 3512
3513 rtl_apply_firmware(tp);
3514
fdf6fc06 3515 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5598bfe5
HW		 3516 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3517
fdf6fc06 3518 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
e0c07557 3519
3520 r810x_aldps_enable(tp);
5598bfe5
HW		 3521}
3522
5615d9f1
FR		 3523static void rtl_hw_phy_config(struct net_device *dev)
3524{
3525 struct rtl8169_private *tp = netdev_priv(dev);
5615d9f1
FR		 3526
3527 rtl8169_print_mac_version(tp);
3528
3529 switch (tp->mac_version) {
3530 case RTL_GIGA_MAC_VER_01:
3531 break;
3532 case RTL_GIGA_MAC_VER_02:
3533 case RTL_GIGA_MAC_VER_03:
4da19633 3534 rtl8169s_hw_phy_config(tp);
5615d9f1
FR		 3535 break;
3536 case RTL_GIGA_MAC_VER_04:
4da19633 3537 rtl8169sb_hw_phy_config(tp);
5615d9f1 3538 break;
2e955856 3539 case RTL_GIGA_MAC_VER_05:
4da19633 3540 rtl8169scd_hw_phy_config(tp);
2e955856 3541 break;
8c7006aa 3542 case RTL_GIGA_MAC_VER_06:
4da19633 3543 rtl8169sce_hw_phy_config(tp);
8c7006aa 3544 break;
2857ffb7
FR		 3545 case RTL_GIGA_MAC_VER_07:
3546 case RTL_GIGA_MAC_VER_08:
3547 case RTL_GIGA_MAC_VER_09:
4da19633 3548 rtl8102e_hw_phy_config(tp);
2857ffb7 3549 break;
236b8082 3550 case RTL_GIGA_MAC_VER_11:
4da19633 3551 rtl8168bb_hw_phy_config(tp);
236b8082
FR		 3552 break;
3553 case RTL_GIGA_MAC_VER_12:
4da19633 3554 rtl8168bef_hw_phy_config(tp);
236b8082
FR		 3555 break;
3556 case RTL_GIGA_MAC_VER_17:
4da19633 3557 rtl8168bef_hw_phy_config(tp);
236b8082 3558 break;
867763c1 3559 case RTL_GIGA_MAC_VER_18:
4da19633 3560 rtl8168cp_1_hw_phy_config(tp);
867763c1
FR		 3561 break;
3562 case RTL_GIGA_MAC_VER_19:
4da19633 3563 rtl8168c_1_hw_phy_config(tp);
867763c1 3564 break;
7da97ec9 3565 case RTL_GIGA_MAC_VER_20:
4da19633 3566 rtl8168c_2_hw_phy_config(tp);
7da97ec9 3567 break;
197ff761 3568 case RTL_GIGA_MAC_VER_21:
4da19633 3569 rtl8168c_3_hw_phy_config(tp);
197ff761 3570 break;
6fb07058 3571 case RTL_GIGA_MAC_VER_22:
4da19633 3572 rtl8168c_4_hw_phy_config(tp);
6fb07058 3573 break;
ef3386f0 3574 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 3575 case RTL_GIGA_MAC_VER_24:
4da19633 3576 rtl8168cp_2_hw_phy_config(tp);
ef3386f0 3577 break;
5b538df9 3578 case RTL_GIGA_MAC_VER_25:
bca03d5f 3579 rtl8168d_1_hw_phy_config(tp);
daf9df6d 3580 break;
3581 case RTL_GIGA_MAC_VER_26:
bca03d5f 3582 rtl8168d_2_hw_phy_config(tp);
daf9df6d 3583 break;
3584 case RTL_GIGA_MAC_VER_27:
4da19633 3585 rtl8168d_3_hw_phy_config(tp);
5b538df9 3586 break;
e6de30d6 3587 case RTL_GIGA_MAC_VER_28:
3588 rtl8168d_4_hw_phy_config(tp);
3589 break;
5a5e4443
HW		 3590 case RTL_GIGA_MAC_VER_29:
3591 case RTL_GIGA_MAC_VER_30:
3592 rtl8105e_hw_phy_config(tp);
3593 break;
cecb5fd7
FR		 3594 case RTL_GIGA_MAC_VER_31:
3595 /* None. */
3596 break;
01dc7fec 3597 case RTL_GIGA_MAC_VER_32:
01dc7fec 3598 case RTL_GIGA_MAC_VER_33:
70090424
HW		 3599 rtl8168e_1_hw_phy_config(tp);
3600 break;
3601 case RTL_GIGA_MAC_VER_34:
3602 rtl8168e_2_hw_phy_config(tp);
01dc7fec 3603 break;
c2218925
HW		 3604 case RTL_GIGA_MAC_VER_35:
3605 rtl8168f_1_hw_phy_config(tp);
3606 break;
3607 case RTL_GIGA_MAC_VER_36:
3608 rtl8168f_2_hw_phy_config(tp);
3609 break;
ef3386f0 3610
7e18dca1
HW		 3611 case RTL_GIGA_MAC_VER_37:
3612 rtl8402_hw_phy_config(tp);
3613 break;
3614
b3d7b2f2
HW		 3615 case RTL_GIGA_MAC_VER_38:
3616 rtl8411_hw_phy_config(tp);
3617 break;
3618
5598bfe5
HW		 3619 case RTL_GIGA_MAC_VER_39:
3620 rtl8106e_hw_phy_config(tp);
3621 break;
3622
c558386b
HW		 3623 case RTL_GIGA_MAC_VER_40:
3624 rtl8168g_1_hw_phy_config(tp);
3625 break;
3626
3627 case RTL_GIGA_MAC_VER_41:
5615d9f1
FR		 3628 default:
3629 break;
3630 }
3631}
3632
da78dbff 3633static void rtl_phy_work(struct rtl8169_private *tp)
1da177e4 3634{
1da177e4
LT		 3635 struct timer_list *timer = &tp->timer;
3636 void __iomem *ioaddr = tp->mmio_addr;
3637 unsigned long timeout = RTL8169_PHY_TIMEOUT;
3638
bcf0bf90 3639 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 3640
4da19633 3641 if (tp->phy_reset_pending(tp)) {
5b0384f4 3642 /*
1da177e4
LT		 3643 * A busy loop could burn quite a few cycles on nowadays CPU.
3644 * Let's delay the execution of the timer for a few ticks.
3645 */
3646 timeout = HZ/10;
3647 goto out_mod_timer;
3648 }
3649
3650 if (tp->link_ok(ioaddr))
da78dbff 3651 return;
1da177e4 3652
da78dbff 3653 netif_warn(tp, link, tp->dev, "PHY reset until link up\n");
1da177e4 3654
4da19633 3655 tp->phy_reset_enable(tp);
1da177e4
LT		 3656
3657out_mod_timer:
3658 mod_timer(timer, jiffies + timeout);
da78dbff
FR		 3659}
3660
3661static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3662{
da78dbff
FR		 3663 if (!test_and_set_bit(flag, tp->wk.flags))
3664 schedule_work(&tp->wk.work);
da78dbff
FR		 3665}
3666
3667static void rtl8169_phy_timer(unsigned long __opaque)
3668{
3669 struct net_device *dev = (struct net_device *)__opaque;
3670 struct rtl8169_private *tp = netdev_priv(dev);
3671
98ddf986 3672 rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
1da177e4
LT		 3673}
3674
1da177e4
LT		 3675static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3676 void __iomem *ioaddr)
3677{
3678 iounmap(ioaddr);
3679 pci_release_regions(pdev);
87aeec76 3680 pci_clear_mwi(pdev);
1da177e4
LT		 3681 pci_disable_device(pdev);
3682 free_netdev(dev);
3683}
3684
ffc46952
FR		 3685DECLARE_RTL_COND(rtl_phy_reset_cond)
3686{
3687 return tp->phy_reset_pending(tp);
3688}
3689
bf793295
FR		 3690static void rtl8169_phy_reset(struct net_device *dev,
3691 struct rtl8169_private *tp)
3692{
4da19633 3693 tp->phy_reset_enable(tp);
ffc46952 3694 rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100);
bf793295
FR		 3695}
3696
2544bfc0
FR		 3697static bool rtl_tbi_enabled(struct rtl8169_private *tp)
3698{
3699 void __iomem *ioaddr = tp->mmio_addr;
3700
3701 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
3702 (RTL_R8(PHYstatus) & TBI_Enable);
3703}
3704
4ff96fa6
FR		 3705static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3706{
3707 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 3708
5615d9f1 3709 rtl_hw_phy_config(dev);
4ff96fa6 3710
77332894
MS		 3711 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3712 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3713 RTL_W8(0x82, 0x01);
3714 }
4ff96fa6 3715
6dccd16b
FR		 3716 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3717
3718 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3719 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 3720
bcf0bf90 3721 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 3722 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3723 RTL_W8(0x82, 0x01);
3724 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4da19633 3725 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4ff96fa6
FR		 3726 }
3727
bf793295
FR		 3728 rtl8169_phy_reset(dev, tp);
3729
54405cde 3730 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
cecb5fd7
FR		 3731 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3732 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3733 (tp->mii.supports_gmii ?
3734 ADVERTISED_1000baseT_Half |
3735 ADVERTISED_1000baseT_Full : 0));
4ff96fa6 3736
2544bfc0 3737 if (rtl_tbi_enabled(tp))
bf82c189 3738 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4ff96fa6
FR		 3739}
3740
773d2021
FR		 3741static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3742{
3743 void __iomem *ioaddr = tp->mmio_addr;
3744 u32 high;
3745 u32 low;
3746
3747 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
3748 high = addr[4] | (addr[5] << 8);
3749
da78dbff 3750 rtl_lock_work(tp);
773d2021
FR		 3751
3752 RTL_W8(Cfg9346, Cfg9346_Unlock);
908ba2bf 3753
773d2021 3754 RTL_W32(MAC4, high);
908ba2bf 3755 RTL_R32(MAC4);
3756
78f1cd02 3757 RTL_W32(MAC0, low);
908ba2bf 3758 RTL_R32(MAC0);
3759
c28aa385 3760 if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
3761 const struct exgmac_reg e[] = {
3762 { .addr = 0xe0, ERIAR_MASK_1111, .val = low },
3763 { .addr = 0xe4, ERIAR_MASK_1111, .val = high },
3764 { .addr = 0xf0, ERIAR_MASK_1111, .val = low << 16 },
3765 { .addr = 0xf4, ERIAR_MASK_1111, .val = high << 16 |
3766 low >> 16 },
3767 };
3768
fdf6fc06 3769 rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
c28aa385 3770 }
3771
773d2021
FR		 3772 RTL_W8(Cfg9346, Cfg9346_Lock);
3773
da78dbff 3774 rtl_unlock_work(tp);
773d2021
FR		 3775}
3776
3777static int rtl_set_mac_address(struct net_device *dev, void *p)
3778{
3779 struct rtl8169_private *tp = netdev_priv(dev);
3780 struct sockaddr *addr = p;
3781
3782 if (!is_valid_ether_addr(addr->sa_data))
3783 return -EADDRNOTAVAIL;
3784
3785 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3786
3787 rtl_rar_set(tp, dev->dev_addr);
3788
3789 return 0;
3790}
3791
5f787a1a
FR		 3792static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3793{
3794 struct rtl8169_private *tp = netdev_priv(dev);
3795 struct mii_ioctl_data *data = if_mii(ifr);
3796
8b4ab28d
FR		 3797 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
3798}
5f787a1a 3799
cecb5fd7
FR		 3800static int rtl_xmii_ioctl(struct rtl8169_private *tp,
3801 struct mii_ioctl_data *data, int cmd)
8b4ab28d 3802{
5f787a1a
FR		 3803 switch (cmd) {
3804 case SIOCGMIIPHY:
3805 data->phy_id = 32; /* Internal PHY */
3806 return 0;
3807
3808 case SIOCGMIIREG:
4da19633 3809 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
5f787a1a
FR		 3810 return 0;
3811
3812 case SIOCSMIIREG:
4da19633 3813 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
5f787a1a
FR		 3814 return 0;
3815 }
3816 return -EOPNOTSUPP;
3817}
3818
8b4ab28d
FR		 3819static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3820{
3821 return -EOPNOTSUPP;
3822}
3823
fbac58fc
FR		 3824static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3825{
3826 if (tp->features & RTL_FEATURE_MSI) {
3827 pci_disable_msi(pdev);
3828 tp->features &= ~RTL_FEATURE_MSI;
3829 }
3830}
3831
c0e45c1c 3832static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
3833{
3834 struct mdio_ops *ops = &tp->mdio_ops;
3835
3836 switch (tp->mac_version) {
3837 case RTL_GIGA_MAC_VER_27:
3838 ops->write = r8168dp_1_mdio_write;
3839 ops->read = r8168dp_1_mdio_read;
3840 break;
e6de30d6 3841 case RTL_GIGA_MAC_VER_28:
4804b3b3 3842 case RTL_GIGA_MAC_VER_31:
e6de30d6 3843 ops->write = r8168dp_2_mdio_write;
3844 ops->read = r8168dp_2_mdio_read;
3845 break;
c558386b
HW		 3846 case RTL_GIGA_MAC_VER_40:
3847 case RTL_GIGA_MAC_VER_41:
3848 ops->write = r8168g_mdio_write;
3849 ops->read = r8168g_mdio_read;
3850 break;
c0e45c1c 3851 default:
3852 ops->write = r8169_mdio_write;
3853 ops->read = r8169_mdio_read;
3854 break;
3855 }
3856}
3857
649b3b8c 3858static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3859{
3860 void __iomem *ioaddr = tp->mmio_addr;
3861
3862 switch (tp->mac_version) {
b00e69de
CB		 3863 case RTL_GIGA_MAC_VER_25:
3864 case RTL_GIGA_MAC_VER_26:
649b3b8c 3865 case RTL_GIGA_MAC_VER_29:
3866 case RTL_GIGA_MAC_VER_30:
3867 case RTL_GIGA_MAC_VER_32:
3868 case RTL_GIGA_MAC_VER_33:
3869 case RTL_GIGA_MAC_VER_34:
7e18dca1 3870 case RTL_GIGA_MAC_VER_37:
b3d7b2f2 3871 case RTL_GIGA_MAC_VER_38:
5598bfe5 3872 case RTL_GIGA_MAC_VER_39:
c558386b
HW		 3873 case RTL_GIGA_MAC_VER_40:
3874 case RTL_GIGA_MAC_VER_41:
649b3b8c 3875 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3876 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3877 break;
3878 default:
3879 break;
3880 }
3881}
3882
3883static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
3884{
3885 if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
3886 return false;
3887
3888 rtl_writephy(tp, 0x1f, 0x0000);
3889 rtl_writephy(tp, MII_BMCR, 0x0000);
3890
3891 rtl_wol_suspend_quirk(tp);
3892
3893 return true;
3894}
3895
065c27c1 3896static void r810x_phy_power_down(struct rtl8169_private *tp)
3897{
3898 rtl_writephy(tp, 0x1f, 0x0000);
3899 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3900}
3901
3902static void r810x_phy_power_up(struct rtl8169_private *tp)
3903{
3904 rtl_writephy(tp, 0x1f, 0x0000);
3905 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3906}
3907
3908static void r810x_pll_power_down(struct rtl8169_private *tp)
3909{
0004299a
HW		 3910 void __iomem *ioaddr = tp->mmio_addr;
3911
649b3b8c 3912 if (rtl_wol_pll_power_down(tp))
065c27c1 3913 return;
065c27c1 3914
3915 r810x_phy_power_down(tp);
0004299a
HW		 3916
3917 switch (tp->mac_version) {
3918 case RTL_GIGA_MAC_VER_07:
3919 case RTL_GIGA_MAC_VER_08:
3920 case RTL_GIGA_MAC_VER_09:
3921 case RTL_GIGA_MAC_VER_10:
3922 case RTL_GIGA_MAC_VER_13:
3923 case RTL_GIGA_MAC_VER_16:
3924 break;
3925 default:
3926 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3927 break;
3928 }
065c27c1 3929}
3930
3931static void r810x_pll_power_up(struct rtl8169_private *tp)
3932{
0004299a
HW		 3933 void __iomem *ioaddr = tp->mmio_addr;
3934
065c27c1 3935 r810x_phy_power_up(tp);
0004299a
HW		 3936
3937 switch (tp->mac_version) {
3938 case RTL_GIGA_MAC_VER_07:
3939 case RTL_GIGA_MAC_VER_08:
3940 case RTL_GIGA_MAC_VER_09:
3941 case RTL_GIGA_MAC_VER_10:
3942 case RTL_GIGA_MAC_VER_13:
3943 case RTL_GIGA_MAC_VER_16:
3944 break;
3945 default:
3946 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3947 break;
3948 }
065c27c1 3949}
3950
3951static void r8168_phy_power_up(struct rtl8169_private *tp)
3952{
3953 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3954 switch (tp->mac_version) {
3955 case RTL_GIGA_MAC_VER_11:
3956 case RTL_GIGA_MAC_VER_12:
3957 case RTL_GIGA_MAC_VER_17:
3958 case RTL_GIGA_MAC_VER_18:
3959 case RTL_GIGA_MAC_VER_19:
3960 case RTL_GIGA_MAC_VER_20:
3961 case RTL_GIGA_MAC_VER_21:
3962 case RTL_GIGA_MAC_VER_22:
3963 case RTL_GIGA_MAC_VER_23:
3964 case RTL_GIGA_MAC_VER_24:
3965 case RTL_GIGA_MAC_VER_25:
3966 case RTL_GIGA_MAC_VER_26:
3967 case RTL_GIGA_MAC_VER_27:
3968 case RTL_GIGA_MAC_VER_28:
3969 case RTL_GIGA_MAC_VER_31:
3970 rtl_writephy(tp, 0x0e, 0x0000);
3971 break;
3972 default:
3973 break;
3974 }
065c27c1 3975 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3976}
3977
3978static void r8168_phy_power_down(struct rtl8169_private *tp)
3979{
3980 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3981 switch (tp->mac_version) {
3982 case RTL_GIGA_MAC_VER_32:
3983 case RTL_GIGA_MAC_VER_33:
3984 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3985 break;
3986
3987 case RTL_GIGA_MAC_VER_11:
3988 case RTL_GIGA_MAC_VER_12:
3989 case RTL_GIGA_MAC_VER_17:
3990 case RTL_GIGA_MAC_VER_18:
3991 case RTL_GIGA_MAC_VER_19:
3992 case RTL_GIGA_MAC_VER_20:
3993 case RTL_GIGA_MAC_VER_21:
3994 case RTL_GIGA_MAC_VER_22:
3995 case RTL_GIGA_MAC_VER_23:
3996 case RTL_GIGA_MAC_VER_24:
3997 case RTL_GIGA_MAC_VER_25:
3998 case RTL_GIGA_MAC_VER_26:
3999 case RTL_GIGA_MAC_VER_27:
4000 case RTL_GIGA_MAC_VER_28:
4001 case RTL_GIGA_MAC_VER_31:
4002 rtl_writephy(tp, 0x0e, 0x0200);
4003 default:
4004 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4005 break;
4006 }
065c27c1 4007}
4008
4009static void r8168_pll_power_down(struct rtl8169_private *tp)
4010{
4011 void __iomem *ioaddr = tp->mmio_addr;
4012
cecb5fd7
FR		 4013 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4014 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4015 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
4804b3b3 4016 r8168dp_check_dash(tp)) {
065c27c1 4017 return;
5d2e1957 4018 }
065c27c1 4019
cecb5fd7
FR		 4020 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
4021 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
065c27c1 4022 (RTL_R16(CPlusCmd) & ASF)) {
4023 return;
4024 }
4025
01dc7fec 4026 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4027 tp->mac_version == RTL_GIGA_MAC_VER_33)
fdf6fc06 4028 rtl_ephy_write(tp, 0x19, 0xff64);
01dc7fec 4029
649b3b8c 4030 if (rtl_wol_pll_power_down(tp))
065c27c1 4031 return;
065c27c1 4032
4033 r8168_phy_power_down(tp);
4034
4035 switch (tp->mac_version) {
4036 case RTL_GIGA_MAC_VER_25:
4037 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 4038 case RTL_GIGA_MAC_VER_27:
4039 case RTL_GIGA_MAC_VER_28:
4804b3b3 4040 case RTL_GIGA_MAC_VER_31:
01dc7fec 4041 case RTL_GIGA_MAC_VER_32:
4042 case RTL_GIGA_MAC_VER_33:
065c27c1 4043 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4044 break;
4045 }
4046}
4047
4048static void r8168_pll_power_up(struct rtl8169_private *tp)
4049{
4050 void __iomem *ioaddr = tp->mmio_addr;
4051
065c27c1 4052 switch (tp->mac_version) {
4053 case RTL_GIGA_MAC_VER_25:
4054 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 4055 case RTL_GIGA_MAC_VER_27:
4056 case RTL_GIGA_MAC_VER_28:
4804b3b3 4057 case RTL_GIGA_MAC_VER_31:
01dc7fec 4058 case RTL_GIGA_MAC_VER_32:
4059 case RTL_GIGA_MAC_VER_33:
065c27c1 4060 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4061 break;
4062 }
4063
4064 r8168_phy_power_up(tp);
4065}
4066
d58d46b5
FR		 4067static void rtl_generic_op(struct rtl8169_private *tp,
4068 void (*op)(struct rtl8169_private *))
065c27c1 4069{
4070 if (op)
4071 op(tp);
4072}
4073
4074static void rtl_pll_power_down(struct rtl8169_private *tp)
4075{
d58d46b5 4076 rtl_generic_op(tp, tp->pll_power_ops.down);
065c27c1 4077}
4078
4079static void rtl_pll_power_up(struct rtl8169_private *tp)
4080{
d58d46b5 4081 rtl_generic_op(tp, tp->pll_power_ops.up);
065c27c1 4082}
4083
4084static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
4085{
4086 struct pll_power_ops *ops = &tp->pll_power_ops;
4087
4088 switch (tp->mac_version) {
4089 case RTL_GIGA_MAC_VER_07:
4090 case RTL_GIGA_MAC_VER_08:
4091 case RTL_GIGA_MAC_VER_09:
4092 case RTL_GIGA_MAC_VER_10:
4093 case RTL_GIGA_MAC_VER_16:
5a5e4443
HW		 4094 case RTL_GIGA_MAC_VER_29:
4095 case RTL_GIGA_MAC_VER_30:
7e18dca1 4096 case RTL_GIGA_MAC_VER_37:
5598bfe5 4097 case RTL_GIGA_MAC_VER_39:
065c27c1 4098 ops->down = r810x_pll_power_down;
4099 ops->up = r810x_pll_power_up;
4100 break;
4101
4102 case RTL_GIGA_MAC_VER_11:
4103 case RTL_GIGA_MAC_VER_12:
4104 case RTL_GIGA_MAC_VER_17:
4105 case RTL_GIGA_MAC_VER_18:
4106 case RTL_GIGA_MAC_VER_19:
4107 case RTL_GIGA_MAC_VER_20:
4108 case RTL_GIGA_MAC_VER_21:
4109 case RTL_GIGA_MAC_VER_22:
4110 case RTL_GIGA_MAC_VER_23:
4111 case RTL_GIGA_MAC_VER_24:
4112 case RTL_GIGA_MAC_VER_25:
4113 case RTL_GIGA_MAC_VER_26:
4114 case RTL_GIGA_MAC_VER_27:
e6de30d6 4115 case RTL_GIGA_MAC_VER_28:
4804b3b3 4116 case RTL_GIGA_MAC_VER_31:
01dc7fec 4117 case RTL_GIGA_MAC_VER_32:
4118 case RTL_GIGA_MAC_VER_33:
70090424 4119 case RTL_GIGA_MAC_VER_34:
c2218925
HW		 4120 case RTL_GIGA_MAC_VER_35:
4121 case RTL_GIGA_MAC_VER_36:
b3d7b2f2 4122 case RTL_GIGA_MAC_VER_38:
c558386b
HW		 4123 case RTL_GIGA_MAC_VER_40:
4124 case RTL_GIGA_MAC_VER_41:
065c27c1 4125 ops->down = r8168_pll_power_down;
4126 ops->up = r8168_pll_power_up;
4127 break;
4128
4129 default:
4130 ops->down = NULL;
4131 ops->up = NULL;
4132 break;
4133 }
4134}
4135
e542a226
HW		 4136static void rtl_init_rxcfg(struct rtl8169_private *tp)
4137{
4138 void __iomem *ioaddr = tp->mmio_addr;
4139
4140 switch (tp->mac_version) {
4141 case RTL_GIGA_MAC_VER_01:
4142 case RTL_GIGA_MAC_VER_02:
4143 case RTL_GIGA_MAC_VER_03:
4144 case RTL_GIGA_MAC_VER_04:
4145 case RTL_GIGA_MAC_VER_05:
4146 case RTL_GIGA_MAC_VER_06:
4147 case RTL_GIGA_MAC_VER_10:
4148 case RTL_GIGA_MAC_VER_11:
4149 case RTL_GIGA_MAC_VER_12:
4150 case RTL_GIGA_MAC_VER_13:
4151 case RTL_GIGA_MAC_VER_14:
4152 case RTL_GIGA_MAC_VER_15:
4153 case RTL_GIGA_MAC_VER_16:
4154 case RTL_GIGA_MAC_VER_17:
4155 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4156 break;
4157 case RTL_GIGA_MAC_VER_18:
4158 case RTL_GIGA_MAC_VER_19:
4159 case RTL_GIGA_MAC_VER_20:
4160 case RTL_GIGA_MAC_VER_21:
4161 case RTL_GIGA_MAC_VER_22:
4162 case RTL_GIGA_MAC_VER_23:
4163 case RTL_GIGA_MAC_VER_24:
eb2dc35d 4164 case RTL_GIGA_MAC_VER_34:
e542a226
HW		 4165 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4166 break;
4167 default:
4168 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
4169 break;
4170 }
4171}
4172
92fc43b4
HW		 4173static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4174{
4175 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
4176}
4177
d58d46b5
FR		 4178static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4179{
9c5028e9 4180 void __iomem *ioaddr = tp->mmio_addr;
4181
4182 RTL_W8(Cfg9346, Cfg9346_Unlock);
d58d46b5 4183 rtl_generic_op(tp, tp->jumbo_ops.enable);
9c5028e9 4184 RTL_W8(Cfg9346, Cfg9346_Lock);
d58d46b5
FR		 4185}
4186
4187static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4188{
9c5028e9 4189 void __iomem *ioaddr = tp->mmio_addr;
4190
4191 RTL_W8(Cfg9346, Cfg9346_Unlock);
d58d46b5 4192 rtl_generic_op(tp, tp->jumbo_ops.disable);
9c5028e9 4193 RTL_W8(Cfg9346, Cfg9346_Lock);
d58d46b5
FR		 4194}
4195
4196static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4197{
4198 void __iomem *ioaddr = tp->mmio_addr;
4199
4200 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4201 RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
4202 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
4203}
4204
4205static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4206{
4207 void __iomem *ioaddr = tp->mmio_addr;
4208
4209 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4210 RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
4211 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
4212}
4213
4214static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4215{
4216 void __iomem *ioaddr = tp->mmio_addr;
4217
4218 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4219}
4220
4221static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4222{
4223 void __iomem *ioaddr = tp->mmio_addr;
4224
4225 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4226}
4227
4228static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4229{
4230 void __iomem *ioaddr = tp->mmio_addr;
d58d46b5
FR		 4231
4232 RTL_W8(MaxTxPacketSize, 0x3f);
4233 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4234 RTL_W8(Config4, RTL_R8(Config4) | 0x01);
4512ff9f 4235 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
d58d46b5
FR		 4236}
4237
4238static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4239{
4240 void __iomem *ioaddr = tp->mmio_addr;
d58d46b5
FR		 4241
4242 RTL_W8(MaxTxPacketSize, 0x0c);
4243 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4244 RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
4512ff9f 4245 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
d58d46b5
FR		 4246}
4247
4248static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4249{
4250 rtl_tx_performance_tweak(tp->pci_dev,
4251 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4252}
4253
4254static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4255{
4256 rtl_tx_performance_tweak(tp->pci_dev,
4257 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4258}
4259
4260static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4261{
4262 void __iomem *ioaddr = tp->mmio_addr;
4263
4264 r8168b_0_hw_jumbo_enable(tp);
4265
4266 RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
4267}
4268
4269static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4270{
4271 void __iomem *ioaddr = tp->mmio_addr;
4272
4273 r8168b_0_hw_jumbo_disable(tp);
4274
4275 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4276}
4277
4278static void __devinit rtl_init_jumbo_ops(struct rtl8169_private *tp)
4279{
4280 struct jumbo_ops *ops = &tp->jumbo_ops;
4281
4282 switch (tp->mac_version) {
4283 case RTL_GIGA_MAC_VER_11:
4284 ops->disable = r8168b_0_hw_jumbo_disable;
4285 ops->enable = r8168b_0_hw_jumbo_enable;
4286 break;
4287 case RTL_GIGA_MAC_VER_12:
4288 case RTL_GIGA_MAC_VER_17:
4289 ops->disable = r8168b_1_hw_jumbo_disable;
4290 ops->enable = r8168b_1_hw_jumbo_enable;
4291 break;
4292 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
4293 case RTL_GIGA_MAC_VER_19:
4294 case RTL_GIGA_MAC_VER_20:
4295 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
4296 case RTL_GIGA_MAC_VER_22:
4297 case RTL_GIGA_MAC_VER_23:
4298 case RTL_GIGA_MAC_VER_24:
4299 case RTL_GIGA_MAC_VER_25:
4300 case RTL_GIGA_MAC_VER_26:
4301 ops->disable = r8168c_hw_jumbo_disable;
4302 ops->enable = r8168c_hw_jumbo_enable;
4303 break;
4304 case RTL_GIGA_MAC_VER_27:
4305 case RTL_GIGA_MAC_VER_28:
4306 ops->disable = r8168dp_hw_jumbo_disable;
4307 ops->enable = r8168dp_hw_jumbo_enable;
4308 break;
4309 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
4310 case RTL_GIGA_MAC_VER_32:
4311 case RTL_GIGA_MAC_VER_33:
4312 case RTL_GIGA_MAC_VER_34:
4313 ops->disable = r8168e_hw_jumbo_disable;
4314 ops->enable = r8168e_hw_jumbo_enable;
4315 break;
4316
4317 /*
4318 * No action needed for jumbo frames with 8169.
4319 * No jumbo for 810x at all.
4320 */
c558386b
HW		 4321 case RTL_GIGA_MAC_VER_40:
4322 case RTL_GIGA_MAC_VER_41:
d58d46b5
FR		 4323 default:
4324 ops->disable = NULL;
4325 ops->enable = NULL;
4326 break;
4327 }
4328}
4329
ffc46952
FR		 4330DECLARE_RTL_COND(rtl_chipcmd_cond)
4331{
4332 void __iomem *ioaddr = tp->mmio_addr;
4333
4334 return RTL_R8(ChipCmd) & CmdReset;
4335}
4336
6f43adc8
FR		 4337static void rtl_hw_reset(struct rtl8169_private *tp)
4338{
4339 void __iomem *ioaddr = tp->mmio_addr;
6f43adc8 4340
6f43adc8
FR		 4341 RTL_W8(ChipCmd, CmdReset);
4342
ffc46952 4343 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
6f43adc8
FR		 4344}
4345
b6ffd97f 4346static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
953a12cc 4347{
b6ffd97f
FR		 4348 struct rtl_fw *rtl_fw;
4349 const char *name;
4350 int rc = -ENOMEM;
953a12cc 4351
b6ffd97f
FR		 4352 name = rtl_lookup_firmware_name(tp);
4353 if (!name)
4354 goto out_no_firmware;
953a12cc 4355
b6ffd97f
FR		 4356 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4357 if (!rtl_fw)
4358 goto err_warn;
31bd204f 4359
b6ffd97f
FR		 4360 rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
4361 if (rc < 0)
4362 goto err_free;
4363
fd112f2e
FR		 4364 rc = rtl_check_firmware(tp, rtl_fw);
4365 if (rc < 0)
4366 goto err_release_firmware;
4367
b6ffd97f
FR		 4368 tp->rtl_fw = rtl_fw;
4369out:
4370 return;
4371
fd112f2e
FR		 4372err_release_firmware:
4373 release_firmware(rtl_fw->fw);
b6ffd97f
FR		 4374err_free:
4375 kfree(rtl_fw);
4376err_warn:
4377 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4378 name, rc);
4379out_no_firmware:
4380 tp->rtl_fw = NULL;
4381 goto out;
4382}
4383
4384static void rtl_request_firmware(struct rtl8169_private *tp)
4385{
4386 if (IS_ERR(tp->rtl_fw))
4387 rtl_request_uncached_firmware(tp);
953a12cc
FR		 4388}
4389
92fc43b4
HW		 4390static void rtl_rx_close(struct rtl8169_private *tp)
4391{
4392 void __iomem *ioaddr = tp->mmio_addr;
92fc43b4 4393
1687b566 4394 RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
92fc43b4
HW		 4395}
4396
ffc46952
FR		 4397DECLARE_RTL_COND(rtl_npq_cond)
4398{
4399 void __iomem *ioaddr = tp->mmio_addr;
4400
4401 return RTL_R8(TxPoll) & NPQ;
4402}
4403
4404DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4405{
4406 void __iomem *ioaddr = tp->mmio_addr;
4407
4408 return RTL_R32(TxConfig) & TXCFG_EMPTY;
4409}
4410
e6de30d6 4411static void rtl8169_hw_reset(struct rtl8169_private *tp)
1da177e4 4412{
e6de30d6 4413 void __iomem *ioaddr = tp->mmio_addr;
4414
1da177e4 4415 /* Disable interrupts */
811fd301 4416 rtl8169_irq_mask_and_ack(tp);
1da177e4 4417
92fc43b4
HW		 4418 rtl_rx_close(tp);
4419
5d2e1957 4420 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4804b3b3 4421 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4422 tp->mac_version == RTL_GIGA_MAC_VER_31) {
ffc46952 4423 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
c2218925
HW		 4424 } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
4425 tp->mac_version == RTL_GIGA_MAC_VER_35 ||
7e18dca1 4426 tp->mac_version == RTL_GIGA_MAC_VER_36 ||
b3d7b2f2 4427 tp->mac_version == RTL_GIGA_MAC_VER_37 ||
c558386b
HW		 4428 tp->mac_version == RTL_GIGA_MAC_VER_40 ||
4429 tp->mac_version == RTL_GIGA_MAC_VER_41 ||
b3d7b2f2 4430 tp->mac_version == RTL_GIGA_MAC_VER_38) {
c2b0c1e7 4431 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
ffc46952 4432 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
92fc43b4
HW		 4433 } else {
4434 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4435 udelay(100);
e6de30d6 4436 }
4437
92fc43b4 4438 rtl_hw_reset(tp);
1da177e4
LT		 4439}
4440
7f796d83 4441static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 4442{
4443 void __iomem *ioaddr = tp->mmio_addr;
9cb427b6
FR		 4444
4445 /* Set DMA burst size and Interframe Gap Time */
4446 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4447 (InterFrameGap << TxInterFrameGapShift));
4448}
4449
07ce4064 4450static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 4451{
4452 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 4453
07ce4064
FR		 4454 tp->hw_start(dev);
4455
da78dbff 4456 rtl_irq_enable_all(tp);
07ce4064
FR		 4457}
4458
7f796d83
FR		 4459static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
4460 void __iomem *ioaddr)
4461{
4462 /*
4463 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4464 * register to be written before TxDescAddrLow to work.
4465 * Switching from MMIO to I/O access fixes the issue as well.
4466 */
4467 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
284901a9 4468 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
7f796d83 4469 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
284901a9 4470 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 4471}
4472
4473static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4474{
4475 u16 cmd;
4476
4477 cmd = RTL_R16(CPlusCmd);
4478 RTL_W16(CPlusCmd, cmd);
4479 return cmd;
4480}
4481
fdd7b4c3 4482static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
7f796d83
FR		 4483{
4484 /* Low hurts. Let's disable the filtering. */
207d6e87 4485 RTL_W16(RxMaxSize, rx_buf_sz + 1);
7f796d83
FR		 4486}
4487
6dccd16b
FR		 4488static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4489{
3744100e 4490 static const struct rtl_cfg2_info {
6dccd16b
FR		 4491 u32 mac_version;
4492 u32 clk;
4493 u32 val;
4494 } cfg2_info [] = {
4495 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4496 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4497 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4498 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3744100e
FR		 4499 };
4500 const struct rtl_cfg2_info *p = cfg2_info;
6dccd16b
FR		 4501 unsigned int i;
4502 u32 clk;
4503
4504 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 4505 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 4506 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4507 RTL_W32(0x7c, p->val);
4508 break;
4509 }
4510 }
4511}
4512
e6b763ea
FR		 4513static void rtl_set_rx_mode(struct net_device *dev)
4514{
4515 struct rtl8169_private *tp = netdev_priv(dev);
4516 void __iomem *ioaddr = tp->mmio_addr;
4517 u32 mc_filter[2]; /* Multicast hash filter */
4518 int rx_mode;
4519 u32 tmp = 0;
4520
4521 if (dev->flags & IFF_PROMISC) {
4522 /* Unconditionally log net taps. */
4523 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4524 rx_mode =
4525 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4526 AcceptAllPhys;
4527 mc_filter[1] = mc_filter[0] = 0xffffffff;
4528 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4529 (dev->flags & IFF_ALLMULTI)) {
4530 /* Too many to filter perfectly -- accept all multicasts. */
4531 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4532 mc_filter[1] = mc_filter[0] = 0xffffffff;
4533 } else {
4534 struct netdev_hw_addr *ha;
4535
4536 rx_mode = AcceptBroadcast | AcceptMyPhys;
4537 mc_filter[1] = mc_filter[0] = 0;
4538 netdev_for_each_mc_addr(ha, dev) {
4539 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4540 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4541 rx_mode |= AcceptMulticast;
4542 }
4543 }
4544
4545 if (dev->features & NETIF_F_RXALL)
4546 rx_mode |= (AcceptErr | AcceptRunt);
4547
4548 tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4549
4550 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4551 u32 data = mc_filter[0];
4552
4553 mc_filter[0] = swab32(mc_filter[1]);
4554 mc_filter[1] = swab32(data);
4555 }
4556
0481776b
NW		 4557 if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4558 mc_filter[1] = mc_filter[0] = 0xffffffff;
4559
e6b763ea
FR		 4560 RTL_W32(MAR0 + 4, mc_filter[1]);
4561 RTL_W32(MAR0 + 0, mc_filter[0]);
4562
4563 RTL_W32(RxConfig, tmp);
4564}
4565
07ce4064
FR		 4566static void rtl_hw_start_8169(struct net_device *dev)
4567{
4568 struct rtl8169_private *tp = netdev_priv(dev);
4569 void __iomem *ioaddr = tp->mmio_addr;
4570 struct pci_dev *pdev = tp->pci_dev;
07ce4064 4571
9cb427b6
FR		 4572 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4573 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4574 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4575 }
4576
1da177e4 4577 RTL_W8(Cfg9346, Cfg9346_Unlock);
cecb5fd7
FR		 4578 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4579 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4580 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4581 tp->mac_version == RTL_GIGA_MAC_VER_04)
9cb427b6
FR		 4582 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4583
e542a226
HW		 4584 rtl_init_rxcfg(tp);
4585
f0298f81 4586 RTL_W8(EarlyTxThres, NoEarlyTx);
1da177e4 4587
6f0333b8 4588 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
1da177e4 4589
cecb5fd7
FR		 4590 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4591 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4592 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4593 tp->mac_version == RTL_GIGA_MAC_VER_04)
c946b304 4594 rtl_set_rx_tx_config_registers(tp);
1da177e4 4595
7f796d83 4596 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 4597
cecb5fd7
FR		 4598 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4599 tp->mac_version == RTL_GIGA_MAC_VER_03) {
06fa7358 4600 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1da177e4 4601 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 4602 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 4603 }
4604
bcf0bf90
FR		 4605 RTL_W16(CPlusCmd, tp->cp_cmd);
4606
6dccd16b
FR		 4607 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4608
1da177e4
LT		 4609 /*
4610 * Undocumented corner. Supposedly:
4611 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4612 */
4613 RTL_W16(IntrMitigate, 0x0000);
4614
7f796d83 4615 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 4616
cecb5fd7
FR		 4617 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4618 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4619 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
4620 tp->mac_version != RTL_GIGA_MAC_VER_04) {
c946b304
FR		 4621 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4622 rtl_set_rx_tx_config_registers(tp);
4623 }
4624
1da177e4 4625 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 4626
4627 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4628 RTL_R8(IntrMask);
1da177e4
LT		 4629
4630 RTL_W32(RxMissed, 0);
4631
07ce4064 4632 rtl_set_rx_mode(dev);
1da177e4
LT		 4633
4634 /* no early-rx interrupts */
4635 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
07ce4064 4636}
1da177e4 4637
beb1fe18
HW		 4638static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4639{
4640 if (tp->csi_ops.write)
52989f0e 4641 tp->csi_ops.write(tp, addr, value);
beb1fe18
HW		 4642}
4643
4644static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4645{
52989f0e 4646 return tp->csi_ops.read ? tp->csi_ops.read(tp, addr) : ~0;
beb1fe18
HW		 4647}
4648
4649static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits)
dacf8154
FR		 4650{
4651 u32 csi;
4652
beb1fe18
HW		 4653 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4654 rtl_csi_write(tp, 0x070c, csi | bits);
4655}
4656
4657static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
4658{
4659 rtl_csi_access_enable(tp, 0x17000000);
650e8d5d 4660}
4661
beb1fe18 4662static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
e6de30d6 4663{
beb1fe18 4664 rtl_csi_access_enable(tp, 0x27000000);
e6de30d6 4665}
4666
ffc46952
FR		 4667DECLARE_RTL_COND(rtl_csiar_cond)
4668{
4669 void __iomem *ioaddr = tp->mmio_addr;
4670
4671 return RTL_R32(CSIAR) & CSIAR_FLAG;
4672}
4673
52989f0e 4674static void r8169_csi_write(struct rtl8169_private *tp, int addr, int value)
650e8d5d 4675{
52989f0e 4676 void __iomem *ioaddr = tp->mmio_addr;
beb1fe18
HW		 4677
4678 RTL_W32(CSIDR, value);
4679 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4680 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4681
ffc46952 4682 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
beb1fe18
HW		 4683}
4684
52989f0e 4685static u32 r8169_csi_read(struct rtl8169_private *tp, int addr)
beb1fe18 4686{
52989f0e 4687 void __iomem *ioaddr = tp->mmio_addr;
beb1fe18
HW		 4688
4689 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
4690 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4691
ffc46952
FR		 4692 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4693 RTL_R32(CSIDR) : ~0;
beb1fe18
HW		 4694}
4695
52989f0e 4696static void r8402_csi_write(struct rtl8169_private *tp, int addr, int value)
7e18dca1 4697{
52989f0e 4698 void __iomem *ioaddr = tp->mmio_addr;
7e18dca1
HW		 4699
4700 RTL_W32(CSIDR, value);
4701 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4702 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
4703 CSIAR_FUNC_NIC);
4704
ffc46952 4705 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
7e18dca1
HW		 4706}
4707
52989f0e 4708static u32 r8402_csi_read(struct rtl8169_private *tp, int addr)
7e18dca1 4709{
52989f0e 4710 void __iomem *ioaddr = tp->mmio_addr;
7e18dca1
HW		 4711
4712 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
4713 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4714
ffc46952
FR		 4715 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4716 RTL_R32(CSIDR) : ~0;
7e18dca1
HW		 4717}
4718
beb1fe18
HW		 4719static void __devinit rtl_init_csi_ops(struct rtl8169_private *tp)
4720{
4721 struct csi_ops *ops = &tp->csi_ops;
4722
4723 switch (tp->mac_version) {
4724 case RTL_GIGA_MAC_VER_01:
4725 case RTL_GIGA_MAC_VER_02:
4726 case RTL_GIGA_MAC_VER_03:
4727 case RTL_GIGA_MAC_VER_04:
4728 case RTL_GIGA_MAC_VER_05:
4729 case RTL_GIGA_MAC_VER_06:
4730 case RTL_GIGA_MAC_VER_10:
4731 case RTL_GIGA_MAC_VER_11:
4732 case RTL_GIGA_MAC_VER_12:
4733 case RTL_GIGA_MAC_VER_13:
4734 case RTL_GIGA_MAC_VER_14:
4735 case RTL_GIGA_MAC_VER_15:
4736 case RTL_GIGA_MAC_VER_16:
4737 case RTL_GIGA_MAC_VER_17:
4738 ops->write = NULL;
4739 ops->read = NULL;
4740 break;
4741
7e18dca1 4742 case RTL_GIGA_MAC_VER_37:
b3d7b2f2 4743 case RTL_GIGA_MAC_VER_38:
7e18dca1
HW		 4744 ops->write = r8402_csi_write;
4745 ops->read = r8402_csi_read;
4746 break;
4747
beb1fe18
HW		 4748 default:
4749 ops->write = r8169_csi_write;
4750 ops->read = r8169_csi_read;
4751 break;
4752 }
dacf8154
FR		 4753}
4754
4755struct ephy_info {
4756 unsigned int offset;
4757 u16 mask;
4758 u16 bits;
4759};
4760
fdf6fc06
FR		 4761static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
4762 int len)
dacf8154
FR		 4763{
4764 u16 w;
4765
4766 while (len-- > 0) {
fdf6fc06
FR		 4767 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4768 rtl_ephy_write(tp, e->offset, w);
dacf8154
FR		 4769 e++;
4770 }
4771}
4772
b726e493
FR		 4773static void rtl_disable_clock_request(struct pci_dev *pdev)
4774{
7d7903b2
JL		 4775 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
4776 PCI_EXP_LNKCTL_CLKREQ_EN);
b726e493
FR		 4777}
4778
e6de30d6 4779static void rtl_enable_clock_request(struct pci_dev *pdev)
4780{
7d7903b2
JL		 4781 pcie_capability_set_word(pdev, PCI_EXP_LNKCTL,
4782 PCI_EXP_LNKCTL_CLKREQ_EN);
e6de30d6 4783}
4784
b726e493
FR		 4785#define R8168_CPCMD_QUIRK_MASK (\
4786 EnableBist | \
4787 Mac_dbgo_oe | \
4788 Force_half_dup | \
4789 Force_rxflow_en | \
4790 Force_txflow_en | \
4791 Cxpl_dbg_sel | \
4792 ASF | \
4793 PktCntrDisable | \
4794 Mac_dbgo_sel)
4795
beb1fe18 4796static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
219a1e9d 4797{
beb1fe18
HW		 4798 void __iomem *ioaddr = tp->mmio_addr;
4799 struct pci_dev *pdev = tp->pci_dev;
4800
b726e493
FR		 4801 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4802
4803 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4804
2e68ae44
FR		 4805 rtl_tx_performance_tweak(pdev,
4806 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
219a1e9d
FR		 4807}
4808
beb1fe18 4809static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
219a1e9d 4810{
beb1fe18
HW		 4811 void __iomem *ioaddr = tp->mmio_addr;
4812
4813 rtl_hw_start_8168bb(tp);
b726e493 4814
f0298f81 4815 RTL_W8(MaxTxPacketSize, TxPacketMax);
b726e493
FR		 4816
4817 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
219a1e9d
FR		 4818}
4819
beb1fe18 4820static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
219a1e9d 4821{
beb1fe18
HW		 4822 void __iomem *ioaddr = tp->mmio_addr;
4823 struct pci_dev *pdev = tp->pci_dev;
4824
b726e493
FR		 4825 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4826
4827 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4828
219a1e9d 4829 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
b726e493
FR		 4830
4831 rtl_disable_clock_request(pdev);
4832
4833 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
219a1e9d
FR		 4834}
4835
beb1fe18 4836static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
219a1e9d 4837{
350f7596 4838 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 4839 { 0x01, 0, 0x0001 },
4840 { 0x02, 0x0800, 0x1000 },
4841 { 0x03, 0, 0x0042 },
4842 { 0x06, 0x0080, 0x0000 },
4843 { 0x07, 0, 0x2000 }
4844 };
4845
beb1fe18 4846 rtl_csi_access_enable_2(tp);
b726e493 4847
fdf6fc06 4848 rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
b726e493 4849
beb1fe18 4850 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 4851}
4852
beb1fe18 4853static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
ef3386f0 4854{
beb1fe18
HW		 4855 void __iomem *ioaddr = tp->mmio_addr;
4856 struct pci_dev *pdev = tp->pci_dev;
4857
4858 rtl_csi_access_enable_2(tp);
ef3386f0
FR		 4859
4860 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4861
4862 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4863
4864 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4865}
4866
beb1fe18 4867static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
7f3e3d3a 4868{
beb1fe18
HW		 4869 void __iomem *ioaddr = tp->mmio_addr;
4870 struct pci_dev *pdev = tp->pci_dev;
4871
4872 rtl_csi_access_enable_2(tp);
7f3e3d3a
FR		 4873
4874 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4875
4876 /* Magic. */
4877 RTL_W8(DBG_REG, 0x20);
4878
f0298f81 4879 RTL_W8(MaxTxPacketSize, TxPacketMax);
7f3e3d3a
FR		 4880
4881 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4882
4883 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4884}
4885
beb1fe18 4886static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
219a1e9d 4887{
beb1fe18 4888 void __iomem *ioaddr = tp->mmio_addr;
350f7596 4889 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 4890 { 0x02, 0x0800, 0x1000 },
4891 { 0x03, 0, 0x0002 },
4892 { 0x06, 0x0080, 0x0000 }
4893 };
4894
beb1fe18 4895 rtl_csi_access_enable_2(tp);
b726e493
FR		 4896
4897 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4898
fdf6fc06 4899 rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
b726e493 4900
beb1fe18 4901 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 4902}
4903
beb1fe18 4904static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
219a1e9d 4905{
350f7596 4906 static const struct ephy_info e_info_8168c_2[] = {
b726e493
FR		 4907 { 0x01, 0, 0x0001 },
4908 { 0x03, 0x0400, 0x0220 }
4909 };
4910
beb1fe18 4911 rtl_csi_access_enable_2(tp);
b726e493 4912
fdf6fc06 4913 rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
b726e493 4914
beb1fe18 4915 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 4916}
4917
beb1fe18 4918static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
197ff761 4919{
beb1fe18 4920 rtl_hw_start_8168c_2(tp);
197ff761
FR		 4921}
4922
beb1fe18 4923static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
6fb07058 4924{
beb1fe18 4925 rtl_csi_access_enable_2(tp);
6fb07058 4926
beb1fe18 4927 __rtl_hw_start_8168cp(tp);
6fb07058
FR		 4928}
4929
beb1fe18 4930static void rtl_hw_start_8168d(struct rtl8169_private *tp)
5b538df9 4931{
beb1fe18
HW		 4932 void __iomem *ioaddr = tp->mmio_addr;
4933 struct pci_dev *pdev = tp->pci_dev;
4934
4935 rtl_csi_access_enable_2(tp);
5b538df9
FR		 4936
4937 rtl_disable_clock_request(pdev);
4938
f0298f81 4939 RTL_W8(MaxTxPacketSize, TxPacketMax);
5b538df9
FR		 4940
4941 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4942
4943 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4944}
4945
beb1fe18 4946static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4804b3b3 4947{
beb1fe18
HW		 4948 void __iomem *ioaddr = tp->mmio_addr;
4949 struct pci_dev *pdev = tp->pci_dev;
4950
4951 rtl_csi_access_enable_1(tp);
4804b3b3 4952
4953 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4954
4955 RTL_W8(MaxTxPacketSize, TxPacketMax);
4956
4957 rtl_disable_clock_request(pdev);
4958}
4959
beb1fe18 4960static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
e6de30d6 4961{
beb1fe18
HW		 4962 void __iomem *ioaddr = tp->mmio_addr;
4963 struct pci_dev *pdev = tp->pci_dev;
e6de30d6 4964 static const struct ephy_info e_info_8168d_4[] = {
4965 { 0x0b, ~0, 0x48 },
4966 { 0x19, 0x20, 0x50 },
4967 { 0x0c, ~0, 0x20 }
4968 };
4969 int i;
4970
beb1fe18 4971 rtl_csi_access_enable_1(tp);
e6de30d6 4972
4973 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4974
4975 RTL_W8(MaxTxPacketSize, TxPacketMax);
4976
4977 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4978 const struct ephy_info *e = e_info_8168d_4 + i;
4979 u16 w;
4980
fdf6fc06
FR		 4981 w = rtl_ephy_read(tp, e->offset);
4982 rtl_ephy_write(tp, 0x03, (w & e->mask) | e->bits);
e6de30d6 4983 }
4984
4985 rtl_enable_clock_request(pdev);
4986}
4987
beb1fe18 4988static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
01dc7fec 4989{
beb1fe18
HW		 4990 void __iomem *ioaddr = tp->mmio_addr;
4991 struct pci_dev *pdev = tp->pci_dev;
70090424 4992 static const struct ephy_info e_info_8168e_1[] = {
01dc7fec 4993 { 0x00, 0x0200, 0x0100 },
4994 { 0x00, 0x0000, 0x0004 },
4995 { 0x06, 0x0002, 0x0001 },
4996 { 0x06, 0x0000, 0x0030 },
4997 { 0x07, 0x0000, 0x2000 },
4998 { 0x00, 0x0000, 0x0020 },
4999 { 0x03, 0x5800, 0x2000 },
5000 { 0x03, 0x0000, 0x0001 },
5001 { 0x01, 0x0800, 0x1000 },
5002 { 0x07, 0x0000, 0x4000 },
5003 { 0x1e, 0x0000, 0x2000 },
5004 { 0x19, 0xffff, 0xfe6c },
5005 { 0x0a, 0x0000, 0x0040 }
5006 };
5007
beb1fe18 5008 rtl_csi_access_enable_2(tp);
01dc7fec 5009
fdf6fc06 5010 rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
01dc7fec 5011
5012 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5013
5014 RTL_W8(MaxTxPacketSize, TxPacketMax);
5015
5016 rtl_disable_clock_request(pdev);
5017
5018 /* Reset tx FIFO pointer */
cecb5fd7
FR		 5019 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
5020 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
01dc7fec 5021
cecb5fd7 5022 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
01dc7fec 5023}
5024
beb1fe18 5025static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
70090424 5026{
beb1fe18
HW		 5027 void __iomem *ioaddr = tp->mmio_addr;
5028 struct pci_dev *pdev = tp->pci_dev;
70090424
HW		 5029 static const struct ephy_info e_info_8168e_2[] = {
5030 { 0x09, 0x0000, 0x0080 },
5031 { 0x19, 0x0000, 0x0224 }
5032 };
5033
beb1fe18 5034 rtl_csi_access_enable_1(tp);
70090424 5035
fdf6fc06 5036 rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
70090424
HW		 5037
5038 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5039
fdf6fc06
FR		 5040 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5041 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5042 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5043 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5044 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5045 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
5046 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5047 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
70090424 5048
3090bd9a 5049 RTL_W8(MaxTxPacketSize, EarlySize);
70090424 5050
70090424
HW		 5051 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5052 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5053
5054 /* Adjust EEE LED frequency */
5055 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5056
5057 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5058 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
d64ec841 5059 RTL_W8(Config5, (RTL_R8(Config5) & ~Spi_en) | ASPM_en);
5060 RTL_W8(Config2, RTL_R8(Config2) | ClkReqEn);
70090424
HW		 5061}
5062
5f886e08 5063static void rtl_hw_start_8168f(struct rtl8169_private *tp)
c2218925 5064{
beb1fe18
HW		 5065 void __iomem *ioaddr = tp->mmio_addr;
5066 struct pci_dev *pdev = tp->pci_dev;
c2218925 5067
5f886e08 5068 rtl_csi_access_enable_2(tp);
c2218925
HW		 5069
5070 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5071
fdf6fc06
FR		 5072 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5073 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5074 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5075 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5076 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5077 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5078 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5079 rtl_w1w0_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5080 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5081 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
c2218925
HW		 5082
5083 RTL_W8(MaxTxPacketSize, EarlySize);
5084
c2218925
HW		 5085 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5086 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
c2218925 5087 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
d64ec841 5088 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN | FORCE_CLK);
5089 RTL_W8(Config5, (RTL_R8(Config5) & ~Spi_en) | ASPM_en);
5090 RTL_W8(Config2, RTL_R8(Config2) | ClkReqEn);
c2218925
HW		 5091}
5092
5f886e08
HW		 5093static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5094{
5095 void __iomem *ioaddr = tp->mmio_addr;
5096 static const struct ephy_info e_info_8168f_1[] = {
5097 { 0x06, 0x00c0, 0x0020 },
5098 { 0x08, 0x0001, 0x0002 },
5099 { 0x09, 0x0000, 0x0080 },
5100 { 0x19, 0x0000, 0x0224 }
5101 };
5102
5103 rtl_hw_start_8168f(tp);
5104
fdf6fc06 5105 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5f886e08 5106
fdf6fc06 5107 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5f886e08
HW		 5108
5109 /* Adjust EEE LED frequency */
5110 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5111}
5112
b3d7b2f2
HW		 5113static void rtl_hw_start_8411(struct rtl8169_private *tp)
5114{
b3d7b2f2
HW		 5115 static const struct ephy_info e_info_8168f_1[] = {
5116 { 0x06, 0x00c0, 0x0020 },
5117 { 0x0f, 0xffff, 0x5200 },
5118 { 0x1e, 0x0000, 0x4000 },
5119 { 0x19, 0x0000, 0x0224 }
5120 };
5121
5122 rtl_hw_start_8168f(tp);
5123
fdf6fc06 5124 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
b3d7b2f2 5125
fdf6fc06 5126 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
b3d7b2f2
HW		 5127}
5128
c558386b
HW		 5129static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5130{
5131 void __iomem *ioaddr = tp->mmio_addr;
5132 struct pci_dev *pdev = tp->pci_dev;
5133
5134 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
5135 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5136 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5137 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5138
5139 rtl_csi_access_enable_1(tp);
5140
5141 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5142
5143 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5144 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5145
5146 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
d64ec841 5147 RTL_W32(MISC, (RTL_R32(MISC) | FORCE_CLK) & ~RXDV_GATED_EN);
c558386b 5148 RTL_W8(MaxTxPacketSize, EarlySize);
d64ec841 5149 RTL_W8(Config5, RTL_R8(Config5) | ASPM_en);
5150 RTL_W8(Config2, RTL_R8(Config2) | ClkReqEn);
c558386b
HW		 5151
5152 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5153 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5154
5155 /* Adjust EEE LED frequency */
5156 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5157
5158 rtl_w1w0_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x02, ERIAR_EXGMAC);
5159}
5160
07ce4064
FR		 5161static void rtl_hw_start_8168(struct net_device *dev)
5162{
2dd99530
FR		 5163 struct rtl8169_private *tp = netdev_priv(dev);
5164 void __iomem *ioaddr = tp->mmio_addr;
5165
5166 RTL_W8(Cfg9346, Cfg9346_Unlock);
5167
f0298f81 5168 RTL_W8(MaxTxPacketSize, TxPacketMax);
2dd99530 5169
6f0333b8 5170 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
2dd99530 5171
0e485150 5172 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 5173
5174 RTL_W16(CPlusCmd, tp->cp_cmd);
5175
0e485150 5176 RTL_W16(IntrMitigate, 0x5151);
2dd99530 5177
0e485150 5178 /* Work around for RxFIFO overflow. */
811fd301 5179 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
da78dbff
FR		 5180 tp->event_slow |= RxFIFOOver | PCSTimeout;
5181 tp->event_slow &= ~RxOverflow;
0e485150
FR		 5182 }
5183
5184 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530 5185
b8363901
FR		 5186 rtl_set_rx_mode(dev);
5187
5188 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
5189 (InterFrameGap << TxInterFrameGapShift));
2dd99530
FR		 5190
5191 RTL_R8(IntrMask);
5192
219a1e9d
FR		 5193 switch (tp->mac_version) {
5194 case RTL_GIGA_MAC_VER_11:
beb1fe18 5195 rtl_hw_start_8168bb(tp);
4804b3b3 5196 break;
219a1e9d
FR		 5197
5198 case RTL_GIGA_MAC_VER_12:
5199 case RTL_GIGA_MAC_VER_17:
beb1fe18 5200 rtl_hw_start_8168bef(tp);
4804b3b3 5201 break;
219a1e9d
FR		 5202
5203 case RTL_GIGA_MAC_VER_18:
beb1fe18 5204 rtl_hw_start_8168cp_1(tp);
4804b3b3 5205 break;
219a1e9d
FR		 5206
5207 case RTL_GIGA_MAC_VER_19:
beb1fe18 5208 rtl_hw_start_8168c_1(tp);
4804b3b3 5209 break;
219a1e9d
FR		 5210
5211 case RTL_GIGA_MAC_VER_20:
beb1fe18 5212 rtl_hw_start_8168c_2(tp);
4804b3b3 5213 break;
219a1e9d 5214
197ff761 5215 case RTL_GIGA_MAC_VER_21:
beb1fe18 5216 rtl_hw_start_8168c_3(tp);
4804b3b3 5217 break;
197ff761 5218
6fb07058 5219 case RTL_GIGA_MAC_VER_22:
beb1fe18 5220 rtl_hw_start_8168c_4(tp);
4804b3b3 5221 break;
6fb07058 5222
ef3386f0 5223 case RTL_GIGA_MAC_VER_23:
beb1fe18 5224 rtl_hw_start_8168cp_2(tp);
4804b3b3 5225 break;
ef3386f0 5226
7f3e3d3a 5227 case RTL_GIGA_MAC_VER_24:
beb1fe18 5228 rtl_hw_start_8168cp_3(tp);
4804b3b3 5229 break;
7f3e3d3a 5230
5b538df9 5231 case RTL_GIGA_MAC_VER_25:
daf9df6d 5232 case RTL_GIGA_MAC_VER_26:
5233 case RTL_GIGA_MAC_VER_27:
beb1fe18 5234 rtl_hw_start_8168d(tp);
4804b3b3 5235 break;
5b538df9 5236
e6de30d6 5237 case RTL_GIGA_MAC_VER_28:
beb1fe18 5238 rtl_hw_start_8168d_4(tp);
4804b3b3 5239 break;
cecb5fd7 5240
4804b3b3 5241 case RTL_GIGA_MAC_VER_31:
beb1fe18 5242 rtl_hw_start_8168dp(tp);
4804b3b3 5243 break;
5244
01dc7fec 5245 case RTL_GIGA_MAC_VER_32:
5246 case RTL_GIGA_MAC_VER_33:
beb1fe18 5247 rtl_hw_start_8168e_1(tp);
70090424
HW		 5248 break;
5249 case RTL_GIGA_MAC_VER_34:
beb1fe18 5250 rtl_hw_start_8168e_2(tp);
01dc7fec 5251 break;
e6de30d6 5252
c2218925
HW		 5253 case RTL_GIGA_MAC_VER_35:
5254 case RTL_GIGA_MAC_VER_36:
beb1fe18 5255 rtl_hw_start_8168f_1(tp);
c2218925
HW		 5256 break;
5257
b3d7b2f2
HW		 5258 case RTL_GIGA_MAC_VER_38:
5259 rtl_hw_start_8411(tp);
5260 break;
5261
c558386b
HW		 5262 case RTL_GIGA_MAC_VER_40:
5263 case RTL_GIGA_MAC_VER_41:
5264 rtl_hw_start_8168g_1(tp);
5265 break;
5266
219a1e9d
FR		 5267 default:
5268 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
5269 dev->name, tp->mac_version);
4804b3b3 5270 break;
219a1e9d 5271 }
2dd99530 5272
0e485150
FR		 5273 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5274
b8363901
FR		 5275 RTL_W8(Cfg9346, Cfg9346_Lock);
5276
2dd99530 5277 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
07ce4064 5278}
1da177e4 5279
2857ffb7
FR		 5280#define R810X_CPCMD_QUIRK_MASK (\
5281 EnableBist | \
5282 Mac_dbgo_oe | \
5283 Force_half_dup | \
5edcc537 5284 Force_rxflow_en | \
2857ffb7
FR		 5285 Force_txflow_en | \
5286 Cxpl_dbg_sel | \
5287 ASF | \
5288 PktCntrDisable | \
d24e9aaf 5289 Mac_dbgo_sel)
2857ffb7 5290
beb1fe18 5291static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
2857ffb7 5292{
beb1fe18
HW		 5293 void __iomem *ioaddr = tp->mmio_addr;
5294 struct pci_dev *pdev = tp->pci_dev;
350f7596 5295 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 5296 { 0x01, 0, 0x6e65 },
5297 { 0x02, 0, 0x091f },
5298 { 0x03, 0, 0xc2f9 },
5299 { 0x06, 0, 0xafb5 },
5300 { 0x07, 0, 0x0e00 },
5301 { 0x19, 0, 0xec80 },
5302 { 0x01, 0, 0x2e65 },
5303 { 0x01, 0, 0x6e65 }
5304 };
5305 u8 cfg1;
5306
beb1fe18 5307 rtl_csi_access_enable_2(tp);
2857ffb7
FR		 5308
5309 RTL_W8(DBG_REG, FIX_NAK_1);
5310
5311 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5312
5313 RTL_W8(Config1,
5314 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5315 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5316
5317 cfg1 = RTL_R8(Config1);
5318 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5319 RTL_W8(Config1, cfg1 & ~LEDS0);
5320
fdf6fc06 5321 rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
2857ffb7
FR		 5322}
5323
beb1fe18 5324static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
2857ffb7 5325{
beb1fe18
HW		 5326 void __iomem *ioaddr = tp->mmio_addr;
5327 struct pci_dev *pdev = tp->pci_dev;
5328
5329 rtl_csi_access_enable_2(tp);
2857ffb7
FR		 5330
5331 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5332
5333 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
5334 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2857ffb7
FR		 5335}
5336
beb1fe18 5337static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
2857ffb7 5338{
beb1fe18 5339 rtl_hw_start_8102e_2(tp);
2857ffb7 5340
fdf6fc06 5341 rtl_ephy_write(tp, 0x03, 0xc2f9);
2857ffb7
FR		 5342}
5343
beb1fe18 5344static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5a5e4443 5345{
beb1fe18 5346 void __iomem *ioaddr = tp->mmio_addr;
5a5e4443
HW		 5347 static const struct ephy_info e_info_8105e_1[] = {
5348 { 0x07, 0, 0x4000 },
5349 { 0x19, 0, 0x0200 },
5350 { 0x19, 0, 0x0020 },
5351 { 0x1e, 0, 0x2000 },
5352 { 0x03, 0, 0x0001 },
5353 { 0x19, 0, 0x0100 },
5354 { 0x19, 0, 0x0004 },
5355 { 0x0a, 0, 0x0020 }
5356 };
5357
cecb5fd7 5358 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5a5e4443
HW		 5359 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5360
cecb5fd7 5361 /* Disable Early Tally Counter */
5a5e4443
HW		 5362 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
5363
5364 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4f6b00e5 5365 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
d64ec841 5366 RTL_W8(Config5, RTL_R8(Config5) | ASPM_en);
5367 RTL_W8(Config2, RTL_R8(Config2) | ClkReqEn);
5368 RTL_W32(MISC, RTL_R32(MISC) | FORCE_CLK);
5a5e4443 5369
fdf6fc06 5370 rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
5a5e4443
HW		 5371}
5372
beb1fe18 5373static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5a5e4443 5374{
beb1fe18 5375 rtl_hw_start_8105e_1(tp);
fdf6fc06 5376 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5a5e4443
HW		 5377}
5378
7e18dca1
HW		 5379static void rtl_hw_start_8402(struct rtl8169_private *tp)
5380{
5381 void __iomem *ioaddr = tp->mmio_addr;
5382 static const struct ephy_info e_info_8402[] = {
5383 { 0x19, 0xffff, 0xff64 },
5384 { 0x1e, 0, 0x4000 }
5385 };
5386
5387 rtl_csi_access_enable_2(tp);
5388
5389 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5390 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5391
5392 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5393 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
d64ec841 5394 RTL_W8(Config5, RTL_R8(Config5) | ASPM_en);
5395 RTL_W8(Config2, RTL_R8(Config2) | ClkReqEn);
5396 RTL_W32(MISC, RTL_R32(MISC) | FORCE_CLK);
7e18dca1 5397
fdf6fc06 5398 rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
7e18dca1
HW		 5399
5400 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
5401
fdf6fc06
FR		 5402 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
5403 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
5404 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5405 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5406 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5407 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5408 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
7e18dca1
HW		 5409}
5410
5598bfe5
HW		 5411static void rtl_hw_start_8106(struct rtl8169_private *tp)
5412{
5413 void __iomem *ioaddr = tp->mmio_addr;
5414
5415 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5416 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5417
d64ec841 5418 RTL_W32(MISC,
5419 (RTL_R32(MISC) | DISABLE_LAN_EN | FORCE_CLK) & ~EARLY_TALLY_EN);
5420 RTL_W8(Config5, RTL_R8(Config5) | ASPM_en);
5421 RTL_W8(Config2, RTL_R8(Config2) | ClkReqEn);
5598bfe5
HW		 5422 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
5423 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
5424}
5425
07ce4064
FR		 5426static void rtl_hw_start_8101(struct net_device *dev)
5427{
cdf1a608
FR		 5428 struct rtl8169_private *tp = netdev_priv(dev);
5429 void __iomem *ioaddr = tp->mmio_addr;
5430 struct pci_dev *pdev = tp->pci_dev;
5431
da78dbff
FR		 5432 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5433 tp->event_slow &= ~RxFIFOOver;
811fd301 5434
cecb5fd7 5435 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
7d7903b2 5436 tp->mac_version == RTL_GIGA_MAC_VER_16)
8200bc72
BH		 5437 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL,
5438 PCI_EXP_DEVCTL_NOSNOOP_EN);
cdf1a608 5439
d24e9aaf
HW		 5440 RTL_W8(Cfg9346, Cfg9346_Unlock);
5441
2857ffb7
FR		 5442 switch (tp->mac_version) {
5443 case RTL_GIGA_MAC_VER_07:
beb1fe18 5444 rtl_hw_start_8102e_1(tp);
2857ffb7
FR		 5445 break;
5446
5447 case RTL_GIGA_MAC_VER_08:
beb1fe18 5448 rtl_hw_start_8102e_3(tp);
2857ffb7
FR		 5449 break;
5450
5451 case RTL_GIGA_MAC_VER_09:
beb1fe18 5452 rtl_hw_start_8102e_2(tp);
2857ffb7 5453 break;
5a5e4443
HW		 5454
5455 case RTL_GIGA_MAC_VER_29:
beb1fe18 5456 rtl_hw_start_8105e_1(tp);
5a5e4443
HW		 5457 break;
5458 case RTL_GIGA_MAC_VER_30:
beb1fe18 5459 rtl_hw_start_8105e_2(tp);
5a5e4443 5460 break;
7e18dca1
HW		 5461
5462 case RTL_GIGA_MAC_VER_37:
5463 rtl_hw_start_8402(tp);
5464 break;
5598bfe5
HW		 5465
5466 case RTL_GIGA_MAC_VER_39:
5467 rtl_hw_start_8106(tp);
5468 break;
cdf1a608
FR		 5469 }
5470
d24e9aaf 5471 RTL_W8(Cfg9346, Cfg9346_Lock);
cdf1a608 5472
f0298f81 5473 RTL_W8(MaxTxPacketSize, TxPacketMax);
cdf1a608 5474
6f0333b8 5475 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
cdf1a608 5476
d24e9aaf 5477 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
cdf1a608
FR		 5478 RTL_W16(CPlusCmd, tp->cp_cmd);
5479
5480 RTL_W16(IntrMitigate, 0x0000);
5481
5482 rtl_set_rx_tx_desc_registers(tp, ioaddr);
5483
5484 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5485 rtl_set_rx_tx_config_registers(tp);
5486
cdf1a608
FR		 5487 RTL_R8(IntrMask);
5488
cdf1a608
FR		 5489 rtl_set_rx_mode(dev);
5490
5491 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
1da177e4
LT		 5492}
5493
5494static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5495{
d58d46b5
FR		 5496 struct rtl8169_private *tp = netdev_priv(dev);
5497
5498 if (new_mtu < ETH_ZLEN ||
5499 new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
1da177e4
LT		 5500 return -EINVAL;
5501
d58d46b5
FR		 5502 if (new_mtu > ETH_DATA_LEN)
5503 rtl_hw_jumbo_enable(tp);
5504 else
5505 rtl_hw_jumbo_disable(tp);
5506
1da177e4 5507 dev->mtu = new_mtu;
350fb32a
MM		 5508 netdev_update_features(dev);
5509
323bb685 5510 return 0;
1da177e4
LT		 5511}
5512
5513static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5514{
95e0918d 5515 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 5516 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5517}
5518
6f0333b8
ED		 5519static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5520 void **data_buff, struct RxDesc *desc)
1da177e4 5521{
48addcc9 5522 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
231aee63 5523 DMA_FROM_DEVICE);
48addcc9 5524
6f0333b8
ED		 5525 kfree(*data_buff);
5526 *data_buff = NULL;
1da177e4
LT		 5527 rtl8169_make_unusable_by_asic(desc);
5528}
5529
5530static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
5531{
5532 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5533
5534 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
5535}
5536
5537static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
5538 u32 rx_buf_sz)
5539{
5540 desc->addr = cpu_to_le64(mapping);
5541 wmb();
5542 rtl8169_mark_to_asic(desc, rx_buf_sz);
5543}
5544
6f0333b8
ED		 5545static inline void *rtl8169_align(void *data)
5546{
5547 return (void *)ALIGN((long)data, 16);
5548}
5549
0ecbe1ca
SG		 5550static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5551 struct RxDesc *desc)
1da177e4 5552{
6f0333b8 5553 void *data;
1da177e4 5554 dma_addr_t mapping;
48addcc9 5555 struct device *d = &tp->pci_dev->dev;
0ecbe1ca 5556 struct net_device *dev = tp->dev;
6f0333b8 5557 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
1da177e4 5558
6f0333b8
ED		 5559 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
5560 if (!data)
5561 return NULL;
e9f63f30 5562
6f0333b8
ED		 5563 if (rtl8169_align(data) != data) {
5564 kfree(data);
5565 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
5566 if (!data)
5567 return NULL;
5568 }
3eafe507 5569
48addcc9 5570 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
231aee63 5571 DMA_FROM_DEVICE);
d827d86b
SG		 5572 if (unlikely(dma_mapping_error(d, mapping))) {
5573 if (net_ratelimit())
5574 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
3eafe507 5575 goto err_out;
d827d86b 5576 }
1da177e4
LT		 5577
5578 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6f0333b8 5579 return data;
3eafe507
SG		 5580
5581err_out:
5582 kfree(data);
5583 return NULL;
1da177e4
LT		 5584}
5585
5586static void rtl8169_rx_clear(struct rtl8169_private *tp)
5587{
07d3f51f 5588 unsigned int i;
1da177e4
LT		 5589
5590 for (i = 0; i < NUM_RX_DESC; i++) {
6f0333b8
ED		 5591 if (tp->Rx_databuff[i]) {
5592 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
1da177e4
LT		 5593 tp->RxDescArray + i);
5594 }
5595 }
5596}
5597
0ecbe1ca 5598static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1da177e4 5599{
0ecbe1ca
SG		 5600 desc->opts1 |= cpu_to_le32(RingEnd);
5601}
5b0384f4 5602
0ecbe1ca
SG		 5603static int rtl8169_rx_fill(struct rtl8169_private *tp)
5604{
5605 unsigned int i;
1da177e4 5606
0ecbe1ca
SG		 5607 for (i = 0; i < NUM_RX_DESC; i++) {
5608 void *data;
4ae47c2d 5609
6f0333b8 5610 if (tp->Rx_databuff[i])
1da177e4 5611 continue;
bcf0bf90 5612
0ecbe1ca 5613 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6f0333b8
ED		 5614 if (!data) {
5615 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
0ecbe1ca 5616 goto err_out;
6f0333b8
ED		 5617 }
5618 tp->Rx_databuff[i] = data;
1da177e4 5619 }
1da177e4 5620
0ecbe1ca
SG		 5621 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5622 return 0;
5623
5624err_out:
5625 rtl8169_rx_clear(tp);
5626 return -ENOMEM;
1da177e4
LT		 5627}
5628
1da177e4
LT		 5629static int rtl8169_init_ring(struct net_device *dev)
5630{
5631 struct rtl8169_private *tp = netdev_priv(dev);
5632
5633 rtl8169_init_ring_indexes(tp);
5634
5635 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
6f0333b8 5636 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
1da177e4 5637
0ecbe1ca 5638 return rtl8169_rx_fill(tp);
1da177e4
LT		 5639}
5640
48addcc9 5641static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
1da177e4
LT		 5642 struct TxDesc *desc)
5643{
5644 unsigned int len = tx_skb->len;
5645
48addcc9
SG		 5646 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5647
1da177e4
LT		 5648 desc->opts1 = 0x00;
5649 desc->opts2 = 0x00;
5650 desc->addr = 0x00;
5651 tx_skb->len = 0;
5652}
5653
3eafe507
SG		 5654static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5655 unsigned int n)
1da177e4
LT		 5656{
5657 unsigned int i;
5658
3eafe507
SG		 5659 for (i = 0; i < n; i++) {
5660 unsigned int entry = (start + i) % NUM_TX_DESC;
1da177e4
LT		 5661 struct ring_info *tx_skb = tp->tx_skb + entry;
5662 unsigned int len = tx_skb->len;
5663
5664 if (len) {
5665 struct sk_buff *skb = tx_skb->skb;
5666
48addcc9 5667 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
1da177e4
LT		 5668 tp->TxDescArray + entry);
5669 if (skb) {
cac4b22f 5670 tp->dev->stats.tx_dropped++;
1da177e4
LT		 5671 dev_kfree_skb(skb);
5672 tx_skb->skb = NULL;
5673 }
1da177e4
LT		 5674 }
5675 }
3eafe507
SG		 5676}
5677
5678static void rtl8169_tx_clear(struct rtl8169_private *tp)
5679{
5680 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
1da177e4
LT		 5681 tp->cur_tx = tp->dirty_tx = 0;
5682}
5683
4422bcd4 5684static void rtl_reset_work(struct rtl8169_private *tp)
1da177e4 5685{
c4028958 5686 struct net_device *dev = tp->dev;
56de414c 5687 int i;
1da177e4 5688
da78dbff
FR		 5689 napi_disable(&tp->napi);
5690 netif_stop_queue(dev);
5691 synchronize_sched();
1da177e4 5692
c7c2c39b 5693 rtl8169_hw_reset(tp);
5694
56de414c
FR		 5695 for (i = 0; i < NUM_RX_DESC; i++)
5696 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
5697
1da177e4 5698 rtl8169_tx_clear(tp);
c7c2c39b 5699 rtl8169_init_ring_indexes(tp);
1da177e4 5700
da78dbff 5701 napi_enable(&tp->napi);
56de414c
FR		 5702 rtl_hw_start(dev);
5703 netif_wake_queue(dev);
5704 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1da177e4
LT		 5705}
5706
5707static void rtl8169_tx_timeout(struct net_device *dev)
5708{
da78dbff
FR		 5709 struct rtl8169_private *tp = netdev_priv(dev);
5710
5711 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 5712}
5713
5714static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2b7b4318 5715 u32 *opts)
1da177e4
LT		 5716{
5717 struct skb_shared_info *info = skb_shinfo(skb);
5718 unsigned int cur_frag, entry;
a6343afb 5719 struct TxDesc * uninitialized_var(txd);
48addcc9 5720 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 5721
5722 entry = tp->cur_tx;
5723 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
9e903e08 5724 const skb_frag_t *frag = info->frags + cur_frag;
1da177e4
LT		 5725 dma_addr_t mapping;
5726 u32 status, len;
5727 void *addr;
5728
5729 entry = (entry + 1) % NUM_TX_DESC;
5730
5731 txd = tp->TxDescArray + entry;
9e903e08 5732 len = skb_frag_size(frag);
929f6189 5733 addr = skb_frag_address(frag);
48addcc9 5734 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
d827d86b
SG		 5735 if (unlikely(dma_mapping_error(d, mapping))) {
5736 if (net_ratelimit())
5737 netif_err(tp, drv, tp->dev,
5738 "Failed to map TX fragments DMA!\n");
3eafe507 5739 goto err_out;
d827d86b 5740 }
1da177e4 5741
cecb5fd7 5742 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318
FR		 5743 status = opts[0] | len |
5744 (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 5745
5746 txd->opts1 = cpu_to_le32(status);
2b7b4318 5747 txd->opts2 = cpu_to_le32(opts[1]);
1da177e4
LT		 5748 txd->addr = cpu_to_le64(mapping);
5749
5750 tp->tx_skb[entry].len = len;
5751 }
5752
5753 if (cur_frag) {
5754 tp->tx_skb[entry].skb = skb;
5755 txd->opts1 |= cpu_to_le32(LastFrag);
5756 }
5757
5758 return cur_frag;
3eafe507
SG		 5759
5760err_out:
5761 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5762 return -EIO;
1da177e4
LT		 5763}
5764
2b7b4318
FR		 5765static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
5766 struct sk_buff *skb, u32 *opts)
1da177e4 5767{
2b7b4318 5768 const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
350fb32a 5769 u32 mss = skb_shinfo(skb)->gso_size;
2b7b4318 5770 int offset = info->opts_offset;
350fb32a 5771
2b7b4318
FR		 5772 if (mss) {
5773 opts[0] |= TD_LSO;
5774 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
5775 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 5776 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 5777
5778 if (ip->protocol == IPPROTO_TCP)
2b7b4318 5779 opts[offset] |= info->checksum.tcp;
1da177e4 5780 else if (ip->protocol == IPPROTO_UDP)
2b7b4318
FR		 5781 opts[offset] |= info->checksum.udp;
5782 else
5783 WARN_ON_ONCE(1);
1da177e4 5784 }
1da177e4
LT		 5785}
5786
61357325
SH		 5787static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5788 struct net_device *dev)
1da177e4
LT		 5789{
5790 struct rtl8169_private *tp = netdev_priv(dev);
3eafe507 5791 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
1da177e4
LT		 5792 struct TxDesc *txd = tp->TxDescArray + entry;
5793 void __iomem *ioaddr = tp->mmio_addr;
48addcc9 5794 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 5795 dma_addr_t mapping;
5796 u32 status, len;
2b7b4318 5797 u32 opts[2];
3eafe507 5798 int frags;
5b0384f4 5799
477206a0 5800 if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
bf82c189 5801 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
3eafe507 5802 goto err_stop_0;
1da177e4
LT		 5803 }
5804
5805 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3eafe507
SG		 5806 goto err_stop_0;
5807
5808 len = skb_headlen(skb);
48addcc9 5809 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
d827d86b
SG		 5810 if (unlikely(dma_mapping_error(d, mapping))) {
5811 if (net_ratelimit())
5812 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
3eafe507 5813 goto err_dma_0;
d827d86b 5814 }
3eafe507
SG		 5815
5816 tp->tx_skb[entry].len = len;
5817 txd->addr = cpu_to_le64(mapping);
1da177e4 5818
2b7b4318
FR		 5819 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
5820 opts[0] = DescOwn;
1da177e4 5821
2b7b4318
FR		 5822 rtl8169_tso_csum(tp, skb, opts);
5823
5824 frags = rtl8169_xmit_frags(tp, skb, opts);
3eafe507
SG		 5825 if (frags < 0)
5826 goto err_dma_1;
5827 else if (frags)
2b7b4318 5828 opts[0] |= FirstFrag;
3eafe507 5829 else {
2b7b4318 5830 opts[0] |= FirstFrag | LastFrag;
1da177e4
LT		 5831 tp->tx_skb[entry].skb = skb;
5832 }
5833
2b7b4318
FR		 5834 txd->opts2 = cpu_to_le32(opts[1]);
5835
5047fb5d
RC		 5836 skb_tx_timestamp(skb);
5837
1da177e4
LT		 5838 wmb();
5839
cecb5fd7 5840 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318 5841 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 5842 txd->opts1 = cpu_to_le32(status);
5843
1da177e4
LT		 5844 tp->cur_tx += frags + 1;
5845
4c020a96 5846 wmb();
1da177e4 5847
cecb5fd7 5848 RTL_W8(TxPoll, NPQ);
1da177e4 5849
da78dbff
FR		 5850 mmiowb();
5851
477206a0 5852 if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
ae1f23fb
FR		 5853 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
5854 * not miss a ring update when it notices a stopped queue.
5855 */
5856 smp_wmb();
1da177e4 5857 netif_stop_queue(dev);
ae1f23fb
FR		 5858 /* Sync with rtl_tx:
5859 * - publish queue status and cur_tx ring index (write barrier)
5860 * - refresh dirty_tx ring index (read barrier).
5861 * May the current thread have a pessimistic view of the ring
5862 * status and forget to wake up queue, a racing rtl_tx thread
5863 * can't.
5864 */
1e874e04 5865 smp_mb();
477206a0 5866 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
1da177e4
LT		 5867 netif_wake_queue(dev);
5868 }
5869
61357325 5870 return NETDEV_TX_OK;
1da177e4 5871
3eafe507 5872err_dma_1:
48addcc9 5873 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
3eafe507
SG		 5874err_dma_0:
5875 dev_kfree_skb(skb);
5876 dev->stats.tx_dropped++;
5877 return NETDEV_TX_OK;
5878
5879err_stop_0:
1da177e4 5880 netif_stop_queue(dev);
cebf8cc7 5881 dev->stats.tx_dropped++;
61357325 5882 return NETDEV_TX_BUSY;
1da177e4
LT		 5883}
5884
5885static void rtl8169_pcierr_interrupt(struct net_device *dev)
5886{
5887 struct rtl8169_private *tp = netdev_priv(dev);
5888 struct pci_dev *pdev = tp->pci_dev;
1da177e4
LT		 5889 u16 pci_status, pci_cmd;
5890
5891 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5892 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5893
bf82c189
JP		 5894 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5895 pci_cmd, pci_status);
1da177e4
LT		 5896
5897 /*
5898 * The recovery sequence below admits a very elaborated explanation:
5899 * - it seems to work;
d03902b8
FR		 5900 * - I did not see what else could be done;
5901 * - it makes iop3xx happy.
1da177e4
LT		 5902 *
5903 * Feel free to adjust to your needs.
5904 */
a27993f3 5905 if (pdev->broken_parity_status)
d03902b8
FR		 5906 pci_cmd &= ~PCI_COMMAND_PARITY;
5907 else
5908 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5909
5910 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 5911
5912 pci_write_config_word(pdev, PCI_STATUS,
5913 pci_status & (PCI_STATUS_DETECTED_PARITY |
5914 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5915 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5916
5917 /* The infamous DAC f*ckup only happens at boot time */
5918 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
e6de30d6 5919 void __iomem *ioaddr = tp->mmio_addr;
5920
bf82c189 5921 netif_info(tp, intr, dev, "disabling PCI DAC\n");
1da177e4
LT		 5922 tp->cp_cmd &= ~PCIDAC;
5923 RTL_W16(CPlusCmd, tp->cp_cmd);
5924 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 5925 }
5926
e6de30d6 5927 rtl8169_hw_reset(tp);
d03902b8 5928
98ddf986 5929 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 5930}
5931
da78dbff 5932static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
1da177e4
LT		 5933{
5934 unsigned int dirty_tx, tx_left;
5935
1da177e4
LT		 5936 dirty_tx = tp->dirty_tx;
5937 smp_rmb();
5938 tx_left = tp->cur_tx - dirty_tx;
5939
5940 while (tx_left > 0) {
5941 unsigned int entry = dirty_tx % NUM_TX_DESC;
5942 struct ring_info *tx_skb = tp->tx_skb + entry;
1da177e4
LT		 5943 u32 status;
5944
5945 rmb();
5946 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5947 if (status & DescOwn)
5948 break;
5949
48addcc9
SG		 5950 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5951 tp->TxDescArray + entry);
1da177e4 5952 if (status & LastFrag) {
17bcb684
FR		 5953 u64_stats_update_begin(&tp->tx_stats.syncp);
5954 tp->tx_stats.packets++;
5955 tp->tx_stats.bytes += tx_skb->skb->len;
5956 u64_stats_update_end(&tp->tx_stats.syncp);
5957 dev_kfree_skb(tx_skb->skb);
1da177e4
LT		 5958 tx_skb->skb = NULL;
5959 }
5960 dirty_tx++;
5961 tx_left--;
5962 }
5963
5964 if (tp->dirty_tx != dirty_tx) {
5965 tp->dirty_tx = dirty_tx;
ae1f23fb
FR		 5966 /* Sync with rtl8169_start_xmit:
5967 * - publish dirty_tx ring index (write barrier)
5968 * - refresh cur_tx ring index and queue status (read barrier)
5969 * May the current thread miss the stopped queue condition,
5970 * a racing xmit thread can only have a right view of the
5971 * ring status.
5972 */
1e874e04 5973 smp_mb();
1da177e4 5974 if (netif_queue_stopped(dev) &&
477206a0 5975 TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
1da177e4
LT		 5976 netif_wake_queue(dev);
5977 }
d78ae2dc
FR		 5978 /*
5979 * 8168 hack: TxPoll requests are lost when the Tx packets are
5980 * too close. Let's kick an extra TxPoll request when a burst
5981 * of start_xmit activity is detected (if it is not detected,
5982 * it is slow enough). -- FR
5983 */
da78dbff
FR		 5984 if (tp->cur_tx != dirty_tx) {
5985 void __iomem *ioaddr = tp->mmio_addr;
5986
d78ae2dc 5987 RTL_W8(TxPoll, NPQ);
da78dbff 5988 }
1da177e4
LT		 5989 }
5990}
5991
126fa4b9
FR		 5992static inline int rtl8169_fragmented_frame(u32 status)
5993{
5994 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
5995}
5996
adea1ac7 5997static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
1da177e4 5998{
1da177e4
LT		 5999 u32 status = opts1 & RxProtoMask;
6000
6001 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
d5d3ebe3 6002 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
1da177e4
LT		 6003 skb->ip_summed = CHECKSUM_UNNECESSARY;
6004 else
bc8acf2c 6005 skb_checksum_none_assert(skb);
1da177e4
LT		 6006}
6007
6f0333b8
ED		 6008static struct sk_buff *rtl8169_try_rx_copy(void *data,
6009 struct rtl8169_private *tp,
6010 int pkt_size,
6011 dma_addr_t addr)
1da177e4 6012{
b449655f 6013 struct sk_buff *skb;
48addcc9 6014 struct device *d = &tp->pci_dev->dev;
b449655f 6015
6f0333b8 6016 data = rtl8169_align(data);
48addcc9 6017 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6f0333b8
ED		 6018 prefetch(data);
6019 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
6020 if (skb)
6021 memcpy(skb->data, data, pkt_size);
48addcc9
SG		 6022 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
6023
6f0333b8 6024 return skb;
1da177e4
LT		 6025}
6026
da78dbff 6027static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
1da177e4
LT		 6028{
6029 unsigned int cur_rx, rx_left;
6f0333b8 6030 unsigned int count;
1da177e4 6031
1da177e4
LT		 6032 cur_rx = tp->cur_rx;
6033 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
865c652d 6034 rx_left = min(rx_left, budget);
1da177e4 6035
4dcb7d33 6036 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 6037 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 6038 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 6039 u32 status;
6040
6041 rmb();
e03f33af 6042 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
1da177e4
LT		 6043
6044 if (status & DescOwn)
6045 break;
4dcb7d33 6046 if (unlikely(status & RxRES)) {
bf82c189
JP		 6047 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6048 status);
cebf8cc7 6049 dev->stats.rx_errors++;
1da177e4 6050 if (status & (RxRWT | RxRUNT))
cebf8cc7 6051 dev->stats.rx_length_errors++;
1da177e4 6052 if (status & RxCRC)
cebf8cc7 6053 dev->stats.rx_crc_errors++;
9dccf611 6054 if (status & RxFOVF) {
da78dbff 6055 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
cebf8cc7 6056 dev->stats.rx_fifo_errors++;
9dccf611 6057 }
6bbe021d
BG		 6058 if ((status & (RxRUNT | RxCRC)) &&
6059 !(status & (RxRWT | RxFOVF)) &&
6060 (dev->features & NETIF_F_RXALL))
6061 goto process_pkt;
6062
6f0333b8 6063 rtl8169_mark_to_asic(desc, rx_buf_sz);
1da177e4 6064 } else {
6f0333b8 6065 struct sk_buff *skb;
6bbe021d
BG		 6066 dma_addr_t addr;
6067 int pkt_size;
6068
6069process_pkt:
6070 addr = le64_to_cpu(desc->addr);
79d0c1d2
BG		 6071 if (likely(!(dev->features & NETIF_F_RXFCS)))
6072 pkt_size = (status & 0x00003fff) - 4;
6073 else
6074 pkt_size = status & 0x00003fff;
1da177e4 6075
126fa4b9
FR		 6076 /*
6077 * The driver does not support incoming fragmented
6078 * frames. They are seen as a symptom of over-mtu
6079 * sized frames.
6080 */
6081 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 6082 dev->stats.rx_dropped++;
6083 dev->stats.rx_length_errors++;
6f0333b8 6084 rtl8169_mark_to_asic(desc, rx_buf_sz);
4dcb7d33 6085 continue;
126fa4b9
FR		 6086 }
6087
6f0333b8
ED		 6088 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6089 tp, pkt_size, addr);
6090 rtl8169_mark_to_asic(desc, rx_buf_sz);
6091 if (!skb) {
6092 dev->stats.rx_dropped++;
6093 continue;
1da177e4
LT		 6094 }
6095
adea1ac7 6096 rtl8169_rx_csum(skb, status);
1da177e4
LT		 6097 skb_put(skb, pkt_size);
6098 skb->protocol = eth_type_trans(skb, dev);
6099
7a8fc77b
FR		 6100 rtl8169_rx_vlan_tag(desc, skb);
6101
56de414c 6102 napi_gro_receive(&tp->napi, skb);
1da177e4 6103
8027aa24
JW		 6104 u64_stats_update_begin(&tp->rx_stats.syncp);
6105 tp->rx_stats.packets++;
6106 tp->rx_stats.bytes += pkt_size;
6107 u64_stats_update_end(&tp->rx_stats.syncp);
1da177e4 6108 }
6dccd16b
FR		 6109
6110 /* Work around for AMD plateform. */
95e0918d 6111 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
6dccd16b
FR		 6112 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
6113 desc->opts2 = 0;
6114 cur_rx++;
6115 }
1da177e4
LT		 6116 }
6117
6118 count = cur_rx - tp->cur_rx;
6119 tp->cur_rx = cur_rx;
6120
6f0333b8 6121 tp->dirty_rx += count;
1da177e4
LT		 6122
6123 return count;
6124}
6125
07d3f51f 6126static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 6127{
07d3f51f 6128 struct net_device *dev = dev_instance;
1da177e4 6129 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 6130 int handled = 0;
9085cdfa 6131 u16 status;
1da177e4 6132
9085cdfa 6133 status = rtl_get_events(tp);
da78dbff
FR		 6134 if (status && status != 0xffff) {
6135 status &= RTL_EVENT_NAPI | tp->event_slow;
6136 if (status) {
6137 handled = 1;
1da177e4 6138
da78dbff
FR		 6139 rtl_irq_disable(tp);
6140 napi_schedule(&tp->napi);
f11a377b 6141 }
da78dbff
FR		 6142 }
6143 return IRQ_RETVAL(handled);
6144}
1da177e4 6145
da78dbff
FR		 6146/*
6147 * Workqueue context.
6148 */
6149static void rtl_slow_event_work(struct rtl8169_private *tp)
6150{
6151 struct net_device *dev = tp->dev;
6152 u16 status;
6153
6154 status = rtl_get_events(tp) & tp->event_slow;
6155 rtl_ack_events(tp, status);
1da177e4 6156
da78dbff
FR		 6157 if (unlikely(status & RxFIFOOver)) {
6158 switch (tp->mac_version) {
6159 /* Work around for rx fifo overflow */
6160 case RTL_GIGA_MAC_VER_11:
6161 netif_stop_queue(dev);
934714d0
FR		 6162 /* XXX - Hack alert. See rtl_task(). */
6163 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
da78dbff 6164 default:
f11a377b
DD		 6165 break;
6166 }
da78dbff 6167 }
1da177e4 6168
da78dbff
FR		 6169 if (unlikely(status & SYSErr))
6170 rtl8169_pcierr_interrupt(dev);
0e485150 6171
da78dbff
FR		 6172 if (status & LinkChg)
6173 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
1da177e4 6174
7dbb4918 6175 rtl_irq_enable_all(tp);
1da177e4
LT		 6176}
6177
4422bcd4
FR		 6178static void rtl_task(struct work_struct *work)
6179{
da78dbff
FR		 6180 static const struct {
6181 int bitnr;
6182 void (*action)(struct rtl8169_private *);
6183 } rtl_work[] = {
934714d0 6184 /* XXX - keep rtl_slow_event_work() as first element. */
da78dbff
FR		 6185 { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work },
6186 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
6187 { RTL_FLAG_TASK_PHY_PENDING, rtl_phy_work }
6188 };
4422bcd4
FR		 6189 struct rtl8169_private *tp =
6190 container_of(work, struct rtl8169_private, wk.work);
da78dbff
FR		 6191 struct net_device *dev = tp->dev;
6192 int i;
6193
6194 rtl_lock_work(tp);
6195
6c4a70c5
FR		 6196 if (!netif_running(dev) ||
6197 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
da78dbff
FR		 6198 goto out_unlock;
6199
6200 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6201 bool pending;
6202
da78dbff 6203 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
da78dbff
FR		 6204 if (pending)
6205 rtl_work[i].action(tp);
6206 }
4422bcd4 6207
da78dbff
FR		 6208out_unlock:
6209 rtl_unlock_work(tp);
4422bcd4
FR		 6210}
6211
bea3348e 6212static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 6213{
bea3348e
SH		 6214 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6215 struct net_device *dev = tp->dev;
da78dbff
FR		 6216 u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
6217 int work_done= 0;
6218 u16 status;
6219
6220 status = rtl_get_events(tp);
6221 rtl_ack_events(tp, status & ~tp->event_slow);
6222
6223 if (status & RTL_EVENT_NAPI_RX)
6224 work_done = rtl_rx(dev, tp, (u32) budget);
6225
6226 if (status & RTL_EVENT_NAPI_TX)
6227 rtl_tx(dev, tp);
1da177e4 6228
da78dbff
FR		 6229 if (status & tp->event_slow) {
6230 enable_mask &= ~tp->event_slow;
6231
6232 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
6233 }
1da177e4 6234
bea3348e 6235 if (work_done < budget) {
288379f0 6236 napi_complete(napi);
f11a377b 6237
da78dbff
FR		 6238 rtl_irq_enable(tp, enable_mask);
6239 mmiowb();
1da177e4
LT		 6240 }
6241
bea3348e 6242 return work_done;
1da177e4 6243}
1da177e4 6244
523a6094
FR		 6245static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
6246{
6247 struct rtl8169_private *tp = netdev_priv(dev);
6248
6249 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6250 return;
6251
6252 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
6253 RTL_W32(RxMissed, 0);
6254}
6255
1da177e4
LT		 6256static void rtl8169_down(struct net_device *dev)
6257{
6258 struct rtl8169_private *tp = netdev_priv(dev);
6259 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 6260
4876cc1e 6261 del_timer_sync(&tp->timer);
1da177e4 6262
93dd79e8 6263 napi_disable(&tp->napi);
da78dbff 6264 netif_stop_queue(dev);
1da177e4 6265
92fc43b4 6266 rtl8169_hw_reset(tp);
323bb685
SG		 6267 /*
6268 * At this point device interrupts can not be enabled in any function,
209e5ac8
FR		 6269 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6270 * and napi is disabled (rtl8169_poll).
323bb685 6271 */
523a6094 6272 rtl8169_rx_missed(dev, ioaddr);
1da177e4 6273
1da177e4 6274 /* Give a racing hard_start_xmit a few cycles to complete. */
da78dbff 6275 synchronize_sched();
1da177e4 6276
1da177e4
LT		 6277 rtl8169_tx_clear(tp);
6278
6279 rtl8169_rx_clear(tp);
065c27c1 6280
6281 rtl_pll_power_down(tp);
1da177e4
LT		 6282}
6283
6284static int rtl8169_close(struct net_device *dev)
6285{
6286 struct rtl8169_private *tp = netdev_priv(dev);
6287 struct pci_dev *pdev = tp->pci_dev;
6288
e1759441
RW		 6289 pm_runtime_get_sync(&pdev->dev);
6290
cecb5fd7 6291 /* Update counters before going down */
355423d0
IV		 6292 rtl8169_update_counters(dev);
6293
da78dbff 6294 rtl_lock_work(tp);
6c4a70c5 6295 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
da78dbff 6296
1da177e4 6297 rtl8169_down(dev);
da78dbff 6298 rtl_unlock_work(tp);
1da177e4 6299
92a7c4e7 6300 free_irq(pdev->irq, dev);
1da177e4 6301
82553bb6
SG		 6302 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6303 tp->RxPhyAddr);
6304 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6305 tp->TxPhyAddr);
1da177e4
LT		 6306 tp->TxDescArray = NULL;
6307 tp->RxDescArray = NULL;
6308
e1759441
RW		 6309 pm_runtime_put_sync(&pdev->dev);
6310
1da177e4
LT		 6311 return 0;
6312}
6313
dc1c00ce
FR		 6314#ifdef CONFIG_NET_POLL_CONTROLLER
6315static void rtl8169_netpoll(struct net_device *dev)
6316{
6317 struct rtl8169_private *tp = netdev_priv(dev);
6318
6319 rtl8169_interrupt(tp->pci_dev->irq, dev);
6320}
6321#endif
6322
df43ac78
FR		 6323static int rtl_open(struct net_device *dev)
6324{
6325 struct rtl8169_private *tp = netdev_priv(dev);
6326 void __iomem *ioaddr = tp->mmio_addr;
6327 struct pci_dev *pdev = tp->pci_dev;
6328 int retval = -ENOMEM;
6329
6330 pm_runtime_get_sync(&pdev->dev);
6331
6332 /*
e75d6606 6333 * Rx and Tx descriptors needs 256 bytes alignment.
df43ac78
FR		 6334 * dma_alloc_coherent provides more.
6335 */
6336 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6337 &tp->TxPhyAddr, GFP_KERNEL);
6338 if (!tp->TxDescArray)
6339 goto err_pm_runtime_put;
6340
6341 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6342 &tp->RxPhyAddr, GFP_KERNEL);
6343 if (!tp->RxDescArray)
6344 goto err_free_tx_0;
6345
6346 retval = rtl8169_init_ring(dev);
6347 if (retval < 0)
6348 goto err_free_rx_1;
6349
6350 INIT_WORK(&tp->wk.work, rtl_task);
6351
6352 smp_mb();
6353
6354 rtl_request_firmware(tp);
6355
92a7c4e7 6356 retval = request_irq(pdev->irq, rtl8169_interrupt,
df43ac78
FR		 6357 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
6358 dev->name, dev);
6359 if (retval < 0)
6360 goto err_release_fw_2;
6361
6362 rtl_lock_work(tp);
6363
6364 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6365
6366 napi_enable(&tp->napi);
6367
6368 rtl8169_init_phy(dev, tp);
6369
6370 __rtl8169_set_features(dev, dev->features);
6371
6372 rtl_pll_power_up(tp);
6373
6374 rtl_hw_start(dev);
6375
6376 netif_start_queue(dev);
6377
6378 rtl_unlock_work(tp);
6379
6380 tp->saved_wolopts = 0;
6381 pm_runtime_put_noidle(&pdev->dev);
6382
6383 rtl8169_check_link_status(dev, tp, ioaddr);
6384out:
6385 return retval;
6386
6387err_release_fw_2:
6388 rtl_release_firmware(tp);
6389 rtl8169_rx_clear(tp);
6390err_free_rx_1:
6391 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6392 tp->RxPhyAddr);
6393 tp->RxDescArray = NULL;
6394err_free_tx_0:
6395 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6396 tp->TxPhyAddr);
6397 tp->TxDescArray = NULL;
6398err_pm_runtime_put:
6399 pm_runtime_put_noidle(&pdev->dev);
6400 goto out;
6401}
6402
8027aa24
JW		 6403static struct rtnl_link_stats64 *
6404rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
1da177e4
LT		 6405{
6406 struct rtl8169_private *tp = netdev_priv(dev);
6407 void __iomem *ioaddr = tp->mmio_addr;
8027aa24 6408 unsigned int start;
1da177e4 6409
da78dbff 6410 if (netif_running(dev))
523a6094 6411 rtl8169_rx_missed(dev, ioaddr);
5b0384f4 6412
8027aa24
JW		 6413 do {
6414 start = u64_stats_fetch_begin_bh(&tp->rx_stats.syncp);
6415 stats->rx_packets = tp->rx_stats.packets;
6416 stats->rx_bytes = tp->rx_stats.bytes;
6417 } while (u64_stats_fetch_retry_bh(&tp->rx_stats.syncp, start));
6418
6419
6420 do {
6421 start = u64_stats_fetch_begin_bh(&tp->tx_stats.syncp);
6422 stats->tx_packets = tp->tx_stats.packets;
6423 stats->tx_bytes = tp->tx_stats.bytes;
6424 } while (u64_stats_fetch_retry_bh(&tp->tx_stats.syncp, start));
6425
6426 stats->rx_dropped = dev->stats.rx_dropped;
6427 stats->tx_dropped = dev->stats.tx_dropped;
6428 stats->rx_length_errors = dev->stats.rx_length_errors;
6429 stats->rx_errors = dev->stats.rx_errors;
6430 stats->rx_crc_errors = dev->stats.rx_crc_errors;
6431 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
6432 stats->rx_missed_errors = dev->stats.rx_missed_errors;
6433
6434 return stats;
1da177e4
LT		 6435}
6436
861ab440 6437static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 6438{
065c27c1 6439 struct rtl8169_private *tp = netdev_priv(dev);
6440
5d06a99f 6441 if (!netif_running(dev))
861ab440 6442 return;
5d06a99f
FR		 6443
6444 netif_device_detach(dev);
6445 netif_stop_queue(dev);
da78dbff
FR		 6446
6447 rtl_lock_work(tp);
6448 napi_disable(&tp->napi);
6c4a70c5 6449 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
da78dbff
FR		 6450 rtl_unlock_work(tp);
6451
6452 rtl_pll_power_down(tp);
861ab440
RW		 6453}
6454
6455#ifdef CONFIG_PM
6456
6457static int rtl8169_suspend(struct device *device)
6458{
6459 struct pci_dev *pdev = to_pci_dev(device);
6460 struct net_device *dev = pci_get_drvdata(pdev);
5d06a99f 6461
861ab440 6462 rtl8169_net_suspend(dev);
1371fa6d 6463
5d06a99f
FR		 6464 return 0;
6465}
6466
e1759441
RW		 6467static void __rtl8169_resume(struct net_device *dev)
6468{
065c27c1 6469 struct rtl8169_private *tp = netdev_priv(dev);
6470
e1759441 6471 netif_device_attach(dev);
065c27c1 6472
6473 rtl_pll_power_up(tp);
6474
cff4c162
AS		 6475 rtl_lock_work(tp);
6476 napi_enable(&tp->napi);
6c4a70c5 6477 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
cff4c162 6478 rtl_unlock_work(tp);
da78dbff 6479
98ddf986 6480 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
e1759441
RW		 6481}
6482
861ab440 6483static int rtl8169_resume(struct device *device)
5d06a99f 6484{
861ab440 6485 struct pci_dev *pdev = to_pci_dev(device);
5d06a99f 6486 struct net_device *dev = pci_get_drvdata(pdev);
fccec10b
SG		 6487 struct rtl8169_private *tp = netdev_priv(dev);
6488
6489 rtl8169_init_phy(dev, tp);
5d06a99f 6490
e1759441
RW		 6491 if (netif_running(dev))
6492 __rtl8169_resume(dev);
5d06a99f 6493
e1759441
RW		 6494 return 0;
6495}
6496
6497static int rtl8169_runtime_suspend(struct device *device)
6498{
6499 struct pci_dev *pdev = to_pci_dev(device);
6500 struct net_device *dev = pci_get_drvdata(pdev);
6501 struct rtl8169_private *tp = netdev_priv(dev);
6502
6503 if (!tp->TxDescArray)
6504 return 0;
6505
da78dbff 6506 rtl_lock_work(tp);
e1759441
RW		 6507 tp->saved_wolopts = __rtl8169_get_wol(tp);
6508 __rtl8169_set_wol(tp, WAKE_ANY);
da78dbff 6509 rtl_unlock_work(tp);
e1759441
RW		 6510
6511 rtl8169_net_suspend(dev);
6512
6513 return 0;
6514}
6515
6516static int rtl8169_runtime_resume(struct device *device)
6517{
6518 struct pci_dev *pdev = to_pci_dev(device);
6519 struct net_device *dev = pci_get_drvdata(pdev);
6520 struct rtl8169_private *tp = netdev_priv(dev);
6521
6522 if (!tp->TxDescArray)
6523 return 0;
6524
da78dbff 6525 rtl_lock_work(tp);
e1759441
RW		 6526 __rtl8169_set_wol(tp, tp->saved_wolopts);
6527 tp->saved_wolopts = 0;
da78dbff 6528 rtl_unlock_work(tp);
e1759441 6529
fccec10b
SG		 6530 rtl8169_init_phy(dev, tp);
6531
e1759441 6532 __rtl8169_resume(dev);
5d06a99f 6533
5d06a99f
FR		 6534 return 0;
6535}
6536
e1759441
RW		 6537static int rtl8169_runtime_idle(struct device *device)
6538{
6539 struct pci_dev *pdev = to_pci_dev(device);
6540 struct net_device *dev = pci_get_drvdata(pdev);
6541 struct rtl8169_private *tp = netdev_priv(dev);
6542
e4fbce74 6543 return tp->TxDescArray ? -EBUSY : 0;
e1759441
RW		 6544}
6545
47145210 6546static const struct dev_pm_ops rtl8169_pm_ops = {
cecb5fd7
FR		 6547 .suspend = rtl8169_suspend,
6548 .resume = rtl8169_resume,
6549 .freeze = rtl8169_suspend,
6550 .thaw = rtl8169_resume,
6551 .poweroff = rtl8169_suspend,
6552 .restore = rtl8169_resume,
6553 .runtime_suspend = rtl8169_runtime_suspend,
6554 .runtime_resume = rtl8169_runtime_resume,
6555 .runtime_idle = rtl8169_runtime_idle,
861ab440
RW		 6556};
6557
6558#define RTL8169_PM_OPS (&rtl8169_pm_ops)
6559
6560#else /* !CONFIG_PM */
6561
6562#define RTL8169_PM_OPS NULL
6563
6564#endif /* !CONFIG_PM */
6565
649b3b8c 6566static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6567{
6568 void __iomem *ioaddr = tp->mmio_addr;
6569
6570 /* WoL fails with 8168b when the receiver is disabled. */
6571 switch (tp->mac_version) {
6572 case RTL_GIGA_MAC_VER_11:
6573 case RTL_GIGA_MAC_VER_12:
6574 case RTL_GIGA_MAC_VER_17:
6575 pci_clear_master(tp->pci_dev);
6576
6577 RTL_W8(ChipCmd, CmdRxEnb);
6578 /* PCI commit */
6579 RTL_R8(ChipCmd);
6580 break;
6581 default:
6582 break;
6583 }
6584}
6585
1765f95d
FR		 6586static void rtl_shutdown(struct pci_dev *pdev)
6587{
861ab440 6588 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 6589 struct rtl8169_private *tp = netdev_priv(dev);
2a15cd2f 6590 struct device *d = &pdev->dev;
6591
6592 pm_runtime_get_sync(d);
861ab440
RW		 6593
6594 rtl8169_net_suspend(dev);
1765f95d 6595
cecb5fd7 6596 /* Restore original MAC address */
cc098dc7
IV		 6597 rtl_rar_set(tp, dev->perm_addr);
6598
92fc43b4 6599 rtl8169_hw_reset(tp);
4bb3f522 6600
861ab440 6601 if (system_state == SYSTEM_POWER_OFF) {
649b3b8c 6602 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
6603 rtl_wol_suspend_quirk(tp);
6604 rtl_wol_shutdown_quirk(tp);
ca52efd5 6605 }
6606
861ab440
RW		 6607 pci_wake_from_d3(pdev, true);
6608 pci_set_power_state(pdev, PCI_D3hot);
6609 }
2a15cd2f 6610
6611 pm_runtime_put_noidle(d);
861ab440 6612}
5d06a99f 6613
e27566ed
FR		 6614static void __devexit rtl_remove_one(struct pci_dev *pdev)
6615{
6616 struct net_device *dev = pci_get_drvdata(pdev);
6617 struct rtl8169_private *tp = netdev_priv(dev);
6618
6619 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
6620 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
6621 tp->mac_version == RTL_GIGA_MAC_VER_31) {
6622 rtl8168_driver_stop(tp);
6623 }
6624
6625 cancel_work_sync(&tp->wk.work);
6626
ad1be8d3
DN		 6627 netif_napi_del(&tp->napi);
6628
e27566ed
FR		 6629 unregister_netdev(dev);
6630
6631 rtl_release_firmware(tp);
6632
6633 if (pci_dev_run_wake(pdev))
6634 pm_runtime_get_noresume(&pdev->dev);
6635
6636 /* restore original MAC address */
6637 rtl_rar_set(tp, dev->perm_addr);
6638
6639 rtl_disable_msi(pdev, tp);
6640 rtl8169_release_board(pdev, dev, tp->mmio_addr);
6641 pci_set_drvdata(pdev, NULL);
6642}
6643
fa9c385e 6644static const struct net_device_ops rtl_netdev_ops = {
df43ac78 6645 .ndo_open = rtl_open,
fa9c385e
FR		 6646 .ndo_stop = rtl8169_close,
6647 .ndo_get_stats64 = rtl8169_get_stats64,
6648 .ndo_start_xmit = rtl8169_start_xmit,
6649 .ndo_tx_timeout = rtl8169_tx_timeout,
6650 .ndo_validate_addr = eth_validate_addr,
6651 .ndo_change_mtu = rtl8169_change_mtu,
6652 .ndo_fix_features = rtl8169_fix_features,
6653 .ndo_set_features = rtl8169_set_features,
6654 .ndo_set_mac_address = rtl_set_mac_address,
6655 .ndo_do_ioctl = rtl8169_ioctl,
6656 .ndo_set_rx_mode = rtl_set_rx_mode,
6657#ifdef CONFIG_NET_POLL_CONTROLLER
6658 .ndo_poll_controller = rtl8169_netpoll,
6659#endif
6660
6661};
6662
31fa8b18
FR		 6663static const struct rtl_cfg_info {
6664 void (*hw_start)(struct net_device *);
6665 unsigned int region;
6666 unsigned int align;
6667 u16 event_slow;
6668 unsigned features;
6669 u8 default_ver;
6670} rtl_cfg_infos [] = {
6671 [RTL_CFG_0] = {
6672 .hw_start = rtl_hw_start_8169,
6673 .region = 1,
6674 .align = 0,
6675 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
6676 .features = RTL_FEATURE_GMII,
6677 .default_ver = RTL_GIGA_MAC_VER_01,
6678 },
6679 [RTL_CFG_1] = {
6680 .hw_start = rtl_hw_start_8168,
6681 .region = 2,
6682 .align = 8,
6683 .event_slow = SYSErr | LinkChg | RxOverflow,
6684 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
6685 .default_ver = RTL_GIGA_MAC_VER_11,
6686 },
6687 [RTL_CFG_2] = {
6688 .hw_start = rtl_hw_start_8101,
6689 .region = 2,
6690 .align = 8,
6691 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
6692 PCSTimeout,
6693 .features = RTL_FEATURE_MSI,
6694 .default_ver = RTL_GIGA_MAC_VER_13,
6695 }
6696};
6697
6698/* Cfg9346_Unlock assumed. */
6699static unsigned rtl_try_msi(struct rtl8169_private *tp,
6700 const struct rtl_cfg_info *cfg)
6701{
6702 void __iomem *ioaddr = tp->mmio_addr;
6703 unsigned msi = 0;
6704 u8 cfg2;
6705
6706 cfg2 = RTL_R8(Config2) & ~MSIEnable;
6707 if (cfg->features & RTL_FEATURE_MSI) {
6708 if (pci_enable_msi(tp->pci_dev)) {
6709 netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
6710 } else {
6711 cfg2 |= MSIEnable;
6712 msi = RTL_FEATURE_MSI;
6713 }
6714 }
6715 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
6716 RTL_W8(Config2, cfg2);
6717 return msi;
6718}
6719
c558386b
HW		 6720DECLARE_RTL_COND(rtl_link_list_ready_cond)
6721{
6722 void __iomem *ioaddr = tp->mmio_addr;
6723
6724 return RTL_R8(MCU) & LINK_LIST_RDY;
6725}
6726
6727DECLARE_RTL_COND(rtl_rxtx_empty_cond)
6728{
6729 void __iomem *ioaddr = tp->mmio_addr;
6730
6731 return (RTL_R8(MCU) & RXTX_EMPTY) == RXTX_EMPTY;
6732}
6733
6734static void __devinit rtl_hw_init_8168g(struct rtl8169_private *tp)
6735{
6736 void __iomem *ioaddr = tp->mmio_addr;
6737 u32 data;
6738
6739 tp->ocp_base = OCP_STD_PHY_BASE;
6740
6741 RTL_W32(MISC, RTL_R32(MISC) | RXDV_GATED_EN);
6742
6743 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
6744 return;
6745
6746 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
6747 return;
6748
6749 RTL_W8(ChipCmd, RTL_R8(ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
6750 msleep(1);
6751 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
6752
5f8bcce9 6753 data = r8168_mac_ocp_read(tp, 0xe8de);
c558386b
HW		 6754 data &= ~(1 << 14);
6755 r8168_mac_ocp_write(tp, 0xe8de, data);
6756
6757 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6758 return;
6759
5f8bcce9 6760 data = r8168_mac_ocp_read(tp, 0xe8de);
c558386b
HW		 6761 data |= (1 << 15);
6762 r8168_mac_ocp_write(tp, 0xe8de, data);
6763
6764 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6765 return;
6766}
6767
6768static void __devinit rtl_hw_initialize(struct rtl8169_private *tp)
6769{
6770 switch (tp->mac_version) {
6771 case RTL_GIGA_MAC_VER_40:
6772 case RTL_GIGA_MAC_VER_41:
6773 rtl_hw_init_8168g(tp);
6774 break;
6775
6776 default:
6777 break;
6778 }
6779}
6780
3b6cf25d
FR		 6781static int __devinit
6782rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6783{
6784 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
6785 const unsigned int region = cfg->region;
6786 struct rtl8169_private *tp;
6787 struct mii_if_info *mii;
6788 struct net_device *dev;
6789 void __iomem *ioaddr;
6790 int chipset, i;
6791 int rc;
6792
6793 if (netif_msg_drv(&debug)) {
6794 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
6795 MODULENAME, RTL8169_VERSION);
6796 }
6797
6798 dev = alloc_etherdev(sizeof (*tp));
6799 if (!dev) {
6800 rc = -ENOMEM;
6801 goto out;
6802 }
6803
6804 SET_NETDEV_DEV(dev, &pdev->dev);
fa9c385e 6805 dev->netdev_ops = &rtl_netdev_ops;
3b6cf25d
FR		 6806 tp = netdev_priv(dev);
6807 tp->dev = dev;
6808 tp->pci_dev = pdev;
6809 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
6810
6811 mii = &tp->mii;
6812 mii->dev = dev;
6813 mii->mdio_read = rtl_mdio_read;
6814 mii->mdio_write = rtl_mdio_write;
6815 mii->phy_id_mask = 0x1f;
6816 mii->reg_num_mask = 0x1f;
6817 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
6818
6819 /* disable ASPM completely as that cause random device stop working
6820 * problems as well as full system hangs for some PCIe devices users */
6821 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
6822 PCIE_LINK_STATE_CLKPM);
6823
6824 /* enable device (incl. PCI PM wakeup and hotplug setup) */
6825 rc = pci_enable_device(pdev);
6826 if (rc < 0) {
6827 netif_err(tp, probe, dev, "enable failure\n");
6828 goto err_out_free_dev_1;
6829 }
6830
6831 if (pci_set_mwi(pdev) < 0)
6832 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
6833
6834 /* make sure PCI base addr 1 is MMIO */
6835 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
6836 netif_err(tp, probe, dev,
6837 "region #%d not an MMIO resource, aborting\n",
6838 region);
6839 rc = -ENODEV;
6840 goto err_out_mwi_2;
6841 }
6842
6843 /* check for weird/broken PCI region reporting */
6844 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
6845 netif_err(tp, probe, dev,
6846 "Invalid PCI region size(s), aborting\n");
6847 rc = -ENODEV;
6848 goto err_out_mwi_2;
6849 }
6850
6851 rc = pci_request_regions(pdev, MODULENAME);
6852 if (rc < 0) {
6853 netif_err(tp, probe, dev, "could not request regions\n");
6854 goto err_out_mwi_2;
6855 }
6856
6857 tp->cp_cmd = RxChkSum;
6858
6859 if ((sizeof(dma_addr_t) > 4) &&
6860 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
6861 tp->cp_cmd |= PCIDAC;
6862 dev->features |= NETIF_F_HIGHDMA;
6863 } else {
6864 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6865 if (rc < 0) {
6866 netif_err(tp, probe, dev, "DMA configuration failed\n");
6867 goto err_out_free_res_3;
6868 }
6869 }
6870
6871 /* ioremap MMIO region */
6872 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
6873 if (!ioaddr) {
6874 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
6875 rc = -EIO;
6876 goto err_out_free_res_3;
6877 }
6878 tp->mmio_addr = ioaddr;
6879
6880 if (!pci_is_pcie(pdev))
6881 netif_info(tp, probe, dev, "not PCI Express\n");
6882
6883 /* Identify chip attached to board */
6884 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
6885
6886 rtl_init_rxcfg(tp);
6887
6888 rtl_irq_disable(tp);
6889
c558386b
HW		 6890 rtl_hw_initialize(tp);
6891
3b6cf25d
FR		 6892 rtl_hw_reset(tp);
6893
6894 rtl_ack_events(tp, 0xffff);
6895
6896 pci_set_master(pdev);
6897
6898 /*
6899 * Pretend we are using VLANs; This bypasses a nasty bug where
6900 * Interrupts stop flowing on high load on 8110SCd controllers.
6901 */
6902 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6903 tp->cp_cmd |= RxVlan;
6904
6905 rtl_init_mdio_ops(tp);
6906 rtl_init_pll_power_ops(tp);
6907 rtl_init_jumbo_ops(tp);
beb1fe18 6908 rtl_init_csi_ops(tp);
3b6cf25d
FR		 6909
6910 rtl8169_print_mac_version(tp);
6911
6912 chipset = tp->mac_version;
6913 tp->txd_version = rtl_chip_infos[chipset].txd_version;
6914
6915 RTL_W8(Cfg9346, Cfg9346_Unlock);
6916 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
6917 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
6918 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
6919 tp->features |= RTL_FEATURE_WOL;
6920 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
6921 tp->features |= RTL_FEATURE_WOL;
6922 tp->features |= rtl_try_msi(tp, cfg);
6923 RTL_W8(Cfg9346, Cfg9346_Lock);
6924
6925 if (rtl_tbi_enabled(tp)) {
6926 tp->set_speed = rtl8169_set_speed_tbi;
6927 tp->get_settings = rtl8169_gset_tbi;
6928 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
6929 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
6930 tp->link_ok = rtl8169_tbi_link_ok;
6931 tp->do_ioctl = rtl_tbi_ioctl;
6932 } else {
6933 tp->set_speed = rtl8169_set_speed_xmii;
6934 tp->get_settings = rtl8169_gset_xmii;
6935 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
6936 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
6937 tp->link_ok = rtl8169_xmii_link_ok;
6938 tp->do_ioctl = rtl_xmii_ioctl;
6939 }
6940
6941 mutex_init(&tp->wk.mutex);
6942
6943 /* Get MAC address */
6944 for (i = 0; i < ETH_ALEN; i++)
6945 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6946 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
6947
6948 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
6949 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3b6cf25d
FR		 6950
6951 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
6952
6953 /* don't enable SG, IP_CSUM and TSO by default - it might not work
6954 * properly for all devices */
6955 dev->features |= NETIF_F_RXCSUM |
6956 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6957
6958 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6959 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6960 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6961 NETIF_F_HIGHDMA;
6962
6963 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6964 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
6965 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
6966
6967 dev->hw_features |= NETIF_F_RXALL;
6968 dev->hw_features |= NETIF_F_RXFCS;
6969
6970 tp->hw_start = cfg->hw_start;
6971 tp->event_slow = cfg->event_slow;
6972
6973 tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
6974 ~(RxBOVF | RxFOVF) : ~0;
6975
6976 init_timer(&tp->timer);
6977 tp->timer.data = (unsigned long) dev;
6978 tp->timer.function = rtl8169_phy_timer;
6979
6980 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
6981
6982 rc = register_netdev(dev);
6983 if (rc < 0)
6984 goto err_out_msi_4;
6985
6986 pci_set_drvdata(pdev, dev);
6987
92a7c4e7
FR		 6988 netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
6989 rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
6990 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
3b6cf25d
FR		 6991 if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
6992 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
6993 "tx checksumming: %s]\n",
6994 rtl_chip_infos[chipset].jumbo_max,
6995 rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
6996 }
6997
6998 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
6999 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
7000 tp->mac_version == RTL_GIGA_MAC_VER_31) {
7001 rtl8168_driver_start(tp);
7002 }
7003
7004 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
7005
7006 if (pci_dev_run_wake(pdev))
7007 pm_runtime_put_noidle(&pdev->dev);
7008
7009 netif_carrier_off(dev);
7010
7011out:
7012 return rc;
7013
7014err_out_msi_4:
ad1be8d3 7015 netif_napi_del(&tp->napi);
3b6cf25d
FR		 7016 rtl_disable_msi(pdev, tp);
7017 iounmap(ioaddr);
7018err_out_free_res_3:
7019 pci_release_regions(pdev);
7020err_out_mwi_2:
7021 pci_clear_mwi(pdev);
7022 pci_disable_device(pdev);
7023err_out_free_dev_1:
7024 free_netdev(dev);
7025 goto out;
7026}
7027
1da177e4
LT		 7028static struct pci_driver rtl8169_pci_driver = {
7029 .name = MODULENAME,
7030 .id_table = rtl8169_pci_tbl,
3b6cf25d 7031 .probe = rtl_init_one,
e27566ed 7032 .remove = __devexit_p(rtl_remove_one),
1765f95d 7033 .shutdown = rtl_shutdown,
861ab440 7034 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 7035};
7036
3eeb7da9 7037module_pci_driver(rtl8169_pci_driver);
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