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r8169:add more chips to support magic packet v2
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / realtek / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
a6b7a407 24#include <linux/interrupt.h>
1da177e4 25#include <linux/dma-mapping.h>
e1759441 26#include <linux/pm_runtime.h>
bca03d5f 27#include <linux/firmware.h>
ba04c7c9 28#include <linux/pci-aspm.h>
70c71606 29#include <linux/prefetch.h>
e974604b 30#include <linux/ipv6.h>
31#include <net/ip6_checksum.h>
1da177e4
LT		 32
33#include <asm/io.h>
34#include <asm/irq.h>
35
865c652d 36#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 37#define MODULENAME "r8169"
38#define PFX MODULENAME ": "
39
bca03d5f 40#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
41#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
01dc7fec 42#define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
43#define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
70090424 44#define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
c2218925
HW		 45#define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
46#define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
5a5e4443 47#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
7e18dca1 48#define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
b3d7b2f2 49#define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
45dd95c4 50#define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
5598bfe5 51#define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
58152cd4 52#define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
beb330a4 53#define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
57538c4a 54#define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
6e1d0b89
CHL		 55#define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw"
56#define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
57#define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw"
58#define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
bca03d5f 59
1da177e4
LT		 60#ifdef RTL8169_DEBUG
61#define assert(expr) \
5b0384f4
FR		 62 if (!(expr)) { \
63 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
b39d66a8 64 #expr,__FILE__,__func__,__LINE__); \
5b0384f4 65 }
06fa7358
JP		 66#define dprintk(fmt, args...) \
67 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 68#else
69#define assert(expr) do {} while (0)
70#define dprintk(fmt, args...) do {} while (0)
71#endif /* RTL8169_DEBUG */
72
b57b7e5a 73#define R8169_MSG_DEFAULT \
f0e837d9 74 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 75
477206a0
JD		 76#define TX_SLOTS_AVAIL(tp) \
77 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
78
79/* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
80#define TX_FRAGS_READY_FOR(tp,nr_frags) \
81 (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
1da177e4 82
1da177e4
LT		 83/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
84 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 85static const int multicast_filter_limit = 32;
1da177e4 86
9c14ceaf 87#define MAX_READ_REQUEST_SHIFT 12
aee77e4a 88#define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
1da177e4
LT		 89#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
90
91#define R8169_REGS_SIZE 256
92#define R8169_NAPI_WEIGHT 64
93#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
9fba0812 94#define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
1da177e4
LT		 95#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
96#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
97
98#define RTL8169_TX_TIMEOUT (6*HZ)
99#define RTL8169_PHY_TIMEOUT (10*HZ)
100
101/* write/read MMIO register */
102#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
103#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
104#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
105#define RTL_R8(reg) readb (ioaddr + (reg))
106#define RTL_R16(reg) readw (ioaddr + (reg))
06f555f3 107#define RTL_R32(reg) readl (ioaddr + (reg))
1da177e4
LT		 108
109enum mac_version {
85bffe6c
FR		 110 RTL_GIGA_MAC_VER_01 = 0,
111 RTL_GIGA_MAC_VER_02,
112 RTL_GIGA_MAC_VER_03,
113 RTL_GIGA_MAC_VER_04,
114 RTL_GIGA_MAC_VER_05,
115 RTL_GIGA_MAC_VER_06,
116 RTL_GIGA_MAC_VER_07,
117 RTL_GIGA_MAC_VER_08,
118 RTL_GIGA_MAC_VER_09,
119 RTL_GIGA_MAC_VER_10,
120 RTL_GIGA_MAC_VER_11,
121 RTL_GIGA_MAC_VER_12,
122 RTL_GIGA_MAC_VER_13,
123 RTL_GIGA_MAC_VER_14,
124 RTL_GIGA_MAC_VER_15,
125 RTL_GIGA_MAC_VER_16,
126 RTL_GIGA_MAC_VER_17,
127 RTL_GIGA_MAC_VER_18,
128 RTL_GIGA_MAC_VER_19,
129 RTL_GIGA_MAC_VER_20,
130 RTL_GIGA_MAC_VER_21,
131 RTL_GIGA_MAC_VER_22,
132 RTL_GIGA_MAC_VER_23,
133 RTL_GIGA_MAC_VER_24,
134 RTL_GIGA_MAC_VER_25,
135 RTL_GIGA_MAC_VER_26,
136 RTL_GIGA_MAC_VER_27,
137 RTL_GIGA_MAC_VER_28,
138 RTL_GIGA_MAC_VER_29,
139 RTL_GIGA_MAC_VER_30,
140 RTL_GIGA_MAC_VER_31,
141 RTL_GIGA_MAC_VER_32,
142 RTL_GIGA_MAC_VER_33,
70090424 143 RTL_GIGA_MAC_VER_34,
c2218925
HW		 144 RTL_GIGA_MAC_VER_35,
145 RTL_GIGA_MAC_VER_36,
7e18dca1 146 RTL_GIGA_MAC_VER_37,
b3d7b2f2 147 RTL_GIGA_MAC_VER_38,
5598bfe5 148 RTL_GIGA_MAC_VER_39,
c558386b
HW		 149 RTL_GIGA_MAC_VER_40,
150 RTL_GIGA_MAC_VER_41,
57538c4a 151 RTL_GIGA_MAC_VER_42,
58152cd4 152 RTL_GIGA_MAC_VER_43,
45dd95c4 153 RTL_GIGA_MAC_VER_44,
6e1d0b89
CHL		 154 RTL_GIGA_MAC_VER_45,
155 RTL_GIGA_MAC_VER_46,
156 RTL_GIGA_MAC_VER_47,
157 RTL_GIGA_MAC_VER_48,
85bffe6c 158 RTL_GIGA_MAC_NONE = 0xff,
1da177e4
LT		 159};
160
2b7b4318
FR		 161enum rtl_tx_desc_version {
162 RTL_TD_0 = 0,
163 RTL_TD_1 = 1,
164};
165
d58d46b5
FR		 166#define JUMBO_1K ETH_DATA_LEN
167#define JUMBO_4K (4*1024 - ETH_HLEN - 2)
168#define JUMBO_6K (6*1024 - ETH_HLEN - 2)
169#define JUMBO_7K (7*1024 - ETH_HLEN - 2)
170#define JUMBO_9K (9*1024 - ETH_HLEN - 2)
171
172#define _R(NAME,TD,FW,SZ,B) { \
173 .name = NAME, \
174 .txd_version = TD, \
175 .fw_name = FW, \
176 .jumbo_max = SZ, \
177 .jumbo_tx_csum = B \
178}
1da177e4 179
3c6bee1d 180static const struct {
1da177e4 181 const char *name;
2b7b4318 182 enum rtl_tx_desc_version txd_version;
953a12cc 183 const char *fw_name;
d58d46b5
FR		 184 u16 jumbo_max;
185 bool jumbo_tx_csum;
85bffe6c
FR		 186} rtl_chip_infos[] = {
187 /* PCI devices. */
188 [RTL_GIGA_MAC_VER_01] =
d58d46b5 189 _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 190 [RTL_GIGA_MAC_VER_02] =
d58d46b5 191 _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 192 [RTL_GIGA_MAC_VER_03] =
d58d46b5 193 _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 194 [RTL_GIGA_MAC_VER_04] =
d58d46b5 195 _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 196 [RTL_GIGA_MAC_VER_05] =
d58d46b5 197 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 198 [RTL_GIGA_MAC_VER_06] =
d58d46b5 199 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c
FR		 200 /* PCI-E devices. */
201 [RTL_GIGA_MAC_VER_07] =
d58d46b5 202 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 203 [RTL_GIGA_MAC_VER_08] =
d58d46b5 204 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 205 [RTL_GIGA_MAC_VER_09] =
d58d46b5 206 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 207 [RTL_GIGA_MAC_VER_10] =
d58d46b5 208 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 209 [RTL_GIGA_MAC_VER_11] =
d58d46b5 210 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
85bffe6c 211 [RTL_GIGA_MAC_VER_12] =
d58d46b5 212 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
85bffe6c 213 [RTL_GIGA_MAC_VER_13] =
d58d46b5 214 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 215 [RTL_GIGA_MAC_VER_14] =
d58d46b5 216 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 217 [RTL_GIGA_MAC_VER_15] =
d58d46b5 218 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 219 [RTL_GIGA_MAC_VER_16] =
d58d46b5 220 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 221 [RTL_GIGA_MAC_VER_17] =
f75761b6 222 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
85bffe6c 223 [RTL_GIGA_MAC_VER_18] =
d58d46b5 224 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 225 [RTL_GIGA_MAC_VER_19] =
d58d46b5 226 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 227 [RTL_GIGA_MAC_VER_20] =
d58d46b5 228 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 229 [RTL_GIGA_MAC_VER_21] =
d58d46b5 230 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 231 [RTL_GIGA_MAC_VER_22] =
d58d46b5 232 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 233 [RTL_GIGA_MAC_VER_23] =
d58d46b5 234 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 235 [RTL_GIGA_MAC_VER_24] =
d58d46b5 236 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 237 [RTL_GIGA_MAC_VER_25] =
d58d46b5
FR		 238 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1,
239 JUMBO_9K, false),
85bffe6c 240 [RTL_GIGA_MAC_VER_26] =
d58d46b5
FR		 241 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2,
242 JUMBO_9K, false),
85bffe6c 243 [RTL_GIGA_MAC_VER_27] =
d58d46b5 244 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 245 [RTL_GIGA_MAC_VER_28] =
d58d46b5 246 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 247 [RTL_GIGA_MAC_VER_29] =
d58d46b5
FR		 248 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
249 JUMBO_1K, true),
85bffe6c 250 [RTL_GIGA_MAC_VER_30] =
d58d46b5
FR		 251 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
252 JUMBO_1K, true),
85bffe6c 253 [RTL_GIGA_MAC_VER_31] =
d58d46b5 254 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 255 [RTL_GIGA_MAC_VER_32] =
d58d46b5
FR		 256 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1,
257 JUMBO_9K, false),
85bffe6c 258 [RTL_GIGA_MAC_VER_33] =
d58d46b5
FR		 259 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2,
260 JUMBO_9K, false),
70090424 261 [RTL_GIGA_MAC_VER_34] =
d58d46b5
FR		 262 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
263 JUMBO_9K, false),
c2218925 264 [RTL_GIGA_MAC_VER_35] =
d58d46b5
FR		 265 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1,
266 JUMBO_9K, false),
c2218925 267 [RTL_GIGA_MAC_VER_36] =
d58d46b5
FR		 268 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2,
269 JUMBO_9K, false),
7e18dca1
HW		 270 [RTL_GIGA_MAC_VER_37] =
271 _R("RTL8402", RTL_TD_1, FIRMWARE_8402_1,
272 JUMBO_1K, true),
b3d7b2f2
HW		 273 [RTL_GIGA_MAC_VER_38] =
274 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_1,
275 JUMBO_9K, false),
5598bfe5
HW		 276 [RTL_GIGA_MAC_VER_39] =
277 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_1,
278 JUMBO_1K, true),
c558386b 279 [RTL_GIGA_MAC_VER_40] =
beb330a4 280 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_2,
c558386b
HW		 281 JUMBO_9K, false),
282 [RTL_GIGA_MAC_VER_41] =
283 _R("RTL8168g/8111g", RTL_TD_1, NULL, JUMBO_9K, false),
57538c4a 284 [RTL_GIGA_MAC_VER_42] =
285 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_3,
286 JUMBO_9K, false),
58152cd4 287 [RTL_GIGA_MAC_VER_43] =
288 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_2,
289 JUMBO_1K, true),
45dd95c4 290 [RTL_GIGA_MAC_VER_44] =
291 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_2,
292 JUMBO_9K, false),
6e1d0b89
CHL		 293 [RTL_GIGA_MAC_VER_45] =
294 _R("RTL8168h/8111h", RTL_TD_1, FIRMWARE_8168H_1,
295 JUMBO_9K, false),
296 [RTL_GIGA_MAC_VER_46] =
297 _R("RTL8168h/8111h", RTL_TD_1, FIRMWARE_8168H_2,
298 JUMBO_9K, false),
299 [RTL_GIGA_MAC_VER_47] =
300 _R("RTL8107e", RTL_TD_1, FIRMWARE_8107E_1,
301 JUMBO_1K, false),
302 [RTL_GIGA_MAC_VER_48] =
303 _R("RTL8107e", RTL_TD_1, FIRMWARE_8107E_2,
304 JUMBO_1K, false),
953a12cc 305};
85bffe6c 306#undef _R
953a12cc 307
bcf0bf90
FR		 308enum cfg_version {
309 RTL_CFG_0 = 0x00,
310 RTL_CFG_1,
311 RTL_CFG_2
312};
313
9baa3c34 314static const struct pci_device_id rtl8169_pci_tbl[] = {
bcf0bf90 315 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 316 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 317 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 318 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90 319 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
2a35cfa5
FR		 320 { PCI_VENDOR_ID_DLINK, 0x4300,
321 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
bcf0bf90 322 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
93a3aa25 323 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
bc1660b5 324 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 325 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
326 { PCI_VENDOR_ID_LINKSYS, 0x1032,
327 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 328 { 0x0001, 0x8168,
329 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 330 {0,},
331};
332
333MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
334
6f0333b8 335static int rx_buf_sz = 16383;
4300e8c7 336static int use_dac;
b57b7e5a
SH		 337static struct {
338 u32 msg_enable;
339} debug = { -1 };
1da177e4 340
07d3f51f
FR		 341enum rtl_registers {
342 MAC0 = 0, /* Ethernet hardware address. */
773d2021 343 MAC4 = 4,
07d3f51f
FR		 344 MAR0 = 8, /* Multicast filter. */
345 CounterAddrLow = 0x10,
346 CounterAddrHigh = 0x14,
347 TxDescStartAddrLow = 0x20,
348 TxDescStartAddrHigh = 0x24,
349 TxHDescStartAddrLow = 0x28,
350 TxHDescStartAddrHigh = 0x2c,
351 FLASH = 0x30,
352 ERSR = 0x36,
353 ChipCmd = 0x37,
354 TxPoll = 0x38,
355 IntrMask = 0x3c,
356 IntrStatus = 0x3e,
4f6b00e5 357
07d3f51f 358 TxConfig = 0x40,
4f6b00e5
HW		 359#define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
360#define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
2b7b4318 361
4f6b00e5
HW		 362 RxConfig = 0x44,
363#define RX128_INT_EN (1 << 15) /* 8111c and later */
364#define RX_MULTI_EN (1 << 14) /* 8111c only */
365#define RXCFG_FIFO_SHIFT 13
366 /* No threshold before first PCI xfer */
367#define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
beb330a4 368#define RX_EARLY_OFF (1 << 11)
4f6b00e5
HW		 369#define RXCFG_DMA_SHIFT 8
370 /* Unlimited maximum PCI burst. */
371#define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
2b7b4318 372
07d3f51f
FR		 373 RxMissed = 0x4c,
374 Cfg9346 = 0x50,
375 Config0 = 0x51,
376 Config1 = 0x52,
377 Config2 = 0x53,
d387b427
FR		 378#define PME_SIGNAL (1 << 5) /* 8168c and later */
379
07d3f51f
FR		 380 Config3 = 0x54,
381 Config4 = 0x55,
382 Config5 = 0x56,
383 MultiIntr = 0x5c,
384 PHYAR = 0x60,
07d3f51f
FR		 385 PHYstatus = 0x6c,
386 RxMaxSize = 0xda,
387 CPlusCmd = 0xe0,
388 IntrMitigate = 0xe2,
389 RxDescAddrLow = 0xe4,
390 RxDescAddrHigh = 0xe8,
f0298f81 391 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
392
393#define NoEarlyTx 0x3f /* Max value : no early transmit. */
394
395 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
396
397#define TxPacketMax (8064 >> 7)
3090bd9a 398#define EarlySize 0x27
f0298f81 399
07d3f51f
FR		 400 FuncEvent = 0xf0,
401 FuncEventMask = 0xf4,
402 FuncPresetState = 0xf8,
403 FuncForceEvent = 0xfc,
1da177e4
LT		 404};
405
f162a5d1
FR		 406enum rtl8110_registers {
407 TBICSR = 0x64,
408 TBI_ANAR = 0x68,
409 TBI_LPAR = 0x6a,
410};
411
412enum rtl8168_8101_registers {
413 CSIDR = 0x64,
414 CSIAR = 0x68,
415#define CSIAR_FLAG 0x80000000
416#define CSIAR_WRITE_CMD 0x80000000
417#define CSIAR_BYTE_ENABLE 0x0f
418#define CSIAR_BYTE_ENABLE_SHIFT 12
419#define CSIAR_ADDR_MASK 0x0fff
7e18dca1
HW		 420#define CSIAR_FUNC_CARD 0x00000000
421#define CSIAR_FUNC_SDIO 0x00010000
422#define CSIAR_FUNC_NIC 0x00020000
45dd95c4 423#define CSIAR_FUNC_NIC2 0x00010000
065c27c1 424 PMCH = 0x6f,
f162a5d1
FR		 425 EPHYAR = 0x80,
426#define EPHYAR_FLAG 0x80000000
427#define EPHYAR_WRITE_CMD 0x80000000
428#define EPHYAR_REG_MASK 0x1f
429#define EPHYAR_REG_SHIFT 16
430#define EPHYAR_DATA_MASK 0xffff
5a5e4443 431 DLLPR = 0xd0,
4f6b00e5 432#define PFM_EN (1 << 6)
6e1d0b89 433#define TX_10M_PS_EN (1 << 7)
f162a5d1
FR		 434 DBG_REG = 0xd1,
435#define FIX_NAK_1 (1 << 4)
436#define FIX_NAK_2 (1 << 3)
5a5e4443
HW		 437 TWSI = 0xd2,
438 MCU = 0xd3,
4f6b00e5 439#define NOW_IS_OOB (1 << 7)
c558386b
HW		 440#define TX_EMPTY (1 << 5)
441#define RX_EMPTY (1 << 4)
442#define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
5a5e4443
HW		 443#define EN_NDP (1 << 3)
444#define EN_OOB_RESET (1 << 2)
c558386b 445#define LINK_LIST_RDY (1 << 1)
daf9df6d 446 EFUSEAR = 0xdc,
447#define EFUSEAR_FLAG 0x80000000
448#define EFUSEAR_WRITE_CMD 0x80000000
449#define EFUSEAR_READ_CMD 0x00000000
450#define EFUSEAR_REG_MASK 0x03ff
451#define EFUSEAR_REG_SHIFT 8
452#define EFUSEAR_DATA_MASK 0xff
6e1d0b89
CHL		 453 MISC_1 = 0xf2,
454#define PFM_D3COLD_EN (1 << 6)
f162a5d1
FR		 455};
456
c0e45c1c 457enum rtl8168_registers {
4f6b00e5
HW		 458 LED_FREQ = 0x1a,
459 EEE_LED = 0x1b,
b646d900 460 ERIDR = 0x70,
461 ERIAR = 0x74,
462#define ERIAR_FLAG 0x80000000
463#define ERIAR_WRITE_CMD 0x80000000
464#define ERIAR_READ_CMD 0x00000000
465#define ERIAR_ADDR_BYTE_ALIGN 4
b646d900 466#define ERIAR_TYPE_SHIFT 16
4f6b00e5
HW		 467#define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
468#define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
469#define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
470#define ERIAR_MASK_SHIFT 12
471#define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
472#define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
6e1d0b89 473#define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
c558386b 474#define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
4f6b00e5 475#define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
c0e45c1c 476 EPHY_RXER_NUM = 0x7c,
477 OCPDR = 0xb0, /* OCP GPHY access */
478#define OCPDR_WRITE_CMD 0x80000000
479#define OCPDR_READ_CMD 0x00000000
480#define OCPDR_REG_MASK 0x7f
481#define OCPDR_GPHY_REG_SHIFT 16
482#define OCPDR_DATA_MASK 0xffff
483 OCPAR = 0xb4,
484#define OCPAR_FLAG 0x80000000
485#define OCPAR_GPHY_WRITE_CMD 0x8000f060
486#define OCPAR_GPHY_READ_CMD 0x0000f060
c558386b 487 GPHY_OCP = 0xb8,
01dc7fec 488 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
489 MISC = 0xf0, /* 8168e only. */
cecb5fd7 490#define TXPLA_RST (1 << 29)
5598bfe5 491#define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
4f6b00e5 492#define PWM_EN (1 << 22)
c558386b 493#define RXDV_GATED_EN (1 << 19)
5598bfe5 494#define EARLY_TALLY_EN (1 << 16)
c0e45c1c 495};
496
07d3f51f 497enum rtl_register_content {
1da177e4 498 /* InterruptStatusBits */
07d3f51f
FR		 499 SYSErr = 0x8000,
500 PCSTimeout = 0x4000,
501 SWInt = 0x0100,
502 TxDescUnavail = 0x0080,
503 RxFIFOOver = 0x0040,
504 LinkChg = 0x0020,
505 RxOverflow = 0x0010,
506 TxErr = 0x0008,
507 TxOK = 0x0004,
508 RxErr = 0x0002,
509 RxOK = 0x0001,
1da177e4
LT		 510
511 /* RxStatusDesc */
e03f33af 512 RxBOVF = (1 << 24),
9dccf611
FR		 513 RxFOVF = (1 << 23),
514 RxRWT = (1 << 22),
515 RxRES = (1 << 21),
516 RxRUNT = (1 << 20),
517 RxCRC = (1 << 19),
1da177e4
LT		 518
519 /* ChipCmdBits */
4f6b00e5 520 StopReq = 0x80,
07d3f51f
FR		 521 CmdReset = 0x10,
522 CmdRxEnb = 0x08,
523 CmdTxEnb = 0x04,
524 RxBufEmpty = 0x01,
1da177e4 525
275391a4
FR		 526 /* TXPoll register p.5 */
527 HPQ = 0x80, /* Poll cmd on the high prio queue */
528 NPQ = 0x40, /* Poll cmd on the low prio queue */
529 FSWInt = 0x01, /* Forced software interrupt */
530
1da177e4 531 /* Cfg9346Bits */
07d3f51f
FR		 532 Cfg9346_Lock = 0x00,
533 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 534
535 /* rx_mode_bits */
07d3f51f
FR		 536 AcceptErr = 0x20,
537 AcceptRunt = 0x10,
538 AcceptBroadcast = 0x08,
539 AcceptMulticast = 0x04,
540 AcceptMyPhys = 0x02,
541 AcceptAllPhys = 0x01,
1687b566 542#define RX_CONFIG_ACCEPT_MASK 0x3f
1da177e4 543
1da177e4
LT		 544 /* TxConfigBits */
545 TxInterFrameGapShift = 24,
546 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
547
5d06a99f 548 /* Config1 register p.24 */
f162a5d1
FR		 549 LEDS1 = (1 << 7),
550 LEDS0 = (1 << 6),
f162a5d1
FR		 551 Speed_down = (1 << 4),
552 MEMMAP = (1 << 3),
553 IOMAP = (1 << 2),
554 VPD = (1 << 1),
5d06a99f
FR		 555 PMEnable = (1 << 0), /* Power Management Enable */
556
6dccd16b 557 /* Config2 register p. 25 */
57538c4a 558 ClkReqEn = (1 << 7), /* Clock Request Enable */
2ca6cf06 559 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
6dccd16b
FR		 560 PCI_Clock_66MHz = 0x01,
561 PCI_Clock_33MHz = 0x00,
562
61a4dcc2
FR		 563 /* Config3 register p.25 */
564 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
565 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
d58d46b5 566 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
b51ecea8 567 Rdy_to_L23 = (1 << 1), /* L23 Enable */
f162a5d1 568 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 569
d58d46b5
FR		 570 /* Config4 register */
571 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
572
5d06a99f 573 /* Config5 register p.27 */
61a4dcc2
FR		 574 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
575 MWF = (1 << 5), /* Accept Multicast wakeup frame */
576 UWF = (1 << 4), /* Accept Unicast wakeup frame */
cecb5fd7 577 Spi_en = (1 << 3),
61a4dcc2 578 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f 579 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
57538c4a 580 ASPM_en = (1 << 0), /* ASPM enable */
5d06a99f 581
1da177e4
LT		 582 /* TBICSR p.28 */
583 TBIReset = 0x80000000,
584 TBILoopback = 0x40000000,
585 TBINwEnable = 0x20000000,
586 TBINwRestart = 0x10000000,
587 TBILinkOk = 0x02000000,
588 TBINwComplete = 0x01000000,
589
590 /* CPlusCmd p.31 */
f162a5d1
FR		 591 EnableBist = (1 << 15), // 8168 8101
592 Mac_dbgo_oe = (1 << 14), // 8168 8101
593 Normal_mode = (1 << 13), // unused
594 Force_half_dup = (1 << 12), // 8168 8101
595 Force_rxflow_en = (1 << 11), // 8168 8101
596 Force_txflow_en = (1 << 10), // 8168 8101
597 Cxpl_dbg_sel = (1 << 9), // 8168 8101
598 ASF = (1 << 8), // 8168 8101
599 PktCntrDisable = (1 << 7), // 8168 8101
600 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 601 RxVlan = (1 << 6),
602 RxChkSum = (1 << 5),
603 PCIDAC = (1 << 4),
604 PCIMulRW = (1 << 3),
0e485150
FR		 605 INTT_0 = 0x0000, // 8168
606 INTT_1 = 0x0001, // 8168
607 INTT_2 = 0x0002, // 8168
608 INTT_3 = 0x0003, // 8168
1da177e4
LT		 609
610 /* rtl8169_PHYstatus */
07d3f51f
FR		 611 TBI_Enable = 0x80,
612 TxFlowCtrl = 0x40,
613 RxFlowCtrl = 0x20,
614 _1000bpsF = 0x10,
615 _100bps = 0x08,
616 _10bps = 0x04,
617 LinkStatus = 0x02,
618 FullDup = 0x01,
1da177e4 619
1da177e4 620 /* _TBICSRBit */
07d3f51f 621 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 622
623 /* DumpCounterCommand */
07d3f51f 624 CounterDump = 0x8,
6e1d0b89
CHL		 625
626 /* magic enable v2 */
627 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */
1da177e4
LT		 628};
629
2b7b4318
FR		 630enum rtl_desc_bit {
631 /* First doubleword. */
1da177e4
LT		 632 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
633 RingEnd = (1 << 30), /* End of descriptor ring */
634 FirstFrag = (1 << 29), /* First segment of a packet */
635 LastFrag = (1 << 28), /* Final segment of a packet */
2b7b4318
FR		 636};
637
638/* Generic case. */
639enum rtl_tx_desc_bit {
640 /* First doubleword. */
641 TD_LSO = (1 << 27), /* Large Send Offload */
642#define TD_MSS_MAX 0x07ffu /* MSS value */
1da177e4 643
2b7b4318
FR		 644 /* Second doubleword. */
645 TxVlanTag = (1 << 17), /* Add VLAN tag */
646};
647
648/* 8169, 8168b and 810x except 8102e. */
649enum rtl_tx_desc_bit_0 {
650 /* First doubleword. */
651#define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
652 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
653 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
654 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
655};
656
657/* 8102e, 8168c and beyond. */
658enum rtl_tx_desc_bit_1 {
bdfa4ed6 659 /* First doubleword. */
660 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */
e974604b 661 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */
bdfa4ed6 662#define GTTCPHO_SHIFT 18
e974604b 663#define GTTCPHO_MAX 0x7fU
bdfa4ed6 664
2b7b4318 665 /* Second doubleword. */
e974604b 666#define TCPHO_SHIFT 18
667#define TCPHO_MAX 0x3ffU
2b7b4318 668#define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
e974604b 669 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */
670 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */
2b7b4318
FR		 671 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
672 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
673};
1da177e4 674
2b7b4318 675enum rtl_rx_desc_bit {
1da177e4
LT		 676 /* Rx private */
677 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
678 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
679
680#define RxProtoUDP (PID1)
681#define RxProtoTCP (PID0)
682#define RxProtoIP (PID1 | PID0)
683#define RxProtoMask RxProtoIP
684
685 IPFail = (1 << 16), /* IP checksum failed */
686 UDPFail = (1 << 15), /* UDP/IP checksum failed */
687 TCPFail = (1 << 14), /* TCP/IP checksum failed */
688 RxVlanTag = (1 << 16), /* VLAN tag available */
689};
690
691#define RsvdMask 0x3fffc000
692
693struct TxDesc {
6cccd6e7
REB		 694 __le32 opts1;
695 __le32 opts2;
696 __le64 addr;
1da177e4
LT		 697};
698
699struct RxDesc {
6cccd6e7
REB		 700 __le32 opts1;
701 __le32 opts2;
702 __le64 addr;
1da177e4
LT		 703};
704
705struct ring_info {
706 struct sk_buff *skb;
707 u32 len;
708 u8 __pad[sizeof(void *) - sizeof(u32)];
709};
710
f23e7fda 711enum features {
ccdffb9a
FR		 712 RTL_FEATURE_WOL = (1 << 0),
713 RTL_FEATURE_MSI = (1 << 1),
714 RTL_FEATURE_GMII = (1 << 2),
f23e7fda
FR		 715};
716
355423d0
IV		 717struct rtl8169_counters {
718 __le64 tx_packets;
719 __le64 rx_packets;
720 __le64 tx_errors;
721 __le32 rx_errors;
722 __le16 rx_missed;
723 __le16 align_errors;
724 __le32 tx_one_collision;
725 __le32 tx_multi_collision;
726 __le64 rx_unicast;
727 __le64 rx_broadcast;
728 __le32 rx_multicast;
729 __le16 tx_aborted;
730 __le16 tx_underun;
731};
732
da78dbff 733enum rtl_flag {
6c4a70c5 734 RTL_FLAG_TASK_ENABLED,
da78dbff
FR		 735 RTL_FLAG_TASK_SLOW_PENDING,
736 RTL_FLAG_TASK_RESET_PENDING,
737 RTL_FLAG_TASK_PHY_PENDING,
738 RTL_FLAG_MAX
739};
740
8027aa24
JW		 741struct rtl8169_stats {
742 u64 packets;
743 u64 bytes;
744 struct u64_stats_sync syncp;
745};
746
1da177e4
LT		 747struct rtl8169_private {
748 void __iomem *mmio_addr; /* memory map physical address */
cecb5fd7 749 struct pci_dev *pci_dev;
c4028958 750 struct net_device *dev;
bea3348e 751 struct napi_struct napi;
b57b7e5a 752 u32 msg_enable;
2b7b4318
FR		 753 u16 txd_version;
754 u16 mac_version;
1da177e4
LT		 755 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
756 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
1da177e4 757 u32 dirty_tx;
8027aa24
JW		 758 struct rtl8169_stats rx_stats;
759 struct rtl8169_stats tx_stats;
1da177e4
LT		 760 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
761 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
762 dma_addr_t TxPhyAddr;
763 dma_addr_t RxPhyAddr;
6f0333b8 764 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
1da177e4 765 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
1da177e4
LT		 766 struct timer_list timer;
767 u16 cp_cmd;
da78dbff
FR		 768
769 u16 event_slow;
c0e45c1c 770
771 struct mdio_ops {
24192210
FR		 772 void (*write)(struct rtl8169_private *, int, int);
773 int (*read)(struct rtl8169_private *, int);
c0e45c1c 774 } mdio_ops;
775
065c27c1 776 struct pll_power_ops {
777 void (*down)(struct rtl8169_private *);
778 void (*up)(struct rtl8169_private *);
779 } pll_power_ops;
780
d58d46b5
FR		 781 struct jumbo_ops {
782 void (*enable)(struct rtl8169_private *);
783 void (*disable)(struct rtl8169_private *);
784 } jumbo_ops;
785
beb1fe18 786 struct csi_ops {
52989f0e
FR		 787 void (*write)(struct rtl8169_private *, int, int);
788 u32 (*read)(struct rtl8169_private *, int);
beb1fe18
HW		 789 } csi_ops;
790
54405cde 791 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
ccdffb9a 792 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
4da19633 793 void (*phy_reset_enable)(struct rtl8169_private *tp);
07ce4064 794 void (*hw_start)(struct net_device *);
4da19633 795 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
1da177e4 796 unsigned int (*link_ok)(void __iomem *);
8b4ab28d 797 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
5888d3fc 798 bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
4422bcd4
FR		 799
800 struct {
da78dbff
FR		 801 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
802 struct mutex mutex;
4422bcd4
FR		 803 struct work_struct work;
804 } wk;
805
f23e7fda 806 unsigned features;
ccdffb9a
FR		 807
808 struct mii_if_info mii;
355423d0 809 struct rtl8169_counters counters;
e1759441 810 u32 saved_wolopts;
e03f33af 811 u32 opts1_mask;
f1e02ed1 812
b6ffd97f
FR		 813 struct rtl_fw {
814 const struct firmware *fw;
1c361efb
FR		 815
816#define RTL_VER_SIZE 32
817
818 char version[RTL_VER_SIZE];
819
820 struct rtl_fw_phy_action {
821 __le32 *code;
822 size_t size;
823 } phy_action;
b6ffd97f 824 } *rtl_fw;
497888cf 825#define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
c558386b
HW		 826
827 u32 ocp_base;
1da177e4
LT		 828};
829
979b6c13 830MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 831MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 832module_param(use_dac, int, 0);
4300e8c7 833MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 834module_param_named(debug, debug.msg_enable, int, 0);
835MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 836MODULE_LICENSE("GPL");
837MODULE_VERSION(RTL8169_VERSION);
bca03d5f 838MODULE_FIRMWARE(FIRMWARE_8168D_1);
839MODULE_FIRMWARE(FIRMWARE_8168D_2);
01dc7fec 840MODULE_FIRMWARE(FIRMWARE_8168E_1);
841MODULE_FIRMWARE(FIRMWARE_8168E_2);
bbb8af75 842MODULE_FIRMWARE(FIRMWARE_8168E_3);
5a5e4443 843MODULE_FIRMWARE(FIRMWARE_8105E_1);
c2218925
HW		 844MODULE_FIRMWARE(FIRMWARE_8168F_1);
845MODULE_FIRMWARE(FIRMWARE_8168F_2);
7e18dca1 846MODULE_FIRMWARE(FIRMWARE_8402_1);
b3d7b2f2 847MODULE_FIRMWARE(FIRMWARE_8411_1);
45dd95c4 848MODULE_FIRMWARE(FIRMWARE_8411_2);
5598bfe5 849MODULE_FIRMWARE(FIRMWARE_8106E_1);
58152cd4 850MODULE_FIRMWARE(FIRMWARE_8106E_2);
beb330a4 851MODULE_FIRMWARE(FIRMWARE_8168G_2);
57538c4a 852MODULE_FIRMWARE(FIRMWARE_8168G_3);
6e1d0b89
CHL		 853MODULE_FIRMWARE(FIRMWARE_8168H_1);
854MODULE_FIRMWARE(FIRMWARE_8168H_2);
a3bf5c42
FR		 855MODULE_FIRMWARE(FIRMWARE_8107E_1);
856MODULE_FIRMWARE(FIRMWARE_8107E_2);
1da177e4 857
da78dbff
FR		 858static void rtl_lock_work(struct rtl8169_private *tp)
859{
860 mutex_lock(&tp->wk.mutex);
861}
862
863static void rtl_unlock_work(struct rtl8169_private *tp)
864{
865 mutex_unlock(&tp->wk.mutex);
866}
867
d58d46b5
FR		 868static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
869{
7d7903b2
JL		 870 pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
871 PCI_EXP_DEVCTL_READRQ, force);
d58d46b5
FR		 872}
873
ffc46952
FR		 874struct rtl_cond {
875 bool (*check)(struct rtl8169_private *);
876 const char *msg;
877};
878
879static void rtl_udelay(unsigned int d)
880{
881 udelay(d);
882}
883
884static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
885 void (*delay)(unsigned int), unsigned int d, int n,
886 bool high)
887{
888 int i;
889
890 for (i = 0; i < n; i++) {
891 delay(d);
892 if (c->check(tp) == high)
893 return true;
894 }
82e316ef
FR		 895 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
896 c->msg, !high, n, d);
ffc46952
FR		 897 return false;
898}
899
900static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
901 const struct rtl_cond *c,
902 unsigned int d, int n)
903{
904 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
905}
906
907static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
908 const struct rtl_cond *c,
909 unsigned int d, int n)
910{
911 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
912}
913
914static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
915 const struct rtl_cond *c,
916 unsigned int d, int n)
917{
918 return rtl_loop_wait(tp, c, msleep, d, n, true);
919}
920
921static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
922 const struct rtl_cond *c,
923 unsigned int d, int n)
924{
925 return rtl_loop_wait(tp, c, msleep, d, n, false);
926}
927
928#define DECLARE_RTL_COND(name) \
929static bool name ## _check(struct rtl8169_private *); \
930 \
931static const struct rtl_cond name = { \
932 .check = name ## _check, \
933 .msg = #name \
934}; \
935 \
936static bool name ## _check(struct rtl8169_private *tp)
937
938DECLARE_RTL_COND(rtl_ocpar_cond)
939{
940 void __iomem *ioaddr = tp->mmio_addr;
941
942 return RTL_R32(OCPAR) & OCPAR_FLAG;
943}
944
b646d900 945static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
946{
947 void __iomem *ioaddr = tp->mmio_addr;
b646d900 948
949 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
ffc46952
FR		 950
951 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
952 RTL_R32(OCPDR) : ~0;
b646d900 953}
954
955static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
956{
957 void __iomem *ioaddr = tp->mmio_addr;
b646d900 958
959 RTL_W32(OCPDR, data);
960 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
ffc46952
FR		 961
962 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
963}
964
965DECLARE_RTL_COND(rtl_eriar_cond)
966{
967 void __iomem *ioaddr = tp->mmio_addr;
968
969 return RTL_R32(ERIAR) & ERIAR_FLAG;
b646d900 970}
971
fac5b3ca 972static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
b646d900 973{
fac5b3ca 974 void __iomem *ioaddr = tp->mmio_addr;
b646d900 975
976 RTL_W8(ERIDR, cmd);
977 RTL_W32(ERIAR, 0x800010e8);
978 msleep(2);
ffc46952
FR		 979
980 if (!rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 5))
981 return;
b646d900 982
fac5b3ca 983 ocp_write(tp, 0x1, 0x30, 0x00000001);
b646d900 984}
985
986#define OOB_CMD_RESET 0x00
987#define OOB_CMD_DRIVER_START 0x05
988#define OOB_CMD_DRIVER_STOP 0x06
989
cecb5fd7
FR		 990static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
991{
992 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
993}
994
ffc46952 995DECLARE_RTL_COND(rtl_ocp_read_cond)
b646d900 996{
cecb5fd7 997 u16 reg;
b646d900 998
cecb5fd7 999 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 1000
ffc46952 1001 return ocp_read(tp, 0x0f, reg) & 0x00000800;
b646d900 1002}
1003
ffc46952 1004static void rtl8168_driver_start(struct rtl8169_private *tp)
b646d900 1005{
ffc46952 1006 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
b646d900 1007
ffc46952
FR		 1008 rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
1009}
b646d900 1010
ffc46952
FR		 1011static void rtl8168_driver_stop(struct rtl8169_private *tp)
1012{
1013 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
4804b3b3 1014
ffc46952 1015 rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
b646d900 1016}
1017
4804b3b3 1018static int r8168dp_check_dash(struct rtl8169_private *tp)
1019{
cecb5fd7 1020 u16 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 1021
cecb5fd7 1022 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
4804b3b3 1023}
b646d900 1024
c558386b
HW		 1025static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
1026{
1027 if (reg & 0xffff0001) {
1028 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
1029 return true;
1030 }
1031 return false;
1032}
1033
1034DECLARE_RTL_COND(rtl_ocp_gphy_cond)
1035{
1036 void __iomem *ioaddr = tp->mmio_addr;
1037
1038 return RTL_R32(GPHY_OCP) & OCPAR_FLAG;
1039}
1040
1041static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1042{
1043 void __iomem *ioaddr = tp->mmio_addr;
1044
1045 if (rtl_ocp_reg_failure(tp, reg))
1046 return;
1047
1048 RTL_W32(GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
1049
1050 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
1051}
1052
1053static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
1054{
1055 void __iomem *ioaddr = tp->mmio_addr;
1056
1057 if (rtl_ocp_reg_failure(tp, reg))
1058 return 0;
1059
1060 RTL_W32(GPHY_OCP, reg << 15);
1061
1062 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
1063 (RTL_R32(GPHY_OCP) & 0xffff) : ~0;
1064}
1065
c558386b
HW		 1066static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1067{
1068 void __iomem *ioaddr = tp->mmio_addr;
1069
1070 if (rtl_ocp_reg_failure(tp, reg))
1071 return;
1072
1073 RTL_W32(OCPDR, OCPAR_FLAG | (reg << 15) | data);
c558386b
HW		 1074}
1075
1076static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1077{
1078 void __iomem *ioaddr = tp->mmio_addr;
1079
1080 if (rtl_ocp_reg_failure(tp, reg))
1081 return 0;
1082
1083 RTL_W32(OCPDR, reg << 15);
1084
3a83ad12 1085 return RTL_R32(OCPDR);
c558386b
HW		 1086}
1087
1088#define OCP_STD_PHY_BASE 0xa400
1089
1090static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
1091{
1092 if (reg == 0x1f) {
1093 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
1094 return;
1095 }
1096
1097 if (tp->ocp_base != OCP_STD_PHY_BASE)
1098 reg -= 0x10;
1099
1100 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
1101}
1102
1103static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1104{
1105 if (tp->ocp_base != OCP_STD_PHY_BASE)
1106 reg -= 0x10;
1107
1108 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
1109}
1110
eee3786f 1111static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
1112{
1113 if (reg == 0x1f) {
1114 tp->ocp_base = value << 4;
1115 return;
1116 }
1117
1118 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
1119}
1120
1121static int mac_mcu_read(struct rtl8169_private *tp, int reg)
1122{
1123 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
1124}
1125
ffc46952
FR		 1126DECLARE_RTL_COND(rtl_phyar_cond)
1127{
1128 void __iomem *ioaddr = tp->mmio_addr;
1129
1130 return RTL_R32(PHYAR) & 0x80000000;
1131}
1132
24192210 1133static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1da177e4 1134{
24192210 1135 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 1136
24192210 1137 RTL_W32(PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1da177e4 1138
ffc46952 1139 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
024a07ba 1140 /*
81a95f04
TT		 1141 * According to hardware specs a 20us delay is required after write
1142 * complete indication, but before sending next command.
024a07ba 1143 */
81a95f04 1144 udelay(20);
1da177e4
LT		 1145}
1146
24192210 1147static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1da177e4 1148{
24192210 1149 void __iomem *ioaddr = tp->mmio_addr;
ffc46952 1150 int value;
1da177e4 1151
24192210 1152 RTL_W32(PHYAR, 0x0 | (reg & 0x1f) << 16);
1da177e4 1153
ffc46952
FR		 1154 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1155 RTL_R32(PHYAR) & 0xffff : ~0;
1156
81a95f04
TT		 1157 /*
1158 * According to hardware specs a 20us delay is required after read
1159 * complete indication, but before sending next command.
1160 */
1161 udelay(20);
1162
1da177e4
LT		 1163 return value;
1164}
1165
24192210 1166static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
c0e45c1c 1167{
24192210 1168 void __iomem *ioaddr = tp->mmio_addr;
c0e45c1c 1169
24192210 1170 RTL_W32(OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
c0e45c1c 1171 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
1172 RTL_W32(EPHY_RXER_NUM, 0);
1173
ffc46952 1174 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
c0e45c1c 1175}
1176
24192210 1177static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
c0e45c1c 1178{
24192210
FR		 1179 r8168dp_1_mdio_access(tp, reg,
1180 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
c0e45c1c 1181}
1182
24192210 1183static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
c0e45c1c 1184{
24192210 1185 void __iomem *ioaddr = tp->mmio_addr;
c0e45c1c 1186
24192210 1187 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
c0e45c1c 1188
1189 mdelay(1);
1190 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
1191 RTL_W32(EPHY_RXER_NUM, 0);
1192
ffc46952
FR		 1193 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1194 RTL_R32(OCPDR) & OCPDR_DATA_MASK : ~0;
c0e45c1c 1195}
1196
e6de30d6 1197#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1198
1199static void r8168dp_2_mdio_start(void __iomem *ioaddr)
1200{
1201 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1202}
1203
1204static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
1205{
1206 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1207}
1208
24192210 1209static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
e6de30d6 1210{
24192210
FR		 1211 void __iomem *ioaddr = tp->mmio_addr;
1212
e6de30d6 1213 r8168dp_2_mdio_start(ioaddr);
1214
24192210 1215 r8169_mdio_write(tp, reg, value);
e6de30d6 1216
1217 r8168dp_2_mdio_stop(ioaddr);
1218}
1219
24192210 1220static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
e6de30d6 1221{
24192210 1222 void __iomem *ioaddr = tp->mmio_addr;
e6de30d6 1223 int value;
1224
1225 r8168dp_2_mdio_start(ioaddr);
1226
24192210 1227 value = r8169_mdio_read(tp, reg);
e6de30d6 1228
1229 r8168dp_2_mdio_stop(ioaddr);
1230
1231 return value;
1232}
1233
4da19633 1234static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
dacf8154 1235{
24192210 1236 tp->mdio_ops.write(tp, location, val);
dacf8154
FR		 1237}
1238
4da19633 1239static int rtl_readphy(struct rtl8169_private *tp, int location)
1240{
24192210 1241 return tp->mdio_ops.read(tp, location);
4da19633 1242}
1243
1244static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1245{
1246 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1247}
1248
1249static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
daf9df6d 1250{
1251 int val;
1252
4da19633 1253 val = rtl_readphy(tp, reg_addr);
1254 rtl_writephy(tp, reg_addr, (val | p) & ~m);
daf9df6d 1255}
1256
ccdffb9a
FR		 1257static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1258 int val)
1259{
1260 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1261
4da19633 1262 rtl_writephy(tp, location, val);
ccdffb9a
FR		 1263}
1264
1265static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1266{
1267 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1268
4da19633 1269 return rtl_readphy(tp, location);
ccdffb9a
FR		 1270}
1271
ffc46952
FR		 1272DECLARE_RTL_COND(rtl_ephyar_cond)
1273{
1274 void __iomem *ioaddr = tp->mmio_addr;
1275
1276 return RTL_R32(EPHYAR) & EPHYAR_FLAG;
1277}
1278
fdf6fc06 1279static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
dacf8154 1280{
fdf6fc06 1281 void __iomem *ioaddr = tp->mmio_addr;
dacf8154
FR		 1282
1283 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1284 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1285
ffc46952
FR		 1286 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1287
1288 udelay(10);
dacf8154
FR		 1289}
1290
fdf6fc06 1291static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
dacf8154 1292{
fdf6fc06 1293 void __iomem *ioaddr = tp->mmio_addr;
dacf8154
FR		 1294
1295 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1296
ffc46952
FR		 1297 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1298 RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0;
dacf8154
FR		 1299}
1300
fdf6fc06
FR		 1301static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1302 u32 val, int type)
133ac40a 1303{
fdf6fc06 1304 void __iomem *ioaddr = tp->mmio_addr;
133ac40a
HW		 1305
1306 BUG_ON((addr & 3) || (mask == 0));
1307 RTL_W32(ERIDR, val);
1308 RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1309
ffc46952 1310 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
133ac40a
HW		 1311}
1312
fdf6fc06 1313static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
133ac40a 1314{
fdf6fc06 1315 void __iomem *ioaddr = tp->mmio_addr;
133ac40a
HW		 1316
1317 RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1318
ffc46952
FR		 1319 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1320 RTL_R32(ERIDR) : ~0;
133ac40a
HW		 1321}
1322
fdf6fc06
FR		 1323static void rtl_w1w0_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1324 u32 m, int type)
133ac40a
HW		 1325{
1326 u32 val;
1327
fdf6fc06
FR		 1328 val = rtl_eri_read(tp, addr, type);
1329 rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
133ac40a
HW		 1330}
1331
c28aa385 1332struct exgmac_reg {
1333 u16 addr;
1334 u16 mask;
1335 u32 val;
1336};
1337
fdf6fc06 1338static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
c28aa385 1339 const struct exgmac_reg *r, int len)
1340{
1341 while (len-- > 0) {
fdf6fc06 1342 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
c28aa385 1343 r++;
1344 }
1345}
1346
ffc46952
FR		 1347DECLARE_RTL_COND(rtl_efusear_cond)
1348{
1349 void __iomem *ioaddr = tp->mmio_addr;
1350
1351 return RTL_R32(EFUSEAR) & EFUSEAR_FLAG;
1352}
1353
fdf6fc06 1354static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
daf9df6d 1355{
fdf6fc06 1356 void __iomem *ioaddr = tp->mmio_addr;
daf9df6d 1357
1358 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1359
ffc46952
FR		 1360 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1361 RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
daf9df6d 1362}
1363
9085cdfa
FR		 1364static u16 rtl_get_events(struct rtl8169_private *tp)
1365{
1366 void __iomem *ioaddr = tp->mmio_addr;
1367
1368 return RTL_R16(IntrStatus);
1369}
1370
1371static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1372{
1373 void __iomem *ioaddr = tp->mmio_addr;
1374
1375 RTL_W16(IntrStatus, bits);
1376 mmiowb();
1377}
1378
1379static void rtl_irq_disable(struct rtl8169_private *tp)
1380{
1381 void __iomem *ioaddr = tp->mmio_addr;
1382
1383 RTL_W16(IntrMask, 0);
1384 mmiowb();
1385}
1386
3e990ff5
FR		 1387static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1388{
1389 void __iomem *ioaddr = tp->mmio_addr;
1390
1391 RTL_W16(IntrMask, bits);
1392}
1393
da78dbff
FR		 1394#define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1395#define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1396#define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1397
1398static void rtl_irq_enable_all(struct rtl8169_private *tp)
1399{
1400 rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1401}
1402
811fd301 1403static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1da177e4 1404{
811fd301 1405 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 1406
9085cdfa 1407 rtl_irq_disable(tp);
da78dbff 1408 rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
811fd301 1409 RTL_R8(ChipCmd);
1da177e4
LT		 1410}
1411
4da19633 1412static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1da177e4 1413{
4da19633 1414 void __iomem *ioaddr = tp->mmio_addr;
1415
1da177e4
LT		 1416 return RTL_R32(TBICSR) & TBIReset;
1417}
1418
4da19633 1419static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1da177e4 1420{
4da19633 1421 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 1422}
1423
1424static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1425{
1426 return RTL_R32(TBICSR) & TBILinkOk;
1427}
1428
1429static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1430{
1431 return RTL_R8(PHYstatus) & LinkStatus;
1432}
1433
4da19633 1434static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1da177e4 1435{
4da19633 1436 void __iomem *ioaddr = tp->mmio_addr;
1437
1da177e4
LT		 1438 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1439}
1440
4da19633 1441static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1da177e4
LT		 1442{
1443 unsigned int val;
1444
4da19633 1445 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1446 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1da177e4
LT		 1447}
1448
70090424
HW		 1449static void rtl_link_chg_patch(struct rtl8169_private *tp)
1450{
1451 void __iomem *ioaddr = tp->mmio_addr;
1452 struct net_device *dev = tp->dev;
1453
1454 if (!netif_running(dev))
1455 return;
1456
b3d7b2f2
HW		 1457 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1458 tp->mac_version == RTL_GIGA_MAC_VER_38) {
70090424 1459 if (RTL_R8(PHYstatus) & _1000bpsF) {
fdf6fc06
FR		 1460 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1461 ERIAR_EXGMAC);
1462 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1463 ERIAR_EXGMAC);
70090424 1464 } else if (RTL_R8(PHYstatus) & _100bps) {
fdf6fc06
FR		 1465 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1466 ERIAR_EXGMAC);
1467 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1468 ERIAR_EXGMAC);
70090424 1469 } else {
fdf6fc06
FR		 1470 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1471 ERIAR_EXGMAC);
1472 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1473 ERIAR_EXGMAC);
70090424
HW		 1474 }
1475 /* Reset packet filter */
fdf6fc06 1476 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
70090424 1477 ERIAR_EXGMAC);
fdf6fc06 1478 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
70090424 1479 ERIAR_EXGMAC);
c2218925
HW		 1480 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1481 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1482 if (RTL_R8(PHYstatus) & _1000bpsF) {
fdf6fc06
FR		 1483 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1484 ERIAR_EXGMAC);
1485 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1486 ERIAR_EXGMAC);
c2218925 1487 } else {
fdf6fc06
FR		 1488 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1489 ERIAR_EXGMAC);
1490 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1491 ERIAR_EXGMAC);
c2218925 1492 }
7e18dca1
HW		 1493 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1494 if (RTL_R8(PHYstatus) & _10bps) {
fdf6fc06
FR		 1495 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1496 ERIAR_EXGMAC);
1497 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1498 ERIAR_EXGMAC);
7e18dca1 1499 } else {
fdf6fc06
FR		 1500 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1501 ERIAR_EXGMAC);
7e18dca1 1502 }
70090424
HW		 1503 }
1504}
1505
e4fbce74 1506static void __rtl8169_check_link_status(struct net_device *dev,
cecb5fd7
FR		 1507 struct rtl8169_private *tp,
1508 void __iomem *ioaddr, bool pm)
1da177e4 1509{
1da177e4 1510 if (tp->link_ok(ioaddr)) {
70090424 1511 rtl_link_chg_patch(tp);
e1759441 1512 /* This is to cancel a scheduled suspend if there's one. */
e4fbce74
RW		 1513 if (pm)
1514 pm_request_resume(&tp->pci_dev->dev);
1da177e4 1515 netif_carrier_on(dev);
1519e57f
FR		 1516 if (net_ratelimit())
1517 netif_info(tp, ifup, dev, "link up\n");
b57b7e5a 1518 } else {
1da177e4 1519 netif_carrier_off(dev);
bf82c189 1520 netif_info(tp, ifdown, dev, "link down\n");
e4fbce74 1521 if (pm)
10953db8 1522 pm_schedule_suspend(&tp->pci_dev->dev, 5000);
b57b7e5a 1523 }
1da177e4
LT		 1524}
1525
e4fbce74
RW		 1526static void rtl8169_check_link_status(struct net_device *dev,
1527 struct rtl8169_private *tp,
1528 void __iomem *ioaddr)
1529{
1530 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1531}
1532
e1759441
RW		 1533#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1534
1535static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
61a4dcc2 1536{
61a4dcc2
FR		 1537 void __iomem *ioaddr = tp->mmio_addr;
1538 u8 options;
e1759441 1539 u32 wolopts = 0;
61a4dcc2
FR		 1540
1541 options = RTL_R8(Config1);
1542 if (!(options & PMEnable))
e1759441 1543 return 0;
61a4dcc2
FR		 1544
1545 options = RTL_R8(Config3);
1546 if (options & LinkUp)
e1759441 1547 wolopts |= WAKE_PHY;
6e1d0b89 1548 switch (tp->mac_version) {
ac85bcdb
CHL		 1549 case RTL_GIGA_MAC_VER_34:
1550 case RTL_GIGA_MAC_VER_35:
1551 case RTL_GIGA_MAC_VER_36:
1552 case RTL_GIGA_MAC_VER_37:
1553 case RTL_GIGA_MAC_VER_38:
1554 case RTL_GIGA_MAC_VER_40:
1555 case RTL_GIGA_MAC_VER_41:
1556 case RTL_GIGA_MAC_VER_42:
1557 case RTL_GIGA_MAC_VER_43:
1558 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 1559 case RTL_GIGA_MAC_VER_45:
1560 case RTL_GIGA_MAC_VER_46:
ac85bcdb
CHL		 1561 case RTL_GIGA_MAC_VER_47:
1562 case RTL_GIGA_MAC_VER_48:
6e1d0b89
CHL		 1563 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
1564 wolopts |= WAKE_MAGIC;
1565 break;
1566 default:
1567 if (options & MagicPacket)
1568 wolopts |= WAKE_MAGIC;
1569 break;
1570 }
61a4dcc2
FR		 1571
1572 options = RTL_R8(Config5);
1573 if (options & UWF)
e1759441 1574 wolopts |= WAKE_UCAST;
61a4dcc2 1575 if (options & BWF)
e1759441 1576 wolopts |= WAKE_BCAST;
61a4dcc2 1577 if (options & MWF)
e1759441 1578 wolopts |= WAKE_MCAST;
61a4dcc2 1579
e1759441 1580 return wolopts;
61a4dcc2
FR		 1581}
1582
e1759441 1583static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
61a4dcc2
FR		 1584{
1585 struct rtl8169_private *tp = netdev_priv(dev);
e1759441 1586
da78dbff 1587 rtl_lock_work(tp);
e1759441
RW		 1588
1589 wol->supported = WAKE_ANY;
1590 wol->wolopts = __rtl8169_get_wol(tp);
1591
da78dbff 1592 rtl_unlock_work(tp);
e1759441
RW		 1593}
1594
1595static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1596{
61a4dcc2 1597 void __iomem *ioaddr = tp->mmio_addr;
6e1d0b89 1598 unsigned int i, tmp;
350f7596 1599 static const struct {
61a4dcc2
FR		 1600 u32 opt;
1601 u16 reg;
1602 u8 mask;
1603 } cfg[] = {
61a4dcc2 1604 { WAKE_PHY, Config3, LinkUp },
61a4dcc2
FR		 1605 { WAKE_UCAST, Config5, UWF },
1606 { WAKE_BCAST, Config5, BWF },
1607 { WAKE_MCAST, Config5, MWF },
6e1d0b89
CHL		 1608 { WAKE_ANY, Config5, LanWake },
1609 { WAKE_MAGIC, Config3, MagicPacket }
61a4dcc2 1610 };
851e6022 1611 u8 options;
61a4dcc2 1612
61a4dcc2
FR		 1613 RTL_W8(Cfg9346, Cfg9346_Unlock);
1614
6e1d0b89 1615 switch (tp->mac_version) {
ac85bcdb
CHL		 1616 case RTL_GIGA_MAC_VER_34:
1617 case RTL_GIGA_MAC_VER_35:
1618 case RTL_GIGA_MAC_VER_36:
1619 case RTL_GIGA_MAC_VER_37:
1620 case RTL_GIGA_MAC_VER_38:
1621 case RTL_GIGA_MAC_VER_40:
1622 case RTL_GIGA_MAC_VER_41:
1623 case RTL_GIGA_MAC_VER_42:
1624 case RTL_GIGA_MAC_VER_43:
1625 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 1626 case RTL_GIGA_MAC_VER_45:
1627 case RTL_GIGA_MAC_VER_46:
ac85bcdb
CHL		 1628 case RTL_GIGA_MAC_VER_47:
1629 case RTL_GIGA_MAC_VER_48:
6e1d0b89
CHL		 1630 tmp = ARRAY_SIZE(cfg) - 1;
1631 if (wolopts & WAKE_MAGIC)
1632 rtl_w1w0_eri(tp,
1633 0x0dc,
1634 ERIAR_MASK_0100,
1635 MagicPacket_v2,
1636 0x0000,
1637 ERIAR_EXGMAC);
1638 else
1639 rtl_w1w0_eri(tp,
1640 0x0dc,
1641 ERIAR_MASK_0100,
1642 0x0000,
1643 MagicPacket_v2,
1644 ERIAR_EXGMAC);
1645 break;
1646 default:
1647 tmp = ARRAY_SIZE(cfg);
1648 break;
1649 }
1650
1651 for (i = 0; i < tmp; i++) {
851e6022 1652 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
e1759441 1653 if (wolopts & cfg[i].opt)
61a4dcc2
FR		 1654 options |= cfg[i].mask;
1655 RTL_W8(cfg[i].reg, options);
1656 }
1657
851e6022
FR		 1658 switch (tp->mac_version) {
1659 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1660 options = RTL_R8(Config1) & ~PMEnable;
1661 if (wolopts)
1662 options |= PMEnable;
1663 RTL_W8(Config1, options);
1664 break;
1665 default:
d387b427
FR		 1666 options = RTL_R8(Config2) & ~PME_SIGNAL;
1667 if (wolopts)
1668 options |= PME_SIGNAL;
1669 RTL_W8(Config2, options);
851e6022
FR		 1670 break;
1671 }
1672
61a4dcc2 1673 RTL_W8(Cfg9346, Cfg9346_Lock);
e1759441
RW		 1674}
1675
1676static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1677{
1678 struct rtl8169_private *tp = netdev_priv(dev);
1679
da78dbff 1680 rtl_lock_work(tp);
61a4dcc2 1681
f23e7fda
FR		 1682 if (wol->wolopts)
1683 tp->features |= RTL_FEATURE_WOL;
1684 else
1685 tp->features &= ~RTL_FEATURE_WOL;
e1759441 1686 __rtl8169_set_wol(tp, wol->wolopts);
da78dbff
FR		 1687
1688 rtl_unlock_work(tp);
61a4dcc2 1689
ea80907f 1690 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1691
61a4dcc2
FR		 1692 return 0;
1693}
1694
31bd204f
FR		 1695static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1696{
85bffe6c 1697 return rtl_chip_infos[tp->mac_version].fw_name;
31bd204f
FR		 1698}
1699
1da177e4
LT		 1700static void rtl8169_get_drvinfo(struct net_device *dev,
1701 struct ethtool_drvinfo *info)
1702{
1703 struct rtl8169_private *tp = netdev_priv(dev);
b6ffd97f 1704 struct rtl_fw *rtl_fw = tp->rtl_fw;
1da177e4 1705
68aad78c
RJ		 1706 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1707 strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1708 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1c361efb 1709 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
8ac72d16
RJ		 1710 if (!IS_ERR_OR_NULL(rtl_fw))
1711 strlcpy(info->fw_version, rtl_fw->version,
1712 sizeof(info->fw_version));
1da177e4
LT		 1713}
1714
1715static int rtl8169_get_regs_len(struct net_device *dev)
1716{
1717 return R8169_REGS_SIZE;
1718}
1719
1720static int rtl8169_set_speed_tbi(struct net_device *dev,
54405cde 1721 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1da177e4
LT		 1722{
1723 struct rtl8169_private *tp = netdev_priv(dev);
1724 void __iomem *ioaddr = tp->mmio_addr;
1725 int ret = 0;
1726 u32 reg;
1727
1728 reg = RTL_R32(TBICSR);
1729 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1730 (duplex == DUPLEX_FULL)) {
1731 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1732 } else if (autoneg == AUTONEG_ENABLE)
1733 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1734 else {
bf82c189
JP		 1735 netif_warn(tp, link, dev,
1736 "incorrect speed setting refused in TBI mode\n");
1da177e4
LT		 1737 ret = -EOPNOTSUPP;
1738 }
1739
1740 return ret;
1741}
1742
1743static int rtl8169_set_speed_xmii(struct net_device *dev,
54405cde 1744 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1da177e4
LT		 1745{
1746 struct rtl8169_private *tp = netdev_priv(dev);
3577aa1b 1747 int giga_ctrl, bmcr;
54405cde 1748 int rc = -EINVAL;
1da177e4 1749
716b50a3 1750 rtl_writephy(tp, 0x1f, 0x0000);
1da177e4
LT		 1751
1752 if (autoneg == AUTONEG_ENABLE) {
3577aa1b 1753 int auto_nego;
1754
4da19633 1755 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
54405cde
ON		 1756 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1757 ADVERTISE_100HALF | ADVERTISE_100FULL);
1758
1759 if (adv & ADVERTISED_10baseT_Half)
1760 auto_nego |= ADVERTISE_10HALF;
1761 if (adv & ADVERTISED_10baseT_Full)
1762 auto_nego |= ADVERTISE_10FULL;
1763 if (adv & ADVERTISED_100baseT_Half)
1764 auto_nego |= ADVERTISE_100HALF;
1765 if (adv & ADVERTISED_100baseT_Full)
1766 auto_nego |= ADVERTISE_100FULL;
1767
3577aa1b 1768 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1da177e4 1769
4da19633 1770 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
3577aa1b 1771 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
bcf0bf90 1772
3577aa1b 1773 /* The 8100e/8101e/8102e do Fast Ethernet only. */
826e6cbd 1774 if (tp->mii.supports_gmii) {
54405cde
ON		 1775 if (adv & ADVERTISED_1000baseT_Half)
1776 giga_ctrl |= ADVERTISE_1000HALF;
1777 if (adv & ADVERTISED_1000baseT_Full)
1778 giga_ctrl |= ADVERTISE_1000FULL;
1779 } else if (adv & (ADVERTISED_1000baseT_Half |
1780 ADVERTISED_1000baseT_Full)) {
bf82c189
JP		 1781 netif_info(tp, link, dev,
1782 "PHY does not support 1000Mbps\n");
54405cde 1783 goto out;
bcf0bf90 1784 }
1da177e4 1785
3577aa1b 1786 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1787
4da19633 1788 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1789 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
3577aa1b 1790 } else {
1791 giga_ctrl = 0;
1792
1793 if (speed == SPEED_10)
1794 bmcr = 0;
1795 else if (speed == SPEED_100)
1796 bmcr = BMCR_SPEED100;
1797 else
54405cde 1798 goto out;
3577aa1b 1799
1800 if (duplex == DUPLEX_FULL)
1801 bmcr |= BMCR_FULLDPLX;
2584fbc3
RS		 1802 }
1803
4da19633 1804 rtl_writephy(tp, MII_BMCR, bmcr);
3577aa1b 1805
cecb5fd7
FR		 1806 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1807 tp->mac_version == RTL_GIGA_MAC_VER_03) {
3577aa1b 1808 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
4da19633 1809 rtl_writephy(tp, 0x17, 0x2138);
1810 rtl_writephy(tp, 0x0e, 0x0260);
3577aa1b 1811 } else {
4da19633 1812 rtl_writephy(tp, 0x17, 0x2108);
1813 rtl_writephy(tp, 0x0e, 0x0000);
3577aa1b 1814 }
1815 }
1816
54405cde
ON		 1817 rc = 0;
1818out:
1819 return rc;
1da177e4
LT		 1820}
1821
1822static int rtl8169_set_speed(struct net_device *dev,
54405cde 1823 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1da177e4
LT		 1824{
1825 struct rtl8169_private *tp = netdev_priv(dev);
1826 int ret;
1827
54405cde 1828 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
4876cc1e
FR		 1829 if (ret < 0)
1830 goto out;
1da177e4 1831
4876cc1e
FR		 1832 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1833 (advertising & ADVERTISED_1000baseT_Full)) {
1da177e4 1834 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
4876cc1e
FR		 1835 }
1836out:
1da177e4
LT		 1837 return ret;
1838}
1839
1840static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1841{
1842 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4
LT		 1843 int ret;
1844
4876cc1e
FR		 1845 del_timer_sync(&tp->timer);
1846
da78dbff 1847 rtl_lock_work(tp);
cecb5fd7 1848 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
25db0338 1849 cmd->duplex, cmd->advertising);
da78dbff 1850 rtl_unlock_work(tp);
5b0384f4 1851
1da177e4
LT		 1852 return ret;
1853}
1854
c8f44aff
MM		 1855static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1856 netdev_features_t features)
1da177e4 1857{
d58d46b5
FR		 1858 struct rtl8169_private *tp = netdev_priv(dev);
1859
2b7b4318 1860 if (dev->mtu > TD_MSS_MAX)
350fb32a 1861 features &= ~NETIF_F_ALL_TSO;
1da177e4 1862
d58d46b5
FR		 1863 if (dev->mtu > JUMBO_1K &&
1864 !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1865 features &= ~NETIF_F_IP_CSUM;
1866
350fb32a 1867 return features;
1da177e4
LT		 1868}
1869
da78dbff
FR		 1870static void __rtl8169_set_features(struct net_device *dev,
1871 netdev_features_t features)
1da177e4
LT		 1872{
1873 struct rtl8169_private *tp = netdev_priv(dev);
da78dbff 1874 void __iomem *ioaddr = tp->mmio_addr;
929a031d 1875 u32 rx_config;
1da177e4 1876
929a031d 1877 rx_config = RTL_R32(RxConfig);
1878 if (features & NETIF_F_RXALL)
1879 rx_config |= (AcceptErr | AcceptRunt);
1880 else
1881 rx_config &= ~(AcceptErr | AcceptRunt);
1da177e4 1882
929a031d 1883 RTL_W32(RxConfig, rx_config);
350fb32a 1884
929a031d 1885 if (features & NETIF_F_RXCSUM)
1886 tp->cp_cmd |= RxChkSum;
1887 else
1888 tp->cp_cmd &= ~RxChkSum;
6bbe021d 1889
929a031d 1890 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1891 tp->cp_cmd |= RxVlan;
1892 else
1893 tp->cp_cmd &= ~RxVlan;
1894
1895 tp->cp_cmd |= RTL_R16(CPlusCmd) & ~(RxVlan | RxChkSum);
1896
1897 RTL_W16(CPlusCmd, tp->cp_cmd);
1898 RTL_R16(CPlusCmd);
da78dbff 1899}
1da177e4 1900
da78dbff
FR		 1901static int rtl8169_set_features(struct net_device *dev,
1902 netdev_features_t features)
1903{
1904 struct rtl8169_private *tp = netdev_priv(dev);
1905
929a031d 1906 features &= NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX;
1907
da78dbff 1908 rtl_lock_work(tp);
85911d71 1909 if (features ^ dev->features)
929a031d 1910 __rtl8169_set_features(dev, features);
da78dbff 1911 rtl_unlock_work(tp);
1da177e4
LT		 1912
1913 return 0;
1914}
1915
da78dbff 1916
810f4893 1917static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1da177e4 1918{
eab6d18d 1919 return (vlan_tx_tag_present(skb)) ?
1da177e4
LT		 1920 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1921}
1922
7a8fc77b 1923static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1da177e4
LT		 1924{
1925 u32 opts2 = le32_to_cpu(desc->opts2);
1da177e4 1926
7a8fc77b 1927 if (opts2 & RxVlanTag)
86a9bad3 1928 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1da177e4
LT		 1929}
1930
ccdffb9a 1931static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1932{
1933 struct rtl8169_private *tp = netdev_priv(dev);
1934 void __iomem *ioaddr = tp->mmio_addr;
1935 u32 status;
1936
1937 cmd->supported =
1938 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1939 cmd->port = PORT_FIBRE;
1940 cmd->transceiver = XCVR_INTERNAL;
1941
1942 status = RTL_R32(TBICSR);
1943 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1944 cmd->autoneg = !!(status & TBINwEnable);
1945
70739497 1946 ethtool_cmd_speed_set(cmd, SPEED_1000);
1da177e4 1947 cmd->duplex = DUPLEX_FULL; /* Always set */
ccdffb9a
FR		 1948
1949 return 0;
1da177e4
LT		 1950}
1951
ccdffb9a 1952static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1953{
1954 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a
FR		 1955
1956 return mii_ethtool_gset(&tp->mii, cmd);
1da177e4
LT		 1957}
1958
1959static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1960{
1961 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1962 int rc;
1da177e4 1963
da78dbff 1964 rtl_lock_work(tp);
ccdffb9a 1965 rc = tp->get_settings(dev, cmd);
da78dbff 1966 rtl_unlock_work(tp);
1da177e4 1967
ccdffb9a 1968 return rc;
1da177e4
LT		 1969}
1970
1971static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1972 void *p)
1973{
5b0384f4 1974 struct rtl8169_private *tp = netdev_priv(dev);
15edae91
PW		 1975 u32 __iomem *data = tp->mmio_addr;
1976 u32 *dw = p;
1977 int i;
1da177e4 1978
da78dbff 1979 rtl_lock_work(tp);
15edae91
PW		 1980 for (i = 0; i < R8169_REGS_SIZE; i += 4)
1981 memcpy_fromio(dw++, data++, 4);
da78dbff 1982 rtl_unlock_work(tp);
1da177e4
LT		 1983}
1984
b57b7e5a
SH		 1985static u32 rtl8169_get_msglevel(struct net_device *dev)
1986{
1987 struct rtl8169_private *tp = netdev_priv(dev);
1988
1989 return tp->msg_enable;
1990}
1991
1992static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1993{
1994 struct rtl8169_private *tp = netdev_priv(dev);
1995
1996 tp->msg_enable = value;
1997}
1998
d4a3a0fc
SH		 1999static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
2000 "tx_packets",
2001 "rx_packets",
2002 "tx_errors",
2003 "rx_errors",
2004 "rx_missed",
2005 "align_errors",
2006 "tx_single_collisions",
2007 "tx_multi_collisions",
2008 "unicast",
2009 "broadcast",
2010 "multicast",
2011 "tx_aborted",
2012 "tx_underrun",
2013};
2014
b9f2c044 2015static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 2016{
b9f2c044
JG		 2017 switch (sset) {
2018 case ETH_SS_STATS:
2019 return ARRAY_SIZE(rtl8169_gstrings);
2020 default:
2021 return -EOPNOTSUPP;
2022 }
d4a3a0fc
SH		 2023}
2024
ffc46952
FR		 2025DECLARE_RTL_COND(rtl_counters_cond)
2026{
2027 void __iomem *ioaddr = tp->mmio_addr;
2028
2029 return RTL_R32(CounterAddrLow) & CounterDump;
2030}
2031
355423d0 2032static void rtl8169_update_counters(struct net_device *dev)
d4a3a0fc
SH		 2033{
2034 struct rtl8169_private *tp = netdev_priv(dev);
2035 void __iomem *ioaddr = tp->mmio_addr;
cecb5fd7 2036 struct device *d = &tp->pci_dev->dev;
d4a3a0fc
SH		 2037 struct rtl8169_counters *counters;
2038 dma_addr_t paddr;
2039 u32 cmd;
2040
355423d0
IV		 2041 /*
2042 * Some chips are unable to dump tally counters when the receiver
2043 * is disabled.
2044 */
2045 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
2046 return;
d4a3a0fc 2047
48addcc9 2048 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
d4a3a0fc
SH		 2049 if (!counters)
2050 return;
2051
2052 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
284901a9 2053 cmd = (u64)paddr & DMA_BIT_MASK(32);
d4a3a0fc
SH		 2054 RTL_W32(CounterAddrLow, cmd);
2055 RTL_W32(CounterAddrLow, cmd | CounterDump);
2056
ffc46952
FR		 2057 if (rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000))
2058 memcpy(&tp->counters, counters, sizeof(*counters));
d4a3a0fc
SH		 2059
2060 RTL_W32(CounterAddrLow, 0);
2061 RTL_W32(CounterAddrHigh, 0);
2062
48addcc9 2063 dma_free_coherent(d, sizeof(*counters), counters, paddr);
d4a3a0fc
SH		 2064}
2065
355423d0
IV		 2066static void rtl8169_get_ethtool_stats(struct net_device *dev,
2067 struct ethtool_stats *stats, u64 *data)
2068{
2069 struct rtl8169_private *tp = netdev_priv(dev);
2070
2071 ASSERT_RTNL();
2072
2073 rtl8169_update_counters(dev);
2074
2075 data[0] = le64_to_cpu(tp->counters.tx_packets);
2076 data[1] = le64_to_cpu(tp->counters.rx_packets);
2077 data[2] = le64_to_cpu(tp->counters.tx_errors);
2078 data[3] = le32_to_cpu(tp->counters.rx_errors);
2079 data[4] = le16_to_cpu(tp->counters.rx_missed);
2080 data[5] = le16_to_cpu(tp->counters.align_errors);
2081 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
2082 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
2083 data[8] = le64_to_cpu(tp->counters.rx_unicast);
2084 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
2085 data[10] = le32_to_cpu(tp->counters.rx_multicast);
2086 data[11] = le16_to_cpu(tp->counters.tx_aborted);
2087 data[12] = le16_to_cpu(tp->counters.tx_underun);
2088}
2089
d4a3a0fc
SH		 2090static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2091{
2092 switch(stringset) {
2093 case ETH_SS_STATS:
2094 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
2095 break;
2096 }
2097}
2098
7282d491 2099static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 2100 .get_drvinfo = rtl8169_get_drvinfo,
2101 .get_regs_len = rtl8169_get_regs_len,
2102 .get_link = ethtool_op_get_link,
2103 .get_settings = rtl8169_get_settings,
2104 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 2105 .get_msglevel = rtl8169_get_msglevel,
2106 .set_msglevel = rtl8169_set_msglevel,
1da177e4 2107 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 2108 .get_wol = rtl8169_get_wol,
2109 .set_wol = rtl8169_set_wol,
d4a3a0fc 2110 .get_strings = rtl8169_get_strings,
b9f2c044 2111 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 2112 .get_ethtool_stats = rtl8169_get_ethtool_stats,
e1593bb1 2113 .get_ts_info = ethtool_op_get_ts_info,
1da177e4
LT		 2114};
2115
07d3f51f 2116static void rtl8169_get_mac_version(struct rtl8169_private *tp,
5d320a20 2117 struct net_device *dev, u8 default_version)
1da177e4 2118{
5d320a20 2119 void __iomem *ioaddr = tp->mmio_addr;
0e485150
FR		 2120 /*
2121 * The driver currently handles the 8168Bf and the 8168Be identically
2122 * but they can be identified more specifically through the test below
2123 * if needed:
2124 *
2125 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 2126 *
2127 * Same thing for the 8101Eb and the 8101Ec:
2128 *
2129 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 2130 */
3744100e 2131 static const struct rtl_mac_info {
1da177e4 2132 u32 mask;
e3cf0cc0 2133 u32 val;
1da177e4
LT		 2134 int mac_version;
2135 } mac_info[] = {
6e1d0b89
CHL		 2136 /* 8168H family. */
2137 { 0x7cf00000, 0x54100000, RTL_GIGA_MAC_VER_46 },
2138 { 0x7cf00000, 0x54000000, RTL_GIGA_MAC_VER_45 },
2139
c558386b 2140 /* 8168G family. */
45dd95c4 2141 { 0x7cf00000, 0x5c800000, RTL_GIGA_MAC_VER_44 },
57538c4a 2142 { 0x7cf00000, 0x50900000, RTL_GIGA_MAC_VER_42 },
c558386b
HW		 2143 { 0x7cf00000, 0x4c100000, RTL_GIGA_MAC_VER_41 },
2144 { 0x7cf00000, 0x4c000000, RTL_GIGA_MAC_VER_40 },
2145
c2218925 2146 /* 8168F family. */
b3d7b2f2 2147 { 0x7c800000, 0x48800000, RTL_GIGA_MAC_VER_38 },
c2218925
HW		 2148 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
2149 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
2150
01dc7fec 2151 /* 8168E family. */
70090424 2152 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
01dc7fec 2153 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
2154 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
2155 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
2156
5b538df9 2157 /* 8168D family. */
daf9df6d 2158 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
2159 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
daf9df6d 2160 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
5b538df9 2161
e6de30d6 2162 /* 8168DP family. */
2163 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
2164 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
4804b3b3 2165 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
e6de30d6 2166
ef808d50 2167 /* 8168C family. */
17c99297 2168 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
ef3386f0 2169 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 2170 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 2171 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 2172 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
2173 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 2174 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
6fb07058 2175 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
ef808d50 2176 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 2177
2178 /* 8168B family. */
2179 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
2180 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
2181 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
2182 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
2183
2184 /* 8101 family. */
5598bfe5
HW		 2185 { 0x7cf00000, 0x44900000, RTL_GIGA_MAC_VER_39 },
2186 { 0x7c800000, 0x44800000, RTL_GIGA_MAC_VER_39 },
7e18dca1 2187 { 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37 },
36a0e6c2 2188 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
5a5e4443
HW		 2189 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
2190 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
2191 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2857ffb7
FR		 2192 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
2193 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
2194 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
2195 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
2196 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
2197 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 2198 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 2199 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 2200 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 2201 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
2202 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 2203 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
2204 /* FIXME: where did these entries come from ? -- FR */
2205 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
2206 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
2207
2208 /* 8110 family. */
2209 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
2210 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
2211 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
2212 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
2213 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
2214 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
2215
f21b75e9
JD		 2216 /* Catch-all */
2217 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
3744100e
FR		 2218 };
2219 const struct rtl_mac_info *p = mac_info;
1da177e4
LT		 2220 u32 reg;
2221
e3cf0cc0
FR		 2222 reg = RTL_R32(TxConfig);
2223 while ((reg & p->mask) != p->val)
1da177e4
LT		 2224 p++;
2225 tp->mac_version = p->mac_version;
5d320a20
FR		 2226
2227 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2228 netif_notice(tp, probe, dev,
2229 "unknown MAC, using family default\n");
2230 tp->mac_version = default_version;
58152cd4 2231 } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
2232 tp->mac_version = tp->mii.supports_gmii ?
2233 RTL_GIGA_MAC_VER_42 :
2234 RTL_GIGA_MAC_VER_43;
6e1d0b89
CHL		 2235 } else if (tp->mac_version == RTL_GIGA_MAC_VER_45) {
2236 tp->mac_version = tp->mii.supports_gmii ?
2237 RTL_GIGA_MAC_VER_45 :
2238 RTL_GIGA_MAC_VER_47;
2239 } else if (tp->mac_version == RTL_GIGA_MAC_VER_46) {
2240 tp->mac_version = tp->mii.supports_gmii ?
2241 RTL_GIGA_MAC_VER_46 :
2242 RTL_GIGA_MAC_VER_48;
5d320a20 2243 }
1da177e4
LT		 2244}
2245
2246static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2247{
bcf0bf90 2248 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 2249}
2250
867763c1
FR		 2251struct phy_reg {
2252 u16 reg;
2253 u16 val;
2254};
2255
4da19633 2256static void rtl_writephy_batch(struct rtl8169_private *tp,
2257 const struct phy_reg *regs, int len)
867763c1
FR		 2258{
2259 while (len-- > 0) {
4da19633 2260 rtl_writephy(tp, regs->reg, regs->val);
867763c1
FR		 2261 regs++;
2262 }
2263}
2264
bca03d5f 2265#define PHY_READ 0x00000000
2266#define PHY_DATA_OR 0x10000000
2267#define PHY_DATA_AND 0x20000000
2268#define PHY_BJMPN 0x30000000
eee3786f 2269#define PHY_MDIO_CHG 0x40000000
bca03d5f 2270#define PHY_CLEAR_READCOUNT 0x70000000
2271#define PHY_WRITE 0x80000000
2272#define PHY_READCOUNT_EQ_SKIP 0x90000000
2273#define PHY_COMP_EQ_SKIPN 0xa0000000
2274#define PHY_COMP_NEQ_SKIPN 0xb0000000
2275#define PHY_WRITE_PREVIOUS 0xc0000000
2276#define PHY_SKIPN 0xd0000000
2277#define PHY_DELAY_MS 0xe0000000
bca03d5f 2278
960aee6c
HW		 2279struct fw_info {
2280 u32 magic;
2281 char version[RTL_VER_SIZE];
2282 __le32 fw_start;
2283 __le32 fw_len;
2284 u8 chksum;
2285} __packed;
2286
1c361efb
FR		 2287#define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2288
2289static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
bca03d5f 2290{
b6ffd97f 2291 const struct firmware *fw = rtl_fw->fw;
960aee6c 2292 struct fw_info *fw_info = (struct fw_info *)fw->data;
1c361efb
FR		 2293 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2294 char *version = rtl_fw->version;
2295 bool rc = false;
2296
2297 if (fw->size < FW_OPCODE_SIZE)
2298 goto out;
960aee6c
HW		 2299
2300 if (!fw_info->magic) {
2301 size_t i, size, start;
2302 u8 checksum = 0;
2303
2304 if (fw->size < sizeof(*fw_info))
2305 goto out;
2306
2307 for (i = 0; i < fw->size; i++)
2308 checksum += fw->data[i];
2309 if (checksum != 0)
2310 goto out;
2311
2312 start = le32_to_cpu(fw_info->fw_start);
2313 if (start > fw->size)
2314 goto out;
2315
2316 size = le32_to_cpu(fw_info->fw_len);
2317 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2318 goto out;
2319
2320 memcpy(version, fw_info->version, RTL_VER_SIZE);
2321
2322 pa->code = (__le32 *)(fw->data + start);
2323 pa->size = size;
2324 } else {
1c361efb
FR		 2325 if (fw->size % FW_OPCODE_SIZE)
2326 goto out;
2327
2328 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2329
2330 pa->code = (__le32 *)fw->data;
2331 pa->size = fw->size / FW_OPCODE_SIZE;
2332 }
2333 version[RTL_VER_SIZE - 1] = 0;
2334
2335 rc = true;
2336out:
2337 return rc;
2338}
2339
fd112f2e
FR		 2340static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2341 struct rtl_fw_phy_action *pa)
1c361efb 2342{
fd112f2e 2343 bool rc = false;
1c361efb 2344 size_t index;
bca03d5f 2345
1c361efb
FR		 2346 for (index = 0; index < pa->size; index++) {
2347 u32 action = le32_to_cpu(pa->code[index]);
42b82dc1 2348 u32 regno = (action & 0x0fff0000) >> 16;
bca03d5f 2349
42b82dc1 2350 switch(action & 0xf0000000) {
2351 case PHY_READ:
2352 case PHY_DATA_OR:
2353 case PHY_DATA_AND:
eee3786f 2354 case PHY_MDIO_CHG:
42b82dc1 2355 case PHY_CLEAR_READCOUNT:
2356 case PHY_WRITE:
2357 case PHY_WRITE_PREVIOUS:
2358 case PHY_DELAY_MS:
2359 break;
2360
2361 case PHY_BJMPN:
2362 if (regno > index) {
fd112f2e 2363 netif_err(tp, ifup, tp->dev,
cecb5fd7 2364 "Out of range of firmware\n");
fd112f2e 2365 goto out;
42b82dc1 2366 }
2367 break;
2368 case PHY_READCOUNT_EQ_SKIP:
1c361efb 2369 if (index + 2 >= pa->size) {
fd112f2e 2370 netif_err(tp, ifup, tp->dev,
cecb5fd7 2371 "Out of range of firmware\n");
fd112f2e 2372 goto out;
42b82dc1 2373 }
2374 break;
2375 case PHY_COMP_EQ_SKIPN:
2376 case PHY_COMP_NEQ_SKIPN:
2377 case PHY_SKIPN:
1c361efb 2378 if (index + 1 + regno >= pa->size) {
fd112f2e 2379 netif_err(tp, ifup, tp->dev,
cecb5fd7 2380 "Out of range of firmware\n");
fd112f2e 2381 goto out;
42b82dc1 2382 }
bca03d5f 2383 break;
2384
42b82dc1 2385 default:
fd112f2e 2386 netif_err(tp, ifup, tp->dev,
42b82dc1 2387 "Invalid action 0x%08x\n", action);
fd112f2e 2388 goto out;
bca03d5f 2389 }
2390 }
fd112f2e
FR		 2391 rc = true;
2392out:
2393 return rc;
2394}
bca03d5f 2395
fd112f2e
FR		 2396static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2397{
2398 struct net_device *dev = tp->dev;
2399 int rc = -EINVAL;
2400
2401 if (!rtl_fw_format_ok(tp, rtl_fw)) {
2402 netif_err(tp, ifup, dev, "invalid firwmare\n");
2403 goto out;
2404 }
2405
2406 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2407 rc = 0;
2408out:
2409 return rc;
2410}
2411
2412static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2413{
2414 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
eee3786f 2415 struct mdio_ops org, *ops = &tp->mdio_ops;
fd112f2e
FR		 2416 u32 predata, count;
2417 size_t index;
2418
2419 predata = count = 0;
eee3786f 2420 org.write = ops->write;
2421 org.read = ops->read;
42b82dc1 2422
1c361efb
FR		 2423 for (index = 0; index < pa->size; ) {
2424 u32 action = le32_to_cpu(pa->code[index]);
bca03d5f 2425 u32 data = action & 0x0000ffff;
42b82dc1 2426 u32 regno = (action & 0x0fff0000) >> 16;
2427
2428 if (!action)
2429 break;
bca03d5f 2430
2431 switch(action & 0xf0000000) {
42b82dc1 2432 case PHY_READ:
2433 predata = rtl_readphy(tp, regno);
2434 count++;
2435 index++;
2436 break;
2437 case PHY_DATA_OR:
2438 predata |= data;
2439 index++;
2440 break;
2441 case PHY_DATA_AND:
2442 predata &= data;
2443 index++;
2444 break;
2445 case PHY_BJMPN:
2446 index -= regno;
2447 break;
eee3786f 2448 case PHY_MDIO_CHG:
2449 if (data == 0) {
2450 ops->write = org.write;
2451 ops->read = org.read;
2452 } else if (data == 1) {
2453 ops->write = mac_mcu_write;
2454 ops->read = mac_mcu_read;
2455 }
2456
42b82dc1 2457 index++;
2458 break;
2459 case PHY_CLEAR_READCOUNT:
2460 count = 0;
2461 index++;
2462 break;
bca03d5f 2463 case PHY_WRITE:
42b82dc1 2464 rtl_writephy(tp, regno, data);
2465 index++;
2466 break;
2467 case PHY_READCOUNT_EQ_SKIP:
cecb5fd7 2468 index += (count == data) ? 2 : 1;
bca03d5f 2469 break;
42b82dc1 2470 case PHY_COMP_EQ_SKIPN:
2471 if (predata == data)
2472 index += regno;
2473 index++;
2474 break;
2475 case PHY_COMP_NEQ_SKIPN:
2476 if (predata != data)
2477 index += regno;
2478 index++;
2479 break;
2480 case PHY_WRITE_PREVIOUS:
2481 rtl_writephy(tp, regno, predata);
2482 index++;
2483 break;
2484 case PHY_SKIPN:
2485 index += regno + 1;
2486 break;
2487 case PHY_DELAY_MS:
2488 mdelay(data);
2489 index++;
2490 break;
2491
bca03d5f 2492 default:
2493 BUG();
2494 }
2495 }
eee3786f 2496
2497 ops->write = org.write;
2498 ops->read = org.read;
bca03d5f 2499}
2500
f1e02ed1 2501static void rtl_release_firmware(struct rtl8169_private *tp)
2502{
b6ffd97f
FR		 2503 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2504 release_firmware(tp->rtl_fw->fw);
2505 kfree(tp->rtl_fw);
2506 }
2507 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
f1e02ed1 2508}
2509
953a12cc 2510static void rtl_apply_firmware(struct rtl8169_private *tp)
f1e02ed1 2511{
b6ffd97f 2512 struct rtl_fw *rtl_fw = tp->rtl_fw;
f1e02ed1 2513
2514 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
eef63cc1 2515 if (!IS_ERR_OR_NULL(rtl_fw))
b6ffd97f 2516 rtl_phy_write_fw(tp, rtl_fw);
953a12cc
FR		 2517}
2518
2519static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2520{
2521 if (rtl_readphy(tp, reg) != val)
2522 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2523 else
2524 rtl_apply_firmware(tp);
f1e02ed1 2525}
2526
4da19633 2527static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1da177e4 2528{
350f7596 2529 static const struct phy_reg phy_reg_init[] = {
0b9b571d 2530 { 0x1f, 0x0001 },
2531 { 0x06, 0x006e },
2532 { 0x08, 0x0708 },
2533 { 0x15, 0x4000 },
2534 { 0x18, 0x65c7 },
1da177e4 2535
0b9b571d 2536 { 0x1f, 0x0001 },
2537 { 0x03, 0x00a1 },
2538 { 0x02, 0x0008 },
2539 { 0x01, 0x0120 },
2540 { 0x00, 0x1000 },
2541 { 0x04, 0x0800 },
2542 { 0x04, 0x0000 },
1da177e4 2543
0b9b571d 2544 { 0x03, 0xff41 },
2545 { 0x02, 0xdf60 },
2546 { 0x01, 0x0140 },
2547 { 0x00, 0x0077 },
2548 { 0x04, 0x7800 },
2549 { 0x04, 0x7000 },
2550
2551 { 0x03, 0x802f },
2552 { 0x02, 0x4f02 },
2553 { 0x01, 0x0409 },
2554 { 0x00, 0xf0f9 },
2555 { 0x04, 0x9800 },
2556 { 0x04, 0x9000 },
2557
2558 { 0x03, 0xdf01 },
2559 { 0x02, 0xdf20 },
2560 { 0x01, 0xff95 },
2561 { 0x00, 0xba00 },
2562 { 0x04, 0xa800 },
2563 { 0x04, 0xa000 },
2564
2565 { 0x03, 0xff41 },
2566 { 0x02, 0xdf20 },
2567 { 0x01, 0x0140 },
2568 { 0x00, 0x00bb },
2569 { 0x04, 0xb800 },
2570 { 0x04, 0xb000 },
2571
2572 { 0x03, 0xdf41 },
2573 { 0x02, 0xdc60 },
2574 { 0x01, 0x6340 },
2575 { 0x00, 0x007d },
2576 { 0x04, 0xd800 },
2577 { 0x04, 0xd000 },
2578
2579 { 0x03, 0xdf01 },
2580 { 0x02, 0xdf20 },
2581 { 0x01, 0x100a },
2582 { 0x00, 0xa0ff },
2583 { 0x04, 0xf800 },
2584 { 0x04, 0xf000 },
2585
2586 { 0x1f, 0x0000 },
2587 { 0x0b, 0x0000 },
2588 { 0x00, 0x9200 }
2589 };
1da177e4 2590
4da19633 2591 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1da177e4
LT		 2592}
2593
4da19633 2594static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
5615d9f1 2595{
350f7596 2596 static const struct phy_reg phy_reg_init[] = {
a441d7b6
FR		 2597 { 0x1f, 0x0002 },
2598 { 0x01, 0x90d0 },
2599 { 0x1f, 0x0000 }
2600 };
2601
4da19633 2602 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 2603}
2604
4da19633 2605static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2e955856 2606{
2607 struct pci_dev *pdev = tp->pci_dev;
2e955856 2608
ccbae55e
SS		 2609 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2610 (pdev->subsystem_device != 0xe000))
2e955856 2611 return;
2612
4da19633 2613 rtl_writephy(tp, 0x1f, 0x0001);
2614 rtl_writephy(tp, 0x10, 0xf01b);
2615 rtl_writephy(tp, 0x1f, 0x0000);
2e955856 2616}
2617
4da19633 2618static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2e955856 2619{
350f7596 2620 static const struct phy_reg phy_reg_init[] = {
2e955856 2621 { 0x1f, 0x0001 },
2622 { 0x04, 0x0000 },
2623 { 0x03, 0x00a1 },
2624 { 0x02, 0x0008 },
2625 { 0x01, 0x0120 },
2626 { 0x00, 0x1000 },
2627 { 0x04, 0x0800 },
2628 { 0x04, 0x9000 },
2629 { 0x03, 0x802f },
2630 { 0x02, 0x4f02 },
2631 { 0x01, 0x0409 },
2632 { 0x00, 0xf099 },
2633 { 0x04, 0x9800 },
2634 { 0x04, 0xa000 },
2635 { 0x03, 0xdf01 },
2636 { 0x02, 0xdf20 },
2637 { 0x01, 0xff95 },
2638 { 0x00, 0xba00 },
2639 { 0x04, 0xa800 },
2640 { 0x04, 0xf000 },
2641 { 0x03, 0xdf01 },
2642 { 0x02, 0xdf20 },
2643 { 0x01, 0x101a },
2644 { 0x00, 0xa0ff },
2645 { 0x04, 0xf800 },
2646 { 0x04, 0x0000 },
2647 { 0x1f, 0x0000 },
2648
2649 { 0x1f, 0x0001 },
2650 { 0x10, 0xf41b },
2651 { 0x14, 0xfb54 },
2652 { 0x18, 0xf5c7 },
2653 { 0x1f, 0x0000 },
2654
2655 { 0x1f, 0x0001 },
2656 { 0x17, 0x0cc0 },
2657 { 0x1f, 0x0000 }
2658 };
2659
4da19633 2660 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2e955856 2661
4da19633 2662 rtl8169scd_hw_phy_config_quirk(tp);
2e955856 2663}
2664
4da19633 2665static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
8c7006aa 2666{
350f7596 2667 static const struct phy_reg phy_reg_init[] = {
8c7006aa 2668 { 0x1f, 0x0001 },
2669 { 0x04, 0x0000 },
2670 { 0x03, 0x00a1 },
2671 { 0x02, 0x0008 },
2672 { 0x01, 0x0120 },
2673 { 0x00, 0x1000 },
2674 { 0x04, 0x0800 },
2675 { 0x04, 0x9000 },
2676 { 0x03, 0x802f },
2677 { 0x02, 0x4f02 },
2678 { 0x01, 0x0409 },
2679 { 0x00, 0xf099 },
2680 { 0x04, 0x9800 },
2681 { 0x04, 0xa000 },
2682 { 0x03, 0xdf01 },
2683 { 0x02, 0xdf20 },
2684 { 0x01, 0xff95 },
2685 { 0x00, 0xba00 },
2686 { 0x04, 0xa800 },
2687 { 0x04, 0xf000 },
2688 { 0x03, 0xdf01 },
2689 { 0x02, 0xdf20 },
2690 { 0x01, 0x101a },
2691 { 0x00, 0xa0ff },
2692 { 0x04, 0xf800 },
2693 { 0x04, 0x0000 },
2694 { 0x1f, 0x0000 },
2695
2696 { 0x1f, 0x0001 },
2697 { 0x0b, 0x8480 },
2698 { 0x1f, 0x0000 },
2699
2700 { 0x1f, 0x0001 },
2701 { 0x18, 0x67c7 },
2702 { 0x04, 0x2000 },
2703 { 0x03, 0x002f },
2704 { 0x02, 0x4360 },
2705 { 0x01, 0x0109 },
2706 { 0x00, 0x3022 },
2707 { 0x04, 0x2800 },
2708 { 0x1f, 0x0000 },
2709
2710 { 0x1f, 0x0001 },
2711 { 0x17, 0x0cc0 },
2712 { 0x1f, 0x0000 }
2713 };
2714
4da19633 2715 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
8c7006aa 2716}
2717
4da19633 2718static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
236b8082 2719{
350f7596 2720 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2721 { 0x10, 0xf41b },
2722 { 0x1f, 0x0000 }
2723 };
2724
4da19633 2725 rtl_writephy(tp, 0x1f, 0x0001);
2726 rtl_patchphy(tp, 0x16, 1 << 0);
236b8082 2727
4da19633 2728 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2729}
2730
4da19633 2731static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
236b8082 2732{
350f7596 2733 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2734 { 0x1f, 0x0001 },
2735 { 0x10, 0xf41b },
2736 { 0x1f, 0x0000 }
2737 };
2738
4da19633 2739 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2740}
2741
4da19633 2742static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2743{
350f7596 2744 static const struct phy_reg phy_reg_init[] = {
867763c1
FR		 2745 { 0x1f, 0x0000 },
2746 { 0x1d, 0x0f00 },
2747 { 0x1f, 0x0002 },
2748 { 0x0c, 0x1ec8 },
2749 { 0x1f, 0x0000 }
2750 };
2751
4da19633 2752 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
867763c1
FR		 2753}
2754
4da19633 2755static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
ef3386f0 2756{
350f7596 2757 static const struct phy_reg phy_reg_init[] = {
ef3386f0
FR		 2758 { 0x1f, 0x0001 },
2759 { 0x1d, 0x3d98 },
2760 { 0x1f, 0x0000 }
2761 };
2762
4da19633 2763 rtl_writephy(tp, 0x1f, 0x0000);
2764 rtl_patchphy(tp, 0x14, 1 << 5);
2765 rtl_patchphy(tp, 0x0d, 1 << 5);
ef3386f0 2766
4da19633 2767 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
ef3386f0
FR		 2768}
2769
4da19633 2770static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2771{
350f7596 2772 static const struct phy_reg phy_reg_init[] = {
a3f80671
FR		 2773 { 0x1f, 0x0001 },
2774 { 0x12, 0x2300 },
867763c1
FR		 2775 { 0x1f, 0x0002 },
2776 { 0x00, 0x88d4 },
2777 { 0x01, 0x82b1 },
2778 { 0x03, 0x7002 },
2779 { 0x08, 0x9e30 },
2780 { 0x09, 0x01f0 },
2781 { 0x0a, 0x5500 },
2782 { 0x0c, 0x00c8 },
2783 { 0x1f, 0x0003 },
2784 { 0x12, 0xc096 },
2785 { 0x16, 0x000a },
f50d4275
FR		 2786 { 0x1f, 0x0000 },
2787 { 0x1f, 0x0000 },
2788 { 0x09, 0x2000 },
2789 { 0x09, 0x0000 }
867763c1
FR		 2790 };
2791
4da19633 2792 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2793
4da19633 2794 rtl_patchphy(tp, 0x14, 1 << 5);
2795 rtl_patchphy(tp, 0x0d, 1 << 5);
2796 rtl_writephy(tp, 0x1f, 0x0000);
867763c1
FR		 2797}
2798
4da19633 2799static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
7da97ec9 2800{
350f7596 2801 static const struct phy_reg phy_reg_init[] = {
f50d4275 2802 { 0x1f, 0x0001 },
7da97ec9 2803 { 0x12, 0x2300 },
f50d4275
FR		 2804 { 0x03, 0x802f },
2805 { 0x02, 0x4f02 },
2806 { 0x01, 0x0409 },
2807 { 0x00, 0xf099 },
2808 { 0x04, 0x9800 },
2809 { 0x04, 0x9000 },
2810 { 0x1d, 0x3d98 },
7da97ec9
FR		 2811 { 0x1f, 0x0002 },
2812 { 0x0c, 0x7eb8 },
f50d4275
FR		 2813 { 0x06, 0x0761 },
2814 { 0x1f, 0x0003 },
2815 { 0x16, 0x0f0a },
7da97ec9
FR		 2816 { 0x1f, 0x0000 }
2817 };
2818
4da19633 2819 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2820
4da19633 2821 rtl_patchphy(tp, 0x16, 1 << 0);
2822 rtl_patchphy(tp, 0x14, 1 << 5);
2823 rtl_patchphy(tp, 0x0d, 1 << 5);
2824 rtl_writephy(tp, 0x1f, 0x0000);
7da97ec9
FR		 2825}
2826
4da19633 2827static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
197ff761 2828{
350f7596 2829 static const struct phy_reg phy_reg_init[] = {
197ff761
FR		 2830 { 0x1f, 0x0001 },
2831 { 0x12, 0x2300 },
2832 { 0x1d, 0x3d98 },
2833 { 0x1f, 0x0002 },
2834 { 0x0c, 0x7eb8 },
2835 { 0x06, 0x5461 },
2836 { 0x1f, 0x0003 },
2837 { 0x16, 0x0f0a },
2838 { 0x1f, 0x0000 }
2839 };
2840
4da19633 2841 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
197ff761 2842
4da19633 2843 rtl_patchphy(tp, 0x16, 1 << 0);
2844 rtl_patchphy(tp, 0x14, 1 << 5);
2845 rtl_patchphy(tp, 0x0d, 1 << 5);
2846 rtl_writephy(tp, 0x1f, 0x0000);
197ff761
FR		 2847}
2848
4da19633 2849static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
6fb07058 2850{
4da19633 2851 rtl8168c_3_hw_phy_config(tp);
6fb07058
FR		 2852}
2853
bca03d5f 2854static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
5b538df9 2855{
350f7596 2856 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2857 /* Channel Estimation */
5b538df9 2858 { 0x1f, 0x0001 },
daf9df6d 2859 { 0x06, 0x4064 },
2860 { 0x07, 0x2863 },
2861 { 0x08, 0x059c },
2862 { 0x09, 0x26b4 },
2863 { 0x0a, 0x6a19 },
2864 { 0x0b, 0xdcc8 },
2865 { 0x10, 0xf06d },
2866 { 0x14, 0x7f68 },
2867 { 0x18, 0x7fd9 },
2868 { 0x1c, 0xf0ff },
2869 { 0x1d, 0x3d9c },
5b538df9 2870 { 0x1f, 0x0003 },
daf9df6d 2871 { 0x12, 0xf49f },
2872 { 0x13, 0x070b },
2873 { 0x1a, 0x05ad },
bca03d5f 2874 { 0x14, 0x94c0 },
2875
2876 /*
2877 * Tx Error Issue
cecb5fd7 2878 * Enhance line driver power
bca03d5f 2879 */
5b538df9 2880 { 0x1f, 0x0002 },
daf9df6d 2881 { 0x06, 0x5561 },
2882 { 0x1f, 0x0005 },
2883 { 0x05, 0x8332 },
bca03d5f 2884 { 0x06, 0x5561 },
2885
2886 /*
2887 * Can not link to 1Gbps with bad cable
2888 * Decrease SNR threshold form 21.07dB to 19.04dB
2889 */
2890 { 0x1f, 0x0001 },
2891 { 0x17, 0x0cc0 },
daf9df6d 2892
5b538df9 2893 { 0x1f, 0x0000 },
bca03d5f 2894 { 0x0d, 0xf880 }
daf9df6d 2895 };
2896
4da19633 2897 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
daf9df6d 2898
bca03d5f 2899 /*
2900 * Rx Error Issue
2901 * Fine Tune Switching regulator parameter
2902 */
4da19633 2903 rtl_writephy(tp, 0x1f, 0x0002);
2904 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2905 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
daf9df6d 2906
fdf6fc06 2907 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
350f7596 2908 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2909 { 0x1f, 0x0002 },
2910 { 0x05, 0x669a },
2911 { 0x1f, 0x0005 },
2912 { 0x05, 0x8330 },
2913 { 0x06, 0x669a },
2914 { 0x1f, 0x0002 }
2915 };
2916 int val;
2917
4da19633 2918 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2919
4da19633 2920 val = rtl_readphy(tp, 0x0d);
daf9df6d 2921
2922 if ((val & 0x00ff) != 0x006c) {
350f7596 2923 static const u32 set[] = {
daf9df6d 2924 0x0065, 0x0066, 0x0067, 0x0068,
2925 0x0069, 0x006a, 0x006b, 0x006c
2926 };
2927 int i;
2928
4da19633 2929 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2930
2931 val &= 0xff00;
2932 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2933 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2934 }
2935 } else {
350f7596 2936 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2937 { 0x1f, 0x0002 },
2938 { 0x05, 0x6662 },
2939 { 0x1f, 0x0005 },
2940 { 0x05, 0x8330 },
2941 { 0x06, 0x6662 }
2942 };
2943
4da19633 2944 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2945 }
2946
bca03d5f 2947 /* RSET couple improve */
4da19633 2948 rtl_writephy(tp, 0x1f, 0x0002);
2949 rtl_patchphy(tp, 0x0d, 0x0300);
2950 rtl_patchphy(tp, 0x0f, 0x0010);
daf9df6d 2951
bca03d5f 2952 /* Fine tune PLL performance */
4da19633 2953 rtl_writephy(tp, 0x1f, 0x0002);
2954 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2955 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2956
4da19633 2957 rtl_writephy(tp, 0x1f, 0x0005);
2958 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2959
2960 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
bca03d5f 2961
4da19633 2962 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2963}
2964
bca03d5f 2965static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2966{
350f7596 2967 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2968 /* Channel Estimation */
daf9df6d 2969 { 0x1f, 0x0001 },
2970 { 0x06, 0x4064 },
2971 { 0x07, 0x2863 },
2972 { 0x08, 0x059c },
2973 { 0x09, 0x26b4 },
2974 { 0x0a, 0x6a19 },
2975 { 0x0b, 0xdcc8 },
2976 { 0x10, 0xf06d },
2977 { 0x14, 0x7f68 },
2978 { 0x18, 0x7fd9 },
2979 { 0x1c, 0xf0ff },
2980 { 0x1d, 0x3d9c },
2981 { 0x1f, 0x0003 },
2982 { 0x12, 0xf49f },
2983 { 0x13, 0x070b },
2984 { 0x1a, 0x05ad },
2985 { 0x14, 0x94c0 },
2986
bca03d5f 2987 /*
2988 * Tx Error Issue
cecb5fd7 2989 * Enhance line driver power
bca03d5f 2990 */
daf9df6d 2991 { 0x1f, 0x0002 },
2992 { 0x06, 0x5561 },
2993 { 0x1f, 0x0005 },
2994 { 0x05, 0x8332 },
bca03d5f 2995 { 0x06, 0x5561 },
2996
2997 /*
2998 * Can not link to 1Gbps with bad cable
2999 * Decrease SNR threshold form 21.07dB to 19.04dB
3000 */
3001 { 0x1f, 0x0001 },
3002 { 0x17, 0x0cc0 },
daf9df6d 3003
3004 { 0x1f, 0x0000 },
bca03d5f 3005 { 0x0d, 0xf880 }
5b538df9
FR		 3006 };
3007
4da19633 3008 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
5b538df9 3009
fdf6fc06 3010 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
350f7596 3011 static const struct phy_reg phy_reg_init[] = {
daf9df6d 3012 { 0x1f, 0x0002 },
3013 { 0x05, 0x669a },
5b538df9 3014 { 0x1f, 0x0005 },
daf9df6d 3015 { 0x05, 0x8330 },
3016 { 0x06, 0x669a },
3017
3018 { 0x1f, 0x0002 }
3019 };
3020 int val;
3021
4da19633 3022 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 3023
4da19633 3024 val = rtl_readphy(tp, 0x0d);
daf9df6d 3025 if ((val & 0x00ff) != 0x006c) {
b6bc7650 3026 static const u32 set[] = {
daf9df6d 3027 0x0065, 0x0066, 0x0067, 0x0068,
3028 0x0069, 0x006a, 0x006b, 0x006c
3029 };
3030 int i;
3031
4da19633 3032 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 3033
3034 val &= 0xff00;
3035 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 3036 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 3037 }
3038 } else {
350f7596 3039 static const struct phy_reg phy_reg_init[] = {
daf9df6d 3040 { 0x1f, 0x0002 },
3041 { 0x05, 0x2642 },
5b538df9 3042 { 0x1f, 0x0005 },
daf9df6d 3043 { 0x05, 0x8330 },
3044 { 0x06, 0x2642 }
5b538df9
FR		 3045 };
3046
4da19633 3047 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 3048 }
3049
bca03d5f 3050 /* Fine tune PLL performance */
4da19633 3051 rtl_writephy(tp, 0x1f, 0x0002);
3052 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
3053 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 3054
bca03d5f 3055 /* Switching regulator Slew rate */
4da19633 3056 rtl_writephy(tp, 0x1f, 0x0002);
3057 rtl_patchphy(tp, 0x0f, 0x0017);
daf9df6d 3058
4da19633 3059 rtl_writephy(tp, 0x1f, 0x0005);
3060 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 3061
3062 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
bca03d5f 3063
4da19633 3064 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 3065}
3066
4da19633 3067static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 3068{
350f7596 3069 static const struct phy_reg phy_reg_init[] = {
daf9df6d 3070 { 0x1f, 0x0002 },
3071 { 0x10, 0x0008 },
3072 { 0x0d, 0x006c },
3073
3074 { 0x1f, 0x0000 },
3075 { 0x0d, 0xf880 },
3076
3077 { 0x1f, 0x0001 },
3078 { 0x17, 0x0cc0 },
3079
3080 { 0x1f, 0x0001 },
3081 { 0x0b, 0xa4d8 },
3082 { 0x09, 0x281c },
3083 { 0x07, 0x2883 },
3084 { 0x0a, 0x6b35 },
3085 { 0x1d, 0x3da4 },
3086 { 0x1c, 0xeffd },
3087 { 0x14, 0x7f52 },
3088 { 0x18, 0x7fc6 },
3089 { 0x08, 0x0601 },
3090 { 0x06, 0x4063 },
3091 { 0x10, 0xf074 },
3092 { 0x1f, 0x0003 },
3093 { 0x13, 0x0789 },
3094 { 0x12, 0xf4bd },
3095 { 0x1a, 0x04fd },
3096 { 0x14, 0x84b0 },
3097 { 0x1f, 0x0000 },
3098 { 0x00, 0x9200 },
3099
3100 { 0x1f, 0x0005 },
3101 { 0x01, 0x0340 },
3102 { 0x1f, 0x0001 },
3103 { 0x04, 0x4000 },
3104 { 0x03, 0x1d21 },
3105 { 0x02, 0x0c32 },
3106 { 0x01, 0x0200 },
3107 { 0x00, 0x5554 },
3108 { 0x04, 0x4800 },
3109 { 0x04, 0x4000 },
3110 { 0x04, 0xf000 },
3111 { 0x03, 0xdf01 },
3112 { 0x02, 0xdf20 },
3113 { 0x01, 0x101a },
3114 { 0x00, 0xa0ff },
3115 { 0x04, 0xf800 },
3116 { 0x04, 0xf000 },
3117 { 0x1f, 0x0000 },
3118
3119 { 0x1f, 0x0007 },
3120 { 0x1e, 0x0023 },
3121 { 0x16, 0x0000 },
3122 { 0x1f, 0x0000 }
3123 };
3124
4da19633 3125 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 3126}
3127
e6de30d6 3128static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3129{
3130 static const struct phy_reg phy_reg_init[] = {
3131 { 0x1f, 0x0001 },
3132 { 0x17, 0x0cc0 },
3133
3134 { 0x1f, 0x0007 },
3135 { 0x1e, 0x002d },
3136 { 0x18, 0x0040 },
3137 { 0x1f, 0x0000 }
3138 };
3139
3140 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3141 rtl_patchphy(tp, 0x0d, 1 << 5);
3142}
3143
70090424 3144static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
01dc7fec 3145{
3146 static const struct phy_reg phy_reg_init[] = {
3147 /* Enable Delay cap */
3148 { 0x1f, 0x0005 },
3149 { 0x05, 0x8b80 },
3150 { 0x06, 0xc896 },
3151 { 0x1f, 0x0000 },
3152
3153 /* Channel estimation fine tune */
3154 { 0x1f, 0x0001 },
3155 { 0x0b, 0x6c20 },
3156 { 0x07, 0x2872 },
3157 { 0x1c, 0xefff },
3158 { 0x1f, 0x0003 },
3159 { 0x14, 0x6420 },
3160 { 0x1f, 0x0000 },
3161
3162 /* Update PFM & 10M TX idle timer */
3163 { 0x1f, 0x0007 },
3164 { 0x1e, 0x002f },
3165 { 0x15, 0x1919 },
3166 { 0x1f, 0x0000 },
3167
3168 { 0x1f, 0x0007 },
3169 { 0x1e, 0x00ac },
3170 { 0x18, 0x0006 },
3171 { 0x1f, 0x0000 }
3172 };
3173
15ecd039
FR		 3174 rtl_apply_firmware(tp);
3175
01dc7fec 3176 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3177
3178 /* DCO enable for 10M IDLE Power */
3179 rtl_writephy(tp, 0x1f, 0x0007);
3180 rtl_writephy(tp, 0x1e, 0x0023);
3181 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
3182 rtl_writephy(tp, 0x1f, 0x0000);
3183
3184 /* For impedance matching */
3185 rtl_writephy(tp, 0x1f, 0x0002);
3186 rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
cecb5fd7 3187 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3188
3189 /* PHY auto speed down */
3190 rtl_writephy(tp, 0x1f, 0x0007);
3191 rtl_writephy(tp, 0x1e, 0x002d);
3192 rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
3193 rtl_writephy(tp, 0x1f, 0x0000);
3194 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3195
3196 rtl_writephy(tp, 0x1f, 0x0005);
3197 rtl_writephy(tp, 0x05, 0x8b86);
3198 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3199 rtl_writephy(tp, 0x1f, 0x0000);
3200
3201 rtl_writephy(tp, 0x1f, 0x0005);
3202 rtl_writephy(tp, 0x05, 0x8b85);
3203 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3204 rtl_writephy(tp, 0x1f, 0x0007);
3205 rtl_writephy(tp, 0x1e, 0x0020);
3206 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
3207 rtl_writephy(tp, 0x1f, 0x0006);
3208 rtl_writephy(tp, 0x00, 0x5a00);
3209 rtl_writephy(tp, 0x1f, 0x0000);
3210 rtl_writephy(tp, 0x0d, 0x0007);
3211 rtl_writephy(tp, 0x0e, 0x003c);
3212 rtl_writephy(tp, 0x0d, 0x4007);
3213 rtl_writephy(tp, 0x0e, 0x0000);
3214 rtl_writephy(tp, 0x0d, 0x0000);
3215}
3216
9ecb9aab 3217static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3218{
3219 const u16 w[] = {
3220 addr[0] | (addr[1] << 8),
3221 addr[2] | (addr[3] << 8),
3222 addr[4] | (addr[5] << 8)
3223 };
3224 const struct exgmac_reg e[] = {
3225 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3226 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3227 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3228 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3229 };
3230
3231 rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3232}
3233
70090424
HW		 3234static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3235{
3236 static const struct phy_reg phy_reg_init[] = {
3237 /* Enable Delay cap */
3238 { 0x1f, 0x0004 },
3239 { 0x1f, 0x0007 },
3240 { 0x1e, 0x00ac },
3241 { 0x18, 0x0006 },
3242 { 0x1f, 0x0002 },
3243 { 0x1f, 0x0000 },
3244 { 0x1f, 0x0000 },
3245
3246 /* Channel estimation fine tune */
3247 { 0x1f, 0x0003 },
3248 { 0x09, 0xa20f },
3249 { 0x1f, 0x0000 },
3250 { 0x1f, 0x0000 },
3251
3252 /* Green Setting */
3253 { 0x1f, 0x0005 },
3254 { 0x05, 0x8b5b },
3255 { 0x06, 0x9222 },
3256 { 0x05, 0x8b6d },
3257 { 0x06, 0x8000 },
3258 { 0x05, 0x8b76 },
3259 { 0x06, 0x8000 },
3260 { 0x1f, 0x0000 }
3261 };
3262
3263 rtl_apply_firmware(tp);
3264
3265 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3266
3267 /* For 4-corner performance improve */
3268 rtl_writephy(tp, 0x1f, 0x0005);
3269 rtl_writephy(tp, 0x05, 0x8b80);
3270 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
3271 rtl_writephy(tp, 0x1f, 0x0000);
3272
3273 /* PHY auto speed down */
3274 rtl_writephy(tp, 0x1f, 0x0004);
3275 rtl_writephy(tp, 0x1f, 0x0007);
3276 rtl_writephy(tp, 0x1e, 0x002d);
3277 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3278 rtl_writephy(tp, 0x1f, 0x0002);
3279 rtl_writephy(tp, 0x1f, 0x0000);
3280 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3281
3282 /* improve 10M EEE waveform */
3283 rtl_writephy(tp, 0x1f, 0x0005);
3284 rtl_writephy(tp, 0x05, 0x8b86);
3285 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3286 rtl_writephy(tp, 0x1f, 0x0000);
3287
3288 /* Improve 2-pair detection performance */
3289 rtl_writephy(tp, 0x1f, 0x0005);
3290 rtl_writephy(tp, 0x05, 0x8b85);
3291 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3292 rtl_writephy(tp, 0x1f, 0x0000);
3293
3294 /* EEE setting */
fdf6fc06 3295 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, ERIAR_EXGMAC);
70090424
HW		 3296 rtl_writephy(tp, 0x1f, 0x0005);
3297 rtl_writephy(tp, 0x05, 0x8b85);
3298 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3299 rtl_writephy(tp, 0x1f, 0x0004);
3300 rtl_writephy(tp, 0x1f, 0x0007);
3301 rtl_writephy(tp, 0x1e, 0x0020);
1b23a3e3 3302 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
70090424
HW		 3303 rtl_writephy(tp, 0x1f, 0x0002);
3304 rtl_writephy(tp, 0x1f, 0x0000);
3305 rtl_writephy(tp, 0x0d, 0x0007);
3306 rtl_writephy(tp, 0x0e, 0x003c);
3307 rtl_writephy(tp, 0x0d, 0x4007);
3308 rtl_writephy(tp, 0x0e, 0x0000);
3309 rtl_writephy(tp, 0x0d, 0x0000);
3310
3311 /* Green feature */
3312 rtl_writephy(tp, 0x1f, 0x0003);
3313 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3314 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3315 rtl_writephy(tp, 0x1f, 0x0000);
e0c07557 3316
9ecb9aab 3317 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3318 rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
70090424
HW		 3319}
3320
5f886e08
HW		 3321static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3322{
3323 /* For 4-corner performance improve */
3324 rtl_writephy(tp, 0x1f, 0x0005);
3325 rtl_writephy(tp, 0x05, 0x8b80);
3326 rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3327 rtl_writephy(tp, 0x1f, 0x0000);
3328
3329 /* PHY auto speed down */
3330 rtl_writephy(tp, 0x1f, 0x0007);
3331 rtl_writephy(tp, 0x1e, 0x002d);
3332 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3333 rtl_writephy(tp, 0x1f, 0x0000);
3334 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3335
3336 /* Improve 10M EEE waveform */
3337 rtl_writephy(tp, 0x1f, 0x0005);
3338 rtl_writephy(tp, 0x05, 0x8b86);
3339 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3340 rtl_writephy(tp, 0x1f, 0x0000);
3341}
3342
c2218925
HW		 3343static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3344{
3345 static const struct phy_reg phy_reg_init[] = {
3346 /* Channel estimation fine tune */
3347 { 0x1f, 0x0003 },
3348 { 0x09, 0xa20f },
3349 { 0x1f, 0x0000 },
3350
3351 /* Modify green table for giga & fnet */
3352 { 0x1f, 0x0005 },
3353 { 0x05, 0x8b55 },
3354 { 0x06, 0x0000 },
3355 { 0x05, 0x8b5e },
3356 { 0x06, 0x0000 },
3357 { 0x05, 0x8b67 },
3358 { 0x06, 0x0000 },
3359 { 0x05, 0x8b70 },
3360 { 0x06, 0x0000 },
3361 { 0x1f, 0x0000 },
3362 { 0x1f, 0x0007 },
3363 { 0x1e, 0x0078 },
3364 { 0x17, 0x0000 },
3365 { 0x19, 0x00fb },
3366 { 0x1f, 0x0000 },
3367
3368 /* Modify green table for 10M */
3369 { 0x1f, 0x0005 },
3370 { 0x05, 0x8b79 },
3371 { 0x06, 0xaa00 },
3372 { 0x1f, 0x0000 },
3373
3374 /* Disable hiimpedance detection (RTCT) */
3375 { 0x1f, 0x0003 },
3376 { 0x01, 0x328a },
3377 { 0x1f, 0x0000 }
3378 };
3379
3380 rtl_apply_firmware(tp);
3381
3382 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3383
5f886e08 3384 rtl8168f_hw_phy_config(tp);
c2218925
HW		 3385
3386 /* Improve 2-pair detection performance */
3387 rtl_writephy(tp, 0x1f, 0x0005);
3388 rtl_writephy(tp, 0x05, 0x8b85);
3389 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3390 rtl_writephy(tp, 0x1f, 0x0000);
3391}
3392
3393static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3394{
3395 rtl_apply_firmware(tp);
3396
5f886e08 3397 rtl8168f_hw_phy_config(tp);
c2218925
HW		 3398}
3399
b3d7b2f2
HW		 3400static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3401{
b3d7b2f2
HW		 3402 static const struct phy_reg phy_reg_init[] = {
3403 /* Channel estimation fine tune */
3404 { 0x1f, 0x0003 },
3405 { 0x09, 0xa20f },
3406 { 0x1f, 0x0000 },
3407
3408 /* Modify green table for giga & fnet */
3409 { 0x1f, 0x0005 },
3410 { 0x05, 0x8b55 },
3411 { 0x06, 0x0000 },
3412 { 0x05, 0x8b5e },
3413 { 0x06, 0x0000 },
3414 { 0x05, 0x8b67 },
3415 { 0x06, 0x0000 },
3416 { 0x05, 0x8b70 },
3417 { 0x06, 0x0000 },
3418 { 0x1f, 0x0000 },
3419 { 0x1f, 0x0007 },
3420 { 0x1e, 0x0078 },
3421 { 0x17, 0x0000 },
3422 { 0x19, 0x00aa },
3423 { 0x1f, 0x0000 },
3424
3425 /* Modify green table for 10M */
3426 { 0x1f, 0x0005 },
3427 { 0x05, 0x8b79 },
3428 { 0x06, 0xaa00 },
3429 { 0x1f, 0x0000 },
3430
3431 /* Disable hiimpedance detection (RTCT) */
3432 { 0x1f, 0x0003 },
3433 { 0x01, 0x328a },
3434 { 0x1f, 0x0000 }
3435 };
3436
3437
3438 rtl_apply_firmware(tp);
3439
3440 rtl8168f_hw_phy_config(tp);
3441
3442 /* Improve 2-pair detection performance */
3443 rtl_writephy(tp, 0x1f, 0x0005);
3444 rtl_writephy(tp, 0x05, 0x8b85);
3445 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3446 rtl_writephy(tp, 0x1f, 0x0000);
3447
3448 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3449
3450 /* Modify green table for giga */
3451 rtl_writephy(tp, 0x1f, 0x0005);
3452 rtl_writephy(tp, 0x05, 0x8b54);
3453 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
3454 rtl_writephy(tp, 0x05, 0x8b5d);
3455 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
3456 rtl_writephy(tp, 0x05, 0x8a7c);
3457 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3458 rtl_writephy(tp, 0x05, 0x8a7f);
3459 rtl_w1w0_phy(tp, 0x06, 0x0100, 0x0000);
3460 rtl_writephy(tp, 0x05, 0x8a82);
3461 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3462 rtl_writephy(tp, 0x05, 0x8a85);
3463 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3464 rtl_writephy(tp, 0x05, 0x8a88);
3465 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3466 rtl_writephy(tp, 0x1f, 0x0000);
3467
3468 /* uc same-seed solution */
3469 rtl_writephy(tp, 0x1f, 0x0005);
3470 rtl_writephy(tp, 0x05, 0x8b85);
3471 rtl_w1w0_phy(tp, 0x06, 0x8000, 0x0000);
3472 rtl_writephy(tp, 0x1f, 0x0000);
3473
3474 /* eee setting */
fdf6fc06 3475 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
b3d7b2f2
HW		 3476 rtl_writephy(tp, 0x1f, 0x0005);
3477 rtl_writephy(tp, 0x05, 0x8b85);
3478 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3479 rtl_writephy(tp, 0x1f, 0x0004);
3480 rtl_writephy(tp, 0x1f, 0x0007);
3481 rtl_writephy(tp, 0x1e, 0x0020);
3482 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
3483 rtl_writephy(tp, 0x1f, 0x0000);
3484 rtl_writephy(tp, 0x0d, 0x0007);
3485 rtl_writephy(tp, 0x0e, 0x003c);
3486 rtl_writephy(tp, 0x0d, 0x4007);
3487 rtl_writephy(tp, 0x0e, 0x0000);
3488 rtl_writephy(tp, 0x0d, 0x0000);
3489
3490 /* Green feature */
3491 rtl_writephy(tp, 0x1f, 0x0003);
3492 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3493 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3494 rtl_writephy(tp, 0x1f, 0x0000);
3495}
3496
c558386b
HW		 3497static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3498{
c558386b
HW		 3499 rtl_apply_firmware(tp);
3500
41f44d13 3501 rtl_writephy(tp, 0x1f, 0x0a46);
3502 if (rtl_readphy(tp, 0x10) & 0x0100) {
3503 rtl_writephy(tp, 0x1f, 0x0bcc);
3504 rtl_w1w0_phy(tp, 0x12, 0x0000, 0x8000);
3505 } else {
3506 rtl_writephy(tp, 0x1f, 0x0bcc);
3507 rtl_w1w0_phy(tp, 0x12, 0x8000, 0x0000);
3508 }
c558386b 3509
41f44d13 3510 rtl_writephy(tp, 0x1f, 0x0a46);
3511 if (rtl_readphy(tp, 0x13) & 0x0100) {
3512 rtl_writephy(tp, 0x1f, 0x0c41);
3513 rtl_w1w0_phy(tp, 0x15, 0x0002, 0x0000);
3514 } else {
fe7524c0 3515 rtl_writephy(tp, 0x1f, 0x0c41);
3516 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0002);
41f44d13 3517 }
c558386b 3518
41f44d13 3519 /* Enable PHY auto speed down */
3520 rtl_writephy(tp, 0x1f, 0x0a44);
3521 rtl_w1w0_phy(tp, 0x11, 0x000c, 0x0000);
c558386b 3522
fe7524c0 3523 rtl_writephy(tp, 0x1f, 0x0bcc);
3524 rtl_w1w0_phy(tp, 0x14, 0x0100, 0x0000);
3525 rtl_writephy(tp, 0x1f, 0x0a44);
3526 rtl_w1w0_phy(tp, 0x11, 0x00c0, 0x0000);
3527 rtl_writephy(tp, 0x1f, 0x0a43);
3528 rtl_writephy(tp, 0x13, 0x8084);
3529 rtl_w1w0_phy(tp, 0x14, 0x0000, 0x6000);
3530 rtl_w1w0_phy(tp, 0x10, 0x1003, 0x0000);
3531
41f44d13 3532 /* EEE auto-fallback function */
3533 rtl_writephy(tp, 0x1f, 0x0a4b);
3534 rtl_w1w0_phy(tp, 0x11, 0x0004, 0x0000);
c558386b 3535
41f44d13 3536 /* Enable UC LPF tune function */
3537 rtl_writephy(tp, 0x1f, 0x0a43);
3538 rtl_writephy(tp, 0x13, 0x8012);
3539 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3540
3541 rtl_writephy(tp, 0x1f, 0x0c42);
3542 rtl_w1w0_phy(tp, 0x11, 0x4000, 0x2000);
3543
fe7524c0 3544 /* Improve SWR Efficiency */
3545 rtl_writephy(tp, 0x1f, 0x0bcd);
3546 rtl_writephy(tp, 0x14, 0x5065);
3547 rtl_writephy(tp, 0x14, 0xd065);
3548 rtl_writephy(tp, 0x1f, 0x0bc8);
3549 rtl_writephy(tp, 0x11, 0x5655);
3550 rtl_writephy(tp, 0x1f, 0x0bcd);
3551 rtl_writephy(tp, 0x14, 0x1065);
3552 rtl_writephy(tp, 0x14, 0x9065);
3553 rtl_writephy(tp, 0x14, 0x1065);
3554
1bac1072
DC		 3555 /* Check ALDPS bit, disable it if enabled */
3556 rtl_writephy(tp, 0x1f, 0x0a43);
3557 if (rtl_readphy(tp, 0x10) & 0x0004)
3558 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0004);
3559
41f44d13 3560 rtl_writephy(tp, 0x1f, 0x0000);
c558386b
HW		 3561}
3562
57538c4a 3563static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3564{
3565 rtl_apply_firmware(tp);
3566}
3567
6e1d0b89
CHL		 3568static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3569{
3570 u16 dout_tapbin;
3571 u32 data;
3572
3573 rtl_apply_firmware(tp);
3574
3575 /* CHN EST parameters adjust - giga master */
3576 rtl_writephy(tp, 0x1f, 0x0a43);
3577 rtl_writephy(tp, 0x13, 0x809b);
3578 rtl_w1w0_phy(tp, 0x14, 0x8000, 0xf800);
3579 rtl_writephy(tp, 0x13, 0x80a2);
3580 rtl_w1w0_phy(tp, 0x14, 0x8000, 0xff00);
3581 rtl_writephy(tp, 0x13, 0x80a4);
3582 rtl_w1w0_phy(tp, 0x14, 0x8500, 0xff00);
3583 rtl_writephy(tp, 0x13, 0x809c);
3584 rtl_w1w0_phy(tp, 0x14, 0xbd00, 0xff00);
3585 rtl_writephy(tp, 0x1f, 0x0000);
3586
3587 /* CHN EST parameters adjust - giga slave */
3588 rtl_writephy(tp, 0x1f, 0x0a43);
3589 rtl_writephy(tp, 0x13, 0x80ad);
3590 rtl_w1w0_phy(tp, 0x14, 0x7000, 0xf800);
3591 rtl_writephy(tp, 0x13, 0x80b4);
3592 rtl_w1w0_phy(tp, 0x14, 0x5000, 0xff00);
3593 rtl_writephy(tp, 0x13, 0x80ac);
3594 rtl_w1w0_phy(tp, 0x14, 0x4000, 0xff00);
3595 rtl_writephy(tp, 0x1f, 0x0000);
3596
3597 /* CHN EST parameters adjust - fnet */
3598 rtl_writephy(tp, 0x1f, 0x0a43);
3599 rtl_writephy(tp, 0x13, 0x808e);
3600 rtl_w1w0_phy(tp, 0x14, 0x1200, 0xff00);
3601 rtl_writephy(tp, 0x13, 0x8090);
3602 rtl_w1w0_phy(tp, 0x14, 0xe500, 0xff00);
3603 rtl_writephy(tp, 0x13, 0x8092);
3604 rtl_w1w0_phy(tp, 0x14, 0x9f00, 0xff00);
3605 rtl_writephy(tp, 0x1f, 0x0000);
3606
3607 /* enable R-tune & PGA-retune function */
3608 dout_tapbin = 0;
3609 rtl_writephy(tp, 0x1f, 0x0a46);
3610 data = rtl_readphy(tp, 0x13);
3611 data &= 3;
3612 data <<= 2;
3613 dout_tapbin |= data;
3614 data = rtl_readphy(tp, 0x12);
3615 data &= 0xc000;
3616 data >>= 14;
3617 dout_tapbin |= data;
3618 dout_tapbin = ~(dout_tapbin^0x08);
3619 dout_tapbin <<= 12;
3620 dout_tapbin &= 0xf000;
3621 rtl_writephy(tp, 0x1f, 0x0a43);
3622 rtl_writephy(tp, 0x13, 0x827a);
3623 rtl_w1w0_phy(tp, 0x14, dout_tapbin, 0xf000);
3624 rtl_writephy(tp, 0x13, 0x827b);
3625 rtl_w1w0_phy(tp, 0x14, dout_tapbin, 0xf000);
3626 rtl_writephy(tp, 0x13, 0x827c);
3627 rtl_w1w0_phy(tp, 0x14, dout_tapbin, 0xf000);
3628 rtl_writephy(tp, 0x13, 0x827d);
3629 rtl_w1w0_phy(tp, 0x14, dout_tapbin, 0xf000);
3630
3631 rtl_writephy(tp, 0x1f, 0x0a43);
3632 rtl_writephy(tp, 0x13, 0x0811);
3633 rtl_w1w0_phy(tp, 0x14, 0x0800, 0x0000);
3634 rtl_writephy(tp, 0x1f, 0x0a42);
3635 rtl_w1w0_phy(tp, 0x16, 0x0002, 0x0000);
3636 rtl_writephy(tp, 0x1f, 0x0000);
3637
3638 /* enable GPHY 10M */
3639 rtl_writephy(tp, 0x1f, 0x0a44);
3640 rtl_w1w0_phy(tp, 0x11, 0x0800, 0x0000);
3641 rtl_writephy(tp, 0x1f, 0x0000);
3642
3643 /* SAR ADC performance */
3644 rtl_writephy(tp, 0x1f, 0x0bca);
3645 rtl_w1w0_phy(tp, 0x17, 0x4000, 0x3000);
3646 rtl_writephy(tp, 0x1f, 0x0000);
3647
3648 rtl_writephy(tp, 0x1f, 0x0a43);
3649 rtl_writephy(tp, 0x13, 0x803f);
3650 rtl_w1w0_phy(tp, 0x14, 0x0000, 0x3000);
3651 rtl_writephy(tp, 0x13, 0x8047);
3652 rtl_w1w0_phy(tp, 0x14, 0x0000, 0x3000);
3653 rtl_writephy(tp, 0x13, 0x804f);
3654 rtl_w1w0_phy(tp, 0x14, 0x0000, 0x3000);
3655 rtl_writephy(tp, 0x13, 0x8057);
3656 rtl_w1w0_phy(tp, 0x14, 0x0000, 0x3000);
3657 rtl_writephy(tp, 0x13, 0x805f);
3658 rtl_w1w0_phy(tp, 0x14, 0x0000, 0x3000);
3659 rtl_writephy(tp, 0x13, 0x8067);
3660 rtl_w1w0_phy(tp, 0x14, 0x0000, 0x3000);
3661 rtl_writephy(tp, 0x13, 0x806f);
3662 rtl_w1w0_phy(tp, 0x14, 0x0000, 0x3000);
3663 rtl_writephy(tp, 0x1f, 0x0000);
3664
3665 /* disable phy pfm mode */
3666 rtl_writephy(tp, 0x1f, 0x0a44);
3667 rtl_w1w0_phy(tp, 0x14, 0x0000, 0x0080);
3668 rtl_writephy(tp, 0x1f, 0x0000);
3669
3670 /* Check ALDPS bit, disable it if enabled */
3671 rtl_writephy(tp, 0x1f, 0x0a43);
3672 if (rtl_readphy(tp, 0x10) & 0x0004)
3673 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0004);
3674
3675 rtl_writephy(tp, 0x1f, 0x0000);
3676}
3677
3678static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3679{
3680 u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3681 u16 rlen;
3682 u32 data;
3683
3684 rtl_apply_firmware(tp);
3685
3686 /* CHIN EST parameter update */
3687 rtl_writephy(tp, 0x1f, 0x0a43);
3688 rtl_writephy(tp, 0x13, 0x808a);
3689 rtl_w1w0_phy(tp, 0x14, 0x000a, 0x003f);
3690 rtl_writephy(tp, 0x1f, 0x0000);
3691
3692 /* enable R-tune & PGA-retune function */
3693 rtl_writephy(tp, 0x1f, 0x0a43);
3694 rtl_writephy(tp, 0x13, 0x0811);
3695 rtl_w1w0_phy(tp, 0x14, 0x0800, 0x0000);
3696 rtl_writephy(tp, 0x1f, 0x0a42);
3697 rtl_w1w0_phy(tp, 0x16, 0x0002, 0x0000);
3698 rtl_writephy(tp, 0x1f, 0x0000);
3699
3700 /* enable GPHY 10M */
3701 rtl_writephy(tp, 0x1f, 0x0a44);
3702 rtl_w1w0_phy(tp, 0x11, 0x0800, 0x0000);
3703 rtl_writephy(tp, 0x1f, 0x0000);
3704
3705 r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3706 data = r8168_mac_ocp_read(tp, 0xdd02);
3707 ioffset_p3 = ((data & 0x80)>>7);
3708 ioffset_p3 <<= 3;
3709
3710 data = r8168_mac_ocp_read(tp, 0xdd00);
3711 ioffset_p3 |= ((data & (0xe000))>>13);
3712 ioffset_p2 = ((data & (0x1e00))>>9);
3713 ioffset_p1 = ((data & (0x01e0))>>5);
3714 ioffset_p0 = ((data & 0x0010)>>4);
3715 ioffset_p0 <<= 3;
3716 ioffset_p0 |= (data & (0x07));
3717 data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3718
05b9687b
CHL		 3719 if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
3720 (ioffset_p1 != 0x0f) || (ioffset_p0 == 0x0f)) {
6e1d0b89
CHL		 3721 rtl_writephy(tp, 0x1f, 0x0bcf);
3722 rtl_writephy(tp, 0x16, data);
3723 rtl_writephy(tp, 0x1f, 0x0000);
3724 }
3725
3726 /* Modify rlen (TX LPF corner frequency) level */
3727 rtl_writephy(tp, 0x1f, 0x0bcd);
3728 data = rtl_readphy(tp, 0x16);
3729 data &= 0x000f;
3730 rlen = 0;
3731 if (data > 3)
3732 rlen = data - 3;
3733 data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3734 rtl_writephy(tp, 0x17, data);
3735 rtl_writephy(tp, 0x1f, 0x0bcd);
3736 rtl_writephy(tp, 0x1f, 0x0000);
3737
3738 /* disable phy pfm mode */
3739 rtl_writephy(tp, 0x1f, 0x0a44);
3740 rtl_w1w0_phy(tp, 0x14, 0x0000, 0x0080);
3741 rtl_writephy(tp, 0x1f, 0x0000);
3742
3743 /* Check ALDPS bit, disable it if enabled */
3744 rtl_writephy(tp, 0x1f, 0x0a43);
3745 if (rtl_readphy(tp, 0x10) & 0x0004)
3746 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0004);
3747
3748 rtl_writephy(tp, 0x1f, 0x0000);
3749}
3750
4da19633 3751static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2857ffb7 3752{
350f7596 3753 static const struct phy_reg phy_reg_init[] = {
2857ffb7
FR		 3754 { 0x1f, 0x0003 },
3755 { 0x08, 0x441d },
3756 { 0x01, 0x9100 },
3757 { 0x1f, 0x0000 }
3758 };
3759
4da19633 3760 rtl_writephy(tp, 0x1f, 0x0000);
3761 rtl_patchphy(tp, 0x11, 1 << 12);
3762 rtl_patchphy(tp, 0x19, 1 << 13);
3763 rtl_patchphy(tp, 0x10, 1 << 15);
2857ffb7 3764
4da19633 3765 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2857ffb7
FR		 3766}
3767
5a5e4443
HW		 3768static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3769{
3770 static const struct phy_reg phy_reg_init[] = {
3771 { 0x1f, 0x0005 },
3772 { 0x1a, 0x0000 },
3773 { 0x1f, 0x0000 },
3774
3775 { 0x1f, 0x0004 },
3776 { 0x1c, 0x0000 },
3777 { 0x1f, 0x0000 },
3778
3779 { 0x1f, 0x0001 },
3780 { 0x15, 0x7701 },
3781 { 0x1f, 0x0000 }
3782 };
3783
3784 /* Disable ALDPS before ram code */
eef63cc1
FR		 3785 rtl_writephy(tp, 0x1f, 0x0000);
3786 rtl_writephy(tp, 0x18, 0x0310);
3787 msleep(100);
5a5e4443 3788
953a12cc 3789 rtl_apply_firmware(tp);
5a5e4443
HW		 3790
3791 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3792}
3793
7e18dca1
HW		 3794static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3795{
7e18dca1 3796 /* Disable ALDPS before setting firmware */
eef63cc1
FR		 3797 rtl_writephy(tp, 0x1f, 0x0000);
3798 rtl_writephy(tp, 0x18, 0x0310);
3799 msleep(20);
7e18dca1
HW		 3800
3801 rtl_apply_firmware(tp);
3802
3803 /* EEE setting */
fdf6fc06 3804 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
7e18dca1
HW		 3805 rtl_writephy(tp, 0x1f, 0x0004);
3806 rtl_writephy(tp, 0x10, 0x401f);
3807 rtl_writephy(tp, 0x19, 0x7030);
3808 rtl_writephy(tp, 0x1f, 0x0000);
3809}
3810
5598bfe5
HW		 3811static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3812{
5598bfe5
HW		 3813 static const struct phy_reg phy_reg_init[] = {
3814 { 0x1f, 0x0004 },
3815 { 0x10, 0xc07f },
3816 { 0x19, 0x7030 },
3817 { 0x1f, 0x0000 }
3818 };
3819
3820 /* Disable ALDPS before ram code */
eef63cc1
FR		 3821 rtl_writephy(tp, 0x1f, 0x0000);
3822 rtl_writephy(tp, 0x18, 0x0310);
3823 msleep(100);
5598bfe5
HW		 3824
3825 rtl_apply_firmware(tp);
3826
fdf6fc06 3827 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5598bfe5
HW		 3828 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3829
fdf6fc06 3830 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5598bfe5
HW		 3831}
3832
5615d9f1
FR		 3833static void rtl_hw_phy_config(struct net_device *dev)
3834{
3835 struct rtl8169_private *tp = netdev_priv(dev);
5615d9f1
FR		 3836
3837 rtl8169_print_mac_version(tp);
3838
3839 switch (tp->mac_version) {
3840 case RTL_GIGA_MAC_VER_01:
3841 break;
3842 case RTL_GIGA_MAC_VER_02:
3843 case RTL_GIGA_MAC_VER_03:
4da19633 3844 rtl8169s_hw_phy_config(tp);
5615d9f1
FR		 3845 break;
3846 case RTL_GIGA_MAC_VER_04:
4da19633 3847 rtl8169sb_hw_phy_config(tp);
5615d9f1 3848 break;
2e955856 3849 case RTL_GIGA_MAC_VER_05:
4da19633 3850 rtl8169scd_hw_phy_config(tp);
2e955856 3851 break;
8c7006aa 3852 case RTL_GIGA_MAC_VER_06:
4da19633 3853 rtl8169sce_hw_phy_config(tp);
8c7006aa 3854 break;
2857ffb7
FR		 3855 case RTL_GIGA_MAC_VER_07:
3856 case RTL_GIGA_MAC_VER_08:
3857 case RTL_GIGA_MAC_VER_09:
4da19633 3858 rtl8102e_hw_phy_config(tp);
2857ffb7 3859 break;
236b8082 3860 case RTL_GIGA_MAC_VER_11:
4da19633 3861 rtl8168bb_hw_phy_config(tp);
236b8082
FR		 3862 break;
3863 case RTL_GIGA_MAC_VER_12:
4da19633 3864 rtl8168bef_hw_phy_config(tp);
236b8082
FR		 3865 break;
3866 case RTL_GIGA_MAC_VER_17:
4da19633 3867 rtl8168bef_hw_phy_config(tp);
236b8082 3868 break;
867763c1 3869 case RTL_GIGA_MAC_VER_18:
4da19633 3870 rtl8168cp_1_hw_phy_config(tp);
867763c1
FR		 3871 break;
3872 case RTL_GIGA_MAC_VER_19:
4da19633 3873 rtl8168c_1_hw_phy_config(tp);
867763c1 3874 break;
7da97ec9 3875 case RTL_GIGA_MAC_VER_20:
4da19633 3876 rtl8168c_2_hw_phy_config(tp);
7da97ec9 3877 break;
197ff761 3878 case RTL_GIGA_MAC_VER_21:
4da19633 3879 rtl8168c_3_hw_phy_config(tp);
197ff761 3880 break;
6fb07058 3881 case RTL_GIGA_MAC_VER_22:
4da19633 3882 rtl8168c_4_hw_phy_config(tp);
6fb07058 3883 break;
ef3386f0 3884 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 3885 case RTL_GIGA_MAC_VER_24:
4da19633 3886 rtl8168cp_2_hw_phy_config(tp);
ef3386f0 3887 break;
5b538df9 3888 case RTL_GIGA_MAC_VER_25:
bca03d5f 3889 rtl8168d_1_hw_phy_config(tp);
daf9df6d 3890 break;
3891 case RTL_GIGA_MAC_VER_26:
bca03d5f 3892 rtl8168d_2_hw_phy_config(tp);
daf9df6d 3893 break;
3894 case RTL_GIGA_MAC_VER_27:
4da19633 3895 rtl8168d_3_hw_phy_config(tp);
5b538df9 3896 break;
e6de30d6 3897 case RTL_GIGA_MAC_VER_28:
3898 rtl8168d_4_hw_phy_config(tp);
3899 break;
5a5e4443
HW		 3900 case RTL_GIGA_MAC_VER_29:
3901 case RTL_GIGA_MAC_VER_30:
3902 rtl8105e_hw_phy_config(tp);
3903 break;
cecb5fd7
FR		 3904 case RTL_GIGA_MAC_VER_31:
3905 /* None. */
3906 break;
01dc7fec 3907 case RTL_GIGA_MAC_VER_32:
01dc7fec 3908 case RTL_GIGA_MAC_VER_33:
70090424
HW		 3909 rtl8168e_1_hw_phy_config(tp);
3910 break;
3911 case RTL_GIGA_MAC_VER_34:
3912 rtl8168e_2_hw_phy_config(tp);
01dc7fec 3913 break;
c2218925
HW		 3914 case RTL_GIGA_MAC_VER_35:
3915 rtl8168f_1_hw_phy_config(tp);
3916 break;
3917 case RTL_GIGA_MAC_VER_36:
3918 rtl8168f_2_hw_phy_config(tp);
3919 break;
ef3386f0 3920
7e18dca1
HW		 3921 case RTL_GIGA_MAC_VER_37:
3922 rtl8402_hw_phy_config(tp);
3923 break;
3924
b3d7b2f2
HW		 3925 case RTL_GIGA_MAC_VER_38:
3926 rtl8411_hw_phy_config(tp);
3927 break;
3928
5598bfe5
HW		 3929 case RTL_GIGA_MAC_VER_39:
3930 rtl8106e_hw_phy_config(tp);
3931 break;
3932
c558386b
HW		 3933 case RTL_GIGA_MAC_VER_40:
3934 rtl8168g_1_hw_phy_config(tp);
3935 break;
57538c4a 3936 case RTL_GIGA_MAC_VER_42:
58152cd4 3937 case RTL_GIGA_MAC_VER_43:
45dd95c4 3938 case RTL_GIGA_MAC_VER_44:
57538c4a 3939 rtl8168g_2_hw_phy_config(tp);
3940 break;
6e1d0b89
CHL		 3941 case RTL_GIGA_MAC_VER_45:
3942 case RTL_GIGA_MAC_VER_47:
3943 rtl8168h_1_hw_phy_config(tp);
3944 break;
3945 case RTL_GIGA_MAC_VER_46:
3946 case RTL_GIGA_MAC_VER_48:
3947 rtl8168h_2_hw_phy_config(tp);
3948 break;
c558386b
HW		 3949
3950 case RTL_GIGA_MAC_VER_41:
5615d9f1
FR		 3951 default:
3952 break;
3953 }
3954}
3955
da78dbff 3956static void rtl_phy_work(struct rtl8169_private *tp)
1da177e4 3957{
1da177e4
LT		 3958 struct timer_list *timer = &tp->timer;
3959 void __iomem *ioaddr = tp->mmio_addr;
3960 unsigned long timeout = RTL8169_PHY_TIMEOUT;
3961
bcf0bf90 3962 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 3963
4da19633 3964 if (tp->phy_reset_pending(tp)) {
5b0384f4 3965 /*
1da177e4
LT		 3966 * A busy loop could burn quite a few cycles on nowadays CPU.
3967 * Let's delay the execution of the timer for a few ticks.
3968 */
3969 timeout = HZ/10;
3970 goto out_mod_timer;
3971 }
3972
3973 if (tp->link_ok(ioaddr))
da78dbff 3974 return;
1da177e4 3975
9bb8eeb5 3976 netif_dbg(tp, link, tp->dev, "PHY reset until link up\n");
1da177e4 3977
4da19633 3978 tp->phy_reset_enable(tp);
1da177e4
LT		 3979
3980out_mod_timer:
3981 mod_timer(timer, jiffies + timeout);
da78dbff
FR		 3982}
3983
3984static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3985{
da78dbff
FR		 3986 if (!test_and_set_bit(flag, tp->wk.flags))
3987 schedule_work(&tp->wk.work);
da78dbff
FR		 3988}
3989
3990static void rtl8169_phy_timer(unsigned long __opaque)
3991{
3992 struct net_device *dev = (struct net_device *)__opaque;
3993 struct rtl8169_private *tp = netdev_priv(dev);
3994
98ddf986 3995 rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
1da177e4
LT		 3996}
3997
1da177e4
LT		 3998static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3999 void __iomem *ioaddr)
4000{
4001 iounmap(ioaddr);
4002 pci_release_regions(pdev);
87aeec76 4003 pci_clear_mwi(pdev);
1da177e4
LT		 4004 pci_disable_device(pdev);
4005 free_netdev(dev);
4006}
4007
ffc46952
FR		 4008DECLARE_RTL_COND(rtl_phy_reset_cond)
4009{
4010 return tp->phy_reset_pending(tp);
4011}
4012
bf793295
FR		 4013static void rtl8169_phy_reset(struct net_device *dev,
4014 struct rtl8169_private *tp)
4015{
4da19633 4016 tp->phy_reset_enable(tp);
ffc46952 4017 rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100);
bf793295
FR		 4018}
4019
2544bfc0
FR		 4020static bool rtl_tbi_enabled(struct rtl8169_private *tp)
4021{
4022 void __iomem *ioaddr = tp->mmio_addr;
4023
4024 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
4025 (RTL_R8(PHYstatus) & TBI_Enable);
4026}
4027
4ff96fa6
FR		 4028static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
4029{
4030 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 4031
5615d9f1 4032 rtl_hw_phy_config(dev);
4ff96fa6 4033
77332894
MS		 4034 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
4035 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4036 RTL_W8(0x82, 0x01);
4037 }
4ff96fa6 4038
6dccd16b
FR		 4039 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
4040
4041 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
4042 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 4043
bcf0bf90 4044 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 4045 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4046 RTL_W8(0x82, 0x01);
4047 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4da19633 4048 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4ff96fa6
FR		 4049 }
4050
bf793295
FR		 4051 rtl8169_phy_reset(dev, tp);
4052
54405cde 4053 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
cecb5fd7
FR		 4054 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4055 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4056 (tp->mii.supports_gmii ?
4057 ADVERTISED_1000baseT_Half |
4058 ADVERTISED_1000baseT_Full : 0));
4ff96fa6 4059
2544bfc0 4060 if (rtl_tbi_enabled(tp))
bf82c189 4061 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4ff96fa6
FR		 4062}
4063
773d2021
FR		 4064static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4065{
4066 void __iomem *ioaddr = tp->mmio_addr;
773d2021 4067
da78dbff 4068 rtl_lock_work(tp);
773d2021
FR		 4069
4070 RTL_W8(Cfg9346, Cfg9346_Unlock);
908ba2bf 4071
9ecb9aab 4072 RTL_W32(MAC4, addr[4] | addr[5] << 8);
908ba2bf 4073 RTL_R32(MAC4);
4074
9ecb9aab 4075 RTL_W32(MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
908ba2bf 4076 RTL_R32(MAC0);
4077
9ecb9aab 4078 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4079 rtl_rar_exgmac_set(tp, addr);
c28aa385 4080
773d2021
FR		 4081 RTL_W8(Cfg9346, Cfg9346_Lock);
4082
da78dbff 4083 rtl_unlock_work(tp);
773d2021
FR		 4084}
4085
4086static int rtl_set_mac_address(struct net_device *dev, void *p)
4087{
4088 struct rtl8169_private *tp = netdev_priv(dev);
4089 struct sockaddr *addr = p;
4090
4091 if (!is_valid_ether_addr(addr->sa_data))
4092 return -EADDRNOTAVAIL;
4093
4094 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
4095
4096 rtl_rar_set(tp, dev->dev_addr);
4097
4098 return 0;
4099}
4100
5f787a1a
FR		 4101static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4102{
4103 struct rtl8169_private *tp = netdev_priv(dev);
4104 struct mii_ioctl_data *data = if_mii(ifr);
4105
8b4ab28d
FR		 4106 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
4107}
5f787a1a 4108
cecb5fd7
FR		 4109static int rtl_xmii_ioctl(struct rtl8169_private *tp,
4110 struct mii_ioctl_data *data, int cmd)
8b4ab28d 4111{
5f787a1a
FR		 4112 switch (cmd) {
4113 case SIOCGMIIPHY:
4114 data->phy_id = 32; /* Internal PHY */
4115 return 0;
4116
4117 case SIOCGMIIREG:
4da19633 4118 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
5f787a1a
FR		 4119 return 0;
4120
4121 case SIOCSMIIREG:
4da19633 4122 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
5f787a1a
FR		 4123 return 0;
4124 }
4125 return -EOPNOTSUPP;
4126}
4127
8b4ab28d
FR		 4128static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
4129{
4130 return -EOPNOTSUPP;
4131}
4132
fbac58fc
FR		 4133static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
4134{
4135 if (tp->features & RTL_FEATURE_MSI) {
4136 pci_disable_msi(pdev);
4137 tp->features &= ~RTL_FEATURE_MSI;
4138 }
4139}
4140
baf63293 4141static void rtl_init_mdio_ops(struct rtl8169_private *tp)
c0e45c1c 4142{
4143 struct mdio_ops *ops = &tp->mdio_ops;
4144
4145 switch (tp->mac_version) {
4146 case RTL_GIGA_MAC_VER_27:
4147 ops->write = r8168dp_1_mdio_write;
4148 ops->read = r8168dp_1_mdio_read;
4149 break;
e6de30d6 4150 case RTL_GIGA_MAC_VER_28:
4804b3b3 4151 case RTL_GIGA_MAC_VER_31:
e6de30d6 4152 ops->write = r8168dp_2_mdio_write;
4153 ops->read = r8168dp_2_mdio_read;
4154 break;
c558386b
HW		 4155 case RTL_GIGA_MAC_VER_40:
4156 case RTL_GIGA_MAC_VER_41:
57538c4a 4157 case RTL_GIGA_MAC_VER_42:
58152cd4 4158 case RTL_GIGA_MAC_VER_43:
45dd95c4 4159 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4160 case RTL_GIGA_MAC_VER_45:
4161 case RTL_GIGA_MAC_VER_46:
4162 case RTL_GIGA_MAC_VER_47:
4163 case RTL_GIGA_MAC_VER_48:
c558386b
HW		 4164 ops->write = r8168g_mdio_write;
4165 ops->read = r8168g_mdio_read;
4166 break;
c0e45c1c 4167 default:
4168 ops->write = r8169_mdio_write;
4169 ops->read = r8169_mdio_read;
4170 break;
4171 }
4172}
4173
e2409d83 4174static void rtl_speed_down(struct rtl8169_private *tp)
4175{
4176 u32 adv;
4177 int lpa;
4178
4179 rtl_writephy(tp, 0x1f, 0x0000);
4180 lpa = rtl_readphy(tp, MII_LPA);
4181
4182 if (lpa & (LPA_10HALF | LPA_10FULL))
4183 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
4184 else if (lpa & (LPA_100HALF | LPA_100FULL))
4185 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4186 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4187 else
4188 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4189 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4190 (tp->mii.supports_gmii ?
4191 ADVERTISED_1000baseT_Half |
4192 ADVERTISED_1000baseT_Full : 0);
4193
4194 rtl8169_set_speed(tp->dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
4195 adv);
4196}
4197
649b3b8c 4198static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4199{
4200 void __iomem *ioaddr = tp->mmio_addr;
4201
4202 switch (tp->mac_version) {
b00e69de
CB		 4203 case RTL_GIGA_MAC_VER_25:
4204 case RTL_GIGA_MAC_VER_26:
649b3b8c 4205 case RTL_GIGA_MAC_VER_29:
4206 case RTL_GIGA_MAC_VER_30:
4207 case RTL_GIGA_MAC_VER_32:
4208 case RTL_GIGA_MAC_VER_33:
4209 case RTL_GIGA_MAC_VER_34:
7e18dca1 4210 case RTL_GIGA_MAC_VER_37:
b3d7b2f2 4211 case RTL_GIGA_MAC_VER_38:
5598bfe5 4212 case RTL_GIGA_MAC_VER_39:
c558386b
HW		 4213 case RTL_GIGA_MAC_VER_40:
4214 case RTL_GIGA_MAC_VER_41:
57538c4a 4215 case RTL_GIGA_MAC_VER_42:
58152cd4 4216 case RTL_GIGA_MAC_VER_43:
45dd95c4 4217 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4218 case RTL_GIGA_MAC_VER_45:
4219 case RTL_GIGA_MAC_VER_46:
4220 case RTL_GIGA_MAC_VER_47:
4221 case RTL_GIGA_MAC_VER_48:
649b3b8c 4222 RTL_W32(RxConfig, RTL_R32(RxConfig) |
4223 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4224 break;
4225 default:
4226 break;
4227 }
4228}
4229
4230static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
4231{
4232 if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
4233 return false;
4234
e2409d83 4235 rtl_speed_down(tp);
649b3b8c 4236 rtl_wol_suspend_quirk(tp);
4237
4238 return true;
4239}
4240
065c27c1 4241static void r810x_phy_power_down(struct rtl8169_private *tp)
4242{
4243 rtl_writephy(tp, 0x1f, 0x0000);
4244 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4245}
4246
4247static void r810x_phy_power_up(struct rtl8169_private *tp)
4248{
4249 rtl_writephy(tp, 0x1f, 0x0000);
4250 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4251}
4252
4253static void r810x_pll_power_down(struct rtl8169_private *tp)
4254{
0004299a
HW		 4255 void __iomem *ioaddr = tp->mmio_addr;
4256
649b3b8c 4257 if (rtl_wol_pll_power_down(tp))
065c27c1 4258 return;
065c27c1 4259
4260 r810x_phy_power_down(tp);
0004299a
HW		 4261
4262 switch (tp->mac_version) {
4263 case RTL_GIGA_MAC_VER_07:
4264 case RTL_GIGA_MAC_VER_08:
4265 case RTL_GIGA_MAC_VER_09:
4266 case RTL_GIGA_MAC_VER_10:
4267 case RTL_GIGA_MAC_VER_13:
4268 case RTL_GIGA_MAC_VER_16:
4269 break;
4270 default:
4271 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4272 break;
4273 }
065c27c1 4274}
4275
4276static void r810x_pll_power_up(struct rtl8169_private *tp)
4277{
0004299a
HW		 4278 void __iomem *ioaddr = tp->mmio_addr;
4279
065c27c1 4280 r810x_phy_power_up(tp);
0004299a
HW		 4281
4282 switch (tp->mac_version) {
4283 case RTL_GIGA_MAC_VER_07:
4284 case RTL_GIGA_MAC_VER_08:
4285 case RTL_GIGA_MAC_VER_09:
4286 case RTL_GIGA_MAC_VER_10:
4287 case RTL_GIGA_MAC_VER_13:
4288 case RTL_GIGA_MAC_VER_16:
4289 break;
6e1d0b89
CHL		 4290 case RTL_GIGA_MAC_VER_47:
4291 case RTL_GIGA_MAC_VER_48:
05b9687b 4292 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
6e1d0b89 4293 break;
0004299a
HW		 4294 default:
4295 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4296 break;
4297 }
065c27c1 4298}
4299
4300static void r8168_phy_power_up(struct rtl8169_private *tp)
4301{
4302 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 4303 switch (tp->mac_version) {
4304 case RTL_GIGA_MAC_VER_11:
4305 case RTL_GIGA_MAC_VER_12:
4306 case RTL_GIGA_MAC_VER_17:
4307 case RTL_GIGA_MAC_VER_18:
4308 case RTL_GIGA_MAC_VER_19:
4309 case RTL_GIGA_MAC_VER_20:
4310 case RTL_GIGA_MAC_VER_21:
4311 case RTL_GIGA_MAC_VER_22:
4312 case RTL_GIGA_MAC_VER_23:
4313 case RTL_GIGA_MAC_VER_24:
4314 case RTL_GIGA_MAC_VER_25:
4315 case RTL_GIGA_MAC_VER_26:
4316 case RTL_GIGA_MAC_VER_27:
4317 case RTL_GIGA_MAC_VER_28:
4318 case RTL_GIGA_MAC_VER_31:
4319 rtl_writephy(tp, 0x0e, 0x0000);
4320 break;
4321 default:
4322 break;
4323 }
065c27c1 4324 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4325}
4326
4327static void r8168_phy_power_down(struct rtl8169_private *tp)
4328{
4329 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 4330 switch (tp->mac_version) {
4331 case RTL_GIGA_MAC_VER_32:
4332 case RTL_GIGA_MAC_VER_33:
beb330a4 4333 case RTL_GIGA_MAC_VER_40:
4334 case RTL_GIGA_MAC_VER_41:
01dc7fec 4335 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
4336 break;
4337
4338 case RTL_GIGA_MAC_VER_11:
4339 case RTL_GIGA_MAC_VER_12:
4340 case RTL_GIGA_MAC_VER_17:
4341 case RTL_GIGA_MAC_VER_18:
4342 case RTL_GIGA_MAC_VER_19:
4343 case RTL_GIGA_MAC_VER_20:
4344 case RTL_GIGA_MAC_VER_21:
4345 case RTL_GIGA_MAC_VER_22:
4346 case RTL_GIGA_MAC_VER_23:
4347 case RTL_GIGA_MAC_VER_24:
4348 case RTL_GIGA_MAC_VER_25:
4349 case RTL_GIGA_MAC_VER_26:
4350 case RTL_GIGA_MAC_VER_27:
4351 case RTL_GIGA_MAC_VER_28:
4352 case RTL_GIGA_MAC_VER_31:
4353 rtl_writephy(tp, 0x0e, 0x0200);
4354 default:
4355 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4356 break;
4357 }
065c27c1 4358}
4359
4360static void r8168_pll_power_down(struct rtl8169_private *tp)
4361{
4362 void __iomem *ioaddr = tp->mmio_addr;
4363
cecb5fd7
FR		 4364 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4365 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4366 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
4804b3b3 4367 r8168dp_check_dash(tp)) {
065c27c1 4368 return;
5d2e1957 4369 }
065c27c1 4370
cecb5fd7
FR		 4371 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
4372 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
065c27c1 4373 (RTL_R16(CPlusCmd) & ASF)) {
4374 return;
4375 }
4376
01dc7fec 4377 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4378 tp->mac_version == RTL_GIGA_MAC_VER_33)
fdf6fc06 4379 rtl_ephy_write(tp, 0x19, 0xff64);
01dc7fec 4380
649b3b8c 4381 if (rtl_wol_pll_power_down(tp))
065c27c1 4382 return;
065c27c1 4383
4384 r8168_phy_power_down(tp);
4385
4386 switch (tp->mac_version) {
4387 case RTL_GIGA_MAC_VER_25:
4388 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 4389 case RTL_GIGA_MAC_VER_27:
4390 case RTL_GIGA_MAC_VER_28:
4804b3b3 4391 case RTL_GIGA_MAC_VER_31:
01dc7fec 4392 case RTL_GIGA_MAC_VER_32:
4393 case RTL_GIGA_MAC_VER_33:
42fde737 4394 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4395 case RTL_GIGA_MAC_VER_45:
4396 case RTL_GIGA_MAC_VER_46:
065c27c1 4397 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4398 break;
beb330a4 4399 case RTL_GIGA_MAC_VER_40:
4400 case RTL_GIGA_MAC_VER_41:
4401 rtl_w1w0_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
4402 0xfc000000, ERIAR_EXGMAC);
b8e5e6ad 4403 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
beb330a4 4404 break;
065c27c1 4405 }
4406}
4407
4408static void r8168_pll_power_up(struct rtl8169_private *tp)
4409{
4410 void __iomem *ioaddr = tp->mmio_addr;
4411
065c27c1 4412 switch (tp->mac_version) {
4413 case RTL_GIGA_MAC_VER_25:
4414 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 4415 case RTL_GIGA_MAC_VER_27:
4416 case RTL_GIGA_MAC_VER_28:
4804b3b3 4417 case RTL_GIGA_MAC_VER_31:
01dc7fec 4418 case RTL_GIGA_MAC_VER_32:
4419 case RTL_GIGA_MAC_VER_33:
065c27c1 4420 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4421 break;
42fde737 4422 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4423 case RTL_GIGA_MAC_VER_45:
4424 case RTL_GIGA_MAC_VER_46:
05b9687b 4425 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
6e1d0b89 4426 break;
beb330a4 4427 case RTL_GIGA_MAC_VER_40:
4428 case RTL_GIGA_MAC_VER_41:
b8e5e6ad 4429 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
beb330a4 4430 rtl_w1w0_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
4431 0x00000000, ERIAR_EXGMAC);
4432 break;
065c27c1 4433 }
4434
4435 r8168_phy_power_up(tp);
4436}
4437
d58d46b5
FR		 4438static void rtl_generic_op(struct rtl8169_private *tp,
4439 void (*op)(struct rtl8169_private *))
065c27c1 4440{
4441 if (op)
4442 op(tp);
4443}
4444
4445static void rtl_pll_power_down(struct rtl8169_private *tp)
4446{
d58d46b5 4447 rtl_generic_op(tp, tp->pll_power_ops.down);
065c27c1 4448}
4449
4450static void rtl_pll_power_up(struct rtl8169_private *tp)
4451{
d58d46b5 4452 rtl_generic_op(tp, tp->pll_power_ops.up);
065c27c1 4453}
4454
baf63293 4455static void rtl_init_pll_power_ops(struct rtl8169_private *tp)
065c27c1 4456{
4457 struct pll_power_ops *ops = &tp->pll_power_ops;
4458
4459 switch (tp->mac_version) {
4460 case RTL_GIGA_MAC_VER_07:
4461 case RTL_GIGA_MAC_VER_08:
4462 case RTL_GIGA_MAC_VER_09:
4463 case RTL_GIGA_MAC_VER_10:
4464 case RTL_GIGA_MAC_VER_16:
5a5e4443
HW		 4465 case RTL_GIGA_MAC_VER_29:
4466 case RTL_GIGA_MAC_VER_30:
7e18dca1 4467 case RTL_GIGA_MAC_VER_37:
5598bfe5 4468 case RTL_GIGA_MAC_VER_39:
58152cd4 4469 case RTL_GIGA_MAC_VER_43:
6e1d0b89
CHL		 4470 case RTL_GIGA_MAC_VER_47:
4471 case RTL_GIGA_MAC_VER_48:
065c27c1 4472 ops->down = r810x_pll_power_down;
4473 ops->up = r810x_pll_power_up;
4474 break;
4475
4476 case RTL_GIGA_MAC_VER_11:
4477 case RTL_GIGA_MAC_VER_12:
4478 case RTL_GIGA_MAC_VER_17:
4479 case RTL_GIGA_MAC_VER_18:
4480 case RTL_GIGA_MAC_VER_19:
4481 case RTL_GIGA_MAC_VER_20:
4482 case RTL_GIGA_MAC_VER_21:
4483 case RTL_GIGA_MAC_VER_22:
4484 case RTL_GIGA_MAC_VER_23:
4485 case RTL_GIGA_MAC_VER_24:
4486 case RTL_GIGA_MAC_VER_25:
4487 case RTL_GIGA_MAC_VER_26:
4488 case RTL_GIGA_MAC_VER_27:
e6de30d6 4489 case RTL_GIGA_MAC_VER_28:
4804b3b3 4490 case RTL_GIGA_MAC_VER_31:
01dc7fec 4491 case RTL_GIGA_MAC_VER_32:
4492 case RTL_GIGA_MAC_VER_33:
70090424 4493 case RTL_GIGA_MAC_VER_34:
c2218925
HW		 4494 case RTL_GIGA_MAC_VER_35:
4495 case RTL_GIGA_MAC_VER_36:
b3d7b2f2 4496 case RTL_GIGA_MAC_VER_38:
c558386b
HW		 4497 case RTL_GIGA_MAC_VER_40:
4498 case RTL_GIGA_MAC_VER_41:
57538c4a 4499 case RTL_GIGA_MAC_VER_42:
45dd95c4 4500 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4501 case RTL_GIGA_MAC_VER_45:
4502 case RTL_GIGA_MAC_VER_46:
065c27c1 4503 ops->down = r8168_pll_power_down;
4504 ops->up = r8168_pll_power_up;
4505 break;
4506
4507 default:
4508 ops->down = NULL;
4509 ops->up = NULL;
4510 break;
4511 }
4512}
4513
e542a226
HW		 4514static void rtl_init_rxcfg(struct rtl8169_private *tp)
4515{
4516 void __iomem *ioaddr = tp->mmio_addr;
4517
4518 switch (tp->mac_version) {
4519 case RTL_GIGA_MAC_VER_01:
4520 case RTL_GIGA_MAC_VER_02:
4521 case RTL_GIGA_MAC_VER_03:
4522 case RTL_GIGA_MAC_VER_04:
4523 case RTL_GIGA_MAC_VER_05:
4524 case RTL_GIGA_MAC_VER_06:
4525 case RTL_GIGA_MAC_VER_10:
4526 case RTL_GIGA_MAC_VER_11:
4527 case RTL_GIGA_MAC_VER_12:
4528 case RTL_GIGA_MAC_VER_13:
4529 case RTL_GIGA_MAC_VER_14:
4530 case RTL_GIGA_MAC_VER_15:
4531 case RTL_GIGA_MAC_VER_16:
4532 case RTL_GIGA_MAC_VER_17:
4533 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4534 break;
4535 case RTL_GIGA_MAC_VER_18:
4536 case RTL_GIGA_MAC_VER_19:
4537 case RTL_GIGA_MAC_VER_20:
4538 case RTL_GIGA_MAC_VER_21:
4539 case RTL_GIGA_MAC_VER_22:
4540 case RTL_GIGA_MAC_VER_23:
4541 case RTL_GIGA_MAC_VER_24:
eb2dc35d 4542 case RTL_GIGA_MAC_VER_34:
3ced8c95 4543 case RTL_GIGA_MAC_VER_35:
e542a226
HW		 4544 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4545 break;
beb330a4 4546 case RTL_GIGA_MAC_VER_40:
7a9810e7
MD		 4547 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
4548 break;
beb330a4 4549 case RTL_GIGA_MAC_VER_41:
57538c4a 4550 case RTL_GIGA_MAC_VER_42:
58152cd4 4551 case RTL_GIGA_MAC_VER_43:
45dd95c4 4552 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4553 case RTL_GIGA_MAC_VER_45:
4554 case RTL_GIGA_MAC_VER_46:
4555 case RTL_GIGA_MAC_VER_47:
4556 case RTL_GIGA_MAC_VER_48:
beb330a4 4557 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST | RX_EARLY_OFF);
4558 break;
e542a226
HW		 4559 default:
4560 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
4561 break;
4562 }
4563}
4564
92fc43b4
HW		 4565static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4566{
9fba0812 4567 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
92fc43b4
HW		 4568}
4569
d58d46b5
FR		 4570static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4571{
9c5028e9 4572 void __iomem *ioaddr = tp->mmio_addr;
4573
4574 RTL_W8(Cfg9346, Cfg9346_Unlock);
d58d46b5 4575 rtl_generic_op(tp, tp->jumbo_ops.enable);
9c5028e9 4576 RTL_W8(Cfg9346, Cfg9346_Lock);
d58d46b5
FR		 4577}
4578
4579static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4580{
9c5028e9 4581 void __iomem *ioaddr = tp->mmio_addr;
4582
4583 RTL_W8(Cfg9346, Cfg9346_Unlock);
d58d46b5 4584 rtl_generic_op(tp, tp->jumbo_ops.disable);
9c5028e9 4585 RTL_W8(Cfg9346, Cfg9346_Lock);
d58d46b5
FR		 4586}
4587
4588static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4589{
4590 void __iomem *ioaddr = tp->mmio_addr;
4591
4592 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4593 RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
4594 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
4595}
4596
4597static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4598{
4599 void __iomem *ioaddr = tp->mmio_addr;
4600
4601 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4602 RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
4603 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
4604}
4605
4606static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4607{
4608 void __iomem *ioaddr = tp->mmio_addr;
4609
4610 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4611}
4612
4613static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4614{
4615 void __iomem *ioaddr = tp->mmio_addr;
4616
4617 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4618}
4619
4620static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4621{
4622 void __iomem *ioaddr = tp->mmio_addr;
d58d46b5
FR		 4623
4624 RTL_W8(MaxTxPacketSize, 0x3f);
4625 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4626 RTL_W8(Config4, RTL_R8(Config4) | 0x01);
4512ff9f 4627 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
d58d46b5
FR		 4628}
4629
4630static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4631{
4632 void __iomem *ioaddr = tp->mmio_addr;
d58d46b5
FR		 4633
4634 RTL_W8(MaxTxPacketSize, 0x0c);
4635 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4636 RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
4512ff9f 4637 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
d58d46b5
FR		 4638}
4639
4640static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4641{
4642 rtl_tx_performance_tweak(tp->pci_dev,
4643 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4644}
4645
4646static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4647{
4648 rtl_tx_performance_tweak(tp->pci_dev,
4649 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4650}
4651
4652static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4653{
4654 void __iomem *ioaddr = tp->mmio_addr;
4655
4656 r8168b_0_hw_jumbo_enable(tp);
4657
4658 RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
4659}
4660
4661static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4662{
4663 void __iomem *ioaddr = tp->mmio_addr;
4664
4665 r8168b_0_hw_jumbo_disable(tp);
4666
4667 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4668}
4669
baf63293 4670static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
d58d46b5
FR		 4671{
4672 struct jumbo_ops *ops = &tp->jumbo_ops;
4673
4674 switch (tp->mac_version) {
4675 case RTL_GIGA_MAC_VER_11:
4676 ops->disable = r8168b_0_hw_jumbo_disable;
4677 ops->enable = r8168b_0_hw_jumbo_enable;
4678 break;
4679 case RTL_GIGA_MAC_VER_12:
4680 case RTL_GIGA_MAC_VER_17:
4681 ops->disable = r8168b_1_hw_jumbo_disable;
4682 ops->enable = r8168b_1_hw_jumbo_enable;
4683 break;
4684 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
4685 case RTL_GIGA_MAC_VER_19:
4686 case RTL_GIGA_MAC_VER_20:
4687 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
4688 case RTL_GIGA_MAC_VER_22:
4689 case RTL_GIGA_MAC_VER_23:
4690 case RTL_GIGA_MAC_VER_24:
4691 case RTL_GIGA_MAC_VER_25:
4692 case RTL_GIGA_MAC_VER_26:
4693 ops->disable = r8168c_hw_jumbo_disable;
4694 ops->enable = r8168c_hw_jumbo_enable;
4695 break;
4696 case RTL_GIGA_MAC_VER_27:
4697 case RTL_GIGA_MAC_VER_28:
4698 ops->disable = r8168dp_hw_jumbo_disable;
4699 ops->enable = r8168dp_hw_jumbo_enable;
4700 break;
4701 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
4702 case RTL_GIGA_MAC_VER_32:
4703 case RTL_GIGA_MAC_VER_33:
4704 case RTL_GIGA_MAC_VER_34:
4705 ops->disable = r8168e_hw_jumbo_disable;
4706 ops->enable = r8168e_hw_jumbo_enable;
4707 break;
4708
4709 /*
4710 * No action needed for jumbo frames with 8169.
4711 * No jumbo for 810x at all.
4712 */
c558386b
HW		 4713 case RTL_GIGA_MAC_VER_40:
4714 case RTL_GIGA_MAC_VER_41:
57538c4a 4715 case RTL_GIGA_MAC_VER_42:
58152cd4 4716 case RTL_GIGA_MAC_VER_43:
45dd95c4 4717 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4718 case RTL_GIGA_MAC_VER_45:
4719 case RTL_GIGA_MAC_VER_46:
4720 case RTL_GIGA_MAC_VER_47:
4721 case RTL_GIGA_MAC_VER_48:
d58d46b5
FR		 4722 default:
4723 ops->disable = NULL;
4724 ops->enable = NULL;
4725 break;
4726 }
4727}
4728
ffc46952
FR		 4729DECLARE_RTL_COND(rtl_chipcmd_cond)
4730{
4731 void __iomem *ioaddr = tp->mmio_addr;
4732
4733 return RTL_R8(ChipCmd) & CmdReset;
4734}
4735
6f43adc8
FR		 4736static void rtl_hw_reset(struct rtl8169_private *tp)
4737{
4738 void __iomem *ioaddr = tp->mmio_addr;
6f43adc8 4739
6f43adc8
FR		 4740 RTL_W8(ChipCmd, CmdReset);
4741
ffc46952 4742 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
6f43adc8
FR		 4743}
4744
b6ffd97f 4745static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
953a12cc 4746{
b6ffd97f
FR		 4747 struct rtl_fw *rtl_fw;
4748 const char *name;
4749 int rc = -ENOMEM;
953a12cc 4750
b6ffd97f
FR		 4751 name = rtl_lookup_firmware_name(tp);
4752 if (!name)
4753 goto out_no_firmware;
953a12cc 4754
b6ffd97f
FR		 4755 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4756 if (!rtl_fw)
4757 goto err_warn;
31bd204f 4758
b6ffd97f
FR		 4759 rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
4760 if (rc < 0)
4761 goto err_free;
4762
fd112f2e
FR		 4763 rc = rtl_check_firmware(tp, rtl_fw);
4764 if (rc < 0)
4765 goto err_release_firmware;
4766
b6ffd97f
FR		 4767 tp->rtl_fw = rtl_fw;
4768out:
4769 return;
4770
fd112f2e
FR		 4771err_release_firmware:
4772 release_firmware(rtl_fw->fw);
b6ffd97f
FR		 4773err_free:
4774 kfree(rtl_fw);
4775err_warn:
4776 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4777 name, rc);
4778out_no_firmware:
4779 tp->rtl_fw = NULL;
4780 goto out;
4781}
4782
4783static void rtl_request_firmware(struct rtl8169_private *tp)
4784{
4785 if (IS_ERR(tp->rtl_fw))
4786 rtl_request_uncached_firmware(tp);
953a12cc
FR		 4787}
4788
92fc43b4
HW		 4789static void rtl_rx_close(struct rtl8169_private *tp)
4790{
4791 void __iomem *ioaddr = tp->mmio_addr;
92fc43b4 4792
1687b566 4793 RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
92fc43b4
HW		 4794}
4795
ffc46952
FR		 4796DECLARE_RTL_COND(rtl_npq_cond)
4797{
4798 void __iomem *ioaddr = tp->mmio_addr;
4799
4800 return RTL_R8(TxPoll) & NPQ;
4801}
4802
4803DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4804{
4805 void __iomem *ioaddr = tp->mmio_addr;
4806
4807 return RTL_R32(TxConfig) & TXCFG_EMPTY;
4808}
4809
e6de30d6 4810static void rtl8169_hw_reset(struct rtl8169_private *tp)
1da177e4 4811{
e6de30d6 4812 void __iomem *ioaddr = tp->mmio_addr;
4813
1da177e4 4814 /* Disable interrupts */
811fd301 4815 rtl8169_irq_mask_and_ack(tp);
1da177e4 4816
92fc43b4
HW		 4817 rtl_rx_close(tp);
4818
5d2e1957 4819 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4804b3b3 4820 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4821 tp->mac_version == RTL_GIGA_MAC_VER_31) {
ffc46952 4822 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
c2218925 4823 } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
6e1d0b89
CHL		 4824 tp->mac_version == RTL_GIGA_MAC_VER_35 ||
4825 tp->mac_version == RTL_GIGA_MAC_VER_36 ||
4826 tp->mac_version == RTL_GIGA_MAC_VER_37 ||
4827 tp->mac_version == RTL_GIGA_MAC_VER_38 ||
4828 tp->mac_version == RTL_GIGA_MAC_VER_40 ||
4829 tp->mac_version == RTL_GIGA_MAC_VER_41 ||
4830 tp->mac_version == RTL_GIGA_MAC_VER_42 ||
4831 tp->mac_version == RTL_GIGA_MAC_VER_43 ||
4832 tp->mac_version == RTL_GIGA_MAC_VER_44 ||
4833 tp->mac_version == RTL_GIGA_MAC_VER_45 ||
4834 tp->mac_version == RTL_GIGA_MAC_VER_46 ||
4835 tp->mac_version == RTL_GIGA_MAC_VER_47 ||
4836 tp->mac_version == RTL_GIGA_MAC_VER_48) {
c2b0c1e7 4837 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
ffc46952 4838 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
92fc43b4
HW		 4839 } else {
4840 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4841 udelay(100);
e6de30d6 4842 }
4843
92fc43b4 4844 rtl_hw_reset(tp);
1da177e4
LT		 4845}
4846
7f796d83 4847static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 4848{
4849 void __iomem *ioaddr = tp->mmio_addr;
9cb427b6
FR		 4850
4851 /* Set DMA burst size and Interframe Gap Time */
4852 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4853 (InterFrameGap << TxInterFrameGapShift));
4854}
4855
07ce4064 4856static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 4857{
4858 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 4859
07ce4064
FR		 4860 tp->hw_start(dev);
4861
da78dbff 4862 rtl_irq_enable_all(tp);
07ce4064
FR		 4863}
4864
7f796d83
FR		 4865static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
4866 void __iomem *ioaddr)
4867{
4868 /*
4869 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4870 * register to be written before TxDescAddrLow to work.
4871 * Switching from MMIO to I/O access fixes the issue as well.
4872 */
4873 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
284901a9 4874 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
7f796d83 4875 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
284901a9 4876 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 4877}
4878
4879static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4880{
4881 u16 cmd;
4882
4883 cmd = RTL_R16(CPlusCmd);
4884 RTL_W16(CPlusCmd, cmd);
4885 return cmd;
4886}
4887
fdd7b4c3 4888static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
7f796d83
FR		 4889{
4890 /* Low hurts. Let's disable the filtering. */
207d6e87 4891 RTL_W16(RxMaxSize, rx_buf_sz + 1);
7f796d83
FR		 4892}
4893
6dccd16b
FR		 4894static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4895{
3744100e 4896 static const struct rtl_cfg2_info {
6dccd16b
FR		 4897 u32 mac_version;
4898 u32 clk;
4899 u32 val;
4900 } cfg2_info [] = {
4901 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4902 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4903 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4904 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3744100e
FR		 4905 };
4906 const struct rtl_cfg2_info *p = cfg2_info;
6dccd16b
FR		 4907 unsigned int i;
4908 u32 clk;
4909
4910 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 4911 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 4912 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4913 RTL_W32(0x7c, p->val);
4914 break;
4915 }
4916 }
4917}
4918
e6b763ea
FR		 4919static void rtl_set_rx_mode(struct net_device *dev)
4920{
4921 struct rtl8169_private *tp = netdev_priv(dev);
4922 void __iomem *ioaddr = tp->mmio_addr;
4923 u32 mc_filter[2]; /* Multicast hash filter */
4924 int rx_mode;
4925 u32 tmp = 0;
4926
4927 if (dev->flags & IFF_PROMISC) {
4928 /* Unconditionally log net taps. */
4929 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4930 rx_mode =
4931 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4932 AcceptAllPhys;
4933 mc_filter[1] = mc_filter[0] = 0xffffffff;
4934 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4935 (dev->flags & IFF_ALLMULTI)) {
4936 /* Too many to filter perfectly -- accept all multicasts. */
4937 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4938 mc_filter[1] = mc_filter[0] = 0xffffffff;
4939 } else {
4940 struct netdev_hw_addr *ha;
4941
4942 rx_mode = AcceptBroadcast | AcceptMyPhys;
4943 mc_filter[1] = mc_filter[0] = 0;
4944 netdev_for_each_mc_addr(ha, dev) {
4945 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4946 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4947 rx_mode |= AcceptMulticast;
4948 }
4949 }
4950
4951 if (dev->features & NETIF_F_RXALL)
4952 rx_mode |= (AcceptErr | AcceptRunt);
4953
4954 tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4955
4956 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4957 u32 data = mc_filter[0];
4958
4959 mc_filter[0] = swab32(mc_filter[1]);
4960 mc_filter[1] = swab32(data);
4961 }
4962
0481776b
NW		 4963 if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4964 mc_filter[1] = mc_filter[0] = 0xffffffff;
4965
e6b763ea
FR		 4966 RTL_W32(MAR0 + 4, mc_filter[1]);
4967 RTL_W32(MAR0 + 0, mc_filter[0]);
4968
4969 RTL_W32(RxConfig, tmp);
4970}
4971
07ce4064
FR		 4972static void rtl_hw_start_8169(struct net_device *dev)
4973{
4974 struct rtl8169_private *tp = netdev_priv(dev);
4975 void __iomem *ioaddr = tp->mmio_addr;
4976 struct pci_dev *pdev = tp->pci_dev;
07ce4064 4977
9cb427b6
FR		 4978 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4979 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4980 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4981 }
4982
1da177e4 4983 RTL_W8(Cfg9346, Cfg9346_Unlock);
cecb5fd7
FR		 4984 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4985 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4986 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4987 tp->mac_version == RTL_GIGA_MAC_VER_04)
9cb427b6
FR		 4988 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4989
e542a226
HW		 4990 rtl_init_rxcfg(tp);
4991
f0298f81 4992 RTL_W8(EarlyTxThres, NoEarlyTx);
1da177e4 4993
6f0333b8 4994 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
1da177e4 4995
cecb5fd7
FR		 4996 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4997 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4998 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4999 tp->mac_version == RTL_GIGA_MAC_VER_04)
c946b304 5000 rtl_set_rx_tx_config_registers(tp);
1da177e4 5001
7f796d83 5002 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 5003
cecb5fd7
FR		 5004 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5005 tp->mac_version == RTL_GIGA_MAC_VER_03) {
05b9687b 5006 dprintk("Set MAC Reg C+CR Offset 0xe0. "
1da177e4 5007 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 5008 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 5009 }
5010
bcf0bf90
FR		 5011 RTL_W16(CPlusCmd, tp->cp_cmd);
5012
6dccd16b
FR		 5013 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
5014
1da177e4
LT		 5015 /*
5016 * Undocumented corner. Supposedly:
5017 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
5018 */
5019 RTL_W16(IntrMitigate, 0x0000);
5020
7f796d83 5021 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 5022
cecb5fd7
FR		 5023 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
5024 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
5025 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
5026 tp->mac_version != RTL_GIGA_MAC_VER_04) {
c946b304
FR		 5027 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5028 rtl_set_rx_tx_config_registers(tp);
5029 }
5030
1da177e4 5031 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 5032
5033 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
5034 RTL_R8(IntrMask);
1da177e4
LT		 5035
5036 RTL_W32(RxMissed, 0);
5037
07ce4064 5038 rtl_set_rx_mode(dev);
1da177e4
LT		 5039
5040 /* no early-rx interrupts */
05b9687b 5041 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
07ce4064 5042}
1da177e4 5043
beb1fe18
HW		 5044static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
5045{
5046 if (tp->csi_ops.write)
52989f0e 5047 tp->csi_ops.write(tp, addr, value);
beb1fe18
HW		 5048}
5049
5050static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
5051{
52989f0e 5052 return tp->csi_ops.read ? tp->csi_ops.read(tp, addr) : ~0;
beb1fe18
HW		 5053}
5054
5055static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits)
dacf8154
FR		 5056{
5057 u32 csi;
5058
beb1fe18
HW		 5059 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
5060 rtl_csi_write(tp, 0x070c, csi | bits);
5061}
5062
5063static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
5064{
5065 rtl_csi_access_enable(tp, 0x17000000);
650e8d5d 5066}
5067
beb1fe18 5068static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
e6de30d6 5069{
beb1fe18 5070 rtl_csi_access_enable(tp, 0x27000000);
e6de30d6 5071}
5072
ffc46952
FR		 5073DECLARE_RTL_COND(rtl_csiar_cond)
5074{
5075 void __iomem *ioaddr = tp->mmio_addr;
5076
5077 return RTL_R32(CSIAR) & CSIAR_FLAG;
5078}
5079
52989f0e 5080static void r8169_csi_write(struct rtl8169_private *tp, int addr, int value)
650e8d5d 5081{
52989f0e 5082 void __iomem *ioaddr = tp->mmio_addr;
beb1fe18
HW		 5083
5084 RTL_W32(CSIDR, value);
5085 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5086 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5087
ffc46952 5088 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
beb1fe18
HW		 5089}
5090
52989f0e 5091static u32 r8169_csi_read(struct rtl8169_private *tp, int addr)
beb1fe18 5092{
52989f0e 5093 void __iomem *ioaddr = tp->mmio_addr;
beb1fe18
HW		 5094
5095 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
5096 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5097
ffc46952
FR		 5098 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5099 RTL_R32(CSIDR) : ~0;
beb1fe18
HW		 5100}
5101
52989f0e 5102static void r8402_csi_write(struct rtl8169_private *tp, int addr, int value)
7e18dca1 5103{
52989f0e 5104 void __iomem *ioaddr = tp->mmio_addr;
7e18dca1
HW		 5105
5106 RTL_W32(CSIDR, value);
5107 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5108 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
5109 CSIAR_FUNC_NIC);
5110
ffc46952 5111 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
7e18dca1
HW		 5112}
5113
52989f0e 5114static u32 r8402_csi_read(struct rtl8169_private *tp, int addr)
7e18dca1 5115{
52989f0e 5116 void __iomem *ioaddr = tp->mmio_addr;
7e18dca1
HW		 5117
5118 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
5119 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5120
ffc46952
FR		 5121 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5122 RTL_R32(CSIDR) : ~0;
7e18dca1
HW		 5123}
5124
45dd95c4 5125static void r8411_csi_write(struct rtl8169_private *tp, int addr, int value)
5126{
5127 void __iomem *ioaddr = tp->mmio_addr;
5128
5129 RTL_W32(CSIDR, value);
5130 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5131 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
5132 CSIAR_FUNC_NIC2);
5133
5134 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5135}
5136
5137static u32 r8411_csi_read(struct rtl8169_private *tp, int addr)
5138{
5139 void __iomem *ioaddr = tp->mmio_addr;
5140
5141 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC2 |
5142 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5143
5144 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5145 RTL_R32(CSIDR) : ~0;
5146}
5147
baf63293 5148static void rtl_init_csi_ops(struct rtl8169_private *tp)
beb1fe18
HW		 5149{
5150 struct csi_ops *ops = &tp->csi_ops;
5151
5152 switch (tp->mac_version) {
5153 case RTL_GIGA_MAC_VER_01:
5154 case RTL_GIGA_MAC_VER_02:
5155 case RTL_GIGA_MAC_VER_03:
5156 case RTL_GIGA_MAC_VER_04:
5157 case RTL_GIGA_MAC_VER_05:
5158 case RTL_GIGA_MAC_VER_06:
5159 case RTL_GIGA_MAC_VER_10:
5160 case RTL_GIGA_MAC_VER_11:
5161 case RTL_GIGA_MAC_VER_12:
5162 case RTL_GIGA_MAC_VER_13:
5163 case RTL_GIGA_MAC_VER_14:
5164 case RTL_GIGA_MAC_VER_15:
5165 case RTL_GIGA_MAC_VER_16:
5166 case RTL_GIGA_MAC_VER_17:
5167 ops->write = NULL;
5168 ops->read = NULL;
5169 break;
5170
7e18dca1 5171 case RTL_GIGA_MAC_VER_37:
b3d7b2f2 5172 case RTL_GIGA_MAC_VER_38:
7e18dca1
HW		 5173 ops->write = r8402_csi_write;
5174 ops->read = r8402_csi_read;
5175 break;
5176
45dd95c4 5177 case RTL_GIGA_MAC_VER_44:
5178 ops->write = r8411_csi_write;
5179 ops->read = r8411_csi_read;
5180 break;
5181
beb1fe18
HW		 5182 default:
5183 ops->write = r8169_csi_write;
5184 ops->read = r8169_csi_read;
5185 break;
5186 }
dacf8154
FR		 5187}
5188
5189struct ephy_info {
5190 unsigned int offset;
5191 u16 mask;
5192 u16 bits;
5193};
5194
fdf6fc06
FR		 5195static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
5196 int len)
dacf8154
FR		 5197{
5198 u16 w;
5199
5200 while (len-- > 0) {
fdf6fc06
FR		 5201 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
5202 rtl_ephy_write(tp, e->offset, w);
dacf8154
FR		 5203 e++;
5204 }
5205}
5206
b726e493
FR		 5207static void rtl_disable_clock_request(struct pci_dev *pdev)
5208{
7d7903b2
JL		 5209 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
5210 PCI_EXP_LNKCTL_CLKREQ_EN);
b726e493
FR		 5211}
5212
e6de30d6 5213static void rtl_enable_clock_request(struct pci_dev *pdev)
5214{
7d7903b2
JL		 5215 pcie_capability_set_word(pdev, PCI_EXP_LNKCTL,
5216 PCI_EXP_LNKCTL_CLKREQ_EN);
e6de30d6 5217}
5218
b51ecea8 5219static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable)
5220{
5221 void __iomem *ioaddr = tp->mmio_addr;
5222 u8 data;
5223
5224 data = RTL_R8(Config3);
5225
5226 if (enable)
5227 data |= Rdy_to_L23;
5228 else
5229 data &= ~Rdy_to_L23;
5230
5231 RTL_W8(Config3, data);
5232}
5233
b726e493
FR		 5234#define R8168_CPCMD_QUIRK_MASK (\
5235 EnableBist | \
5236 Mac_dbgo_oe | \
5237 Force_half_dup | \
5238 Force_rxflow_en | \
5239 Force_txflow_en | \
5240 Cxpl_dbg_sel | \
5241 ASF | \
5242 PktCntrDisable | \
5243 Mac_dbgo_sel)
5244
beb1fe18 5245static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
219a1e9d 5246{
beb1fe18
HW		 5247 void __iomem *ioaddr = tp->mmio_addr;
5248 struct pci_dev *pdev = tp->pci_dev;
5249
b726e493
FR		 5250 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5251
5252 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5253
faf1e785 5254 if (tp->dev->mtu <= ETH_DATA_LEN) {
5255 rtl_tx_performance_tweak(pdev, (0x5 << MAX_READ_REQUEST_SHIFT) |
5256 PCI_EXP_DEVCTL_NOSNOOP_EN);
5257 }
219a1e9d
FR		 5258}
5259
beb1fe18 5260static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
219a1e9d 5261{
beb1fe18
HW		 5262 void __iomem *ioaddr = tp->mmio_addr;
5263
5264 rtl_hw_start_8168bb(tp);
b726e493 5265
f0298f81 5266 RTL_W8(MaxTxPacketSize, TxPacketMax);
b726e493
FR		 5267
5268 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
219a1e9d
FR		 5269}
5270
beb1fe18 5271static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
219a1e9d 5272{
beb1fe18
HW		 5273 void __iomem *ioaddr = tp->mmio_addr;
5274 struct pci_dev *pdev = tp->pci_dev;
5275
b726e493
FR		 5276 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
5277
5278 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5279
faf1e785 5280 if (tp->dev->mtu <= ETH_DATA_LEN)
5281 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
b726e493
FR		 5282
5283 rtl_disable_clock_request(pdev);
5284
5285 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
219a1e9d
FR		 5286}
5287
beb1fe18 5288static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
219a1e9d 5289{
350f7596 5290 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 5291 { 0x01, 0, 0x0001 },
5292 { 0x02, 0x0800, 0x1000 },
5293 { 0x03, 0, 0x0042 },
5294 { 0x06, 0x0080, 0x0000 },
5295 { 0x07, 0, 0x2000 }
5296 };
5297
beb1fe18 5298 rtl_csi_access_enable_2(tp);
b726e493 5299
fdf6fc06 5300 rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
b726e493 5301
beb1fe18 5302 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 5303}
5304
beb1fe18 5305static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
ef3386f0 5306{
beb1fe18
HW		 5307 void __iomem *ioaddr = tp->mmio_addr;
5308 struct pci_dev *pdev = tp->pci_dev;
5309
5310 rtl_csi_access_enable_2(tp);
ef3386f0
FR		 5311
5312 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5313
faf1e785 5314 if (tp->dev->mtu <= ETH_DATA_LEN)
5315 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
ef3386f0
FR		 5316
5317 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5318}
5319
beb1fe18 5320static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
7f3e3d3a 5321{
beb1fe18
HW		 5322 void __iomem *ioaddr = tp->mmio_addr;
5323 struct pci_dev *pdev = tp->pci_dev;
5324
5325 rtl_csi_access_enable_2(tp);
7f3e3d3a
FR		 5326
5327 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5328
5329 /* Magic. */
5330 RTL_W8(DBG_REG, 0x20);
5331
f0298f81 5332 RTL_W8(MaxTxPacketSize, TxPacketMax);
7f3e3d3a 5333
faf1e785 5334 if (tp->dev->mtu <= ETH_DATA_LEN)
5335 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
7f3e3d3a
FR		 5336
5337 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5338}
5339
beb1fe18 5340static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
219a1e9d 5341{
beb1fe18 5342 void __iomem *ioaddr = tp->mmio_addr;
350f7596 5343 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 5344 { 0x02, 0x0800, 0x1000 },
5345 { 0x03, 0, 0x0002 },
5346 { 0x06, 0x0080, 0x0000 }
5347 };
5348
beb1fe18 5349 rtl_csi_access_enable_2(tp);
b726e493
FR		 5350
5351 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
5352
fdf6fc06 5353 rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
b726e493 5354
beb1fe18 5355 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 5356}
5357
beb1fe18 5358static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
219a1e9d 5359{
350f7596 5360 static const struct ephy_info e_info_8168c_2[] = {
b726e493
FR		 5361 { 0x01, 0, 0x0001 },
5362 { 0x03, 0x0400, 0x0220 }
5363 };
5364
beb1fe18 5365 rtl_csi_access_enable_2(tp);
b726e493 5366
fdf6fc06 5367 rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
b726e493 5368
beb1fe18 5369 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 5370}
5371
beb1fe18 5372static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
197ff761 5373{
beb1fe18 5374 rtl_hw_start_8168c_2(tp);
197ff761
FR		 5375}
5376
beb1fe18 5377static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
6fb07058 5378{
beb1fe18 5379 rtl_csi_access_enable_2(tp);
6fb07058 5380
beb1fe18 5381 __rtl_hw_start_8168cp(tp);
6fb07058
FR		 5382}
5383
beb1fe18 5384static void rtl_hw_start_8168d(struct rtl8169_private *tp)
5b538df9 5385{
beb1fe18
HW		 5386 void __iomem *ioaddr = tp->mmio_addr;
5387 struct pci_dev *pdev = tp->pci_dev;
5388
5389 rtl_csi_access_enable_2(tp);
5b538df9
FR		 5390
5391 rtl_disable_clock_request(pdev);
5392
f0298f81 5393 RTL_W8(MaxTxPacketSize, TxPacketMax);
5b538df9 5394
faf1e785 5395 if (tp->dev->mtu <= ETH_DATA_LEN)
5396 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5b538df9
FR		 5397
5398 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5399}
5400
beb1fe18 5401static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4804b3b3 5402{
beb1fe18
HW		 5403 void __iomem *ioaddr = tp->mmio_addr;
5404 struct pci_dev *pdev = tp->pci_dev;
5405
5406 rtl_csi_access_enable_1(tp);
4804b3b3 5407
faf1e785 5408 if (tp->dev->mtu <= ETH_DATA_LEN)
5409 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4804b3b3 5410
5411 RTL_W8(MaxTxPacketSize, TxPacketMax);
5412
5413 rtl_disable_clock_request(pdev);
5414}
5415
beb1fe18 5416static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
e6de30d6 5417{
beb1fe18
HW		 5418 void __iomem *ioaddr = tp->mmio_addr;
5419 struct pci_dev *pdev = tp->pci_dev;
e6de30d6 5420 static const struct ephy_info e_info_8168d_4[] = {
5421 { 0x0b, ~0, 0x48 },
5422 { 0x19, 0x20, 0x50 },
5423 { 0x0c, ~0, 0x20 }
5424 };
5425 int i;
5426
beb1fe18 5427 rtl_csi_access_enable_1(tp);
e6de30d6 5428
5429 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5430
5431 RTL_W8(MaxTxPacketSize, TxPacketMax);
5432
5433 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
5434 const struct ephy_info *e = e_info_8168d_4 + i;
5435 u16 w;
5436
fdf6fc06
FR		 5437 w = rtl_ephy_read(tp, e->offset);
5438 rtl_ephy_write(tp, 0x03, (w & e->mask) | e->bits);
e6de30d6 5439 }
5440
5441 rtl_enable_clock_request(pdev);
5442}
5443
beb1fe18 5444static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
01dc7fec 5445{
beb1fe18
HW		 5446 void __iomem *ioaddr = tp->mmio_addr;
5447 struct pci_dev *pdev = tp->pci_dev;
70090424 5448 static const struct ephy_info e_info_8168e_1[] = {
01dc7fec 5449 { 0x00, 0x0200, 0x0100 },
5450 { 0x00, 0x0000, 0x0004 },
5451 { 0x06, 0x0002, 0x0001 },
5452 { 0x06, 0x0000, 0x0030 },
5453 { 0x07, 0x0000, 0x2000 },
5454 { 0x00, 0x0000, 0x0020 },
5455 { 0x03, 0x5800, 0x2000 },
5456 { 0x03, 0x0000, 0x0001 },
5457 { 0x01, 0x0800, 0x1000 },
5458 { 0x07, 0x0000, 0x4000 },
5459 { 0x1e, 0x0000, 0x2000 },
5460 { 0x19, 0xffff, 0xfe6c },
5461 { 0x0a, 0x0000, 0x0040 }
5462 };
5463
beb1fe18 5464 rtl_csi_access_enable_2(tp);
01dc7fec 5465
fdf6fc06 5466 rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
01dc7fec 5467
faf1e785 5468 if (tp->dev->mtu <= ETH_DATA_LEN)
5469 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
01dc7fec 5470
5471 RTL_W8(MaxTxPacketSize, TxPacketMax);
5472
5473 rtl_disable_clock_request(pdev);
5474
5475 /* Reset tx FIFO pointer */
cecb5fd7
FR		 5476 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
5477 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
01dc7fec 5478
cecb5fd7 5479 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
01dc7fec 5480}
5481
beb1fe18 5482static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
70090424 5483{
beb1fe18
HW		 5484 void __iomem *ioaddr = tp->mmio_addr;
5485 struct pci_dev *pdev = tp->pci_dev;
70090424
HW		 5486 static const struct ephy_info e_info_8168e_2[] = {
5487 { 0x09, 0x0000, 0x0080 },
5488 { 0x19, 0x0000, 0x0224 }
5489 };
5490
beb1fe18 5491 rtl_csi_access_enable_1(tp);
70090424 5492
fdf6fc06 5493 rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
70090424 5494
faf1e785 5495 if (tp->dev->mtu <= ETH_DATA_LEN)
5496 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
70090424 5497
fdf6fc06
FR		 5498 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5499 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5500 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5501 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5502 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5503 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
5504 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5505 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
70090424 5506
3090bd9a 5507 RTL_W8(MaxTxPacketSize, EarlySize);
70090424 5508
4521e1a9
FR		 5509 rtl_disable_clock_request(pdev);
5510
70090424
HW		 5511 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5512 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5513
5514 /* Adjust EEE LED frequency */
5515 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5516
5517 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5518 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4521e1a9 5519 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
70090424
HW		 5520}
5521
5f886e08 5522static void rtl_hw_start_8168f(struct rtl8169_private *tp)
c2218925 5523{
beb1fe18
HW		 5524 void __iomem *ioaddr = tp->mmio_addr;
5525 struct pci_dev *pdev = tp->pci_dev;
c2218925 5526
5f886e08 5527 rtl_csi_access_enable_2(tp);
c2218925
HW		 5528
5529 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5530
fdf6fc06
FR		 5531 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5532 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5533 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5534 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5535 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5536 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5537 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5538 rtl_w1w0_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5539 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5540 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
c2218925
HW		 5541
5542 RTL_W8(MaxTxPacketSize, EarlySize);
5543
4521e1a9
FR		 5544 rtl_disable_clock_request(pdev);
5545
c2218925
HW		 5546 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5547 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
c2218925 5548 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4521e1a9
FR		 5549 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5550 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
c2218925
HW		 5551}
5552
5f886e08
HW		 5553static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5554{
5555 void __iomem *ioaddr = tp->mmio_addr;
5556 static const struct ephy_info e_info_8168f_1[] = {
5557 { 0x06, 0x00c0, 0x0020 },
5558 { 0x08, 0x0001, 0x0002 },
5559 { 0x09, 0x0000, 0x0080 },
5560 { 0x19, 0x0000, 0x0224 }
5561 };
5562
5563 rtl_hw_start_8168f(tp);
5564
fdf6fc06 5565 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5f886e08 5566
fdf6fc06 5567 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5f886e08
HW		 5568
5569 /* Adjust EEE LED frequency */
5570 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5571}
5572
b3d7b2f2
HW		 5573static void rtl_hw_start_8411(struct rtl8169_private *tp)
5574{
b3d7b2f2
HW		 5575 static const struct ephy_info e_info_8168f_1[] = {
5576 { 0x06, 0x00c0, 0x0020 },
5577 { 0x0f, 0xffff, 0x5200 },
5578 { 0x1e, 0x0000, 0x4000 },
5579 { 0x19, 0x0000, 0x0224 }
5580 };
5581
5582 rtl_hw_start_8168f(tp);
b51ecea8 5583 rtl_pcie_state_l2l3_enable(tp, false);
b3d7b2f2 5584
fdf6fc06 5585 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
b3d7b2f2 5586
fdf6fc06 5587 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
b3d7b2f2
HW		 5588}
5589
c558386b
HW		 5590static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5591{
5592 void __iomem *ioaddr = tp->mmio_addr;
5593 struct pci_dev *pdev = tp->pci_dev;
5594
beb330a4 5595 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5596
c558386b
HW		 5597 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
5598 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5599 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5600 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5601
5602 rtl_csi_access_enable_1(tp);
5603
5604 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5605
5606 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5607 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
beb330a4 5608 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
c558386b
HW		 5609
5610 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4521e1a9 5611 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
c558386b
HW		 5612 RTL_W8(MaxTxPacketSize, EarlySize);
5613
5614 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5615 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5616
5617 /* Adjust EEE LED frequency */
5618 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5619
beb330a4 5620 rtl_w1w0_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5621 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
b51ecea8 5622
5623 rtl_pcie_state_l2l3_enable(tp, false);
c558386b
HW		 5624}
5625
57538c4a 5626static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
5627{
5628 void __iomem *ioaddr = tp->mmio_addr;
5629 static const struct ephy_info e_info_8168g_2[] = {
5630 { 0x00, 0x0000, 0x0008 },
5631 { 0x0c, 0x3df0, 0x0200 },
5632 { 0x19, 0xffff, 0xfc00 },
5633 { 0x1e, 0xffff, 0x20eb }
5634 };
5635
5636 rtl_hw_start_8168g_1(tp);
5637
5638 /* disable aspm and clock request before access ephy */
5639 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
5640 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
5641 rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
5642}
5643
45dd95c4 5644static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
5645{
5646 void __iomem *ioaddr = tp->mmio_addr;
5647 static const struct ephy_info e_info_8411_2[] = {
5648 { 0x00, 0x0000, 0x0008 },
5649 { 0x0c, 0x3df0, 0x0200 },
5650 { 0x0f, 0xffff, 0x5200 },
5651 { 0x19, 0x0020, 0x0000 },
5652 { 0x1e, 0x0000, 0x2000 }
5653 };
5654
5655 rtl_hw_start_8168g_1(tp);
5656
5657 /* disable aspm and clock request before access ephy */
5658 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
5659 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
5660 rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
5661}
5662
6e1d0b89
CHL		 5663static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
5664{
5665 void __iomem *ioaddr = tp->mmio_addr;
5666 struct pci_dev *pdev = tp->pci_dev;
5667 u16 rg_saw_cnt;
5668 u32 data;
5669 static const struct ephy_info e_info_8168h_1[] = {
5670 { 0x1e, 0x0800, 0x0001 },
5671 { 0x1d, 0x0000, 0x0800 },
5672 { 0x05, 0xffff, 0x2089 },
5673 { 0x06, 0xffff, 0x5881 },
5674 { 0x04, 0xffff, 0x154a },
5675 { 0x01, 0xffff, 0x068b }
5676 };
5677
5678 /* disable aspm and clock request before access ephy */
5679 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
5680 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
5681 rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));
5682
5683 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5684
5685 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
5686 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5687 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5688 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5689
5690 rtl_csi_access_enable_1(tp);
5691
5692 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5693
5694 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5695 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5696
5697 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);
5698
5699 rtl_w1w0_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);
5700
5701 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
5702
5703 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5704 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
5705 RTL_W8(MaxTxPacketSize, EarlySize);
5706
5707 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5708 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5709
5710 /* Adjust EEE LED frequency */
5711 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5712
5713 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
5714 RTL_W8(DLLPR, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
5715
5716 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~TX_10M_PS_EN);
5717
5718 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
5719
5720 rtl_pcie_state_l2l3_enable(tp, false);
5721
5722 rtl_writephy(tp, 0x1f, 0x0c42);
5723 rg_saw_cnt = rtl_readphy(tp, 0x13);
5724 rtl_writephy(tp, 0x1f, 0x0000);
5725 if (rg_saw_cnt > 0) {
5726 u16 sw_cnt_1ms_ini;
5727
5728 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
5729 sw_cnt_1ms_ini &= 0x0fff;
5730 data = r8168_mac_ocp_read(tp, 0xd412);
5731 data &= 0x0fff;
5732 data |= sw_cnt_1ms_ini;
5733 r8168_mac_ocp_write(tp, 0xd412, data);
5734 }
5735
5736 data = r8168_mac_ocp_read(tp, 0xe056);
5737 data &= 0xf0;
5738 data |= 0x07;
5739 r8168_mac_ocp_write(tp, 0xe056, data);
5740
5741 data = r8168_mac_ocp_read(tp, 0xe052);
5742 data &= 0x8008;
5743 data |= 0x6000;
5744 r8168_mac_ocp_write(tp, 0xe052, data);
5745
5746 data = r8168_mac_ocp_read(tp, 0xe0d6);
5747 data &= 0x01ff;
5748 data |= 0x017f;
5749 r8168_mac_ocp_write(tp, 0xe0d6, data);
5750
5751 data = r8168_mac_ocp_read(tp, 0xd420);
5752 data &= 0x0fff;
5753 data |= 0x047f;
5754 r8168_mac_ocp_write(tp, 0xd420, data);
5755
5756 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
5757 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
5758 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
5759 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
5760}
5761
07ce4064
FR		 5762static void rtl_hw_start_8168(struct net_device *dev)
5763{
2dd99530
FR		 5764 struct rtl8169_private *tp = netdev_priv(dev);
5765 void __iomem *ioaddr = tp->mmio_addr;
5766
5767 RTL_W8(Cfg9346, Cfg9346_Unlock);
5768
f0298f81 5769 RTL_W8(MaxTxPacketSize, TxPacketMax);
2dd99530 5770
6f0333b8 5771 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
2dd99530 5772
0e485150 5773 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 5774
5775 RTL_W16(CPlusCmd, tp->cp_cmd);
5776
0e485150 5777 RTL_W16(IntrMitigate, 0x5151);
2dd99530 5778
0e485150 5779 /* Work around for RxFIFO overflow. */
811fd301 5780 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
da78dbff
FR		 5781 tp->event_slow |= RxFIFOOver | PCSTimeout;
5782 tp->event_slow &= ~RxOverflow;
0e485150
FR		 5783 }
5784
5785 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530 5786
1a964649 5787 rtl_set_rx_tx_config_registers(tp);
2dd99530
FR		 5788
5789 RTL_R8(IntrMask);
5790
219a1e9d
FR		 5791 switch (tp->mac_version) {
5792 case RTL_GIGA_MAC_VER_11:
beb1fe18 5793 rtl_hw_start_8168bb(tp);
4804b3b3 5794 break;
219a1e9d
FR		 5795
5796 case RTL_GIGA_MAC_VER_12:
5797 case RTL_GIGA_MAC_VER_17:
beb1fe18 5798 rtl_hw_start_8168bef(tp);
4804b3b3 5799 break;
219a1e9d
FR		 5800
5801 case RTL_GIGA_MAC_VER_18:
beb1fe18 5802 rtl_hw_start_8168cp_1(tp);
4804b3b3 5803 break;
219a1e9d
FR		 5804
5805 case RTL_GIGA_MAC_VER_19:
beb1fe18 5806 rtl_hw_start_8168c_1(tp);
4804b3b3 5807 break;
219a1e9d
FR		 5808
5809 case RTL_GIGA_MAC_VER_20:
beb1fe18 5810 rtl_hw_start_8168c_2(tp);
4804b3b3 5811 break;
219a1e9d 5812
197ff761 5813 case RTL_GIGA_MAC_VER_21:
beb1fe18 5814 rtl_hw_start_8168c_3(tp);
4804b3b3 5815 break;
197ff761 5816
6fb07058 5817 case RTL_GIGA_MAC_VER_22:
beb1fe18 5818 rtl_hw_start_8168c_4(tp);
4804b3b3 5819 break;
6fb07058 5820
ef3386f0 5821 case RTL_GIGA_MAC_VER_23:
beb1fe18 5822 rtl_hw_start_8168cp_2(tp);
4804b3b3 5823 break;
ef3386f0 5824
7f3e3d3a 5825 case RTL_GIGA_MAC_VER_24:
beb1fe18 5826 rtl_hw_start_8168cp_3(tp);
4804b3b3 5827 break;
7f3e3d3a 5828
5b538df9 5829 case RTL_GIGA_MAC_VER_25:
daf9df6d 5830 case RTL_GIGA_MAC_VER_26:
5831 case RTL_GIGA_MAC_VER_27:
beb1fe18 5832 rtl_hw_start_8168d(tp);
4804b3b3 5833 break;
5b538df9 5834
e6de30d6 5835 case RTL_GIGA_MAC_VER_28:
beb1fe18 5836 rtl_hw_start_8168d_4(tp);
4804b3b3 5837 break;
cecb5fd7 5838
4804b3b3 5839 case RTL_GIGA_MAC_VER_31:
beb1fe18 5840 rtl_hw_start_8168dp(tp);
4804b3b3 5841 break;
5842
01dc7fec 5843 case RTL_GIGA_MAC_VER_32:
5844 case RTL_GIGA_MAC_VER_33:
beb1fe18 5845 rtl_hw_start_8168e_1(tp);
70090424
HW		 5846 break;
5847 case RTL_GIGA_MAC_VER_34:
beb1fe18 5848 rtl_hw_start_8168e_2(tp);
01dc7fec 5849 break;
e6de30d6 5850
c2218925
HW		 5851 case RTL_GIGA_MAC_VER_35:
5852 case RTL_GIGA_MAC_VER_36:
beb1fe18 5853 rtl_hw_start_8168f_1(tp);
c2218925
HW		 5854 break;
5855
b3d7b2f2
HW		 5856 case RTL_GIGA_MAC_VER_38:
5857 rtl_hw_start_8411(tp);
5858 break;
5859
c558386b
HW		 5860 case RTL_GIGA_MAC_VER_40:
5861 case RTL_GIGA_MAC_VER_41:
5862 rtl_hw_start_8168g_1(tp);
5863 break;
57538c4a 5864 case RTL_GIGA_MAC_VER_42:
5865 rtl_hw_start_8168g_2(tp);
5866 break;
c558386b 5867
45dd95c4 5868 case RTL_GIGA_MAC_VER_44:
5869 rtl_hw_start_8411_2(tp);
5870 break;
5871
6e1d0b89
CHL		 5872 case RTL_GIGA_MAC_VER_45:
5873 case RTL_GIGA_MAC_VER_46:
5874 rtl_hw_start_8168h_1(tp);
5875 break;
5876
219a1e9d
FR		 5877 default:
5878 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
5879 dev->name, tp->mac_version);
4804b3b3 5880 break;
219a1e9d 5881 }
2dd99530 5882
1a964649 5883 RTL_W8(Cfg9346, Cfg9346_Lock);
5884
0e485150
FR		 5885 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5886
1a964649 5887 rtl_set_rx_mode(dev);
b8363901 5888
05b9687b 5889 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
07ce4064 5890}
1da177e4 5891
2857ffb7
FR		 5892#define R810X_CPCMD_QUIRK_MASK (\
5893 EnableBist | \
5894 Mac_dbgo_oe | \
5895 Force_half_dup | \
5edcc537 5896 Force_rxflow_en | \
2857ffb7
FR		 5897 Force_txflow_en | \
5898 Cxpl_dbg_sel | \
5899 ASF | \
5900 PktCntrDisable | \
d24e9aaf 5901 Mac_dbgo_sel)
2857ffb7 5902
beb1fe18 5903static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
2857ffb7 5904{
beb1fe18
HW		 5905 void __iomem *ioaddr = tp->mmio_addr;
5906 struct pci_dev *pdev = tp->pci_dev;
350f7596 5907 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 5908 { 0x01, 0, 0x6e65 },
5909 { 0x02, 0, 0x091f },
5910 { 0x03, 0, 0xc2f9 },
5911 { 0x06, 0, 0xafb5 },
5912 { 0x07, 0, 0x0e00 },
5913 { 0x19, 0, 0xec80 },
5914 { 0x01, 0, 0x2e65 },
5915 { 0x01, 0, 0x6e65 }
5916 };
5917 u8 cfg1;
5918
beb1fe18 5919 rtl_csi_access_enable_2(tp);
2857ffb7
FR		 5920
5921 RTL_W8(DBG_REG, FIX_NAK_1);
5922
5923 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5924
5925 RTL_W8(Config1,
5926 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5927 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5928
5929 cfg1 = RTL_R8(Config1);
5930 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5931 RTL_W8(Config1, cfg1 & ~LEDS0);
5932
fdf6fc06 5933 rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
2857ffb7
FR		 5934}
5935
beb1fe18 5936static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
2857ffb7 5937{
beb1fe18
HW		 5938 void __iomem *ioaddr = tp->mmio_addr;
5939 struct pci_dev *pdev = tp->pci_dev;
5940
5941 rtl_csi_access_enable_2(tp);
2857ffb7
FR		 5942
5943 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5944
5945 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
5946 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2857ffb7
FR		 5947}
5948
beb1fe18 5949static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
2857ffb7 5950{
beb1fe18 5951 rtl_hw_start_8102e_2(tp);
2857ffb7 5952
fdf6fc06 5953 rtl_ephy_write(tp, 0x03, 0xc2f9);
2857ffb7
FR		 5954}
5955
beb1fe18 5956static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5a5e4443 5957{
beb1fe18 5958 void __iomem *ioaddr = tp->mmio_addr;
5a5e4443
HW		 5959 static const struct ephy_info e_info_8105e_1[] = {
5960 { 0x07, 0, 0x4000 },
5961 { 0x19, 0, 0x0200 },
5962 { 0x19, 0, 0x0020 },
5963 { 0x1e, 0, 0x2000 },
5964 { 0x03, 0, 0x0001 },
5965 { 0x19, 0, 0x0100 },
5966 { 0x19, 0, 0x0004 },
5967 { 0x0a, 0, 0x0020 }
5968 };
5969
cecb5fd7 5970 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5a5e4443
HW		 5971 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5972
cecb5fd7 5973 /* Disable Early Tally Counter */
5a5e4443
HW		 5974 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
5975
5976 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4f6b00e5 5977 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5a5e4443 5978
fdf6fc06 5979 rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
b51ecea8 5980
5981 rtl_pcie_state_l2l3_enable(tp, false);
5a5e4443
HW		 5982}
5983
beb1fe18 5984static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5a5e4443 5985{
beb1fe18 5986 rtl_hw_start_8105e_1(tp);
fdf6fc06 5987 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5a5e4443
HW		 5988}
5989
7e18dca1
HW		 5990static void rtl_hw_start_8402(struct rtl8169_private *tp)
5991{
5992 void __iomem *ioaddr = tp->mmio_addr;
5993 static const struct ephy_info e_info_8402[] = {
5994 { 0x19, 0xffff, 0xff64 },
5995 { 0x1e, 0, 0x4000 }
5996 };
5997
5998 rtl_csi_access_enable_2(tp);
5999
6000 /* Force LAN exit from ASPM if Rx/Tx are not idle */
6001 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6002
6003 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6004 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
6005
fdf6fc06 6006 rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
7e18dca1
HW		 6007
6008 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
6009
fdf6fc06
FR		 6010 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
6011 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
6012 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6013 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6014 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6015 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6016 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
b51ecea8 6017
6018 rtl_pcie_state_l2l3_enable(tp, false);
7e18dca1
HW		 6019}
6020
5598bfe5
HW		 6021static void rtl_hw_start_8106(struct rtl8169_private *tp)
6022{
6023 void __iomem *ioaddr = tp->mmio_addr;
6024
6025 /* Force LAN exit from ASPM if Rx/Tx are not idle */
6026 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6027
4521e1a9 6028 RTL_W32(MISC, (RTL_R32(MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5598bfe5
HW		 6029 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
6030 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
b51ecea8 6031
6032 rtl_pcie_state_l2l3_enable(tp, false);
5598bfe5
HW		 6033}
6034
07ce4064
FR		 6035static void rtl_hw_start_8101(struct net_device *dev)
6036{
cdf1a608
FR		 6037 struct rtl8169_private *tp = netdev_priv(dev);
6038 void __iomem *ioaddr = tp->mmio_addr;
6039 struct pci_dev *pdev = tp->pci_dev;
6040
da78dbff
FR		 6041 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
6042 tp->event_slow &= ~RxFIFOOver;
811fd301 6043
cecb5fd7 6044 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
7d7903b2 6045 tp->mac_version == RTL_GIGA_MAC_VER_16)
8200bc72
BH		 6046 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL,
6047 PCI_EXP_DEVCTL_NOSNOOP_EN);
cdf1a608 6048
d24e9aaf
HW		 6049 RTL_W8(Cfg9346, Cfg9346_Unlock);
6050
1a964649 6051 RTL_W8(MaxTxPacketSize, TxPacketMax);
6052
6053 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
6054
6055 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
6056 RTL_W16(CPlusCmd, tp->cp_cmd);
6057
6058 rtl_set_rx_tx_desc_registers(tp, ioaddr);
6059
6060 rtl_set_rx_tx_config_registers(tp);
6061
2857ffb7
FR		 6062 switch (tp->mac_version) {
6063 case RTL_GIGA_MAC_VER_07:
beb1fe18 6064 rtl_hw_start_8102e_1(tp);
2857ffb7
FR		 6065 break;
6066
6067 case RTL_GIGA_MAC_VER_08:
beb1fe18 6068 rtl_hw_start_8102e_3(tp);
2857ffb7
FR		 6069 break;
6070
6071 case RTL_GIGA_MAC_VER_09:
beb1fe18 6072 rtl_hw_start_8102e_2(tp);
2857ffb7 6073 break;
5a5e4443
HW		 6074
6075 case RTL_GIGA_MAC_VER_29:
beb1fe18 6076 rtl_hw_start_8105e_1(tp);
5a5e4443
HW		 6077 break;
6078 case RTL_GIGA_MAC_VER_30:
beb1fe18 6079 rtl_hw_start_8105e_2(tp);
5a5e4443 6080 break;
7e18dca1
HW		 6081
6082 case RTL_GIGA_MAC_VER_37:
6083 rtl_hw_start_8402(tp);
6084 break;
5598bfe5
HW		 6085
6086 case RTL_GIGA_MAC_VER_39:
6087 rtl_hw_start_8106(tp);
6088 break;
58152cd4 6089 case RTL_GIGA_MAC_VER_43:
6090 rtl_hw_start_8168g_2(tp);
6091 break;
6e1d0b89
CHL		 6092 case RTL_GIGA_MAC_VER_47:
6093 case RTL_GIGA_MAC_VER_48:
6094 rtl_hw_start_8168h_1(tp);
6095 break;
cdf1a608
FR		 6096 }
6097
d24e9aaf 6098 RTL_W8(Cfg9346, Cfg9346_Lock);
cdf1a608 6099
cdf1a608
FR		 6100 RTL_W16(IntrMitigate, 0x0000);
6101
cdf1a608 6102 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
cdf1a608 6103
cdf1a608
FR		 6104 rtl_set_rx_mode(dev);
6105
1a964649 6106 RTL_R8(IntrMask);
6107
cdf1a608 6108 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
1da177e4
LT		 6109}
6110
6111static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
6112{
d58d46b5
FR		 6113 struct rtl8169_private *tp = netdev_priv(dev);
6114
6115 if (new_mtu < ETH_ZLEN ||
6116 new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
1da177e4
LT		 6117 return -EINVAL;
6118
d58d46b5
FR		 6119 if (new_mtu > ETH_DATA_LEN)
6120 rtl_hw_jumbo_enable(tp);
6121 else
6122 rtl_hw_jumbo_disable(tp);
6123
1da177e4 6124 dev->mtu = new_mtu;
350fb32a
MM		 6125 netdev_update_features(dev);
6126
323bb685 6127 return 0;
1da177e4
LT		 6128}
6129
6130static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
6131{
95e0918d 6132 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 6133 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
6134}
6135
6f0333b8
ED		 6136static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
6137 void **data_buff, struct RxDesc *desc)
1da177e4 6138{
48addcc9 6139 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
231aee63 6140 DMA_FROM_DEVICE);
48addcc9 6141
6f0333b8
ED		 6142 kfree(*data_buff);
6143 *data_buff = NULL;
1da177e4
LT		 6144 rtl8169_make_unusable_by_asic(desc);
6145}
6146
6147static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
6148{
6149 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
6150
6151 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
6152}
6153
6154static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
6155 u32 rx_buf_sz)
6156{
6157 desc->addr = cpu_to_le64(mapping);
6158 wmb();
6159 rtl8169_mark_to_asic(desc, rx_buf_sz);
6160}
6161
6f0333b8
ED		 6162static inline void *rtl8169_align(void *data)
6163{
6164 return (void *)ALIGN((long)data, 16);
6165}
6166
0ecbe1ca
SG		 6167static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
6168 struct RxDesc *desc)
1da177e4 6169{
6f0333b8 6170 void *data;
1da177e4 6171 dma_addr_t mapping;
48addcc9 6172 struct device *d = &tp->pci_dev->dev;
0ecbe1ca 6173 struct net_device *dev = tp->dev;
6f0333b8 6174 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
1da177e4 6175
6f0333b8
ED		 6176 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
6177 if (!data)
6178 return NULL;
e9f63f30 6179
6f0333b8
ED		 6180 if (rtl8169_align(data) != data) {
6181 kfree(data);
6182 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
6183 if (!data)
6184 return NULL;
6185 }
3eafe507 6186
48addcc9 6187 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
231aee63 6188 DMA_FROM_DEVICE);
d827d86b
SG		 6189 if (unlikely(dma_mapping_error(d, mapping))) {
6190 if (net_ratelimit())
6191 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
3eafe507 6192 goto err_out;
d827d86b 6193 }
1da177e4
LT		 6194
6195 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6f0333b8 6196 return data;
3eafe507
SG		 6197
6198err_out:
6199 kfree(data);
6200 return NULL;
1da177e4
LT		 6201}
6202
6203static void rtl8169_rx_clear(struct rtl8169_private *tp)
6204{
07d3f51f 6205 unsigned int i;
1da177e4
LT		 6206
6207 for (i = 0; i < NUM_RX_DESC; i++) {
6f0333b8
ED		 6208 if (tp->Rx_databuff[i]) {
6209 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
1da177e4
LT		 6210 tp->RxDescArray + i);
6211 }
6212 }
6213}
6214
0ecbe1ca 6215static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1da177e4 6216{
0ecbe1ca
SG		 6217 desc->opts1 |= cpu_to_le32(RingEnd);
6218}
5b0384f4 6219
0ecbe1ca
SG		 6220static int rtl8169_rx_fill(struct rtl8169_private *tp)
6221{
6222 unsigned int i;
1da177e4 6223
0ecbe1ca
SG		 6224 for (i = 0; i < NUM_RX_DESC; i++) {
6225 void *data;
4ae47c2d 6226
6f0333b8 6227 if (tp->Rx_databuff[i])
1da177e4 6228 continue;
bcf0bf90 6229
0ecbe1ca 6230 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6f0333b8
ED		 6231 if (!data) {
6232 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
0ecbe1ca 6233 goto err_out;
6f0333b8
ED		 6234 }
6235 tp->Rx_databuff[i] = data;
1da177e4 6236 }
1da177e4 6237
0ecbe1ca
SG		 6238 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
6239 return 0;
6240
6241err_out:
6242 rtl8169_rx_clear(tp);
6243 return -ENOMEM;
1da177e4
LT		 6244}
6245
1da177e4
LT		 6246static int rtl8169_init_ring(struct net_device *dev)
6247{
6248 struct rtl8169_private *tp = netdev_priv(dev);
6249
6250 rtl8169_init_ring_indexes(tp);
6251
6252 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
6f0333b8 6253 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
1da177e4 6254
0ecbe1ca 6255 return rtl8169_rx_fill(tp);
1da177e4
LT		 6256}
6257
48addcc9 6258static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
1da177e4
LT		 6259 struct TxDesc *desc)
6260{
6261 unsigned int len = tx_skb->len;
6262
48addcc9
SG		 6263 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
6264
1da177e4
LT		 6265 desc->opts1 = 0x00;
6266 desc->opts2 = 0x00;
6267 desc->addr = 0x00;
6268 tx_skb->len = 0;
6269}
6270
3eafe507
SG		 6271static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
6272 unsigned int n)
1da177e4
LT		 6273{
6274 unsigned int i;
6275
3eafe507
SG		 6276 for (i = 0; i < n; i++) {
6277 unsigned int entry = (start + i) % NUM_TX_DESC;
1da177e4
LT		 6278 struct ring_info *tx_skb = tp->tx_skb + entry;
6279 unsigned int len = tx_skb->len;
6280
6281 if (len) {
6282 struct sk_buff *skb = tx_skb->skb;
6283
48addcc9 6284 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
1da177e4
LT		 6285 tp->TxDescArray + entry);
6286 if (skb) {
cac4b22f 6287 tp->dev->stats.tx_dropped++;
989c9ba1 6288 dev_kfree_skb_any(skb);
1da177e4
LT		 6289 tx_skb->skb = NULL;
6290 }
1da177e4
LT		 6291 }
6292 }
3eafe507
SG		 6293}
6294
6295static void rtl8169_tx_clear(struct rtl8169_private *tp)
6296{
6297 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
1da177e4
LT		 6298 tp->cur_tx = tp->dirty_tx = 0;
6299}
6300
4422bcd4 6301static void rtl_reset_work(struct rtl8169_private *tp)
1da177e4 6302{
c4028958 6303 struct net_device *dev = tp->dev;
56de414c 6304 int i;
1da177e4 6305
da78dbff
FR		 6306 napi_disable(&tp->napi);
6307 netif_stop_queue(dev);
6308 synchronize_sched();
1da177e4 6309
c7c2c39b 6310 rtl8169_hw_reset(tp);
6311
56de414c
FR		 6312 for (i = 0; i < NUM_RX_DESC; i++)
6313 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
6314
1da177e4 6315 rtl8169_tx_clear(tp);
c7c2c39b 6316 rtl8169_init_ring_indexes(tp);
1da177e4 6317
da78dbff 6318 napi_enable(&tp->napi);
56de414c
FR		 6319 rtl_hw_start(dev);
6320 netif_wake_queue(dev);
6321 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1da177e4
LT		 6322}
6323
6324static void rtl8169_tx_timeout(struct net_device *dev)
6325{
da78dbff
FR		 6326 struct rtl8169_private *tp = netdev_priv(dev);
6327
6328 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 6329}
6330
6331static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2b7b4318 6332 u32 *opts)
1da177e4
LT		 6333{
6334 struct skb_shared_info *info = skb_shinfo(skb);
6335 unsigned int cur_frag, entry;
6e1d0b89 6336 struct TxDesc *uninitialized_var(txd);
48addcc9 6337 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 6338
6339 entry = tp->cur_tx;
6340 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
9e903e08 6341 const skb_frag_t *frag = info->frags + cur_frag;
1da177e4
LT		 6342 dma_addr_t mapping;
6343 u32 status, len;
6344 void *addr;
6345
6346 entry = (entry + 1) % NUM_TX_DESC;
6347
6348 txd = tp->TxDescArray + entry;
9e903e08 6349 len = skb_frag_size(frag);
929f6189 6350 addr = skb_frag_address(frag);
48addcc9 6351 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
d827d86b
SG		 6352 if (unlikely(dma_mapping_error(d, mapping))) {
6353 if (net_ratelimit())
6354 netif_err(tp, drv, tp->dev,
6355 "Failed to map TX fragments DMA!\n");
3eafe507 6356 goto err_out;
d827d86b 6357 }
1da177e4 6358
cecb5fd7 6359 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318
FR		 6360 status = opts[0] | len |
6361 (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 6362
6363 txd->opts1 = cpu_to_le32(status);
2b7b4318 6364 txd->opts2 = cpu_to_le32(opts[1]);
1da177e4
LT		 6365 txd->addr = cpu_to_le64(mapping);
6366
6367 tp->tx_skb[entry].len = len;
6368 }
6369
6370 if (cur_frag) {
6371 tp->tx_skb[entry].skb = skb;
6372 txd->opts1 |= cpu_to_le32(LastFrag);
6373 }
6374
6375 return cur_frag;
3eafe507
SG		 6376
6377err_out:
6378 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
6379 return -EIO;
1da177e4
LT		 6380}
6381
b423e9ae 6382static bool rtl_skb_pad(struct sk_buff *skb)
6383{
6384 if (skb_padto(skb, ETH_ZLEN))
6385 return false;
6386 skb_put(skb, ETH_ZLEN - skb->len);
6387 return true;
6388}
6389
6390static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
6391{
6392 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
6393}
6394
e974604b 6395static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6396 struct net_device *dev);
6397/* r8169_csum_workaround()
6398 * The hw limites the value the transport offset. When the offset is out of the
6399 * range, calculate the checksum by sw.
6400 */
6401static void r8169_csum_workaround(struct rtl8169_private *tp,
6402 struct sk_buff *skb)
6403{
6404 if (skb_shinfo(skb)->gso_size) {
6405 netdev_features_t features = tp->dev->features;
6406 struct sk_buff *segs, *nskb;
6407
6408 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
6409 segs = skb_gso_segment(skb, features);
6410 if (IS_ERR(segs) || !segs)
6411 goto drop;
6412
6413 do {
6414 nskb = segs;
6415 segs = segs->next;
6416 nskb->next = NULL;
6417 rtl8169_start_xmit(nskb, tp->dev);
6418 } while (segs);
6419
6420 dev_kfree_skb(skb);
6421 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6422 if (skb_checksum_help(skb) < 0)
6423 goto drop;
6424
6425 rtl8169_start_xmit(skb, tp->dev);
6426 } else {
6427 struct net_device_stats *stats;
6428
6429drop:
6430 stats = &tp->dev->stats;
6431 stats->tx_dropped++;
6432 dev_kfree_skb(skb);
6433 }
6434}
6435
6436/* msdn_giant_send_check()
6437 * According to the document of microsoft, the TCP Pseudo Header excludes the
6438 * packet length for IPv6 TCP large packets.
6439 */
6440static int msdn_giant_send_check(struct sk_buff *skb)
6441{
6442 const struct ipv6hdr *ipv6h;
6443 struct tcphdr *th;
6444 int ret;
6445
6446 ret = skb_cow_head(skb, 0);
6447 if (ret)
6448 return ret;
6449
6450 ipv6h = ipv6_hdr(skb);
6451 th = tcp_hdr(skb);
6452
6453 th->check = 0;
6454 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
6455
6456 return ret;
6457}
6458
6459static inline __be16 get_protocol(struct sk_buff *skb)
6460{
6461 __be16 protocol;
6462
6463 if (skb->protocol == htons(ETH_P_8021Q))
6464 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
6465 else
6466 protocol = skb->protocol;
6467
6468 return protocol;
6469}
6470
5888d3fc 6471static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
6472 struct sk_buff *skb, u32 *opts)
1da177e4 6473{
350fb32a
MM		 6474 u32 mss = skb_shinfo(skb)->gso_size;
6475
2b7b4318
FR		 6476 if (mss) {
6477 opts[0] |= TD_LSO;
5888d3fc 6478 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
6479 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6480 const struct iphdr *ip = ip_hdr(skb);
6481
6482 if (ip->protocol == IPPROTO_TCP)
6483 opts[0] |= TD0_IP_CS | TD0_TCP_CS;
6484 else if (ip->protocol == IPPROTO_UDP)
6485 opts[0] |= TD0_IP_CS | TD0_UDP_CS;
6486 else
6487 WARN_ON_ONCE(1);
6488 }
6489
6490 return true;
6491}
6492
6493static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
6494 struct sk_buff *skb, u32 *opts)
6495{
bdfa4ed6 6496 u32 transport_offset = (u32)skb_transport_offset(skb);
5888d3fc 6497 u32 mss = skb_shinfo(skb)->gso_size;
6498
6499 if (mss) {
e974604b 6500 if (transport_offset > GTTCPHO_MAX) {
6501 netif_warn(tp, tx_err, tp->dev,
6502 "Invalid transport offset 0x%x for TSO\n",
6503 transport_offset);
6504 return false;
6505 }
6506
6507 switch (get_protocol(skb)) {
6508 case htons(ETH_P_IP):
6509 opts[0] |= TD1_GTSENV4;
6510 break;
6511
6512 case htons(ETH_P_IPV6):
6513 if (msdn_giant_send_check(skb))
6514 return false;
6515
6516 opts[0] |= TD1_GTSENV6;
6517 break;
6518
6519 default:
6520 WARN_ON_ONCE(1);
6521 break;
6522 }
6523
bdfa4ed6 6524 opts[0] |= transport_offset << GTTCPHO_SHIFT;
5888d3fc 6525 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
2b7b4318 6526 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
e974604b 6527 u8 ip_protocol;
1da177e4 6528
b423e9ae 6529 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
6530 return skb_checksum_help(skb) == 0 && rtl_skb_pad(skb);
6531
e974604b 6532 if (transport_offset > TCPHO_MAX) {
6533 netif_warn(tp, tx_err, tp->dev,
6534 "Invalid transport offset 0x%x\n",
6535 transport_offset);
6536 return false;
6537 }
6538
6539 switch (get_protocol(skb)) {
6540 case htons(ETH_P_IP):
6541 opts[1] |= TD1_IPv4_CS;
6542 ip_protocol = ip_hdr(skb)->protocol;
6543 break;
6544
6545 case htons(ETH_P_IPV6):
6546 opts[1] |= TD1_IPv6_CS;
6547 ip_protocol = ipv6_hdr(skb)->nexthdr;
6548 break;
6549
6550 default:
6551 ip_protocol = IPPROTO_RAW;
6552 break;
6553 }
6554
6555 if (ip_protocol == IPPROTO_TCP)
6556 opts[1] |= TD1_TCP_CS;
6557 else if (ip_protocol == IPPROTO_UDP)
6558 opts[1] |= TD1_UDP_CS;
2b7b4318
FR		 6559 else
6560 WARN_ON_ONCE(1);
e974604b 6561
6562 opts[1] |= transport_offset << TCPHO_SHIFT;
b423e9ae 6563 } else {
6564 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
6565 return rtl_skb_pad(skb);
1da177e4 6566 }
5888d3fc 6567
b423e9ae 6568 return true;
1da177e4
LT		 6569}
6570
61357325
SH		 6571static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6572 struct net_device *dev)
1da177e4
LT		 6573{
6574 struct rtl8169_private *tp = netdev_priv(dev);
3eafe507 6575 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
1da177e4
LT		 6576 struct TxDesc *txd = tp->TxDescArray + entry;
6577 void __iomem *ioaddr = tp->mmio_addr;
48addcc9 6578 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 6579 dma_addr_t mapping;
6580 u32 status, len;
2b7b4318 6581 u32 opts[2];
3eafe507 6582 int frags;
5b0384f4 6583
477206a0 6584 if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
bf82c189 6585 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
3eafe507 6586 goto err_stop_0;
1da177e4
LT		 6587 }
6588
6589 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3eafe507
SG		 6590 goto err_stop_0;
6591
b423e9ae 6592 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
6593 opts[0] = DescOwn;
6594
e974604b 6595 if (!tp->tso_csum(tp, skb, opts)) {
6596 r8169_csum_workaround(tp, skb);
6597 return NETDEV_TX_OK;
6598 }
b423e9ae 6599
3eafe507 6600 len = skb_headlen(skb);
48addcc9 6601 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
d827d86b
SG		 6602 if (unlikely(dma_mapping_error(d, mapping))) {
6603 if (net_ratelimit())
6604 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
3eafe507 6605 goto err_dma_0;
d827d86b 6606 }
3eafe507
SG		 6607
6608 tp->tx_skb[entry].len = len;
6609 txd->addr = cpu_to_le64(mapping);
1da177e4 6610
2b7b4318 6611 frags = rtl8169_xmit_frags(tp, skb, opts);
3eafe507
SG		 6612 if (frags < 0)
6613 goto err_dma_1;
6614 else if (frags)
2b7b4318 6615 opts[0] |= FirstFrag;
3eafe507 6616 else {
2b7b4318 6617 opts[0] |= FirstFrag | LastFrag;
1da177e4
LT		 6618 tp->tx_skb[entry].skb = skb;
6619 }
6620
2b7b4318
FR		 6621 txd->opts2 = cpu_to_le32(opts[1]);
6622
5047fb5d
RC		 6623 skb_tx_timestamp(skb);
6624
1da177e4
LT		 6625 wmb();
6626
cecb5fd7 6627 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318 6628 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 6629 txd->opts1 = cpu_to_le32(status);
6630
1da177e4
LT		 6631 tp->cur_tx += frags + 1;
6632
4c020a96 6633 wmb();
1da177e4 6634
cecb5fd7 6635 RTL_W8(TxPoll, NPQ);
1da177e4 6636
da78dbff
FR		 6637 mmiowb();
6638
477206a0 6639 if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
ae1f23fb
FR		 6640 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
6641 * not miss a ring update when it notices a stopped queue.
6642 */
6643 smp_wmb();
1da177e4 6644 netif_stop_queue(dev);
ae1f23fb
FR		 6645 /* Sync with rtl_tx:
6646 * - publish queue status and cur_tx ring index (write barrier)
6647 * - refresh dirty_tx ring index (read barrier).
6648 * May the current thread have a pessimistic view of the ring
6649 * status and forget to wake up queue, a racing rtl_tx thread
6650 * can't.
6651 */
1e874e04 6652 smp_mb();
477206a0 6653 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
1da177e4
LT		 6654 netif_wake_queue(dev);
6655 }
6656
61357325 6657 return NETDEV_TX_OK;
1da177e4 6658
3eafe507 6659err_dma_1:
48addcc9 6660 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
3eafe507 6661err_dma_0:
989c9ba1 6662 dev_kfree_skb_any(skb);
3eafe507
SG		 6663 dev->stats.tx_dropped++;
6664 return NETDEV_TX_OK;
6665
6666err_stop_0:
1da177e4 6667 netif_stop_queue(dev);
cebf8cc7 6668 dev->stats.tx_dropped++;
61357325 6669 return NETDEV_TX_BUSY;
1da177e4
LT		 6670}
6671
6672static void rtl8169_pcierr_interrupt(struct net_device *dev)
6673{
6674 struct rtl8169_private *tp = netdev_priv(dev);
6675 struct pci_dev *pdev = tp->pci_dev;
1da177e4
LT		 6676 u16 pci_status, pci_cmd;
6677
6678 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
6679 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
6680
bf82c189
JP		 6681 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
6682 pci_cmd, pci_status);
1da177e4
LT		 6683
6684 /*
6685 * The recovery sequence below admits a very elaborated explanation:
6686 * - it seems to work;
d03902b8
FR		 6687 * - I did not see what else could be done;
6688 * - it makes iop3xx happy.
1da177e4
LT		 6689 *
6690 * Feel free to adjust to your needs.
6691 */
a27993f3 6692 if (pdev->broken_parity_status)
d03902b8
FR		 6693 pci_cmd &= ~PCI_COMMAND_PARITY;
6694 else
6695 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
6696
6697 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 6698
6699 pci_write_config_word(pdev, PCI_STATUS,
6700 pci_status & (PCI_STATUS_DETECTED_PARITY |
6701 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
6702 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
6703
6704 /* The infamous DAC f*ckup only happens at boot time */
9fba0812 6705 if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
e6de30d6 6706 void __iomem *ioaddr = tp->mmio_addr;
6707
bf82c189 6708 netif_info(tp, intr, dev, "disabling PCI DAC\n");
1da177e4
LT		 6709 tp->cp_cmd &= ~PCIDAC;
6710 RTL_W16(CPlusCmd, tp->cp_cmd);
6711 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 6712 }
6713
e6de30d6 6714 rtl8169_hw_reset(tp);
d03902b8 6715
98ddf986 6716 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 6717}
6718
da78dbff 6719static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
1da177e4
LT		 6720{
6721 unsigned int dirty_tx, tx_left;
6722
1da177e4
LT		 6723 dirty_tx = tp->dirty_tx;
6724 smp_rmb();
6725 tx_left = tp->cur_tx - dirty_tx;
6726
6727 while (tx_left > 0) {
6728 unsigned int entry = dirty_tx % NUM_TX_DESC;
6729 struct ring_info *tx_skb = tp->tx_skb + entry;
1da177e4
LT		 6730 u32 status;
6731
6732 rmb();
6733 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
6734 if (status & DescOwn)
6735 break;
6736
48addcc9
SG		 6737 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
6738 tp->TxDescArray + entry);
1da177e4 6739 if (status & LastFrag) {
17bcb684
FR		 6740 u64_stats_update_begin(&tp->tx_stats.syncp);
6741 tp->tx_stats.packets++;
6742 tp->tx_stats.bytes += tx_skb->skb->len;
6743 u64_stats_update_end(&tp->tx_stats.syncp);
989c9ba1 6744 dev_kfree_skb_any(tx_skb->skb);
1da177e4
LT		 6745 tx_skb->skb = NULL;
6746 }
6747 dirty_tx++;
6748 tx_left--;
6749 }
6750
6751 if (tp->dirty_tx != dirty_tx) {
6752 tp->dirty_tx = dirty_tx;
ae1f23fb
FR		 6753 /* Sync with rtl8169_start_xmit:
6754 * - publish dirty_tx ring index (write barrier)
6755 * - refresh cur_tx ring index and queue status (read barrier)
6756 * May the current thread miss the stopped queue condition,
6757 * a racing xmit thread can only have a right view of the
6758 * ring status.
6759 */
1e874e04 6760 smp_mb();
1da177e4 6761 if (netif_queue_stopped(dev) &&
477206a0 6762 TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
1da177e4
LT		 6763 netif_wake_queue(dev);
6764 }
d78ae2dc
FR		 6765 /*
6766 * 8168 hack: TxPoll requests are lost when the Tx packets are
6767 * too close. Let's kick an extra TxPoll request when a burst
6768 * of start_xmit activity is detected (if it is not detected,
6769 * it is slow enough). -- FR
6770 */
da78dbff
FR		 6771 if (tp->cur_tx != dirty_tx) {
6772 void __iomem *ioaddr = tp->mmio_addr;
6773
d78ae2dc 6774 RTL_W8(TxPoll, NPQ);
da78dbff 6775 }
1da177e4
LT		 6776 }
6777}
6778
126fa4b9
FR		 6779static inline int rtl8169_fragmented_frame(u32 status)
6780{
6781 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
6782}
6783
adea1ac7 6784static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
1da177e4 6785{
1da177e4
LT		 6786 u32 status = opts1 & RxProtoMask;
6787
6788 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
d5d3ebe3 6789 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
1da177e4
LT		 6790 skb->ip_summed = CHECKSUM_UNNECESSARY;
6791 else
bc8acf2c 6792 skb_checksum_none_assert(skb);
1da177e4
LT		 6793}
6794
6f0333b8
ED		 6795static struct sk_buff *rtl8169_try_rx_copy(void *data,
6796 struct rtl8169_private *tp,
6797 int pkt_size,
6798 dma_addr_t addr)
1da177e4 6799{
b449655f 6800 struct sk_buff *skb;
48addcc9 6801 struct device *d = &tp->pci_dev->dev;
b449655f 6802
6f0333b8 6803 data = rtl8169_align(data);
48addcc9 6804 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6f0333b8
ED		 6805 prefetch(data);
6806 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
6807 if (skb)
6808 memcpy(skb->data, data, pkt_size);
48addcc9
SG		 6809 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
6810
6f0333b8 6811 return skb;
1da177e4
LT		 6812}
6813
da78dbff 6814static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
1da177e4
LT		 6815{
6816 unsigned int cur_rx, rx_left;
6f0333b8 6817 unsigned int count;
1da177e4 6818
1da177e4 6819 cur_rx = tp->cur_rx;
1da177e4 6820
9fba0812 6821 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
1da177e4 6822 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 6823 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 6824 u32 status;
6825
6826 rmb();
e03f33af 6827 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
1da177e4
LT		 6828
6829 if (status & DescOwn)
6830 break;
4dcb7d33 6831 if (unlikely(status & RxRES)) {
bf82c189
JP		 6832 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6833 status);
cebf8cc7 6834 dev->stats.rx_errors++;
1da177e4 6835 if (status & (RxRWT | RxRUNT))
cebf8cc7 6836 dev->stats.rx_length_errors++;
1da177e4 6837 if (status & RxCRC)
cebf8cc7 6838 dev->stats.rx_crc_errors++;
9dccf611 6839 if (status & RxFOVF) {
da78dbff 6840 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
cebf8cc7 6841 dev->stats.rx_fifo_errors++;
9dccf611 6842 }
6bbe021d
BG		 6843 if ((status & (RxRUNT | RxCRC)) &&
6844 !(status & (RxRWT | RxFOVF)) &&
6845 (dev->features & NETIF_F_RXALL))
6846 goto process_pkt;
1da177e4 6847 } else {
6f0333b8 6848 struct sk_buff *skb;
6bbe021d
BG		 6849 dma_addr_t addr;
6850 int pkt_size;
6851
6852process_pkt:
6853 addr = le64_to_cpu(desc->addr);
79d0c1d2
BG		 6854 if (likely(!(dev->features & NETIF_F_RXFCS)))
6855 pkt_size = (status & 0x00003fff) - 4;
6856 else
6857 pkt_size = status & 0x00003fff;
1da177e4 6858
126fa4b9
FR		 6859 /*
6860 * The driver does not support incoming fragmented
6861 * frames. They are seen as a symptom of over-mtu
6862 * sized frames.
6863 */
6864 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 6865 dev->stats.rx_dropped++;
6866 dev->stats.rx_length_errors++;
ce11ff5e 6867 goto release_descriptor;
126fa4b9
FR		 6868 }
6869
6f0333b8
ED		 6870 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6871 tp, pkt_size, addr);
6f0333b8
ED		 6872 if (!skb) {
6873 dev->stats.rx_dropped++;
ce11ff5e 6874 goto release_descriptor;
1da177e4
LT		 6875 }
6876
adea1ac7 6877 rtl8169_rx_csum(skb, status);
1da177e4
LT		 6878 skb_put(skb, pkt_size);
6879 skb->protocol = eth_type_trans(skb, dev);
6880
7a8fc77b
FR		 6881 rtl8169_rx_vlan_tag(desc, skb);
6882
56de414c 6883 napi_gro_receive(&tp->napi, skb);
1da177e4 6884
8027aa24
JW		 6885 u64_stats_update_begin(&tp->rx_stats.syncp);
6886 tp->rx_stats.packets++;
6887 tp->rx_stats.bytes += pkt_size;
6888 u64_stats_update_end(&tp->rx_stats.syncp);
1da177e4 6889 }
ce11ff5e 6890release_descriptor:
6891 desc->opts2 = 0;
6892 wmb();
6893 rtl8169_mark_to_asic(desc, rx_buf_sz);
1da177e4
LT		 6894 }
6895
6896 count = cur_rx - tp->cur_rx;
6897 tp->cur_rx = cur_rx;
6898
1da177e4
LT		 6899 return count;
6900}
6901
07d3f51f 6902static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 6903{
07d3f51f 6904 struct net_device *dev = dev_instance;
1da177e4 6905 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 6906 int handled = 0;
9085cdfa 6907 u16 status;
1da177e4 6908
9085cdfa 6909 status = rtl_get_events(tp);
da78dbff
FR		 6910 if (status && status != 0xffff) {
6911 status &= RTL_EVENT_NAPI | tp->event_slow;
6912 if (status) {
6913 handled = 1;
1da177e4 6914
da78dbff
FR		 6915 rtl_irq_disable(tp);
6916 napi_schedule(&tp->napi);
f11a377b 6917 }
da78dbff
FR		 6918 }
6919 return IRQ_RETVAL(handled);
6920}
1da177e4 6921
da78dbff
FR		 6922/*
6923 * Workqueue context.
6924 */
6925static void rtl_slow_event_work(struct rtl8169_private *tp)
6926{
6927 struct net_device *dev = tp->dev;
6928 u16 status;
6929
6930 status = rtl_get_events(tp) & tp->event_slow;
6931 rtl_ack_events(tp, status);
1da177e4 6932
da78dbff
FR		 6933 if (unlikely(status & RxFIFOOver)) {
6934 switch (tp->mac_version) {
6935 /* Work around for rx fifo overflow */
6936 case RTL_GIGA_MAC_VER_11:
6937 netif_stop_queue(dev);
934714d0
FR		 6938 /* XXX - Hack alert. See rtl_task(). */
6939 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
da78dbff 6940 default:
f11a377b
DD		 6941 break;
6942 }
da78dbff 6943 }
1da177e4 6944
da78dbff
FR		 6945 if (unlikely(status & SYSErr))
6946 rtl8169_pcierr_interrupt(dev);
0e485150 6947
da78dbff
FR		 6948 if (status & LinkChg)
6949 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
1da177e4 6950
7dbb4918 6951 rtl_irq_enable_all(tp);
1da177e4
LT		 6952}
6953
4422bcd4
FR		 6954static void rtl_task(struct work_struct *work)
6955{
da78dbff
FR		 6956 static const struct {
6957 int bitnr;
6958 void (*action)(struct rtl8169_private *);
6959 } rtl_work[] = {
934714d0 6960 /* XXX - keep rtl_slow_event_work() as first element. */
da78dbff
FR		 6961 { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work },
6962 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
6963 { RTL_FLAG_TASK_PHY_PENDING, rtl_phy_work }
6964 };
4422bcd4
FR		 6965 struct rtl8169_private *tp =
6966 container_of(work, struct rtl8169_private, wk.work);
da78dbff
FR		 6967 struct net_device *dev = tp->dev;
6968 int i;
6969
6970 rtl_lock_work(tp);
6971
6c4a70c5
FR		 6972 if (!netif_running(dev) ||
6973 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
da78dbff
FR		 6974 goto out_unlock;
6975
6976 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6977 bool pending;
6978
da78dbff 6979 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
da78dbff
FR		 6980 if (pending)
6981 rtl_work[i].action(tp);
6982 }
4422bcd4 6983
da78dbff
FR		 6984out_unlock:
6985 rtl_unlock_work(tp);
4422bcd4
FR		 6986}
6987
bea3348e 6988static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 6989{
bea3348e
SH		 6990 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6991 struct net_device *dev = tp->dev;
da78dbff
FR		 6992 u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
6993 int work_done= 0;
6994 u16 status;
6995
6996 status = rtl_get_events(tp);
6997 rtl_ack_events(tp, status & ~tp->event_slow);
6998
6999 if (status & RTL_EVENT_NAPI_RX)
7000 work_done = rtl_rx(dev, tp, (u32) budget);
7001
7002 if (status & RTL_EVENT_NAPI_TX)
7003 rtl_tx(dev, tp);
1da177e4 7004
da78dbff
FR		 7005 if (status & tp->event_slow) {
7006 enable_mask &= ~tp->event_slow;
7007
7008 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
7009 }
1da177e4 7010
bea3348e 7011 if (work_done < budget) {
288379f0 7012 napi_complete(napi);
f11a377b 7013
da78dbff
FR		 7014 rtl_irq_enable(tp, enable_mask);
7015 mmiowb();
1da177e4
LT		 7016 }
7017
bea3348e 7018 return work_done;
1da177e4 7019}
1da177e4 7020
523a6094
FR		 7021static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
7022{
7023 struct rtl8169_private *tp = netdev_priv(dev);
7024
7025 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
7026 return;
7027
7028 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
7029 RTL_W32(RxMissed, 0);
7030}
7031
1da177e4
LT		 7032static void rtl8169_down(struct net_device *dev)
7033{
7034 struct rtl8169_private *tp = netdev_priv(dev);
7035 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 7036
4876cc1e 7037 del_timer_sync(&tp->timer);
1da177e4 7038
93dd79e8 7039 napi_disable(&tp->napi);
da78dbff 7040 netif_stop_queue(dev);
1da177e4 7041
92fc43b4 7042 rtl8169_hw_reset(tp);
323bb685
SG		 7043 /*
7044 * At this point device interrupts can not be enabled in any function,
209e5ac8
FR		 7045 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
7046 * and napi is disabled (rtl8169_poll).
323bb685 7047 */
523a6094 7048 rtl8169_rx_missed(dev, ioaddr);
1da177e4 7049
1da177e4 7050 /* Give a racing hard_start_xmit a few cycles to complete. */
da78dbff 7051 synchronize_sched();
1da177e4 7052
1da177e4
LT		 7053 rtl8169_tx_clear(tp);
7054
7055 rtl8169_rx_clear(tp);
065c27c1 7056
7057 rtl_pll_power_down(tp);
1da177e4
LT		 7058}
7059
7060static int rtl8169_close(struct net_device *dev)
7061{
7062 struct rtl8169_private *tp = netdev_priv(dev);
7063 struct pci_dev *pdev = tp->pci_dev;
7064
e1759441
RW		 7065 pm_runtime_get_sync(&pdev->dev);
7066
cecb5fd7 7067 /* Update counters before going down */
355423d0
IV		 7068 rtl8169_update_counters(dev);
7069
da78dbff 7070 rtl_lock_work(tp);
6c4a70c5 7071 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
da78dbff 7072
1da177e4 7073 rtl8169_down(dev);
da78dbff 7074 rtl_unlock_work(tp);
1da177e4 7075
4ea72445
L		 7076 cancel_work_sync(&tp->wk.work);
7077
92a7c4e7 7078 free_irq(pdev->irq, dev);
1da177e4 7079
82553bb6
SG		 7080 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7081 tp->RxPhyAddr);
7082 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7083 tp->TxPhyAddr);
1da177e4
LT		 7084 tp->TxDescArray = NULL;
7085 tp->RxDescArray = NULL;
7086
e1759441
RW		 7087 pm_runtime_put_sync(&pdev->dev);
7088
1da177e4
LT		 7089 return 0;
7090}
7091
dc1c00ce
FR		 7092#ifdef CONFIG_NET_POLL_CONTROLLER
7093static void rtl8169_netpoll(struct net_device *dev)
7094{
7095 struct rtl8169_private *tp = netdev_priv(dev);
7096
7097 rtl8169_interrupt(tp->pci_dev->irq, dev);
7098}
7099#endif
7100
df43ac78
FR		 7101static int rtl_open(struct net_device *dev)
7102{
7103 struct rtl8169_private *tp = netdev_priv(dev);
7104 void __iomem *ioaddr = tp->mmio_addr;
7105 struct pci_dev *pdev = tp->pci_dev;
7106 int retval = -ENOMEM;
7107
7108 pm_runtime_get_sync(&pdev->dev);
7109
7110 /*
e75d6606 7111 * Rx and Tx descriptors needs 256 bytes alignment.
df43ac78
FR		 7112 * dma_alloc_coherent provides more.
7113 */
7114 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
7115 &tp->TxPhyAddr, GFP_KERNEL);
7116 if (!tp->TxDescArray)
7117 goto err_pm_runtime_put;
7118
7119 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
7120 &tp->RxPhyAddr, GFP_KERNEL);
7121 if (!tp->RxDescArray)
7122 goto err_free_tx_0;
7123
7124 retval = rtl8169_init_ring(dev);
7125 if (retval < 0)
7126 goto err_free_rx_1;
7127
7128 INIT_WORK(&tp->wk.work, rtl_task);
7129
7130 smp_mb();
7131
7132 rtl_request_firmware(tp);
7133
92a7c4e7 7134 retval = request_irq(pdev->irq, rtl8169_interrupt,
df43ac78
FR		 7135 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
7136 dev->name, dev);
7137 if (retval < 0)
7138 goto err_release_fw_2;
7139
7140 rtl_lock_work(tp);
7141
7142 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7143
7144 napi_enable(&tp->napi);
7145
7146 rtl8169_init_phy(dev, tp);
7147
7148 __rtl8169_set_features(dev, dev->features);
7149
7150 rtl_pll_power_up(tp);
7151
7152 rtl_hw_start(dev);
7153
7154 netif_start_queue(dev);
7155
7156 rtl_unlock_work(tp);
7157
7158 tp->saved_wolopts = 0;
7159 pm_runtime_put_noidle(&pdev->dev);
7160
7161 rtl8169_check_link_status(dev, tp, ioaddr);
7162out:
7163 return retval;
7164
7165err_release_fw_2:
7166 rtl_release_firmware(tp);
7167 rtl8169_rx_clear(tp);
7168err_free_rx_1:
7169 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7170 tp->RxPhyAddr);
7171 tp->RxDescArray = NULL;
7172err_free_tx_0:
7173 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7174 tp->TxPhyAddr);
7175 tp->TxDescArray = NULL;
7176err_pm_runtime_put:
7177 pm_runtime_put_noidle(&pdev->dev);
7178 goto out;
7179}
7180
8027aa24
JW		 7181static struct rtnl_link_stats64 *
7182rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
1da177e4
LT		 7183{
7184 struct rtl8169_private *tp = netdev_priv(dev);
7185 void __iomem *ioaddr = tp->mmio_addr;
8027aa24 7186 unsigned int start;
1da177e4 7187
da78dbff 7188 if (netif_running(dev))
523a6094 7189 rtl8169_rx_missed(dev, ioaddr);
5b0384f4 7190
8027aa24 7191 do {
57a7744e 7192 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
8027aa24
JW		 7193 stats->rx_packets = tp->rx_stats.packets;
7194 stats->rx_bytes = tp->rx_stats.bytes;
57a7744e 7195 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
8027aa24
JW		 7196
7197
7198 do {
57a7744e 7199 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
8027aa24
JW		 7200 stats->tx_packets = tp->tx_stats.packets;
7201 stats->tx_bytes = tp->tx_stats.bytes;
57a7744e 7202 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
8027aa24
JW		 7203
7204 stats->rx_dropped = dev->stats.rx_dropped;
7205 stats->tx_dropped = dev->stats.tx_dropped;
7206 stats->rx_length_errors = dev->stats.rx_length_errors;
7207 stats->rx_errors = dev->stats.rx_errors;
7208 stats->rx_crc_errors = dev->stats.rx_crc_errors;
7209 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
7210 stats->rx_missed_errors = dev->stats.rx_missed_errors;
7211
7212 return stats;
1da177e4
LT		 7213}
7214
861ab440 7215static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 7216{
065c27c1 7217 struct rtl8169_private *tp = netdev_priv(dev);
7218
5d06a99f 7219 if (!netif_running(dev))
861ab440 7220 return;
5d06a99f
FR		 7221
7222 netif_device_detach(dev);
7223 netif_stop_queue(dev);
da78dbff
FR		 7224
7225 rtl_lock_work(tp);
7226 napi_disable(&tp->napi);
6c4a70c5 7227 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
da78dbff
FR		 7228 rtl_unlock_work(tp);
7229
7230 rtl_pll_power_down(tp);
861ab440
RW		 7231}
7232
7233#ifdef CONFIG_PM
7234
7235static int rtl8169_suspend(struct device *device)
7236{
7237 struct pci_dev *pdev = to_pci_dev(device);
7238 struct net_device *dev = pci_get_drvdata(pdev);
5d06a99f 7239
861ab440 7240 rtl8169_net_suspend(dev);
1371fa6d 7241
5d06a99f
FR		 7242 return 0;
7243}
7244
e1759441
RW		 7245static void __rtl8169_resume(struct net_device *dev)
7246{
065c27c1 7247 struct rtl8169_private *tp = netdev_priv(dev);
7248
e1759441 7249 netif_device_attach(dev);
065c27c1 7250
7251 rtl_pll_power_up(tp);
7252
cff4c162
AS		 7253 rtl_lock_work(tp);
7254 napi_enable(&tp->napi);
6c4a70c5 7255 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
cff4c162 7256 rtl_unlock_work(tp);
da78dbff 7257
98ddf986 7258 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
e1759441
RW		 7259}
7260
861ab440 7261static int rtl8169_resume(struct device *device)
5d06a99f 7262{
861ab440 7263 struct pci_dev *pdev = to_pci_dev(device);
5d06a99f 7264 struct net_device *dev = pci_get_drvdata(pdev);
fccec10b
SG		 7265 struct rtl8169_private *tp = netdev_priv(dev);
7266
7267 rtl8169_init_phy(dev, tp);
5d06a99f 7268
e1759441
RW		 7269 if (netif_running(dev))
7270 __rtl8169_resume(dev);
5d06a99f 7271
e1759441
RW		 7272 return 0;
7273}
7274
7275static int rtl8169_runtime_suspend(struct device *device)
7276{
7277 struct pci_dev *pdev = to_pci_dev(device);
7278 struct net_device *dev = pci_get_drvdata(pdev);
7279 struct rtl8169_private *tp = netdev_priv(dev);
7280
7281 if (!tp->TxDescArray)
7282 return 0;
7283
da78dbff 7284 rtl_lock_work(tp);
e1759441
RW		 7285 tp->saved_wolopts = __rtl8169_get_wol(tp);
7286 __rtl8169_set_wol(tp, WAKE_ANY);
da78dbff 7287 rtl_unlock_work(tp);
e1759441
RW		 7288
7289 rtl8169_net_suspend(dev);
7290
7291 return 0;
7292}
7293
7294static int rtl8169_runtime_resume(struct device *device)
7295{
7296 struct pci_dev *pdev = to_pci_dev(device);
7297 struct net_device *dev = pci_get_drvdata(pdev);
7298 struct rtl8169_private *tp = netdev_priv(dev);
7299
7300 if (!tp->TxDescArray)
7301 return 0;
7302
da78dbff 7303 rtl_lock_work(tp);
e1759441
RW		 7304 __rtl8169_set_wol(tp, tp->saved_wolopts);
7305 tp->saved_wolopts = 0;
da78dbff 7306 rtl_unlock_work(tp);
e1759441 7307
fccec10b
SG		 7308 rtl8169_init_phy(dev, tp);
7309
e1759441 7310 __rtl8169_resume(dev);
5d06a99f 7311
5d06a99f
FR		 7312 return 0;
7313}
7314
e1759441
RW		 7315static int rtl8169_runtime_idle(struct device *device)
7316{
7317 struct pci_dev *pdev = to_pci_dev(device);
7318 struct net_device *dev = pci_get_drvdata(pdev);
7319 struct rtl8169_private *tp = netdev_priv(dev);
7320
e4fbce74 7321 return tp->TxDescArray ? -EBUSY : 0;
e1759441
RW		 7322}
7323
47145210 7324static const struct dev_pm_ops rtl8169_pm_ops = {
cecb5fd7
FR		 7325 .suspend = rtl8169_suspend,
7326 .resume = rtl8169_resume,
7327 .freeze = rtl8169_suspend,
7328 .thaw = rtl8169_resume,
7329 .poweroff = rtl8169_suspend,
7330 .restore = rtl8169_resume,
7331 .runtime_suspend = rtl8169_runtime_suspend,
7332 .runtime_resume = rtl8169_runtime_resume,
7333 .runtime_idle = rtl8169_runtime_idle,
861ab440
RW		 7334};
7335
7336#define RTL8169_PM_OPS (&rtl8169_pm_ops)
7337
7338#else /* !CONFIG_PM */
7339
7340#define RTL8169_PM_OPS NULL
7341
7342#endif /* !CONFIG_PM */
7343
649b3b8c 7344static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
7345{
7346 void __iomem *ioaddr = tp->mmio_addr;
7347
7348 /* WoL fails with 8168b when the receiver is disabled. */
7349 switch (tp->mac_version) {
7350 case RTL_GIGA_MAC_VER_11:
7351 case RTL_GIGA_MAC_VER_12:
7352 case RTL_GIGA_MAC_VER_17:
7353 pci_clear_master(tp->pci_dev);
7354
7355 RTL_W8(ChipCmd, CmdRxEnb);
7356 /* PCI commit */
7357 RTL_R8(ChipCmd);
7358 break;
7359 default:
7360 break;
7361 }
7362}
7363
1765f95d
FR		 7364static void rtl_shutdown(struct pci_dev *pdev)
7365{
861ab440 7366 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 7367 struct rtl8169_private *tp = netdev_priv(dev);
2a15cd2f 7368 struct device *d = &pdev->dev;
7369
7370 pm_runtime_get_sync(d);
861ab440
RW		 7371
7372 rtl8169_net_suspend(dev);
1765f95d 7373
cecb5fd7 7374 /* Restore original MAC address */
cc098dc7
IV		 7375 rtl_rar_set(tp, dev->perm_addr);
7376
92fc43b4 7377 rtl8169_hw_reset(tp);
4bb3f522 7378
861ab440 7379 if (system_state == SYSTEM_POWER_OFF) {
649b3b8c 7380 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
7381 rtl_wol_suspend_quirk(tp);
7382 rtl_wol_shutdown_quirk(tp);
ca52efd5 7383 }
7384
861ab440
RW		 7385 pci_wake_from_d3(pdev, true);
7386 pci_set_power_state(pdev, PCI_D3hot);
7387 }
2a15cd2f 7388
7389 pm_runtime_put_noidle(d);
861ab440 7390}
5d06a99f 7391
baf63293 7392static void rtl_remove_one(struct pci_dev *pdev)
e27566ed
FR		 7393{
7394 struct net_device *dev = pci_get_drvdata(pdev);
7395 struct rtl8169_private *tp = netdev_priv(dev);
7396
7397 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
7398 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
7399 tp->mac_version == RTL_GIGA_MAC_VER_31) {
7400 rtl8168_driver_stop(tp);
7401 }
7402
ad1be8d3
DN		 7403 netif_napi_del(&tp->napi);
7404
e27566ed
FR		 7405 unregister_netdev(dev);
7406
7407 rtl_release_firmware(tp);
7408
7409 if (pci_dev_run_wake(pdev))
7410 pm_runtime_get_noresume(&pdev->dev);
7411
7412 /* restore original MAC address */
7413 rtl_rar_set(tp, dev->perm_addr);
7414
7415 rtl_disable_msi(pdev, tp);
7416 rtl8169_release_board(pdev, dev, tp->mmio_addr);
e27566ed
FR		 7417}
7418
fa9c385e 7419static const struct net_device_ops rtl_netdev_ops = {
df43ac78 7420 .ndo_open = rtl_open,
fa9c385e
FR		 7421 .ndo_stop = rtl8169_close,
7422 .ndo_get_stats64 = rtl8169_get_stats64,
7423 .ndo_start_xmit = rtl8169_start_xmit,
7424 .ndo_tx_timeout = rtl8169_tx_timeout,
7425 .ndo_validate_addr = eth_validate_addr,
7426 .ndo_change_mtu = rtl8169_change_mtu,
7427 .ndo_fix_features = rtl8169_fix_features,
7428 .ndo_set_features = rtl8169_set_features,
7429 .ndo_set_mac_address = rtl_set_mac_address,
7430 .ndo_do_ioctl = rtl8169_ioctl,
7431 .ndo_set_rx_mode = rtl_set_rx_mode,
7432#ifdef CONFIG_NET_POLL_CONTROLLER
7433 .ndo_poll_controller = rtl8169_netpoll,
7434#endif
7435
7436};
7437
31fa8b18
FR		 7438static const struct rtl_cfg_info {
7439 void (*hw_start)(struct net_device *);
7440 unsigned int region;
7441 unsigned int align;
7442 u16 event_slow;
7443 unsigned features;
7444 u8 default_ver;
7445} rtl_cfg_infos [] = {
7446 [RTL_CFG_0] = {
7447 .hw_start = rtl_hw_start_8169,
7448 .region = 1,
7449 .align = 0,
7450 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
7451 .features = RTL_FEATURE_GMII,
7452 .default_ver = RTL_GIGA_MAC_VER_01,
7453 },
7454 [RTL_CFG_1] = {
7455 .hw_start = rtl_hw_start_8168,
7456 .region = 2,
7457 .align = 8,
7458 .event_slow = SYSErr | LinkChg | RxOverflow,
7459 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
7460 .default_ver = RTL_GIGA_MAC_VER_11,
7461 },
7462 [RTL_CFG_2] = {
7463 .hw_start = rtl_hw_start_8101,
7464 .region = 2,
7465 .align = 8,
7466 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
7467 PCSTimeout,
7468 .features = RTL_FEATURE_MSI,
7469 .default_ver = RTL_GIGA_MAC_VER_13,
7470 }
7471};
7472
7473/* Cfg9346_Unlock assumed. */
7474static unsigned rtl_try_msi(struct rtl8169_private *tp,
7475 const struct rtl_cfg_info *cfg)
7476{
7477 void __iomem *ioaddr = tp->mmio_addr;
7478 unsigned msi = 0;
7479 u8 cfg2;
7480
7481 cfg2 = RTL_R8(Config2) & ~MSIEnable;
7482 if (cfg->features & RTL_FEATURE_MSI) {
7483 if (pci_enable_msi(tp->pci_dev)) {
7484 netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
7485 } else {
7486 cfg2 |= MSIEnable;
7487 msi = RTL_FEATURE_MSI;
7488 }
7489 }
7490 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
7491 RTL_W8(Config2, cfg2);
7492 return msi;
7493}
7494
c558386b
HW		 7495DECLARE_RTL_COND(rtl_link_list_ready_cond)
7496{
7497 void __iomem *ioaddr = tp->mmio_addr;
7498
7499 return RTL_R8(MCU) & LINK_LIST_RDY;
7500}
7501
7502DECLARE_RTL_COND(rtl_rxtx_empty_cond)
7503{
7504 void __iomem *ioaddr = tp->mmio_addr;
7505
7506 return (RTL_R8(MCU) & RXTX_EMPTY) == RXTX_EMPTY;
7507}
7508
baf63293 7509static void rtl_hw_init_8168g(struct rtl8169_private *tp)
c558386b
HW		 7510{
7511 void __iomem *ioaddr = tp->mmio_addr;
7512 u32 data;
7513
7514 tp->ocp_base = OCP_STD_PHY_BASE;
7515
7516 RTL_W32(MISC, RTL_R32(MISC) | RXDV_GATED_EN);
7517
7518 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
7519 return;
7520
7521 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
7522 return;
7523
7524 RTL_W8(ChipCmd, RTL_R8(ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
7525 msleep(1);
7526 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
7527
5f8bcce9 7528 data = r8168_mac_ocp_read(tp, 0xe8de);
c558386b
HW		 7529 data &= ~(1 << 14);
7530 r8168_mac_ocp_write(tp, 0xe8de, data);
7531
7532 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7533 return;
7534
5f8bcce9 7535 data = r8168_mac_ocp_read(tp, 0xe8de);
c558386b
HW		 7536 data |= (1 << 15);
7537 r8168_mac_ocp_write(tp, 0xe8de, data);
7538
7539 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7540 return;
7541}
7542
baf63293 7543static void rtl_hw_initialize(struct rtl8169_private *tp)
c558386b
HW		 7544{
7545 switch (tp->mac_version) {
7546 case RTL_GIGA_MAC_VER_40:
7547 case RTL_GIGA_MAC_VER_41:
57538c4a 7548 case RTL_GIGA_MAC_VER_42:
58152cd4 7549 case RTL_GIGA_MAC_VER_43:
45dd95c4 7550 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 7551 case RTL_GIGA_MAC_VER_45:
7552 case RTL_GIGA_MAC_VER_46:
7553 case RTL_GIGA_MAC_VER_47:
7554 case RTL_GIGA_MAC_VER_48:
c558386b
HW		 7555 rtl_hw_init_8168g(tp);
7556 break;
7557
7558 default:
7559 break;
7560 }
7561}
7562
929a031d 7563static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3b6cf25d
FR		 7564{
7565 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
7566 const unsigned int region = cfg->region;
7567 struct rtl8169_private *tp;
7568 struct mii_if_info *mii;
7569 struct net_device *dev;
7570 void __iomem *ioaddr;
7571 int chipset, i;
7572 int rc;
7573
7574 if (netif_msg_drv(&debug)) {
7575 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
7576 MODULENAME, RTL8169_VERSION);
7577 }
7578
7579 dev = alloc_etherdev(sizeof (*tp));
7580 if (!dev) {
7581 rc = -ENOMEM;
7582 goto out;
7583 }
7584
7585 SET_NETDEV_DEV(dev, &pdev->dev);
fa9c385e 7586 dev->netdev_ops = &rtl_netdev_ops;
3b6cf25d
FR		 7587 tp = netdev_priv(dev);
7588 tp->dev = dev;
7589 tp->pci_dev = pdev;
7590 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
7591
7592 mii = &tp->mii;
7593 mii->dev = dev;
7594 mii->mdio_read = rtl_mdio_read;
7595 mii->mdio_write = rtl_mdio_write;
7596 mii->phy_id_mask = 0x1f;
7597 mii->reg_num_mask = 0x1f;
7598 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
7599
7600 /* disable ASPM completely as that cause random device stop working
7601 * problems as well as full system hangs for some PCIe devices users */
7602 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
7603 PCIE_LINK_STATE_CLKPM);
7604
7605 /* enable device (incl. PCI PM wakeup and hotplug setup) */
7606 rc = pci_enable_device(pdev);
7607 if (rc < 0) {
7608 netif_err(tp, probe, dev, "enable failure\n");
7609 goto err_out_free_dev_1;
7610 }
7611
7612 if (pci_set_mwi(pdev) < 0)
7613 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
7614
7615 /* make sure PCI base addr 1 is MMIO */
7616 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
7617 netif_err(tp, probe, dev,
7618 "region #%d not an MMIO resource, aborting\n",
7619 region);
7620 rc = -ENODEV;
7621 goto err_out_mwi_2;
7622 }
7623
7624 /* check for weird/broken PCI region reporting */
7625 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
7626 netif_err(tp, probe, dev,
7627 "Invalid PCI region size(s), aborting\n");
7628 rc = -ENODEV;
7629 goto err_out_mwi_2;
7630 }
7631
7632 rc = pci_request_regions(pdev, MODULENAME);
7633 if (rc < 0) {
7634 netif_err(tp, probe, dev, "could not request regions\n");
7635 goto err_out_mwi_2;
7636 }
7637
929a031d 7638 tp->cp_cmd = 0;
3b6cf25d
FR		 7639
7640 if ((sizeof(dma_addr_t) > 4) &&
7641 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
7642 tp->cp_cmd |= PCIDAC;
7643 dev->features |= NETIF_F_HIGHDMA;
7644 } else {
7645 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
7646 if (rc < 0) {
7647 netif_err(tp, probe, dev, "DMA configuration failed\n");
7648 goto err_out_free_res_3;
7649 }
7650 }
7651
7652 /* ioremap MMIO region */
7653 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
7654 if (!ioaddr) {
7655 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
7656 rc = -EIO;
7657 goto err_out_free_res_3;
7658 }
7659 tp->mmio_addr = ioaddr;
7660
7661 if (!pci_is_pcie(pdev))
7662 netif_info(tp, probe, dev, "not PCI Express\n");
7663
7664 /* Identify chip attached to board */
7665 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
7666
7667 rtl_init_rxcfg(tp);
7668
7669 rtl_irq_disable(tp);
7670
c558386b
HW		 7671 rtl_hw_initialize(tp);
7672
3b6cf25d
FR		 7673 rtl_hw_reset(tp);
7674
7675 rtl_ack_events(tp, 0xffff);
7676
7677 pci_set_master(pdev);
7678
3b6cf25d
FR		 7679 rtl_init_mdio_ops(tp);
7680 rtl_init_pll_power_ops(tp);
7681 rtl_init_jumbo_ops(tp);
beb1fe18 7682 rtl_init_csi_ops(tp);
3b6cf25d
FR		 7683
7684 rtl8169_print_mac_version(tp);
7685
7686 chipset = tp->mac_version;
7687 tp->txd_version = rtl_chip_infos[chipset].txd_version;
7688
7689 RTL_W8(Cfg9346, Cfg9346_Unlock);
7690 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
8f9d5138 7691 RTL_W8(Config5, RTL_R8(Config5) & (BWF | MWF | UWF | LanWake | PMEStatus));
6e1d0b89 7692 switch (tp->mac_version) {
ac85bcdb
CHL		 7693 case RTL_GIGA_MAC_VER_34:
7694 case RTL_GIGA_MAC_VER_35:
7695 case RTL_GIGA_MAC_VER_36:
7696 case RTL_GIGA_MAC_VER_37:
7697 case RTL_GIGA_MAC_VER_38:
7698 case RTL_GIGA_MAC_VER_40:
7699 case RTL_GIGA_MAC_VER_41:
7700 case RTL_GIGA_MAC_VER_42:
7701 case RTL_GIGA_MAC_VER_43:
7702 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 7703 case RTL_GIGA_MAC_VER_45:
7704 case RTL_GIGA_MAC_VER_46:
ac85bcdb
CHL		 7705 case RTL_GIGA_MAC_VER_47:
7706 case RTL_GIGA_MAC_VER_48:
6e1d0b89
CHL		 7707 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
7708 tp->features |= RTL_FEATURE_WOL;
7709 if ((RTL_R8(Config3) & LinkUp) != 0)
7710 tp->features |= RTL_FEATURE_WOL;
7711 break;
7712 default:
7713 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
7714 tp->features |= RTL_FEATURE_WOL;
7715 break;
7716 }
3b6cf25d
FR		 7717 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
7718 tp->features |= RTL_FEATURE_WOL;
7719 tp->features |= rtl_try_msi(tp, cfg);
7720 RTL_W8(Cfg9346, Cfg9346_Lock);
7721
7722 if (rtl_tbi_enabled(tp)) {
7723 tp->set_speed = rtl8169_set_speed_tbi;
7724 tp->get_settings = rtl8169_gset_tbi;
7725 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
7726 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
7727 tp->link_ok = rtl8169_tbi_link_ok;
7728 tp->do_ioctl = rtl_tbi_ioctl;
7729 } else {
7730 tp->set_speed = rtl8169_set_speed_xmii;
7731 tp->get_settings = rtl8169_gset_xmii;
7732 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
7733 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
7734 tp->link_ok = rtl8169_xmii_link_ok;
7735 tp->do_ioctl = rtl_xmii_ioctl;
7736 }
7737
7738 mutex_init(&tp->wk.mutex);
340fea3d
KM		 7739 u64_stats_init(&tp->rx_stats.syncp);
7740 u64_stats_init(&tp->tx_stats.syncp);
3b6cf25d
FR		 7741
7742 /* Get MAC address */
89cceb27
CHL		 7743 if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
7744 tp->mac_version == RTL_GIGA_MAC_VER_36 ||
7745 tp->mac_version == RTL_GIGA_MAC_VER_37 ||
7746 tp->mac_version == RTL_GIGA_MAC_VER_38 ||
7747 tp->mac_version == RTL_GIGA_MAC_VER_40 ||
7748 tp->mac_version == RTL_GIGA_MAC_VER_41 ||
7749 tp->mac_version == RTL_GIGA_MAC_VER_42 ||
7750 tp->mac_version == RTL_GIGA_MAC_VER_43 ||
7751 tp->mac_version == RTL_GIGA_MAC_VER_44 ||
7752 tp->mac_version == RTL_GIGA_MAC_VER_45 ||
6e1d0b89
CHL		 7753 tp->mac_version == RTL_GIGA_MAC_VER_46 ||
7754 tp->mac_version == RTL_GIGA_MAC_VER_47 ||
7755 tp->mac_version == RTL_GIGA_MAC_VER_48) {
7756 u16 mac_addr[3];
7757
05b9687b
CHL		 7758 *(u32 *)&mac_addr[0] = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC);
7759 *(u16 *)&mac_addr[2] = rtl_eri_read(tp, 0xe4, ERIAR_EXGMAC);
6e1d0b89
CHL		 7760
7761 if (is_valid_ether_addr((u8 *)mac_addr))
7762 rtl_rar_set(tp, (u8 *)mac_addr);
7763 }
3b6cf25d
FR		 7764 for (i = 0; i < ETH_ALEN; i++)
7765 dev->dev_addr[i] = RTL_R8(MAC0 + i);
3b6cf25d 7766
7ad24ea4 7767 dev->ethtool_ops = &rtl8169_ethtool_ops;
3b6cf25d 7768 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3b6cf25d
FR		 7769
7770 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
7771
7772 /* don't enable SG, IP_CSUM and TSO by default - it might not work
7773 * properly for all devices */
7774 dev->features |= NETIF_F_RXCSUM |
f646968f 7775 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d
FR		 7776
7777 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
f646968f
PM		 7778 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
7779 NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d
FR		 7780 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7781 NETIF_F_HIGHDMA;
7782
929a031d 7783 tp->cp_cmd |= RxChkSum | RxVlan;
7784
7785 /*
7786 * Pretend we are using VLANs; This bypasses a nasty bug where
7787 * Interrupts stop flowing on high load on 8110SCd controllers.
7788 */
3b6cf25d 7789 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
929a031d 7790 /* Disallow toggling */
f646968f 7791 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d 7792
5888d3fc 7793 if (tp->txd_version == RTL_TD_0)
7794 tp->tso_csum = rtl8169_tso_csum_v1;
e974604b 7795 else if (tp->txd_version == RTL_TD_1) {
5888d3fc 7796 tp->tso_csum = rtl8169_tso_csum_v2;
e974604b 7797 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
7798 } else
5888d3fc 7799 WARN_ON_ONCE(1);
7800
3b6cf25d
FR		 7801 dev->hw_features |= NETIF_F_RXALL;
7802 dev->hw_features |= NETIF_F_RXFCS;
7803
7804 tp->hw_start = cfg->hw_start;
7805 tp->event_slow = cfg->event_slow;
7806
7807 tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
7808 ~(RxBOVF | RxFOVF) : ~0;
7809
7810 init_timer(&tp->timer);
7811 tp->timer.data = (unsigned long) dev;
7812 tp->timer.function = rtl8169_phy_timer;
7813
7814 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
7815
7816 rc = register_netdev(dev);
7817 if (rc < 0)
7818 goto err_out_msi_4;
7819
7820 pci_set_drvdata(pdev, dev);
7821
92a7c4e7
FR		 7822 netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
7823 rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
7824 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
3b6cf25d
FR		 7825 if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
7826 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
7827 "tx checksumming: %s]\n",
7828 rtl_chip_infos[chipset].jumbo_max,
7829 rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
7830 }
7831
7832 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
7833 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
7834 tp->mac_version == RTL_GIGA_MAC_VER_31) {
7835 rtl8168_driver_start(tp);
7836 }
7837
7838 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
7839
7840 if (pci_dev_run_wake(pdev))
7841 pm_runtime_put_noidle(&pdev->dev);
7842
7843 netif_carrier_off(dev);
7844
7845out:
7846 return rc;
7847
7848err_out_msi_4:
ad1be8d3 7849 netif_napi_del(&tp->napi);
3b6cf25d
FR		 7850 rtl_disable_msi(pdev, tp);
7851 iounmap(ioaddr);
7852err_out_free_res_3:
7853 pci_release_regions(pdev);
7854err_out_mwi_2:
7855 pci_clear_mwi(pdev);
7856 pci_disable_device(pdev);
7857err_out_free_dev_1:
7858 free_netdev(dev);
7859 goto out;
7860}
7861
1da177e4
LT		 7862static struct pci_driver rtl8169_pci_driver = {
7863 .name = MODULENAME,
7864 .id_table = rtl8169_pci_tbl,
3b6cf25d 7865 .probe = rtl_init_one,
baf63293 7866 .remove = rtl_remove_one,
1765f95d 7867 .shutdown = rtl_shutdown,
861ab440 7868 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 7869};
7870
3eeb7da9 7871module_pci_driver(rtl8169_pci_driver);
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