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[mirror_ubuntu-focal-kernel.git] / drivers / net / ethernet / realtek / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
a6b7a407 24#include <linux/interrupt.h>
1da177e4 25#include <linux/dma-mapping.h>
e1759441 26#include <linux/pm_runtime.h>
bca03d5f 27#include <linux/firmware.h>
ba04c7c9 28#include <linux/pci-aspm.h>
70c71606 29#include <linux/prefetch.h>
e974604b 30#include <linux/ipv6.h>
31#include <net/ip6_checksum.h>
1da177e4
LT		 32
33#include <asm/io.h>
34#include <asm/irq.h>
35
865c652d 36#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 37#define MODULENAME "r8169"
38#define PFX MODULENAME ": "
39
bca03d5f 40#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
41#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
01dc7fec 42#define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
43#define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
70090424 44#define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
c2218925
HW		 45#define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
46#define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
5a5e4443 47#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
7e18dca1 48#define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
b3d7b2f2 49#define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
45dd95c4 50#define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
5598bfe5 51#define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
58152cd4 52#define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
beb330a4 53#define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
57538c4a 54#define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
6e1d0b89
CHL		 55#define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw"
56#define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
57#define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw"
58#define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
bca03d5f 59
1da177e4
LT		 60#ifdef RTL8169_DEBUG
61#define assert(expr) \
5b0384f4
FR		 62 if (!(expr)) { \
63 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
b39d66a8 64 #expr,__FILE__,__func__,__LINE__); \
5b0384f4 65 }
06fa7358
JP		 66#define dprintk(fmt, args...) \
67 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 68#else
69#define assert(expr) do {} while (0)
70#define dprintk(fmt, args...) do {} while (0)
71#endif /* RTL8169_DEBUG */
72
b57b7e5a 73#define R8169_MSG_DEFAULT \
f0e837d9 74 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 75
477206a0
JD		 76#define TX_SLOTS_AVAIL(tp) \
77 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
78
79/* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
80#define TX_FRAGS_READY_FOR(tp,nr_frags) \
81 (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
1da177e4 82
1da177e4
LT		 83/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
84 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 85static const int multicast_filter_limit = 32;
1da177e4 86
9c14ceaf 87#define MAX_READ_REQUEST_SHIFT 12
aee77e4a 88#define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
1da177e4
LT		 89#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
90
91#define R8169_REGS_SIZE 256
92#define R8169_NAPI_WEIGHT 64
93#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
9fba0812 94#define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
1da177e4
LT		 95#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
96#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
97
98#define RTL8169_TX_TIMEOUT (6*HZ)
99#define RTL8169_PHY_TIMEOUT (10*HZ)
100
101/* write/read MMIO register */
102#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
103#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
104#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
105#define RTL_R8(reg) readb (ioaddr + (reg))
106#define RTL_R16(reg) readw (ioaddr + (reg))
06f555f3 107#define RTL_R32(reg) readl (ioaddr + (reg))
1da177e4
LT		 108
109enum mac_version {
85bffe6c
FR		 110 RTL_GIGA_MAC_VER_01 = 0,
111 RTL_GIGA_MAC_VER_02,
112 RTL_GIGA_MAC_VER_03,
113 RTL_GIGA_MAC_VER_04,
114 RTL_GIGA_MAC_VER_05,
115 RTL_GIGA_MAC_VER_06,
116 RTL_GIGA_MAC_VER_07,
117 RTL_GIGA_MAC_VER_08,
118 RTL_GIGA_MAC_VER_09,
119 RTL_GIGA_MAC_VER_10,
120 RTL_GIGA_MAC_VER_11,
121 RTL_GIGA_MAC_VER_12,
122 RTL_GIGA_MAC_VER_13,
123 RTL_GIGA_MAC_VER_14,
124 RTL_GIGA_MAC_VER_15,
125 RTL_GIGA_MAC_VER_16,
126 RTL_GIGA_MAC_VER_17,
127 RTL_GIGA_MAC_VER_18,
128 RTL_GIGA_MAC_VER_19,
129 RTL_GIGA_MAC_VER_20,
130 RTL_GIGA_MAC_VER_21,
131 RTL_GIGA_MAC_VER_22,
132 RTL_GIGA_MAC_VER_23,
133 RTL_GIGA_MAC_VER_24,
134 RTL_GIGA_MAC_VER_25,
135 RTL_GIGA_MAC_VER_26,
136 RTL_GIGA_MAC_VER_27,
137 RTL_GIGA_MAC_VER_28,
138 RTL_GIGA_MAC_VER_29,
139 RTL_GIGA_MAC_VER_30,
140 RTL_GIGA_MAC_VER_31,
141 RTL_GIGA_MAC_VER_32,
142 RTL_GIGA_MAC_VER_33,
70090424 143 RTL_GIGA_MAC_VER_34,
c2218925
HW		 144 RTL_GIGA_MAC_VER_35,
145 RTL_GIGA_MAC_VER_36,
7e18dca1 146 RTL_GIGA_MAC_VER_37,
b3d7b2f2 147 RTL_GIGA_MAC_VER_38,
5598bfe5 148 RTL_GIGA_MAC_VER_39,
c558386b
HW		 149 RTL_GIGA_MAC_VER_40,
150 RTL_GIGA_MAC_VER_41,
57538c4a 151 RTL_GIGA_MAC_VER_42,
58152cd4 152 RTL_GIGA_MAC_VER_43,
45dd95c4 153 RTL_GIGA_MAC_VER_44,
6e1d0b89
CHL		 154 RTL_GIGA_MAC_VER_45,
155 RTL_GIGA_MAC_VER_46,
156 RTL_GIGA_MAC_VER_47,
157 RTL_GIGA_MAC_VER_48,
935e2218
CHL		 158 RTL_GIGA_MAC_VER_49,
159 RTL_GIGA_MAC_VER_50,
160 RTL_GIGA_MAC_VER_51,
85bffe6c 161 RTL_GIGA_MAC_NONE = 0xff,
1da177e4
LT		 162};
163
2b7b4318
FR		 164enum rtl_tx_desc_version {
165 RTL_TD_0 = 0,
166 RTL_TD_1 = 1,
167};
168
d58d46b5
FR		 169#define JUMBO_1K ETH_DATA_LEN
170#define JUMBO_4K (4*1024 - ETH_HLEN - 2)
171#define JUMBO_6K (6*1024 - ETH_HLEN - 2)
172#define JUMBO_7K (7*1024 - ETH_HLEN - 2)
173#define JUMBO_9K (9*1024 - ETH_HLEN - 2)
174
175#define _R(NAME,TD,FW,SZ,B) { \
176 .name = NAME, \
177 .txd_version = TD, \
178 .fw_name = FW, \
179 .jumbo_max = SZ, \
180 .jumbo_tx_csum = B \
181}
1da177e4 182
3c6bee1d 183static const struct {
1da177e4 184 const char *name;
2b7b4318 185 enum rtl_tx_desc_version txd_version;
953a12cc 186 const char *fw_name;
d58d46b5
FR		 187 u16 jumbo_max;
188 bool jumbo_tx_csum;
85bffe6c
FR		 189} rtl_chip_infos[] = {
190 /* PCI devices. */
191 [RTL_GIGA_MAC_VER_01] =
d58d46b5 192 _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 193 [RTL_GIGA_MAC_VER_02] =
d58d46b5 194 _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 195 [RTL_GIGA_MAC_VER_03] =
d58d46b5 196 _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 197 [RTL_GIGA_MAC_VER_04] =
d58d46b5 198 _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 199 [RTL_GIGA_MAC_VER_05] =
d58d46b5 200 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 201 [RTL_GIGA_MAC_VER_06] =
d58d46b5 202 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c
FR		 203 /* PCI-E devices. */
204 [RTL_GIGA_MAC_VER_07] =
d58d46b5 205 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 206 [RTL_GIGA_MAC_VER_08] =
d58d46b5 207 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 208 [RTL_GIGA_MAC_VER_09] =
d58d46b5 209 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 210 [RTL_GIGA_MAC_VER_10] =
d58d46b5 211 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 212 [RTL_GIGA_MAC_VER_11] =
d58d46b5 213 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
85bffe6c 214 [RTL_GIGA_MAC_VER_12] =
d58d46b5 215 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
85bffe6c 216 [RTL_GIGA_MAC_VER_13] =
d58d46b5 217 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 218 [RTL_GIGA_MAC_VER_14] =
d58d46b5 219 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 220 [RTL_GIGA_MAC_VER_15] =
d58d46b5 221 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 222 [RTL_GIGA_MAC_VER_16] =
d58d46b5 223 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 224 [RTL_GIGA_MAC_VER_17] =
f75761b6 225 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
85bffe6c 226 [RTL_GIGA_MAC_VER_18] =
d58d46b5 227 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 228 [RTL_GIGA_MAC_VER_19] =
d58d46b5 229 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 230 [RTL_GIGA_MAC_VER_20] =
d58d46b5 231 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 232 [RTL_GIGA_MAC_VER_21] =
d58d46b5 233 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 234 [RTL_GIGA_MAC_VER_22] =
d58d46b5 235 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 236 [RTL_GIGA_MAC_VER_23] =
d58d46b5 237 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 238 [RTL_GIGA_MAC_VER_24] =
d58d46b5 239 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 240 [RTL_GIGA_MAC_VER_25] =
d58d46b5
FR		 241 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1,
242 JUMBO_9K, false),
85bffe6c 243 [RTL_GIGA_MAC_VER_26] =
d58d46b5
FR		 244 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2,
245 JUMBO_9K, false),
85bffe6c 246 [RTL_GIGA_MAC_VER_27] =
d58d46b5 247 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 248 [RTL_GIGA_MAC_VER_28] =
d58d46b5 249 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 250 [RTL_GIGA_MAC_VER_29] =
d58d46b5
FR		 251 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
252 JUMBO_1K, true),
85bffe6c 253 [RTL_GIGA_MAC_VER_30] =
d58d46b5
FR		 254 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
255 JUMBO_1K, true),
85bffe6c 256 [RTL_GIGA_MAC_VER_31] =
d58d46b5 257 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 258 [RTL_GIGA_MAC_VER_32] =
d58d46b5
FR		 259 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1,
260 JUMBO_9K, false),
85bffe6c 261 [RTL_GIGA_MAC_VER_33] =
d58d46b5
FR		 262 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2,
263 JUMBO_9K, false),
70090424 264 [RTL_GIGA_MAC_VER_34] =
d58d46b5
FR		 265 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
266 JUMBO_9K, false),
c2218925 267 [RTL_GIGA_MAC_VER_35] =
d58d46b5
FR		 268 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1,
269 JUMBO_9K, false),
c2218925 270 [RTL_GIGA_MAC_VER_36] =
d58d46b5
FR		 271 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2,
272 JUMBO_9K, false),
7e18dca1
HW		 273 [RTL_GIGA_MAC_VER_37] =
274 _R("RTL8402", RTL_TD_1, FIRMWARE_8402_1,
275 JUMBO_1K, true),
b3d7b2f2
HW		 276 [RTL_GIGA_MAC_VER_38] =
277 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_1,
278 JUMBO_9K, false),
5598bfe5
HW		 279 [RTL_GIGA_MAC_VER_39] =
280 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_1,
281 JUMBO_1K, true),
c558386b 282 [RTL_GIGA_MAC_VER_40] =
beb330a4 283 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_2,
c558386b
HW		 284 JUMBO_9K, false),
285 [RTL_GIGA_MAC_VER_41] =
286 _R("RTL8168g/8111g", RTL_TD_1, NULL, JUMBO_9K, false),
57538c4a 287 [RTL_GIGA_MAC_VER_42] =
288 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_3,
289 JUMBO_9K, false),
58152cd4 290 [RTL_GIGA_MAC_VER_43] =
291 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_2,
292 JUMBO_1K, true),
45dd95c4 293 [RTL_GIGA_MAC_VER_44] =
294 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_2,
295 JUMBO_9K, false),
6e1d0b89
CHL		 296 [RTL_GIGA_MAC_VER_45] =
297 _R("RTL8168h/8111h", RTL_TD_1, FIRMWARE_8168H_1,
298 JUMBO_9K, false),
299 [RTL_GIGA_MAC_VER_46] =
300 _R("RTL8168h/8111h", RTL_TD_1, FIRMWARE_8168H_2,
301 JUMBO_9K, false),
302 [RTL_GIGA_MAC_VER_47] =
303 _R("RTL8107e", RTL_TD_1, FIRMWARE_8107E_1,
304 JUMBO_1K, false),
305 [RTL_GIGA_MAC_VER_48] =
306 _R("RTL8107e", RTL_TD_1, FIRMWARE_8107E_2,
307 JUMBO_1K, false),
935e2218
CHL		 308 [RTL_GIGA_MAC_VER_49] =
309 _R("RTL8168ep/8111ep", RTL_TD_1, NULL,
310 JUMBO_9K, false),
311 [RTL_GIGA_MAC_VER_50] =
312 _R("RTL8168ep/8111ep", RTL_TD_1, NULL,
313 JUMBO_9K, false),
314 [RTL_GIGA_MAC_VER_51] =
315 _R("RTL8168ep/8111ep", RTL_TD_1, NULL,
316 JUMBO_9K, false),
953a12cc 317};
85bffe6c 318#undef _R
953a12cc 319
bcf0bf90
FR		 320enum cfg_version {
321 RTL_CFG_0 = 0x00,
322 RTL_CFG_1,
323 RTL_CFG_2
324};
325
9baa3c34 326static const struct pci_device_id rtl8169_pci_tbl[] = {
bcf0bf90 327 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 328 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 329 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 330 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90 331 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
2a35cfa5
FR		 332 { PCI_VENDOR_ID_DLINK, 0x4300,
333 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
bcf0bf90 334 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
93a3aa25 335 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
bc1660b5 336 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 337 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
338 { PCI_VENDOR_ID_LINKSYS, 0x1032,
339 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 340 { 0x0001, 0x8168,
341 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 342 {0,},
343};
344
345MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
346
6f0333b8 347static int rx_buf_sz = 16383;
27896c83 348static int use_dac = -1;
b57b7e5a
SH		 349static struct {
350 u32 msg_enable;
351} debug = { -1 };
1da177e4 352
07d3f51f
FR		 353enum rtl_registers {
354 MAC0 = 0, /* Ethernet hardware address. */
773d2021 355 MAC4 = 4,
07d3f51f
FR		 356 MAR0 = 8, /* Multicast filter. */
357 CounterAddrLow = 0x10,
358 CounterAddrHigh = 0x14,
359 TxDescStartAddrLow = 0x20,
360 TxDescStartAddrHigh = 0x24,
361 TxHDescStartAddrLow = 0x28,
362 TxHDescStartAddrHigh = 0x2c,
363 FLASH = 0x30,
364 ERSR = 0x36,
365 ChipCmd = 0x37,
366 TxPoll = 0x38,
367 IntrMask = 0x3c,
368 IntrStatus = 0x3e,
4f6b00e5 369
07d3f51f 370 TxConfig = 0x40,
4f6b00e5
HW		 371#define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
372#define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
2b7b4318 373
4f6b00e5
HW		 374 RxConfig = 0x44,
375#define RX128_INT_EN (1 << 15) /* 8111c and later */
376#define RX_MULTI_EN (1 << 14) /* 8111c only */
377#define RXCFG_FIFO_SHIFT 13
378 /* No threshold before first PCI xfer */
379#define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
beb330a4 380#define RX_EARLY_OFF (1 << 11)
4f6b00e5
HW		 381#define RXCFG_DMA_SHIFT 8
382 /* Unlimited maximum PCI burst. */
383#define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
2b7b4318 384
07d3f51f
FR		 385 RxMissed = 0x4c,
386 Cfg9346 = 0x50,
387 Config0 = 0x51,
388 Config1 = 0x52,
389 Config2 = 0x53,
d387b427
FR		 390#define PME_SIGNAL (1 << 5) /* 8168c and later */
391
07d3f51f
FR		 392 Config3 = 0x54,
393 Config4 = 0x55,
394 Config5 = 0x56,
395 MultiIntr = 0x5c,
396 PHYAR = 0x60,
07d3f51f
FR		 397 PHYstatus = 0x6c,
398 RxMaxSize = 0xda,
399 CPlusCmd = 0xe0,
400 IntrMitigate = 0xe2,
401 RxDescAddrLow = 0xe4,
402 RxDescAddrHigh = 0xe8,
f0298f81 403 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
404
405#define NoEarlyTx 0x3f /* Max value : no early transmit. */
406
407 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
408
409#define TxPacketMax (8064 >> 7)
3090bd9a 410#define EarlySize 0x27
f0298f81 411
07d3f51f
FR		 412 FuncEvent = 0xf0,
413 FuncEventMask = 0xf4,
414 FuncPresetState = 0xf8,
935e2218
CHL		 415 IBCR0 = 0xf8,
416 IBCR2 = 0xf9,
417 IBIMR0 = 0xfa,
418 IBISR0 = 0xfb,
07d3f51f 419 FuncForceEvent = 0xfc,
1da177e4
LT		 420};
421
f162a5d1
FR		 422enum rtl8110_registers {
423 TBICSR = 0x64,
424 TBI_ANAR = 0x68,
425 TBI_LPAR = 0x6a,
426};
427
428enum rtl8168_8101_registers {
429 CSIDR = 0x64,
430 CSIAR = 0x68,
431#define CSIAR_FLAG 0x80000000
432#define CSIAR_WRITE_CMD 0x80000000
433#define CSIAR_BYTE_ENABLE 0x0f
434#define CSIAR_BYTE_ENABLE_SHIFT 12
435#define CSIAR_ADDR_MASK 0x0fff
7e18dca1
HW		 436#define CSIAR_FUNC_CARD 0x00000000
437#define CSIAR_FUNC_SDIO 0x00010000
438#define CSIAR_FUNC_NIC 0x00020000
45dd95c4 439#define CSIAR_FUNC_NIC2 0x00010000
065c27c1 440 PMCH = 0x6f,
f162a5d1
FR		 441 EPHYAR = 0x80,
442#define EPHYAR_FLAG 0x80000000
443#define EPHYAR_WRITE_CMD 0x80000000
444#define EPHYAR_REG_MASK 0x1f
445#define EPHYAR_REG_SHIFT 16
446#define EPHYAR_DATA_MASK 0xffff
5a5e4443 447 DLLPR = 0xd0,
4f6b00e5 448#define PFM_EN (1 << 6)
6e1d0b89 449#define TX_10M_PS_EN (1 << 7)
f162a5d1
FR		 450 DBG_REG = 0xd1,
451#define FIX_NAK_1 (1 << 4)
452#define FIX_NAK_2 (1 << 3)
5a5e4443
HW		 453 TWSI = 0xd2,
454 MCU = 0xd3,
4f6b00e5 455#define NOW_IS_OOB (1 << 7)
c558386b
HW		 456#define TX_EMPTY (1 << 5)
457#define RX_EMPTY (1 << 4)
458#define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
5a5e4443
HW		 459#define EN_NDP (1 << 3)
460#define EN_OOB_RESET (1 << 2)
c558386b 461#define LINK_LIST_RDY (1 << 1)
daf9df6d 462 EFUSEAR = 0xdc,
463#define EFUSEAR_FLAG 0x80000000
464#define EFUSEAR_WRITE_CMD 0x80000000
465#define EFUSEAR_READ_CMD 0x00000000
466#define EFUSEAR_REG_MASK 0x03ff
467#define EFUSEAR_REG_SHIFT 8
468#define EFUSEAR_DATA_MASK 0xff
6e1d0b89
CHL		 469 MISC_1 = 0xf2,
470#define PFM_D3COLD_EN (1 << 6)
f162a5d1
FR		 471};
472
c0e45c1c 473enum rtl8168_registers {
4f6b00e5
HW		 474 LED_FREQ = 0x1a,
475 EEE_LED = 0x1b,
b646d900 476 ERIDR = 0x70,
477 ERIAR = 0x74,
478#define ERIAR_FLAG 0x80000000
479#define ERIAR_WRITE_CMD 0x80000000
480#define ERIAR_READ_CMD 0x00000000
481#define ERIAR_ADDR_BYTE_ALIGN 4
b646d900 482#define ERIAR_TYPE_SHIFT 16
4f6b00e5
HW		 483#define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
484#define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
485#define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
935e2218 486#define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
4f6b00e5
HW		 487#define ERIAR_MASK_SHIFT 12
488#define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
489#define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
6e1d0b89 490#define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
c558386b 491#define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
4f6b00e5 492#define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
c0e45c1c 493 EPHY_RXER_NUM = 0x7c,
494 OCPDR = 0xb0, /* OCP GPHY access */
495#define OCPDR_WRITE_CMD 0x80000000
496#define OCPDR_READ_CMD 0x00000000
497#define OCPDR_REG_MASK 0x7f
498#define OCPDR_GPHY_REG_SHIFT 16
499#define OCPDR_DATA_MASK 0xffff
500 OCPAR = 0xb4,
501#define OCPAR_FLAG 0x80000000
502#define OCPAR_GPHY_WRITE_CMD 0x8000f060
503#define OCPAR_GPHY_READ_CMD 0x0000f060
c558386b 504 GPHY_OCP = 0xb8,
01dc7fec 505 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
506 MISC = 0xf0, /* 8168e only. */
cecb5fd7 507#define TXPLA_RST (1 << 29)
5598bfe5 508#define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
4f6b00e5 509#define PWM_EN (1 << 22)
c558386b 510#define RXDV_GATED_EN (1 << 19)
5598bfe5 511#define EARLY_TALLY_EN (1 << 16)
c0e45c1c 512};
513
07d3f51f 514enum rtl_register_content {
1da177e4 515 /* InterruptStatusBits */
07d3f51f
FR		 516 SYSErr = 0x8000,
517 PCSTimeout = 0x4000,
518 SWInt = 0x0100,
519 TxDescUnavail = 0x0080,
520 RxFIFOOver = 0x0040,
521 LinkChg = 0x0020,
522 RxOverflow = 0x0010,
523 TxErr = 0x0008,
524 TxOK = 0x0004,
525 RxErr = 0x0002,
526 RxOK = 0x0001,
1da177e4
LT		 527
528 /* RxStatusDesc */
e03f33af 529 RxBOVF = (1 << 24),
9dccf611
FR		 530 RxFOVF = (1 << 23),
531 RxRWT = (1 << 22),
532 RxRES = (1 << 21),
533 RxRUNT = (1 << 20),
534 RxCRC = (1 << 19),
1da177e4
LT		 535
536 /* ChipCmdBits */
4f6b00e5 537 StopReq = 0x80,
07d3f51f
FR		 538 CmdReset = 0x10,
539 CmdRxEnb = 0x08,
540 CmdTxEnb = 0x04,
541 RxBufEmpty = 0x01,
1da177e4 542
275391a4
FR		 543 /* TXPoll register p.5 */
544 HPQ = 0x80, /* Poll cmd on the high prio queue */
545 NPQ = 0x40, /* Poll cmd on the low prio queue */
546 FSWInt = 0x01, /* Forced software interrupt */
547
1da177e4 548 /* Cfg9346Bits */
07d3f51f
FR		 549 Cfg9346_Lock = 0x00,
550 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 551
552 /* rx_mode_bits */
07d3f51f
FR		 553 AcceptErr = 0x20,
554 AcceptRunt = 0x10,
555 AcceptBroadcast = 0x08,
556 AcceptMulticast = 0x04,
557 AcceptMyPhys = 0x02,
558 AcceptAllPhys = 0x01,
1687b566 559#define RX_CONFIG_ACCEPT_MASK 0x3f
1da177e4 560
1da177e4
LT		 561 /* TxConfigBits */
562 TxInterFrameGapShift = 24,
563 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
564
5d06a99f 565 /* Config1 register p.24 */
f162a5d1
FR		 566 LEDS1 = (1 << 7),
567 LEDS0 = (1 << 6),
f162a5d1
FR		 568 Speed_down = (1 << 4),
569 MEMMAP = (1 << 3),
570 IOMAP = (1 << 2),
571 VPD = (1 << 1),
5d06a99f
FR		 572 PMEnable = (1 << 0), /* Power Management Enable */
573
6dccd16b 574 /* Config2 register p. 25 */
57538c4a 575 ClkReqEn = (1 << 7), /* Clock Request Enable */
2ca6cf06 576 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
6dccd16b
FR		 577 PCI_Clock_66MHz = 0x01,
578 PCI_Clock_33MHz = 0x00,
579
61a4dcc2
FR		 580 /* Config3 register p.25 */
581 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
582 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
d58d46b5 583 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
b51ecea8 584 Rdy_to_L23 = (1 << 1), /* L23 Enable */
f162a5d1 585 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 586
d58d46b5
FR		 587 /* Config4 register */
588 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
589
5d06a99f 590 /* Config5 register p.27 */
61a4dcc2
FR		 591 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
592 MWF = (1 << 5), /* Accept Multicast wakeup frame */
593 UWF = (1 << 4), /* Accept Unicast wakeup frame */
cecb5fd7 594 Spi_en = (1 << 3),
61a4dcc2 595 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f 596 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
57538c4a 597 ASPM_en = (1 << 0), /* ASPM enable */
5d06a99f 598
1da177e4
LT		 599 /* TBICSR p.28 */
600 TBIReset = 0x80000000,
601 TBILoopback = 0x40000000,
602 TBINwEnable = 0x20000000,
603 TBINwRestart = 0x10000000,
604 TBILinkOk = 0x02000000,
605 TBINwComplete = 0x01000000,
606
607 /* CPlusCmd p.31 */
f162a5d1
FR		 608 EnableBist = (1 << 15), // 8168 8101
609 Mac_dbgo_oe = (1 << 14), // 8168 8101
610 Normal_mode = (1 << 13), // unused
611 Force_half_dup = (1 << 12), // 8168 8101
612 Force_rxflow_en = (1 << 11), // 8168 8101
613 Force_txflow_en = (1 << 10), // 8168 8101
614 Cxpl_dbg_sel = (1 << 9), // 8168 8101
615 ASF = (1 << 8), // 8168 8101
616 PktCntrDisable = (1 << 7), // 8168 8101
617 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 618 RxVlan = (1 << 6),
619 RxChkSum = (1 << 5),
620 PCIDAC = (1 << 4),
621 PCIMulRW = (1 << 3),
0e485150
FR		 622 INTT_0 = 0x0000, // 8168
623 INTT_1 = 0x0001, // 8168
624 INTT_2 = 0x0002, // 8168
625 INTT_3 = 0x0003, // 8168
1da177e4
LT		 626
627 /* rtl8169_PHYstatus */
07d3f51f
FR		 628 TBI_Enable = 0x80,
629 TxFlowCtrl = 0x40,
630 RxFlowCtrl = 0x20,
631 _1000bpsF = 0x10,
632 _100bps = 0x08,
633 _10bps = 0x04,
634 LinkStatus = 0x02,
635 FullDup = 0x01,
1da177e4 636
1da177e4 637 /* _TBICSRBit */
07d3f51f 638 TBILinkOK = 0x02000000,
d4a3a0fc 639
6e85d5ad
CV		 640 /* ResetCounterCommand */
641 CounterReset = 0x1,
642
d4a3a0fc 643 /* DumpCounterCommand */
07d3f51f 644 CounterDump = 0x8,
6e1d0b89
CHL		 645
646 /* magic enable v2 */
647 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */
1da177e4
LT		 648};
649
2b7b4318
FR		 650enum rtl_desc_bit {
651 /* First doubleword. */
1da177e4
LT		 652 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
653 RingEnd = (1 << 30), /* End of descriptor ring */
654 FirstFrag = (1 << 29), /* First segment of a packet */
655 LastFrag = (1 << 28), /* Final segment of a packet */
2b7b4318
FR		 656};
657
658/* Generic case. */
659enum rtl_tx_desc_bit {
660 /* First doubleword. */
661 TD_LSO = (1 << 27), /* Large Send Offload */
662#define TD_MSS_MAX 0x07ffu /* MSS value */
1da177e4 663
2b7b4318
FR		 664 /* Second doubleword. */
665 TxVlanTag = (1 << 17), /* Add VLAN tag */
666};
667
668/* 8169, 8168b and 810x except 8102e. */
669enum rtl_tx_desc_bit_0 {
670 /* First doubleword. */
671#define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
672 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
673 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
674 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
675};
676
677/* 8102e, 8168c and beyond. */
678enum rtl_tx_desc_bit_1 {
bdfa4ed6 679 /* First doubleword. */
680 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */
e974604b 681 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */
bdfa4ed6 682#define GTTCPHO_SHIFT 18
e974604b 683#define GTTCPHO_MAX 0x7fU
bdfa4ed6 684
2b7b4318 685 /* Second doubleword. */
e974604b 686#define TCPHO_SHIFT 18
687#define TCPHO_MAX 0x3ffU
2b7b4318 688#define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
e974604b 689 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */
690 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */
2b7b4318
FR		 691 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
692 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
693};
1da177e4 694
2b7b4318 695enum rtl_rx_desc_bit {
1da177e4
LT		 696 /* Rx private */
697 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
698 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
699
700#define RxProtoUDP (PID1)
701#define RxProtoTCP (PID0)
702#define RxProtoIP (PID1 | PID0)
703#define RxProtoMask RxProtoIP
704
705 IPFail = (1 << 16), /* IP checksum failed */
706 UDPFail = (1 << 15), /* UDP/IP checksum failed */
707 TCPFail = (1 << 14), /* TCP/IP checksum failed */
708 RxVlanTag = (1 << 16), /* VLAN tag available */
709};
710
711#define RsvdMask 0x3fffc000
712
713struct TxDesc {
6cccd6e7
REB		 714 __le32 opts1;
715 __le32 opts2;
716 __le64 addr;
1da177e4
LT		 717};
718
719struct RxDesc {
6cccd6e7
REB		 720 __le32 opts1;
721 __le32 opts2;
722 __le64 addr;
1da177e4
LT		 723};
724
725struct ring_info {
726 struct sk_buff *skb;
727 u32 len;
728 u8 __pad[sizeof(void *) - sizeof(u32)];
729};
730
f23e7fda 731enum features {
ccdffb9a
FR		 732 RTL_FEATURE_WOL = (1 << 0),
733 RTL_FEATURE_MSI = (1 << 1),
734 RTL_FEATURE_GMII = (1 << 2),
f23e7fda
FR		 735};
736
355423d0
IV		 737struct rtl8169_counters {
738 __le64 tx_packets;
739 __le64 rx_packets;
740 __le64 tx_errors;
741 __le32 rx_errors;
742 __le16 rx_missed;
743 __le16 align_errors;
744 __le32 tx_one_collision;
745 __le32 tx_multi_collision;
746 __le64 rx_unicast;
747 __le64 rx_broadcast;
748 __le32 rx_multicast;
749 __le16 tx_aborted;
750 __le16 tx_underun;
751};
752
6e85d5ad
CV		 753struct rtl8169_tc_offsets {
754 bool inited;
755 __le64 tx_errors;
756 __le32 tx_multi_collision;
6e85d5ad
CV		 757 __le16 tx_aborted;
758};
759
da78dbff 760enum rtl_flag {
6c4a70c5 761 RTL_FLAG_TASK_ENABLED,
da78dbff
FR		 762 RTL_FLAG_TASK_SLOW_PENDING,
763 RTL_FLAG_TASK_RESET_PENDING,
764 RTL_FLAG_TASK_PHY_PENDING,
765 RTL_FLAG_MAX
766};
767
8027aa24
JW		 768struct rtl8169_stats {
769 u64 packets;
770 u64 bytes;
771 struct u64_stats_sync syncp;
772};
773
1da177e4
LT		 774struct rtl8169_private {
775 void __iomem *mmio_addr; /* memory map physical address */
cecb5fd7 776 struct pci_dev *pci_dev;
c4028958 777 struct net_device *dev;
bea3348e 778 struct napi_struct napi;
b57b7e5a 779 u32 msg_enable;
2b7b4318
FR		 780 u16 txd_version;
781 u16 mac_version;
1da177e4
LT		 782 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
783 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
1da177e4 784 u32 dirty_tx;
8027aa24
JW		 785 struct rtl8169_stats rx_stats;
786 struct rtl8169_stats tx_stats;
1da177e4
LT		 787 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
788 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
789 dma_addr_t TxPhyAddr;
790 dma_addr_t RxPhyAddr;
6f0333b8 791 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
1da177e4 792 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
1da177e4
LT		 793 struct timer_list timer;
794 u16 cp_cmd;
da78dbff
FR		 795
796 u16 event_slow;
c0e45c1c 797
798 struct mdio_ops {
24192210
FR		 799 void (*write)(struct rtl8169_private *, int, int);
800 int (*read)(struct rtl8169_private *, int);
c0e45c1c 801 } mdio_ops;
802
065c27c1 803 struct pll_power_ops {
804 void (*down)(struct rtl8169_private *);
805 void (*up)(struct rtl8169_private *);
806 } pll_power_ops;
807
d58d46b5
FR		 808 struct jumbo_ops {
809 void (*enable)(struct rtl8169_private *);
810 void (*disable)(struct rtl8169_private *);
811 } jumbo_ops;
812
beb1fe18 813 struct csi_ops {
52989f0e
FR		 814 void (*write)(struct rtl8169_private *, int, int);
815 u32 (*read)(struct rtl8169_private *, int);
beb1fe18
HW		 816 } csi_ops;
817
54405cde 818 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
ccdffb9a 819 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
4da19633 820 void (*phy_reset_enable)(struct rtl8169_private *tp);
07ce4064 821 void (*hw_start)(struct net_device *);
4da19633 822 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
1da177e4 823 unsigned int (*link_ok)(void __iomem *);
8b4ab28d 824 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
5888d3fc 825 bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
4422bcd4
FR		 826
827 struct {
da78dbff
FR		 828 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
829 struct mutex mutex;
4422bcd4
FR		 830 struct work_struct work;
831 } wk;
832
f23e7fda 833 unsigned features;
ccdffb9a
FR		 834
835 struct mii_if_info mii;
42020320
CV		 836 dma_addr_t counters_phys_addr;
837 struct rtl8169_counters *counters;
6e85d5ad 838 struct rtl8169_tc_offsets tc_offset;
e1759441 839 u32 saved_wolopts;
e03f33af 840 u32 opts1_mask;
f1e02ed1 841
b6ffd97f
FR		 842 struct rtl_fw {
843 const struct firmware *fw;
1c361efb
FR		 844
845#define RTL_VER_SIZE 32
846
847 char version[RTL_VER_SIZE];
848
849 struct rtl_fw_phy_action {
850 __le32 *code;
851 size_t size;
852 } phy_action;
b6ffd97f 853 } *rtl_fw;
497888cf 854#define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
c558386b
HW		 855
856 u32 ocp_base;
1da177e4
LT		 857};
858
979b6c13 859MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 860MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 861module_param(use_dac, int, 0);
4300e8c7 862MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 863module_param_named(debug, debug.msg_enable, int, 0);
864MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 865MODULE_LICENSE("GPL");
866MODULE_VERSION(RTL8169_VERSION);
bca03d5f 867MODULE_FIRMWARE(FIRMWARE_8168D_1);
868MODULE_FIRMWARE(FIRMWARE_8168D_2);
01dc7fec 869MODULE_FIRMWARE(FIRMWARE_8168E_1);
870MODULE_FIRMWARE(FIRMWARE_8168E_2);
bbb8af75 871MODULE_FIRMWARE(FIRMWARE_8168E_3);
5a5e4443 872MODULE_FIRMWARE(FIRMWARE_8105E_1);
c2218925
HW		 873MODULE_FIRMWARE(FIRMWARE_8168F_1);
874MODULE_FIRMWARE(FIRMWARE_8168F_2);
7e18dca1 875MODULE_FIRMWARE(FIRMWARE_8402_1);
b3d7b2f2 876MODULE_FIRMWARE(FIRMWARE_8411_1);
45dd95c4 877MODULE_FIRMWARE(FIRMWARE_8411_2);
5598bfe5 878MODULE_FIRMWARE(FIRMWARE_8106E_1);
58152cd4 879MODULE_FIRMWARE(FIRMWARE_8106E_2);
beb330a4 880MODULE_FIRMWARE(FIRMWARE_8168G_2);
57538c4a 881MODULE_FIRMWARE(FIRMWARE_8168G_3);
6e1d0b89
CHL		 882MODULE_FIRMWARE(FIRMWARE_8168H_1);
883MODULE_FIRMWARE(FIRMWARE_8168H_2);
a3bf5c42
FR		 884MODULE_FIRMWARE(FIRMWARE_8107E_1);
885MODULE_FIRMWARE(FIRMWARE_8107E_2);
1da177e4 886
da78dbff
FR		 887static void rtl_lock_work(struct rtl8169_private *tp)
888{
889 mutex_lock(&tp->wk.mutex);
890}
891
892static void rtl_unlock_work(struct rtl8169_private *tp)
893{
894 mutex_unlock(&tp->wk.mutex);
895}
896
d58d46b5
FR		 897static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
898{
7d7903b2
JL		 899 pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
900 PCI_EXP_DEVCTL_READRQ, force);
d58d46b5
FR		 901}
902
ffc46952
FR		 903struct rtl_cond {
904 bool (*check)(struct rtl8169_private *);
905 const char *msg;
906};
907
908static void rtl_udelay(unsigned int d)
909{
910 udelay(d);
911}
912
913static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
914 void (*delay)(unsigned int), unsigned int d, int n,
915 bool high)
916{
917 int i;
918
919 for (i = 0; i < n; i++) {
920 delay(d);
921 if (c->check(tp) == high)
922 return true;
923 }
82e316ef
FR		 924 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
925 c->msg, !high, n, d);
ffc46952
FR		 926 return false;
927}
928
929static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
930 const struct rtl_cond *c,
931 unsigned int d, int n)
932{
933 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
934}
935
936static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
937 const struct rtl_cond *c,
938 unsigned int d, int n)
939{
940 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
941}
942
943static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
944 const struct rtl_cond *c,
945 unsigned int d, int n)
946{
947 return rtl_loop_wait(tp, c, msleep, d, n, true);
948}
949
950static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
951 const struct rtl_cond *c,
952 unsigned int d, int n)
953{
954 return rtl_loop_wait(tp, c, msleep, d, n, false);
955}
956
957#define DECLARE_RTL_COND(name) \
958static bool name ## _check(struct rtl8169_private *); \
959 \
960static const struct rtl_cond name = { \
961 .check = name ## _check, \
962 .msg = #name \
963}; \
964 \
965static bool name ## _check(struct rtl8169_private *tp)
966
c558386b
HW		 967static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
968{
969 if (reg & 0xffff0001) {
970 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
971 return true;
972 }
973 return false;
974}
975
976DECLARE_RTL_COND(rtl_ocp_gphy_cond)
977{
978 void __iomem *ioaddr = tp->mmio_addr;
979
980 return RTL_R32(GPHY_OCP) & OCPAR_FLAG;
981}
982
983static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
984{
985 void __iomem *ioaddr = tp->mmio_addr;
986
987 if (rtl_ocp_reg_failure(tp, reg))
988 return;
989
990 RTL_W32(GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
991
992 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
993}
994
995static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
996{
997 void __iomem *ioaddr = tp->mmio_addr;
998
999 if (rtl_ocp_reg_failure(tp, reg))
1000 return 0;
1001
1002 RTL_W32(GPHY_OCP, reg << 15);
1003
1004 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
1005 (RTL_R32(GPHY_OCP) & 0xffff) : ~0;
1006}
1007
c558386b
HW		 1008static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1009{
1010 void __iomem *ioaddr = tp->mmio_addr;
1011
1012 if (rtl_ocp_reg_failure(tp, reg))
1013 return;
1014
1015 RTL_W32(OCPDR, OCPAR_FLAG | (reg << 15) | data);
c558386b
HW		 1016}
1017
1018static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1019{
1020 void __iomem *ioaddr = tp->mmio_addr;
1021
1022 if (rtl_ocp_reg_failure(tp, reg))
1023 return 0;
1024
1025 RTL_W32(OCPDR, reg << 15);
1026
3a83ad12 1027 return RTL_R32(OCPDR);
c558386b
HW		 1028}
1029
1030#define OCP_STD_PHY_BASE 0xa400
1031
1032static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
1033{
1034 if (reg == 0x1f) {
1035 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
1036 return;
1037 }
1038
1039 if (tp->ocp_base != OCP_STD_PHY_BASE)
1040 reg -= 0x10;
1041
1042 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
1043}
1044
1045static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1046{
1047 if (tp->ocp_base != OCP_STD_PHY_BASE)
1048 reg -= 0x10;
1049
1050 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
1051}
1052
eee3786f 1053static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
1054{
1055 if (reg == 0x1f) {
1056 tp->ocp_base = value << 4;
1057 return;
1058 }
1059
1060 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
1061}
1062
1063static int mac_mcu_read(struct rtl8169_private *tp, int reg)
1064{
1065 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
1066}
1067
ffc46952
FR		 1068DECLARE_RTL_COND(rtl_phyar_cond)
1069{
1070 void __iomem *ioaddr = tp->mmio_addr;
1071
1072 return RTL_R32(PHYAR) & 0x80000000;
1073}
1074
24192210 1075static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1da177e4 1076{
24192210 1077 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 1078
24192210 1079 RTL_W32(PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1da177e4 1080
ffc46952 1081 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
024a07ba 1082 /*
81a95f04
TT		 1083 * According to hardware specs a 20us delay is required after write
1084 * complete indication, but before sending next command.
024a07ba 1085 */
81a95f04 1086 udelay(20);
1da177e4
LT		 1087}
1088
24192210 1089static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1da177e4 1090{
24192210 1091 void __iomem *ioaddr = tp->mmio_addr;
ffc46952 1092 int value;
1da177e4 1093
24192210 1094 RTL_W32(PHYAR, 0x0 | (reg & 0x1f) << 16);
1da177e4 1095
ffc46952
FR		 1096 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1097 RTL_R32(PHYAR) & 0xffff : ~0;
1098
81a95f04
TT		 1099 /*
1100 * According to hardware specs a 20us delay is required after read
1101 * complete indication, but before sending next command.
1102 */
1103 udelay(20);
1104
1da177e4
LT		 1105 return value;
1106}
1107
935e2218
CHL		 1108DECLARE_RTL_COND(rtl_ocpar_cond)
1109{
1110 void __iomem *ioaddr = tp->mmio_addr;
1111
1112 return RTL_R32(OCPAR) & OCPAR_FLAG;
1113}
1114
24192210 1115static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
c0e45c1c 1116{
24192210 1117 void __iomem *ioaddr = tp->mmio_addr;
c0e45c1c 1118
24192210 1119 RTL_W32(OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
c0e45c1c 1120 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
1121 RTL_W32(EPHY_RXER_NUM, 0);
1122
ffc46952 1123 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
c0e45c1c 1124}
1125
24192210 1126static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
c0e45c1c 1127{
24192210
FR		 1128 r8168dp_1_mdio_access(tp, reg,
1129 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
c0e45c1c 1130}
1131
24192210 1132static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
c0e45c1c 1133{
24192210 1134 void __iomem *ioaddr = tp->mmio_addr;
c0e45c1c 1135
24192210 1136 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
c0e45c1c 1137
1138 mdelay(1);
1139 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
1140 RTL_W32(EPHY_RXER_NUM, 0);
1141
ffc46952
FR		 1142 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1143 RTL_R32(OCPDR) & OCPDR_DATA_MASK : ~0;
c0e45c1c 1144}
1145
e6de30d6 1146#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1147
1148static void r8168dp_2_mdio_start(void __iomem *ioaddr)
1149{
1150 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1151}
1152
1153static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
1154{
1155 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1156}
1157
24192210 1158static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
e6de30d6 1159{
24192210
FR		 1160 void __iomem *ioaddr = tp->mmio_addr;
1161
e6de30d6 1162 r8168dp_2_mdio_start(ioaddr);
1163
24192210 1164 r8169_mdio_write(tp, reg, value);
e6de30d6 1165
1166 r8168dp_2_mdio_stop(ioaddr);
1167}
1168
24192210 1169static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
e6de30d6 1170{
24192210 1171 void __iomem *ioaddr = tp->mmio_addr;
e6de30d6 1172 int value;
1173
1174 r8168dp_2_mdio_start(ioaddr);
1175
24192210 1176 value = r8169_mdio_read(tp, reg);
e6de30d6 1177
1178 r8168dp_2_mdio_stop(ioaddr);
1179
1180 return value;
1181}
1182
4da19633 1183static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
dacf8154 1184{
24192210 1185 tp->mdio_ops.write(tp, location, val);
dacf8154
FR		 1186}
1187
4da19633 1188static int rtl_readphy(struct rtl8169_private *tp, int location)
1189{
24192210 1190 return tp->mdio_ops.read(tp, location);
4da19633 1191}
1192
1193static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1194{
1195 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1196}
1197
76564428 1198static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
daf9df6d 1199{
1200 int val;
1201
4da19633 1202 val = rtl_readphy(tp, reg_addr);
76564428 1203 rtl_writephy(tp, reg_addr, (val & ~m) | p);
daf9df6d 1204}
1205
ccdffb9a
FR		 1206static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1207 int val)
1208{
1209 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1210
4da19633 1211 rtl_writephy(tp, location, val);
ccdffb9a
FR		 1212}
1213
1214static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1215{
1216 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1217
4da19633 1218 return rtl_readphy(tp, location);
ccdffb9a
FR		 1219}
1220
ffc46952
FR		 1221DECLARE_RTL_COND(rtl_ephyar_cond)
1222{
1223 void __iomem *ioaddr = tp->mmio_addr;
1224
1225 return RTL_R32(EPHYAR) & EPHYAR_FLAG;
1226}
1227
fdf6fc06 1228static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
dacf8154 1229{
fdf6fc06 1230 void __iomem *ioaddr = tp->mmio_addr;
dacf8154
FR		 1231
1232 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1233 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1234
ffc46952
FR		 1235 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1236
1237 udelay(10);
dacf8154
FR		 1238}
1239
fdf6fc06 1240static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
dacf8154 1241{
fdf6fc06 1242 void __iomem *ioaddr = tp->mmio_addr;
dacf8154
FR		 1243
1244 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1245
ffc46952
FR		 1246 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1247 RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0;
dacf8154
FR		 1248}
1249
935e2218
CHL		 1250DECLARE_RTL_COND(rtl_eriar_cond)
1251{
1252 void __iomem *ioaddr = tp->mmio_addr;
1253
1254 return RTL_R32(ERIAR) & ERIAR_FLAG;
1255}
1256
fdf6fc06
FR		 1257static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1258 u32 val, int type)
133ac40a 1259{
fdf6fc06 1260 void __iomem *ioaddr = tp->mmio_addr;
133ac40a
HW		 1261
1262 BUG_ON((addr & 3) || (mask == 0));
1263 RTL_W32(ERIDR, val);
1264 RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1265
ffc46952 1266 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
133ac40a
HW		 1267}
1268
fdf6fc06 1269static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
133ac40a 1270{
fdf6fc06 1271 void __iomem *ioaddr = tp->mmio_addr;
133ac40a
HW		 1272
1273 RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1274
ffc46952
FR		 1275 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1276 RTL_R32(ERIDR) : ~0;
133ac40a
HW		 1277}
1278
706123d0 1279static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
fdf6fc06 1280 u32 m, int type)
133ac40a
HW		 1281{
1282 u32 val;
1283
fdf6fc06
FR		 1284 val = rtl_eri_read(tp, addr, type);
1285 rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
133ac40a
HW		 1286}
1287
935e2218
CHL		 1288static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1289{
1290 void __iomem *ioaddr = tp->mmio_addr;
1291
1292 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1293 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1294 RTL_R32(OCPDR) : ~0;
1295}
1296
1297static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1298{
1299 return rtl_eri_read(tp, reg, ERIAR_OOB);
1300}
1301
1302static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1303{
1304 switch (tp->mac_version) {
1305 case RTL_GIGA_MAC_VER_27:
1306 case RTL_GIGA_MAC_VER_28:
1307 case RTL_GIGA_MAC_VER_31:
1308 return r8168dp_ocp_read(tp, mask, reg);
1309 case RTL_GIGA_MAC_VER_49:
1310 case RTL_GIGA_MAC_VER_50:
1311 case RTL_GIGA_MAC_VER_51:
1312 return r8168ep_ocp_read(tp, mask, reg);
1313 default:
1314 BUG();
1315 return ~0;
1316 }
1317}
1318
1319static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1320 u32 data)
1321{
1322 void __iomem *ioaddr = tp->mmio_addr;
1323
1324 RTL_W32(OCPDR, data);
1325 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1326 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1327}
1328
1329static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1330 u32 data)
1331{
1332 rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1333 data, ERIAR_OOB);
1334}
1335
1336static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
1337{
1338 switch (tp->mac_version) {
1339 case RTL_GIGA_MAC_VER_27:
1340 case RTL_GIGA_MAC_VER_28:
1341 case RTL_GIGA_MAC_VER_31:
1342 r8168dp_ocp_write(tp, mask, reg, data);
1343 break;
1344 case RTL_GIGA_MAC_VER_49:
1345 case RTL_GIGA_MAC_VER_50:
1346 case RTL_GIGA_MAC_VER_51:
1347 r8168ep_ocp_write(tp, mask, reg, data);
1348 break;
1349 default:
1350 BUG();
1351 break;
1352 }
1353}
1354
2a9b4d96
CHL		 1355static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
1356{
1357 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC);
1358
1359 ocp_write(tp, 0x1, 0x30, 0x00000001);
1360}
1361
1362#define OOB_CMD_RESET 0x00
1363#define OOB_CMD_DRIVER_START 0x05
1364#define OOB_CMD_DRIVER_STOP 0x06
1365
1366static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1367{
1368 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1369}
1370
1371DECLARE_RTL_COND(rtl_ocp_read_cond)
1372{
1373 u16 reg;
1374
1375 reg = rtl8168_get_ocp_reg(tp);
1376
1377 return ocp_read(tp, 0x0f, reg) & 0x00000800;
1378}
1379
935e2218 1380DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
2a9b4d96 1381{
935e2218
CHL		 1382 return ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1383}
1384
1385DECLARE_RTL_COND(rtl_ocp_tx_cond)
1386{
1387 void __iomem *ioaddr = tp->mmio_addr;
1388
1389 return RTL_R8(IBISR0) & 0x02;
1390}
2a9b4d96 1391
003609da
CHL		 1392static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1393{
1394 void __iomem *ioaddr = tp->mmio_addr;
1395
1396 RTL_W8(IBCR2, RTL_R8(IBCR2) & ~0x01);
1397 rtl_msleep_loop_wait_low(tp, &rtl_ocp_tx_cond, 50, 2000);
1398 RTL_W8(IBISR0, RTL_R8(IBISR0) | 0x20);
1399 RTL_W8(IBCR0, RTL_R8(IBCR0) & ~0x01);
1400}
1401
935e2218
CHL		 1402static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1403{
1404 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
2a9b4d96
CHL		 1405 rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
1406}
1407
935e2218 1408static void rtl8168ep_driver_start(struct rtl8169_private *tp)
2a9b4d96 1409{
935e2218
CHL		 1410 ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1411 ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1412 rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1413}
1414
1415static void rtl8168_driver_start(struct rtl8169_private *tp)
1416{
1417 switch (tp->mac_version) {
1418 case RTL_GIGA_MAC_VER_27:
1419 case RTL_GIGA_MAC_VER_28:
1420 case RTL_GIGA_MAC_VER_31:
1421 rtl8168dp_driver_start(tp);
1422 break;
1423 case RTL_GIGA_MAC_VER_49:
1424 case RTL_GIGA_MAC_VER_50:
1425 case RTL_GIGA_MAC_VER_51:
1426 rtl8168ep_driver_start(tp);
1427 break;
1428 default:
1429 BUG();
1430 break;
1431 }
1432}
2a9b4d96 1433
935e2218
CHL		 1434static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1435{
1436 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
2a9b4d96
CHL		 1437 rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
1438}
1439
935e2218
CHL		 1440static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1441{
003609da 1442 rtl8168ep_stop_cmac(tp);
935e2218
CHL		 1443 ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1444 ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1445 rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1446}
1447
1448static void rtl8168_driver_stop(struct rtl8169_private *tp)
1449{
1450 switch (tp->mac_version) {
1451 case RTL_GIGA_MAC_VER_27:
1452 case RTL_GIGA_MAC_VER_28:
1453 case RTL_GIGA_MAC_VER_31:
1454 rtl8168dp_driver_stop(tp);
1455 break;
1456 case RTL_GIGA_MAC_VER_49:
1457 case RTL_GIGA_MAC_VER_50:
1458 case RTL_GIGA_MAC_VER_51:
1459 rtl8168ep_driver_stop(tp);
1460 break;
1461 default:
1462 BUG();
1463 break;
1464 }
1465}
1466
1467static int r8168dp_check_dash(struct rtl8169_private *tp)
2a9b4d96
CHL		 1468{
1469 u16 reg = rtl8168_get_ocp_reg(tp);
1470
1471 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
1472}
1473
935e2218
CHL		 1474static int r8168ep_check_dash(struct rtl8169_private *tp)
1475{
1476 return (ocp_read(tp, 0x0f, 0x128) & 0x00000001) ? 1 : 0;
1477}
1478
1479static int r8168_check_dash(struct rtl8169_private *tp)
1480{
1481 switch (tp->mac_version) {
1482 case RTL_GIGA_MAC_VER_27:
1483 case RTL_GIGA_MAC_VER_28:
1484 case RTL_GIGA_MAC_VER_31:
1485 return r8168dp_check_dash(tp);
1486 case RTL_GIGA_MAC_VER_49:
1487 case RTL_GIGA_MAC_VER_50:
1488 case RTL_GIGA_MAC_VER_51:
1489 return r8168ep_check_dash(tp);
1490 default:
1491 return 0;
1492 }
1493}
1494
c28aa385 1495struct exgmac_reg {
1496 u16 addr;
1497 u16 mask;
1498 u32 val;
1499};
1500
fdf6fc06 1501static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
c28aa385 1502 const struct exgmac_reg *r, int len)
1503{
1504 while (len-- > 0) {
fdf6fc06 1505 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
c28aa385 1506 r++;
1507 }
1508}
1509
ffc46952
FR		 1510DECLARE_RTL_COND(rtl_efusear_cond)
1511{
1512 void __iomem *ioaddr = tp->mmio_addr;
1513
1514 return RTL_R32(EFUSEAR) & EFUSEAR_FLAG;
1515}
1516
fdf6fc06 1517static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
daf9df6d 1518{
fdf6fc06 1519 void __iomem *ioaddr = tp->mmio_addr;
daf9df6d 1520
1521 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1522
ffc46952
FR		 1523 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1524 RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
daf9df6d 1525}
1526
9085cdfa
FR		 1527static u16 rtl_get_events(struct rtl8169_private *tp)
1528{
1529 void __iomem *ioaddr = tp->mmio_addr;
1530
1531 return RTL_R16(IntrStatus);
1532}
1533
1534static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1535{
1536 void __iomem *ioaddr = tp->mmio_addr;
1537
1538 RTL_W16(IntrStatus, bits);
1539 mmiowb();
1540}
1541
1542static void rtl_irq_disable(struct rtl8169_private *tp)
1543{
1544 void __iomem *ioaddr = tp->mmio_addr;
1545
1546 RTL_W16(IntrMask, 0);
1547 mmiowb();
1548}
1549
3e990ff5
FR		 1550static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1551{
1552 void __iomem *ioaddr = tp->mmio_addr;
1553
1554 RTL_W16(IntrMask, bits);
1555}
1556
da78dbff
FR		 1557#define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1558#define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1559#define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1560
1561static void rtl_irq_enable_all(struct rtl8169_private *tp)
1562{
1563 rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1564}
1565
811fd301 1566static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1da177e4 1567{
811fd301 1568 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 1569
9085cdfa 1570 rtl_irq_disable(tp);
da78dbff 1571 rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
811fd301 1572 RTL_R8(ChipCmd);
1da177e4
LT		 1573}
1574
4da19633 1575static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1da177e4 1576{
4da19633 1577 void __iomem *ioaddr = tp->mmio_addr;
1578
1da177e4
LT		 1579 return RTL_R32(TBICSR) & TBIReset;
1580}
1581
4da19633 1582static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1da177e4 1583{
4da19633 1584 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 1585}
1586
1587static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1588{
1589 return RTL_R32(TBICSR) & TBILinkOk;
1590}
1591
1592static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1593{
1594 return RTL_R8(PHYstatus) & LinkStatus;
1595}
1596
4da19633 1597static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1da177e4 1598{
4da19633 1599 void __iomem *ioaddr = tp->mmio_addr;
1600
1da177e4
LT		 1601 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1602}
1603
4da19633 1604static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1da177e4
LT		 1605{
1606 unsigned int val;
1607
4da19633 1608 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1609 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1da177e4
LT		 1610}
1611
70090424
HW		 1612static void rtl_link_chg_patch(struct rtl8169_private *tp)
1613{
1614 void __iomem *ioaddr = tp->mmio_addr;
1615 struct net_device *dev = tp->dev;
1616
1617 if (!netif_running(dev))
1618 return;
1619
b3d7b2f2
HW		 1620 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1621 tp->mac_version == RTL_GIGA_MAC_VER_38) {
70090424 1622 if (RTL_R8(PHYstatus) & _1000bpsF) {
fdf6fc06
FR		 1623 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1624 ERIAR_EXGMAC);
1625 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1626 ERIAR_EXGMAC);
70090424 1627 } else if (RTL_R8(PHYstatus) & _100bps) {
fdf6fc06
FR		 1628 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1629 ERIAR_EXGMAC);
1630 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1631 ERIAR_EXGMAC);
70090424 1632 } else {
fdf6fc06
FR		 1633 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1634 ERIAR_EXGMAC);
1635 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1636 ERIAR_EXGMAC);
70090424
HW		 1637 }
1638 /* Reset packet filter */
706123d0 1639 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
70090424 1640 ERIAR_EXGMAC);
706123d0 1641 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
70090424 1642 ERIAR_EXGMAC);
c2218925
HW		 1643 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1644 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1645 if (RTL_R8(PHYstatus) & _1000bpsF) {
fdf6fc06
FR		 1646 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1647 ERIAR_EXGMAC);
1648 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1649 ERIAR_EXGMAC);
c2218925 1650 } else {
fdf6fc06
FR		 1651 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1652 ERIAR_EXGMAC);
1653 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1654 ERIAR_EXGMAC);
c2218925 1655 }
7e18dca1
HW		 1656 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1657 if (RTL_R8(PHYstatus) & _10bps) {
fdf6fc06
FR		 1658 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1659 ERIAR_EXGMAC);
1660 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1661 ERIAR_EXGMAC);
7e18dca1 1662 } else {
fdf6fc06
FR		 1663 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1664 ERIAR_EXGMAC);
7e18dca1 1665 }
70090424
HW		 1666 }
1667}
1668
e4fbce74 1669static void __rtl8169_check_link_status(struct net_device *dev,
cecb5fd7
FR		 1670 struct rtl8169_private *tp,
1671 void __iomem *ioaddr, bool pm)
1da177e4 1672{
1da177e4 1673 if (tp->link_ok(ioaddr)) {
70090424 1674 rtl_link_chg_patch(tp);
e1759441 1675 /* This is to cancel a scheduled suspend if there's one. */
e4fbce74
RW		 1676 if (pm)
1677 pm_request_resume(&tp->pci_dev->dev);
1da177e4 1678 netif_carrier_on(dev);
1519e57f
FR		 1679 if (net_ratelimit())
1680 netif_info(tp, ifup, dev, "link up\n");
b57b7e5a 1681 } else {
1da177e4 1682 netif_carrier_off(dev);
bf82c189 1683 netif_info(tp, ifdown, dev, "link down\n");
e4fbce74 1684 if (pm)
10953db8 1685 pm_schedule_suspend(&tp->pci_dev->dev, 5000);
b57b7e5a 1686 }
1da177e4
LT		 1687}
1688
e4fbce74
RW		 1689static void rtl8169_check_link_status(struct net_device *dev,
1690 struct rtl8169_private *tp,
1691 void __iomem *ioaddr)
1692{
1693 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1694}
1695
e1759441
RW		 1696#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1697
1698static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
61a4dcc2 1699{
61a4dcc2
FR		 1700 void __iomem *ioaddr = tp->mmio_addr;
1701 u8 options;
e1759441 1702 u32 wolopts = 0;
61a4dcc2
FR		 1703
1704 options = RTL_R8(Config1);
1705 if (!(options & PMEnable))
e1759441 1706 return 0;
61a4dcc2
FR		 1707
1708 options = RTL_R8(Config3);
1709 if (options & LinkUp)
e1759441 1710 wolopts |= WAKE_PHY;
6e1d0b89 1711 switch (tp->mac_version) {
ac85bcdb
CHL		 1712 case RTL_GIGA_MAC_VER_34:
1713 case RTL_GIGA_MAC_VER_35:
1714 case RTL_GIGA_MAC_VER_36:
1715 case RTL_GIGA_MAC_VER_37:
1716 case RTL_GIGA_MAC_VER_38:
1717 case RTL_GIGA_MAC_VER_40:
1718 case RTL_GIGA_MAC_VER_41:
1719 case RTL_GIGA_MAC_VER_42:
1720 case RTL_GIGA_MAC_VER_43:
1721 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 1722 case RTL_GIGA_MAC_VER_45:
1723 case RTL_GIGA_MAC_VER_46:
ac85bcdb
CHL		 1724 case RTL_GIGA_MAC_VER_47:
1725 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 1726 case RTL_GIGA_MAC_VER_49:
1727 case RTL_GIGA_MAC_VER_50:
1728 case RTL_GIGA_MAC_VER_51:
6e1d0b89
CHL		 1729 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
1730 wolopts |= WAKE_MAGIC;
1731 break;
1732 default:
1733 if (options & MagicPacket)
1734 wolopts |= WAKE_MAGIC;
1735 break;
1736 }
61a4dcc2
FR		 1737
1738 options = RTL_R8(Config5);
1739 if (options & UWF)
e1759441 1740 wolopts |= WAKE_UCAST;
61a4dcc2 1741 if (options & BWF)
e1759441 1742 wolopts |= WAKE_BCAST;
61a4dcc2 1743 if (options & MWF)
e1759441 1744 wolopts |= WAKE_MCAST;
61a4dcc2 1745
e1759441 1746 return wolopts;
61a4dcc2
FR		 1747}
1748
e1759441 1749static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
61a4dcc2
FR		 1750{
1751 struct rtl8169_private *tp = netdev_priv(dev);
5fa80a32
CHL		 1752 struct device *d = &tp->pci_dev->dev;
1753
1754 pm_runtime_get_noresume(d);
e1759441 1755
da78dbff 1756 rtl_lock_work(tp);
e1759441
RW		 1757
1758 wol->supported = WAKE_ANY;
5fa80a32
CHL		 1759 if (pm_runtime_active(d))
1760 wol->wolopts = __rtl8169_get_wol(tp);
1761 else
1762 wol->wolopts = tp->saved_wolopts;
e1759441 1763
da78dbff 1764 rtl_unlock_work(tp);
5fa80a32
CHL		 1765
1766 pm_runtime_put_noidle(d);
e1759441
RW		 1767}
1768
1769static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1770{
61a4dcc2 1771 void __iomem *ioaddr = tp->mmio_addr;
6e1d0b89 1772 unsigned int i, tmp;
350f7596 1773 static const struct {
61a4dcc2
FR		 1774 u32 opt;
1775 u16 reg;
1776 u8 mask;
1777 } cfg[] = {
61a4dcc2 1778 { WAKE_PHY, Config3, LinkUp },
61a4dcc2
FR		 1779 { WAKE_UCAST, Config5, UWF },
1780 { WAKE_BCAST, Config5, BWF },
1781 { WAKE_MCAST, Config5, MWF },
6e1d0b89
CHL		 1782 { WAKE_ANY, Config5, LanWake },
1783 { WAKE_MAGIC, Config3, MagicPacket }
61a4dcc2 1784 };
851e6022 1785 u8 options;
61a4dcc2 1786
61a4dcc2
FR		 1787 RTL_W8(Cfg9346, Cfg9346_Unlock);
1788
6e1d0b89 1789 switch (tp->mac_version) {
ac85bcdb
CHL		 1790 case RTL_GIGA_MAC_VER_34:
1791 case RTL_GIGA_MAC_VER_35:
1792 case RTL_GIGA_MAC_VER_36:
1793 case RTL_GIGA_MAC_VER_37:
1794 case RTL_GIGA_MAC_VER_38:
1795 case RTL_GIGA_MAC_VER_40:
1796 case RTL_GIGA_MAC_VER_41:
1797 case RTL_GIGA_MAC_VER_42:
1798 case RTL_GIGA_MAC_VER_43:
1799 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 1800 case RTL_GIGA_MAC_VER_45:
1801 case RTL_GIGA_MAC_VER_46:
ac85bcdb
CHL		 1802 case RTL_GIGA_MAC_VER_47:
1803 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 1804 case RTL_GIGA_MAC_VER_49:
1805 case RTL_GIGA_MAC_VER_50:
1806 case RTL_GIGA_MAC_VER_51:
6e1d0b89
CHL		 1807 tmp = ARRAY_SIZE(cfg) - 1;
1808 if (wolopts & WAKE_MAGIC)
706123d0 1809 rtl_w0w1_eri(tp,
6e1d0b89
CHL		 1810 0x0dc,
1811 ERIAR_MASK_0100,
1812 MagicPacket_v2,
1813 0x0000,
1814 ERIAR_EXGMAC);
1815 else
706123d0 1816 rtl_w0w1_eri(tp,
6e1d0b89
CHL		 1817 0x0dc,
1818 ERIAR_MASK_0100,
1819 0x0000,
1820 MagicPacket_v2,
1821 ERIAR_EXGMAC);
1822 break;
1823 default:
1824 tmp = ARRAY_SIZE(cfg);
1825 break;
1826 }
1827
1828 for (i = 0; i < tmp; i++) {
851e6022 1829 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
e1759441 1830 if (wolopts & cfg[i].opt)
61a4dcc2
FR		 1831 options |= cfg[i].mask;
1832 RTL_W8(cfg[i].reg, options);
1833 }
1834
851e6022
FR		 1835 switch (tp->mac_version) {
1836 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1837 options = RTL_R8(Config1) & ~PMEnable;
1838 if (wolopts)
1839 options |= PMEnable;
1840 RTL_W8(Config1, options);
1841 break;
1842 default:
d387b427
FR		 1843 options = RTL_R8(Config2) & ~PME_SIGNAL;
1844 if (wolopts)
1845 options |= PME_SIGNAL;
1846 RTL_W8(Config2, options);
851e6022
FR		 1847 break;
1848 }
1849
61a4dcc2 1850 RTL_W8(Cfg9346, Cfg9346_Lock);
e1759441
RW		 1851}
1852
1853static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1854{
1855 struct rtl8169_private *tp = netdev_priv(dev);
5fa80a32
CHL		 1856 struct device *d = &tp->pci_dev->dev;
1857
1858 pm_runtime_get_noresume(d);
e1759441 1859
da78dbff 1860 rtl_lock_work(tp);
61a4dcc2 1861
f23e7fda
FR		 1862 if (wol->wolopts)
1863 tp->features |= RTL_FEATURE_WOL;
1864 else
1865 tp->features &= ~RTL_FEATURE_WOL;
5fa80a32
CHL		 1866 if (pm_runtime_active(d))
1867 __rtl8169_set_wol(tp, wol->wolopts);
1868 else
1869 tp->saved_wolopts = wol->wolopts;
da78dbff
FR		 1870
1871 rtl_unlock_work(tp);
61a4dcc2 1872
ea80907f 1873 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1874
5fa80a32
CHL		 1875 pm_runtime_put_noidle(d);
1876
61a4dcc2
FR		 1877 return 0;
1878}
1879
31bd204f
FR		 1880static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1881{
85bffe6c 1882 return rtl_chip_infos[tp->mac_version].fw_name;
31bd204f
FR		 1883}
1884
1da177e4
LT		 1885static void rtl8169_get_drvinfo(struct net_device *dev,
1886 struct ethtool_drvinfo *info)
1887{
1888 struct rtl8169_private *tp = netdev_priv(dev);
b6ffd97f 1889 struct rtl_fw *rtl_fw = tp->rtl_fw;
1da177e4 1890
68aad78c
RJ		 1891 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1892 strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1893 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1c361efb 1894 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
8ac72d16
RJ		 1895 if (!IS_ERR_OR_NULL(rtl_fw))
1896 strlcpy(info->fw_version, rtl_fw->version,
1897 sizeof(info->fw_version));
1da177e4
LT		 1898}
1899
1900static int rtl8169_get_regs_len(struct net_device *dev)
1901{
1902 return R8169_REGS_SIZE;
1903}
1904
1905static int rtl8169_set_speed_tbi(struct net_device *dev,
54405cde 1906 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1da177e4
LT		 1907{
1908 struct rtl8169_private *tp = netdev_priv(dev);
1909 void __iomem *ioaddr = tp->mmio_addr;
1910 int ret = 0;
1911 u32 reg;
1912
1913 reg = RTL_R32(TBICSR);
1914 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1915 (duplex == DUPLEX_FULL)) {
1916 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1917 } else if (autoneg == AUTONEG_ENABLE)
1918 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1919 else {
bf82c189
JP		 1920 netif_warn(tp, link, dev,
1921 "incorrect speed setting refused in TBI mode\n");
1da177e4
LT		 1922 ret = -EOPNOTSUPP;
1923 }
1924
1925 return ret;
1926}
1927
1928static int rtl8169_set_speed_xmii(struct net_device *dev,
54405cde 1929 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1da177e4
LT		 1930{
1931 struct rtl8169_private *tp = netdev_priv(dev);
3577aa1b 1932 int giga_ctrl, bmcr;
54405cde 1933 int rc = -EINVAL;
1da177e4 1934
716b50a3 1935 rtl_writephy(tp, 0x1f, 0x0000);
1da177e4
LT		 1936
1937 if (autoneg == AUTONEG_ENABLE) {
3577aa1b 1938 int auto_nego;
1939
4da19633 1940 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
54405cde
ON		 1941 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1942 ADVERTISE_100HALF | ADVERTISE_100FULL);
1943
1944 if (adv & ADVERTISED_10baseT_Half)
1945 auto_nego |= ADVERTISE_10HALF;
1946 if (adv & ADVERTISED_10baseT_Full)
1947 auto_nego |= ADVERTISE_10FULL;
1948 if (adv & ADVERTISED_100baseT_Half)
1949 auto_nego |= ADVERTISE_100HALF;
1950 if (adv & ADVERTISED_100baseT_Full)
1951 auto_nego |= ADVERTISE_100FULL;
1952
3577aa1b 1953 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1da177e4 1954
4da19633 1955 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
3577aa1b 1956 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
bcf0bf90 1957
3577aa1b 1958 /* The 8100e/8101e/8102e do Fast Ethernet only. */
826e6cbd 1959 if (tp->mii.supports_gmii) {
54405cde
ON		 1960 if (adv & ADVERTISED_1000baseT_Half)
1961 giga_ctrl |= ADVERTISE_1000HALF;
1962 if (adv & ADVERTISED_1000baseT_Full)
1963 giga_ctrl |= ADVERTISE_1000FULL;
1964 } else if (adv & (ADVERTISED_1000baseT_Half |
1965 ADVERTISED_1000baseT_Full)) {
bf82c189
JP		 1966 netif_info(tp, link, dev,
1967 "PHY does not support 1000Mbps\n");
54405cde 1968 goto out;
bcf0bf90 1969 }
1da177e4 1970
3577aa1b 1971 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1972
4da19633 1973 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1974 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
3577aa1b 1975 } else {
1976 giga_ctrl = 0;
1977
1978 if (speed == SPEED_10)
1979 bmcr = 0;
1980 else if (speed == SPEED_100)
1981 bmcr = BMCR_SPEED100;
1982 else
54405cde 1983 goto out;
3577aa1b 1984
1985 if (duplex == DUPLEX_FULL)
1986 bmcr |= BMCR_FULLDPLX;
2584fbc3
RS		 1987 }
1988
4da19633 1989 rtl_writephy(tp, MII_BMCR, bmcr);
3577aa1b 1990
cecb5fd7
FR		 1991 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1992 tp->mac_version == RTL_GIGA_MAC_VER_03) {
3577aa1b 1993 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
4da19633 1994 rtl_writephy(tp, 0x17, 0x2138);
1995 rtl_writephy(tp, 0x0e, 0x0260);
3577aa1b 1996 } else {
4da19633 1997 rtl_writephy(tp, 0x17, 0x2108);
1998 rtl_writephy(tp, 0x0e, 0x0000);
3577aa1b 1999 }
2000 }
2001
54405cde
ON		 2002 rc = 0;
2003out:
2004 return rc;
1da177e4
LT		 2005}
2006
2007static int rtl8169_set_speed(struct net_device *dev,
54405cde 2008 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1da177e4
LT		 2009{
2010 struct rtl8169_private *tp = netdev_priv(dev);
2011 int ret;
2012
54405cde 2013 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
4876cc1e
FR		 2014 if (ret < 0)
2015 goto out;
1da177e4 2016
4876cc1e 2017 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
c4556975
CHL		 2018 (advertising & ADVERTISED_1000baseT_Full) &&
2019 !pci_is_pcie(tp->pci_dev)) {
1da177e4 2020 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
4876cc1e
FR		 2021 }
2022out:
1da177e4
LT		 2023 return ret;
2024}
2025
2026static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2027{
2028 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4
LT		 2029 int ret;
2030
4876cc1e
FR		 2031 del_timer_sync(&tp->timer);
2032
da78dbff 2033 rtl_lock_work(tp);
cecb5fd7 2034 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
25db0338 2035 cmd->duplex, cmd->advertising);
da78dbff 2036 rtl_unlock_work(tp);
5b0384f4 2037
1da177e4
LT		 2038 return ret;
2039}
2040
c8f44aff
MM		 2041static netdev_features_t rtl8169_fix_features(struct net_device *dev,
2042 netdev_features_t features)
1da177e4 2043{
d58d46b5
FR		 2044 struct rtl8169_private *tp = netdev_priv(dev);
2045
2b7b4318 2046 if (dev->mtu > TD_MSS_MAX)
350fb32a 2047 features &= ~NETIF_F_ALL_TSO;
1da177e4 2048
d58d46b5
FR		 2049 if (dev->mtu > JUMBO_1K &&
2050 !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
2051 features &= ~NETIF_F_IP_CSUM;
2052
350fb32a 2053 return features;
1da177e4
LT		 2054}
2055
da78dbff
FR		 2056static void __rtl8169_set_features(struct net_device *dev,
2057 netdev_features_t features)
1da177e4
LT		 2058{
2059 struct rtl8169_private *tp = netdev_priv(dev);
da78dbff 2060 void __iomem *ioaddr = tp->mmio_addr;
929a031d 2061 u32 rx_config;
1da177e4 2062
929a031d 2063 rx_config = RTL_R32(RxConfig);
2064 if (features & NETIF_F_RXALL)
2065 rx_config |= (AcceptErr | AcceptRunt);
2066 else
2067 rx_config &= ~(AcceptErr | AcceptRunt);
1da177e4 2068
929a031d 2069 RTL_W32(RxConfig, rx_config);
350fb32a 2070
929a031d 2071 if (features & NETIF_F_RXCSUM)
2072 tp->cp_cmd |= RxChkSum;
2073 else
2074 tp->cp_cmd &= ~RxChkSum;
6bbe021d 2075
929a031d 2076 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2077 tp->cp_cmd |= RxVlan;
2078 else
2079 tp->cp_cmd &= ~RxVlan;
2080
2081 tp->cp_cmd |= RTL_R16(CPlusCmd) & ~(RxVlan | RxChkSum);
2082
2083 RTL_W16(CPlusCmd, tp->cp_cmd);
2084 RTL_R16(CPlusCmd);
da78dbff 2085}
1da177e4 2086
da78dbff
FR		 2087static int rtl8169_set_features(struct net_device *dev,
2088 netdev_features_t features)
2089{
2090 struct rtl8169_private *tp = netdev_priv(dev);
2091
929a031d 2092 features &= NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX;
2093
da78dbff 2094 rtl_lock_work(tp);
85911d71 2095 if (features ^ dev->features)
929a031d 2096 __rtl8169_set_features(dev, features);
da78dbff 2097 rtl_unlock_work(tp);
1da177e4
LT		 2098
2099 return 0;
2100}
2101
da78dbff 2102
810f4893 2103static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1da177e4 2104{
df8a39de
JP		 2105 return (skb_vlan_tag_present(skb)) ?
2106 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1da177e4
LT		 2107}
2108
7a8fc77b 2109static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1da177e4
LT		 2110{
2111 u32 opts2 = le32_to_cpu(desc->opts2);
1da177e4 2112
7a8fc77b 2113 if (opts2 & RxVlanTag)
86a9bad3 2114 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1da177e4
LT		 2115}
2116
ccdffb9a 2117static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 2118{
2119 struct rtl8169_private *tp = netdev_priv(dev);
2120 void __iomem *ioaddr = tp->mmio_addr;
2121 u32 status;
2122
2123 cmd->supported =
2124 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
2125 cmd->port = PORT_FIBRE;
2126 cmd->transceiver = XCVR_INTERNAL;
2127
2128 status = RTL_R32(TBICSR);
2129 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
2130 cmd->autoneg = !!(status & TBINwEnable);
2131
70739497 2132 ethtool_cmd_speed_set(cmd, SPEED_1000);
1da177e4 2133 cmd->duplex = DUPLEX_FULL; /* Always set */
ccdffb9a
FR		 2134
2135 return 0;
1da177e4
LT		 2136}
2137
ccdffb9a 2138static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 2139{
2140 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a
FR		 2141
2142 return mii_ethtool_gset(&tp->mii, cmd);
1da177e4
LT		 2143}
2144
2145static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2146{
2147 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 2148 int rc;
1da177e4 2149
da78dbff 2150 rtl_lock_work(tp);
ccdffb9a 2151 rc = tp->get_settings(dev, cmd);
da78dbff 2152 rtl_unlock_work(tp);
1da177e4 2153
ccdffb9a 2154 return rc;
1da177e4
LT		 2155}
2156
2157static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2158 void *p)
2159{
5b0384f4 2160 struct rtl8169_private *tp = netdev_priv(dev);
15edae91
PW		 2161 u32 __iomem *data = tp->mmio_addr;
2162 u32 *dw = p;
2163 int i;
1da177e4 2164
da78dbff 2165 rtl_lock_work(tp);
15edae91
PW		 2166 for (i = 0; i < R8169_REGS_SIZE; i += 4)
2167 memcpy_fromio(dw++, data++, 4);
da78dbff 2168 rtl_unlock_work(tp);
1da177e4
LT		 2169}
2170
b57b7e5a
SH		 2171static u32 rtl8169_get_msglevel(struct net_device *dev)
2172{
2173 struct rtl8169_private *tp = netdev_priv(dev);
2174
2175 return tp->msg_enable;
2176}
2177
2178static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
2179{
2180 struct rtl8169_private *tp = netdev_priv(dev);
2181
2182 tp->msg_enable = value;
2183}
2184
d4a3a0fc
SH		 2185static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
2186 "tx_packets",
2187 "rx_packets",
2188 "tx_errors",
2189 "rx_errors",
2190 "rx_missed",
2191 "align_errors",
2192 "tx_single_collisions",
2193 "tx_multi_collisions",
2194 "unicast",
2195 "broadcast",
2196 "multicast",
2197 "tx_aborted",
2198 "tx_underrun",
2199};
2200
b9f2c044 2201static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 2202{
b9f2c044
JG		 2203 switch (sset) {
2204 case ETH_SS_STATS:
2205 return ARRAY_SIZE(rtl8169_gstrings);
2206 default:
2207 return -EOPNOTSUPP;
2208 }
d4a3a0fc
SH		 2209}
2210
42020320 2211DECLARE_RTL_COND(rtl_counters_cond)
6e85d5ad 2212{
6e85d5ad 2213 void __iomem *ioaddr = tp->mmio_addr;
6e85d5ad 2214
42020320 2215 return RTL_R32(CounterAddrLow) & (CounterReset | CounterDump);
6e85d5ad
CV		 2216}
2217
42020320 2218static bool rtl8169_do_counters(struct net_device *dev, u32 counter_cmd)
6e85d5ad
CV		 2219{
2220 struct rtl8169_private *tp = netdev_priv(dev);
2221 void __iomem *ioaddr = tp->mmio_addr;
42020320
CV		 2222 dma_addr_t paddr = tp->counters_phys_addr;
2223 u32 cmd;
2224 bool ret;
6e85d5ad 2225
42020320
CV		 2226 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
2227 cmd = (u64)paddr & DMA_BIT_MASK(32);
2228 RTL_W32(CounterAddrLow, cmd);
2229 RTL_W32(CounterAddrLow, cmd | counter_cmd);
6e85d5ad 2230
42020320 2231 ret = rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
6e85d5ad 2232
42020320
CV		 2233 RTL_W32(CounterAddrLow, 0);
2234 RTL_W32(CounterAddrHigh, 0);
6e85d5ad 2235
42020320 2236 return ret;
6e85d5ad
CV		 2237}
2238
2239static bool rtl8169_reset_counters(struct net_device *dev)
2240{
2241 struct rtl8169_private *tp = netdev_priv(dev);
6e85d5ad
CV		 2242
2243 /*
2244 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
2245 * tally counters.
2246 */
2247 if (tp->mac_version < RTL_GIGA_MAC_VER_19)
2248 return true;
2249
42020320 2250 return rtl8169_do_counters(dev, CounterReset);
ffc46952
FR		 2251}
2252
6e85d5ad 2253static bool rtl8169_update_counters(struct net_device *dev)
d4a3a0fc
SH		 2254{
2255 struct rtl8169_private *tp = netdev_priv(dev);
2256 void __iomem *ioaddr = tp->mmio_addr;
d4a3a0fc 2257
355423d0
IV		 2258 /*
2259 * Some chips are unable to dump tally counters when the receiver
2260 * is disabled.
2261 */
2262 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
6e85d5ad 2263 return true;
d4a3a0fc 2264
42020320 2265 return rtl8169_do_counters(dev, CounterDump);
6e85d5ad
CV		 2266}
2267
2268static bool rtl8169_init_counter_offsets(struct net_device *dev)
2269{
2270 struct rtl8169_private *tp = netdev_priv(dev);
42020320 2271 struct rtl8169_counters *counters = tp->counters;
6e85d5ad
CV		 2272 bool ret = false;
2273
2274 /*
2275 * rtl8169_init_counter_offsets is called from rtl_open. On chip
2276 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
2277 * reset by a power cycle, while the counter values collected by the
2278 * driver are reset at every driver unload/load cycle.
2279 *
2280 * To make sure the HW values returned by @get_stats64 match the SW
2281 * values, we collect the initial values at first open(*) and use them
2282 * as offsets to normalize the values returned by @get_stats64.
2283 *
2284 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
2285 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
2286 * set at open time by rtl_hw_start.
2287 */
2288
2289 if (tp->tc_offset.inited)
2290 return true;
2291
2292 /* If both, reset and update fail, propagate to caller. */
2293 if (rtl8169_reset_counters(dev))
2294 ret = true;
2295
2296 if (rtl8169_update_counters(dev))
2297 ret = true;
2298
42020320
CV		 2299 tp->tc_offset.tx_errors = counters->tx_errors;
2300 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
2301 tp->tc_offset.tx_aborted = counters->tx_aborted;
6e85d5ad
CV		 2302 tp->tc_offset.inited = true;
2303
2304 return ret;
d4a3a0fc
SH		 2305}
2306
355423d0
IV		 2307static void rtl8169_get_ethtool_stats(struct net_device *dev,
2308 struct ethtool_stats *stats, u64 *data)
2309{
2310 struct rtl8169_private *tp = netdev_priv(dev);
e0636236 2311 struct device *d = &tp->pci_dev->dev;
42020320 2312 struct rtl8169_counters *counters = tp->counters;
355423d0
IV		 2313
2314 ASSERT_RTNL();
2315
e0636236
CHL		 2316 pm_runtime_get_noresume(d);
2317
2318 if (pm_runtime_active(d))
2319 rtl8169_update_counters(dev);
2320
2321 pm_runtime_put_noidle(d);
355423d0 2322
42020320
CV		 2323 data[0] = le64_to_cpu(counters->tx_packets);
2324 data[1] = le64_to_cpu(counters->rx_packets);
2325 data[2] = le64_to_cpu(counters->tx_errors);
2326 data[3] = le32_to_cpu(counters->rx_errors);
2327 data[4] = le16_to_cpu(counters->rx_missed);
2328 data[5] = le16_to_cpu(counters->align_errors);
2329 data[6] = le32_to_cpu(counters->tx_one_collision);
2330 data[7] = le32_to_cpu(counters->tx_multi_collision);
2331 data[8] = le64_to_cpu(counters->rx_unicast);
2332 data[9] = le64_to_cpu(counters->rx_broadcast);
2333 data[10] = le32_to_cpu(counters->rx_multicast);
2334 data[11] = le16_to_cpu(counters->tx_aborted);
2335 data[12] = le16_to_cpu(counters->tx_underun);
355423d0
IV		 2336}
2337
d4a3a0fc
SH		 2338static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2339{
2340 switch(stringset) {
2341 case ETH_SS_STATS:
2342 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
2343 break;
2344 }
2345}
2346
f0903ea3
FF		 2347static int rtl8169_nway_reset(struct net_device *dev)
2348{
2349 struct rtl8169_private *tp = netdev_priv(dev);
2350
2351 return mii_nway_restart(&tp->mii);
2352}
2353
7282d491 2354static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 2355 .get_drvinfo = rtl8169_get_drvinfo,
2356 .get_regs_len = rtl8169_get_regs_len,
2357 .get_link = ethtool_op_get_link,
2358 .get_settings = rtl8169_get_settings,
2359 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 2360 .get_msglevel = rtl8169_get_msglevel,
2361 .set_msglevel = rtl8169_set_msglevel,
1da177e4 2362 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 2363 .get_wol = rtl8169_get_wol,
2364 .set_wol = rtl8169_set_wol,
d4a3a0fc 2365 .get_strings = rtl8169_get_strings,
b9f2c044 2366 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 2367 .get_ethtool_stats = rtl8169_get_ethtool_stats,
e1593bb1 2368 .get_ts_info = ethtool_op_get_ts_info,
f0903ea3 2369 .nway_reset = rtl8169_nway_reset,
1da177e4
LT		 2370};
2371
07d3f51f 2372static void rtl8169_get_mac_version(struct rtl8169_private *tp,
5d320a20 2373 struct net_device *dev, u8 default_version)
1da177e4 2374{
5d320a20 2375 void __iomem *ioaddr = tp->mmio_addr;
0e485150
FR		 2376 /*
2377 * The driver currently handles the 8168Bf and the 8168Be identically
2378 * but they can be identified more specifically through the test below
2379 * if needed:
2380 *
2381 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 2382 *
2383 * Same thing for the 8101Eb and the 8101Ec:
2384 *
2385 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 2386 */
3744100e 2387 static const struct rtl_mac_info {
1da177e4 2388 u32 mask;
e3cf0cc0 2389 u32 val;
1da177e4
LT		 2390 int mac_version;
2391 } mac_info[] = {
935e2218
CHL		 2392 /* 8168EP family. */
2393 { 0x7cf00000, 0x50200000, RTL_GIGA_MAC_VER_51 },
2394 { 0x7cf00000, 0x50100000, RTL_GIGA_MAC_VER_50 },
2395 { 0x7cf00000, 0x50000000, RTL_GIGA_MAC_VER_49 },
2396
6e1d0b89
CHL		 2397 /* 8168H family. */
2398 { 0x7cf00000, 0x54100000, RTL_GIGA_MAC_VER_46 },
2399 { 0x7cf00000, 0x54000000, RTL_GIGA_MAC_VER_45 },
2400
c558386b 2401 /* 8168G family. */
45dd95c4 2402 { 0x7cf00000, 0x5c800000, RTL_GIGA_MAC_VER_44 },
57538c4a 2403 { 0x7cf00000, 0x50900000, RTL_GIGA_MAC_VER_42 },
c558386b
HW		 2404 { 0x7cf00000, 0x4c100000, RTL_GIGA_MAC_VER_41 },
2405 { 0x7cf00000, 0x4c000000, RTL_GIGA_MAC_VER_40 },
2406
c2218925 2407 /* 8168F family. */
b3d7b2f2 2408 { 0x7c800000, 0x48800000, RTL_GIGA_MAC_VER_38 },
c2218925
HW		 2409 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
2410 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
2411
01dc7fec 2412 /* 8168E family. */
70090424 2413 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
01dc7fec 2414 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
2415 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
2416 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
2417
5b538df9 2418 /* 8168D family. */
daf9df6d 2419 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
2420 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
daf9df6d 2421 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
5b538df9 2422
e6de30d6 2423 /* 8168DP family. */
2424 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
2425 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
4804b3b3 2426 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
e6de30d6 2427
ef808d50 2428 /* 8168C family. */
17c99297 2429 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
ef3386f0 2430 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 2431 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 2432 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 2433 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
2434 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 2435 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
6fb07058 2436 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
ef808d50 2437 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 2438
2439 /* 8168B family. */
2440 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
2441 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
2442 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
2443 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
2444
2445 /* 8101 family. */
5598bfe5
HW		 2446 { 0x7cf00000, 0x44900000, RTL_GIGA_MAC_VER_39 },
2447 { 0x7c800000, 0x44800000, RTL_GIGA_MAC_VER_39 },
7e18dca1 2448 { 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37 },
36a0e6c2 2449 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
5a5e4443
HW		 2450 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
2451 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
2452 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2857ffb7
FR		 2453 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
2454 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
2455 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
2456 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
2457 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
2458 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 2459 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 2460 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 2461 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 2462 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
2463 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 2464 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
2465 /* FIXME: where did these entries come from ? -- FR */
2466 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
2467 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
2468
2469 /* 8110 family. */
2470 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
2471 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
2472 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
2473 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
2474 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
2475 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
2476
f21b75e9
JD		 2477 /* Catch-all */
2478 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
3744100e
FR		 2479 };
2480 const struct rtl_mac_info *p = mac_info;
1da177e4
LT		 2481 u32 reg;
2482
e3cf0cc0
FR		 2483 reg = RTL_R32(TxConfig);
2484 while ((reg & p->mask) != p->val)
1da177e4
LT		 2485 p++;
2486 tp->mac_version = p->mac_version;
5d320a20
FR		 2487
2488 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2489 netif_notice(tp, probe, dev,
2490 "unknown MAC, using family default\n");
2491 tp->mac_version = default_version;
58152cd4 2492 } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
2493 tp->mac_version = tp->mii.supports_gmii ?
2494 RTL_GIGA_MAC_VER_42 :
2495 RTL_GIGA_MAC_VER_43;
6e1d0b89
CHL		 2496 } else if (tp->mac_version == RTL_GIGA_MAC_VER_45) {
2497 tp->mac_version = tp->mii.supports_gmii ?
2498 RTL_GIGA_MAC_VER_45 :
2499 RTL_GIGA_MAC_VER_47;
2500 } else if (tp->mac_version == RTL_GIGA_MAC_VER_46) {
2501 tp->mac_version = tp->mii.supports_gmii ?
2502 RTL_GIGA_MAC_VER_46 :
2503 RTL_GIGA_MAC_VER_48;
5d320a20 2504 }
1da177e4
LT		 2505}
2506
2507static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2508{
bcf0bf90 2509 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 2510}
2511
867763c1
FR		 2512struct phy_reg {
2513 u16 reg;
2514 u16 val;
2515};
2516
4da19633 2517static void rtl_writephy_batch(struct rtl8169_private *tp,
2518 const struct phy_reg *regs, int len)
867763c1
FR		 2519{
2520 while (len-- > 0) {
4da19633 2521 rtl_writephy(tp, regs->reg, regs->val);
867763c1
FR		 2522 regs++;
2523 }
2524}
2525
bca03d5f 2526#define PHY_READ 0x00000000
2527#define PHY_DATA_OR 0x10000000
2528#define PHY_DATA_AND 0x20000000
2529#define PHY_BJMPN 0x30000000
eee3786f 2530#define PHY_MDIO_CHG 0x40000000
bca03d5f 2531#define PHY_CLEAR_READCOUNT 0x70000000
2532#define PHY_WRITE 0x80000000
2533#define PHY_READCOUNT_EQ_SKIP 0x90000000
2534#define PHY_COMP_EQ_SKIPN 0xa0000000
2535#define PHY_COMP_NEQ_SKIPN 0xb0000000
2536#define PHY_WRITE_PREVIOUS 0xc0000000
2537#define PHY_SKIPN 0xd0000000
2538#define PHY_DELAY_MS 0xe0000000
bca03d5f 2539
960aee6c
HW		 2540struct fw_info {
2541 u32 magic;
2542 char version[RTL_VER_SIZE];
2543 __le32 fw_start;
2544 __le32 fw_len;
2545 u8 chksum;
2546} __packed;
2547
1c361efb
FR		 2548#define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2549
2550static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
bca03d5f 2551{
b6ffd97f 2552 const struct firmware *fw = rtl_fw->fw;
960aee6c 2553 struct fw_info *fw_info = (struct fw_info *)fw->data;
1c361efb
FR		 2554 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2555 char *version = rtl_fw->version;
2556 bool rc = false;
2557
2558 if (fw->size < FW_OPCODE_SIZE)
2559 goto out;
960aee6c
HW		 2560
2561 if (!fw_info->magic) {
2562 size_t i, size, start;
2563 u8 checksum = 0;
2564
2565 if (fw->size < sizeof(*fw_info))
2566 goto out;
2567
2568 for (i = 0; i < fw->size; i++)
2569 checksum += fw->data[i];
2570 if (checksum != 0)
2571 goto out;
2572
2573 start = le32_to_cpu(fw_info->fw_start);
2574 if (start > fw->size)
2575 goto out;
2576
2577 size = le32_to_cpu(fw_info->fw_len);
2578 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2579 goto out;
2580
2581 memcpy(version, fw_info->version, RTL_VER_SIZE);
2582
2583 pa->code = (__le32 *)(fw->data + start);
2584 pa->size = size;
2585 } else {
1c361efb
FR		 2586 if (fw->size % FW_OPCODE_SIZE)
2587 goto out;
2588
2589 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2590
2591 pa->code = (__le32 *)fw->data;
2592 pa->size = fw->size / FW_OPCODE_SIZE;
2593 }
2594 version[RTL_VER_SIZE - 1] = 0;
2595
2596 rc = true;
2597out:
2598 return rc;
2599}
2600
fd112f2e
FR		 2601static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2602 struct rtl_fw_phy_action *pa)
1c361efb 2603{
fd112f2e 2604 bool rc = false;
1c361efb 2605 size_t index;
bca03d5f 2606
1c361efb
FR		 2607 for (index = 0; index < pa->size; index++) {
2608 u32 action = le32_to_cpu(pa->code[index]);
42b82dc1 2609 u32 regno = (action & 0x0fff0000) >> 16;
bca03d5f 2610
42b82dc1 2611 switch(action & 0xf0000000) {
2612 case PHY_READ:
2613 case PHY_DATA_OR:
2614 case PHY_DATA_AND:
eee3786f 2615 case PHY_MDIO_CHG:
42b82dc1 2616 case PHY_CLEAR_READCOUNT:
2617 case PHY_WRITE:
2618 case PHY_WRITE_PREVIOUS:
2619 case PHY_DELAY_MS:
2620 break;
2621
2622 case PHY_BJMPN:
2623 if (regno > index) {
fd112f2e 2624 netif_err(tp, ifup, tp->dev,
cecb5fd7 2625 "Out of range of firmware\n");
fd112f2e 2626 goto out;
42b82dc1 2627 }
2628 break;
2629 case PHY_READCOUNT_EQ_SKIP:
1c361efb 2630 if (index + 2 >= pa->size) {
fd112f2e 2631 netif_err(tp, ifup, tp->dev,
cecb5fd7 2632 "Out of range of firmware\n");
fd112f2e 2633 goto out;
42b82dc1 2634 }
2635 break;
2636 case PHY_COMP_EQ_SKIPN:
2637 case PHY_COMP_NEQ_SKIPN:
2638 case PHY_SKIPN:
1c361efb 2639 if (index + 1 + regno >= pa->size) {
fd112f2e 2640 netif_err(tp, ifup, tp->dev,
cecb5fd7 2641 "Out of range of firmware\n");
fd112f2e 2642 goto out;
42b82dc1 2643 }
bca03d5f 2644 break;
2645
42b82dc1 2646 default:
fd112f2e 2647 netif_err(tp, ifup, tp->dev,
42b82dc1 2648 "Invalid action 0x%08x\n", action);
fd112f2e 2649 goto out;
bca03d5f 2650 }
2651 }
fd112f2e
FR		 2652 rc = true;
2653out:
2654 return rc;
2655}
bca03d5f 2656
fd112f2e
FR		 2657static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2658{
2659 struct net_device *dev = tp->dev;
2660 int rc = -EINVAL;
2661
2662 if (!rtl_fw_format_ok(tp, rtl_fw)) {
5c2d2b14 2663 netif_err(tp, ifup, dev, "invalid firmware\n");
fd112f2e
FR		 2664 goto out;
2665 }
2666
2667 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2668 rc = 0;
2669out:
2670 return rc;
2671}
2672
2673static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2674{
2675 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
eee3786f 2676 struct mdio_ops org, *ops = &tp->mdio_ops;
fd112f2e
FR		 2677 u32 predata, count;
2678 size_t index;
2679
2680 predata = count = 0;
eee3786f 2681 org.write = ops->write;
2682 org.read = ops->read;
42b82dc1 2683
1c361efb
FR		 2684 for (index = 0; index < pa->size; ) {
2685 u32 action = le32_to_cpu(pa->code[index]);
bca03d5f 2686 u32 data = action & 0x0000ffff;
42b82dc1 2687 u32 regno = (action & 0x0fff0000) >> 16;
2688
2689 if (!action)
2690 break;
bca03d5f 2691
2692 switch(action & 0xf0000000) {
42b82dc1 2693 case PHY_READ:
2694 predata = rtl_readphy(tp, regno);
2695 count++;
2696 index++;
2697 break;
2698 case PHY_DATA_OR:
2699 predata |= data;
2700 index++;
2701 break;
2702 case PHY_DATA_AND:
2703 predata &= data;
2704 index++;
2705 break;
2706 case PHY_BJMPN:
2707 index -= regno;
2708 break;
eee3786f 2709 case PHY_MDIO_CHG:
2710 if (data == 0) {
2711 ops->write = org.write;
2712 ops->read = org.read;
2713 } else if (data == 1) {
2714 ops->write = mac_mcu_write;
2715 ops->read = mac_mcu_read;
2716 }
2717
42b82dc1 2718 index++;
2719 break;
2720 case PHY_CLEAR_READCOUNT:
2721 count = 0;
2722 index++;
2723 break;
bca03d5f 2724 case PHY_WRITE:
42b82dc1 2725 rtl_writephy(tp, regno, data);
2726 index++;
2727 break;
2728 case PHY_READCOUNT_EQ_SKIP:
cecb5fd7 2729 index += (count == data) ? 2 : 1;
bca03d5f 2730 break;
42b82dc1 2731 case PHY_COMP_EQ_SKIPN:
2732 if (predata == data)
2733 index += regno;
2734 index++;
2735 break;
2736 case PHY_COMP_NEQ_SKIPN:
2737 if (predata != data)
2738 index += regno;
2739 index++;
2740 break;
2741 case PHY_WRITE_PREVIOUS:
2742 rtl_writephy(tp, regno, predata);
2743 index++;
2744 break;
2745 case PHY_SKIPN:
2746 index += regno + 1;
2747 break;
2748 case PHY_DELAY_MS:
2749 mdelay(data);
2750 index++;
2751 break;
2752
bca03d5f 2753 default:
2754 BUG();
2755 }
2756 }
eee3786f 2757
2758 ops->write = org.write;
2759 ops->read = org.read;
bca03d5f 2760}
2761
f1e02ed1 2762static void rtl_release_firmware(struct rtl8169_private *tp)
2763{
b6ffd97f
FR		 2764 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2765 release_firmware(tp->rtl_fw->fw);
2766 kfree(tp->rtl_fw);
2767 }
2768 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
f1e02ed1 2769}
2770
953a12cc 2771static void rtl_apply_firmware(struct rtl8169_private *tp)
f1e02ed1 2772{
b6ffd97f 2773 struct rtl_fw *rtl_fw = tp->rtl_fw;
f1e02ed1 2774
2775 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
eef63cc1 2776 if (!IS_ERR_OR_NULL(rtl_fw))
b6ffd97f 2777 rtl_phy_write_fw(tp, rtl_fw);
953a12cc
FR		 2778}
2779
2780static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2781{
2782 if (rtl_readphy(tp, reg) != val)
2783 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2784 else
2785 rtl_apply_firmware(tp);
f1e02ed1 2786}
2787
4da19633 2788static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1da177e4 2789{
350f7596 2790 static const struct phy_reg phy_reg_init[] = {
0b9b571d 2791 { 0x1f, 0x0001 },
2792 { 0x06, 0x006e },
2793 { 0x08, 0x0708 },
2794 { 0x15, 0x4000 },
2795 { 0x18, 0x65c7 },
1da177e4 2796
0b9b571d 2797 { 0x1f, 0x0001 },
2798 { 0x03, 0x00a1 },
2799 { 0x02, 0x0008 },
2800 { 0x01, 0x0120 },
2801 { 0x00, 0x1000 },
2802 { 0x04, 0x0800 },
2803 { 0x04, 0x0000 },
1da177e4 2804
0b9b571d 2805 { 0x03, 0xff41 },
2806 { 0x02, 0xdf60 },
2807 { 0x01, 0x0140 },
2808 { 0x00, 0x0077 },
2809 { 0x04, 0x7800 },
2810 { 0x04, 0x7000 },
2811
2812 { 0x03, 0x802f },
2813 { 0x02, 0x4f02 },
2814 { 0x01, 0x0409 },
2815 { 0x00, 0xf0f9 },
2816 { 0x04, 0x9800 },
2817 { 0x04, 0x9000 },
2818
2819 { 0x03, 0xdf01 },
2820 { 0x02, 0xdf20 },
2821 { 0x01, 0xff95 },
2822 { 0x00, 0xba00 },
2823 { 0x04, 0xa800 },
2824 { 0x04, 0xa000 },
2825
2826 { 0x03, 0xff41 },
2827 { 0x02, 0xdf20 },
2828 { 0x01, 0x0140 },
2829 { 0x00, 0x00bb },
2830 { 0x04, 0xb800 },
2831 { 0x04, 0xb000 },
2832
2833 { 0x03, 0xdf41 },
2834 { 0x02, 0xdc60 },
2835 { 0x01, 0x6340 },
2836 { 0x00, 0x007d },
2837 { 0x04, 0xd800 },
2838 { 0x04, 0xd000 },
2839
2840 { 0x03, 0xdf01 },
2841 { 0x02, 0xdf20 },
2842 { 0x01, 0x100a },
2843 { 0x00, 0xa0ff },
2844 { 0x04, 0xf800 },
2845 { 0x04, 0xf000 },
2846
2847 { 0x1f, 0x0000 },
2848 { 0x0b, 0x0000 },
2849 { 0x00, 0x9200 }
2850 };
1da177e4 2851
4da19633 2852 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1da177e4
LT		 2853}
2854
4da19633 2855static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
5615d9f1 2856{
350f7596 2857 static const struct phy_reg phy_reg_init[] = {
a441d7b6
FR		 2858 { 0x1f, 0x0002 },
2859 { 0x01, 0x90d0 },
2860 { 0x1f, 0x0000 }
2861 };
2862
4da19633 2863 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 2864}
2865
4da19633 2866static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2e955856 2867{
2868 struct pci_dev *pdev = tp->pci_dev;
2e955856 2869
ccbae55e
SS		 2870 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2871 (pdev->subsystem_device != 0xe000))
2e955856 2872 return;
2873
4da19633 2874 rtl_writephy(tp, 0x1f, 0x0001);
2875 rtl_writephy(tp, 0x10, 0xf01b);
2876 rtl_writephy(tp, 0x1f, 0x0000);
2e955856 2877}
2878
4da19633 2879static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2e955856 2880{
350f7596 2881 static const struct phy_reg phy_reg_init[] = {
2e955856 2882 { 0x1f, 0x0001 },
2883 { 0x04, 0x0000 },
2884 { 0x03, 0x00a1 },
2885 { 0x02, 0x0008 },
2886 { 0x01, 0x0120 },
2887 { 0x00, 0x1000 },
2888 { 0x04, 0x0800 },
2889 { 0x04, 0x9000 },
2890 { 0x03, 0x802f },
2891 { 0x02, 0x4f02 },
2892 { 0x01, 0x0409 },
2893 { 0x00, 0xf099 },
2894 { 0x04, 0x9800 },
2895 { 0x04, 0xa000 },
2896 { 0x03, 0xdf01 },
2897 { 0x02, 0xdf20 },
2898 { 0x01, 0xff95 },
2899 { 0x00, 0xba00 },
2900 { 0x04, 0xa800 },
2901 { 0x04, 0xf000 },
2902 { 0x03, 0xdf01 },
2903 { 0x02, 0xdf20 },
2904 { 0x01, 0x101a },
2905 { 0x00, 0xa0ff },
2906 { 0x04, 0xf800 },
2907 { 0x04, 0x0000 },
2908 { 0x1f, 0x0000 },
2909
2910 { 0x1f, 0x0001 },
2911 { 0x10, 0xf41b },
2912 { 0x14, 0xfb54 },
2913 { 0x18, 0xf5c7 },
2914 { 0x1f, 0x0000 },
2915
2916 { 0x1f, 0x0001 },
2917 { 0x17, 0x0cc0 },
2918 { 0x1f, 0x0000 }
2919 };
2920
4da19633 2921 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2e955856 2922
4da19633 2923 rtl8169scd_hw_phy_config_quirk(tp);
2e955856 2924}
2925
4da19633 2926static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
8c7006aa 2927{
350f7596 2928 static const struct phy_reg phy_reg_init[] = {
8c7006aa 2929 { 0x1f, 0x0001 },
2930 { 0x04, 0x0000 },
2931 { 0x03, 0x00a1 },
2932 { 0x02, 0x0008 },
2933 { 0x01, 0x0120 },
2934 { 0x00, 0x1000 },
2935 { 0x04, 0x0800 },
2936 { 0x04, 0x9000 },
2937 { 0x03, 0x802f },
2938 { 0x02, 0x4f02 },
2939 { 0x01, 0x0409 },
2940 { 0x00, 0xf099 },
2941 { 0x04, 0x9800 },
2942 { 0x04, 0xa000 },
2943 { 0x03, 0xdf01 },
2944 { 0x02, 0xdf20 },
2945 { 0x01, 0xff95 },
2946 { 0x00, 0xba00 },
2947 { 0x04, 0xa800 },
2948 { 0x04, 0xf000 },
2949 { 0x03, 0xdf01 },
2950 { 0x02, 0xdf20 },
2951 { 0x01, 0x101a },
2952 { 0x00, 0xa0ff },
2953 { 0x04, 0xf800 },
2954 { 0x04, 0x0000 },
2955 { 0x1f, 0x0000 },
2956
2957 { 0x1f, 0x0001 },
2958 { 0x0b, 0x8480 },
2959 { 0x1f, 0x0000 },
2960
2961 { 0x1f, 0x0001 },
2962 { 0x18, 0x67c7 },
2963 { 0x04, 0x2000 },
2964 { 0x03, 0x002f },
2965 { 0x02, 0x4360 },
2966 { 0x01, 0x0109 },
2967 { 0x00, 0x3022 },
2968 { 0x04, 0x2800 },
2969 { 0x1f, 0x0000 },
2970
2971 { 0x1f, 0x0001 },
2972 { 0x17, 0x0cc0 },
2973 { 0x1f, 0x0000 }
2974 };
2975
4da19633 2976 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
8c7006aa 2977}
2978
4da19633 2979static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
236b8082 2980{
350f7596 2981 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2982 { 0x10, 0xf41b },
2983 { 0x1f, 0x0000 }
2984 };
2985
4da19633 2986 rtl_writephy(tp, 0x1f, 0x0001);
2987 rtl_patchphy(tp, 0x16, 1 << 0);
236b8082 2988
4da19633 2989 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2990}
2991
4da19633 2992static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
236b8082 2993{
350f7596 2994 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2995 { 0x1f, 0x0001 },
2996 { 0x10, 0xf41b },
2997 { 0x1f, 0x0000 }
2998 };
2999
4da19633 3000 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 3001}
3002
4da19633 3003static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 3004{
350f7596 3005 static const struct phy_reg phy_reg_init[] = {
867763c1
FR		 3006 { 0x1f, 0x0000 },
3007 { 0x1d, 0x0f00 },
3008 { 0x1f, 0x0002 },
3009 { 0x0c, 0x1ec8 },
3010 { 0x1f, 0x0000 }
3011 };
3012
4da19633 3013 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
867763c1
FR		 3014}
3015
4da19633 3016static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
ef3386f0 3017{
350f7596 3018 static const struct phy_reg phy_reg_init[] = {
ef3386f0
FR		 3019 { 0x1f, 0x0001 },
3020 { 0x1d, 0x3d98 },
3021 { 0x1f, 0x0000 }
3022 };
3023
4da19633 3024 rtl_writephy(tp, 0x1f, 0x0000);
3025 rtl_patchphy(tp, 0x14, 1 << 5);
3026 rtl_patchphy(tp, 0x0d, 1 << 5);
ef3386f0 3027
4da19633 3028 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
ef3386f0
FR		 3029}
3030
4da19633 3031static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 3032{
350f7596 3033 static const struct phy_reg phy_reg_init[] = {
a3f80671
FR		 3034 { 0x1f, 0x0001 },
3035 { 0x12, 0x2300 },
867763c1
FR		 3036 { 0x1f, 0x0002 },
3037 { 0x00, 0x88d4 },
3038 { 0x01, 0x82b1 },
3039 { 0x03, 0x7002 },
3040 { 0x08, 0x9e30 },
3041 { 0x09, 0x01f0 },
3042 { 0x0a, 0x5500 },
3043 { 0x0c, 0x00c8 },
3044 { 0x1f, 0x0003 },
3045 { 0x12, 0xc096 },
3046 { 0x16, 0x000a },
f50d4275
FR		 3047 { 0x1f, 0x0000 },
3048 { 0x1f, 0x0000 },
3049 { 0x09, 0x2000 },
3050 { 0x09, 0x0000 }
867763c1
FR		 3051 };
3052
4da19633 3053 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 3054
4da19633 3055 rtl_patchphy(tp, 0x14, 1 << 5);
3056 rtl_patchphy(tp, 0x0d, 1 << 5);
3057 rtl_writephy(tp, 0x1f, 0x0000);
867763c1
FR		 3058}
3059
4da19633 3060static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
7da97ec9 3061{
350f7596 3062 static const struct phy_reg phy_reg_init[] = {
f50d4275 3063 { 0x1f, 0x0001 },
7da97ec9 3064 { 0x12, 0x2300 },
f50d4275
FR		 3065 { 0x03, 0x802f },
3066 { 0x02, 0x4f02 },
3067 { 0x01, 0x0409 },
3068 { 0x00, 0xf099 },
3069 { 0x04, 0x9800 },
3070 { 0x04, 0x9000 },
3071 { 0x1d, 0x3d98 },
7da97ec9
FR		 3072 { 0x1f, 0x0002 },
3073 { 0x0c, 0x7eb8 },
f50d4275
FR		 3074 { 0x06, 0x0761 },
3075 { 0x1f, 0x0003 },
3076 { 0x16, 0x0f0a },
7da97ec9
FR		 3077 { 0x1f, 0x0000 }
3078 };
3079
4da19633 3080 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 3081
4da19633 3082 rtl_patchphy(tp, 0x16, 1 << 0);
3083 rtl_patchphy(tp, 0x14, 1 << 5);
3084 rtl_patchphy(tp, 0x0d, 1 << 5);
3085 rtl_writephy(tp, 0x1f, 0x0000);
7da97ec9
FR		 3086}
3087
4da19633 3088static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
197ff761 3089{
350f7596 3090 static const struct phy_reg phy_reg_init[] = {
197ff761
FR		 3091 { 0x1f, 0x0001 },
3092 { 0x12, 0x2300 },
3093 { 0x1d, 0x3d98 },
3094 { 0x1f, 0x0002 },
3095 { 0x0c, 0x7eb8 },
3096 { 0x06, 0x5461 },
3097 { 0x1f, 0x0003 },
3098 { 0x16, 0x0f0a },
3099 { 0x1f, 0x0000 }
3100 };
3101
4da19633 3102 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
197ff761 3103
4da19633 3104 rtl_patchphy(tp, 0x16, 1 << 0);
3105 rtl_patchphy(tp, 0x14, 1 << 5);
3106 rtl_patchphy(tp, 0x0d, 1 << 5);
3107 rtl_writephy(tp, 0x1f, 0x0000);
197ff761
FR		 3108}
3109
4da19633 3110static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
6fb07058 3111{
4da19633 3112 rtl8168c_3_hw_phy_config(tp);
6fb07058
FR		 3113}
3114
bca03d5f 3115static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
5b538df9 3116{
350f7596 3117 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 3118 /* Channel Estimation */
5b538df9 3119 { 0x1f, 0x0001 },
daf9df6d 3120 { 0x06, 0x4064 },
3121 { 0x07, 0x2863 },
3122 { 0x08, 0x059c },
3123 { 0x09, 0x26b4 },
3124 { 0x0a, 0x6a19 },
3125 { 0x0b, 0xdcc8 },
3126 { 0x10, 0xf06d },
3127 { 0x14, 0x7f68 },
3128 { 0x18, 0x7fd9 },
3129 { 0x1c, 0xf0ff },
3130 { 0x1d, 0x3d9c },
5b538df9 3131 { 0x1f, 0x0003 },
daf9df6d 3132 { 0x12, 0xf49f },
3133 { 0x13, 0x070b },
3134 { 0x1a, 0x05ad },
bca03d5f 3135 { 0x14, 0x94c0 },
3136
3137 /*
3138 * Tx Error Issue
cecb5fd7 3139 * Enhance line driver power
bca03d5f 3140 */
5b538df9 3141 { 0x1f, 0x0002 },
daf9df6d 3142 { 0x06, 0x5561 },
3143 { 0x1f, 0x0005 },
3144 { 0x05, 0x8332 },
bca03d5f 3145 { 0x06, 0x5561 },
3146
3147 /*
3148 * Can not link to 1Gbps with bad cable
3149 * Decrease SNR threshold form 21.07dB to 19.04dB
3150 */
3151 { 0x1f, 0x0001 },
3152 { 0x17, 0x0cc0 },
daf9df6d 3153
5b538df9 3154 { 0x1f, 0x0000 },
bca03d5f 3155 { 0x0d, 0xf880 }
daf9df6d 3156 };
3157
4da19633 3158 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
daf9df6d 3159
bca03d5f 3160 /*
3161 * Rx Error Issue
3162 * Fine Tune Switching regulator parameter
3163 */
4da19633 3164 rtl_writephy(tp, 0x1f, 0x0002);
76564428
CHL		 3165 rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
3166 rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
daf9df6d 3167
fdf6fc06 3168 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
350f7596 3169 static const struct phy_reg phy_reg_init[] = {
daf9df6d 3170 { 0x1f, 0x0002 },
3171 { 0x05, 0x669a },
3172 { 0x1f, 0x0005 },
3173 { 0x05, 0x8330 },
3174 { 0x06, 0x669a },
3175 { 0x1f, 0x0002 }
3176 };
3177 int val;
3178
4da19633 3179 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 3180
4da19633 3181 val = rtl_readphy(tp, 0x0d);
daf9df6d 3182
3183 if ((val & 0x00ff) != 0x006c) {
350f7596 3184 static const u32 set[] = {
daf9df6d 3185 0x0065, 0x0066, 0x0067, 0x0068,
3186 0x0069, 0x006a, 0x006b, 0x006c
3187 };
3188 int i;
3189
4da19633 3190 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 3191
3192 val &= 0xff00;
3193 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 3194 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 3195 }
3196 } else {
350f7596 3197 static const struct phy_reg phy_reg_init[] = {
daf9df6d 3198 { 0x1f, 0x0002 },
3199 { 0x05, 0x6662 },
3200 { 0x1f, 0x0005 },
3201 { 0x05, 0x8330 },
3202 { 0x06, 0x6662 }
3203 };
3204
4da19633 3205 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 3206 }
3207
bca03d5f 3208 /* RSET couple improve */
4da19633 3209 rtl_writephy(tp, 0x1f, 0x0002);
3210 rtl_patchphy(tp, 0x0d, 0x0300);
3211 rtl_patchphy(tp, 0x0f, 0x0010);
daf9df6d 3212
bca03d5f 3213 /* Fine tune PLL performance */
4da19633 3214 rtl_writephy(tp, 0x1f, 0x0002);
76564428
CHL		 3215 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3216 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 3217
4da19633 3218 rtl_writephy(tp, 0x1f, 0x0005);
3219 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 3220
3221 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
bca03d5f 3222
4da19633 3223 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 3224}
3225
bca03d5f 3226static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 3227{
350f7596 3228 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 3229 /* Channel Estimation */
daf9df6d 3230 { 0x1f, 0x0001 },
3231 { 0x06, 0x4064 },
3232 { 0x07, 0x2863 },
3233 { 0x08, 0x059c },
3234 { 0x09, 0x26b4 },
3235 { 0x0a, 0x6a19 },
3236 { 0x0b, 0xdcc8 },
3237 { 0x10, 0xf06d },
3238 { 0x14, 0x7f68 },
3239 { 0x18, 0x7fd9 },
3240 { 0x1c, 0xf0ff },
3241 { 0x1d, 0x3d9c },
3242 { 0x1f, 0x0003 },
3243 { 0x12, 0xf49f },
3244 { 0x13, 0x070b },
3245 { 0x1a, 0x05ad },
3246 { 0x14, 0x94c0 },
3247
bca03d5f 3248 /*
3249 * Tx Error Issue
cecb5fd7 3250 * Enhance line driver power
bca03d5f 3251 */
daf9df6d 3252 { 0x1f, 0x0002 },
3253 { 0x06, 0x5561 },
3254 { 0x1f, 0x0005 },
3255 { 0x05, 0x8332 },
bca03d5f 3256 { 0x06, 0x5561 },
3257
3258 /*
3259 * Can not link to 1Gbps with bad cable
3260 * Decrease SNR threshold form 21.07dB to 19.04dB
3261 */
3262 { 0x1f, 0x0001 },
3263 { 0x17, 0x0cc0 },
daf9df6d 3264
3265 { 0x1f, 0x0000 },
bca03d5f 3266 { 0x0d, 0xf880 }
5b538df9
FR		 3267 };
3268
4da19633 3269 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
5b538df9 3270
fdf6fc06 3271 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
350f7596 3272 static const struct phy_reg phy_reg_init[] = {
daf9df6d 3273 { 0x1f, 0x0002 },
3274 { 0x05, 0x669a },
5b538df9 3275 { 0x1f, 0x0005 },
daf9df6d 3276 { 0x05, 0x8330 },
3277 { 0x06, 0x669a },
3278
3279 { 0x1f, 0x0002 }
3280 };
3281 int val;
3282
4da19633 3283 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 3284
4da19633 3285 val = rtl_readphy(tp, 0x0d);
daf9df6d 3286 if ((val & 0x00ff) != 0x006c) {
b6bc7650 3287 static const u32 set[] = {
daf9df6d 3288 0x0065, 0x0066, 0x0067, 0x0068,
3289 0x0069, 0x006a, 0x006b, 0x006c
3290 };
3291 int i;
3292
4da19633 3293 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 3294
3295 val &= 0xff00;
3296 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 3297 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 3298 }
3299 } else {
350f7596 3300 static const struct phy_reg phy_reg_init[] = {
daf9df6d 3301 { 0x1f, 0x0002 },
3302 { 0x05, 0x2642 },
5b538df9 3303 { 0x1f, 0x0005 },
daf9df6d 3304 { 0x05, 0x8330 },
3305 { 0x06, 0x2642 }
5b538df9
FR		 3306 };
3307
4da19633 3308 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 3309 }
3310
bca03d5f 3311 /* Fine tune PLL performance */
4da19633 3312 rtl_writephy(tp, 0x1f, 0x0002);
76564428
CHL		 3313 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3314 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 3315
bca03d5f 3316 /* Switching regulator Slew rate */
4da19633 3317 rtl_writephy(tp, 0x1f, 0x0002);
3318 rtl_patchphy(tp, 0x0f, 0x0017);
daf9df6d 3319
4da19633 3320 rtl_writephy(tp, 0x1f, 0x0005);
3321 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 3322
3323 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
bca03d5f 3324
4da19633 3325 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 3326}
3327
4da19633 3328static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 3329{
350f7596 3330 static const struct phy_reg phy_reg_init[] = {
daf9df6d 3331 { 0x1f, 0x0002 },
3332 { 0x10, 0x0008 },
3333 { 0x0d, 0x006c },
3334
3335 { 0x1f, 0x0000 },
3336 { 0x0d, 0xf880 },
3337
3338 { 0x1f, 0x0001 },
3339 { 0x17, 0x0cc0 },
3340
3341 { 0x1f, 0x0001 },
3342 { 0x0b, 0xa4d8 },
3343 { 0x09, 0x281c },
3344 { 0x07, 0x2883 },
3345 { 0x0a, 0x6b35 },
3346 { 0x1d, 0x3da4 },
3347 { 0x1c, 0xeffd },
3348 { 0x14, 0x7f52 },
3349 { 0x18, 0x7fc6 },
3350 { 0x08, 0x0601 },
3351 { 0x06, 0x4063 },
3352 { 0x10, 0xf074 },
3353 { 0x1f, 0x0003 },
3354 { 0x13, 0x0789 },
3355 { 0x12, 0xf4bd },
3356 { 0x1a, 0x04fd },
3357 { 0x14, 0x84b0 },
3358 { 0x1f, 0x0000 },
3359 { 0x00, 0x9200 },
3360
3361 { 0x1f, 0x0005 },
3362 { 0x01, 0x0340 },
3363 { 0x1f, 0x0001 },
3364 { 0x04, 0x4000 },
3365 { 0x03, 0x1d21 },
3366 { 0x02, 0x0c32 },
3367 { 0x01, 0x0200 },
3368 { 0x00, 0x5554 },
3369 { 0x04, 0x4800 },
3370 { 0x04, 0x4000 },
3371 { 0x04, 0xf000 },
3372 { 0x03, 0xdf01 },
3373 { 0x02, 0xdf20 },
3374 { 0x01, 0x101a },
3375 { 0x00, 0xa0ff },
3376 { 0x04, 0xf800 },
3377 { 0x04, 0xf000 },
3378 { 0x1f, 0x0000 },
3379
3380 { 0x1f, 0x0007 },
3381 { 0x1e, 0x0023 },
3382 { 0x16, 0x0000 },
3383 { 0x1f, 0x0000 }
3384 };
3385
4da19633 3386 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 3387}
3388
e6de30d6 3389static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3390{
3391 static const struct phy_reg phy_reg_init[] = {
3392 { 0x1f, 0x0001 },
3393 { 0x17, 0x0cc0 },
3394
3395 { 0x1f, 0x0007 },
3396 { 0x1e, 0x002d },
3397 { 0x18, 0x0040 },
3398 { 0x1f, 0x0000 }
3399 };
3400
3401 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3402 rtl_patchphy(tp, 0x0d, 1 << 5);
3403}
3404
70090424 3405static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
01dc7fec 3406{
3407 static const struct phy_reg phy_reg_init[] = {
3408 /* Enable Delay cap */
3409 { 0x1f, 0x0005 },
3410 { 0x05, 0x8b80 },
3411 { 0x06, 0xc896 },
3412 { 0x1f, 0x0000 },
3413
3414 /* Channel estimation fine tune */
3415 { 0x1f, 0x0001 },
3416 { 0x0b, 0x6c20 },
3417 { 0x07, 0x2872 },
3418 { 0x1c, 0xefff },
3419 { 0x1f, 0x0003 },
3420 { 0x14, 0x6420 },
3421 { 0x1f, 0x0000 },
3422
3423 /* Update PFM & 10M TX idle timer */
3424 { 0x1f, 0x0007 },
3425 { 0x1e, 0x002f },
3426 { 0x15, 0x1919 },
3427 { 0x1f, 0x0000 },
3428
3429 { 0x1f, 0x0007 },
3430 { 0x1e, 0x00ac },
3431 { 0x18, 0x0006 },
3432 { 0x1f, 0x0000 }
3433 };
3434
15ecd039
FR		 3435 rtl_apply_firmware(tp);
3436
01dc7fec 3437 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3438
3439 /* DCO enable for 10M IDLE Power */
3440 rtl_writephy(tp, 0x1f, 0x0007);
3441 rtl_writephy(tp, 0x1e, 0x0023);
76564428 3442 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
01dc7fec 3443 rtl_writephy(tp, 0x1f, 0x0000);
3444
3445 /* For impedance matching */
3446 rtl_writephy(tp, 0x1f, 0x0002);
76564428 3447 rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
cecb5fd7 3448 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3449
3450 /* PHY auto speed down */
3451 rtl_writephy(tp, 0x1f, 0x0007);
3452 rtl_writephy(tp, 0x1e, 0x002d);
76564428 3453 rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
01dc7fec 3454 rtl_writephy(tp, 0x1f, 0x0000);
76564428 3455 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
01dc7fec 3456
3457 rtl_writephy(tp, 0x1f, 0x0005);
3458 rtl_writephy(tp, 0x05, 0x8b86);
76564428 3459 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
01dc7fec 3460 rtl_writephy(tp, 0x1f, 0x0000);
3461
3462 rtl_writephy(tp, 0x1f, 0x0005);
3463 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3464 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
01dc7fec 3465 rtl_writephy(tp, 0x1f, 0x0007);
3466 rtl_writephy(tp, 0x1e, 0x0020);
76564428 3467 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
01dc7fec 3468 rtl_writephy(tp, 0x1f, 0x0006);
3469 rtl_writephy(tp, 0x00, 0x5a00);
3470 rtl_writephy(tp, 0x1f, 0x0000);
3471 rtl_writephy(tp, 0x0d, 0x0007);
3472 rtl_writephy(tp, 0x0e, 0x003c);
3473 rtl_writephy(tp, 0x0d, 0x4007);
3474 rtl_writephy(tp, 0x0e, 0x0000);
3475 rtl_writephy(tp, 0x0d, 0x0000);
3476}
3477
9ecb9aab 3478static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3479{
3480 const u16 w[] = {
3481 addr[0] | (addr[1] << 8),
3482 addr[2] | (addr[3] << 8),
3483 addr[4] | (addr[5] << 8)
3484 };
3485 const struct exgmac_reg e[] = {
3486 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3487 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3488 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3489 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3490 };
3491
3492 rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3493}
3494
70090424
HW		 3495static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3496{
3497 static const struct phy_reg phy_reg_init[] = {
3498 /* Enable Delay cap */
3499 { 0x1f, 0x0004 },
3500 { 0x1f, 0x0007 },
3501 { 0x1e, 0x00ac },
3502 { 0x18, 0x0006 },
3503 { 0x1f, 0x0002 },
3504 { 0x1f, 0x0000 },
3505 { 0x1f, 0x0000 },
3506
3507 /* Channel estimation fine tune */
3508 { 0x1f, 0x0003 },
3509 { 0x09, 0xa20f },
3510 { 0x1f, 0x0000 },
3511 { 0x1f, 0x0000 },
3512
3513 /* Green Setting */
3514 { 0x1f, 0x0005 },
3515 { 0x05, 0x8b5b },
3516 { 0x06, 0x9222 },
3517 { 0x05, 0x8b6d },
3518 { 0x06, 0x8000 },
3519 { 0x05, 0x8b76 },
3520 { 0x06, 0x8000 },
3521 { 0x1f, 0x0000 }
3522 };
3523
3524 rtl_apply_firmware(tp);
3525
3526 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3527
3528 /* For 4-corner performance improve */
3529 rtl_writephy(tp, 0x1f, 0x0005);
3530 rtl_writephy(tp, 0x05, 0x8b80);
76564428 3531 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
70090424
HW		 3532 rtl_writephy(tp, 0x1f, 0x0000);
3533
3534 /* PHY auto speed down */
3535 rtl_writephy(tp, 0x1f, 0x0004);
3536 rtl_writephy(tp, 0x1f, 0x0007);
3537 rtl_writephy(tp, 0x1e, 0x002d);
76564428 3538 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
70090424
HW		 3539 rtl_writephy(tp, 0x1f, 0x0002);
3540 rtl_writephy(tp, 0x1f, 0x0000);
76564428 3541 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
70090424
HW		 3542
3543 /* improve 10M EEE waveform */
3544 rtl_writephy(tp, 0x1f, 0x0005);
3545 rtl_writephy(tp, 0x05, 0x8b86);
76564428 3546 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
70090424
HW		 3547 rtl_writephy(tp, 0x1f, 0x0000);
3548
3549 /* Improve 2-pair detection performance */
3550 rtl_writephy(tp, 0x1f, 0x0005);
3551 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3552 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
70090424
HW		 3553 rtl_writephy(tp, 0x1f, 0x0000);
3554
3555 /* EEE setting */
706123d0 3556 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, ERIAR_EXGMAC);
70090424
HW		 3557 rtl_writephy(tp, 0x1f, 0x0005);
3558 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3559 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
70090424
HW		 3560 rtl_writephy(tp, 0x1f, 0x0004);
3561 rtl_writephy(tp, 0x1f, 0x0007);
3562 rtl_writephy(tp, 0x1e, 0x0020);
76564428 3563 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
70090424
HW		 3564 rtl_writephy(tp, 0x1f, 0x0002);
3565 rtl_writephy(tp, 0x1f, 0x0000);
3566 rtl_writephy(tp, 0x0d, 0x0007);
3567 rtl_writephy(tp, 0x0e, 0x003c);
3568 rtl_writephy(tp, 0x0d, 0x4007);
3569 rtl_writephy(tp, 0x0e, 0x0000);
3570 rtl_writephy(tp, 0x0d, 0x0000);
3571
3572 /* Green feature */
3573 rtl_writephy(tp, 0x1f, 0x0003);
76564428
CHL		 3574 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3575 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
70090424 3576 rtl_writephy(tp, 0x1f, 0x0000);
e0c07557 3577
9ecb9aab 3578 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3579 rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
70090424
HW		 3580}
3581
5f886e08
HW		 3582static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3583{
3584 /* For 4-corner performance improve */
3585 rtl_writephy(tp, 0x1f, 0x0005);
3586 rtl_writephy(tp, 0x05, 0x8b80);
76564428 3587 rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
5f886e08
HW		 3588 rtl_writephy(tp, 0x1f, 0x0000);
3589
3590 /* PHY auto speed down */
3591 rtl_writephy(tp, 0x1f, 0x0007);
3592 rtl_writephy(tp, 0x1e, 0x002d);
76564428 3593 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
5f886e08 3594 rtl_writephy(tp, 0x1f, 0x0000);
76564428 3595 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
5f886e08
HW		 3596
3597 /* Improve 10M EEE waveform */
3598 rtl_writephy(tp, 0x1f, 0x0005);
3599 rtl_writephy(tp, 0x05, 0x8b86);
76564428 3600 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
5f886e08
HW		 3601 rtl_writephy(tp, 0x1f, 0x0000);
3602}
3603
c2218925
HW		 3604static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3605{
3606 static const struct phy_reg phy_reg_init[] = {
3607 /* Channel estimation fine tune */
3608 { 0x1f, 0x0003 },
3609 { 0x09, 0xa20f },
3610 { 0x1f, 0x0000 },
3611
3612 /* Modify green table for giga & fnet */
3613 { 0x1f, 0x0005 },
3614 { 0x05, 0x8b55 },
3615 { 0x06, 0x0000 },
3616 { 0x05, 0x8b5e },
3617 { 0x06, 0x0000 },
3618 { 0x05, 0x8b67 },
3619 { 0x06, 0x0000 },
3620 { 0x05, 0x8b70 },
3621 { 0x06, 0x0000 },
3622 { 0x1f, 0x0000 },
3623 { 0x1f, 0x0007 },
3624 { 0x1e, 0x0078 },
3625 { 0x17, 0x0000 },
3626 { 0x19, 0x00fb },
3627 { 0x1f, 0x0000 },
3628
3629 /* Modify green table for 10M */
3630 { 0x1f, 0x0005 },
3631 { 0x05, 0x8b79 },
3632 { 0x06, 0xaa00 },
3633 { 0x1f, 0x0000 },
3634
3635 /* Disable hiimpedance detection (RTCT) */
3636 { 0x1f, 0x0003 },
3637 { 0x01, 0x328a },
3638 { 0x1f, 0x0000 }
3639 };
3640
3641 rtl_apply_firmware(tp);
3642
3643 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3644
5f886e08 3645 rtl8168f_hw_phy_config(tp);
c2218925
HW		 3646
3647 /* Improve 2-pair detection performance */
3648 rtl_writephy(tp, 0x1f, 0x0005);
3649 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3650 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
c2218925
HW		 3651 rtl_writephy(tp, 0x1f, 0x0000);
3652}
3653
3654static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3655{
3656 rtl_apply_firmware(tp);
3657
5f886e08 3658 rtl8168f_hw_phy_config(tp);
c2218925
HW		 3659}
3660
b3d7b2f2
HW		 3661static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3662{
b3d7b2f2
HW		 3663 static const struct phy_reg phy_reg_init[] = {
3664 /* Channel estimation fine tune */
3665 { 0x1f, 0x0003 },
3666 { 0x09, 0xa20f },
3667 { 0x1f, 0x0000 },
3668
3669 /* Modify green table for giga & fnet */
3670 { 0x1f, 0x0005 },
3671 { 0x05, 0x8b55 },
3672 { 0x06, 0x0000 },
3673 { 0x05, 0x8b5e },
3674 { 0x06, 0x0000 },
3675 { 0x05, 0x8b67 },
3676 { 0x06, 0x0000 },
3677 { 0x05, 0x8b70 },
3678 { 0x06, 0x0000 },
3679 { 0x1f, 0x0000 },
3680 { 0x1f, 0x0007 },
3681 { 0x1e, 0x0078 },
3682 { 0x17, 0x0000 },
3683 { 0x19, 0x00aa },
3684 { 0x1f, 0x0000 },
3685
3686 /* Modify green table for 10M */
3687 { 0x1f, 0x0005 },
3688 { 0x05, 0x8b79 },
3689 { 0x06, 0xaa00 },
3690 { 0x1f, 0x0000 },
3691
3692 /* Disable hiimpedance detection (RTCT) */
3693 { 0x1f, 0x0003 },
3694 { 0x01, 0x328a },
3695 { 0x1f, 0x0000 }
3696 };
3697
3698
3699 rtl_apply_firmware(tp);
3700
3701 rtl8168f_hw_phy_config(tp);
3702
3703 /* Improve 2-pair detection performance */
3704 rtl_writephy(tp, 0x1f, 0x0005);
3705 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3706 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
b3d7b2f2
HW		 3707 rtl_writephy(tp, 0x1f, 0x0000);
3708
3709 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3710
3711 /* Modify green table for giga */
3712 rtl_writephy(tp, 0x1f, 0x0005);
3713 rtl_writephy(tp, 0x05, 0x8b54);
76564428 3714 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
b3d7b2f2 3715 rtl_writephy(tp, 0x05, 0x8b5d);
76564428 3716 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
b3d7b2f2 3717 rtl_writephy(tp, 0x05, 0x8a7c);
76564428 3718 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2 3719 rtl_writephy(tp, 0x05, 0x8a7f);
76564428 3720 rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
b3d7b2f2 3721 rtl_writephy(tp, 0x05, 0x8a82);
76564428 3722 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2 3723 rtl_writephy(tp, 0x05, 0x8a85);
76564428 3724 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2 3725 rtl_writephy(tp, 0x05, 0x8a88);
76564428 3726 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2
HW		 3727 rtl_writephy(tp, 0x1f, 0x0000);
3728
3729 /* uc same-seed solution */
3730 rtl_writephy(tp, 0x1f, 0x0005);
3731 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3732 rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
b3d7b2f2
HW		 3733 rtl_writephy(tp, 0x1f, 0x0000);
3734
3735 /* eee setting */
706123d0 3736 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
b3d7b2f2
HW		 3737 rtl_writephy(tp, 0x1f, 0x0005);
3738 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3739 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
b3d7b2f2
HW		 3740 rtl_writephy(tp, 0x1f, 0x0004);
3741 rtl_writephy(tp, 0x1f, 0x0007);
3742 rtl_writephy(tp, 0x1e, 0x0020);
76564428 3743 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
b3d7b2f2
HW		 3744 rtl_writephy(tp, 0x1f, 0x0000);
3745 rtl_writephy(tp, 0x0d, 0x0007);
3746 rtl_writephy(tp, 0x0e, 0x003c);
3747 rtl_writephy(tp, 0x0d, 0x4007);
3748 rtl_writephy(tp, 0x0e, 0x0000);
3749 rtl_writephy(tp, 0x0d, 0x0000);
3750
3751 /* Green feature */
3752 rtl_writephy(tp, 0x1f, 0x0003);
76564428
CHL		 3753 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3754 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
b3d7b2f2
HW		 3755 rtl_writephy(tp, 0x1f, 0x0000);
3756}
3757
c558386b
HW		 3758static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3759{
c558386b
HW		 3760 rtl_apply_firmware(tp);
3761
41f44d13 3762 rtl_writephy(tp, 0x1f, 0x0a46);
3763 if (rtl_readphy(tp, 0x10) & 0x0100) {
3764 rtl_writephy(tp, 0x1f, 0x0bcc);
76564428 3765 rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
41f44d13 3766 } else {
3767 rtl_writephy(tp, 0x1f, 0x0bcc);
76564428 3768 rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
41f44d13 3769 }
c558386b 3770
41f44d13 3771 rtl_writephy(tp, 0x1f, 0x0a46);
3772 if (rtl_readphy(tp, 0x13) & 0x0100) {
3773 rtl_writephy(tp, 0x1f, 0x0c41);
76564428 3774 rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
41f44d13 3775 } else {
fe7524c0 3776 rtl_writephy(tp, 0x1f, 0x0c41);
76564428 3777 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
41f44d13 3778 }
c558386b 3779
41f44d13 3780 /* Enable PHY auto speed down */
3781 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 3782 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
c558386b 3783
fe7524c0 3784 rtl_writephy(tp, 0x1f, 0x0bcc);
76564428 3785 rtl_w0w1_phy(tp, 0x14, 0x0100, 0x0000);
fe7524c0 3786 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 3787 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
fe7524c0 3788 rtl_writephy(tp, 0x1f, 0x0a43);
3789 rtl_writephy(tp, 0x13, 0x8084);
76564428
CHL		 3790 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3791 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
fe7524c0 3792
41f44d13 3793 /* EEE auto-fallback function */
3794 rtl_writephy(tp, 0x1f, 0x0a4b);
76564428 3795 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
c558386b 3796
41f44d13 3797 /* Enable UC LPF tune function */
3798 rtl_writephy(tp, 0x1f, 0x0a43);
3799 rtl_writephy(tp, 0x13, 0x8012);
76564428 3800 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
41f44d13 3801
3802 rtl_writephy(tp, 0x1f, 0x0c42);
76564428 3803 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
41f44d13 3804
fe7524c0 3805 /* Improve SWR Efficiency */
3806 rtl_writephy(tp, 0x1f, 0x0bcd);
3807 rtl_writephy(tp, 0x14, 0x5065);
3808 rtl_writephy(tp, 0x14, 0xd065);
3809 rtl_writephy(tp, 0x1f, 0x0bc8);
3810 rtl_writephy(tp, 0x11, 0x5655);
3811 rtl_writephy(tp, 0x1f, 0x0bcd);
3812 rtl_writephy(tp, 0x14, 0x1065);
3813 rtl_writephy(tp, 0x14, 0x9065);
3814 rtl_writephy(tp, 0x14, 0x1065);
3815
1bac1072
DC		 3816 /* Check ALDPS bit, disable it if enabled */
3817 rtl_writephy(tp, 0x1f, 0x0a43);
3818 if (rtl_readphy(tp, 0x10) & 0x0004)
76564428 3819 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
1bac1072 3820
41f44d13 3821 rtl_writephy(tp, 0x1f, 0x0000);
c558386b
HW		 3822}
3823
57538c4a 3824static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3825{
3826 rtl_apply_firmware(tp);
3827}
3828
6e1d0b89
CHL		 3829static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3830{
3831 u16 dout_tapbin;
3832 u32 data;
3833
3834 rtl_apply_firmware(tp);
3835
3836 /* CHN EST parameters adjust - giga master */
3837 rtl_writephy(tp, 0x1f, 0x0a43);
3838 rtl_writephy(tp, 0x13, 0x809b);
76564428 3839 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
6e1d0b89 3840 rtl_writephy(tp, 0x13, 0x80a2);
76564428 3841 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
6e1d0b89 3842 rtl_writephy(tp, 0x13, 0x80a4);
76564428 3843 rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
6e1d0b89 3844 rtl_writephy(tp, 0x13, 0x809c);
76564428 3845 rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
6e1d0b89
CHL		 3846 rtl_writephy(tp, 0x1f, 0x0000);
3847
3848 /* CHN EST parameters adjust - giga slave */
3849 rtl_writephy(tp, 0x1f, 0x0a43);
3850 rtl_writephy(tp, 0x13, 0x80ad);
76564428 3851 rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
6e1d0b89 3852 rtl_writephy(tp, 0x13, 0x80b4);
76564428 3853 rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
6e1d0b89 3854 rtl_writephy(tp, 0x13, 0x80ac);
76564428 3855 rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
6e1d0b89
CHL		 3856 rtl_writephy(tp, 0x1f, 0x0000);
3857
3858 /* CHN EST parameters adjust - fnet */
3859 rtl_writephy(tp, 0x1f, 0x0a43);
3860 rtl_writephy(tp, 0x13, 0x808e);
76564428 3861 rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
6e1d0b89 3862 rtl_writephy(tp, 0x13, 0x8090);
76564428 3863 rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
6e1d0b89 3864 rtl_writephy(tp, 0x13, 0x8092);
76564428 3865 rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
6e1d0b89
CHL		 3866 rtl_writephy(tp, 0x1f, 0x0000);
3867
3868 /* enable R-tune & PGA-retune function */
3869 dout_tapbin = 0;
3870 rtl_writephy(tp, 0x1f, 0x0a46);
3871 data = rtl_readphy(tp, 0x13);
3872 data &= 3;
3873 data <<= 2;
3874 dout_tapbin |= data;
3875 data = rtl_readphy(tp, 0x12);
3876 data &= 0xc000;
3877 data >>= 14;
3878 dout_tapbin |= data;
3879 dout_tapbin = ~(dout_tapbin^0x08);
3880 dout_tapbin <<= 12;
3881 dout_tapbin &= 0xf000;
3882 rtl_writephy(tp, 0x1f, 0x0a43);
3883 rtl_writephy(tp, 0x13, 0x827a);
76564428 3884 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
6e1d0b89 3885 rtl_writephy(tp, 0x13, 0x827b);
76564428 3886 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
6e1d0b89 3887 rtl_writephy(tp, 0x13, 0x827c);
76564428 3888 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
6e1d0b89 3889 rtl_writephy(tp, 0x13, 0x827d);
76564428 3890 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
6e1d0b89
CHL		 3891
3892 rtl_writephy(tp, 0x1f, 0x0a43);
3893 rtl_writephy(tp, 0x13, 0x0811);
76564428 3894 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
6e1d0b89 3895 rtl_writephy(tp, 0x1f, 0x0a42);
76564428 3896 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
6e1d0b89
CHL		 3897 rtl_writephy(tp, 0x1f, 0x0000);
3898
3899 /* enable GPHY 10M */
3900 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 3901 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
6e1d0b89
CHL		 3902 rtl_writephy(tp, 0x1f, 0x0000);
3903
3904 /* SAR ADC performance */
3905 rtl_writephy(tp, 0x1f, 0x0bca);
76564428 3906 rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
6e1d0b89
CHL		 3907 rtl_writephy(tp, 0x1f, 0x0000);
3908
3909 rtl_writephy(tp, 0x1f, 0x0a43);
3910 rtl_writephy(tp, 0x13, 0x803f);
76564428 3911 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3912 rtl_writephy(tp, 0x13, 0x8047);
76564428 3913 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3914 rtl_writephy(tp, 0x13, 0x804f);
76564428 3915 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3916 rtl_writephy(tp, 0x13, 0x8057);
76564428 3917 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3918 rtl_writephy(tp, 0x13, 0x805f);
76564428 3919 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3920 rtl_writephy(tp, 0x13, 0x8067);
76564428 3921 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3922 rtl_writephy(tp, 0x13, 0x806f);
76564428 3923 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89
CHL		 3924 rtl_writephy(tp, 0x1f, 0x0000);
3925
3926 /* disable phy pfm mode */
3927 rtl_writephy(tp, 0x1f, 0x0a44);
c832c35f 3928 rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
6e1d0b89
CHL		 3929 rtl_writephy(tp, 0x1f, 0x0000);
3930
3931 /* Check ALDPS bit, disable it if enabled */
3932 rtl_writephy(tp, 0x1f, 0x0a43);
3933 if (rtl_readphy(tp, 0x10) & 0x0004)
76564428 3934 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
6e1d0b89
CHL		 3935
3936 rtl_writephy(tp, 0x1f, 0x0000);
3937}
3938
3939static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3940{
3941 u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3942 u16 rlen;
3943 u32 data;
3944
3945 rtl_apply_firmware(tp);
3946
3947 /* CHIN EST parameter update */
3948 rtl_writephy(tp, 0x1f, 0x0a43);
3949 rtl_writephy(tp, 0x13, 0x808a);
76564428 3950 rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
6e1d0b89
CHL		 3951 rtl_writephy(tp, 0x1f, 0x0000);
3952
3953 /* enable R-tune & PGA-retune function */
3954 rtl_writephy(tp, 0x1f, 0x0a43);
3955 rtl_writephy(tp, 0x13, 0x0811);
76564428 3956 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
6e1d0b89 3957 rtl_writephy(tp, 0x1f, 0x0a42);
76564428 3958 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
6e1d0b89
CHL		 3959 rtl_writephy(tp, 0x1f, 0x0000);
3960
3961 /* enable GPHY 10M */
3962 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 3963 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
6e1d0b89
CHL		 3964 rtl_writephy(tp, 0x1f, 0x0000);
3965
3966 r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3967 data = r8168_mac_ocp_read(tp, 0xdd02);
3968 ioffset_p3 = ((data & 0x80)>>7);
3969 ioffset_p3 <<= 3;
3970
3971 data = r8168_mac_ocp_read(tp, 0xdd00);
3972 ioffset_p3 |= ((data & (0xe000))>>13);
3973 ioffset_p2 = ((data & (0x1e00))>>9);
3974 ioffset_p1 = ((data & (0x01e0))>>5);
3975 ioffset_p0 = ((data & 0x0010)>>4);
3976 ioffset_p0 <<= 3;
3977 ioffset_p0 |= (data & (0x07));
3978 data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3979
05b9687b 3980 if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
e2e2788e 3981 (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
6e1d0b89
CHL		 3982 rtl_writephy(tp, 0x1f, 0x0bcf);
3983 rtl_writephy(tp, 0x16, data);
3984 rtl_writephy(tp, 0x1f, 0x0000);
3985 }
3986
3987 /* Modify rlen (TX LPF corner frequency) level */
3988 rtl_writephy(tp, 0x1f, 0x0bcd);
3989 data = rtl_readphy(tp, 0x16);
3990 data &= 0x000f;
3991 rlen = 0;
3992 if (data > 3)
3993 rlen = data - 3;
3994 data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3995 rtl_writephy(tp, 0x17, data);
3996 rtl_writephy(tp, 0x1f, 0x0bcd);
3997 rtl_writephy(tp, 0x1f, 0x0000);
3998
3999 /* disable phy pfm mode */
4000 rtl_writephy(tp, 0x1f, 0x0a44);
c832c35f 4001 rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
6e1d0b89
CHL		 4002 rtl_writephy(tp, 0x1f, 0x0000);
4003
4004 /* Check ALDPS bit, disable it if enabled */
4005 rtl_writephy(tp, 0x1f, 0x0a43);
4006 if (rtl_readphy(tp, 0x10) & 0x0004)
76564428 4007 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
6e1d0b89
CHL		 4008
4009 rtl_writephy(tp, 0x1f, 0x0000);
4010}
4011
935e2218
CHL		 4012static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
4013{
4014 /* Enable PHY auto speed down */
4015 rtl_writephy(tp, 0x1f, 0x0a44);
4016 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
4017 rtl_writephy(tp, 0x1f, 0x0000);
4018
4019 /* patch 10M & ALDPS */
4020 rtl_writephy(tp, 0x1f, 0x0bcc);
4021 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
4022 rtl_writephy(tp, 0x1f, 0x0a44);
4023 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
4024 rtl_writephy(tp, 0x1f, 0x0a43);
4025 rtl_writephy(tp, 0x13, 0x8084);
4026 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
4027 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
4028 rtl_writephy(tp, 0x1f, 0x0000);
4029
4030 /* Enable EEE auto-fallback function */
4031 rtl_writephy(tp, 0x1f, 0x0a4b);
4032 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
4033 rtl_writephy(tp, 0x1f, 0x0000);
4034
4035 /* Enable UC LPF tune function */
4036 rtl_writephy(tp, 0x1f, 0x0a43);
4037 rtl_writephy(tp, 0x13, 0x8012);
4038 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
4039 rtl_writephy(tp, 0x1f, 0x0000);
4040
4041 /* set rg_sel_sdm_rate */
4042 rtl_writephy(tp, 0x1f, 0x0c42);
4043 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
4044 rtl_writephy(tp, 0x1f, 0x0000);
4045
4046 /* Check ALDPS bit, disable it if enabled */
4047 rtl_writephy(tp, 0x1f, 0x0a43);
4048 if (rtl_readphy(tp, 0x10) & 0x0004)
4049 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4050
4051 rtl_writephy(tp, 0x1f, 0x0000);
4052}
4053
4054static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
4055{
4056 /* patch 10M & ALDPS */
4057 rtl_writephy(tp, 0x1f, 0x0bcc);
4058 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
4059 rtl_writephy(tp, 0x1f, 0x0a44);
4060 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
4061 rtl_writephy(tp, 0x1f, 0x0a43);
4062 rtl_writephy(tp, 0x13, 0x8084);
4063 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
4064 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
4065 rtl_writephy(tp, 0x1f, 0x0000);
4066
4067 /* Enable UC LPF tune function */
4068 rtl_writephy(tp, 0x1f, 0x0a43);
4069 rtl_writephy(tp, 0x13, 0x8012);
4070 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
4071 rtl_writephy(tp, 0x1f, 0x0000);
4072
4073 /* Set rg_sel_sdm_rate */
4074 rtl_writephy(tp, 0x1f, 0x0c42);
4075 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
4076 rtl_writephy(tp, 0x1f, 0x0000);
4077
4078 /* Channel estimation parameters */
4079 rtl_writephy(tp, 0x1f, 0x0a43);
4080 rtl_writephy(tp, 0x13, 0x80f3);
4081 rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
4082 rtl_writephy(tp, 0x13, 0x80f0);
4083 rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
4084 rtl_writephy(tp, 0x13, 0x80ef);
4085 rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
4086 rtl_writephy(tp, 0x13, 0x80f6);
4087 rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
4088 rtl_writephy(tp, 0x13, 0x80ec);
4089 rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
4090 rtl_writephy(tp, 0x13, 0x80ed);
4091 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
4092 rtl_writephy(tp, 0x13, 0x80f2);
4093 rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
4094 rtl_writephy(tp, 0x13, 0x80f4);
4095 rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
4096 rtl_writephy(tp, 0x1f, 0x0a43);
4097 rtl_writephy(tp, 0x13, 0x8110);
4098 rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
4099 rtl_writephy(tp, 0x13, 0x810f);
4100 rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
4101 rtl_writephy(tp, 0x13, 0x8111);
4102 rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
4103 rtl_writephy(tp, 0x13, 0x8113);
4104 rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
4105 rtl_writephy(tp, 0x13, 0x8115);
4106 rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
4107 rtl_writephy(tp, 0x13, 0x810e);
4108 rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
4109 rtl_writephy(tp, 0x13, 0x810c);
4110 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
4111 rtl_writephy(tp, 0x13, 0x810b);
4112 rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
4113 rtl_writephy(tp, 0x1f, 0x0a43);
4114 rtl_writephy(tp, 0x13, 0x80d1);
4115 rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
4116 rtl_writephy(tp, 0x13, 0x80cd);
4117 rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
4118 rtl_writephy(tp, 0x13, 0x80d3);
4119 rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
4120 rtl_writephy(tp, 0x13, 0x80d5);
4121 rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
4122 rtl_writephy(tp, 0x13, 0x80d7);
4123 rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
4124
4125 /* Force PWM-mode */
4126 rtl_writephy(tp, 0x1f, 0x0bcd);
4127 rtl_writephy(tp, 0x14, 0x5065);
4128 rtl_writephy(tp, 0x14, 0xd065);
4129 rtl_writephy(tp, 0x1f, 0x0bc8);
4130 rtl_writephy(tp, 0x12, 0x00ed);
4131 rtl_writephy(tp, 0x1f, 0x0bcd);
4132 rtl_writephy(tp, 0x14, 0x1065);
4133 rtl_writephy(tp, 0x14, 0x9065);
4134 rtl_writephy(tp, 0x14, 0x1065);
4135 rtl_writephy(tp, 0x1f, 0x0000);
4136
4137 /* Check ALDPS bit, disable it if enabled */
4138 rtl_writephy(tp, 0x1f, 0x0a43);
4139 if (rtl_readphy(tp, 0x10) & 0x0004)
4140 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4141
4142 rtl_writephy(tp, 0x1f, 0x0000);
4143}
4144
4da19633 4145static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2857ffb7 4146{
350f7596 4147 static const struct phy_reg phy_reg_init[] = {
2857ffb7
FR		 4148 { 0x1f, 0x0003 },
4149 { 0x08, 0x441d },
4150 { 0x01, 0x9100 },
4151 { 0x1f, 0x0000 }
4152 };
4153
4da19633 4154 rtl_writephy(tp, 0x1f, 0x0000);
4155 rtl_patchphy(tp, 0x11, 1 << 12);
4156 rtl_patchphy(tp, 0x19, 1 << 13);
4157 rtl_patchphy(tp, 0x10, 1 << 15);
2857ffb7 4158
4da19633 4159 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2857ffb7
FR		 4160}
4161
5a5e4443
HW		 4162static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
4163{
4164 static const struct phy_reg phy_reg_init[] = {
4165 { 0x1f, 0x0005 },
4166 { 0x1a, 0x0000 },
4167 { 0x1f, 0x0000 },
4168
4169 { 0x1f, 0x0004 },
4170 { 0x1c, 0x0000 },
4171 { 0x1f, 0x0000 },
4172
4173 { 0x1f, 0x0001 },
4174 { 0x15, 0x7701 },
4175 { 0x1f, 0x0000 }
4176 };
4177
4178 /* Disable ALDPS before ram code */
eef63cc1
FR		 4179 rtl_writephy(tp, 0x1f, 0x0000);
4180 rtl_writephy(tp, 0x18, 0x0310);
4181 msleep(100);
5a5e4443 4182
953a12cc 4183 rtl_apply_firmware(tp);
5a5e4443
HW		 4184
4185 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4186}
4187
7e18dca1
HW		 4188static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
4189{
7e18dca1 4190 /* Disable ALDPS before setting firmware */
eef63cc1
FR		 4191 rtl_writephy(tp, 0x1f, 0x0000);
4192 rtl_writephy(tp, 0x18, 0x0310);
4193 msleep(20);
7e18dca1
HW		 4194
4195 rtl_apply_firmware(tp);
4196
4197 /* EEE setting */
fdf6fc06 4198 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
7e18dca1
HW		 4199 rtl_writephy(tp, 0x1f, 0x0004);
4200 rtl_writephy(tp, 0x10, 0x401f);
4201 rtl_writephy(tp, 0x19, 0x7030);
4202 rtl_writephy(tp, 0x1f, 0x0000);
4203}
4204
5598bfe5
HW		 4205static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
4206{
5598bfe5
HW		 4207 static const struct phy_reg phy_reg_init[] = {
4208 { 0x1f, 0x0004 },
4209 { 0x10, 0xc07f },
4210 { 0x19, 0x7030 },
4211 { 0x1f, 0x0000 }
4212 };
4213
4214 /* Disable ALDPS before ram code */
eef63cc1
FR		 4215 rtl_writephy(tp, 0x1f, 0x0000);
4216 rtl_writephy(tp, 0x18, 0x0310);
4217 msleep(100);
5598bfe5
HW		 4218
4219 rtl_apply_firmware(tp);
4220
fdf6fc06 4221 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5598bfe5
HW		 4222 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4223
fdf6fc06 4224 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5598bfe5
HW		 4225}
4226
5615d9f1
FR		 4227static void rtl_hw_phy_config(struct net_device *dev)
4228{
4229 struct rtl8169_private *tp = netdev_priv(dev);
5615d9f1
FR		 4230
4231 rtl8169_print_mac_version(tp);
4232
4233 switch (tp->mac_version) {
4234 case RTL_GIGA_MAC_VER_01:
4235 break;
4236 case RTL_GIGA_MAC_VER_02:
4237 case RTL_GIGA_MAC_VER_03:
4da19633 4238 rtl8169s_hw_phy_config(tp);
5615d9f1
FR		 4239 break;
4240 case RTL_GIGA_MAC_VER_04:
4da19633 4241 rtl8169sb_hw_phy_config(tp);
5615d9f1 4242 break;
2e955856 4243 case RTL_GIGA_MAC_VER_05:
4da19633 4244 rtl8169scd_hw_phy_config(tp);
2e955856 4245 break;
8c7006aa 4246 case RTL_GIGA_MAC_VER_06:
4da19633 4247 rtl8169sce_hw_phy_config(tp);
8c7006aa 4248 break;
2857ffb7
FR		 4249 case RTL_GIGA_MAC_VER_07:
4250 case RTL_GIGA_MAC_VER_08:
4251 case RTL_GIGA_MAC_VER_09:
4da19633 4252 rtl8102e_hw_phy_config(tp);
2857ffb7 4253 break;
236b8082 4254 case RTL_GIGA_MAC_VER_11:
4da19633 4255 rtl8168bb_hw_phy_config(tp);
236b8082
FR		 4256 break;
4257 case RTL_GIGA_MAC_VER_12:
4da19633 4258 rtl8168bef_hw_phy_config(tp);
236b8082
FR		 4259 break;
4260 case RTL_GIGA_MAC_VER_17:
4da19633 4261 rtl8168bef_hw_phy_config(tp);
236b8082 4262 break;
867763c1 4263 case RTL_GIGA_MAC_VER_18:
4da19633 4264 rtl8168cp_1_hw_phy_config(tp);
867763c1
FR		 4265 break;
4266 case RTL_GIGA_MAC_VER_19:
4da19633 4267 rtl8168c_1_hw_phy_config(tp);
867763c1 4268 break;
7da97ec9 4269 case RTL_GIGA_MAC_VER_20:
4da19633 4270 rtl8168c_2_hw_phy_config(tp);
7da97ec9 4271 break;
197ff761 4272 case RTL_GIGA_MAC_VER_21:
4da19633 4273 rtl8168c_3_hw_phy_config(tp);
197ff761 4274 break;
6fb07058 4275 case RTL_GIGA_MAC_VER_22:
4da19633 4276 rtl8168c_4_hw_phy_config(tp);
6fb07058 4277 break;
ef3386f0 4278 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 4279 case RTL_GIGA_MAC_VER_24:
4da19633 4280 rtl8168cp_2_hw_phy_config(tp);
ef3386f0 4281 break;
5b538df9 4282 case RTL_GIGA_MAC_VER_25:
bca03d5f 4283 rtl8168d_1_hw_phy_config(tp);
daf9df6d 4284 break;
4285 case RTL_GIGA_MAC_VER_26:
bca03d5f 4286 rtl8168d_2_hw_phy_config(tp);
daf9df6d 4287 break;
4288 case RTL_GIGA_MAC_VER_27:
4da19633 4289 rtl8168d_3_hw_phy_config(tp);
5b538df9 4290 break;
e6de30d6 4291 case RTL_GIGA_MAC_VER_28:
4292 rtl8168d_4_hw_phy_config(tp);
4293 break;
5a5e4443
HW		 4294 case RTL_GIGA_MAC_VER_29:
4295 case RTL_GIGA_MAC_VER_30:
4296 rtl8105e_hw_phy_config(tp);
4297 break;
cecb5fd7
FR		 4298 case RTL_GIGA_MAC_VER_31:
4299 /* None. */
4300 break;
01dc7fec 4301 case RTL_GIGA_MAC_VER_32:
01dc7fec 4302 case RTL_GIGA_MAC_VER_33:
70090424
HW		 4303 rtl8168e_1_hw_phy_config(tp);
4304 break;
4305 case RTL_GIGA_MAC_VER_34:
4306 rtl8168e_2_hw_phy_config(tp);
01dc7fec 4307 break;
c2218925
HW		 4308 case RTL_GIGA_MAC_VER_35:
4309 rtl8168f_1_hw_phy_config(tp);
4310 break;
4311 case RTL_GIGA_MAC_VER_36:
4312 rtl8168f_2_hw_phy_config(tp);
4313 break;
ef3386f0 4314
7e18dca1
HW		 4315 case RTL_GIGA_MAC_VER_37:
4316 rtl8402_hw_phy_config(tp);
4317 break;
4318
b3d7b2f2
HW		 4319 case RTL_GIGA_MAC_VER_38:
4320 rtl8411_hw_phy_config(tp);
4321 break;
4322
5598bfe5
HW		 4323 case RTL_GIGA_MAC_VER_39:
4324 rtl8106e_hw_phy_config(tp);
4325 break;
4326
c558386b
HW		 4327 case RTL_GIGA_MAC_VER_40:
4328 rtl8168g_1_hw_phy_config(tp);
4329 break;
57538c4a 4330 case RTL_GIGA_MAC_VER_42:
58152cd4 4331 case RTL_GIGA_MAC_VER_43:
45dd95c4 4332 case RTL_GIGA_MAC_VER_44:
57538c4a 4333 rtl8168g_2_hw_phy_config(tp);
4334 break;
6e1d0b89
CHL		 4335 case RTL_GIGA_MAC_VER_45:
4336 case RTL_GIGA_MAC_VER_47:
4337 rtl8168h_1_hw_phy_config(tp);
4338 break;
4339 case RTL_GIGA_MAC_VER_46:
4340 case RTL_GIGA_MAC_VER_48:
4341 rtl8168h_2_hw_phy_config(tp);
4342 break;
c558386b 4343
935e2218
CHL		 4344 case RTL_GIGA_MAC_VER_49:
4345 rtl8168ep_1_hw_phy_config(tp);
4346 break;
4347 case RTL_GIGA_MAC_VER_50:
4348 case RTL_GIGA_MAC_VER_51:
4349 rtl8168ep_2_hw_phy_config(tp);
4350 break;
4351
c558386b 4352 case RTL_GIGA_MAC_VER_41:
5615d9f1
FR		 4353 default:
4354 break;
4355 }
4356}
4357
da78dbff 4358static void rtl_phy_work(struct rtl8169_private *tp)
1da177e4 4359{
1da177e4
LT		 4360 struct timer_list *timer = &tp->timer;
4361 void __iomem *ioaddr = tp->mmio_addr;
4362 unsigned long timeout = RTL8169_PHY_TIMEOUT;
4363
bcf0bf90 4364 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 4365
4da19633 4366 if (tp->phy_reset_pending(tp)) {
5b0384f4 4367 /*
1da177e4
LT		 4368 * A busy loop could burn quite a few cycles on nowadays CPU.
4369 * Let's delay the execution of the timer for a few ticks.
4370 */
4371 timeout = HZ/10;
4372 goto out_mod_timer;
4373 }
4374
4375 if (tp->link_ok(ioaddr))
da78dbff 4376 return;
1da177e4 4377
9bb8eeb5 4378 netif_dbg(tp, link, tp->dev, "PHY reset until link up\n");
1da177e4 4379
4da19633 4380 tp->phy_reset_enable(tp);
1da177e4
LT		 4381
4382out_mod_timer:
4383 mod_timer(timer, jiffies + timeout);
da78dbff
FR		 4384}
4385
4386static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
4387{
da78dbff
FR		 4388 if (!test_and_set_bit(flag, tp->wk.flags))
4389 schedule_work(&tp->wk.work);
da78dbff
FR		 4390}
4391
4392static void rtl8169_phy_timer(unsigned long __opaque)
4393{
4394 struct net_device *dev = (struct net_device *)__opaque;
4395 struct rtl8169_private *tp = netdev_priv(dev);
4396
98ddf986 4397 rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
1da177e4
LT		 4398}
4399
1da177e4
LT		 4400static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
4401 void __iomem *ioaddr)
4402{
4403 iounmap(ioaddr);
4404 pci_release_regions(pdev);
87aeec76 4405 pci_clear_mwi(pdev);
1da177e4
LT		 4406 pci_disable_device(pdev);
4407 free_netdev(dev);
4408}
4409
ffc46952
FR		 4410DECLARE_RTL_COND(rtl_phy_reset_cond)
4411{
4412 return tp->phy_reset_pending(tp);
4413}
4414
bf793295
FR		 4415static void rtl8169_phy_reset(struct net_device *dev,
4416 struct rtl8169_private *tp)
4417{
4da19633 4418 tp->phy_reset_enable(tp);
ffc46952 4419 rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100);
bf793295
FR		 4420}
4421
2544bfc0
FR		 4422static bool rtl_tbi_enabled(struct rtl8169_private *tp)
4423{
4424 void __iomem *ioaddr = tp->mmio_addr;
4425
4426 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
4427 (RTL_R8(PHYstatus) & TBI_Enable);
4428}
4429
4ff96fa6
FR		 4430static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
4431{
4432 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 4433
5615d9f1 4434 rtl_hw_phy_config(dev);
4ff96fa6 4435
77332894
MS		 4436 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
4437 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4438 RTL_W8(0x82, 0x01);
4439 }
4ff96fa6 4440
6dccd16b
FR		 4441 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
4442
4443 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
4444 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 4445
bcf0bf90 4446 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 4447 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4448 RTL_W8(0x82, 0x01);
4449 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4da19633 4450 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4ff96fa6
FR		 4451 }
4452
bf793295
FR		 4453 rtl8169_phy_reset(dev, tp);
4454
54405cde 4455 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
cecb5fd7
FR		 4456 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4457 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4458 (tp->mii.supports_gmii ?
4459 ADVERTISED_1000baseT_Half |
4460 ADVERTISED_1000baseT_Full : 0));
4ff96fa6 4461
2544bfc0 4462 if (rtl_tbi_enabled(tp))
bf82c189 4463 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4ff96fa6
FR		 4464}
4465
773d2021
FR		 4466static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4467{
4468 void __iomem *ioaddr = tp->mmio_addr;
773d2021 4469
da78dbff 4470 rtl_lock_work(tp);
773d2021
FR		 4471
4472 RTL_W8(Cfg9346, Cfg9346_Unlock);
908ba2bf 4473
9ecb9aab 4474 RTL_W32(MAC4, addr[4] | addr[5] << 8);
908ba2bf 4475 RTL_R32(MAC4);
4476
9ecb9aab 4477 RTL_W32(MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
908ba2bf 4478 RTL_R32(MAC0);
4479
9ecb9aab 4480 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4481 rtl_rar_exgmac_set(tp, addr);
c28aa385 4482
773d2021
FR		 4483 RTL_W8(Cfg9346, Cfg9346_Lock);
4484
da78dbff 4485 rtl_unlock_work(tp);
773d2021
FR		 4486}
4487
4488static int rtl_set_mac_address(struct net_device *dev, void *p)
4489{
4490 struct rtl8169_private *tp = netdev_priv(dev);
f51d4a10 4491 struct device *d = &tp->pci_dev->dev;
773d2021
FR		 4492 struct sockaddr *addr = p;
4493
4494 if (!is_valid_ether_addr(addr->sa_data))
4495 return -EADDRNOTAVAIL;
4496
4497 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
4498
f51d4a10
CHL		 4499 pm_runtime_get_noresume(d);
4500
4501 if (pm_runtime_active(d))
4502 rtl_rar_set(tp, dev->dev_addr);
4503
4504 pm_runtime_put_noidle(d);
773d2021
FR		 4505
4506 return 0;
4507}
4508
5f787a1a
FR		 4509static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4510{
4511 struct rtl8169_private *tp = netdev_priv(dev);
4512 struct mii_ioctl_data *data = if_mii(ifr);
4513
8b4ab28d
FR		 4514 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
4515}
5f787a1a 4516
cecb5fd7
FR		 4517static int rtl_xmii_ioctl(struct rtl8169_private *tp,
4518 struct mii_ioctl_data *data, int cmd)
8b4ab28d 4519{
5f787a1a
FR		 4520 switch (cmd) {
4521 case SIOCGMIIPHY:
4522 data->phy_id = 32; /* Internal PHY */
4523 return 0;
4524
4525 case SIOCGMIIREG:
4da19633 4526 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
5f787a1a
FR		 4527 return 0;
4528
4529 case SIOCSMIIREG:
4da19633 4530 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
5f787a1a
FR		 4531 return 0;
4532 }
4533 return -EOPNOTSUPP;
4534}
4535
8b4ab28d
FR		 4536static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
4537{
4538 return -EOPNOTSUPP;
4539}
4540
fbac58fc
FR		 4541static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
4542{
4543 if (tp->features & RTL_FEATURE_MSI) {
4544 pci_disable_msi(pdev);
4545 tp->features &= ~RTL_FEATURE_MSI;
4546 }
4547}
4548
baf63293 4549static void rtl_init_mdio_ops(struct rtl8169_private *tp)
c0e45c1c 4550{
4551 struct mdio_ops *ops = &tp->mdio_ops;
4552
4553 switch (tp->mac_version) {
4554 case RTL_GIGA_MAC_VER_27:
4555 ops->write = r8168dp_1_mdio_write;
4556 ops->read = r8168dp_1_mdio_read;
4557 break;
e6de30d6 4558 case RTL_GIGA_MAC_VER_28:
4804b3b3 4559 case RTL_GIGA_MAC_VER_31:
e6de30d6 4560 ops->write = r8168dp_2_mdio_write;
4561 ops->read = r8168dp_2_mdio_read;
4562 break;
c558386b
HW		 4563 case RTL_GIGA_MAC_VER_40:
4564 case RTL_GIGA_MAC_VER_41:
57538c4a 4565 case RTL_GIGA_MAC_VER_42:
58152cd4 4566 case RTL_GIGA_MAC_VER_43:
45dd95c4 4567 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4568 case RTL_GIGA_MAC_VER_45:
4569 case RTL_GIGA_MAC_VER_46:
4570 case RTL_GIGA_MAC_VER_47:
4571 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 4572 case RTL_GIGA_MAC_VER_49:
4573 case RTL_GIGA_MAC_VER_50:
4574 case RTL_GIGA_MAC_VER_51:
c558386b
HW		 4575 ops->write = r8168g_mdio_write;
4576 ops->read = r8168g_mdio_read;
4577 break;
c0e45c1c 4578 default:
4579 ops->write = r8169_mdio_write;
4580 ops->read = r8169_mdio_read;
4581 break;
4582 }
4583}
4584
e2409d83 4585static void rtl_speed_down(struct rtl8169_private *tp)
4586{
4587 u32 adv;
4588 int lpa;
4589
4590 rtl_writephy(tp, 0x1f, 0x0000);
4591 lpa = rtl_readphy(tp, MII_LPA);
4592
4593 if (lpa & (LPA_10HALF | LPA_10FULL))
4594 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
4595 else if (lpa & (LPA_100HALF | LPA_100FULL))
4596 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4597 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4598 else
4599 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4600 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4601 (tp->mii.supports_gmii ?
4602 ADVERTISED_1000baseT_Half |
4603 ADVERTISED_1000baseT_Full : 0);
4604
4605 rtl8169_set_speed(tp->dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
4606 adv);
4607}
4608
649b3b8c 4609static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4610{
4611 void __iomem *ioaddr = tp->mmio_addr;
4612
4613 switch (tp->mac_version) {
b00e69de
CB		 4614 case RTL_GIGA_MAC_VER_25:
4615 case RTL_GIGA_MAC_VER_26:
649b3b8c 4616 case RTL_GIGA_MAC_VER_29:
4617 case RTL_GIGA_MAC_VER_30:
4618 case RTL_GIGA_MAC_VER_32:
4619 case RTL_GIGA_MAC_VER_33:
4620 case RTL_GIGA_MAC_VER_34:
7e18dca1 4621 case RTL_GIGA_MAC_VER_37:
b3d7b2f2 4622 case RTL_GIGA_MAC_VER_38:
5598bfe5 4623 case RTL_GIGA_MAC_VER_39:
c558386b
HW		 4624 case RTL_GIGA_MAC_VER_40:
4625 case RTL_GIGA_MAC_VER_41:
57538c4a 4626 case RTL_GIGA_MAC_VER_42:
58152cd4 4627 case RTL_GIGA_MAC_VER_43:
45dd95c4 4628 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4629 case RTL_GIGA_MAC_VER_45:
4630 case RTL_GIGA_MAC_VER_46:
4631 case RTL_GIGA_MAC_VER_47:
4632 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 4633 case RTL_GIGA_MAC_VER_49:
4634 case RTL_GIGA_MAC_VER_50:
4635 case RTL_GIGA_MAC_VER_51:
649b3b8c 4636 RTL_W32(RxConfig, RTL_R32(RxConfig) |
4637 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4638 break;
4639 default:
4640 break;
4641 }
4642}
4643
4644static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
4645{
4646 if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
4647 return false;
4648
e2409d83 4649 rtl_speed_down(tp);
649b3b8c 4650 rtl_wol_suspend_quirk(tp);
4651
4652 return true;
4653}
4654
065c27c1 4655static void r810x_phy_power_down(struct rtl8169_private *tp)
4656{
4657 rtl_writephy(tp, 0x1f, 0x0000);
4658 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4659}
4660
4661static void r810x_phy_power_up(struct rtl8169_private *tp)
4662{
4663 rtl_writephy(tp, 0x1f, 0x0000);
4664 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4665}
4666
4667static void r810x_pll_power_down(struct rtl8169_private *tp)
4668{
0004299a
HW		 4669 void __iomem *ioaddr = tp->mmio_addr;
4670
649b3b8c 4671 if (rtl_wol_pll_power_down(tp))
065c27c1 4672 return;
065c27c1 4673
4674 r810x_phy_power_down(tp);
0004299a
HW		 4675
4676 switch (tp->mac_version) {
4677 case RTL_GIGA_MAC_VER_07:
4678 case RTL_GIGA_MAC_VER_08:
4679 case RTL_GIGA_MAC_VER_09:
4680 case RTL_GIGA_MAC_VER_10:
4681 case RTL_GIGA_MAC_VER_13:
4682 case RTL_GIGA_MAC_VER_16:
4683 break;
4684 default:
4685 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4686 break;
4687 }
065c27c1 4688}
4689
4690static void r810x_pll_power_up(struct rtl8169_private *tp)
4691{
0004299a
HW		 4692 void __iomem *ioaddr = tp->mmio_addr;
4693
065c27c1 4694 r810x_phy_power_up(tp);
0004299a
HW		 4695
4696 switch (tp->mac_version) {
4697 case RTL_GIGA_MAC_VER_07:
4698 case RTL_GIGA_MAC_VER_08:
4699 case RTL_GIGA_MAC_VER_09:
4700 case RTL_GIGA_MAC_VER_10:
4701 case RTL_GIGA_MAC_VER_13:
4702 case RTL_GIGA_MAC_VER_16:
4703 break;
6e1d0b89
CHL		 4704 case RTL_GIGA_MAC_VER_47:
4705 case RTL_GIGA_MAC_VER_48:
05b9687b 4706 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
6e1d0b89 4707 break;
0004299a
HW		 4708 default:
4709 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4710 break;
4711 }
065c27c1 4712}
4713
4714static void r8168_phy_power_up(struct rtl8169_private *tp)
4715{
4716 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 4717 switch (tp->mac_version) {
4718 case RTL_GIGA_MAC_VER_11:
4719 case RTL_GIGA_MAC_VER_12:
4720 case RTL_GIGA_MAC_VER_17:
4721 case RTL_GIGA_MAC_VER_18:
4722 case RTL_GIGA_MAC_VER_19:
4723 case RTL_GIGA_MAC_VER_20:
4724 case RTL_GIGA_MAC_VER_21:
4725 case RTL_GIGA_MAC_VER_22:
4726 case RTL_GIGA_MAC_VER_23:
4727 case RTL_GIGA_MAC_VER_24:
4728 case RTL_GIGA_MAC_VER_25:
4729 case RTL_GIGA_MAC_VER_26:
4730 case RTL_GIGA_MAC_VER_27:
4731 case RTL_GIGA_MAC_VER_28:
4732 case RTL_GIGA_MAC_VER_31:
4733 rtl_writephy(tp, 0x0e, 0x0000);
4734 break;
4735 default:
4736 break;
4737 }
065c27c1 4738 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4739}
4740
4741static void r8168_phy_power_down(struct rtl8169_private *tp)
4742{
4743 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 4744 switch (tp->mac_version) {
4745 case RTL_GIGA_MAC_VER_32:
4746 case RTL_GIGA_MAC_VER_33:
beb330a4 4747 case RTL_GIGA_MAC_VER_40:
4748 case RTL_GIGA_MAC_VER_41:
01dc7fec 4749 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
4750 break;
4751
4752 case RTL_GIGA_MAC_VER_11:
4753 case RTL_GIGA_MAC_VER_12:
4754 case RTL_GIGA_MAC_VER_17:
4755 case RTL_GIGA_MAC_VER_18:
4756 case RTL_GIGA_MAC_VER_19:
4757 case RTL_GIGA_MAC_VER_20:
4758 case RTL_GIGA_MAC_VER_21:
4759 case RTL_GIGA_MAC_VER_22:
4760 case RTL_GIGA_MAC_VER_23:
4761 case RTL_GIGA_MAC_VER_24:
4762 case RTL_GIGA_MAC_VER_25:
4763 case RTL_GIGA_MAC_VER_26:
4764 case RTL_GIGA_MAC_VER_27:
4765 case RTL_GIGA_MAC_VER_28:
4766 case RTL_GIGA_MAC_VER_31:
4767 rtl_writephy(tp, 0x0e, 0x0200);
4768 default:
4769 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4770 break;
4771 }
065c27c1 4772}
4773
4774static void r8168_pll_power_down(struct rtl8169_private *tp)
4775{
4776 void __iomem *ioaddr = tp->mmio_addr;
4777
cecb5fd7
FR		 4778 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4779 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
935e2218
CHL		 4780 tp->mac_version == RTL_GIGA_MAC_VER_31 ||
4781 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
4782 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
4783 tp->mac_version == RTL_GIGA_MAC_VER_51) &&
2f8c040c 4784 r8168_check_dash(tp)) {
065c27c1 4785 return;
5d2e1957 4786 }
065c27c1 4787
cecb5fd7
FR		 4788 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
4789 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
065c27c1 4790 (RTL_R16(CPlusCmd) & ASF)) {
4791 return;
4792 }
4793
01dc7fec 4794 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4795 tp->mac_version == RTL_GIGA_MAC_VER_33)
fdf6fc06 4796 rtl_ephy_write(tp, 0x19, 0xff64);
01dc7fec 4797
649b3b8c 4798 if (rtl_wol_pll_power_down(tp))
065c27c1 4799 return;
065c27c1 4800
4801 r8168_phy_power_down(tp);
4802
4803 switch (tp->mac_version) {
4804 case RTL_GIGA_MAC_VER_25:
4805 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 4806 case RTL_GIGA_MAC_VER_27:
4807 case RTL_GIGA_MAC_VER_28:
4804b3b3 4808 case RTL_GIGA_MAC_VER_31:
01dc7fec 4809 case RTL_GIGA_MAC_VER_32:
4810 case RTL_GIGA_MAC_VER_33:
42fde737 4811 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4812 case RTL_GIGA_MAC_VER_45:
4813 case RTL_GIGA_MAC_VER_46:
935e2218
CHL		 4814 case RTL_GIGA_MAC_VER_50:
4815 case RTL_GIGA_MAC_VER_51:
065c27c1 4816 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4817 break;
beb330a4 4818 case RTL_GIGA_MAC_VER_40:
4819 case RTL_GIGA_MAC_VER_41:
935e2218 4820 case RTL_GIGA_MAC_VER_49:
706123d0 4821 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
beb330a4 4822 0xfc000000, ERIAR_EXGMAC);
b8e5e6ad 4823 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
beb330a4 4824 break;
065c27c1 4825 }
4826}
4827
4828static void r8168_pll_power_up(struct rtl8169_private *tp)
4829{
4830 void __iomem *ioaddr = tp->mmio_addr;
4831
065c27c1 4832 switch (tp->mac_version) {
4833 case RTL_GIGA_MAC_VER_25:
4834 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 4835 case RTL_GIGA_MAC_VER_27:
4836 case RTL_GIGA_MAC_VER_28:
4804b3b3 4837 case RTL_GIGA_MAC_VER_31:
01dc7fec 4838 case RTL_GIGA_MAC_VER_32:
4839 case RTL_GIGA_MAC_VER_33:
065c27c1 4840 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4841 break;
42fde737 4842 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4843 case RTL_GIGA_MAC_VER_45:
4844 case RTL_GIGA_MAC_VER_46:
935e2218
CHL		 4845 case RTL_GIGA_MAC_VER_50:
4846 case RTL_GIGA_MAC_VER_51:
05b9687b 4847 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
6e1d0b89 4848 break;
beb330a4 4849 case RTL_GIGA_MAC_VER_40:
4850 case RTL_GIGA_MAC_VER_41:
935e2218 4851 case RTL_GIGA_MAC_VER_49:
b8e5e6ad 4852 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
706123d0 4853 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
beb330a4 4854 0x00000000, ERIAR_EXGMAC);
4855 break;
065c27c1 4856 }
4857
4858 r8168_phy_power_up(tp);
4859}
4860
d58d46b5
FR		 4861static void rtl_generic_op(struct rtl8169_private *tp,
4862 void (*op)(struct rtl8169_private *))
065c27c1 4863{
4864 if (op)
4865 op(tp);
4866}
4867
4868static void rtl_pll_power_down(struct rtl8169_private *tp)
4869{
d58d46b5 4870 rtl_generic_op(tp, tp->pll_power_ops.down);
065c27c1 4871}
4872
4873static void rtl_pll_power_up(struct rtl8169_private *tp)
4874{
d58d46b5 4875 rtl_generic_op(tp, tp->pll_power_ops.up);
065c27c1 4876}
4877
baf63293 4878static void rtl_init_pll_power_ops(struct rtl8169_private *tp)
065c27c1 4879{
4880 struct pll_power_ops *ops = &tp->pll_power_ops;
4881
4882 switch (tp->mac_version) {
4883 case RTL_GIGA_MAC_VER_07:
4884 case RTL_GIGA_MAC_VER_08:
4885 case RTL_GIGA_MAC_VER_09:
4886 case RTL_GIGA_MAC_VER_10:
4887 case RTL_GIGA_MAC_VER_16:
5a5e4443
HW		 4888 case RTL_GIGA_MAC_VER_29:
4889 case RTL_GIGA_MAC_VER_30:
7e18dca1 4890 case RTL_GIGA_MAC_VER_37:
5598bfe5 4891 case RTL_GIGA_MAC_VER_39:
58152cd4 4892 case RTL_GIGA_MAC_VER_43:
6e1d0b89
CHL		 4893 case RTL_GIGA_MAC_VER_47:
4894 case RTL_GIGA_MAC_VER_48:
065c27c1 4895 ops->down = r810x_pll_power_down;
4896 ops->up = r810x_pll_power_up;
4897 break;
4898
4899 case RTL_GIGA_MAC_VER_11:
4900 case RTL_GIGA_MAC_VER_12:
4901 case RTL_GIGA_MAC_VER_17:
4902 case RTL_GIGA_MAC_VER_18:
4903 case RTL_GIGA_MAC_VER_19:
4904 case RTL_GIGA_MAC_VER_20:
4905 case RTL_GIGA_MAC_VER_21:
4906 case RTL_GIGA_MAC_VER_22:
4907 case RTL_GIGA_MAC_VER_23:
4908 case RTL_GIGA_MAC_VER_24:
4909 case RTL_GIGA_MAC_VER_25:
4910 case RTL_GIGA_MAC_VER_26:
4911 case RTL_GIGA_MAC_VER_27:
e6de30d6 4912 case RTL_GIGA_MAC_VER_28:
4804b3b3 4913 case RTL_GIGA_MAC_VER_31:
01dc7fec 4914 case RTL_GIGA_MAC_VER_32:
4915 case RTL_GIGA_MAC_VER_33:
70090424 4916 case RTL_GIGA_MAC_VER_34:
c2218925
HW		 4917 case RTL_GIGA_MAC_VER_35:
4918 case RTL_GIGA_MAC_VER_36:
b3d7b2f2 4919 case RTL_GIGA_MAC_VER_38:
c558386b
HW		 4920 case RTL_GIGA_MAC_VER_40:
4921 case RTL_GIGA_MAC_VER_41:
57538c4a 4922 case RTL_GIGA_MAC_VER_42:
45dd95c4 4923 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4924 case RTL_GIGA_MAC_VER_45:
4925 case RTL_GIGA_MAC_VER_46:
935e2218
CHL		 4926 case RTL_GIGA_MAC_VER_49:
4927 case RTL_GIGA_MAC_VER_50:
4928 case RTL_GIGA_MAC_VER_51:
065c27c1 4929 ops->down = r8168_pll_power_down;
4930 ops->up = r8168_pll_power_up;
4931 break;
4932
4933 default:
4934 ops->down = NULL;
4935 ops->up = NULL;
4936 break;
4937 }
4938}
4939
e542a226
HW		 4940static void rtl_init_rxcfg(struct rtl8169_private *tp)
4941{
4942 void __iomem *ioaddr = tp->mmio_addr;
4943
4944 switch (tp->mac_version) {
4945 case RTL_GIGA_MAC_VER_01:
4946 case RTL_GIGA_MAC_VER_02:
4947 case RTL_GIGA_MAC_VER_03:
4948 case RTL_GIGA_MAC_VER_04:
4949 case RTL_GIGA_MAC_VER_05:
4950 case RTL_GIGA_MAC_VER_06:
4951 case RTL_GIGA_MAC_VER_10:
4952 case RTL_GIGA_MAC_VER_11:
4953 case RTL_GIGA_MAC_VER_12:
4954 case RTL_GIGA_MAC_VER_13:
4955 case RTL_GIGA_MAC_VER_14:
4956 case RTL_GIGA_MAC_VER_15:
4957 case RTL_GIGA_MAC_VER_16:
4958 case RTL_GIGA_MAC_VER_17:
4959 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4960 break;
4961 case RTL_GIGA_MAC_VER_18:
4962 case RTL_GIGA_MAC_VER_19:
4963 case RTL_GIGA_MAC_VER_20:
4964 case RTL_GIGA_MAC_VER_21:
4965 case RTL_GIGA_MAC_VER_22:
4966 case RTL_GIGA_MAC_VER_23:
4967 case RTL_GIGA_MAC_VER_24:
eb2dc35d 4968 case RTL_GIGA_MAC_VER_34:
3ced8c95 4969 case RTL_GIGA_MAC_VER_35:
e542a226
HW		 4970 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4971 break;
beb330a4 4972 case RTL_GIGA_MAC_VER_40:
4973 case RTL_GIGA_MAC_VER_41:
57538c4a 4974 case RTL_GIGA_MAC_VER_42:
58152cd4 4975 case RTL_GIGA_MAC_VER_43:
45dd95c4 4976 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4977 case RTL_GIGA_MAC_VER_45:
4978 case RTL_GIGA_MAC_VER_46:
4979 case RTL_GIGA_MAC_VER_47:
4980 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 4981 case RTL_GIGA_MAC_VER_49:
4982 case RTL_GIGA_MAC_VER_50:
4983 case RTL_GIGA_MAC_VER_51:
7ebc4822 4984 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
beb330a4 4985 break;
e542a226
HW		 4986 default:
4987 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
4988 break;
4989 }
4990}
4991
92fc43b4
HW		 4992static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4993{
9fba0812 4994 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
92fc43b4
HW		 4995}
4996
d58d46b5
FR		 4997static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4998{
9c5028e9 4999 void __iomem *ioaddr = tp->mmio_addr;
5000
5001 RTL_W8(Cfg9346, Cfg9346_Unlock);
d58d46b5 5002 rtl_generic_op(tp, tp->jumbo_ops.enable);
9c5028e9 5003 RTL_W8(Cfg9346, Cfg9346_Lock);
d58d46b5
FR		 5004}
5005
5006static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
5007{
9c5028e9 5008 void __iomem *ioaddr = tp->mmio_addr;
5009
5010 RTL_W8(Cfg9346, Cfg9346_Unlock);
d58d46b5 5011 rtl_generic_op(tp, tp->jumbo_ops.disable);
9c5028e9 5012 RTL_W8(Cfg9346, Cfg9346_Lock);
d58d46b5
FR		 5013}
5014
5015static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
5016{
5017 void __iomem *ioaddr = tp->mmio_addr;
5018
5019 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
5020 RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
f65d539c 5021 rtl_tx_performance_tweak(tp->pci_dev, PCI_EXP_DEVCTL_READRQ_512B);
d58d46b5
FR		 5022}
5023
5024static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
5025{
5026 void __iomem *ioaddr = tp->mmio_addr;
5027
5028 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
5029 RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
5030 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
5031}
5032
5033static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
5034{
5035 void __iomem *ioaddr = tp->mmio_addr;
5036
5037 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
5038}
5039
5040static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
5041{
5042 void __iomem *ioaddr = tp->mmio_addr;
5043
5044 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
5045}
5046
5047static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
5048{
5049 void __iomem *ioaddr = tp->mmio_addr;
d58d46b5
FR		 5050
5051 RTL_W8(MaxTxPacketSize, 0x3f);
5052 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
5053 RTL_W8(Config4, RTL_R8(Config4) | 0x01);
f65d539c 5054 rtl_tx_performance_tweak(tp->pci_dev, PCI_EXP_DEVCTL_READRQ_512B);
d58d46b5
FR		 5055}
5056
5057static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
5058{
5059 void __iomem *ioaddr = tp->mmio_addr;
d58d46b5
FR		 5060
5061 RTL_W8(MaxTxPacketSize, 0x0c);
5062 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
5063 RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
4512ff9f 5064 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
d58d46b5
FR		 5065}
5066
5067static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
5068{
5069 rtl_tx_performance_tweak(tp->pci_dev,
f65d539c 5070 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
d58d46b5
FR		 5071}
5072
5073static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
5074{
5075 rtl_tx_performance_tweak(tp->pci_dev,
5076 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
5077}
5078
5079static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
5080{
5081 void __iomem *ioaddr = tp->mmio_addr;
5082
5083 r8168b_0_hw_jumbo_enable(tp);
5084
5085 RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
5086}
5087
5088static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
5089{
5090 void __iomem *ioaddr = tp->mmio_addr;
5091
5092 r8168b_0_hw_jumbo_disable(tp);
5093
5094 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
5095}
5096
baf63293 5097static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
d58d46b5
FR		 5098{
5099 struct jumbo_ops *ops = &tp->jumbo_ops;
5100
5101 switch (tp->mac_version) {
5102 case RTL_GIGA_MAC_VER_11:
5103 ops->disable = r8168b_0_hw_jumbo_disable;
5104 ops->enable = r8168b_0_hw_jumbo_enable;
5105 break;
5106 case RTL_GIGA_MAC_VER_12:
5107 case RTL_GIGA_MAC_VER_17:
5108 ops->disable = r8168b_1_hw_jumbo_disable;
5109 ops->enable = r8168b_1_hw_jumbo_enable;
5110 break;
5111 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
5112 case RTL_GIGA_MAC_VER_19:
5113 case RTL_GIGA_MAC_VER_20:
5114 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
5115 case RTL_GIGA_MAC_VER_22:
5116 case RTL_GIGA_MAC_VER_23:
5117 case RTL_GIGA_MAC_VER_24:
5118 case RTL_GIGA_MAC_VER_25:
5119 case RTL_GIGA_MAC_VER_26:
5120 ops->disable = r8168c_hw_jumbo_disable;
5121 ops->enable = r8168c_hw_jumbo_enable;
5122 break;
5123 case RTL_GIGA_MAC_VER_27:
5124 case RTL_GIGA_MAC_VER_28:
5125 ops->disable = r8168dp_hw_jumbo_disable;
5126 ops->enable = r8168dp_hw_jumbo_enable;
5127 break;
5128 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
5129 case RTL_GIGA_MAC_VER_32:
5130 case RTL_GIGA_MAC_VER_33:
5131 case RTL_GIGA_MAC_VER_34:
5132 ops->disable = r8168e_hw_jumbo_disable;
5133 ops->enable = r8168e_hw_jumbo_enable;
5134 break;
5135
5136 /*
5137 * No action needed for jumbo frames with 8169.
5138 * No jumbo for 810x at all.
5139 */
c558386b
HW		 5140 case RTL_GIGA_MAC_VER_40:
5141 case RTL_GIGA_MAC_VER_41:
57538c4a 5142 case RTL_GIGA_MAC_VER_42:
58152cd4 5143 case RTL_GIGA_MAC_VER_43:
45dd95c4 5144 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 5145 case RTL_GIGA_MAC_VER_45:
5146 case RTL_GIGA_MAC_VER_46:
5147 case RTL_GIGA_MAC_VER_47:
5148 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 5149 case RTL_GIGA_MAC_VER_49:
5150 case RTL_GIGA_MAC_VER_50:
5151 case RTL_GIGA_MAC_VER_51:
d58d46b5
FR		 5152 default:
5153 ops->disable = NULL;
5154 ops->enable = NULL;
5155 break;
5156 }
5157}
5158
ffc46952
FR		 5159DECLARE_RTL_COND(rtl_chipcmd_cond)
5160{
5161 void __iomem *ioaddr = tp->mmio_addr;
5162
5163 return RTL_R8(ChipCmd) & CmdReset;
5164}
5165
6f43adc8
FR		 5166static void rtl_hw_reset(struct rtl8169_private *tp)
5167{
5168 void __iomem *ioaddr = tp->mmio_addr;
6f43adc8 5169
6f43adc8
FR		 5170 RTL_W8(ChipCmd, CmdReset);
5171
ffc46952 5172 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
6f43adc8
FR		 5173}
5174
b6ffd97f 5175static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
953a12cc 5176{
b6ffd97f
FR		 5177 struct rtl_fw *rtl_fw;
5178 const char *name;
5179 int rc = -ENOMEM;
953a12cc 5180
b6ffd97f
FR		 5181 name = rtl_lookup_firmware_name(tp);
5182 if (!name)
5183 goto out_no_firmware;
953a12cc 5184
b6ffd97f
FR		 5185 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
5186 if (!rtl_fw)
5187 goto err_warn;
31bd204f 5188
b6ffd97f
FR		 5189 rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
5190 if (rc < 0)
5191 goto err_free;
5192
fd112f2e
FR		 5193 rc = rtl_check_firmware(tp, rtl_fw);
5194 if (rc < 0)
5195 goto err_release_firmware;
5196
b6ffd97f
FR		 5197 tp->rtl_fw = rtl_fw;
5198out:
5199 return;
5200
fd112f2e
FR		 5201err_release_firmware:
5202 release_firmware(rtl_fw->fw);
b6ffd97f
FR		 5203err_free:
5204 kfree(rtl_fw);
5205err_warn:
5206 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
5207 name, rc);
5208out_no_firmware:
5209 tp->rtl_fw = NULL;
5210 goto out;
5211}
5212
5213static void rtl_request_firmware(struct rtl8169_private *tp)
5214{
5215 if (IS_ERR(tp->rtl_fw))
5216 rtl_request_uncached_firmware(tp);
953a12cc
FR		 5217}
5218
92fc43b4
HW		 5219static void rtl_rx_close(struct rtl8169_private *tp)
5220{
5221 void __iomem *ioaddr = tp->mmio_addr;
92fc43b4 5222
1687b566 5223 RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
92fc43b4
HW		 5224}
5225
ffc46952
FR		 5226DECLARE_RTL_COND(rtl_npq_cond)
5227{
5228 void __iomem *ioaddr = tp->mmio_addr;
5229
5230 return RTL_R8(TxPoll) & NPQ;
5231}
5232
5233DECLARE_RTL_COND(rtl_txcfg_empty_cond)
5234{
5235 void __iomem *ioaddr = tp->mmio_addr;
5236
5237 return RTL_R32(TxConfig) & TXCFG_EMPTY;
5238}
5239
e6de30d6 5240static void rtl8169_hw_reset(struct rtl8169_private *tp)
1da177e4 5241{
e6de30d6 5242 void __iomem *ioaddr = tp->mmio_addr;
5243
1da177e4 5244 /* Disable interrupts */
811fd301 5245 rtl8169_irq_mask_and_ack(tp);
1da177e4 5246
92fc43b4
HW		 5247 rtl_rx_close(tp);
5248
5d2e1957 5249 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4804b3b3 5250 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
5251 tp->mac_version == RTL_GIGA_MAC_VER_31) {
ffc46952 5252 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
c2218925 5253 } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
6e1d0b89
CHL		 5254 tp->mac_version == RTL_GIGA_MAC_VER_35 ||
5255 tp->mac_version == RTL_GIGA_MAC_VER_36 ||
5256 tp->mac_version == RTL_GIGA_MAC_VER_37 ||
5257 tp->mac_version == RTL_GIGA_MAC_VER_38 ||
5258 tp->mac_version == RTL_GIGA_MAC_VER_40 ||
5259 tp->mac_version == RTL_GIGA_MAC_VER_41 ||
5260 tp->mac_version == RTL_GIGA_MAC_VER_42 ||
5261 tp->mac_version == RTL_GIGA_MAC_VER_43 ||
5262 tp->mac_version == RTL_GIGA_MAC_VER_44 ||
5263 tp->mac_version == RTL_GIGA_MAC_VER_45 ||
5264 tp->mac_version == RTL_GIGA_MAC_VER_46 ||
5265 tp->mac_version == RTL_GIGA_MAC_VER_47 ||
935e2218
CHL		 5266 tp->mac_version == RTL_GIGA_MAC_VER_48 ||
5267 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
5268 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
5269 tp->mac_version == RTL_GIGA_MAC_VER_51) {
c2b0c1e7 5270 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
ffc46952 5271 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
92fc43b4
HW		 5272 } else {
5273 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
5274 udelay(100);
e6de30d6 5275 }
5276
92fc43b4 5277 rtl_hw_reset(tp);
1da177e4
LT		 5278}
5279
7f796d83 5280static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 5281{
5282 void __iomem *ioaddr = tp->mmio_addr;
9cb427b6
FR		 5283
5284 /* Set DMA burst size and Interframe Gap Time */
5285 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
5286 (InterFrameGap << TxInterFrameGapShift));
5287}
5288
07ce4064 5289static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 5290{
5291 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 5292
07ce4064
FR		 5293 tp->hw_start(dev);
5294
da78dbff 5295 rtl_irq_enable_all(tp);
07ce4064
FR		 5296}
5297
7f796d83
FR		 5298static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
5299 void __iomem *ioaddr)
5300{
5301 /*
5302 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
5303 * register to be written before TxDescAddrLow to work.
5304 * Switching from MMIO to I/O access fixes the issue as well.
5305 */
5306 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
284901a9 5307 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
7f796d83 5308 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
284901a9 5309 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 5310}
5311
5312static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
5313{
5314 u16 cmd;
5315
5316 cmd = RTL_R16(CPlusCmd);
5317 RTL_W16(CPlusCmd, cmd);
5318 return cmd;
5319}
5320
fdd7b4c3 5321static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
7f796d83
FR		 5322{
5323 /* Low hurts. Let's disable the filtering. */
207d6e87 5324 RTL_W16(RxMaxSize, rx_buf_sz + 1);
7f796d83
FR		 5325}
5326
6dccd16b
FR		 5327static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
5328{
3744100e 5329 static const struct rtl_cfg2_info {
6dccd16b
FR		 5330 u32 mac_version;
5331 u32 clk;
5332 u32 val;
5333 } cfg2_info [] = {
5334 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
5335 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
5336 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
5337 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3744100e
FR		 5338 };
5339 const struct rtl_cfg2_info *p = cfg2_info;
6dccd16b
FR		 5340 unsigned int i;
5341 u32 clk;
5342
5343 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 5344 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 5345 if ((p->mac_version == mac_version) && (p->clk == clk)) {
5346 RTL_W32(0x7c, p->val);
5347 break;
5348 }
5349 }
5350}
5351
e6b763ea
FR		 5352static void rtl_set_rx_mode(struct net_device *dev)
5353{
5354 struct rtl8169_private *tp = netdev_priv(dev);
5355 void __iomem *ioaddr = tp->mmio_addr;
5356 u32 mc_filter[2]; /* Multicast hash filter */
5357 int rx_mode;
5358 u32 tmp = 0;
5359
5360 if (dev->flags & IFF_PROMISC) {
5361 /* Unconditionally log net taps. */
5362 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
5363 rx_mode =
5364 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5365 AcceptAllPhys;
5366 mc_filter[1] = mc_filter[0] = 0xffffffff;
5367 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
5368 (dev->flags & IFF_ALLMULTI)) {
5369 /* Too many to filter perfectly -- accept all multicasts. */
5370 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5371 mc_filter[1] = mc_filter[0] = 0xffffffff;
5372 } else {
5373 struct netdev_hw_addr *ha;
5374
5375 rx_mode = AcceptBroadcast | AcceptMyPhys;
5376 mc_filter[1] = mc_filter[0] = 0;
5377 netdev_for_each_mc_addr(ha, dev) {
5378 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
5379 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5380 rx_mode |= AcceptMulticast;
5381 }
5382 }
5383
5384 if (dev->features & NETIF_F_RXALL)
5385 rx_mode |= (AcceptErr | AcceptRunt);
5386
5387 tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
5388
5389 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
5390 u32 data = mc_filter[0];
5391
5392 mc_filter[0] = swab32(mc_filter[1]);
5393 mc_filter[1] = swab32(data);
5394 }
5395
0481776b
NW		 5396 if (tp->mac_version == RTL_GIGA_MAC_VER_35)
5397 mc_filter[1] = mc_filter[0] = 0xffffffff;
5398
e6b763ea
FR		 5399 RTL_W32(MAR0 + 4, mc_filter[1]);
5400 RTL_W32(MAR0 + 0, mc_filter[0]);
5401
5402 RTL_W32(RxConfig, tmp);
5403}
5404
07ce4064
FR		 5405static void rtl_hw_start_8169(struct net_device *dev)
5406{
5407 struct rtl8169_private *tp = netdev_priv(dev);
5408 void __iomem *ioaddr = tp->mmio_addr;
5409 struct pci_dev *pdev = tp->pci_dev;
07ce4064 5410
9cb427b6
FR		 5411 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
5412 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
5413 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
5414 }
5415
1da177e4 5416 RTL_W8(Cfg9346, Cfg9346_Unlock);
cecb5fd7
FR		 5417 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
5418 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5419 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
5420 tp->mac_version == RTL_GIGA_MAC_VER_04)
9cb427b6
FR		 5421 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5422
e542a226
HW		 5423 rtl_init_rxcfg(tp);
5424
f0298f81 5425 RTL_W8(EarlyTxThres, NoEarlyTx);
1da177e4 5426
6f0333b8 5427 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
1da177e4 5428
cecb5fd7
FR		 5429 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
5430 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5431 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
5432 tp->mac_version == RTL_GIGA_MAC_VER_04)
c946b304 5433 rtl_set_rx_tx_config_registers(tp);
1da177e4 5434
7f796d83 5435 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 5436
cecb5fd7
FR		 5437 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5438 tp->mac_version == RTL_GIGA_MAC_VER_03) {
05b9687b 5439 dprintk("Set MAC Reg C+CR Offset 0xe0. "
1da177e4 5440 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 5441 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 5442 }
5443
bcf0bf90
FR		 5444 RTL_W16(CPlusCmd, tp->cp_cmd);
5445
6dccd16b
FR		 5446 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
5447
1da177e4
LT		 5448 /*
5449 * Undocumented corner. Supposedly:
5450 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
5451 */
5452 RTL_W16(IntrMitigate, 0x0000);
5453
7f796d83 5454 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 5455
cecb5fd7
FR		 5456 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
5457 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
5458 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
5459 tp->mac_version != RTL_GIGA_MAC_VER_04) {
c946b304
FR		 5460 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5461 rtl_set_rx_tx_config_registers(tp);
5462 }
5463
1da177e4 5464 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 5465
5466 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
5467 RTL_R8(IntrMask);
1da177e4
LT		 5468
5469 RTL_W32(RxMissed, 0);
5470
07ce4064 5471 rtl_set_rx_mode(dev);
1da177e4
LT		 5472
5473 /* no early-rx interrupts */
05b9687b 5474 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
07ce4064 5475}
1da177e4 5476
beb1fe18
HW		 5477static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
5478{
5479 if (tp->csi_ops.write)
52989f0e 5480 tp->csi_ops.write(tp, addr, value);
beb1fe18
HW		 5481}
5482
5483static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
5484{
52989f0e 5485 return tp->csi_ops.read ? tp->csi_ops.read(tp, addr) : ~0;
beb1fe18
HW		 5486}
5487
5488static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits)
dacf8154
FR		 5489{
5490 u32 csi;
5491
beb1fe18
HW		 5492 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
5493 rtl_csi_write(tp, 0x070c, csi | bits);
5494}
5495
5496static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
5497{
5498 rtl_csi_access_enable(tp, 0x17000000);
650e8d5d 5499}
5500
beb1fe18 5501static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
e6de30d6 5502{
beb1fe18 5503 rtl_csi_access_enable(tp, 0x27000000);
e6de30d6 5504}
5505
ffc46952
FR		 5506DECLARE_RTL_COND(rtl_csiar_cond)
5507{
5508 void __iomem *ioaddr = tp->mmio_addr;
5509
5510 return RTL_R32(CSIAR) & CSIAR_FLAG;
5511}
5512
52989f0e 5513static void r8169_csi_write(struct rtl8169_private *tp, int addr, int value)
650e8d5d 5514{
52989f0e 5515 void __iomem *ioaddr = tp->mmio_addr;
beb1fe18
HW		 5516
5517 RTL_W32(CSIDR, value);
5518 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5519 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5520
ffc46952 5521 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
beb1fe18
HW		 5522}
5523
52989f0e 5524static u32 r8169_csi_read(struct rtl8169_private *tp, int addr)
beb1fe18 5525{
52989f0e 5526 void __iomem *ioaddr = tp->mmio_addr;
beb1fe18
HW		 5527
5528 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
5529 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5530
ffc46952
FR		 5531 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5532 RTL_R32(CSIDR) : ~0;
beb1fe18
HW		 5533}
5534
52989f0e 5535static void r8402_csi_write(struct rtl8169_private *tp, int addr, int value)
7e18dca1 5536{
52989f0e 5537 void __iomem *ioaddr = tp->mmio_addr;
7e18dca1
HW		 5538
5539 RTL_W32(CSIDR, value);
5540 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5541 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
5542 CSIAR_FUNC_NIC);
5543
ffc46952 5544 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
7e18dca1
HW		 5545}
5546
52989f0e 5547static u32 r8402_csi_read(struct rtl8169_private *tp, int addr)
7e18dca1 5548{
52989f0e 5549 void __iomem *ioaddr = tp->mmio_addr;
7e18dca1
HW		 5550
5551 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
5552 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5553
ffc46952
FR		 5554 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5555 RTL_R32(CSIDR) : ~0;
7e18dca1
HW		 5556}
5557
45dd95c4 5558static void r8411_csi_write(struct rtl8169_private *tp, int addr, int value)
5559{
5560 void __iomem *ioaddr = tp->mmio_addr;
5561
5562 RTL_W32(CSIDR, value);
5563 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5564 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
5565 CSIAR_FUNC_NIC2);
5566
5567 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5568}
5569
5570static u32 r8411_csi_read(struct rtl8169_private *tp, int addr)
5571{
5572 void __iomem *ioaddr = tp->mmio_addr;
5573
5574 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC2 |
5575 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5576
5577 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5578 RTL_R32(CSIDR) : ~0;
5579}
5580
baf63293 5581static void rtl_init_csi_ops(struct rtl8169_private *tp)
beb1fe18
HW		 5582{
5583 struct csi_ops *ops = &tp->csi_ops;
5584
5585 switch (tp->mac_version) {
5586 case RTL_GIGA_MAC_VER_01:
5587 case RTL_GIGA_MAC_VER_02:
5588 case RTL_GIGA_MAC_VER_03:
5589 case RTL_GIGA_MAC_VER_04:
5590 case RTL_GIGA_MAC_VER_05:
5591 case RTL_GIGA_MAC_VER_06:
5592 case RTL_GIGA_MAC_VER_10:
5593 case RTL_GIGA_MAC_VER_11:
5594 case RTL_GIGA_MAC_VER_12:
5595 case RTL_GIGA_MAC_VER_13:
5596 case RTL_GIGA_MAC_VER_14:
5597 case RTL_GIGA_MAC_VER_15:
5598 case RTL_GIGA_MAC_VER_16:
5599 case RTL_GIGA_MAC_VER_17:
5600 ops->write = NULL;
5601 ops->read = NULL;
5602 break;
5603
7e18dca1 5604 case RTL_GIGA_MAC_VER_37:
b3d7b2f2 5605 case RTL_GIGA_MAC_VER_38:
7e18dca1
HW		 5606 ops->write = r8402_csi_write;
5607 ops->read = r8402_csi_read;
5608 break;
5609
45dd95c4 5610 case RTL_GIGA_MAC_VER_44:
5611 ops->write = r8411_csi_write;
5612 ops->read = r8411_csi_read;
5613 break;
5614
beb1fe18
HW		 5615 default:
5616 ops->write = r8169_csi_write;
5617 ops->read = r8169_csi_read;
5618 break;
5619 }
dacf8154
FR		 5620}
5621
5622struct ephy_info {
5623 unsigned int offset;
5624 u16 mask;
5625 u16 bits;
5626};
5627
fdf6fc06
FR		 5628static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
5629 int len)
dacf8154
FR		 5630{
5631 u16 w;
5632
5633 while (len-- > 0) {
fdf6fc06
FR		 5634 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
5635 rtl_ephy_write(tp, e->offset, w);
dacf8154
FR		 5636 e++;
5637 }
5638}
5639
b726e493
FR		 5640static void rtl_disable_clock_request(struct pci_dev *pdev)
5641{
7d7903b2
JL		 5642 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
5643 PCI_EXP_LNKCTL_CLKREQ_EN);
b726e493
FR		 5644}
5645
e6de30d6 5646static void rtl_enable_clock_request(struct pci_dev *pdev)
5647{
7d7903b2
JL		 5648 pcie_capability_set_word(pdev, PCI_EXP_LNKCTL,
5649 PCI_EXP_LNKCTL_CLKREQ_EN);
e6de30d6 5650}
5651
b51ecea8 5652static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable)
5653{
5654 void __iomem *ioaddr = tp->mmio_addr;
5655 u8 data;
5656
5657 data = RTL_R8(Config3);
5658
5659 if (enable)
5660 data |= Rdy_to_L23;
5661 else
5662 data &= ~Rdy_to_L23;
5663
5664 RTL_W8(Config3, data);
5665}
5666
b726e493
FR		 5667#define R8168_CPCMD_QUIRK_MASK (\
5668 EnableBist | \
5669 Mac_dbgo_oe | \
5670 Force_half_dup | \
5671 Force_rxflow_en | \
5672 Force_txflow_en | \
5673 Cxpl_dbg_sel | \
5674 ASF | \
5675 PktCntrDisable | \
5676 Mac_dbgo_sel)
5677
beb1fe18 5678static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
219a1e9d 5679{
beb1fe18
HW		 5680 void __iomem *ioaddr = tp->mmio_addr;
5681 struct pci_dev *pdev = tp->pci_dev;
5682
b726e493
FR		 5683 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5684
5685 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5686
faf1e785 5687 if (tp->dev->mtu <= ETH_DATA_LEN) {
5688 rtl_tx_performance_tweak(pdev, (0x5 << MAX_READ_REQUEST_SHIFT) |
5689 PCI_EXP_DEVCTL_NOSNOOP_EN);
5690 }
219a1e9d
FR		 5691}
5692
beb1fe18 5693static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
219a1e9d 5694{
beb1fe18
HW		 5695 void __iomem *ioaddr = tp->mmio_addr;
5696
5697 rtl_hw_start_8168bb(tp);
b726e493 5698
f0298f81 5699 RTL_W8(MaxTxPacketSize, TxPacketMax);
b726e493
FR		 5700
5701 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
219a1e9d
FR		 5702}
5703
beb1fe18 5704static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
219a1e9d 5705{
beb1fe18
HW		 5706 void __iomem *ioaddr = tp->mmio_addr;
5707 struct pci_dev *pdev = tp->pci_dev;
5708
b726e493
FR		 5709 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
5710
5711 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5712
faf1e785 5713 if (tp->dev->mtu <= ETH_DATA_LEN)
5714 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
b726e493
FR		 5715
5716 rtl_disable_clock_request(pdev);
5717
5718 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
219a1e9d
FR		 5719}
5720
beb1fe18 5721static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
219a1e9d 5722{
350f7596 5723 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 5724 { 0x01, 0, 0x0001 },
5725 { 0x02, 0x0800, 0x1000 },
5726 { 0x03, 0, 0x0042 },
5727 { 0x06, 0x0080, 0x0000 },
5728 { 0x07, 0, 0x2000 }
5729 };
5730
beb1fe18 5731 rtl_csi_access_enable_2(tp);
b726e493 5732
fdf6fc06 5733 rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
b726e493 5734
beb1fe18 5735 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 5736}
5737
beb1fe18 5738static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
ef3386f0 5739{
beb1fe18
HW		 5740 void __iomem *ioaddr = tp->mmio_addr;
5741 struct pci_dev *pdev = tp->pci_dev;
5742
5743 rtl_csi_access_enable_2(tp);
ef3386f0
FR		 5744
5745 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5746
faf1e785 5747 if (tp->dev->mtu <= ETH_DATA_LEN)
5748 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
ef3386f0
FR		 5749
5750 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5751}
5752
beb1fe18 5753static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
7f3e3d3a 5754{
beb1fe18
HW		 5755 void __iomem *ioaddr = tp->mmio_addr;
5756 struct pci_dev *pdev = tp->pci_dev;
5757
5758 rtl_csi_access_enable_2(tp);
7f3e3d3a
FR		 5759
5760 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5761
5762 /* Magic. */
5763 RTL_W8(DBG_REG, 0x20);
5764
f0298f81 5765 RTL_W8(MaxTxPacketSize, TxPacketMax);
7f3e3d3a 5766
faf1e785 5767 if (tp->dev->mtu <= ETH_DATA_LEN)
5768 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
7f3e3d3a
FR		 5769
5770 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5771}
5772
beb1fe18 5773static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
219a1e9d 5774{
beb1fe18 5775 void __iomem *ioaddr = tp->mmio_addr;
350f7596 5776 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 5777 { 0x02, 0x0800, 0x1000 },
5778 { 0x03, 0, 0x0002 },
5779 { 0x06, 0x0080, 0x0000 }
5780 };
5781
beb1fe18 5782 rtl_csi_access_enable_2(tp);
b726e493
FR		 5783
5784 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
5785
fdf6fc06 5786 rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
b726e493 5787
beb1fe18 5788 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 5789}
5790
beb1fe18 5791static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
219a1e9d 5792{
350f7596 5793 static const struct ephy_info e_info_8168c_2[] = {
b726e493
FR		 5794 { 0x01, 0, 0x0001 },
5795 { 0x03, 0x0400, 0x0220 }
5796 };
5797
beb1fe18 5798 rtl_csi_access_enable_2(tp);
b726e493 5799
fdf6fc06 5800 rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
b726e493 5801
beb1fe18 5802 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 5803}
5804
beb1fe18 5805static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
197ff761 5806{
beb1fe18 5807 rtl_hw_start_8168c_2(tp);
197ff761
FR		 5808}
5809
beb1fe18 5810static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
6fb07058 5811{
beb1fe18 5812 rtl_csi_access_enable_2(tp);
6fb07058 5813
beb1fe18 5814 __rtl_hw_start_8168cp(tp);
6fb07058
FR		 5815}
5816
beb1fe18 5817static void rtl_hw_start_8168d(struct rtl8169_private *tp)
5b538df9 5818{
beb1fe18
HW		 5819 void __iomem *ioaddr = tp->mmio_addr;
5820 struct pci_dev *pdev = tp->pci_dev;
5821
5822 rtl_csi_access_enable_2(tp);
5b538df9
FR		 5823
5824 rtl_disable_clock_request(pdev);
5825
f0298f81 5826 RTL_W8(MaxTxPacketSize, TxPacketMax);
5b538df9 5827
faf1e785 5828 if (tp->dev->mtu <= ETH_DATA_LEN)
5829 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5b538df9
FR		 5830
5831 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5832}
5833
beb1fe18 5834static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4804b3b3 5835{
beb1fe18
HW		 5836 void __iomem *ioaddr = tp->mmio_addr;
5837 struct pci_dev *pdev = tp->pci_dev;
5838
5839 rtl_csi_access_enable_1(tp);
4804b3b3 5840
faf1e785 5841 if (tp->dev->mtu <= ETH_DATA_LEN)
5842 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4804b3b3 5843
5844 RTL_W8(MaxTxPacketSize, TxPacketMax);
5845
5846 rtl_disable_clock_request(pdev);
5847}
5848
beb1fe18 5849static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
e6de30d6 5850{
beb1fe18
HW		 5851 void __iomem *ioaddr = tp->mmio_addr;
5852 struct pci_dev *pdev = tp->pci_dev;
e6de30d6 5853 static const struct ephy_info e_info_8168d_4[] = {
1016a4a1
CHL		 5854 { 0x0b, 0x0000, 0x0048 },
5855 { 0x19, 0x0020, 0x0050 },
5856 { 0x0c, 0x0100, 0x0020 }
e6de30d6 5857 };
e6de30d6 5858
beb1fe18 5859 rtl_csi_access_enable_1(tp);
e6de30d6 5860
5861 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5862
5863 RTL_W8(MaxTxPacketSize, TxPacketMax);
5864
1016a4a1 5865 rtl_ephy_init(tp, e_info_8168d_4, ARRAY_SIZE(e_info_8168d_4));
e6de30d6 5866
5867 rtl_enable_clock_request(pdev);
5868}
5869
beb1fe18 5870static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
01dc7fec 5871{
beb1fe18
HW		 5872 void __iomem *ioaddr = tp->mmio_addr;
5873 struct pci_dev *pdev = tp->pci_dev;
70090424 5874 static const struct ephy_info e_info_8168e_1[] = {
01dc7fec 5875 { 0x00, 0x0200, 0x0100 },
5876 { 0x00, 0x0000, 0x0004 },
5877 { 0x06, 0x0002, 0x0001 },
5878 { 0x06, 0x0000, 0x0030 },
5879 { 0x07, 0x0000, 0x2000 },
5880 { 0x00, 0x0000, 0x0020 },
5881 { 0x03, 0x5800, 0x2000 },
5882 { 0x03, 0x0000, 0x0001 },
5883 { 0x01, 0x0800, 0x1000 },
5884 { 0x07, 0x0000, 0x4000 },
5885 { 0x1e, 0x0000, 0x2000 },
5886 { 0x19, 0xffff, 0xfe6c },
5887 { 0x0a, 0x0000, 0x0040 }
5888 };
5889
beb1fe18 5890 rtl_csi_access_enable_2(tp);
01dc7fec 5891
fdf6fc06 5892 rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
01dc7fec 5893
faf1e785 5894 if (tp->dev->mtu <= ETH_DATA_LEN)
5895 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
01dc7fec 5896
5897 RTL_W8(MaxTxPacketSize, TxPacketMax);
5898
5899 rtl_disable_clock_request(pdev);
5900
5901 /* Reset tx FIFO pointer */
cecb5fd7
FR		 5902 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
5903 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
01dc7fec 5904
cecb5fd7 5905 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
01dc7fec 5906}
5907
beb1fe18 5908static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
70090424 5909{
beb1fe18
HW		 5910 void __iomem *ioaddr = tp->mmio_addr;
5911 struct pci_dev *pdev = tp->pci_dev;
70090424
HW		 5912 static const struct ephy_info e_info_8168e_2[] = {
5913 { 0x09, 0x0000, 0x0080 },
5914 { 0x19, 0x0000, 0x0224 }
5915 };
5916
beb1fe18 5917 rtl_csi_access_enable_1(tp);
70090424 5918
fdf6fc06 5919 rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
70090424 5920
faf1e785 5921 if (tp->dev->mtu <= ETH_DATA_LEN)
5922 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
70090424 5923
fdf6fc06
FR		 5924 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5925 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5926 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5927 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5928 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5929 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
706123d0
CHL		 5930 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5931 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
70090424 5932
3090bd9a 5933 RTL_W8(MaxTxPacketSize, EarlySize);
70090424 5934
4521e1a9
FR		 5935 rtl_disable_clock_request(pdev);
5936
70090424
HW		 5937 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5938 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5939
5940 /* Adjust EEE LED frequency */
5941 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5942
5943 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5944 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4521e1a9 5945 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
70090424
HW		 5946}
5947
5f886e08 5948static void rtl_hw_start_8168f(struct rtl8169_private *tp)
c2218925 5949{
beb1fe18
HW		 5950 void __iomem *ioaddr = tp->mmio_addr;
5951 struct pci_dev *pdev = tp->pci_dev;
c2218925 5952
5f886e08 5953 rtl_csi_access_enable_2(tp);
c2218925
HW		 5954
5955 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5956
fdf6fc06
FR		 5957 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5958 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5959 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5960 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
706123d0
CHL		 5961 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5962 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5963 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5964 rtl_w0w1_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
fdf6fc06
FR		 5965 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5966 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
c2218925
HW		 5967
5968 RTL_W8(MaxTxPacketSize, EarlySize);
5969
4521e1a9
FR		 5970 rtl_disable_clock_request(pdev);
5971
c2218925
HW		 5972 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5973 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
c2218925 5974 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4521e1a9
FR		 5975 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5976 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
c2218925
HW		 5977}
5978
5f886e08
HW		 5979static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5980{
5981 void __iomem *ioaddr = tp->mmio_addr;
5982 static const struct ephy_info e_info_8168f_1[] = {
5983 { 0x06, 0x00c0, 0x0020 },
5984 { 0x08, 0x0001, 0x0002 },
5985 { 0x09, 0x0000, 0x0080 },
5986 { 0x19, 0x0000, 0x0224 }
5987 };
5988
5989 rtl_hw_start_8168f(tp);
5990
fdf6fc06 5991 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5f886e08 5992
706123d0 5993 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5f886e08
HW		 5994
5995 /* Adjust EEE LED frequency */
5996 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5997}
5998
b3d7b2f2
HW		 5999static void rtl_hw_start_8411(struct rtl8169_private *tp)
6000{
b3d7b2f2
HW		 6001 static const struct ephy_info e_info_8168f_1[] = {
6002 { 0x06, 0x00c0, 0x0020 },
6003 { 0x0f, 0xffff, 0x5200 },
6004 { 0x1e, 0x0000, 0x4000 },
6005 { 0x19, 0x0000, 0x0224 }
6006 };
6007
6008 rtl_hw_start_8168f(tp);
b51ecea8 6009 rtl_pcie_state_l2l3_enable(tp, false);
b3d7b2f2 6010
fdf6fc06 6011 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
b3d7b2f2 6012
706123d0 6013 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
b3d7b2f2
HW		 6014}
6015
5fbea337 6016static void rtl_hw_start_8168g(struct rtl8169_private *tp)
c558386b
HW		 6017{
6018 void __iomem *ioaddr = tp->mmio_addr;
6019 struct pci_dev *pdev = tp->pci_dev;
6020
beb330a4 6021 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6022
c558386b
HW		 6023 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
6024 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
6025 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
6026 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6027
6028 rtl_csi_access_enable_1(tp);
6029
6030 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6031
706123d0
CHL		 6032 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6033 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
beb330a4 6034 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
c558386b 6035
4521e1a9 6036 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
c558386b
HW		 6037 RTL_W8(MaxTxPacketSize, EarlySize);
6038
6039 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6040 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6041
6042 /* Adjust EEE LED frequency */
6043 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6044
706123d0
CHL		 6045 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
6046 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
b51ecea8 6047
6048 rtl_pcie_state_l2l3_enable(tp, false);
c558386b
HW		 6049}
6050
5fbea337
CHL		 6051static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
6052{
6053 void __iomem *ioaddr = tp->mmio_addr;
6054 static const struct ephy_info e_info_8168g_1[] = {
6055 { 0x00, 0x0000, 0x0008 },
6056 { 0x0c, 0x37d0, 0x0820 },
6057 { 0x1e, 0x0000, 0x0001 },
6058 { 0x19, 0x8000, 0x0000 }
6059 };
6060
6061 rtl_hw_start_8168g(tp);
6062
6063 /* disable aspm and clock request before access ephy */
6064 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6065 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6066 rtl_ephy_init(tp, e_info_8168g_1, ARRAY_SIZE(e_info_8168g_1));
6067}
6068
57538c4a 6069static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
6070{
6071 void __iomem *ioaddr = tp->mmio_addr;
6072 static const struct ephy_info e_info_8168g_2[] = {
6073 { 0x00, 0x0000, 0x0008 },
6074 { 0x0c, 0x3df0, 0x0200 },
6075 { 0x19, 0xffff, 0xfc00 },
6076 { 0x1e, 0xffff, 0x20eb }
6077 };
6078
5fbea337 6079 rtl_hw_start_8168g(tp);
57538c4a 6080
6081 /* disable aspm and clock request before access ephy */
6082 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6083 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6084 rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
6085}
6086
45dd95c4 6087static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
6088{
6089 void __iomem *ioaddr = tp->mmio_addr;
6090 static const struct ephy_info e_info_8411_2[] = {
6091 { 0x00, 0x0000, 0x0008 },
6092 { 0x0c, 0x3df0, 0x0200 },
6093 { 0x0f, 0xffff, 0x5200 },
6094 { 0x19, 0x0020, 0x0000 },
6095 { 0x1e, 0x0000, 0x2000 }
6096 };
6097
5fbea337 6098 rtl_hw_start_8168g(tp);
45dd95c4 6099
6100 /* disable aspm and clock request before access ephy */
6101 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6102 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6103 rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
6104}
6105
6e1d0b89
CHL		 6106static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
6107{
6108 void __iomem *ioaddr = tp->mmio_addr;
6109 struct pci_dev *pdev = tp->pci_dev;
72521ea0 6110 int rg_saw_cnt;
6e1d0b89
CHL		 6111 u32 data;
6112 static const struct ephy_info e_info_8168h_1[] = {
6113 { 0x1e, 0x0800, 0x0001 },
6114 { 0x1d, 0x0000, 0x0800 },
6115 { 0x05, 0xffff, 0x2089 },
6116 { 0x06, 0xffff, 0x5881 },
6117 { 0x04, 0xffff, 0x154a },
6118 { 0x01, 0xffff, 0x068b }
6119 };
6120
6121 /* disable aspm and clock request before access ephy */
6122 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6123 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6124 rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));
6125
6126 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6127
6128 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
6129 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
6130 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
6131 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6132
6133 rtl_csi_access_enable_1(tp);
6134
6135 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6136
706123d0
CHL		 6137 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6138 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6e1d0b89 6139
706123d0 6140 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);
6e1d0b89 6141
706123d0 6142 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);
6e1d0b89
CHL		 6143
6144 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
6145
6e1d0b89
CHL		 6146 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
6147 RTL_W8(MaxTxPacketSize, EarlySize);
6148
6149 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6150 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6151
6152 /* Adjust EEE LED frequency */
6153 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6154
6155 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
69f3dc37 6156 RTL_W8(MISC_1, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
6e1d0b89
CHL		 6157
6158 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~TX_10M_PS_EN);
6159
706123d0 6160 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
6e1d0b89
CHL		 6161
6162 rtl_pcie_state_l2l3_enable(tp, false);
6163
6164 rtl_writephy(tp, 0x1f, 0x0c42);
58493333 6165 rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
6e1d0b89
CHL		 6166 rtl_writephy(tp, 0x1f, 0x0000);
6167 if (rg_saw_cnt > 0) {
6168 u16 sw_cnt_1ms_ini;
6169
6170 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
6171 sw_cnt_1ms_ini &= 0x0fff;
6172 data = r8168_mac_ocp_read(tp, 0xd412);
a2cb7ec0 6173 data &= ~0x0fff;
6e1d0b89
CHL		 6174 data |= sw_cnt_1ms_ini;
6175 r8168_mac_ocp_write(tp, 0xd412, data);
6176 }
6177
6178 data = r8168_mac_ocp_read(tp, 0xe056);
a2cb7ec0
CHL		 6179 data &= ~0xf0;
6180 data |= 0x70;
6e1d0b89
CHL		 6181 r8168_mac_ocp_write(tp, 0xe056, data);
6182
6183 data = r8168_mac_ocp_read(tp, 0xe052);
a2cb7ec0
CHL		 6184 data &= ~0x6000;
6185 data |= 0x8008;
6e1d0b89
CHL		 6186 r8168_mac_ocp_write(tp, 0xe052, data);
6187
6188 data = r8168_mac_ocp_read(tp, 0xe0d6);
a2cb7ec0 6189 data &= ~0x01ff;
6e1d0b89
CHL		 6190 data |= 0x017f;
6191 r8168_mac_ocp_write(tp, 0xe0d6, data);
6192
6193 data = r8168_mac_ocp_read(tp, 0xd420);
a2cb7ec0 6194 data &= ~0x0fff;
6e1d0b89
CHL		 6195 data |= 0x047f;
6196 r8168_mac_ocp_write(tp, 0xd420, data);
6197
6198 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
6199 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
6200 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
6201 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
6202}
6203
935e2218
CHL		 6204static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
6205{
6206 void __iomem *ioaddr = tp->mmio_addr;
6207 struct pci_dev *pdev = tp->pci_dev;
6208
003609da
CHL		 6209 rtl8168ep_stop_cmac(tp);
6210
935e2218
CHL		 6211 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6212
6213 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
6214 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x2f, ERIAR_EXGMAC);
6215 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x5f, ERIAR_EXGMAC);
6216 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6217
6218 rtl_csi_access_enable_1(tp);
6219
6220 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6221
6222 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6223 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6224
6225 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f80, 0x00, ERIAR_EXGMAC);
6226
6227 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
6228
935e2218
CHL		 6229 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
6230 RTL_W8(MaxTxPacketSize, EarlySize);
6231
6232 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6233 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6234
6235 /* Adjust EEE LED frequency */
6236 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6237
6238 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
6239
6240 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~TX_10M_PS_EN);
6241
6242 rtl_pcie_state_l2l3_enable(tp, false);
6243}
6244
6245static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
6246{
6247 void __iomem *ioaddr = tp->mmio_addr;
6248 static const struct ephy_info e_info_8168ep_1[] = {
6249 { 0x00, 0xffff, 0x10ab },
6250 { 0x06, 0xffff, 0xf030 },
6251 { 0x08, 0xffff, 0x2006 },
6252 { 0x0d, 0xffff, 0x1666 },
6253 { 0x0c, 0x3ff0, 0x0000 }
6254 };
6255
6256 /* disable aspm and clock request before access ephy */
6257 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6258 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6259 rtl_ephy_init(tp, e_info_8168ep_1, ARRAY_SIZE(e_info_8168ep_1));
6260
6261 rtl_hw_start_8168ep(tp);
6262}
6263
6264static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
6265{
6266 void __iomem *ioaddr = tp->mmio_addr;
6267 static const struct ephy_info e_info_8168ep_2[] = {
6268 { 0x00, 0xffff, 0x10a3 },
6269 { 0x19, 0xffff, 0xfc00 },
6270 { 0x1e, 0xffff, 0x20ea }
6271 };
6272
6273 /* disable aspm and clock request before access ephy */
6274 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6275 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6276 rtl_ephy_init(tp, e_info_8168ep_2, ARRAY_SIZE(e_info_8168ep_2));
6277
6278 rtl_hw_start_8168ep(tp);
6279
6280 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
69f3dc37 6281 RTL_W8(MISC_1, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
935e2218
CHL		 6282}
6283
6284static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
6285{
6286 void __iomem *ioaddr = tp->mmio_addr;
6287 u32 data;
6288 static const struct ephy_info e_info_8168ep_3[] = {
6289 { 0x00, 0xffff, 0x10a3 },
6290 { 0x19, 0xffff, 0x7c00 },
6291 { 0x1e, 0xffff, 0x20eb },
6292 { 0x0d, 0xffff, 0x1666 }
6293 };
6294
6295 /* disable aspm and clock request before access ephy */
6296 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6297 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6298 rtl_ephy_init(tp, e_info_8168ep_3, ARRAY_SIZE(e_info_8168ep_3));
6299
6300 rtl_hw_start_8168ep(tp);
6301
6302 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
69f3dc37 6303 RTL_W8(MISC_1, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
935e2218
CHL		 6304
6305 data = r8168_mac_ocp_read(tp, 0xd3e2);
6306 data &= 0xf000;
6307 data |= 0x0271;
6308 r8168_mac_ocp_write(tp, 0xd3e2, data);
6309
6310 data = r8168_mac_ocp_read(tp, 0xd3e4);
6311 data &= 0xff00;
6312 r8168_mac_ocp_write(tp, 0xd3e4, data);
6313
6314 data = r8168_mac_ocp_read(tp, 0xe860);
6315 data |= 0x0080;
6316 r8168_mac_ocp_write(tp, 0xe860, data);
6317}
6318
07ce4064
FR		 6319static void rtl_hw_start_8168(struct net_device *dev)
6320{
2dd99530
FR		 6321 struct rtl8169_private *tp = netdev_priv(dev);
6322 void __iomem *ioaddr = tp->mmio_addr;
6323
6324 RTL_W8(Cfg9346, Cfg9346_Unlock);
6325
f0298f81 6326 RTL_W8(MaxTxPacketSize, TxPacketMax);
2dd99530 6327
6f0333b8 6328 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
2dd99530 6329
0e485150 6330 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 6331
6332 RTL_W16(CPlusCmd, tp->cp_cmd);
6333
0e485150 6334 RTL_W16(IntrMitigate, 0x5151);
2dd99530 6335
0e485150 6336 /* Work around for RxFIFO overflow. */
811fd301 6337 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
da78dbff
FR		 6338 tp->event_slow |= RxFIFOOver | PCSTimeout;
6339 tp->event_slow &= ~RxOverflow;
0e485150
FR		 6340 }
6341
6342 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530 6343
1a964649 6344 rtl_set_rx_tx_config_registers(tp);
2dd99530
FR		 6345
6346 RTL_R8(IntrMask);
6347
219a1e9d
FR		 6348 switch (tp->mac_version) {
6349 case RTL_GIGA_MAC_VER_11:
beb1fe18 6350 rtl_hw_start_8168bb(tp);
4804b3b3 6351 break;
219a1e9d
FR		 6352
6353 case RTL_GIGA_MAC_VER_12:
6354 case RTL_GIGA_MAC_VER_17:
beb1fe18 6355 rtl_hw_start_8168bef(tp);
4804b3b3 6356 break;
219a1e9d
FR		 6357
6358 case RTL_GIGA_MAC_VER_18:
beb1fe18 6359 rtl_hw_start_8168cp_1(tp);
4804b3b3 6360 break;
219a1e9d
FR		 6361
6362 case RTL_GIGA_MAC_VER_19:
beb1fe18 6363 rtl_hw_start_8168c_1(tp);
4804b3b3 6364 break;
219a1e9d
FR		 6365
6366 case RTL_GIGA_MAC_VER_20:
beb1fe18 6367 rtl_hw_start_8168c_2(tp);
4804b3b3 6368 break;
219a1e9d 6369
197ff761 6370 case RTL_GIGA_MAC_VER_21:
beb1fe18 6371 rtl_hw_start_8168c_3(tp);
4804b3b3 6372 break;
197ff761 6373
6fb07058 6374 case RTL_GIGA_MAC_VER_22:
beb1fe18 6375 rtl_hw_start_8168c_4(tp);
4804b3b3 6376 break;
6fb07058 6377
ef3386f0 6378 case RTL_GIGA_MAC_VER_23:
beb1fe18 6379 rtl_hw_start_8168cp_2(tp);
4804b3b3 6380 break;
ef3386f0 6381
7f3e3d3a 6382 case RTL_GIGA_MAC_VER_24:
beb1fe18 6383 rtl_hw_start_8168cp_3(tp);
4804b3b3 6384 break;
7f3e3d3a 6385
5b538df9 6386 case RTL_GIGA_MAC_VER_25:
daf9df6d 6387 case RTL_GIGA_MAC_VER_26:
6388 case RTL_GIGA_MAC_VER_27:
beb1fe18 6389 rtl_hw_start_8168d(tp);
4804b3b3 6390 break;
5b538df9 6391
e6de30d6 6392 case RTL_GIGA_MAC_VER_28:
beb1fe18 6393 rtl_hw_start_8168d_4(tp);
4804b3b3 6394 break;
cecb5fd7 6395
4804b3b3 6396 case RTL_GIGA_MAC_VER_31:
beb1fe18 6397 rtl_hw_start_8168dp(tp);
4804b3b3 6398 break;
6399
01dc7fec 6400 case RTL_GIGA_MAC_VER_32:
6401 case RTL_GIGA_MAC_VER_33:
beb1fe18 6402 rtl_hw_start_8168e_1(tp);
70090424
HW		 6403 break;
6404 case RTL_GIGA_MAC_VER_34:
beb1fe18 6405 rtl_hw_start_8168e_2(tp);
01dc7fec 6406 break;
e6de30d6 6407
c2218925
HW		 6408 case RTL_GIGA_MAC_VER_35:
6409 case RTL_GIGA_MAC_VER_36:
beb1fe18 6410 rtl_hw_start_8168f_1(tp);
c2218925
HW		 6411 break;
6412
b3d7b2f2
HW		 6413 case RTL_GIGA_MAC_VER_38:
6414 rtl_hw_start_8411(tp);
6415 break;
6416
c558386b
HW		 6417 case RTL_GIGA_MAC_VER_40:
6418 case RTL_GIGA_MAC_VER_41:
6419 rtl_hw_start_8168g_1(tp);
6420 break;
57538c4a 6421 case RTL_GIGA_MAC_VER_42:
6422 rtl_hw_start_8168g_2(tp);
6423 break;
c558386b 6424
45dd95c4 6425 case RTL_GIGA_MAC_VER_44:
6426 rtl_hw_start_8411_2(tp);
6427 break;
6428
6e1d0b89
CHL		 6429 case RTL_GIGA_MAC_VER_45:
6430 case RTL_GIGA_MAC_VER_46:
6431 rtl_hw_start_8168h_1(tp);
6432 break;
6433
935e2218
CHL		 6434 case RTL_GIGA_MAC_VER_49:
6435 rtl_hw_start_8168ep_1(tp);
6436 break;
6437
6438 case RTL_GIGA_MAC_VER_50:
6439 rtl_hw_start_8168ep_2(tp);
6440 break;
6441
6442 case RTL_GIGA_MAC_VER_51:
6443 rtl_hw_start_8168ep_3(tp);
6444 break;
6445
219a1e9d
FR		 6446 default:
6447 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
6448 dev->name, tp->mac_version);
4804b3b3 6449 break;
219a1e9d 6450 }
2dd99530 6451
1a964649 6452 RTL_W8(Cfg9346, Cfg9346_Lock);
6453
0e485150
FR		 6454 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
6455
1a964649 6456 rtl_set_rx_mode(dev);
b8363901 6457
05b9687b 6458 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
07ce4064 6459}
1da177e4 6460
2857ffb7
FR		 6461#define R810X_CPCMD_QUIRK_MASK (\
6462 EnableBist | \
6463 Mac_dbgo_oe | \
6464 Force_half_dup | \
5edcc537 6465 Force_rxflow_en | \
2857ffb7
FR		 6466 Force_txflow_en | \
6467 Cxpl_dbg_sel | \
6468 ASF | \
6469 PktCntrDisable | \
d24e9aaf 6470 Mac_dbgo_sel)
2857ffb7 6471
beb1fe18 6472static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
2857ffb7 6473{
beb1fe18
HW		 6474 void __iomem *ioaddr = tp->mmio_addr;
6475 struct pci_dev *pdev = tp->pci_dev;
350f7596 6476 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 6477 { 0x01, 0, 0x6e65 },
6478 { 0x02, 0, 0x091f },
6479 { 0x03, 0, 0xc2f9 },
6480 { 0x06, 0, 0xafb5 },
6481 { 0x07, 0, 0x0e00 },
6482 { 0x19, 0, 0xec80 },
6483 { 0x01, 0, 0x2e65 },
6484 { 0x01, 0, 0x6e65 }
6485 };
6486 u8 cfg1;
6487
beb1fe18 6488 rtl_csi_access_enable_2(tp);
2857ffb7
FR		 6489
6490 RTL_W8(DBG_REG, FIX_NAK_1);
6491
6492 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6493
6494 RTL_W8(Config1,
6495 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
6496 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
6497
6498 cfg1 = RTL_R8(Config1);
6499 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
6500 RTL_W8(Config1, cfg1 & ~LEDS0);
6501
fdf6fc06 6502 rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
2857ffb7
FR		 6503}
6504
beb1fe18 6505static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
2857ffb7 6506{
beb1fe18
HW		 6507 void __iomem *ioaddr = tp->mmio_addr;
6508 struct pci_dev *pdev = tp->pci_dev;
6509
6510 rtl_csi_access_enable_2(tp);
2857ffb7
FR		 6511
6512 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6513
6514 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
6515 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2857ffb7
FR		 6516}
6517
beb1fe18 6518static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
2857ffb7 6519{
beb1fe18 6520 rtl_hw_start_8102e_2(tp);
2857ffb7 6521
fdf6fc06 6522 rtl_ephy_write(tp, 0x03, 0xc2f9);
2857ffb7
FR		 6523}
6524
beb1fe18 6525static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5a5e4443 6526{
beb1fe18 6527 void __iomem *ioaddr = tp->mmio_addr;
5a5e4443
HW		 6528 static const struct ephy_info e_info_8105e_1[] = {
6529 { 0x07, 0, 0x4000 },
6530 { 0x19, 0, 0x0200 },
6531 { 0x19, 0, 0x0020 },
6532 { 0x1e, 0, 0x2000 },
6533 { 0x03, 0, 0x0001 },
6534 { 0x19, 0, 0x0100 },
6535 { 0x19, 0, 0x0004 },
6536 { 0x0a, 0, 0x0020 }
6537 };
6538
cecb5fd7 6539 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5a5e4443
HW		 6540 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6541
cecb5fd7 6542 /* Disable Early Tally Counter */
5a5e4443
HW		 6543 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
6544
6545 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4f6b00e5 6546 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5a5e4443 6547
fdf6fc06 6548 rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
b51ecea8 6549
6550 rtl_pcie_state_l2l3_enable(tp, false);
5a5e4443
HW		 6551}
6552
beb1fe18 6553static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5a5e4443 6554{
beb1fe18 6555 rtl_hw_start_8105e_1(tp);
fdf6fc06 6556 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5a5e4443
HW		 6557}
6558
7e18dca1
HW		 6559static void rtl_hw_start_8402(struct rtl8169_private *tp)
6560{
6561 void __iomem *ioaddr = tp->mmio_addr;
6562 static const struct ephy_info e_info_8402[] = {
6563 { 0x19, 0xffff, 0xff64 },
6564 { 0x1e, 0, 0x4000 }
6565 };
6566
6567 rtl_csi_access_enable_2(tp);
6568
6569 /* Force LAN exit from ASPM if Rx/Tx are not idle */
6570 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6571
6572 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6573 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
6574
fdf6fc06 6575 rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
7e18dca1
HW		 6576
6577 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
6578
fdf6fc06
FR		 6579 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
6580 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
706123d0
CHL		 6581 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6582 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
fdf6fc06
FR		 6583 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6584 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
706123d0 6585 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
b51ecea8 6586
6587 rtl_pcie_state_l2l3_enable(tp, false);
7e18dca1
HW		 6588}
6589
5598bfe5
HW		 6590static void rtl_hw_start_8106(struct rtl8169_private *tp)
6591{
6592 void __iomem *ioaddr = tp->mmio_addr;
6593
6594 /* Force LAN exit from ASPM if Rx/Tx are not idle */
6595 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6596
4521e1a9 6597 RTL_W32(MISC, (RTL_R32(MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5598bfe5
HW		 6598 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
6599 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
b51ecea8 6600
6601 rtl_pcie_state_l2l3_enable(tp, false);
5598bfe5
HW		 6602}
6603
07ce4064
FR		 6604static void rtl_hw_start_8101(struct net_device *dev)
6605{
cdf1a608
FR		 6606 struct rtl8169_private *tp = netdev_priv(dev);
6607 void __iomem *ioaddr = tp->mmio_addr;
6608 struct pci_dev *pdev = tp->pci_dev;
6609
da78dbff
FR		 6610 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
6611 tp->event_slow &= ~RxFIFOOver;
811fd301 6612
cecb5fd7 6613 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
7d7903b2 6614 tp->mac_version == RTL_GIGA_MAC_VER_16)
8200bc72
BH		 6615 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL,
6616 PCI_EXP_DEVCTL_NOSNOOP_EN);
cdf1a608 6617
d24e9aaf
HW		 6618 RTL_W8(Cfg9346, Cfg9346_Unlock);
6619
1a964649 6620 RTL_W8(MaxTxPacketSize, TxPacketMax);
6621
6622 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
6623
6624 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
6625 RTL_W16(CPlusCmd, tp->cp_cmd);
6626
6627 rtl_set_rx_tx_desc_registers(tp, ioaddr);
6628
6629 rtl_set_rx_tx_config_registers(tp);
6630
2857ffb7
FR		 6631 switch (tp->mac_version) {
6632 case RTL_GIGA_MAC_VER_07:
beb1fe18 6633 rtl_hw_start_8102e_1(tp);
2857ffb7
FR		 6634 break;
6635
6636 case RTL_GIGA_MAC_VER_08:
beb1fe18 6637 rtl_hw_start_8102e_3(tp);
2857ffb7
FR		 6638 break;
6639
6640 case RTL_GIGA_MAC_VER_09:
beb1fe18 6641 rtl_hw_start_8102e_2(tp);
2857ffb7 6642 break;
5a5e4443
HW		 6643
6644 case RTL_GIGA_MAC_VER_29:
beb1fe18 6645 rtl_hw_start_8105e_1(tp);
5a5e4443
HW		 6646 break;
6647 case RTL_GIGA_MAC_VER_30:
beb1fe18 6648 rtl_hw_start_8105e_2(tp);
5a5e4443 6649 break;
7e18dca1
HW		 6650
6651 case RTL_GIGA_MAC_VER_37:
6652 rtl_hw_start_8402(tp);
6653 break;
5598bfe5
HW		 6654
6655 case RTL_GIGA_MAC_VER_39:
6656 rtl_hw_start_8106(tp);
6657 break;
58152cd4 6658 case RTL_GIGA_MAC_VER_43:
6659 rtl_hw_start_8168g_2(tp);
6660 break;
6e1d0b89
CHL		 6661 case RTL_GIGA_MAC_VER_47:
6662 case RTL_GIGA_MAC_VER_48:
6663 rtl_hw_start_8168h_1(tp);
6664 break;
cdf1a608
FR		 6665 }
6666
d24e9aaf 6667 RTL_W8(Cfg9346, Cfg9346_Lock);
cdf1a608 6668
cdf1a608
FR		 6669 RTL_W16(IntrMitigate, 0x0000);
6670
cdf1a608 6671 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
cdf1a608 6672
cdf1a608
FR		 6673 rtl_set_rx_mode(dev);
6674
1a964649 6675 RTL_R8(IntrMask);
6676
cdf1a608 6677 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
1da177e4
LT		 6678}
6679
6680static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
6681{
d58d46b5
FR		 6682 struct rtl8169_private *tp = netdev_priv(dev);
6683
d58d46b5
FR		 6684 if (new_mtu > ETH_DATA_LEN)
6685 rtl_hw_jumbo_enable(tp);
6686 else
6687 rtl_hw_jumbo_disable(tp);
6688
1da177e4 6689 dev->mtu = new_mtu;
350fb32a
MM		 6690 netdev_update_features(dev);
6691
323bb685 6692 return 0;
1da177e4
LT		 6693}
6694
6695static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
6696{
95e0918d 6697 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 6698 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
6699}
6700
6f0333b8
ED		 6701static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
6702 void **data_buff, struct RxDesc *desc)
1da177e4 6703{
48addcc9 6704 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
231aee63 6705 DMA_FROM_DEVICE);
48addcc9 6706
6f0333b8
ED		 6707 kfree(*data_buff);
6708 *data_buff = NULL;
1da177e4
LT		 6709 rtl8169_make_unusable_by_asic(desc);
6710}
6711
6712static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
6713{
6714 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
6715
a0750138
AD		 6716 /* Force memory writes to complete before releasing descriptor */
6717 dma_wmb();
6718
1da177e4
LT		 6719 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
6720}
6721
6722static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
6723 u32 rx_buf_sz)
6724{
6725 desc->addr = cpu_to_le64(mapping);
1da177e4
LT		 6726 rtl8169_mark_to_asic(desc, rx_buf_sz);
6727}
6728
6f0333b8
ED		 6729static inline void *rtl8169_align(void *data)
6730{
6731 return (void *)ALIGN((long)data, 16);
6732}
6733
0ecbe1ca
SG		 6734static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
6735 struct RxDesc *desc)
1da177e4 6736{
6f0333b8 6737 void *data;
1da177e4 6738 dma_addr_t mapping;
48addcc9 6739 struct device *d = &tp->pci_dev->dev;
0ecbe1ca 6740 struct net_device *dev = tp->dev;
6f0333b8 6741 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
1da177e4 6742
6f0333b8
ED		 6743 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
6744 if (!data)
6745 return NULL;
e9f63f30 6746
6f0333b8
ED		 6747 if (rtl8169_align(data) != data) {
6748 kfree(data);
6749 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
6750 if (!data)
6751 return NULL;
6752 }
3eafe507 6753
48addcc9 6754 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
231aee63 6755 DMA_FROM_DEVICE);
d827d86b
SG		 6756 if (unlikely(dma_mapping_error(d, mapping))) {
6757 if (net_ratelimit())
6758 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
3eafe507 6759 goto err_out;
d827d86b 6760 }
1da177e4
LT		 6761
6762 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6f0333b8 6763 return data;
3eafe507
SG		 6764
6765err_out:
6766 kfree(data);
6767 return NULL;
1da177e4
LT		 6768}
6769
6770static void rtl8169_rx_clear(struct rtl8169_private *tp)
6771{
07d3f51f 6772 unsigned int i;
1da177e4
LT		 6773
6774 for (i = 0; i < NUM_RX_DESC; i++) {
6f0333b8
ED		 6775 if (tp->Rx_databuff[i]) {
6776 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
1da177e4
LT		 6777 tp->RxDescArray + i);
6778 }
6779 }
6780}
6781
0ecbe1ca 6782static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1da177e4 6783{
0ecbe1ca
SG		 6784 desc->opts1 |= cpu_to_le32(RingEnd);
6785}
5b0384f4 6786
0ecbe1ca
SG		 6787static int rtl8169_rx_fill(struct rtl8169_private *tp)
6788{
6789 unsigned int i;
1da177e4 6790
0ecbe1ca
SG		 6791 for (i = 0; i < NUM_RX_DESC; i++) {
6792 void *data;
4ae47c2d 6793
6f0333b8 6794 if (tp->Rx_databuff[i])
1da177e4 6795 continue;
bcf0bf90 6796
0ecbe1ca 6797 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6f0333b8
ED		 6798 if (!data) {
6799 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
0ecbe1ca 6800 goto err_out;
6f0333b8
ED		 6801 }
6802 tp->Rx_databuff[i] = data;
1da177e4 6803 }
1da177e4 6804
0ecbe1ca
SG		 6805 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
6806 return 0;
6807
6808err_out:
6809 rtl8169_rx_clear(tp);
6810 return -ENOMEM;
1da177e4
LT		 6811}
6812
1da177e4
LT		 6813static int rtl8169_init_ring(struct net_device *dev)
6814{
6815 struct rtl8169_private *tp = netdev_priv(dev);
6816
6817 rtl8169_init_ring_indexes(tp);
6818
6819 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
6f0333b8 6820 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
1da177e4 6821
0ecbe1ca 6822 return rtl8169_rx_fill(tp);
1da177e4
LT		 6823}
6824
48addcc9 6825static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
1da177e4
LT		 6826 struct TxDesc *desc)
6827{
6828 unsigned int len = tx_skb->len;
6829
48addcc9
SG		 6830 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
6831
1da177e4
LT		 6832 desc->opts1 = 0x00;
6833 desc->opts2 = 0x00;
6834 desc->addr = 0x00;
6835 tx_skb->len = 0;
6836}
6837
3eafe507
SG		 6838static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
6839 unsigned int n)
1da177e4
LT		 6840{
6841 unsigned int i;
6842
3eafe507
SG		 6843 for (i = 0; i < n; i++) {
6844 unsigned int entry = (start + i) % NUM_TX_DESC;
1da177e4
LT		 6845 struct ring_info *tx_skb = tp->tx_skb + entry;
6846 unsigned int len = tx_skb->len;
6847
6848 if (len) {
6849 struct sk_buff *skb = tx_skb->skb;
6850
48addcc9 6851 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
1da177e4
LT		 6852 tp->TxDescArray + entry);
6853 if (skb) {
cac4b22f 6854 tp->dev->stats.tx_dropped++;
989c9ba1 6855 dev_kfree_skb_any(skb);
1da177e4
LT		 6856 tx_skb->skb = NULL;
6857 }
1da177e4
LT		 6858 }
6859 }
3eafe507
SG		 6860}
6861
6862static void rtl8169_tx_clear(struct rtl8169_private *tp)
6863{
6864 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
1da177e4
LT		 6865 tp->cur_tx = tp->dirty_tx = 0;
6866}
6867
4422bcd4 6868static void rtl_reset_work(struct rtl8169_private *tp)
1da177e4 6869{
c4028958 6870 struct net_device *dev = tp->dev;
56de414c 6871 int i;
1da177e4 6872
da78dbff
FR		 6873 napi_disable(&tp->napi);
6874 netif_stop_queue(dev);
6875 synchronize_sched();
1da177e4 6876
c7c2c39b 6877 rtl8169_hw_reset(tp);
6878
56de414c
FR		 6879 for (i = 0; i < NUM_RX_DESC; i++)
6880 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
6881
1da177e4 6882 rtl8169_tx_clear(tp);
c7c2c39b 6883 rtl8169_init_ring_indexes(tp);
1da177e4 6884
da78dbff 6885 napi_enable(&tp->napi);
56de414c
FR		 6886 rtl_hw_start(dev);
6887 netif_wake_queue(dev);
6888 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1da177e4
LT		 6889}
6890
6891static void rtl8169_tx_timeout(struct net_device *dev)
6892{
da78dbff
FR		 6893 struct rtl8169_private *tp = netdev_priv(dev);
6894
6895 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 6896}
6897
6898static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2b7b4318 6899 u32 *opts)
1da177e4
LT		 6900{
6901 struct skb_shared_info *info = skb_shinfo(skb);
6902 unsigned int cur_frag, entry;
6e1d0b89 6903 struct TxDesc *uninitialized_var(txd);
48addcc9 6904 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 6905
6906 entry = tp->cur_tx;
6907 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
9e903e08 6908 const skb_frag_t *frag = info->frags + cur_frag;
1da177e4
LT		 6909 dma_addr_t mapping;
6910 u32 status, len;
6911 void *addr;
6912
6913 entry = (entry + 1) % NUM_TX_DESC;
6914
6915 txd = tp->TxDescArray + entry;
9e903e08 6916 len = skb_frag_size(frag);
929f6189 6917 addr = skb_frag_address(frag);
48addcc9 6918 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
d827d86b
SG		 6919 if (unlikely(dma_mapping_error(d, mapping))) {
6920 if (net_ratelimit())
6921 netif_err(tp, drv, tp->dev,
6922 "Failed to map TX fragments DMA!\n");
3eafe507 6923 goto err_out;
d827d86b 6924 }
1da177e4 6925
cecb5fd7 6926 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318
FR		 6927 status = opts[0] | len |
6928 (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 6929
6930 txd->opts1 = cpu_to_le32(status);
2b7b4318 6931 txd->opts2 = cpu_to_le32(opts[1]);
1da177e4
LT		 6932 txd->addr = cpu_to_le64(mapping);
6933
6934 tp->tx_skb[entry].len = len;
6935 }
6936
6937 if (cur_frag) {
6938 tp->tx_skb[entry].skb = skb;
6939 txd->opts1 |= cpu_to_le32(LastFrag);
6940 }
6941
6942 return cur_frag;
3eafe507
SG		 6943
6944err_out:
6945 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
6946 return -EIO;
1da177e4
LT		 6947}
6948
b423e9ae 6949static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
6950{
6951 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
6952}
6953
e974604b 6954static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6955 struct net_device *dev);
6956/* r8169_csum_workaround()
6957 * The hw limites the value the transport offset. When the offset is out of the
6958 * range, calculate the checksum by sw.
6959 */
6960static void r8169_csum_workaround(struct rtl8169_private *tp,
6961 struct sk_buff *skb)
6962{
6963 if (skb_shinfo(skb)->gso_size) {
6964 netdev_features_t features = tp->dev->features;
6965 struct sk_buff *segs, *nskb;
6966
6967 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
6968 segs = skb_gso_segment(skb, features);
6969 if (IS_ERR(segs) || !segs)
6970 goto drop;
6971
6972 do {
6973 nskb = segs;
6974 segs = segs->next;
6975 nskb->next = NULL;
6976 rtl8169_start_xmit(nskb, tp->dev);
6977 } while (segs);
6978
eb781397 6979 dev_consume_skb_any(skb);
e974604b 6980 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6981 if (skb_checksum_help(skb) < 0)
6982 goto drop;
6983
6984 rtl8169_start_xmit(skb, tp->dev);
6985 } else {
6986 struct net_device_stats *stats;
6987
6988drop:
6989 stats = &tp->dev->stats;
6990 stats->tx_dropped++;
eb781397 6991 dev_kfree_skb_any(skb);
e974604b 6992 }
6993}
6994
6995/* msdn_giant_send_check()
6996 * According to the document of microsoft, the TCP Pseudo Header excludes the
6997 * packet length for IPv6 TCP large packets.
6998 */
6999static int msdn_giant_send_check(struct sk_buff *skb)
7000{
7001 const struct ipv6hdr *ipv6h;
7002 struct tcphdr *th;
7003 int ret;
7004
7005 ret = skb_cow_head(skb, 0);
7006 if (ret)
7007 return ret;
7008
7009 ipv6h = ipv6_hdr(skb);
7010 th = tcp_hdr(skb);
7011
7012 th->check = 0;
7013 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
7014
7015 return ret;
7016}
7017
7018static inline __be16 get_protocol(struct sk_buff *skb)
7019{
7020 __be16 protocol;
7021
7022 if (skb->protocol == htons(ETH_P_8021Q))
7023 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
7024 else
7025 protocol = skb->protocol;
7026
7027 return protocol;
7028}
7029
5888d3fc 7030static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
7031 struct sk_buff *skb, u32 *opts)
1da177e4 7032{
350fb32a
MM		 7033 u32 mss = skb_shinfo(skb)->gso_size;
7034
2b7b4318
FR		 7035 if (mss) {
7036 opts[0] |= TD_LSO;
5888d3fc 7037 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
7038 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
7039 const struct iphdr *ip = ip_hdr(skb);
7040
7041 if (ip->protocol == IPPROTO_TCP)
7042 opts[0] |= TD0_IP_CS | TD0_TCP_CS;
7043 else if (ip->protocol == IPPROTO_UDP)
7044 opts[0] |= TD0_IP_CS | TD0_UDP_CS;
7045 else
7046 WARN_ON_ONCE(1);
7047 }
7048
7049 return true;
7050}
7051
7052static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
7053 struct sk_buff *skb, u32 *opts)
7054{
bdfa4ed6 7055 u32 transport_offset = (u32)skb_transport_offset(skb);
5888d3fc 7056 u32 mss = skb_shinfo(skb)->gso_size;
7057
7058 if (mss) {
e974604b 7059 if (transport_offset > GTTCPHO_MAX) {
7060 netif_warn(tp, tx_err, tp->dev,
7061 "Invalid transport offset 0x%x for TSO\n",
7062 transport_offset);
7063 return false;
7064 }
7065
7066 switch (get_protocol(skb)) {
7067 case htons(ETH_P_IP):
7068 opts[0] |= TD1_GTSENV4;
7069 break;
7070
7071 case htons(ETH_P_IPV6):
7072 if (msdn_giant_send_check(skb))
7073 return false;
7074
7075 opts[0] |= TD1_GTSENV6;
7076 break;
7077
7078 default:
7079 WARN_ON_ONCE(1);
7080 break;
7081 }
7082
bdfa4ed6 7083 opts[0] |= transport_offset << GTTCPHO_SHIFT;
5888d3fc 7084 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
2b7b4318 7085 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
e974604b 7086 u8 ip_protocol;
1da177e4 7087
b423e9ae 7088 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
207c5f44 7089 return !(skb_checksum_help(skb) || eth_skb_pad(skb));
b423e9ae 7090
e974604b 7091 if (transport_offset > TCPHO_MAX) {
7092 netif_warn(tp, tx_err, tp->dev,
7093 "Invalid transport offset 0x%x\n",
7094 transport_offset);
7095 return false;
7096 }
7097
7098 switch (get_protocol(skb)) {
7099 case htons(ETH_P_IP):
7100 opts[1] |= TD1_IPv4_CS;
7101 ip_protocol = ip_hdr(skb)->protocol;
7102 break;
7103
7104 case htons(ETH_P_IPV6):
7105 opts[1] |= TD1_IPv6_CS;
7106 ip_protocol = ipv6_hdr(skb)->nexthdr;
7107 break;
7108
7109 default:
7110 ip_protocol = IPPROTO_RAW;
7111 break;
7112 }
7113
7114 if (ip_protocol == IPPROTO_TCP)
7115 opts[1] |= TD1_TCP_CS;
7116 else if (ip_protocol == IPPROTO_UDP)
7117 opts[1] |= TD1_UDP_CS;
2b7b4318
FR		 7118 else
7119 WARN_ON_ONCE(1);
e974604b 7120
7121 opts[1] |= transport_offset << TCPHO_SHIFT;
b423e9ae 7122 } else {
7123 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
207c5f44 7124 return !eth_skb_pad(skb);
1da177e4 7125 }
5888d3fc 7126
b423e9ae 7127 return true;
1da177e4
LT		 7128}
7129
61357325
SH		 7130static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
7131 struct net_device *dev)
1da177e4
LT		 7132{
7133 struct rtl8169_private *tp = netdev_priv(dev);
3eafe507 7134 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
1da177e4
LT		 7135 struct TxDesc *txd = tp->TxDescArray + entry;
7136 void __iomem *ioaddr = tp->mmio_addr;
48addcc9 7137 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 7138 dma_addr_t mapping;
7139 u32 status, len;
2b7b4318 7140 u32 opts[2];
3eafe507 7141 int frags;
5b0384f4 7142
477206a0 7143 if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
bf82c189 7144 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
3eafe507 7145 goto err_stop_0;
1da177e4
LT		 7146 }
7147
7148 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3eafe507
SG		 7149 goto err_stop_0;
7150
b423e9ae 7151 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
7152 opts[0] = DescOwn;
7153
e974604b 7154 if (!tp->tso_csum(tp, skb, opts)) {
7155 r8169_csum_workaround(tp, skb);
7156 return NETDEV_TX_OK;
7157 }
b423e9ae 7158
3eafe507 7159 len = skb_headlen(skb);
48addcc9 7160 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
d827d86b
SG		 7161 if (unlikely(dma_mapping_error(d, mapping))) {
7162 if (net_ratelimit())
7163 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
3eafe507 7164 goto err_dma_0;
d827d86b 7165 }
3eafe507
SG		 7166
7167 tp->tx_skb[entry].len = len;
7168 txd->addr = cpu_to_le64(mapping);
1da177e4 7169
2b7b4318 7170 frags = rtl8169_xmit_frags(tp, skb, opts);
3eafe507
SG		 7171 if (frags < 0)
7172 goto err_dma_1;
7173 else if (frags)
2b7b4318 7174 opts[0] |= FirstFrag;
3eafe507 7175 else {
2b7b4318 7176 opts[0] |= FirstFrag | LastFrag;
1da177e4
LT		 7177 tp->tx_skb[entry].skb = skb;
7178 }
7179
2b7b4318
FR		 7180 txd->opts2 = cpu_to_le32(opts[1]);
7181
5047fb5d
RC		 7182 skb_tx_timestamp(skb);
7183
a0750138
AD		 7184 /* Force memory writes to complete before releasing descriptor */
7185 dma_wmb();
1da177e4 7186
cecb5fd7 7187 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318 7188 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 7189 txd->opts1 = cpu_to_le32(status);
7190
a0750138 7191 /* Force all memory writes to complete before notifying device */
4c020a96 7192 wmb();
1da177e4 7193
a0750138
AD		 7194 tp->cur_tx += frags + 1;
7195
87cda7cb 7196 RTL_W8(TxPoll, NPQ);
1da177e4 7197
87cda7cb 7198 mmiowb();
da78dbff 7199
87cda7cb 7200 if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
ae1f23fb
FR		 7201 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
7202 * not miss a ring update when it notices a stopped queue.
7203 */
7204 smp_wmb();
1da177e4 7205 netif_stop_queue(dev);
ae1f23fb
FR		 7206 /* Sync with rtl_tx:
7207 * - publish queue status and cur_tx ring index (write barrier)
7208 * - refresh dirty_tx ring index (read barrier).
7209 * May the current thread have a pessimistic view of the ring
7210 * status and forget to wake up queue, a racing rtl_tx thread
7211 * can't.
7212 */
1e874e04 7213 smp_mb();
477206a0 7214 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
1da177e4
LT		 7215 netif_wake_queue(dev);
7216 }
7217
61357325 7218 return NETDEV_TX_OK;
1da177e4 7219
3eafe507 7220err_dma_1:
48addcc9 7221 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
3eafe507 7222err_dma_0:
989c9ba1 7223 dev_kfree_skb_any(skb);
3eafe507
SG		 7224 dev->stats.tx_dropped++;
7225 return NETDEV_TX_OK;
7226
7227err_stop_0:
1da177e4 7228 netif_stop_queue(dev);
cebf8cc7 7229 dev->stats.tx_dropped++;
61357325 7230 return NETDEV_TX_BUSY;
1da177e4
LT		 7231}
7232
7233static void rtl8169_pcierr_interrupt(struct net_device *dev)
7234{
7235 struct rtl8169_private *tp = netdev_priv(dev);
7236 struct pci_dev *pdev = tp->pci_dev;
1da177e4
LT		 7237 u16 pci_status, pci_cmd;
7238
7239 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
7240 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
7241
bf82c189
JP		 7242 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
7243 pci_cmd, pci_status);
1da177e4
LT		 7244
7245 /*
7246 * The recovery sequence below admits a very elaborated explanation:
7247 * - it seems to work;
d03902b8
FR		 7248 * - I did not see what else could be done;
7249 * - it makes iop3xx happy.
1da177e4
LT		 7250 *
7251 * Feel free to adjust to your needs.
7252 */
a27993f3 7253 if (pdev->broken_parity_status)
d03902b8
FR		 7254 pci_cmd &= ~PCI_COMMAND_PARITY;
7255 else
7256 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
7257
7258 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 7259
7260 pci_write_config_word(pdev, PCI_STATUS,
7261 pci_status & (PCI_STATUS_DETECTED_PARITY |
7262 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
7263 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
7264
7265 /* The infamous DAC f*ckup only happens at boot time */
9fba0812 7266 if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
e6de30d6 7267 void __iomem *ioaddr = tp->mmio_addr;
7268
bf82c189 7269 netif_info(tp, intr, dev, "disabling PCI DAC\n");
1da177e4
LT		 7270 tp->cp_cmd &= ~PCIDAC;
7271 RTL_W16(CPlusCmd, tp->cp_cmd);
7272 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 7273 }
7274
e6de30d6 7275 rtl8169_hw_reset(tp);
d03902b8 7276
98ddf986 7277 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 7278}
7279
da78dbff 7280static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
1da177e4
LT		 7281{
7282 unsigned int dirty_tx, tx_left;
7283
1da177e4
LT		 7284 dirty_tx = tp->dirty_tx;
7285 smp_rmb();
7286 tx_left = tp->cur_tx - dirty_tx;
7287
7288 while (tx_left > 0) {
7289 unsigned int entry = dirty_tx % NUM_TX_DESC;
7290 struct ring_info *tx_skb = tp->tx_skb + entry;
1da177e4
LT		 7291 u32 status;
7292
1da177e4
LT		 7293 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
7294 if (status & DescOwn)
7295 break;
7296
a0750138
AD		 7297 /* This barrier is needed to keep us from reading
7298 * any other fields out of the Tx descriptor until
7299 * we know the status of DescOwn
7300 */
7301 dma_rmb();
7302
48addcc9
SG		 7303 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
7304 tp->TxDescArray + entry);
1da177e4 7305 if (status & LastFrag) {
87cda7cb
DM		 7306 u64_stats_update_begin(&tp->tx_stats.syncp);
7307 tp->tx_stats.packets++;
7308 tp->tx_stats.bytes += tx_skb->skb->len;
7309 u64_stats_update_end(&tp->tx_stats.syncp);
989c9ba1 7310 dev_kfree_skb_any(tx_skb->skb);
1da177e4
LT		 7311 tx_skb->skb = NULL;
7312 }
7313 dirty_tx++;
7314 tx_left--;
7315 }
7316
7317 if (tp->dirty_tx != dirty_tx) {
7318 tp->dirty_tx = dirty_tx;
ae1f23fb
FR		 7319 /* Sync with rtl8169_start_xmit:
7320 * - publish dirty_tx ring index (write barrier)
7321 * - refresh cur_tx ring index and queue status (read barrier)
7322 * May the current thread miss the stopped queue condition,
7323 * a racing xmit thread can only have a right view of the
7324 * ring status.
7325 */
1e874e04 7326 smp_mb();
1da177e4 7327 if (netif_queue_stopped(dev) &&
477206a0 7328 TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
1da177e4
LT		 7329 netif_wake_queue(dev);
7330 }
d78ae2dc
FR		 7331 /*
7332 * 8168 hack: TxPoll requests are lost when the Tx packets are
7333 * too close. Let's kick an extra TxPoll request when a burst
7334 * of start_xmit activity is detected (if it is not detected,
7335 * it is slow enough). -- FR
7336 */
da78dbff
FR		 7337 if (tp->cur_tx != dirty_tx) {
7338 void __iomem *ioaddr = tp->mmio_addr;
7339
d78ae2dc 7340 RTL_W8(TxPoll, NPQ);
da78dbff 7341 }
1da177e4
LT		 7342 }
7343}
7344
126fa4b9
FR		 7345static inline int rtl8169_fragmented_frame(u32 status)
7346{
7347 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
7348}
7349
adea1ac7 7350static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
1da177e4 7351{
1da177e4
LT		 7352 u32 status = opts1 & RxProtoMask;
7353
7354 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
d5d3ebe3 7355 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
1da177e4
LT		 7356 skb->ip_summed = CHECKSUM_UNNECESSARY;
7357 else
bc8acf2c 7358 skb_checksum_none_assert(skb);
1da177e4
LT		 7359}
7360
6f0333b8
ED		 7361static struct sk_buff *rtl8169_try_rx_copy(void *data,
7362 struct rtl8169_private *tp,
7363 int pkt_size,
7364 dma_addr_t addr)
1da177e4 7365{
b449655f 7366 struct sk_buff *skb;
48addcc9 7367 struct device *d = &tp->pci_dev->dev;
b449655f 7368
6f0333b8 7369 data = rtl8169_align(data);
48addcc9 7370 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6f0333b8 7371 prefetch(data);
e2338f86 7372 skb = napi_alloc_skb(&tp->napi, pkt_size);
6f0333b8
ED		 7373 if (skb)
7374 memcpy(skb->data, data, pkt_size);
48addcc9
SG		 7375 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
7376
6f0333b8 7377 return skb;
1da177e4
LT		 7378}
7379
da78dbff 7380static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
1da177e4
LT		 7381{
7382 unsigned int cur_rx, rx_left;
6f0333b8 7383 unsigned int count;
1da177e4 7384
1da177e4 7385 cur_rx = tp->cur_rx;
1da177e4 7386
9fba0812 7387 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
1da177e4 7388 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 7389 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 7390 u32 status;
7391
e03f33af 7392 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
1da177e4
LT		 7393 if (status & DescOwn)
7394 break;
a0750138
AD		 7395
7396 /* This barrier is needed to keep us from reading
7397 * any other fields out of the Rx descriptor until
7398 * we know the status of DescOwn
7399 */
7400 dma_rmb();
7401
4dcb7d33 7402 if (unlikely(status & RxRES)) {
bf82c189
JP		 7403 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
7404 status);
cebf8cc7 7405 dev->stats.rx_errors++;
1da177e4 7406 if (status & (RxRWT | RxRUNT))
cebf8cc7 7407 dev->stats.rx_length_errors++;
1da177e4 7408 if (status & RxCRC)
cebf8cc7 7409 dev->stats.rx_crc_errors++;
9dccf611 7410 if (status & RxFOVF) {
da78dbff 7411 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
cebf8cc7 7412 dev->stats.rx_fifo_errors++;
9dccf611 7413 }
6bbe021d
BG		 7414 if ((status & (RxRUNT | RxCRC)) &&
7415 !(status & (RxRWT | RxFOVF)) &&
7416 (dev->features & NETIF_F_RXALL))
7417 goto process_pkt;
1da177e4 7418 } else {
6f0333b8 7419 struct sk_buff *skb;
6bbe021d
BG		 7420 dma_addr_t addr;
7421 int pkt_size;
7422
7423process_pkt:
7424 addr = le64_to_cpu(desc->addr);
79d0c1d2
BG		 7425 if (likely(!(dev->features & NETIF_F_RXFCS)))
7426 pkt_size = (status & 0x00003fff) - 4;
7427 else
7428 pkt_size = status & 0x00003fff;
1da177e4 7429
126fa4b9
FR		 7430 /*
7431 * The driver does not support incoming fragmented
7432 * frames. They are seen as a symptom of over-mtu
7433 * sized frames.
7434 */
7435 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 7436 dev->stats.rx_dropped++;
7437 dev->stats.rx_length_errors++;
ce11ff5e 7438 goto release_descriptor;
126fa4b9
FR		 7439 }
7440
6f0333b8
ED		 7441 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
7442 tp, pkt_size, addr);
6f0333b8
ED		 7443 if (!skb) {
7444 dev->stats.rx_dropped++;
ce11ff5e 7445 goto release_descriptor;
1da177e4
LT		 7446 }
7447
adea1ac7 7448 rtl8169_rx_csum(skb, status);
1da177e4
LT		 7449 skb_put(skb, pkt_size);
7450 skb->protocol = eth_type_trans(skb, dev);
7451
7a8fc77b
FR		 7452 rtl8169_rx_vlan_tag(desc, skb);
7453
39174291 7454 if (skb->pkt_type == PACKET_MULTICAST)
7455 dev->stats.multicast++;
7456
56de414c 7457 napi_gro_receive(&tp->napi, skb);
1da177e4 7458
8027aa24
JW		 7459 u64_stats_update_begin(&tp->rx_stats.syncp);
7460 tp->rx_stats.packets++;
7461 tp->rx_stats.bytes += pkt_size;
7462 u64_stats_update_end(&tp->rx_stats.syncp);
1da177e4 7463 }
ce11ff5e 7464release_descriptor:
7465 desc->opts2 = 0;
ce11ff5e 7466 rtl8169_mark_to_asic(desc, rx_buf_sz);
1da177e4
LT		 7467 }
7468
7469 count = cur_rx - tp->cur_rx;
7470 tp->cur_rx = cur_rx;
7471
1da177e4
LT		 7472 return count;
7473}
7474
07d3f51f 7475static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 7476{
07d3f51f 7477 struct net_device *dev = dev_instance;
1da177e4 7478 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 7479 int handled = 0;
9085cdfa 7480 u16 status;
1da177e4 7481
9085cdfa 7482 status = rtl_get_events(tp);
da78dbff
FR		 7483 if (status && status != 0xffff) {
7484 status &= RTL_EVENT_NAPI | tp->event_slow;
7485 if (status) {
7486 handled = 1;
1da177e4 7487
da78dbff
FR		 7488 rtl_irq_disable(tp);
7489 napi_schedule(&tp->napi);
f11a377b 7490 }
da78dbff
FR		 7491 }
7492 return IRQ_RETVAL(handled);
7493}
1da177e4 7494
da78dbff
FR		 7495/*
7496 * Workqueue context.
7497 */
7498static void rtl_slow_event_work(struct rtl8169_private *tp)
7499{
7500 struct net_device *dev = tp->dev;
7501 u16 status;
7502
7503 status = rtl_get_events(tp) & tp->event_slow;
7504 rtl_ack_events(tp, status);
1da177e4 7505
da78dbff
FR		 7506 if (unlikely(status & RxFIFOOver)) {
7507 switch (tp->mac_version) {
7508 /* Work around for rx fifo overflow */
7509 case RTL_GIGA_MAC_VER_11:
7510 netif_stop_queue(dev);
934714d0
FR		 7511 /* XXX - Hack alert. See rtl_task(). */
7512 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
da78dbff 7513 default:
f11a377b
DD		 7514 break;
7515 }
da78dbff 7516 }
1da177e4 7517
da78dbff
FR		 7518 if (unlikely(status & SYSErr))
7519 rtl8169_pcierr_interrupt(dev);
0e485150 7520
da78dbff
FR		 7521 if (status & LinkChg)
7522 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
1da177e4 7523
7dbb4918 7524 rtl_irq_enable_all(tp);
1da177e4
LT		 7525}
7526
4422bcd4
FR		 7527static void rtl_task(struct work_struct *work)
7528{
da78dbff
FR		 7529 static const struct {
7530 int bitnr;
7531 void (*action)(struct rtl8169_private *);
7532 } rtl_work[] = {
934714d0 7533 /* XXX - keep rtl_slow_event_work() as first element. */
da78dbff
FR		 7534 { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work },
7535 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
7536 { RTL_FLAG_TASK_PHY_PENDING, rtl_phy_work }
7537 };
4422bcd4
FR		 7538 struct rtl8169_private *tp =
7539 container_of(work, struct rtl8169_private, wk.work);
da78dbff
FR		 7540 struct net_device *dev = tp->dev;
7541 int i;
7542
7543 rtl_lock_work(tp);
7544
6c4a70c5
FR		 7545 if (!netif_running(dev) ||
7546 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
da78dbff
FR		 7547 goto out_unlock;
7548
7549 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
7550 bool pending;
7551
da78dbff 7552 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
da78dbff
FR		 7553 if (pending)
7554 rtl_work[i].action(tp);
7555 }
4422bcd4 7556
da78dbff
FR		 7557out_unlock:
7558 rtl_unlock_work(tp);
4422bcd4
FR		 7559}
7560
bea3348e 7561static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 7562{
bea3348e
SH		 7563 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
7564 struct net_device *dev = tp->dev;
da78dbff
FR		 7565 u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
7566 int work_done= 0;
7567 u16 status;
7568
7569 status = rtl_get_events(tp);
7570 rtl_ack_events(tp, status & ~tp->event_slow);
7571
7572 if (status & RTL_EVENT_NAPI_RX)
7573 work_done = rtl_rx(dev, tp, (u32) budget);
7574
7575 if (status & RTL_EVENT_NAPI_TX)
7576 rtl_tx(dev, tp);
1da177e4 7577
da78dbff
FR		 7578 if (status & tp->event_slow) {
7579 enable_mask &= ~tp->event_slow;
7580
7581 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
7582 }
1da177e4 7583
bea3348e 7584 if (work_done < budget) {
288379f0 7585 napi_complete(napi);
f11a377b 7586
da78dbff
FR		 7587 rtl_irq_enable(tp, enable_mask);
7588 mmiowb();
1da177e4
LT		 7589 }
7590
bea3348e 7591 return work_done;
1da177e4 7592}
1da177e4 7593
523a6094
FR		 7594static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
7595{
7596 struct rtl8169_private *tp = netdev_priv(dev);
7597
7598 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
7599 return;
7600
7601 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
7602 RTL_W32(RxMissed, 0);
7603}
7604
1da177e4
LT		 7605static void rtl8169_down(struct net_device *dev)
7606{
7607 struct rtl8169_private *tp = netdev_priv(dev);
7608 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 7609
4876cc1e 7610 del_timer_sync(&tp->timer);
1da177e4 7611
93dd79e8 7612 napi_disable(&tp->napi);
da78dbff 7613 netif_stop_queue(dev);
1da177e4 7614
92fc43b4 7615 rtl8169_hw_reset(tp);
323bb685
SG		 7616 /*
7617 * At this point device interrupts can not be enabled in any function,
209e5ac8
FR		 7618 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
7619 * and napi is disabled (rtl8169_poll).
323bb685 7620 */
523a6094 7621 rtl8169_rx_missed(dev, ioaddr);
1da177e4 7622
1da177e4 7623 /* Give a racing hard_start_xmit a few cycles to complete. */
da78dbff 7624 synchronize_sched();
1da177e4 7625
1da177e4
LT		 7626 rtl8169_tx_clear(tp);
7627
7628 rtl8169_rx_clear(tp);
065c27c1 7629
7630 rtl_pll_power_down(tp);
1da177e4
LT		 7631}
7632
7633static int rtl8169_close(struct net_device *dev)
7634{
7635 struct rtl8169_private *tp = netdev_priv(dev);
7636 struct pci_dev *pdev = tp->pci_dev;
7637
e1759441
RW		 7638 pm_runtime_get_sync(&pdev->dev);
7639
cecb5fd7 7640 /* Update counters before going down */
355423d0
IV		 7641 rtl8169_update_counters(dev);
7642
da78dbff 7643 rtl_lock_work(tp);
6c4a70c5 7644 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
da78dbff 7645
1da177e4 7646 rtl8169_down(dev);
da78dbff 7647 rtl_unlock_work(tp);
1da177e4 7648
4ea72445
L		 7649 cancel_work_sync(&tp->wk.work);
7650
92a7c4e7 7651 free_irq(pdev->irq, dev);
1da177e4 7652
82553bb6
SG		 7653 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7654 tp->RxPhyAddr);
7655 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7656 tp->TxPhyAddr);
1da177e4
LT		 7657 tp->TxDescArray = NULL;
7658 tp->RxDescArray = NULL;
7659
e1759441
RW		 7660 pm_runtime_put_sync(&pdev->dev);
7661
1da177e4
LT		 7662 return 0;
7663}
7664
dc1c00ce
FR		 7665#ifdef CONFIG_NET_POLL_CONTROLLER
7666static void rtl8169_netpoll(struct net_device *dev)
7667{
7668 struct rtl8169_private *tp = netdev_priv(dev);
7669
7670 rtl8169_interrupt(tp->pci_dev->irq, dev);
7671}
7672#endif
7673
df43ac78
FR		 7674static int rtl_open(struct net_device *dev)
7675{
7676 struct rtl8169_private *tp = netdev_priv(dev);
7677 void __iomem *ioaddr = tp->mmio_addr;
7678 struct pci_dev *pdev = tp->pci_dev;
7679 int retval = -ENOMEM;
7680
7681 pm_runtime_get_sync(&pdev->dev);
7682
7683 /*
e75d6606 7684 * Rx and Tx descriptors needs 256 bytes alignment.
df43ac78
FR		 7685 * dma_alloc_coherent provides more.
7686 */
7687 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
7688 &tp->TxPhyAddr, GFP_KERNEL);
7689 if (!tp->TxDescArray)
7690 goto err_pm_runtime_put;
7691
7692 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
7693 &tp->RxPhyAddr, GFP_KERNEL);
7694 if (!tp->RxDescArray)
7695 goto err_free_tx_0;
7696
7697 retval = rtl8169_init_ring(dev);
7698 if (retval < 0)
7699 goto err_free_rx_1;
7700
7701 INIT_WORK(&tp->wk.work, rtl_task);
7702
7703 smp_mb();
7704
7705 rtl_request_firmware(tp);
7706
92a7c4e7 7707 retval = request_irq(pdev->irq, rtl8169_interrupt,
df43ac78
FR		 7708 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
7709 dev->name, dev);
7710 if (retval < 0)
7711 goto err_release_fw_2;
7712
7713 rtl_lock_work(tp);
7714
7715 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7716
7717 napi_enable(&tp->napi);
7718
7719 rtl8169_init_phy(dev, tp);
7720
7721 __rtl8169_set_features(dev, dev->features);
7722
7723 rtl_pll_power_up(tp);
7724
7725 rtl_hw_start(dev);
7726
6e85d5ad
CV		 7727 if (!rtl8169_init_counter_offsets(dev))
7728 netif_warn(tp, hw, dev, "counter reset/update failed\n");
7729
df43ac78
FR		 7730 netif_start_queue(dev);
7731
7732 rtl_unlock_work(tp);
7733
7734 tp->saved_wolopts = 0;
7735 pm_runtime_put_noidle(&pdev->dev);
7736
7737 rtl8169_check_link_status(dev, tp, ioaddr);
7738out:
7739 return retval;
7740
7741err_release_fw_2:
7742 rtl_release_firmware(tp);
7743 rtl8169_rx_clear(tp);
7744err_free_rx_1:
7745 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7746 tp->RxPhyAddr);
7747 tp->RxDescArray = NULL;
7748err_free_tx_0:
7749 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7750 tp->TxPhyAddr);
7751 tp->TxDescArray = NULL;
7752err_pm_runtime_put:
7753 pm_runtime_put_noidle(&pdev->dev);
7754 goto out;
7755}
7756
8027aa24
JW		 7757static struct rtnl_link_stats64 *
7758rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
1da177e4
LT		 7759{
7760 struct rtl8169_private *tp = netdev_priv(dev);
7761 void __iomem *ioaddr = tp->mmio_addr;
f09cf4b7 7762 struct pci_dev *pdev = tp->pci_dev;
42020320 7763 struct rtl8169_counters *counters = tp->counters;
8027aa24 7764 unsigned int start;
1da177e4 7765
f09cf4b7
CHL		 7766 pm_runtime_get_noresume(&pdev->dev);
7767
7768 if (netif_running(dev) && pm_runtime_active(&pdev->dev))
523a6094 7769 rtl8169_rx_missed(dev, ioaddr);
5b0384f4 7770
8027aa24 7771 do {
57a7744e 7772 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
8027aa24
JW		 7773 stats->rx_packets = tp->rx_stats.packets;
7774 stats->rx_bytes = tp->rx_stats.bytes;
57a7744e 7775 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
8027aa24 7776
8027aa24 7777 do {
57a7744e 7778 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
8027aa24
JW		 7779 stats->tx_packets = tp->tx_stats.packets;
7780 stats->tx_bytes = tp->tx_stats.bytes;
57a7744e 7781 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
8027aa24
JW		 7782
7783 stats->rx_dropped = dev->stats.rx_dropped;
7784 stats->tx_dropped = dev->stats.tx_dropped;
7785 stats->rx_length_errors = dev->stats.rx_length_errors;
7786 stats->rx_errors = dev->stats.rx_errors;
7787 stats->rx_crc_errors = dev->stats.rx_crc_errors;
7788 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
7789 stats->rx_missed_errors = dev->stats.rx_missed_errors;
d7d2d89d 7790 stats->multicast = dev->stats.multicast;
8027aa24 7791
6e85d5ad
CV		 7792 /*
7793 * Fetch additonal counter values missing in stats collected by driver
7794 * from tally counters.
7795 */
f09cf4b7
CHL		 7796 if (pm_runtime_active(&pdev->dev))
7797 rtl8169_update_counters(dev);
6e85d5ad
CV		 7798
7799 /*
7800 * Subtract values fetched during initalization.
7801 * See rtl8169_init_counter_offsets for a description why we do that.
7802 */
42020320 7803 stats->tx_errors = le64_to_cpu(counters->tx_errors) -
6e85d5ad 7804 le64_to_cpu(tp->tc_offset.tx_errors);
42020320 7805 stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
6e85d5ad 7806 le32_to_cpu(tp->tc_offset.tx_multi_collision);
42020320 7807 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
6e85d5ad
CV		 7808 le16_to_cpu(tp->tc_offset.tx_aborted);
7809
f09cf4b7
CHL		 7810 pm_runtime_put_noidle(&pdev->dev);
7811
8027aa24 7812 return stats;
1da177e4
LT		 7813}
7814
861ab440 7815static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 7816{
065c27c1 7817 struct rtl8169_private *tp = netdev_priv(dev);
7818
5d06a99f 7819 if (!netif_running(dev))
861ab440 7820 return;
5d06a99f
FR		 7821
7822 netif_device_detach(dev);
7823 netif_stop_queue(dev);
da78dbff
FR		 7824
7825 rtl_lock_work(tp);
7826 napi_disable(&tp->napi);
6c4a70c5 7827 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
da78dbff
FR		 7828 rtl_unlock_work(tp);
7829
7830 rtl_pll_power_down(tp);
861ab440
RW		 7831}
7832
7833#ifdef CONFIG_PM
7834
7835static int rtl8169_suspend(struct device *device)
7836{
7837 struct pci_dev *pdev = to_pci_dev(device);
7838 struct net_device *dev = pci_get_drvdata(pdev);
5d06a99f 7839
861ab440 7840 rtl8169_net_suspend(dev);
1371fa6d 7841
5d06a99f
FR		 7842 return 0;
7843}
7844
e1759441
RW		 7845static void __rtl8169_resume(struct net_device *dev)
7846{
065c27c1 7847 struct rtl8169_private *tp = netdev_priv(dev);
7848
e1759441 7849 netif_device_attach(dev);
065c27c1 7850
7851 rtl_pll_power_up(tp);
7852
cff4c162
AS		 7853 rtl_lock_work(tp);
7854 napi_enable(&tp->napi);
6c4a70c5 7855 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
cff4c162 7856 rtl_unlock_work(tp);
da78dbff 7857
98ddf986 7858 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
e1759441
RW		 7859}
7860
861ab440 7861static int rtl8169_resume(struct device *device)
5d06a99f 7862{
861ab440 7863 struct pci_dev *pdev = to_pci_dev(device);
5d06a99f 7864 struct net_device *dev = pci_get_drvdata(pdev);
fccec10b
SG		 7865 struct rtl8169_private *tp = netdev_priv(dev);
7866
7867 rtl8169_init_phy(dev, tp);
5d06a99f 7868
e1759441
RW		 7869 if (netif_running(dev))
7870 __rtl8169_resume(dev);
5d06a99f 7871
e1759441
RW		 7872 return 0;
7873}
7874
7875static int rtl8169_runtime_suspend(struct device *device)
7876{
7877 struct pci_dev *pdev = to_pci_dev(device);
7878 struct net_device *dev = pci_get_drvdata(pdev);
7879 struct rtl8169_private *tp = netdev_priv(dev);
7880
7881 if (!tp->TxDescArray)
7882 return 0;
7883
da78dbff 7884 rtl_lock_work(tp);
e1759441
RW		 7885 tp->saved_wolopts = __rtl8169_get_wol(tp);
7886 __rtl8169_set_wol(tp, WAKE_ANY);
da78dbff 7887 rtl_unlock_work(tp);
e1759441
RW		 7888
7889 rtl8169_net_suspend(dev);
7890
f09cf4b7
CHL		 7891 /* Update counters before going runtime suspend */
7892 rtl8169_rx_missed(dev, tp->mmio_addr);
7893 rtl8169_update_counters(dev);
7894
e1759441
RW		 7895 return 0;
7896}
7897
7898static int rtl8169_runtime_resume(struct device *device)
7899{
7900 struct pci_dev *pdev = to_pci_dev(device);
7901 struct net_device *dev = pci_get_drvdata(pdev);
7902 struct rtl8169_private *tp = netdev_priv(dev);
f51d4a10 7903 rtl_rar_set(tp, dev->dev_addr);
e1759441
RW		 7904
7905 if (!tp->TxDescArray)
7906 return 0;
7907
da78dbff 7908 rtl_lock_work(tp);
e1759441
RW		 7909 __rtl8169_set_wol(tp, tp->saved_wolopts);
7910 tp->saved_wolopts = 0;
da78dbff 7911 rtl_unlock_work(tp);
e1759441 7912
fccec10b
SG		 7913 rtl8169_init_phy(dev, tp);
7914
e1759441 7915 __rtl8169_resume(dev);
5d06a99f 7916
5d06a99f
FR		 7917 return 0;
7918}
7919
e1759441
RW		 7920static int rtl8169_runtime_idle(struct device *device)
7921{
7922 struct pci_dev *pdev = to_pci_dev(device);
7923 struct net_device *dev = pci_get_drvdata(pdev);
7924 struct rtl8169_private *tp = netdev_priv(dev);
7925
e4fbce74 7926 return tp->TxDescArray ? -EBUSY : 0;
e1759441
RW		 7927}
7928
47145210 7929static const struct dev_pm_ops rtl8169_pm_ops = {
cecb5fd7
FR		 7930 .suspend = rtl8169_suspend,
7931 .resume = rtl8169_resume,
7932 .freeze = rtl8169_suspend,
7933 .thaw = rtl8169_resume,
7934 .poweroff = rtl8169_suspend,
7935 .restore = rtl8169_resume,
7936 .runtime_suspend = rtl8169_runtime_suspend,
7937 .runtime_resume = rtl8169_runtime_resume,
7938 .runtime_idle = rtl8169_runtime_idle,
861ab440
RW		 7939};
7940
7941#define RTL8169_PM_OPS (&rtl8169_pm_ops)
7942
7943#else /* !CONFIG_PM */
7944
7945#define RTL8169_PM_OPS NULL
7946
7947#endif /* !CONFIG_PM */
7948
649b3b8c 7949static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
7950{
7951 void __iomem *ioaddr = tp->mmio_addr;
7952
7953 /* WoL fails with 8168b when the receiver is disabled. */
7954 switch (tp->mac_version) {
7955 case RTL_GIGA_MAC_VER_11:
7956 case RTL_GIGA_MAC_VER_12:
7957 case RTL_GIGA_MAC_VER_17:
7958 pci_clear_master(tp->pci_dev);
7959
7960 RTL_W8(ChipCmd, CmdRxEnb);
7961 /* PCI commit */
7962 RTL_R8(ChipCmd);
7963 break;
7964 default:
7965 break;
7966 }
7967}
7968
1765f95d
FR		 7969static void rtl_shutdown(struct pci_dev *pdev)
7970{
861ab440 7971 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 7972 struct rtl8169_private *tp = netdev_priv(dev);
2a15cd2f 7973 struct device *d = &pdev->dev;
7974
7975 pm_runtime_get_sync(d);
861ab440
RW		 7976
7977 rtl8169_net_suspend(dev);
1765f95d 7978
cecb5fd7 7979 /* Restore original MAC address */
cc098dc7
IV		 7980 rtl_rar_set(tp, dev->perm_addr);
7981
92fc43b4 7982 rtl8169_hw_reset(tp);
4bb3f522 7983
861ab440 7984 if (system_state == SYSTEM_POWER_OFF) {
649b3b8c 7985 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
7986 rtl_wol_suspend_quirk(tp);
7987 rtl_wol_shutdown_quirk(tp);
ca52efd5 7988 }
7989
861ab440
RW		 7990 pci_wake_from_d3(pdev, true);
7991 pci_set_power_state(pdev, PCI_D3hot);
7992 }
2a15cd2f 7993
7994 pm_runtime_put_noidle(d);
861ab440 7995}
5d06a99f 7996
baf63293 7997static void rtl_remove_one(struct pci_dev *pdev)
e27566ed
FR		 7998{
7999 struct net_device *dev = pci_get_drvdata(pdev);
8000 struct rtl8169_private *tp = netdev_priv(dev);
8001
ee7a1beb
CHL		 8002 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
8003 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
935e2218
CHL		 8004 tp->mac_version == RTL_GIGA_MAC_VER_31 ||
8005 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
8006 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
8007 tp->mac_version == RTL_GIGA_MAC_VER_51) &&
ee7a1beb 8008 r8168_check_dash(tp)) {
e27566ed
FR		 8009 rtl8168_driver_stop(tp);
8010 }
8011
ad1be8d3
DN		 8012 netif_napi_del(&tp->napi);
8013
e27566ed
FR		 8014 unregister_netdev(dev);
8015
42020320
CV		 8016 dma_free_coherent(&tp->pci_dev->dev, sizeof(*tp->counters),
8017 tp->counters, tp->counters_phys_addr);
8018
e27566ed
FR		 8019 rtl_release_firmware(tp);
8020
8021 if (pci_dev_run_wake(pdev))
8022 pm_runtime_get_noresume(&pdev->dev);
8023
8024 /* restore original MAC address */
8025 rtl_rar_set(tp, dev->perm_addr);
8026
8027 rtl_disable_msi(pdev, tp);
8028 rtl8169_release_board(pdev, dev, tp->mmio_addr);
e27566ed
FR		 8029}
8030
fa9c385e 8031static const struct net_device_ops rtl_netdev_ops = {
df43ac78 8032 .ndo_open = rtl_open,
fa9c385e
FR		 8033 .ndo_stop = rtl8169_close,
8034 .ndo_get_stats64 = rtl8169_get_stats64,
8035 .ndo_start_xmit = rtl8169_start_xmit,
8036 .ndo_tx_timeout = rtl8169_tx_timeout,
8037 .ndo_validate_addr = eth_validate_addr,
8038 .ndo_change_mtu = rtl8169_change_mtu,
8039 .ndo_fix_features = rtl8169_fix_features,
8040 .ndo_set_features = rtl8169_set_features,
8041 .ndo_set_mac_address = rtl_set_mac_address,
8042 .ndo_do_ioctl = rtl8169_ioctl,
8043 .ndo_set_rx_mode = rtl_set_rx_mode,
8044#ifdef CONFIG_NET_POLL_CONTROLLER
8045 .ndo_poll_controller = rtl8169_netpoll,
8046#endif
8047
8048};
8049
31fa8b18
FR		 8050static const struct rtl_cfg_info {
8051 void (*hw_start)(struct net_device *);
8052 unsigned int region;
8053 unsigned int align;
8054 u16 event_slow;
8055 unsigned features;
8056 u8 default_ver;
8057} rtl_cfg_infos [] = {
8058 [RTL_CFG_0] = {
8059 .hw_start = rtl_hw_start_8169,
8060 .region = 1,
8061 .align = 0,
8062 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
8063 .features = RTL_FEATURE_GMII,
8064 .default_ver = RTL_GIGA_MAC_VER_01,
8065 },
8066 [RTL_CFG_1] = {
8067 .hw_start = rtl_hw_start_8168,
8068 .region = 2,
8069 .align = 8,
8070 .event_slow = SYSErr | LinkChg | RxOverflow,
8071 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
8072 .default_ver = RTL_GIGA_MAC_VER_11,
8073 },
8074 [RTL_CFG_2] = {
8075 .hw_start = rtl_hw_start_8101,
8076 .region = 2,
8077 .align = 8,
8078 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
8079 PCSTimeout,
8080 .features = RTL_FEATURE_MSI,
8081 .default_ver = RTL_GIGA_MAC_VER_13,
8082 }
8083};
8084
8085/* Cfg9346_Unlock assumed. */
8086static unsigned rtl_try_msi(struct rtl8169_private *tp,
8087 const struct rtl_cfg_info *cfg)
8088{
8089 void __iomem *ioaddr = tp->mmio_addr;
8090 unsigned msi = 0;
8091 u8 cfg2;
8092
8093 cfg2 = RTL_R8(Config2) & ~MSIEnable;
8094 if (cfg->features & RTL_FEATURE_MSI) {
8095 if (pci_enable_msi(tp->pci_dev)) {
8096 netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
8097 } else {
8098 cfg2 |= MSIEnable;
8099 msi = RTL_FEATURE_MSI;
8100 }
8101 }
8102 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
8103 RTL_W8(Config2, cfg2);
8104 return msi;
8105}
8106
c558386b
HW		 8107DECLARE_RTL_COND(rtl_link_list_ready_cond)
8108{
8109 void __iomem *ioaddr = tp->mmio_addr;
8110
8111 return RTL_R8(MCU) & LINK_LIST_RDY;
8112}
8113
8114DECLARE_RTL_COND(rtl_rxtx_empty_cond)
8115{
8116 void __iomem *ioaddr = tp->mmio_addr;
8117
8118 return (RTL_R8(MCU) & RXTX_EMPTY) == RXTX_EMPTY;
8119}
8120
baf63293 8121static void rtl_hw_init_8168g(struct rtl8169_private *tp)
c558386b
HW		 8122{
8123 void __iomem *ioaddr = tp->mmio_addr;
8124 u32 data;
8125
8126 tp->ocp_base = OCP_STD_PHY_BASE;
8127
8128 RTL_W32(MISC, RTL_R32(MISC) | RXDV_GATED_EN);
8129
8130 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
8131 return;
8132
8133 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
8134 return;
8135
8136 RTL_W8(ChipCmd, RTL_R8(ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
8137 msleep(1);
8138 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
8139
5f8bcce9 8140 data = r8168_mac_ocp_read(tp, 0xe8de);
c558386b
HW		 8141 data &= ~(1 << 14);
8142 r8168_mac_ocp_write(tp, 0xe8de, data);
8143
8144 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
8145 return;
8146
5f8bcce9 8147 data = r8168_mac_ocp_read(tp, 0xe8de);
c558386b
HW		 8148 data |= (1 << 15);
8149 r8168_mac_ocp_write(tp, 0xe8de, data);
8150
8151 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
8152 return;
8153}
8154
003609da
CHL		 8155static void rtl_hw_init_8168ep(struct rtl8169_private *tp)
8156{
8157 rtl8168ep_stop_cmac(tp);
8158 rtl_hw_init_8168g(tp);
8159}
8160
baf63293 8161static void rtl_hw_initialize(struct rtl8169_private *tp)
c558386b
HW		 8162{
8163 switch (tp->mac_version) {
8164 case RTL_GIGA_MAC_VER_40:
8165 case RTL_GIGA_MAC_VER_41:
57538c4a 8166 case RTL_GIGA_MAC_VER_42:
58152cd4 8167 case RTL_GIGA_MAC_VER_43:
45dd95c4 8168 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 8169 case RTL_GIGA_MAC_VER_45:
8170 case RTL_GIGA_MAC_VER_46:
8171 case RTL_GIGA_MAC_VER_47:
8172 case RTL_GIGA_MAC_VER_48:
003609da
CHL		 8173 rtl_hw_init_8168g(tp);
8174 break;
935e2218
CHL		 8175 case RTL_GIGA_MAC_VER_49:
8176 case RTL_GIGA_MAC_VER_50:
8177 case RTL_GIGA_MAC_VER_51:
003609da 8178 rtl_hw_init_8168ep(tp);
c558386b 8179 break;
c558386b
HW		 8180 default:
8181 break;
8182 }
8183}
8184
929a031d 8185static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3b6cf25d
FR		 8186{
8187 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
8188 const unsigned int region = cfg->region;
8189 struct rtl8169_private *tp;
8190 struct mii_if_info *mii;
8191 struct net_device *dev;
8192 void __iomem *ioaddr;
8193 int chipset, i;
8194 int rc;
8195
8196 if (netif_msg_drv(&debug)) {
8197 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
8198 MODULENAME, RTL8169_VERSION);
8199 }
8200
8201 dev = alloc_etherdev(sizeof (*tp));
8202 if (!dev) {
8203 rc = -ENOMEM;
8204 goto out;
8205 }
8206
8207 SET_NETDEV_DEV(dev, &pdev->dev);
fa9c385e 8208 dev->netdev_ops = &rtl_netdev_ops;
3b6cf25d
FR		 8209 tp = netdev_priv(dev);
8210 tp->dev = dev;
8211 tp->pci_dev = pdev;
8212 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
8213
8214 mii = &tp->mii;
8215 mii->dev = dev;
8216 mii->mdio_read = rtl_mdio_read;
8217 mii->mdio_write = rtl_mdio_write;
8218 mii->phy_id_mask = 0x1f;
8219 mii->reg_num_mask = 0x1f;
8220 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
8221
8222 /* disable ASPM completely as that cause random device stop working
8223 * problems as well as full system hangs for some PCIe devices users */
8224 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
8225 PCIE_LINK_STATE_CLKPM);
8226
8227 /* enable device (incl. PCI PM wakeup and hotplug setup) */
8228 rc = pci_enable_device(pdev);
8229 if (rc < 0) {
8230 netif_err(tp, probe, dev, "enable failure\n");
8231 goto err_out_free_dev_1;
8232 }
8233
8234 if (pci_set_mwi(pdev) < 0)
8235 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
8236
8237 /* make sure PCI base addr 1 is MMIO */
8238 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
8239 netif_err(tp, probe, dev,
8240 "region #%d not an MMIO resource, aborting\n",
8241 region);
8242 rc = -ENODEV;
8243 goto err_out_mwi_2;
8244 }
8245
8246 /* check for weird/broken PCI region reporting */
8247 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
8248 netif_err(tp, probe, dev,
8249 "Invalid PCI region size(s), aborting\n");
8250 rc = -ENODEV;
8251 goto err_out_mwi_2;
8252 }
8253
8254 rc = pci_request_regions(pdev, MODULENAME);
8255 if (rc < 0) {
8256 netif_err(tp, probe, dev, "could not request regions\n");
8257 goto err_out_mwi_2;
8258 }
8259
3b6cf25d
FR		 8260 /* ioremap MMIO region */
8261 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
8262 if (!ioaddr) {
8263 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
8264 rc = -EIO;
8265 goto err_out_free_res_3;
8266 }
8267 tp->mmio_addr = ioaddr;
8268
8269 if (!pci_is_pcie(pdev))
8270 netif_info(tp, probe, dev, "not PCI Express\n");
8271
8272 /* Identify chip attached to board */
8273 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
8274
27896c83
AB		 8275 tp->cp_cmd = 0;
8276
8277 if ((sizeof(dma_addr_t) > 4) &&
8278 (use_dac == 1 || (use_dac == -1 && pci_is_pcie(pdev) &&
8279 tp->mac_version >= RTL_GIGA_MAC_VER_18)) &&
f0076436
AB		 8280 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
8281 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
27896c83
AB		 8282
8283 /* CPlusCmd Dual Access Cycle is only needed for non-PCIe */
8284 if (!pci_is_pcie(pdev))
8285 tp->cp_cmd |= PCIDAC;
8286 dev->features |= NETIF_F_HIGHDMA;
8287 } else {
8288 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
8289 if (rc < 0) {
8290 netif_err(tp, probe, dev, "DMA configuration failed\n");
8291 goto err_out_unmap_4;
8292 }
8293 }
8294
3b6cf25d
FR		 8295 rtl_init_rxcfg(tp);
8296
8297 rtl_irq_disable(tp);
8298
c558386b
HW		 8299 rtl_hw_initialize(tp);
8300
3b6cf25d
FR		 8301 rtl_hw_reset(tp);
8302
8303 rtl_ack_events(tp, 0xffff);
8304
8305 pci_set_master(pdev);
8306
3b6cf25d
FR		 8307 rtl_init_mdio_ops(tp);
8308 rtl_init_pll_power_ops(tp);
8309 rtl_init_jumbo_ops(tp);
beb1fe18 8310 rtl_init_csi_ops(tp);
3b6cf25d
FR		 8311
8312 rtl8169_print_mac_version(tp);
8313
8314 chipset = tp->mac_version;
8315 tp->txd_version = rtl_chip_infos[chipset].txd_version;
8316
8317 RTL_W8(Cfg9346, Cfg9346_Unlock);
8318 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
8f9d5138 8319 RTL_W8(Config5, RTL_R8(Config5) & (BWF | MWF | UWF | LanWake | PMEStatus));
6e1d0b89 8320 switch (tp->mac_version) {
ac85bcdb
CHL		 8321 case RTL_GIGA_MAC_VER_34:
8322 case RTL_GIGA_MAC_VER_35:
8323 case RTL_GIGA_MAC_VER_36:
8324 case RTL_GIGA_MAC_VER_37:
8325 case RTL_GIGA_MAC_VER_38:
8326 case RTL_GIGA_MAC_VER_40:
8327 case RTL_GIGA_MAC_VER_41:
8328 case RTL_GIGA_MAC_VER_42:
8329 case RTL_GIGA_MAC_VER_43:
8330 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 8331 case RTL_GIGA_MAC_VER_45:
8332 case RTL_GIGA_MAC_VER_46:
ac85bcdb
CHL		 8333 case RTL_GIGA_MAC_VER_47:
8334 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 8335 case RTL_GIGA_MAC_VER_49:
8336 case RTL_GIGA_MAC_VER_50:
8337 case RTL_GIGA_MAC_VER_51:
6e1d0b89
CHL		 8338 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
8339 tp->features |= RTL_FEATURE_WOL;
8340 if ((RTL_R8(Config3) & LinkUp) != 0)
8341 tp->features |= RTL_FEATURE_WOL;
8342 break;
8343 default:
8344 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
8345 tp->features |= RTL_FEATURE_WOL;
8346 break;
8347 }
3b6cf25d
FR		 8348 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
8349 tp->features |= RTL_FEATURE_WOL;
8350 tp->features |= rtl_try_msi(tp, cfg);
8351 RTL_W8(Cfg9346, Cfg9346_Lock);
8352
8353 if (rtl_tbi_enabled(tp)) {
8354 tp->set_speed = rtl8169_set_speed_tbi;
8355 tp->get_settings = rtl8169_gset_tbi;
8356 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
8357 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
8358 tp->link_ok = rtl8169_tbi_link_ok;
8359 tp->do_ioctl = rtl_tbi_ioctl;
8360 } else {
8361 tp->set_speed = rtl8169_set_speed_xmii;
8362 tp->get_settings = rtl8169_gset_xmii;
8363 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
8364 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
8365 tp->link_ok = rtl8169_xmii_link_ok;
8366 tp->do_ioctl = rtl_xmii_ioctl;
8367 }
8368
8369 mutex_init(&tp->wk.mutex);
340fea3d
KM		 8370 u64_stats_init(&tp->rx_stats.syncp);
8371 u64_stats_init(&tp->tx_stats.syncp);
3b6cf25d
FR		 8372
8373 /* Get MAC address */
89cceb27
CHL		 8374 if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
8375 tp->mac_version == RTL_GIGA_MAC_VER_36 ||
8376 tp->mac_version == RTL_GIGA_MAC_VER_37 ||
8377 tp->mac_version == RTL_GIGA_MAC_VER_38 ||
8378 tp->mac_version == RTL_GIGA_MAC_VER_40 ||
8379 tp->mac_version == RTL_GIGA_MAC_VER_41 ||
8380 tp->mac_version == RTL_GIGA_MAC_VER_42 ||
8381 tp->mac_version == RTL_GIGA_MAC_VER_43 ||
8382 tp->mac_version == RTL_GIGA_MAC_VER_44 ||
8383 tp->mac_version == RTL_GIGA_MAC_VER_45 ||
6e1d0b89
CHL		 8384 tp->mac_version == RTL_GIGA_MAC_VER_46 ||
8385 tp->mac_version == RTL_GIGA_MAC_VER_47 ||
935e2218
CHL		 8386 tp->mac_version == RTL_GIGA_MAC_VER_48 ||
8387 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
8388 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
8389 tp->mac_version == RTL_GIGA_MAC_VER_51) {
6e1d0b89
CHL		 8390 u16 mac_addr[3];
8391
05b9687b
CHL		 8392 *(u32 *)&mac_addr[0] = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC);
8393 *(u16 *)&mac_addr[2] = rtl_eri_read(tp, 0xe4, ERIAR_EXGMAC);
6e1d0b89
CHL		 8394
8395 if (is_valid_ether_addr((u8 *)mac_addr))
8396 rtl_rar_set(tp, (u8 *)mac_addr);
8397 }
3b6cf25d
FR		 8398 for (i = 0; i < ETH_ALEN; i++)
8399 dev->dev_addr[i] = RTL_R8(MAC0 + i);
3b6cf25d 8400
7ad24ea4 8401 dev->ethtool_ops = &rtl8169_ethtool_ops;
3b6cf25d 8402 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3b6cf25d
FR		 8403
8404 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
8405
8406 /* don't enable SG, IP_CSUM and TSO by default - it might not work
8407 * properly for all devices */
8408 dev->features |= NETIF_F_RXCSUM |
f646968f 8409 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d
FR		 8410
8411 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
f646968f
PM		 8412 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
8413 NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d
FR		 8414 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
8415 NETIF_F_HIGHDMA;
8416
929a031d 8417 tp->cp_cmd |= RxChkSum | RxVlan;
8418
8419 /*
8420 * Pretend we are using VLANs; This bypasses a nasty bug where
8421 * Interrupts stop flowing on high load on 8110SCd controllers.
8422 */
3b6cf25d 8423 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
929a031d 8424 /* Disallow toggling */
f646968f 8425 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d 8426
5888d3fc 8427 if (tp->txd_version == RTL_TD_0)
8428 tp->tso_csum = rtl8169_tso_csum_v1;
e974604b 8429 else if (tp->txd_version == RTL_TD_1) {
5888d3fc 8430 tp->tso_csum = rtl8169_tso_csum_v2;
e974604b 8431 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
8432 } else
5888d3fc 8433 WARN_ON_ONCE(1);
8434
3b6cf25d
FR		 8435 dev->hw_features |= NETIF_F_RXALL;
8436 dev->hw_features |= NETIF_F_RXFCS;
8437
c7315a95
JW		 8438 /* MTU range: 60 - hw-specific max */
8439 dev->min_mtu = ETH_ZLEN;
8440 dev->max_mtu = rtl_chip_infos[chipset].jumbo_max;
8441
3b6cf25d
FR		 8442 tp->hw_start = cfg->hw_start;
8443 tp->event_slow = cfg->event_slow;
8444
8445 tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
8446 ~(RxBOVF | RxFOVF) : ~0;
8447
8448 init_timer(&tp->timer);
8449 tp->timer.data = (unsigned long) dev;
8450 tp->timer.function = rtl8169_phy_timer;
8451
8452 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
8453
42020320
CV		 8454 tp->counters = dma_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
8455 &tp->counters_phys_addr, GFP_KERNEL);
8456 if (!tp->counters) {
8457 rc = -ENOMEM;
27896c83 8458 goto err_out_msi_5;
42020320
CV		 8459 }
8460
3b6cf25d
FR		 8461 rc = register_netdev(dev);
8462 if (rc < 0)
27896c83 8463 goto err_out_cnt_6;
3b6cf25d
FR		 8464
8465 pci_set_drvdata(pdev, dev);
8466
92a7c4e7
FR		 8467 netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
8468 rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
8469 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
3b6cf25d
FR		 8470 if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
8471 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
8472 "tx checksumming: %s]\n",
8473 rtl_chip_infos[chipset].jumbo_max,
8474 rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
8475 }
8476
ee7a1beb
CHL		 8477 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
8478 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
935e2218
CHL		 8479 tp->mac_version == RTL_GIGA_MAC_VER_31 ||
8480 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
8481 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
8482 tp->mac_version == RTL_GIGA_MAC_VER_51) &&
ee7a1beb 8483 r8168_check_dash(tp)) {
3b6cf25d
FR		 8484 rtl8168_driver_start(tp);
8485 }
8486
8487 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
8488
8489 if (pci_dev_run_wake(pdev))
8490 pm_runtime_put_noidle(&pdev->dev);
8491
8492 netif_carrier_off(dev);
8493
8494out:
8495 return rc;
8496
27896c83 8497err_out_cnt_6:
42020320
CV		 8498 dma_free_coherent(&pdev->dev, sizeof(*tp->counters), tp->counters,
8499 tp->counters_phys_addr);
27896c83 8500err_out_msi_5:
ad1be8d3 8501 netif_napi_del(&tp->napi);
3b6cf25d 8502 rtl_disable_msi(pdev, tp);
27896c83 8503err_out_unmap_4:
3b6cf25d
FR		 8504 iounmap(ioaddr);
8505err_out_free_res_3:
8506 pci_release_regions(pdev);
8507err_out_mwi_2:
8508 pci_clear_mwi(pdev);
8509 pci_disable_device(pdev);
8510err_out_free_dev_1:
8511 free_netdev(dev);
8512 goto out;
8513}
8514
1da177e4
LT		 8515static struct pci_driver rtl8169_pci_driver = {
8516 .name = MODULENAME,
8517 .id_table = rtl8169_pci_tbl,
3b6cf25d 8518 .probe = rtl_init_one,
baf63293 8519 .remove = rtl_remove_one,
1765f95d 8520 .shutdown = rtl_shutdown,
861ab440 8521 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 8522};
8523
3eeb7da9 8524module_pci_driver(rtl8169_pci_driver);
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