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Merge branch 'for-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/bluetoot...
[mirror_ubuntu-focal-kernel.git] / drivers / net / ethernet / realtek / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
a6b7a407 24#include <linux/interrupt.h>
1da177e4 25#include <linux/dma-mapping.h>
e1759441 26#include <linux/pm_runtime.h>
bca03d5f 27#include <linux/firmware.h>
ba04c7c9 28#include <linux/pci-aspm.h>
70c71606 29#include <linux/prefetch.h>
e974604b 30#include <linux/ipv6.h>
31#include <net/ip6_checksum.h>
1da177e4
LT		 32
33#include <asm/io.h>
34#include <asm/irq.h>
35
865c652d 36#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 37#define MODULENAME "r8169"
38#define PFX MODULENAME ": "
39
bca03d5f 40#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
41#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
01dc7fec 42#define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
43#define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
70090424 44#define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
c2218925
HW		 45#define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
46#define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
5a5e4443 47#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
7e18dca1 48#define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
b3d7b2f2 49#define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
45dd95c4 50#define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
5598bfe5 51#define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
58152cd4 52#define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
beb330a4 53#define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
57538c4a 54#define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
6e1d0b89
CHL		 55#define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw"
56#define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
57#define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw"
58#define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
bca03d5f 59
1da177e4
LT		 60#ifdef RTL8169_DEBUG
61#define assert(expr) \
5b0384f4
FR		 62 if (!(expr)) { \
63 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
b39d66a8 64 #expr,__FILE__,__func__,__LINE__); \
5b0384f4 65 }
06fa7358
JP		 66#define dprintk(fmt, args...) \
67 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 68#else
69#define assert(expr) do {} while (0)
70#define dprintk(fmt, args...) do {} while (0)
71#endif /* RTL8169_DEBUG */
72
b57b7e5a 73#define R8169_MSG_DEFAULT \
f0e837d9 74 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 75
477206a0
JD		 76#define TX_SLOTS_AVAIL(tp) \
77 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
78
79/* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
80#define TX_FRAGS_READY_FOR(tp,nr_frags) \
81 (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
1da177e4 82
1da177e4
LT		 83/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
84 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 85static const int multicast_filter_limit = 32;
1da177e4 86
9c14ceaf 87#define MAX_READ_REQUEST_SHIFT 12
aee77e4a 88#define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
1da177e4
LT		 89#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
90
91#define R8169_REGS_SIZE 256
92#define R8169_NAPI_WEIGHT 64
93#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
9fba0812 94#define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
1da177e4
LT		 95#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
96#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
97
98#define RTL8169_TX_TIMEOUT (6*HZ)
99#define RTL8169_PHY_TIMEOUT (10*HZ)
100
101/* write/read MMIO register */
102#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
103#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
104#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
105#define RTL_R8(reg) readb (ioaddr + (reg))
106#define RTL_R16(reg) readw (ioaddr + (reg))
06f555f3 107#define RTL_R32(reg) readl (ioaddr + (reg))
1da177e4
LT		 108
109enum mac_version {
85bffe6c
FR		 110 RTL_GIGA_MAC_VER_01 = 0,
111 RTL_GIGA_MAC_VER_02,
112 RTL_GIGA_MAC_VER_03,
113 RTL_GIGA_MAC_VER_04,
114 RTL_GIGA_MAC_VER_05,
115 RTL_GIGA_MAC_VER_06,
116 RTL_GIGA_MAC_VER_07,
117 RTL_GIGA_MAC_VER_08,
118 RTL_GIGA_MAC_VER_09,
119 RTL_GIGA_MAC_VER_10,
120 RTL_GIGA_MAC_VER_11,
121 RTL_GIGA_MAC_VER_12,
122 RTL_GIGA_MAC_VER_13,
123 RTL_GIGA_MAC_VER_14,
124 RTL_GIGA_MAC_VER_15,
125 RTL_GIGA_MAC_VER_16,
126 RTL_GIGA_MAC_VER_17,
127 RTL_GIGA_MAC_VER_18,
128 RTL_GIGA_MAC_VER_19,
129 RTL_GIGA_MAC_VER_20,
130 RTL_GIGA_MAC_VER_21,
131 RTL_GIGA_MAC_VER_22,
132 RTL_GIGA_MAC_VER_23,
133 RTL_GIGA_MAC_VER_24,
134 RTL_GIGA_MAC_VER_25,
135 RTL_GIGA_MAC_VER_26,
136 RTL_GIGA_MAC_VER_27,
137 RTL_GIGA_MAC_VER_28,
138 RTL_GIGA_MAC_VER_29,
139 RTL_GIGA_MAC_VER_30,
140 RTL_GIGA_MAC_VER_31,
141 RTL_GIGA_MAC_VER_32,
142 RTL_GIGA_MAC_VER_33,
70090424 143 RTL_GIGA_MAC_VER_34,
c2218925
HW		 144 RTL_GIGA_MAC_VER_35,
145 RTL_GIGA_MAC_VER_36,
7e18dca1 146 RTL_GIGA_MAC_VER_37,
b3d7b2f2 147 RTL_GIGA_MAC_VER_38,
5598bfe5 148 RTL_GIGA_MAC_VER_39,
c558386b
HW		 149 RTL_GIGA_MAC_VER_40,
150 RTL_GIGA_MAC_VER_41,
57538c4a 151 RTL_GIGA_MAC_VER_42,
58152cd4 152 RTL_GIGA_MAC_VER_43,
45dd95c4 153 RTL_GIGA_MAC_VER_44,
6e1d0b89
CHL		 154 RTL_GIGA_MAC_VER_45,
155 RTL_GIGA_MAC_VER_46,
156 RTL_GIGA_MAC_VER_47,
157 RTL_GIGA_MAC_VER_48,
935e2218
CHL		 158 RTL_GIGA_MAC_VER_49,
159 RTL_GIGA_MAC_VER_50,
160 RTL_GIGA_MAC_VER_51,
85bffe6c 161 RTL_GIGA_MAC_NONE = 0xff,
1da177e4
LT		 162};
163
2b7b4318
FR		 164enum rtl_tx_desc_version {
165 RTL_TD_0 = 0,
166 RTL_TD_1 = 1,
167};
168
d58d46b5
FR		 169#define JUMBO_1K ETH_DATA_LEN
170#define JUMBO_4K (4*1024 - ETH_HLEN - 2)
171#define JUMBO_6K (6*1024 - ETH_HLEN - 2)
172#define JUMBO_7K (7*1024 - ETH_HLEN - 2)
173#define JUMBO_9K (9*1024 - ETH_HLEN - 2)
174
175#define _R(NAME,TD,FW,SZ,B) { \
176 .name = NAME, \
177 .txd_version = TD, \
178 .fw_name = FW, \
179 .jumbo_max = SZ, \
180 .jumbo_tx_csum = B \
181}
1da177e4 182
3c6bee1d 183static const struct {
1da177e4 184 const char *name;
2b7b4318 185 enum rtl_tx_desc_version txd_version;
953a12cc 186 const char *fw_name;
d58d46b5
FR		 187 u16 jumbo_max;
188 bool jumbo_tx_csum;
85bffe6c
FR		 189} rtl_chip_infos[] = {
190 /* PCI devices. */
191 [RTL_GIGA_MAC_VER_01] =
d58d46b5 192 _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 193 [RTL_GIGA_MAC_VER_02] =
d58d46b5 194 _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 195 [RTL_GIGA_MAC_VER_03] =
d58d46b5 196 _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 197 [RTL_GIGA_MAC_VER_04] =
d58d46b5 198 _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 199 [RTL_GIGA_MAC_VER_05] =
d58d46b5 200 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 201 [RTL_GIGA_MAC_VER_06] =
d58d46b5 202 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c
FR		 203 /* PCI-E devices. */
204 [RTL_GIGA_MAC_VER_07] =
d58d46b5 205 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 206 [RTL_GIGA_MAC_VER_08] =
d58d46b5 207 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 208 [RTL_GIGA_MAC_VER_09] =
d58d46b5 209 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 210 [RTL_GIGA_MAC_VER_10] =
d58d46b5 211 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 212 [RTL_GIGA_MAC_VER_11] =
d58d46b5 213 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
85bffe6c 214 [RTL_GIGA_MAC_VER_12] =
d58d46b5 215 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
85bffe6c 216 [RTL_GIGA_MAC_VER_13] =
d58d46b5 217 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 218 [RTL_GIGA_MAC_VER_14] =
d58d46b5 219 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 220 [RTL_GIGA_MAC_VER_15] =
d58d46b5 221 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 222 [RTL_GIGA_MAC_VER_16] =
d58d46b5 223 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 224 [RTL_GIGA_MAC_VER_17] =
f75761b6 225 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
85bffe6c 226 [RTL_GIGA_MAC_VER_18] =
d58d46b5 227 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 228 [RTL_GIGA_MAC_VER_19] =
d58d46b5 229 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 230 [RTL_GIGA_MAC_VER_20] =
d58d46b5 231 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 232 [RTL_GIGA_MAC_VER_21] =
d58d46b5 233 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 234 [RTL_GIGA_MAC_VER_22] =
d58d46b5 235 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 236 [RTL_GIGA_MAC_VER_23] =
d58d46b5 237 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 238 [RTL_GIGA_MAC_VER_24] =
d58d46b5 239 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 240 [RTL_GIGA_MAC_VER_25] =
d58d46b5
FR		 241 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1,
242 JUMBO_9K, false),
85bffe6c 243 [RTL_GIGA_MAC_VER_26] =
d58d46b5
FR		 244 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2,
245 JUMBO_9K, false),
85bffe6c 246 [RTL_GIGA_MAC_VER_27] =
d58d46b5 247 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 248 [RTL_GIGA_MAC_VER_28] =
d58d46b5 249 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 250 [RTL_GIGA_MAC_VER_29] =
d58d46b5
FR		 251 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
252 JUMBO_1K, true),
85bffe6c 253 [RTL_GIGA_MAC_VER_30] =
d58d46b5
FR		 254 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
255 JUMBO_1K, true),
85bffe6c 256 [RTL_GIGA_MAC_VER_31] =
d58d46b5 257 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 258 [RTL_GIGA_MAC_VER_32] =
d58d46b5
FR		 259 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1,
260 JUMBO_9K, false),
85bffe6c 261 [RTL_GIGA_MAC_VER_33] =
d58d46b5
FR		 262 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2,
263 JUMBO_9K, false),
70090424 264 [RTL_GIGA_MAC_VER_34] =
d58d46b5
FR		 265 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
266 JUMBO_9K, false),
c2218925 267 [RTL_GIGA_MAC_VER_35] =
d58d46b5
FR		 268 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1,
269 JUMBO_9K, false),
c2218925 270 [RTL_GIGA_MAC_VER_36] =
d58d46b5
FR		 271 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2,
272 JUMBO_9K, false),
7e18dca1
HW		 273 [RTL_GIGA_MAC_VER_37] =
274 _R("RTL8402", RTL_TD_1, FIRMWARE_8402_1,
275 JUMBO_1K, true),
b3d7b2f2
HW		 276 [RTL_GIGA_MAC_VER_38] =
277 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_1,
278 JUMBO_9K, false),
5598bfe5
HW		 279 [RTL_GIGA_MAC_VER_39] =
280 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_1,
281 JUMBO_1K, true),
c558386b 282 [RTL_GIGA_MAC_VER_40] =
beb330a4 283 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_2,
c558386b
HW		 284 JUMBO_9K, false),
285 [RTL_GIGA_MAC_VER_41] =
286 _R("RTL8168g/8111g", RTL_TD_1, NULL, JUMBO_9K, false),
57538c4a 287 [RTL_GIGA_MAC_VER_42] =
288 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_3,
289 JUMBO_9K, false),
58152cd4 290 [RTL_GIGA_MAC_VER_43] =
291 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_2,
292 JUMBO_1K, true),
45dd95c4 293 [RTL_GIGA_MAC_VER_44] =
294 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_2,
295 JUMBO_9K, false),
6e1d0b89
CHL		 296 [RTL_GIGA_MAC_VER_45] =
297 _R("RTL8168h/8111h", RTL_TD_1, FIRMWARE_8168H_1,
298 JUMBO_9K, false),
299 [RTL_GIGA_MAC_VER_46] =
300 _R("RTL8168h/8111h", RTL_TD_1, FIRMWARE_8168H_2,
301 JUMBO_9K, false),
302 [RTL_GIGA_MAC_VER_47] =
303 _R("RTL8107e", RTL_TD_1, FIRMWARE_8107E_1,
304 JUMBO_1K, false),
305 [RTL_GIGA_MAC_VER_48] =
306 _R("RTL8107e", RTL_TD_1, FIRMWARE_8107E_2,
307 JUMBO_1K, false),
935e2218
CHL		 308 [RTL_GIGA_MAC_VER_49] =
309 _R("RTL8168ep/8111ep", RTL_TD_1, NULL,
310 JUMBO_9K, false),
311 [RTL_GIGA_MAC_VER_50] =
312 _R("RTL8168ep/8111ep", RTL_TD_1, NULL,
313 JUMBO_9K, false),
314 [RTL_GIGA_MAC_VER_51] =
315 _R("RTL8168ep/8111ep", RTL_TD_1, NULL,
316 JUMBO_9K, false),
953a12cc 317};
85bffe6c 318#undef _R
953a12cc 319
bcf0bf90
FR		 320enum cfg_version {
321 RTL_CFG_0 = 0x00,
322 RTL_CFG_1,
323 RTL_CFG_2
324};
325
9baa3c34 326static const struct pci_device_id rtl8169_pci_tbl[] = {
bcf0bf90 327 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 328 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 329 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 330 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90 331 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
2a35cfa5
FR		 332 { PCI_VENDOR_ID_DLINK, 0x4300,
333 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
bcf0bf90 334 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
93a3aa25 335 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
bc1660b5 336 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 337 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
338 { PCI_VENDOR_ID_LINKSYS, 0x1032,
339 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 340 { 0x0001, 0x8168,
341 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 342 {0,},
343};
344
345MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
346
6f0333b8 347static int rx_buf_sz = 16383;
27896c83 348static int use_dac = -1;
b57b7e5a
SH		 349static struct {
350 u32 msg_enable;
351} debug = { -1 };
1da177e4 352
07d3f51f
FR		 353enum rtl_registers {
354 MAC0 = 0, /* Ethernet hardware address. */
773d2021 355 MAC4 = 4,
07d3f51f
FR		 356 MAR0 = 8, /* Multicast filter. */
357 CounterAddrLow = 0x10,
358 CounterAddrHigh = 0x14,
359 TxDescStartAddrLow = 0x20,
360 TxDescStartAddrHigh = 0x24,
361 TxHDescStartAddrLow = 0x28,
362 TxHDescStartAddrHigh = 0x2c,
363 FLASH = 0x30,
364 ERSR = 0x36,
365 ChipCmd = 0x37,
366 TxPoll = 0x38,
367 IntrMask = 0x3c,
368 IntrStatus = 0x3e,
4f6b00e5 369
07d3f51f 370 TxConfig = 0x40,
4f6b00e5
HW		 371#define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
372#define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
2b7b4318 373
4f6b00e5
HW		 374 RxConfig = 0x44,
375#define RX128_INT_EN (1 << 15) /* 8111c and later */
376#define RX_MULTI_EN (1 << 14) /* 8111c only */
377#define RXCFG_FIFO_SHIFT 13
378 /* No threshold before first PCI xfer */
379#define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
beb330a4 380#define RX_EARLY_OFF (1 << 11)
4f6b00e5
HW		 381#define RXCFG_DMA_SHIFT 8
382 /* Unlimited maximum PCI burst. */
383#define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
2b7b4318 384
07d3f51f
FR		 385 RxMissed = 0x4c,
386 Cfg9346 = 0x50,
387 Config0 = 0x51,
388 Config1 = 0x52,
389 Config2 = 0x53,
d387b427
FR		 390#define PME_SIGNAL (1 << 5) /* 8168c and later */
391
07d3f51f
FR		 392 Config3 = 0x54,
393 Config4 = 0x55,
394 Config5 = 0x56,
395 MultiIntr = 0x5c,
396 PHYAR = 0x60,
07d3f51f
FR		 397 PHYstatus = 0x6c,
398 RxMaxSize = 0xda,
399 CPlusCmd = 0xe0,
400 IntrMitigate = 0xe2,
401 RxDescAddrLow = 0xe4,
402 RxDescAddrHigh = 0xe8,
f0298f81 403 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
404
405#define NoEarlyTx 0x3f /* Max value : no early transmit. */
406
407 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
408
409#define TxPacketMax (8064 >> 7)
3090bd9a 410#define EarlySize 0x27
f0298f81 411
07d3f51f
FR		 412 FuncEvent = 0xf0,
413 FuncEventMask = 0xf4,
414 FuncPresetState = 0xf8,
935e2218
CHL		 415 IBCR0 = 0xf8,
416 IBCR2 = 0xf9,
417 IBIMR0 = 0xfa,
418 IBISR0 = 0xfb,
07d3f51f 419 FuncForceEvent = 0xfc,
1da177e4
LT		 420};
421
f162a5d1
FR		 422enum rtl8110_registers {
423 TBICSR = 0x64,
424 TBI_ANAR = 0x68,
425 TBI_LPAR = 0x6a,
426};
427
428enum rtl8168_8101_registers {
429 CSIDR = 0x64,
430 CSIAR = 0x68,
431#define CSIAR_FLAG 0x80000000
432#define CSIAR_WRITE_CMD 0x80000000
433#define CSIAR_BYTE_ENABLE 0x0f
434#define CSIAR_BYTE_ENABLE_SHIFT 12
435#define CSIAR_ADDR_MASK 0x0fff
7e18dca1
HW		 436#define CSIAR_FUNC_CARD 0x00000000
437#define CSIAR_FUNC_SDIO 0x00010000
438#define CSIAR_FUNC_NIC 0x00020000
45dd95c4 439#define CSIAR_FUNC_NIC2 0x00010000
065c27c1 440 PMCH = 0x6f,
f162a5d1
FR		 441 EPHYAR = 0x80,
442#define EPHYAR_FLAG 0x80000000
443#define EPHYAR_WRITE_CMD 0x80000000
444#define EPHYAR_REG_MASK 0x1f
445#define EPHYAR_REG_SHIFT 16
446#define EPHYAR_DATA_MASK 0xffff
5a5e4443 447 DLLPR = 0xd0,
4f6b00e5 448#define PFM_EN (1 << 6)
6e1d0b89 449#define TX_10M_PS_EN (1 << 7)
f162a5d1
FR		 450 DBG_REG = 0xd1,
451#define FIX_NAK_1 (1 << 4)
452#define FIX_NAK_2 (1 << 3)
5a5e4443
HW		 453 TWSI = 0xd2,
454 MCU = 0xd3,
4f6b00e5 455#define NOW_IS_OOB (1 << 7)
c558386b
HW		 456#define TX_EMPTY (1 << 5)
457#define RX_EMPTY (1 << 4)
458#define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
5a5e4443
HW		 459#define EN_NDP (1 << 3)
460#define EN_OOB_RESET (1 << 2)
c558386b 461#define LINK_LIST_RDY (1 << 1)
daf9df6d 462 EFUSEAR = 0xdc,
463#define EFUSEAR_FLAG 0x80000000
464#define EFUSEAR_WRITE_CMD 0x80000000
465#define EFUSEAR_READ_CMD 0x00000000
466#define EFUSEAR_REG_MASK 0x03ff
467#define EFUSEAR_REG_SHIFT 8
468#define EFUSEAR_DATA_MASK 0xff
6e1d0b89
CHL		 469 MISC_1 = 0xf2,
470#define PFM_D3COLD_EN (1 << 6)
f162a5d1
FR		 471};
472
c0e45c1c 473enum rtl8168_registers {
4f6b00e5
HW		 474 LED_FREQ = 0x1a,
475 EEE_LED = 0x1b,
b646d900 476 ERIDR = 0x70,
477 ERIAR = 0x74,
478#define ERIAR_FLAG 0x80000000
479#define ERIAR_WRITE_CMD 0x80000000
480#define ERIAR_READ_CMD 0x00000000
481#define ERIAR_ADDR_BYTE_ALIGN 4
b646d900 482#define ERIAR_TYPE_SHIFT 16
4f6b00e5
HW		 483#define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
484#define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
485#define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
935e2218 486#define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
4f6b00e5
HW		 487#define ERIAR_MASK_SHIFT 12
488#define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
489#define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
6e1d0b89 490#define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
c558386b 491#define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
4f6b00e5 492#define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
c0e45c1c 493 EPHY_RXER_NUM = 0x7c,
494 OCPDR = 0xb0, /* OCP GPHY access */
495#define OCPDR_WRITE_CMD 0x80000000
496#define OCPDR_READ_CMD 0x00000000
497#define OCPDR_REG_MASK 0x7f
498#define OCPDR_GPHY_REG_SHIFT 16
499#define OCPDR_DATA_MASK 0xffff
500 OCPAR = 0xb4,
501#define OCPAR_FLAG 0x80000000
502#define OCPAR_GPHY_WRITE_CMD 0x8000f060
503#define OCPAR_GPHY_READ_CMD 0x0000f060
c558386b 504 GPHY_OCP = 0xb8,
01dc7fec 505 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
506 MISC = 0xf0, /* 8168e only. */
cecb5fd7 507#define TXPLA_RST (1 << 29)
5598bfe5 508#define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
4f6b00e5 509#define PWM_EN (1 << 22)
c558386b 510#define RXDV_GATED_EN (1 << 19)
5598bfe5 511#define EARLY_TALLY_EN (1 << 16)
c0e45c1c 512};
513
07d3f51f 514enum rtl_register_content {
1da177e4 515 /* InterruptStatusBits */
07d3f51f
FR		 516 SYSErr = 0x8000,
517 PCSTimeout = 0x4000,
518 SWInt = 0x0100,
519 TxDescUnavail = 0x0080,
520 RxFIFOOver = 0x0040,
521 LinkChg = 0x0020,
522 RxOverflow = 0x0010,
523 TxErr = 0x0008,
524 TxOK = 0x0004,
525 RxErr = 0x0002,
526 RxOK = 0x0001,
1da177e4
LT		 527
528 /* RxStatusDesc */
e03f33af 529 RxBOVF = (1 << 24),
9dccf611
FR		 530 RxFOVF = (1 << 23),
531 RxRWT = (1 << 22),
532 RxRES = (1 << 21),
533 RxRUNT = (1 << 20),
534 RxCRC = (1 << 19),
1da177e4
LT		 535
536 /* ChipCmdBits */
4f6b00e5 537 StopReq = 0x80,
07d3f51f
FR		 538 CmdReset = 0x10,
539 CmdRxEnb = 0x08,
540 CmdTxEnb = 0x04,
541 RxBufEmpty = 0x01,
1da177e4 542
275391a4
FR		 543 /* TXPoll register p.5 */
544 HPQ = 0x80, /* Poll cmd on the high prio queue */
545 NPQ = 0x40, /* Poll cmd on the low prio queue */
546 FSWInt = 0x01, /* Forced software interrupt */
547
1da177e4 548 /* Cfg9346Bits */
07d3f51f
FR		 549 Cfg9346_Lock = 0x00,
550 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 551
552 /* rx_mode_bits */
07d3f51f
FR		 553 AcceptErr = 0x20,
554 AcceptRunt = 0x10,
555 AcceptBroadcast = 0x08,
556 AcceptMulticast = 0x04,
557 AcceptMyPhys = 0x02,
558 AcceptAllPhys = 0x01,
1687b566 559#define RX_CONFIG_ACCEPT_MASK 0x3f
1da177e4 560
1da177e4
LT		 561 /* TxConfigBits */
562 TxInterFrameGapShift = 24,
563 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
564
5d06a99f 565 /* Config1 register p.24 */
f162a5d1
FR		 566 LEDS1 = (1 << 7),
567 LEDS0 = (1 << 6),
f162a5d1
FR		 568 Speed_down = (1 << 4),
569 MEMMAP = (1 << 3),
570 IOMAP = (1 << 2),
571 VPD = (1 << 1),
5d06a99f
FR		 572 PMEnable = (1 << 0), /* Power Management Enable */
573
6dccd16b 574 /* Config2 register p. 25 */
57538c4a 575 ClkReqEn = (1 << 7), /* Clock Request Enable */
2ca6cf06 576 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
6dccd16b
FR		 577 PCI_Clock_66MHz = 0x01,
578 PCI_Clock_33MHz = 0x00,
579
61a4dcc2
FR		 580 /* Config3 register p.25 */
581 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
582 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
d58d46b5 583 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
b51ecea8 584 Rdy_to_L23 = (1 << 1), /* L23 Enable */
f162a5d1 585 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 586
d58d46b5
FR		 587 /* Config4 register */
588 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
589
5d06a99f 590 /* Config5 register p.27 */
61a4dcc2
FR		 591 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
592 MWF = (1 << 5), /* Accept Multicast wakeup frame */
593 UWF = (1 << 4), /* Accept Unicast wakeup frame */
cecb5fd7 594 Spi_en = (1 << 3),
61a4dcc2 595 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f 596 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
57538c4a 597 ASPM_en = (1 << 0), /* ASPM enable */
5d06a99f 598
1da177e4
LT		 599 /* TBICSR p.28 */
600 TBIReset = 0x80000000,
601 TBILoopback = 0x40000000,
602 TBINwEnable = 0x20000000,
603 TBINwRestart = 0x10000000,
604 TBILinkOk = 0x02000000,
605 TBINwComplete = 0x01000000,
606
607 /* CPlusCmd p.31 */
f162a5d1
FR		 608 EnableBist = (1 << 15), // 8168 8101
609 Mac_dbgo_oe = (1 << 14), // 8168 8101
610 Normal_mode = (1 << 13), // unused
611 Force_half_dup = (1 << 12), // 8168 8101
612 Force_rxflow_en = (1 << 11), // 8168 8101
613 Force_txflow_en = (1 << 10), // 8168 8101
614 Cxpl_dbg_sel = (1 << 9), // 8168 8101
615 ASF = (1 << 8), // 8168 8101
616 PktCntrDisable = (1 << 7), // 8168 8101
617 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 618 RxVlan = (1 << 6),
619 RxChkSum = (1 << 5),
620 PCIDAC = (1 << 4),
621 PCIMulRW = (1 << 3),
0e485150
FR		 622 INTT_0 = 0x0000, // 8168
623 INTT_1 = 0x0001, // 8168
624 INTT_2 = 0x0002, // 8168
625 INTT_3 = 0x0003, // 8168
1da177e4
LT		 626
627 /* rtl8169_PHYstatus */
07d3f51f
FR		 628 TBI_Enable = 0x80,
629 TxFlowCtrl = 0x40,
630 RxFlowCtrl = 0x20,
631 _1000bpsF = 0x10,
632 _100bps = 0x08,
633 _10bps = 0x04,
634 LinkStatus = 0x02,
635 FullDup = 0x01,
1da177e4 636
1da177e4 637 /* _TBICSRBit */
07d3f51f 638 TBILinkOK = 0x02000000,
d4a3a0fc 639
6e85d5ad
CV		 640 /* ResetCounterCommand */
641 CounterReset = 0x1,
642
d4a3a0fc 643 /* DumpCounterCommand */
07d3f51f 644 CounterDump = 0x8,
6e1d0b89
CHL		 645
646 /* magic enable v2 */
647 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */
1da177e4
LT		 648};
649
2b7b4318
FR		 650enum rtl_desc_bit {
651 /* First doubleword. */
1da177e4
LT		 652 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
653 RingEnd = (1 << 30), /* End of descriptor ring */
654 FirstFrag = (1 << 29), /* First segment of a packet */
655 LastFrag = (1 << 28), /* Final segment of a packet */
2b7b4318
FR		 656};
657
658/* Generic case. */
659enum rtl_tx_desc_bit {
660 /* First doubleword. */
661 TD_LSO = (1 << 27), /* Large Send Offload */
662#define TD_MSS_MAX 0x07ffu /* MSS value */
1da177e4 663
2b7b4318
FR		 664 /* Second doubleword. */
665 TxVlanTag = (1 << 17), /* Add VLAN tag */
666};
667
668/* 8169, 8168b and 810x except 8102e. */
669enum rtl_tx_desc_bit_0 {
670 /* First doubleword. */
671#define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
672 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
673 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
674 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
675};
676
677/* 8102e, 8168c and beyond. */
678enum rtl_tx_desc_bit_1 {
bdfa4ed6 679 /* First doubleword. */
680 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */
e974604b 681 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */
bdfa4ed6 682#define GTTCPHO_SHIFT 18
e974604b 683#define GTTCPHO_MAX 0x7fU
bdfa4ed6 684
2b7b4318 685 /* Second doubleword. */
e974604b 686#define TCPHO_SHIFT 18
687#define TCPHO_MAX 0x3ffU
2b7b4318 688#define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
e974604b 689 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */
690 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */
2b7b4318
FR		 691 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
692 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
693};
1da177e4 694
2b7b4318 695enum rtl_rx_desc_bit {
1da177e4
LT		 696 /* Rx private */
697 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
698 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
699
700#define RxProtoUDP (PID1)
701#define RxProtoTCP (PID0)
702#define RxProtoIP (PID1 | PID0)
703#define RxProtoMask RxProtoIP
704
705 IPFail = (1 << 16), /* IP checksum failed */
706 UDPFail = (1 << 15), /* UDP/IP checksum failed */
707 TCPFail = (1 << 14), /* TCP/IP checksum failed */
708 RxVlanTag = (1 << 16), /* VLAN tag available */
709};
710
711#define RsvdMask 0x3fffc000
712
713struct TxDesc {
6cccd6e7
REB		 714 __le32 opts1;
715 __le32 opts2;
716 __le64 addr;
1da177e4
LT		 717};
718
719struct RxDesc {
6cccd6e7
REB		 720 __le32 opts1;
721 __le32 opts2;
722 __le64 addr;
1da177e4
LT		 723};
724
725struct ring_info {
726 struct sk_buff *skb;
727 u32 len;
728 u8 __pad[sizeof(void *) - sizeof(u32)];
729};
730
f23e7fda 731enum features {
ccdffb9a
FR		 732 RTL_FEATURE_WOL = (1 << 0),
733 RTL_FEATURE_MSI = (1 << 1),
734 RTL_FEATURE_GMII = (1 << 2),
f23e7fda
FR		 735};
736
355423d0
IV		 737struct rtl8169_counters {
738 __le64 tx_packets;
739 __le64 rx_packets;
740 __le64 tx_errors;
741 __le32 rx_errors;
742 __le16 rx_missed;
743 __le16 align_errors;
744 __le32 tx_one_collision;
745 __le32 tx_multi_collision;
746 __le64 rx_unicast;
747 __le64 rx_broadcast;
748 __le32 rx_multicast;
749 __le16 tx_aborted;
750 __le16 tx_underun;
751};
752
6e85d5ad
CV		 753struct rtl8169_tc_offsets {
754 bool inited;
755 __le64 tx_errors;
756 __le32 tx_multi_collision;
6e85d5ad
CV		 757 __le16 tx_aborted;
758};
759
da78dbff 760enum rtl_flag {
6c4a70c5 761 RTL_FLAG_TASK_ENABLED,
da78dbff
FR		 762 RTL_FLAG_TASK_SLOW_PENDING,
763 RTL_FLAG_TASK_RESET_PENDING,
764 RTL_FLAG_TASK_PHY_PENDING,
765 RTL_FLAG_MAX
766};
767
8027aa24
JW		 768struct rtl8169_stats {
769 u64 packets;
770 u64 bytes;
771 struct u64_stats_sync syncp;
772};
773
1da177e4
LT		 774struct rtl8169_private {
775 void __iomem *mmio_addr; /* memory map physical address */
cecb5fd7 776 struct pci_dev *pci_dev;
c4028958 777 struct net_device *dev;
bea3348e 778 struct napi_struct napi;
b57b7e5a 779 u32 msg_enable;
2b7b4318
FR		 780 u16 txd_version;
781 u16 mac_version;
1da177e4
LT		 782 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
783 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
1da177e4 784 u32 dirty_tx;
8027aa24
JW		 785 struct rtl8169_stats rx_stats;
786 struct rtl8169_stats tx_stats;
1da177e4
LT		 787 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
788 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
789 dma_addr_t TxPhyAddr;
790 dma_addr_t RxPhyAddr;
6f0333b8 791 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
1da177e4 792 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
1da177e4
LT		 793 struct timer_list timer;
794 u16 cp_cmd;
da78dbff
FR		 795
796 u16 event_slow;
c0e45c1c 797
798 struct mdio_ops {
24192210
FR		 799 void (*write)(struct rtl8169_private *, int, int);
800 int (*read)(struct rtl8169_private *, int);
c0e45c1c 801 } mdio_ops;
802
065c27c1 803 struct pll_power_ops {
804 void (*down)(struct rtl8169_private *);
805 void (*up)(struct rtl8169_private *);
806 } pll_power_ops;
807
d58d46b5
FR		 808 struct jumbo_ops {
809 void (*enable)(struct rtl8169_private *);
810 void (*disable)(struct rtl8169_private *);
811 } jumbo_ops;
812
beb1fe18 813 struct csi_ops {
52989f0e
FR		 814 void (*write)(struct rtl8169_private *, int, int);
815 u32 (*read)(struct rtl8169_private *, int);
beb1fe18
HW		 816 } csi_ops;
817
54405cde 818 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
ccdffb9a 819 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
4da19633 820 void (*phy_reset_enable)(struct rtl8169_private *tp);
07ce4064 821 void (*hw_start)(struct net_device *);
4da19633 822 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
1da177e4 823 unsigned int (*link_ok)(void __iomem *);
8b4ab28d 824 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
5888d3fc 825 bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
4422bcd4
FR		 826
827 struct {
da78dbff
FR		 828 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
829 struct mutex mutex;
4422bcd4
FR		 830 struct work_struct work;
831 } wk;
832
f23e7fda 833 unsigned features;
ccdffb9a
FR		 834
835 struct mii_if_info mii;
42020320
CV		 836 dma_addr_t counters_phys_addr;
837 struct rtl8169_counters *counters;
6e85d5ad 838 struct rtl8169_tc_offsets tc_offset;
e1759441 839 u32 saved_wolopts;
e03f33af 840 u32 opts1_mask;
f1e02ed1 841
b6ffd97f
FR		 842 struct rtl_fw {
843 const struct firmware *fw;
1c361efb
FR		 844
845#define RTL_VER_SIZE 32
846
847 char version[RTL_VER_SIZE];
848
849 struct rtl_fw_phy_action {
850 __le32 *code;
851 size_t size;
852 } phy_action;
b6ffd97f 853 } *rtl_fw;
497888cf 854#define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
c558386b
HW		 855
856 u32 ocp_base;
1da177e4
LT		 857};
858
979b6c13 859MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 860MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 861module_param(use_dac, int, 0);
4300e8c7 862MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 863module_param_named(debug, debug.msg_enable, int, 0);
864MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 865MODULE_LICENSE("GPL");
866MODULE_VERSION(RTL8169_VERSION);
bca03d5f 867MODULE_FIRMWARE(FIRMWARE_8168D_1);
868MODULE_FIRMWARE(FIRMWARE_8168D_2);
01dc7fec 869MODULE_FIRMWARE(FIRMWARE_8168E_1);
870MODULE_FIRMWARE(FIRMWARE_8168E_2);
bbb8af75 871MODULE_FIRMWARE(FIRMWARE_8168E_3);
5a5e4443 872MODULE_FIRMWARE(FIRMWARE_8105E_1);
c2218925
HW		 873MODULE_FIRMWARE(FIRMWARE_8168F_1);
874MODULE_FIRMWARE(FIRMWARE_8168F_2);
7e18dca1 875MODULE_FIRMWARE(FIRMWARE_8402_1);
b3d7b2f2 876MODULE_FIRMWARE(FIRMWARE_8411_1);
45dd95c4 877MODULE_FIRMWARE(FIRMWARE_8411_2);
5598bfe5 878MODULE_FIRMWARE(FIRMWARE_8106E_1);
58152cd4 879MODULE_FIRMWARE(FIRMWARE_8106E_2);
beb330a4 880MODULE_FIRMWARE(FIRMWARE_8168G_2);
57538c4a 881MODULE_FIRMWARE(FIRMWARE_8168G_3);
6e1d0b89
CHL		 882MODULE_FIRMWARE(FIRMWARE_8168H_1);
883MODULE_FIRMWARE(FIRMWARE_8168H_2);
a3bf5c42
FR		 884MODULE_FIRMWARE(FIRMWARE_8107E_1);
885MODULE_FIRMWARE(FIRMWARE_8107E_2);
1da177e4 886
da78dbff
FR		 887static void rtl_lock_work(struct rtl8169_private *tp)
888{
889 mutex_lock(&tp->wk.mutex);
890}
891
892static void rtl_unlock_work(struct rtl8169_private *tp)
893{
894 mutex_unlock(&tp->wk.mutex);
895}
896
d58d46b5
FR		 897static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
898{
7d7903b2
JL		 899 pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
900 PCI_EXP_DEVCTL_READRQ, force);
d58d46b5
FR		 901}
902
ffc46952
FR		 903struct rtl_cond {
904 bool (*check)(struct rtl8169_private *);
905 const char *msg;
906};
907
908static void rtl_udelay(unsigned int d)
909{
910 udelay(d);
911}
912
913static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
914 void (*delay)(unsigned int), unsigned int d, int n,
915 bool high)
916{
917 int i;
918
919 for (i = 0; i < n; i++) {
920 delay(d);
921 if (c->check(tp) == high)
922 return true;
923 }
82e316ef
FR		 924 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
925 c->msg, !high, n, d);
ffc46952
FR		 926 return false;
927}
928
929static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
930 const struct rtl_cond *c,
931 unsigned int d, int n)
932{
933 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
934}
935
936static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
937 const struct rtl_cond *c,
938 unsigned int d, int n)
939{
940 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
941}
942
943static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
944 const struct rtl_cond *c,
945 unsigned int d, int n)
946{
947 return rtl_loop_wait(tp, c, msleep, d, n, true);
948}
949
950static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
951 const struct rtl_cond *c,
952 unsigned int d, int n)
953{
954 return rtl_loop_wait(tp, c, msleep, d, n, false);
955}
956
957#define DECLARE_RTL_COND(name) \
958static bool name ## _check(struct rtl8169_private *); \
959 \
960static const struct rtl_cond name = { \
961 .check = name ## _check, \
962 .msg = #name \
963}; \
964 \
965static bool name ## _check(struct rtl8169_private *tp)
966
c558386b
HW		 967static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
968{
969 if (reg & 0xffff0001) {
970 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
971 return true;
972 }
973 return false;
974}
975
976DECLARE_RTL_COND(rtl_ocp_gphy_cond)
977{
978 void __iomem *ioaddr = tp->mmio_addr;
979
980 return RTL_R32(GPHY_OCP) & OCPAR_FLAG;
981}
982
983static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
984{
985 void __iomem *ioaddr = tp->mmio_addr;
986
987 if (rtl_ocp_reg_failure(tp, reg))
988 return;
989
990 RTL_W32(GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
991
992 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
993}
994
995static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
996{
997 void __iomem *ioaddr = tp->mmio_addr;
998
999 if (rtl_ocp_reg_failure(tp, reg))
1000 return 0;
1001
1002 RTL_W32(GPHY_OCP, reg << 15);
1003
1004 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
1005 (RTL_R32(GPHY_OCP) & 0xffff) : ~0;
1006}
1007
c558386b
HW		 1008static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1009{
1010 void __iomem *ioaddr = tp->mmio_addr;
1011
1012 if (rtl_ocp_reg_failure(tp, reg))
1013 return;
1014
1015 RTL_W32(OCPDR, OCPAR_FLAG | (reg << 15) | data);
c558386b
HW		 1016}
1017
1018static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1019{
1020 void __iomem *ioaddr = tp->mmio_addr;
1021
1022 if (rtl_ocp_reg_failure(tp, reg))
1023 return 0;
1024
1025 RTL_W32(OCPDR, reg << 15);
1026
3a83ad12 1027 return RTL_R32(OCPDR);
c558386b
HW		 1028}
1029
1030#define OCP_STD_PHY_BASE 0xa400
1031
1032static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
1033{
1034 if (reg == 0x1f) {
1035 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
1036 return;
1037 }
1038
1039 if (tp->ocp_base != OCP_STD_PHY_BASE)
1040 reg -= 0x10;
1041
1042 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
1043}
1044
1045static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1046{
1047 if (tp->ocp_base != OCP_STD_PHY_BASE)
1048 reg -= 0x10;
1049
1050 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
1051}
1052
eee3786f 1053static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
1054{
1055 if (reg == 0x1f) {
1056 tp->ocp_base = value << 4;
1057 return;
1058 }
1059
1060 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
1061}
1062
1063static int mac_mcu_read(struct rtl8169_private *tp, int reg)
1064{
1065 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
1066}
1067
ffc46952
FR		 1068DECLARE_RTL_COND(rtl_phyar_cond)
1069{
1070 void __iomem *ioaddr = tp->mmio_addr;
1071
1072 return RTL_R32(PHYAR) & 0x80000000;
1073}
1074
24192210 1075static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1da177e4 1076{
24192210 1077 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 1078
24192210 1079 RTL_W32(PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1da177e4 1080
ffc46952 1081 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
024a07ba 1082 /*
81a95f04
TT		 1083 * According to hardware specs a 20us delay is required after write
1084 * complete indication, but before sending next command.
024a07ba 1085 */
81a95f04 1086 udelay(20);
1da177e4
LT		 1087}
1088
24192210 1089static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1da177e4 1090{
24192210 1091 void __iomem *ioaddr = tp->mmio_addr;
ffc46952 1092 int value;
1da177e4 1093
24192210 1094 RTL_W32(PHYAR, 0x0 | (reg & 0x1f) << 16);
1da177e4 1095
ffc46952
FR		 1096 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1097 RTL_R32(PHYAR) & 0xffff : ~0;
1098
81a95f04
TT		 1099 /*
1100 * According to hardware specs a 20us delay is required after read
1101 * complete indication, but before sending next command.
1102 */
1103 udelay(20);
1104
1da177e4
LT		 1105 return value;
1106}
1107
935e2218
CHL		 1108DECLARE_RTL_COND(rtl_ocpar_cond)
1109{
1110 void __iomem *ioaddr = tp->mmio_addr;
1111
1112 return RTL_R32(OCPAR) & OCPAR_FLAG;
1113}
1114
24192210 1115static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
c0e45c1c 1116{
24192210 1117 void __iomem *ioaddr = tp->mmio_addr;
c0e45c1c 1118
24192210 1119 RTL_W32(OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
c0e45c1c 1120 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
1121 RTL_W32(EPHY_RXER_NUM, 0);
1122
ffc46952 1123 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
c0e45c1c 1124}
1125
24192210 1126static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
c0e45c1c 1127{
24192210
FR		 1128 r8168dp_1_mdio_access(tp, reg,
1129 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
c0e45c1c 1130}
1131
24192210 1132static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
c0e45c1c 1133{
24192210 1134 void __iomem *ioaddr = tp->mmio_addr;
c0e45c1c 1135
24192210 1136 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
c0e45c1c 1137
1138 mdelay(1);
1139 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
1140 RTL_W32(EPHY_RXER_NUM, 0);
1141
ffc46952
FR		 1142 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1143 RTL_R32(OCPDR) & OCPDR_DATA_MASK : ~0;
c0e45c1c 1144}
1145
e6de30d6 1146#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1147
1148static void r8168dp_2_mdio_start(void __iomem *ioaddr)
1149{
1150 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1151}
1152
1153static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
1154{
1155 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1156}
1157
24192210 1158static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
e6de30d6 1159{
24192210
FR		 1160 void __iomem *ioaddr = tp->mmio_addr;
1161
e6de30d6 1162 r8168dp_2_mdio_start(ioaddr);
1163
24192210 1164 r8169_mdio_write(tp, reg, value);
e6de30d6 1165
1166 r8168dp_2_mdio_stop(ioaddr);
1167}
1168
24192210 1169static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
e6de30d6 1170{
24192210 1171 void __iomem *ioaddr = tp->mmio_addr;
e6de30d6 1172 int value;
1173
1174 r8168dp_2_mdio_start(ioaddr);
1175
24192210 1176 value = r8169_mdio_read(tp, reg);
e6de30d6 1177
1178 r8168dp_2_mdio_stop(ioaddr);
1179
1180 return value;
1181}
1182
4da19633 1183static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
dacf8154 1184{
24192210 1185 tp->mdio_ops.write(tp, location, val);
dacf8154
FR		 1186}
1187
4da19633 1188static int rtl_readphy(struct rtl8169_private *tp, int location)
1189{
24192210 1190 return tp->mdio_ops.read(tp, location);
4da19633 1191}
1192
1193static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1194{
1195 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1196}
1197
76564428 1198static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
daf9df6d 1199{
1200 int val;
1201
4da19633 1202 val = rtl_readphy(tp, reg_addr);
76564428 1203 rtl_writephy(tp, reg_addr, (val & ~m) | p);
daf9df6d 1204}
1205
ccdffb9a
FR		 1206static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1207 int val)
1208{
1209 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1210
4da19633 1211 rtl_writephy(tp, location, val);
ccdffb9a
FR		 1212}
1213
1214static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1215{
1216 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1217
4da19633 1218 return rtl_readphy(tp, location);
ccdffb9a
FR		 1219}
1220
ffc46952
FR		 1221DECLARE_RTL_COND(rtl_ephyar_cond)
1222{
1223 void __iomem *ioaddr = tp->mmio_addr;
1224
1225 return RTL_R32(EPHYAR) & EPHYAR_FLAG;
1226}
1227
fdf6fc06 1228static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
dacf8154 1229{
fdf6fc06 1230 void __iomem *ioaddr = tp->mmio_addr;
dacf8154
FR		 1231
1232 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1233 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1234
ffc46952
FR		 1235 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1236
1237 udelay(10);
dacf8154
FR		 1238}
1239
fdf6fc06 1240static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
dacf8154 1241{
fdf6fc06 1242 void __iomem *ioaddr = tp->mmio_addr;
dacf8154
FR		 1243
1244 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1245
ffc46952
FR		 1246 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1247 RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0;
dacf8154
FR		 1248}
1249
935e2218
CHL		 1250DECLARE_RTL_COND(rtl_eriar_cond)
1251{
1252 void __iomem *ioaddr = tp->mmio_addr;
1253
1254 return RTL_R32(ERIAR) & ERIAR_FLAG;
1255}
1256
fdf6fc06
FR		 1257static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1258 u32 val, int type)
133ac40a 1259{
fdf6fc06 1260 void __iomem *ioaddr = tp->mmio_addr;
133ac40a
HW		 1261
1262 BUG_ON((addr & 3) || (mask == 0));
1263 RTL_W32(ERIDR, val);
1264 RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1265
ffc46952 1266 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
133ac40a
HW		 1267}
1268
fdf6fc06 1269static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
133ac40a 1270{
fdf6fc06 1271 void __iomem *ioaddr = tp->mmio_addr;
133ac40a
HW		 1272
1273 RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1274
ffc46952
FR		 1275 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1276 RTL_R32(ERIDR) : ~0;
133ac40a
HW		 1277}
1278
706123d0 1279static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
fdf6fc06 1280 u32 m, int type)
133ac40a
HW		 1281{
1282 u32 val;
1283
fdf6fc06
FR		 1284 val = rtl_eri_read(tp, addr, type);
1285 rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
133ac40a
HW		 1286}
1287
935e2218
CHL		 1288static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1289{
1290 void __iomem *ioaddr = tp->mmio_addr;
1291
1292 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1293 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1294 RTL_R32(OCPDR) : ~0;
1295}
1296
1297static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1298{
1299 return rtl_eri_read(tp, reg, ERIAR_OOB);
1300}
1301
1302static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1303{
1304 switch (tp->mac_version) {
1305 case RTL_GIGA_MAC_VER_27:
1306 case RTL_GIGA_MAC_VER_28:
1307 case RTL_GIGA_MAC_VER_31:
1308 return r8168dp_ocp_read(tp, mask, reg);
1309 case RTL_GIGA_MAC_VER_49:
1310 case RTL_GIGA_MAC_VER_50:
1311 case RTL_GIGA_MAC_VER_51:
1312 return r8168ep_ocp_read(tp, mask, reg);
1313 default:
1314 BUG();
1315 return ~0;
1316 }
1317}
1318
1319static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1320 u32 data)
1321{
1322 void __iomem *ioaddr = tp->mmio_addr;
1323
1324 RTL_W32(OCPDR, data);
1325 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1326 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1327}
1328
1329static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1330 u32 data)
1331{
1332 rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1333 data, ERIAR_OOB);
1334}
1335
1336static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
1337{
1338 switch (tp->mac_version) {
1339 case RTL_GIGA_MAC_VER_27:
1340 case RTL_GIGA_MAC_VER_28:
1341 case RTL_GIGA_MAC_VER_31:
1342 r8168dp_ocp_write(tp, mask, reg, data);
1343 break;
1344 case RTL_GIGA_MAC_VER_49:
1345 case RTL_GIGA_MAC_VER_50:
1346 case RTL_GIGA_MAC_VER_51:
1347 r8168ep_ocp_write(tp, mask, reg, data);
1348 break;
1349 default:
1350 BUG();
1351 break;
1352 }
1353}
1354
2a9b4d96
CHL		 1355static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
1356{
1357 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC);
1358
1359 ocp_write(tp, 0x1, 0x30, 0x00000001);
1360}
1361
1362#define OOB_CMD_RESET 0x00
1363#define OOB_CMD_DRIVER_START 0x05
1364#define OOB_CMD_DRIVER_STOP 0x06
1365
1366static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1367{
1368 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1369}
1370
1371DECLARE_RTL_COND(rtl_ocp_read_cond)
1372{
1373 u16 reg;
1374
1375 reg = rtl8168_get_ocp_reg(tp);
1376
1377 return ocp_read(tp, 0x0f, reg) & 0x00000800;
1378}
1379
935e2218 1380DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
2a9b4d96 1381{
935e2218
CHL		 1382 return ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1383}
1384
1385DECLARE_RTL_COND(rtl_ocp_tx_cond)
1386{
1387 void __iomem *ioaddr = tp->mmio_addr;
1388
1389 return RTL_R8(IBISR0) & 0x02;
1390}
2a9b4d96 1391
003609da
CHL		 1392static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1393{
1394 void __iomem *ioaddr = tp->mmio_addr;
1395
1396 RTL_W8(IBCR2, RTL_R8(IBCR2) & ~0x01);
1397 rtl_msleep_loop_wait_low(tp, &rtl_ocp_tx_cond, 50, 2000);
1398 RTL_W8(IBISR0, RTL_R8(IBISR0) | 0x20);
1399 RTL_W8(IBCR0, RTL_R8(IBCR0) & ~0x01);
1400}
1401
935e2218
CHL		 1402static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1403{
1404 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
2a9b4d96
CHL		 1405 rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
1406}
1407
935e2218 1408static void rtl8168ep_driver_start(struct rtl8169_private *tp)
2a9b4d96 1409{
935e2218
CHL		 1410 ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1411 ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1412 rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1413}
1414
1415static void rtl8168_driver_start(struct rtl8169_private *tp)
1416{
1417 switch (tp->mac_version) {
1418 case RTL_GIGA_MAC_VER_27:
1419 case RTL_GIGA_MAC_VER_28:
1420 case RTL_GIGA_MAC_VER_31:
1421 rtl8168dp_driver_start(tp);
1422 break;
1423 case RTL_GIGA_MAC_VER_49:
1424 case RTL_GIGA_MAC_VER_50:
1425 case RTL_GIGA_MAC_VER_51:
1426 rtl8168ep_driver_start(tp);
1427 break;
1428 default:
1429 BUG();
1430 break;
1431 }
1432}
2a9b4d96 1433
935e2218
CHL		 1434static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1435{
1436 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
2a9b4d96
CHL		 1437 rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
1438}
1439
935e2218
CHL		 1440static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1441{
003609da 1442 rtl8168ep_stop_cmac(tp);
935e2218
CHL		 1443 ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1444 ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1445 rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1446}
1447
1448static void rtl8168_driver_stop(struct rtl8169_private *tp)
1449{
1450 switch (tp->mac_version) {
1451 case RTL_GIGA_MAC_VER_27:
1452 case RTL_GIGA_MAC_VER_28:
1453 case RTL_GIGA_MAC_VER_31:
1454 rtl8168dp_driver_stop(tp);
1455 break;
1456 case RTL_GIGA_MAC_VER_49:
1457 case RTL_GIGA_MAC_VER_50:
1458 case RTL_GIGA_MAC_VER_51:
1459 rtl8168ep_driver_stop(tp);
1460 break;
1461 default:
1462 BUG();
1463 break;
1464 }
1465}
1466
1467static int r8168dp_check_dash(struct rtl8169_private *tp)
2a9b4d96
CHL		 1468{
1469 u16 reg = rtl8168_get_ocp_reg(tp);
1470
1471 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
1472}
1473
935e2218
CHL		 1474static int r8168ep_check_dash(struct rtl8169_private *tp)
1475{
1476 return (ocp_read(tp, 0x0f, 0x128) & 0x00000001) ? 1 : 0;
1477}
1478
1479static int r8168_check_dash(struct rtl8169_private *tp)
1480{
1481 switch (tp->mac_version) {
1482 case RTL_GIGA_MAC_VER_27:
1483 case RTL_GIGA_MAC_VER_28:
1484 case RTL_GIGA_MAC_VER_31:
1485 return r8168dp_check_dash(tp);
1486 case RTL_GIGA_MAC_VER_49:
1487 case RTL_GIGA_MAC_VER_50:
1488 case RTL_GIGA_MAC_VER_51:
1489 return r8168ep_check_dash(tp);
1490 default:
1491 return 0;
1492 }
1493}
1494
c28aa385 1495struct exgmac_reg {
1496 u16 addr;
1497 u16 mask;
1498 u32 val;
1499};
1500
fdf6fc06 1501static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
c28aa385 1502 const struct exgmac_reg *r, int len)
1503{
1504 while (len-- > 0) {
fdf6fc06 1505 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
c28aa385 1506 r++;
1507 }
1508}
1509
ffc46952
FR		 1510DECLARE_RTL_COND(rtl_efusear_cond)
1511{
1512 void __iomem *ioaddr = tp->mmio_addr;
1513
1514 return RTL_R32(EFUSEAR) & EFUSEAR_FLAG;
1515}
1516
fdf6fc06 1517static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
daf9df6d 1518{
fdf6fc06 1519 void __iomem *ioaddr = tp->mmio_addr;
daf9df6d 1520
1521 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1522
ffc46952
FR		 1523 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1524 RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
daf9df6d 1525}
1526
9085cdfa
FR		 1527static u16 rtl_get_events(struct rtl8169_private *tp)
1528{
1529 void __iomem *ioaddr = tp->mmio_addr;
1530
1531 return RTL_R16(IntrStatus);
1532}
1533
1534static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1535{
1536 void __iomem *ioaddr = tp->mmio_addr;
1537
1538 RTL_W16(IntrStatus, bits);
1539 mmiowb();
1540}
1541
1542static void rtl_irq_disable(struct rtl8169_private *tp)
1543{
1544 void __iomem *ioaddr = tp->mmio_addr;
1545
1546 RTL_W16(IntrMask, 0);
1547 mmiowb();
1548}
1549
3e990ff5
FR		 1550static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1551{
1552 void __iomem *ioaddr = tp->mmio_addr;
1553
1554 RTL_W16(IntrMask, bits);
1555}
1556
da78dbff
FR		 1557#define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1558#define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1559#define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1560
1561static void rtl_irq_enable_all(struct rtl8169_private *tp)
1562{
1563 rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1564}
1565
811fd301 1566static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1da177e4 1567{
811fd301 1568 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 1569
9085cdfa 1570 rtl_irq_disable(tp);
da78dbff 1571 rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
811fd301 1572 RTL_R8(ChipCmd);
1da177e4
LT		 1573}
1574
4da19633 1575static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1da177e4 1576{
4da19633 1577 void __iomem *ioaddr = tp->mmio_addr;
1578
1da177e4
LT		 1579 return RTL_R32(TBICSR) & TBIReset;
1580}
1581
4da19633 1582static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1da177e4 1583{
4da19633 1584 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 1585}
1586
1587static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1588{
1589 return RTL_R32(TBICSR) & TBILinkOk;
1590}
1591
1592static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1593{
1594 return RTL_R8(PHYstatus) & LinkStatus;
1595}
1596
4da19633 1597static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1da177e4 1598{
4da19633 1599 void __iomem *ioaddr = tp->mmio_addr;
1600
1da177e4
LT		 1601 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1602}
1603
4da19633 1604static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1da177e4
LT		 1605{
1606 unsigned int val;
1607
4da19633 1608 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1609 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1da177e4
LT		 1610}
1611
70090424
HW		 1612static void rtl_link_chg_patch(struct rtl8169_private *tp)
1613{
1614 void __iomem *ioaddr = tp->mmio_addr;
1615 struct net_device *dev = tp->dev;
1616
1617 if (!netif_running(dev))
1618 return;
1619
b3d7b2f2
HW		 1620 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1621 tp->mac_version == RTL_GIGA_MAC_VER_38) {
70090424 1622 if (RTL_R8(PHYstatus) & _1000bpsF) {
fdf6fc06
FR		 1623 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1624 ERIAR_EXGMAC);
1625 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1626 ERIAR_EXGMAC);
70090424 1627 } else if (RTL_R8(PHYstatus) & _100bps) {
fdf6fc06
FR		 1628 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1629 ERIAR_EXGMAC);
1630 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1631 ERIAR_EXGMAC);
70090424 1632 } else {
fdf6fc06
FR		 1633 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1634 ERIAR_EXGMAC);
1635 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1636 ERIAR_EXGMAC);
70090424
HW		 1637 }
1638 /* Reset packet filter */
706123d0 1639 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
70090424 1640 ERIAR_EXGMAC);
706123d0 1641 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
70090424 1642 ERIAR_EXGMAC);
c2218925
HW		 1643 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1644 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1645 if (RTL_R8(PHYstatus) & _1000bpsF) {
fdf6fc06
FR		 1646 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1647 ERIAR_EXGMAC);
1648 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1649 ERIAR_EXGMAC);
c2218925 1650 } else {
fdf6fc06
FR		 1651 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1652 ERIAR_EXGMAC);
1653 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1654 ERIAR_EXGMAC);
c2218925 1655 }
7e18dca1
HW		 1656 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1657 if (RTL_R8(PHYstatus) & _10bps) {
fdf6fc06
FR		 1658 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1659 ERIAR_EXGMAC);
1660 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1661 ERIAR_EXGMAC);
7e18dca1 1662 } else {
fdf6fc06
FR		 1663 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1664 ERIAR_EXGMAC);
7e18dca1 1665 }
70090424
HW		 1666 }
1667}
1668
e4fbce74 1669static void __rtl8169_check_link_status(struct net_device *dev,
cecb5fd7
FR		 1670 struct rtl8169_private *tp,
1671 void __iomem *ioaddr, bool pm)
1da177e4 1672{
1da177e4 1673 if (tp->link_ok(ioaddr)) {
70090424 1674 rtl_link_chg_patch(tp);
e1759441 1675 /* This is to cancel a scheduled suspend if there's one. */
e4fbce74
RW		 1676 if (pm)
1677 pm_request_resume(&tp->pci_dev->dev);
1da177e4 1678 netif_carrier_on(dev);
1519e57f
FR		 1679 if (net_ratelimit())
1680 netif_info(tp, ifup, dev, "link up\n");
b57b7e5a 1681 } else {
1da177e4 1682 netif_carrier_off(dev);
bf82c189 1683 netif_info(tp, ifdown, dev, "link down\n");
e4fbce74 1684 if (pm)
10953db8 1685 pm_schedule_suspend(&tp->pci_dev->dev, 5000);
b57b7e5a 1686 }
1da177e4
LT		 1687}
1688
e4fbce74
RW		 1689static void rtl8169_check_link_status(struct net_device *dev,
1690 struct rtl8169_private *tp,
1691 void __iomem *ioaddr)
1692{
1693 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1694}
1695
e1759441
RW		 1696#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1697
1698static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
61a4dcc2 1699{
61a4dcc2
FR		 1700 void __iomem *ioaddr = tp->mmio_addr;
1701 u8 options;
e1759441 1702 u32 wolopts = 0;
61a4dcc2
FR		 1703
1704 options = RTL_R8(Config1);
1705 if (!(options & PMEnable))
e1759441 1706 return 0;
61a4dcc2
FR		 1707
1708 options = RTL_R8(Config3);
1709 if (options & LinkUp)
e1759441 1710 wolopts |= WAKE_PHY;
6e1d0b89 1711 switch (tp->mac_version) {
ac85bcdb
CHL		 1712 case RTL_GIGA_MAC_VER_34:
1713 case RTL_GIGA_MAC_VER_35:
1714 case RTL_GIGA_MAC_VER_36:
1715 case RTL_GIGA_MAC_VER_37:
1716 case RTL_GIGA_MAC_VER_38:
1717 case RTL_GIGA_MAC_VER_40:
1718 case RTL_GIGA_MAC_VER_41:
1719 case RTL_GIGA_MAC_VER_42:
1720 case RTL_GIGA_MAC_VER_43:
1721 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 1722 case RTL_GIGA_MAC_VER_45:
1723 case RTL_GIGA_MAC_VER_46:
ac85bcdb
CHL		 1724 case RTL_GIGA_MAC_VER_47:
1725 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 1726 case RTL_GIGA_MAC_VER_49:
1727 case RTL_GIGA_MAC_VER_50:
1728 case RTL_GIGA_MAC_VER_51:
6e1d0b89
CHL		 1729 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
1730 wolopts |= WAKE_MAGIC;
1731 break;
1732 default:
1733 if (options & MagicPacket)
1734 wolopts |= WAKE_MAGIC;
1735 break;
1736 }
61a4dcc2
FR		 1737
1738 options = RTL_R8(Config5);
1739 if (options & UWF)
e1759441 1740 wolopts |= WAKE_UCAST;
61a4dcc2 1741 if (options & BWF)
e1759441 1742 wolopts |= WAKE_BCAST;
61a4dcc2 1743 if (options & MWF)
e1759441 1744 wolopts |= WAKE_MCAST;
61a4dcc2 1745
e1759441 1746 return wolopts;
61a4dcc2
FR		 1747}
1748
e1759441 1749static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
61a4dcc2
FR		 1750{
1751 struct rtl8169_private *tp = netdev_priv(dev);
5fa80a32
CHL		 1752 struct device *d = &tp->pci_dev->dev;
1753
1754 pm_runtime_get_noresume(d);
e1759441 1755
da78dbff 1756 rtl_lock_work(tp);
e1759441
RW		 1757
1758 wol->supported = WAKE_ANY;
5fa80a32
CHL		 1759 if (pm_runtime_active(d))
1760 wol->wolopts = __rtl8169_get_wol(tp);
1761 else
1762 wol->wolopts = tp->saved_wolopts;
e1759441 1763
da78dbff 1764 rtl_unlock_work(tp);
5fa80a32
CHL		 1765
1766 pm_runtime_put_noidle(d);
e1759441
RW		 1767}
1768
1769static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1770{
61a4dcc2 1771 void __iomem *ioaddr = tp->mmio_addr;
6e1d0b89 1772 unsigned int i, tmp;
350f7596 1773 static const struct {
61a4dcc2
FR		 1774 u32 opt;
1775 u16 reg;
1776 u8 mask;
1777 } cfg[] = {
61a4dcc2 1778 { WAKE_PHY, Config3, LinkUp },
61a4dcc2
FR		 1779 { WAKE_UCAST, Config5, UWF },
1780 { WAKE_BCAST, Config5, BWF },
1781 { WAKE_MCAST, Config5, MWF },
6e1d0b89
CHL		 1782 { WAKE_ANY, Config5, LanWake },
1783 { WAKE_MAGIC, Config3, MagicPacket }
61a4dcc2 1784 };
851e6022 1785 u8 options;
61a4dcc2 1786
61a4dcc2
FR		 1787 RTL_W8(Cfg9346, Cfg9346_Unlock);
1788
6e1d0b89 1789 switch (tp->mac_version) {
ac85bcdb
CHL		 1790 case RTL_GIGA_MAC_VER_34:
1791 case RTL_GIGA_MAC_VER_35:
1792 case RTL_GIGA_MAC_VER_36:
1793 case RTL_GIGA_MAC_VER_37:
1794 case RTL_GIGA_MAC_VER_38:
1795 case RTL_GIGA_MAC_VER_40:
1796 case RTL_GIGA_MAC_VER_41:
1797 case RTL_GIGA_MAC_VER_42:
1798 case RTL_GIGA_MAC_VER_43:
1799 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 1800 case RTL_GIGA_MAC_VER_45:
1801 case RTL_GIGA_MAC_VER_46:
ac85bcdb
CHL		 1802 case RTL_GIGA_MAC_VER_47:
1803 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 1804 case RTL_GIGA_MAC_VER_49:
1805 case RTL_GIGA_MAC_VER_50:
1806 case RTL_GIGA_MAC_VER_51:
6e1d0b89
CHL		 1807 tmp = ARRAY_SIZE(cfg) - 1;
1808 if (wolopts & WAKE_MAGIC)
706123d0 1809 rtl_w0w1_eri(tp,
6e1d0b89
CHL		 1810 0x0dc,
1811 ERIAR_MASK_0100,
1812 MagicPacket_v2,
1813 0x0000,
1814 ERIAR_EXGMAC);
1815 else
706123d0 1816 rtl_w0w1_eri(tp,
6e1d0b89
CHL		 1817 0x0dc,
1818 ERIAR_MASK_0100,
1819 0x0000,
1820 MagicPacket_v2,
1821 ERIAR_EXGMAC);
1822 break;
1823 default:
1824 tmp = ARRAY_SIZE(cfg);
1825 break;
1826 }
1827
1828 for (i = 0; i < tmp; i++) {
851e6022 1829 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
e1759441 1830 if (wolopts & cfg[i].opt)
61a4dcc2
FR		 1831 options |= cfg[i].mask;
1832 RTL_W8(cfg[i].reg, options);
1833 }
1834
851e6022
FR		 1835 switch (tp->mac_version) {
1836 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1837 options = RTL_R8(Config1) & ~PMEnable;
1838 if (wolopts)
1839 options |= PMEnable;
1840 RTL_W8(Config1, options);
1841 break;
1842 default:
d387b427
FR		 1843 options = RTL_R8(Config2) & ~PME_SIGNAL;
1844 if (wolopts)
1845 options |= PME_SIGNAL;
1846 RTL_W8(Config2, options);
851e6022
FR		 1847 break;
1848 }
1849
61a4dcc2 1850 RTL_W8(Cfg9346, Cfg9346_Lock);
e1759441
RW		 1851}
1852
1853static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1854{
1855 struct rtl8169_private *tp = netdev_priv(dev);
5fa80a32
CHL		 1856 struct device *d = &tp->pci_dev->dev;
1857
1858 pm_runtime_get_noresume(d);
e1759441 1859
da78dbff 1860 rtl_lock_work(tp);
61a4dcc2 1861
f23e7fda
FR		 1862 if (wol->wolopts)
1863 tp->features |= RTL_FEATURE_WOL;
1864 else
1865 tp->features &= ~RTL_FEATURE_WOL;
5fa80a32
CHL		 1866 if (pm_runtime_active(d))
1867 __rtl8169_set_wol(tp, wol->wolopts);
1868 else
1869 tp->saved_wolopts = wol->wolopts;
da78dbff
FR		 1870
1871 rtl_unlock_work(tp);
61a4dcc2 1872
ea80907f 1873 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1874
5fa80a32
CHL		 1875 pm_runtime_put_noidle(d);
1876
61a4dcc2
FR		 1877 return 0;
1878}
1879
31bd204f
FR		 1880static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1881{
85bffe6c 1882 return rtl_chip_infos[tp->mac_version].fw_name;
31bd204f
FR		 1883}
1884
1da177e4
LT		 1885static void rtl8169_get_drvinfo(struct net_device *dev,
1886 struct ethtool_drvinfo *info)
1887{
1888 struct rtl8169_private *tp = netdev_priv(dev);
b6ffd97f 1889 struct rtl_fw *rtl_fw = tp->rtl_fw;
1da177e4 1890
68aad78c
RJ		 1891 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1892 strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1893 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1c361efb 1894 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
8ac72d16
RJ		 1895 if (!IS_ERR_OR_NULL(rtl_fw))
1896 strlcpy(info->fw_version, rtl_fw->version,
1897 sizeof(info->fw_version));
1da177e4
LT		 1898}
1899
1900static int rtl8169_get_regs_len(struct net_device *dev)
1901{
1902 return R8169_REGS_SIZE;
1903}
1904
1905static int rtl8169_set_speed_tbi(struct net_device *dev,
54405cde 1906 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1da177e4
LT		 1907{
1908 struct rtl8169_private *tp = netdev_priv(dev);
1909 void __iomem *ioaddr = tp->mmio_addr;
1910 int ret = 0;
1911 u32 reg;
1912
1913 reg = RTL_R32(TBICSR);
1914 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1915 (duplex == DUPLEX_FULL)) {
1916 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1917 } else if (autoneg == AUTONEG_ENABLE)
1918 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1919 else {
bf82c189
JP		 1920 netif_warn(tp, link, dev,
1921 "incorrect speed setting refused in TBI mode\n");
1da177e4
LT		 1922 ret = -EOPNOTSUPP;
1923 }
1924
1925 return ret;
1926}
1927
1928static int rtl8169_set_speed_xmii(struct net_device *dev,
54405cde 1929 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1da177e4
LT		 1930{
1931 struct rtl8169_private *tp = netdev_priv(dev);
3577aa1b 1932 int giga_ctrl, bmcr;
54405cde 1933 int rc = -EINVAL;
1da177e4 1934
716b50a3 1935 rtl_writephy(tp, 0x1f, 0x0000);
1da177e4
LT		 1936
1937 if (autoneg == AUTONEG_ENABLE) {
3577aa1b 1938 int auto_nego;
1939
4da19633 1940 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
54405cde
ON		 1941 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1942 ADVERTISE_100HALF | ADVERTISE_100FULL);
1943
1944 if (adv & ADVERTISED_10baseT_Half)
1945 auto_nego |= ADVERTISE_10HALF;
1946 if (adv & ADVERTISED_10baseT_Full)
1947 auto_nego |= ADVERTISE_10FULL;
1948 if (adv & ADVERTISED_100baseT_Half)
1949 auto_nego |= ADVERTISE_100HALF;
1950 if (adv & ADVERTISED_100baseT_Full)
1951 auto_nego |= ADVERTISE_100FULL;
1952
3577aa1b 1953 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1da177e4 1954
4da19633 1955 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
3577aa1b 1956 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
bcf0bf90 1957
3577aa1b 1958 /* The 8100e/8101e/8102e do Fast Ethernet only. */
826e6cbd 1959 if (tp->mii.supports_gmii) {
54405cde
ON		 1960 if (adv & ADVERTISED_1000baseT_Half)
1961 giga_ctrl |= ADVERTISE_1000HALF;
1962 if (adv & ADVERTISED_1000baseT_Full)
1963 giga_ctrl |= ADVERTISE_1000FULL;
1964 } else if (adv & (ADVERTISED_1000baseT_Half |
1965 ADVERTISED_1000baseT_Full)) {
bf82c189
JP		 1966 netif_info(tp, link, dev,
1967 "PHY does not support 1000Mbps\n");
54405cde 1968 goto out;
bcf0bf90 1969 }
1da177e4 1970
3577aa1b 1971 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1972
4da19633 1973 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1974 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
3577aa1b 1975 } else {
1976 giga_ctrl = 0;
1977
1978 if (speed == SPEED_10)
1979 bmcr = 0;
1980 else if (speed == SPEED_100)
1981 bmcr = BMCR_SPEED100;
1982 else
54405cde 1983 goto out;
3577aa1b 1984
1985 if (duplex == DUPLEX_FULL)
1986 bmcr |= BMCR_FULLDPLX;
2584fbc3
RS		 1987 }
1988
4da19633 1989 rtl_writephy(tp, MII_BMCR, bmcr);
3577aa1b 1990
cecb5fd7
FR		 1991 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1992 tp->mac_version == RTL_GIGA_MAC_VER_03) {
3577aa1b 1993 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
4da19633 1994 rtl_writephy(tp, 0x17, 0x2138);
1995 rtl_writephy(tp, 0x0e, 0x0260);
3577aa1b 1996 } else {
4da19633 1997 rtl_writephy(tp, 0x17, 0x2108);
1998 rtl_writephy(tp, 0x0e, 0x0000);
3577aa1b 1999 }
2000 }
2001
54405cde
ON		 2002 rc = 0;
2003out:
2004 return rc;
1da177e4
LT		 2005}
2006
2007static int rtl8169_set_speed(struct net_device *dev,
54405cde 2008 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1da177e4
LT		 2009{
2010 struct rtl8169_private *tp = netdev_priv(dev);
2011 int ret;
2012
54405cde 2013 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
4876cc1e
FR		 2014 if (ret < 0)
2015 goto out;
1da177e4 2016
4876cc1e 2017 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
c4556975
CHL		 2018 (advertising & ADVERTISED_1000baseT_Full) &&
2019 !pci_is_pcie(tp->pci_dev)) {
1da177e4 2020 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
4876cc1e
FR		 2021 }
2022out:
1da177e4
LT		 2023 return ret;
2024}
2025
2026static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2027{
2028 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4
LT		 2029 int ret;
2030
4876cc1e
FR		 2031 del_timer_sync(&tp->timer);
2032
da78dbff 2033 rtl_lock_work(tp);
cecb5fd7 2034 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
25db0338 2035 cmd->duplex, cmd->advertising);
da78dbff 2036 rtl_unlock_work(tp);
5b0384f4 2037
1da177e4
LT		 2038 return ret;
2039}
2040
c8f44aff
MM		 2041static netdev_features_t rtl8169_fix_features(struct net_device *dev,
2042 netdev_features_t features)
1da177e4 2043{
d58d46b5
FR		 2044 struct rtl8169_private *tp = netdev_priv(dev);
2045
2b7b4318 2046 if (dev->mtu > TD_MSS_MAX)
350fb32a 2047 features &= ~NETIF_F_ALL_TSO;
1da177e4 2048
d58d46b5
FR		 2049 if (dev->mtu > JUMBO_1K &&
2050 !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
2051 features &= ~NETIF_F_IP_CSUM;
2052
350fb32a 2053 return features;
1da177e4
LT		 2054}
2055
da78dbff
FR		 2056static void __rtl8169_set_features(struct net_device *dev,
2057 netdev_features_t features)
1da177e4
LT		 2058{
2059 struct rtl8169_private *tp = netdev_priv(dev);
da78dbff 2060 void __iomem *ioaddr = tp->mmio_addr;
929a031d 2061 u32 rx_config;
1da177e4 2062
929a031d 2063 rx_config = RTL_R32(RxConfig);
2064 if (features & NETIF_F_RXALL)
2065 rx_config |= (AcceptErr | AcceptRunt);
2066 else
2067 rx_config &= ~(AcceptErr | AcceptRunt);
1da177e4 2068
929a031d 2069 RTL_W32(RxConfig, rx_config);
350fb32a 2070
929a031d 2071 if (features & NETIF_F_RXCSUM)
2072 tp->cp_cmd |= RxChkSum;
2073 else
2074 tp->cp_cmd &= ~RxChkSum;
6bbe021d 2075
929a031d 2076 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2077 tp->cp_cmd |= RxVlan;
2078 else
2079 tp->cp_cmd &= ~RxVlan;
2080
2081 tp->cp_cmd |= RTL_R16(CPlusCmd) & ~(RxVlan | RxChkSum);
2082
2083 RTL_W16(CPlusCmd, tp->cp_cmd);
2084 RTL_R16(CPlusCmd);
da78dbff 2085}
1da177e4 2086
da78dbff
FR		 2087static int rtl8169_set_features(struct net_device *dev,
2088 netdev_features_t features)
2089{
2090 struct rtl8169_private *tp = netdev_priv(dev);
2091
929a031d 2092 features &= NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX;
2093
da78dbff 2094 rtl_lock_work(tp);
85911d71 2095 if (features ^ dev->features)
929a031d 2096 __rtl8169_set_features(dev, features);
da78dbff 2097 rtl_unlock_work(tp);
1da177e4
LT		 2098
2099 return 0;
2100}
2101
da78dbff 2102
810f4893 2103static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1da177e4 2104{
df8a39de
JP		 2105 return (skb_vlan_tag_present(skb)) ?
2106 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1da177e4
LT		 2107}
2108
7a8fc77b 2109static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1da177e4
LT		 2110{
2111 u32 opts2 = le32_to_cpu(desc->opts2);
1da177e4 2112
7a8fc77b 2113 if (opts2 & RxVlanTag)
86a9bad3 2114 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1da177e4
LT		 2115}
2116
ccdffb9a 2117static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 2118{
2119 struct rtl8169_private *tp = netdev_priv(dev);
2120 void __iomem *ioaddr = tp->mmio_addr;
2121 u32 status;
2122
2123 cmd->supported =
2124 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
2125 cmd->port = PORT_FIBRE;
2126 cmd->transceiver = XCVR_INTERNAL;
2127
2128 status = RTL_R32(TBICSR);
2129 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
2130 cmd->autoneg = !!(status & TBINwEnable);
2131
70739497 2132 ethtool_cmd_speed_set(cmd, SPEED_1000);
1da177e4 2133 cmd->duplex = DUPLEX_FULL; /* Always set */
ccdffb9a
FR		 2134
2135 return 0;
1da177e4
LT		 2136}
2137
ccdffb9a 2138static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 2139{
2140 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a
FR		 2141
2142 return mii_ethtool_gset(&tp->mii, cmd);
1da177e4
LT		 2143}
2144
2145static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2146{
2147 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 2148 int rc;
1da177e4 2149
da78dbff 2150 rtl_lock_work(tp);
ccdffb9a 2151 rc = tp->get_settings(dev, cmd);
da78dbff 2152 rtl_unlock_work(tp);
1da177e4 2153
ccdffb9a 2154 return rc;
1da177e4
LT		 2155}
2156
2157static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2158 void *p)
2159{
5b0384f4 2160 struct rtl8169_private *tp = netdev_priv(dev);
15edae91
PW		 2161 u32 __iomem *data = tp->mmio_addr;
2162 u32 *dw = p;
2163 int i;
1da177e4 2164
da78dbff 2165 rtl_lock_work(tp);
15edae91
PW		 2166 for (i = 0; i < R8169_REGS_SIZE; i += 4)
2167 memcpy_fromio(dw++, data++, 4);
da78dbff 2168 rtl_unlock_work(tp);
1da177e4
LT		 2169}
2170
b57b7e5a
SH		 2171static u32 rtl8169_get_msglevel(struct net_device *dev)
2172{
2173 struct rtl8169_private *tp = netdev_priv(dev);
2174
2175 return tp->msg_enable;
2176}
2177
2178static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
2179{
2180 struct rtl8169_private *tp = netdev_priv(dev);
2181
2182 tp->msg_enable = value;
2183}
2184
d4a3a0fc
SH		 2185static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
2186 "tx_packets",
2187 "rx_packets",
2188 "tx_errors",
2189 "rx_errors",
2190 "rx_missed",
2191 "align_errors",
2192 "tx_single_collisions",
2193 "tx_multi_collisions",
2194 "unicast",
2195 "broadcast",
2196 "multicast",
2197 "tx_aborted",
2198 "tx_underrun",
2199};
2200
b9f2c044 2201static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 2202{
b9f2c044
JG		 2203 switch (sset) {
2204 case ETH_SS_STATS:
2205 return ARRAY_SIZE(rtl8169_gstrings);
2206 default:
2207 return -EOPNOTSUPP;
2208 }
d4a3a0fc
SH		 2209}
2210
42020320 2211DECLARE_RTL_COND(rtl_counters_cond)
6e85d5ad 2212{
6e85d5ad 2213 void __iomem *ioaddr = tp->mmio_addr;
6e85d5ad 2214
42020320 2215 return RTL_R32(CounterAddrLow) & (CounterReset | CounterDump);
6e85d5ad
CV		 2216}
2217
42020320 2218static bool rtl8169_do_counters(struct net_device *dev, u32 counter_cmd)
6e85d5ad
CV		 2219{
2220 struct rtl8169_private *tp = netdev_priv(dev);
2221 void __iomem *ioaddr = tp->mmio_addr;
42020320
CV		 2222 dma_addr_t paddr = tp->counters_phys_addr;
2223 u32 cmd;
2224 bool ret;
6e85d5ad 2225
42020320
CV		 2226 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
2227 cmd = (u64)paddr & DMA_BIT_MASK(32);
2228 RTL_W32(CounterAddrLow, cmd);
2229 RTL_W32(CounterAddrLow, cmd | counter_cmd);
6e85d5ad 2230
42020320 2231 ret = rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
6e85d5ad 2232
42020320
CV		 2233 RTL_W32(CounterAddrLow, 0);
2234 RTL_W32(CounterAddrHigh, 0);
6e85d5ad 2235
42020320 2236 return ret;
6e85d5ad
CV		 2237}
2238
2239static bool rtl8169_reset_counters(struct net_device *dev)
2240{
2241 struct rtl8169_private *tp = netdev_priv(dev);
6e85d5ad
CV		 2242
2243 /*
2244 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
2245 * tally counters.
2246 */
2247 if (tp->mac_version < RTL_GIGA_MAC_VER_19)
2248 return true;
2249
42020320 2250 return rtl8169_do_counters(dev, CounterReset);
ffc46952
FR		 2251}
2252
6e85d5ad 2253static bool rtl8169_update_counters(struct net_device *dev)
d4a3a0fc
SH		 2254{
2255 struct rtl8169_private *tp = netdev_priv(dev);
2256 void __iomem *ioaddr = tp->mmio_addr;
d4a3a0fc 2257
355423d0
IV		 2258 /*
2259 * Some chips are unable to dump tally counters when the receiver
2260 * is disabled.
2261 */
2262 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
6e85d5ad 2263 return true;
d4a3a0fc 2264
42020320 2265 return rtl8169_do_counters(dev, CounterDump);
6e85d5ad
CV		 2266}
2267
2268static bool rtl8169_init_counter_offsets(struct net_device *dev)
2269{
2270 struct rtl8169_private *tp = netdev_priv(dev);
42020320 2271 struct rtl8169_counters *counters = tp->counters;
6e85d5ad
CV		 2272 bool ret = false;
2273
2274 /*
2275 * rtl8169_init_counter_offsets is called from rtl_open. On chip
2276 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
2277 * reset by a power cycle, while the counter values collected by the
2278 * driver are reset at every driver unload/load cycle.
2279 *
2280 * To make sure the HW values returned by @get_stats64 match the SW
2281 * values, we collect the initial values at first open(*) and use them
2282 * as offsets to normalize the values returned by @get_stats64.
2283 *
2284 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
2285 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
2286 * set at open time by rtl_hw_start.
2287 */
2288
2289 if (tp->tc_offset.inited)
2290 return true;
2291
2292 /* If both, reset and update fail, propagate to caller. */
2293 if (rtl8169_reset_counters(dev))
2294 ret = true;
2295
2296 if (rtl8169_update_counters(dev))
2297 ret = true;
2298
42020320
CV		 2299 tp->tc_offset.tx_errors = counters->tx_errors;
2300 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
2301 tp->tc_offset.tx_aborted = counters->tx_aborted;
6e85d5ad
CV		 2302 tp->tc_offset.inited = true;
2303
2304 return ret;
d4a3a0fc
SH		 2305}
2306
355423d0
IV		 2307static void rtl8169_get_ethtool_stats(struct net_device *dev,
2308 struct ethtool_stats *stats, u64 *data)
2309{
2310 struct rtl8169_private *tp = netdev_priv(dev);
e0636236 2311 struct device *d = &tp->pci_dev->dev;
42020320 2312 struct rtl8169_counters *counters = tp->counters;
355423d0
IV		 2313
2314 ASSERT_RTNL();
2315
e0636236
CHL		 2316 pm_runtime_get_noresume(d);
2317
2318 if (pm_runtime_active(d))
2319 rtl8169_update_counters(dev);
2320
2321 pm_runtime_put_noidle(d);
355423d0 2322
42020320
CV		 2323 data[0] = le64_to_cpu(counters->tx_packets);
2324 data[1] = le64_to_cpu(counters->rx_packets);
2325 data[2] = le64_to_cpu(counters->tx_errors);
2326 data[3] = le32_to_cpu(counters->rx_errors);
2327 data[4] = le16_to_cpu(counters->rx_missed);
2328 data[5] = le16_to_cpu(counters->align_errors);
2329 data[6] = le32_to_cpu(counters->tx_one_collision);
2330 data[7] = le32_to_cpu(counters->tx_multi_collision);
2331 data[8] = le64_to_cpu(counters->rx_unicast);
2332 data[9] = le64_to_cpu(counters->rx_broadcast);
2333 data[10] = le32_to_cpu(counters->rx_multicast);
2334 data[11] = le16_to_cpu(counters->tx_aborted);
2335 data[12] = le16_to_cpu(counters->tx_underun);
355423d0
IV		 2336}
2337
d4a3a0fc
SH		 2338static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2339{
2340 switch(stringset) {
2341 case ETH_SS_STATS:
2342 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
2343 break;
2344 }
2345}
2346
7282d491 2347static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 2348 .get_drvinfo = rtl8169_get_drvinfo,
2349 .get_regs_len = rtl8169_get_regs_len,
2350 .get_link = ethtool_op_get_link,
2351 .get_settings = rtl8169_get_settings,
2352 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 2353 .get_msglevel = rtl8169_get_msglevel,
2354 .set_msglevel = rtl8169_set_msglevel,
1da177e4 2355 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 2356 .get_wol = rtl8169_get_wol,
2357 .set_wol = rtl8169_set_wol,
d4a3a0fc 2358 .get_strings = rtl8169_get_strings,
b9f2c044 2359 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 2360 .get_ethtool_stats = rtl8169_get_ethtool_stats,
e1593bb1 2361 .get_ts_info = ethtool_op_get_ts_info,
1da177e4
LT		 2362};
2363
07d3f51f 2364static void rtl8169_get_mac_version(struct rtl8169_private *tp,
5d320a20 2365 struct net_device *dev, u8 default_version)
1da177e4 2366{
5d320a20 2367 void __iomem *ioaddr = tp->mmio_addr;
0e485150
FR		 2368 /*
2369 * The driver currently handles the 8168Bf and the 8168Be identically
2370 * but they can be identified more specifically through the test below
2371 * if needed:
2372 *
2373 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 2374 *
2375 * Same thing for the 8101Eb and the 8101Ec:
2376 *
2377 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 2378 */
3744100e 2379 static const struct rtl_mac_info {
1da177e4 2380 u32 mask;
e3cf0cc0 2381 u32 val;
1da177e4
LT		 2382 int mac_version;
2383 } mac_info[] = {
935e2218
CHL		 2384 /* 8168EP family. */
2385 { 0x7cf00000, 0x50200000, RTL_GIGA_MAC_VER_51 },
2386 { 0x7cf00000, 0x50100000, RTL_GIGA_MAC_VER_50 },
2387 { 0x7cf00000, 0x50000000, RTL_GIGA_MAC_VER_49 },
2388
6e1d0b89
CHL		 2389 /* 8168H family. */
2390 { 0x7cf00000, 0x54100000, RTL_GIGA_MAC_VER_46 },
2391 { 0x7cf00000, 0x54000000, RTL_GIGA_MAC_VER_45 },
2392
c558386b 2393 /* 8168G family. */
45dd95c4 2394 { 0x7cf00000, 0x5c800000, RTL_GIGA_MAC_VER_44 },
57538c4a 2395 { 0x7cf00000, 0x50900000, RTL_GIGA_MAC_VER_42 },
c558386b
HW		 2396 { 0x7cf00000, 0x4c100000, RTL_GIGA_MAC_VER_41 },
2397 { 0x7cf00000, 0x4c000000, RTL_GIGA_MAC_VER_40 },
2398
c2218925 2399 /* 8168F family. */
b3d7b2f2 2400 { 0x7c800000, 0x48800000, RTL_GIGA_MAC_VER_38 },
c2218925
HW		 2401 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
2402 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
2403
01dc7fec 2404 /* 8168E family. */
70090424 2405 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
01dc7fec 2406 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
2407 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
2408 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
2409
5b538df9 2410 /* 8168D family. */
daf9df6d 2411 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
2412 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
daf9df6d 2413 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
5b538df9 2414
e6de30d6 2415 /* 8168DP family. */
2416 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
2417 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
4804b3b3 2418 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
e6de30d6 2419
ef808d50 2420 /* 8168C family. */
17c99297 2421 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
ef3386f0 2422 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 2423 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 2424 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 2425 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
2426 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 2427 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
6fb07058 2428 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
ef808d50 2429 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 2430
2431 /* 8168B family. */
2432 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
2433 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
2434 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
2435 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
2436
2437 /* 8101 family. */
5598bfe5
HW		 2438 { 0x7cf00000, 0x44900000, RTL_GIGA_MAC_VER_39 },
2439 { 0x7c800000, 0x44800000, RTL_GIGA_MAC_VER_39 },
7e18dca1 2440 { 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37 },
36a0e6c2 2441 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
5a5e4443
HW		 2442 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
2443 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
2444 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2857ffb7
FR		 2445 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
2446 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
2447 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
2448 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
2449 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
2450 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 2451 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 2452 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 2453 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 2454 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
2455 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 2456 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
2457 /* FIXME: where did these entries come from ? -- FR */
2458 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
2459 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
2460
2461 /* 8110 family. */
2462 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
2463 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
2464 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
2465 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
2466 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
2467 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
2468
f21b75e9
JD		 2469 /* Catch-all */
2470 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
3744100e
FR		 2471 };
2472 const struct rtl_mac_info *p = mac_info;
1da177e4
LT		 2473 u32 reg;
2474
e3cf0cc0
FR		 2475 reg = RTL_R32(TxConfig);
2476 while ((reg & p->mask) != p->val)
1da177e4
LT		 2477 p++;
2478 tp->mac_version = p->mac_version;
5d320a20
FR		 2479
2480 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2481 netif_notice(tp, probe, dev,
2482 "unknown MAC, using family default\n");
2483 tp->mac_version = default_version;
58152cd4 2484 } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
2485 tp->mac_version = tp->mii.supports_gmii ?
2486 RTL_GIGA_MAC_VER_42 :
2487 RTL_GIGA_MAC_VER_43;
6e1d0b89
CHL		 2488 } else if (tp->mac_version == RTL_GIGA_MAC_VER_45) {
2489 tp->mac_version = tp->mii.supports_gmii ?
2490 RTL_GIGA_MAC_VER_45 :
2491 RTL_GIGA_MAC_VER_47;
2492 } else if (tp->mac_version == RTL_GIGA_MAC_VER_46) {
2493 tp->mac_version = tp->mii.supports_gmii ?
2494 RTL_GIGA_MAC_VER_46 :
2495 RTL_GIGA_MAC_VER_48;
5d320a20 2496 }
1da177e4
LT		 2497}
2498
2499static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2500{
bcf0bf90 2501 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 2502}
2503
867763c1
FR		 2504struct phy_reg {
2505 u16 reg;
2506 u16 val;
2507};
2508
4da19633 2509static void rtl_writephy_batch(struct rtl8169_private *tp,
2510 const struct phy_reg *regs, int len)
867763c1
FR		 2511{
2512 while (len-- > 0) {
4da19633 2513 rtl_writephy(tp, regs->reg, regs->val);
867763c1
FR		 2514 regs++;
2515 }
2516}
2517
bca03d5f 2518#define PHY_READ 0x00000000
2519#define PHY_DATA_OR 0x10000000
2520#define PHY_DATA_AND 0x20000000
2521#define PHY_BJMPN 0x30000000
eee3786f 2522#define PHY_MDIO_CHG 0x40000000
bca03d5f 2523#define PHY_CLEAR_READCOUNT 0x70000000
2524#define PHY_WRITE 0x80000000
2525#define PHY_READCOUNT_EQ_SKIP 0x90000000
2526#define PHY_COMP_EQ_SKIPN 0xa0000000
2527#define PHY_COMP_NEQ_SKIPN 0xb0000000
2528#define PHY_WRITE_PREVIOUS 0xc0000000
2529#define PHY_SKIPN 0xd0000000
2530#define PHY_DELAY_MS 0xe0000000
bca03d5f 2531
960aee6c
HW		 2532struct fw_info {
2533 u32 magic;
2534 char version[RTL_VER_SIZE];
2535 __le32 fw_start;
2536 __le32 fw_len;
2537 u8 chksum;
2538} __packed;
2539
1c361efb
FR		 2540#define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2541
2542static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
bca03d5f 2543{
b6ffd97f 2544 const struct firmware *fw = rtl_fw->fw;
960aee6c 2545 struct fw_info *fw_info = (struct fw_info *)fw->data;
1c361efb
FR		 2546 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2547 char *version = rtl_fw->version;
2548 bool rc = false;
2549
2550 if (fw->size < FW_OPCODE_SIZE)
2551 goto out;
960aee6c
HW		 2552
2553 if (!fw_info->magic) {
2554 size_t i, size, start;
2555 u8 checksum = 0;
2556
2557 if (fw->size < sizeof(*fw_info))
2558 goto out;
2559
2560 for (i = 0; i < fw->size; i++)
2561 checksum += fw->data[i];
2562 if (checksum != 0)
2563 goto out;
2564
2565 start = le32_to_cpu(fw_info->fw_start);
2566 if (start > fw->size)
2567 goto out;
2568
2569 size = le32_to_cpu(fw_info->fw_len);
2570 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2571 goto out;
2572
2573 memcpy(version, fw_info->version, RTL_VER_SIZE);
2574
2575 pa->code = (__le32 *)(fw->data + start);
2576 pa->size = size;
2577 } else {
1c361efb
FR		 2578 if (fw->size % FW_OPCODE_SIZE)
2579 goto out;
2580
2581 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2582
2583 pa->code = (__le32 *)fw->data;
2584 pa->size = fw->size / FW_OPCODE_SIZE;
2585 }
2586 version[RTL_VER_SIZE - 1] = 0;
2587
2588 rc = true;
2589out:
2590 return rc;
2591}
2592
fd112f2e
FR		 2593static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2594 struct rtl_fw_phy_action *pa)
1c361efb 2595{
fd112f2e 2596 bool rc = false;
1c361efb 2597 size_t index;
bca03d5f 2598
1c361efb
FR		 2599 for (index = 0; index < pa->size; index++) {
2600 u32 action = le32_to_cpu(pa->code[index]);
42b82dc1 2601 u32 regno = (action & 0x0fff0000) >> 16;
bca03d5f 2602
42b82dc1 2603 switch(action & 0xf0000000) {
2604 case PHY_READ:
2605 case PHY_DATA_OR:
2606 case PHY_DATA_AND:
eee3786f 2607 case PHY_MDIO_CHG:
42b82dc1 2608 case PHY_CLEAR_READCOUNT:
2609 case PHY_WRITE:
2610 case PHY_WRITE_PREVIOUS:
2611 case PHY_DELAY_MS:
2612 break;
2613
2614 case PHY_BJMPN:
2615 if (regno > index) {
fd112f2e 2616 netif_err(tp, ifup, tp->dev,
cecb5fd7 2617 "Out of range of firmware\n");
fd112f2e 2618 goto out;
42b82dc1 2619 }
2620 break;
2621 case PHY_READCOUNT_EQ_SKIP:
1c361efb 2622 if (index + 2 >= pa->size) {
fd112f2e 2623 netif_err(tp, ifup, tp->dev,
cecb5fd7 2624 "Out of range of firmware\n");
fd112f2e 2625 goto out;
42b82dc1 2626 }
2627 break;
2628 case PHY_COMP_EQ_SKIPN:
2629 case PHY_COMP_NEQ_SKIPN:
2630 case PHY_SKIPN:
1c361efb 2631 if (index + 1 + regno >= pa->size) {
fd112f2e 2632 netif_err(tp, ifup, tp->dev,
cecb5fd7 2633 "Out of range of firmware\n");
fd112f2e 2634 goto out;
42b82dc1 2635 }
bca03d5f 2636 break;
2637
42b82dc1 2638 default:
fd112f2e 2639 netif_err(tp, ifup, tp->dev,
42b82dc1 2640 "Invalid action 0x%08x\n", action);
fd112f2e 2641 goto out;
bca03d5f 2642 }
2643 }
fd112f2e
FR		 2644 rc = true;
2645out:
2646 return rc;
2647}
bca03d5f 2648
fd112f2e
FR		 2649static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2650{
2651 struct net_device *dev = tp->dev;
2652 int rc = -EINVAL;
2653
2654 if (!rtl_fw_format_ok(tp, rtl_fw)) {
5c2d2b14 2655 netif_err(tp, ifup, dev, "invalid firmware\n");
fd112f2e
FR		 2656 goto out;
2657 }
2658
2659 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2660 rc = 0;
2661out:
2662 return rc;
2663}
2664
2665static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2666{
2667 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
eee3786f 2668 struct mdio_ops org, *ops = &tp->mdio_ops;
fd112f2e
FR		 2669 u32 predata, count;
2670 size_t index;
2671
2672 predata = count = 0;
eee3786f 2673 org.write = ops->write;
2674 org.read = ops->read;
42b82dc1 2675
1c361efb
FR		 2676 for (index = 0; index < pa->size; ) {
2677 u32 action = le32_to_cpu(pa->code[index]);
bca03d5f 2678 u32 data = action & 0x0000ffff;
42b82dc1 2679 u32 regno = (action & 0x0fff0000) >> 16;
2680
2681 if (!action)
2682 break;
bca03d5f 2683
2684 switch(action & 0xf0000000) {
42b82dc1 2685 case PHY_READ:
2686 predata = rtl_readphy(tp, regno);
2687 count++;
2688 index++;
2689 break;
2690 case PHY_DATA_OR:
2691 predata |= data;
2692 index++;
2693 break;
2694 case PHY_DATA_AND:
2695 predata &= data;
2696 index++;
2697 break;
2698 case PHY_BJMPN:
2699 index -= regno;
2700 break;
eee3786f 2701 case PHY_MDIO_CHG:
2702 if (data == 0) {
2703 ops->write = org.write;
2704 ops->read = org.read;
2705 } else if (data == 1) {
2706 ops->write = mac_mcu_write;
2707 ops->read = mac_mcu_read;
2708 }
2709
42b82dc1 2710 index++;
2711 break;
2712 case PHY_CLEAR_READCOUNT:
2713 count = 0;
2714 index++;
2715 break;
bca03d5f 2716 case PHY_WRITE:
42b82dc1 2717 rtl_writephy(tp, regno, data);
2718 index++;
2719 break;
2720 case PHY_READCOUNT_EQ_SKIP:
cecb5fd7 2721 index += (count == data) ? 2 : 1;
bca03d5f 2722 break;
42b82dc1 2723 case PHY_COMP_EQ_SKIPN:
2724 if (predata == data)
2725 index += regno;
2726 index++;
2727 break;
2728 case PHY_COMP_NEQ_SKIPN:
2729 if (predata != data)
2730 index += regno;
2731 index++;
2732 break;
2733 case PHY_WRITE_PREVIOUS:
2734 rtl_writephy(tp, regno, predata);
2735 index++;
2736 break;
2737 case PHY_SKIPN:
2738 index += regno + 1;
2739 break;
2740 case PHY_DELAY_MS:
2741 mdelay(data);
2742 index++;
2743 break;
2744
bca03d5f 2745 default:
2746 BUG();
2747 }
2748 }
eee3786f 2749
2750 ops->write = org.write;
2751 ops->read = org.read;
bca03d5f 2752}
2753
f1e02ed1 2754static void rtl_release_firmware(struct rtl8169_private *tp)
2755{
b6ffd97f
FR		 2756 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2757 release_firmware(tp->rtl_fw->fw);
2758 kfree(tp->rtl_fw);
2759 }
2760 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
f1e02ed1 2761}
2762
953a12cc 2763static void rtl_apply_firmware(struct rtl8169_private *tp)
f1e02ed1 2764{
b6ffd97f 2765 struct rtl_fw *rtl_fw = tp->rtl_fw;
f1e02ed1 2766
2767 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
eef63cc1 2768 if (!IS_ERR_OR_NULL(rtl_fw))
b6ffd97f 2769 rtl_phy_write_fw(tp, rtl_fw);
953a12cc
FR		 2770}
2771
2772static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2773{
2774 if (rtl_readphy(tp, reg) != val)
2775 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2776 else
2777 rtl_apply_firmware(tp);
f1e02ed1 2778}
2779
4da19633 2780static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1da177e4 2781{
350f7596 2782 static const struct phy_reg phy_reg_init[] = {
0b9b571d 2783 { 0x1f, 0x0001 },
2784 { 0x06, 0x006e },
2785 { 0x08, 0x0708 },
2786 { 0x15, 0x4000 },
2787 { 0x18, 0x65c7 },
1da177e4 2788
0b9b571d 2789 { 0x1f, 0x0001 },
2790 { 0x03, 0x00a1 },
2791 { 0x02, 0x0008 },
2792 { 0x01, 0x0120 },
2793 { 0x00, 0x1000 },
2794 { 0x04, 0x0800 },
2795 { 0x04, 0x0000 },
1da177e4 2796
0b9b571d 2797 { 0x03, 0xff41 },
2798 { 0x02, 0xdf60 },
2799 { 0x01, 0x0140 },
2800 { 0x00, 0x0077 },
2801 { 0x04, 0x7800 },
2802 { 0x04, 0x7000 },
2803
2804 { 0x03, 0x802f },
2805 { 0x02, 0x4f02 },
2806 { 0x01, 0x0409 },
2807 { 0x00, 0xf0f9 },
2808 { 0x04, 0x9800 },
2809 { 0x04, 0x9000 },
2810
2811 { 0x03, 0xdf01 },
2812 { 0x02, 0xdf20 },
2813 { 0x01, 0xff95 },
2814 { 0x00, 0xba00 },
2815 { 0x04, 0xa800 },
2816 { 0x04, 0xa000 },
2817
2818 { 0x03, 0xff41 },
2819 { 0x02, 0xdf20 },
2820 { 0x01, 0x0140 },
2821 { 0x00, 0x00bb },
2822 { 0x04, 0xb800 },
2823 { 0x04, 0xb000 },
2824
2825 { 0x03, 0xdf41 },
2826 { 0x02, 0xdc60 },
2827 { 0x01, 0x6340 },
2828 { 0x00, 0x007d },
2829 { 0x04, 0xd800 },
2830 { 0x04, 0xd000 },
2831
2832 { 0x03, 0xdf01 },
2833 { 0x02, 0xdf20 },
2834 { 0x01, 0x100a },
2835 { 0x00, 0xa0ff },
2836 { 0x04, 0xf800 },
2837 { 0x04, 0xf000 },
2838
2839 { 0x1f, 0x0000 },
2840 { 0x0b, 0x0000 },
2841 { 0x00, 0x9200 }
2842 };
1da177e4 2843
4da19633 2844 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1da177e4
LT		 2845}
2846
4da19633 2847static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
5615d9f1 2848{
350f7596 2849 static const struct phy_reg phy_reg_init[] = {
a441d7b6
FR		 2850 { 0x1f, 0x0002 },
2851 { 0x01, 0x90d0 },
2852 { 0x1f, 0x0000 }
2853 };
2854
4da19633 2855 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 2856}
2857
4da19633 2858static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2e955856 2859{
2860 struct pci_dev *pdev = tp->pci_dev;
2e955856 2861
ccbae55e
SS		 2862 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2863 (pdev->subsystem_device != 0xe000))
2e955856 2864 return;
2865
4da19633 2866 rtl_writephy(tp, 0x1f, 0x0001);
2867 rtl_writephy(tp, 0x10, 0xf01b);
2868 rtl_writephy(tp, 0x1f, 0x0000);
2e955856 2869}
2870
4da19633 2871static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2e955856 2872{
350f7596 2873 static const struct phy_reg phy_reg_init[] = {
2e955856 2874 { 0x1f, 0x0001 },
2875 { 0x04, 0x0000 },
2876 { 0x03, 0x00a1 },
2877 { 0x02, 0x0008 },
2878 { 0x01, 0x0120 },
2879 { 0x00, 0x1000 },
2880 { 0x04, 0x0800 },
2881 { 0x04, 0x9000 },
2882 { 0x03, 0x802f },
2883 { 0x02, 0x4f02 },
2884 { 0x01, 0x0409 },
2885 { 0x00, 0xf099 },
2886 { 0x04, 0x9800 },
2887 { 0x04, 0xa000 },
2888 { 0x03, 0xdf01 },
2889 { 0x02, 0xdf20 },
2890 { 0x01, 0xff95 },
2891 { 0x00, 0xba00 },
2892 { 0x04, 0xa800 },
2893 { 0x04, 0xf000 },
2894 { 0x03, 0xdf01 },
2895 { 0x02, 0xdf20 },
2896 { 0x01, 0x101a },
2897 { 0x00, 0xa0ff },
2898 { 0x04, 0xf800 },
2899 { 0x04, 0x0000 },
2900 { 0x1f, 0x0000 },
2901
2902 { 0x1f, 0x0001 },
2903 { 0x10, 0xf41b },
2904 { 0x14, 0xfb54 },
2905 { 0x18, 0xf5c7 },
2906 { 0x1f, 0x0000 },
2907
2908 { 0x1f, 0x0001 },
2909 { 0x17, 0x0cc0 },
2910 { 0x1f, 0x0000 }
2911 };
2912
4da19633 2913 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2e955856 2914
4da19633 2915 rtl8169scd_hw_phy_config_quirk(tp);
2e955856 2916}
2917
4da19633 2918static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
8c7006aa 2919{
350f7596 2920 static const struct phy_reg phy_reg_init[] = {
8c7006aa 2921 { 0x1f, 0x0001 },
2922 { 0x04, 0x0000 },
2923 { 0x03, 0x00a1 },
2924 { 0x02, 0x0008 },
2925 { 0x01, 0x0120 },
2926 { 0x00, 0x1000 },
2927 { 0x04, 0x0800 },
2928 { 0x04, 0x9000 },
2929 { 0x03, 0x802f },
2930 { 0x02, 0x4f02 },
2931 { 0x01, 0x0409 },
2932 { 0x00, 0xf099 },
2933 { 0x04, 0x9800 },
2934 { 0x04, 0xa000 },
2935 { 0x03, 0xdf01 },
2936 { 0x02, 0xdf20 },
2937 { 0x01, 0xff95 },
2938 { 0x00, 0xba00 },
2939 { 0x04, 0xa800 },
2940 { 0x04, 0xf000 },
2941 { 0x03, 0xdf01 },
2942 { 0x02, 0xdf20 },
2943 { 0x01, 0x101a },
2944 { 0x00, 0xa0ff },
2945 { 0x04, 0xf800 },
2946 { 0x04, 0x0000 },
2947 { 0x1f, 0x0000 },
2948
2949 { 0x1f, 0x0001 },
2950 { 0x0b, 0x8480 },
2951 { 0x1f, 0x0000 },
2952
2953 { 0x1f, 0x0001 },
2954 { 0x18, 0x67c7 },
2955 { 0x04, 0x2000 },
2956 { 0x03, 0x002f },
2957 { 0x02, 0x4360 },
2958 { 0x01, 0x0109 },
2959 { 0x00, 0x3022 },
2960 { 0x04, 0x2800 },
2961 { 0x1f, 0x0000 },
2962
2963 { 0x1f, 0x0001 },
2964 { 0x17, 0x0cc0 },
2965 { 0x1f, 0x0000 }
2966 };
2967
4da19633 2968 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
8c7006aa 2969}
2970
4da19633 2971static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
236b8082 2972{
350f7596 2973 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2974 { 0x10, 0xf41b },
2975 { 0x1f, 0x0000 }
2976 };
2977
4da19633 2978 rtl_writephy(tp, 0x1f, 0x0001);
2979 rtl_patchphy(tp, 0x16, 1 << 0);
236b8082 2980
4da19633 2981 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2982}
2983
4da19633 2984static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
236b8082 2985{
350f7596 2986 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2987 { 0x1f, 0x0001 },
2988 { 0x10, 0xf41b },
2989 { 0x1f, 0x0000 }
2990 };
2991
4da19633 2992 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2993}
2994
4da19633 2995static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2996{
350f7596 2997 static const struct phy_reg phy_reg_init[] = {
867763c1
FR		 2998 { 0x1f, 0x0000 },
2999 { 0x1d, 0x0f00 },
3000 { 0x1f, 0x0002 },
3001 { 0x0c, 0x1ec8 },
3002 { 0x1f, 0x0000 }
3003 };
3004
4da19633 3005 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
867763c1
FR		 3006}
3007
4da19633 3008static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
ef3386f0 3009{
350f7596 3010 static const struct phy_reg phy_reg_init[] = {
ef3386f0
FR		 3011 { 0x1f, 0x0001 },
3012 { 0x1d, 0x3d98 },
3013 { 0x1f, 0x0000 }
3014 };
3015
4da19633 3016 rtl_writephy(tp, 0x1f, 0x0000);
3017 rtl_patchphy(tp, 0x14, 1 << 5);
3018 rtl_patchphy(tp, 0x0d, 1 << 5);
ef3386f0 3019
4da19633 3020 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
ef3386f0
FR		 3021}
3022
4da19633 3023static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 3024{
350f7596 3025 static const struct phy_reg phy_reg_init[] = {
a3f80671
FR		 3026 { 0x1f, 0x0001 },
3027 { 0x12, 0x2300 },
867763c1
FR		 3028 { 0x1f, 0x0002 },
3029 { 0x00, 0x88d4 },
3030 { 0x01, 0x82b1 },
3031 { 0x03, 0x7002 },
3032 { 0x08, 0x9e30 },
3033 { 0x09, 0x01f0 },
3034 { 0x0a, 0x5500 },
3035 { 0x0c, 0x00c8 },
3036 { 0x1f, 0x0003 },
3037 { 0x12, 0xc096 },
3038 { 0x16, 0x000a },
f50d4275
FR		 3039 { 0x1f, 0x0000 },
3040 { 0x1f, 0x0000 },
3041 { 0x09, 0x2000 },
3042 { 0x09, 0x0000 }
867763c1
FR		 3043 };
3044
4da19633 3045 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 3046
4da19633 3047 rtl_patchphy(tp, 0x14, 1 << 5);
3048 rtl_patchphy(tp, 0x0d, 1 << 5);
3049 rtl_writephy(tp, 0x1f, 0x0000);
867763c1
FR		 3050}
3051
4da19633 3052static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
7da97ec9 3053{
350f7596 3054 static const struct phy_reg phy_reg_init[] = {
f50d4275 3055 { 0x1f, 0x0001 },
7da97ec9 3056 { 0x12, 0x2300 },
f50d4275
FR		 3057 { 0x03, 0x802f },
3058 { 0x02, 0x4f02 },
3059 { 0x01, 0x0409 },
3060 { 0x00, 0xf099 },
3061 { 0x04, 0x9800 },
3062 { 0x04, 0x9000 },
3063 { 0x1d, 0x3d98 },
7da97ec9
FR		 3064 { 0x1f, 0x0002 },
3065 { 0x0c, 0x7eb8 },
f50d4275
FR		 3066 { 0x06, 0x0761 },
3067 { 0x1f, 0x0003 },
3068 { 0x16, 0x0f0a },
7da97ec9
FR		 3069 { 0x1f, 0x0000 }
3070 };
3071
4da19633 3072 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 3073
4da19633 3074 rtl_patchphy(tp, 0x16, 1 << 0);
3075 rtl_patchphy(tp, 0x14, 1 << 5);
3076 rtl_patchphy(tp, 0x0d, 1 << 5);
3077 rtl_writephy(tp, 0x1f, 0x0000);
7da97ec9
FR		 3078}
3079
4da19633 3080static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
197ff761 3081{
350f7596 3082 static const struct phy_reg phy_reg_init[] = {
197ff761
FR		 3083 { 0x1f, 0x0001 },
3084 { 0x12, 0x2300 },
3085 { 0x1d, 0x3d98 },
3086 { 0x1f, 0x0002 },
3087 { 0x0c, 0x7eb8 },
3088 { 0x06, 0x5461 },
3089 { 0x1f, 0x0003 },
3090 { 0x16, 0x0f0a },
3091 { 0x1f, 0x0000 }
3092 };
3093
4da19633 3094 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
197ff761 3095
4da19633 3096 rtl_patchphy(tp, 0x16, 1 << 0);
3097 rtl_patchphy(tp, 0x14, 1 << 5);
3098 rtl_patchphy(tp, 0x0d, 1 << 5);
3099 rtl_writephy(tp, 0x1f, 0x0000);
197ff761
FR		 3100}
3101
4da19633 3102static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
6fb07058 3103{
4da19633 3104 rtl8168c_3_hw_phy_config(tp);
6fb07058
FR		 3105}
3106
bca03d5f 3107static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
5b538df9 3108{
350f7596 3109 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 3110 /* Channel Estimation */
5b538df9 3111 { 0x1f, 0x0001 },
daf9df6d 3112 { 0x06, 0x4064 },
3113 { 0x07, 0x2863 },
3114 { 0x08, 0x059c },
3115 { 0x09, 0x26b4 },
3116 { 0x0a, 0x6a19 },
3117 { 0x0b, 0xdcc8 },
3118 { 0x10, 0xf06d },
3119 { 0x14, 0x7f68 },
3120 { 0x18, 0x7fd9 },
3121 { 0x1c, 0xf0ff },
3122 { 0x1d, 0x3d9c },
5b538df9 3123 { 0x1f, 0x0003 },
daf9df6d 3124 { 0x12, 0xf49f },
3125 { 0x13, 0x070b },
3126 { 0x1a, 0x05ad },
bca03d5f 3127 { 0x14, 0x94c0 },
3128
3129 /*
3130 * Tx Error Issue
cecb5fd7 3131 * Enhance line driver power
bca03d5f 3132 */
5b538df9 3133 { 0x1f, 0x0002 },
daf9df6d 3134 { 0x06, 0x5561 },
3135 { 0x1f, 0x0005 },
3136 { 0x05, 0x8332 },
bca03d5f 3137 { 0x06, 0x5561 },
3138
3139 /*
3140 * Can not link to 1Gbps with bad cable
3141 * Decrease SNR threshold form 21.07dB to 19.04dB
3142 */
3143 { 0x1f, 0x0001 },
3144 { 0x17, 0x0cc0 },
daf9df6d 3145
5b538df9 3146 { 0x1f, 0x0000 },
bca03d5f 3147 { 0x0d, 0xf880 }
daf9df6d 3148 };
3149
4da19633 3150 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
daf9df6d 3151
bca03d5f 3152 /*
3153 * Rx Error Issue
3154 * Fine Tune Switching regulator parameter
3155 */
4da19633 3156 rtl_writephy(tp, 0x1f, 0x0002);
76564428
CHL		 3157 rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
3158 rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
daf9df6d 3159
fdf6fc06 3160 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
350f7596 3161 static const struct phy_reg phy_reg_init[] = {
daf9df6d 3162 { 0x1f, 0x0002 },
3163 { 0x05, 0x669a },
3164 { 0x1f, 0x0005 },
3165 { 0x05, 0x8330 },
3166 { 0x06, 0x669a },
3167 { 0x1f, 0x0002 }
3168 };
3169 int val;
3170
4da19633 3171 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 3172
4da19633 3173 val = rtl_readphy(tp, 0x0d);
daf9df6d 3174
3175 if ((val & 0x00ff) != 0x006c) {
350f7596 3176 static const u32 set[] = {
daf9df6d 3177 0x0065, 0x0066, 0x0067, 0x0068,
3178 0x0069, 0x006a, 0x006b, 0x006c
3179 };
3180 int i;
3181
4da19633 3182 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 3183
3184 val &= 0xff00;
3185 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 3186 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 3187 }
3188 } else {
350f7596 3189 static const struct phy_reg phy_reg_init[] = {
daf9df6d 3190 { 0x1f, 0x0002 },
3191 { 0x05, 0x6662 },
3192 { 0x1f, 0x0005 },
3193 { 0x05, 0x8330 },
3194 { 0x06, 0x6662 }
3195 };
3196
4da19633 3197 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 3198 }
3199
bca03d5f 3200 /* RSET couple improve */
4da19633 3201 rtl_writephy(tp, 0x1f, 0x0002);
3202 rtl_patchphy(tp, 0x0d, 0x0300);
3203 rtl_patchphy(tp, 0x0f, 0x0010);
daf9df6d 3204
bca03d5f 3205 /* Fine tune PLL performance */
4da19633 3206 rtl_writephy(tp, 0x1f, 0x0002);
76564428
CHL		 3207 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3208 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 3209
4da19633 3210 rtl_writephy(tp, 0x1f, 0x0005);
3211 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 3212
3213 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
bca03d5f 3214
4da19633 3215 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 3216}
3217
bca03d5f 3218static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 3219{
350f7596 3220 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 3221 /* Channel Estimation */
daf9df6d 3222 { 0x1f, 0x0001 },
3223 { 0x06, 0x4064 },
3224 { 0x07, 0x2863 },
3225 { 0x08, 0x059c },
3226 { 0x09, 0x26b4 },
3227 { 0x0a, 0x6a19 },
3228 { 0x0b, 0xdcc8 },
3229 { 0x10, 0xf06d },
3230 { 0x14, 0x7f68 },
3231 { 0x18, 0x7fd9 },
3232 { 0x1c, 0xf0ff },
3233 { 0x1d, 0x3d9c },
3234 { 0x1f, 0x0003 },
3235 { 0x12, 0xf49f },
3236 { 0x13, 0x070b },
3237 { 0x1a, 0x05ad },
3238 { 0x14, 0x94c0 },
3239
bca03d5f 3240 /*
3241 * Tx Error Issue
cecb5fd7 3242 * Enhance line driver power
bca03d5f 3243 */
daf9df6d 3244 { 0x1f, 0x0002 },
3245 { 0x06, 0x5561 },
3246 { 0x1f, 0x0005 },
3247 { 0x05, 0x8332 },
bca03d5f 3248 { 0x06, 0x5561 },
3249
3250 /*
3251 * Can not link to 1Gbps with bad cable
3252 * Decrease SNR threshold form 21.07dB to 19.04dB
3253 */
3254 { 0x1f, 0x0001 },
3255 { 0x17, 0x0cc0 },
daf9df6d 3256
3257 { 0x1f, 0x0000 },
bca03d5f 3258 { 0x0d, 0xf880 }
5b538df9
FR		 3259 };
3260
4da19633 3261 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
5b538df9 3262
fdf6fc06 3263 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
350f7596 3264 static const struct phy_reg phy_reg_init[] = {
daf9df6d 3265 { 0x1f, 0x0002 },
3266 { 0x05, 0x669a },
5b538df9 3267 { 0x1f, 0x0005 },
daf9df6d 3268 { 0x05, 0x8330 },
3269 { 0x06, 0x669a },
3270
3271 { 0x1f, 0x0002 }
3272 };
3273 int val;
3274
4da19633 3275 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 3276
4da19633 3277 val = rtl_readphy(tp, 0x0d);
daf9df6d 3278 if ((val & 0x00ff) != 0x006c) {
b6bc7650 3279 static const u32 set[] = {
daf9df6d 3280 0x0065, 0x0066, 0x0067, 0x0068,
3281 0x0069, 0x006a, 0x006b, 0x006c
3282 };
3283 int i;
3284
4da19633 3285 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 3286
3287 val &= 0xff00;
3288 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 3289 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 3290 }
3291 } else {
350f7596 3292 static const struct phy_reg phy_reg_init[] = {
daf9df6d 3293 { 0x1f, 0x0002 },
3294 { 0x05, 0x2642 },
5b538df9 3295 { 0x1f, 0x0005 },
daf9df6d 3296 { 0x05, 0x8330 },
3297 { 0x06, 0x2642 }
5b538df9
FR		 3298 };
3299
4da19633 3300 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 3301 }
3302
bca03d5f 3303 /* Fine tune PLL performance */
4da19633 3304 rtl_writephy(tp, 0x1f, 0x0002);
76564428
CHL		 3305 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3306 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 3307
bca03d5f 3308 /* Switching regulator Slew rate */
4da19633 3309 rtl_writephy(tp, 0x1f, 0x0002);
3310 rtl_patchphy(tp, 0x0f, 0x0017);
daf9df6d 3311
4da19633 3312 rtl_writephy(tp, 0x1f, 0x0005);
3313 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 3314
3315 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
bca03d5f 3316
4da19633 3317 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 3318}
3319
4da19633 3320static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 3321{
350f7596 3322 static const struct phy_reg phy_reg_init[] = {
daf9df6d 3323 { 0x1f, 0x0002 },
3324 { 0x10, 0x0008 },
3325 { 0x0d, 0x006c },
3326
3327 { 0x1f, 0x0000 },
3328 { 0x0d, 0xf880 },
3329
3330 { 0x1f, 0x0001 },
3331 { 0x17, 0x0cc0 },
3332
3333 { 0x1f, 0x0001 },
3334 { 0x0b, 0xa4d8 },
3335 { 0x09, 0x281c },
3336 { 0x07, 0x2883 },
3337 { 0x0a, 0x6b35 },
3338 { 0x1d, 0x3da4 },
3339 { 0x1c, 0xeffd },
3340 { 0x14, 0x7f52 },
3341 { 0x18, 0x7fc6 },
3342 { 0x08, 0x0601 },
3343 { 0x06, 0x4063 },
3344 { 0x10, 0xf074 },
3345 { 0x1f, 0x0003 },
3346 { 0x13, 0x0789 },
3347 { 0x12, 0xf4bd },
3348 { 0x1a, 0x04fd },
3349 { 0x14, 0x84b0 },
3350 { 0x1f, 0x0000 },
3351 { 0x00, 0x9200 },
3352
3353 { 0x1f, 0x0005 },
3354 { 0x01, 0x0340 },
3355 { 0x1f, 0x0001 },
3356 { 0x04, 0x4000 },
3357 { 0x03, 0x1d21 },
3358 { 0x02, 0x0c32 },
3359 { 0x01, 0x0200 },
3360 { 0x00, 0x5554 },
3361 { 0x04, 0x4800 },
3362 { 0x04, 0x4000 },
3363 { 0x04, 0xf000 },
3364 { 0x03, 0xdf01 },
3365 { 0x02, 0xdf20 },
3366 { 0x01, 0x101a },
3367 { 0x00, 0xa0ff },
3368 { 0x04, 0xf800 },
3369 { 0x04, 0xf000 },
3370 { 0x1f, 0x0000 },
3371
3372 { 0x1f, 0x0007 },
3373 { 0x1e, 0x0023 },
3374 { 0x16, 0x0000 },
3375 { 0x1f, 0x0000 }
3376 };
3377
4da19633 3378 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 3379}
3380
e6de30d6 3381static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3382{
3383 static const struct phy_reg phy_reg_init[] = {
3384 { 0x1f, 0x0001 },
3385 { 0x17, 0x0cc0 },
3386
3387 { 0x1f, 0x0007 },
3388 { 0x1e, 0x002d },
3389 { 0x18, 0x0040 },
3390 { 0x1f, 0x0000 }
3391 };
3392
3393 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3394 rtl_patchphy(tp, 0x0d, 1 << 5);
3395}
3396
70090424 3397static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
01dc7fec 3398{
3399 static const struct phy_reg phy_reg_init[] = {
3400 /* Enable Delay cap */
3401 { 0x1f, 0x0005 },
3402 { 0x05, 0x8b80 },
3403 { 0x06, 0xc896 },
3404 { 0x1f, 0x0000 },
3405
3406 /* Channel estimation fine tune */
3407 { 0x1f, 0x0001 },
3408 { 0x0b, 0x6c20 },
3409 { 0x07, 0x2872 },
3410 { 0x1c, 0xefff },
3411 { 0x1f, 0x0003 },
3412 { 0x14, 0x6420 },
3413 { 0x1f, 0x0000 },
3414
3415 /* Update PFM & 10M TX idle timer */
3416 { 0x1f, 0x0007 },
3417 { 0x1e, 0x002f },
3418 { 0x15, 0x1919 },
3419 { 0x1f, 0x0000 },
3420
3421 { 0x1f, 0x0007 },
3422 { 0x1e, 0x00ac },
3423 { 0x18, 0x0006 },
3424 { 0x1f, 0x0000 }
3425 };
3426
15ecd039
FR		 3427 rtl_apply_firmware(tp);
3428
01dc7fec 3429 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3430
3431 /* DCO enable for 10M IDLE Power */
3432 rtl_writephy(tp, 0x1f, 0x0007);
3433 rtl_writephy(tp, 0x1e, 0x0023);
76564428 3434 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
01dc7fec 3435 rtl_writephy(tp, 0x1f, 0x0000);
3436
3437 /* For impedance matching */
3438 rtl_writephy(tp, 0x1f, 0x0002);
76564428 3439 rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
cecb5fd7 3440 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3441
3442 /* PHY auto speed down */
3443 rtl_writephy(tp, 0x1f, 0x0007);
3444 rtl_writephy(tp, 0x1e, 0x002d);
76564428 3445 rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
01dc7fec 3446 rtl_writephy(tp, 0x1f, 0x0000);
76564428 3447 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
01dc7fec 3448
3449 rtl_writephy(tp, 0x1f, 0x0005);
3450 rtl_writephy(tp, 0x05, 0x8b86);
76564428 3451 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
01dc7fec 3452 rtl_writephy(tp, 0x1f, 0x0000);
3453
3454 rtl_writephy(tp, 0x1f, 0x0005);
3455 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3456 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
01dc7fec 3457 rtl_writephy(tp, 0x1f, 0x0007);
3458 rtl_writephy(tp, 0x1e, 0x0020);
76564428 3459 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
01dc7fec 3460 rtl_writephy(tp, 0x1f, 0x0006);
3461 rtl_writephy(tp, 0x00, 0x5a00);
3462 rtl_writephy(tp, 0x1f, 0x0000);
3463 rtl_writephy(tp, 0x0d, 0x0007);
3464 rtl_writephy(tp, 0x0e, 0x003c);
3465 rtl_writephy(tp, 0x0d, 0x4007);
3466 rtl_writephy(tp, 0x0e, 0x0000);
3467 rtl_writephy(tp, 0x0d, 0x0000);
3468}
3469
9ecb9aab 3470static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3471{
3472 const u16 w[] = {
3473 addr[0] | (addr[1] << 8),
3474 addr[2] | (addr[3] << 8),
3475 addr[4] | (addr[5] << 8)
3476 };
3477 const struct exgmac_reg e[] = {
3478 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3479 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3480 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3481 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3482 };
3483
3484 rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3485}
3486
70090424
HW		 3487static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3488{
3489 static const struct phy_reg phy_reg_init[] = {
3490 /* Enable Delay cap */
3491 { 0x1f, 0x0004 },
3492 { 0x1f, 0x0007 },
3493 { 0x1e, 0x00ac },
3494 { 0x18, 0x0006 },
3495 { 0x1f, 0x0002 },
3496 { 0x1f, 0x0000 },
3497 { 0x1f, 0x0000 },
3498
3499 /* Channel estimation fine tune */
3500 { 0x1f, 0x0003 },
3501 { 0x09, 0xa20f },
3502 { 0x1f, 0x0000 },
3503 { 0x1f, 0x0000 },
3504
3505 /* Green Setting */
3506 { 0x1f, 0x0005 },
3507 { 0x05, 0x8b5b },
3508 { 0x06, 0x9222 },
3509 { 0x05, 0x8b6d },
3510 { 0x06, 0x8000 },
3511 { 0x05, 0x8b76 },
3512 { 0x06, 0x8000 },
3513 { 0x1f, 0x0000 }
3514 };
3515
3516 rtl_apply_firmware(tp);
3517
3518 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3519
3520 /* For 4-corner performance improve */
3521 rtl_writephy(tp, 0x1f, 0x0005);
3522 rtl_writephy(tp, 0x05, 0x8b80);
76564428 3523 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
70090424
HW		 3524 rtl_writephy(tp, 0x1f, 0x0000);
3525
3526 /* PHY auto speed down */
3527 rtl_writephy(tp, 0x1f, 0x0004);
3528 rtl_writephy(tp, 0x1f, 0x0007);
3529 rtl_writephy(tp, 0x1e, 0x002d);
76564428 3530 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
70090424
HW		 3531 rtl_writephy(tp, 0x1f, 0x0002);
3532 rtl_writephy(tp, 0x1f, 0x0000);
76564428 3533 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
70090424
HW		 3534
3535 /* improve 10M EEE waveform */
3536 rtl_writephy(tp, 0x1f, 0x0005);
3537 rtl_writephy(tp, 0x05, 0x8b86);
76564428 3538 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
70090424
HW		 3539 rtl_writephy(tp, 0x1f, 0x0000);
3540
3541 /* Improve 2-pair detection performance */
3542 rtl_writephy(tp, 0x1f, 0x0005);
3543 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3544 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
70090424
HW		 3545 rtl_writephy(tp, 0x1f, 0x0000);
3546
3547 /* EEE setting */
706123d0 3548 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, ERIAR_EXGMAC);
70090424
HW		 3549 rtl_writephy(tp, 0x1f, 0x0005);
3550 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3551 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
70090424
HW		 3552 rtl_writephy(tp, 0x1f, 0x0004);
3553 rtl_writephy(tp, 0x1f, 0x0007);
3554 rtl_writephy(tp, 0x1e, 0x0020);
76564428 3555 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
70090424
HW		 3556 rtl_writephy(tp, 0x1f, 0x0002);
3557 rtl_writephy(tp, 0x1f, 0x0000);
3558 rtl_writephy(tp, 0x0d, 0x0007);
3559 rtl_writephy(tp, 0x0e, 0x003c);
3560 rtl_writephy(tp, 0x0d, 0x4007);
3561 rtl_writephy(tp, 0x0e, 0x0000);
3562 rtl_writephy(tp, 0x0d, 0x0000);
3563
3564 /* Green feature */
3565 rtl_writephy(tp, 0x1f, 0x0003);
76564428
CHL		 3566 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3567 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
70090424 3568 rtl_writephy(tp, 0x1f, 0x0000);
e0c07557 3569
9ecb9aab 3570 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3571 rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
70090424
HW		 3572}
3573
5f886e08
HW		 3574static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3575{
3576 /* For 4-corner performance improve */
3577 rtl_writephy(tp, 0x1f, 0x0005);
3578 rtl_writephy(tp, 0x05, 0x8b80);
76564428 3579 rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
5f886e08
HW		 3580 rtl_writephy(tp, 0x1f, 0x0000);
3581
3582 /* PHY auto speed down */
3583 rtl_writephy(tp, 0x1f, 0x0007);
3584 rtl_writephy(tp, 0x1e, 0x002d);
76564428 3585 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
5f886e08 3586 rtl_writephy(tp, 0x1f, 0x0000);
76564428 3587 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
5f886e08
HW		 3588
3589 /* Improve 10M EEE waveform */
3590 rtl_writephy(tp, 0x1f, 0x0005);
3591 rtl_writephy(tp, 0x05, 0x8b86);
76564428 3592 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
5f886e08
HW		 3593 rtl_writephy(tp, 0x1f, 0x0000);
3594}
3595
c2218925
HW		 3596static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3597{
3598 static const struct phy_reg phy_reg_init[] = {
3599 /* Channel estimation fine tune */
3600 { 0x1f, 0x0003 },
3601 { 0x09, 0xa20f },
3602 { 0x1f, 0x0000 },
3603
3604 /* Modify green table for giga & fnet */
3605 { 0x1f, 0x0005 },
3606 { 0x05, 0x8b55 },
3607 { 0x06, 0x0000 },
3608 { 0x05, 0x8b5e },
3609 { 0x06, 0x0000 },
3610 { 0x05, 0x8b67 },
3611 { 0x06, 0x0000 },
3612 { 0x05, 0x8b70 },
3613 { 0x06, 0x0000 },
3614 { 0x1f, 0x0000 },
3615 { 0x1f, 0x0007 },
3616 { 0x1e, 0x0078 },
3617 { 0x17, 0x0000 },
3618 { 0x19, 0x00fb },
3619 { 0x1f, 0x0000 },
3620
3621 /* Modify green table for 10M */
3622 { 0x1f, 0x0005 },
3623 { 0x05, 0x8b79 },
3624 { 0x06, 0xaa00 },
3625 { 0x1f, 0x0000 },
3626
3627 /* Disable hiimpedance detection (RTCT) */
3628 { 0x1f, 0x0003 },
3629 { 0x01, 0x328a },
3630 { 0x1f, 0x0000 }
3631 };
3632
3633 rtl_apply_firmware(tp);
3634
3635 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3636
5f886e08 3637 rtl8168f_hw_phy_config(tp);
c2218925
HW		 3638
3639 /* Improve 2-pair detection performance */
3640 rtl_writephy(tp, 0x1f, 0x0005);
3641 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3642 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
c2218925
HW		 3643 rtl_writephy(tp, 0x1f, 0x0000);
3644}
3645
3646static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3647{
3648 rtl_apply_firmware(tp);
3649
5f886e08 3650 rtl8168f_hw_phy_config(tp);
c2218925
HW		 3651}
3652
b3d7b2f2
HW		 3653static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3654{
b3d7b2f2
HW		 3655 static const struct phy_reg phy_reg_init[] = {
3656 /* Channel estimation fine tune */
3657 { 0x1f, 0x0003 },
3658 { 0x09, 0xa20f },
3659 { 0x1f, 0x0000 },
3660
3661 /* Modify green table for giga & fnet */
3662 { 0x1f, 0x0005 },
3663 { 0x05, 0x8b55 },
3664 { 0x06, 0x0000 },
3665 { 0x05, 0x8b5e },
3666 { 0x06, 0x0000 },
3667 { 0x05, 0x8b67 },
3668 { 0x06, 0x0000 },
3669 { 0x05, 0x8b70 },
3670 { 0x06, 0x0000 },
3671 { 0x1f, 0x0000 },
3672 { 0x1f, 0x0007 },
3673 { 0x1e, 0x0078 },
3674 { 0x17, 0x0000 },
3675 { 0x19, 0x00aa },
3676 { 0x1f, 0x0000 },
3677
3678 /* Modify green table for 10M */
3679 { 0x1f, 0x0005 },
3680 { 0x05, 0x8b79 },
3681 { 0x06, 0xaa00 },
3682 { 0x1f, 0x0000 },
3683
3684 /* Disable hiimpedance detection (RTCT) */
3685 { 0x1f, 0x0003 },
3686 { 0x01, 0x328a },
3687 { 0x1f, 0x0000 }
3688 };
3689
3690
3691 rtl_apply_firmware(tp);
3692
3693 rtl8168f_hw_phy_config(tp);
3694
3695 /* Improve 2-pair detection performance */
3696 rtl_writephy(tp, 0x1f, 0x0005);
3697 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3698 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
b3d7b2f2
HW		 3699 rtl_writephy(tp, 0x1f, 0x0000);
3700
3701 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3702
3703 /* Modify green table for giga */
3704 rtl_writephy(tp, 0x1f, 0x0005);
3705 rtl_writephy(tp, 0x05, 0x8b54);
76564428 3706 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
b3d7b2f2 3707 rtl_writephy(tp, 0x05, 0x8b5d);
76564428 3708 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
b3d7b2f2 3709 rtl_writephy(tp, 0x05, 0x8a7c);
76564428 3710 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2 3711 rtl_writephy(tp, 0x05, 0x8a7f);
76564428 3712 rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
b3d7b2f2 3713 rtl_writephy(tp, 0x05, 0x8a82);
76564428 3714 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2 3715 rtl_writephy(tp, 0x05, 0x8a85);
76564428 3716 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2 3717 rtl_writephy(tp, 0x05, 0x8a88);
76564428 3718 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2
HW		 3719 rtl_writephy(tp, 0x1f, 0x0000);
3720
3721 /* uc same-seed solution */
3722 rtl_writephy(tp, 0x1f, 0x0005);
3723 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3724 rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
b3d7b2f2
HW		 3725 rtl_writephy(tp, 0x1f, 0x0000);
3726
3727 /* eee setting */
706123d0 3728 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
b3d7b2f2
HW		 3729 rtl_writephy(tp, 0x1f, 0x0005);
3730 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3731 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
b3d7b2f2
HW		 3732 rtl_writephy(tp, 0x1f, 0x0004);
3733 rtl_writephy(tp, 0x1f, 0x0007);
3734 rtl_writephy(tp, 0x1e, 0x0020);
76564428 3735 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
b3d7b2f2
HW		 3736 rtl_writephy(tp, 0x1f, 0x0000);
3737 rtl_writephy(tp, 0x0d, 0x0007);
3738 rtl_writephy(tp, 0x0e, 0x003c);
3739 rtl_writephy(tp, 0x0d, 0x4007);
3740 rtl_writephy(tp, 0x0e, 0x0000);
3741 rtl_writephy(tp, 0x0d, 0x0000);
3742
3743 /* Green feature */
3744 rtl_writephy(tp, 0x1f, 0x0003);
76564428
CHL		 3745 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3746 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
b3d7b2f2
HW		 3747 rtl_writephy(tp, 0x1f, 0x0000);
3748}
3749
c558386b
HW		 3750static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3751{
c558386b
HW		 3752 rtl_apply_firmware(tp);
3753
41f44d13 3754 rtl_writephy(tp, 0x1f, 0x0a46);
3755 if (rtl_readphy(tp, 0x10) & 0x0100) {
3756 rtl_writephy(tp, 0x1f, 0x0bcc);
76564428 3757 rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
41f44d13 3758 } else {
3759 rtl_writephy(tp, 0x1f, 0x0bcc);
76564428 3760 rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
41f44d13 3761 }
c558386b 3762
41f44d13 3763 rtl_writephy(tp, 0x1f, 0x0a46);
3764 if (rtl_readphy(tp, 0x13) & 0x0100) {
3765 rtl_writephy(tp, 0x1f, 0x0c41);
76564428 3766 rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
41f44d13 3767 } else {
fe7524c0 3768 rtl_writephy(tp, 0x1f, 0x0c41);
76564428 3769 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
41f44d13 3770 }
c558386b 3771
41f44d13 3772 /* Enable PHY auto speed down */
3773 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 3774 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
c558386b 3775
fe7524c0 3776 rtl_writephy(tp, 0x1f, 0x0bcc);
76564428 3777 rtl_w0w1_phy(tp, 0x14, 0x0100, 0x0000);
fe7524c0 3778 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 3779 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
fe7524c0 3780 rtl_writephy(tp, 0x1f, 0x0a43);
3781 rtl_writephy(tp, 0x13, 0x8084);
76564428
CHL		 3782 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3783 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
fe7524c0 3784
41f44d13 3785 /* EEE auto-fallback function */
3786 rtl_writephy(tp, 0x1f, 0x0a4b);
76564428 3787 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
c558386b 3788
41f44d13 3789 /* Enable UC LPF tune function */
3790 rtl_writephy(tp, 0x1f, 0x0a43);
3791 rtl_writephy(tp, 0x13, 0x8012);
76564428 3792 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
41f44d13 3793
3794 rtl_writephy(tp, 0x1f, 0x0c42);
76564428 3795 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
41f44d13 3796
fe7524c0 3797 /* Improve SWR Efficiency */
3798 rtl_writephy(tp, 0x1f, 0x0bcd);
3799 rtl_writephy(tp, 0x14, 0x5065);
3800 rtl_writephy(tp, 0x14, 0xd065);
3801 rtl_writephy(tp, 0x1f, 0x0bc8);
3802 rtl_writephy(tp, 0x11, 0x5655);
3803 rtl_writephy(tp, 0x1f, 0x0bcd);
3804 rtl_writephy(tp, 0x14, 0x1065);
3805 rtl_writephy(tp, 0x14, 0x9065);
3806 rtl_writephy(tp, 0x14, 0x1065);
3807
1bac1072
DC		 3808 /* Check ALDPS bit, disable it if enabled */
3809 rtl_writephy(tp, 0x1f, 0x0a43);
3810 if (rtl_readphy(tp, 0x10) & 0x0004)
76564428 3811 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
1bac1072 3812
41f44d13 3813 rtl_writephy(tp, 0x1f, 0x0000);
c558386b
HW		 3814}
3815
57538c4a 3816static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3817{
3818 rtl_apply_firmware(tp);
3819}
3820
6e1d0b89
CHL		 3821static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3822{
3823 u16 dout_tapbin;
3824 u32 data;
3825
3826 rtl_apply_firmware(tp);
3827
3828 /* CHN EST parameters adjust - giga master */
3829 rtl_writephy(tp, 0x1f, 0x0a43);
3830 rtl_writephy(tp, 0x13, 0x809b);
76564428 3831 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
6e1d0b89 3832 rtl_writephy(tp, 0x13, 0x80a2);
76564428 3833 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
6e1d0b89 3834 rtl_writephy(tp, 0x13, 0x80a4);
76564428 3835 rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
6e1d0b89 3836 rtl_writephy(tp, 0x13, 0x809c);
76564428 3837 rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
6e1d0b89
CHL		 3838 rtl_writephy(tp, 0x1f, 0x0000);
3839
3840 /* CHN EST parameters adjust - giga slave */
3841 rtl_writephy(tp, 0x1f, 0x0a43);
3842 rtl_writephy(tp, 0x13, 0x80ad);
76564428 3843 rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
6e1d0b89 3844 rtl_writephy(tp, 0x13, 0x80b4);
76564428 3845 rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
6e1d0b89 3846 rtl_writephy(tp, 0x13, 0x80ac);
76564428 3847 rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
6e1d0b89
CHL		 3848 rtl_writephy(tp, 0x1f, 0x0000);
3849
3850 /* CHN EST parameters adjust - fnet */
3851 rtl_writephy(tp, 0x1f, 0x0a43);
3852 rtl_writephy(tp, 0x13, 0x808e);
76564428 3853 rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
6e1d0b89 3854 rtl_writephy(tp, 0x13, 0x8090);
76564428 3855 rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
6e1d0b89 3856 rtl_writephy(tp, 0x13, 0x8092);
76564428 3857 rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
6e1d0b89
CHL		 3858 rtl_writephy(tp, 0x1f, 0x0000);
3859
3860 /* enable R-tune & PGA-retune function */
3861 dout_tapbin = 0;
3862 rtl_writephy(tp, 0x1f, 0x0a46);
3863 data = rtl_readphy(tp, 0x13);
3864 data &= 3;
3865 data <<= 2;
3866 dout_tapbin |= data;
3867 data = rtl_readphy(tp, 0x12);
3868 data &= 0xc000;
3869 data >>= 14;
3870 dout_tapbin |= data;
3871 dout_tapbin = ~(dout_tapbin^0x08);
3872 dout_tapbin <<= 12;
3873 dout_tapbin &= 0xf000;
3874 rtl_writephy(tp, 0x1f, 0x0a43);
3875 rtl_writephy(tp, 0x13, 0x827a);
76564428 3876 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
6e1d0b89 3877 rtl_writephy(tp, 0x13, 0x827b);
76564428 3878 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
6e1d0b89 3879 rtl_writephy(tp, 0x13, 0x827c);
76564428 3880 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
6e1d0b89 3881 rtl_writephy(tp, 0x13, 0x827d);
76564428 3882 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
6e1d0b89
CHL		 3883
3884 rtl_writephy(tp, 0x1f, 0x0a43);
3885 rtl_writephy(tp, 0x13, 0x0811);
76564428 3886 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
6e1d0b89 3887 rtl_writephy(tp, 0x1f, 0x0a42);
76564428 3888 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
6e1d0b89
CHL		 3889 rtl_writephy(tp, 0x1f, 0x0000);
3890
3891 /* enable GPHY 10M */
3892 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 3893 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
6e1d0b89
CHL		 3894 rtl_writephy(tp, 0x1f, 0x0000);
3895
3896 /* SAR ADC performance */
3897 rtl_writephy(tp, 0x1f, 0x0bca);
76564428 3898 rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
6e1d0b89
CHL		 3899 rtl_writephy(tp, 0x1f, 0x0000);
3900
3901 rtl_writephy(tp, 0x1f, 0x0a43);
3902 rtl_writephy(tp, 0x13, 0x803f);
76564428 3903 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3904 rtl_writephy(tp, 0x13, 0x8047);
76564428 3905 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3906 rtl_writephy(tp, 0x13, 0x804f);
76564428 3907 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3908 rtl_writephy(tp, 0x13, 0x8057);
76564428 3909 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3910 rtl_writephy(tp, 0x13, 0x805f);
76564428 3911 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3912 rtl_writephy(tp, 0x13, 0x8067);
76564428 3913 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3914 rtl_writephy(tp, 0x13, 0x806f);
76564428 3915 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89
CHL		 3916 rtl_writephy(tp, 0x1f, 0x0000);
3917
3918 /* disable phy pfm mode */
3919 rtl_writephy(tp, 0x1f, 0x0a44);
c832c35f 3920 rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
6e1d0b89
CHL		 3921 rtl_writephy(tp, 0x1f, 0x0000);
3922
3923 /* Check ALDPS bit, disable it if enabled */
3924 rtl_writephy(tp, 0x1f, 0x0a43);
3925 if (rtl_readphy(tp, 0x10) & 0x0004)
76564428 3926 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
6e1d0b89
CHL		 3927
3928 rtl_writephy(tp, 0x1f, 0x0000);
3929}
3930
3931static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3932{
3933 u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3934 u16 rlen;
3935 u32 data;
3936
3937 rtl_apply_firmware(tp);
3938
3939 /* CHIN EST parameter update */
3940 rtl_writephy(tp, 0x1f, 0x0a43);
3941 rtl_writephy(tp, 0x13, 0x808a);
76564428 3942 rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
6e1d0b89
CHL		 3943 rtl_writephy(tp, 0x1f, 0x0000);
3944
3945 /* enable R-tune & PGA-retune function */
3946 rtl_writephy(tp, 0x1f, 0x0a43);
3947 rtl_writephy(tp, 0x13, 0x0811);
76564428 3948 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
6e1d0b89 3949 rtl_writephy(tp, 0x1f, 0x0a42);
76564428 3950 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
6e1d0b89
CHL		 3951 rtl_writephy(tp, 0x1f, 0x0000);
3952
3953 /* enable GPHY 10M */
3954 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 3955 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
6e1d0b89
CHL		 3956 rtl_writephy(tp, 0x1f, 0x0000);
3957
3958 r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3959 data = r8168_mac_ocp_read(tp, 0xdd02);
3960 ioffset_p3 = ((data & 0x80)>>7);
3961 ioffset_p3 <<= 3;
3962
3963 data = r8168_mac_ocp_read(tp, 0xdd00);
3964 ioffset_p3 |= ((data & (0xe000))>>13);
3965 ioffset_p2 = ((data & (0x1e00))>>9);
3966 ioffset_p1 = ((data & (0x01e0))>>5);
3967 ioffset_p0 = ((data & 0x0010)>>4);
3968 ioffset_p0 <<= 3;
3969 ioffset_p0 |= (data & (0x07));
3970 data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3971
05b9687b 3972 if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
e2e2788e 3973 (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
6e1d0b89
CHL		 3974 rtl_writephy(tp, 0x1f, 0x0bcf);
3975 rtl_writephy(tp, 0x16, data);
3976 rtl_writephy(tp, 0x1f, 0x0000);
3977 }
3978
3979 /* Modify rlen (TX LPF corner frequency) level */
3980 rtl_writephy(tp, 0x1f, 0x0bcd);
3981 data = rtl_readphy(tp, 0x16);
3982 data &= 0x000f;
3983 rlen = 0;
3984 if (data > 3)
3985 rlen = data - 3;
3986 data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3987 rtl_writephy(tp, 0x17, data);
3988 rtl_writephy(tp, 0x1f, 0x0bcd);
3989 rtl_writephy(tp, 0x1f, 0x0000);
3990
3991 /* disable phy pfm mode */
3992 rtl_writephy(tp, 0x1f, 0x0a44);
c832c35f 3993 rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
6e1d0b89
CHL		 3994 rtl_writephy(tp, 0x1f, 0x0000);
3995
3996 /* Check ALDPS bit, disable it if enabled */
3997 rtl_writephy(tp, 0x1f, 0x0a43);
3998 if (rtl_readphy(tp, 0x10) & 0x0004)
76564428 3999 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
6e1d0b89
CHL		 4000
4001 rtl_writephy(tp, 0x1f, 0x0000);
4002}
4003
935e2218
CHL		 4004static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
4005{
4006 /* Enable PHY auto speed down */
4007 rtl_writephy(tp, 0x1f, 0x0a44);
4008 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
4009 rtl_writephy(tp, 0x1f, 0x0000);
4010
4011 /* patch 10M & ALDPS */
4012 rtl_writephy(tp, 0x1f, 0x0bcc);
4013 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
4014 rtl_writephy(tp, 0x1f, 0x0a44);
4015 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
4016 rtl_writephy(tp, 0x1f, 0x0a43);
4017 rtl_writephy(tp, 0x13, 0x8084);
4018 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
4019 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
4020 rtl_writephy(tp, 0x1f, 0x0000);
4021
4022 /* Enable EEE auto-fallback function */
4023 rtl_writephy(tp, 0x1f, 0x0a4b);
4024 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
4025 rtl_writephy(tp, 0x1f, 0x0000);
4026
4027 /* Enable UC LPF tune function */
4028 rtl_writephy(tp, 0x1f, 0x0a43);
4029 rtl_writephy(tp, 0x13, 0x8012);
4030 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
4031 rtl_writephy(tp, 0x1f, 0x0000);
4032
4033 /* set rg_sel_sdm_rate */
4034 rtl_writephy(tp, 0x1f, 0x0c42);
4035 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
4036 rtl_writephy(tp, 0x1f, 0x0000);
4037
4038 /* Check ALDPS bit, disable it if enabled */
4039 rtl_writephy(tp, 0x1f, 0x0a43);
4040 if (rtl_readphy(tp, 0x10) & 0x0004)
4041 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4042
4043 rtl_writephy(tp, 0x1f, 0x0000);
4044}
4045
4046static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
4047{
4048 /* patch 10M & ALDPS */
4049 rtl_writephy(tp, 0x1f, 0x0bcc);
4050 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
4051 rtl_writephy(tp, 0x1f, 0x0a44);
4052 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
4053 rtl_writephy(tp, 0x1f, 0x0a43);
4054 rtl_writephy(tp, 0x13, 0x8084);
4055 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
4056 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
4057 rtl_writephy(tp, 0x1f, 0x0000);
4058
4059 /* Enable UC LPF tune function */
4060 rtl_writephy(tp, 0x1f, 0x0a43);
4061 rtl_writephy(tp, 0x13, 0x8012);
4062 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
4063 rtl_writephy(tp, 0x1f, 0x0000);
4064
4065 /* Set rg_sel_sdm_rate */
4066 rtl_writephy(tp, 0x1f, 0x0c42);
4067 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
4068 rtl_writephy(tp, 0x1f, 0x0000);
4069
4070 /* Channel estimation parameters */
4071 rtl_writephy(tp, 0x1f, 0x0a43);
4072 rtl_writephy(tp, 0x13, 0x80f3);
4073 rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
4074 rtl_writephy(tp, 0x13, 0x80f0);
4075 rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
4076 rtl_writephy(tp, 0x13, 0x80ef);
4077 rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
4078 rtl_writephy(tp, 0x13, 0x80f6);
4079 rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
4080 rtl_writephy(tp, 0x13, 0x80ec);
4081 rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
4082 rtl_writephy(tp, 0x13, 0x80ed);
4083 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
4084 rtl_writephy(tp, 0x13, 0x80f2);
4085 rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
4086 rtl_writephy(tp, 0x13, 0x80f4);
4087 rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
4088 rtl_writephy(tp, 0x1f, 0x0a43);
4089 rtl_writephy(tp, 0x13, 0x8110);
4090 rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
4091 rtl_writephy(tp, 0x13, 0x810f);
4092 rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
4093 rtl_writephy(tp, 0x13, 0x8111);
4094 rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
4095 rtl_writephy(tp, 0x13, 0x8113);
4096 rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
4097 rtl_writephy(tp, 0x13, 0x8115);
4098 rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
4099 rtl_writephy(tp, 0x13, 0x810e);
4100 rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
4101 rtl_writephy(tp, 0x13, 0x810c);
4102 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
4103 rtl_writephy(tp, 0x13, 0x810b);
4104 rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
4105 rtl_writephy(tp, 0x1f, 0x0a43);
4106 rtl_writephy(tp, 0x13, 0x80d1);
4107 rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
4108 rtl_writephy(tp, 0x13, 0x80cd);
4109 rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
4110 rtl_writephy(tp, 0x13, 0x80d3);
4111 rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
4112 rtl_writephy(tp, 0x13, 0x80d5);
4113 rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
4114 rtl_writephy(tp, 0x13, 0x80d7);
4115 rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
4116
4117 /* Force PWM-mode */
4118 rtl_writephy(tp, 0x1f, 0x0bcd);
4119 rtl_writephy(tp, 0x14, 0x5065);
4120 rtl_writephy(tp, 0x14, 0xd065);
4121 rtl_writephy(tp, 0x1f, 0x0bc8);
4122 rtl_writephy(tp, 0x12, 0x00ed);
4123 rtl_writephy(tp, 0x1f, 0x0bcd);
4124 rtl_writephy(tp, 0x14, 0x1065);
4125 rtl_writephy(tp, 0x14, 0x9065);
4126 rtl_writephy(tp, 0x14, 0x1065);
4127 rtl_writephy(tp, 0x1f, 0x0000);
4128
4129 /* Check ALDPS bit, disable it if enabled */
4130 rtl_writephy(tp, 0x1f, 0x0a43);
4131 if (rtl_readphy(tp, 0x10) & 0x0004)
4132 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4133
4134 rtl_writephy(tp, 0x1f, 0x0000);
4135}
4136
4da19633 4137static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2857ffb7 4138{
350f7596 4139 static const struct phy_reg phy_reg_init[] = {
2857ffb7
FR		 4140 { 0x1f, 0x0003 },
4141 { 0x08, 0x441d },
4142 { 0x01, 0x9100 },
4143 { 0x1f, 0x0000 }
4144 };
4145
4da19633 4146 rtl_writephy(tp, 0x1f, 0x0000);
4147 rtl_patchphy(tp, 0x11, 1 << 12);
4148 rtl_patchphy(tp, 0x19, 1 << 13);
4149 rtl_patchphy(tp, 0x10, 1 << 15);
2857ffb7 4150
4da19633 4151 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2857ffb7
FR		 4152}
4153
5a5e4443
HW		 4154static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
4155{
4156 static const struct phy_reg phy_reg_init[] = {
4157 { 0x1f, 0x0005 },
4158 { 0x1a, 0x0000 },
4159 { 0x1f, 0x0000 },
4160
4161 { 0x1f, 0x0004 },
4162 { 0x1c, 0x0000 },
4163 { 0x1f, 0x0000 },
4164
4165 { 0x1f, 0x0001 },
4166 { 0x15, 0x7701 },
4167 { 0x1f, 0x0000 }
4168 };
4169
4170 /* Disable ALDPS before ram code */
eef63cc1
FR		 4171 rtl_writephy(tp, 0x1f, 0x0000);
4172 rtl_writephy(tp, 0x18, 0x0310);
4173 msleep(100);
5a5e4443 4174
953a12cc 4175 rtl_apply_firmware(tp);
5a5e4443
HW		 4176
4177 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4178}
4179
7e18dca1
HW		 4180static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
4181{
7e18dca1 4182 /* Disable ALDPS before setting firmware */
eef63cc1
FR		 4183 rtl_writephy(tp, 0x1f, 0x0000);
4184 rtl_writephy(tp, 0x18, 0x0310);
4185 msleep(20);
7e18dca1
HW		 4186
4187 rtl_apply_firmware(tp);
4188
4189 /* EEE setting */
fdf6fc06 4190 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
7e18dca1
HW		 4191 rtl_writephy(tp, 0x1f, 0x0004);
4192 rtl_writephy(tp, 0x10, 0x401f);
4193 rtl_writephy(tp, 0x19, 0x7030);
4194 rtl_writephy(tp, 0x1f, 0x0000);
4195}
4196
5598bfe5
HW		 4197static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
4198{
5598bfe5
HW		 4199 static const struct phy_reg phy_reg_init[] = {
4200 { 0x1f, 0x0004 },
4201 { 0x10, 0xc07f },
4202 { 0x19, 0x7030 },
4203 { 0x1f, 0x0000 }
4204 };
4205
4206 /* Disable ALDPS before ram code */
eef63cc1
FR		 4207 rtl_writephy(tp, 0x1f, 0x0000);
4208 rtl_writephy(tp, 0x18, 0x0310);
4209 msleep(100);
5598bfe5
HW		 4210
4211 rtl_apply_firmware(tp);
4212
fdf6fc06 4213 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5598bfe5
HW		 4214 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4215
fdf6fc06 4216 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5598bfe5
HW		 4217}
4218
5615d9f1
FR		 4219static void rtl_hw_phy_config(struct net_device *dev)
4220{
4221 struct rtl8169_private *tp = netdev_priv(dev);
5615d9f1
FR		 4222
4223 rtl8169_print_mac_version(tp);
4224
4225 switch (tp->mac_version) {
4226 case RTL_GIGA_MAC_VER_01:
4227 break;
4228 case RTL_GIGA_MAC_VER_02:
4229 case RTL_GIGA_MAC_VER_03:
4da19633 4230 rtl8169s_hw_phy_config(tp);
5615d9f1
FR		 4231 break;
4232 case RTL_GIGA_MAC_VER_04:
4da19633 4233 rtl8169sb_hw_phy_config(tp);
5615d9f1 4234 break;
2e955856 4235 case RTL_GIGA_MAC_VER_05:
4da19633 4236 rtl8169scd_hw_phy_config(tp);
2e955856 4237 break;
8c7006aa 4238 case RTL_GIGA_MAC_VER_06:
4da19633 4239 rtl8169sce_hw_phy_config(tp);
8c7006aa 4240 break;
2857ffb7
FR		 4241 case RTL_GIGA_MAC_VER_07:
4242 case RTL_GIGA_MAC_VER_08:
4243 case RTL_GIGA_MAC_VER_09:
4da19633 4244 rtl8102e_hw_phy_config(tp);
2857ffb7 4245 break;
236b8082 4246 case RTL_GIGA_MAC_VER_11:
4da19633 4247 rtl8168bb_hw_phy_config(tp);
236b8082
FR		 4248 break;
4249 case RTL_GIGA_MAC_VER_12:
4da19633 4250 rtl8168bef_hw_phy_config(tp);
236b8082
FR		 4251 break;
4252 case RTL_GIGA_MAC_VER_17:
4da19633 4253 rtl8168bef_hw_phy_config(tp);
236b8082 4254 break;
867763c1 4255 case RTL_GIGA_MAC_VER_18:
4da19633 4256 rtl8168cp_1_hw_phy_config(tp);
867763c1
FR		 4257 break;
4258 case RTL_GIGA_MAC_VER_19:
4da19633 4259 rtl8168c_1_hw_phy_config(tp);
867763c1 4260 break;
7da97ec9 4261 case RTL_GIGA_MAC_VER_20:
4da19633 4262 rtl8168c_2_hw_phy_config(tp);
7da97ec9 4263 break;
197ff761 4264 case RTL_GIGA_MAC_VER_21:
4da19633 4265 rtl8168c_3_hw_phy_config(tp);
197ff761 4266 break;
6fb07058 4267 case RTL_GIGA_MAC_VER_22:
4da19633 4268 rtl8168c_4_hw_phy_config(tp);
6fb07058 4269 break;
ef3386f0 4270 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 4271 case RTL_GIGA_MAC_VER_24:
4da19633 4272 rtl8168cp_2_hw_phy_config(tp);
ef3386f0 4273 break;
5b538df9 4274 case RTL_GIGA_MAC_VER_25:
bca03d5f 4275 rtl8168d_1_hw_phy_config(tp);
daf9df6d 4276 break;
4277 case RTL_GIGA_MAC_VER_26:
bca03d5f 4278 rtl8168d_2_hw_phy_config(tp);
daf9df6d 4279 break;
4280 case RTL_GIGA_MAC_VER_27:
4da19633 4281 rtl8168d_3_hw_phy_config(tp);
5b538df9 4282 break;
e6de30d6 4283 case RTL_GIGA_MAC_VER_28:
4284 rtl8168d_4_hw_phy_config(tp);
4285 break;
5a5e4443
HW		 4286 case RTL_GIGA_MAC_VER_29:
4287 case RTL_GIGA_MAC_VER_30:
4288 rtl8105e_hw_phy_config(tp);
4289 break;
cecb5fd7
FR		 4290 case RTL_GIGA_MAC_VER_31:
4291 /* None. */
4292 break;
01dc7fec 4293 case RTL_GIGA_MAC_VER_32:
01dc7fec 4294 case RTL_GIGA_MAC_VER_33:
70090424
HW		 4295 rtl8168e_1_hw_phy_config(tp);
4296 break;
4297 case RTL_GIGA_MAC_VER_34:
4298 rtl8168e_2_hw_phy_config(tp);
01dc7fec 4299 break;
c2218925
HW		 4300 case RTL_GIGA_MAC_VER_35:
4301 rtl8168f_1_hw_phy_config(tp);
4302 break;
4303 case RTL_GIGA_MAC_VER_36:
4304 rtl8168f_2_hw_phy_config(tp);
4305 break;
ef3386f0 4306
7e18dca1
HW		 4307 case RTL_GIGA_MAC_VER_37:
4308 rtl8402_hw_phy_config(tp);
4309 break;
4310
b3d7b2f2
HW		 4311 case RTL_GIGA_MAC_VER_38:
4312 rtl8411_hw_phy_config(tp);
4313 break;
4314
5598bfe5
HW		 4315 case RTL_GIGA_MAC_VER_39:
4316 rtl8106e_hw_phy_config(tp);
4317 break;
4318
c558386b
HW		 4319 case RTL_GIGA_MAC_VER_40:
4320 rtl8168g_1_hw_phy_config(tp);
4321 break;
57538c4a 4322 case RTL_GIGA_MAC_VER_42:
58152cd4 4323 case RTL_GIGA_MAC_VER_43:
45dd95c4 4324 case RTL_GIGA_MAC_VER_44:
57538c4a 4325 rtl8168g_2_hw_phy_config(tp);
4326 break;
6e1d0b89
CHL		 4327 case RTL_GIGA_MAC_VER_45:
4328 case RTL_GIGA_MAC_VER_47:
4329 rtl8168h_1_hw_phy_config(tp);
4330 break;
4331 case RTL_GIGA_MAC_VER_46:
4332 case RTL_GIGA_MAC_VER_48:
4333 rtl8168h_2_hw_phy_config(tp);
4334 break;
c558386b 4335
935e2218
CHL		 4336 case RTL_GIGA_MAC_VER_49:
4337 rtl8168ep_1_hw_phy_config(tp);
4338 break;
4339 case RTL_GIGA_MAC_VER_50:
4340 case RTL_GIGA_MAC_VER_51:
4341 rtl8168ep_2_hw_phy_config(tp);
4342 break;
4343
c558386b 4344 case RTL_GIGA_MAC_VER_41:
5615d9f1
FR		 4345 default:
4346 break;
4347 }
4348}
4349
da78dbff 4350static void rtl_phy_work(struct rtl8169_private *tp)
1da177e4 4351{
1da177e4
LT		 4352 struct timer_list *timer = &tp->timer;
4353 void __iomem *ioaddr = tp->mmio_addr;
4354 unsigned long timeout = RTL8169_PHY_TIMEOUT;
4355
bcf0bf90 4356 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 4357
4da19633 4358 if (tp->phy_reset_pending(tp)) {
5b0384f4 4359 /*
1da177e4
LT		 4360 * A busy loop could burn quite a few cycles on nowadays CPU.
4361 * Let's delay the execution of the timer for a few ticks.
4362 */
4363 timeout = HZ/10;
4364 goto out_mod_timer;
4365 }
4366
4367 if (tp->link_ok(ioaddr))
da78dbff 4368 return;
1da177e4 4369
9bb8eeb5 4370 netif_dbg(tp, link, tp->dev, "PHY reset until link up\n");
1da177e4 4371
4da19633 4372 tp->phy_reset_enable(tp);
1da177e4
LT		 4373
4374out_mod_timer:
4375 mod_timer(timer, jiffies + timeout);
da78dbff
FR		 4376}
4377
4378static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
4379{
da78dbff
FR		 4380 if (!test_and_set_bit(flag, tp->wk.flags))
4381 schedule_work(&tp->wk.work);
da78dbff
FR		 4382}
4383
4384static void rtl8169_phy_timer(unsigned long __opaque)
4385{
4386 struct net_device *dev = (struct net_device *)__opaque;
4387 struct rtl8169_private *tp = netdev_priv(dev);
4388
98ddf986 4389 rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
1da177e4
LT		 4390}
4391
1da177e4
LT		 4392static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
4393 void __iomem *ioaddr)
4394{
4395 iounmap(ioaddr);
4396 pci_release_regions(pdev);
87aeec76 4397 pci_clear_mwi(pdev);
1da177e4
LT		 4398 pci_disable_device(pdev);
4399 free_netdev(dev);
4400}
4401
ffc46952
FR		 4402DECLARE_RTL_COND(rtl_phy_reset_cond)
4403{
4404 return tp->phy_reset_pending(tp);
4405}
4406
bf793295
FR		 4407static void rtl8169_phy_reset(struct net_device *dev,
4408 struct rtl8169_private *tp)
4409{
4da19633 4410 tp->phy_reset_enable(tp);
ffc46952 4411 rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100);
bf793295
FR		 4412}
4413
2544bfc0
FR		 4414static bool rtl_tbi_enabled(struct rtl8169_private *tp)
4415{
4416 void __iomem *ioaddr = tp->mmio_addr;
4417
4418 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
4419 (RTL_R8(PHYstatus) & TBI_Enable);
4420}
4421
4ff96fa6
FR		 4422static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
4423{
4424 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 4425
5615d9f1 4426 rtl_hw_phy_config(dev);
4ff96fa6 4427
77332894
MS		 4428 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
4429 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4430 RTL_W8(0x82, 0x01);
4431 }
4ff96fa6 4432
6dccd16b
FR		 4433 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
4434
4435 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
4436 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 4437
bcf0bf90 4438 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 4439 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4440 RTL_W8(0x82, 0x01);
4441 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4da19633 4442 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4ff96fa6
FR		 4443 }
4444
bf793295
FR		 4445 rtl8169_phy_reset(dev, tp);
4446
54405cde 4447 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
cecb5fd7
FR		 4448 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4449 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4450 (tp->mii.supports_gmii ?
4451 ADVERTISED_1000baseT_Half |
4452 ADVERTISED_1000baseT_Full : 0));
4ff96fa6 4453
2544bfc0 4454 if (rtl_tbi_enabled(tp))
bf82c189 4455 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4ff96fa6
FR		 4456}
4457
773d2021
FR		 4458static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4459{
4460 void __iomem *ioaddr = tp->mmio_addr;
773d2021 4461
da78dbff 4462 rtl_lock_work(tp);
773d2021
FR		 4463
4464 RTL_W8(Cfg9346, Cfg9346_Unlock);
908ba2bf 4465
9ecb9aab 4466 RTL_W32(MAC4, addr[4] | addr[5] << 8);
908ba2bf 4467 RTL_R32(MAC4);
4468
9ecb9aab 4469 RTL_W32(MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
908ba2bf 4470 RTL_R32(MAC0);
4471
9ecb9aab 4472 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4473 rtl_rar_exgmac_set(tp, addr);
c28aa385 4474
773d2021
FR		 4475 RTL_W8(Cfg9346, Cfg9346_Lock);
4476
da78dbff 4477 rtl_unlock_work(tp);
773d2021
FR		 4478}
4479
4480static int rtl_set_mac_address(struct net_device *dev, void *p)
4481{
4482 struct rtl8169_private *tp = netdev_priv(dev);
f51d4a10 4483 struct device *d = &tp->pci_dev->dev;
773d2021
FR		 4484 struct sockaddr *addr = p;
4485
4486 if (!is_valid_ether_addr(addr->sa_data))
4487 return -EADDRNOTAVAIL;
4488
4489 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
4490
f51d4a10
CHL		 4491 pm_runtime_get_noresume(d);
4492
4493 if (pm_runtime_active(d))
4494 rtl_rar_set(tp, dev->dev_addr);
4495
4496 pm_runtime_put_noidle(d);
773d2021
FR		 4497
4498 return 0;
4499}
4500
5f787a1a
FR		 4501static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4502{
4503 struct rtl8169_private *tp = netdev_priv(dev);
4504 struct mii_ioctl_data *data = if_mii(ifr);
4505
8b4ab28d
FR		 4506 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
4507}
5f787a1a 4508
cecb5fd7
FR		 4509static int rtl_xmii_ioctl(struct rtl8169_private *tp,
4510 struct mii_ioctl_data *data, int cmd)
8b4ab28d 4511{
5f787a1a
FR		 4512 switch (cmd) {
4513 case SIOCGMIIPHY:
4514 data->phy_id = 32; /* Internal PHY */
4515 return 0;
4516
4517 case SIOCGMIIREG:
4da19633 4518 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
5f787a1a
FR		 4519 return 0;
4520
4521 case SIOCSMIIREG:
4da19633 4522 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
5f787a1a
FR		 4523 return 0;
4524 }
4525 return -EOPNOTSUPP;
4526}
4527
8b4ab28d
FR		 4528static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
4529{
4530 return -EOPNOTSUPP;
4531}
4532
fbac58fc
FR		 4533static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
4534{
4535 if (tp->features & RTL_FEATURE_MSI) {
4536 pci_disable_msi(pdev);
4537 tp->features &= ~RTL_FEATURE_MSI;
4538 }
4539}
4540
baf63293 4541static void rtl_init_mdio_ops(struct rtl8169_private *tp)
c0e45c1c 4542{
4543 struct mdio_ops *ops = &tp->mdio_ops;
4544
4545 switch (tp->mac_version) {
4546 case RTL_GIGA_MAC_VER_27:
4547 ops->write = r8168dp_1_mdio_write;
4548 ops->read = r8168dp_1_mdio_read;
4549 break;
e6de30d6 4550 case RTL_GIGA_MAC_VER_28:
4804b3b3 4551 case RTL_GIGA_MAC_VER_31:
e6de30d6 4552 ops->write = r8168dp_2_mdio_write;
4553 ops->read = r8168dp_2_mdio_read;
4554 break;
c558386b
HW		 4555 case RTL_GIGA_MAC_VER_40:
4556 case RTL_GIGA_MAC_VER_41:
57538c4a 4557 case RTL_GIGA_MAC_VER_42:
58152cd4 4558 case RTL_GIGA_MAC_VER_43:
45dd95c4 4559 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4560 case RTL_GIGA_MAC_VER_45:
4561 case RTL_GIGA_MAC_VER_46:
4562 case RTL_GIGA_MAC_VER_47:
4563 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 4564 case RTL_GIGA_MAC_VER_49:
4565 case RTL_GIGA_MAC_VER_50:
4566 case RTL_GIGA_MAC_VER_51:
c558386b
HW		 4567 ops->write = r8168g_mdio_write;
4568 ops->read = r8168g_mdio_read;
4569 break;
c0e45c1c 4570 default:
4571 ops->write = r8169_mdio_write;
4572 ops->read = r8169_mdio_read;
4573 break;
4574 }
4575}
4576
e2409d83 4577static void rtl_speed_down(struct rtl8169_private *tp)
4578{
4579 u32 adv;
4580 int lpa;
4581
4582 rtl_writephy(tp, 0x1f, 0x0000);
4583 lpa = rtl_readphy(tp, MII_LPA);
4584
4585 if (lpa & (LPA_10HALF | LPA_10FULL))
4586 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
4587 else if (lpa & (LPA_100HALF | LPA_100FULL))
4588 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4589 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4590 else
4591 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4592 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4593 (tp->mii.supports_gmii ?
4594 ADVERTISED_1000baseT_Half |
4595 ADVERTISED_1000baseT_Full : 0);
4596
4597 rtl8169_set_speed(tp->dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
4598 adv);
4599}
4600
649b3b8c 4601static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4602{
4603 void __iomem *ioaddr = tp->mmio_addr;
4604
4605 switch (tp->mac_version) {
b00e69de
CB		 4606 case RTL_GIGA_MAC_VER_25:
4607 case RTL_GIGA_MAC_VER_26:
649b3b8c 4608 case RTL_GIGA_MAC_VER_29:
4609 case RTL_GIGA_MAC_VER_30:
4610 case RTL_GIGA_MAC_VER_32:
4611 case RTL_GIGA_MAC_VER_33:
4612 case RTL_GIGA_MAC_VER_34:
7e18dca1 4613 case RTL_GIGA_MAC_VER_37:
b3d7b2f2 4614 case RTL_GIGA_MAC_VER_38:
5598bfe5 4615 case RTL_GIGA_MAC_VER_39:
c558386b
HW		 4616 case RTL_GIGA_MAC_VER_40:
4617 case RTL_GIGA_MAC_VER_41:
57538c4a 4618 case RTL_GIGA_MAC_VER_42:
58152cd4 4619 case RTL_GIGA_MAC_VER_43:
45dd95c4 4620 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4621 case RTL_GIGA_MAC_VER_45:
4622 case RTL_GIGA_MAC_VER_46:
4623 case RTL_GIGA_MAC_VER_47:
4624 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 4625 case RTL_GIGA_MAC_VER_49:
4626 case RTL_GIGA_MAC_VER_50:
4627 case RTL_GIGA_MAC_VER_51:
649b3b8c 4628 RTL_W32(RxConfig, RTL_R32(RxConfig) |
4629 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4630 break;
4631 default:
4632 break;
4633 }
4634}
4635
4636static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
4637{
4638 if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
4639 return false;
4640
e2409d83 4641 rtl_speed_down(tp);
649b3b8c 4642 rtl_wol_suspend_quirk(tp);
4643
4644 return true;
4645}
4646
065c27c1 4647static void r810x_phy_power_down(struct rtl8169_private *tp)
4648{
4649 rtl_writephy(tp, 0x1f, 0x0000);
4650 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4651}
4652
4653static void r810x_phy_power_up(struct rtl8169_private *tp)
4654{
4655 rtl_writephy(tp, 0x1f, 0x0000);
4656 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4657}
4658
4659static void r810x_pll_power_down(struct rtl8169_private *tp)
4660{
0004299a
HW		 4661 void __iomem *ioaddr = tp->mmio_addr;
4662
649b3b8c 4663 if (rtl_wol_pll_power_down(tp))
065c27c1 4664 return;
065c27c1 4665
4666 r810x_phy_power_down(tp);
0004299a
HW		 4667
4668 switch (tp->mac_version) {
4669 case RTL_GIGA_MAC_VER_07:
4670 case RTL_GIGA_MAC_VER_08:
4671 case RTL_GIGA_MAC_VER_09:
4672 case RTL_GIGA_MAC_VER_10:
4673 case RTL_GIGA_MAC_VER_13:
4674 case RTL_GIGA_MAC_VER_16:
4675 break;
4676 default:
4677 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4678 break;
4679 }
065c27c1 4680}
4681
4682static void r810x_pll_power_up(struct rtl8169_private *tp)
4683{
0004299a
HW		 4684 void __iomem *ioaddr = tp->mmio_addr;
4685
065c27c1 4686 r810x_phy_power_up(tp);
0004299a
HW		 4687
4688 switch (tp->mac_version) {
4689 case RTL_GIGA_MAC_VER_07:
4690 case RTL_GIGA_MAC_VER_08:
4691 case RTL_GIGA_MAC_VER_09:
4692 case RTL_GIGA_MAC_VER_10:
4693 case RTL_GIGA_MAC_VER_13:
4694 case RTL_GIGA_MAC_VER_16:
4695 break;
6e1d0b89
CHL		 4696 case RTL_GIGA_MAC_VER_47:
4697 case RTL_GIGA_MAC_VER_48:
05b9687b 4698 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
6e1d0b89 4699 break;
0004299a
HW		 4700 default:
4701 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4702 break;
4703 }
065c27c1 4704}
4705
4706static void r8168_phy_power_up(struct rtl8169_private *tp)
4707{
4708 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 4709 switch (tp->mac_version) {
4710 case RTL_GIGA_MAC_VER_11:
4711 case RTL_GIGA_MAC_VER_12:
4712 case RTL_GIGA_MAC_VER_17:
4713 case RTL_GIGA_MAC_VER_18:
4714 case RTL_GIGA_MAC_VER_19:
4715 case RTL_GIGA_MAC_VER_20:
4716 case RTL_GIGA_MAC_VER_21:
4717 case RTL_GIGA_MAC_VER_22:
4718 case RTL_GIGA_MAC_VER_23:
4719 case RTL_GIGA_MAC_VER_24:
4720 case RTL_GIGA_MAC_VER_25:
4721 case RTL_GIGA_MAC_VER_26:
4722 case RTL_GIGA_MAC_VER_27:
4723 case RTL_GIGA_MAC_VER_28:
4724 case RTL_GIGA_MAC_VER_31:
4725 rtl_writephy(tp, 0x0e, 0x0000);
4726 break;
4727 default:
4728 break;
4729 }
065c27c1 4730 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4731}
4732
4733static void r8168_phy_power_down(struct rtl8169_private *tp)
4734{
4735 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 4736 switch (tp->mac_version) {
4737 case RTL_GIGA_MAC_VER_32:
4738 case RTL_GIGA_MAC_VER_33:
beb330a4 4739 case RTL_GIGA_MAC_VER_40:
4740 case RTL_GIGA_MAC_VER_41:
01dc7fec 4741 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
4742 break;
4743
4744 case RTL_GIGA_MAC_VER_11:
4745 case RTL_GIGA_MAC_VER_12:
4746 case RTL_GIGA_MAC_VER_17:
4747 case RTL_GIGA_MAC_VER_18:
4748 case RTL_GIGA_MAC_VER_19:
4749 case RTL_GIGA_MAC_VER_20:
4750 case RTL_GIGA_MAC_VER_21:
4751 case RTL_GIGA_MAC_VER_22:
4752 case RTL_GIGA_MAC_VER_23:
4753 case RTL_GIGA_MAC_VER_24:
4754 case RTL_GIGA_MAC_VER_25:
4755 case RTL_GIGA_MAC_VER_26:
4756 case RTL_GIGA_MAC_VER_27:
4757 case RTL_GIGA_MAC_VER_28:
4758 case RTL_GIGA_MAC_VER_31:
4759 rtl_writephy(tp, 0x0e, 0x0200);
4760 default:
4761 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4762 break;
4763 }
065c27c1 4764}
4765
4766static void r8168_pll_power_down(struct rtl8169_private *tp)
4767{
4768 void __iomem *ioaddr = tp->mmio_addr;
4769
cecb5fd7
FR		 4770 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4771 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
935e2218
CHL		 4772 tp->mac_version == RTL_GIGA_MAC_VER_31 ||
4773 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
4774 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
4775 tp->mac_version == RTL_GIGA_MAC_VER_51) &&
2f8c040c 4776 r8168_check_dash(tp)) {
065c27c1 4777 return;
5d2e1957 4778 }
065c27c1 4779
cecb5fd7
FR		 4780 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
4781 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
065c27c1 4782 (RTL_R16(CPlusCmd) & ASF)) {
4783 return;
4784 }
4785
01dc7fec 4786 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4787 tp->mac_version == RTL_GIGA_MAC_VER_33)
fdf6fc06 4788 rtl_ephy_write(tp, 0x19, 0xff64);
01dc7fec 4789
649b3b8c 4790 if (rtl_wol_pll_power_down(tp))
065c27c1 4791 return;
065c27c1 4792
4793 r8168_phy_power_down(tp);
4794
4795 switch (tp->mac_version) {
4796 case RTL_GIGA_MAC_VER_25:
4797 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 4798 case RTL_GIGA_MAC_VER_27:
4799 case RTL_GIGA_MAC_VER_28:
4804b3b3 4800 case RTL_GIGA_MAC_VER_31:
01dc7fec 4801 case RTL_GIGA_MAC_VER_32:
4802 case RTL_GIGA_MAC_VER_33:
42fde737 4803 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4804 case RTL_GIGA_MAC_VER_45:
4805 case RTL_GIGA_MAC_VER_46:
935e2218
CHL		 4806 case RTL_GIGA_MAC_VER_50:
4807 case RTL_GIGA_MAC_VER_51:
065c27c1 4808 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4809 break;
beb330a4 4810 case RTL_GIGA_MAC_VER_40:
4811 case RTL_GIGA_MAC_VER_41:
935e2218 4812 case RTL_GIGA_MAC_VER_49:
706123d0 4813 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
beb330a4 4814 0xfc000000, ERIAR_EXGMAC);
b8e5e6ad 4815 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
beb330a4 4816 break;
065c27c1 4817 }
4818}
4819
4820static void r8168_pll_power_up(struct rtl8169_private *tp)
4821{
4822 void __iomem *ioaddr = tp->mmio_addr;
4823
065c27c1 4824 switch (tp->mac_version) {
4825 case RTL_GIGA_MAC_VER_25:
4826 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 4827 case RTL_GIGA_MAC_VER_27:
4828 case RTL_GIGA_MAC_VER_28:
4804b3b3 4829 case RTL_GIGA_MAC_VER_31:
01dc7fec 4830 case RTL_GIGA_MAC_VER_32:
4831 case RTL_GIGA_MAC_VER_33:
065c27c1 4832 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4833 break;
42fde737 4834 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4835 case RTL_GIGA_MAC_VER_45:
4836 case RTL_GIGA_MAC_VER_46:
935e2218
CHL		 4837 case RTL_GIGA_MAC_VER_50:
4838 case RTL_GIGA_MAC_VER_51:
05b9687b 4839 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
6e1d0b89 4840 break;
beb330a4 4841 case RTL_GIGA_MAC_VER_40:
4842 case RTL_GIGA_MAC_VER_41:
935e2218 4843 case RTL_GIGA_MAC_VER_49:
b8e5e6ad 4844 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
706123d0 4845 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
beb330a4 4846 0x00000000, ERIAR_EXGMAC);
4847 break;
065c27c1 4848 }
4849
4850 r8168_phy_power_up(tp);
4851}
4852
d58d46b5
FR		 4853static void rtl_generic_op(struct rtl8169_private *tp,
4854 void (*op)(struct rtl8169_private *))
065c27c1 4855{
4856 if (op)
4857 op(tp);
4858}
4859
4860static void rtl_pll_power_down(struct rtl8169_private *tp)
4861{
d58d46b5 4862 rtl_generic_op(tp, tp->pll_power_ops.down);
065c27c1 4863}
4864
4865static void rtl_pll_power_up(struct rtl8169_private *tp)
4866{
d58d46b5 4867 rtl_generic_op(tp, tp->pll_power_ops.up);
065c27c1 4868}
4869
baf63293 4870static void rtl_init_pll_power_ops(struct rtl8169_private *tp)
065c27c1 4871{
4872 struct pll_power_ops *ops = &tp->pll_power_ops;
4873
4874 switch (tp->mac_version) {
4875 case RTL_GIGA_MAC_VER_07:
4876 case RTL_GIGA_MAC_VER_08:
4877 case RTL_GIGA_MAC_VER_09:
4878 case RTL_GIGA_MAC_VER_10:
4879 case RTL_GIGA_MAC_VER_16:
5a5e4443
HW		 4880 case RTL_GIGA_MAC_VER_29:
4881 case RTL_GIGA_MAC_VER_30:
7e18dca1 4882 case RTL_GIGA_MAC_VER_37:
5598bfe5 4883 case RTL_GIGA_MAC_VER_39:
58152cd4 4884 case RTL_GIGA_MAC_VER_43:
6e1d0b89
CHL		 4885 case RTL_GIGA_MAC_VER_47:
4886 case RTL_GIGA_MAC_VER_48:
065c27c1 4887 ops->down = r810x_pll_power_down;
4888 ops->up = r810x_pll_power_up;
4889 break;
4890
4891 case RTL_GIGA_MAC_VER_11:
4892 case RTL_GIGA_MAC_VER_12:
4893 case RTL_GIGA_MAC_VER_17:
4894 case RTL_GIGA_MAC_VER_18:
4895 case RTL_GIGA_MAC_VER_19:
4896 case RTL_GIGA_MAC_VER_20:
4897 case RTL_GIGA_MAC_VER_21:
4898 case RTL_GIGA_MAC_VER_22:
4899 case RTL_GIGA_MAC_VER_23:
4900 case RTL_GIGA_MAC_VER_24:
4901 case RTL_GIGA_MAC_VER_25:
4902 case RTL_GIGA_MAC_VER_26:
4903 case RTL_GIGA_MAC_VER_27:
e6de30d6 4904 case RTL_GIGA_MAC_VER_28:
4804b3b3 4905 case RTL_GIGA_MAC_VER_31:
01dc7fec 4906 case RTL_GIGA_MAC_VER_32:
4907 case RTL_GIGA_MAC_VER_33:
70090424 4908 case RTL_GIGA_MAC_VER_34:
c2218925
HW		 4909 case RTL_GIGA_MAC_VER_35:
4910 case RTL_GIGA_MAC_VER_36:
b3d7b2f2 4911 case RTL_GIGA_MAC_VER_38:
c558386b
HW		 4912 case RTL_GIGA_MAC_VER_40:
4913 case RTL_GIGA_MAC_VER_41:
57538c4a 4914 case RTL_GIGA_MAC_VER_42:
45dd95c4 4915 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4916 case RTL_GIGA_MAC_VER_45:
4917 case RTL_GIGA_MAC_VER_46:
935e2218
CHL		 4918 case RTL_GIGA_MAC_VER_49:
4919 case RTL_GIGA_MAC_VER_50:
4920 case RTL_GIGA_MAC_VER_51:
065c27c1 4921 ops->down = r8168_pll_power_down;
4922 ops->up = r8168_pll_power_up;
4923 break;
4924
4925 default:
4926 ops->down = NULL;
4927 ops->up = NULL;
4928 break;
4929 }
4930}
4931
e542a226
HW		 4932static void rtl_init_rxcfg(struct rtl8169_private *tp)
4933{
4934 void __iomem *ioaddr = tp->mmio_addr;
4935
4936 switch (tp->mac_version) {
4937 case RTL_GIGA_MAC_VER_01:
4938 case RTL_GIGA_MAC_VER_02:
4939 case RTL_GIGA_MAC_VER_03:
4940 case RTL_GIGA_MAC_VER_04:
4941 case RTL_GIGA_MAC_VER_05:
4942 case RTL_GIGA_MAC_VER_06:
4943 case RTL_GIGA_MAC_VER_10:
4944 case RTL_GIGA_MAC_VER_11:
4945 case RTL_GIGA_MAC_VER_12:
4946 case RTL_GIGA_MAC_VER_13:
4947 case RTL_GIGA_MAC_VER_14:
4948 case RTL_GIGA_MAC_VER_15:
4949 case RTL_GIGA_MAC_VER_16:
4950 case RTL_GIGA_MAC_VER_17:
4951 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4952 break;
4953 case RTL_GIGA_MAC_VER_18:
4954 case RTL_GIGA_MAC_VER_19:
4955 case RTL_GIGA_MAC_VER_20:
4956 case RTL_GIGA_MAC_VER_21:
4957 case RTL_GIGA_MAC_VER_22:
4958 case RTL_GIGA_MAC_VER_23:
4959 case RTL_GIGA_MAC_VER_24:
eb2dc35d 4960 case RTL_GIGA_MAC_VER_34:
3ced8c95 4961 case RTL_GIGA_MAC_VER_35:
e542a226
HW		 4962 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4963 break;
beb330a4 4964 case RTL_GIGA_MAC_VER_40:
4965 case RTL_GIGA_MAC_VER_41:
57538c4a 4966 case RTL_GIGA_MAC_VER_42:
58152cd4 4967 case RTL_GIGA_MAC_VER_43:
45dd95c4 4968 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4969 case RTL_GIGA_MAC_VER_45:
4970 case RTL_GIGA_MAC_VER_46:
4971 case RTL_GIGA_MAC_VER_47:
4972 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 4973 case RTL_GIGA_MAC_VER_49:
4974 case RTL_GIGA_MAC_VER_50:
4975 case RTL_GIGA_MAC_VER_51:
7ebc4822 4976 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
beb330a4 4977 break;
e542a226
HW		 4978 default:
4979 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
4980 break;
4981 }
4982}
4983
92fc43b4
HW		 4984static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4985{
9fba0812 4986 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
92fc43b4
HW		 4987}
4988
d58d46b5
FR		 4989static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4990{
9c5028e9 4991 void __iomem *ioaddr = tp->mmio_addr;
4992
4993 RTL_W8(Cfg9346, Cfg9346_Unlock);
d58d46b5 4994 rtl_generic_op(tp, tp->jumbo_ops.enable);
9c5028e9 4995 RTL_W8(Cfg9346, Cfg9346_Lock);
d58d46b5
FR		 4996}
4997
4998static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4999{
9c5028e9 5000 void __iomem *ioaddr = tp->mmio_addr;
5001
5002 RTL_W8(Cfg9346, Cfg9346_Unlock);
d58d46b5 5003 rtl_generic_op(tp, tp->jumbo_ops.disable);
9c5028e9 5004 RTL_W8(Cfg9346, Cfg9346_Lock);
d58d46b5
FR		 5005}
5006
5007static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
5008{
5009 void __iomem *ioaddr = tp->mmio_addr;
5010
5011 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
5012 RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
f65d539c 5013 rtl_tx_performance_tweak(tp->pci_dev, PCI_EXP_DEVCTL_READRQ_512B);
d58d46b5
FR		 5014}
5015
5016static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
5017{
5018 void __iomem *ioaddr = tp->mmio_addr;
5019
5020 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
5021 RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
5022 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
5023}
5024
5025static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
5026{
5027 void __iomem *ioaddr = tp->mmio_addr;
5028
5029 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
5030}
5031
5032static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
5033{
5034 void __iomem *ioaddr = tp->mmio_addr;
5035
5036 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
5037}
5038
5039static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
5040{
5041 void __iomem *ioaddr = tp->mmio_addr;
d58d46b5
FR		 5042
5043 RTL_W8(MaxTxPacketSize, 0x3f);
5044 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
5045 RTL_W8(Config4, RTL_R8(Config4) | 0x01);
f65d539c 5046 rtl_tx_performance_tweak(tp->pci_dev, PCI_EXP_DEVCTL_READRQ_512B);
d58d46b5
FR		 5047}
5048
5049static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
5050{
5051 void __iomem *ioaddr = tp->mmio_addr;
d58d46b5
FR		 5052
5053 RTL_W8(MaxTxPacketSize, 0x0c);
5054 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
5055 RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
4512ff9f 5056 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
d58d46b5
FR		 5057}
5058
5059static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
5060{
5061 rtl_tx_performance_tweak(tp->pci_dev,
f65d539c 5062 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
d58d46b5
FR		 5063}
5064
5065static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
5066{
5067 rtl_tx_performance_tweak(tp->pci_dev,
5068 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
5069}
5070
5071static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
5072{
5073 void __iomem *ioaddr = tp->mmio_addr;
5074
5075 r8168b_0_hw_jumbo_enable(tp);
5076
5077 RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
5078}
5079
5080static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
5081{
5082 void __iomem *ioaddr = tp->mmio_addr;
5083
5084 r8168b_0_hw_jumbo_disable(tp);
5085
5086 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
5087}
5088
baf63293 5089static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
d58d46b5
FR		 5090{
5091 struct jumbo_ops *ops = &tp->jumbo_ops;
5092
5093 switch (tp->mac_version) {
5094 case RTL_GIGA_MAC_VER_11:
5095 ops->disable = r8168b_0_hw_jumbo_disable;
5096 ops->enable = r8168b_0_hw_jumbo_enable;
5097 break;
5098 case RTL_GIGA_MAC_VER_12:
5099 case RTL_GIGA_MAC_VER_17:
5100 ops->disable = r8168b_1_hw_jumbo_disable;
5101 ops->enable = r8168b_1_hw_jumbo_enable;
5102 break;
5103 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
5104 case RTL_GIGA_MAC_VER_19:
5105 case RTL_GIGA_MAC_VER_20:
5106 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
5107 case RTL_GIGA_MAC_VER_22:
5108 case RTL_GIGA_MAC_VER_23:
5109 case RTL_GIGA_MAC_VER_24:
5110 case RTL_GIGA_MAC_VER_25:
5111 case RTL_GIGA_MAC_VER_26:
5112 ops->disable = r8168c_hw_jumbo_disable;
5113 ops->enable = r8168c_hw_jumbo_enable;
5114 break;
5115 case RTL_GIGA_MAC_VER_27:
5116 case RTL_GIGA_MAC_VER_28:
5117 ops->disable = r8168dp_hw_jumbo_disable;
5118 ops->enable = r8168dp_hw_jumbo_enable;
5119 break;
5120 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
5121 case RTL_GIGA_MAC_VER_32:
5122 case RTL_GIGA_MAC_VER_33:
5123 case RTL_GIGA_MAC_VER_34:
5124 ops->disable = r8168e_hw_jumbo_disable;
5125 ops->enable = r8168e_hw_jumbo_enable;
5126 break;
5127
5128 /*
5129 * No action needed for jumbo frames with 8169.
5130 * No jumbo for 810x at all.
5131 */
c558386b
HW		 5132 case RTL_GIGA_MAC_VER_40:
5133 case RTL_GIGA_MAC_VER_41:
57538c4a 5134 case RTL_GIGA_MAC_VER_42:
58152cd4 5135 case RTL_GIGA_MAC_VER_43:
45dd95c4 5136 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 5137 case RTL_GIGA_MAC_VER_45:
5138 case RTL_GIGA_MAC_VER_46:
5139 case RTL_GIGA_MAC_VER_47:
5140 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 5141 case RTL_GIGA_MAC_VER_49:
5142 case RTL_GIGA_MAC_VER_50:
5143 case RTL_GIGA_MAC_VER_51:
d58d46b5
FR		 5144 default:
5145 ops->disable = NULL;
5146 ops->enable = NULL;
5147 break;
5148 }
5149}
5150
ffc46952
FR		 5151DECLARE_RTL_COND(rtl_chipcmd_cond)
5152{
5153 void __iomem *ioaddr = tp->mmio_addr;
5154
5155 return RTL_R8(ChipCmd) & CmdReset;
5156}
5157
6f43adc8
FR		 5158static void rtl_hw_reset(struct rtl8169_private *tp)
5159{
5160 void __iomem *ioaddr = tp->mmio_addr;
6f43adc8 5161
6f43adc8
FR		 5162 RTL_W8(ChipCmd, CmdReset);
5163
ffc46952 5164 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
6f43adc8
FR		 5165}
5166
b6ffd97f 5167static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
953a12cc 5168{
b6ffd97f
FR		 5169 struct rtl_fw *rtl_fw;
5170 const char *name;
5171 int rc = -ENOMEM;
953a12cc 5172
b6ffd97f
FR		 5173 name = rtl_lookup_firmware_name(tp);
5174 if (!name)
5175 goto out_no_firmware;
953a12cc 5176
b6ffd97f
FR		 5177 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
5178 if (!rtl_fw)
5179 goto err_warn;
31bd204f 5180
b6ffd97f
FR		 5181 rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
5182 if (rc < 0)
5183 goto err_free;
5184
fd112f2e
FR		 5185 rc = rtl_check_firmware(tp, rtl_fw);
5186 if (rc < 0)
5187 goto err_release_firmware;
5188
b6ffd97f
FR		 5189 tp->rtl_fw = rtl_fw;
5190out:
5191 return;
5192
fd112f2e
FR		 5193err_release_firmware:
5194 release_firmware(rtl_fw->fw);
b6ffd97f
FR		 5195err_free:
5196 kfree(rtl_fw);
5197err_warn:
5198 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
5199 name, rc);
5200out_no_firmware:
5201 tp->rtl_fw = NULL;
5202 goto out;
5203}
5204
5205static void rtl_request_firmware(struct rtl8169_private *tp)
5206{
5207 if (IS_ERR(tp->rtl_fw))
5208 rtl_request_uncached_firmware(tp);
953a12cc
FR		 5209}
5210
92fc43b4
HW		 5211static void rtl_rx_close(struct rtl8169_private *tp)
5212{
5213 void __iomem *ioaddr = tp->mmio_addr;
92fc43b4 5214
1687b566 5215 RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
92fc43b4
HW		 5216}
5217
ffc46952
FR		 5218DECLARE_RTL_COND(rtl_npq_cond)
5219{
5220 void __iomem *ioaddr = tp->mmio_addr;
5221
5222 return RTL_R8(TxPoll) & NPQ;
5223}
5224
5225DECLARE_RTL_COND(rtl_txcfg_empty_cond)
5226{
5227 void __iomem *ioaddr = tp->mmio_addr;
5228
5229 return RTL_R32(TxConfig) & TXCFG_EMPTY;
5230}
5231
e6de30d6 5232static void rtl8169_hw_reset(struct rtl8169_private *tp)
1da177e4 5233{
e6de30d6 5234 void __iomem *ioaddr = tp->mmio_addr;
5235
1da177e4 5236 /* Disable interrupts */
811fd301 5237 rtl8169_irq_mask_and_ack(tp);
1da177e4 5238
92fc43b4
HW		 5239 rtl_rx_close(tp);
5240
5d2e1957 5241 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4804b3b3 5242 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
5243 tp->mac_version == RTL_GIGA_MAC_VER_31) {
ffc46952 5244 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
c2218925 5245 } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
6e1d0b89
CHL		 5246 tp->mac_version == RTL_GIGA_MAC_VER_35 ||
5247 tp->mac_version == RTL_GIGA_MAC_VER_36 ||
5248 tp->mac_version == RTL_GIGA_MAC_VER_37 ||
5249 tp->mac_version == RTL_GIGA_MAC_VER_38 ||
5250 tp->mac_version == RTL_GIGA_MAC_VER_40 ||
5251 tp->mac_version == RTL_GIGA_MAC_VER_41 ||
5252 tp->mac_version == RTL_GIGA_MAC_VER_42 ||
5253 tp->mac_version == RTL_GIGA_MAC_VER_43 ||
5254 tp->mac_version == RTL_GIGA_MAC_VER_44 ||
5255 tp->mac_version == RTL_GIGA_MAC_VER_45 ||
5256 tp->mac_version == RTL_GIGA_MAC_VER_46 ||
5257 tp->mac_version == RTL_GIGA_MAC_VER_47 ||
935e2218
CHL		 5258 tp->mac_version == RTL_GIGA_MAC_VER_48 ||
5259 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
5260 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
5261 tp->mac_version == RTL_GIGA_MAC_VER_51) {
c2b0c1e7 5262 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
ffc46952 5263 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
92fc43b4
HW		 5264 } else {
5265 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
5266 udelay(100);
e6de30d6 5267 }
5268
92fc43b4 5269 rtl_hw_reset(tp);
1da177e4
LT		 5270}
5271
7f796d83 5272static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 5273{
5274 void __iomem *ioaddr = tp->mmio_addr;
9cb427b6
FR		 5275
5276 /* Set DMA burst size and Interframe Gap Time */
5277 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
5278 (InterFrameGap << TxInterFrameGapShift));
5279}
5280
07ce4064 5281static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 5282{
5283 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 5284
07ce4064
FR		 5285 tp->hw_start(dev);
5286
da78dbff 5287 rtl_irq_enable_all(tp);
07ce4064
FR		 5288}
5289
7f796d83
FR		 5290static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
5291 void __iomem *ioaddr)
5292{
5293 /*
5294 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
5295 * register to be written before TxDescAddrLow to work.
5296 * Switching from MMIO to I/O access fixes the issue as well.
5297 */
5298 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
284901a9 5299 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
7f796d83 5300 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
284901a9 5301 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 5302}
5303
5304static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
5305{
5306 u16 cmd;
5307
5308 cmd = RTL_R16(CPlusCmd);
5309 RTL_W16(CPlusCmd, cmd);
5310 return cmd;
5311}
5312
fdd7b4c3 5313static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
7f796d83
FR		 5314{
5315 /* Low hurts. Let's disable the filtering. */
207d6e87 5316 RTL_W16(RxMaxSize, rx_buf_sz + 1);
7f796d83
FR		 5317}
5318
6dccd16b
FR		 5319static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
5320{
3744100e 5321 static const struct rtl_cfg2_info {
6dccd16b
FR		 5322 u32 mac_version;
5323 u32 clk;
5324 u32 val;
5325 } cfg2_info [] = {
5326 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
5327 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
5328 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
5329 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3744100e
FR		 5330 };
5331 const struct rtl_cfg2_info *p = cfg2_info;
6dccd16b
FR		 5332 unsigned int i;
5333 u32 clk;
5334
5335 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 5336 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 5337 if ((p->mac_version == mac_version) && (p->clk == clk)) {
5338 RTL_W32(0x7c, p->val);
5339 break;
5340 }
5341 }
5342}
5343
e6b763ea
FR		 5344static void rtl_set_rx_mode(struct net_device *dev)
5345{
5346 struct rtl8169_private *tp = netdev_priv(dev);
5347 void __iomem *ioaddr = tp->mmio_addr;
5348 u32 mc_filter[2]; /* Multicast hash filter */
5349 int rx_mode;
5350 u32 tmp = 0;
5351
5352 if (dev->flags & IFF_PROMISC) {
5353 /* Unconditionally log net taps. */
5354 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
5355 rx_mode =
5356 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5357 AcceptAllPhys;
5358 mc_filter[1] = mc_filter[0] = 0xffffffff;
5359 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
5360 (dev->flags & IFF_ALLMULTI)) {
5361 /* Too many to filter perfectly -- accept all multicasts. */
5362 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5363 mc_filter[1] = mc_filter[0] = 0xffffffff;
5364 } else {
5365 struct netdev_hw_addr *ha;
5366
5367 rx_mode = AcceptBroadcast | AcceptMyPhys;
5368 mc_filter[1] = mc_filter[0] = 0;
5369 netdev_for_each_mc_addr(ha, dev) {
5370 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
5371 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5372 rx_mode |= AcceptMulticast;
5373 }
5374 }
5375
5376 if (dev->features & NETIF_F_RXALL)
5377 rx_mode |= (AcceptErr | AcceptRunt);
5378
5379 tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
5380
5381 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
5382 u32 data = mc_filter[0];
5383
5384 mc_filter[0] = swab32(mc_filter[1]);
5385 mc_filter[1] = swab32(data);
5386 }
5387
0481776b
NW		 5388 if (tp->mac_version == RTL_GIGA_MAC_VER_35)
5389 mc_filter[1] = mc_filter[0] = 0xffffffff;
5390
e6b763ea
FR		 5391 RTL_W32(MAR0 + 4, mc_filter[1]);
5392 RTL_W32(MAR0 + 0, mc_filter[0]);
5393
5394 RTL_W32(RxConfig, tmp);
5395}
5396
07ce4064
FR		 5397static void rtl_hw_start_8169(struct net_device *dev)
5398{
5399 struct rtl8169_private *tp = netdev_priv(dev);
5400 void __iomem *ioaddr = tp->mmio_addr;
5401 struct pci_dev *pdev = tp->pci_dev;
07ce4064 5402
9cb427b6
FR		 5403 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
5404 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
5405 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
5406 }
5407
1da177e4 5408 RTL_W8(Cfg9346, Cfg9346_Unlock);
cecb5fd7
FR		 5409 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
5410 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5411 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
5412 tp->mac_version == RTL_GIGA_MAC_VER_04)
9cb427b6
FR		 5413 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5414
e542a226
HW		 5415 rtl_init_rxcfg(tp);
5416
f0298f81 5417 RTL_W8(EarlyTxThres, NoEarlyTx);
1da177e4 5418
6f0333b8 5419 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
1da177e4 5420
cecb5fd7
FR		 5421 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
5422 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5423 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
5424 tp->mac_version == RTL_GIGA_MAC_VER_04)
c946b304 5425 rtl_set_rx_tx_config_registers(tp);
1da177e4 5426
7f796d83 5427 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 5428
cecb5fd7
FR		 5429 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5430 tp->mac_version == RTL_GIGA_MAC_VER_03) {
05b9687b 5431 dprintk("Set MAC Reg C+CR Offset 0xe0. "
1da177e4 5432 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 5433 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 5434 }
5435
bcf0bf90
FR		 5436 RTL_W16(CPlusCmd, tp->cp_cmd);
5437
6dccd16b
FR		 5438 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
5439
1da177e4
LT		 5440 /*
5441 * Undocumented corner. Supposedly:
5442 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
5443 */
5444 RTL_W16(IntrMitigate, 0x0000);
5445
7f796d83 5446 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 5447
cecb5fd7
FR		 5448 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
5449 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
5450 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
5451 tp->mac_version != RTL_GIGA_MAC_VER_04) {
c946b304
FR		 5452 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5453 rtl_set_rx_tx_config_registers(tp);
5454 }
5455
1da177e4 5456 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 5457
5458 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
5459 RTL_R8(IntrMask);
1da177e4
LT		 5460
5461 RTL_W32(RxMissed, 0);
5462
07ce4064 5463 rtl_set_rx_mode(dev);
1da177e4
LT		 5464
5465 /* no early-rx interrupts */
05b9687b 5466 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
07ce4064 5467}
1da177e4 5468
beb1fe18
HW		 5469static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
5470{
5471 if (tp->csi_ops.write)
52989f0e 5472 tp->csi_ops.write(tp, addr, value);
beb1fe18
HW		 5473}
5474
5475static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
5476{
52989f0e 5477 return tp->csi_ops.read ? tp->csi_ops.read(tp, addr) : ~0;
beb1fe18
HW		 5478}
5479
5480static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits)
dacf8154
FR		 5481{
5482 u32 csi;
5483
beb1fe18
HW		 5484 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
5485 rtl_csi_write(tp, 0x070c, csi | bits);
5486}
5487
5488static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
5489{
5490 rtl_csi_access_enable(tp, 0x17000000);
650e8d5d 5491}
5492
beb1fe18 5493static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
e6de30d6 5494{
beb1fe18 5495 rtl_csi_access_enable(tp, 0x27000000);
e6de30d6 5496}
5497
ffc46952
FR		 5498DECLARE_RTL_COND(rtl_csiar_cond)
5499{
5500 void __iomem *ioaddr = tp->mmio_addr;
5501
5502 return RTL_R32(CSIAR) & CSIAR_FLAG;
5503}
5504
52989f0e 5505static void r8169_csi_write(struct rtl8169_private *tp, int addr, int value)
650e8d5d 5506{
52989f0e 5507 void __iomem *ioaddr = tp->mmio_addr;
beb1fe18
HW		 5508
5509 RTL_W32(CSIDR, value);
5510 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5511 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5512
ffc46952 5513 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
beb1fe18
HW		 5514}
5515
52989f0e 5516static u32 r8169_csi_read(struct rtl8169_private *tp, int addr)
beb1fe18 5517{
52989f0e 5518 void __iomem *ioaddr = tp->mmio_addr;
beb1fe18
HW		 5519
5520 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
5521 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5522
ffc46952
FR		 5523 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5524 RTL_R32(CSIDR) : ~0;
beb1fe18
HW		 5525}
5526
52989f0e 5527static void r8402_csi_write(struct rtl8169_private *tp, int addr, int value)
7e18dca1 5528{
52989f0e 5529 void __iomem *ioaddr = tp->mmio_addr;
7e18dca1
HW		 5530
5531 RTL_W32(CSIDR, value);
5532 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5533 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
5534 CSIAR_FUNC_NIC);
5535
ffc46952 5536 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
7e18dca1
HW		 5537}
5538
52989f0e 5539static u32 r8402_csi_read(struct rtl8169_private *tp, int addr)
7e18dca1 5540{
52989f0e 5541 void __iomem *ioaddr = tp->mmio_addr;
7e18dca1
HW		 5542
5543 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
5544 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5545
ffc46952
FR		 5546 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5547 RTL_R32(CSIDR) : ~0;
7e18dca1
HW		 5548}
5549
45dd95c4 5550static void r8411_csi_write(struct rtl8169_private *tp, int addr, int value)
5551{
5552 void __iomem *ioaddr = tp->mmio_addr;
5553
5554 RTL_W32(CSIDR, value);
5555 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5556 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
5557 CSIAR_FUNC_NIC2);
5558
5559 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5560}
5561
5562static u32 r8411_csi_read(struct rtl8169_private *tp, int addr)
5563{
5564 void __iomem *ioaddr = tp->mmio_addr;
5565
5566 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC2 |
5567 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5568
5569 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5570 RTL_R32(CSIDR) : ~0;
5571}
5572
baf63293 5573static void rtl_init_csi_ops(struct rtl8169_private *tp)
beb1fe18
HW		 5574{
5575 struct csi_ops *ops = &tp->csi_ops;
5576
5577 switch (tp->mac_version) {
5578 case RTL_GIGA_MAC_VER_01:
5579 case RTL_GIGA_MAC_VER_02:
5580 case RTL_GIGA_MAC_VER_03:
5581 case RTL_GIGA_MAC_VER_04:
5582 case RTL_GIGA_MAC_VER_05:
5583 case RTL_GIGA_MAC_VER_06:
5584 case RTL_GIGA_MAC_VER_10:
5585 case RTL_GIGA_MAC_VER_11:
5586 case RTL_GIGA_MAC_VER_12:
5587 case RTL_GIGA_MAC_VER_13:
5588 case RTL_GIGA_MAC_VER_14:
5589 case RTL_GIGA_MAC_VER_15:
5590 case RTL_GIGA_MAC_VER_16:
5591 case RTL_GIGA_MAC_VER_17:
5592 ops->write = NULL;
5593 ops->read = NULL;
5594 break;
5595
7e18dca1 5596 case RTL_GIGA_MAC_VER_37:
b3d7b2f2 5597 case RTL_GIGA_MAC_VER_38:
7e18dca1
HW		 5598 ops->write = r8402_csi_write;
5599 ops->read = r8402_csi_read;
5600 break;
5601
45dd95c4 5602 case RTL_GIGA_MAC_VER_44:
5603 ops->write = r8411_csi_write;
5604 ops->read = r8411_csi_read;
5605 break;
5606
beb1fe18
HW		 5607 default:
5608 ops->write = r8169_csi_write;
5609 ops->read = r8169_csi_read;
5610 break;
5611 }
dacf8154
FR		 5612}
5613
5614struct ephy_info {
5615 unsigned int offset;
5616 u16 mask;
5617 u16 bits;
5618};
5619
fdf6fc06
FR		 5620static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
5621 int len)
dacf8154
FR		 5622{
5623 u16 w;
5624
5625 while (len-- > 0) {
fdf6fc06
FR		 5626 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
5627 rtl_ephy_write(tp, e->offset, w);
dacf8154
FR		 5628 e++;
5629 }
5630}
5631
b726e493
FR		 5632static void rtl_disable_clock_request(struct pci_dev *pdev)
5633{
7d7903b2
JL		 5634 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
5635 PCI_EXP_LNKCTL_CLKREQ_EN);
b726e493
FR		 5636}
5637
e6de30d6 5638static void rtl_enable_clock_request(struct pci_dev *pdev)
5639{
7d7903b2
JL		 5640 pcie_capability_set_word(pdev, PCI_EXP_LNKCTL,
5641 PCI_EXP_LNKCTL_CLKREQ_EN);
e6de30d6 5642}
5643
b51ecea8 5644static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable)
5645{
5646 void __iomem *ioaddr = tp->mmio_addr;
5647 u8 data;
5648
5649 data = RTL_R8(Config3);
5650
5651 if (enable)
5652 data |= Rdy_to_L23;
5653 else
5654 data &= ~Rdy_to_L23;
5655
5656 RTL_W8(Config3, data);
5657}
5658
b726e493
FR		 5659#define R8168_CPCMD_QUIRK_MASK (\
5660 EnableBist | \
5661 Mac_dbgo_oe | \
5662 Force_half_dup | \
5663 Force_rxflow_en | \
5664 Force_txflow_en | \
5665 Cxpl_dbg_sel | \
5666 ASF | \
5667 PktCntrDisable | \
5668 Mac_dbgo_sel)
5669
beb1fe18 5670static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
219a1e9d 5671{
beb1fe18
HW		 5672 void __iomem *ioaddr = tp->mmio_addr;
5673 struct pci_dev *pdev = tp->pci_dev;
5674
b726e493
FR		 5675 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5676
5677 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5678
faf1e785 5679 if (tp->dev->mtu <= ETH_DATA_LEN) {
5680 rtl_tx_performance_tweak(pdev, (0x5 << MAX_READ_REQUEST_SHIFT) |
5681 PCI_EXP_DEVCTL_NOSNOOP_EN);
5682 }
219a1e9d
FR		 5683}
5684
beb1fe18 5685static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
219a1e9d 5686{
beb1fe18
HW		 5687 void __iomem *ioaddr = tp->mmio_addr;
5688
5689 rtl_hw_start_8168bb(tp);
b726e493 5690
f0298f81 5691 RTL_W8(MaxTxPacketSize, TxPacketMax);
b726e493
FR		 5692
5693 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
219a1e9d
FR		 5694}
5695
beb1fe18 5696static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
219a1e9d 5697{
beb1fe18
HW		 5698 void __iomem *ioaddr = tp->mmio_addr;
5699 struct pci_dev *pdev = tp->pci_dev;
5700
b726e493
FR		 5701 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
5702
5703 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5704
faf1e785 5705 if (tp->dev->mtu <= ETH_DATA_LEN)
5706 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
b726e493
FR		 5707
5708 rtl_disable_clock_request(pdev);
5709
5710 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
219a1e9d
FR		 5711}
5712
beb1fe18 5713static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
219a1e9d 5714{
350f7596 5715 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 5716 { 0x01, 0, 0x0001 },
5717 { 0x02, 0x0800, 0x1000 },
5718 { 0x03, 0, 0x0042 },
5719 { 0x06, 0x0080, 0x0000 },
5720 { 0x07, 0, 0x2000 }
5721 };
5722
beb1fe18 5723 rtl_csi_access_enable_2(tp);
b726e493 5724
fdf6fc06 5725 rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
b726e493 5726
beb1fe18 5727 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 5728}
5729
beb1fe18 5730static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
ef3386f0 5731{
beb1fe18
HW		 5732 void __iomem *ioaddr = tp->mmio_addr;
5733 struct pci_dev *pdev = tp->pci_dev;
5734
5735 rtl_csi_access_enable_2(tp);
ef3386f0
FR		 5736
5737 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5738
faf1e785 5739 if (tp->dev->mtu <= ETH_DATA_LEN)
5740 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
ef3386f0
FR		 5741
5742 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5743}
5744
beb1fe18 5745static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
7f3e3d3a 5746{
beb1fe18
HW		 5747 void __iomem *ioaddr = tp->mmio_addr;
5748 struct pci_dev *pdev = tp->pci_dev;
5749
5750 rtl_csi_access_enable_2(tp);
7f3e3d3a
FR		 5751
5752 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5753
5754 /* Magic. */
5755 RTL_W8(DBG_REG, 0x20);
5756
f0298f81 5757 RTL_W8(MaxTxPacketSize, TxPacketMax);
7f3e3d3a 5758
faf1e785 5759 if (tp->dev->mtu <= ETH_DATA_LEN)
5760 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
7f3e3d3a
FR		 5761
5762 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5763}
5764
beb1fe18 5765static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
219a1e9d 5766{
beb1fe18 5767 void __iomem *ioaddr = tp->mmio_addr;
350f7596 5768 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 5769 { 0x02, 0x0800, 0x1000 },
5770 { 0x03, 0, 0x0002 },
5771 { 0x06, 0x0080, 0x0000 }
5772 };
5773
beb1fe18 5774 rtl_csi_access_enable_2(tp);
b726e493
FR		 5775
5776 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
5777
fdf6fc06 5778 rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
b726e493 5779
beb1fe18 5780 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 5781}
5782
beb1fe18 5783static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
219a1e9d 5784{
350f7596 5785 static const struct ephy_info e_info_8168c_2[] = {
b726e493
FR		 5786 { 0x01, 0, 0x0001 },
5787 { 0x03, 0x0400, 0x0220 }
5788 };
5789
beb1fe18 5790 rtl_csi_access_enable_2(tp);
b726e493 5791
fdf6fc06 5792 rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
b726e493 5793
beb1fe18 5794 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 5795}
5796
beb1fe18 5797static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
197ff761 5798{
beb1fe18 5799 rtl_hw_start_8168c_2(tp);
197ff761
FR		 5800}
5801
beb1fe18 5802static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
6fb07058 5803{
beb1fe18 5804 rtl_csi_access_enable_2(tp);
6fb07058 5805
beb1fe18 5806 __rtl_hw_start_8168cp(tp);
6fb07058
FR		 5807}
5808
beb1fe18 5809static void rtl_hw_start_8168d(struct rtl8169_private *tp)
5b538df9 5810{
beb1fe18
HW		 5811 void __iomem *ioaddr = tp->mmio_addr;
5812 struct pci_dev *pdev = tp->pci_dev;
5813
5814 rtl_csi_access_enable_2(tp);
5b538df9
FR		 5815
5816 rtl_disable_clock_request(pdev);
5817
f0298f81 5818 RTL_W8(MaxTxPacketSize, TxPacketMax);
5b538df9 5819
faf1e785 5820 if (tp->dev->mtu <= ETH_DATA_LEN)
5821 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5b538df9
FR		 5822
5823 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5824}
5825
beb1fe18 5826static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4804b3b3 5827{
beb1fe18
HW		 5828 void __iomem *ioaddr = tp->mmio_addr;
5829 struct pci_dev *pdev = tp->pci_dev;
5830
5831 rtl_csi_access_enable_1(tp);
4804b3b3 5832
faf1e785 5833 if (tp->dev->mtu <= ETH_DATA_LEN)
5834 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4804b3b3 5835
5836 RTL_W8(MaxTxPacketSize, TxPacketMax);
5837
5838 rtl_disable_clock_request(pdev);
5839}
5840
beb1fe18 5841static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
e6de30d6 5842{
beb1fe18
HW		 5843 void __iomem *ioaddr = tp->mmio_addr;
5844 struct pci_dev *pdev = tp->pci_dev;
e6de30d6 5845 static const struct ephy_info e_info_8168d_4[] = {
1016a4a1
CHL		 5846 { 0x0b, 0x0000, 0x0048 },
5847 { 0x19, 0x0020, 0x0050 },
5848 { 0x0c, 0x0100, 0x0020 }
e6de30d6 5849 };
e6de30d6 5850
beb1fe18 5851 rtl_csi_access_enable_1(tp);
e6de30d6 5852
5853 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5854
5855 RTL_W8(MaxTxPacketSize, TxPacketMax);
5856
1016a4a1 5857 rtl_ephy_init(tp, e_info_8168d_4, ARRAY_SIZE(e_info_8168d_4));
e6de30d6 5858
5859 rtl_enable_clock_request(pdev);
5860}
5861
beb1fe18 5862static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
01dc7fec 5863{
beb1fe18
HW		 5864 void __iomem *ioaddr = tp->mmio_addr;
5865 struct pci_dev *pdev = tp->pci_dev;
70090424 5866 static const struct ephy_info e_info_8168e_1[] = {
01dc7fec 5867 { 0x00, 0x0200, 0x0100 },
5868 { 0x00, 0x0000, 0x0004 },
5869 { 0x06, 0x0002, 0x0001 },
5870 { 0x06, 0x0000, 0x0030 },
5871 { 0x07, 0x0000, 0x2000 },
5872 { 0x00, 0x0000, 0x0020 },
5873 { 0x03, 0x5800, 0x2000 },
5874 { 0x03, 0x0000, 0x0001 },
5875 { 0x01, 0x0800, 0x1000 },
5876 { 0x07, 0x0000, 0x4000 },
5877 { 0x1e, 0x0000, 0x2000 },
5878 { 0x19, 0xffff, 0xfe6c },
5879 { 0x0a, 0x0000, 0x0040 }
5880 };
5881
beb1fe18 5882 rtl_csi_access_enable_2(tp);
01dc7fec 5883
fdf6fc06 5884 rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
01dc7fec 5885
faf1e785 5886 if (tp->dev->mtu <= ETH_DATA_LEN)
5887 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
01dc7fec 5888
5889 RTL_W8(MaxTxPacketSize, TxPacketMax);
5890
5891 rtl_disable_clock_request(pdev);
5892
5893 /* Reset tx FIFO pointer */
cecb5fd7
FR		 5894 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
5895 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
01dc7fec 5896
cecb5fd7 5897 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
01dc7fec 5898}
5899
beb1fe18 5900static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
70090424 5901{
beb1fe18
HW		 5902 void __iomem *ioaddr = tp->mmio_addr;
5903 struct pci_dev *pdev = tp->pci_dev;
70090424
HW		 5904 static const struct ephy_info e_info_8168e_2[] = {
5905 { 0x09, 0x0000, 0x0080 },
5906 { 0x19, 0x0000, 0x0224 }
5907 };
5908
beb1fe18 5909 rtl_csi_access_enable_1(tp);
70090424 5910
fdf6fc06 5911 rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
70090424 5912
faf1e785 5913 if (tp->dev->mtu <= ETH_DATA_LEN)
5914 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
70090424 5915
fdf6fc06
FR		 5916 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5917 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5918 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5919 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5920 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5921 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
706123d0
CHL		 5922 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5923 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
70090424 5924
3090bd9a 5925 RTL_W8(MaxTxPacketSize, EarlySize);
70090424 5926
4521e1a9
FR		 5927 rtl_disable_clock_request(pdev);
5928
70090424
HW		 5929 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5930 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5931
5932 /* Adjust EEE LED frequency */
5933 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5934
5935 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5936 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4521e1a9 5937 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
70090424
HW		 5938}
5939
5f886e08 5940static void rtl_hw_start_8168f(struct rtl8169_private *tp)
c2218925 5941{
beb1fe18
HW		 5942 void __iomem *ioaddr = tp->mmio_addr;
5943 struct pci_dev *pdev = tp->pci_dev;
c2218925 5944
5f886e08 5945 rtl_csi_access_enable_2(tp);
c2218925
HW		 5946
5947 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5948
fdf6fc06
FR		 5949 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5950 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5951 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5952 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
706123d0
CHL		 5953 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5954 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5955 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5956 rtl_w0w1_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
fdf6fc06
FR		 5957 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5958 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
c2218925
HW		 5959
5960 RTL_W8(MaxTxPacketSize, EarlySize);
5961
4521e1a9
FR		 5962 rtl_disable_clock_request(pdev);
5963
c2218925
HW		 5964 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5965 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
c2218925 5966 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4521e1a9
FR		 5967 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5968 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
c2218925
HW		 5969}
5970
5f886e08
HW		 5971static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5972{
5973 void __iomem *ioaddr = tp->mmio_addr;
5974 static const struct ephy_info e_info_8168f_1[] = {
5975 { 0x06, 0x00c0, 0x0020 },
5976 { 0x08, 0x0001, 0x0002 },
5977 { 0x09, 0x0000, 0x0080 },
5978 { 0x19, 0x0000, 0x0224 }
5979 };
5980
5981 rtl_hw_start_8168f(tp);
5982
fdf6fc06 5983 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5f886e08 5984
706123d0 5985 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5f886e08
HW		 5986
5987 /* Adjust EEE LED frequency */
5988 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5989}
5990
b3d7b2f2
HW		 5991static void rtl_hw_start_8411(struct rtl8169_private *tp)
5992{
b3d7b2f2
HW		 5993 static const struct ephy_info e_info_8168f_1[] = {
5994 { 0x06, 0x00c0, 0x0020 },
5995 { 0x0f, 0xffff, 0x5200 },
5996 { 0x1e, 0x0000, 0x4000 },
5997 { 0x19, 0x0000, 0x0224 }
5998 };
5999
6000 rtl_hw_start_8168f(tp);
b51ecea8 6001 rtl_pcie_state_l2l3_enable(tp, false);
b3d7b2f2 6002
fdf6fc06 6003 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
b3d7b2f2 6004
706123d0 6005 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
b3d7b2f2
HW		 6006}
6007
5fbea337 6008static void rtl_hw_start_8168g(struct rtl8169_private *tp)
c558386b
HW		 6009{
6010 void __iomem *ioaddr = tp->mmio_addr;
6011 struct pci_dev *pdev = tp->pci_dev;
6012
beb330a4 6013 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6014
c558386b
HW		 6015 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
6016 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
6017 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
6018 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6019
6020 rtl_csi_access_enable_1(tp);
6021
6022 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6023
706123d0
CHL		 6024 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6025 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
beb330a4 6026 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
c558386b 6027
4521e1a9 6028 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
c558386b
HW		 6029 RTL_W8(MaxTxPacketSize, EarlySize);
6030
6031 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6032 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6033
6034 /* Adjust EEE LED frequency */
6035 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6036
706123d0
CHL		 6037 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
6038 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
b51ecea8 6039
6040 rtl_pcie_state_l2l3_enable(tp, false);
c558386b
HW		 6041}
6042
5fbea337
CHL		 6043static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
6044{
6045 void __iomem *ioaddr = tp->mmio_addr;
6046 static const struct ephy_info e_info_8168g_1[] = {
6047 { 0x00, 0x0000, 0x0008 },
6048 { 0x0c, 0x37d0, 0x0820 },
6049 { 0x1e, 0x0000, 0x0001 },
6050 { 0x19, 0x8000, 0x0000 }
6051 };
6052
6053 rtl_hw_start_8168g(tp);
6054
6055 /* disable aspm and clock request before access ephy */
6056 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6057 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6058 rtl_ephy_init(tp, e_info_8168g_1, ARRAY_SIZE(e_info_8168g_1));
6059}
6060
57538c4a 6061static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
6062{
6063 void __iomem *ioaddr = tp->mmio_addr;
6064 static const struct ephy_info e_info_8168g_2[] = {
6065 { 0x00, 0x0000, 0x0008 },
6066 { 0x0c, 0x3df0, 0x0200 },
6067 { 0x19, 0xffff, 0xfc00 },
6068 { 0x1e, 0xffff, 0x20eb }
6069 };
6070
5fbea337 6071 rtl_hw_start_8168g(tp);
57538c4a 6072
6073 /* disable aspm and clock request before access ephy */
6074 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6075 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6076 rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
6077}
6078
45dd95c4 6079static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
6080{
6081 void __iomem *ioaddr = tp->mmio_addr;
6082 static const struct ephy_info e_info_8411_2[] = {
6083 { 0x00, 0x0000, 0x0008 },
6084 { 0x0c, 0x3df0, 0x0200 },
6085 { 0x0f, 0xffff, 0x5200 },
6086 { 0x19, 0x0020, 0x0000 },
6087 { 0x1e, 0x0000, 0x2000 }
6088 };
6089
5fbea337 6090 rtl_hw_start_8168g(tp);
45dd95c4 6091
6092 /* disable aspm and clock request before access ephy */
6093 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6094 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6095 rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
6096}
6097
6e1d0b89
CHL		 6098static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
6099{
6100 void __iomem *ioaddr = tp->mmio_addr;
6101 struct pci_dev *pdev = tp->pci_dev;
72521ea0 6102 int rg_saw_cnt;
6e1d0b89
CHL		 6103 u32 data;
6104 static const struct ephy_info e_info_8168h_1[] = {
6105 { 0x1e, 0x0800, 0x0001 },
6106 { 0x1d, 0x0000, 0x0800 },
6107 { 0x05, 0xffff, 0x2089 },
6108 { 0x06, 0xffff, 0x5881 },
6109 { 0x04, 0xffff, 0x154a },
6110 { 0x01, 0xffff, 0x068b }
6111 };
6112
6113 /* disable aspm and clock request before access ephy */
6114 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6115 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6116 rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));
6117
6118 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6119
6120 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
6121 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
6122 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
6123 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6124
6125 rtl_csi_access_enable_1(tp);
6126
6127 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6128
706123d0
CHL		 6129 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6130 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6e1d0b89 6131
706123d0 6132 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);
6e1d0b89 6133
706123d0 6134 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);
6e1d0b89
CHL		 6135
6136 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
6137
6e1d0b89
CHL		 6138 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
6139 RTL_W8(MaxTxPacketSize, EarlySize);
6140
6141 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6142 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6143
6144 /* Adjust EEE LED frequency */
6145 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6146
6147 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
69f3dc37 6148 RTL_W8(MISC_1, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
6e1d0b89
CHL		 6149
6150 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~TX_10M_PS_EN);
6151
706123d0 6152 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
6e1d0b89
CHL		 6153
6154 rtl_pcie_state_l2l3_enable(tp, false);
6155
6156 rtl_writephy(tp, 0x1f, 0x0c42);
58493333 6157 rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
6e1d0b89
CHL		 6158 rtl_writephy(tp, 0x1f, 0x0000);
6159 if (rg_saw_cnt > 0) {
6160 u16 sw_cnt_1ms_ini;
6161
6162 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
6163 sw_cnt_1ms_ini &= 0x0fff;
6164 data = r8168_mac_ocp_read(tp, 0xd412);
a2cb7ec0 6165 data &= ~0x0fff;
6e1d0b89
CHL		 6166 data |= sw_cnt_1ms_ini;
6167 r8168_mac_ocp_write(tp, 0xd412, data);
6168 }
6169
6170 data = r8168_mac_ocp_read(tp, 0xe056);
a2cb7ec0
CHL		 6171 data &= ~0xf0;
6172 data |= 0x70;
6e1d0b89
CHL		 6173 r8168_mac_ocp_write(tp, 0xe056, data);
6174
6175 data = r8168_mac_ocp_read(tp, 0xe052);
a2cb7ec0
CHL		 6176 data &= ~0x6000;
6177 data |= 0x8008;
6e1d0b89
CHL		 6178 r8168_mac_ocp_write(tp, 0xe052, data);
6179
6180 data = r8168_mac_ocp_read(tp, 0xe0d6);
a2cb7ec0 6181 data &= ~0x01ff;
6e1d0b89
CHL		 6182 data |= 0x017f;
6183 r8168_mac_ocp_write(tp, 0xe0d6, data);
6184
6185 data = r8168_mac_ocp_read(tp, 0xd420);
a2cb7ec0 6186 data &= ~0x0fff;
6e1d0b89
CHL		 6187 data |= 0x047f;
6188 r8168_mac_ocp_write(tp, 0xd420, data);
6189
6190 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
6191 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
6192 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
6193 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
6194}
6195
935e2218
CHL		 6196static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
6197{
6198 void __iomem *ioaddr = tp->mmio_addr;
6199 struct pci_dev *pdev = tp->pci_dev;
6200
003609da
CHL		 6201 rtl8168ep_stop_cmac(tp);
6202
935e2218
CHL		 6203 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6204
6205 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
6206 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x2f, ERIAR_EXGMAC);
6207 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x5f, ERIAR_EXGMAC);
6208 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6209
6210 rtl_csi_access_enable_1(tp);
6211
6212 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6213
6214 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6215 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6216
6217 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f80, 0x00, ERIAR_EXGMAC);
6218
6219 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
6220
935e2218
CHL		 6221 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
6222 RTL_W8(MaxTxPacketSize, EarlySize);
6223
6224 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6225 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6226
6227 /* Adjust EEE LED frequency */
6228 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6229
6230 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
6231
6232 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~TX_10M_PS_EN);
6233
6234 rtl_pcie_state_l2l3_enable(tp, false);
6235}
6236
6237static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
6238{
6239 void __iomem *ioaddr = tp->mmio_addr;
6240 static const struct ephy_info e_info_8168ep_1[] = {
6241 { 0x00, 0xffff, 0x10ab },
6242 { 0x06, 0xffff, 0xf030 },
6243 { 0x08, 0xffff, 0x2006 },
6244 { 0x0d, 0xffff, 0x1666 },
6245 { 0x0c, 0x3ff0, 0x0000 }
6246 };
6247
6248 /* disable aspm and clock request before access ephy */
6249 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6250 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6251 rtl_ephy_init(tp, e_info_8168ep_1, ARRAY_SIZE(e_info_8168ep_1));
6252
6253 rtl_hw_start_8168ep(tp);
6254}
6255
6256static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
6257{
6258 void __iomem *ioaddr = tp->mmio_addr;
6259 static const struct ephy_info e_info_8168ep_2[] = {
6260 { 0x00, 0xffff, 0x10a3 },
6261 { 0x19, 0xffff, 0xfc00 },
6262 { 0x1e, 0xffff, 0x20ea }
6263 };
6264
6265 /* disable aspm and clock request before access ephy */
6266 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6267 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6268 rtl_ephy_init(tp, e_info_8168ep_2, ARRAY_SIZE(e_info_8168ep_2));
6269
6270 rtl_hw_start_8168ep(tp);
6271
6272 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
69f3dc37 6273 RTL_W8(MISC_1, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
935e2218
CHL		 6274}
6275
6276static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
6277{
6278 void __iomem *ioaddr = tp->mmio_addr;
6279 u32 data;
6280 static const struct ephy_info e_info_8168ep_3[] = {
6281 { 0x00, 0xffff, 0x10a3 },
6282 { 0x19, 0xffff, 0x7c00 },
6283 { 0x1e, 0xffff, 0x20eb },
6284 { 0x0d, 0xffff, 0x1666 }
6285 };
6286
6287 /* disable aspm and clock request before access ephy */
6288 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6289 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6290 rtl_ephy_init(tp, e_info_8168ep_3, ARRAY_SIZE(e_info_8168ep_3));
6291
6292 rtl_hw_start_8168ep(tp);
6293
6294 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
69f3dc37 6295 RTL_W8(MISC_1, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
935e2218
CHL		 6296
6297 data = r8168_mac_ocp_read(tp, 0xd3e2);
6298 data &= 0xf000;
6299 data |= 0x0271;
6300 r8168_mac_ocp_write(tp, 0xd3e2, data);
6301
6302 data = r8168_mac_ocp_read(tp, 0xd3e4);
6303 data &= 0xff00;
6304 r8168_mac_ocp_write(tp, 0xd3e4, data);
6305
6306 data = r8168_mac_ocp_read(tp, 0xe860);
6307 data |= 0x0080;
6308 r8168_mac_ocp_write(tp, 0xe860, data);
6309}
6310
07ce4064
FR		 6311static void rtl_hw_start_8168(struct net_device *dev)
6312{
2dd99530
FR		 6313 struct rtl8169_private *tp = netdev_priv(dev);
6314 void __iomem *ioaddr = tp->mmio_addr;
6315
6316 RTL_W8(Cfg9346, Cfg9346_Unlock);
6317
f0298f81 6318 RTL_W8(MaxTxPacketSize, TxPacketMax);
2dd99530 6319
6f0333b8 6320 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
2dd99530 6321
0e485150 6322 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 6323
6324 RTL_W16(CPlusCmd, tp->cp_cmd);
6325
0e485150 6326 RTL_W16(IntrMitigate, 0x5151);
2dd99530 6327
0e485150 6328 /* Work around for RxFIFO overflow. */
811fd301 6329 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
da78dbff
FR		 6330 tp->event_slow |= RxFIFOOver | PCSTimeout;
6331 tp->event_slow &= ~RxOverflow;
0e485150
FR		 6332 }
6333
6334 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530 6335
1a964649 6336 rtl_set_rx_tx_config_registers(tp);
2dd99530
FR		 6337
6338 RTL_R8(IntrMask);
6339
219a1e9d
FR		 6340 switch (tp->mac_version) {
6341 case RTL_GIGA_MAC_VER_11:
beb1fe18 6342 rtl_hw_start_8168bb(tp);
4804b3b3 6343 break;
219a1e9d
FR		 6344
6345 case RTL_GIGA_MAC_VER_12:
6346 case RTL_GIGA_MAC_VER_17:
beb1fe18 6347 rtl_hw_start_8168bef(tp);
4804b3b3 6348 break;
219a1e9d
FR		 6349
6350 case RTL_GIGA_MAC_VER_18:
beb1fe18 6351 rtl_hw_start_8168cp_1(tp);
4804b3b3 6352 break;
219a1e9d
FR		 6353
6354 case RTL_GIGA_MAC_VER_19:
beb1fe18 6355 rtl_hw_start_8168c_1(tp);
4804b3b3 6356 break;
219a1e9d
FR		 6357
6358 case RTL_GIGA_MAC_VER_20:
beb1fe18 6359 rtl_hw_start_8168c_2(tp);
4804b3b3 6360 break;
219a1e9d 6361
197ff761 6362 case RTL_GIGA_MAC_VER_21:
beb1fe18 6363 rtl_hw_start_8168c_3(tp);
4804b3b3 6364 break;
197ff761 6365
6fb07058 6366 case RTL_GIGA_MAC_VER_22:
beb1fe18 6367 rtl_hw_start_8168c_4(tp);
4804b3b3 6368 break;
6fb07058 6369
ef3386f0 6370 case RTL_GIGA_MAC_VER_23:
beb1fe18 6371 rtl_hw_start_8168cp_2(tp);
4804b3b3 6372 break;
ef3386f0 6373
7f3e3d3a 6374 case RTL_GIGA_MAC_VER_24:
beb1fe18 6375 rtl_hw_start_8168cp_3(tp);
4804b3b3 6376 break;
7f3e3d3a 6377
5b538df9 6378 case RTL_GIGA_MAC_VER_25:
daf9df6d 6379 case RTL_GIGA_MAC_VER_26:
6380 case RTL_GIGA_MAC_VER_27:
beb1fe18 6381 rtl_hw_start_8168d(tp);
4804b3b3 6382 break;
5b538df9 6383
e6de30d6 6384 case RTL_GIGA_MAC_VER_28:
beb1fe18 6385 rtl_hw_start_8168d_4(tp);
4804b3b3 6386 break;
cecb5fd7 6387
4804b3b3 6388 case RTL_GIGA_MAC_VER_31:
beb1fe18 6389 rtl_hw_start_8168dp(tp);
4804b3b3 6390 break;
6391
01dc7fec 6392 case RTL_GIGA_MAC_VER_32:
6393 case RTL_GIGA_MAC_VER_33:
beb1fe18 6394 rtl_hw_start_8168e_1(tp);
70090424
HW		 6395 break;
6396 case RTL_GIGA_MAC_VER_34:
beb1fe18 6397 rtl_hw_start_8168e_2(tp);
01dc7fec 6398 break;
e6de30d6 6399
c2218925
HW		 6400 case RTL_GIGA_MAC_VER_35:
6401 case RTL_GIGA_MAC_VER_36:
beb1fe18 6402 rtl_hw_start_8168f_1(tp);
c2218925
HW		 6403 break;
6404
b3d7b2f2
HW		 6405 case RTL_GIGA_MAC_VER_38:
6406 rtl_hw_start_8411(tp);
6407 break;
6408
c558386b
HW		 6409 case RTL_GIGA_MAC_VER_40:
6410 case RTL_GIGA_MAC_VER_41:
6411 rtl_hw_start_8168g_1(tp);
6412 break;
57538c4a 6413 case RTL_GIGA_MAC_VER_42:
6414 rtl_hw_start_8168g_2(tp);
6415 break;
c558386b 6416
45dd95c4 6417 case RTL_GIGA_MAC_VER_44:
6418 rtl_hw_start_8411_2(tp);
6419 break;
6420
6e1d0b89
CHL		 6421 case RTL_GIGA_MAC_VER_45:
6422 case RTL_GIGA_MAC_VER_46:
6423 rtl_hw_start_8168h_1(tp);
6424 break;
6425
935e2218
CHL		 6426 case RTL_GIGA_MAC_VER_49:
6427 rtl_hw_start_8168ep_1(tp);
6428 break;
6429
6430 case RTL_GIGA_MAC_VER_50:
6431 rtl_hw_start_8168ep_2(tp);
6432 break;
6433
6434 case RTL_GIGA_MAC_VER_51:
6435 rtl_hw_start_8168ep_3(tp);
6436 break;
6437
219a1e9d
FR		 6438 default:
6439 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
6440 dev->name, tp->mac_version);
4804b3b3 6441 break;
219a1e9d 6442 }
2dd99530 6443
1a964649 6444 RTL_W8(Cfg9346, Cfg9346_Lock);
6445
0e485150
FR		 6446 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
6447
1a964649 6448 rtl_set_rx_mode(dev);
b8363901 6449
05b9687b 6450 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
07ce4064 6451}
1da177e4 6452
2857ffb7
FR		 6453#define R810X_CPCMD_QUIRK_MASK (\
6454 EnableBist | \
6455 Mac_dbgo_oe | \
6456 Force_half_dup | \
5edcc537 6457 Force_rxflow_en | \
2857ffb7
FR		 6458 Force_txflow_en | \
6459 Cxpl_dbg_sel | \
6460 ASF | \
6461 PktCntrDisable | \
d24e9aaf 6462 Mac_dbgo_sel)
2857ffb7 6463
beb1fe18 6464static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
2857ffb7 6465{
beb1fe18
HW		 6466 void __iomem *ioaddr = tp->mmio_addr;
6467 struct pci_dev *pdev = tp->pci_dev;
350f7596 6468 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 6469 { 0x01, 0, 0x6e65 },
6470 { 0x02, 0, 0x091f },
6471 { 0x03, 0, 0xc2f9 },
6472 { 0x06, 0, 0xafb5 },
6473 { 0x07, 0, 0x0e00 },
6474 { 0x19, 0, 0xec80 },
6475 { 0x01, 0, 0x2e65 },
6476 { 0x01, 0, 0x6e65 }
6477 };
6478 u8 cfg1;
6479
beb1fe18 6480 rtl_csi_access_enable_2(tp);
2857ffb7
FR		 6481
6482 RTL_W8(DBG_REG, FIX_NAK_1);
6483
6484 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6485
6486 RTL_W8(Config1,
6487 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
6488 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
6489
6490 cfg1 = RTL_R8(Config1);
6491 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
6492 RTL_W8(Config1, cfg1 & ~LEDS0);
6493
fdf6fc06 6494 rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
2857ffb7
FR		 6495}
6496
beb1fe18 6497static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
2857ffb7 6498{
beb1fe18
HW		 6499 void __iomem *ioaddr = tp->mmio_addr;
6500 struct pci_dev *pdev = tp->pci_dev;
6501
6502 rtl_csi_access_enable_2(tp);
2857ffb7
FR		 6503
6504 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6505
6506 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
6507 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2857ffb7
FR		 6508}
6509
beb1fe18 6510static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
2857ffb7 6511{
beb1fe18 6512 rtl_hw_start_8102e_2(tp);
2857ffb7 6513
fdf6fc06 6514 rtl_ephy_write(tp, 0x03, 0xc2f9);
2857ffb7
FR		 6515}
6516
beb1fe18 6517static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5a5e4443 6518{
beb1fe18 6519 void __iomem *ioaddr = tp->mmio_addr;
5a5e4443
HW		 6520 static const struct ephy_info e_info_8105e_1[] = {
6521 { 0x07, 0, 0x4000 },
6522 { 0x19, 0, 0x0200 },
6523 { 0x19, 0, 0x0020 },
6524 { 0x1e, 0, 0x2000 },
6525 { 0x03, 0, 0x0001 },
6526 { 0x19, 0, 0x0100 },
6527 { 0x19, 0, 0x0004 },
6528 { 0x0a, 0, 0x0020 }
6529 };
6530
cecb5fd7 6531 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5a5e4443
HW		 6532 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6533
cecb5fd7 6534 /* Disable Early Tally Counter */
5a5e4443
HW		 6535 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
6536
6537 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4f6b00e5 6538 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5a5e4443 6539
fdf6fc06 6540 rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
b51ecea8 6541
6542 rtl_pcie_state_l2l3_enable(tp, false);
5a5e4443
HW		 6543}
6544
beb1fe18 6545static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5a5e4443 6546{
beb1fe18 6547 rtl_hw_start_8105e_1(tp);
fdf6fc06 6548 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5a5e4443
HW		 6549}
6550
7e18dca1
HW		 6551static void rtl_hw_start_8402(struct rtl8169_private *tp)
6552{
6553 void __iomem *ioaddr = tp->mmio_addr;
6554 static const struct ephy_info e_info_8402[] = {
6555 { 0x19, 0xffff, 0xff64 },
6556 { 0x1e, 0, 0x4000 }
6557 };
6558
6559 rtl_csi_access_enable_2(tp);
6560
6561 /* Force LAN exit from ASPM if Rx/Tx are not idle */
6562 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6563
6564 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6565 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
6566
fdf6fc06 6567 rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
7e18dca1
HW		 6568
6569 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
6570
fdf6fc06
FR		 6571 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
6572 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
706123d0
CHL		 6573 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6574 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
fdf6fc06
FR		 6575 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6576 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
706123d0 6577 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
b51ecea8 6578
6579 rtl_pcie_state_l2l3_enable(tp, false);
7e18dca1
HW		 6580}
6581
5598bfe5
HW		 6582static void rtl_hw_start_8106(struct rtl8169_private *tp)
6583{
6584 void __iomem *ioaddr = tp->mmio_addr;
6585
6586 /* Force LAN exit from ASPM if Rx/Tx are not idle */
6587 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6588
4521e1a9 6589 RTL_W32(MISC, (RTL_R32(MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5598bfe5
HW		 6590 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
6591 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
b51ecea8 6592
6593 rtl_pcie_state_l2l3_enable(tp, false);
5598bfe5
HW		 6594}
6595
07ce4064
FR		 6596static void rtl_hw_start_8101(struct net_device *dev)
6597{
cdf1a608
FR		 6598 struct rtl8169_private *tp = netdev_priv(dev);
6599 void __iomem *ioaddr = tp->mmio_addr;
6600 struct pci_dev *pdev = tp->pci_dev;
6601
da78dbff
FR		 6602 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
6603 tp->event_slow &= ~RxFIFOOver;
811fd301 6604
cecb5fd7 6605 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
7d7903b2 6606 tp->mac_version == RTL_GIGA_MAC_VER_16)
8200bc72
BH		 6607 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL,
6608 PCI_EXP_DEVCTL_NOSNOOP_EN);
cdf1a608 6609
d24e9aaf
HW		 6610 RTL_W8(Cfg9346, Cfg9346_Unlock);
6611
1a964649 6612 RTL_W8(MaxTxPacketSize, TxPacketMax);
6613
6614 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
6615
6616 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
6617 RTL_W16(CPlusCmd, tp->cp_cmd);
6618
6619 rtl_set_rx_tx_desc_registers(tp, ioaddr);
6620
6621 rtl_set_rx_tx_config_registers(tp);
6622
2857ffb7
FR		 6623 switch (tp->mac_version) {
6624 case RTL_GIGA_MAC_VER_07:
beb1fe18 6625 rtl_hw_start_8102e_1(tp);
2857ffb7
FR		 6626 break;
6627
6628 case RTL_GIGA_MAC_VER_08:
beb1fe18 6629 rtl_hw_start_8102e_3(tp);
2857ffb7
FR		 6630 break;
6631
6632 case RTL_GIGA_MAC_VER_09:
beb1fe18 6633 rtl_hw_start_8102e_2(tp);
2857ffb7 6634 break;
5a5e4443
HW		 6635
6636 case RTL_GIGA_MAC_VER_29:
beb1fe18 6637 rtl_hw_start_8105e_1(tp);
5a5e4443
HW		 6638 break;
6639 case RTL_GIGA_MAC_VER_30:
beb1fe18 6640 rtl_hw_start_8105e_2(tp);
5a5e4443 6641 break;
7e18dca1
HW		 6642
6643 case RTL_GIGA_MAC_VER_37:
6644 rtl_hw_start_8402(tp);
6645 break;
5598bfe5
HW		 6646
6647 case RTL_GIGA_MAC_VER_39:
6648 rtl_hw_start_8106(tp);
6649 break;
58152cd4 6650 case RTL_GIGA_MAC_VER_43:
6651 rtl_hw_start_8168g_2(tp);
6652 break;
6e1d0b89
CHL		 6653 case RTL_GIGA_MAC_VER_47:
6654 case RTL_GIGA_MAC_VER_48:
6655 rtl_hw_start_8168h_1(tp);
6656 break;
cdf1a608
FR		 6657 }
6658
d24e9aaf 6659 RTL_W8(Cfg9346, Cfg9346_Lock);
cdf1a608 6660
cdf1a608
FR		 6661 RTL_W16(IntrMitigate, 0x0000);
6662
cdf1a608 6663 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
cdf1a608 6664
cdf1a608
FR		 6665 rtl_set_rx_mode(dev);
6666
1a964649 6667 RTL_R8(IntrMask);
6668
cdf1a608 6669 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
1da177e4
LT		 6670}
6671
6672static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
6673{
d58d46b5
FR		 6674 struct rtl8169_private *tp = netdev_priv(dev);
6675
d58d46b5
FR		 6676 if (new_mtu > ETH_DATA_LEN)
6677 rtl_hw_jumbo_enable(tp);
6678 else
6679 rtl_hw_jumbo_disable(tp);
6680
1da177e4 6681 dev->mtu = new_mtu;
350fb32a
MM		 6682 netdev_update_features(dev);
6683
323bb685 6684 return 0;
1da177e4
LT		 6685}
6686
6687static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
6688{
95e0918d 6689 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 6690 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
6691}
6692
6f0333b8
ED		 6693static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
6694 void **data_buff, struct RxDesc *desc)
1da177e4 6695{
48addcc9 6696 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
231aee63 6697 DMA_FROM_DEVICE);
48addcc9 6698
6f0333b8
ED		 6699 kfree(*data_buff);
6700 *data_buff = NULL;
1da177e4
LT		 6701 rtl8169_make_unusable_by_asic(desc);
6702}
6703
6704static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
6705{
6706 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
6707
a0750138
AD		 6708 /* Force memory writes to complete before releasing descriptor */
6709 dma_wmb();
6710
1da177e4
LT		 6711 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
6712}
6713
6714static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
6715 u32 rx_buf_sz)
6716{
6717 desc->addr = cpu_to_le64(mapping);
1da177e4
LT		 6718 rtl8169_mark_to_asic(desc, rx_buf_sz);
6719}
6720
6f0333b8
ED		 6721static inline void *rtl8169_align(void *data)
6722{
6723 return (void *)ALIGN((long)data, 16);
6724}
6725
0ecbe1ca
SG		 6726static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
6727 struct RxDesc *desc)
1da177e4 6728{
6f0333b8 6729 void *data;
1da177e4 6730 dma_addr_t mapping;
48addcc9 6731 struct device *d = &tp->pci_dev->dev;
0ecbe1ca 6732 struct net_device *dev = tp->dev;
6f0333b8 6733 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
1da177e4 6734
6f0333b8
ED		 6735 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
6736 if (!data)
6737 return NULL;
e9f63f30 6738
6f0333b8
ED		 6739 if (rtl8169_align(data) != data) {
6740 kfree(data);
6741 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
6742 if (!data)
6743 return NULL;
6744 }
3eafe507 6745
48addcc9 6746 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
231aee63 6747 DMA_FROM_DEVICE);
d827d86b
SG		 6748 if (unlikely(dma_mapping_error(d, mapping))) {
6749 if (net_ratelimit())
6750 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
3eafe507 6751 goto err_out;
d827d86b 6752 }
1da177e4
LT		 6753
6754 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6f0333b8 6755 return data;
3eafe507
SG		 6756
6757err_out:
6758 kfree(data);
6759 return NULL;
1da177e4
LT		 6760}
6761
6762static void rtl8169_rx_clear(struct rtl8169_private *tp)
6763{
07d3f51f 6764 unsigned int i;
1da177e4
LT		 6765
6766 for (i = 0; i < NUM_RX_DESC; i++) {
6f0333b8
ED		 6767 if (tp->Rx_databuff[i]) {
6768 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
1da177e4
LT		 6769 tp->RxDescArray + i);
6770 }
6771 }
6772}
6773
0ecbe1ca 6774static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1da177e4 6775{
0ecbe1ca
SG		 6776 desc->opts1 |= cpu_to_le32(RingEnd);
6777}
5b0384f4 6778
0ecbe1ca
SG		 6779static int rtl8169_rx_fill(struct rtl8169_private *tp)
6780{
6781 unsigned int i;
1da177e4 6782
0ecbe1ca
SG		 6783 for (i = 0; i < NUM_RX_DESC; i++) {
6784 void *data;
4ae47c2d 6785
6f0333b8 6786 if (tp->Rx_databuff[i])
1da177e4 6787 continue;
bcf0bf90 6788
0ecbe1ca 6789 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6f0333b8
ED		 6790 if (!data) {
6791 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
0ecbe1ca 6792 goto err_out;
6f0333b8
ED		 6793 }
6794 tp->Rx_databuff[i] = data;
1da177e4 6795 }
1da177e4 6796
0ecbe1ca
SG		 6797 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
6798 return 0;
6799
6800err_out:
6801 rtl8169_rx_clear(tp);
6802 return -ENOMEM;
1da177e4
LT		 6803}
6804
1da177e4
LT		 6805static int rtl8169_init_ring(struct net_device *dev)
6806{
6807 struct rtl8169_private *tp = netdev_priv(dev);
6808
6809 rtl8169_init_ring_indexes(tp);
6810
6811 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
6f0333b8 6812 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
1da177e4 6813
0ecbe1ca 6814 return rtl8169_rx_fill(tp);
1da177e4
LT		 6815}
6816
48addcc9 6817static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
1da177e4
LT		 6818 struct TxDesc *desc)
6819{
6820 unsigned int len = tx_skb->len;
6821
48addcc9
SG		 6822 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
6823
1da177e4
LT		 6824 desc->opts1 = 0x00;
6825 desc->opts2 = 0x00;
6826 desc->addr = 0x00;
6827 tx_skb->len = 0;
6828}
6829
3eafe507
SG		 6830static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
6831 unsigned int n)
1da177e4
LT		 6832{
6833 unsigned int i;
6834
3eafe507
SG		 6835 for (i = 0; i < n; i++) {
6836 unsigned int entry = (start + i) % NUM_TX_DESC;
1da177e4
LT		 6837 struct ring_info *tx_skb = tp->tx_skb + entry;
6838 unsigned int len = tx_skb->len;
6839
6840 if (len) {
6841 struct sk_buff *skb = tx_skb->skb;
6842
48addcc9 6843 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
1da177e4
LT		 6844 tp->TxDescArray + entry);
6845 if (skb) {
cac4b22f 6846 tp->dev->stats.tx_dropped++;
989c9ba1 6847 dev_kfree_skb_any(skb);
1da177e4
LT		 6848 tx_skb->skb = NULL;
6849 }
1da177e4
LT		 6850 }
6851 }
3eafe507
SG		 6852}
6853
6854static void rtl8169_tx_clear(struct rtl8169_private *tp)
6855{
6856 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
1da177e4
LT		 6857 tp->cur_tx = tp->dirty_tx = 0;
6858}
6859
4422bcd4 6860static void rtl_reset_work(struct rtl8169_private *tp)
1da177e4 6861{
c4028958 6862 struct net_device *dev = tp->dev;
56de414c 6863 int i;
1da177e4 6864
da78dbff
FR		 6865 napi_disable(&tp->napi);
6866 netif_stop_queue(dev);
6867 synchronize_sched();
1da177e4 6868
c7c2c39b 6869 rtl8169_hw_reset(tp);
6870
56de414c
FR		 6871 for (i = 0; i < NUM_RX_DESC; i++)
6872 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
6873
1da177e4 6874 rtl8169_tx_clear(tp);
c7c2c39b 6875 rtl8169_init_ring_indexes(tp);
1da177e4 6876
da78dbff 6877 napi_enable(&tp->napi);
56de414c
FR		 6878 rtl_hw_start(dev);
6879 netif_wake_queue(dev);
6880 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1da177e4
LT		 6881}
6882
6883static void rtl8169_tx_timeout(struct net_device *dev)
6884{
da78dbff
FR		 6885 struct rtl8169_private *tp = netdev_priv(dev);
6886
6887 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 6888}
6889
6890static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2b7b4318 6891 u32 *opts)
1da177e4
LT		 6892{
6893 struct skb_shared_info *info = skb_shinfo(skb);
6894 unsigned int cur_frag, entry;
6e1d0b89 6895 struct TxDesc *uninitialized_var(txd);
48addcc9 6896 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 6897
6898 entry = tp->cur_tx;
6899 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
9e903e08 6900 const skb_frag_t *frag = info->frags + cur_frag;
1da177e4
LT		 6901 dma_addr_t mapping;
6902 u32 status, len;
6903 void *addr;
6904
6905 entry = (entry + 1) % NUM_TX_DESC;
6906
6907 txd = tp->TxDescArray + entry;
9e903e08 6908 len = skb_frag_size(frag);
929f6189 6909 addr = skb_frag_address(frag);
48addcc9 6910 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
d827d86b
SG		 6911 if (unlikely(dma_mapping_error(d, mapping))) {
6912 if (net_ratelimit())
6913 netif_err(tp, drv, tp->dev,
6914 "Failed to map TX fragments DMA!\n");
3eafe507 6915 goto err_out;
d827d86b 6916 }
1da177e4 6917
cecb5fd7 6918 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318
FR		 6919 status = opts[0] | len |
6920 (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 6921
6922 txd->opts1 = cpu_to_le32(status);
2b7b4318 6923 txd->opts2 = cpu_to_le32(opts[1]);
1da177e4
LT		 6924 txd->addr = cpu_to_le64(mapping);
6925
6926 tp->tx_skb[entry].len = len;
6927 }
6928
6929 if (cur_frag) {
6930 tp->tx_skb[entry].skb = skb;
6931 txd->opts1 |= cpu_to_le32(LastFrag);
6932 }
6933
6934 return cur_frag;
3eafe507
SG		 6935
6936err_out:
6937 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
6938 return -EIO;
1da177e4
LT		 6939}
6940
b423e9ae 6941static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
6942{
6943 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
6944}
6945
e974604b 6946static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6947 struct net_device *dev);
6948/* r8169_csum_workaround()
6949 * The hw limites the value the transport offset. When the offset is out of the
6950 * range, calculate the checksum by sw.
6951 */
6952static void r8169_csum_workaround(struct rtl8169_private *tp,
6953 struct sk_buff *skb)
6954{
6955 if (skb_shinfo(skb)->gso_size) {
6956 netdev_features_t features = tp->dev->features;
6957 struct sk_buff *segs, *nskb;
6958
6959 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
6960 segs = skb_gso_segment(skb, features);
6961 if (IS_ERR(segs) || !segs)
6962 goto drop;
6963
6964 do {
6965 nskb = segs;
6966 segs = segs->next;
6967 nskb->next = NULL;
6968 rtl8169_start_xmit(nskb, tp->dev);
6969 } while (segs);
6970
eb781397 6971 dev_consume_skb_any(skb);
e974604b 6972 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6973 if (skb_checksum_help(skb) < 0)
6974 goto drop;
6975
6976 rtl8169_start_xmit(skb, tp->dev);
6977 } else {
6978 struct net_device_stats *stats;
6979
6980drop:
6981 stats = &tp->dev->stats;
6982 stats->tx_dropped++;
eb781397 6983 dev_kfree_skb_any(skb);
e974604b 6984 }
6985}
6986
6987/* msdn_giant_send_check()
6988 * According to the document of microsoft, the TCP Pseudo Header excludes the
6989 * packet length for IPv6 TCP large packets.
6990 */
6991static int msdn_giant_send_check(struct sk_buff *skb)
6992{
6993 const struct ipv6hdr *ipv6h;
6994 struct tcphdr *th;
6995 int ret;
6996
6997 ret = skb_cow_head(skb, 0);
6998 if (ret)
6999 return ret;
7000
7001 ipv6h = ipv6_hdr(skb);
7002 th = tcp_hdr(skb);
7003
7004 th->check = 0;
7005 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
7006
7007 return ret;
7008}
7009
7010static inline __be16 get_protocol(struct sk_buff *skb)
7011{
7012 __be16 protocol;
7013
7014 if (skb->protocol == htons(ETH_P_8021Q))
7015 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
7016 else
7017 protocol = skb->protocol;
7018
7019 return protocol;
7020}
7021
5888d3fc 7022static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
7023 struct sk_buff *skb, u32 *opts)
1da177e4 7024{
350fb32a
MM		 7025 u32 mss = skb_shinfo(skb)->gso_size;
7026
2b7b4318
FR		 7027 if (mss) {
7028 opts[0] |= TD_LSO;
5888d3fc 7029 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
7030 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
7031 const struct iphdr *ip = ip_hdr(skb);
7032
7033 if (ip->protocol == IPPROTO_TCP)
7034 opts[0] |= TD0_IP_CS | TD0_TCP_CS;
7035 else if (ip->protocol == IPPROTO_UDP)
7036 opts[0] |= TD0_IP_CS | TD0_UDP_CS;
7037 else
7038 WARN_ON_ONCE(1);
7039 }
7040
7041 return true;
7042}
7043
7044static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
7045 struct sk_buff *skb, u32 *opts)
7046{
bdfa4ed6 7047 u32 transport_offset = (u32)skb_transport_offset(skb);
5888d3fc 7048 u32 mss = skb_shinfo(skb)->gso_size;
7049
7050 if (mss) {
e974604b 7051 if (transport_offset > GTTCPHO_MAX) {
7052 netif_warn(tp, tx_err, tp->dev,
7053 "Invalid transport offset 0x%x for TSO\n",
7054 transport_offset);
7055 return false;
7056 }
7057
7058 switch (get_protocol(skb)) {
7059 case htons(ETH_P_IP):
7060 opts[0] |= TD1_GTSENV4;
7061 break;
7062
7063 case htons(ETH_P_IPV6):
7064 if (msdn_giant_send_check(skb))
7065 return false;
7066
7067 opts[0] |= TD1_GTSENV6;
7068 break;
7069
7070 default:
7071 WARN_ON_ONCE(1);
7072 break;
7073 }
7074
bdfa4ed6 7075 opts[0] |= transport_offset << GTTCPHO_SHIFT;
5888d3fc 7076 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
2b7b4318 7077 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
e974604b 7078 u8 ip_protocol;
1da177e4 7079
b423e9ae 7080 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
207c5f44 7081 return !(skb_checksum_help(skb) || eth_skb_pad(skb));
b423e9ae 7082
e974604b 7083 if (transport_offset > TCPHO_MAX) {
7084 netif_warn(tp, tx_err, tp->dev,
7085 "Invalid transport offset 0x%x\n",
7086 transport_offset);
7087 return false;
7088 }
7089
7090 switch (get_protocol(skb)) {
7091 case htons(ETH_P_IP):
7092 opts[1] |= TD1_IPv4_CS;
7093 ip_protocol = ip_hdr(skb)->protocol;
7094 break;
7095
7096 case htons(ETH_P_IPV6):
7097 opts[1] |= TD1_IPv6_CS;
7098 ip_protocol = ipv6_hdr(skb)->nexthdr;
7099 break;
7100
7101 default:
7102 ip_protocol = IPPROTO_RAW;
7103 break;
7104 }
7105
7106 if (ip_protocol == IPPROTO_TCP)
7107 opts[1] |= TD1_TCP_CS;
7108 else if (ip_protocol == IPPROTO_UDP)
7109 opts[1] |= TD1_UDP_CS;
2b7b4318
FR		 7110 else
7111 WARN_ON_ONCE(1);
e974604b 7112
7113 opts[1] |= transport_offset << TCPHO_SHIFT;
b423e9ae 7114 } else {
7115 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
207c5f44 7116 return !eth_skb_pad(skb);
1da177e4 7117 }
5888d3fc 7118
b423e9ae 7119 return true;
1da177e4
LT		 7120}
7121
61357325
SH		 7122static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
7123 struct net_device *dev)
1da177e4
LT		 7124{
7125 struct rtl8169_private *tp = netdev_priv(dev);
3eafe507 7126 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
1da177e4
LT		 7127 struct TxDesc *txd = tp->TxDescArray + entry;
7128 void __iomem *ioaddr = tp->mmio_addr;
48addcc9 7129 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 7130 dma_addr_t mapping;
7131 u32 status, len;
2b7b4318 7132 u32 opts[2];
3eafe507 7133 int frags;
5b0384f4 7134
477206a0 7135 if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
bf82c189 7136 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
3eafe507 7137 goto err_stop_0;
1da177e4
LT		 7138 }
7139
7140 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3eafe507
SG		 7141 goto err_stop_0;
7142
b423e9ae 7143 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
7144 opts[0] = DescOwn;
7145
e974604b 7146 if (!tp->tso_csum(tp, skb, opts)) {
7147 r8169_csum_workaround(tp, skb);
7148 return NETDEV_TX_OK;
7149 }
b423e9ae 7150
3eafe507 7151 len = skb_headlen(skb);
48addcc9 7152 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
d827d86b
SG		 7153 if (unlikely(dma_mapping_error(d, mapping))) {
7154 if (net_ratelimit())
7155 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
3eafe507 7156 goto err_dma_0;
d827d86b 7157 }
3eafe507
SG		 7158
7159 tp->tx_skb[entry].len = len;
7160 txd->addr = cpu_to_le64(mapping);
1da177e4 7161
2b7b4318 7162 frags = rtl8169_xmit_frags(tp, skb, opts);
3eafe507
SG		 7163 if (frags < 0)
7164 goto err_dma_1;
7165 else if (frags)
2b7b4318 7166 opts[0] |= FirstFrag;
3eafe507 7167 else {
2b7b4318 7168 opts[0] |= FirstFrag | LastFrag;
1da177e4
LT		 7169 tp->tx_skb[entry].skb = skb;
7170 }
7171
2b7b4318
FR		 7172 txd->opts2 = cpu_to_le32(opts[1]);
7173
5047fb5d
RC		 7174 skb_tx_timestamp(skb);
7175
a0750138
AD		 7176 /* Force memory writes to complete before releasing descriptor */
7177 dma_wmb();
1da177e4 7178
cecb5fd7 7179 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318 7180 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 7181 txd->opts1 = cpu_to_le32(status);
7182
a0750138 7183 /* Force all memory writes to complete before notifying device */
4c020a96 7184 wmb();
1da177e4 7185
a0750138
AD		 7186 tp->cur_tx += frags + 1;
7187
87cda7cb 7188 RTL_W8(TxPoll, NPQ);
1da177e4 7189
87cda7cb 7190 mmiowb();
da78dbff 7191
87cda7cb 7192 if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
ae1f23fb
FR		 7193 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
7194 * not miss a ring update when it notices a stopped queue.
7195 */
7196 smp_wmb();
1da177e4 7197 netif_stop_queue(dev);
ae1f23fb
FR		 7198 /* Sync with rtl_tx:
7199 * - publish queue status and cur_tx ring index (write barrier)
7200 * - refresh dirty_tx ring index (read barrier).
7201 * May the current thread have a pessimistic view of the ring
7202 * status and forget to wake up queue, a racing rtl_tx thread
7203 * can't.
7204 */
1e874e04 7205 smp_mb();
477206a0 7206 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
1da177e4
LT		 7207 netif_wake_queue(dev);
7208 }
7209
61357325 7210 return NETDEV_TX_OK;
1da177e4 7211
3eafe507 7212err_dma_1:
48addcc9 7213 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
3eafe507 7214err_dma_0:
989c9ba1 7215 dev_kfree_skb_any(skb);
3eafe507
SG		 7216 dev->stats.tx_dropped++;
7217 return NETDEV_TX_OK;
7218
7219err_stop_0:
1da177e4 7220 netif_stop_queue(dev);
cebf8cc7 7221 dev->stats.tx_dropped++;
61357325 7222 return NETDEV_TX_BUSY;
1da177e4
LT		 7223}
7224
7225static void rtl8169_pcierr_interrupt(struct net_device *dev)
7226{
7227 struct rtl8169_private *tp = netdev_priv(dev);
7228 struct pci_dev *pdev = tp->pci_dev;
1da177e4
LT		 7229 u16 pci_status, pci_cmd;
7230
7231 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
7232 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
7233
bf82c189
JP		 7234 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
7235 pci_cmd, pci_status);
1da177e4
LT		 7236
7237 /*
7238 * The recovery sequence below admits a very elaborated explanation:
7239 * - it seems to work;
d03902b8
FR		 7240 * - I did not see what else could be done;
7241 * - it makes iop3xx happy.
1da177e4
LT		 7242 *
7243 * Feel free to adjust to your needs.
7244 */
a27993f3 7245 if (pdev->broken_parity_status)
d03902b8
FR		 7246 pci_cmd &= ~PCI_COMMAND_PARITY;
7247 else
7248 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
7249
7250 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 7251
7252 pci_write_config_word(pdev, PCI_STATUS,
7253 pci_status & (PCI_STATUS_DETECTED_PARITY |
7254 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
7255 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
7256
7257 /* The infamous DAC f*ckup only happens at boot time */
9fba0812 7258 if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
e6de30d6 7259 void __iomem *ioaddr = tp->mmio_addr;
7260
bf82c189 7261 netif_info(tp, intr, dev, "disabling PCI DAC\n");
1da177e4
LT		 7262 tp->cp_cmd &= ~PCIDAC;
7263 RTL_W16(CPlusCmd, tp->cp_cmd);
7264 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 7265 }
7266
e6de30d6 7267 rtl8169_hw_reset(tp);
d03902b8 7268
98ddf986 7269 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 7270}
7271
da78dbff 7272static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
1da177e4
LT		 7273{
7274 unsigned int dirty_tx, tx_left;
7275
1da177e4
LT		 7276 dirty_tx = tp->dirty_tx;
7277 smp_rmb();
7278 tx_left = tp->cur_tx - dirty_tx;
7279
7280 while (tx_left > 0) {
7281 unsigned int entry = dirty_tx % NUM_TX_DESC;
7282 struct ring_info *tx_skb = tp->tx_skb + entry;
1da177e4
LT		 7283 u32 status;
7284
1da177e4
LT		 7285 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
7286 if (status & DescOwn)
7287 break;
7288
a0750138
AD		 7289 /* This barrier is needed to keep us from reading
7290 * any other fields out of the Tx descriptor until
7291 * we know the status of DescOwn
7292 */
7293 dma_rmb();
7294
48addcc9
SG		 7295 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
7296 tp->TxDescArray + entry);
1da177e4 7297 if (status & LastFrag) {
87cda7cb
DM		 7298 u64_stats_update_begin(&tp->tx_stats.syncp);
7299 tp->tx_stats.packets++;
7300 tp->tx_stats.bytes += tx_skb->skb->len;
7301 u64_stats_update_end(&tp->tx_stats.syncp);
989c9ba1 7302 dev_kfree_skb_any(tx_skb->skb);
1da177e4
LT		 7303 tx_skb->skb = NULL;
7304 }
7305 dirty_tx++;
7306 tx_left--;
7307 }
7308
7309 if (tp->dirty_tx != dirty_tx) {
7310 tp->dirty_tx = dirty_tx;
ae1f23fb
FR		 7311 /* Sync with rtl8169_start_xmit:
7312 * - publish dirty_tx ring index (write barrier)
7313 * - refresh cur_tx ring index and queue status (read barrier)
7314 * May the current thread miss the stopped queue condition,
7315 * a racing xmit thread can only have a right view of the
7316 * ring status.
7317 */
1e874e04 7318 smp_mb();
1da177e4 7319 if (netif_queue_stopped(dev) &&
477206a0 7320 TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
1da177e4
LT		 7321 netif_wake_queue(dev);
7322 }
d78ae2dc
FR		 7323 /*
7324 * 8168 hack: TxPoll requests are lost when the Tx packets are
7325 * too close. Let's kick an extra TxPoll request when a burst
7326 * of start_xmit activity is detected (if it is not detected,
7327 * it is slow enough). -- FR
7328 */
da78dbff
FR		 7329 if (tp->cur_tx != dirty_tx) {
7330 void __iomem *ioaddr = tp->mmio_addr;
7331
d78ae2dc 7332 RTL_W8(TxPoll, NPQ);
da78dbff 7333 }
1da177e4
LT		 7334 }
7335}
7336
126fa4b9
FR		 7337static inline int rtl8169_fragmented_frame(u32 status)
7338{
7339 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
7340}
7341
adea1ac7 7342static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
1da177e4 7343{
1da177e4
LT		 7344 u32 status = opts1 & RxProtoMask;
7345
7346 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
d5d3ebe3 7347 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
1da177e4
LT		 7348 skb->ip_summed = CHECKSUM_UNNECESSARY;
7349 else
bc8acf2c 7350 skb_checksum_none_assert(skb);
1da177e4
LT		 7351}
7352
6f0333b8
ED		 7353static struct sk_buff *rtl8169_try_rx_copy(void *data,
7354 struct rtl8169_private *tp,
7355 int pkt_size,
7356 dma_addr_t addr)
1da177e4 7357{
b449655f 7358 struct sk_buff *skb;
48addcc9 7359 struct device *d = &tp->pci_dev->dev;
b449655f 7360
6f0333b8 7361 data = rtl8169_align(data);
48addcc9 7362 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6f0333b8 7363 prefetch(data);
e2338f86 7364 skb = napi_alloc_skb(&tp->napi, pkt_size);
6f0333b8
ED		 7365 if (skb)
7366 memcpy(skb->data, data, pkt_size);
48addcc9
SG		 7367 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
7368
6f0333b8 7369 return skb;
1da177e4
LT		 7370}
7371
da78dbff 7372static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
1da177e4
LT		 7373{
7374 unsigned int cur_rx, rx_left;
6f0333b8 7375 unsigned int count;
1da177e4 7376
1da177e4 7377 cur_rx = tp->cur_rx;
1da177e4 7378
9fba0812 7379 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
1da177e4 7380 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 7381 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 7382 u32 status;
7383
e03f33af 7384 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
1da177e4
LT		 7385 if (status & DescOwn)
7386 break;
a0750138
AD		 7387
7388 /* This barrier is needed to keep us from reading
7389 * any other fields out of the Rx descriptor until
7390 * we know the status of DescOwn
7391 */
7392 dma_rmb();
7393
4dcb7d33 7394 if (unlikely(status & RxRES)) {
bf82c189
JP		 7395 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
7396 status);
cebf8cc7 7397 dev->stats.rx_errors++;
1da177e4 7398 if (status & (RxRWT | RxRUNT))
cebf8cc7 7399 dev->stats.rx_length_errors++;
1da177e4 7400 if (status & RxCRC)
cebf8cc7 7401 dev->stats.rx_crc_errors++;
9dccf611 7402 if (status & RxFOVF) {
da78dbff 7403 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
cebf8cc7 7404 dev->stats.rx_fifo_errors++;
9dccf611 7405 }
6bbe021d
BG		 7406 if ((status & (RxRUNT | RxCRC)) &&
7407 !(status & (RxRWT | RxFOVF)) &&
7408 (dev->features & NETIF_F_RXALL))
7409 goto process_pkt;
1da177e4 7410 } else {
6f0333b8 7411 struct sk_buff *skb;
6bbe021d
BG		 7412 dma_addr_t addr;
7413 int pkt_size;
7414
7415process_pkt:
7416 addr = le64_to_cpu(desc->addr);
79d0c1d2
BG		 7417 if (likely(!(dev->features & NETIF_F_RXFCS)))
7418 pkt_size = (status & 0x00003fff) - 4;
7419 else
7420 pkt_size = status & 0x00003fff;
1da177e4 7421
126fa4b9
FR		 7422 /*
7423 * The driver does not support incoming fragmented
7424 * frames. They are seen as a symptom of over-mtu
7425 * sized frames.
7426 */
7427 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 7428 dev->stats.rx_dropped++;
7429 dev->stats.rx_length_errors++;
ce11ff5e 7430 goto release_descriptor;
126fa4b9
FR		 7431 }
7432
6f0333b8
ED		 7433 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
7434 tp, pkt_size, addr);
6f0333b8
ED		 7435 if (!skb) {
7436 dev->stats.rx_dropped++;
ce11ff5e 7437 goto release_descriptor;
1da177e4
LT		 7438 }
7439
adea1ac7 7440 rtl8169_rx_csum(skb, status);
1da177e4
LT		 7441 skb_put(skb, pkt_size);
7442 skb->protocol = eth_type_trans(skb, dev);
7443
7a8fc77b
FR		 7444 rtl8169_rx_vlan_tag(desc, skb);
7445
39174291 7446 if (skb->pkt_type == PACKET_MULTICAST)
7447 dev->stats.multicast++;
7448
56de414c 7449 napi_gro_receive(&tp->napi, skb);
1da177e4 7450
8027aa24
JW		 7451 u64_stats_update_begin(&tp->rx_stats.syncp);
7452 tp->rx_stats.packets++;
7453 tp->rx_stats.bytes += pkt_size;
7454 u64_stats_update_end(&tp->rx_stats.syncp);
1da177e4 7455 }
ce11ff5e 7456release_descriptor:
7457 desc->opts2 = 0;
ce11ff5e 7458 rtl8169_mark_to_asic(desc, rx_buf_sz);
1da177e4
LT		 7459 }
7460
7461 count = cur_rx - tp->cur_rx;
7462 tp->cur_rx = cur_rx;
7463
1da177e4
LT		 7464 return count;
7465}
7466
07d3f51f 7467static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 7468{
07d3f51f 7469 struct net_device *dev = dev_instance;
1da177e4 7470 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 7471 int handled = 0;
9085cdfa 7472 u16 status;
1da177e4 7473
9085cdfa 7474 status = rtl_get_events(tp);
da78dbff
FR		 7475 if (status && status != 0xffff) {
7476 status &= RTL_EVENT_NAPI | tp->event_slow;
7477 if (status) {
7478 handled = 1;
1da177e4 7479
da78dbff
FR		 7480 rtl_irq_disable(tp);
7481 napi_schedule(&tp->napi);
f11a377b 7482 }
da78dbff
FR		 7483 }
7484 return IRQ_RETVAL(handled);
7485}
1da177e4 7486
da78dbff
FR		 7487/*
7488 * Workqueue context.
7489 */
7490static void rtl_slow_event_work(struct rtl8169_private *tp)
7491{
7492 struct net_device *dev = tp->dev;
7493 u16 status;
7494
7495 status = rtl_get_events(tp) & tp->event_slow;
7496 rtl_ack_events(tp, status);
1da177e4 7497
da78dbff
FR		 7498 if (unlikely(status & RxFIFOOver)) {
7499 switch (tp->mac_version) {
7500 /* Work around for rx fifo overflow */
7501 case RTL_GIGA_MAC_VER_11:
7502 netif_stop_queue(dev);
934714d0
FR		 7503 /* XXX - Hack alert. See rtl_task(). */
7504 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
da78dbff 7505 default:
f11a377b
DD		 7506 break;
7507 }
da78dbff 7508 }
1da177e4 7509
da78dbff
FR		 7510 if (unlikely(status & SYSErr))
7511 rtl8169_pcierr_interrupt(dev);
0e485150 7512
da78dbff
FR		 7513 if (status & LinkChg)
7514 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
1da177e4 7515
7dbb4918 7516 rtl_irq_enable_all(tp);
1da177e4
LT		 7517}
7518
4422bcd4
FR		 7519static void rtl_task(struct work_struct *work)
7520{
da78dbff
FR		 7521 static const struct {
7522 int bitnr;
7523 void (*action)(struct rtl8169_private *);
7524 } rtl_work[] = {
934714d0 7525 /* XXX - keep rtl_slow_event_work() as first element. */
da78dbff
FR		 7526 { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work },
7527 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
7528 { RTL_FLAG_TASK_PHY_PENDING, rtl_phy_work }
7529 };
4422bcd4
FR		 7530 struct rtl8169_private *tp =
7531 container_of(work, struct rtl8169_private, wk.work);
da78dbff
FR		 7532 struct net_device *dev = tp->dev;
7533 int i;
7534
7535 rtl_lock_work(tp);
7536
6c4a70c5
FR		 7537 if (!netif_running(dev) ||
7538 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
da78dbff
FR		 7539 goto out_unlock;
7540
7541 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
7542 bool pending;
7543
da78dbff 7544 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
da78dbff
FR		 7545 if (pending)
7546 rtl_work[i].action(tp);
7547 }
4422bcd4 7548
da78dbff
FR		 7549out_unlock:
7550 rtl_unlock_work(tp);
4422bcd4
FR		 7551}
7552
bea3348e 7553static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 7554{
bea3348e
SH		 7555 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
7556 struct net_device *dev = tp->dev;
da78dbff
FR		 7557 u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
7558 int work_done= 0;
7559 u16 status;
7560
7561 status = rtl_get_events(tp);
7562 rtl_ack_events(tp, status & ~tp->event_slow);
7563
7564 if (status & RTL_EVENT_NAPI_RX)
7565 work_done = rtl_rx(dev, tp, (u32) budget);
7566
7567 if (status & RTL_EVENT_NAPI_TX)
7568 rtl_tx(dev, tp);
1da177e4 7569
da78dbff
FR		 7570 if (status & tp->event_slow) {
7571 enable_mask &= ~tp->event_slow;
7572
7573 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
7574 }
1da177e4 7575
bea3348e 7576 if (work_done < budget) {
288379f0 7577 napi_complete(napi);
f11a377b 7578
da78dbff
FR		 7579 rtl_irq_enable(tp, enable_mask);
7580 mmiowb();
1da177e4
LT		 7581 }
7582
bea3348e 7583 return work_done;
1da177e4 7584}
1da177e4 7585
523a6094
FR		 7586static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
7587{
7588 struct rtl8169_private *tp = netdev_priv(dev);
7589
7590 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
7591 return;
7592
7593 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
7594 RTL_W32(RxMissed, 0);
7595}
7596
1da177e4
LT		 7597static void rtl8169_down(struct net_device *dev)
7598{
7599 struct rtl8169_private *tp = netdev_priv(dev);
7600 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 7601
4876cc1e 7602 del_timer_sync(&tp->timer);
1da177e4 7603
93dd79e8 7604 napi_disable(&tp->napi);
da78dbff 7605 netif_stop_queue(dev);
1da177e4 7606
92fc43b4 7607 rtl8169_hw_reset(tp);
323bb685
SG		 7608 /*
7609 * At this point device interrupts can not be enabled in any function,
209e5ac8
FR		 7610 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
7611 * and napi is disabled (rtl8169_poll).
323bb685 7612 */
523a6094 7613 rtl8169_rx_missed(dev, ioaddr);
1da177e4 7614
1da177e4 7615 /* Give a racing hard_start_xmit a few cycles to complete. */
da78dbff 7616 synchronize_sched();
1da177e4 7617
1da177e4
LT		 7618 rtl8169_tx_clear(tp);
7619
7620 rtl8169_rx_clear(tp);
065c27c1 7621
7622 rtl_pll_power_down(tp);
1da177e4
LT		 7623}
7624
7625static int rtl8169_close(struct net_device *dev)
7626{
7627 struct rtl8169_private *tp = netdev_priv(dev);
7628 struct pci_dev *pdev = tp->pci_dev;
7629
e1759441
RW		 7630 pm_runtime_get_sync(&pdev->dev);
7631
cecb5fd7 7632 /* Update counters before going down */
355423d0
IV		 7633 rtl8169_update_counters(dev);
7634
da78dbff 7635 rtl_lock_work(tp);
6c4a70c5 7636 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
da78dbff 7637
1da177e4 7638 rtl8169_down(dev);
da78dbff 7639 rtl_unlock_work(tp);
1da177e4 7640
4ea72445
L		 7641 cancel_work_sync(&tp->wk.work);
7642
92a7c4e7 7643 free_irq(pdev->irq, dev);
1da177e4 7644
82553bb6
SG		 7645 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7646 tp->RxPhyAddr);
7647 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7648 tp->TxPhyAddr);
1da177e4
LT		 7649 tp->TxDescArray = NULL;
7650 tp->RxDescArray = NULL;
7651
e1759441
RW		 7652 pm_runtime_put_sync(&pdev->dev);
7653
1da177e4
LT		 7654 return 0;
7655}
7656
dc1c00ce
FR		 7657#ifdef CONFIG_NET_POLL_CONTROLLER
7658static void rtl8169_netpoll(struct net_device *dev)
7659{
7660 struct rtl8169_private *tp = netdev_priv(dev);
7661
7662 rtl8169_interrupt(tp->pci_dev->irq, dev);
7663}
7664#endif
7665
df43ac78
FR		 7666static int rtl_open(struct net_device *dev)
7667{
7668 struct rtl8169_private *tp = netdev_priv(dev);
7669 void __iomem *ioaddr = tp->mmio_addr;
7670 struct pci_dev *pdev = tp->pci_dev;
7671 int retval = -ENOMEM;
7672
7673 pm_runtime_get_sync(&pdev->dev);
7674
7675 /*
e75d6606 7676 * Rx and Tx descriptors needs 256 bytes alignment.
df43ac78
FR		 7677 * dma_alloc_coherent provides more.
7678 */
7679 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
7680 &tp->TxPhyAddr, GFP_KERNEL);
7681 if (!tp->TxDescArray)
7682 goto err_pm_runtime_put;
7683
7684 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
7685 &tp->RxPhyAddr, GFP_KERNEL);
7686 if (!tp->RxDescArray)
7687 goto err_free_tx_0;
7688
7689 retval = rtl8169_init_ring(dev);
7690 if (retval < 0)
7691 goto err_free_rx_1;
7692
7693 INIT_WORK(&tp->wk.work, rtl_task);
7694
7695 smp_mb();
7696
7697 rtl_request_firmware(tp);
7698
92a7c4e7 7699 retval = request_irq(pdev->irq, rtl8169_interrupt,
df43ac78
FR		 7700 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
7701 dev->name, dev);
7702 if (retval < 0)
7703 goto err_release_fw_2;
7704
7705 rtl_lock_work(tp);
7706
7707 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7708
7709 napi_enable(&tp->napi);
7710
7711 rtl8169_init_phy(dev, tp);
7712
7713 __rtl8169_set_features(dev, dev->features);
7714
7715 rtl_pll_power_up(tp);
7716
7717 rtl_hw_start(dev);
7718
6e85d5ad
CV		 7719 if (!rtl8169_init_counter_offsets(dev))
7720 netif_warn(tp, hw, dev, "counter reset/update failed\n");
7721
df43ac78
FR		 7722 netif_start_queue(dev);
7723
7724 rtl_unlock_work(tp);
7725
7726 tp->saved_wolopts = 0;
7727 pm_runtime_put_noidle(&pdev->dev);
7728
7729 rtl8169_check_link_status(dev, tp, ioaddr);
7730out:
7731 return retval;
7732
7733err_release_fw_2:
7734 rtl_release_firmware(tp);
7735 rtl8169_rx_clear(tp);
7736err_free_rx_1:
7737 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7738 tp->RxPhyAddr);
7739 tp->RxDescArray = NULL;
7740err_free_tx_0:
7741 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7742 tp->TxPhyAddr);
7743 tp->TxDescArray = NULL;
7744err_pm_runtime_put:
7745 pm_runtime_put_noidle(&pdev->dev);
7746 goto out;
7747}
7748
8027aa24
JW		 7749static struct rtnl_link_stats64 *
7750rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
1da177e4
LT		 7751{
7752 struct rtl8169_private *tp = netdev_priv(dev);
7753 void __iomem *ioaddr = tp->mmio_addr;
f09cf4b7 7754 struct pci_dev *pdev = tp->pci_dev;
42020320 7755 struct rtl8169_counters *counters = tp->counters;
8027aa24 7756 unsigned int start;
1da177e4 7757
f09cf4b7
CHL		 7758 pm_runtime_get_noresume(&pdev->dev);
7759
7760 if (netif_running(dev) && pm_runtime_active(&pdev->dev))
523a6094 7761 rtl8169_rx_missed(dev, ioaddr);
5b0384f4 7762
8027aa24 7763 do {
57a7744e 7764 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
8027aa24
JW		 7765 stats->rx_packets = tp->rx_stats.packets;
7766 stats->rx_bytes = tp->rx_stats.bytes;
57a7744e 7767 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
8027aa24 7768
8027aa24 7769 do {
57a7744e 7770 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
8027aa24
JW		 7771 stats->tx_packets = tp->tx_stats.packets;
7772 stats->tx_bytes = tp->tx_stats.bytes;
57a7744e 7773 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
8027aa24
JW		 7774
7775 stats->rx_dropped = dev->stats.rx_dropped;
7776 stats->tx_dropped = dev->stats.tx_dropped;
7777 stats->rx_length_errors = dev->stats.rx_length_errors;
7778 stats->rx_errors = dev->stats.rx_errors;
7779 stats->rx_crc_errors = dev->stats.rx_crc_errors;
7780 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
7781 stats->rx_missed_errors = dev->stats.rx_missed_errors;
d7d2d89d 7782 stats->multicast = dev->stats.multicast;
8027aa24 7783
6e85d5ad
CV		 7784 /*
7785 * Fetch additonal counter values missing in stats collected by driver
7786 * from tally counters.
7787 */
f09cf4b7
CHL		 7788 if (pm_runtime_active(&pdev->dev))
7789 rtl8169_update_counters(dev);
6e85d5ad
CV		 7790
7791 /*
7792 * Subtract values fetched during initalization.
7793 * See rtl8169_init_counter_offsets for a description why we do that.
7794 */
42020320 7795 stats->tx_errors = le64_to_cpu(counters->tx_errors) -
6e85d5ad 7796 le64_to_cpu(tp->tc_offset.tx_errors);
42020320 7797 stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
6e85d5ad 7798 le32_to_cpu(tp->tc_offset.tx_multi_collision);
42020320 7799 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
6e85d5ad
CV		 7800 le16_to_cpu(tp->tc_offset.tx_aborted);
7801
f09cf4b7
CHL		 7802 pm_runtime_put_noidle(&pdev->dev);
7803
8027aa24 7804 return stats;
1da177e4
LT		 7805}
7806
861ab440 7807static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 7808{
065c27c1 7809 struct rtl8169_private *tp = netdev_priv(dev);
7810
5d06a99f 7811 if (!netif_running(dev))
861ab440 7812 return;
5d06a99f
FR		 7813
7814 netif_device_detach(dev);
7815 netif_stop_queue(dev);
da78dbff
FR		 7816
7817 rtl_lock_work(tp);
7818 napi_disable(&tp->napi);
6c4a70c5 7819 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
da78dbff
FR		 7820 rtl_unlock_work(tp);
7821
7822 rtl_pll_power_down(tp);
861ab440
RW		 7823}
7824
7825#ifdef CONFIG_PM
7826
7827static int rtl8169_suspend(struct device *device)
7828{
7829 struct pci_dev *pdev = to_pci_dev(device);
7830 struct net_device *dev = pci_get_drvdata(pdev);
5d06a99f 7831
861ab440 7832 rtl8169_net_suspend(dev);
1371fa6d 7833
5d06a99f
FR		 7834 return 0;
7835}
7836
e1759441
RW		 7837static void __rtl8169_resume(struct net_device *dev)
7838{
065c27c1 7839 struct rtl8169_private *tp = netdev_priv(dev);
7840
e1759441 7841 netif_device_attach(dev);
065c27c1 7842
7843 rtl_pll_power_up(tp);
7844
cff4c162
AS		 7845 rtl_lock_work(tp);
7846 napi_enable(&tp->napi);
6c4a70c5 7847 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
cff4c162 7848 rtl_unlock_work(tp);
da78dbff 7849
98ddf986 7850 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
e1759441
RW		 7851}
7852
861ab440 7853static int rtl8169_resume(struct device *device)
5d06a99f 7854{
861ab440 7855 struct pci_dev *pdev = to_pci_dev(device);
5d06a99f 7856 struct net_device *dev = pci_get_drvdata(pdev);
fccec10b
SG		 7857 struct rtl8169_private *tp = netdev_priv(dev);
7858
7859 rtl8169_init_phy(dev, tp);
5d06a99f 7860
e1759441
RW		 7861 if (netif_running(dev))
7862 __rtl8169_resume(dev);
5d06a99f 7863
e1759441
RW		 7864 return 0;
7865}
7866
7867static int rtl8169_runtime_suspend(struct device *device)
7868{
7869 struct pci_dev *pdev = to_pci_dev(device);
7870 struct net_device *dev = pci_get_drvdata(pdev);
7871 struct rtl8169_private *tp = netdev_priv(dev);
7872
7873 if (!tp->TxDescArray)
7874 return 0;
7875
da78dbff 7876 rtl_lock_work(tp);
e1759441
RW		 7877 tp->saved_wolopts = __rtl8169_get_wol(tp);
7878 __rtl8169_set_wol(tp, WAKE_ANY);
da78dbff 7879 rtl_unlock_work(tp);
e1759441
RW		 7880
7881 rtl8169_net_suspend(dev);
7882
f09cf4b7
CHL		 7883 /* Update counters before going runtime suspend */
7884 rtl8169_rx_missed(dev, tp->mmio_addr);
7885 rtl8169_update_counters(dev);
7886
e1759441
RW		 7887 return 0;
7888}
7889
7890static int rtl8169_runtime_resume(struct device *device)
7891{
7892 struct pci_dev *pdev = to_pci_dev(device);
7893 struct net_device *dev = pci_get_drvdata(pdev);
7894 struct rtl8169_private *tp = netdev_priv(dev);
f51d4a10 7895 rtl_rar_set(tp, dev->dev_addr);
e1759441
RW		 7896
7897 if (!tp->TxDescArray)
7898 return 0;
7899
da78dbff 7900 rtl_lock_work(tp);
e1759441
RW		 7901 __rtl8169_set_wol(tp, tp->saved_wolopts);
7902 tp->saved_wolopts = 0;
da78dbff 7903 rtl_unlock_work(tp);
e1759441 7904
fccec10b
SG		 7905 rtl8169_init_phy(dev, tp);
7906
e1759441 7907 __rtl8169_resume(dev);
5d06a99f 7908
5d06a99f
FR		 7909 return 0;
7910}
7911
e1759441
RW		 7912static int rtl8169_runtime_idle(struct device *device)
7913{
7914 struct pci_dev *pdev = to_pci_dev(device);
7915 struct net_device *dev = pci_get_drvdata(pdev);
7916 struct rtl8169_private *tp = netdev_priv(dev);
7917
e4fbce74 7918 return tp->TxDescArray ? -EBUSY : 0;
e1759441
RW		 7919}
7920
47145210 7921static const struct dev_pm_ops rtl8169_pm_ops = {
cecb5fd7
FR		 7922 .suspend = rtl8169_suspend,
7923 .resume = rtl8169_resume,
7924 .freeze = rtl8169_suspend,
7925 .thaw = rtl8169_resume,
7926 .poweroff = rtl8169_suspend,
7927 .restore = rtl8169_resume,
7928 .runtime_suspend = rtl8169_runtime_suspend,
7929 .runtime_resume = rtl8169_runtime_resume,
7930 .runtime_idle = rtl8169_runtime_idle,
861ab440
RW		 7931};
7932
7933#define RTL8169_PM_OPS (&rtl8169_pm_ops)
7934
7935#else /* !CONFIG_PM */
7936
7937#define RTL8169_PM_OPS NULL
7938
7939#endif /* !CONFIG_PM */
7940
649b3b8c 7941static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
7942{
7943 void __iomem *ioaddr = tp->mmio_addr;
7944
7945 /* WoL fails with 8168b when the receiver is disabled. */
7946 switch (tp->mac_version) {
7947 case RTL_GIGA_MAC_VER_11:
7948 case RTL_GIGA_MAC_VER_12:
7949 case RTL_GIGA_MAC_VER_17:
7950 pci_clear_master(tp->pci_dev);
7951
7952 RTL_W8(ChipCmd, CmdRxEnb);
7953 /* PCI commit */
7954 RTL_R8(ChipCmd);
7955 break;
7956 default:
7957 break;
7958 }
7959}
7960
1765f95d
FR		 7961static void rtl_shutdown(struct pci_dev *pdev)
7962{
861ab440 7963 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 7964 struct rtl8169_private *tp = netdev_priv(dev);
2a15cd2f 7965 struct device *d = &pdev->dev;
7966
7967 pm_runtime_get_sync(d);
861ab440
RW		 7968
7969 rtl8169_net_suspend(dev);
1765f95d 7970
cecb5fd7 7971 /* Restore original MAC address */
cc098dc7
IV		 7972 rtl_rar_set(tp, dev->perm_addr);
7973
92fc43b4 7974 rtl8169_hw_reset(tp);
4bb3f522 7975
861ab440 7976 if (system_state == SYSTEM_POWER_OFF) {
649b3b8c 7977 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
7978 rtl_wol_suspend_quirk(tp);
7979 rtl_wol_shutdown_quirk(tp);
ca52efd5 7980 }
7981
861ab440
RW		 7982 pci_wake_from_d3(pdev, true);
7983 pci_set_power_state(pdev, PCI_D3hot);
7984 }
2a15cd2f 7985
7986 pm_runtime_put_noidle(d);
861ab440 7987}
5d06a99f 7988
baf63293 7989static void rtl_remove_one(struct pci_dev *pdev)
e27566ed
FR		 7990{
7991 struct net_device *dev = pci_get_drvdata(pdev);
7992 struct rtl8169_private *tp = netdev_priv(dev);
7993
ee7a1beb
CHL		 7994 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
7995 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
935e2218
CHL		 7996 tp->mac_version == RTL_GIGA_MAC_VER_31 ||
7997 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
7998 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
7999 tp->mac_version == RTL_GIGA_MAC_VER_51) &&
ee7a1beb 8000 r8168_check_dash(tp)) {
e27566ed
FR		 8001 rtl8168_driver_stop(tp);
8002 }
8003
ad1be8d3
DN		 8004 netif_napi_del(&tp->napi);
8005
e27566ed
FR		 8006 unregister_netdev(dev);
8007
42020320
CV		 8008 dma_free_coherent(&tp->pci_dev->dev, sizeof(*tp->counters),
8009 tp->counters, tp->counters_phys_addr);
8010
e27566ed
FR		 8011 rtl_release_firmware(tp);
8012
8013 if (pci_dev_run_wake(pdev))
8014 pm_runtime_get_noresume(&pdev->dev);
8015
8016 /* restore original MAC address */
8017 rtl_rar_set(tp, dev->perm_addr);
8018
8019 rtl_disable_msi(pdev, tp);
8020 rtl8169_release_board(pdev, dev, tp->mmio_addr);
e27566ed
FR		 8021}
8022
fa9c385e 8023static const struct net_device_ops rtl_netdev_ops = {
df43ac78 8024 .ndo_open = rtl_open,
fa9c385e
FR		 8025 .ndo_stop = rtl8169_close,
8026 .ndo_get_stats64 = rtl8169_get_stats64,
8027 .ndo_start_xmit = rtl8169_start_xmit,
8028 .ndo_tx_timeout = rtl8169_tx_timeout,
8029 .ndo_validate_addr = eth_validate_addr,
8030 .ndo_change_mtu = rtl8169_change_mtu,
8031 .ndo_fix_features = rtl8169_fix_features,
8032 .ndo_set_features = rtl8169_set_features,
8033 .ndo_set_mac_address = rtl_set_mac_address,
8034 .ndo_do_ioctl = rtl8169_ioctl,
8035 .ndo_set_rx_mode = rtl_set_rx_mode,
8036#ifdef CONFIG_NET_POLL_CONTROLLER
8037 .ndo_poll_controller = rtl8169_netpoll,
8038#endif
8039
8040};
8041
31fa8b18
FR		 8042static const struct rtl_cfg_info {
8043 void (*hw_start)(struct net_device *);
8044 unsigned int region;
8045 unsigned int align;
8046 u16 event_slow;
8047 unsigned features;
8048 u8 default_ver;
8049} rtl_cfg_infos [] = {
8050 [RTL_CFG_0] = {
8051 .hw_start = rtl_hw_start_8169,
8052 .region = 1,
8053 .align = 0,
8054 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
8055 .features = RTL_FEATURE_GMII,
8056 .default_ver = RTL_GIGA_MAC_VER_01,
8057 },
8058 [RTL_CFG_1] = {
8059 .hw_start = rtl_hw_start_8168,
8060 .region = 2,
8061 .align = 8,
8062 .event_slow = SYSErr | LinkChg | RxOverflow,
8063 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
8064 .default_ver = RTL_GIGA_MAC_VER_11,
8065 },
8066 [RTL_CFG_2] = {
8067 .hw_start = rtl_hw_start_8101,
8068 .region = 2,
8069 .align = 8,
8070 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
8071 PCSTimeout,
8072 .features = RTL_FEATURE_MSI,
8073 .default_ver = RTL_GIGA_MAC_VER_13,
8074 }
8075};
8076
8077/* Cfg9346_Unlock assumed. */
8078static unsigned rtl_try_msi(struct rtl8169_private *tp,
8079 const struct rtl_cfg_info *cfg)
8080{
8081 void __iomem *ioaddr = tp->mmio_addr;
8082 unsigned msi = 0;
8083 u8 cfg2;
8084
8085 cfg2 = RTL_R8(Config2) & ~MSIEnable;
8086 if (cfg->features & RTL_FEATURE_MSI) {
8087 if (pci_enable_msi(tp->pci_dev)) {
8088 netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
8089 } else {
8090 cfg2 |= MSIEnable;
8091 msi = RTL_FEATURE_MSI;
8092 }
8093 }
8094 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
8095 RTL_W8(Config2, cfg2);
8096 return msi;
8097}
8098
c558386b
HW		 8099DECLARE_RTL_COND(rtl_link_list_ready_cond)
8100{
8101 void __iomem *ioaddr = tp->mmio_addr;
8102
8103 return RTL_R8(MCU) & LINK_LIST_RDY;
8104}
8105
8106DECLARE_RTL_COND(rtl_rxtx_empty_cond)
8107{
8108 void __iomem *ioaddr = tp->mmio_addr;
8109
8110 return (RTL_R8(MCU) & RXTX_EMPTY) == RXTX_EMPTY;
8111}
8112
baf63293 8113static void rtl_hw_init_8168g(struct rtl8169_private *tp)
c558386b
HW		 8114{
8115 void __iomem *ioaddr = tp->mmio_addr;
8116 u32 data;
8117
8118 tp->ocp_base = OCP_STD_PHY_BASE;
8119
8120 RTL_W32(MISC, RTL_R32(MISC) | RXDV_GATED_EN);
8121
8122 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
8123 return;
8124
8125 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
8126 return;
8127
8128 RTL_W8(ChipCmd, RTL_R8(ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
8129 msleep(1);
8130 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
8131
5f8bcce9 8132 data = r8168_mac_ocp_read(tp, 0xe8de);
c558386b
HW		 8133 data &= ~(1 << 14);
8134 r8168_mac_ocp_write(tp, 0xe8de, data);
8135
8136 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
8137 return;
8138
5f8bcce9 8139 data = r8168_mac_ocp_read(tp, 0xe8de);
c558386b
HW		 8140 data |= (1 << 15);
8141 r8168_mac_ocp_write(tp, 0xe8de, data);
8142
8143 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
8144 return;
8145}
8146
003609da
CHL		 8147static void rtl_hw_init_8168ep(struct rtl8169_private *tp)
8148{
8149 rtl8168ep_stop_cmac(tp);
8150 rtl_hw_init_8168g(tp);
8151}
8152
baf63293 8153static void rtl_hw_initialize(struct rtl8169_private *tp)
c558386b
HW		 8154{
8155 switch (tp->mac_version) {
8156 case RTL_GIGA_MAC_VER_40:
8157 case RTL_GIGA_MAC_VER_41:
57538c4a 8158 case RTL_GIGA_MAC_VER_42:
58152cd4 8159 case RTL_GIGA_MAC_VER_43:
45dd95c4 8160 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 8161 case RTL_GIGA_MAC_VER_45:
8162 case RTL_GIGA_MAC_VER_46:
8163 case RTL_GIGA_MAC_VER_47:
8164 case RTL_GIGA_MAC_VER_48:
003609da
CHL		 8165 rtl_hw_init_8168g(tp);
8166 break;
935e2218
CHL		 8167 case RTL_GIGA_MAC_VER_49:
8168 case RTL_GIGA_MAC_VER_50:
8169 case RTL_GIGA_MAC_VER_51:
003609da 8170 rtl_hw_init_8168ep(tp);
c558386b 8171 break;
c558386b
HW		 8172 default:
8173 break;
8174 }
8175}
8176
929a031d 8177static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3b6cf25d
FR		 8178{
8179 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
8180 const unsigned int region = cfg->region;
8181 struct rtl8169_private *tp;
8182 struct mii_if_info *mii;
8183 struct net_device *dev;
8184 void __iomem *ioaddr;
8185 int chipset, i;
8186 int rc;
8187
8188 if (netif_msg_drv(&debug)) {
8189 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
8190 MODULENAME, RTL8169_VERSION);
8191 }
8192
8193 dev = alloc_etherdev(sizeof (*tp));
8194 if (!dev) {
8195 rc = -ENOMEM;
8196 goto out;
8197 }
8198
8199 SET_NETDEV_DEV(dev, &pdev->dev);
fa9c385e 8200 dev->netdev_ops = &rtl_netdev_ops;
3b6cf25d
FR		 8201 tp = netdev_priv(dev);
8202 tp->dev = dev;
8203 tp->pci_dev = pdev;
8204 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
8205
8206 mii = &tp->mii;
8207 mii->dev = dev;
8208 mii->mdio_read = rtl_mdio_read;
8209 mii->mdio_write = rtl_mdio_write;
8210 mii->phy_id_mask = 0x1f;
8211 mii->reg_num_mask = 0x1f;
8212 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
8213
8214 /* disable ASPM completely as that cause random device stop working
8215 * problems as well as full system hangs for some PCIe devices users */
8216 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
8217 PCIE_LINK_STATE_CLKPM);
8218
8219 /* enable device (incl. PCI PM wakeup and hotplug setup) */
8220 rc = pci_enable_device(pdev);
8221 if (rc < 0) {
8222 netif_err(tp, probe, dev, "enable failure\n");
8223 goto err_out_free_dev_1;
8224 }
8225
8226 if (pci_set_mwi(pdev) < 0)
8227 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
8228
8229 /* make sure PCI base addr 1 is MMIO */
8230 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
8231 netif_err(tp, probe, dev,
8232 "region #%d not an MMIO resource, aborting\n",
8233 region);
8234 rc = -ENODEV;
8235 goto err_out_mwi_2;
8236 }
8237
8238 /* check for weird/broken PCI region reporting */
8239 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
8240 netif_err(tp, probe, dev,
8241 "Invalid PCI region size(s), aborting\n");
8242 rc = -ENODEV;
8243 goto err_out_mwi_2;
8244 }
8245
8246 rc = pci_request_regions(pdev, MODULENAME);
8247 if (rc < 0) {
8248 netif_err(tp, probe, dev, "could not request regions\n");
8249 goto err_out_mwi_2;
8250 }
8251
3b6cf25d
FR		 8252 /* ioremap MMIO region */
8253 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
8254 if (!ioaddr) {
8255 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
8256 rc = -EIO;
8257 goto err_out_free_res_3;
8258 }
8259 tp->mmio_addr = ioaddr;
8260
8261 if (!pci_is_pcie(pdev))
8262 netif_info(tp, probe, dev, "not PCI Express\n");
8263
8264 /* Identify chip attached to board */
8265 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
8266
27896c83
AB		 8267 tp->cp_cmd = 0;
8268
8269 if ((sizeof(dma_addr_t) > 4) &&
8270 (use_dac == 1 || (use_dac == -1 && pci_is_pcie(pdev) &&
8271 tp->mac_version >= RTL_GIGA_MAC_VER_18)) &&
f0076436
AB		 8272 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
8273 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
27896c83
AB		 8274
8275 /* CPlusCmd Dual Access Cycle is only needed for non-PCIe */
8276 if (!pci_is_pcie(pdev))
8277 tp->cp_cmd |= PCIDAC;
8278 dev->features |= NETIF_F_HIGHDMA;
8279 } else {
8280 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
8281 if (rc < 0) {
8282 netif_err(tp, probe, dev, "DMA configuration failed\n");
8283 goto err_out_unmap_4;
8284 }
8285 }
8286
3b6cf25d
FR		 8287 rtl_init_rxcfg(tp);
8288
8289 rtl_irq_disable(tp);
8290
c558386b
HW		 8291 rtl_hw_initialize(tp);
8292
3b6cf25d
FR		 8293 rtl_hw_reset(tp);
8294
8295 rtl_ack_events(tp, 0xffff);
8296
8297 pci_set_master(pdev);
8298
3b6cf25d
FR		 8299 rtl_init_mdio_ops(tp);
8300 rtl_init_pll_power_ops(tp);
8301 rtl_init_jumbo_ops(tp);
beb1fe18 8302 rtl_init_csi_ops(tp);
3b6cf25d
FR		 8303
8304 rtl8169_print_mac_version(tp);
8305
8306 chipset = tp->mac_version;
8307 tp->txd_version = rtl_chip_infos[chipset].txd_version;
8308
8309 RTL_W8(Cfg9346, Cfg9346_Unlock);
8310 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
8f9d5138 8311 RTL_W8(Config5, RTL_R8(Config5) & (BWF | MWF | UWF | LanWake | PMEStatus));
6e1d0b89 8312 switch (tp->mac_version) {
ac85bcdb
CHL		 8313 case RTL_GIGA_MAC_VER_34:
8314 case RTL_GIGA_MAC_VER_35:
8315 case RTL_GIGA_MAC_VER_36:
8316 case RTL_GIGA_MAC_VER_37:
8317 case RTL_GIGA_MAC_VER_38:
8318 case RTL_GIGA_MAC_VER_40:
8319 case RTL_GIGA_MAC_VER_41:
8320 case RTL_GIGA_MAC_VER_42:
8321 case RTL_GIGA_MAC_VER_43:
8322 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 8323 case RTL_GIGA_MAC_VER_45:
8324 case RTL_GIGA_MAC_VER_46:
ac85bcdb
CHL		 8325 case RTL_GIGA_MAC_VER_47:
8326 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 8327 case RTL_GIGA_MAC_VER_49:
8328 case RTL_GIGA_MAC_VER_50:
8329 case RTL_GIGA_MAC_VER_51:
6e1d0b89
CHL		 8330 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
8331 tp->features |= RTL_FEATURE_WOL;
8332 if ((RTL_R8(Config3) & LinkUp) != 0)
8333 tp->features |= RTL_FEATURE_WOL;
8334 break;
8335 default:
8336 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
8337 tp->features |= RTL_FEATURE_WOL;
8338 break;
8339 }
3b6cf25d
FR		 8340 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
8341 tp->features |= RTL_FEATURE_WOL;
8342 tp->features |= rtl_try_msi(tp, cfg);
8343 RTL_W8(Cfg9346, Cfg9346_Lock);
8344
8345 if (rtl_tbi_enabled(tp)) {
8346 tp->set_speed = rtl8169_set_speed_tbi;
8347 tp->get_settings = rtl8169_gset_tbi;
8348 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
8349 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
8350 tp->link_ok = rtl8169_tbi_link_ok;
8351 tp->do_ioctl = rtl_tbi_ioctl;
8352 } else {
8353 tp->set_speed = rtl8169_set_speed_xmii;
8354 tp->get_settings = rtl8169_gset_xmii;
8355 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
8356 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
8357 tp->link_ok = rtl8169_xmii_link_ok;
8358 tp->do_ioctl = rtl_xmii_ioctl;
8359 }
8360
8361 mutex_init(&tp->wk.mutex);
340fea3d
KM		 8362 u64_stats_init(&tp->rx_stats.syncp);
8363 u64_stats_init(&tp->tx_stats.syncp);
3b6cf25d
FR		 8364
8365 /* Get MAC address */
89cceb27
CHL		 8366 if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
8367 tp->mac_version == RTL_GIGA_MAC_VER_36 ||
8368 tp->mac_version == RTL_GIGA_MAC_VER_37 ||
8369 tp->mac_version == RTL_GIGA_MAC_VER_38 ||
8370 tp->mac_version == RTL_GIGA_MAC_VER_40 ||
8371 tp->mac_version == RTL_GIGA_MAC_VER_41 ||
8372 tp->mac_version == RTL_GIGA_MAC_VER_42 ||
8373 tp->mac_version == RTL_GIGA_MAC_VER_43 ||
8374 tp->mac_version == RTL_GIGA_MAC_VER_44 ||
8375 tp->mac_version == RTL_GIGA_MAC_VER_45 ||
6e1d0b89
CHL		 8376 tp->mac_version == RTL_GIGA_MAC_VER_46 ||
8377 tp->mac_version == RTL_GIGA_MAC_VER_47 ||
935e2218
CHL		 8378 tp->mac_version == RTL_GIGA_MAC_VER_48 ||
8379 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
8380 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
8381 tp->mac_version == RTL_GIGA_MAC_VER_51) {
6e1d0b89
CHL		 8382 u16 mac_addr[3];
8383
05b9687b
CHL		 8384 *(u32 *)&mac_addr[0] = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC);
8385 *(u16 *)&mac_addr[2] = rtl_eri_read(tp, 0xe4, ERIAR_EXGMAC);
6e1d0b89
CHL		 8386
8387 if (is_valid_ether_addr((u8 *)mac_addr))
8388 rtl_rar_set(tp, (u8 *)mac_addr);
8389 }
3b6cf25d
FR		 8390 for (i = 0; i < ETH_ALEN; i++)
8391 dev->dev_addr[i] = RTL_R8(MAC0 + i);
3b6cf25d 8392
7ad24ea4 8393 dev->ethtool_ops = &rtl8169_ethtool_ops;
3b6cf25d 8394 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3b6cf25d
FR		 8395
8396 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
8397
8398 /* don't enable SG, IP_CSUM and TSO by default - it might not work
8399 * properly for all devices */
8400 dev->features |= NETIF_F_RXCSUM |
f646968f 8401 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d
FR		 8402
8403 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
f646968f
PM		 8404 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
8405 NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d
FR		 8406 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
8407 NETIF_F_HIGHDMA;
8408
929a031d 8409 tp->cp_cmd |= RxChkSum | RxVlan;
8410
8411 /*
8412 * Pretend we are using VLANs; This bypasses a nasty bug where
8413 * Interrupts stop flowing on high load on 8110SCd controllers.
8414 */
3b6cf25d 8415 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
929a031d 8416 /* Disallow toggling */
f646968f 8417 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d 8418
5888d3fc 8419 if (tp->txd_version == RTL_TD_0)
8420 tp->tso_csum = rtl8169_tso_csum_v1;
e974604b 8421 else if (tp->txd_version == RTL_TD_1) {
5888d3fc 8422 tp->tso_csum = rtl8169_tso_csum_v2;
e974604b 8423 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
8424 } else
5888d3fc 8425 WARN_ON_ONCE(1);
8426
3b6cf25d
FR		 8427 dev->hw_features |= NETIF_F_RXALL;
8428 dev->hw_features |= NETIF_F_RXFCS;
8429
c7315a95
JW		 8430 /* MTU range: 60 - hw-specific max */
8431 dev->min_mtu = ETH_ZLEN;
8432 dev->max_mtu = rtl_chip_infos[chipset].jumbo_max;
8433
3b6cf25d
FR		 8434 tp->hw_start = cfg->hw_start;
8435 tp->event_slow = cfg->event_slow;
8436
8437 tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
8438 ~(RxBOVF | RxFOVF) : ~0;
8439
8440 init_timer(&tp->timer);
8441 tp->timer.data = (unsigned long) dev;
8442 tp->timer.function = rtl8169_phy_timer;
8443
8444 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
8445
42020320
CV		 8446 tp->counters = dma_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
8447 &tp->counters_phys_addr, GFP_KERNEL);
8448 if (!tp->counters) {
8449 rc = -ENOMEM;
27896c83 8450 goto err_out_msi_5;
42020320
CV		 8451 }
8452
3b6cf25d
FR		 8453 rc = register_netdev(dev);
8454 if (rc < 0)
27896c83 8455 goto err_out_cnt_6;
3b6cf25d
FR		 8456
8457 pci_set_drvdata(pdev, dev);
8458
92a7c4e7
FR		 8459 netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
8460 rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
8461 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
3b6cf25d
FR		 8462 if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
8463 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
8464 "tx checksumming: %s]\n",
8465 rtl_chip_infos[chipset].jumbo_max,
8466 rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
8467 }
8468
ee7a1beb
CHL		 8469 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
8470 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
935e2218
CHL		 8471 tp->mac_version == RTL_GIGA_MAC_VER_31 ||
8472 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
8473 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
8474 tp->mac_version == RTL_GIGA_MAC_VER_51) &&
ee7a1beb 8475 r8168_check_dash(tp)) {
3b6cf25d
FR		 8476 rtl8168_driver_start(tp);
8477 }
8478
8479 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
8480
8481 if (pci_dev_run_wake(pdev))
8482 pm_runtime_put_noidle(&pdev->dev);
8483
8484 netif_carrier_off(dev);
8485
8486out:
8487 return rc;
8488
27896c83 8489err_out_cnt_6:
42020320
CV		 8490 dma_free_coherent(&pdev->dev, sizeof(*tp->counters), tp->counters,
8491 tp->counters_phys_addr);
27896c83 8492err_out_msi_5:
ad1be8d3 8493 netif_napi_del(&tp->napi);
3b6cf25d 8494 rtl_disable_msi(pdev, tp);
27896c83 8495err_out_unmap_4:
3b6cf25d
FR		 8496 iounmap(ioaddr);
8497err_out_free_res_3:
8498 pci_release_regions(pdev);
8499err_out_mwi_2:
8500 pci_clear_mwi(pdev);
8501 pci_disable_device(pdev);
8502err_out_free_dev_1:
8503 free_netdev(dev);
8504 goto out;
8505}
8506
1da177e4
LT		 8507static struct pci_driver rtl8169_pci_driver = {
8508 .name = MODULENAME,
8509 .id_table = rtl8169_pci_tbl,
3b6cf25d 8510 .probe = rtl_init_one,
baf63293 8511 .remove = rtl_remove_one,
1765f95d 8512 .shutdown = rtl_shutdown,
861ab440 8513 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 8514};
8515
3eeb7da9 8516module_pci_driver(rtl8169_pci_driver);
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