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bonding: create netlink event when bonding option is changed
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / realtek / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
a6b7a407 24#include <linux/interrupt.h>
1da177e4 25#include <linux/dma-mapping.h>
e1759441 26#include <linux/pm_runtime.h>
bca03d5f 27#include <linux/firmware.h>
ba04c7c9 28#include <linux/pci-aspm.h>
70c71606 29#include <linux/prefetch.h>
e974604b 30#include <linux/ipv6.h>
31#include <net/ip6_checksum.h>
1da177e4
LT		 32
33#include <asm/io.h>
34#include <asm/irq.h>
35
865c652d 36#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 37#define MODULENAME "r8169"
38#define PFX MODULENAME ": "
39
bca03d5f 40#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
41#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
01dc7fec 42#define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
43#define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
70090424 44#define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
c2218925
HW		 45#define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
46#define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
5a5e4443 47#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
7e18dca1 48#define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
b3d7b2f2 49#define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
45dd95c4 50#define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
5598bfe5 51#define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
58152cd4 52#define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
beb330a4 53#define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
57538c4a 54#define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
bca03d5f 55
1da177e4
LT		 56#ifdef RTL8169_DEBUG
57#define assert(expr) \
5b0384f4
FR		 58 if (!(expr)) { \
59 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
b39d66a8 60 #expr,__FILE__,__func__,__LINE__); \
5b0384f4 61 }
06fa7358
JP		 62#define dprintk(fmt, args...) \
63 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 64#else
65#define assert(expr) do {} while (0)
66#define dprintk(fmt, args...) do {} while (0)
67#endif /* RTL8169_DEBUG */
68
b57b7e5a 69#define R8169_MSG_DEFAULT \
f0e837d9 70 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 71
477206a0
JD		 72#define TX_SLOTS_AVAIL(tp) \
73 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
74
75/* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
76#define TX_FRAGS_READY_FOR(tp,nr_frags) \
77 (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
1da177e4 78
1da177e4
LT		 79/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
80 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 81static const int multicast_filter_limit = 32;
1da177e4 82
9c14ceaf 83#define MAX_READ_REQUEST_SHIFT 12
aee77e4a 84#define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
1da177e4
LT		 85#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
86
87#define R8169_REGS_SIZE 256
88#define R8169_NAPI_WEIGHT 64
89#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
9fba0812 90#define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
1da177e4
LT		 91#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
92#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
93
94#define RTL8169_TX_TIMEOUT (6*HZ)
95#define RTL8169_PHY_TIMEOUT (10*HZ)
96
97/* write/read MMIO register */
98#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
99#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
100#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
101#define RTL_R8(reg) readb (ioaddr + (reg))
102#define RTL_R16(reg) readw (ioaddr + (reg))
06f555f3 103#define RTL_R32(reg) readl (ioaddr + (reg))
1da177e4
LT		 104
105enum mac_version {
85bffe6c
FR		 106 RTL_GIGA_MAC_VER_01 = 0,
107 RTL_GIGA_MAC_VER_02,
108 RTL_GIGA_MAC_VER_03,
109 RTL_GIGA_MAC_VER_04,
110 RTL_GIGA_MAC_VER_05,
111 RTL_GIGA_MAC_VER_06,
112 RTL_GIGA_MAC_VER_07,
113 RTL_GIGA_MAC_VER_08,
114 RTL_GIGA_MAC_VER_09,
115 RTL_GIGA_MAC_VER_10,
116 RTL_GIGA_MAC_VER_11,
117 RTL_GIGA_MAC_VER_12,
118 RTL_GIGA_MAC_VER_13,
119 RTL_GIGA_MAC_VER_14,
120 RTL_GIGA_MAC_VER_15,
121 RTL_GIGA_MAC_VER_16,
122 RTL_GIGA_MAC_VER_17,
123 RTL_GIGA_MAC_VER_18,
124 RTL_GIGA_MAC_VER_19,
125 RTL_GIGA_MAC_VER_20,
126 RTL_GIGA_MAC_VER_21,
127 RTL_GIGA_MAC_VER_22,
128 RTL_GIGA_MAC_VER_23,
129 RTL_GIGA_MAC_VER_24,
130 RTL_GIGA_MAC_VER_25,
131 RTL_GIGA_MAC_VER_26,
132 RTL_GIGA_MAC_VER_27,
133 RTL_GIGA_MAC_VER_28,
134 RTL_GIGA_MAC_VER_29,
135 RTL_GIGA_MAC_VER_30,
136 RTL_GIGA_MAC_VER_31,
137 RTL_GIGA_MAC_VER_32,
138 RTL_GIGA_MAC_VER_33,
70090424 139 RTL_GIGA_MAC_VER_34,
c2218925
HW		 140 RTL_GIGA_MAC_VER_35,
141 RTL_GIGA_MAC_VER_36,
7e18dca1 142 RTL_GIGA_MAC_VER_37,
b3d7b2f2 143 RTL_GIGA_MAC_VER_38,
5598bfe5 144 RTL_GIGA_MAC_VER_39,
c558386b
HW		 145 RTL_GIGA_MAC_VER_40,
146 RTL_GIGA_MAC_VER_41,
57538c4a 147 RTL_GIGA_MAC_VER_42,
58152cd4 148 RTL_GIGA_MAC_VER_43,
45dd95c4 149 RTL_GIGA_MAC_VER_44,
85bffe6c 150 RTL_GIGA_MAC_NONE = 0xff,
1da177e4
LT		 151};
152
2b7b4318
FR		 153enum rtl_tx_desc_version {
154 RTL_TD_0 = 0,
155 RTL_TD_1 = 1,
156};
157
d58d46b5
FR		 158#define JUMBO_1K ETH_DATA_LEN
159#define JUMBO_4K (4*1024 - ETH_HLEN - 2)
160#define JUMBO_6K (6*1024 - ETH_HLEN - 2)
161#define JUMBO_7K (7*1024 - ETH_HLEN - 2)
162#define JUMBO_9K (9*1024 - ETH_HLEN - 2)
163
164#define _R(NAME,TD,FW,SZ,B) { \
165 .name = NAME, \
166 .txd_version = TD, \
167 .fw_name = FW, \
168 .jumbo_max = SZ, \
169 .jumbo_tx_csum = B \
170}
1da177e4 171
3c6bee1d 172static const struct {
1da177e4 173 const char *name;
2b7b4318 174 enum rtl_tx_desc_version txd_version;
953a12cc 175 const char *fw_name;
d58d46b5
FR		 176 u16 jumbo_max;
177 bool jumbo_tx_csum;
85bffe6c
FR		 178} rtl_chip_infos[] = {
179 /* PCI devices. */
180 [RTL_GIGA_MAC_VER_01] =
d58d46b5 181 _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 182 [RTL_GIGA_MAC_VER_02] =
d58d46b5 183 _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 184 [RTL_GIGA_MAC_VER_03] =
d58d46b5 185 _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 186 [RTL_GIGA_MAC_VER_04] =
d58d46b5 187 _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 188 [RTL_GIGA_MAC_VER_05] =
d58d46b5 189 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c 190 [RTL_GIGA_MAC_VER_06] =
d58d46b5 191 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
85bffe6c
FR		 192 /* PCI-E devices. */
193 [RTL_GIGA_MAC_VER_07] =
d58d46b5 194 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 195 [RTL_GIGA_MAC_VER_08] =
d58d46b5 196 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 197 [RTL_GIGA_MAC_VER_09] =
d58d46b5 198 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
85bffe6c 199 [RTL_GIGA_MAC_VER_10] =
d58d46b5 200 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 201 [RTL_GIGA_MAC_VER_11] =
d58d46b5 202 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
85bffe6c 203 [RTL_GIGA_MAC_VER_12] =
d58d46b5 204 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
85bffe6c 205 [RTL_GIGA_MAC_VER_13] =
d58d46b5 206 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 207 [RTL_GIGA_MAC_VER_14] =
d58d46b5 208 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 209 [RTL_GIGA_MAC_VER_15] =
d58d46b5 210 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 211 [RTL_GIGA_MAC_VER_16] =
d58d46b5 212 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
85bffe6c 213 [RTL_GIGA_MAC_VER_17] =
f75761b6 214 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
85bffe6c 215 [RTL_GIGA_MAC_VER_18] =
d58d46b5 216 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 217 [RTL_GIGA_MAC_VER_19] =
d58d46b5 218 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 219 [RTL_GIGA_MAC_VER_20] =
d58d46b5 220 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 221 [RTL_GIGA_MAC_VER_21] =
d58d46b5 222 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 223 [RTL_GIGA_MAC_VER_22] =
d58d46b5 224 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 225 [RTL_GIGA_MAC_VER_23] =
d58d46b5 226 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 227 [RTL_GIGA_MAC_VER_24] =
d58d46b5 228 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
85bffe6c 229 [RTL_GIGA_MAC_VER_25] =
d58d46b5
FR		 230 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1,
231 JUMBO_9K, false),
85bffe6c 232 [RTL_GIGA_MAC_VER_26] =
d58d46b5
FR		 233 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2,
234 JUMBO_9K, false),
85bffe6c 235 [RTL_GIGA_MAC_VER_27] =
d58d46b5 236 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 237 [RTL_GIGA_MAC_VER_28] =
d58d46b5 238 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 239 [RTL_GIGA_MAC_VER_29] =
d58d46b5
FR		 240 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
241 JUMBO_1K, true),
85bffe6c 242 [RTL_GIGA_MAC_VER_30] =
d58d46b5
FR		 243 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
244 JUMBO_1K, true),
85bffe6c 245 [RTL_GIGA_MAC_VER_31] =
d58d46b5 246 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
85bffe6c 247 [RTL_GIGA_MAC_VER_32] =
d58d46b5
FR		 248 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1,
249 JUMBO_9K, false),
85bffe6c 250 [RTL_GIGA_MAC_VER_33] =
d58d46b5
FR		 251 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2,
252 JUMBO_9K, false),
70090424 253 [RTL_GIGA_MAC_VER_34] =
d58d46b5
FR		 254 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
255 JUMBO_9K, false),
c2218925 256 [RTL_GIGA_MAC_VER_35] =
d58d46b5
FR		 257 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1,
258 JUMBO_9K, false),
c2218925 259 [RTL_GIGA_MAC_VER_36] =
d58d46b5
FR		 260 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2,
261 JUMBO_9K, false),
7e18dca1
HW		 262 [RTL_GIGA_MAC_VER_37] =
263 _R("RTL8402", RTL_TD_1, FIRMWARE_8402_1,
264 JUMBO_1K, true),
b3d7b2f2
HW		 265 [RTL_GIGA_MAC_VER_38] =
266 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_1,
267 JUMBO_9K, false),
5598bfe5
HW		 268 [RTL_GIGA_MAC_VER_39] =
269 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_1,
270 JUMBO_1K, true),
c558386b 271 [RTL_GIGA_MAC_VER_40] =
beb330a4 272 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_2,
c558386b
HW		 273 JUMBO_9K, false),
274 [RTL_GIGA_MAC_VER_41] =
275 _R("RTL8168g/8111g", RTL_TD_1, NULL, JUMBO_9K, false),
57538c4a 276 [RTL_GIGA_MAC_VER_42] =
277 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_3,
278 JUMBO_9K, false),
58152cd4 279 [RTL_GIGA_MAC_VER_43] =
280 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_2,
281 JUMBO_1K, true),
45dd95c4 282 [RTL_GIGA_MAC_VER_44] =
283 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_2,
284 JUMBO_9K, false),
953a12cc 285};
85bffe6c 286#undef _R
953a12cc 287
bcf0bf90
FR		 288enum cfg_version {
289 RTL_CFG_0 = 0x00,
290 RTL_CFG_1,
291 RTL_CFG_2
292};
293
9baa3c34 294static const struct pci_device_id rtl8169_pci_tbl[] = {
bcf0bf90 295 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 296 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 297 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 298 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90 299 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
2a35cfa5
FR		 300 { PCI_VENDOR_ID_DLINK, 0x4300,
301 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
bcf0bf90 302 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
93a3aa25 303 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
bc1660b5 304 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 305 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
306 { PCI_VENDOR_ID_LINKSYS, 0x1032,
307 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 308 { 0x0001, 0x8168,
309 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 310 {0,},
311};
312
313MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
314
6f0333b8 315static int rx_buf_sz = 16383;
4300e8c7 316static int use_dac;
b57b7e5a
SH		 317static struct {
318 u32 msg_enable;
319} debug = { -1 };
1da177e4 320
07d3f51f
FR		 321enum rtl_registers {
322 MAC0 = 0, /* Ethernet hardware address. */
773d2021 323 MAC4 = 4,
07d3f51f
FR		 324 MAR0 = 8, /* Multicast filter. */
325 CounterAddrLow = 0x10,
326 CounterAddrHigh = 0x14,
327 TxDescStartAddrLow = 0x20,
328 TxDescStartAddrHigh = 0x24,
329 TxHDescStartAddrLow = 0x28,
330 TxHDescStartAddrHigh = 0x2c,
331 FLASH = 0x30,
332 ERSR = 0x36,
333 ChipCmd = 0x37,
334 TxPoll = 0x38,
335 IntrMask = 0x3c,
336 IntrStatus = 0x3e,
4f6b00e5 337
07d3f51f 338 TxConfig = 0x40,
4f6b00e5
HW		 339#define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
340#define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
2b7b4318 341
4f6b00e5
HW		 342 RxConfig = 0x44,
343#define RX128_INT_EN (1 << 15) /* 8111c and later */
344#define RX_MULTI_EN (1 << 14) /* 8111c only */
345#define RXCFG_FIFO_SHIFT 13
346 /* No threshold before first PCI xfer */
347#define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
beb330a4 348#define RX_EARLY_OFF (1 << 11)
4f6b00e5
HW		 349#define RXCFG_DMA_SHIFT 8
350 /* Unlimited maximum PCI burst. */
351#define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
2b7b4318 352
07d3f51f
FR		 353 RxMissed = 0x4c,
354 Cfg9346 = 0x50,
355 Config0 = 0x51,
356 Config1 = 0x52,
357 Config2 = 0x53,
d387b427
FR		 358#define PME_SIGNAL (1 << 5) /* 8168c and later */
359
07d3f51f
FR		 360 Config3 = 0x54,
361 Config4 = 0x55,
362 Config5 = 0x56,
363 MultiIntr = 0x5c,
364 PHYAR = 0x60,
07d3f51f
FR		 365 PHYstatus = 0x6c,
366 RxMaxSize = 0xda,
367 CPlusCmd = 0xe0,
368 IntrMitigate = 0xe2,
369 RxDescAddrLow = 0xe4,
370 RxDescAddrHigh = 0xe8,
f0298f81 371 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
372
373#define NoEarlyTx 0x3f /* Max value : no early transmit. */
374
375 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
376
377#define TxPacketMax (8064 >> 7)
3090bd9a 378#define EarlySize 0x27
f0298f81 379
07d3f51f
FR		 380 FuncEvent = 0xf0,
381 FuncEventMask = 0xf4,
382 FuncPresetState = 0xf8,
383 FuncForceEvent = 0xfc,
1da177e4
LT		 384};
385
f162a5d1
FR		 386enum rtl8110_registers {
387 TBICSR = 0x64,
388 TBI_ANAR = 0x68,
389 TBI_LPAR = 0x6a,
390};
391
392enum rtl8168_8101_registers {
393 CSIDR = 0x64,
394 CSIAR = 0x68,
395#define CSIAR_FLAG 0x80000000
396#define CSIAR_WRITE_CMD 0x80000000
397#define CSIAR_BYTE_ENABLE 0x0f
398#define CSIAR_BYTE_ENABLE_SHIFT 12
399#define CSIAR_ADDR_MASK 0x0fff
7e18dca1
HW		 400#define CSIAR_FUNC_CARD 0x00000000
401#define CSIAR_FUNC_SDIO 0x00010000
402#define CSIAR_FUNC_NIC 0x00020000
45dd95c4 403#define CSIAR_FUNC_NIC2 0x00010000
065c27c1 404 PMCH = 0x6f,
f162a5d1
FR		 405 EPHYAR = 0x80,
406#define EPHYAR_FLAG 0x80000000
407#define EPHYAR_WRITE_CMD 0x80000000
408#define EPHYAR_REG_MASK 0x1f
409#define EPHYAR_REG_SHIFT 16
410#define EPHYAR_DATA_MASK 0xffff
5a5e4443 411 DLLPR = 0xd0,
4f6b00e5 412#define PFM_EN (1 << 6)
f162a5d1
FR		 413 DBG_REG = 0xd1,
414#define FIX_NAK_1 (1 << 4)
415#define FIX_NAK_2 (1 << 3)
5a5e4443
HW		 416 TWSI = 0xd2,
417 MCU = 0xd3,
4f6b00e5 418#define NOW_IS_OOB (1 << 7)
c558386b
HW		 419#define TX_EMPTY (1 << 5)
420#define RX_EMPTY (1 << 4)
421#define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
5a5e4443
HW		 422#define EN_NDP (1 << 3)
423#define EN_OOB_RESET (1 << 2)
c558386b 424#define LINK_LIST_RDY (1 << 1)
daf9df6d 425 EFUSEAR = 0xdc,
426#define EFUSEAR_FLAG 0x80000000
427#define EFUSEAR_WRITE_CMD 0x80000000
428#define EFUSEAR_READ_CMD 0x00000000
429#define EFUSEAR_REG_MASK 0x03ff
430#define EFUSEAR_REG_SHIFT 8
431#define EFUSEAR_DATA_MASK 0xff
f162a5d1
FR		 432};
433
c0e45c1c 434enum rtl8168_registers {
4f6b00e5
HW		 435 LED_FREQ = 0x1a,
436 EEE_LED = 0x1b,
b646d900 437 ERIDR = 0x70,
438 ERIAR = 0x74,
439#define ERIAR_FLAG 0x80000000
440#define ERIAR_WRITE_CMD 0x80000000
441#define ERIAR_READ_CMD 0x00000000
442#define ERIAR_ADDR_BYTE_ALIGN 4
b646d900 443#define ERIAR_TYPE_SHIFT 16
4f6b00e5
HW		 444#define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
445#define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
446#define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
447#define ERIAR_MASK_SHIFT 12
448#define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
449#define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
c558386b 450#define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
4f6b00e5 451#define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
c0e45c1c 452 EPHY_RXER_NUM = 0x7c,
453 OCPDR = 0xb0, /* OCP GPHY access */
454#define OCPDR_WRITE_CMD 0x80000000
455#define OCPDR_READ_CMD 0x00000000
456#define OCPDR_REG_MASK 0x7f
457#define OCPDR_GPHY_REG_SHIFT 16
458#define OCPDR_DATA_MASK 0xffff
459 OCPAR = 0xb4,
460#define OCPAR_FLAG 0x80000000
461#define OCPAR_GPHY_WRITE_CMD 0x8000f060
462#define OCPAR_GPHY_READ_CMD 0x0000f060
c558386b 463 GPHY_OCP = 0xb8,
01dc7fec 464 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
465 MISC = 0xf0, /* 8168e only. */
cecb5fd7 466#define TXPLA_RST (1 << 29)
5598bfe5 467#define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
4f6b00e5 468#define PWM_EN (1 << 22)
c558386b 469#define RXDV_GATED_EN (1 << 19)
5598bfe5 470#define EARLY_TALLY_EN (1 << 16)
c0e45c1c 471};
472
07d3f51f 473enum rtl_register_content {
1da177e4 474 /* InterruptStatusBits */
07d3f51f
FR		 475 SYSErr = 0x8000,
476 PCSTimeout = 0x4000,
477 SWInt = 0x0100,
478 TxDescUnavail = 0x0080,
479 RxFIFOOver = 0x0040,
480 LinkChg = 0x0020,
481 RxOverflow = 0x0010,
482 TxErr = 0x0008,
483 TxOK = 0x0004,
484 RxErr = 0x0002,
485 RxOK = 0x0001,
1da177e4
LT		 486
487 /* RxStatusDesc */
e03f33af 488 RxBOVF = (1 << 24),
9dccf611
FR		 489 RxFOVF = (1 << 23),
490 RxRWT = (1 << 22),
491 RxRES = (1 << 21),
492 RxRUNT = (1 << 20),
493 RxCRC = (1 << 19),
1da177e4
LT		 494
495 /* ChipCmdBits */
4f6b00e5 496 StopReq = 0x80,
07d3f51f
FR		 497 CmdReset = 0x10,
498 CmdRxEnb = 0x08,
499 CmdTxEnb = 0x04,
500 RxBufEmpty = 0x01,
1da177e4 501
275391a4
FR		 502 /* TXPoll register p.5 */
503 HPQ = 0x80, /* Poll cmd on the high prio queue */
504 NPQ = 0x40, /* Poll cmd on the low prio queue */
505 FSWInt = 0x01, /* Forced software interrupt */
506
1da177e4 507 /* Cfg9346Bits */
07d3f51f
FR		 508 Cfg9346_Lock = 0x00,
509 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 510
511 /* rx_mode_bits */
07d3f51f
FR		 512 AcceptErr = 0x20,
513 AcceptRunt = 0x10,
514 AcceptBroadcast = 0x08,
515 AcceptMulticast = 0x04,
516 AcceptMyPhys = 0x02,
517 AcceptAllPhys = 0x01,
1687b566 518#define RX_CONFIG_ACCEPT_MASK 0x3f
1da177e4 519
1da177e4
LT		 520 /* TxConfigBits */
521 TxInterFrameGapShift = 24,
522 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
523
5d06a99f 524 /* Config1 register p.24 */
f162a5d1
FR		 525 LEDS1 = (1 << 7),
526 LEDS0 = (1 << 6),
f162a5d1
FR		 527 Speed_down = (1 << 4),
528 MEMMAP = (1 << 3),
529 IOMAP = (1 << 2),
530 VPD = (1 << 1),
5d06a99f
FR		 531 PMEnable = (1 << 0), /* Power Management Enable */
532
6dccd16b 533 /* Config2 register p. 25 */
57538c4a 534 ClkReqEn = (1 << 7), /* Clock Request Enable */
2ca6cf06 535 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
6dccd16b
FR		 536 PCI_Clock_66MHz = 0x01,
537 PCI_Clock_33MHz = 0x00,
538
61a4dcc2
FR		 539 /* Config3 register p.25 */
540 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
541 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
d58d46b5 542 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
b51ecea8 543 Rdy_to_L23 = (1 << 1), /* L23 Enable */
f162a5d1 544 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 545
d58d46b5
FR		 546 /* Config4 register */
547 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
548
5d06a99f 549 /* Config5 register p.27 */
61a4dcc2
FR		 550 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
551 MWF = (1 << 5), /* Accept Multicast wakeup frame */
552 UWF = (1 << 4), /* Accept Unicast wakeup frame */
cecb5fd7 553 Spi_en = (1 << 3),
61a4dcc2 554 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f 555 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
57538c4a 556 ASPM_en = (1 << 0), /* ASPM enable */
5d06a99f 557
1da177e4
LT		 558 /* TBICSR p.28 */
559 TBIReset = 0x80000000,
560 TBILoopback = 0x40000000,
561 TBINwEnable = 0x20000000,
562 TBINwRestart = 0x10000000,
563 TBILinkOk = 0x02000000,
564 TBINwComplete = 0x01000000,
565
566 /* CPlusCmd p.31 */
f162a5d1
FR		 567 EnableBist = (1 << 15), // 8168 8101
568 Mac_dbgo_oe = (1 << 14), // 8168 8101
569 Normal_mode = (1 << 13), // unused
570 Force_half_dup = (1 << 12), // 8168 8101
571 Force_rxflow_en = (1 << 11), // 8168 8101
572 Force_txflow_en = (1 << 10), // 8168 8101
573 Cxpl_dbg_sel = (1 << 9), // 8168 8101
574 ASF = (1 << 8), // 8168 8101
575 PktCntrDisable = (1 << 7), // 8168 8101
576 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 577 RxVlan = (1 << 6),
578 RxChkSum = (1 << 5),
579 PCIDAC = (1 << 4),
580 PCIMulRW = (1 << 3),
0e485150
FR		 581 INTT_0 = 0x0000, // 8168
582 INTT_1 = 0x0001, // 8168
583 INTT_2 = 0x0002, // 8168
584 INTT_3 = 0x0003, // 8168
1da177e4
LT		 585
586 /* rtl8169_PHYstatus */
07d3f51f
FR		 587 TBI_Enable = 0x80,
588 TxFlowCtrl = 0x40,
589 RxFlowCtrl = 0x20,
590 _1000bpsF = 0x10,
591 _100bps = 0x08,
592 _10bps = 0x04,
593 LinkStatus = 0x02,
594 FullDup = 0x01,
1da177e4 595
1da177e4 596 /* _TBICSRBit */
07d3f51f 597 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 598
599 /* DumpCounterCommand */
07d3f51f 600 CounterDump = 0x8,
1da177e4
LT		 601};
602
2b7b4318
FR		 603enum rtl_desc_bit {
604 /* First doubleword. */
1da177e4
LT		 605 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
606 RingEnd = (1 << 30), /* End of descriptor ring */
607 FirstFrag = (1 << 29), /* First segment of a packet */
608 LastFrag = (1 << 28), /* Final segment of a packet */
2b7b4318
FR		 609};
610
611/* Generic case. */
612enum rtl_tx_desc_bit {
613 /* First doubleword. */
614 TD_LSO = (1 << 27), /* Large Send Offload */
615#define TD_MSS_MAX 0x07ffu /* MSS value */
1da177e4 616
2b7b4318
FR		 617 /* Second doubleword. */
618 TxVlanTag = (1 << 17), /* Add VLAN tag */
619};
620
621/* 8169, 8168b and 810x except 8102e. */
622enum rtl_tx_desc_bit_0 {
623 /* First doubleword. */
624#define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
625 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
626 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
627 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
628};
629
630/* 8102e, 8168c and beyond. */
631enum rtl_tx_desc_bit_1 {
bdfa4ed6 632 /* First doubleword. */
633 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */
e974604b 634 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */
bdfa4ed6 635#define GTTCPHO_SHIFT 18
e974604b 636#define GTTCPHO_MAX 0x7fU
bdfa4ed6 637
2b7b4318 638 /* Second doubleword. */
e974604b 639#define TCPHO_SHIFT 18
640#define TCPHO_MAX 0x3ffU
2b7b4318 641#define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
e974604b 642 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */
643 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */
2b7b4318
FR		 644 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
645 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
646};
1da177e4 647
2b7b4318 648enum rtl_rx_desc_bit {
1da177e4
LT		 649 /* Rx private */
650 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
651 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
652
653#define RxProtoUDP (PID1)
654#define RxProtoTCP (PID0)
655#define RxProtoIP (PID1 | PID0)
656#define RxProtoMask RxProtoIP
657
658 IPFail = (1 << 16), /* IP checksum failed */
659 UDPFail = (1 << 15), /* UDP/IP checksum failed */
660 TCPFail = (1 << 14), /* TCP/IP checksum failed */
661 RxVlanTag = (1 << 16), /* VLAN tag available */
662};
663
664#define RsvdMask 0x3fffc000
665
666struct TxDesc {
6cccd6e7
REB		 667 __le32 opts1;
668 __le32 opts2;
669 __le64 addr;
1da177e4
LT		 670};
671
672struct RxDesc {
6cccd6e7
REB		 673 __le32 opts1;
674 __le32 opts2;
675 __le64 addr;
1da177e4
LT		 676};
677
678struct ring_info {
679 struct sk_buff *skb;
680 u32 len;
681 u8 __pad[sizeof(void *) - sizeof(u32)];
682};
683
f23e7fda 684enum features {
ccdffb9a
FR		 685 RTL_FEATURE_WOL = (1 << 0),
686 RTL_FEATURE_MSI = (1 << 1),
687 RTL_FEATURE_GMII = (1 << 2),
f23e7fda
FR		 688};
689
355423d0
IV		 690struct rtl8169_counters {
691 __le64 tx_packets;
692 __le64 rx_packets;
693 __le64 tx_errors;
694 __le32 rx_errors;
695 __le16 rx_missed;
696 __le16 align_errors;
697 __le32 tx_one_collision;
698 __le32 tx_multi_collision;
699 __le64 rx_unicast;
700 __le64 rx_broadcast;
701 __le32 rx_multicast;
702 __le16 tx_aborted;
703 __le16 tx_underun;
704};
705
da78dbff 706enum rtl_flag {
6c4a70c5 707 RTL_FLAG_TASK_ENABLED,
da78dbff
FR		 708 RTL_FLAG_TASK_SLOW_PENDING,
709 RTL_FLAG_TASK_RESET_PENDING,
710 RTL_FLAG_TASK_PHY_PENDING,
711 RTL_FLAG_MAX
712};
713
8027aa24
JW		 714struct rtl8169_stats {
715 u64 packets;
716 u64 bytes;
717 struct u64_stats_sync syncp;
718};
719
1da177e4
LT		 720struct rtl8169_private {
721 void __iomem *mmio_addr; /* memory map physical address */
cecb5fd7 722 struct pci_dev *pci_dev;
c4028958 723 struct net_device *dev;
bea3348e 724 struct napi_struct napi;
b57b7e5a 725 u32 msg_enable;
2b7b4318
FR		 726 u16 txd_version;
727 u16 mac_version;
1da177e4
LT		 728 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
729 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
1da177e4 730 u32 dirty_tx;
8027aa24
JW		 731 struct rtl8169_stats rx_stats;
732 struct rtl8169_stats tx_stats;
1da177e4
LT		 733 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
734 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
735 dma_addr_t TxPhyAddr;
736 dma_addr_t RxPhyAddr;
6f0333b8 737 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
1da177e4 738 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
1da177e4
LT		 739 struct timer_list timer;
740 u16 cp_cmd;
da78dbff
FR		 741
742 u16 event_slow;
c0e45c1c 743
744 struct mdio_ops {
24192210
FR		 745 void (*write)(struct rtl8169_private *, int, int);
746 int (*read)(struct rtl8169_private *, int);
c0e45c1c 747 } mdio_ops;
748
065c27c1 749 struct pll_power_ops {
750 void (*down)(struct rtl8169_private *);
751 void (*up)(struct rtl8169_private *);
752 } pll_power_ops;
753
d58d46b5
FR		 754 struct jumbo_ops {
755 void (*enable)(struct rtl8169_private *);
756 void (*disable)(struct rtl8169_private *);
757 } jumbo_ops;
758
beb1fe18 759 struct csi_ops {
52989f0e
FR		 760 void (*write)(struct rtl8169_private *, int, int);
761 u32 (*read)(struct rtl8169_private *, int);
beb1fe18
HW		 762 } csi_ops;
763
54405cde 764 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
ccdffb9a 765 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
4da19633 766 void (*phy_reset_enable)(struct rtl8169_private *tp);
07ce4064 767 void (*hw_start)(struct net_device *);
4da19633 768 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
1da177e4 769 unsigned int (*link_ok)(void __iomem *);
8b4ab28d 770 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
5888d3fc 771 bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
4422bcd4
FR		 772
773 struct {
da78dbff
FR		 774 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
775 struct mutex mutex;
4422bcd4
FR		 776 struct work_struct work;
777 } wk;
778
f23e7fda 779 unsigned features;
ccdffb9a
FR		 780
781 struct mii_if_info mii;
355423d0 782 struct rtl8169_counters counters;
e1759441 783 u32 saved_wolopts;
e03f33af 784 u32 opts1_mask;
f1e02ed1 785
b6ffd97f
FR		 786 struct rtl_fw {
787 const struct firmware *fw;
1c361efb
FR		 788
789#define RTL_VER_SIZE 32
790
791 char version[RTL_VER_SIZE];
792
793 struct rtl_fw_phy_action {
794 __le32 *code;
795 size_t size;
796 } phy_action;
b6ffd97f 797 } *rtl_fw;
497888cf 798#define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
c558386b
HW		 799
800 u32 ocp_base;
1da177e4
LT		 801};
802
979b6c13 803MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 804MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 805module_param(use_dac, int, 0);
4300e8c7 806MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 807module_param_named(debug, debug.msg_enable, int, 0);
808MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 809MODULE_LICENSE("GPL");
810MODULE_VERSION(RTL8169_VERSION);
bca03d5f 811MODULE_FIRMWARE(FIRMWARE_8168D_1);
812MODULE_FIRMWARE(FIRMWARE_8168D_2);
01dc7fec 813MODULE_FIRMWARE(FIRMWARE_8168E_1);
814MODULE_FIRMWARE(FIRMWARE_8168E_2);
bbb8af75 815MODULE_FIRMWARE(FIRMWARE_8168E_3);
5a5e4443 816MODULE_FIRMWARE(FIRMWARE_8105E_1);
c2218925
HW		 817MODULE_FIRMWARE(FIRMWARE_8168F_1);
818MODULE_FIRMWARE(FIRMWARE_8168F_2);
7e18dca1 819MODULE_FIRMWARE(FIRMWARE_8402_1);
b3d7b2f2 820MODULE_FIRMWARE(FIRMWARE_8411_1);
45dd95c4 821MODULE_FIRMWARE(FIRMWARE_8411_2);
5598bfe5 822MODULE_FIRMWARE(FIRMWARE_8106E_1);
58152cd4 823MODULE_FIRMWARE(FIRMWARE_8106E_2);
beb330a4 824MODULE_FIRMWARE(FIRMWARE_8168G_2);
57538c4a 825MODULE_FIRMWARE(FIRMWARE_8168G_3);
1da177e4 826
da78dbff
FR		 827static void rtl_lock_work(struct rtl8169_private *tp)
828{
829 mutex_lock(&tp->wk.mutex);
830}
831
832static void rtl_unlock_work(struct rtl8169_private *tp)
833{
834 mutex_unlock(&tp->wk.mutex);
835}
836
d58d46b5
FR		 837static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
838{
7d7903b2
JL		 839 pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
840 PCI_EXP_DEVCTL_READRQ, force);
d58d46b5
FR		 841}
842
ffc46952
FR		 843struct rtl_cond {
844 bool (*check)(struct rtl8169_private *);
845 const char *msg;
846};
847
848static void rtl_udelay(unsigned int d)
849{
850 udelay(d);
851}
852
853static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
854 void (*delay)(unsigned int), unsigned int d, int n,
855 bool high)
856{
857 int i;
858
859 for (i = 0; i < n; i++) {
860 delay(d);
861 if (c->check(tp) == high)
862 return true;
863 }
82e316ef
FR		 864 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
865 c->msg, !high, n, d);
ffc46952
FR		 866 return false;
867}
868
869static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
870 const struct rtl_cond *c,
871 unsigned int d, int n)
872{
873 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
874}
875
876static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
877 const struct rtl_cond *c,
878 unsigned int d, int n)
879{
880 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
881}
882
883static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
884 const struct rtl_cond *c,
885 unsigned int d, int n)
886{
887 return rtl_loop_wait(tp, c, msleep, d, n, true);
888}
889
890static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
891 const struct rtl_cond *c,
892 unsigned int d, int n)
893{
894 return rtl_loop_wait(tp, c, msleep, d, n, false);
895}
896
897#define DECLARE_RTL_COND(name) \
898static bool name ## _check(struct rtl8169_private *); \
899 \
900static const struct rtl_cond name = { \
901 .check = name ## _check, \
902 .msg = #name \
903}; \
904 \
905static bool name ## _check(struct rtl8169_private *tp)
906
907DECLARE_RTL_COND(rtl_ocpar_cond)
908{
909 void __iomem *ioaddr = tp->mmio_addr;
910
911 return RTL_R32(OCPAR) & OCPAR_FLAG;
912}
913
b646d900 914static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
915{
916 void __iomem *ioaddr = tp->mmio_addr;
b646d900 917
918 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
ffc46952
FR		 919
920 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
921 RTL_R32(OCPDR) : ~0;
b646d900 922}
923
924static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
925{
926 void __iomem *ioaddr = tp->mmio_addr;
b646d900 927
928 RTL_W32(OCPDR, data);
929 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
ffc46952
FR		 930
931 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
932}
933
934DECLARE_RTL_COND(rtl_eriar_cond)
935{
936 void __iomem *ioaddr = tp->mmio_addr;
937
938 return RTL_R32(ERIAR) & ERIAR_FLAG;
b646d900 939}
940
fac5b3ca 941static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
b646d900 942{
fac5b3ca 943 void __iomem *ioaddr = tp->mmio_addr;
b646d900 944
945 RTL_W8(ERIDR, cmd);
946 RTL_W32(ERIAR, 0x800010e8);
947 msleep(2);
ffc46952
FR		 948
949 if (!rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 5))
950 return;
b646d900 951
fac5b3ca 952 ocp_write(tp, 0x1, 0x30, 0x00000001);
b646d900 953}
954
955#define OOB_CMD_RESET 0x00
956#define OOB_CMD_DRIVER_START 0x05
957#define OOB_CMD_DRIVER_STOP 0x06
958
cecb5fd7
FR		 959static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
960{
961 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
962}
963
ffc46952 964DECLARE_RTL_COND(rtl_ocp_read_cond)
b646d900 965{
cecb5fd7 966 u16 reg;
b646d900 967
cecb5fd7 968 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 969
ffc46952 970 return ocp_read(tp, 0x0f, reg) & 0x00000800;
b646d900 971}
972
ffc46952 973static void rtl8168_driver_start(struct rtl8169_private *tp)
b646d900 974{
ffc46952 975 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
b646d900 976
ffc46952
FR		 977 rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
978}
b646d900 979
ffc46952
FR		 980static void rtl8168_driver_stop(struct rtl8169_private *tp)
981{
982 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
4804b3b3 983
ffc46952 984 rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
b646d900 985}
986
4804b3b3 987static int r8168dp_check_dash(struct rtl8169_private *tp)
988{
cecb5fd7 989 u16 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 990
cecb5fd7 991 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
4804b3b3 992}
b646d900 993
c558386b
HW		 994static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
995{
996 if (reg & 0xffff0001) {
997 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
998 return true;
999 }
1000 return false;
1001}
1002
1003DECLARE_RTL_COND(rtl_ocp_gphy_cond)
1004{
1005 void __iomem *ioaddr = tp->mmio_addr;
1006
1007 return RTL_R32(GPHY_OCP) & OCPAR_FLAG;
1008}
1009
1010static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1011{
1012 void __iomem *ioaddr = tp->mmio_addr;
1013
1014 if (rtl_ocp_reg_failure(tp, reg))
1015 return;
1016
1017 RTL_W32(GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
1018
1019 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
1020}
1021
1022static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
1023{
1024 void __iomem *ioaddr = tp->mmio_addr;
1025
1026 if (rtl_ocp_reg_failure(tp, reg))
1027 return 0;
1028
1029 RTL_W32(GPHY_OCP, reg << 15);
1030
1031 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
1032 (RTL_R32(GPHY_OCP) & 0xffff) : ~0;
1033}
1034
c558386b
HW		 1035static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1036{
1037 void __iomem *ioaddr = tp->mmio_addr;
1038
1039 if (rtl_ocp_reg_failure(tp, reg))
1040 return;
1041
1042 RTL_W32(OCPDR, OCPAR_FLAG | (reg << 15) | data);
c558386b
HW		 1043}
1044
1045static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1046{
1047 void __iomem *ioaddr = tp->mmio_addr;
1048
1049 if (rtl_ocp_reg_failure(tp, reg))
1050 return 0;
1051
1052 RTL_W32(OCPDR, reg << 15);
1053
3a83ad12 1054 return RTL_R32(OCPDR);
c558386b
HW		 1055}
1056
1057#define OCP_STD_PHY_BASE 0xa400
1058
1059static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
1060{
1061 if (reg == 0x1f) {
1062 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
1063 return;
1064 }
1065
1066 if (tp->ocp_base != OCP_STD_PHY_BASE)
1067 reg -= 0x10;
1068
1069 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
1070}
1071
1072static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1073{
1074 if (tp->ocp_base != OCP_STD_PHY_BASE)
1075 reg -= 0x10;
1076
1077 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
1078}
1079
eee3786f 1080static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
1081{
1082 if (reg == 0x1f) {
1083 tp->ocp_base = value << 4;
1084 return;
1085 }
1086
1087 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
1088}
1089
1090static int mac_mcu_read(struct rtl8169_private *tp, int reg)
1091{
1092 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
1093}
1094
ffc46952
FR		 1095DECLARE_RTL_COND(rtl_phyar_cond)
1096{
1097 void __iomem *ioaddr = tp->mmio_addr;
1098
1099 return RTL_R32(PHYAR) & 0x80000000;
1100}
1101
24192210 1102static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1da177e4 1103{
24192210 1104 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 1105
24192210 1106 RTL_W32(PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1da177e4 1107
ffc46952 1108 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
024a07ba 1109 /*
81a95f04
TT		 1110 * According to hardware specs a 20us delay is required after write
1111 * complete indication, but before sending next command.
024a07ba 1112 */
81a95f04 1113 udelay(20);
1da177e4
LT		 1114}
1115
24192210 1116static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1da177e4 1117{
24192210 1118 void __iomem *ioaddr = tp->mmio_addr;
ffc46952 1119 int value;
1da177e4 1120
24192210 1121 RTL_W32(PHYAR, 0x0 | (reg & 0x1f) << 16);
1da177e4 1122
ffc46952
FR		 1123 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1124 RTL_R32(PHYAR) & 0xffff : ~0;
1125
81a95f04
TT		 1126 /*
1127 * According to hardware specs a 20us delay is required after read
1128 * complete indication, but before sending next command.
1129 */
1130 udelay(20);
1131
1da177e4
LT		 1132 return value;
1133}
1134
24192210 1135static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
c0e45c1c 1136{
24192210 1137 void __iomem *ioaddr = tp->mmio_addr;
c0e45c1c 1138
24192210 1139 RTL_W32(OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
c0e45c1c 1140 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
1141 RTL_W32(EPHY_RXER_NUM, 0);
1142
ffc46952 1143 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
c0e45c1c 1144}
1145
24192210 1146static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
c0e45c1c 1147{
24192210
FR		 1148 r8168dp_1_mdio_access(tp, reg,
1149 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
c0e45c1c 1150}
1151
24192210 1152static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
c0e45c1c 1153{
24192210 1154 void __iomem *ioaddr = tp->mmio_addr;
c0e45c1c 1155
24192210 1156 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
c0e45c1c 1157
1158 mdelay(1);
1159 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
1160 RTL_W32(EPHY_RXER_NUM, 0);
1161
ffc46952
FR		 1162 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1163 RTL_R32(OCPDR) & OCPDR_DATA_MASK : ~0;
c0e45c1c 1164}
1165
e6de30d6 1166#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1167
1168static void r8168dp_2_mdio_start(void __iomem *ioaddr)
1169{
1170 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1171}
1172
1173static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
1174{
1175 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1176}
1177
24192210 1178static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
e6de30d6 1179{
24192210
FR		 1180 void __iomem *ioaddr = tp->mmio_addr;
1181
e6de30d6 1182 r8168dp_2_mdio_start(ioaddr);
1183
24192210 1184 r8169_mdio_write(tp, reg, value);
e6de30d6 1185
1186 r8168dp_2_mdio_stop(ioaddr);
1187}
1188
24192210 1189static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
e6de30d6 1190{
24192210 1191 void __iomem *ioaddr = tp->mmio_addr;
e6de30d6 1192 int value;
1193
1194 r8168dp_2_mdio_start(ioaddr);
1195
24192210 1196 value = r8169_mdio_read(tp, reg);
e6de30d6 1197
1198 r8168dp_2_mdio_stop(ioaddr);
1199
1200 return value;
1201}
1202
4da19633 1203static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
dacf8154 1204{
24192210 1205 tp->mdio_ops.write(tp, location, val);
dacf8154
FR		 1206}
1207
4da19633 1208static int rtl_readphy(struct rtl8169_private *tp, int location)
1209{
24192210 1210 return tp->mdio_ops.read(tp, location);
4da19633 1211}
1212
1213static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1214{
1215 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1216}
1217
1218static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
daf9df6d 1219{
1220 int val;
1221
4da19633 1222 val = rtl_readphy(tp, reg_addr);
1223 rtl_writephy(tp, reg_addr, (val | p) & ~m);
daf9df6d 1224}
1225
ccdffb9a
FR		 1226static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1227 int val)
1228{
1229 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1230
4da19633 1231 rtl_writephy(tp, location, val);
ccdffb9a
FR		 1232}
1233
1234static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1235{
1236 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1237
4da19633 1238 return rtl_readphy(tp, location);
ccdffb9a
FR		 1239}
1240
ffc46952
FR		 1241DECLARE_RTL_COND(rtl_ephyar_cond)
1242{
1243 void __iomem *ioaddr = tp->mmio_addr;
1244
1245 return RTL_R32(EPHYAR) & EPHYAR_FLAG;
1246}
1247
fdf6fc06 1248static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
dacf8154 1249{
fdf6fc06 1250 void __iomem *ioaddr = tp->mmio_addr;
dacf8154
FR		 1251
1252 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1253 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1254
ffc46952
FR		 1255 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1256
1257 udelay(10);
dacf8154
FR		 1258}
1259
fdf6fc06 1260static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
dacf8154 1261{
fdf6fc06 1262 void __iomem *ioaddr = tp->mmio_addr;
dacf8154
FR		 1263
1264 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1265
ffc46952
FR		 1266 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1267 RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0;
dacf8154
FR		 1268}
1269
fdf6fc06
FR		 1270static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1271 u32 val, int type)
133ac40a 1272{
fdf6fc06 1273 void __iomem *ioaddr = tp->mmio_addr;
133ac40a
HW		 1274
1275 BUG_ON((addr & 3) || (mask == 0));
1276 RTL_W32(ERIDR, val);
1277 RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1278
ffc46952 1279 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
133ac40a
HW		 1280}
1281
fdf6fc06 1282static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
133ac40a 1283{
fdf6fc06 1284 void __iomem *ioaddr = tp->mmio_addr;
133ac40a
HW		 1285
1286 RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1287
ffc46952
FR		 1288 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1289 RTL_R32(ERIDR) : ~0;
133ac40a
HW		 1290}
1291
fdf6fc06
FR		 1292static void rtl_w1w0_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1293 u32 m, int type)
133ac40a
HW		 1294{
1295 u32 val;
1296
fdf6fc06
FR		 1297 val = rtl_eri_read(tp, addr, type);
1298 rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
133ac40a
HW		 1299}
1300
c28aa385 1301struct exgmac_reg {
1302 u16 addr;
1303 u16 mask;
1304 u32 val;
1305};
1306
fdf6fc06 1307static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
c28aa385 1308 const struct exgmac_reg *r, int len)
1309{
1310 while (len-- > 0) {
fdf6fc06 1311 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
c28aa385 1312 r++;
1313 }
1314}
1315
ffc46952
FR		 1316DECLARE_RTL_COND(rtl_efusear_cond)
1317{
1318 void __iomem *ioaddr = tp->mmio_addr;
1319
1320 return RTL_R32(EFUSEAR) & EFUSEAR_FLAG;
1321}
1322
fdf6fc06 1323static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
daf9df6d 1324{
fdf6fc06 1325 void __iomem *ioaddr = tp->mmio_addr;
daf9df6d 1326
1327 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1328
ffc46952
FR		 1329 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1330 RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
daf9df6d 1331}
1332
9085cdfa
FR		 1333static u16 rtl_get_events(struct rtl8169_private *tp)
1334{
1335 void __iomem *ioaddr = tp->mmio_addr;
1336
1337 return RTL_R16(IntrStatus);
1338}
1339
1340static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1341{
1342 void __iomem *ioaddr = tp->mmio_addr;
1343
1344 RTL_W16(IntrStatus, bits);
1345 mmiowb();
1346}
1347
1348static void rtl_irq_disable(struct rtl8169_private *tp)
1349{
1350 void __iomem *ioaddr = tp->mmio_addr;
1351
1352 RTL_W16(IntrMask, 0);
1353 mmiowb();
1354}
1355
3e990ff5
FR		 1356static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1357{
1358 void __iomem *ioaddr = tp->mmio_addr;
1359
1360 RTL_W16(IntrMask, bits);
1361}
1362
da78dbff
FR		 1363#define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1364#define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1365#define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1366
1367static void rtl_irq_enable_all(struct rtl8169_private *tp)
1368{
1369 rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1370}
1371
811fd301 1372static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1da177e4 1373{
811fd301 1374 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 1375
9085cdfa 1376 rtl_irq_disable(tp);
da78dbff 1377 rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
811fd301 1378 RTL_R8(ChipCmd);
1da177e4
LT		 1379}
1380
4da19633 1381static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1da177e4 1382{
4da19633 1383 void __iomem *ioaddr = tp->mmio_addr;
1384
1da177e4
LT		 1385 return RTL_R32(TBICSR) & TBIReset;
1386}
1387
4da19633 1388static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1da177e4 1389{
4da19633 1390 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 1391}
1392
1393static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1394{
1395 return RTL_R32(TBICSR) & TBILinkOk;
1396}
1397
1398static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1399{
1400 return RTL_R8(PHYstatus) & LinkStatus;
1401}
1402
4da19633 1403static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1da177e4 1404{
4da19633 1405 void __iomem *ioaddr = tp->mmio_addr;
1406
1da177e4
LT		 1407 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1408}
1409
4da19633 1410static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1da177e4
LT		 1411{
1412 unsigned int val;
1413
4da19633 1414 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1415 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1da177e4
LT		 1416}
1417
70090424
HW		 1418static void rtl_link_chg_patch(struct rtl8169_private *tp)
1419{
1420 void __iomem *ioaddr = tp->mmio_addr;
1421 struct net_device *dev = tp->dev;
1422
1423 if (!netif_running(dev))
1424 return;
1425
b3d7b2f2
HW		 1426 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1427 tp->mac_version == RTL_GIGA_MAC_VER_38) {
70090424 1428 if (RTL_R8(PHYstatus) & _1000bpsF) {
fdf6fc06
FR		 1429 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1430 ERIAR_EXGMAC);
1431 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1432 ERIAR_EXGMAC);
70090424 1433 } else if (RTL_R8(PHYstatus) & _100bps) {
fdf6fc06
FR		 1434 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1435 ERIAR_EXGMAC);
1436 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1437 ERIAR_EXGMAC);
70090424 1438 } else {
fdf6fc06
FR		 1439 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1440 ERIAR_EXGMAC);
1441 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1442 ERIAR_EXGMAC);
70090424
HW		 1443 }
1444 /* Reset packet filter */
fdf6fc06 1445 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
70090424 1446 ERIAR_EXGMAC);
fdf6fc06 1447 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
70090424 1448 ERIAR_EXGMAC);
c2218925
HW		 1449 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1450 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1451 if (RTL_R8(PHYstatus) & _1000bpsF) {
fdf6fc06
FR		 1452 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1453 ERIAR_EXGMAC);
1454 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1455 ERIAR_EXGMAC);
c2218925 1456 } else {
fdf6fc06
FR		 1457 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1458 ERIAR_EXGMAC);
1459 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1460 ERIAR_EXGMAC);
c2218925 1461 }
7e18dca1
HW		 1462 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1463 if (RTL_R8(PHYstatus) & _10bps) {
fdf6fc06
FR		 1464 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1465 ERIAR_EXGMAC);
1466 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1467 ERIAR_EXGMAC);
7e18dca1 1468 } else {
fdf6fc06
FR		 1469 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1470 ERIAR_EXGMAC);
7e18dca1 1471 }
70090424
HW		 1472 }
1473}
1474
e4fbce74 1475static void __rtl8169_check_link_status(struct net_device *dev,
cecb5fd7
FR		 1476 struct rtl8169_private *tp,
1477 void __iomem *ioaddr, bool pm)
1da177e4 1478{
1da177e4 1479 if (tp->link_ok(ioaddr)) {
70090424 1480 rtl_link_chg_patch(tp);
e1759441 1481 /* This is to cancel a scheduled suspend if there's one. */
e4fbce74
RW		 1482 if (pm)
1483 pm_request_resume(&tp->pci_dev->dev);
1da177e4 1484 netif_carrier_on(dev);
1519e57f
FR		 1485 if (net_ratelimit())
1486 netif_info(tp, ifup, dev, "link up\n");
b57b7e5a 1487 } else {
1da177e4 1488 netif_carrier_off(dev);
bf82c189 1489 netif_info(tp, ifdown, dev, "link down\n");
e4fbce74 1490 if (pm)
10953db8 1491 pm_schedule_suspend(&tp->pci_dev->dev, 5000);
b57b7e5a 1492 }
1da177e4
LT		 1493}
1494
e4fbce74
RW		 1495static void rtl8169_check_link_status(struct net_device *dev,
1496 struct rtl8169_private *tp,
1497 void __iomem *ioaddr)
1498{
1499 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1500}
1501
e1759441
RW		 1502#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1503
1504static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
61a4dcc2 1505{
61a4dcc2
FR		 1506 void __iomem *ioaddr = tp->mmio_addr;
1507 u8 options;
e1759441 1508 u32 wolopts = 0;
61a4dcc2
FR		 1509
1510 options = RTL_R8(Config1);
1511 if (!(options & PMEnable))
e1759441 1512 return 0;
61a4dcc2
FR		 1513
1514 options = RTL_R8(Config3);
1515 if (options & LinkUp)
e1759441 1516 wolopts |= WAKE_PHY;
61a4dcc2 1517 if (options & MagicPacket)
e1759441 1518 wolopts |= WAKE_MAGIC;
61a4dcc2
FR		 1519
1520 options = RTL_R8(Config5);
1521 if (options & UWF)
e1759441 1522 wolopts |= WAKE_UCAST;
61a4dcc2 1523 if (options & BWF)
e1759441 1524 wolopts |= WAKE_BCAST;
61a4dcc2 1525 if (options & MWF)
e1759441 1526 wolopts |= WAKE_MCAST;
61a4dcc2 1527
e1759441 1528 return wolopts;
61a4dcc2
FR		 1529}
1530
e1759441 1531static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
61a4dcc2
FR		 1532{
1533 struct rtl8169_private *tp = netdev_priv(dev);
e1759441 1534
da78dbff 1535 rtl_lock_work(tp);
e1759441
RW		 1536
1537 wol->supported = WAKE_ANY;
1538 wol->wolopts = __rtl8169_get_wol(tp);
1539
da78dbff 1540 rtl_unlock_work(tp);
e1759441
RW		 1541}
1542
1543static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1544{
61a4dcc2 1545 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1546 unsigned int i;
350f7596 1547 static const struct {
61a4dcc2
FR		 1548 u32 opt;
1549 u16 reg;
1550 u8 mask;
1551 } cfg[] = {
61a4dcc2
FR		 1552 { WAKE_PHY, Config3, LinkUp },
1553 { WAKE_MAGIC, Config3, MagicPacket },
1554 { WAKE_UCAST, Config5, UWF },
1555 { WAKE_BCAST, Config5, BWF },
1556 { WAKE_MCAST, Config5, MWF },
1557 { WAKE_ANY, Config5, LanWake }
1558 };
851e6022 1559 u8 options;
61a4dcc2 1560
61a4dcc2
FR		 1561 RTL_W8(Cfg9346, Cfg9346_Unlock);
1562
1563 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
851e6022 1564 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
e1759441 1565 if (wolopts & cfg[i].opt)
61a4dcc2
FR		 1566 options |= cfg[i].mask;
1567 RTL_W8(cfg[i].reg, options);
1568 }
1569
851e6022
FR		 1570 switch (tp->mac_version) {
1571 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1572 options = RTL_R8(Config1) & ~PMEnable;
1573 if (wolopts)
1574 options |= PMEnable;
1575 RTL_W8(Config1, options);
1576 break;
1577 default:
d387b427
FR		 1578 options = RTL_R8(Config2) & ~PME_SIGNAL;
1579 if (wolopts)
1580 options |= PME_SIGNAL;
1581 RTL_W8(Config2, options);
851e6022
FR		 1582 break;
1583 }
1584
61a4dcc2 1585 RTL_W8(Cfg9346, Cfg9346_Lock);
e1759441
RW		 1586}
1587
1588static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1589{
1590 struct rtl8169_private *tp = netdev_priv(dev);
1591
da78dbff 1592 rtl_lock_work(tp);
61a4dcc2 1593
f23e7fda
FR		 1594 if (wol->wolopts)
1595 tp->features |= RTL_FEATURE_WOL;
1596 else
1597 tp->features &= ~RTL_FEATURE_WOL;
e1759441 1598 __rtl8169_set_wol(tp, wol->wolopts);
da78dbff
FR		 1599
1600 rtl_unlock_work(tp);
61a4dcc2 1601
ea80907f 1602 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1603
61a4dcc2
FR		 1604 return 0;
1605}
1606
31bd204f
FR		 1607static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1608{
85bffe6c 1609 return rtl_chip_infos[tp->mac_version].fw_name;
31bd204f
FR		 1610}
1611
1da177e4
LT		 1612static void rtl8169_get_drvinfo(struct net_device *dev,
1613 struct ethtool_drvinfo *info)
1614{
1615 struct rtl8169_private *tp = netdev_priv(dev);
b6ffd97f 1616 struct rtl_fw *rtl_fw = tp->rtl_fw;
1da177e4 1617
68aad78c
RJ		 1618 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1619 strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1620 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1c361efb 1621 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
8ac72d16
RJ		 1622 if (!IS_ERR_OR_NULL(rtl_fw))
1623 strlcpy(info->fw_version, rtl_fw->version,
1624 sizeof(info->fw_version));
1da177e4
LT		 1625}
1626
1627static int rtl8169_get_regs_len(struct net_device *dev)
1628{
1629 return R8169_REGS_SIZE;
1630}
1631
1632static int rtl8169_set_speed_tbi(struct net_device *dev,
54405cde 1633 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1da177e4
LT		 1634{
1635 struct rtl8169_private *tp = netdev_priv(dev);
1636 void __iomem *ioaddr = tp->mmio_addr;
1637 int ret = 0;
1638 u32 reg;
1639
1640 reg = RTL_R32(TBICSR);
1641 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1642 (duplex == DUPLEX_FULL)) {
1643 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1644 } else if (autoneg == AUTONEG_ENABLE)
1645 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1646 else {
bf82c189
JP		 1647 netif_warn(tp, link, dev,
1648 "incorrect speed setting refused in TBI mode\n");
1da177e4
LT		 1649 ret = -EOPNOTSUPP;
1650 }
1651
1652 return ret;
1653}
1654
1655static int rtl8169_set_speed_xmii(struct net_device *dev,
54405cde 1656 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1da177e4
LT		 1657{
1658 struct rtl8169_private *tp = netdev_priv(dev);
3577aa1b 1659 int giga_ctrl, bmcr;
54405cde 1660 int rc = -EINVAL;
1da177e4 1661
716b50a3 1662 rtl_writephy(tp, 0x1f, 0x0000);
1da177e4
LT		 1663
1664 if (autoneg == AUTONEG_ENABLE) {
3577aa1b 1665 int auto_nego;
1666
4da19633 1667 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
54405cde
ON		 1668 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1669 ADVERTISE_100HALF | ADVERTISE_100FULL);
1670
1671 if (adv & ADVERTISED_10baseT_Half)
1672 auto_nego |= ADVERTISE_10HALF;
1673 if (adv & ADVERTISED_10baseT_Full)
1674 auto_nego |= ADVERTISE_10FULL;
1675 if (adv & ADVERTISED_100baseT_Half)
1676 auto_nego |= ADVERTISE_100HALF;
1677 if (adv & ADVERTISED_100baseT_Full)
1678 auto_nego |= ADVERTISE_100FULL;
1679
3577aa1b 1680 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1da177e4 1681
4da19633 1682 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
3577aa1b 1683 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
bcf0bf90 1684
3577aa1b 1685 /* The 8100e/8101e/8102e do Fast Ethernet only. */
826e6cbd 1686 if (tp->mii.supports_gmii) {
54405cde
ON		 1687 if (adv & ADVERTISED_1000baseT_Half)
1688 giga_ctrl |= ADVERTISE_1000HALF;
1689 if (adv & ADVERTISED_1000baseT_Full)
1690 giga_ctrl |= ADVERTISE_1000FULL;
1691 } else if (adv & (ADVERTISED_1000baseT_Half |
1692 ADVERTISED_1000baseT_Full)) {
bf82c189
JP		 1693 netif_info(tp, link, dev,
1694 "PHY does not support 1000Mbps\n");
54405cde 1695 goto out;
bcf0bf90 1696 }
1da177e4 1697
3577aa1b 1698 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1699
4da19633 1700 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1701 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
3577aa1b 1702 } else {
1703 giga_ctrl = 0;
1704
1705 if (speed == SPEED_10)
1706 bmcr = 0;
1707 else if (speed == SPEED_100)
1708 bmcr = BMCR_SPEED100;
1709 else
54405cde 1710 goto out;
3577aa1b 1711
1712 if (duplex == DUPLEX_FULL)
1713 bmcr |= BMCR_FULLDPLX;
2584fbc3
RS		 1714 }
1715
4da19633 1716 rtl_writephy(tp, MII_BMCR, bmcr);
3577aa1b 1717
cecb5fd7
FR		 1718 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1719 tp->mac_version == RTL_GIGA_MAC_VER_03) {
3577aa1b 1720 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
4da19633 1721 rtl_writephy(tp, 0x17, 0x2138);
1722 rtl_writephy(tp, 0x0e, 0x0260);
3577aa1b 1723 } else {
4da19633 1724 rtl_writephy(tp, 0x17, 0x2108);
1725 rtl_writephy(tp, 0x0e, 0x0000);
3577aa1b 1726 }
1727 }
1728
54405cde
ON		 1729 rc = 0;
1730out:
1731 return rc;
1da177e4
LT		 1732}
1733
1734static int rtl8169_set_speed(struct net_device *dev,
54405cde 1735 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1da177e4
LT		 1736{
1737 struct rtl8169_private *tp = netdev_priv(dev);
1738 int ret;
1739
54405cde 1740 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
4876cc1e
FR		 1741 if (ret < 0)
1742 goto out;
1da177e4 1743
4876cc1e
FR		 1744 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1745 (advertising & ADVERTISED_1000baseT_Full)) {
1da177e4 1746 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
4876cc1e
FR		 1747 }
1748out:
1da177e4
LT		 1749 return ret;
1750}
1751
1752static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1753{
1754 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4
LT		 1755 int ret;
1756
4876cc1e
FR		 1757 del_timer_sync(&tp->timer);
1758
da78dbff 1759 rtl_lock_work(tp);
cecb5fd7 1760 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
25db0338 1761 cmd->duplex, cmd->advertising);
da78dbff 1762 rtl_unlock_work(tp);
5b0384f4 1763
1da177e4
LT		 1764 return ret;
1765}
1766
c8f44aff
MM		 1767static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1768 netdev_features_t features)
1da177e4 1769{
d58d46b5
FR		 1770 struct rtl8169_private *tp = netdev_priv(dev);
1771
2b7b4318 1772 if (dev->mtu > TD_MSS_MAX)
350fb32a 1773 features &= ~NETIF_F_ALL_TSO;
1da177e4 1774
d58d46b5
FR		 1775 if (dev->mtu > JUMBO_1K &&
1776 !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1777 features &= ~NETIF_F_IP_CSUM;
1778
350fb32a 1779 return features;
1da177e4
LT		 1780}
1781
da78dbff
FR		 1782static void __rtl8169_set_features(struct net_device *dev,
1783 netdev_features_t features)
1da177e4
LT		 1784{
1785 struct rtl8169_private *tp = netdev_priv(dev);
6bbe021d 1786 netdev_features_t changed = features ^ dev->features;
da78dbff 1787 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 1788
f646968f
PM		 1789 if (!(changed & (NETIF_F_RXALL | NETIF_F_RXCSUM |
1790 NETIF_F_HW_VLAN_CTAG_RX)))
6bbe021d 1791 return;
1da177e4 1792
f646968f 1793 if (changed & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX)) {
6bbe021d
BG		 1794 if (features & NETIF_F_RXCSUM)
1795 tp->cp_cmd |= RxChkSum;
1796 else
1797 tp->cp_cmd &= ~RxChkSum;
350fb32a 1798
f646968f 1799 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX)
6bbe021d
BG		 1800 tp->cp_cmd |= RxVlan;
1801 else
1802 tp->cp_cmd &= ~RxVlan;
1803
1804 RTL_W16(CPlusCmd, tp->cp_cmd);
1805 RTL_R16(CPlusCmd);
1806 }
1807 if (changed & NETIF_F_RXALL) {
1808 int tmp = (RTL_R32(RxConfig) & ~(AcceptErr | AcceptRunt));
1809 if (features & NETIF_F_RXALL)
1810 tmp |= (AcceptErr | AcceptRunt);
1811 RTL_W32(RxConfig, tmp);
1812 }
da78dbff 1813}
1da177e4 1814
da78dbff
FR		 1815static int rtl8169_set_features(struct net_device *dev,
1816 netdev_features_t features)
1817{
1818 struct rtl8169_private *tp = netdev_priv(dev);
1819
1820 rtl_lock_work(tp);
1821 __rtl8169_set_features(dev, features);
1822 rtl_unlock_work(tp);
1da177e4
LT		 1823
1824 return 0;
1825}
1826
da78dbff 1827
810f4893 1828static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1da177e4 1829{
eab6d18d 1830 return (vlan_tx_tag_present(skb)) ?
1da177e4
LT		 1831 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1832}
1833
7a8fc77b 1834static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1da177e4
LT		 1835{
1836 u32 opts2 = le32_to_cpu(desc->opts2);
1da177e4 1837
7a8fc77b 1838 if (opts2 & RxVlanTag)
86a9bad3 1839 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1da177e4
LT		 1840}
1841
ccdffb9a 1842static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1843{
1844 struct rtl8169_private *tp = netdev_priv(dev);
1845 void __iomem *ioaddr = tp->mmio_addr;
1846 u32 status;
1847
1848 cmd->supported =
1849 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1850 cmd->port = PORT_FIBRE;
1851 cmd->transceiver = XCVR_INTERNAL;
1852
1853 status = RTL_R32(TBICSR);
1854 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1855 cmd->autoneg = !!(status & TBINwEnable);
1856
70739497 1857 ethtool_cmd_speed_set(cmd, SPEED_1000);
1da177e4 1858 cmd->duplex = DUPLEX_FULL; /* Always set */
ccdffb9a
FR		 1859
1860 return 0;
1da177e4
LT		 1861}
1862
ccdffb9a 1863static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1864{
1865 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a
FR		 1866
1867 return mii_ethtool_gset(&tp->mii, cmd);
1da177e4
LT		 1868}
1869
1870static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1871{
1872 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 1873 int rc;
1da177e4 1874
da78dbff 1875 rtl_lock_work(tp);
ccdffb9a 1876 rc = tp->get_settings(dev, cmd);
da78dbff 1877 rtl_unlock_work(tp);
1da177e4 1878
ccdffb9a 1879 return rc;
1da177e4
LT		 1880}
1881
1882static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1883 void *p)
1884{
5b0384f4 1885 struct rtl8169_private *tp = netdev_priv(dev);
15edae91
PW		 1886 u32 __iomem *data = tp->mmio_addr;
1887 u32 *dw = p;
1888 int i;
1da177e4 1889
da78dbff 1890 rtl_lock_work(tp);
15edae91
PW		 1891 for (i = 0; i < R8169_REGS_SIZE; i += 4)
1892 memcpy_fromio(dw++, data++, 4);
da78dbff 1893 rtl_unlock_work(tp);
1da177e4
LT		 1894}
1895
b57b7e5a
SH		 1896static u32 rtl8169_get_msglevel(struct net_device *dev)
1897{
1898 struct rtl8169_private *tp = netdev_priv(dev);
1899
1900 return tp->msg_enable;
1901}
1902
1903static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1904{
1905 struct rtl8169_private *tp = netdev_priv(dev);
1906
1907 tp->msg_enable = value;
1908}
1909
d4a3a0fc
SH		 1910static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1911 "tx_packets",
1912 "rx_packets",
1913 "tx_errors",
1914 "rx_errors",
1915 "rx_missed",
1916 "align_errors",
1917 "tx_single_collisions",
1918 "tx_multi_collisions",
1919 "unicast",
1920 "broadcast",
1921 "multicast",
1922 "tx_aborted",
1923 "tx_underrun",
1924};
1925
b9f2c044 1926static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1927{
b9f2c044
JG		 1928 switch (sset) {
1929 case ETH_SS_STATS:
1930 return ARRAY_SIZE(rtl8169_gstrings);
1931 default:
1932 return -EOPNOTSUPP;
1933 }
d4a3a0fc
SH		 1934}
1935
ffc46952
FR		 1936DECLARE_RTL_COND(rtl_counters_cond)
1937{
1938 void __iomem *ioaddr = tp->mmio_addr;
1939
1940 return RTL_R32(CounterAddrLow) & CounterDump;
1941}
1942
355423d0 1943static void rtl8169_update_counters(struct net_device *dev)
d4a3a0fc
SH		 1944{
1945 struct rtl8169_private *tp = netdev_priv(dev);
1946 void __iomem *ioaddr = tp->mmio_addr;
cecb5fd7 1947 struct device *d = &tp->pci_dev->dev;
d4a3a0fc
SH		 1948 struct rtl8169_counters *counters;
1949 dma_addr_t paddr;
1950 u32 cmd;
1951
355423d0
IV		 1952 /*
1953 * Some chips are unable to dump tally counters when the receiver
1954 * is disabled.
1955 */
1956 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1957 return;
d4a3a0fc 1958
48addcc9 1959 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
d4a3a0fc
SH		 1960 if (!counters)
1961 return;
1962
1963 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
284901a9 1964 cmd = (u64)paddr & DMA_BIT_MASK(32);
d4a3a0fc
SH		 1965 RTL_W32(CounterAddrLow, cmd);
1966 RTL_W32(CounterAddrLow, cmd | CounterDump);
1967
ffc46952
FR		 1968 if (rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000))
1969 memcpy(&tp->counters, counters, sizeof(*counters));
d4a3a0fc
SH		 1970
1971 RTL_W32(CounterAddrLow, 0);
1972 RTL_W32(CounterAddrHigh, 0);
1973
48addcc9 1974 dma_free_coherent(d, sizeof(*counters), counters, paddr);
d4a3a0fc
SH		 1975}
1976
355423d0
IV		 1977static void rtl8169_get_ethtool_stats(struct net_device *dev,
1978 struct ethtool_stats *stats, u64 *data)
1979{
1980 struct rtl8169_private *tp = netdev_priv(dev);
1981
1982 ASSERT_RTNL();
1983
1984 rtl8169_update_counters(dev);
1985
1986 data[0] = le64_to_cpu(tp->counters.tx_packets);
1987 data[1] = le64_to_cpu(tp->counters.rx_packets);
1988 data[2] = le64_to_cpu(tp->counters.tx_errors);
1989 data[3] = le32_to_cpu(tp->counters.rx_errors);
1990 data[4] = le16_to_cpu(tp->counters.rx_missed);
1991 data[5] = le16_to_cpu(tp->counters.align_errors);
1992 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1993 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1994 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1995 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1996 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1997 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1998 data[12] = le16_to_cpu(tp->counters.tx_underun);
1999}
2000
d4a3a0fc
SH		 2001static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2002{
2003 switch(stringset) {
2004 case ETH_SS_STATS:
2005 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
2006 break;
2007 }
2008}
2009
7282d491 2010static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 2011 .get_drvinfo = rtl8169_get_drvinfo,
2012 .get_regs_len = rtl8169_get_regs_len,
2013 .get_link = ethtool_op_get_link,
2014 .get_settings = rtl8169_get_settings,
2015 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 2016 .get_msglevel = rtl8169_get_msglevel,
2017 .set_msglevel = rtl8169_set_msglevel,
1da177e4 2018 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 2019 .get_wol = rtl8169_get_wol,
2020 .set_wol = rtl8169_set_wol,
d4a3a0fc 2021 .get_strings = rtl8169_get_strings,
b9f2c044 2022 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 2023 .get_ethtool_stats = rtl8169_get_ethtool_stats,
e1593bb1 2024 .get_ts_info = ethtool_op_get_ts_info,
1da177e4
LT		 2025};
2026
07d3f51f 2027static void rtl8169_get_mac_version(struct rtl8169_private *tp,
5d320a20 2028 struct net_device *dev, u8 default_version)
1da177e4 2029{
5d320a20 2030 void __iomem *ioaddr = tp->mmio_addr;
0e485150
FR		 2031 /*
2032 * The driver currently handles the 8168Bf and the 8168Be identically
2033 * but they can be identified more specifically through the test below
2034 * if needed:
2035 *
2036 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 2037 *
2038 * Same thing for the 8101Eb and the 8101Ec:
2039 *
2040 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 2041 */
3744100e 2042 static const struct rtl_mac_info {
1da177e4 2043 u32 mask;
e3cf0cc0 2044 u32 val;
1da177e4
LT		 2045 int mac_version;
2046 } mac_info[] = {
c558386b 2047 /* 8168G family. */
45dd95c4 2048 { 0x7cf00000, 0x5c800000, RTL_GIGA_MAC_VER_44 },
57538c4a 2049 { 0x7cf00000, 0x50900000, RTL_GIGA_MAC_VER_42 },
c558386b
HW		 2050 { 0x7cf00000, 0x4c100000, RTL_GIGA_MAC_VER_41 },
2051 { 0x7cf00000, 0x4c000000, RTL_GIGA_MAC_VER_40 },
2052
c2218925 2053 /* 8168F family. */
b3d7b2f2 2054 { 0x7c800000, 0x48800000, RTL_GIGA_MAC_VER_38 },
c2218925
HW		 2055 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
2056 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
2057
01dc7fec 2058 /* 8168E family. */
70090424 2059 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
01dc7fec 2060 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
2061 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
2062 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
2063
5b538df9 2064 /* 8168D family. */
daf9df6d 2065 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
2066 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
daf9df6d 2067 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
5b538df9 2068
e6de30d6 2069 /* 8168DP family. */
2070 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
2071 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
4804b3b3 2072 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
e6de30d6 2073
ef808d50 2074 /* 8168C family. */
17c99297 2075 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
ef3386f0 2076 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 2077 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 2078 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 2079 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
2080 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 2081 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
6fb07058 2082 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
ef808d50 2083 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 2084
2085 /* 8168B family. */
2086 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
2087 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
2088 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
2089 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
2090
2091 /* 8101 family. */
5598bfe5
HW		 2092 { 0x7cf00000, 0x44900000, RTL_GIGA_MAC_VER_39 },
2093 { 0x7c800000, 0x44800000, RTL_GIGA_MAC_VER_39 },
7e18dca1 2094 { 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37 },
36a0e6c2 2095 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
5a5e4443
HW		 2096 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
2097 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
2098 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2857ffb7
FR		 2099 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
2100 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
2101 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
2102 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
2103 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
2104 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 2105 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 2106 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 2107 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 2108 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
2109 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 2110 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
2111 /* FIXME: where did these entries come from ? -- FR */
2112 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
2113 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
2114
2115 /* 8110 family. */
2116 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
2117 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
2118 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
2119 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
2120 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
2121 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
2122
f21b75e9
JD		 2123 /* Catch-all */
2124 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
3744100e
FR		 2125 };
2126 const struct rtl_mac_info *p = mac_info;
1da177e4
LT		 2127 u32 reg;
2128
e3cf0cc0
FR		 2129 reg = RTL_R32(TxConfig);
2130 while ((reg & p->mask) != p->val)
1da177e4
LT		 2131 p++;
2132 tp->mac_version = p->mac_version;
5d320a20
FR		 2133
2134 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2135 netif_notice(tp, probe, dev,
2136 "unknown MAC, using family default\n");
2137 tp->mac_version = default_version;
58152cd4 2138 } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
2139 tp->mac_version = tp->mii.supports_gmii ?
2140 RTL_GIGA_MAC_VER_42 :
2141 RTL_GIGA_MAC_VER_43;
5d320a20 2142 }
1da177e4
LT		 2143}
2144
2145static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2146{
bcf0bf90 2147 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 2148}
2149
867763c1
FR		 2150struct phy_reg {
2151 u16 reg;
2152 u16 val;
2153};
2154
4da19633 2155static void rtl_writephy_batch(struct rtl8169_private *tp,
2156 const struct phy_reg *regs, int len)
867763c1
FR		 2157{
2158 while (len-- > 0) {
4da19633 2159 rtl_writephy(tp, regs->reg, regs->val);
867763c1
FR		 2160 regs++;
2161 }
2162}
2163
bca03d5f 2164#define PHY_READ 0x00000000
2165#define PHY_DATA_OR 0x10000000
2166#define PHY_DATA_AND 0x20000000
2167#define PHY_BJMPN 0x30000000
eee3786f 2168#define PHY_MDIO_CHG 0x40000000
bca03d5f 2169#define PHY_CLEAR_READCOUNT 0x70000000
2170#define PHY_WRITE 0x80000000
2171#define PHY_READCOUNT_EQ_SKIP 0x90000000
2172#define PHY_COMP_EQ_SKIPN 0xa0000000
2173#define PHY_COMP_NEQ_SKIPN 0xb0000000
2174#define PHY_WRITE_PREVIOUS 0xc0000000
2175#define PHY_SKIPN 0xd0000000
2176#define PHY_DELAY_MS 0xe0000000
bca03d5f 2177
960aee6c
HW		 2178struct fw_info {
2179 u32 magic;
2180 char version[RTL_VER_SIZE];
2181 __le32 fw_start;
2182 __le32 fw_len;
2183 u8 chksum;
2184} __packed;
2185
1c361efb
FR		 2186#define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2187
2188static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
bca03d5f 2189{
b6ffd97f 2190 const struct firmware *fw = rtl_fw->fw;
960aee6c 2191 struct fw_info *fw_info = (struct fw_info *)fw->data;
1c361efb
FR		 2192 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2193 char *version = rtl_fw->version;
2194 bool rc = false;
2195
2196 if (fw->size < FW_OPCODE_SIZE)
2197 goto out;
960aee6c
HW		 2198
2199 if (!fw_info->magic) {
2200 size_t i, size, start;
2201 u8 checksum = 0;
2202
2203 if (fw->size < sizeof(*fw_info))
2204 goto out;
2205
2206 for (i = 0; i < fw->size; i++)
2207 checksum += fw->data[i];
2208 if (checksum != 0)
2209 goto out;
2210
2211 start = le32_to_cpu(fw_info->fw_start);
2212 if (start > fw->size)
2213 goto out;
2214
2215 size = le32_to_cpu(fw_info->fw_len);
2216 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2217 goto out;
2218
2219 memcpy(version, fw_info->version, RTL_VER_SIZE);
2220
2221 pa->code = (__le32 *)(fw->data + start);
2222 pa->size = size;
2223 } else {
1c361efb
FR		 2224 if (fw->size % FW_OPCODE_SIZE)
2225 goto out;
2226
2227 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2228
2229 pa->code = (__le32 *)fw->data;
2230 pa->size = fw->size / FW_OPCODE_SIZE;
2231 }
2232 version[RTL_VER_SIZE - 1] = 0;
2233
2234 rc = true;
2235out:
2236 return rc;
2237}
2238
fd112f2e
FR		 2239static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2240 struct rtl_fw_phy_action *pa)
1c361efb 2241{
fd112f2e 2242 bool rc = false;
1c361efb 2243 size_t index;
bca03d5f 2244
1c361efb
FR		 2245 for (index = 0; index < pa->size; index++) {
2246 u32 action = le32_to_cpu(pa->code[index]);
42b82dc1 2247 u32 regno = (action & 0x0fff0000) >> 16;
bca03d5f 2248
42b82dc1 2249 switch(action & 0xf0000000) {
2250 case PHY_READ:
2251 case PHY_DATA_OR:
2252 case PHY_DATA_AND:
eee3786f 2253 case PHY_MDIO_CHG:
42b82dc1 2254 case PHY_CLEAR_READCOUNT:
2255 case PHY_WRITE:
2256 case PHY_WRITE_PREVIOUS:
2257 case PHY_DELAY_MS:
2258 break;
2259
2260 case PHY_BJMPN:
2261 if (regno > index) {
fd112f2e 2262 netif_err(tp, ifup, tp->dev,
cecb5fd7 2263 "Out of range of firmware\n");
fd112f2e 2264 goto out;
42b82dc1 2265 }
2266 break;
2267 case PHY_READCOUNT_EQ_SKIP:
1c361efb 2268 if (index + 2 >= pa->size) {
fd112f2e 2269 netif_err(tp, ifup, tp->dev,
cecb5fd7 2270 "Out of range of firmware\n");
fd112f2e 2271 goto out;
42b82dc1 2272 }
2273 break;
2274 case PHY_COMP_EQ_SKIPN:
2275 case PHY_COMP_NEQ_SKIPN:
2276 case PHY_SKIPN:
1c361efb 2277 if (index + 1 + regno >= pa->size) {
fd112f2e 2278 netif_err(tp, ifup, tp->dev,
cecb5fd7 2279 "Out of range of firmware\n");
fd112f2e 2280 goto out;
42b82dc1 2281 }
bca03d5f 2282 break;
2283
42b82dc1 2284 default:
fd112f2e 2285 netif_err(tp, ifup, tp->dev,
42b82dc1 2286 "Invalid action 0x%08x\n", action);
fd112f2e 2287 goto out;
bca03d5f 2288 }
2289 }
fd112f2e
FR		 2290 rc = true;
2291out:
2292 return rc;
2293}
bca03d5f 2294
fd112f2e
FR		 2295static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2296{
2297 struct net_device *dev = tp->dev;
2298 int rc = -EINVAL;
2299
2300 if (!rtl_fw_format_ok(tp, rtl_fw)) {
2301 netif_err(tp, ifup, dev, "invalid firwmare\n");
2302 goto out;
2303 }
2304
2305 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2306 rc = 0;
2307out:
2308 return rc;
2309}
2310
2311static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2312{
2313 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
eee3786f 2314 struct mdio_ops org, *ops = &tp->mdio_ops;
fd112f2e
FR		 2315 u32 predata, count;
2316 size_t index;
2317
2318 predata = count = 0;
eee3786f 2319 org.write = ops->write;
2320 org.read = ops->read;
42b82dc1 2321
1c361efb
FR		 2322 for (index = 0; index < pa->size; ) {
2323 u32 action = le32_to_cpu(pa->code[index]);
bca03d5f 2324 u32 data = action & 0x0000ffff;
42b82dc1 2325 u32 regno = (action & 0x0fff0000) >> 16;
2326
2327 if (!action)
2328 break;
bca03d5f 2329
2330 switch(action & 0xf0000000) {
42b82dc1 2331 case PHY_READ:
2332 predata = rtl_readphy(tp, regno);
2333 count++;
2334 index++;
2335 break;
2336 case PHY_DATA_OR:
2337 predata |= data;
2338 index++;
2339 break;
2340 case PHY_DATA_AND:
2341 predata &= data;
2342 index++;
2343 break;
2344 case PHY_BJMPN:
2345 index -= regno;
2346 break;
eee3786f 2347 case PHY_MDIO_CHG:
2348 if (data == 0) {
2349 ops->write = org.write;
2350 ops->read = org.read;
2351 } else if (data == 1) {
2352 ops->write = mac_mcu_write;
2353 ops->read = mac_mcu_read;
2354 }
2355
42b82dc1 2356 index++;
2357 break;
2358 case PHY_CLEAR_READCOUNT:
2359 count = 0;
2360 index++;
2361 break;
bca03d5f 2362 case PHY_WRITE:
42b82dc1 2363 rtl_writephy(tp, regno, data);
2364 index++;
2365 break;
2366 case PHY_READCOUNT_EQ_SKIP:
cecb5fd7 2367 index += (count == data) ? 2 : 1;
bca03d5f 2368 break;
42b82dc1 2369 case PHY_COMP_EQ_SKIPN:
2370 if (predata == data)
2371 index += regno;
2372 index++;
2373 break;
2374 case PHY_COMP_NEQ_SKIPN:
2375 if (predata != data)
2376 index += regno;
2377 index++;
2378 break;
2379 case PHY_WRITE_PREVIOUS:
2380 rtl_writephy(tp, regno, predata);
2381 index++;
2382 break;
2383 case PHY_SKIPN:
2384 index += regno + 1;
2385 break;
2386 case PHY_DELAY_MS:
2387 mdelay(data);
2388 index++;
2389 break;
2390
bca03d5f 2391 default:
2392 BUG();
2393 }
2394 }
eee3786f 2395
2396 ops->write = org.write;
2397 ops->read = org.read;
bca03d5f 2398}
2399
f1e02ed1 2400static void rtl_release_firmware(struct rtl8169_private *tp)
2401{
b6ffd97f
FR		 2402 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2403 release_firmware(tp->rtl_fw->fw);
2404 kfree(tp->rtl_fw);
2405 }
2406 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
f1e02ed1 2407}
2408
953a12cc 2409static void rtl_apply_firmware(struct rtl8169_private *tp)
f1e02ed1 2410{
b6ffd97f 2411 struct rtl_fw *rtl_fw = tp->rtl_fw;
f1e02ed1 2412
2413 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
eef63cc1 2414 if (!IS_ERR_OR_NULL(rtl_fw))
b6ffd97f 2415 rtl_phy_write_fw(tp, rtl_fw);
953a12cc
FR		 2416}
2417
2418static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2419{
2420 if (rtl_readphy(tp, reg) != val)
2421 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2422 else
2423 rtl_apply_firmware(tp);
f1e02ed1 2424}
2425
4da19633 2426static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1da177e4 2427{
350f7596 2428 static const struct phy_reg phy_reg_init[] = {
0b9b571d 2429 { 0x1f, 0x0001 },
2430 { 0x06, 0x006e },
2431 { 0x08, 0x0708 },
2432 { 0x15, 0x4000 },
2433 { 0x18, 0x65c7 },
1da177e4 2434
0b9b571d 2435 { 0x1f, 0x0001 },
2436 { 0x03, 0x00a1 },
2437 { 0x02, 0x0008 },
2438 { 0x01, 0x0120 },
2439 { 0x00, 0x1000 },
2440 { 0x04, 0x0800 },
2441 { 0x04, 0x0000 },
1da177e4 2442
0b9b571d 2443 { 0x03, 0xff41 },
2444 { 0x02, 0xdf60 },
2445 { 0x01, 0x0140 },
2446 { 0x00, 0x0077 },
2447 { 0x04, 0x7800 },
2448 { 0x04, 0x7000 },
2449
2450 { 0x03, 0x802f },
2451 { 0x02, 0x4f02 },
2452 { 0x01, 0x0409 },
2453 { 0x00, 0xf0f9 },
2454 { 0x04, 0x9800 },
2455 { 0x04, 0x9000 },
2456
2457 { 0x03, 0xdf01 },
2458 { 0x02, 0xdf20 },
2459 { 0x01, 0xff95 },
2460 { 0x00, 0xba00 },
2461 { 0x04, 0xa800 },
2462 { 0x04, 0xa000 },
2463
2464 { 0x03, 0xff41 },
2465 { 0x02, 0xdf20 },
2466 { 0x01, 0x0140 },
2467 { 0x00, 0x00bb },
2468 { 0x04, 0xb800 },
2469 { 0x04, 0xb000 },
2470
2471 { 0x03, 0xdf41 },
2472 { 0x02, 0xdc60 },
2473 { 0x01, 0x6340 },
2474 { 0x00, 0x007d },
2475 { 0x04, 0xd800 },
2476 { 0x04, 0xd000 },
2477
2478 { 0x03, 0xdf01 },
2479 { 0x02, 0xdf20 },
2480 { 0x01, 0x100a },
2481 { 0x00, 0xa0ff },
2482 { 0x04, 0xf800 },
2483 { 0x04, 0xf000 },
2484
2485 { 0x1f, 0x0000 },
2486 { 0x0b, 0x0000 },
2487 { 0x00, 0x9200 }
2488 };
1da177e4 2489
4da19633 2490 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1da177e4
LT		 2491}
2492
4da19633 2493static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
5615d9f1 2494{
350f7596 2495 static const struct phy_reg phy_reg_init[] = {
a441d7b6
FR		 2496 { 0x1f, 0x0002 },
2497 { 0x01, 0x90d0 },
2498 { 0x1f, 0x0000 }
2499 };
2500
4da19633 2501 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 2502}
2503
4da19633 2504static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2e955856 2505{
2506 struct pci_dev *pdev = tp->pci_dev;
2e955856 2507
ccbae55e
SS		 2508 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2509 (pdev->subsystem_device != 0xe000))
2e955856 2510 return;
2511
4da19633 2512 rtl_writephy(tp, 0x1f, 0x0001);
2513 rtl_writephy(tp, 0x10, 0xf01b);
2514 rtl_writephy(tp, 0x1f, 0x0000);
2e955856 2515}
2516
4da19633 2517static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2e955856 2518{
350f7596 2519 static const struct phy_reg phy_reg_init[] = {
2e955856 2520 { 0x1f, 0x0001 },
2521 { 0x04, 0x0000 },
2522 { 0x03, 0x00a1 },
2523 { 0x02, 0x0008 },
2524 { 0x01, 0x0120 },
2525 { 0x00, 0x1000 },
2526 { 0x04, 0x0800 },
2527 { 0x04, 0x9000 },
2528 { 0x03, 0x802f },
2529 { 0x02, 0x4f02 },
2530 { 0x01, 0x0409 },
2531 { 0x00, 0xf099 },
2532 { 0x04, 0x9800 },
2533 { 0x04, 0xa000 },
2534 { 0x03, 0xdf01 },
2535 { 0x02, 0xdf20 },
2536 { 0x01, 0xff95 },
2537 { 0x00, 0xba00 },
2538 { 0x04, 0xa800 },
2539 { 0x04, 0xf000 },
2540 { 0x03, 0xdf01 },
2541 { 0x02, 0xdf20 },
2542 { 0x01, 0x101a },
2543 { 0x00, 0xa0ff },
2544 { 0x04, 0xf800 },
2545 { 0x04, 0x0000 },
2546 { 0x1f, 0x0000 },
2547
2548 { 0x1f, 0x0001 },
2549 { 0x10, 0xf41b },
2550 { 0x14, 0xfb54 },
2551 { 0x18, 0xf5c7 },
2552 { 0x1f, 0x0000 },
2553
2554 { 0x1f, 0x0001 },
2555 { 0x17, 0x0cc0 },
2556 { 0x1f, 0x0000 }
2557 };
2558
4da19633 2559 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2e955856 2560
4da19633 2561 rtl8169scd_hw_phy_config_quirk(tp);
2e955856 2562}
2563
4da19633 2564static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
8c7006aa 2565{
350f7596 2566 static const struct phy_reg phy_reg_init[] = {
8c7006aa 2567 { 0x1f, 0x0001 },
2568 { 0x04, 0x0000 },
2569 { 0x03, 0x00a1 },
2570 { 0x02, 0x0008 },
2571 { 0x01, 0x0120 },
2572 { 0x00, 0x1000 },
2573 { 0x04, 0x0800 },
2574 { 0x04, 0x9000 },
2575 { 0x03, 0x802f },
2576 { 0x02, 0x4f02 },
2577 { 0x01, 0x0409 },
2578 { 0x00, 0xf099 },
2579 { 0x04, 0x9800 },
2580 { 0x04, 0xa000 },
2581 { 0x03, 0xdf01 },
2582 { 0x02, 0xdf20 },
2583 { 0x01, 0xff95 },
2584 { 0x00, 0xba00 },
2585 { 0x04, 0xa800 },
2586 { 0x04, 0xf000 },
2587 { 0x03, 0xdf01 },
2588 { 0x02, 0xdf20 },
2589 { 0x01, 0x101a },
2590 { 0x00, 0xa0ff },
2591 { 0x04, 0xf800 },
2592 { 0x04, 0x0000 },
2593 { 0x1f, 0x0000 },
2594
2595 { 0x1f, 0x0001 },
2596 { 0x0b, 0x8480 },
2597 { 0x1f, 0x0000 },
2598
2599 { 0x1f, 0x0001 },
2600 { 0x18, 0x67c7 },
2601 { 0x04, 0x2000 },
2602 { 0x03, 0x002f },
2603 { 0x02, 0x4360 },
2604 { 0x01, 0x0109 },
2605 { 0x00, 0x3022 },
2606 { 0x04, 0x2800 },
2607 { 0x1f, 0x0000 },
2608
2609 { 0x1f, 0x0001 },
2610 { 0x17, 0x0cc0 },
2611 { 0x1f, 0x0000 }
2612 };
2613
4da19633 2614 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
8c7006aa 2615}
2616
4da19633 2617static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
236b8082 2618{
350f7596 2619 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2620 { 0x10, 0xf41b },
2621 { 0x1f, 0x0000 }
2622 };
2623
4da19633 2624 rtl_writephy(tp, 0x1f, 0x0001);
2625 rtl_patchphy(tp, 0x16, 1 << 0);
236b8082 2626
4da19633 2627 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2628}
2629
4da19633 2630static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
236b8082 2631{
350f7596 2632 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2633 { 0x1f, 0x0001 },
2634 { 0x10, 0xf41b },
2635 { 0x1f, 0x0000 }
2636 };
2637
4da19633 2638 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2639}
2640
4da19633 2641static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2642{
350f7596 2643 static const struct phy_reg phy_reg_init[] = {
867763c1
FR		 2644 { 0x1f, 0x0000 },
2645 { 0x1d, 0x0f00 },
2646 { 0x1f, 0x0002 },
2647 { 0x0c, 0x1ec8 },
2648 { 0x1f, 0x0000 }
2649 };
2650
4da19633 2651 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
867763c1
FR		 2652}
2653
4da19633 2654static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
ef3386f0 2655{
350f7596 2656 static const struct phy_reg phy_reg_init[] = {
ef3386f0
FR		 2657 { 0x1f, 0x0001 },
2658 { 0x1d, 0x3d98 },
2659 { 0x1f, 0x0000 }
2660 };
2661
4da19633 2662 rtl_writephy(tp, 0x1f, 0x0000);
2663 rtl_patchphy(tp, 0x14, 1 << 5);
2664 rtl_patchphy(tp, 0x0d, 1 << 5);
ef3386f0 2665
4da19633 2666 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
ef3386f0
FR		 2667}
2668
4da19633 2669static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2670{
350f7596 2671 static const struct phy_reg phy_reg_init[] = {
a3f80671
FR		 2672 { 0x1f, 0x0001 },
2673 { 0x12, 0x2300 },
867763c1
FR		 2674 { 0x1f, 0x0002 },
2675 { 0x00, 0x88d4 },
2676 { 0x01, 0x82b1 },
2677 { 0x03, 0x7002 },
2678 { 0x08, 0x9e30 },
2679 { 0x09, 0x01f0 },
2680 { 0x0a, 0x5500 },
2681 { 0x0c, 0x00c8 },
2682 { 0x1f, 0x0003 },
2683 { 0x12, 0xc096 },
2684 { 0x16, 0x000a },
f50d4275
FR		 2685 { 0x1f, 0x0000 },
2686 { 0x1f, 0x0000 },
2687 { 0x09, 0x2000 },
2688 { 0x09, 0x0000 }
867763c1
FR		 2689 };
2690
4da19633 2691 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2692
4da19633 2693 rtl_patchphy(tp, 0x14, 1 << 5);
2694 rtl_patchphy(tp, 0x0d, 1 << 5);
2695 rtl_writephy(tp, 0x1f, 0x0000);
867763c1
FR		 2696}
2697
4da19633 2698static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
7da97ec9 2699{
350f7596 2700 static const struct phy_reg phy_reg_init[] = {
f50d4275 2701 { 0x1f, 0x0001 },
7da97ec9 2702 { 0x12, 0x2300 },
f50d4275
FR		 2703 { 0x03, 0x802f },
2704 { 0x02, 0x4f02 },
2705 { 0x01, 0x0409 },
2706 { 0x00, 0xf099 },
2707 { 0x04, 0x9800 },
2708 { 0x04, 0x9000 },
2709 { 0x1d, 0x3d98 },
7da97ec9
FR		 2710 { 0x1f, 0x0002 },
2711 { 0x0c, 0x7eb8 },
f50d4275
FR		 2712 { 0x06, 0x0761 },
2713 { 0x1f, 0x0003 },
2714 { 0x16, 0x0f0a },
7da97ec9
FR		 2715 { 0x1f, 0x0000 }
2716 };
2717
4da19633 2718 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2719
4da19633 2720 rtl_patchphy(tp, 0x16, 1 << 0);
2721 rtl_patchphy(tp, 0x14, 1 << 5);
2722 rtl_patchphy(tp, 0x0d, 1 << 5);
2723 rtl_writephy(tp, 0x1f, 0x0000);
7da97ec9
FR		 2724}
2725
4da19633 2726static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
197ff761 2727{
350f7596 2728 static const struct phy_reg phy_reg_init[] = {
197ff761
FR		 2729 { 0x1f, 0x0001 },
2730 { 0x12, 0x2300 },
2731 { 0x1d, 0x3d98 },
2732 { 0x1f, 0x0002 },
2733 { 0x0c, 0x7eb8 },
2734 { 0x06, 0x5461 },
2735 { 0x1f, 0x0003 },
2736 { 0x16, 0x0f0a },
2737 { 0x1f, 0x0000 }
2738 };
2739
4da19633 2740 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
197ff761 2741
4da19633 2742 rtl_patchphy(tp, 0x16, 1 << 0);
2743 rtl_patchphy(tp, 0x14, 1 << 5);
2744 rtl_patchphy(tp, 0x0d, 1 << 5);
2745 rtl_writephy(tp, 0x1f, 0x0000);
197ff761
FR		 2746}
2747
4da19633 2748static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
6fb07058 2749{
4da19633 2750 rtl8168c_3_hw_phy_config(tp);
6fb07058
FR		 2751}
2752
bca03d5f 2753static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
5b538df9 2754{
350f7596 2755 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2756 /* Channel Estimation */
5b538df9 2757 { 0x1f, 0x0001 },
daf9df6d 2758 { 0x06, 0x4064 },
2759 { 0x07, 0x2863 },
2760 { 0x08, 0x059c },
2761 { 0x09, 0x26b4 },
2762 { 0x0a, 0x6a19 },
2763 { 0x0b, 0xdcc8 },
2764 { 0x10, 0xf06d },
2765 { 0x14, 0x7f68 },
2766 { 0x18, 0x7fd9 },
2767 { 0x1c, 0xf0ff },
2768 { 0x1d, 0x3d9c },
5b538df9 2769 { 0x1f, 0x0003 },
daf9df6d 2770 { 0x12, 0xf49f },
2771 { 0x13, 0x070b },
2772 { 0x1a, 0x05ad },
bca03d5f 2773 { 0x14, 0x94c0 },
2774
2775 /*
2776 * Tx Error Issue
cecb5fd7 2777 * Enhance line driver power
bca03d5f 2778 */
5b538df9 2779 { 0x1f, 0x0002 },
daf9df6d 2780 { 0x06, 0x5561 },
2781 { 0x1f, 0x0005 },
2782 { 0x05, 0x8332 },
bca03d5f 2783 { 0x06, 0x5561 },
2784
2785 /*
2786 * Can not link to 1Gbps with bad cable
2787 * Decrease SNR threshold form 21.07dB to 19.04dB
2788 */
2789 { 0x1f, 0x0001 },
2790 { 0x17, 0x0cc0 },
daf9df6d 2791
5b538df9 2792 { 0x1f, 0x0000 },
bca03d5f 2793 { 0x0d, 0xf880 }
daf9df6d 2794 };
2795
4da19633 2796 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
daf9df6d 2797
bca03d5f 2798 /*
2799 * Rx Error Issue
2800 * Fine Tune Switching regulator parameter
2801 */
4da19633 2802 rtl_writephy(tp, 0x1f, 0x0002);
2803 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2804 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
daf9df6d 2805
fdf6fc06 2806 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
350f7596 2807 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2808 { 0x1f, 0x0002 },
2809 { 0x05, 0x669a },
2810 { 0x1f, 0x0005 },
2811 { 0x05, 0x8330 },
2812 { 0x06, 0x669a },
2813 { 0x1f, 0x0002 }
2814 };
2815 int val;
2816
4da19633 2817 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2818
4da19633 2819 val = rtl_readphy(tp, 0x0d);
daf9df6d 2820
2821 if ((val & 0x00ff) != 0x006c) {
350f7596 2822 static const u32 set[] = {
daf9df6d 2823 0x0065, 0x0066, 0x0067, 0x0068,
2824 0x0069, 0x006a, 0x006b, 0x006c
2825 };
2826 int i;
2827
4da19633 2828 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2829
2830 val &= 0xff00;
2831 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2832 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2833 }
2834 } else {
350f7596 2835 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2836 { 0x1f, 0x0002 },
2837 { 0x05, 0x6662 },
2838 { 0x1f, 0x0005 },
2839 { 0x05, 0x8330 },
2840 { 0x06, 0x6662 }
2841 };
2842
4da19633 2843 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2844 }
2845
bca03d5f 2846 /* RSET couple improve */
4da19633 2847 rtl_writephy(tp, 0x1f, 0x0002);
2848 rtl_patchphy(tp, 0x0d, 0x0300);
2849 rtl_patchphy(tp, 0x0f, 0x0010);
daf9df6d 2850
bca03d5f 2851 /* Fine tune PLL performance */
4da19633 2852 rtl_writephy(tp, 0x1f, 0x0002);
2853 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2854 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2855
4da19633 2856 rtl_writephy(tp, 0x1f, 0x0005);
2857 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2858
2859 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
bca03d5f 2860
4da19633 2861 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2862}
2863
bca03d5f 2864static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2865{
350f7596 2866 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2867 /* Channel Estimation */
daf9df6d 2868 { 0x1f, 0x0001 },
2869 { 0x06, 0x4064 },
2870 { 0x07, 0x2863 },
2871 { 0x08, 0x059c },
2872 { 0x09, 0x26b4 },
2873 { 0x0a, 0x6a19 },
2874 { 0x0b, 0xdcc8 },
2875 { 0x10, 0xf06d },
2876 { 0x14, 0x7f68 },
2877 { 0x18, 0x7fd9 },
2878 { 0x1c, 0xf0ff },
2879 { 0x1d, 0x3d9c },
2880 { 0x1f, 0x0003 },
2881 { 0x12, 0xf49f },
2882 { 0x13, 0x070b },
2883 { 0x1a, 0x05ad },
2884 { 0x14, 0x94c0 },
2885
bca03d5f 2886 /*
2887 * Tx Error Issue
cecb5fd7 2888 * Enhance line driver power
bca03d5f 2889 */
daf9df6d 2890 { 0x1f, 0x0002 },
2891 { 0x06, 0x5561 },
2892 { 0x1f, 0x0005 },
2893 { 0x05, 0x8332 },
bca03d5f 2894 { 0x06, 0x5561 },
2895
2896 /*
2897 * Can not link to 1Gbps with bad cable
2898 * Decrease SNR threshold form 21.07dB to 19.04dB
2899 */
2900 { 0x1f, 0x0001 },
2901 { 0x17, 0x0cc0 },
daf9df6d 2902
2903 { 0x1f, 0x0000 },
bca03d5f 2904 { 0x0d, 0xf880 }
5b538df9
FR		 2905 };
2906
4da19633 2907 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
5b538df9 2908
fdf6fc06 2909 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
350f7596 2910 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2911 { 0x1f, 0x0002 },
2912 { 0x05, 0x669a },
5b538df9 2913 { 0x1f, 0x0005 },
daf9df6d 2914 { 0x05, 0x8330 },
2915 { 0x06, 0x669a },
2916
2917 { 0x1f, 0x0002 }
2918 };
2919 int val;
2920
4da19633 2921 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2922
4da19633 2923 val = rtl_readphy(tp, 0x0d);
daf9df6d 2924 if ((val & 0x00ff) != 0x006c) {
b6bc7650 2925 static const u32 set[] = {
daf9df6d 2926 0x0065, 0x0066, 0x0067, 0x0068,
2927 0x0069, 0x006a, 0x006b, 0x006c
2928 };
2929 int i;
2930
4da19633 2931 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2932
2933 val &= 0xff00;
2934 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2935 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2936 }
2937 } else {
350f7596 2938 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2939 { 0x1f, 0x0002 },
2940 { 0x05, 0x2642 },
5b538df9 2941 { 0x1f, 0x0005 },
daf9df6d 2942 { 0x05, 0x8330 },
2943 { 0x06, 0x2642 }
5b538df9
FR		 2944 };
2945
4da19633 2946 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2947 }
2948
bca03d5f 2949 /* Fine tune PLL performance */
4da19633 2950 rtl_writephy(tp, 0x1f, 0x0002);
2951 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2952 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2953
bca03d5f 2954 /* Switching regulator Slew rate */
4da19633 2955 rtl_writephy(tp, 0x1f, 0x0002);
2956 rtl_patchphy(tp, 0x0f, 0x0017);
daf9df6d 2957
4da19633 2958 rtl_writephy(tp, 0x1f, 0x0005);
2959 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2960
2961 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
bca03d5f 2962
4da19633 2963 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2964}
2965
4da19633 2966static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2967{
350f7596 2968 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2969 { 0x1f, 0x0002 },
2970 { 0x10, 0x0008 },
2971 { 0x0d, 0x006c },
2972
2973 { 0x1f, 0x0000 },
2974 { 0x0d, 0xf880 },
2975
2976 { 0x1f, 0x0001 },
2977 { 0x17, 0x0cc0 },
2978
2979 { 0x1f, 0x0001 },
2980 { 0x0b, 0xa4d8 },
2981 { 0x09, 0x281c },
2982 { 0x07, 0x2883 },
2983 { 0x0a, 0x6b35 },
2984 { 0x1d, 0x3da4 },
2985 { 0x1c, 0xeffd },
2986 { 0x14, 0x7f52 },
2987 { 0x18, 0x7fc6 },
2988 { 0x08, 0x0601 },
2989 { 0x06, 0x4063 },
2990 { 0x10, 0xf074 },
2991 { 0x1f, 0x0003 },
2992 { 0x13, 0x0789 },
2993 { 0x12, 0xf4bd },
2994 { 0x1a, 0x04fd },
2995 { 0x14, 0x84b0 },
2996 { 0x1f, 0x0000 },
2997 { 0x00, 0x9200 },
2998
2999 { 0x1f, 0x0005 },
3000 { 0x01, 0x0340 },
3001 { 0x1f, 0x0001 },
3002 { 0x04, 0x4000 },
3003 { 0x03, 0x1d21 },
3004 { 0x02, 0x0c32 },
3005 { 0x01, 0x0200 },
3006 { 0x00, 0x5554 },
3007 { 0x04, 0x4800 },
3008 { 0x04, 0x4000 },
3009 { 0x04, 0xf000 },
3010 { 0x03, 0xdf01 },
3011 { 0x02, 0xdf20 },
3012 { 0x01, 0x101a },
3013 { 0x00, 0xa0ff },
3014 { 0x04, 0xf800 },
3015 { 0x04, 0xf000 },
3016 { 0x1f, 0x0000 },
3017
3018 { 0x1f, 0x0007 },
3019 { 0x1e, 0x0023 },
3020 { 0x16, 0x0000 },
3021 { 0x1f, 0x0000 }
3022 };
3023
4da19633 3024 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 3025}
3026
e6de30d6 3027static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3028{
3029 static const struct phy_reg phy_reg_init[] = {
3030 { 0x1f, 0x0001 },
3031 { 0x17, 0x0cc0 },
3032
3033 { 0x1f, 0x0007 },
3034 { 0x1e, 0x002d },
3035 { 0x18, 0x0040 },
3036 { 0x1f, 0x0000 }
3037 };
3038
3039 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3040 rtl_patchphy(tp, 0x0d, 1 << 5);
3041}
3042
70090424 3043static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
01dc7fec 3044{
3045 static const struct phy_reg phy_reg_init[] = {
3046 /* Enable Delay cap */
3047 { 0x1f, 0x0005 },
3048 { 0x05, 0x8b80 },
3049 { 0x06, 0xc896 },
3050 { 0x1f, 0x0000 },
3051
3052 /* Channel estimation fine tune */
3053 { 0x1f, 0x0001 },
3054 { 0x0b, 0x6c20 },
3055 { 0x07, 0x2872 },
3056 { 0x1c, 0xefff },
3057 { 0x1f, 0x0003 },
3058 { 0x14, 0x6420 },
3059 { 0x1f, 0x0000 },
3060
3061 /* Update PFM & 10M TX idle timer */
3062 { 0x1f, 0x0007 },
3063 { 0x1e, 0x002f },
3064 { 0x15, 0x1919 },
3065 { 0x1f, 0x0000 },
3066
3067 { 0x1f, 0x0007 },
3068 { 0x1e, 0x00ac },
3069 { 0x18, 0x0006 },
3070 { 0x1f, 0x0000 }
3071 };
3072
15ecd039
FR		 3073 rtl_apply_firmware(tp);
3074
01dc7fec 3075 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3076
3077 /* DCO enable for 10M IDLE Power */
3078 rtl_writephy(tp, 0x1f, 0x0007);
3079 rtl_writephy(tp, 0x1e, 0x0023);
3080 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
3081 rtl_writephy(tp, 0x1f, 0x0000);
3082
3083 /* For impedance matching */
3084 rtl_writephy(tp, 0x1f, 0x0002);
3085 rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
cecb5fd7 3086 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3087
3088 /* PHY auto speed down */
3089 rtl_writephy(tp, 0x1f, 0x0007);
3090 rtl_writephy(tp, 0x1e, 0x002d);
3091 rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
3092 rtl_writephy(tp, 0x1f, 0x0000);
3093 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3094
3095 rtl_writephy(tp, 0x1f, 0x0005);
3096 rtl_writephy(tp, 0x05, 0x8b86);
3097 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3098 rtl_writephy(tp, 0x1f, 0x0000);
3099
3100 rtl_writephy(tp, 0x1f, 0x0005);
3101 rtl_writephy(tp, 0x05, 0x8b85);
3102 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3103 rtl_writephy(tp, 0x1f, 0x0007);
3104 rtl_writephy(tp, 0x1e, 0x0020);
3105 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
3106 rtl_writephy(tp, 0x1f, 0x0006);
3107 rtl_writephy(tp, 0x00, 0x5a00);
3108 rtl_writephy(tp, 0x1f, 0x0000);
3109 rtl_writephy(tp, 0x0d, 0x0007);
3110 rtl_writephy(tp, 0x0e, 0x003c);
3111 rtl_writephy(tp, 0x0d, 0x4007);
3112 rtl_writephy(tp, 0x0e, 0x0000);
3113 rtl_writephy(tp, 0x0d, 0x0000);
3114}
3115
9ecb9aab 3116static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3117{
3118 const u16 w[] = {
3119 addr[0] | (addr[1] << 8),
3120 addr[2] | (addr[3] << 8),
3121 addr[4] | (addr[5] << 8)
3122 };
3123 const struct exgmac_reg e[] = {
3124 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3125 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3126 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3127 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3128 };
3129
3130 rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3131}
3132
70090424
HW		 3133static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3134{
3135 static const struct phy_reg phy_reg_init[] = {
3136 /* Enable Delay cap */
3137 { 0x1f, 0x0004 },
3138 { 0x1f, 0x0007 },
3139 { 0x1e, 0x00ac },
3140 { 0x18, 0x0006 },
3141 { 0x1f, 0x0002 },
3142 { 0x1f, 0x0000 },
3143 { 0x1f, 0x0000 },
3144
3145 /* Channel estimation fine tune */
3146 { 0x1f, 0x0003 },
3147 { 0x09, 0xa20f },
3148 { 0x1f, 0x0000 },
3149 { 0x1f, 0x0000 },
3150
3151 /* Green Setting */
3152 { 0x1f, 0x0005 },
3153 { 0x05, 0x8b5b },
3154 { 0x06, 0x9222 },
3155 { 0x05, 0x8b6d },
3156 { 0x06, 0x8000 },
3157 { 0x05, 0x8b76 },
3158 { 0x06, 0x8000 },
3159 { 0x1f, 0x0000 }
3160 };
3161
3162 rtl_apply_firmware(tp);
3163
3164 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3165
3166 /* For 4-corner performance improve */
3167 rtl_writephy(tp, 0x1f, 0x0005);
3168 rtl_writephy(tp, 0x05, 0x8b80);
3169 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
3170 rtl_writephy(tp, 0x1f, 0x0000);
3171
3172 /* PHY auto speed down */
3173 rtl_writephy(tp, 0x1f, 0x0004);
3174 rtl_writephy(tp, 0x1f, 0x0007);
3175 rtl_writephy(tp, 0x1e, 0x002d);
3176 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3177 rtl_writephy(tp, 0x1f, 0x0002);
3178 rtl_writephy(tp, 0x1f, 0x0000);
3179 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3180
3181 /* improve 10M EEE waveform */
3182 rtl_writephy(tp, 0x1f, 0x0005);
3183 rtl_writephy(tp, 0x05, 0x8b86);
3184 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3185 rtl_writephy(tp, 0x1f, 0x0000);
3186
3187 /* Improve 2-pair detection performance */
3188 rtl_writephy(tp, 0x1f, 0x0005);
3189 rtl_writephy(tp, 0x05, 0x8b85);
3190 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3191 rtl_writephy(tp, 0x1f, 0x0000);
3192
3193 /* EEE setting */
fdf6fc06 3194 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, ERIAR_EXGMAC);
70090424
HW		 3195 rtl_writephy(tp, 0x1f, 0x0005);
3196 rtl_writephy(tp, 0x05, 0x8b85);
3197 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3198 rtl_writephy(tp, 0x1f, 0x0004);
3199 rtl_writephy(tp, 0x1f, 0x0007);
3200 rtl_writephy(tp, 0x1e, 0x0020);
1b23a3e3 3201 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
70090424
HW		 3202 rtl_writephy(tp, 0x1f, 0x0002);
3203 rtl_writephy(tp, 0x1f, 0x0000);
3204 rtl_writephy(tp, 0x0d, 0x0007);
3205 rtl_writephy(tp, 0x0e, 0x003c);
3206 rtl_writephy(tp, 0x0d, 0x4007);
3207 rtl_writephy(tp, 0x0e, 0x0000);
3208 rtl_writephy(tp, 0x0d, 0x0000);
3209
3210 /* Green feature */
3211 rtl_writephy(tp, 0x1f, 0x0003);
3212 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3213 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3214 rtl_writephy(tp, 0x1f, 0x0000);
e0c07557 3215
9ecb9aab 3216 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3217 rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
70090424
HW		 3218}
3219
5f886e08
HW		 3220static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3221{
3222 /* For 4-corner performance improve */
3223 rtl_writephy(tp, 0x1f, 0x0005);
3224 rtl_writephy(tp, 0x05, 0x8b80);
3225 rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3226 rtl_writephy(tp, 0x1f, 0x0000);
3227
3228 /* PHY auto speed down */
3229 rtl_writephy(tp, 0x1f, 0x0007);
3230 rtl_writephy(tp, 0x1e, 0x002d);
3231 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3232 rtl_writephy(tp, 0x1f, 0x0000);
3233 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3234
3235 /* Improve 10M EEE waveform */
3236 rtl_writephy(tp, 0x1f, 0x0005);
3237 rtl_writephy(tp, 0x05, 0x8b86);
3238 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3239 rtl_writephy(tp, 0x1f, 0x0000);
3240}
3241
c2218925
HW		 3242static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3243{
3244 static const struct phy_reg phy_reg_init[] = {
3245 /* Channel estimation fine tune */
3246 { 0x1f, 0x0003 },
3247 { 0x09, 0xa20f },
3248 { 0x1f, 0x0000 },
3249
3250 /* Modify green table for giga & fnet */
3251 { 0x1f, 0x0005 },
3252 { 0x05, 0x8b55 },
3253 { 0x06, 0x0000 },
3254 { 0x05, 0x8b5e },
3255 { 0x06, 0x0000 },
3256 { 0x05, 0x8b67 },
3257 { 0x06, 0x0000 },
3258 { 0x05, 0x8b70 },
3259 { 0x06, 0x0000 },
3260 { 0x1f, 0x0000 },
3261 { 0x1f, 0x0007 },
3262 { 0x1e, 0x0078 },
3263 { 0x17, 0x0000 },
3264 { 0x19, 0x00fb },
3265 { 0x1f, 0x0000 },
3266
3267 /* Modify green table for 10M */
3268 { 0x1f, 0x0005 },
3269 { 0x05, 0x8b79 },
3270 { 0x06, 0xaa00 },
3271 { 0x1f, 0x0000 },
3272
3273 /* Disable hiimpedance detection (RTCT) */
3274 { 0x1f, 0x0003 },
3275 { 0x01, 0x328a },
3276 { 0x1f, 0x0000 }
3277 };
3278
3279 rtl_apply_firmware(tp);
3280
3281 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3282
5f886e08 3283 rtl8168f_hw_phy_config(tp);
c2218925
HW		 3284
3285 /* Improve 2-pair detection performance */
3286 rtl_writephy(tp, 0x1f, 0x0005);
3287 rtl_writephy(tp, 0x05, 0x8b85);
3288 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3289 rtl_writephy(tp, 0x1f, 0x0000);
3290}
3291
3292static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3293{
3294 rtl_apply_firmware(tp);
3295
5f886e08 3296 rtl8168f_hw_phy_config(tp);
c2218925
HW		 3297}
3298
b3d7b2f2
HW		 3299static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3300{
b3d7b2f2
HW		 3301 static const struct phy_reg phy_reg_init[] = {
3302 /* Channel estimation fine tune */
3303 { 0x1f, 0x0003 },
3304 { 0x09, 0xa20f },
3305 { 0x1f, 0x0000 },
3306
3307 /* Modify green table for giga & fnet */
3308 { 0x1f, 0x0005 },
3309 { 0x05, 0x8b55 },
3310 { 0x06, 0x0000 },
3311 { 0x05, 0x8b5e },
3312 { 0x06, 0x0000 },
3313 { 0x05, 0x8b67 },
3314 { 0x06, 0x0000 },
3315 { 0x05, 0x8b70 },
3316 { 0x06, 0x0000 },
3317 { 0x1f, 0x0000 },
3318 { 0x1f, 0x0007 },
3319 { 0x1e, 0x0078 },
3320 { 0x17, 0x0000 },
3321 { 0x19, 0x00aa },
3322 { 0x1f, 0x0000 },
3323
3324 /* Modify green table for 10M */
3325 { 0x1f, 0x0005 },
3326 { 0x05, 0x8b79 },
3327 { 0x06, 0xaa00 },
3328 { 0x1f, 0x0000 },
3329
3330 /* Disable hiimpedance detection (RTCT) */
3331 { 0x1f, 0x0003 },
3332 { 0x01, 0x328a },
3333 { 0x1f, 0x0000 }
3334 };
3335
3336
3337 rtl_apply_firmware(tp);
3338
3339 rtl8168f_hw_phy_config(tp);
3340
3341 /* Improve 2-pair detection performance */
3342 rtl_writephy(tp, 0x1f, 0x0005);
3343 rtl_writephy(tp, 0x05, 0x8b85);
3344 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3345 rtl_writephy(tp, 0x1f, 0x0000);
3346
3347 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3348
3349 /* Modify green table for giga */
3350 rtl_writephy(tp, 0x1f, 0x0005);
3351 rtl_writephy(tp, 0x05, 0x8b54);
3352 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
3353 rtl_writephy(tp, 0x05, 0x8b5d);
3354 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
3355 rtl_writephy(tp, 0x05, 0x8a7c);
3356 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3357 rtl_writephy(tp, 0x05, 0x8a7f);
3358 rtl_w1w0_phy(tp, 0x06, 0x0100, 0x0000);
3359 rtl_writephy(tp, 0x05, 0x8a82);
3360 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3361 rtl_writephy(tp, 0x05, 0x8a85);
3362 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3363 rtl_writephy(tp, 0x05, 0x8a88);
3364 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3365 rtl_writephy(tp, 0x1f, 0x0000);
3366
3367 /* uc same-seed solution */
3368 rtl_writephy(tp, 0x1f, 0x0005);
3369 rtl_writephy(tp, 0x05, 0x8b85);
3370 rtl_w1w0_phy(tp, 0x06, 0x8000, 0x0000);
3371 rtl_writephy(tp, 0x1f, 0x0000);
3372
3373 /* eee setting */
fdf6fc06 3374 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
b3d7b2f2
HW		 3375 rtl_writephy(tp, 0x1f, 0x0005);
3376 rtl_writephy(tp, 0x05, 0x8b85);
3377 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3378 rtl_writephy(tp, 0x1f, 0x0004);
3379 rtl_writephy(tp, 0x1f, 0x0007);
3380 rtl_writephy(tp, 0x1e, 0x0020);
3381 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
3382 rtl_writephy(tp, 0x1f, 0x0000);
3383 rtl_writephy(tp, 0x0d, 0x0007);
3384 rtl_writephy(tp, 0x0e, 0x003c);
3385 rtl_writephy(tp, 0x0d, 0x4007);
3386 rtl_writephy(tp, 0x0e, 0x0000);
3387 rtl_writephy(tp, 0x0d, 0x0000);
3388
3389 /* Green feature */
3390 rtl_writephy(tp, 0x1f, 0x0003);
3391 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3392 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3393 rtl_writephy(tp, 0x1f, 0x0000);
3394}
3395
c558386b
HW		 3396static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3397{
c558386b
HW		 3398 rtl_apply_firmware(tp);
3399
41f44d13 3400 rtl_writephy(tp, 0x1f, 0x0a46);
3401 if (rtl_readphy(tp, 0x10) & 0x0100) {
3402 rtl_writephy(tp, 0x1f, 0x0bcc);
3403 rtl_w1w0_phy(tp, 0x12, 0x0000, 0x8000);
3404 } else {
3405 rtl_writephy(tp, 0x1f, 0x0bcc);
3406 rtl_w1w0_phy(tp, 0x12, 0x8000, 0x0000);
3407 }
c558386b 3408
41f44d13 3409 rtl_writephy(tp, 0x1f, 0x0a46);
3410 if (rtl_readphy(tp, 0x13) & 0x0100) {
3411 rtl_writephy(tp, 0x1f, 0x0c41);
3412 rtl_w1w0_phy(tp, 0x15, 0x0002, 0x0000);
3413 } else {
fe7524c0 3414 rtl_writephy(tp, 0x1f, 0x0c41);
3415 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0002);
41f44d13 3416 }
c558386b 3417
41f44d13 3418 /* Enable PHY auto speed down */
3419 rtl_writephy(tp, 0x1f, 0x0a44);
3420 rtl_w1w0_phy(tp, 0x11, 0x000c, 0x0000);
c558386b 3421
fe7524c0 3422 rtl_writephy(tp, 0x1f, 0x0bcc);
3423 rtl_w1w0_phy(tp, 0x14, 0x0100, 0x0000);
3424 rtl_writephy(tp, 0x1f, 0x0a44);
3425 rtl_w1w0_phy(tp, 0x11, 0x00c0, 0x0000);
3426 rtl_writephy(tp, 0x1f, 0x0a43);
3427 rtl_writephy(tp, 0x13, 0x8084);
3428 rtl_w1w0_phy(tp, 0x14, 0x0000, 0x6000);
3429 rtl_w1w0_phy(tp, 0x10, 0x1003, 0x0000);
3430
41f44d13 3431 /* EEE auto-fallback function */
3432 rtl_writephy(tp, 0x1f, 0x0a4b);
3433 rtl_w1w0_phy(tp, 0x11, 0x0004, 0x0000);
c558386b 3434
41f44d13 3435 /* Enable UC LPF tune function */
3436 rtl_writephy(tp, 0x1f, 0x0a43);
3437 rtl_writephy(tp, 0x13, 0x8012);
3438 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3439
3440 rtl_writephy(tp, 0x1f, 0x0c42);
3441 rtl_w1w0_phy(tp, 0x11, 0x4000, 0x2000);
3442
fe7524c0 3443 /* Improve SWR Efficiency */
3444 rtl_writephy(tp, 0x1f, 0x0bcd);
3445 rtl_writephy(tp, 0x14, 0x5065);
3446 rtl_writephy(tp, 0x14, 0xd065);
3447 rtl_writephy(tp, 0x1f, 0x0bc8);
3448 rtl_writephy(tp, 0x11, 0x5655);
3449 rtl_writephy(tp, 0x1f, 0x0bcd);
3450 rtl_writephy(tp, 0x14, 0x1065);
3451 rtl_writephy(tp, 0x14, 0x9065);
3452 rtl_writephy(tp, 0x14, 0x1065);
3453
1bac1072
DC		 3454 /* Check ALDPS bit, disable it if enabled */
3455 rtl_writephy(tp, 0x1f, 0x0a43);
3456 if (rtl_readphy(tp, 0x10) & 0x0004)
3457 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0004);
3458
41f44d13 3459 rtl_writephy(tp, 0x1f, 0x0000);
c558386b
HW		 3460}
3461
57538c4a 3462static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3463{
3464 rtl_apply_firmware(tp);
3465}
3466
4da19633 3467static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2857ffb7 3468{
350f7596 3469 static const struct phy_reg phy_reg_init[] = {
2857ffb7
FR		 3470 { 0x1f, 0x0003 },
3471 { 0x08, 0x441d },
3472 { 0x01, 0x9100 },
3473 { 0x1f, 0x0000 }
3474 };
3475
4da19633 3476 rtl_writephy(tp, 0x1f, 0x0000);
3477 rtl_patchphy(tp, 0x11, 1 << 12);
3478 rtl_patchphy(tp, 0x19, 1 << 13);
3479 rtl_patchphy(tp, 0x10, 1 << 15);
2857ffb7 3480
4da19633 3481 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2857ffb7
FR		 3482}
3483
5a5e4443
HW		 3484static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3485{
3486 static const struct phy_reg phy_reg_init[] = {
3487 { 0x1f, 0x0005 },
3488 { 0x1a, 0x0000 },
3489 { 0x1f, 0x0000 },
3490
3491 { 0x1f, 0x0004 },
3492 { 0x1c, 0x0000 },
3493 { 0x1f, 0x0000 },
3494
3495 { 0x1f, 0x0001 },
3496 { 0x15, 0x7701 },
3497 { 0x1f, 0x0000 }
3498 };
3499
3500 /* Disable ALDPS before ram code */
eef63cc1
FR		 3501 rtl_writephy(tp, 0x1f, 0x0000);
3502 rtl_writephy(tp, 0x18, 0x0310);
3503 msleep(100);
5a5e4443 3504
953a12cc 3505 rtl_apply_firmware(tp);
5a5e4443
HW		 3506
3507 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3508}
3509
7e18dca1
HW		 3510static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3511{
7e18dca1 3512 /* Disable ALDPS before setting firmware */
eef63cc1
FR		 3513 rtl_writephy(tp, 0x1f, 0x0000);
3514 rtl_writephy(tp, 0x18, 0x0310);
3515 msleep(20);
7e18dca1
HW		 3516
3517 rtl_apply_firmware(tp);
3518
3519 /* EEE setting */
fdf6fc06 3520 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
7e18dca1
HW		 3521 rtl_writephy(tp, 0x1f, 0x0004);
3522 rtl_writephy(tp, 0x10, 0x401f);
3523 rtl_writephy(tp, 0x19, 0x7030);
3524 rtl_writephy(tp, 0x1f, 0x0000);
3525}
3526
5598bfe5
HW		 3527static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3528{
5598bfe5
HW		 3529 static const struct phy_reg phy_reg_init[] = {
3530 { 0x1f, 0x0004 },
3531 { 0x10, 0xc07f },
3532 { 0x19, 0x7030 },
3533 { 0x1f, 0x0000 }
3534 };
3535
3536 /* Disable ALDPS before ram code */
eef63cc1
FR		 3537 rtl_writephy(tp, 0x1f, 0x0000);
3538 rtl_writephy(tp, 0x18, 0x0310);
3539 msleep(100);
5598bfe5
HW		 3540
3541 rtl_apply_firmware(tp);
3542
fdf6fc06 3543 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5598bfe5
HW		 3544 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3545
fdf6fc06 3546 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5598bfe5
HW		 3547}
3548
5615d9f1
FR		 3549static void rtl_hw_phy_config(struct net_device *dev)
3550{
3551 struct rtl8169_private *tp = netdev_priv(dev);
5615d9f1
FR		 3552
3553 rtl8169_print_mac_version(tp);
3554
3555 switch (tp->mac_version) {
3556 case RTL_GIGA_MAC_VER_01:
3557 break;
3558 case RTL_GIGA_MAC_VER_02:
3559 case RTL_GIGA_MAC_VER_03:
4da19633 3560 rtl8169s_hw_phy_config(tp);
5615d9f1
FR		 3561 break;
3562 case RTL_GIGA_MAC_VER_04:
4da19633 3563 rtl8169sb_hw_phy_config(tp);
5615d9f1 3564 break;
2e955856 3565 case RTL_GIGA_MAC_VER_05:
4da19633 3566 rtl8169scd_hw_phy_config(tp);
2e955856 3567 break;
8c7006aa 3568 case RTL_GIGA_MAC_VER_06:
4da19633 3569 rtl8169sce_hw_phy_config(tp);
8c7006aa 3570 break;
2857ffb7
FR		 3571 case RTL_GIGA_MAC_VER_07:
3572 case RTL_GIGA_MAC_VER_08:
3573 case RTL_GIGA_MAC_VER_09:
4da19633 3574 rtl8102e_hw_phy_config(tp);
2857ffb7 3575 break;
236b8082 3576 case RTL_GIGA_MAC_VER_11:
4da19633 3577 rtl8168bb_hw_phy_config(tp);
236b8082
FR		 3578 break;
3579 case RTL_GIGA_MAC_VER_12:
4da19633 3580 rtl8168bef_hw_phy_config(tp);
236b8082
FR		 3581 break;
3582 case RTL_GIGA_MAC_VER_17:
4da19633 3583 rtl8168bef_hw_phy_config(tp);
236b8082 3584 break;
867763c1 3585 case RTL_GIGA_MAC_VER_18:
4da19633 3586 rtl8168cp_1_hw_phy_config(tp);
867763c1
FR		 3587 break;
3588 case RTL_GIGA_MAC_VER_19:
4da19633 3589 rtl8168c_1_hw_phy_config(tp);
867763c1 3590 break;
7da97ec9 3591 case RTL_GIGA_MAC_VER_20:
4da19633 3592 rtl8168c_2_hw_phy_config(tp);
7da97ec9 3593 break;
197ff761 3594 case RTL_GIGA_MAC_VER_21:
4da19633 3595 rtl8168c_3_hw_phy_config(tp);
197ff761 3596 break;
6fb07058 3597 case RTL_GIGA_MAC_VER_22:
4da19633 3598 rtl8168c_4_hw_phy_config(tp);
6fb07058 3599 break;
ef3386f0 3600 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 3601 case RTL_GIGA_MAC_VER_24:
4da19633 3602 rtl8168cp_2_hw_phy_config(tp);
ef3386f0 3603 break;
5b538df9 3604 case RTL_GIGA_MAC_VER_25:
bca03d5f 3605 rtl8168d_1_hw_phy_config(tp);
daf9df6d 3606 break;
3607 case RTL_GIGA_MAC_VER_26:
bca03d5f 3608 rtl8168d_2_hw_phy_config(tp);
daf9df6d 3609 break;
3610 case RTL_GIGA_MAC_VER_27:
4da19633 3611 rtl8168d_3_hw_phy_config(tp);
5b538df9 3612 break;
e6de30d6 3613 case RTL_GIGA_MAC_VER_28:
3614 rtl8168d_4_hw_phy_config(tp);
3615 break;
5a5e4443
HW		 3616 case RTL_GIGA_MAC_VER_29:
3617 case RTL_GIGA_MAC_VER_30:
3618 rtl8105e_hw_phy_config(tp);
3619 break;
cecb5fd7
FR		 3620 case RTL_GIGA_MAC_VER_31:
3621 /* None. */
3622 break;
01dc7fec 3623 case RTL_GIGA_MAC_VER_32:
01dc7fec 3624 case RTL_GIGA_MAC_VER_33:
70090424
HW		 3625 rtl8168e_1_hw_phy_config(tp);
3626 break;
3627 case RTL_GIGA_MAC_VER_34:
3628 rtl8168e_2_hw_phy_config(tp);
01dc7fec 3629 break;
c2218925
HW		 3630 case RTL_GIGA_MAC_VER_35:
3631 rtl8168f_1_hw_phy_config(tp);
3632 break;
3633 case RTL_GIGA_MAC_VER_36:
3634 rtl8168f_2_hw_phy_config(tp);
3635 break;
ef3386f0 3636
7e18dca1
HW		 3637 case RTL_GIGA_MAC_VER_37:
3638 rtl8402_hw_phy_config(tp);
3639 break;
3640
b3d7b2f2
HW		 3641 case RTL_GIGA_MAC_VER_38:
3642 rtl8411_hw_phy_config(tp);
3643 break;
3644
5598bfe5
HW		 3645 case RTL_GIGA_MAC_VER_39:
3646 rtl8106e_hw_phy_config(tp);
3647 break;
3648
c558386b
HW		 3649 case RTL_GIGA_MAC_VER_40:
3650 rtl8168g_1_hw_phy_config(tp);
3651 break;
57538c4a 3652 case RTL_GIGA_MAC_VER_42:
58152cd4 3653 case RTL_GIGA_MAC_VER_43:
45dd95c4 3654 case RTL_GIGA_MAC_VER_44:
57538c4a 3655 rtl8168g_2_hw_phy_config(tp);
3656 break;
c558386b
HW		 3657
3658 case RTL_GIGA_MAC_VER_41:
5615d9f1
FR		 3659 default:
3660 break;
3661 }
3662}
3663
da78dbff 3664static void rtl_phy_work(struct rtl8169_private *tp)
1da177e4 3665{
1da177e4
LT		 3666 struct timer_list *timer = &tp->timer;
3667 void __iomem *ioaddr = tp->mmio_addr;
3668 unsigned long timeout = RTL8169_PHY_TIMEOUT;
3669
bcf0bf90 3670 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 3671
4da19633 3672 if (tp->phy_reset_pending(tp)) {
5b0384f4 3673 /*
1da177e4
LT		 3674 * A busy loop could burn quite a few cycles on nowadays CPU.
3675 * Let's delay the execution of the timer for a few ticks.
3676 */
3677 timeout = HZ/10;
3678 goto out_mod_timer;
3679 }
3680
3681 if (tp->link_ok(ioaddr))
da78dbff 3682 return;
1da177e4 3683
9bb8eeb5 3684 netif_dbg(tp, link, tp->dev, "PHY reset until link up\n");
1da177e4 3685
4da19633 3686 tp->phy_reset_enable(tp);
1da177e4
LT		 3687
3688out_mod_timer:
3689 mod_timer(timer, jiffies + timeout);
da78dbff
FR		 3690}
3691
3692static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3693{
da78dbff
FR		 3694 if (!test_and_set_bit(flag, tp->wk.flags))
3695 schedule_work(&tp->wk.work);
da78dbff
FR		 3696}
3697
3698static void rtl8169_phy_timer(unsigned long __opaque)
3699{
3700 struct net_device *dev = (struct net_device *)__opaque;
3701 struct rtl8169_private *tp = netdev_priv(dev);
3702
98ddf986 3703 rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
1da177e4
LT		 3704}
3705
1da177e4
LT		 3706static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3707 void __iomem *ioaddr)
3708{
3709 iounmap(ioaddr);
3710 pci_release_regions(pdev);
87aeec76 3711 pci_clear_mwi(pdev);
1da177e4
LT		 3712 pci_disable_device(pdev);
3713 free_netdev(dev);
3714}
3715
ffc46952
FR		 3716DECLARE_RTL_COND(rtl_phy_reset_cond)
3717{
3718 return tp->phy_reset_pending(tp);
3719}
3720
bf793295
FR		 3721static void rtl8169_phy_reset(struct net_device *dev,
3722 struct rtl8169_private *tp)
3723{
4da19633 3724 tp->phy_reset_enable(tp);
ffc46952 3725 rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100);
bf793295
FR		 3726}
3727
2544bfc0
FR		 3728static bool rtl_tbi_enabled(struct rtl8169_private *tp)
3729{
3730 void __iomem *ioaddr = tp->mmio_addr;
3731
3732 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
3733 (RTL_R8(PHYstatus) & TBI_Enable);
3734}
3735
4ff96fa6
FR		 3736static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3737{
3738 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 3739
5615d9f1 3740 rtl_hw_phy_config(dev);
4ff96fa6 3741
77332894
MS		 3742 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3743 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3744 RTL_W8(0x82, 0x01);
3745 }
4ff96fa6 3746
6dccd16b
FR		 3747 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3748
3749 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3750 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 3751
bcf0bf90 3752 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 3753 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3754 RTL_W8(0x82, 0x01);
3755 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4da19633 3756 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4ff96fa6
FR		 3757 }
3758
bf793295
FR		 3759 rtl8169_phy_reset(dev, tp);
3760
54405cde 3761 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
cecb5fd7
FR		 3762 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3763 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3764 (tp->mii.supports_gmii ?
3765 ADVERTISED_1000baseT_Half |
3766 ADVERTISED_1000baseT_Full : 0));
4ff96fa6 3767
2544bfc0 3768 if (rtl_tbi_enabled(tp))
bf82c189 3769 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4ff96fa6
FR		 3770}
3771
773d2021
FR		 3772static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3773{
3774 void __iomem *ioaddr = tp->mmio_addr;
773d2021 3775
da78dbff 3776 rtl_lock_work(tp);
773d2021
FR		 3777
3778 RTL_W8(Cfg9346, Cfg9346_Unlock);
908ba2bf 3779
9ecb9aab 3780 RTL_W32(MAC4, addr[4] | addr[5] << 8);
908ba2bf 3781 RTL_R32(MAC4);
3782
9ecb9aab 3783 RTL_W32(MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
908ba2bf 3784 RTL_R32(MAC0);
3785
9ecb9aab 3786 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
3787 rtl_rar_exgmac_set(tp, addr);
c28aa385 3788
773d2021
FR		 3789 RTL_W8(Cfg9346, Cfg9346_Lock);
3790
da78dbff 3791 rtl_unlock_work(tp);
773d2021
FR		 3792}
3793
3794static int rtl_set_mac_address(struct net_device *dev, void *p)
3795{
3796 struct rtl8169_private *tp = netdev_priv(dev);
3797 struct sockaddr *addr = p;
3798
3799 if (!is_valid_ether_addr(addr->sa_data))
3800 return -EADDRNOTAVAIL;
3801
3802 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3803
3804 rtl_rar_set(tp, dev->dev_addr);
3805
3806 return 0;
3807}
3808
5f787a1a
FR		 3809static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3810{
3811 struct rtl8169_private *tp = netdev_priv(dev);
3812 struct mii_ioctl_data *data = if_mii(ifr);
3813
8b4ab28d
FR		 3814 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
3815}
5f787a1a 3816
cecb5fd7
FR		 3817static int rtl_xmii_ioctl(struct rtl8169_private *tp,
3818 struct mii_ioctl_data *data, int cmd)
8b4ab28d 3819{
5f787a1a
FR		 3820 switch (cmd) {
3821 case SIOCGMIIPHY:
3822 data->phy_id = 32; /* Internal PHY */
3823 return 0;
3824
3825 case SIOCGMIIREG:
4da19633 3826 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
5f787a1a
FR		 3827 return 0;
3828
3829 case SIOCSMIIREG:
4da19633 3830 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
5f787a1a
FR		 3831 return 0;
3832 }
3833 return -EOPNOTSUPP;
3834}
3835
8b4ab28d
FR		 3836static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3837{
3838 return -EOPNOTSUPP;
3839}
3840
fbac58fc
FR		 3841static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3842{
3843 if (tp->features & RTL_FEATURE_MSI) {
3844 pci_disable_msi(pdev);
3845 tp->features &= ~RTL_FEATURE_MSI;
3846 }
3847}
3848
baf63293 3849static void rtl_init_mdio_ops(struct rtl8169_private *tp)
c0e45c1c 3850{
3851 struct mdio_ops *ops = &tp->mdio_ops;
3852
3853 switch (tp->mac_version) {
3854 case RTL_GIGA_MAC_VER_27:
3855 ops->write = r8168dp_1_mdio_write;
3856 ops->read = r8168dp_1_mdio_read;
3857 break;
e6de30d6 3858 case RTL_GIGA_MAC_VER_28:
4804b3b3 3859 case RTL_GIGA_MAC_VER_31:
e6de30d6 3860 ops->write = r8168dp_2_mdio_write;
3861 ops->read = r8168dp_2_mdio_read;
3862 break;
c558386b
HW		 3863 case RTL_GIGA_MAC_VER_40:
3864 case RTL_GIGA_MAC_VER_41:
57538c4a 3865 case RTL_GIGA_MAC_VER_42:
58152cd4 3866 case RTL_GIGA_MAC_VER_43:
45dd95c4 3867 case RTL_GIGA_MAC_VER_44:
c558386b
HW		 3868 ops->write = r8168g_mdio_write;
3869 ops->read = r8168g_mdio_read;
3870 break;
c0e45c1c 3871 default:
3872 ops->write = r8169_mdio_write;
3873 ops->read = r8169_mdio_read;
3874 break;
3875 }
3876}
3877
e2409d83 3878static void rtl_speed_down(struct rtl8169_private *tp)
3879{
3880 u32 adv;
3881 int lpa;
3882
3883 rtl_writephy(tp, 0x1f, 0x0000);
3884 lpa = rtl_readphy(tp, MII_LPA);
3885
3886 if (lpa & (LPA_10HALF | LPA_10FULL))
3887 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
3888 else if (lpa & (LPA_100HALF | LPA_100FULL))
3889 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3890 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
3891 else
3892 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3893 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3894 (tp->mii.supports_gmii ?
3895 ADVERTISED_1000baseT_Half |
3896 ADVERTISED_1000baseT_Full : 0);
3897
3898 rtl8169_set_speed(tp->dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
3899 adv);
3900}
3901
649b3b8c 3902static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3903{
3904 void __iomem *ioaddr = tp->mmio_addr;
3905
3906 switch (tp->mac_version) {
b00e69de
CB		 3907 case RTL_GIGA_MAC_VER_25:
3908 case RTL_GIGA_MAC_VER_26:
649b3b8c 3909 case RTL_GIGA_MAC_VER_29:
3910 case RTL_GIGA_MAC_VER_30:
3911 case RTL_GIGA_MAC_VER_32:
3912 case RTL_GIGA_MAC_VER_33:
3913 case RTL_GIGA_MAC_VER_34:
7e18dca1 3914 case RTL_GIGA_MAC_VER_37:
b3d7b2f2 3915 case RTL_GIGA_MAC_VER_38:
5598bfe5 3916 case RTL_GIGA_MAC_VER_39:
c558386b
HW		 3917 case RTL_GIGA_MAC_VER_40:
3918 case RTL_GIGA_MAC_VER_41:
57538c4a 3919 case RTL_GIGA_MAC_VER_42:
58152cd4 3920 case RTL_GIGA_MAC_VER_43:
45dd95c4 3921 case RTL_GIGA_MAC_VER_44:
649b3b8c 3922 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3923 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3924 break;
3925 default:
3926 break;
3927 }
3928}
3929
3930static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
3931{
3932 if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
3933 return false;
3934
e2409d83 3935 rtl_speed_down(tp);
649b3b8c 3936 rtl_wol_suspend_quirk(tp);
3937
3938 return true;
3939}
3940
065c27c1 3941static void r810x_phy_power_down(struct rtl8169_private *tp)
3942{
3943 rtl_writephy(tp, 0x1f, 0x0000);
3944 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3945}
3946
3947static void r810x_phy_power_up(struct rtl8169_private *tp)
3948{
3949 rtl_writephy(tp, 0x1f, 0x0000);
3950 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3951}
3952
3953static void r810x_pll_power_down(struct rtl8169_private *tp)
3954{
0004299a
HW		 3955 void __iomem *ioaddr = tp->mmio_addr;
3956
649b3b8c 3957 if (rtl_wol_pll_power_down(tp))
065c27c1 3958 return;
065c27c1 3959
3960 r810x_phy_power_down(tp);
0004299a
HW		 3961
3962 switch (tp->mac_version) {
3963 case RTL_GIGA_MAC_VER_07:
3964 case RTL_GIGA_MAC_VER_08:
3965 case RTL_GIGA_MAC_VER_09:
3966 case RTL_GIGA_MAC_VER_10:
3967 case RTL_GIGA_MAC_VER_13:
3968 case RTL_GIGA_MAC_VER_16:
3969 break;
3970 default:
3971 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3972 break;
3973 }
065c27c1 3974}
3975
3976static void r810x_pll_power_up(struct rtl8169_private *tp)
3977{
0004299a
HW		 3978 void __iomem *ioaddr = tp->mmio_addr;
3979
065c27c1 3980 r810x_phy_power_up(tp);
0004299a
HW		 3981
3982 switch (tp->mac_version) {
3983 case RTL_GIGA_MAC_VER_07:
3984 case RTL_GIGA_MAC_VER_08:
3985 case RTL_GIGA_MAC_VER_09:
3986 case RTL_GIGA_MAC_VER_10:
3987 case RTL_GIGA_MAC_VER_13:
3988 case RTL_GIGA_MAC_VER_16:
3989 break;
3990 default:
3991 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3992 break;
3993 }
065c27c1 3994}
3995
3996static void r8168_phy_power_up(struct rtl8169_private *tp)
3997{
3998 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3999 switch (tp->mac_version) {
4000 case RTL_GIGA_MAC_VER_11:
4001 case RTL_GIGA_MAC_VER_12:
4002 case RTL_GIGA_MAC_VER_17:
4003 case RTL_GIGA_MAC_VER_18:
4004 case RTL_GIGA_MAC_VER_19:
4005 case RTL_GIGA_MAC_VER_20:
4006 case RTL_GIGA_MAC_VER_21:
4007 case RTL_GIGA_MAC_VER_22:
4008 case RTL_GIGA_MAC_VER_23:
4009 case RTL_GIGA_MAC_VER_24:
4010 case RTL_GIGA_MAC_VER_25:
4011 case RTL_GIGA_MAC_VER_26:
4012 case RTL_GIGA_MAC_VER_27:
4013 case RTL_GIGA_MAC_VER_28:
4014 case RTL_GIGA_MAC_VER_31:
4015 rtl_writephy(tp, 0x0e, 0x0000);
4016 break;
4017 default:
4018 break;
4019 }
065c27c1 4020 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4021}
4022
4023static void r8168_phy_power_down(struct rtl8169_private *tp)
4024{
4025 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 4026 switch (tp->mac_version) {
4027 case RTL_GIGA_MAC_VER_32:
4028 case RTL_GIGA_MAC_VER_33:
beb330a4 4029 case RTL_GIGA_MAC_VER_40:
4030 case RTL_GIGA_MAC_VER_41:
01dc7fec 4031 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
4032 break;
4033
4034 case RTL_GIGA_MAC_VER_11:
4035 case RTL_GIGA_MAC_VER_12:
4036 case RTL_GIGA_MAC_VER_17:
4037 case RTL_GIGA_MAC_VER_18:
4038 case RTL_GIGA_MAC_VER_19:
4039 case RTL_GIGA_MAC_VER_20:
4040 case RTL_GIGA_MAC_VER_21:
4041 case RTL_GIGA_MAC_VER_22:
4042 case RTL_GIGA_MAC_VER_23:
4043 case RTL_GIGA_MAC_VER_24:
4044 case RTL_GIGA_MAC_VER_25:
4045 case RTL_GIGA_MAC_VER_26:
4046 case RTL_GIGA_MAC_VER_27:
4047 case RTL_GIGA_MAC_VER_28:
4048 case RTL_GIGA_MAC_VER_31:
4049 rtl_writephy(tp, 0x0e, 0x0200);
4050 default:
4051 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4052 break;
4053 }
065c27c1 4054}
4055
4056static void r8168_pll_power_down(struct rtl8169_private *tp)
4057{
4058 void __iomem *ioaddr = tp->mmio_addr;
4059
cecb5fd7
FR		 4060 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4061 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4062 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
4804b3b3 4063 r8168dp_check_dash(tp)) {
065c27c1 4064 return;
5d2e1957 4065 }
065c27c1 4066
cecb5fd7
FR		 4067 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
4068 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
065c27c1 4069 (RTL_R16(CPlusCmd) & ASF)) {
4070 return;
4071 }
4072
01dc7fec 4073 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4074 tp->mac_version == RTL_GIGA_MAC_VER_33)
fdf6fc06 4075 rtl_ephy_write(tp, 0x19, 0xff64);
01dc7fec 4076
649b3b8c 4077 if (rtl_wol_pll_power_down(tp))
065c27c1 4078 return;
065c27c1 4079
4080 r8168_phy_power_down(tp);
4081
4082 switch (tp->mac_version) {
4083 case RTL_GIGA_MAC_VER_25:
4084 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 4085 case RTL_GIGA_MAC_VER_27:
4086 case RTL_GIGA_MAC_VER_28:
4804b3b3 4087 case RTL_GIGA_MAC_VER_31:
01dc7fec 4088 case RTL_GIGA_MAC_VER_32:
4089 case RTL_GIGA_MAC_VER_33:
065c27c1 4090 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4091 break;
beb330a4 4092 case RTL_GIGA_MAC_VER_40:
4093 case RTL_GIGA_MAC_VER_41:
4094 rtl_w1w0_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
4095 0xfc000000, ERIAR_EXGMAC);
4096 break;
065c27c1 4097 }
4098}
4099
4100static void r8168_pll_power_up(struct rtl8169_private *tp)
4101{
4102 void __iomem *ioaddr = tp->mmio_addr;
4103
065c27c1 4104 switch (tp->mac_version) {
4105 case RTL_GIGA_MAC_VER_25:
4106 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 4107 case RTL_GIGA_MAC_VER_27:
4108 case RTL_GIGA_MAC_VER_28:
4804b3b3 4109 case RTL_GIGA_MAC_VER_31:
01dc7fec 4110 case RTL_GIGA_MAC_VER_32:
4111 case RTL_GIGA_MAC_VER_33:
065c27c1 4112 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4113 break;
beb330a4 4114 case RTL_GIGA_MAC_VER_40:
4115 case RTL_GIGA_MAC_VER_41:
4116 rtl_w1w0_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
4117 0x00000000, ERIAR_EXGMAC);
4118 break;
065c27c1 4119 }
4120
4121 r8168_phy_power_up(tp);
4122}
4123
d58d46b5
FR		 4124static void rtl_generic_op(struct rtl8169_private *tp,
4125 void (*op)(struct rtl8169_private *))
065c27c1 4126{
4127 if (op)
4128 op(tp);
4129}
4130
4131static void rtl_pll_power_down(struct rtl8169_private *tp)
4132{
d58d46b5 4133 rtl_generic_op(tp, tp->pll_power_ops.down);
065c27c1 4134}
4135
4136static void rtl_pll_power_up(struct rtl8169_private *tp)
4137{
d58d46b5 4138 rtl_generic_op(tp, tp->pll_power_ops.up);
065c27c1 4139}
4140
baf63293 4141static void rtl_init_pll_power_ops(struct rtl8169_private *tp)
065c27c1 4142{
4143 struct pll_power_ops *ops = &tp->pll_power_ops;
4144
4145 switch (tp->mac_version) {
4146 case RTL_GIGA_MAC_VER_07:
4147 case RTL_GIGA_MAC_VER_08:
4148 case RTL_GIGA_MAC_VER_09:
4149 case RTL_GIGA_MAC_VER_10:
4150 case RTL_GIGA_MAC_VER_16:
5a5e4443
HW		 4151 case RTL_GIGA_MAC_VER_29:
4152 case RTL_GIGA_MAC_VER_30:
7e18dca1 4153 case RTL_GIGA_MAC_VER_37:
5598bfe5 4154 case RTL_GIGA_MAC_VER_39:
58152cd4 4155 case RTL_GIGA_MAC_VER_43:
065c27c1 4156 ops->down = r810x_pll_power_down;
4157 ops->up = r810x_pll_power_up;
4158 break;
4159
4160 case RTL_GIGA_MAC_VER_11:
4161 case RTL_GIGA_MAC_VER_12:
4162 case RTL_GIGA_MAC_VER_17:
4163 case RTL_GIGA_MAC_VER_18:
4164 case RTL_GIGA_MAC_VER_19:
4165 case RTL_GIGA_MAC_VER_20:
4166 case RTL_GIGA_MAC_VER_21:
4167 case RTL_GIGA_MAC_VER_22:
4168 case RTL_GIGA_MAC_VER_23:
4169 case RTL_GIGA_MAC_VER_24:
4170 case RTL_GIGA_MAC_VER_25:
4171 case RTL_GIGA_MAC_VER_26:
4172 case RTL_GIGA_MAC_VER_27:
e6de30d6 4173 case RTL_GIGA_MAC_VER_28:
4804b3b3 4174 case RTL_GIGA_MAC_VER_31:
01dc7fec 4175 case RTL_GIGA_MAC_VER_32:
4176 case RTL_GIGA_MAC_VER_33:
70090424 4177 case RTL_GIGA_MAC_VER_34:
c2218925
HW		 4178 case RTL_GIGA_MAC_VER_35:
4179 case RTL_GIGA_MAC_VER_36:
b3d7b2f2 4180 case RTL_GIGA_MAC_VER_38:
c558386b
HW		 4181 case RTL_GIGA_MAC_VER_40:
4182 case RTL_GIGA_MAC_VER_41:
57538c4a 4183 case RTL_GIGA_MAC_VER_42:
45dd95c4 4184 case RTL_GIGA_MAC_VER_44:
065c27c1 4185 ops->down = r8168_pll_power_down;
4186 ops->up = r8168_pll_power_up;
4187 break;
4188
4189 default:
4190 ops->down = NULL;
4191 ops->up = NULL;
4192 break;
4193 }
4194}
4195
e542a226
HW		 4196static void rtl_init_rxcfg(struct rtl8169_private *tp)
4197{
4198 void __iomem *ioaddr = tp->mmio_addr;
4199
4200 switch (tp->mac_version) {
4201 case RTL_GIGA_MAC_VER_01:
4202 case RTL_GIGA_MAC_VER_02:
4203 case RTL_GIGA_MAC_VER_03:
4204 case RTL_GIGA_MAC_VER_04:
4205 case RTL_GIGA_MAC_VER_05:
4206 case RTL_GIGA_MAC_VER_06:
4207 case RTL_GIGA_MAC_VER_10:
4208 case RTL_GIGA_MAC_VER_11:
4209 case RTL_GIGA_MAC_VER_12:
4210 case RTL_GIGA_MAC_VER_13:
4211 case RTL_GIGA_MAC_VER_14:
4212 case RTL_GIGA_MAC_VER_15:
4213 case RTL_GIGA_MAC_VER_16:
4214 case RTL_GIGA_MAC_VER_17:
4215 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4216 break;
4217 case RTL_GIGA_MAC_VER_18:
4218 case RTL_GIGA_MAC_VER_19:
4219 case RTL_GIGA_MAC_VER_20:
4220 case RTL_GIGA_MAC_VER_21:
4221 case RTL_GIGA_MAC_VER_22:
4222 case RTL_GIGA_MAC_VER_23:
4223 case RTL_GIGA_MAC_VER_24:
eb2dc35d 4224 case RTL_GIGA_MAC_VER_34:
3ced8c95 4225 case RTL_GIGA_MAC_VER_35:
e542a226
HW		 4226 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4227 break;
beb330a4 4228 case RTL_GIGA_MAC_VER_40:
7a9810e7
MD		 4229 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
4230 break;
beb330a4 4231 case RTL_GIGA_MAC_VER_41:
57538c4a 4232 case RTL_GIGA_MAC_VER_42:
58152cd4 4233 case RTL_GIGA_MAC_VER_43:
45dd95c4 4234 case RTL_GIGA_MAC_VER_44:
beb330a4 4235 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST | RX_EARLY_OFF);
4236 break;
e542a226
HW		 4237 default:
4238 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
4239 break;
4240 }
4241}
4242
92fc43b4
HW		 4243static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4244{
9fba0812 4245 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
92fc43b4
HW		 4246}
4247
d58d46b5
FR		 4248static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4249{
9c5028e9 4250 void __iomem *ioaddr = tp->mmio_addr;
4251
4252 RTL_W8(Cfg9346, Cfg9346_Unlock);
d58d46b5 4253 rtl_generic_op(tp, tp->jumbo_ops.enable);
9c5028e9 4254 RTL_W8(Cfg9346, Cfg9346_Lock);
d58d46b5
FR		 4255}
4256
4257static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4258{
9c5028e9 4259 void __iomem *ioaddr = tp->mmio_addr;
4260
4261 RTL_W8(Cfg9346, Cfg9346_Unlock);
d58d46b5 4262 rtl_generic_op(tp, tp->jumbo_ops.disable);
9c5028e9 4263 RTL_W8(Cfg9346, Cfg9346_Lock);
d58d46b5
FR		 4264}
4265
4266static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4267{
4268 void __iomem *ioaddr = tp->mmio_addr;
4269
4270 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4271 RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
4272 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
4273}
4274
4275static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4276{
4277 void __iomem *ioaddr = tp->mmio_addr;
4278
4279 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4280 RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
4281 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
4282}
4283
4284static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4285{
4286 void __iomem *ioaddr = tp->mmio_addr;
4287
4288 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4289}
4290
4291static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4292{
4293 void __iomem *ioaddr = tp->mmio_addr;
4294
4295 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4296}
4297
4298static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4299{
4300 void __iomem *ioaddr = tp->mmio_addr;
d58d46b5
FR		 4301
4302 RTL_W8(MaxTxPacketSize, 0x3f);
4303 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4304 RTL_W8(Config4, RTL_R8(Config4) | 0x01);
4512ff9f 4305 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
d58d46b5
FR		 4306}
4307
4308static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4309{
4310 void __iomem *ioaddr = tp->mmio_addr;
d58d46b5
FR		 4311
4312 RTL_W8(MaxTxPacketSize, 0x0c);
4313 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4314 RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
4512ff9f 4315 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
d58d46b5
FR		 4316}
4317
4318static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4319{
4320 rtl_tx_performance_tweak(tp->pci_dev,
4321 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4322}
4323
4324static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4325{
4326 rtl_tx_performance_tweak(tp->pci_dev,
4327 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4328}
4329
4330static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4331{
4332 void __iomem *ioaddr = tp->mmio_addr;
4333
4334 r8168b_0_hw_jumbo_enable(tp);
4335
4336 RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
4337}
4338
4339static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4340{
4341 void __iomem *ioaddr = tp->mmio_addr;
4342
4343 r8168b_0_hw_jumbo_disable(tp);
4344
4345 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4346}
4347
baf63293 4348static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
d58d46b5
FR		 4349{
4350 struct jumbo_ops *ops = &tp->jumbo_ops;
4351
4352 switch (tp->mac_version) {
4353 case RTL_GIGA_MAC_VER_11:
4354 ops->disable = r8168b_0_hw_jumbo_disable;
4355 ops->enable = r8168b_0_hw_jumbo_enable;
4356 break;
4357 case RTL_GIGA_MAC_VER_12:
4358 case RTL_GIGA_MAC_VER_17:
4359 ops->disable = r8168b_1_hw_jumbo_disable;
4360 ops->enable = r8168b_1_hw_jumbo_enable;
4361 break;
4362 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
4363 case RTL_GIGA_MAC_VER_19:
4364 case RTL_GIGA_MAC_VER_20:
4365 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
4366 case RTL_GIGA_MAC_VER_22:
4367 case RTL_GIGA_MAC_VER_23:
4368 case RTL_GIGA_MAC_VER_24:
4369 case RTL_GIGA_MAC_VER_25:
4370 case RTL_GIGA_MAC_VER_26:
4371 ops->disable = r8168c_hw_jumbo_disable;
4372 ops->enable = r8168c_hw_jumbo_enable;
4373 break;
4374 case RTL_GIGA_MAC_VER_27:
4375 case RTL_GIGA_MAC_VER_28:
4376 ops->disable = r8168dp_hw_jumbo_disable;
4377 ops->enable = r8168dp_hw_jumbo_enable;
4378 break;
4379 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
4380 case RTL_GIGA_MAC_VER_32:
4381 case RTL_GIGA_MAC_VER_33:
4382 case RTL_GIGA_MAC_VER_34:
4383 ops->disable = r8168e_hw_jumbo_disable;
4384 ops->enable = r8168e_hw_jumbo_enable;
4385 break;
4386
4387 /*
4388 * No action needed for jumbo frames with 8169.
4389 * No jumbo for 810x at all.
4390 */
c558386b
HW		 4391 case RTL_GIGA_MAC_VER_40:
4392 case RTL_GIGA_MAC_VER_41:
57538c4a 4393 case RTL_GIGA_MAC_VER_42:
58152cd4 4394 case RTL_GIGA_MAC_VER_43:
45dd95c4 4395 case RTL_GIGA_MAC_VER_44:
d58d46b5
FR		 4396 default:
4397 ops->disable = NULL;
4398 ops->enable = NULL;
4399 break;
4400 }
4401}
4402
ffc46952
FR		 4403DECLARE_RTL_COND(rtl_chipcmd_cond)
4404{
4405 void __iomem *ioaddr = tp->mmio_addr;
4406
4407 return RTL_R8(ChipCmd) & CmdReset;
4408}
4409
6f43adc8
FR		 4410static void rtl_hw_reset(struct rtl8169_private *tp)
4411{
4412 void __iomem *ioaddr = tp->mmio_addr;
6f43adc8 4413
6f43adc8
FR		 4414 RTL_W8(ChipCmd, CmdReset);
4415
ffc46952 4416 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
6f43adc8
FR		 4417}
4418
b6ffd97f 4419static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
953a12cc 4420{
b6ffd97f
FR		 4421 struct rtl_fw *rtl_fw;
4422 const char *name;
4423 int rc = -ENOMEM;
953a12cc 4424
b6ffd97f
FR		 4425 name = rtl_lookup_firmware_name(tp);
4426 if (!name)
4427 goto out_no_firmware;
953a12cc 4428
b6ffd97f
FR		 4429 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4430 if (!rtl_fw)
4431 goto err_warn;
31bd204f 4432
b6ffd97f
FR		 4433 rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
4434 if (rc < 0)
4435 goto err_free;
4436
fd112f2e
FR		 4437 rc = rtl_check_firmware(tp, rtl_fw);
4438 if (rc < 0)
4439 goto err_release_firmware;
4440
b6ffd97f
FR		 4441 tp->rtl_fw = rtl_fw;
4442out:
4443 return;
4444
fd112f2e
FR		 4445err_release_firmware:
4446 release_firmware(rtl_fw->fw);
b6ffd97f
FR		 4447err_free:
4448 kfree(rtl_fw);
4449err_warn:
4450 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4451 name, rc);
4452out_no_firmware:
4453 tp->rtl_fw = NULL;
4454 goto out;
4455}
4456
4457static void rtl_request_firmware(struct rtl8169_private *tp)
4458{
4459 if (IS_ERR(tp->rtl_fw))
4460 rtl_request_uncached_firmware(tp);
953a12cc
FR		 4461}
4462
92fc43b4
HW		 4463static void rtl_rx_close(struct rtl8169_private *tp)
4464{
4465 void __iomem *ioaddr = tp->mmio_addr;
92fc43b4 4466
1687b566 4467 RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
92fc43b4
HW		 4468}
4469
ffc46952
FR		 4470DECLARE_RTL_COND(rtl_npq_cond)
4471{
4472 void __iomem *ioaddr = tp->mmio_addr;
4473
4474 return RTL_R8(TxPoll) & NPQ;
4475}
4476
4477DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4478{
4479 void __iomem *ioaddr = tp->mmio_addr;
4480
4481 return RTL_R32(TxConfig) & TXCFG_EMPTY;
4482}
4483
e6de30d6 4484static void rtl8169_hw_reset(struct rtl8169_private *tp)
1da177e4 4485{
e6de30d6 4486 void __iomem *ioaddr = tp->mmio_addr;
4487
1da177e4 4488 /* Disable interrupts */
811fd301 4489 rtl8169_irq_mask_and_ack(tp);
1da177e4 4490
92fc43b4
HW		 4491 rtl_rx_close(tp);
4492
5d2e1957 4493 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4804b3b3 4494 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4495 tp->mac_version == RTL_GIGA_MAC_VER_31) {
ffc46952 4496 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
c2218925
HW		 4497 } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
4498 tp->mac_version == RTL_GIGA_MAC_VER_35 ||
7e18dca1 4499 tp->mac_version == RTL_GIGA_MAC_VER_36 ||
b3d7b2f2 4500 tp->mac_version == RTL_GIGA_MAC_VER_37 ||
c558386b
HW		 4501 tp->mac_version == RTL_GIGA_MAC_VER_40 ||
4502 tp->mac_version == RTL_GIGA_MAC_VER_41 ||
57538c4a 4503 tp->mac_version == RTL_GIGA_MAC_VER_42 ||
58152cd4 4504 tp->mac_version == RTL_GIGA_MAC_VER_43 ||
45dd95c4 4505 tp->mac_version == RTL_GIGA_MAC_VER_44 ||
b3d7b2f2 4506 tp->mac_version == RTL_GIGA_MAC_VER_38) {
c2b0c1e7 4507 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
ffc46952 4508 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
92fc43b4
HW		 4509 } else {
4510 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4511 udelay(100);
e6de30d6 4512 }
4513
92fc43b4 4514 rtl_hw_reset(tp);
1da177e4
LT		 4515}
4516
7f796d83 4517static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 4518{
4519 void __iomem *ioaddr = tp->mmio_addr;
9cb427b6
FR		 4520
4521 /* Set DMA burst size and Interframe Gap Time */
4522 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4523 (InterFrameGap << TxInterFrameGapShift));
4524}
4525
07ce4064 4526static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 4527{
4528 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 4529
07ce4064
FR		 4530 tp->hw_start(dev);
4531
da78dbff 4532 rtl_irq_enable_all(tp);
07ce4064
FR		 4533}
4534
7f796d83
FR		 4535static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
4536 void __iomem *ioaddr)
4537{
4538 /*
4539 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4540 * register to be written before TxDescAddrLow to work.
4541 * Switching from MMIO to I/O access fixes the issue as well.
4542 */
4543 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
284901a9 4544 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
7f796d83 4545 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
284901a9 4546 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 4547}
4548
4549static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4550{
4551 u16 cmd;
4552
4553 cmd = RTL_R16(CPlusCmd);
4554 RTL_W16(CPlusCmd, cmd);
4555 return cmd;
4556}
4557
fdd7b4c3 4558static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
7f796d83
FR		 4559{
4560 /* Low hurts. Let's disable the filtering. */
207d6e87 4561 RTL_W16(RxMaxSize, rx_buf_sz + 1);
7f796d83
FR		 4562}
4563
6dccd16b
FR		 4564static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4565{
3744100e 4566 static const struct rtl_cfg2_info {
6dccd16b
FR		 4567 u32 mac_version;
4568 u32 clk;
4569 u32 val;
4570 } cfg2_info [] = {
4571 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4572 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4573 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4574 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3744100e
FR		 4575 };
4576 const struct rtl_cfg2_info *p = cfg2_info;
6dccd16b
FR		 4577 unsigned int i;
4578 u32 clk;
4579
4580 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 4581 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 4582 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4583 RTL_W32(0x7c, p->val);
4584 break;
4585 }
4586 }
4587}
4588
e6b763ea
FR		 4589static void rtl_set_rx_mode(struct net_device *dev)
4590{
4591 struct rtl8169_private *tp = netdev_priv(dev);
4592 void __iomem *ioaddr = tp->mmio_addr;
4593 u32 mc_filter[2]; /* Multicast hash filter */
4594 int rx_mode;
4595 u32 tmp = 0;
4596
4597 if (dev->flags & IFF_PROMISC) {
4598 /* Unconditionally log net taps. */
4599 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4600 rx_mode =
4601 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4602 AcceptAllPhys;
4603 mc_filter[1] = mc_filter[0] = 0xffffffff;
4604 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4605 (dev->flags & IFF_ALLMULTI)) {
4606 /* Too many to filter perfectly -- accept all multicasts. */
4607 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4608 mc_filter[1] = mc_filter[0] = 0xffffffff;
4609 } else {
4610 struct netdev_hw_addr *ha;
4611
4612 rx_mode = AcceptBroadcast | AcceptMyPhys;
4613 mc_filter[1] = mc_filter[0] = 0;
4614 netdev_for_each_mc_addr(ha, dev) {
4615 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4616 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4617 rx_mode |= AcceptMulticast;
4618 }
4619 }
4620
4621 if (dev->features & NETIF_F_RXALL)
4622 rx_mode |= (AcceptErr | AcceptRunt);
4623
4624 tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4625
4626 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4627 u32 data = mc_filter[0];
4628
4629 mc_filter[0] = swab32(mc_filter[1]);
4630 mc_filter[1] = swab32(data);
4631 }
4632
0481776b
NW		 4633 if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4634 mc_filter[1] = mc_filter[0] = 0xffffffff;
4635
e6b763ea
FR		 4636 RTL_W32(MAR0 + 4, mc_filter[1]);
4637 RTL_W32(MAR0 + 0, mc_filter[0]);
4638
4639 RTL_W32(RxConfig, tmp);
4640}
4641
07ce4064
FR		 4642static void rtl_hw_start_8169(struct net_device *dev)
4643{
4644 struct rtl8169_private *tp = netdev_priv(dev);
4645 void __iomem *ioaddr = tp->mmio_addr;
4646 struct pci_dev *pdev = tp->pci_dev;
07ce4064 4647
9cb427b6
FR		 4648 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4649 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4650 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4651 }
4652
1da177e4 4653 RTL_W8(Cfg9346, Cfg9346_Unlock);
cecb5fd7
FR		 4654 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4655 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4656 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4657 tp->mac_version == RTL_GIGA_MAC_VER_04)
9cb427b6
FR		 4658 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4659
e542a226
HW		 4660 rtl_init_rxcfg(tp);
4661
f0298f81 4662 RTL_W8(EarlyTxThres, NoEarlyTx);
1da177e4 4663
6f0333b8 4664 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
1da177e4 4665
cecb5fd7
FR		 4666 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4667 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4668 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4669 tp->mac_version == RTL_GIGA_MAC_VER_04)
c946b304 4670 rtl_set_rx_tx_config_registers(tp);
1da177e4 4671
7f796d83 4672 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 4673
cecb5fd7
FR		 4674 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4675 tp->mac_version == RTL_GIGA_MAC_VER_03) {
06fa7358 4676 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1da177e4 4677 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 4678 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 4679 }
4680
bcf0bf90
FR		 4681 RTL_W16(CPlusCmd, tp->cp_cmd);
4682
6dccd16b
FR		 4683 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4684
1da177e4
LT		 4685 /*
4686 * Undocumented corner. Supposedly:
4687 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4688 */
4689 RTL_W16(IntrMitigate, 0x0000);
4690
7f796d83 4691 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 4692
cecb5fd7
FR		 4693 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4694 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4695 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
4696 tp->mac_version != RTL_GIGA_MAC_VER_04) {
c946b304
FR		 4697 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4698 rtl_set_rx_tx_config_registers(tp);
4699 }
4700
1da177e4 4701 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 4702
4703 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4704 RTL_R8(IntrMask);
1da177e4
LT		 4705
4706 RTL_W32(RxMissed, 0);
4707
07ce4064 4708 rtl_set_rx_mode(dev);
1da177e4
LT		 4709
4710 /* no early-rx interrupts */
4711 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
07ce4064 4712}
1da177e4 4713
beb1fe18
HW		 4714static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4715{
4716 if (tp->csi_ops.write)
52989f0e 4717 tp->csi_ops.write(tp, addr, value);
beb1fe18
HW		 4718}
4719
4720static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4721{
52989f0e 4722 return tp->csi_ops.read ? tp->csi_ops.read(tp, addr) : ~0;
beb1fe18
HW		 4723}
4724
4725static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits)
dacf8154
FR		 4726{
4727 u32 csi;
4728
beb1fe18
HW		 4729 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4730 rtl_csi_write(tp, 0x070c, csi | bits);
4731}
4732
4733static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
4734{
4735 rtl_csi_access_enable(tp, 0x17000000);
650e8d5d 4736}
4737
beb1fe18 4738static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
e6de30d6 4739{
beb1fe18 4740 rtl_csi_access_enable(tp, 0x27000000);
e6de30d6 4741}
4742
ffc46952
FR		 4743DECLARE_RTL_COND(rtl_csiar_cond)
4744{
4745 void __iomem *ioaddr = tp->mmio_addr;
4746
4747 return RTL_R32(CSIAR) & CSIAR_FLAG;
4748}
4749
52989f0e 4750static void r8169_csi_write(struct rtl8169_private *tp, int addr, int value)
650e8d5d 4751{
52989f0e 4752 void __iomem *ioaddr = tp->mmio_addr;
beb1fe18
HW		 4753
4754 RTL_W32(CSIDR, value);
4755 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4756 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4757
ffc46952 4758 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
beb1fe18
HW		 4759}
4760
52989f0e 4761static u32 r8169_csi_read(struct rtl8169_private *tp, int addr)
beb1fe18 4762{
52989f0e 4763 void __iomem *ioaddr = tp->mmio_addr;
beb1fe18
HW		 4764
4765 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
4766 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4767
ffc46952
FR		 4768 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4769 RTL_R32(CSIDR) : ~0;
beb1fe18
HW		 4770}
4771
52989f0e 4772static void r8402_csi_write(struct rtl8169_private *tp, int addr, int value)
7e18dca1 4773{
52989f0e 4774 void __iomem *ioaddr = tp->mmio_addr;
7e18dca1
HW		 4775
4776 RTL_W32(CSIDR, value);
4777 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4778 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
4779 CSIAR_FUNC_NIC);
4780
ffc46952 4781 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
7e18dca1
HW		 4782}
4783
52989f0e 4784static u32 r8402_csi_read(struct rtl8169_private *tp, int addr)
7e18dca1 4785{
52989f0e 4786 void __iomem *ioaddr = tp->mmio_addr;
7e18dca1
HW		 4787
4788 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
4789 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4790
ffc46952
FR		 4791 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4792 RTL_R32(CSIDR) : ~0;
7e18dca1
HW		 4793}
4794
45dd95c4 4795static void r8411_csi_write(struct rtl8169_private *tp, int addr, int value)
4796{
4797 void __iomem *ioaddr = tp->mmio_addr;
4798
4799 RTL_W32(CSIDR, value);
4800 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4801 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
4802 CSIAR_FUNC_NIC2);
4803
4804 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4805}
4806
4807static u32 r8411_csi_read(struct rtl8169_private *tp, int addr)
4808{
4809 void __iomem *ioaddr = tp->mmio_addr;
4810
4811 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC2 |
4812 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4813
4814 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4815 RTL_R32(CSIDR) : ~0;
4816}
4817
baf63293 4818static void rtl_init_csi_ops(struct rtl8169_private *tp)
beb1fe18
HW		 4819{
4820 struct csi_ops *ops = &tp->csi_ops;
4821
4822 switch (tp->mac_version) {
4823 case RTL_GIGA_MAC_VER_01:
4824 case RTL_GIGA_MAC_VER_02:
4825 case RTL_GIGA_MAC_VER_03:
4826 case RTL_GIGA_MAC_VER_04:
4827 case RTL_GIGA_MAC_VER_05:
4828 case RTL_GIGA_MAC_VER_06:
4829 case RTL_GIGA_MAC_VER_10:
4830 case RTL_GIGA_MAC_VER_11:
4831 case RTL_GIGA_MAC_VER_12:
4832 case RTL_GIGA_MAC_VER_13:
4833 case RTL_GIGA_MAC_VER_14:
4834 case RTL_GIGA_MAC_VER_15:
4835 case RTL_GIGA_MAC_VER_16:
4836 case RTL_GIGA_MAC_VER_17:
4837 ops->write = NULL;
4838 ops->read = NULL;
4839 break;
4840
7e18dca1 4841 case RTL_GIGA_MAC_VER_37:
b3d7b2f2 4842 case RTL_GIGA_MAC_VER_38:
7e18dca1
HW		 4843 ops->write = r8402_csi_write;
4844 ops->read = r8402_csi_read;
4845 break;
4846
45dd95c4 4847 case RTL_GIGA_MAC_VER_44:
4848 ops->write = r8411_csi_write;
4849 ops->read = r8411_csi_read;
4850 break;
4851
beb1fe18
HW		 4852 default:
4853 ops->write = r8169_csi_write;
4854 ops->read = r8169_csi_read;
4855 break;
4856 }
dacf8154
FR		 4857}
4858
4859struct ephy_info {
4860 unsigned int offset;
4861 u16 mask;
4862 u16 bits;
4863};
4864
fdf6fc06
FR		 4865static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
4866 int len)
dacf8154
FR		 4867{
4868 u16 w;
4869
4870 while (len-- > 0) {
fdf6fc06
FR		 4871 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4872 rtl_ephy_write(tp, e->offset, w);
dacf8154
FR		 4873 e++;
4874 }
4875}
4876
b726e493
FR		 4877static void rtl_disable_clock_request(struct pci_dev *pdev)
4878{
7d7903b2
JL		 4879 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
4880 PCI_EXP_LNKCTL_CLKREQ_EN);
b726e493
FR		 4881}
4882
e6de30d6 4883static void rtl_enable_clock_request(struct pci_dev *pdev)
4884{
7d7903b2
JL		 4885 pcie_capability_set_word(pdev, PCI_EXP_LNKCTL,
4886 PCI_EXP_LNKCTL_CLKREQ_EN);
e6de30d6 4887}
4888
b51ecea8 4889static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable)
4890{
4891 void __iomem *ioaddr = tp->mmio_addr;
4892 u8 data;
4893
4894 data = RTL_R8(Config3);
4895
4896 if (enable)
4897 data |= Rdy_to_L23;
4898 else
4899 data &= ~Rdy_to_L23;
4900
4901 RTL_W8(Config3, data);
4902}
4903
b726e493
FR		 4904#define R8168_CPCMD_QUIRK_MASK (\
4905 EnableBist | \
4906 Mac_dbgo_oe | \
4907 Force_half_dup | \
4908 Force_rxflow_en | \
4909 Force_txflow_en | \
4910 Cxpl_dbg_sel | \
4911 ASF | \
4912 PktCntrDisable | \
4913 Mac_dbgo_sel)
4914
beb1fe18 4915static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
219a1e9d 4916{
beb1fe18
HW		 4917 void __iomem *ioaddr = tp->mmio_addr;
4918 struct pci_dev *pdev = tp->pci_dev;
4919
b726e493
FR		 4920 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4921
4922 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4923
faf1e785 4924 if (tp->dev->mtu <= ETH_DATA_LEN) {
4925 rtl_tx_performance_tweak(pdev, (0x5 << MAX_READ_REQUEST_SHIFT) |
4926 PCI_EXP_DEVCTL_NOSNOOP_EN);
4927 }
219a1e9d
FR		 4928}
4929
beb1fe18 4930static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
219a1e9d 4931{
beb1fe18
HW		 4932 void __iomem *ioaddr = tp->mmio_addr;
4933
4934 rtl_hw_start_8168bb(tp);
b726e493 4935
f0298f81 4936 RTL_W8(MaxTxPacketSize, TxPacketMax);
b726e493
FR		 4937
4938 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
219a1e9d
FR		 4939}
4940
beb1fe18 4941static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
219a1e9d 4942{
beb1fe18
HW		 4943 void __iomem *ioaddr = tp->mmio_addr;
4944 struct pci_dev *pdev = tp->pci_dev;
4945
b726e493
FR		 4946 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4947
4948 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4949
faf1e785 4950 if (tp->dev->mtu <= ETH_DATA_LEN)
4951 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
b726e493
FR		 4952
4953 rtl_disable_clock_request(pdev);
4954
4955 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
219a1e9d
FR		 4956}
4957
beb1fe18 4958static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
219a1e9d 4959{
350f7596 4960 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 4961 { 0x01, 0, 0x0001 },
4962 { 0x02, 0x0800, 0x1000 },
4963 { 0x03, 0, 0x0042 },
4964 { 0x06, 0x0080, 0x0000 },
4965 { 0x07, 0, 0x2000 }
4966 };
4967
beb1fe18 4968 rtl_csi_access_enable_2(tp);
b726e493 4969
fdf6fc06 4970 rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
b726e493 4971
beb1fe18 4972 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 4973}
4974
beb1fe18 4975static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
ef3386f0 4976{
beb1fe18
HW		 4977 void __iomem *ioaddr = tp->mmio_addr;
4978 struct pci_dev *pdev = tp->pci_dev;
4979
4980 rtl_csi_access_enable_2(tp);
ef3386f0
FR		 4981
4982 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4983
faf1e785 4984 if (tp->dev->mtu <= ETH_DATA_LEN)
4985 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
ef3386f0
FR		 4986
4987 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4988}
4989
beb1fe18 4990static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
7f3e3d3a 4991{
beb1fe18
HW		 4992 void __iomem *ioaddr = tp->mmio_addr;
4993 struct pci_dev *pdev = tp->pci_dev;
4994
4995 rtl_csi_access_enable_2(tp);
7f3e3d3a
FR		 4996
4997 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4998
4999 /* Magic. */
5000 RTL_W8(DBG_REG, 0x20);
5001
f0298f81 5002 RTL_W8(MaxTxPacketSize, TxPacketMax);
7f3e3d3a 5003
faf1e785 5004 if (tp->dev->mtu <= ETH_DATA_LEN)
5005 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
7f3e3d3a
FR		 5006
5007 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5008}
5009
beb1fe18 5010static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
219a1e9d 5011{
beb1fe18 5012 void __iomem *ioaddr = tp->mmio_addr;
350f7596 5013 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 5014 { 0x02, 0x0800, 0x1000 },
5015 { 0x03, 0, 0x0002 },
5016 { 0x06, 0x0080, 0x0000 }
5017 };
5018
beb1fe18 5019 rtl_csi_access_enable_2(tp);
b726e493
FR		 5020
5021 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
5022
fdf6fc06 5023 rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
b726e493 5024
beb1fe18 5025 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 5026}
5027
beb1fe18 5028static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
219a1e9d 5029{
350f7596 5030 static const struct ephy_info e_info_8168c_2[] = {
b726e493
FR		 5031 { 0x01, 0, 0x0001 },
5032 { 0x03, 0x0400, 0x0220 }
5033 };
5034
beb1fe18 5035 rtl_csi_access_enable_2(tp);
b726e493 5036
fdf6fc06 5037 rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
b726e493 5038
beb1fe18 5039 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 5040}
5041
beb1fe18 5042static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
197ff761 5043{
beb1fe18 5044 rtl_hw_start_8168c_2(tp);
197ff761
FR		 5045}
5046
beb1fe18 5047static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
6fb07058 5048{
beb1fe18 5049 rtl_csi_access_enable_2(tp);
6fb07058 5050
beb1fe18 5051 __rtl_hw_start_8168cp(tp);
6fb07058
FR		 5052}
5053
beb1fe18 5054static void rtl_hw_start_8168d(struct rtl8169_private *tp)
5b538df9 5055{
beb1fe18
HW		 5056 void __iomem *ioaddr = tp->mmio_addr;
5057 struct pci_dev *pdev = tp->pci_dev;
5058
5059 rtl_csi_access_enable_2(tp);
5b538df9
FR		 5060
5061 rtl_disable_clock_request(pdev);
5062
f0298f81 5063 RTL_W8(MaxTxPacketSize, TxPacketMax);
5b538df9 5064
faf1e785 5065 if (tp->dev->mtu <= ETH_DATA_LEN)
5066 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5b538df9
FR		 5067
5068 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5069}
5070
beb1fe18 5071static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4804b3b3 5072{
beb1fe18
HW		 5073 void __iomem *ioaddr = tp->mmio_addr;
5074 struct pci_dev *pdev = tp->pci_dev;
5075
5076 rtl_csi_access_enable_1(tp);
4804b3b3 5077
faf1e785 5078 if (tp->dev->mtu <= ETH_DATA_LEN)
5079 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4804b3b3 5080
5081 RTL_W8(MaxTxPacketSize, TxPacketMax);
5082
5083 rtl_disable_clock_request(pdev);
5084}
5085
beb1fe18 5086static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
e6de30d6 5087{
beb1fe18
HW		 5088 void __iomem *ioaddr = tp->mmio_addr;
5089 struct pci_dev *pdev = tp->pci_dev;
e6de30d6 5090 static const struct ephy_info e_info_8168d_4[] = {
5091 { 0x0b, ~0, 0x48 },
5092 { 0x19, 0x20, 0x50 },
5093 { 0x0c, ~0, 0x20 }
5094 };
5095 int i;
5096
beb1fe18 5097 rtl_csi_access_enable_1(tp);
e6de30d6 5098
5099 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5100
5101 RTL_W8(MaxTxPacketSize, TxPacketMax);
5102
5103 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
5104 const struct ephy_info *e = e_info_8168d_4 + i;
5105 u16 w;
5106
fdf6fc06
FR		 5107 w = rtl_ephy_read(tp, e->offset);
5108 rtl_ephy_write(tp, 0x03, (w & e->mask) | e->bits);
e6de30d6 5109 }
5110
5111 rtl_enable_clock_request(pdev);
5112}
5113
beb1fe18 5114static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
01dc7fec 5115{
beb1fe18
HW		 5116 void __iomem *ioaddr = tp->mmio_addr;
5117 struct pci_dev *pdev = tp->pci_dev;
70090424 5118 static const struct ephy_info e_info_8168e_1[] = {
01dc7fec 5119 { 0x00, 0x0200, 0x0100 },
5120 { 0x00, 0x0000, 0x0004 },
5121 { 0x06, 0x0002, 0x0001 },
5122 { 0x06, 0x0000, 0x0030 },
5123 { 0x07, 0x0000, 0x2000 },
5124 { 0x00, 0x0000, 0x0020 },
5125 { 0x03, 0x5800, 0x2000 },
5126 { 0x03, 0x0000, 0x0001 },
5127 { 0x01, 0x0800, 0x1000 },
5128 { 0x07, 0x0000, 0x4000 },
5129 { 0x1e, 0x0000, 0x2000 },
5130 { 0x19, 0xffff, 0xfe6c },
5131 { 0x0a, 0x0000, 0x0040 }
5132 };
5133
beb1fe18 5134 rtl_csi_access_enable_2(tp);
01dc7fec 5135
fdf6fc06 5136 rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
01dc7fec 5137
faf1e785 5138 if (tp->dev->mtu <= ETH_DATA_LEN)
5139 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
01dc7fec 5140
5141 RTL_W8(MaxTxPacketSize, TxPacketMax);
5142
5143 rtl_disable_clock_request(pdev);
5144
5145 /* Reset tx FIFO pointer */
cecb5fd7
FR		 5146 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
5147 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
01dc7fec 5148
cecb5fd7 5149 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
01dc7fec 5150}
5151
beb1fe18 5152static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
70090424 5153{
beb1fe18
HW		 5154 void __iomem *ioaddr = tp->mmio_addr;
5155 struct pci_dev *pdev = tp->pci_dev;
70090424
HW		 5156 static const struct ephy_info e_info_8168e_2[] = {
5157 { 0x09, 0x0000, 0x0080 },
5158 { 0x19, 0x0000, 0x0224 }
5159 };
5160
beb1fe18 5161 rtl_csi_access_enable_1(tp);
70090424 5162
fdf6fc06 5163 rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
70090424 5164
faf1e785 5165 if (tp->dev->mtu <= ETH_DATA_LEN)
5166 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
70090424 5167
fdf6fc06
FR		 5168 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5169 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5170 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5171 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5172 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5173 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
5174 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5175 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
70090424 5176
3090bd9a 5177 RTL_W8(MaxTxPacketSize, EarlySize);
70090424 5178
4521e1a9
FR		 5179 rtl_disable_clock_request(pdev);
5180
70090424
HW		 5181 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5182 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5183
5184 /* Adjust EEE LED frequency */
5185 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5186
5187 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5188 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4521e1a9 5189 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
70090424
HW		 5190}
5191
5f886e08 5192static void rtl_hw_start_8168f(struct rtl8169_private *tp)
c2218925 5193{
beb1fe18
HW		 5194 void __iomem *ioaddr = tp->mmio_addr;
5195 struct pci_dev *pdev = tp->pci_dev;
c2218925 5196
5f886e08 5197 rtl_csi_access_enable_2(tp);
c2218925
HW		 5198
5199 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5200
fdf6fc06
FR		 5201 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5202 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5203 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5204 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5205 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5206 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5207 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5208 rtl_w1w0_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5209 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5210 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
c2218925
HW		 5211
5212 RTL_W8(MaxTxPacketSize, EarlySize);
5213
4521e1a9
FR		 5214 rtl_disable_clock_request(pdev);
5215
c2218925
HW		 5216 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5217 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
c2218925 5218 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4521e1a9
FR		 5219 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5220 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
c2218925
HW		 5221}
5222
5f886e08
HW		 5223static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5224{
5225 void __iomem *ioaddr = tp->mmio_addr;
5226 static const struct ephy_info e_info_8168f_1[] = {
5227 { 0x06, 0x00c0, 0x0020 },
5228 { 0x08, 0x0001, 0x0002 },
5229 { 0x09, 0x0000, 0x0080 },
5230 { 0x19, 0x0000, 0x0224 }
5231 };
5232
5233 rtl_hw_start_8168f(tp);
5234
fdf6fc06 5235 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5f886e08 5236
fdf6fc06 5237 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5f886e08
HW		 5238
5239 /* Adjust EEE LED frequency */
5240 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5241}
5242
b3d7b2f2
HW		 5243static void rtl_hw_start_8411(struct rtl8169_private *tp)
5244{
b3d7b2f2
HW		 5245 static const struct ephy_info e_info_8168f_1[] = {
5246 { 0x06, 0x00c0, 0x0020 },
5247 { 0x0f, 0xffff, 0x5200 },
5248 { 0x1e, 0x0000, 0x4000 },
5249 { 0x19, 0x0000, 0x0224 }
5250 };
5251
5252 rtl_hw_start_8168f(tp);
b51ecea8 5253 rtl_pcie_state_l2l3_enable(tp, false);
b3d7b2f2 5254
fdf6fc06 5255 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
b3d7b2f2 5256
fdf6fc06 5257 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
b3d7b2f2
HW		 5258}
5259
c558386b
HW		 5260static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5261{
5262 void __iomem *ioaddr = tp->mmio_addr;
5263 struct pci_dev *pdev = tp->pci_dev;
5264
beb330a4 5265 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5266
c558386b
HW		 5267 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
5268 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5269 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5270 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5271
5272 rtl_csi_access_enable_1(tp);
5273
5274 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5275
5276 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5277 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
beb330a4 5278 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
c558386b
HW		 5279
5280 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4521e1a9 5281 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
c558386b
HW		 5282 RTL_W8(MaxTxPacketSize, EarlySize);
5283
5284 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5285 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5286
5287 /* Adjust EEE LED frequency */
5288 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5289
beb330a4 5290 rtl_w1w0_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5291 rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
b51ecea8 5292
5293 rtl_pcie_state_l2l3_enable(tp, false);
c558386b
HW		 5294}
5295
57538c4a 5296static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
5297{
5298 void __iomem *ioaddr = tp->mmio_addr;
5299 static const struct ephy_info e_info_8168g_2[] = {
5300 { 0x00, 0x0000, 0x0008 },
5301 { 0x0c, 0x3df0, 0x0200 },
5302 { 0x19, 0xffff, 0xfc00 },
5303 { 0x1e, 0xffff, 0x20eb }
5304 };
5305
5306 rtl_hw_start_8168g_1(tp);
5307
5308 /* disable aspm and clock request before access ephy */
5309 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
5310 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
5311 rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
5312}
5313
45dd95c4 5314static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
5315{
5316 void __iomem *ioaddr = tp->mmio_addr;
5317 static const struct ephy_info e_info_8411_2[] = {
5318 { 0x00, 0x0000, 0x0008 },
5319 { 0x0c, 0x3df0, 0x0200 },
5320 { 0x0f, 0xffff, 0x5200 },
5321 { 0x19, 0x0020, 0x0000 },
5322 { 0x1e, 0x0000, 0x2000 }
5323 };
5324
5325 rtl_hw_start_8168g_1(tp);
5326
5327 /* disable aspm and clock request before access ephy */
5328 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
5329 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
5330 rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
5331}
5332
07ce4064
FR		 5333static void rtl_hw_start_8168(struct net_device *dev)
5334{
2dd99530
FR		 5335 struct rtl8169_private *tp = netdev_priv(dev);
5336 void __iomem *ioaddr = tp->mmio_addr;
5337
5338 RTL_W8(Cfg9346, Cfg9346_Unlock);
5339
f0298f81 5340 RTL_W8(MaxTxPacketSize, TxPacketMax);
2dd99530 5341
6f0333b8 5342 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
2dd99530 5343
0e485150 5344 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 5345
5346 RTL_W16(CPlusCmd, tp->cp_cmd);
5347
0e485150 5348 RTL_W16(IntrMitigate, 0x5151);
2dd99530 5349
0e485150 5350 /* Work around for RxFIFO overflow. */
811fd301 5351 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
da78dbff
FR		 5352 tp->event_slow |= RxFIFOOver | PCSTimeout;
5353 tp->event_slow &= ~RxOverflow;
0e485150
FR		 5354 }
5355
5356 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530 5357
1a964649 5358 rtl_set_rx_tx_config_registers(tp);
2dd99530
FR		 5359
5360 RTL_R8(IntrMask);
5361
219a1e9d
FR		 5362 switch (tp->mac_version) {
5363 case RTL_GIGA_MAC_VER_11:
beb1fe18 5364 rtl_hw_start_8168bb(tp);
4804b3b3 5365 break;
219a1e9d
FR		 5366
5367 case RTL_GIGA_MAC_VER_12:
5368 case RTL_GIGA_MAC_VER_17:
beb1fe18 5369 rtl_hw_start_8168bef(tp);
4804b3b3 5370 break;
219a1e9d
FR		 5371
5372 case RTL_GIGA_MAC_VER_18:
beb1fe18 5373 rtl_hw_start_8168cp_1(tp);
4804b3b3 5374 break;
219a1e9d
FR		 5375
5376 case RTL_GIGA_MAC_VER_19:
beb1fe18 5377 rtl_hw_start_8168c_1(tp);
4804b3b3 5378 break;
219a1e9d
FR		 5379
5380 case RTL_GIGA_MAC_VER_20:
beb1fe18 5381 rtl_hw_start_8168c_2(tp);
4804b3b3 5382 break;
219a1e9d 5383
197ff761 5384 case RTL_GIGA_MAC_VER_21:
beb1fe18 5385 rtl_hw_start_8168c_3(tp);
4804b3b3 5386 break;
197ff761 5387
6fb07058 5388 case RTL_GIGA_MAC_VER_22:
beb1fe18 5389 rtl_hw_start_8168c_4(tp);
4804b3b3 5390 break;
6fb07058 5391
ef3386f0 5392 case RTL_GIGA_MAC_VER_23:
beb1fe18 5393 rtl_hw_start_8168cp_2(tp);
4804b3b3 5394 break;
ef3386f0 5395
7f3e3d3a 5396 case RTL_GIGA_MAC_VER_24:
beb1fe18 5397 rtl_hw_start_8168cp_3(tp);
4804b3b3 5398 break;
7f3e3d3a 5399
5b538df9 5400 case RTL_GIGA_MAC_VER_25:
daf9df6d 5401 case RTL_GIGA_MAC_VER_26:
5402 case RTL_GIGA_MAC_VER_27:
beb1fe18 5403 rtl_hw_start_8168d(tp);
4804b3b3 5404 break;
5b538df9 5405
e6de30d6 5406 case RTL_GIGA_MAC_VER_28:
beb1fe18 5407 rtl_hw_start_8168d_4(tp);
4804b3b3 5408 break;
cecb5fd7 5409
4804b3b3 5410 case RTL_GIGA_MAC_VER_31:
beb1fe18 5411 rtl_hw_start_8168dp(tp);
4804b3b3 5412 break;
5413
01dc7fec 5414 case RTL_GIGA_MAC_VER_32:
5415 case RTL_GIGA_MAC_VER_33:
beb1fe18 5416 rtl_hw_start_8168e_1(tp);
70090424
HW		 5417 break;
5418 case RTL_GIGA_MAC_VER_34:
beb1fe18 5419 rtl_hw_start_8168e_2(tp);
01dc7fec 5420 break;
e6de30d6 5421
c2218925
HW		 5422 case RTL_GIGA_MAC_VER_35:
5423 case RTL_GIGA_MAC_VER_36:
beb1fe18 5424 rtl_hw_start_8168f_1(tp);
c2218925
HW		 5425 break;
5426
b3d7b2f2
HW		 5427 case RTL_GIGA_MAC_VER_38:
5428 rtl_hw_start_8411(tp);
5429 break;
5430
c558386b
HW		 5431 case RTL_GIGA_MAC_VER_40:
5432 case RTL_GIGA_MAC_VER_41:
5433 rtl_hw_start_8168g_1(tp);
5434 break;
57538c4a 5435 case RTL_GIGA_MAC_VER_42:
5436 rtl_hw_start_8168g_2(tp);
5437 break;
c558386b 5438
45dd95c4 5439 case RTL_GIGA_MAC_VER_44:
5440 rtl_hw_start_8411_2(tp);
5441 break;
5442
219a1e9d
FR		 5443 default:
5444 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
5445 dev->name, tp->mac_version);
4804b3b3 5446 break;
219a1e9d 5447 }
2dd99530 5448
1a964649 5449 RTL_W8(Cfg9346, Cfg9346_Lock);
5450
0e485150
FR		 5451 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5452
1a964649 5453 rtl_set_rx_mode(dev);
b8363901 5454
2dd99530 5455 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
07ce4064 5456}
1da177e4 5457
2857ffb7
FR		 5458#define R810X_CPCMD_QUIRK_MASK (\
5459 EnableBist | \
5460 Mac_dbgo_oe | \
5461 Force_half_dup | \
5edcc537 5462 Force_rxflow_en | \
2857ffb7
FR		 5463 Force_txflow_en | \
5464 Cxpl_dbg_sel | \
5465 ASF | \
5466 PktCntrDisable | \
d24e9aaf 5467 Mac_dbgo_sel)
2857ffb7 5468
beb1fe18 5469static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
2857ffb7 5470{
beb1fe18
HW		 5471 void __iomem *ioaddr = tp->mmio_addr;
5472 struct pci_dev *pdev = tp->pci_dev;
350f7596 5473 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 5474 { 0x01, 0, 0x6e65 },
5475 { 0x02, 0, 0x091f },
5476 { 0x03, 0, 0xc2f9 },
5477 { 0x06, 0, 0xafb5 },
5478 { 0x07, 0, 0x0e00 },
5479 { 0x19, 0, 0xec80 },
5480 { 0x01, 0, 0x2e65 },
5481 { 0x01, 0, 0x6e65 }
5482 };
5483 u8 cfg1;
5484
beb1fe18 5485 rtl_csi_access_enable_2(tp);
2857ffb7
FR		 5486
5487 RTL_W8(DBG_REG, FIX_NAK_1);
5488
5489 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5490
5491 RTL_W8(Config1,
5492 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5493 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5494
5495 cfg1 = RTL_R8(Config1);
5496 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5497 RTL_W8(Config1, cfg1 & ~LEDS0);
5498
fdf6fc06 5499 rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
2857ffb7
FR		 5500}
5501
beb1fe18 5502static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
2857ffb7 5503{
beb1fe18
HW		 5504 void __iomem *ioaddr = tp->mmio_addr;
5505 struct pci_dev *pdev = tp->pci_dev;
5506
5507 rtl_csi_access_enable_2(tp);
2857ffb7
FR		 5508
5509 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5510
5511 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
5512 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2857ffb7
FR		 5513}
5514
beb1fe18 5515static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
2857ffb7 5516{
beb1fe18 5517 rtl_hw_start_8102e_2(tp);
2857ffb7 5518
fdf6fc06 5519 rtl_ephy_write(tp, 0x03, 0xc2f9);
2857ffb7
FR		 5520}
5521
beb1fe18 5522static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5a5e4443 5523{
beb1fe18 5524 void __iomem *ioaddr = tp->mmio_addr;
5a5e4443
HW		 5525 static const struct ephy_info e_info_8105e_1[] = {
5526 { 0x07, 0, 0x4000 },
5527 { 0x19, 0, 0x0200 },
5528 { 0x19, 0, 0x0020 },
5529 { 0x1e, 0, 0x2000 },
5530 { 0x03, 0, 0x0001 },
5531 { 0x19, 0, 0x0100 },
5532 { 0x19, 0, 0x0004 },
5533 { 0x0a, 0, 0x0020 }
5534 };
5535
cecb5fd7 5536 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5a5e4443
HW		 5537 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5538
cecb5fd7 5539 /* Disable Early Tally Counter */
5a5e4443
HW		 5540 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
5541
5542 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4f6b00e5 5543 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5a5e4443 5544
fdf6fc06 5545 rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
b51ecea8 5546
5547 rtl_pcie_state_l2l3_enable(tp, false);
5a5e4443
HW		 5548}
5549
beb1fe18 5550static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5a5e4443 5551{
beb1fe18 5552 rtl_hw_start_8105e_1(tp);
fdf6fc06 5553 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5a5e4443
HW		 5554}
5555
7e18dca1
HW		 5556static void rtl_hw_start_8402(struct rtl8169_private *tp)
5557{
5558 void __iomem *ioaddr = tp->mmio_addr;
5559 static const struct ephy_info e_info_8402[] = {
5560 { 0x19, 0xffff, 0xff64 },
5561 { 0x1e, 0, 0x4000 }
5562 };
5563
5564 rtl_csi_access_enable_2(tp);
5565
5566 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5567 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5568
5569 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5570 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5571
fdf6fc06 5572 rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
7e18dca1
HW		 5573
5574 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
5575
fdf6fc06
FR		 5576 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
5577 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
5578 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5579 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5580 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5581 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5582 rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
b51ecea8 5583
5584 rtl_pcie_state_l2l3_enable(tp, false);
7e18dca1
HW		 5585}
5586
5598bfe5
HW		 5587static void rtl_hw_start_8106(struct rtl8169_private *tp)
5588{
5589 void __iomem *ioaddr = tp->mmio_addr;
5590
5591 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5592 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5593
4521e1a9 5594 RTL_W32(MISC, (RTL_R32(MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5598bfe5
HW		 5595 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
5596 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
b51ecea8 5597
5598 rtl_pcie_state_l2l3_enable(tp, false);
5598bfe5
HW		 5599}
5600
07ce4064
FR		 5601static void rtl_hw_start_8101(struct net_device *dev)
5602{
cdf1a608
FR		 5603 struct rtl8169_private *tp = netdev_priv(dev);
5604 void __iomem *ioaddr = tp->mmio_addr;
5605 struct pci_dev *pdev = tp->pci_dev;
5606
da78dbff
FR		 5607 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5608 tp->event_slow &= ~RxFIFOOver;
811fd301 5609
cecb5fd7 5610 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
7d7903b2 5611 tp->mac_version == RTL_GIGA_MAC_VER_16)
8200bc72
BH		 5612 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL,
5613 PCI_EXP_DEVCTL_NOSNOOP_EN);
cdf1a608 5614
d24e9aaf
HW		 5615 RTL_W8(Cfg9346, Cfg9346_Unlock);
5616
1a964649 5617 RTL_W8(MaxTxPacketSize, TxPacketMax);
5618
5619 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
5620
5621 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
5622 RTL_W16(CPlusCmd, tp->cp_cmd);
5623
5624 rtl_set_rx_tx_desc_registers(tp, ioaddr);
5625
5626 rtl_set_rx_tx_config_registers(tp);
5627
2857ffb7
FR		 5628 switch (tp->mac_version) {
5629 case RTL_GIGA_MAC_VER_07:
beb1fe18 5630 rtl_hw_start_8102e_1(tp);
2857ffb7
FR		 5631 break;
5632
5633 case RTL_GIGA_MAC_VER_08:
beb1fe18 5634 rtl_hw_start_8102e_3(tp);
2857ffb7
FR		 5635 break;
5636
5637 case RTL_GIGA_MAC_VER_09:
beb1fe18 5638 rtl_hw_start_8102e_2(tp);
2857ffb7 5639 break;
5a5e4443
HW		 5640
5641 case RTL_GIGA_MAC_VER_29:
beb1fe18 5642 rtl_hw_start_8105e_1(tp);
5a5e4443
HW		 5643 break;
5644 case RTL_GIGA_MAC_VER_30:
beb1fe18 5645 rtl_hw_start_8105e_2(tp);
5a5e4443 5646 break;
7e18dca1
HW		 5647
5648 case RTL_GIGA_MAC_VER_37:
5649 rtl_hw_start_8402(tp);
5650 break;
5598bfe5
HW		 5651
5652 case RTL_GIGA_MAC_VER_39:
5653 rtl_hw_start_8106(tp);
5654 break;
58152cd4 5655 case RTL_GIGA_MAC_VER_43:
5656 rtl_hw_start_8168g_2(tp);
5657 break;
cdf1a608
FR		 5658 }
5659
d24e9aaf 5660 RTL_W8(Cfg9346, Cfg9346_Lock);
cdf1a608 5661
cdf1a608
FR		 5662 RTL_W16(IntrMitigate, 0x0000);
5663
cdf1a608 5664 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
cdf1a608 5665
cdf1a608
FR		 5666 rtl_set_rx_mode(dev);
5667
1a964649 5668 RTL_R8(IntrMask);
5669
cdf1a608 5670 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
1da177e4
LT		 5671}
5672
5673static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5674{
d58d46b5
FR		 5675 struct rtl8169_private *tp = netdev_priv(dev);
5676
5677 if (new_mtu < ETH_ZLEN ||
5678 new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
1da177e4
LT		 5679 return -EINVAL;
5680
d58d46b5
FR		 5681 if (new_mtu > ETH_DATA_LEN)
5682 rtl_hw_jumbo_enable(tp);
5683 else
5684 rtl_hw_jumbo_disable(tp);
5685
1da177e4 5686 dev->mtu = new_mtu;
350fb32a
MM		 5687 netdev_update_features(dev);
5688
323bb685 5689 return 0;
1da177e4
LT		 5690}
5691
5692static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5693{
95e0918d 5694 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 5695 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5696}
5697
6f0333b8
ED		 5698static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5699 void **data_buff, struct RxDesc *desc)
1da177e4 5700{
48addcc9 5701 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
231aee63 5702 DMA_FROM_DEVICE);
48addcc9 5703
6f0333b8
ED		 5704 kfree(*data_buff);
5705 *data_buff = NULL;
1da177e4
LT		 5706 rtl8169_make_unusable_by_asic(desc);
5707}
5708
5709static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
5710{
5711 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5712
5713 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
5714}
5715
5716static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
5717 u32 rx_buf_sz)
5718{
5719 desc->addr = cpu_to_le64(mapping);
5720 wmb();
5721 rtl8169_mark_to_asic(desc, rx_buf_sz);
5722}
5723
6f0333b8
ED		 5724static inline void *rtl8169_align(void *data)
5725{
5726 return (void *)ALIGN((long)data, 16);
5727}
5728
0ecbe1ca
SG		 5729static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5730 struct RxDesc *desc)
1da177e4 5731{
6f0333b8 5732 void *data;
1da177e4 5733 dma_addr_t mapping;
48addcc9 5734 struct device *d = &tp->pci_dev->dev;
0ecbe1ca 5735 struct net_device *dev = tp->dev;
6f0333b8 5736 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
1da177e4 5737
6f0333b8
ED		 5738 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
5739 if (!data)
5740 return NULL;
e9f63f30 5741
6f0333b8
ED		 5742 if (rtl8169_align(data) != data) {
5743 kfree(data);
5744 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
5745 if (!data)
5746 return NULL;
5747 }
3eafe507 5748
48addcc9 5749 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
231aee63 5750 DMA_FROM_DEVICE);
d827d86b
SG		 5751 if (unlikely(dma_mapping_error(d, mapping))) {
5752 if (net_ratelimit())
5753 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
3eafe507 5754 goto err_out;
d827d86b 5755 }
1da177e4
LT		 5756
5757 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6f0333b8 5758 return data;
3eafe507
SG		 5759
5760err_out:
5761 kfree(data);
5762 return NULL;
1da177e4
LT		 5763}
5764
5765static void rtl8169_rx_clear(struct rtl8169_private *tp)
5766{
07d3f51f 5767 unsigned int i;
1da177e4
LT		 5768
5769 for (i = 0; i < NUM_RX_DESC; i++) {
6f0333b8
ED		 5770 if (tp->Rx_databuff[i]) {
5771 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
1da177e4
LT		 5772 tp->RxDescArray + i);
5773 }
5774 }
5775}
5776
0ecbe1ca 5777static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1da177e4 5778{
0ecbe1ca
SG		 5779 desc->opts1 |= cpu_to_le32(RingEnd);
5780}
5b0384f4 5781
0ecbe1ca
SG		 5782static int rtl8169_rx_fill(struct rtl8169_private *tp)
5783{
5784 unsigned int i;
1da177e4 5785
0ecbe1ca
SG		 5786 for (i = 0; i < NUM_RX_DESC; i++) {
5787 void *data;
4ae47c2d 5788
6f0333b8 5789 if (tp->Rx_databuff[i])
1da177e4 5790 continue;
bcf0bf90 5791
0ecbe1ca 5792 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6f0333b8
ED		 5793 if (!data) {
5794 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
0ecbe1ca 5795 goto err_out;
6f0333b8
ED		 5796 }
5797 tp->Rx_databuff[i] = data;
1da177e4 5798 }
1da177e4 5799
0ecbe1ca
SG		 5800 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5801 return 0;
5802
5803err_out:
5804 rtl8169_rx_clear(tp);
5805 return -ENOMEM;
1da177e4
LT		 5806}
5807
1da177e4
LT		 5808static int rtl8169_init_ring(struct net_device *dev)
5809{
5810 struct rtl8169_private *tp = netdev_priv(dev);
5811
5812 rtl8169_init_ring_indexes(tp);
5813
5814 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
6f0333b8 5815 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
1da177e4 5816
0ecbe1ca 5817 return rtl8169_rx_fill(tp);
1da177e4
LT		 5818}
5819
48addcc9 5820static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
1da177e4
LT		 5821 struct TxDesc *desc)
5822{
5823 unsigned int len = tx_skb->len;
5824
48addcc9
SG		 5825 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5826
1da177e4
LT		 5827 desc->opts1 = 0x00;
5828 desc->opts2 = 0x00;
5829 desc->addr = 0x00;
5830 tx_skb->len = 0;
5831}
5832
3eafe507
SG		 5833static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5834 unsigned int n)
1da177e4
LT		 5835{
5836 unsigned int i;
5837
3eafe507
SG		 5838 for (i = 0; i < n; i++) {
5839 unsigned int entry = (start + i) % NUM_TX_DESC;
1da177e4
LT		 5840 struct ring_info *tx_skb = tp->tx_skb + entry;
5841 unsigned int len = tx_skb->len;
5842
5843 if (len) {
5844 struct sk_buff *skb = tx_skb->skb;
5845
48addcc9 5846 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
1da177e4
LT		 5847 tp->TxDescArray + entry);
5848 if (skb) {
cac4b22f 5849 tp->dev->stats.tx_dropped++;
989c9ba1 5850 dev_kfree_skb_any(skb);
1da177e4
LT		 5851 tx_skb->skb = NULL;
5852 }
1da177e4
LT		 5853 }
5854 }
3eafe507
SG		 5855}
5856
5857static void rtl8169_tx_clear(struct rtl8169_private *tp)
5858{
5859 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
1da177e4
LT		 5860 tp->cur_tx = tp->dirty_tx = 0;
5861}
5862
4422bcd4 5863static void rtl_reset_work(struct rtl8169_private *tp)
1da177e4 5864{
c4028958 5865 struct net_device *dev = tp->dev;
56de414c 5866 int i;
1da177e4 5867
da78dbff
FR		 5868 napi_disable(&tp->napi);
5869 netif_stop_queue(dev);
5870 synchronize_sched();
1da177e4 5871
c7c2c39b 5872 rtl8169_hw_reset(tp);
5873
56de414c
FR		 5874 for (i = 0; i < NUM_RX_DESC; i++)
5875 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
5876
1da177e4 5877 rtl8169_tx_clear(tp);
c7c2c39b 5878 rtl8169_init_ring_indexes(tp);
1da177e4 5879
da78dbff 5880 napi_enable(&tp->napi);
56de414c
FR		 5881 rtl_hw_start(dev);
5882 netif_wake_queue(dev);
5883 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1da177e4
LT		 5884}
5885
5886static void rtl8169_tx_timeout(struct net_device *dev)
5887{
da78dbff
FR		 5888 struct rtl8169_private *tp = netdev_priv(dev);
5889
5890 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 5891}
5892
5893static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2b7b4318 5894 u32 *opts)
1da177e4
LT		 5895{
5896 struct skb_shared_info *info = skb_shinfo(skb);
5897 unsigned int cur_frag, entry;
a6343afb 5898 struct TxDesc * uninitialized_var(txd);
48addcc9 5899 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 5900
5901 entry = tp->cur_tx;
5902 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
9e903e08 5903 const skb_frag_t *frag = info->frags + cur_frag;
1da177e4
LT		 5904 dma_addr_t mapping;
5905 u32 status, len;
5906 void *addr;
5907
5908 entry = (entry + 1) % NUM_TX_DESC;
5909
5910 txd = tp->TxDescArray + entry;
9e903e08 5911 len = skb_frag_size(frag);
929f6189 5912 addr = skb_frag_address(frag);
48addcc9 5913 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
d827d86b
SG		 5914 if (unlikely(dma_mapping_error(d, mapping))) {
5915 if (net_ratelimit())
5916 netif_err(tp, drv, tp->dev,
5917 "Failed to map TX fragments DMA!\n");
3eafe507 5918 goto err_out;
d827d86b 5919 }
1da177e4 5920
cecb5fd7 5921 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318
FR		 5922 status = opts[0] | len |
5923 (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 5924
5925 txd->opts1 = cpu_to_le32(status);
2b7b4318 5926 txd->opts2 = cpu_to_le32(opts[1]);
1da177e4
LT		 5927 txd->addr = cpu_to_le64(mapping);
5928
5929 tp->tx_skb[entry].len = len;
5930 }
5931
5932 if (cur_frag) {
5933 tp->tx_skb[entry].skb = skb;
5934 txd->opts1 |= cpu_to_le32(LastFrag);
5935 }
5936
5937 return cur_frag;
3eafe507
SG		 5938
5939err_out:
5940 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5941 return -EIO;
1da177e4
LT		 5942}
5943
b423e9ae 5944static bool rtl_skb_pad(struct sk_buff *skb)
5945{
5946 if (skb_padto(skb, ETH_ZLEN))
5947 return false;
5948 skb_put(skb, ETH_ZLEN - skb->len);
5949 return true;
5950}
5951
5952static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
5953{
5954 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
5955}
5956
e974604b 5957static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5958 struct net_device *dev);
5959/* r8169_csum_workaround()
5960 * The hw limites the value the transport offset. When the offset is out of the
5961 * range, calculate the checksum by sw.
5962 */
5963static void r8169_csum_workaround(struct rtl8169_private *tp,
5964 struct sk_buff *skb)
5965{
5966 if (skb_shinfo(skb)->gso_size) {
5967 netdev_features_t features = tp->dev->features;
5968 struct sk_buff *segs, *nskb;
5969
5970 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
5971 segs = skb_gso_segment(skb, features);
5972 if (IS_ERR(segs) || !segs)
5973 goto drop;
5974
5975 do {
5976 nskb = segs;
5977 segs = segs->next;
5978 nskb->next = NULL;
5979 rtl8169_start_xmit(nskb, tp->dev);
5980 } while (segs);
5981
5982 dev_kfree_skb(skb);
5983 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5984 if (skb_checksum_help(skb) < 0)
5985 goto drop;
5986
5987 rtl8169_start_xmit(skb, tp->dev);
5988 } else {
5989 struct net_device_stats *stats;
5990
5991drop:
5992 stats = &tp->dev->stats;
5993 stats->tx_dropped++;
5994 dev_kfree_skb(skb);
5995 }
5996}
5997
5998/* msdn_giant_send_check()
5999 * According to the document of microsoft, the TCP Pseudo Header excludes the
6000 * packet length for IPv6 TCP large packets.
6001 */
6002static int msdn_giant_send_check(struct sk_buff *skb)
6003{
6004 const struct ipv6hdr *ipv6h;
6005 struct tcphdr *th;
6006 int ret;
6007
6008 ret = skb_cow_head(skb, 0);
6009 if (ret)
6010 return ret;
6011
6012 ipv6h = ipv6_hdr(skb);
6013 th = tcp_hdr(skb);
6014
6015 th->check = 0;
6016 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
6017
6018 return ret;
6019}
6020
6021static inline __be16 get_protocol(struct sk_buff *skb)
6022{
6023 __be16 protocol;
6024
6025 if (skb->protocol == htons(ETH_P_8021Q))
6026 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
6027 else
6028 protocol = skb->protocol;
6029
6030 return protocol;
6031}
6032
5888d3fc 6033static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
6034 struct sk_buff *skb, u32 *opts)
1da177e4 6035{
350fb32a
MM		 6036 u32 mss = skb_shinfo(skb)->gso_size;
6037
2b7b4318
FR		 6038 if (mss) {
6039 opts[0] |= TD_LSO;
5888d3fc 6040 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
6041 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6042 const struct iphdr *ip = ip_hdr(skb);
6043
6044 if (ip->protocol == IPPROTO_TCP)
6045 opts[0] |= TD0_IP_CS | TD0_TCP_CS;
6046 else if (ip->protocol == IPPROTO_UDP)
6047 opts[0] |= TD0_IP_CS | TD0_UDP_CS;
6048 else
6049 WARN_ON_ONCE(1);
6050 }
6051
6052 return true;
6053}
6054
6055static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
6056 struct sk_buff *skb, u32 *opts)
6057{
bdfa4ed6 6058 u32 transport_offset = (u32)skb_transport_offset(skb);
5888d3fc 6059 u32 mss = skb_shinfo(skb)->gso_size;
6060
6061 if (mss) {
e974604b 6062 if (transport_offset > GTTCPHO_MAX) {
6063 netif_warn(tp, tx_err, tp->dev,
6064 "Invalid transport offset 0x%x for TSO\n",
6065 transport_offset);
6066 return false;
6067 }
6068
6069 switch (get_protocol(skb)) {
6070 case htons(ETH_P_IP):
6071 opts[0] |= TD1_GTSENV4;
6072 break;
6073
6074 case htons(ETH_P_IPV6):
6075 if (msdn_giant_send_check(skb))
6076 return false;
6077
6078 opts[0] |= TD1_GTSENV6;
6079 break;
6080
6081 default:
6082 WARN_ON_ONCE(1);
6083 break;
6084 }
6085
bdfa4ed6 6086 opts[0] |= transport_offset << GTTCPHO_SHIFT;
5888d3fc 6087 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
2b7b4318 6088 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
e974604b 6089 u8 ip_protocol;
1da177e4 6090
b423e9ae 6091 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
6092 return skb_checksum_help(skb) == 0 && rtl_skb_pad(skb);
6093
e974604b 6094 if (transport_offset > TCPHO_MAX) {
6095 netif_warn(tp, tx_err, tp->dev,
6096 "Invalid transport offset 0x%x\n",
6097 transport_offset);
6098 return false;
6099 }
6100
6101 switch (get_protocol(skb)) {
6102 case htons(ETH_P_IP):
6103 opts[1] |= TD1_IPv4_CS;
6104 ip_protocol = ip_hdr(skb)->protocol;
6105 break;
6106
6107 case htons(ETH_P_IPV6):
6108 opts[1] |= TD1_IPv6_CS;
6109 ip_protocol = ipv6_hdr(skb)->nexthdr;
6110 break;
6111
6112 default:
6113 ip_protocol = IPPROTO_RAW;
6114 break;
6115 }
6116
6117 if (ip_protocol == IPPROTO_TCP)
6118 opts[1] |= TD1_TCP_CS;
6119 else if (ip_protocol == IPPROTO_UDP)
6120 opts[1] |= TD1_UDP_CS;
2b7b4318
FR		 6121 else
6122 WARN_ON_ONCE(1);
e974604b 6123
6124 opts[1] |= transport_offset << TCPHO_SHIFT;
b423e9ae 6125 } else {
6126 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
6127 return rtl_skb_pad(skb);
1da177e4 6128 }
5888d3fc 6129
b423e9ae 6130 return true;
1da177e4
LT		 6131}
6132
61357325
SH		 6133static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6134 struct net_device *dev)
1da177e4
LT		 6135{
6136 struct rtl8169_private *tp = netdev_priv(dev);
3eafe507 6137 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
1da177e4
LT		 6138 struct TxDesc *txd = tp->TxDescArray + entry;
6139 void __iomem *ioaddr = tp->mmio_addr;
48addcc9 6140 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 6141 dma_addr_t mapping;
6142 u32 status, len;
2b7b4318 6143 u32 opts[2];
3eafe507 6144 int frags;
5b0384f4 6145
477206a0 6146 if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
bf82c189 6147 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
3eafe507 6148 goto err_stop_0;
1da177e4
LT		 6149 }
6150
6151 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3eafe507
SG		 6152 goto err_stop_0;
6153
b423e9ae 6154 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
6155 opts[0] = DescOwn;
6156
e974604b 6157 if (!tp->tso_csum(tp, skb, opts)) {
6158 r8169_csum_workaround(tp, skb);
6159 return NETDEV_TX_OK;
6160 }
b423e9ae 6161
3eafe507 6162 len = skb_headlen(skb);
48addcc9 6163 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
d827d86b
SG		 6164 if (unlikely(dma_mapping_error(d, mapping))) {
6165 if (net_ratelimit())
6166 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
3eafe507 6167 goto err_dma_0;
d827d86b 6168 }
3eafe507
SG		 6169
6170 tp->tx_skb[entry].len = len;
6171 txd->addr = cpu_to_le64(mapping);
1da177e4 6172
2b7b4318 6173 frags = rtl8169_xmit_frags(tp, skb, opts);
3eafe507
SG		 6174 if (frags < 0)
6175 goto err_dma_1;
6176 else if (frags)
2b7b4318 6177 opts[0] |= FirstFrag;
3eafe507 6178 else {
2b7b4318 6179 opts[0] |= FirstFrag | LastFrag;
1da177e4
LT		 6180 tp->tx_skb[entry].skb = skb;
6181 }
6182
2b7b4318
FR		 6183 txd->opts2 = cpu_to_le32(opts[1]);
6184
5047fb5d
RC		 6185 skb_tx_timestamp(skb);
6186
1da177e4
LT		 6187 wmb();
6188
cecb5fd7 6189 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318 6190 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 6191 txd->opts1 = cpu_to_le32(status);
6192
1da177e4
LT		 6193 tp->cur_tx += frags + 1;
6194
4c020a96 6195 wmb();
1da177e4 6196
cecb5fd7 6197 RTL_W8(TxPoll, NPQ);
1da177e4 6198
da78dbff
FR		 6199 mmiowb();
6200
477206a0 6201 if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
ae1f23fb
FR		 6202 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
6203 * not miss a ring update when it notices a stopped queue.
6204 */
6205 smp_wmb();
1da177e4 6206 netif_stop_queue(dev);
ae1f23fb
FR		 6207 /* Sync with rtl_tx:
6208 * - publish queue status and cur_tx ring index (write barrier)
6209 * - refresh dirty_tx ring index (read barrier).
6210 * May the current thread have a pessimistic view of the ring
6211 * status and forget to wake up queue, a racing rtl_tx thread
6212 * can't.
6213 */
1e874e04 6214 smp_mb();
477206a0 6215 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
1da177e4
LT		 6216 netif_wake_queue(dev);
6217 }
6218
61357325 6219 return NETDEV_TX_OK;
1da177e4 6220
3eafe507 6221err_dma_1:
48addcc9 6222 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
3eafe507 6223err_dma_0:
989c9ba1 6224 dev_kfree_skb_any(skb);
3eafe507
SG		 6225 dev->stats.tx_dropped++;
6226 return NETDEV_TX_OK;
6227
6228err_stop_0:
1da177e4 6229 netif_stop_queue(dev);
cebf8cc7 6230 dev->stats.tx_dropped++;
61357325 6231 return NETDEV_TX_BUSY;
1da177e4
LT		 6232}
6233
6234static void rtl8169_pcierr_interrupt(struct net_device *dev)
6235{
6236 struct rtl8169_private *tp = netdev_priv(dev);
6237 struct pci_dev *pdev = tp->pci_dev;
1da177e4
LT		 6238 u16 pci_status, pci_cmd;
6239
6240 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
6241 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
6242
bf82c189
JP		 6243 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
6244 pci_cmd, pci_status);
1da177e4
LT		 6245
6246 /*
6247 * The recovery sequence below admits a very elaborated explanation:
6248 * - it seems to work;
d03902b8
FR		 6249 * - I did not see what else could be done;
6250 * - it makes iop3xx happy.
1da177e4
LT		 6251 *
6252 * Feel free to adjust to your needs.
6253 */
a27993f3 6254 if (pdev->broken_parity_status)
d03902b8
FR		 6255 pci_cmd &= ~PCI_COMMAND_PARITY;
6256 else
6257 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
6258
6259 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 6260
6261 pci_write_config_word(pdev, PCI_STATUS,
6262 pci_status & (PCI_STATUS_DETECTED_PARITY |
6263 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
6264 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
6265
6266 /* The infamous DAC f*ckup only happens at boot time */
9fba0812 6267 if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
e6de30d6 6268 void __iomem *ioaddr = tp->mmio_addr;
6269
bf82c189 6270 netif_info(tp, intr, dev, "disabling PCI DAC\n");
1da177e4
LT		 6271 tp->cp_cmd &= ~PCIDAC;
6272 RTL_W16(CPlusCmd, tp->cp_cmd);
6273 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 6274 }
6275
e6de30d6 6276 rtl8169_hw_reset(tp);
d03902b8 6277
98ddf986 6278 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 6279}
6280
da78dbff 6281static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
1da177e4
LT		 6282{
6283 unsigned int dirty_tx, tx_left;
6284
1da177e4
LT		 6285 dirty_tx = tp->dirty_tx;
6286 smp_rmb();
6287 tx_left = tp->cur_tx - dirty_tx;
6288
6289 while (tx_left > 0) {
6290 unsigned int entry = dirty_tx % NUM_TX_DESC;
6291 struct ring_info *tx_skb = tp->tx_skb + entry;
1da177e4
LT		 6292 u32 status;
6293
6294 rmb();
6295 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
6296 if (status & DescOwn)
6297 break;
6298
48addcc9
SG		 6299 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
6300 tp->TxDescArray + entry);
1da177e4 6301 if (status & LastFrag) {
17bcb684
FR		 6302 u64_stats_update_begin(&tp->tx_stats.syncp);
6303 tp->tx_stats.packets++;
6304 tp->tx_stats.bytes += tx_skb->skb->len;
6305 u64_stats_update_end(&tp->tx_stats.syncp);
989c9ba1 6306 dev_kfree_skb_any(tx_skb->skb);
1da177e4
LT		 6307 tx_skb->skb = NULL;
6308 }
6309 dirty_tx++;
6310 tx_left--;
6311 }
6312
6313 if (tp->dirty_tx != dirty_tx) {
6314 tp->dirty_tx = dirty_tx;
ae1f23fb
FR		 6315 /* Sync with rtl8169_start_xmit:
6316 * - publish dirty_tx ring index (write barrier)
6317 * - refresh cur_tx ring index and queue status (read barrier)
6318 * May the current thread miss the stopped queue condition,
6319 * a racing xmit thread can only have a right view of the
6320 * ring status.
6321 */
1e874e04 6322 smp_mb();
1da177e4 6323 if (netif_queue_stopped(dev) &&
477206a0 6324 TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
1da177e4
LT		 6325 netif_wake_queue(dev);
6326 }
d78ae2dc
FR		 6327 /*
6328 * 8168 hack: TxPoll requests are lost when the Tx packets are
6329 * too close. Let's kick an extra TxPoll request when a burst
6330 * of start_xmit activity is detected (if it is not detected,
6331 * it is slow enough). -- FR
6332 */
da78dbff
FR		 6333 if (tp->cur_tx != dirty_tx) {
6334 void __iomem *ioaddr = tp->mmio_addr;
6335
d78ae2dc 6336 RTL_W8(TxPoll, NPQ);
da78dbff 6337 }
1da177e4
LT		 6338 }
6339}
6340
126fa4b9
FR		 6341static inline int rtl8169_fragmented_frame(u32 status)
6342{
6343 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
6344}
6345
adea1ac7 6346static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
1da177e4 6347{
1da177e4
LT		 6348 u32 status = opts1 & RxProtoMask;
6349
6350 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
d5d3ebe3 6351 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
1da177e4
LT		 6352 skb->ip_summed = CHECKSUM_UNNECESSARY;
6353 else
bc8acf2c 6354 skb_checksum_none_assert(skb);
1da177e4
LT		 6355}
6356
6f0333b8
ED		 6357static struct sk_buff *rtl8169_try_rx_copy(void *data,
6358 struct rtl8169_private *tp,
6359 int pkt_size,
6360 dma_addr_t addr)
1da177e4 6361{
b449655f 6362 struct sk_buff *skb;
48addcc9 6363 struct device *d = &tp->pci_dev->dev;
b449655f 6364
6f0333b8 6365 data = rtl8169_align(data);
48addcc9 6366 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6f0333b8
ED		 6367 prefetch(data);
6368 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
6369 if (skb)
6370 memcpy(skb->data, data, pkt_size);
48addcc9
SG		 6371 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
6372
6f0333b8 6373 return skb;
1da177e4
LT		 6374}
6375
da78dbff 6376static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
1da177e4
LT		 6377{
6378 unsigned int cur_rx, rx_left;
6f0333b8 6379 unsigned int count;
1da177e4 6380
1da177e4 6381 cur_rx = tp->cur_rx;
1da177e4 6382
9fba0812 6383 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
1da177e4 6384 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 6385 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 6386 u32 status;
6387
6388 rmb();
e03f33af 6389 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
1da177e4
LT		 6390
6391 if (status & DescOwn)
6392 break;
4dcb7d33 6393 if (unlikely(status & RxRES)) {
bf82c189
JP		 6394 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6395 status);
cebf8cc7 6396 dev->stats.rx_errors++;
1da177e4 6397 if (status & (RxRWT | RxRUNT))
cebf8cc7 6398 dev->stats.rx_length_errors++;
1da177e4 6399 if (status & RxCRC)
cebf8cc7 6400 dev->stats.rx_crc_errors++;
9dccf611 6401 if (status & RxFOVF) {
da78dbff 6402 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
cebf8cc7 6403 dev->stats.rx_fifo_errors++;
9dccf611 6404 }
6bbe021d
BG		 6405 if ((status & (RxRUNT | RxCRC)) &&
6406 !(status & (RxRWT | RxFOVF)) &&
6407 (dev->features & NETIF_F_RXALL))
6408 goto process_pkt;
1da177e4 6409 } else {
6f0333b8 6410 struct sk_buff *skb;
6bbe021d
BG		 6411 dma_addr_t addr;
6412 int pkt_size;
6413
6414process_pkt:
6415 addr = le64_to_cpu(desc->addr);
79d0c1d2
BG		 6416 if (likely(!(dev->features & NETIF_F_RXFCS)))
6417 pkt_size = (status & 0x00003fff) - 4;
6418 else
6419 pkt_size = status & 0x00003fff;
1da177e4 6420
126fa4b9
FR		 6421 /*
6422 * The driver does not support incoming fragmented
6423 * frames. They are seen as a symptom of over-mtu
6424 * sized frames.
6425 */
6426 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 6427 dev->stats.rx_dropped++;
6428 dev->stats.rx_length_errors++;
ce11ff5e 6429 goto release_descriptor;
126fa4b9
FR		 6430 }
6431
6f0333b8
ED		 6432 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6433 tp, pkt_size, addr);
6f0333b8
ED		 6434 if (!skb) {
6435 dev->stats.rx_dropped++;
ce11ff5e 6436 goto release_descriptor;
1da177e4
LT		 6437 }
6438
adea1ac7 6439 rtl8169_rx_csum(skb, status);
1da177e4
LT		 6440 skb_put(skb, pkt_size);
6441 skb->protocol = eth_type_trans(skb, dev);
6442
7a8fc77b
FR		 6443 rtl8169_rx_vlan_tag(desc, skb);
6444
56de414c 6445 napi_gro_receive(&tp->napi, skb);
1da177e4 6446
8027aa24
JW		 6447 u64_stats_update_begin(&tp->rx_stats.syncp);
6448 tp->rx_stats.packets++;
6449 tp->rx_stats.bytes += pkt_size;
6450 u64_stats_update_end(&tp->rx_stats.syncp);
1da177e4 6451 }
ce11ff5e 6452release_descriptor:
6453 desc->opts2 = 0;
6454 wmb();
6455 rtl8169_mark_to_asic(desc, rx_buf_sz);
1da177e4
LT		 6456 }
6457
6458 count = cur_rx - tp->cur_rx;
6459 tp->cur_rx = cur_rx;
6460
1da177e4
LT		 6461 return count;
6462}
6463
07d3f51f 6464static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 6465{
07d3f51f 6466 struct net_device *dev = dev_instance;
1da177e4 6467 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 6468 int handled = 0;
9085cdfa 6469 u16 status;
1da177e4 6470
9085cdfa 6471 status = rtl_get_events(tp);
da78dbff
FR		 6472 if (status && status != 0xffff) {
6473 status &= RTL_EVENT_NAPI | tp->event_slow;
6474 if (status) {
6475 handled = 1;
1da177e4 6476
da78dbff
FR		 6477 rtl_irq_disable(tp);
6478 napi_schedule(&tp->napi);
f11a377b 6479 }
da78dbff
FR		 6480 }
6481 return IRQ_RETVAL(handled);
6482}
1da177e4 6483
da78dbff
FR		 6484/*
6485 * Workqueue context.
6486 */
6487static void rtl_slow_event_work(struct rtl8169_private *tp)
6488{
6489 struct net_device *dev = tp->dev;
6490 u16 status;
6491
6492 status = rtl_get_events(tp) & tp->event_slow;
6493 rtl_ack_events(tp, status);
1da177e4 6494
da78dbff
FR		 6495 if (unlikely(status & RxFIFOOver)) {
6496 switch (tp->mac_version) {
6497 /* Work around for rx fifo overflow */
6498 case RTL_GIGA_MAC_VER_11:
6499 netif_stop_queue(dev);
934714d0
FR		 6500 /* XXX - Hack alert. See rtl_task(). */
6501 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
da78dbff 6502 default:
f11a377b
DD		 6503 break;
6504 }
da78dbff 6505 }
1da177e4 6506
da78dbff
FR		 6507 if (unlikely(status & SYSErr))
6508 rtl8169_pcierr_interrupt(dev);
0e485150 6509
da78dbff
FR		 6510 if (status & LinkChg)
6511 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
1da177e4 6512
7dbb4918 6513 rtl_irq_enable_all(tp);
1da177e4
LT		 6514}
6515
4422bcd4
FR		 6516static void rtl_task(struct work_struct *work)
6517{
da78dbff
FR		 6518 static const struct {
6519 int bitnr;
6520 void (*action)(struct rtl8169_private *);
6521 } rtl_work[] = {
934714d0 6522 /* XXX - keep rtl_slow_event_work() as first element. */
da78dbff
FR		 6523 { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work },
6524 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
6525 { RTL_FLAG_TASK_PHY_PENDING, rtl_phy_work }
6526 };
4422bcd4
FR		 6527 struct rtl8169_private *tp =
6528 container_of(work, struct rtl8169_private, wk.work);
da78dbff
FR		 6529 struct net_device *dev = tp->dev;
6530 int i;
6531
6532 rtl_lock_work(tp);
6533
6c4a70c5
FR		 6534 if (!netif_running(dev) ||
6535 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
da78dbff
FR		 6536 goto out_unlock;
6537
6538 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6539 bool pending;
6540
da78dbff 6541 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
da78dbff
FR		 6542 if (pending)
6543 rtl_work[i].action(tp);
6544 }
4422bcd4 6545
da78dbff
FR		 6546out_unlock:
6547 rtl_unlock_work(tp);
4422bcd4
FR		 6548}
6549
bea3348e 6550static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 6551{
bea3348e
SH		 6552 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6553 struct net_device *dev = tp->dev;
da78dbff
FR		 6554 u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
6555 int work_done= 0;
6556 u16 status;
6557
6558 status = rtl_get_events(tp);
6559 rtl_ack_events(tp, status & ~tp->event_slow);
6560
6561 if (status & RTL_EVENT_NAPI_RX)
6562 work_done = rtl_rx(dev, tp, (u32) budget);
6563
6564 if (status & RTL_EVENT_NAPI_TX)
6565 rtl_tx(dev, tp);
1da177e4 6566
da78dbff
FR		 6567 if (status & tp->event_slow) {
6568 enable_mask &= ~tp->event_slow;
6569
6570 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
6571 }
1da177e4 6572
bea3348e 6573 if (work_done < budget) {
288379f0 6574 napi_complete(napi);
f11a377b 6575
da78dbff
FR		 6576 rtl_irq_enable(tp, enable_mask);
6577 mmiowb();
1da177e4
LT		 6578 }
6579
bea3348e 6580 return work_done;
1da177e4 6581}
1da177e4 6582
523a6094
FR		 6583static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
6584{
6585 struct rtl8169_private *tp = netdev_priv(dev);
6586
6587 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6588 return;
6589
6590 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
6591 RTL_W32(RxMissed, 0);
6592}
6593
1da177e4
LT		 6594static void rtl8169_down(struct net_device *dev)
6595{
6596 struct rtl8169_private *tp = netdev_priv(dev);
6597 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 6598
4876cc1e 6599 del_timer_sync(&tp->timer);
1da177e4 6600
93dd79e8 6601 napi_disable(&tp->napi);
da78dbff 6602 netif_stop_queue(dev);
1da177e4 6603
92fc43b4 6604 rtl8169_hw_reset(tp);
323bb685
SG		 6605 /*
6606 * At this point device interrupts can not be enabled in any function,
209e5ac8
FR		 6607 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6608 * and napi is disabled (rtl8169_poll).
323bb685 6609 */
523a6094 6610 rtl8169_rx_missed(dev, ioaddr);
1da177e4 6611
1da177e4 6612 /* Give a racing hard_start_xmit a few cycles to complete. */
da78dbff 6613 synchronize_sched();
1da177e4 6614
1da177e4
LT		 6615 rtl8169_tx_clear(tp);
6616
6617 rtl8169_rx_clear(tp);
065c27c1 6618
6619 rtl_pll_power_down(tp);
1da177e4
LT		 6620}
6621
6622static int rtl8169_close(struct net_device *dev)
6623{
6624 struct rtl8169_private *tp = netdev_priv(dev);
6625 struct pci_dev *pdev = tp->pci_dev;
6626
e1759441
RW		 6627 pm_runtime_get_sync(&pdev->dev);
6628
cecb5fd7 6629 /* Update counters before going down */
355423d0
IV		 6630 rtl8169_update_counters(dev);
6631
da78dbff 6632 rtl_lock_work(tp);
6c4a70c5 6633 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
da78dbff 6634
1da177e4 6635 rtl8169_down(dev);
da78dbff 6636 rtl_unlock_work(tp);
1da177e4 6637
4ea72445
L		 6638 cancel_work_sync(&tp->wk.work);
6639
92a7c4e7 6640 free_irq(pdev->irq, dev);
1da177e4 6641
82553bb6
SG		 6642 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6643 tp->RxPhyAddr);
6644 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6645 tp->TxPhyAddr);
1da177e4
LT		 6646 tp->TxDescArray = NULL;
6647 tp->RxDescArray = NULL;
6648
e1759441
RW		 6649 pm_runtime_put_sync(&pdev->dev);
6650
1da177e4
LT		 6651 return 0;
6652}
6653
dc1c00ce
FR		 6654#ifdef CONFIG_NET_POLL_CONTROLLER
6655static void rtl8169_netpoll(struct net_device *dev)
6656{
6657 struct rtl8169_private *tp = netdev_priv(dev);
6658
6659 rtl8169_interrupt(tp->pci_dev->irq, dev);
6660}
6661#endif
6662
df43ac78
FR		 6663static int rtl_open(struct net_device *dev)
6664{
6665 struct rtl8169_private *tp = netdev_priv(dev);
6666 void __iomem *ioaddr = tp->mmio_addr;
6667 struct pci_dev *pdev = tp->pci_dev;
6668 int retval = -ENOMEM;
6669
6670 pm_runtime_get_sync(&pdev->dev);
6671
6672 /*
e75d6606 6673 * Rx and Tx descriptors needs 256 bytes alignment.
df43ac78
FR		 6674 * dma_alloc_coherent provides more.
6675 */
6676 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6677 &tp->TxPhyAddr, GFP_KERNEL);
6678 if (!tp->TxDescArray)
6679 goto err_pm_runtime_put;
6680
6681 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6682 &tp->RxPhyAddr, GFP_KERNEL);
6683 if (!tp->RxDescArray)
6684 goto err_free_tx_0;
6685
6686 retval = rtl8169_init_ring(dev);
6687 if (retval < 0)
6688 goto err_free_rx_1;
6689
6690 INIT_WORK(&tp->wk.work, rtl_task);
6691
6692 smp_mb();
6693
6694 rtl_request_firmware(tp);
6695
92a7c4e7 6696 retval = request_irq(pdev->irq, rtl8169_interrupt,
df43ac78
FR		 6697 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
6698 dev->name, dev);
6699 if (retval < 0)
6700 goto err_release_fw_2;
6701
6702 rtl_lock_work(tp);
6703
6704 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6705
6706 napi_enable(&tp->napi);
6707
6708 rtl8169_init_phy(dev, tp);
6709
6710 __rtl8169_set_features(dev, dev->features);
6711
6712 rtl_pll_power_up(tp);
6713
6714 rtl_hw_start(dev);
6715
6716 netif_start_queue(dev);
6717
6718 rtl_unlock_work(tp);
6719
6720 tp->saved_wolopts = 0;
6721 pm_runtime_put_noidle(&pdev->dev);
6722
6723 rtl8169_check_link_status(dev, tp, ioaddr);
6724out:
6725 return retval;
6726
6727err_release_fw_2:
6728 rtl_release_firmware(tp);
6729 rtl8169_rx_clear(tp);
6730err_free_rx_1:
6731 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6732 tp->RxPhyAddr);
6733 tp->RxDescArray = NULL;
6734err_free_tx_0:
6735 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6736 tp->TxPhyAddr);
6737 tp->TxDescArray = NULL;
6738err_pm_runtime_put:
6739 pm_runtime_put_noidle(&pdev->dev);
6740 goto out;
6741}
6742
8027aa24
JW		 6743static struct rtnl_link_stats64 *
6744rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
1da177e4
LT		 6745{
6746 struct rtl8169_private *tp = netdev_priv(dev);
6747 void __iomem *ioaddr = tp->mmio_addr;
8027aa24 6748 unsigned int start;
1da177e4 6749
da78dbff 6750 if (netif_running(dev))
523a6094 6751 rtl8169_rx_missed(dev, ioaddr);
5b0384f4 6752
8027aa24 6753 do {
57a7744e 6754 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
8027aa24
JW		 6755 stats->rx_packets = tp->rx_stats.packets;
6756 stats->rx_bytes = tp->rx_stats.bytes;
57a7744e 6757 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
8027aa24
JW		 6758
6759
6760 do {
57a7744e 6761 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
8027aa24
JW		 6762 stats->tx_packets = tp->tx_stats.packets;
6763 stats->tx_bytes = tp->tx_stats.bytes;
57a7744e 6764 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
8027aa24
JW		 6765
6766 stats->rx_dropped = dev->stats.rx_dropped;
6767 stats->tx_dropped = dev->stats.tx_dropped;
6768 stats->rx_length_errors = dev->stats.rx_length_errors;
6769 stats->rx_errors = dev->stats.rx_errors;
6770 stats->rx_crc_errors = dev->stats.rx_crc_errors;
6771 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
6772 stats->rx_missed_errors = dev->stats.rx_missed_errors;
6773
6774 return stats;
1da177e4
LT		 6775}
6776
861ab440 6777static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 6778{
065c27c1 6779 struct rtl8169_private *tp = netdev_priv(dev);
6780
5d06a99f 6781 if (!netif_running(dev))
861ab440 6782 return;
5d06a99f
FR		 6783
6784 netif_device_detach(dev);
6785 netif_stop_queue(dev);
da78dbff
FR		 6786
6787 rtl_lock_work(tp);
6788 napi_disable(&tp->napi);
6c4a70c5 6789 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
da78dbff
FR		 6790 rtl_unlock_work(tp);
6791
6792 rtl_pll_power_down(tp);
861ab440
RW		 6793}
6794
6795#ifdef CONFIG_PM
6796
6797static int rtl8169_suspend(struct device *device)
6798{
6799 struct pci_dev *pdev = to_pci_dev(device);
6800 struct net_device *dev = pci_get_drvdata(pdev);
5d06a99f 6801
861ab440 6802 rtl8169_net_suspend(dev);
1371fa6d 6803
5d06a99f
FR		 6804 return 0;
6805}
6806
e1759441
RW		 6807static void __rtl8169_resume(struct net_device *dev)
6808{
065c27c1 6809 struct rtl8169_private *tp = netdev_priv(dev);
6810
e1759441 6811 netif_device_attach(dev);
065c27c1 6812
6813 rtl_pll_power_up(tp);
6814
cff4c162
AS		 6815 rtl_lock_work(tp);
6816 napi_enable(&tp->napi);
6c4a70c5 6817 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
cff4c162 6818 rtl_unlock_work(tp);
da78dbff 6819
98ddf986 6820 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
e1759441
RW		 6821}
6822
861ab440 6823static int rtl8169_resume(struct device *device)
5d06a99f 6824{
861ab440 6825 struct pci_dev *pdev = to_pci_dev(device);
5d06a99f 6826 struct net_device *dev = pci_get_drvdata(pdev);
fccec10b
SG		 6827 struct rtl8169_private *tp = netdev_priv(dev);
6828
6829 rtl8169_init_phy(dev, tp);
5d06a99f 6830
e1759441
RW		 6831 if (netif_running(dev))
6832 __rtl8169_resume(dev);
5d06a99f 6833
e1759441
RW		 6834 return 0;
6835}
6836
6837static int rtl8169_runtime_suspend(struct device *device)
6838{
6839 struct pci_dev *pdev = to_pci_dev(device);
6840 struct net_device *dev = pci_get_drvdata(pdev);
6841 struct rtl8169_private *tp = netdev_priv(dev);
6842
6843 if (!tp->TxDescArray)
6844 return 0;
6845
da78dbff 6846 rtl_lock_work(tp);
e1759441
RW		 6847 tp->saved_wolopts = __rtl8169_get_wol(tp);
6848 __rtl8169_set_wol(tp, WAKE_ANY);
da78dbff 6849 rtl_unlock_work(tp);
e1759441
RW		 6850
6851 rtl8169_net_suspend(dev);
6852
6853 return 0;
6854}
6855
6856static int rtl8169_runtime_resume(struct device *device)
6857{
6858 struct pci_dev *pdev = to_pci_dev(device);
6859 struct net_device *dev = pci_get_drvdata(pdev);
6860 struct rtl8169_private *tp = netdev_priv(dev);
6861
6862 if (!tp->TxDescArray)
6863 return 0;
6864
da78dbff 6865 rtl_lock_work(tp);
e1759441
RW		 6866 __rtl8169_set_wol(tp, tp->saved_wolopts);
6867 tp->saved_wolopts = 0;
da78dbff 6868 rtl_unlock_work(tp);
e1759441 6869
fccec10b
SG		 6870 rtl8169_init_phy(dev, tp);
6871
e1759441 6872 __rtl8169_resume(dev);
5d06a99f 6873
5d06a99f
FR		 6874 return 0;
6875}
6876
e1759441
RW		 6877static int rtl8169_runtime_idle(struct device *device)
6878{
6879 struct pci_dev *pdev = to_pci_dev(device);
6880 struct net_device *dev = pci_get_drvdata(pdev);
6881 struct rtl8169_private *tp = netdev_priv(dev);
6882
e4fbce74 6883 return tp->TxDescArray ? -EBUSY : 0;
e1759441
RW		 6884}
6885
47145210 6886static const struct dev_pm_ops rtl8169_pm_ops = {
cecb5fd7
FR		 6887 .suspend = rtl8169_suspend,
6888 .resume = rtl8169_resume,
6889 .freeze = rtl8169_suspend,
6890 .thaw = rtl8169_resume,
6891 .poweroff = rtl8169_suspend,
6892 .restore = rtl8169_resume,
6893 .runtime_suspend = rtl8169_runtime_suspend,
6894 .runtime_resume = rtl8169_runtime_resume,
6895 .runtime_idle = rtl8169_runtime_idle,
861ab440
RW		 6896};
6897
6898#define RTL8169_PM_OPS (&rtl8169_pm_ops)
6899
6900#else /* !CONFIG_PM */
6901
6902#define RTL8169_PM_OPS NULL
6903
6904#endif /* !CONFIG_PM */
6905
649b3b8c 6906static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6907{
6908 void __iomem *ioaddr = tp->mmio_addr;
6909
6910 /* WoL fails with 8168b when the receiver is disabled. */
6911 switch (tp->mac_version) {
6912 case RTL_GIGA_MAC_VER_11:
6913 case RTL_GIGA_MAC_VER_12:
6914 case RTL_GIGA_MAC_VER_17:
6915 pci_clear_master(tp->pci_dev);
6916
6917 RTL_W8(ChipCmd, CmdRxEnb);
6918 /* PCI commit */
6919 RTL_R8(ChipCmd);
6920 break;
6921 default:
6922 break;
6923 }
6924}
6925
1765f95d
FR		 6926static void rtl_shutdown(struct pci_dev *pdev)
6927{
861ab440 6928 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 6929 struct rtl8169_private *tp = netdev_priv(dev);
2a15cd2f 6930 struct device *d = &pdev->dev;
6931
6932 pm_runtime_get_sync(d);
861ab440
RW		 6933
6934 rtl8169_net_suspend(dev);
1765f95d 6935
cecb5fd7 6936 /* Restore original MAC address */
cc098dc7
IV		 6937 rtl_rar_set(tp, dev->perm_addr);
6938
92fc43b4 6939 rtl8169_hw_reset(tp);
4bb3f522 6940
861ab440 6941 if (system_state == SYSTEM_POWER_OFF) {
649b3b8c 6942 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
6943 rtl_wol_suspend_quirk(tp);
6944 rtl_wol_shutdown_quirk(tp);
ca52efd5 6945 }
6946
861ab440
RW		 6947 pci_wake_from_d3(pdev, true);
6948 pci_set_power_state(pdev, PCI_D3hot);
6949 }
2a15cd2f 6950
6951 pm_runtime_put_noidle(d);
861ab440 6952}
5d06a99f 6953
baf63293 6954static void rtl_remove_one(struct pci_dev *pdev)
e27566ed
FR		 6955{
6956 struct net_device *dev = pci_get_drvdata(pdev);
6957 struct rtl8169_private *tp = netdev_priv(dev);
6958
6959 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
6960 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
6961 tp->mac_version == RTL_GIGA_MAC_VER_31) {
6962 rtl8168_driver_stop(tp);
6963 }
6964
ad1be8d3
DN		 6965 netif_napi_del(&tp->napi);
6966
e27566ed
FR		 6967 unregister_netdev(dev);
6968
6969 rtl_release_firmware(tp);
6970
6971 if (pci_dev_run_wake(pdev))
6972 pm_runtime_get_noresume(&pdev->dev);
6973
6974 /* restore original MAC address */
6975 rtl_rar_set(tp, dev->perm_addr);
6976
6977 rtl_disable_msi(pdev, tp);
6978 rtl8169_release_board(pdev, dev, tp->mmio_addr);
e27566ed
FR		 6979}
6980
fa9c385e 6981static const struct net_device_ops rtl_netdev_ops = {
df43ac78 6982 .ndo_open = rtl_open,
fa9c385e
FR		 6983 .ndo_stop = rtl8169_close,
6984 .ndo_get_stats64 = rtl8169_get_stats64,
6985 .ndo_start_xmit = rtl8169_start_xmit,
6986 .ndo_tx_timeout = rtl8169_tx_timeout,
6987 .ndo_validate_addr = eth_validate_addr,
6988 .ndo_change_mtu = rtl8169_change_mtu,
6989 .ndo_fix_features = rtl8169_fix_features,
6990 .ndo_set_features = rtl8169_set_features,
6991 .ndo_set_mac_address = rtl_set_mac_address,
6992 .ndo_do_ioctl = rtl8169_ioctl,
6993 .ndo_set_rx_mode = rtl_set_rx_mode,
6994#ifdef CONFIG_NET_POLL_CONTROLLER
6995 .ndo_poll_controller = rtl8169_netpoll,
6996#endif
6997
6998};
6999
31fa8b18
FR		 7000static const struct rtl_cfg_info {
7001 void (*hw_start)(struct net_device *);
7002 unsigned int region;
7003 unsigned int align;
7004 u16 event_slow;
7005 unsigned features;
7006 u8 default_ver;
7007} rtl_cfg_infos [] = {
7008 [RTL_CFG_0] = {
7009 .hw_start = rtl_hw_start_8169,
7010 .region = 1,
7011 .align = 0,
7012 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
7013 .features = RTL_FEATURE_GMII,
7014 .default_ver = RTL_GIGA_MAC_VER_01,
7015 },
7016 [RTL_CFG_1] = {
7017 .hw_start = rtl_hw_start_8168,
7018 .region = 2,
7019 .align = 8,
7020 .event_slow = SYSErr | LinkChg | RxOverflow,
7021 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
7022 .default_ver = RTL_GIGA_MAC_VER_11,
7023 },
7024 [RTL_CFG_2] = {
7025 .hw_start = rtl_hw_start_8101,
7026 .region = 2,
7027 .align = 8,
7028 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
7029 PCSTimeout,
7030 .features = RTL_FEATURE_MSI,
7031 .default_ver = RTL_GIGA_MAC_VER_13,
7032 }
7033};
7034
7035/* Cfg9346_Unlock assumed. */
7036static unsigned rtl_try_msi(struct rtl8169_private *tp,
7037 const struct rtl_cfg_info *cfg)
7038{
7039 void __iomem *ioaddr = tp->mmio_addr;
7040 unsigned msi = 0;
7041 u8 cfg2;
7042
7043 cfg2 = RTL_R8(Config2) & ~MSIEnable;
7044 if (cfg->features & RTL_FEATURE_MSI) {
7045 if (pci_enable_msi(tp->pci_dev)) {
7046 netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
7047 } else {
7048 cfg2 |= MSIEnable;
7049 msi = RTL_FEATURE_MSI;
7050 }
7051 }
7052 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
7053 RTL_W8(Config2, cfg2);
7054 return msi;
7055}
7056
c558386b
HW		 7057DECLARE_RTL_COND(rtl_link_list_ready_cond)
7058{
7059 void __iomem *ioaddr = tp->mmio_addr;
7060
7061 return RTL_R8(MCU) & LINK_LIST_RDY;
7062}
7063
7064DECLARE_RTL_COND(rtl_rxtx_empty_cond)
7065{
7066 void __iomem *ioaddr = tp->mmio_addr;
7067
7068 return (RTL_R8(MCU) & RXTX_EMPTY) == RXTX_EMPTY;
7069}
7070
baf63293 7071static void rtl_hw_init_8168g(struct rtl8169_private *tp)
c558386b
HW		 7072{
7073 void __iomem *ioaddr = tp->mmio_addr;
7074 u32 data;
7075
7076 tp->ocp_base = OCP_STD_PHY_BASE;
7077
7078 RTL_W32(MISC, RTL_R32(MISC) | RXDV_GATED_EN);
7079
7080 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
7081 return;
7082
7083 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
7084 return;
7085
7086 RTL_W8(ChipCmd, RTL_R8(ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
7087 msleep(1);
7088 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
7089
5f8bcce9 7090 data = r8168_mac_ocp_read(tp, 0xe8de);
c558386b
HW		 7091 data &= ~(1 << 14);
7092 r8168_mac_ocp_write(tp, 0xe8de, data);
7093
7094 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7095 return;
7096
5f8bcce9 7097 data = r8168_mac_ocp_read(tp, 0xe8de);
c558386b
HW		 7098 data |= (1 << 15);
7099 r8168_mac_ocp_write(tp, 0xe8de, data);
7100
7101 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7102 return;
7103}
7104
baf63293 7105static void rtl_hw_initialize(struct rtl8169_private *tp)
c558386b
HW		 7106{
7107 switch (tp->mac_version) {
7108 case RTL_GIGA_MAC_VER_40:
7109 case RTL_GIGA_MAC_VER_41:
57538c4a 7110 case RTL_GIGA_MAC_VER_42:
58152cd4 7111 case RTL_GIGA_MAC_VER_43:
45dd95c4 7112 case RTL_GIGA_MAC_VER_44:
c558386b
HW		 7113 rtl_hw_init_8168g(tp);
7114 break;
7115
7116 default:
7117 break;
7118 }
7119}
7120
baf63293 7121static int
3b6cf25d
FR		 7122rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7123{
7124 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
7125 const unsigned int region = cfg->region;
7126 struct rtl8169_private *tp;
7127 struct mii_if_info *mii;
7128 struct net_device *dev;
7129 void __iomem *ioaddr;
7130 int chipset, i;
7131 int rc;
7132
7133 if (netif_msg_drv(&debug)) {
7134 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
7135 MODULENAME, RTL8169_VERSION);
7136 }
7137
7138 dev = alloc_etherdev(sizeof (*tp));
7139 if (!dev) {
7140 rc = -ENOMEM;
7141 goto out;
7142 }
7143
7144 SET_NETDEV_DEV(dev, &pdev->dev);
fa9c385e 7145 dev->netdev_ops = &rtl_netdev_ops;
3b6cf25d
FR		 7146 tp = netdev_priv(dev);
7147 tp->dev = dev;
7148 tp->pci_dev = pdev;
7149 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
7150
7151 mii = &tp->mii;
7152 mii->dev = dev;
7153 mii->mdio_read = rtl_mdio_read;
7154 mii->mdio_write = rtl_mdio_write;
7155 mii->phy_id_mask = 0x1f;
7156 mii->reg_num_mask = 0x1f;
7157 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
7158
7159 /* disable ASPM completely as that cause random device stop working
7160 * problems as well as full system hangs for some PCIe devices users */
7161 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
7162 PCIE_LINK_STATE_CLKPM);
7163
7164 /* enable device (incl. PCI PM wakeup and hotplug setup) */
7165 rc = pci_enable_device(pdev);
7166 if (rc < 0) {
7167 netif_err(tp, probe, dev, "enable failure\n");
7168 goto err_out_free_dev_1;
7169 }
7170
7171 if (pci_set_mwi(pdev) < 0)
7172 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
7173
7174 /* make sure PCI base addr 1 is MMIO */
7175 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
7176 netif_err(tp, probe, dev,
7177 "region #%d not an MMIO resource, aborting\n",
7178 region);
7179 rc = -ENODEV;
7180 goto err_out_mwi_2;
7181 }
7182
7183 /* check for weird/broken PCI region reporting */
7184 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
7185 netif_err(tp, probe, dev,
7186 "Invalid PCI region size(s), aborting\n");
7187 rc = -ENODEV;
7188 goto err_out_mwi_2;
7189 }
7190
7191 rc = pci_request_regions(pdev, MODULENAME);
7192 if (rc < 0) {
7193 netif_err(tp, probe, dev, "could not request regions\n");
7194 goto err_out_mwi_2;
7195 }
7196
7197 tp->cp_cmd = RxChkSum;
7198
7199 if ((sizeof(dma_addr_t) > 4) &&
7200 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
7201 tp->cp_cmd |= PCIDAC;
7202 dev->features |= NETIF_F_HIGHDMA;
7203 } else {
7204 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
7205 if (rc < 0) {
7206 netif_err(tp, probe, dev, "DMA configuration failed\n");
7207 goto err_out_free_res_3;
7208 }
7209 }
7210
7211 /* ioremap MMIO region */
7212 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
7213 if (!ioaddr) {
7214 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
7215 rc = -EIO;
7216 goto err_out_free_res_3;
7217 }
7218 tp->mmio_addr = ioaddr;
7219
7220 if (!pci_is_pcie(pdev))
7221 netif_info(tp, probe, dev, "not PCI Express\n");
7222
7223 /* Identify chip attached to board */
7224 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
7225
7226 rtl_init_rxcfg(tp);
7227
7228 rtl_irq_disable(tp);
7229
c558386b
HW		 7230 rtl_hw_initialize(tp);
7231
3b6cf25d
FR		 7232 rtl_hw_reset(tp);
7233
7234 rtl_ack_events(tp, 0xffff);
7235
7236 pci_set_master(pdev);
7237
7238 /*
7239 * Pretend we are using VLANs; This bypasses a nasty bug where
7240 * Interrupts stop flowing on high load on 8110SCd controllers.
7241 */
7242 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
7243 tp->cp_cmd |= RxVlan;
7244
7245 rtl_init_mdio_ops(tp);
7246 rtl_init_pll_power_ops(tp);
7247 rtl_init_jumbo_ops(tp);
beb1fe18 7248 rtl_init_csi_ops(tp);
3b6cf25d
FR		 7249
7250 rtl8169_print_mac_version(tp);
7251
7252 chipset = tp->mac_version;
7253 tp->txd_version = rtl_chip_infos[chipset].txd_version;
7254
7255 RTL_W8(Cfg9346, Cfg9346_Unlock);
7256 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
8f9d5138 7257 RTL_W8(Config5, RTL_R8(Config5) & (BWF | MWF | UWF | LanWake | PMEStatus));
3b6cf25d
FR		 7258 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
7259 tp->features |= RTL_FEATURE_WOL;
7260 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
7261 tp->features |= RTL_FEATURE_WOL;
7262 tp->features |= rtl_try_msi(tp, cfg);
7263 RTL_W8(Cfg9346, Cfg9346_Lock);
7264
7265 if (rtl_tbi_enabled(tp)) {
7266 tp->set_speed = rtl8169_set_speed_tbi;
7267 tp->get_settings = rtl8169_gset_tbi;
7268 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
7269 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
7270 tp->link_ok = rtl8169_tbi_link_ok;
7271 tp->do_ioctl = rtl_tbi_ioctl;
7272 } else {
7273 tp->set_speed = rtl8169_set_speed_xmii;
7274 tp->get_settings = rtl8169_gset_xmii;
7275 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
7276 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
7277 tp->link_ok = rtl8169_xmii_link_ok;
7278 tp->do_ioctl = rtl_xmii_ioctl;
7279 }
7280
7281 mutex_init(&tp->wk.mutex);
340fea3d
KM		 7282 u64_stats_init(&tp->rx_stats.syncp);
7283 u64_stats_init(&tp->tx_stats.syncp);
3b6cf25d
FR		 7284
7285 /* Get MAC address */
7286 for (i = 0; i < ETH_ALEN; i++)
7287 dev->dev_addr[i] = RTL_R8(MAC0 + i);
3b6cf25d 7288
7ad24ea4 7289 dev->ethtool_ops = &rtl8169_ethtool_ops;
3b6cf25d 7290 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3b6cf25d
FR		 7291
7292 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
7293
7294 /* don't enable SG, IP_CSUM and TSO by default - it might not work
7295 * properly for all devices */
7296 dev->features |= NETIF_F_RXCSUM |
f646968f 7297 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d
FR		 7298
7299 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
f646968f
PM		 7300 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
7301 NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d
FR		 7302 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7303 NETIF_F_HIGHDMA;
7304
7305 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
7306 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
f646968f 7307 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d 7308
5888d3fc 7309 if (tp->txd_version == RTL_TD_0)
7310 tp->tso_csum = rtl8169_tso_csum_v1;
e974604b 7311 else if (tp->txd_version == RTL_TD_1) {
5888d3fc 7312 tp->tso_csum = rtl8169_tso_csum_v2;
e974604b 7313 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
7314 } else
5888d3fc 7315 WARN_ON_ONCE(1);
7316
3b6cf25d
FR		 7317 dev->hw_features |= NETIF_F_RXALL;
7318 dev->hw_features |= NETIF_F_RXFCS;
7319
7320 tp->hw_start = cfg->hw_start;
7321 tp->event_slow = cfg->event_slow;
7322
7323 tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
7324 ~(RxBOVF | RxFOVF) : ~0;
7325
7326 init_timer(&tp->timer);
7327 tp->timer.data = (unsigned long) dev;
7328 tp->timer.function = rtl8169_phy_timer;
7329
7330 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
7331
7332 rc = register_netdev(dev);
7333 if (rc < 0)
7334 goto err_out_msi_4;
7335
7336 pci_set_drvdata(pdev, dev);
7337
92a7c4e7
FR		 7338 netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
7339 rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
7340 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
3b6cf25d
FR		 7341 if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
7342 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
7343 "tx checksumming: %s]\n",
7344 rtl_chip_infos[chipset].jumbo_max,
7345 rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
7346 }
7347
7348 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
7349 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
7350 tp->mac_version == RTL_GIGA_MAC_VER_31) {
7351 rtl8168_driver_start(tp);
7352 }
7353
7354 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
7355
7356 if (pci_dev_run_wake(pdev))
7357 pm_runtime_put_noidle(&pdev->dev);
7358
7359 netif_carrier_off(dev);
7360
7361out:
7362 return rc;
7363
7364err_out_msi_4:
ad1be8d3 7365 netif_napi_del(&tp->napi);
3b6cf25d
FR		 7366 rtl_disable_msi(pdev, tp);
7367 iounmap(ioaddr);
7368err_out_free_res_3:
7369 pci_release_regions(pdev);
7370err_out_mwi_2:
7371 pci_clear_mwi(pdev);
7372 pci_disable_device(pdev);
7373err_out_free_dev_1:
7374 free_netdev(dev);
7375 goto out;
7376}
7377
1da177e4
LT		 7378static struct pci_driver rtl8169_pci_driver = {
7379 .name = MODULENAME,
7380 .id_table = rtl8169_pci_tbl,
3b6cf25d 7381 .probe = rtl_init_one,
baf63293 7382 .remove = rtl_remove_one,
1765f95d 7383 .shutdown = rtl_shutdown,
861ab440 7384 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 7385};
7386
3eeb7da9 7387module_pci_driver(rtl8169_pci_driver);
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